commit be7c60e4dd6bf2a6ffde7e60949a74aef45ad21c Author: Sergei Gusenkov Date: Fri May 22 21:52:50 2026 +0300 3.3.7 diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..9ac1a5f --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,503 @@ +# Check ESP-IDF version and error out if it is not in the supported range. +# +# Note for arduino-esp32 developers: to bypass the version check locally, +# set ARDUINO_SKIP_IDF_VERSION_CHECK environment variable to 1. For example: +# export ARDUINO_SKIP_IDF_VERSION_CHECK=1 +# idf.py build + +set(min_supported_idf_version "5.3.0") +set(max_supported_idf_version "5.5.99") +set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}") + +if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}") + if (idf_version VERSION_LESS min_supported_idf_version) + message(FATAL_ERROR "Arduino-esp32 can be used with ESP-IDF versions " + "between ${min_supported_idf_version} and ${max_supported_idf_version}, " + "but an older version is detected: ${idf_version}.") + endif() + if (idf_version VERSION_GREATER max_supported_idf_version) + message(FATAL_ERROR "Arduino-esp32 can be used with ESP-IDF versions " + "between ${min_supported_idf_version} and ${max_supported_idf_version}, " + "but a newer version is detected: ${idf_version}.") + endif() +endif() + +set(CORE_SRCS + cores/esp32/base64.cpp + cores/esp32/cbuf.cpp + cores/esp32/ColorFormat.c + cores/esp32/chip-debug-report.cpp + cores/esp32/esp32-hal-adc.c + cores/esp32/esp32-hal-bt.c + cores/esp32/esp32-hal-cpu.c + cores/esp32/esp32-hal-dac.c + cores/esp32/esp32-hal-gpio.c + cores/esp32/esp32-hal-hosted.c + cores/esp32/esp32-hal-i2c.c + cores/esp32/esp32-hal-i2c-ng.c + cores/esp32/esp32-hal-i2c-slave.c + cores/esp32/esp32-hal-ledc.c + cores/esp32/esp32-hal-log-wrapper.c + cores/esp32/esp32-hal-matrix.c + cores/esp32/esp32-hal-misc.c + cores/esp32/esp32-hal-periman.c + cores/esp32/esp32-hal-psram.c + cores/esp32/esp32-hal-rgb-led.c + cores/esp32/esp32-hal-sigmadelta.c + cores/esp32/esp32-hal-spi.c + cores/esp32/esp32-hal-time.c + cores/esp32/esp32-hal-timer.c + cores/esp32/esp32-hal-tinyusb.c + cores/esp32/esp32-hal-touch.c + cores/esp32/esp32-hal-touch-ng.c + cores/esp32/esp32-hal-uart.c + cores/esp32/esp32-hal-rmt.c + cores/esp32/Esp.cpp + cores/esp32/freertos_stats.cpp + cores/esp32/FunctionalInterrupt.cpp + cores/esp32/HardwareSerial.cpp + cores/esp32/HashBuilder.cpp + cores/esp32/HEXBuilder.cpp + cores/esp32/idf_openthread_mpool_wrapper.c + cores/esp32/IPAddress.cpp + cores/esp32/libb64/cdecode.c + cores/esp32/libb64/cencode.c + cores/esp32/MacAddress.cpp + cores/esp32/main.cpp + cores/esp32/MD5Builder.cpp + cores/esp32/Print.cpp + cores/esp32/stdlib_noniso.c + cores/esp32/Stream.cpp + cores/esp32/StreamString.cpp + cores/esp32/Tone.cpp + cores/esp32/HWCDC.cpp + cores/esp32/USB.cpp + cores/esp32/USBCDC.cpp + cores/esp32/USBMSC.cpp + cores/esp32/FirmwareMSC.cpp + cores/esp32/firmware_msc_fat.c + cores/esp32/wiring_pulse.c + cores/esp32/wiring_shift.c + cores/esp32/WMath.cpp + cores/esp32/WString.cpp + ) + +set(ARDUINO_ALL_LIBRARIES + ArduinoOTA + AsyncUDP + BLE + BluetoothSerial + DNSServer + EEPROM + ESP_I2S + ESP_NOW + ESP_SR + ESP_HostedOTA + ESPmDNS + Ethernet + FFat + FS + Hash + HTTPClient + HTTPUpdate + Insights + LittleFS + Matter + NetBIOS + Network + OpenThread + PPP + Preferences + RainMaker + SD_MMC + SD + SimpleBLE + SPIFFS + SPI + Ticker + Update + USB + WebServer + NetworkClientSecure + WiFi + WiFiProv + Wire + Zigbee + ) + +set(ARDUINO_LIBRARY_ArduinoOTA_SRCS libraries/ArduinoOTA/src/ArduinoOTA.cpp) + +set(ARDUINO_LIBRARY_AsyncUDP_SRCS libraries/AsyncUDP/src/AsyncUDP.cpp) + +set(ARDUINO_LIBRARY_BluetoothSerial_SRCS + libraries/BluetoothSerial/src/BluetoothSerial.cpp + libraries/BluetoothSerial/src/BTAddress.cpp + libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp + libraries/BluetoothSerial/src/BTScanResultsSet.cpp) + +set(ARDUINO_LIBRARY_DNSServer_SRCS libraries/DNSServer/src/DNSServer.cpp) + +set(ARDUINO_LIBRARY_EEPROM_SRCS libraries/EEPROM/src/EEPROM.cpp) + +set(ARDUINO_LIBRARY_ESP_I2S_SRCS libraries/ESP_I2S/src/ESP_I2S.cpp) + +set(ARDUINO_LIBRARY_ESP_NOW_SRCS + libraries/ESP_NOW/src/ESP32_NOW.cpp + libraries/ESP_NOW/src/ESP32_NOW_Serial.cpp) + +set(ARDUINO_LIBRARY_ESP_SR_SRCS + libraries/ESP_SR/src/ESP_SR.cpp + libraries/ESP_SR/src/esp32-hal-sr.c) + +set(ARDUINO_LIBRARY_ESP_HostedOTA_SRCS + libraries/ESP_HostedOTA/src/ESP_HostedOTA.cpp) + +set(ARDUINO_LIBRARY_ESPmDNS_SRCS libraries/ESPmDNS/src/ESPmDNS.cpp) + +set(ARDUINO_LIBRARY_Ethernet_SRCS libraries/Ethernet/src/ETH.cpp) + +set(ARDUINO_LIBRARY_FFat_SRCS libraries/FFat/src/FFat.cpp) + +set(ARDUINO_LIBRARY_FS_SRCS + libraries/FS/src/FS.cpp + libraries/FS/src/vfs_api.cpp) + +set(ARDUINO_LIBRARY_Hash_SRCS + libraries/Hash/src/SHA1Builder.cpp + libraries/Hash/src/SHA2Builder.cpp + libraries/Hash/src/SHA3Builder.cpp + libraries/Hash/src/PBKDF2_HMACBuilder.cpp + ) + +set(ARDUINO_LIBRARY_HTTPClient_SRCS libraries/HTTPClient/src/HTTPClient.cpp) + +set(ARDUINO_LIBRARY_HTTPUpdate_SRCS libraries/HTTPUpdate/src/HTTPUpdate.cpp) + +set(ARDUINO_LIBRARY_Insights_SRCS libraries/Insights/src/Insights.cpp) + +set(ARDUINO_LIBRARY_LittleFS_SRCS libraries/LittleFS/src/LittleFS.cpp) + +set(ARDUINO_LIBRARY_NetBIOS_SRCS libraries/NetBIOS/src/NetBIOS.cpp) + +set(ARDUINO_LIBRARY_OpenThread_SRCS + libraries/OpenThread/src/OThread.cpp + libraries/OpenThread/src/OThreadCLI.cpp + libraries/OpenThread/src/OThreadCLI_Util.cpp) + +set(ARDUINO_LIBRARY_Matter_SRCS + libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.cpp + libraries/Matter/src/MatterEndpoints/MatterOnOffLight.cpp + libraries/Matter/src/MatterEndpoints/MatterDimmableLight.cpp + libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.cpp + libraries/Matter/src/MatterEndpoints/MatterColorLight.cpp + libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.cpp + libraries/Matter/src/MatterEndpoints/MatterFan.cpp + libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.cpp + libraries/Matter/src/MatterEndpoints/MatterTemperatureControlledCabinet.cpp + libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.cpp + libraries/Matter/src/MatterEndpoints/MatterContactSensor.cpp + libraries/Matter/src/MatterEndpoints/MatterWaterLeakDetector.cpp + libraries/Matter/src/MatterEndpoints/MatterWaterFreezeDetector.cpp + libraries/Matter/src/MatterEndpoints/MatterRainSensor.cpp + libraries/Matter/src/MatterEndpoints/MatterPressureSensor.cpp + libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp + libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp + libraries/Matter/src/MatterEndpoints/MatterDimmablePlugin.cpp + libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp + libraries/Matter/src/MatterEndpoints/MatterWindowCovering.cpp + libraries/Matter/src/Matter.cpp + libraries/Matter/src/MatterEndPoint.cpp) + +set(ARDUINO_LIBRARY_PPP_SRCS libraries/PPP/src/PPP.cpp) + +set(ARDUINO_LIBRARY_Preferences_SRCS libraries/Preferences/src/Preferences.cpp) + +set(ARDUINO_LIBRARY_RainMaker_SRCS + libraries/RainMaker/src/RMaker.cpp + libraries/RainMaker/src/RMakerNode.cpp + libraries/RainMaker/src/RMakerParam.cpp + libraries/RainMaker/src/RMakerDevice.cpp + libraries/RainMaker/src/RMakerType.cpp + libraries/RainMaker/src/RMakerQR.cpp + libraries/RainMaker/src/RMakerUtils.cpp + libraries/RainMaker/src/AppInsights.cpp) + +set(ARDUINO_LIBRARY_SD_MMC_SRCS libraries/SD_MMC/src/SD_MMC.cpp) + +set(ARDUINO_LIBRARY_SD_SRCS + libraries/SD/src/SD.cpp + libraries/SD/src/sd_diskio.cpp + libraries/SD/src/sd_diskio_crc.c) + +set(ARDUINO_LIBRARY_SimpleBLE_SRCS libraries/SimpleBLE/src/SimpleBLE.cpp) + +set(ARDUINO_LIBRARY_SPIFFS_SRCS libraries/SPIFFS/src/SPIFFS.cpp) + +set(ARDUINO_LIBRARY_SPI_SRCS libraries/SPI/src/SPI.cpp) + +set(ARDUINO_LIBRARY_Ticker_SRCS libraries/Ticker/src/Ticker.cpp) + +set(ARDUINO_LIBRARY_Update_SRCS + libraries/Update/src/Updater.cpp + libraries/Update/src/HttpsOTAUpdate.cpp + libraries/Update/src/Updater_Signing.cpp) + +set(ARDUINO_LIBRARY_USB_SRCS + libraries/USB/src/USBHID.cpp + libraries/USB/src/USBMIDI.cpp + libraries/USB/src/USBHIDMouse.cpp + libraries/USB/src/USBHIDKeyboard.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp + libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp + libraries/USB/src/USBHIDGamepad.cpp + libraries/USB/src/USBHIDConsumerControl.cpp + libraries/USB/src/USBHIDSystemControl.cpp + libraries/USB/src/USBHIDVendor.cpp + libraries/USB/src/USBVendor.cpp) + +set(ARDUINO_LIBRARY_WebServer_SRCS + libraries/WebServer/src/WebServer.cpp + libraries/WebServer/src/Parsing.cpp + libraries/WebServer/src/detail/mimetable.cpp + libraries/WebServer/src/middleware/MiddlewareChain.cpp + libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp + libraries/WebServer/src/middleware/CorsMiddleware.cpp + libraries/WebServer/src/middleware/LoggingMiddleware.cpp) + +set(ARDUINO_LIBRARY_NetworkClientSecure_SRCS + libraries/NetworkClientSecure/src/ssl_client.cpp + libraries/NetworkClientSecure/src/NetworkClientSecure.cpp) + +set(ARDUINO_LIBRARY_Network_SRCS + libraries/Network/src/NetworkInterface.cpp + libraries/Network/src/NetworkEvents.cpp + libraries/Network/src/NetworkManager.cpp + libraries/Network/src/NetworkClient.cpp + libraries/Network/src/NetworkServer.cpp + libraries/Network/src/NetworkUdp.cpp) + +set(ARDUINO_LIBRARY_WiFi_SRCS + libraries/WiFi/src/WiFiAP.cpp + libraries/WiFi/src/WiFi.cpp + libraries/WiFi/src/WiFiGeneric.cpp + libraries/WiFi/src/WiFiMulti.cpp + libraries/WiFi/src/WiFiScan.cpp + libraries/WiFi/src/WiFiSTA.cpp + libraries/WiFi/src/STA.cpp + libraries/WiFi/src/AP.cpp) + +set(ARDUINO_LIBRARY_WiFiProv_SRCS libraries/WiFiProv/src/WiFiProv.cpp) + +set(ARDUINO_LIBRARY_Wire_SRCS libraries/Wire/src/Wire.cpp) + +set(ARDUINO_LIBRARY_Zigbee_SRCS + libraries/Zigbee/src/ZigbeeCore.cpp + libraries/Zigbee/src/ZigbeeEP.cpp + libraries/Zigbee/src/ZigbeeHandlers.cpp + libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp + libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp + libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp + libraries/Zigbee/src/ep/ZigbeeLight.cpp + libraries/Zigbee/src/ep/ZigbeeSwitch.cpp + libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp + libraries/Zigbee/src/ep/ZigbeeThermostat.cpp + libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp + libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp + libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp + libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp + libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp + libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp + libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp + libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp + libraries/Zigbee/src/ep/ZigbeeAnalog.cpp + libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp + libraries/Zigbee/src/ep/ZigbeeGateway.cpp + libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp + libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp + libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp + libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.cpp + libraries/Zigbee/src/ep/ZigbeeBinary.cpp + libraries/Zigbee/src/ep/ZigbeePowerOutlet.cpp + libraries/Zigbee/src/ep/ZigbeeFanControl.cpp + libraries/Zigbee/src/ep/ZigbeeMultistate.cpp + ) + +set(ARDUINO_LIBRARY_BLE_SRCS + libraries/BLE/src/BLE2901.cpp + libraries/BLE/src/BLE2902.cpp + libraries/BLE/src/BLE2904.cpp + libraries/BLE/src/BLEAddress.cpp + libraries/BLE/src/BLEAdvertisedDevice.cpp + libraries/BLE/src/BLEAdvertising.cpp + libraries/BLE/src/BLEBeacon.cpp + libraries/BLE/src/BLECharacteristic.cpp + libraries/BLE/src/BLECharacteristicMap.cpp + libraries/BLE/src/BLEClient.cpp + libraries/BLE/src/BLEDescriptor.cpp + libraries/BLE/src/BLEDescriptorMap.cpp + libraries/BLE/src/BLEDevice.cpp + libraries/BLE/src/BLEEddystoneTLM.cpp + libraries/BLE/src/BLEEddystoneURL.cpp + libraries/BLE/src/BLEExceptions.cpp + libraries/BLE/src/BLEHIDDevice.cpp + libraries/BLE/src/BLERemoteCharacteristic.cpp + libraries/BLE/src/BLERemoteDescriptor.cpp + libraries/BLE/src/BLERemoteService.cpp + libraries/BLE/src/BLEScan.cpp + libraries/BLE/src/BLESecurity.cpp + libraries/BLE/src/BLEServer.cpp + libraries/BLE/src/BLEService.cpp + libraries/BLE/src/BLEServiceMap.cpp + libraries/BLE/src/BLEUtils.cpp + libraries/BLE/src/BLEUUID.cpp + libraries/BLE/src/BLEValue.cpp + libraries/BLE/src/FreeRTOS.cpp + libraries/BLE/src/GeneralUtils.cpp + ) + +set(ARDUINO_LIBRARIES_SRCS) +set(ARDUINO_LIBRARIES_REQUIRES) +set(ARDUINO_LIBRARIES_INCLUDEDIRS) +foreach(libname IN LISTS ARDUINO_ALL_LIBRARIES) + if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_${libname}) + if(ARDUINO_LIBRARY_${libname}_SRCS) + list(APPEND ARDUINO_LIBRARIES_SRCS ${ARDUINO_LIBRARY_${libname}_SRCS}) + endif() + if(ARDUINO_LIBRARY_${libname}_REQUIRES) + list(APPEND ARDUINO_LIBRARIES_REQUIRES ${ARDUINO_LIBRARY_${libname}_REQUIRES}) + endif() + if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/libraries/${libname}/src) + list(APPEND ARDUINO_LIBRARIES_INCLUDEDIRS libraries/${libname}/src) + endif() + endif() +endforeach() + +set(includedirs variants/${CONFIG_ARDUINO_VARIANT}/ cores/esp32/ ${ARDUINO_LIBRARIES_INCLUDEDIRS}) +set(srcs ${CORE_SRCS} ${ARDUINO_LIBRARIES_SRCS}) +set(priv_includes cores/esp32/libb64) +set(requires spi_flash esp_partition mbedtls wpa_supplicant esp_adc esp_eth http_parser esp_ringbuf esp_driver_gptimer esp_driver_usb_serial_jtag driver esp_http_client esp_https_ota) +set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hid usb esp_psram ${ARDUINO_LIBRARIES_REQUIRES}) + +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread) + #if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work! + #if(CONFIG_OPENTHREAD_ENABLED) # Does not work! + if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5") # Sadly only this works + list(APPEND requires openthread) + endif() +endif() + +if(IDF_TARGET STREQUAL "esp32" OR IDF_TARGET STREQUAL "esp32s2" OR IDF_TARGET STREQUAL "esp32s3" OR IDF_TARGET STREQUAL "esp32p4") + list(APPEND requires esp_driver_touch_sens) +endif() + +idf_component_register(INCLUDE_DIRS ${includedirs} PRIV_INCLUDE_DIRS ${priv_includes} SRCS ${srcs} REQUIRES ${requires} PRIV_REQUIRES ${priv_requires}) + +if(NOT CONFIG_FREERTOS_HZ EQUAL 1000 AND NOT "$ENV{ARDUINO_SKIP_TICK_CHECK}") + # See delay() in cores/esp32/esp32-hal-misc.c. + message(FATAL_ERROR "esp32-arduino requires CONFIG_FREERTOS_HZ=1000 " + "(currently ${CONFIG_FREERTOS_HZ})") +endif() + +string(TOUPPER ${CONFIG_ARDUINO_VARIANT} idf_target_caps) +string(REPLACE "-" "_" idf_target_for_macro "${idf_target_caps}") +target_compile_options(${COMPONENT_TARGET} PUBLIC + -DARDUINO=10812 + -DARDUINO_${idf_target_for_macro}_DEV + -DARDUINO_ARCH_ESP32 + -DARDUINO_BOARD="${idf_target_caps}_DEV" + -DARDUINO_VARIANT="${CONFIG_ARDUINO_VARIANT}" + -DESP32=ESP32) + +if(CONFIG_AUTOSTART_ARDUINO) + # in autostart mode, arduino-esp32 contains app_main() function and needs to + # reference setup() and loop() in the main component. If we add main + # component to priv_requires then we create a large circular dependency + # (arduino-esp32 -> main -> arduino-esp32) and can get linker errors, so + # instead we add setup() and loop() to the undefined symbols list so the + # linker will always include them. + # + # (As they are C++ symbol, we need to add the C++ mangled names.) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u _Z5setupv -u _Z4loopv") +endif() + +# Fix for WiFi/Bluetooth linker errors when CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP is not enabled +# +# Problem: +# WiFi and Bluetooth binary libraries reference __wrap_esp_log_write functions. +# When CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP=y, esp_diagnostics provides these wrappers. +# When not set, no component provides them, causing "undefined reference" linker errors. +# +# Solution: +# cores/esp32/esp32-hal-log-wrapper.c provides simple pass-through wrapper implementations +# that forward calls to the real ESP-IDF logging functions without additional processing. +# +# Two linker flags are required: +# +# 1. --wrap=symbol: Sets up the wrapping/redirection mechanism +# Effect: esp_log_write() calls → redirected to → __wrap_esp_log_write() +# __real_esp_log_write() → created as alias → original esp_log_write() +# Note: Applied at build level (idf_build_set_property) so it works when Arduino is a component +# +# 2. -u symbol: Forces inclusion of wrapper symbols from static library +# Why needed: Static library linking is "lazy" - only pulls objects with referenced symbols. +# Without -u, linker sees wrapper as unreferenced and drops it from the library. +# The -u flag marks symbols as "undefined", forcing linker to search and include them. +# Analogy: Same technique used for setup()/loop() symbols (see above) +if(NOT CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=esp_log_write" APPEND) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=esp_log_writev" APPEND) + target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __wrap_esp_log_write" "-u __wrap_esp_log_writev") +endif() + +# OpenThread message pool: redirect to Arduino wrapper (BOARD_HAS_PSRAM / PSRAM-aware allocation). +# Same pattern as esp_log wrap: --wrap so calls use __wrap_* ; -u so linker keeps our wrapper .o. +# Applied on OpenThread-capable targets (same targets that may add openthread to requires). +if(CONFIG_OPENTHREAD_ENABLED AND CONFIG_SOC_IEEE802154_SUPPORTED) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=otPlatMessagePoolInit" APPEND) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=otPlatMessagePoolNew" APPEND) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=otPlatMessagePoolFree" APPEND) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=otPlatMessagePoolNumFreeBuffers" APPEND) + idf_build_set_property(LINK_OPTIONS "-Wl,--wrap=otPlatMessagePoolDeinit" APPEND) + target_link_libraries(${COMPONENT_LIB} INTERFACE + "-u __wrap_otPlatMessagePoolInit" + "-u __wrap_otPlatMessagePoolNew" + "-u __wrap_otPlatMessagePoolFree" + "-u __wrap_otPlatMessagePoolNumFreeBuffers" + "-u __wrap_otPlatMessagePoolDeinit") +endif() + +# This function adds a dependency on the given component if the component is included into the build. +function(maybe_add_component component_name) + idf_build_get_property(components BUILD_COMPONENTS) + if (${component_name} IN_LIST components) + idf_component_get_property(lib_name ${component_name} COMPONENT_LIB) + target_link_libraries(${COMPONENT_LIB} PUBLIC ${lib_name}) + endif() +endfunction() + +if(IDF_TARGET MATCHES "esp32s2|esp32s3|esp32p4" AND CONFIG_TINYUSB_ENABLED) + maybe_add_component(arduino_tinyusb) +endif() +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_ArduinoOTA) + maybe_add_component(esp_https_ota) +endif() +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_ESP_SR) + maybe_add_component(espressif__esp_sr) +endif() +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_Matter) + maybe_add_component(espressif__esp_matter) +endif() +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_LittleFS) + maybe_add_component(joltwallet__littlefs) +endif() +if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_WiFiProv) + maybe_add_component(espressif__network_provisioning) +endif() diff --git a/Kconfig.projbuild b/Kconfig.projbuild new file mode 100644 index 0000000..a276174 --- /dev/null +++ b/Kconfig.projbuild @@ -0,0 +1,445 @@ +menu "Arduino Configuration" + +config ARDUINO_VARIANT + string "Arduino target variant (board)" + default IDF_TARGET + help + The name of a target variant (e.g., a specific board) in the variants/ + folder, e.g. "heltec_wifi_lora_32_V2". The name is case sensitive. + Specifying a variant name different from the target enables additional + customization, for example the definition of GPIO pins. + +config ENABLE_ARDUINO_DEPENDS + bool + select LWIP_SO_RCVBUF + select ETHERNET + select WIFI_ENABLED + select ESP32_PHY_CALIBRATION_AND_DATA_STORAGE if IDF_TARGET_ESP32 + select MEMMAP_SMP + default "y" + +config AUTOSTART_ARDUINO + bool "Autostart Arduino setup and loop on boot" + default "n" + help + Enabling this option will implement app_main and start Arduino. + All you need to implement in your main.cpp is setup() and loop() + and include Arduino.h + If disabled, you can call initArduino() to run any preparations + required by the framework + +choice ARDUINO_RUNNING_CORE + bool "Core on which Arduino's setup() and loop() are running" + default ARDUINO_RUN_CORE0 if FREERTOS_UNICORE + default ARDUINO_RUN_CORE1 if !FREERTOS_UNICORE + help + Select on which core Arduino's setup() and loop() functions run + + config ARDUINO_RUN_CORE0 + bool "CORE 0" + config ARDUINO_RUN_CORE1 + bool "CORE 1" + depends on !FREERTOS_UNICORE + config ARDUINO_RUN_NO_AFFINITY + bool "BOTH" + depends on !FREERTOS_UNICORE + +endchoice + +config ARDUINO_RUNNING_CORE + int + default 0 if ARDUINO_RUN_CORE0 + default 1 if ARDUINO_RUN_CORE1 + default -1 if ARDUINO_RUN_NO_AFFINITY + +config ARDUINO_LOOP_STACK_SIZE + int "Loop thread stack size" + default 8192 + help + Amount of stack available for the Arduino task. + +choice ARDUINO_EVENT_RUNNING_CORE + bool "Core on which Arduino's event handler is running" + default ARDUINO_EVENT_RUN_CORE0 if FREERTOS_UNICORE + default ARDUINO_EVENT_RUN_CORE1 if !FREERTOS_UNICORE + help + Select on which core Arduino's WiFi.onEvent() run + + config ARDUINO_EVENT_RUN_CORE0 + bool "CORE 0" + config ARDUINO_EVENT_RUN_CORE1 + bool "CORE 1" + depends on !FREERTOS_UNICORE + config ARDUINO_EVENT_RUN_NO_AFFINITY + bool "BOTH" + depends on !FREERTOS_UNICORE + +endchoice + +config ARDUINO_EVENT_RUNNING_CORE + int + default 0 if ARDUINO_EVENT_RUN_CORE0 + default 1 if ARDUINO_EVENT_RUN_CORE1 + default -1 if ARDUINO_EVENT_RUN_NO_AFFINITY + +choice ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE + bool "Core on which Arduino's Serial Event task is running" + default ARDUINO_SERIAL_EVENT_RUN_CORE0 if FREERTOS_UNICORE + default ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY if !FREERTOS_UNICORE + help + Select on which core Arduino's Serial Event task run + + config ARDUINO_SERIAL_EVENT_RUN_CORE0 + bool "CORE 0" + config ARDUINO_SERIAL_EVENT_RUN_CORE1 + bool "CORE 1" + depends on !FREERTOS_UNICORE + config ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY + bool "BOTH" + depends on !FREERTOS_UNICORE + +endchoice + +config ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE + int + default 0 if ARDUINO_SERIAL_EVENT_RUN_CORE0 + default 1 if ARDUINO_SERIAL_EVENT_RUN_CORE1 + default -1 if ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY + +config ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE + int "Serial Event task stack size" + default 2048 + help + Amount of stack available for the Serial Event task. + +config ARDUINO_SERIAL_EVENT_TASK_PRIORITY + int "Priority of the Serial Event task" + default 24 + help + Select at what priority you want the Serial Event task to run. + +choice ARDUINO_UDP_RUNNING_CORE + bool "Core on which Arduino's UDP is running" + default ARDUINO_UDP_RUN_CORE0 + help + Select on which core Arduino's UDP run + + config ARDUINO_UDP_RUN_CORE0 + bool "CORE 0" + config ARDUINO_UDP_RUN_CORE1 + bool "CORE 1" + depends on !FREERTOS_UNICORE + config ARDUINO_UDP_RUN_NO_AFFINITY + bool "BOTH" + depends on !FREERTOS_UNICORE + +endchoice + +config ARDUINO_UDP_RUNNING_CORE + int + default 0 if ARDUINO_UDP_RUN_CORE0 + default 1 if ARDUINO_UDP_RUN_CORE1 + default -1 if ARDUINO_UDP_RUN_NO_AFFINITY + +config ARDUINO_UDP_TASK_PRIORITY + int "Priority of the UDP task" + default 3 + help + Select at what priority you want the UDP task to run. + +config ARDUINO_UDP_TASK_STACK_SIZE + int "UDP task stack size" + default 4096 + help + Amount of stack available for the UDP task. + +config ARDUINO_ISR_IRAM + bool "Run interrupts in IRAM" + default "n" + help + Enabling this option will Attach all interrupts with the IRAm flag. + It will also make some HAL function, like, digitalRead/Write and more + be loaded into IRAM for access inside ISRs. + Beware that this is a very dangerous setting. Enable it only if you + are fully aware of the consequences. + +config DISABLE_HAL_LOCKS + bool "Disable mutex locks for HAL" + default "n" + help + Enabling this option will run all hardware abstraction without locks. + While communication with external hardware will be faster, you need to + make sure that there is no option to use the same bus from another thread + or interrupt at the same time. Option is best used with Arduino enabled + and code implemented only in setup/loop and Arduino callbacks + +menu "Debug Log Configuration" +choice ARDUHAL_LOG_DEFAULT_LEVEL + bool "Default log level" + default ARDUHAL_LOG_DEFAULT_LEVEL_ERROR + help + Specify how much output to see in logs by default. + +config ARDUHAL_LOG_DEFAULT_LEVEL_NONE + bool "No output" +config ARDUHAL_LOG_DEFAULT_LEVEL_ERROR + bool "Error" +config ARDUHAL_LOG_DEFAULT_LEVEL_WARN + bool "Warning" +config ARDUHAL_LOG_DEFAULT_LEVEL_INFO + bool "Info" +config ARDUHAL_LOG_DEFAULT_LEVEL_DEBUG + bool "Debug" +config ARDUHAL_LOG_DEFAULT_LEVEL_VERBOSE + bool "Verbose" +endchoice + +config ARDUHAL_LOG_DEFAULT_LEVEL + int + default 0 if ARDUHAL_LOG_DEFAULT_LEVEL_NONE + default 1 if ARDUHAL_LOG_DEFAULT_LEVEL_ERROR + default 2 if ARDUHAL_LOG_DEFAULT_LEVEL_WARN + default 3 if ARDUHAL_LOG_DEFAULT_LEVEL_INFO + default 4 if ARDUHAL_LOG_DEFAULT_LEVEL_DEBUG + default 5 if ARDUHAL_LOG_DEFAULT_LEVEL_VERBOSE + +config ARDUHAL_LOG_COLORS + bool "Use ANSI terminal colors in log output" + default "n" + help + Enable ANSI terminal color codes in bootloader output. + In order to view these, your terminal program must support ANSI color codes. + +config ARDUHAL_ESP_LOG + bool "Forward ESP_LOGx to Arduino log output" + default "n" + help + This option will redefine the ESP_LOGx macros to Arduino's log_x macros. + To enable for your application, add the following after your includes: + #ifdef ARDUINO_ARCH_ESP32 + #include "esp32-hal-log.h" + #endif + +endmenu + +choice ARDUHAL_PARTITION_SCHEME + bool "Used partition scheme" + default ARDUHAL_PARTITION_SCHEME_DEFAULT + help + Specify which partition scheme to be used. + +config ARDUHAL_PARTITION_SCHEME_DEFAULT + bool "Default" +config ARDUHAL_PARTITION_SCHEME_MINIMAL + bool "Minimal (for 2MB FLASH)" +config ARDUHAL_PARTITION_SCHEME_NO_OTA + bool "No OTA (for large apps)" +config ARDUHAL_PARTITION_SCHEME_HUGE_APP + bool "Huge App (for very large apps)" +config ARDUHAL_PARTITION_SCHEME_MIN_SPIFFS + bool "Minimal SPIFFS (for large apps with OTA)" +endchoice + +config ARDUHAL_PARTITION_SCHEME + string + default "default" if ARDUHAL_PARTITION_SCHEME_DEFAULT + default "minimal" if ARDUHAL_PARTITION_SCHEME_MINIMAL + default "no_ota" if ARDUHAL_PARTITION_SCHEME_NO_OTA + default "huge_app" if ARDUHAL_PARTITION_SCHEME_HUGE_APP + default "min_spiffs" if ARDUHAL_PARTITION_SCHEME_MIN_SPIFFS + + +config AUTOCONNECT_WIFI + bool "Autoconnect WiFi on boot" + default "n" + depends on AUTOSTART_ARDUINO + select ARDUINO_SELECTIVE_WiFi + help + If enabled, WiFi will connect to the last used SSID (if station was enabled), + else connection will be started only after calling WiFi.begin(ssid, password) + +config ARDUINO_SELECTIVE_COMPILATION + bool "Include only specific Arduino libraries" + default n + +config ARDUINO_SELECTIVE_SPI + bool "Enable SPI" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Wire + bool "Enable Wire" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_ESP_SR + bool "Enable ESP-SR" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_EEPROM + bool "Enable EEPROM" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Preferences + bool "Enable Preferences" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Ticker + bool "Enable Ticker" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Update + bool "Enable Update" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Zigbee + bool "Enable Zigbee" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_FS + bool "Enable FS" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_SD + bool "Enable SD" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS + default y + +config ARDUINO_SELECTIVE_SD_MMC + bool "Enable SD_MMC" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS + default y + +config ARDUINO_SELECTIVE_SPIFFS + bool "Enable SPIFFS" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS + default y + +config ARDUINO_SELECTIVE_FFat + bool "Enable FFat" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS + default y + +config ARDUINO_SELECTIVE_LittleFS + bool "Enable LittleFS" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS + default y + +config ARDUINO_SELECTIVE_Network + bool "Enable Networking" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Ethernet + bool "Enable Ethernet" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_PPP + bool "Enable PPP" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Hash + bool "Enable Hash" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_ArduinoOTA + bool "Enable ArduinoOTA" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + select ARDUINO_SELECTIVE_Hash + select ARDUINO_SELECTIVE_ESPmDNS + default y + +config ARDUINO_SELECTIVE_AsyncUDP + bool "Enable AsyncUDP" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_DNSServer + bool "Enable DNSServer" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_ESPmDNS + bool "Enable ESPmDNS" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_HTTPClient + bool "Enable HTTPClient" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + select ARDUINO_SELECTIVE_NetworkClientSecure + default y + +config ARDUINO_SELECTIVE_Matter + bool "Enable Matter" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_NetBIOS + bool "Enable NetBIOS" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_WebServer + bool "Enable WebServer" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + select ARDUINO_SELECTIVE_FS + select ARDUINO_SELECTIVE_Hash + +config ARDUINO_SELECTIVE_WiFi + bool "Enable WiFi" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_NetworkClientSecure + bool "Enable NetworkClientSecure" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network + default y + +config ARDUINO_SELECTIVE_WiFiProv + bool "Enable WiFiProv" + depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network && ARDUINO_SELECTIVE_WiFi + default y + +config ARDUINO_SELECTIVE_BLE + bool "Enable BLE" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_BluetoothSerial + bool "Enable BluetoothSerial" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_SimpleBLE + bool "Enable SimpleBLE" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_RainMaker + bool "Enable RainMaker" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_OpenThread + bool "Enable OpenThread" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +config ARDUINO_SELECTIVE_Insights + bool "Enable Insights" + depends on ARDUINO_SELECTIVE_COMPILATION + default y + +endmenu diff --git a/boards.txt b/boards.txt new file mode 100644 index 0000000..f748f05 --- /dev/null +++ b/boards.txt @@ -0,0 +1,56399 @@ +# Official Espressif options +menu.UploadSpeed=Upload Speed +menu.USBMode=USB Mode +menu.CDCOnBoot=USB CDC On Boot +menu.MSCOnBoot=USB Firmware MSC On Boot +menu.DFUOnBoot=USB DFU On Boot +menu.UploadMode=Upload Mode +menu.CPUFreq=CPU Frequency +menu.FlashFreq=Flash Frequency +menu.FlashMode=Flash Mode +menu.FlashSize=Flash Size +menu.PartitionScheme=Partition Scheme +menu.DebugLevel=Core Debug Level +menu.PSRAM=PSRAM +menu.LoopCore=Arduino Runs On +menu.EventsCore=Events Run On +menu.MemoryType=Memory Type +menu.EraseFlash=Erase All Flash Before Sketch Upload +menu.JTAGAdapter=JTAG Adapter +menu.ZigbeeMode=Zigbee Mode +menu.PinNumbers=Pin Numbering +menu.ChipVariant=Chip Variant + +# Custom options +menu.Revision=Board Revision +menu.LORAWAN_REGION=LoRaWan Region +menu.LoRaWanDebugLevel=LoRaWan Debug Level +menu.LORAWAN_DEVEUI=LoRaWan DevEUI +menu.LORAWAN_PREAMBLE_LENGTH=LoRaWan Preamble Length +menu.SLOW_CLK_TPYE=Slow Clk Type(only for LoRaWAN) +menu.einksize=E-Ink Display Size +menu.NetworkLogLevel=Network Log Level +menu.DisplayModel=Display Model + +############################################################## +### DO NOT PUT BOARDS ABOVE THE OFFICIAL ESPRESSIF BOARDS! ### +############################################################## + +# Generic definition to be used for USB discovery of CDC/JTAG +esp32_family.name=ESP32 Family Device +esp32_family.hide=true +esp32_family.vid.0=0x303a +esp32_family.pid.0=0x1001 +esp32_family.upload_port.0.vid=0x303a +esp32_family.upload_port.0.pid=0x1001 +esp32_family.build.board=ESP32_FAMILY + +############################################################## + +esp32c2.name=ESP32C2 Dev Module +esp32c2.hide=true + +esp32c2.bootloader.tool=esptool_py +esp32c2.bootloader.tool.default=esptool_py + +esp32c2.upload.tool=esptool_py +esp32c2.upload.tool.default=esptool_py +esp32c2.upload.tool.network=esp_ota + +esp32c2.upload.maximum_size=1310720 +esp32c2.upload.maximum_data_size=327680 +esp32c2.upload.flags= +esp32c2.upload.extra_flags= +esp32c2.upload.use_1200bps_touch=false +esp32c2.upload.wait_for_upload_port=false + +esp32c2.serial.disableDTR=false +esp32c2.serial.disableRTS=false + +esp32c2.build.tarch=riscv32 +esp32c2.build.target=esp +esp32c2.build.mcu=esp32c2 +esp32c2.build.core=esp32 +esp32c2.build.variant=esp32c2 +esp32c2.build.board=ESP32C2_DEV +esp32c2.build.bootloader_addr=0x0 + +esp32c2.build.cdc_on_boot=0 +esp32c2.build.f_cpu=120000000L +esp32c2.build.flash_size=2MB +esp32c2.build.flash_freq=60m +esp32c2.build.flash_mode=qio +esp32c2.build.boot=qio +esp32c2.build.partitions=minimal +esp32c2.build.defines= + +esp32c2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c2.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c2.menu.PartitionScheme.default.build.partitions=default +esp32c2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c2.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c2.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c2.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32c2.menu.FlashMode.qio=QIO +esp32c2.menu.FlashMode.qio.build.flash_mode=dio +esp32c2.menu.FlashMode.qio.build.boot=qio +esp32c2.menu.FlashMode.dio=DIO +esp32c2.menu.FlashMode.dio.build.flash_mode=dio +esp32c2.menu.FlashMode.dio.build.boot=dio + +esp32c2.menu.FlashFreq.60=60MHz +esp32c2.menu.FlashFreq.60.build.flash_freq=60m +esp32c2.menu.FlashFreq.30=30MHz +esp32c2.menu.FlashFreq.30.build.flash_freq=30m + +esp32c2.menu.FlashSize.2M=2MB (16Mb) +esp32c2.menu.FlashSize.2M.build.flash_size=2MB +esp32c2.menu.FlashSize.4M=4MB (32Mb) +esp32c2.menu.FlashSize.4M.build.flash_size=4MB + +esp32c2.menu.UploadSpeed.921600=921600 +esp32c2.menu.UploadSpeed.921600.upload.speed=921600 +esp32c2.menu.UploadSpeed.115200=115200 +esp32c2.menu.UploadSpeed.115200.upload.speed=115200 +esp32c2.menu.UploadSpeed.256000.windows=256000 +esp32c2.menu.UploadSpeed.256000.upload.speed=256000 +esp32c2.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c2.menu.UploadSpeed.230400=230400 +esp32c2.menu.UploadSpeed.230400.upload.speed=230400 +esp32c2.menu.UploadSpeed.460800.linux=460800 +esp32c2.menu.UploadSpeed.460800.macosx=460800 +esp32c2.menu.UploadSpeed.460800.upload.speed=460800 +esp32c2.menu.UploadSpeed.512000.windows=512000 +esp32c2.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c2.menu.DebugLevel.none=None +esp32c2.menu.DebugLevel.none.build.code_debug=0 +esp32c2.menu.DebugLevel.error=Error +esp32c2.menu.DebugLevel.error.build.code_debug=1 +esp32c2.menu.DebugLevel.warn=Warn +esp32c2.menu.DebugLevel.warn.build.code_debug=2 +esp32c2.menu.DebugLevel.info=Info +esp32c2.menu.DebugLevel.info.build.code_debug=3 +esp32c2.menu.DebugLevel.debug=Debug +esp32c2.menu.DebugLevel.debug.build.code_debug=4 +esp32c2.menu.DebugLevel.verbose=Verbose +esp32c2.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c2.menu.EraseFlash.none=Disabled +esp32c2.menu.EraseFlash.none.upload.erase_cmd= +esp32c2.menu.EraseFlash.all=Enabled +esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32c5.name=ESP32C5 Dev Module + +esp32c5.bootloader.tool=esptool_py +esp32c5.bootloader.tool.default=esptool_py + +esp32c5.upload.tool=esptool_py +esp32c5.upload.tool.default=esptool_py +esp32c5.upload.tool.network=esp_ota + +esp32c5.upload.maximum_size=1310720 +esp32c5.upload.maximum_data_size=327680 +esp32c5.upload.flags= +esp32c5.upload.extra_flags= +esp32c5.upload.use_1200bps_touch=false +esp32c5.upload.wait_for_upload_port=false + +esp32c5.serial.disableDTR=false +esp32c5.serial.disableRTS=false + +esp32c5.build.tarch=riscv32 +esp32c5.build.target=esp +esp32c5.build.mcu=esp32c5 +esp32c5.build.core=esp32 +esp32c5.build.variant=esp32c5 +esp32c5.build.board=ESP32C5_DEV +esp32c5.build.bootloader_addr=0x2000 + +esp32c5.build.cdc_on_boot=0 +esp32c5.build.f_cpu=240000000L +esp32c5.build.flash_size=4MB +esp32c5.build.flash_freq=80m +esp32c5.build.flash_mode=qio +esp32c5.build.boot=qio +esp32c5.build.partitions=default +esp32c5.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c5.menu.JTAGAdapter.default=Disabled +esp32c5.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c5.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg +esp32c5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c5.menu.JTAGAdapter.external=FTDI Adapter +esp32c5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg +esp32c5.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg +esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c5.menu.PSRAM.disabled=Disabled +esp32c5.menu.PSRAM.disabled.build.defines= +esp32c5.menu.PSRAM.enabled=Enabled +esp32c5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32c5.menu.CDCOnBoot.default=Disabled +esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c5.menu.CDCOnBoot.cdc=Enabled +esp32c5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c5.menu.PartitionScheme.default.build.partitions=default +esp32c5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c5.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c5.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c5.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c5.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32c5.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32c5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32c5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32c5.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480 +esp32c5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs +esp32c5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB +esp32c5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720 +esp32c5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +esp32c5.menu.PartitionScheme.zigbee.build.partitions=zigbee +esp32c5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +esp32c5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +esp32c5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +esp32c5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +esp32c5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs +esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB +esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720 +esp32c5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32c5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32c5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32c5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32c5.menu.PartitionScheme.custom=Custom +esp32c5.menu.PartitionScheme.custom.build.partitions= +esp32c5.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32c5.menu.CPUFreq.240=240MHz (WiFi) +esp32c5.menu.CPUFreq.240.build.f_cpu=240000000L +esp32c5.menu.CPUFreq.120=120MHz (WiFi) +esp32c5.menu.CPUFreq.120.build.f_cpu=120000000L +esp32c5.menu.CPUFreq.80=80MHz (WiFi) +esp32c5.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c5.menu.CPUFreq.40=40MHz +esp32c5.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c5.menu.CPUFreq.20=20MHz +esp32c5.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c5.menu.CPUFreq.10=10MHz +esp32c5.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c5.menu.FlashMode.qio=QIO +esp32c5.menu.FlashMode.qio.build.flash_mode=dio +esp32c5.menu.FlashMode.qio.build.boot=qio +esp32c5.menu.FlashMode.dio=DIO +esp32c5.menu.FlashMode.dio.build.flash_mode=dio +esp32c5.menu.FlashMode.dio.build.boot=dio + +esp32c5.menu.FlashFreq.80=80MHz +esp32c5.menu.FlashFreq.80.build.flash_freq=80m +esp32c5.menu.FlashFreq.40=40MHz +esp32c5.menu.FlashFreq.40.build.flash_freq=40m + +esp32c5.menu.FlashSize.4M=4MB (32Mb) +esp32c5.menu.FlashSize.4M.build.flash_size=4MB +esp32c5.menu.FlashSize.8M=8MB (64Mb) +esp32c5.menu.FlashSize.8M.build.flash_size=8MB +esp32c5.menu.FlashSize.2M=2MB (16Mb) +esp32c5.menu.FlashSize.2M.build.flash_size=2MB +esp32c5.menu.FlashSize.16M=16MB (128Mb) +esp32c5.menu.FlashSize.16M.build.flash_size=16MB + +esp32c5.menu.UploadSpeed.921600=921600 +esp32c5.menu.UploadSpeed.921600.upload.speed=921600 +esp32c5.menu.UploadSpeed.115200=115200 +esp32c5.menu.UploadSpeed.115200.upload.speed=115200 +esp32c5.menu.UploadSpeed.256000.windows=256000 +esp32c5.menu.UploadSpeed.256000.upload.speed=256000 +esp32c5.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c5.menu.UploadSpeed.230400=230400 +esp32c5.menu.UploadSpeed.230400.upload.speed=230400 +esp32c5.menu.UploadSpeed.460800.linux=460800 +esp32c5.menu.UploadSpeed.460800.macosx=460800 +esp32c5.menu.UploadSpeed.460800.upload.speed=460800 +esp32c5.menu.UploadSpeed.512000.windows=512000 +esp32c5.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c5.menu.DebugLevel.none=None +esp32c5.menu.DebugLevel.none.build.code_debug=0 +esp32c5.menu.DebugLevel.error=Error +esp32c5.menu.DebugLevel.error.build.code_debug=1 +esp32c5.menu.DebugLevel.warn=Warn +esp32c5.menu.DebugLevel.warn.build.code_debug=2 +esp32c5.menu.DebugLevel.info=Info +esp32c5.menu.DebugLevel.info.build.code_debug=3 +esp32c5.menu.DebugLevel.debug=Debug +esp32c5.menu.DebugLevel.debug.build.code_debug=4 +esp32c5.menu.DebugLevel.verbose=Verbose +esp32c5.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c5.menu.EraseFlash.none=Disabled +esp32c5.menu.EraseFlash.none.upload.erase_cmd= +esp32c5.menu.EraseFlash.all=Enabled +esp32c5.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32c5.menu.ZigbeeMode.default=Disabled +esp32c5.menu.ZigbeeMode.default.build.zigbee_mode= +esp32c5.menu.ZigbeeMode.default.build.zigbee_libs= +esp32c5.menu.ZigbeeMode.ed=Zigbee ED (end device) +esp32c5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32c5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +esp32c5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32c5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +esp32c5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +esp32c5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## + +esp32p4.name=ESP32P4 Dev Module + +esp32p4.bootloader.tool=esptool_py +esp32p4.bootloader.tool.default=esptool_py + +esp32p4.upload.tool=esptool_py +esp32p4.upload.tool.default=esptool_py +esp32p4.upload.tool.network=esp_ota + +esp32p4.upload.maximum_size=1310720 +esp32p4.upload.maximum_data_size=327680 +esp32p4.upload.flags= +esp32p4.upload.extra_flags= +esp32p4.upload.use_1200bps_touch=false +esp32p4.upload.wait_for_upload_port=false + +esp32p4.serial.disableDTR=false +esp32p4.serial.disableRTS=false + +esp32p4.build.tarch=riscv32 +esp32p4.build.target=esp +esp32p4.build.mcu=esp32p4 +esp32p4.build.core=esp32 +esp32p4.build.variant=esp32p4 +esp32p4.build.chip_variant=esp32p4_es +esp32p4.build.board=ESP32P4_DEV +esp32p4.build.bootloader_addr=0x2000 + +esp32p4.build.usb_mode=0 +esp32p4.build.cdc_on_boot=0 +esp32p4.build.msc_on_boot=0 +esp32p4.build.dfu_on_boot=0 +esp32p4.build.f_cpu=360000000L +esp32p4.build.flash_size=4MB +esp32p4.build.flash_freq=80m +esp32p4.build.img_freq=80m +esp32p4.build.flash_mode=qio +esp32p4.build.boot=qio +esp32p4.build.partitions=default +esp32p4.build.defines= + +esp32p4.menu.ChipVariant.prev3=Before v3.00 +esp32p4.menu.ChipVariant.prev3.build.chip_variant=esp32p4_es +esp32p4.menu.ChipVariant.prev3.build.f_cpu=360000000L +esp32p4.menu.ChipVariant.postv3=v3.00 or newer +esp32p4.menu.ChipVariant.postv3.build.chip_variant=esp32p4 +esp32p4.menu.ChipVariant.postv3.build.f_cpu=400000000L + +## IDE 2.0 Seems to not update the value +esp32p4.menu.JTAGAdapter.default=Disabled +esp32p4.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32p4.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32p4.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg +esp32p4.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32p4.menu.JTAGAdapter.external=FTDI Adapter +esp32p4.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg +esp32p4.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32p4.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32p4.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg +esp32p4.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32p4.menu.PSRAM.disabled=Disabled +esp32p4.menu.PSRAM.disabled.build.defines= +esp32p4.menu.PSRAM.enabled=Enabled +esp32p4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32p4.menu.USBMode.default=USB-OTG (TinyUSB) +esp32p4.menu.USBMode.default.build.usb_mode=0 +esp32p4.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32p4.menu.USBMode.hwcdc.build.usb_mode=1 + +esp32p4.menu.CDCOnBoot.default=Disabled +esp32p4.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32p4.menu.CDCOnBoot.cdc=Enabled +esp32p4.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32p4.menu.MSCOnBoot.default=Disabled +esp32p4.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32p4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32p4.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32p4.menu.DFUOnBoot.default=Disabled +esp32p4.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32p4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32p4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32p4.menu.UploadMode.default=UART0 / Hardware CDC +esp32p4.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32p4.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32p4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32p4.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32p4.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32p4.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32p4.menu.PartitionScheme.default.build.partitions=default +esp32p4.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32p4.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32p4.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32p4.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32p4.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32p4.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32p4.menu.PartitionScheme.minimal.build.partitions=minimal +esp32p4.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32p4.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32p4.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32p4.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32p4.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32p4.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32p4.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32p4.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32p4.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32p4.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32p4.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32p4.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32p4.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32p4.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32p4.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32p4.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32p4.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32p4.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32p4.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32p4.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32p4.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32p4.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32p4.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32p4.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32p4.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32p4.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32p4.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32p4.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32p4.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32p4.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32p4.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32p4.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32p4.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32p4.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +esp32p4.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +esp32p4.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 +esp32p4.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +esp32p4.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +esp32p4.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +esp32p4.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +esp32p4.menu.PartitionScheme.custom=Custom +esp32p4.menu.PartitionScheme.custom.build.partitions= +esp32p4.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32p4.menu.FlashMode.qio=QIO +esp32p4.menu.FlashMode.qio.build.flash_mode=dio +esp32p4.menu.FlashMode.qio.build.boot=qio +esp32p4.menu.FlashMode.dio=DIO +esp32p4.menu.FlashMode.dio.build.flash_mode=dio +esp32p4.menu.FlashMode.dio.build.boot=dio + +esp32p4.menu.FlashFreq.80=80MHz +esp32p4.menu.FlashFreq.80.build.flash_freq=80m +esp32p4.menu.FlashFreq.40=40MHz +esp32p4.menu.FlashFreq.40.build.flash_freq=40m + +esp32p4.menu.FlashSize.4M=4MB (32Mb) +esp32p4.menu.FlashSize.4M.build.flash_size=4MB +esp32p4.menu.FlashSize.8M=8MB (64Mb) +esp32p4.menu.FlashSize.8M.build.flash_size=8MB +esp32p4.menu.FlashSize.8M.build.partitions=default_8MB +esp32p4.menu.FlashSize.2M=2MB (16Mb) +esp32p4.menu.FlashSize.2M.build.flash_size=2MB +esp32p4.menu.FlashSize.2M.build.partitions=minimal +esp32p4.menu.FlashSize.16M=16MB (128Mb) +esp32p4.menu.FlashSize.16M.build.flash_size=16MB +esp32p4.menu.FlashSize.32M=32MB (256Mb) +esp32p4.menu.FlashSize.32M.build.flash_size=32MB + +esp32p4.menu.UploadSpeed.921600=921600 +esp32p4.menu.UploadSpeed.921600.upload.speed=921600 +esp32p4.menu.UploadSpeed.115200=115200 +esp32p4.menu.UploadSpeed.115200.upload.speed=115200 +esp32p4.menu.UploadSpeed.256000.windows=256000 +esp32p4.menu.UploadSpeed.256000.upload.speed=256000 +esp32p4.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32p4.menu.UploadSpeed.230400=230400 +esp32p4.menu.UploadSpeed.230400.upload.speed=230400 +esp32p4.menu.UploadSpeed.460800.linux=460800 +esp32p4.menu.UploadSpeed.460800.macosx=460800 +esp32p4.menu.UploadSpeed.460800.upload.speed=460800 +esp32p4.menu.UploadSpeed.512000.windows=512000 +esp32p4.menu.UploadSpeed.512000.upload.speed=512000 + +esp32p4.menu.DebugLevel.none=None +esp32p4.menu.DebugLevel.none.build.code_debug=0 +esp32p4.menu.DebugLevel.error=Error +esp32p4.menu.DebugLevel.error.build.code_debug=1 +esp32p4.menu.DebugLevel.warn=Warn +esp32p4.menu.DebugLevel.warn.build.code_debug=2 +esp32p4.menu.DebugLevel.info=Info +esp32p4.menu.DebugLevel.info.build.code_debug=3 +esp32p4.menu.DebugLevel.debug=Debug +esp32p4.menu.DebugLevel.debug.build.code_debug=4 +esp32p4.menu.DebugLevel.verbose=Verbose +esp32p4.menu.DebugLevel.verbose.build.code_debug=5 + +esp32p4.menu.EraseFlash.none=Disabled +esp32p4.menu.EraseFlash.none.upload.erase_cmd= +esp32p4.menu.EraseFlash.all=Enabled +esp32p4.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32h2.name=ESP32H2 Dev Module + +esp32h2.bootloader.tool=esptool_py +esp32h2.bootloader.tool.default=esptool_py + +esp32h2.upload.tool=esptool_py +esp32h2.upload.tool.default=esptool_py +esp32h2.upload.tool.network=esp_ota + +esp32h2.upload.maximum_size=1310720 +esp32h2.upload.maximum_data_size=327680 +esp32h2.upload.flags= +esp32h2.upload.extra_flags= +esp32h2.upload.use_1200bps_touch=false +esp32h2.upload.wait_for_upload_port=false + +esp32h2.serial.disableDTR=false +esp32h2.serial.disableRTS=false + +esp32h2.build.tarch=riscv32 +esp32h2.build.target=esp +esp32h2.build.mcu=esp32h2 +esp32h2.build.core=esp32 +esp32h2.build.variant=esp32h2 +esp32h2.build.board=ESP32H2_DEV +esp32h2.build.bootloader_addr=0x0 + +esp32h2.build.cdc_on_boot=0 +esp32h2.build.f_cpu=96000000L +esp32h2.build.flash_size=4MB +esp32h2.build.flash_freq=64m +esp32h2.build.img_freq=48m +esp32h2.build.flash_mode=qio +esp32h2.build.boot=qio +esp32h2.build.partitions=default +esp32h2.build.defines= + +## IDE 2.0 Seems to not update the value +esp32h2.menu.JTAGAdapter.default=Disabled +esp32h2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32h2.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32h2.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg +esp32h2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32h2.menu.JTAGAdapter.external=FTDI Adapter +esp32h2.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg +esp32h2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32h2.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32h2.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg +esp32h2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32h2.menu.CDCOnBoot.default=Disabled +esp32h2.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32h2.menu.CDCOnBoot.cdc=Enabled +esp32h2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32h2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32h2.menu.PartitionScheme.default.build.partitions=default +esp32h2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32h2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32h2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32h2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32h2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32h2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32h2.menu.PartitionScheme.minimal.build.partitions=minimal +esp32h2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32h2.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32h2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32h2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32h2.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32h2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32h2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32h2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32h2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32h2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32h2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32h2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32h2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32h2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32h2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32h2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32h2.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32h2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32h2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32h2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32h2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32h2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32h2.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32h2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32h2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +#esp32h2.menu.PartitionScheme.rainmaker=RainMaker 4MB +#esp32h2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +#esp32h2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +#esp32h2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +#esp32h2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +#esp32h2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +#esp32h2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +#esp32h2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +#esp32h2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32h2.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs +esp32h2.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB +esp32h2.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720 +esp32h2.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +esp32h2.menu.PartitionScheme.zigbee.build.partitions=zigbee +esp32h2.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +esp32h2.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +esp32h2.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +esp32h2.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +esp32h2.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs +esp32h2.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB +esp32h2.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720 +esp32h2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32h2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32h2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32h2.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32h2.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32h2.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32h2.menu.PartitionScheme.custom=Custom +esp32h2.menu.PartitionScheme.custom.build.partitions= +esp32h2.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32h2.menu.FlashMode.qio=QIO +esp32h2.menu.FlashMode.qio.build.flash_mode=dio +esp32h2.menu.FlashMode.qio.build.boot=qio +esp32h2.menu.FlashMode.dio=DIO +esp32h2.menu.FlashMode.dio.build.flash_mode=dio +esp32h2.menu.FlashMode.dio.build.boot=dio + +esp32h2.menu.FlashFreq.64=64MHz +esp32h2.menu.FlashFreq.64.build.flash_freq=64m +esp32h2.menu.FlashFreq.64.build.img_freq=48m +#esp32h2.menu.FlashFreq.32=32MHz +#esp32h2.menu.FlashFreq.32.build.flash_freq=32m +#esp32h2.menu.FlashFreq.32.build.img_freq=24m +esp32h2.menu.FlashFreq.16=16MHz +esp32h2.menu.FlashFreq.16.build.flash_freq=16m +esp32h2.menu.FlashFreq.16.build.img_freq=12m + +esp32h2.menu.FlashSize.4M=4MB (32Mb) +esp32h2.menu.FlashSize.4M.build.flash_size=4MB +esp32h2.menu.FlashSize.8M=8MB (64Mb) +esp32h2.menu.FlashSize.8M.build.flash_size=8MB +esp32h2.menu.FlashSize.2M=2MB (16Mb) +esp32h2.menu.FlashSize.2M.build.flash_size=2MB +esp32h2.menu.FlashSize.16M=16MB (128Mb) +esp32h2.menu.FlashSize.16M.build.flash_size=16MB + +esp32h2.menu.UploadSpeed.921600=921600 +esp32h2.menu.UploadSpeed.921600.upload.speed=921600 +esp32h2.menu.UploadSpeed.115200=115200 +esp32h2.menu.UploadSpeed.115200.upload.speed=115200 +esp32h2.menu.UploadSpeed.256000.windows=256000 +esp32h2.menu.UploadSpeed.256000.upload.speed=256000 +esp32h2.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32h2.menu.UploadSpeed.230400=230400 +esp32h2.menu.UploadSpeed.230400.upload.speed=230400 +esp32h2.menu.UploadSpeed.460800.linux=460800 +esp32h2.menu.UploadSpeed.460800.macosx=460800 +esp32h2.menu.UploadSpeed.460800.upload.speed=460800 +esp32h2.menu.UploadSpeed.512000.windows=512000 +esp32h2.menu.UploadSpeed.512000.upload.speed=512000 + +esp32h2.menu.DebugLevel.none=None +esp32h2.menu.DebugLevel.none.build.code_debug=0 +esp32h2.menu.DebugLevel.error=Error +esp32h2.menu.DebugLevel.error.build.code_debug=1 +esp32h2.menu.DebugLevel.warn=Warn +esp32h2.menu.DebugLevel.warn.build.code_debug=2 +esp32h2.menu.DebugLevel.info=Info +esp32h2.menu.DebugLevel.info.build.code_debug=3 +esp32h2.menu.DebugLevel.debug=Debug +esp32h2.menu.DebugLevel.debug.build.code_debug=4 +esp32h2.menu.DebugLevel.verbose=Verbose +esp32h2.menu.DebugLevel.verbose.build.code_debug=5 + +esp32h2.menu.EraseFlash.none=Disabled +esp32h2.menu.EraseFlash.none.upload.erase_cmd= +esp32h2.menu.EraseFlash.all=Enabled +esp32h2.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32h2.menu.ZigbeeMode.default=Disabled +esp32h2.menu.ZigbeeMode.default.build.zigbee_mode= +esp32h2.menu.ZigbeeMode.default.build.zigbee_libs= +esp32h2.menu.ZigbeeMode.ed=Zigbee ED (end device) +esp32h2.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32h2.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +esp32h2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32h2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32h2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +esp32h2.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +esp32h2.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32h2.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +esp32h2.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +esp32h2.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32h2.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## + +esp32c6.name=ESP32C6 Dev Module + +esp32c6.bootloader.tool=esptool_py +esp32c6.bootloader.tool.default=esptool_py + +esp32c6.upload.tool=esptool_py +esp32c6.upload.tool.default=esptool_py +esp32c6.upload.tool.network=esp_ota + +esp32c6.upload.maximum_size=1310720 +esp32c6.upload.maximum_data_size=327680 +esp32c6.upload.flags= +esp32c6.upload.extra_flags= +esp32c6.upload.use_1200bps_touch=false +esp32c6.upload.wait_for_upload_port=false + +esp32c6.serial.disableDTR=false +esp32c6.serial.disableRTS=false + +esp32c6.build.tarch=riscv32 +esp32c6.build.target=esp +esp32c6.build.mcu=esp32c6 +esp32c6.build.core=esp32 +esp32c6.build.variant=esp32c6 +esp32c6.build.board=ESP32C6_DEV +esp32c6.build.bootloader_addr=0x0 + +esp32c6.build.cdc_on_boot=0 +esp32c6.build.f_cpu=160000000L +esp32c6.build.flash_size=4MB +esp32c6.build.flash_freq=80m +esp32c6.build.flash_mode=qio +esp32c6.build.boot=qio +esp32c6.build.partitions=default +esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c6.menu.JTAGAdapter.default=Disabled +esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c6.menu.JTAGAdapter.external=FTDI Adapter +esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c6.menu.CDCOnBoot.default=Disabled +esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c6.menu.CDCOnBoot.cdc=Enabled +esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c6.menu.PartitionScheme.default.build.partitions=default +esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c6.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32c6.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32c6.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32c6.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c6.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c6.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c6.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c6.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs +esp32c6.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB +esp32c6.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720 +esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +esp32c6.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +esp32c6.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +esp32c6.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +esp32c6.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs +esp32c6.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB +esp32c6.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720 +esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32c6.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32c6.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32c6.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32c6.menu.PartitionScheme.custom=Custom +esp32c6.menu.PartitionScheme.custom.build.partitions= +esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32c6.menu.CPUFreq.160=160MHz (WiFi) +esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c6.menu.CPUFreq.120=120MHz (WiFi) +esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L +esp32c6.menu.CPUFreq.80=80MHz (WiFi) +esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c6.menu.CPUFreq.40=40MHz +esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c6.menu.CPUFreq.20=20MHz +esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c6.menu.CPUFreq.10=10MHz +esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c6.menu.FlashMode.qio=QIO +esp32c6.menu.FlashMode.qio.build.flash_mode=dio +esp32c6.menu.FlashMode.qio.build.boot=qio +esp32c6.menu.FlashMode.dio=DIO +esp32c6.menu.FlashMode.dio.build.flash_mode=dio +esp32c6.menu.FlashMode.dio.build.boot=dio + +esp32c6.menu.FlashFreq.80=80MHz +esp32c6.menu.FlashFreq.80.build.flash_freq=80m +esp32c6.menu.FlashFreq.40=40MHz +esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +esp32c6.menu.FlashSize.4M=4MB (32Mb) +esp32c6.menu.FlashSize.4M.build.flash_size=4MB +esp32c6.menu.FlashSize.8M=8MB (64Mb) +esp32c6.menu.FlashSize.8M.build.flash_size=8MB +esp32c6.menu.FlashSize.2M=2MB (16Mb) +esp32c6.menu.FlashSize.2M.build.flash_size=2MB +esp32c6.menu.FlashSize.16M=16MB (128Mb) +esp32c6.menu.FlashSize.16M.build.flash_size=16MB + +esp32c6.menu.UploadSpeed.921600=921600 +esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +esp32c6.menu.UploadSpeed.115200=115200 +esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +esp32c6.menu.UploadSpeed.256000.windows=256000 +esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c6.menu.UploadSpeed.230400=230400 +esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +esp32c6.menu.UploadSpeed.460800.linux=460800 +esp32c6.menu.UploadSpeed.460800.macosx=460800 +esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +esp32c6.menu.UploadSpeed.512000.windows=512000 +esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c6.menu.DebugLevel.none=None +esp32c6.menu.DebugLevel.none.build.code_debug=0 +esp32c6.menu.DebugLevel.error=Error +esp32c6.menu.DebugLevel.error.build.code_debug=1 +esp32c6.menu.DebugLevel.warn=Warn +esp32c6.menu.DebugLevel.warn.build.code_debug=2 +esp32c6.menu.DebugLevel.info=Info +esp32c6.menu.DebugLevel.info.build.code_debug=3 +esp32c6.menu.DebugLevel.debug=Debug +esp32c6.menu.DebugLevel.debug.build.code_debug=4 +esp32c6.menu.DebugLevel.verbose=Verbose +esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c6.menu.EraseFlash.none=Disabled +esp32c6.menu.EraseFlash.none.upload.erase_cmd= +esp32c6.menu.EraseFlash.all=Enabled +esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32c6.menu.ZigbeeMode.default=Disabled +esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +esp32c6.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +esp32c6.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32c6.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +esp32c6.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## + +esp32c61.name=ESP32C61 Dev Module +esp32c61.hide=true + +esp32c61.bootloader.tool=esptool_py +esp32c61.bootloader.tool.default=esptool_py + +esp32c61.upload.tool=esptool_py +esp32c61.upload.tool.default=esptool_py +esp32c61.upload.tool.network=esp_ota + +esp32c61.upload.maximum_size=1310720 +esp32c61.upload.maximum_data_size=327680 +esp32c61.upload.flags= +esp32c61.upload.extra_flags= +esp32c61.upload.use_1200bps_touch=false +esp32c61.upload.wait_for_upload_port=false + +esp32c61.serial.disableDTR=false +esp32c61.serial.disableRTS=false + +esp32c61.build.tarch=riscv32 +esp32c61.build.target=esp +esp32c61.build.mcu=esp32c61 +esp32c61.build.core=esp32 +esp32c61.build.variant=esp32c61 +esp32c61.build.board=ESP32C61_DEV +esp32c61.build.bootloader_addr=0x0 + +esp32c61.build.cdc_on_boot=0 +esp32c61.build.f_cpu=160000000L +esp32c61.build.flash_size=4MB +esp32c61.build.flash_freq=80m +esp32c61.build.flash_mode=qio +esp32c61.build.boot=qio +esp32c61.build.partitions=default +esp32c61.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c61.menu.JTAGAdapter.default=Disabled +esp32c61.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c61.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c61.menu.JTAGAdapter.builtin.build.openocdscript=esp32c61-builtin.cfg +esp32c61.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c61.menu.JTAGAdapter.external=FTDI Adapter +esp32c61.menu.JTAGAdapter.external.build.openocdscript=esp32c61-ftdi.cfg +esp32c61.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c61.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c61.menu.JTAGAdapter.bridge.build.openocdscript=esp32c61-bridge.cfg +esp32c61.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c61.menu.PSRAM.disabled=Disabled +esp32c61.menu.PSRAM.disabled.build.defines= +esp32c61.menu.PSRAM.enabled=Enabled +esp32c61.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32c61.menu.CDCOnBoot.default=Disabled +esp32c61.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c61.menu.CDCOnBoot.cdc=Enabled +esp32c61.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c61.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c61.menu.PartitionScheme.default.build.partitions=default +esp32c61.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c61.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c61.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c61.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c61.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c61.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c61.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c61.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c61.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c61.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c61.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c61.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c61.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c61.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c61.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c61.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c61.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c61.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c61.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c61.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c61.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c61.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c61.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c61.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c61.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c61.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +esp32c61.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c61.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c61.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c61.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c61.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c61.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c61.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c61.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c61.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c61.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c61.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c61.menu.PartitionScheme.custom=Custom +esp32c61.menu.PartitionScheme.custom.build.partitions= +esp32c61.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +esp32c61.menu.CPUFreq.160=160MHz (WiFi) +esp32c61.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c61.menu.CPUFreq.120=120MHz (WiFi) +esp32c61.menu.CPUFreq.120.build.f_cpu=120000000L +esp32c61.menu.CPUFreq.80=80MHz (WiFi) +esp32c61.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c61.menu.CPUFreq.40=40MHz +esp32c61.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c61.menu.CPUFreq.20=20MHz +esp32c61.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c61.menu.CPUFreq.10=10MHz +esp32c61.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c61.menu.FlashMode.qio=QIO +esp32c61.menu.FlashMode.qio.build.flash_mode=dio +esp32c61.menu.FlashMode.qio.build.boot=qio +esp32c61.menu.FlashMode.dio=DIO +esp32c61.menu.FlashMode.dio.build.flash_mode=dio +esp32c61.menu.FlashMode.dio.build.boot=dio + +esp32c61.menu.FlashFreq.80=80MHz +esp32c61.menu.FlashFreq.80.build.flash_freq=80m +esp32c61.menu.FlashFreq.40=40MHz +esp32c61.menu.FlashFreq.40.build.flash_freq=40m + +esp32c61.menu.FlashSize.4M=4MB (32Mb) +esp32c61.menu.FlashSize.4M.build.flash_size=4MB +esp32c61.menu.FlashSize.8M=8MB (64Mb) +esp32c61.menu.FlashSize.8M.build.flash_size=8MB +esp32c61.menu.FlashSize.2M=2MB (16Mb) +esp32c61.menu.FlashSize.2M.build.flash_size=2MB + +esp32c61.menu.UploadSpeed.921600=921600 +esp32c61.menu.UploadSpeed.921600.upload.speed=921600 +esp32c61.menu.UploadSpeed.115200=115200 +esp32c61.menu.UploadSpeed.115200.upload.speed=115200 +esp32c61.menu.UploadSpeed.256000.windows=256000 +esp32c61.menu.UploadSpeed.256000.upload.speed=256000 +esp32c61.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c61.menu.UploadSpeed.230400=230400 +esp32c61.menu.UploadSpeed.230400.upload.speed=230400 +esp32c61.menu.UploadSpeed.460800.linux=460800 +esp32c61.menu.UploadSpeed.460800.macosx=460800 +esp32c61.menu.UploadSpeed.460800.upload.speed=460800 +esp32c61.menu.UploadSpeed.512000.windows=512000 +esp32c61.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c61.menu.DebugLevel.none=None +esp32c61.menu.DebugLevel.none.build.code_debug=0 +esp32c61.menu.DebugLevel.error=Error +esp32c61.menu.DebugLevel.error.build.code_debug=1 +esp32c61.menu.DebugLevel.warn=Warn +esp32c61.menu.DebugLevel.warn.build.code_debug=2 +esp32c61.menu.DebugLevel.info=Info +esp32c61.menu.DebugLevel.info.build.code_debug=3 +esp32c61.menu.DebugLevel.debug=Debug +esp32c61.menu.DebugLevel.debug.build.code_debug=4 +esp32c61.menu.DebugLevel.verbose=Verbose +esp32c61.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c61.menu.EraseFlash.none=Disabled +esp32c61.menu.EraseFlash.none.upload.erase_cmd= +esp32c61.menu.EraseFlash.all=Enabled +esp32c61.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3.name=ESP32S3 Dev Module + +esp32s3.bootloader.tool=esptool_py +esp32s3.bootloader.tool.default=esptool_py + +esp32s3.upload.tool=esptool_py +esp32s3.upload.tool.default=esptool_py +esp32s3.upload.tool.network=esp_ota + +esp32s3.upload.maximum_size=1310720 +esp32s3.upload.maximum_data_size=327680 +esp32s3.upload.flags= +esp32s3.upload.extra_flags= +esp32s3.upload.use_1200bps_touch=false +esp32s3.upload.wait_for_upload_port=false + +esp32s3.serial.disableDTR=false +esp32s3.serial.disableRTS=false + +esp32s3.build.tarch=xtensa +esp32s3.build.bootloader_addr=0x0 +esp32s3.build.target=esp32s3 +esp32s3.build.mcu=esp32s3 +esp32s3.build.core=esp32 +esp32s3.build.variant=esp32s3 +esp32s3.build.board=ESP32S3_DEV + +esp32s3.build.usb_mode=1 +esp32s3.build.cdc_on_boot=0 +esp32s3.build.msc_on_boot=0 +esp32s3.build.dfu_on_boot=0 +esp32s3.build.f_cpu=240000000L +esp32s3.build.flash_size=4MB +esp32s3.build.flash_freq=80m +esp32s3.build.flash_mode=dio +esp32s3.build.boot=qio +esp32s3.build.boot_freq=80m +esp32s3.build.partitions=default +esp32s3.build.defines= +esp32s3.build.loop_core= +esp32s3.build.event_core= +esp32s3.build.psram_type=qspi +esp32s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +esp32s3.menu.JTAGAdapter.default=Disabled +esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32s3.menu.JTAGAdapter.external=FTDI Adapter +esp32s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s3.menu.PSRAM.disabled=Disabled +esp32s3.menu.PSRAM.disabled.build.defines= +esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +esp32s3.menu.PSRAM.enabled=QSPI PSRAM +esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +esp32s3.menu.PSRAM.opi=OPI PSRAM +esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +esp32s3.menu.PSRAM.opi.build.psram_type=opi + +esp32s3.menu.FlashMode.qio=QIO 80MHz +esp32s3.menu.FlashMode.qio.build.flash_mode=dio +esp32s3.menu.FlashMode.qio.build.boot=qio +esp32s3.menu.FlashMode.qio.build.boot_freq=80m +esp32s3.menu.FlashMode.qio.build.flash_freq=80m +esp32s3.menu.FlashMode.qio120=QIO 120MHz +esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +esp32s3.menu.FlashMode.qio120.build.boot=qio +esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +esp32s3.menu.FlashMode.dio=DIO 80MHz +esp32s3.menu.FlashMode.dio.build.flash_mode=dio +esp32s3.menu.FlashMode.dio.build.boot=dio +esp32s3.menu.FlashMode.dio.build.boot_freq=80m +esp32s3.menu.FlashMode.dio.build.flash_freq=80m +esp32s3.menu.FlashMode.opi=OPI 80MHz +esp32s3.menu.FlashMode.opi.build.flash_mode=dout +esp32s3.menu.FlashMode.opi.build.boot=opi +esp32s3.menu.FlashMode.opi.build.boot_freq=80m +esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +esp32s3.menu.FlashSize.4M=4MB (32Mb) +esp32s3.menu.FlashSize.4M.build.flash_size=4MB +esp32s3.menu.FlashSize.8M=8MB (64Mb) +esp32s3.menu.FlashSize.8M.build.flash_size=8MB +esp32s3.menu.FlashSize.16M=16MB (128Mb) +esp32s3.menu.FlashSize.16M.build.flash_size=16MB +esp32s3.menu.FlashSize.32M=32MB (256Mb) +esp32s3.menu.FlashSize.32M.build.flash_size=32MB + +esp32s3.menu.LoopCore.1=Core 1 +esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3.menu.LoopCore.0=Core 0 +esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32s3.menu.EventsCore.1=Core 1 +esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32s3.menu.EventsCore.0=Core 0 +esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +esp32s3.menu.USBMode.default.build.usb_mode=0 + +esp32s3.menu.CDCOnBoot.default=Disabled +esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32s3.menu.CDCOnBoot.cdc=Enabled +esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32s3.menu.MSCOnBoot.default=Disabled +esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3.menu.DFUOnBoot.default=Disabled +esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3.menu.PartitionScheme.default.build.partitions=default +esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32s3.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32s3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32s3.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +esp32s3.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +esp32s3.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 +esp32s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +esp32s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +esp32s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +esp32s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +esp32s3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32s3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32s3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32s3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32s3.menu.PartitionScheme.custom=Custom +esp32s3.menu.PartitionScheme.custom.build.partitions= +esp32s3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s3.menu.CPUFreq.240=240MHz (WiFi) +esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s3.menu.CPUFreq.160=160MHz (WiFi) +esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s3.menu.CPUFreq.80=80MHz (WiFi) +esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s3.menu.CPUFreq.40=40MHz +esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s3.menu.CPUFreq.20=20MHz +esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s3.menu.CPUFreq.10=10MHz +esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s3.menu.UploadSpeed.921600=921600 +esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +esp32s3.menu.UploadSpeed.115200=115200 +esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +esp32s3.menu.UploadSpeed.256000.windows=256000 +esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s3.menu.UploadSpeed.230400=230400 +esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +esp32s3.menu.UploadSpeed.460800.linux=460800 +esp32s3.menu.UploadSpeed.460800.macosx=460800 +esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +esp32s3.menu.UploadSpeed.512000.windows=512000 +esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s3.menu.DebugLevel.none=None +esp32s3.menu.DebugLevel.none.build.code_debug=0 +esp32s3.menu.DebugLevel.error=Error +esp32s3.menu.DebugLevel.error.build.code_debug=1 +esp32s3.menu.DebugLevel.warn=Warn +esp32s3.menu.DebugLevel.warn.build.code_debug=2 +esp32s3.menu.DebugLevel.info=Info +esp32s3.menu.DebugLevel.info.build.code_debug=3 +esp32s3.menu.DebugLevel.debug=Debug +esp32s3.menu.DebugLevel.debug.build.code_debug=4 +esp32s3.menu.DebugLevel.verbose=Verbose +esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3.menu.EraseFlash.none=Disabled +esp32s3.menu.EraseFlash.none.upload.erase_cmd= +esp32s3.menu.EraseFlash.all=Enabled +esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32s3.menu.ZigbeeMode.default=Disabled +esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +esp32c3.name=ESP32C3 Dev Module + +esp32c3.bootloader.tool=esptool_py +esp32c3.bootloader.tool.default=esptool_py + +esp32c3.upload.tool=esptool_py +esp32c3.upload.tool.default=esptool_py +esp32c3.upload.tool.network=esp_ota + +esp32c3.upload.maximum_size=1310720 +esp32c3.upload.maximum_data_size=327680 +esp32c3.upload.flags= +esp32c3.upload.extra_flags= +esp32c3.upload.use_1200bps_touch=false +esp32c3.upload.wait_for_upload_port=false + +esp32c3.serial.disableDTR=false +esp32c3.serial.disableRTS=false + +esp32c3.build.tarch=riscv32 +esp32c3.build.target=esp +esp32c3.build.mcu=esp32c3 +esp32c3.build.core=esp32 +esp32c3.build.variant=esp32c3 +esp32c3.build.board=ESP32C3_DEV +esp32c3.build.bootloader_addr=0x0 + +esp32c3.build.cdc_on_boot=0 +esp32c3.build.f_cpu=160000000L +esp32c3.build.flash_size=4MB +esp32c3.build.flash_freq=80m +esp32c3.build.flash_mode=qio +esp32c3.build.boot=qio +esp32c3.build.partitions=default +esp32c3.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c3.menu.JTAGAdapter.default=Disabled +esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c3.menu.JTAGAdapter.external=FTDI Adapter +esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c3.menu.CDCOnBoot.default=Disabled +esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c3.menu.CDCOnBoot.cdc=Enabled +esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c3.menu.PartitionScheme.default.build.partitions=default +esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c3.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32c3.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32c3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32c3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32c3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32c3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32c3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32c3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32c3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32c3.menu.PartitionScheme.custom=Custom +esp32c3.menu.PartitionScheme.custom.build.partitions= +esp32c3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32c3.menu.CPUFreq.160=160MHz (WiFi) +esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c3.menu.CPUFreq.80=80MHz (WiFi) +esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c3.menu.CPUFreq.40=40MHz +esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c3.menu.CPUFreq.20=20MHz +esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c3.menu.CPUFreq.10=10MHz +esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c3.menu.FlashMode.qio=QIO +esp32c3.menu.FlashMode.qio.build.flash_mode=dio +esp32c3.menu.FlashMode.qio.build.boot=qio +esp32c3.menu.FlashMode.dio=DIO +esp32c3.menu.FlashMode.dio.build.flash_mode=dio +esp32c3.menu.FlashMode.dio.build.boot=dio + +esp32c3.menu.FlashFreq.80=80MHz +esp32c3.menu.FlashFreq.80.build.flash_freq=80m +esp32c3.menu.FlashFreq.40=40MHz +esp32c3.menu.FlashFreq.40.build.flash_freq=40m + +esp32c3.menu.FlashSize.4M=4MB (32Mb) +esp32c3.menu.FlashSize.4M.build.flash_size=4MB +esp32c3.menu.FlashSize.8M=8MB (64Mb) +esp32c3.menu.FlashSize.8M.build.flash_size=8MB +esp32c3.menu.FlashSize.2M=2MB (16Mb) +esp32c3.menu.FlashSize.2M.build.flash_size=2MB +esp32c3.menu.FlashSize.16M=16MB (128Mb) +esp32c3.menu.FlashSize.16M.build.flash_size=16MB + +esp32c3.menu.UploadSpeed.921600=921600 +esp32c3.menu.UploadSpeed.921600.upload.speed=921600 +esp32c3.menu.UploadSpeed.115200=115200 +esp32c3.menu.UploadSpeed.115200.upload.speed=115200 +esp32c3.menu.UploadSpeed.256000.windows=256000 +esp32c3.menu.UploadSpeed.256000.upload.speed=256000 +esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c3.menu.UploadSpeed.230400=230400 +esp32c3.menu.UploadSpeed.230400.upload.speed=230400 +esp32c3.menu.UploadSpeed.460800.linux=460800 +esp32c3.menu.UploadSpeed.460800.macosx=460800 +esp32c3.menu.UploadSpeed.460800.upload.speed=460800 +esp32c3.menu.UploadSpeed.512000.windows=512000 +esp32c3.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c3.menu.DebugLevel.none=None +esp32c3.menu.DebugLevel.none.build.code_debug=0 +esp32c3.menu.DebugLevel.error=Error +esp32c3.menu.DebugLevel.error.build.code_debug=1 +esp32c3.menu.DebugLevel.warn=Warn +esp32c3.menu.DebugLevel.warn.build.code_debug=2 +esp32c3.menu.DebugLevel.info=Info +esp32c3.menu.DebugLevel.info.build.code_debug=3 +esp32c3.menu.DebugLevel.debug=Debug +esp32c3.menu.DebugLevel.debug.build.code_debug=4 +esp32c3.menu.DebugLevel.verbose=Verbose +esp32c3.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c3.menu.EraseFlash.none=Disabled +esp32c3.menu.EraseFlash.none.upload.erase_cmd= +esp32c3.menu.EraseFlash.all=Enabled +esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32c3.menu.ZigbeeMode.default=Disabled +esp32c3.menu.ZigbeeMode.default.build.zigbee_mode= +esp32c3.menu.ZigbeeMode.default.build.zigbee_libs= +esp32c3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32c3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +esp32s2.name=ESP32S2 Dev Module +esp32s2.vid.0=0x303a +esp32s2.pid.0=0x0002 +esp32s2.upload_port.vid.0=0x303a +esp32s2.upload_port.pid.0=0x0002 + +esp32s2.bootloader.tool=esptool_py +esp32s2.bootloader.tool.default=esptool_py + +esp32s2.upload.tool=esptool_py +esp32s2.upload.tool.default=esptool_py +esp32s2.upload.tool.network=esp_ota + +esp32s2.upload.maximum_size=1310720 +esp32s2.upload.maximum_data_size=327680 +esp32s2.upload.flags= +esp32s2.upload.extra_flags= +esp32s2.upload.use_1200bps_touch=false +esp32s2.upload.wait_for_upload_port=false + +esp32s2.serial.disableDTR=false +esp32s2.serial.disableRTS=false + +esp32s2.build.tarch=xtensa +esp32s2.build.bootloader_addr=0x1000 +esp32s2.build.target=esp32s2 +esp32s2.build.mcu=esp32s2 +esp32s2.build.core=esp32 +esp32s2.build.variant=esp32s2 +esp32s2.build.board=ESP32S2_DEV + +esp32s2.build.cdc_on_boot=0 +esp32s2.build.msc_on_boot=0 +esp32s2.build.dfu_on_boot=0 +esp32s2.build.f_cpu=240000000L +esp32s2.build.flash_size=4MB +esp32s2.build.flash_freq=80m +esp32s2.build.flash_mode=dio +esp32s2.build.boot=qio +esp32s2.build.partitions=default +esp32s2.build.defines= + +## IDE 2.0 Seems to not update the value +esp32s2.menu.JTAGAdapter.default=Disabled +esp32s2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s2.menu.JTAGAdapter.external=FTDI Adapter +esp32s2.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg +esp32s2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s2.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg +esp32s2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s2.menu.CDCOnBoot.default=Disabled +esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32s2.menu.CDCOnBoot.cdc=Enabled +esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32s2.menu.MSCOnBoot.default=Disabled +esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s2.menu.MSCOnBoot.msc=Enabled +esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s2.menu.DFUOnBoot.default=Disabled +esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s2.menu.DFUOnBoot.dfu=Enabled +esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s2.menu.UploadMode.default=UART0 +esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s2.menu.UploadMode.cdc=Internal USB +esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s2.menu.PSRAM.disabled=Disabled +esp32s2.menu.PSRAM.disabled.build.defines= +esp32s2.menu.PSRAM.enabled=Enabled +esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s2.menu.PartitionScheme.default.build.partitions=default +esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32s2.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32s2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s2.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32s2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32s2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32s2.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32s2.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32s2.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32s2.menu.PartitionScheme.custom=Custom +esp32s2.menu.PartitionScheme.custom.build.partitions= +esp32s2.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s2.menu.CPUFreq.240=240MHz (WiFi) +esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s2.menu.CPUFreq.160=160MHz (WiFi) +esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s2.menu.CPUFreq.80=80MHz (WiFi) +esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s2.menu.CPUFreq.40=40MHz +esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s2.menu.CPUFreq.20=20MHz +esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s2.menu.CPUFreq.10=10MHz +esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s2.menu.FlashMode.qio=QIO +esp32s2.menu.FlashMode.qio.build.flash_mode=dio +esp32s2.menu.FlashMode.qio.build.boot=qio +esp32s2.menu.FlashMode.dio=DIO +esp32s2.menu.FlashMode.dio.build.flash_mode=dio +esp32s2.menu.FlashMode.dio.build.boot=dio + +esp32s2.menu.FlashFreq.80=80MHz +esp32s2.menu.FlashFreq.80.build.flash_freq=80m +esp32s2.menu.FlashFreq.40=40MHz +esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +esp32s2.menu.FlashSize.4M=4MB (32Mb) +esp32s2.menu.FlashSize.4M.build.flash_size=4MB +esp32s2.menu.FlashSize.8M=8MB (64Mb) +esp32s2.menu.FlashSize.8M.build.flash_size=8MB +esp32s2.menu.FlashSize.2M=2MB (16Mb) +esp32s2.menu.FlashSize.2M.build.flash_size=2MB +esp32s2.menu.FlashSize.16M=16MB (128Mb) +esp32s2.menu.FlashSize.16M.build.flash_size=16MB + +esp32s2.menu.UploadSpeed.921600=921600 +esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +esp32s2.menu.UploadSpeed.115200=115200 +esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +esp32s2.menu.UploadSpeed.256000.windows=256000 +esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s2.menu.UploadSpeed.230400=230400 +esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +esp32s2.menu.UploadSpeed.460800.linux=460800 +esp32s2.menu.UploadSpeed.460800.macosx=460800 +esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +esp32s2.menu.UploadSpeed.512000.windows=512000 +esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s2.menu.DebugLevel.none=None +esp32s2.menu.DebugLevel.none.build.code_debug=0 +esp32s2.menu.DebugLevel.error=Error +esp32s2.menu.DebugLevel.error.build.code_debug=1 +esp32s2.menu.DebugLevel.warn=Warn +esp32s2.menu.DebugLevel.warn.build.code_debug=2 +esp32s2.menu.DebugLevel.info=Info +esp32s2.menu.DebugLevel.info.build.code_debug=3 +esp32s2.menu.DebugLevel.debug=Debug +esp32s2.menu.DebugLevel.debug.build.code_debug=4 +esp32s2.menu.DebugLevel.verbose=Verbose +esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s2.menu.EraseFlash.none=Disabled +esp32s2.menu.EraseFlash.none.upload.erase_cmd= +esp32s2.menu.EraseFlash.all=Enabled +esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32s2.menu.ZigbeeMode.default=Disabled +esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +esp32.name=ESP32 Dev Module + +esp32.bootloader.tool=esptool_py +esp32.bootloader.tool.default=esptool_py + +esp32.upload.tool=esptool_py +esp32.upload.tool.default=esptool_py +esp32.upload.tool.network=esp_ota + +esp32.upload.maximum_size=1310720 +esp32.upload.maximum_data_size=327680 +esp32.upload.flags= +esp32.upload.extra_flags= + +esp32.serial.disableDTR=true +esp32.serial.disableRTS=true + +esp32.build.tarch=xtensa +esp32.build.bootloader_addr=0x1000 +esp32.build.target=esp32 +esp32.build.mcu=esp32 +esp32.build.core=esp32 +esp32.build.variant=esp32 +esp32.build.board=ESP32_DEV + +esp32.build.f_cpu=240000000L +esp32.build.flash_size=4MB +esp32.build.flash_freq=40m +esp32.build.flash_mode=dio +esp32.build.boot=dio +esp32.build.partitions=default +esp32.build.defines= +esp32.build.loop_core= +esp32.build.event_core= + +## IDE 2.0 Seems to not update the value +esp32.menu.JTAGAdapter.default=Disabled +esp32.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32.menu.JTAGAdapter.external=FTDI Adapter +esp32.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg +esp32.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg +esp32.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32.menu.PSRAM.disabled=Disabled +esp32.menu.PSRAM.disabled.build.defines= +esp32.menu.PSRAM.disabled.build.extra_libs= +esp32.menu.PSRAM.enabled=Enabled +esp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32.menu.PSRAM.enabled.build.extra_libs= + +esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32.menu.PartitionScheme.default.build.partitions=default +esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32.menu.PartitionScheme.minimal.build.partitions=minimal +esp32.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32.menu.PartitionScheme.storage_4MB=Storage APP (2MB APP/1MB NVS/1MB SPIFFS) +esp32.menu.PartitionScheme.storage_4MB.build.partitions=storage_4MB_noota +esp32.menu.PartitionScheme.storage_4MB.upload.maximum_size=2097152 +esp32.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +esp32.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +esp32.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +esp32.menu.PartitionScheme.custom=Custom +esp32.menu.PartitionScheme.custom.build.partitions= +esp32.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32.menu.CPUFreq.240.build.f_cpu=240000000L +esp32.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32.menu.CPUFreq.160.build.f_cpu=160000000L +esp32.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32.menu.CPUFreq.80.build.f_cpu=80000000L +esp32.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32.menu.CPUFreq.40.build.f_cpu=40000000L +esp32.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32.menu.CPUFreq.26.build.f_cpu=26000000L +esp32.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32.menu.CPUFreq.20.build.f_cpu=20000000L +esp32.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32.menu.CPUFreq.13.build.f_cpu=13000000L +esp32.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32.menu.FlashMode.qio=QIO +esp32.menu.FlashMode.qio.build.flash_mode=dio +esp32.menu.FlashMode.qio.build.boot=qio +esp32.menu.FlashMode.dio=DIO +esp32.menu.FlashMode.dio.build.flash_mode=dio +esp32.menu.FlashMode.dio.build.boot=dio + +esp32.menu.FlashFreq.80=80MHz +esp32.menu.FlashFreq.80.build.flash_freq=80m +esp32.menu.FlashFreq.40=40MHz +esp32.menu.FlashFreq.40.build.flash_freq=40m + +esp32.menu.FlashSize.4M=4MB (32Mb) +esp32.menu.FlashSize.4M.build.flash_size=4MB +esp32.menu.FlashSize.8M=8MB (64Mb) +esp32.menu.FlashSize.8M.build.flash_size=8MB +esp32.menu.FlashSize.2M=2MB (16Mb) +esp32.menu.FlashSize.2M.build.flash_size=2MB +esp32.menu.FlashSize.16M=16MB (128Mb) +esp32.menu.FlashSize.16M.build.flash_size=16MB + +esp32.menu.UploadSpeed.921600=921600 +esp32.menu.UploadSpeed.921600.upload.speed=921600 +esp32.menu.UploadSpeed.115200=115200 +esp32.menu.UploadSpeed.115200.upload.speed=115200 +esp32.menu.UploadSpeed.256000.windows=256000 +esp32.menu.UploadSpeed.256000.upload.speed=256000 +esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32.menu.UploadSpeed.230400=230400 +esp32.menu.UploadSpeed.230400.upload.speed=230400 +esp32.menu.UploadSpeed.460800.linux=460800 +esp32.menu.UploadSpeed.460800.macosx=460800 +esp32.menu.UploadSpeed.460800.upload.speed=460800 +esp32.menu.UploadSpeed.512000.windows=512000 +esp32.menu.UploadSpeed.512000.upload.speed=512000 + +esp32.menu.LoopCore.1=Core 1 +esp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32.menu.LoopCore.0=Core 0 +esp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32.menu.EventsCore.1=Core 1 +esp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32.menu.EventsCore.0=Core 0 +esp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32.menu.DebugLevel.none=None +esp32.menu.DebugLevel.none.build.code_debug=0 +esp32.menu.DebugLevel.error=Error +esp32.menu.DebugLevel.error.build.code_debug=1 +esp32.menu.DebugLevel.warn=Warn +esp32.menu.DebugLevel.warn.build.code_debug=2 +esp32.menu.DebugLevel.info=Info +esp32.menu.DebugLevel.info.build.code_debug=3 +esp32.menu.DebugLevel.debug=Debug +esp32.menu.DebugLevel.debug.build.code_debug=4 +esp32.menu.DebugLevel.verbose=Verbose +esp32.menu.DebugLevel.verbose.build.code_debug=5 + +esp32.menu.EraseFlash.none=Disabled +esp32.menu.EraseFlash.none.upload.erase_cmd= +esp32.menu.EraseFlash.all=Enabled +esp32.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32.menu.ZigbeeMode.default=Disabled +esp32.menu.ZigbeeMode.default.build.zigbee_mode= +esp32.menu.ZigbeeMode.default.build.zigbee_libs= +esp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +esp32da.name=ESP32-WROOM-DA Module + +esp32da.bootloader.tool=esptool_py +esp32da.bootloader.tool.default=esptool_py + +esp32da.upload.tool=esptool_py +esp32da.upload.tool.default=esptool_py +esp32da.upload.tool.network=esp_ota + +esp32da.upload.maximum_size=1310720 +esp32da.upload.maximum_data_size=327680 +esp32da.upload.flags= +esp32da.upload.extra_flags= + +esp32da.serial.disableDTR=true +esp32da.serial.disableRTS=true + +esp32da.build.tarch=xtensa +esp32da.build.bootloader_addr=0x1000 +esp32da.build.target=esp32 +esp32da.build.mcu=esp32 +esp32da.build.core=esp32 +esp32da.build.variant=esp32da +esp32da.build.board=ESP32_WROOM_DA + +esp32da.build.f_cpu=240000000L +esp32da.build.flash_size=4MB +esp32da.build.flash_freq=40m +esp32da.build.flash_mode=dio +esp32da.build.boot=dio +esp32da.build.partitions=default +esp32da.build.defines= +esp32da.build.loop_core= +esp32da.build.event_core= + +esp32da.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32da.menu.PartitionScheme.default.build.partitions=default +esp32da.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32da.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32da.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32da.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32da.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32da.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32da.menu.PartitionScheme.minimal.build.partitions=minimal +esp32da.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32da.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32da.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32da.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32da.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32da.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32da.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32da.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32da.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32da.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32da.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32da.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32da.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32da.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32da.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32da.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32da.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32da.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32da.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32da.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32da.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32da.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32da.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32da.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32da.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32da.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32da.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32da.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32da.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32da.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32da.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32da.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32da.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32da.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32da.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32da.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32da.menu.PartitionScheme.custom=Custom +esp32da.menu.PartitionScheme.custom.build.partitions= +esp32da.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32da.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32da.menu.CPUFreq.240.build.f_cpu=240000000L +esp32da.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32da.menu.CPUFreq.160.build.f_cpu=160000000L +esp32da.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32da.menu.CPUFreq.80.build.f_cpu=80000000L +esp32da.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32da.menu.CPUFreq.40.build.f_cpu=40000000L +esp32da.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32da.menu.CPUFreq.26.build.f_cpu=26000000L +esp32da.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32da.menu.CPUFreq.20.build.f_cpu=20000000L +esp32da.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32da.menu.CPUFreq.13.build.f_cpu=13000000L +esp32da.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32da.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32da.menu.FlashMode.qio=QIO +esp32da.menu.FlashMode.qio.build.flash_mode=dio +esp32da.menu.FlashMode.qio.build.boot=qio +esp32da.menu.FlashMode.dio=DIO +esp32da.menu.FlashMode.dio.build.flash_mode=dio +esp32da.menu.FlashMode.dio.build.boot=dio + +esp32da.menu.FlashFreq.80=80MHz +esp32da.menu.FlashFreq.80.build.flash_freq=80m +esp32da.menu.FlashFreq.40=40MHz +esp32da.menu.FlashFreq.40.build.flash_freq=40m + +esp32da.menu.FlashSize.4M=4MB (32Mb) +esp32da.menu.FlashSize.4M.build.flash_size=4MB +esp32da.menu.FlashSize.8M=8MB (64Mb) +esp32da.menu.FlashSize.8M.build.flash_size=8MB +esp32da.menu.FlashSize.16M=16MB (128Mb) +esp32da.menu.FlashSize.16M.build.flash_size=16MB + +esp32da.menu.UploadSpeed.921600=921600 +esp32da.menu.UploadSpeed.921600.upload.speed=921600 +esp32da.menu.UploadSpeed.115200=115200 +esp32da.menu.UploadSpeed.115200.upload.speed=115200 +esp32da.menu.UploadSpeed.256000.windows=256000 +esp32da.menu.UploadSpeed.256000.upload.speed=256000 +esp32da.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32da.menu.UploadSpeed.230400=230400 +esp32da.menu.UploadSpeed.230400.upload.speed=230400 +esp32da.menu.UploadSpeed.460800.linux=460800 +esp32da.menu.UploadSpeed.460800.macosx=460800 +esp32da.menu.UploadSpeed.460800.upload.speed=460800 +esp32da.menu.UploadSpeed.512000.windows=512000 +esp32da.menu.UploadSpeed.512000.upload.speed=512000 + +esp32da.menu.LoopCore.1=Core 1 +esp32da.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32da.menu.LoopCore.0=Core 0 +esp32da.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32da.menu.EventsCore.1=Core 1 +esp32da.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32da.menu.EventsCore.0=Core 0 +esp32da.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32da.menu.DebugLevel.none=None +esp32da.menu.DebugLevel.none.build.code_debug=0 +esp32da.menu.DebugLevel.error=Error +esp32da.menu.DebugLevel.error.build.code_debug=1 +esp32da.menu.DebugLevel.warn=Warn +esp32da.menu.DebugLevel.warn.build.code_debug=2 +esp32da.menu.DebugLevel.info=Info +esp32da.menu.DebugLevel.info.build.code_debug=3 +esp32da.menu.DebugLevel.debug=Debug +esp32da.menu.DebugLevel.debug.build.code_debug=4 +esp32da.menu.DebugLevel.verbose=Verbose +esp32da.menu.DebugLevel.verbose.build.code_debug=5 + +esp32da.menu.EraseFlash.none=Disabled +esp32da.menu.EraseFlash.none.upload.erase_cmd= +esp32da.menu.EraseFlash.all=Enabled +esp32da.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32wrover.name=ESP32 Wrover Module + +esp32wrover.bootloader.tool=esptool_py +esp32wrover.bootloader.tool.default=esptool_py + +esp32wrover.upload.tool=esptool_py +esp32wrover.upload.tool.default=esptool_py +esp32wrover.upload.tool.network=esp_ota + +esp32wrover.upload.maximum_size=1310720 +esp32wrover.upload.maximum_data_size=327680 +esp32wrover.upload.flags= +esp32wrover.upload.extra_flags= + +esp32wrover.serial.disableDTR=true +esp32wrover.serial.disableRTS=true + +esp32wrover.build.tarch=xtensa +esp32wrover.build.bootloader_addr=0x1000 +esp32wrover.build.target=esp32 +esp32wrover.build.mcu=esp32 +esp32wrover.build.core=esp32 +esp32wrover.build.variant=esp32 +esp32wrover.build.board=ESP32_DEV + +esp32wrover.build.f_cpu=240000000L +esp32wrover.build.flash_size=4MB +esp32wrover.build.flash_freq=40m +esp32wrover.build.flash_mode=dio +esp32wrover.build.boot=dio +esp32wrover.build.partitions=default +esp32wrover.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32wrover.build.extra_libs= + +esp32wrover.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32wrover.menu.PartitionScheme.default.build.partitions=default +esp32wrover.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32wrover.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32wrover.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32wrover.menu.PartitionScheme.minimal.build.partitions=minimal +esp32wrover.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32wrover.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32wrover.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32wrover.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32wrover.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32wrover.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32wrover.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32wrover.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32wrover.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32wrover.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32wrover.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32wrover.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32wrover.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32wrover.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32wrover.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32wrover.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32wrover.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32wrover.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32wrover.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32wrover.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32wrover.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32wrover.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32wrover.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32wrover.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32wrover.menu.PartitionScheme.custom=Custom +esp32wrover.menu.PartitionScheme.custom.build.partitions= +esp32wrover.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +esp32wrover.menu.FlashMode.qio=QIO +esp32wrover.menu.FlashMode.qio.build.flash_mode=dio +esp32wrover.menu.FlashMode.qio.build.boot=qio +esp32wrover.menu.FlashMode.dio=DIO +esp32wrover.menu.FlashMode.dio.build.flash_mode=dio +esp32wrover.menu.FlashMode.dio.build.boot=dio + +esp32wrover.menu.FlashFreq.80=80MHz +esp32wrover.menu.FlashFreq.80.build.flash_freq=80m +esp32wrover.menu.FlashFreq.40=40MHz +esp32wrover.menu.FlashFreq.40.build.flash_freq=40m + +esp32wrover.menu.UploadSpeed.921600=921600 +esp32wrover.menu.UploadSpeed.921600.upload.speed=921600 +esp32wrover.menu.UploadSpeed.115200=115200 +esp32wrover.menu.UploadSpeed.115200.upload.speed=115200 +esp32wrover.menu.UploadSpeed.256000.windows=256000 +esp32wrover.menu.UploadSpeed.256000.upload.speed=256000 +esp32wrover.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32wrover.menu.UploadSpeed.230400=230400 +esp32wrover.menu.UploadSpeed.230400.upload.speed=230400 +esp32wrover.menu.UploadSpeed.460800.linux=460800 +esp32wrover.menu.UploadSpeed.460800.macosx=460800 +esp32wrover.menu.UploadSpeed.460800.upload.speed=460800 +esp32wrover.menu.UploadSpeed.512000.windows=512000 +esp32wrover.menu.UploadSpeed.512000.upload.speed=512000 + +esp32wrover.menu.DebugLevel.none=None +esp32wrover.menu.DebugLevel.none.build.code_debug=0 +esp32wrover.menu.DebugLevel.error=Error +esp32wrover.menu.DebugLevel.error.build.code_debug=1 +esp32wrover.menu.DebugLevel.warn=Warn +esp32wrover.menu.DebugLevel.warn.build.code_debug=2 +esp32wrover.menu.DebugLevel.info=Info +esp32wrover.menu.DebugLevel.info.build.code_debug=3 +esp32wrover.menu.DebugLevel.debug=Debug +esp32wrover.menu.DebugLevel.debug.build.code_debug=4 +esp32wrover.menu.DebugLevel.verbose=Verbose +esp32wrover.menu.DebugLevel.verbose.build.code_debug=5 + +esp32wrover.menu.EraseFlash.none=Disabled +esp32wrover.menu.EraseFlash.none.upload.erase_cmd= +esp32wrover.menu.EraseFlash.all=Enabled +esp32wrover.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +pico32.name=ESP32 PICO-D4 + +pico32.bootloader.tool=esptool_py +pico32.bootloader.tool.default=esptool_py + +pico32.upload.tool=esptool_py +pico32.upload.tool.default=esptool_py +pico32.upload.tool.network=esp_ota + +pico32.upload.maximum_size=1310720 +pico32.upload.maximum_data_size=327680 +pico32.upload.flags= +pico32.upload.extra_flags= + +pico32.serial.disableDTR=true +pico32.serial.disableRTS=true + +pico32.build.tarch=xtensa +pico32.build.bootloader_addr=0x1000 +pico32.build.target=esp32 +pico32.build.mcu=esp32 +pico32.build.core=esp32 +pico32.build.variant=pico32 +pico32.build.board=ESP32_PICO + +pico32.build.f_cpu=240000000L +pico32.build.flash_size=4MB +pico32.build.flash_freq=80m +pico32.build.flash_mode=dio +pico32.build.boot=dio +pico32.build.partitions=default +pico32.build.defines= + +pico32.menu.PartitionScheme.default=Default +pico32.menu.PartitionScheme.default.build.partitions=default +pico32.menu.PartitionScheme.no_ota=No OTA (Large APP) +pico32.menu.PartitionScheme.no_ota.build.partitions=no_ota +pico32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pico32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +pico32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pico32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +pico32.menu.PartitionScheme.custom=Custom +pico32.menu.PartitionScheme.custom.build.partitions= +pico32.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +pico32.menu.UploadSpeed.921600=921600 +pico32.menu.UploadSpeed.921600.upload.speed=921600 +pico32.menu.UploadSpeed.115200=115200 +pico32.menu.UploadSpeed.115200.upload.speed=115200 +pico32.menu.UploadSpeed.256000.windows=256000 +pico32.menu.UploadSpeed.256000.upload.speed=256000 +pico32.menu.UploadSpeed.230400.windows.upload.speed=256000 +pico32.menu.UploadSpeed.230400=230400 +pico32.menu.UploadSpeed.230400.upload.speed=230400 +pico32.menu.UploadSpeed.460800.linux=460800 +pico32.menu.UploadSpeed.460800.macosx=460800 +pico32.menu.UploadSpeed.460800.upload.speed=460800 +pico32.menu.UploadSpeed.512000.windows=512000 +pico32.menu.UploadSpeed.512000.upload.speed=512000 + +pico32.menu.DebugLevel.none=None +pico32.menu.DebugLevel.none.build.code_debug=0 +pico32.menu.DebugLevel.error=Error +pico32.menu.DebugLevel.error.build.code_debug=1 +pico32.menu.DebugLevel.warn=Warn +pico32.menu.DebugLevel.warn.build.code_debug=2 +pico32.menu.DebugLevel.info=Info +pico32.menu.DebugLevel.info.build.code_debug=3 +pico32.menu.DebugLevel.debug=Debug +pico32.menu.DebugLevel.debug.build.code_debug=4 +pico32.menu.DebugLevel.verbose=Verbose +pico32.menu.DebugLevel.verbose.build.code_debug=5 + +pico32.menu.EraseFlash.none=Disabled +pico32.menu.EraseFlash.none.upload.erase_cmd= +pico32.menu.EraseFlash.all=Enabled +pico32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3-octal.name=ESP32S3 Dev Module Octal (WROOM2) + +esp32s3-octal.bootloader.tool=esptool_py +esp32s3-octal.bootloader.tool.default=esptool_py + +esp32s3-octal.upload.tool=esptool_py +esp32s3-octal.upload.tool.default=esptool_py +esp32s3-octal.upload.tool.network=esp_ota +esp32s3-octal.upload.maximum_size=1310720 +esp32s3-octal.upload.maximum_data_size=327680 +esp32s3-octal.upload.flags= +esp32s3-octal.upload.extra_flags= +esp32s3-octal.upload.use_1200bps_touch=false +esp32s3-octal.upload.wait_for_upload_port=false + +esp32s3-octal.serial.disableDTR=false +esp32s3-octal.serial.disableRTS=false + +esp32s3-octal.build.tarch=xtensa +esp32s3-octal.build.bootloader_addr=0x0 +esp32s3-octal.build.target=esp32s3 +esp32s3-octal.build.mcu=esp32s3 +esp32s3-octal.build.core=esp32 +esp32s3-octal.build.variant=esp32s3 +esp32s3-octal.build.board=ESP32S3_DEV + +esp32s3-octal.build.usb_mode=1 +esp32s3-octal.build.cdc_on_boot=0 +esp32s3-octal.build.msc_on_boot=0 +esp32s3-octal.build.dfu_on_boot=0 +esp32s3-octal.build.f_cpu=240000000L +esp32s3-octal.build.flash_size=4MB +esp32s3-octal.build.flash_freq=80m +esp32s3-octal.build.flash_mode=dio + +esp32s3-octal.build.boot=opi +esp32s3-octal.build.boot_freq=80m +esp32s3-octal.build.partitions=default +esp32s3-octal.build.defines= +esp32s3-octal.build.loop_core= +esp32s3-octal.build.event_core= +esp32s3-octal.build.psram_type=opi +esp32s3-octal.build.memory_type={build.boot}_{build.psram_type} + +esp32s3-octal.menu.JTAGAdapter.default=Disabled +esp32s3-octal.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s3-octal.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32s3-octal.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +esp32s3-octal.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32s3-octal.menu.JTAGAdapter.external=FTDI Adapter +esp32s3-octal.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +esp32s3-octal.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s3-octal.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s3-octal.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +esp32s3-octal.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s3-octal.menu.PSRAM.opi=OPI PSRAM +esp32s3-octal.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +esp32s3-octal.menu.PSRAM.opi.build.psram_type=opi +esp32s3-octal.menu.PSRAM.enabled=QSPI PSRAM +esp32s3-octal.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +esp32s3-octal.menu.PSRAM.enabled.build.psram_type=qspi +esp32s3-octal.menu.PSRAM.disabled=Disabled +esp32s3-octal.menu.PSRAM.disabled.build.defines= +esp32s3-octal.menu.PSRAM.disabled.build.psram_type=qspi + +esp32s3-octal.menu.FlashMode.opi=OPI 80MHz +esp32s3-octal.menu.FlashMode.opi.build.flash_mode=dout +esp32s3-octal.menu.FlashMode.opi.build.boot=opi +esp32s3-octal.menu.FlashMode.opi.build.boot_freq=80m +esp32s3-octal.menu.FlashMode.opi.build.flash_freq=80m +esp32s3-octal.menu.FlashMode.qio=QIO 80MHz +esp32s3-octal.menu.FlashMode.qio.build.flash_mode=dio +esp32s3-octal.menu.FlashMode.qio.build.boot=qio +esp32s3-octal.menu.FlashMode.qio.build.boot_freq=80m +esp32s3-octal.menu.FlashMode.qio.build.flash_freq=80m +esp32s3-octal.menu.FlashMode.qio120=QIO 120MHz +esp32s3-octal.menu.FlashMode.qio120.build.flash_mode=dio +esp32s3-octal.menu.FlashMode.qio120.build.boot=qio +esp32s3-octal.menu.FlashMode.qio120.build.boot_freq=120m +esp32s3-octal.menu.FlashMode.qio120.build.flash_freq=80m +esp32s3-octal.menu.FlashMode.dio=DIO 80MHz +esp32s3-octal.menu.FlashMode.dio.build.flash_mode=dio +esp32s3-octal.menu.FlashMode.dio.build.boot=dio +esp32s3-octal.menu.FlashMode.dio.build.boot_freq=80m +esp32s3-octal.menu.FlashMode.dio.build.flash_freq=80m + +esp32s3-octal.menu.FlashSize.16M=16MB (128Mb) +esp32s3-octal.menu.FlashSize.16M.build.flash_size=16MB +esp32s3-octal.menu.FlashSize.4M=4MB (32Mb) +esp32s3-octal.menu.FlashSize.4M.build.flash_size=4MB +esp32s3-octal.menu.FlashSize.8M=8MB (64Mb) +esp32s3-octal.menu.FlashSize.8M.build.flash_size=8MB +esp32s3-octal.menu.FlashSize.32M=32MB (256Mb) +esp32s3-octal.menu.FlashSize.32M.build.flash_size=32MB + +esp32s3-octal.menu.LoopCore.1=Core 1 +esp32s3-octal.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3-octal.menu.LoopCore.0=Core 0 +esp32s3-octal.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32s3-octal.menu.EventsCore.1=Core 1 +esp32s3-octal.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32s3-octal.menu.EventsCore.0=Core 0 +esp32s3-octal.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32s3-octal.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3-octal.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3-octal.menu.USBMode.default=USB-OTG (TinyUSB) +esp32s3-octal.menu.USBMode.default.build.usb_mode=0 + +esp32s3-octal.menu.CDCOnBoot.default=Disabled +esp32s3-octal.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32s3-octal.menu.CDCOnBoot.cdc=Enabled +esp32s3-octal.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32s3-octal.menu.MSCOnBoot.default=Disabled +esp32s3-octal.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3-octal.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3-octal.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3-octal.menu.DFUOnBoot.default=Disabled +esp32s3-octal.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3-octal.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3-octal.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3-octal.menu.UploadMode.default=UART0 / Hardware CDC +esp32s3-octal.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s3-octal.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s3-octal.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32s3-octal.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s3-octal.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s3-octal.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.default.build.partitions=default +esp32s3-octal.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3-octal.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3-octal.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3-octal.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3-octal.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s3-octal.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s3-octal.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3-octal.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3-octal.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3-octal.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3-octal.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3-octal.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3-octal.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3-octal.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3-octal.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3-octal.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3-octal.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3-octal.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3-octal.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s3-octal.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3-octal.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s3-octal.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s3-octal.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s3-octal.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s3-octal.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s3-octal.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s3-octal.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s3-octal.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s3-octal.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s3-octal.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s3-octal.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s3-octal.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s3-octal.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 + +esp32s3-octal.menu.CPUFreq.240=240MHz (WiFi) +esp32s3-octal.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s3-octal.menu.CPUFreq.160=160MHz (WiFi) +esp32s3-octal.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s3-octal.menu.CPUFreq.80=80MHz (WiFi) +esp32s3-octal.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s3-octal.menu.CPUFreq.40=40MHz +esp32s3-octal.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s3-octal.menu.CPUFreq.20=20MHz +esp32s3-octal.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s3-octal.menu.CPUFreq.10=10MHz +esp32s3-octal.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s3-octal.menu.UploadSpeed.921600=921600 +esp32s3-octal.menu.UploadSpeed.921600.upload.speed=921600 +esp32s3-octal.menu.UploadSpeed.115200=115200 +esp32s3-octal.menu.UploadSpeed.115200.upload.speed=115200 +esp32s3-octal.menu.UploadSpeed.256000.windows=256000 +esp32s3-octal.menu.UploadSpeed.256000.upload.speed=256000 +esp32s3-octal.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s3-octal.menu.UploadSpeed.230400=230400 +esp32s3-octal.menu.UploadSpeed.230400.upload.speed=230400 +esp32s3-octal.menu.UploadSpeed.460800.linux=460800 +esp32s3-octal.menu.UploadSpeed.460800.macosx=460800 +esp32s3-octal.menu.UploadSpeed.460800.upload.speed=460800 +esp32s3-octal.menu.UploadSpeed.512000.windows=512000 +esp32s3-octal.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s3-octal.menu.DebugLevel.none=None +esp32s3-octal.menu.DebugLevel.none.build.code_debug=0 +esp32s3-octal.menu.DebugLevel.error=Error +esp32s3-octal.menu.DebugLevel.error.build.code_debug=1 +esp32s3-octal.menu.DebugLevel.warn=Warn +esp32s3-octal.menu.DebugLevel.warn.build.code_debug=2 +esp32s3-octal.menu.DebugLevel.info=Info +esp32s3-octal.menu.DebugLevel.info.build.code_debug=3 +esp32s3-octal.menu.DebugLevel.debug=Debug +esp32s3-octal.menu.DebugLevel.debug.build.code_debug=4 +esp32s3-octal.menu.DebugLevel.verbose=Verbose +esp32s3-octal.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3-octal.menu.EraseFlash.none=Disabled +esp32s3-octal.menu.EraseFlash.none.upload.erase_cmd= +esp32s3-octal.menu.EraseFlash.all=Enabled +esp32s3-octal.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3box.name=ESP32-S3-Box + +esp32s3box.bootloader.tool=esptool_py +esp32s3box.bootloader.tool.default=esptool_py + +esp32s3box.upload.tool=esptool_py +esp32s3box.upload.tool.default=esptool_py +esp32s3box.upload.tool.network=esp_ota + +esp32s3box.upload.maximum_size=3145728 +esp32s3box.upload.maximum_data_size=327680 +esp32s3box.upload.speed=921600 +esp32s3box.upload.flags= +esp32s3box.upload.extra_flags= +esp32s3box.upload.use_1200bps_touch=false +esp32s3box.upload.wait_for_upload_port=false + +esp32s3box.serial.disableDTR=false +esp32s3box.serial.disableRTS=false + +esp32s3box.build.tarch=xtensa +esp32s3box.build.bootloader_addr=0x0 +esp32s3box.build.target=esp32s3 +esp32s3box.build.mcu=esp32s3 +esp32s3box.build.core=esp32 +esp32s3box.build.variant=esp32s3box +esp32s3box.build.board=ESP32_S3_BOX + +esp32s3box.build.usb_mode=1 +esp32s3box.build.cdc_on_boot=1 +esp32s3box.build.msc_on_boot=0 +esp32s3box.build.dfu_on_boot=0 +esp32s3box.build.f_cpu=240000000L +esp32s3box.build.flash_size=16MB +esp32s3box.build.flash_freq=80m +esp32s3box.build.flash_mode=dio +esp32s3box.build.boot=qio +esp32s3box.build.partitions=default +esp32s3box.build.defines=-DBOARD_HAS_PSRAM +esp32s3box.build.memory_type=qio_opi +esp32s3box.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3box.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +esp32s3box.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3box.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3box.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +esp32s3box.menu.USBMode.hwcdc.upload.wait_for_upload_port=false +esp32s3box.menu.USBMode.default=USB-OTG +esp32s3box.menu.USBMode.default.build.usb_mode=0 +esp32s3box.menu.USBMode.default.upload.use_1200bps_touch=true +esp32s3box.menu.USBMode.default.upload.wait_for_upload_port=true + +esp32s3box.menu.MSCOnBoot.default=Disabled +esp32s3box.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3box.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3box.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3box.menu.DFUOnBoot.default=Disabled +esp32s3box.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3box.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3box.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s3box.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s3box.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s3box.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s3box.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s3box.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s3box.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s3box.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +esp32s3box.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +esp32s3box.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +esp32s3box.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +esp32s3box.menu.PartitionScheme.custom=Custom +esp32s3box.menu.PartitionScheme.custom.build.partitions= +esp32s3box.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s3box.menu.DebugLevel.none=None +esp32s3box.menu.DebugLevel.none.build.code_debug=0 +esp32s3box.menu.DebugLevel.error=Error +esp32s3box.menu.DebugLevel.error.build.code_debug=1 +esp32s3box.menu.DebugLevel.warn=Warn +esp32s3box.menu.DebugLevel.warn.build.code_debug=2 +esp32s3box.menu.DebugLevel.info=Info +esp32s3box.menu.DebugLevel.info.build.code_debug=3 +esp32s3box.menu.DebugLevel.debug=Debug +esp32s3box.menu.DebugLevel.debug.build.code_debug=4 +esp32s3box.menu.DebugLevel.verbose=Verbose +esp32s3box.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3box.menu.EraseFlash.none=Disabled +esp32s3box.menu.EraseFlash.none.upload.erase_cmd= +esp32s3box.menu.EraseFlash.all=Enabled +esp32s3box.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3usbotg.name=ESP32-S3-USB-OTG + +esp32s3usbotg.bootloader.tool=esptool_py +esp32s3usbotg.bootloader.tool.default=esptool_py + +esp32s3usbotg.upload.tool=esptool_py +esp32s3usbotg.upload.tool.default=esptool_py +esp32s3usbotg.upload.tool.network=esp_ota + +esp32s3usbotg.upload.maximum_size=1310720 +esp32s3usbotg.upload.maximum_data_size=327680 +esp32s3usbotg.upload.speed=921600 +esp32s3usbotg.upload.flags= +esp32s3usbotg.upload.extra_flags= +esp32s3usbotg.upload.use_1200bps_touch=false +esp32s3usbotg.upload.wait_for_upload_port=false + +esp32s3usbotg.serial.disableDTR=false +esp32s3usbotg.serial.disableRTS=false + +esp32s3usbotg.build.tarch=xtensa +esp32s3usbotg.build.bootloader_addr=0x0 +esp32s3usbotg.build.target=esp32s3 +esp32s3usbotg.build.mcu=esp32s3 +esp32s3usbotg.build.core=esp32 +esp32s3usbotg.build.variant=esp32s3usbotg +esp32s3usbotg.build.board=ESP32_S3_USB_OTG + +esp32s3usbotg.build.usb_mode=0 +esp32s3usbotg.build.cdc_on_boot=0 +esp32s3usbotg.build.msc_on_boot=0 +esp32s3usbotg.build.dfu_on_boot=0 +esp32s3usbotg.build.f_cpu=240000000L +esp32s3usbotg.build.flash_size=8MB +esp32s3usbotg.build.flash_freq=80m +esp32s3usbotg.build.flash_mode=dio +esp32s3usbotg.build.boot=qio +esp32s3usbotg.build.partitions=default +esp32s3usbotg.build.defines= +esp32s3usbotg.build.memory_type=qio_qspi +esp32s3usbotg.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3usbotg.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +esp32s3usbotg.menu.USBMode.default=USB-OTG +esp32s3usbotg.menu.USBMode.default.build.usb_mode=0 +esp32s3usbotg.menu.USBMode.default.build.cdc_on_boot=0 +esp32s3usbotg.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3usbotg.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3usbotg.menu.USBMode.hwcdc.build.cdc_on_boot=1 + +esp32s3usbotg.menu.UploadMode.default=UART0 / Hardware CDC +esp32s3usbotg.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s3usbotg.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s3usbotg.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32s3usbotg.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s3usbotg.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s3usbotg.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.default.build.partitions=default +esp32s3usbotg.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3usbotg.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3usbotg.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3usbotg.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3usbotg.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3usbotg.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3usbotg.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3usbotg.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3usbotg.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3usbotg.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3usbotg.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3usbotg.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3usbotg.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3usbotg.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3usbotg.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3usbotg.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3usbotg.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s3usbotg.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3usbotg.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s3usbotg.menu.PartitionScheme.custom=Custom +esp32s3usbotg.menu.PartitionScheme.custom.build.partitions= +esp32s3usbotg.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +esp32s3usbotg.menu.DebugLevel.none=None +esp32s3usbotg.menu.DebugLevel.none.build.code_debug=0 +esp32s3usbotg.menu.DebugLevel.error=Error +esp32s3usbotg.menu.DebugLevel.error.build.code_debug=1 +esp32s3usbotg.menu.DebugLevel.warn=Warn +esp32s3usbotg.menu.DebugLevel.warn.build.code_debug=2 +esp32s3usbotg.menu.DebugLevel.info=Info +esp32s3usbotg.menu.DebugLevel.info.build.code_debug=3 +esp32s3usbotg.menu.DebugLevel.debug=Debug +esp32s3usbotg.menu.DebugLevel.debug.build.code_debug=4 +esp32s3usbotg.menu.DebugLevel.verbose=Verbose +esp32s3usbotg.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3usbotg.menu.EraseFlash.none=Disabled +esp32s3usbotg.menu.EraseFlash.none.upload.erase_cmd= +esp32s3usbotg.menu.EraseFlash.all=Enabled +esp32s3usbotg.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3camlcd.name=ESP32S3 CAM LCD + +esp32s3camlcd.bootloader.tool=esptool_py +esp32s3camlcd.bootloader.tool.default=esptool_py + +esp32s3camlcd.upload.tool=esptool_py +esp32s3camlcd.upload.tool.default=esptool_py +esp32s3camlcd.upload.tool.network=esp_ota + +esp32s3camlcd.upload.maximum_size=1310720 +esp32s3camlcd.upload.maximum_data_size=327680 +esp32s3camlcd.upload.flags= +esp32s3camlcd.upload.extra_flags= +esp32s3camlcd.upload.use_1200bps_touch=false +esp32s3camlcd.upload.wait_for_upload_port=false + +esp32s3camlcd.serial.disableDTR=false +esp32s3camlcd.serial.disableRTS=false + +esp32s3camlcd.build.tarch=xtensa +esp32s3camlcd.build.bootloader_addr=0x0 +esp32s3camlcd.build.target=esp32s3 +esp32s3camlcd.build.mcu=esp32s3 +esp32s3camlcd.build.core=esp32 +esp32s3camlcd.build.variant=esp32s3camlcd +esp32s3camlcd.build.board=ESP32S3_CAM_LCD + +esp32s3camlcd.build.usb_mode=1 +esp32s3camlcd.build.cdc_on_boot=0 +esp32s3camlcd.build.msc_on_boot=0 +esp32s3camlcd.build.dfu_on_boot=0 +esp32s3camlcd.build.f_cpu=240000000L +esp32s3camlcd.build.flash_size=4MB +esp32s3camlcd.build.flash_freq=80m +esp32s3camlcd.build.flash_mode=dout +esp32s3camlcd.build.boot=opi +esp32s3camlcd.build.partitions=default +esp32s3camlcd.build.defines=-DBOARD_HAS_PSRAM +esp32s3camlcd.build.memory_type=opi_opi +esp32s3camlcd.build.loop_core= +esp32s3camlcd.build.event_core= + +esp32s3camlcd.menu.LoopCore.1=Core 1 +esp32s3camlcd.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3camlcd.menu.LoopCore.0=Core 0 +esp32s3camlcd.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32s3camlcd.menu.EventsCore.1=Core 1 +esp32s3camlcd.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32s3camlcd.menu.EventsCore.0=Core 0 +esp32s3camlcd.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32s3camlcd.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.default.build.partitions=default +esp32s3camlcd.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3camlcd.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3camlcd.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s3camlcd.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3camlcd.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3camlcd.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3camlcd.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3camlcd.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3camlcd.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3camlcd.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3camlcd.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3camlcd.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3camlcd.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3camlcd.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3camlcd.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3camlcd.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s3camlcd.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3camlcd.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32s3camlcd.menu.UploadSpeed.921600=921600 +esp32s3camlcd.menu.UploadSpeed.921600.upload.speed=921600 +esp32s3camlcd.menu.UploadSpeed.115200=115200 +esp32s3camlcd.menu.UploadSpeed.115200.upload.speed=115200 +esp32s3camlcd.menu.UploadSpeed.256000.windows=256000 +esp32s3camlcd.menu.UploadSpeed.256000.upload.speed=256000 +esp32s3camlcd.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s3camlcd.menu.UploadSpeed.230400=230400 +esp32s3camlcd.menu.UploadSpeed.230400.upload.speed=230400 +esp32s3camlcd.menu.UploadSpeed.460800.linux=460800 +esp32s3camlcd.menu.UploadSpeed.460800.macosx=460800 +esp32s3camlcd.menu.UploadSpeed.460800.upload.speed=460800 +esp32s3camlcd.menu.UploadSpeed.512000.windows=512000 +esp32s3camlcd.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s3camlcd.menu.DebugLevel.none=None +esp32s3camlcd.menu.DebugLevel.none.build.code_debug=0 +esp32s3camlcd.menu.DebugLevel.error=Error +esp32s3camlcd.menu.DebugLevel.error.build.code_debug=1 +esp32s3camlcd.menu.DebugLevel.warn=Warn +esp32s3camlcd.menu.DebugLevel.warn.build.code_debug=2 +esp32s3camlcd.menu.DebugLevel.info=Info +esp32s3camlcd.menu.DebugLevel.info.build.code_debug=3 +esp32s3camlcd.menu.DebugLevel.debug=Debug +esp32s3camlcd.menu.DebugLevel.debug.build.code_debug=4 +esp32s3camlcd.menu.DebugLevel.verbose=Verbose +esp32s3camlcd.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3camlcd.menu.EraseFlash.none=Disabled +esp32s3camlcd.menu.EraseFlash.none.upload.erase_cmd= +esp32s3camlcd.menu.EraseFlash.all=Enabled +esp32s3camlcd.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s2usb.name=ESP32S2 Native USB +esp32s2usb.vid.0=0x303a +esp32s2usb.pid.0=0x0003 +esp32s2usb.upload_port.vid.0=0x303a +esp32s2usb.upload_port.pid.0=0x0003 + +esp32s2usb.bootloader.tool=esptool_py +esp32s2usb.bootloader.tool.default=esptool_py + +esp32s2usb.upload.tool=esptool_py +esp32s2usb.upload.tool.default=esptool_py +esp32s2usb.upload.tool.network=esp_ota + +esp32s2usb.upload.maximum_size=1310720 +esp32s2usb.upload.maximum_data_size=327680 +esp32s2usb.upload.flags= +esp32s2usb.upload.extra_flags= +esp32s2usb.upload.use_1200bps_touch=true +esp32s2usb.upload.wait_for_upload_port=true +esp32s2usb.upload.speed=921600 + +esp32s2usb.serial.disableDTR=false +esp32s2usb.serial.disableRTS=false + +esp32s2usb.build.tarch=xtensa +esp32s2usb.build.bootloader_addr=0x1000 +esp32s2usb.build.target=esp32s2 +esp32s2usb.build.mcu=esp32s2 +esp32s2usb.build.core=esp32 +esp32s2usb.build.variant=esp32s2usb +esp32s2usb.build.board=ESP32S2_USB + +esp32s2usb.build.cdc_on_boot=1 +esp32s2usb.build.msc_on_boot=1 +esp32s2usb.build.dfu_on_boot=1 +esp32s2usb.build.f_cpu=240000000L +esp32s2usb.build.flash_size=4MB +esp32s2usb.build.flash_freq=80m +esp32s2usb.build.flash_mode=dio +esp32s2usb.build.boot=qio +esp32s2usb.build.partitions=default +esp32s2usb.build.defines= + +esp32s2usb.menu.PSRAM.disabled=Disabled +esp32s2usb.menu.PSRAM.disabled.build.defines= +esp32s2usb.menu.PSRAM.enabled=Enabled +esp32s2usb.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32s2usb.menu.FlashSize.4M=4MB (32Mb) +esp32s2usb.menu.FlashSize.4M.build.flash_size=4MB +esp32s2usb.menu.FlashSize.8M=8MB (64Mb) +esp32s2usb.menu.FlashSize.8M.build.flash_size=8MB +esp32s2usb.menu.FlashSize.16M=16MB (128Mb) +esp32s2usb.menu.FlashSize.16M.build.flash_size=16MB + +esp32s2usb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s2usb.menu.PartitionScheme.default.build.partitions=default +esp32s2usb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s2usb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s2usb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s2usb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s2usb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s2usb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s2usb.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s2usb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s2usb.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s2usb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s2usb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s2usb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s2usb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s2usb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s2usb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s2usb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s2usb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s2usb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s2usb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s2usb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s2usb.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s2usb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s2usb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s2usb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s2usb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s2usb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s2usb.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s2usb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +esp32s2usb.menu.DebugLevel.none=None +esp32s2usb.menu.DebugLevel.none.build.code_debug=0 +esp32s2usb.menu.DebugLevel.error=Error +esp32s2usb.menu.DebugLevel.error.build.code_debug=1 +esp32s2usb.menu.DebugLevel.warn=Warn +esp32s2usb.menu.DebugLevel.warn.build.code_debug=2 +esp32s2usb.menu.DebugLevel.info=Info +esp32s2usb.menu.DebugLevel.info.build.code_debug=3 +esp32s2usb.menu.DebugLevel.debug=Debug +esp32s2usb.menu.DebugLevel.debug.build.code_debug=4 +esp32s2usb.menu.DebugLevel.verbose=Verbose +esp32s2usb.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s2usb.menu.EraseFlash.none=Disabled +esp32s2usb.menu.EraseFlash.none.upload.erase_cmd= +esp32s2usb.menu.EraseFlash.all=Enabled +esp32s2usb.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32wroverkit.name=ESP32 Wrover Kit (all versions) + +esp32wroverkit.bootloader.tool=esptool_py +esp32wroverkit.bootloader.tool.default=esptool_py + +esp32wroverkit.upload.tool=esptool_py +esp32wroverkit.upload.tool.default=esptool_py +esp32wroverkit.upload.tool.network=esp_ota + +esp32wroverkit.upload.maximum_size=1310720 +esp32wroverkit.upload.maximum_data_size=327680 +esp32wroverkit.upload.flags= +esp32wroverkit.upload.extra_flags= + +esp32wroverkit.serial.disableDTR=true +esp32wroverkit.serial.disableRTS=true + +esp32wroverkit.build.tarch=xtensa +esp32wroverkit.build.bootloader_addr=0x1000 +esp32wroverkit.build.target=esp32 +esp32wroverkit.build.mcu=esp32 +esp32wroverkit.build.core=esp32 +esp32wroverkit.build.variant=esp32 +esp32wroverkit.build.board=ESP32_WROVER_KIT + +esp32wroverkit.build.f_cpu=240000000L +esp32wroverkit.build.flash_size=4MB +esp32wroverkit.build.flash_freq=40m +esp32wroverkit.build.flash_mode=dio +esp32wroverkit.build.boot=dio +esp32wroverkit.build.partitions=default + +esp32wroverkit.menu.FlashSize.4M=4MB (32Mb) +esp32wroverkit.menu.FlashSize.4M.build.flash_size=4MB +esp32wroverkit.menu.FlashSize.8M=8MB (64Mb) +esp32wroverkit.menu.FlashSize.8M.build.flash_size=8MB +esp32wroverkit.menu.FlashSize.2M=2MB (16Mb) +esp32wroverkit.menu.FlashSize.2M.build.flash_size=2MB +esp32wroverkit.menu.FlashSize.16M=16MB (128Mb) +esp32wroverkit.menu.FlashSize.16M.build.flash_size=16MB + +esp32wroverkit.menu.PSRAM.enabled=Enabled +esp32wroverkit.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32wroverkit.menu.PSRAM.disabled=Disabled +esp32wroverkit.menu.PSRAM.disabled.build.defines= + +esp32wroverkit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.default.build.partitions=default +esp32wroverkit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32wroverkit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32wroverkit.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32wroverkit.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32wroverkit.menu.PartitionScheme.default_16MB=16M with spiffs (6.25MB APP/3.43MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +esp32wroverkit.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +esp32wroverkit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32wroverkit.menu.PartitionScheme.minimal.build.partitions=minimal +esp32wroverkit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32wroverkit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32wroverkit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32wroverkit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32wroverkit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32wroverkit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32wroverkit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32wroverkit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32wroverkit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32wroverkit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32wroverkit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32wroverkit.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32wroverkit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32wroverkit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32wroverkit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32wroverkit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32wroverkit.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32wroverkit.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32wroverkit.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32wroverkit.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32wroverkit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32wroverkit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32wroverkit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32wroverkit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32wroverkit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32wroverkit.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32wroverkit.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32wroverkit.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +esp32wroverkit.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32wroverkit.menu.CPUFreq.240.build.f_cpu=240000000L +esp32wroverkit.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32wroverkit.menu.CPUFreq.160.build.f_cpu=160000000L +esp32wroverkit.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32wroverkit.menu.CPUFreq.80.build.f_cpu=80000000L +esp32wroverkit.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32wroverkit.menu.CPUFreq.40.build.f_cpu=40000000L +esp32wroverkit.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32wroverkit.menu.CPUFreq.26.build.f_cpu=26000000L +esp32wroverkit.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32wroverkit.menu.CPUFreq.20.build.f_cpu=20000000L +esp32wroverkit.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32wroverkit.menu.CPUFreq.13.build.f_cpu=13000000L +esp32wroverkit.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32wroverkit.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32wroverkit.menu.FlashMode.qio=QIO +esp32wroverkit.menu.FlashMode.qio.build.flash_mode=dio +esp32wroverkit.menu.FlashMode.qio.build.boot=qio +esp32wroverkit.menu.FlashMode.dio=DIO +esp32wroverkit.menu.FlashMode.dio.build.flash_mode=dio +esp32wroverkit.menu.FlashMode.dio.build.boot=dio +esp32wroverkit.menu.FlashFreq.80=80MHz +esp32wroverkit.menu.FlashFreq.80.build.flash_freq=80m +esp32wroverkit.menu.FlashFreq.40=40MHz +esp32wroverkit.menu.FlashFreq.40.build.flash_freq=40m + +esp32wroverkit.menu.UploadSpeed.921600=921600 +esp32wroverkit.menu.UploadSpeed.921600.upload.speed=921600 +esp32wroverkit.menu.UploadSpeed.115200=115200 +esp32wroverkit.menu.UploadSpeed.115200.upload.speed=115200 +esp32wroverkit.menu.UploadSpeed.256000.windows=256000 +esp32wroverkit.menu.UploadSpeed.256000.upload.speed=256000 +esp32wroverkit.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32wroverkit.menu.UploadSpeed.230400=230400 +esp32wroverkit.menu.UploadSpeed.230400.upload.speed=230400 +esp32wroverkit.menu.UploadSpeed.460800.linux=460800 +esp32wroverkit.menu.UploadSpeed.460800.macosx=460800 +esp32wroverkit.menu.UploadSpeed.460800.upload.speed=460800 +esp32wroverkit.menu.UploadSpeed.512000.windows=512000 +esp32wroverkit.menu.UploadSpeed.512000.upload.speed=512000 + +esp32wroverkit.menu.DebugLevel.none=None +esp32wroverkit.menu.DebugLevel.none.build.code_debug=0 +esp32wroverkit.menu.DebugLevel.error=Error +esp32wroverkit.menu.DebugLevel.error.build.code_debug=1 +esp32wroverkit.menu.DebugLevel.warn=Warn +esp32wroverkit.menu.DebugLevel.warn.build.code_debug=2 +esp32wroverkit.menu.DebugLevel.info=Info +esp32wroverkit.menu.DebugLevel.info.build.code_debug=3 +esp32wroverkit.menu.DebugLevel.debug=Debug +esp32wroverkit.menu.DebugLevel.debug.build.code_debug=4 +esp32wroverkit.menu.DebugLevel.verbose=Verbose +esp32wroverkit.menu.DebugLevel.verbose.build.code_debug=5 + +esp32wroverkit.menu.EraseFlash.none=Disabled +esp32wroverkit.menu.EraseFlash.none.upload.erase_cmd= +esp32wroverkit.menu.EraseFlash.all=Enabled +esp32wroverkit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32p4_core_board.name=ESP32P4 Core Board + +esp32p4_core_board.bootloader.tool=esptool_py +esp32p4_core_board.bootloader.tool.default=esptool_py + +esp32p4_core_board.upload.tool=esptool_py +esp32p4_core_board.upload.tool.default=esptool_py +esp32p4_core_board.upload.tool.network=esp_ota + +esp32p4_core_board.upload.maximum_size=1310720 +esp32p4_core_board.upload.maximum_data_size=327680 +esp32p4_core_board.upload.flags= +esp32p4_core_board.upload.extra_flags= +esp32p4_core_board.upload.use_1200bps_touch=false +esp32p4_core_board.upload.wait_for_upload_port=false + +esp32p4_core_board.serial.disableDTR=false +esp32p4_core_board.serial.disableRTS=false + +esp32p4_core_board.build.tarch=riscv32 +esp32p4_core_board.build.target=esp +esp32p4_core_board.build.mcu=esp32p4 +esp32p4_core_board.build.core=esp32 +esp32p4_core_board.build.variant=esp32p4_core_board +esp32p4_core_board.build.chip_variant=esp32p4_es +esp32p4_core_board.build.board=ESP32P4_CORE_BOARD +esp32p4_core_board.build.bootloader_addr=0x2000 + +esp32p4_core_board.build.usb_mode=0 +esp32p4_core_board.build.cdc_on_boot=0 +esp32p4_core_board.build.msc_on_boot=0 +esp32p4_core_board.build.dfu_on_boot=0 +esp32p4_core_board.build.f_cpu=360000000L +esp32p4_core_board.build.flash_size=16MB +esp32p4_core_board.build.flash_freq=80m +esp32p4_core_board.build.img_freq=80m +esp32p4_core_board.build.flash_mode=qio +esp32p4_core_board.build.boot=qio +esp32p4_core_board.build.partitions=default +esp32p4_core_board.build.defines=-DBOARD_HAS_PSRAM + +esp32p4_core_board.menu.ChipVariant.prev3=Before v3.00 +esp32p4_core_board.menu.ChipVariant.prev3.build.chip_variant=esp32p4_es +esp32p4_core_board.menu.ChipVariant.prev3.build.f_cpu=360000000L +esp32p4_core_board.menu.ChipVariant.postv3=v3.00 or newer +esp32p4_core_board.menu.ChipVariant.postv3.build.chip_variant=esp32p4 +esp32p4_core_board.menu.ChipVariant.postv3.build.f_cpu=400000000L + +## IDE 2.0 Seems to not update the value +esp32p4_core_board.menu.JTAGAdapter.default=Disabled +esp32p4_core_board.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32p4_core_board.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32p4_core_board.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg +esp32p4_core_board.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32p4_core_board.menu.JTAGAdapter.external=FTDI Adapter +esp32p4_core_board.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg +esp32p4_core_board.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32p4_core_board.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32p4_core_board.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg +esp32p4_core_board.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32p4_core_board.menu.USBMode.default=USB-OTG (TinyUSB) +esp32p4_core_board.menu.USBMode.default.build.usb_mode=0 +esp32p4_core_board.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32p4_core_board.menu.USBMode.hwcdc.build.usb_mode=1 + +esp32p4_core_board.menu.CDCOnBoot.default=Disabled +esp32p4_core_board.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32p4_core_board.menu.CDCOnBoot.cdc=Enabled +esp32p4_core_board.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32p4_core_board.menu.MSCOnBoot.default=Disabled +esp32p4_core_board.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32p4_core_board.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32p4_core_board.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32p4_core_board.menu.DFUOnBoot.default=Disabled +esp32p4_core_board.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32p4_core_board.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32p4_core_board.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32p4_core_board.menu.UploadMode.default=UART0 / Hardware CDC +esp32p4_core_board.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32p4_core_board.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32p4_core_board.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32p4_core_board.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32p4_core_board.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32p4_core_board.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.default.build.partitions=default +esp32p4_core_board.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32p4_core_board.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32p4_core_board.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32p4_core_board.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32p4_core_board.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.minimal.build.partitions=minimal +esp32p4_core_board.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32p4_core_board.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32p4_core_board.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32p4_core_board.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32p4_core_board.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32p4_core_board.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32p4_core_board.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32p4_core_board.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32p4_core_board.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32p4_core_board.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32p4_core_board.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32p4_core_board.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32p4_core_board.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32p4_core_board.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32p4_core_board.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32p4_core_board.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32p4_core_board.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32p4_core_board.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32p4_core_board.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32p4_core_board.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32p4_core_board.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32p4_core_board.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32p4_core_board.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32p4_core_board.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32p4_core_board.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +esp32p4_core_board.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +esp32p4_core_board.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +esp32p4_core_board.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +esp32p4_core_board.menu.PartitionScheme.custom=Custom +esp32p4_core_board.menu.PartitionScheme.custom.build.partitions= +esp32p4_core_board.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32p4_core_board.menu.UploadSpeed.921600=921600 +esp32p4_core_board.menu.UploadSpeed.921600.upload.speed=921600 +esp32p4_core_board.menu.UploadSpeed.115200=115200 +esp32p4_core_board.menu.UploadSpeed.115200.upload.speed=115200 +esp32p4_core_board.menu.UploadSpeed.256000.windows=256000 +esp32p4_core_board.menu.UploadSpeed.256000.upload.speed=256000 +esp32p4_core_board.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32p4_core_board.menu.UploadSpeed.230400=230400 +esp32p4_core_board.menu.UploadSpeed.230400.upload.speed=230400 +esp32p4_core_board.menu.UploadSpeed.460800.linux=460800 +esp32p4_core_board.menu.UploadSpeed.460800.macosx=460800 +esp32p4_core_board.menu.UploadSpeed.460800.upload.speed=460800 +esp32p4_core_board.menu.UploadSpeed.512000.windows=512000 +esp32p4_core_board.menu.UploadSpeed.512000.upload.speed=512000 + +esp32p4_core_board.menu.DebugLevel.none=None +esp32p4_core_board.menu.DebugLevel.none.build.code_debug=0 +esp32p4_core_board.menu.DebugLevel.error=Error +esp32p4_core_board.menu.DebugLevel.error.build.code_debug=1 +esp32p4_core_board.menu.DebugLevel.warn=Warn +esp32p4_core_board.menu.DebugLevel.warn.build.code_debug=2 +esp32p4_core_board.menu.DebugLevel.info=Info +esp32p4_core_board.menu.DebugLevel.info.build.code_debug=3 +esp32p4_core_board.menu.DebugLevel.debug=Debug +esp32p4_core_board.menu.DebugLevel.debug.build.code_debug=4 +esp32p4_core_board.menu.DebugLevel.verbose=Verbose +esp32p4_core_board.menu.DebugLevel.verbose.build.code_debug=5 + +esp32p4_core_board.menu.EraseFlash.none=Disabled +esp32p4_core_board.menu.EraseFlash.none.upload.erase_cmd= +esp32p4_core_board.menu.EraseFlash.all=Enabled +esp32p4_core_board.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +aventen_s3_sync.name=Aventen S3 Sync +## Based upon ESP32-S3 Dev Board + +aventen_s3_sync.bootloader.tool=esptool_py +aventen_s3_sync.bootloader.tool.default=esptool_py + +aventen_s3_sync.upload.tool=esptool_py +aventen_s3_sync.upload.tool.default=esptool_py +aventen_s3_sync.upload.tool.network=esp_ota + +aventen_s3_sync.upload.maximum_size=1310720 +aventen_s3_sync.upload.maximum_data_size=327680 +aventen_s3_sync.upload.flags= +aventen_s3_sync.upload.extra_flags= +aventen_s3_sync.upload.use_1200bps_touch=false +aventen_s3_sync.upload.wait_for_upload_port=false + +aventen_s3_sync.serial.disableDTR=false +aventen_s3_sync.serial.disableRTS=false + +aventen_s3_sync.build.tarch=xtensa +aventen_s3_sync.build.bootloader_addr=0x0 +aventen_s3_sync.build.target=esp32s3 +aventen_s3_sync.build.mcu=esp32s3 +aventen_s3_sync.build.core=esp32 +aventen_s3_sync.build.variant=Aventen_S3_Sync +aventen_s3_sync.build.board=AVENTEN_S3_SYNC + +aventen_s3_sync.build.usb_mode=1 +aventen_s3_sync.build.cdc_on_boot=0 +aventen_s3_sync.build.msc_on_boot=0 +aventen_s3_sync.build.dfu_on_boot=0 +aventen_s3_sync.build.f_cpu=240000000L +aventen_s3_sync.build.flash_size=16MB +aventen_s3_sync.build.flash_freq=80m +aventen_s3_sync.build.flash_mode=dio +aventen_s3_sync.build.boot=qio +aventen_s3_sync.build.boot_freq=80m +aventen_s3_sync.build.partitions=default +aventen_s3_sync.build.defines= +aventen_s3_sync.build.loop_core= +aventen_s3_sync.build.event_core= +aventen_s3_sync.build.psram_type=qspi +aventen_s3_sync.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 +aventen_s3_sync.menu.JTAGAdapter.default=Disabled +aventen_s3_sync.menu.JTAGAdapter.default.build.copy_jtag_files=0 +aventen_s3_sync.menu.JTAGAdapter.builtin=Integrated USB JTAG +aventen_s3_sync.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +aventen_s3_sync.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +aventen_s3_sync.menu.JTAGAdapter.external=FTDI Adapter +aventen_s3_sync.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +aventen_s3_sync.menu.JTAGAdapter.external.build.copy_jtag_files=1 +aventen_s3_sync.menu.JTAGAdapter.bridge=ESP USB Bridge +aventen_s3_sync.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +aventen_s3_sync.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +aventen_s3_sync.menu.PSRAM.disabled=Disabled +aventen_s3_sync.menu.PSRAM.disabled.build.defines= +aventen_s3_sync.menu.PSRAM.disabled.build.psram_type=qspi +aventen_s3_sync.menu.PSRAM.enabled=QSPI PSRAM +aventen_s3_sync.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +aventen_s3_sync.menu.PSRAM.enabled.build.psram_type=qspi +aventen_s3_sync.menu.PSRAM.opi=OPI PSRAM +aventen_s3_sync.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +aventen_s3_sync.menu.PSRAM.opi.build.psram_type=opi + +aventen_s3_sync.menu.FlashMode.qio=QIO 80MHz +aventen_s3_sync.menu.FlashMode.qio.build.flash_mode=dio +aventen_s3_sync.menu.FlashMode.qio.build.boot=qio +aventen_s3_sync.menu.FlashMode.qio.build.boot_freq=80m +aventen_s3_sync.menu.FlashMode.qio.build.flash_freq=80m +aventen_s3_sync.menu.FlashMode.qio120=QIO 120MHz +aventen_s3_sync.menu.FlashMode.qio120.build.flash_mode=dio +aventen_s3_sync.menu.FlashMode.qio120.build.boot=qio +aventen_s3_sync.menu.FlashMode.qio120.build.boot_freq=120m +aventen_s3_sync.menu.FlashMode.qio120.build.flash_freq=80m +aventen_s3_sync.menu.FlashMode.dio=DIO 80MHz +aventen_s3_sync.menu.FlashMode.dio.build.flash_mode=dio +aventen_s3_sync.menu.FlashMode.dio.build.boot=dio +aventen_s3_sync.menu.FlashMode.dio.build.boot_freq=80m +aventen_s3_sync.menu.FlashMode.dio.build.flash_freq=80m +aventen_s3_sync.menu.FlashMode.opi=OPI 80MHz +aventen_s3_sync.menu.FlashMode.opi.build.flash_mode=dout +aventen_s3_sync.menu.FlashMode.opi.build.boot=opi +aventen_s3_sync.menu.FlashMode.opi.build.boot_freq=80m +aventen_s3_sync.menu.FlashMode.opi.build.flash_freq=80m + +aventen_s3_sync.menu.FlashSize.16M=16MB (128Mb) +aventen_s3_sync.menu.FlashSize.16M.build.flash_size=16MB + +aventen_s3_sync.menu.LoopCore.1=Core 1 +aventen_s3_sync.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +aventen_s3_sync.menu.LoopCore.0=Core 0 +aventen_s3_sync.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +aventen_s3_sync.menu.EventsCore.1=Core 1 +aventen_s3_sync.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +aventen_s3_sync.menu.EventsCore.0=Core 0 +aventen_s3_sync.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +aventen_s3_sync.menu.USBMode.hwcdc=Hardware CDC and JTAG +aventen_s3_sync.menu.USBMode.hwcdc.build.usb_mode=1 +aventen_s3_sync.menu.USBMode.default=USB-OTG (TinyUSB) +aventen_s3_sync.menu.USBMode.default.build.usb_mode=0 + +aventen_s3_sync.menu.CDCOnBoot.default=Disabled +aventen_s3_sync.menu.CDCOnBoot.default.build.cdc_on_boot=0 +aventen_s3_sync.menu.CDCOnBoot.cdc=Enabled +aventen_s3_sync.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +aventen_s3_sync.menu.MSCOnBoot.default=Disabled +aventen_s3_sync.menu.MSCOnBoot.default.build.msc_on_boot=0 +aventen_s3_sync.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +aventen_s3_sync.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +aventen_s3_sync.menu.DFUOnBoot.default=Disabled +aventen_s3_sync.menu.DFUOnBoot.default.build.dfu_on_boot=0 +aventen_s3_sync.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +aventen_s3_sync.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +aventen_s3_sync.menu.UploadMode.default=UART0 / Hardware CDC +aventen_s3_sync.menu.UploadMode.default.upload.use_1200bps_touch=false +aventen_s3_sync.menu.UploadMode.default.upload.wait_for_upload_port=false +aventen_s3_sync.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +aventen_s3_sync.menu.UploadMode.cdc.upload.use_1200bps_touch=true +aventen_s3_sync.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +aventen_s3_sync.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.default.build.partitions=default +aventen_s3_sync.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +aventen_s3_sync.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +aventen_s3_sync.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +aventen_s3_sync.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +aventen_s3_sync.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.minimal.build.partitions=minimal +aventen_s3_sync.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.no_ota.build.partitions=no_ota +aventen_s3_sync.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +aventen_s3_sync.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +aventen_s3_sync.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +aventen_s3_sync.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +aventen_s3_sync.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +aventen_s3_sync.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +aventen_s3_sync.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +aventen_s3_sync.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +aventen_s3_sync.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +aventen_s3_sync.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.huge_app.build.partitions=huge_app +aventen_s3_sync.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +aventen_s3_sync.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +aventen_s3_sync.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +aventen_s3_sync.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +aventen_s3_sync.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +aventen_s3_sync.menu.PartitionScheme.fatflash.build.partitions=ffat +aventen_s3_sync.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +aventen_s3_sync.menu.PartitionScheme.rainmaker=RainMaker 4MB +aventen_s3_sync.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +aventen_s3_sync.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +aventen_s3_sync.menu.CPUFreq.240=240MHz (WiFi) +aventen_s3_sync.menu.CPUFreq.240.build.f_cpu=240000000L +aventen_s3_sync.menu.CPUFreq.160=160MHz (WiFi) +aventen_s3_sync.menu.CPUFreq.160.build.f_cpu=160000000L +aventen_s3_sync.menu.CPUFreq.80=80MHz (WiFi) +aventen_s3_sync.menu.CPUFreq.80.build.f_cpu=80000000L +aventen_s3_sync.menu.CPUFreq.40=40MHz +aventen_s3_sync.menu.CPUFreq.40.build.f_cpu=40000000L +aventen_s3_sync.menu.CPUFreq.20=20MHz +aventen_s3_sync.menu.CPUFreq.20.build.f_cpu=20000000L +aventen_s3_sync.menu.CPUFreq.10=10MHz +aventen_s3_sync.menu.CPUFreq.10.build.f_cpu=10000000L + +aventen_s3_sync.menu.UploadSpeed.921600=921600 +aventen_s3_sync.menu.UploadSpeed.921600.upload.speed=921600 +aventen_s3_sync.menu.UploadSpeed.115200=115200 +aventen_s3_sync.menu.UploadSpeed.115200.upload.speed=115200 +aventen_s3_sync.menu.UploadSpeed.256000.windows=256000 +aventen_s3_sync.menu.UploadSpeed.256000.upload.speed=256000 +aventen_s3_sync.menu.UploadSpeed.230400.windows.upload.speed=256000 +aventen_s3_sync.menu.UploadSpeed.230400=230400 +aventen_s3_sync.menu.UploadSpeed.230400.upload.speed=230400 +aventen_s3_sync.menu.UploadSpeed.460800.linux=460800 +aventen_s3_sync.menu.UploadSpeed.460800.macosx=460800 +aventen_s3_sync.menu.UploadSpeed.460800.upload.speed=460800 +aventen_s3_sync.menu.UploadSpeed.512000.windows=512000 +aventen_s3_sync.menu.UploadSpeed.512000.upload.speed=512000 + +aventen_s3_sync.menu.DebugLevel.none=None +aventen_s3_sync.menu.DebugLevel.none.build.code_debug=0 +aventen_s3_sync.menu.DebugLevel.error=Error +aventen_s3_sync.menu.DebugLevel.error.build.code_debug=1 +aventen_s3_sync.menu.DebugLevel.warn=Warn +aventen_s3_sync.menu.DebugLevel.warn.build.code_debug=2 +aventen_s3_sync.menu.DebugLevel.info=Info +aventen_s3_sync.menu.DebugLevel.info.build.code_debug=3 +aventen_s3_sync.menu.DebugLevel.debug=Debug +aventen_s3_sync.menu.DebugLevel.debug.build.code_debug=4 +aventen_s3_sync.menu.DebugLevel.verbose=Verbose +aventen_s3_sync.menu.DebugLevel.verbose.build.code_debug=5 + +aventen_s3_sync.menu.EraseFlash.none=Disabled +aventen_s3_sync.menu.EraseFlash.none.upload.erase_cmd= +aventen_s3_sync.menu.EraseFlash.all=Enabled +aventen_s3_sync.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +BharatPi-Node-Wifi.name=BharatPi Node Wifi Module + +BharatPi-Node-Wifi.bootloader.tool=esptool_py +BharatPi-Node-Wifi.bootloader.tool.default=esptool_py + +BharatPi-Node-Wifi.upload.tool=esptool_py +BharatPi-Node-Wifi.upload.tool.default=esptool_py +BharatPi-Node-Wifi.upload.tool.network=esp_ota + +BharatPi-Node-Wifi.upload.maximum_size=1310720 +BharatPi-Node-Wifi.upload.maximum_data_size=327680 +BharatPi-Node-Wifi.upload.flags= +BharatPi-Node-Wifi.upload.extra_flags= + +BharatPi-Node-Wifi.serial.disableDTR=true +BharatPi-Node-Wifi.serial.disableRTS=true + +BharatPi-Node-Wifi.build.tarch=xtensa +BharatPi-Node-Wifi.build.bootloader_addr=0x1000 +BharatPi-Node-Wifi.build.target=esp32 +BharatPi-Node-Wifi.build.mcu=esp32 +BharatPi-Node-Wifi.build.core=esp32 +BharatPi-Node-Wifi.build.variant=BharatPi-Node-Wifi +BharatPi-Node-Wifi.build.board=BHARATPI_NODE_WIFI + +BharatPi-Node-Wifi.build.f_cpu=240000000L +BharatPi-Node-Wifi.build.flash_size=4MB +BharatPi-Node-Wifi.build.flash_freq=40m +BharatPi-Node-Wifi.build.flash_mode=dio +BharatPi-Node-Wifi.build.boot=dio +BharatPi-Node-Wifi.build.partitions=default +BharatPi-Node-Wifi.build.defines= +BharatPi-Node-Wifi.build.loop_core= +BharatPi-Node-Wifi.build.event_core= + +BharatPi-Node-Wifi.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.default.build.partitions=default +BharatPi-Node-Wifi.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +BharatPi-Node-Wifi.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +BharatPi-Node-Wifi.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.minimal.build.partitions=minimal +BharatPi-Node-Wifi.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.no_ota.build.partitions=no_ota +BharatPi-Node-Wifi.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +BharatPi-Node-Wifi.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.huge_app.build.partitions=huge_app +BharatPi-Node-Wifi.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +BharatPi-Node-Wifi.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +BharatPi-Node-Wifi.menu.PartitionScheme.fatflash.build.partitions=ffat +BharatPi-Node-Wifi.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker=RainMaker +BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728 +BharatPi-Node-Wifi.menu.PartitionScheme.custom=Custom +BharatPi-Node-Wifi.menu.PartitionScheme.custom.build.partitions= +BharatPi-Node-Wifi.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +BharatPi-Node-Wifi.menu.CPUFreq.240=240MHz (WiFi/BT) +BharatPi-Node-Wifi.menu.CPUFreq.240.build.f_cpu=240000000L +BharatPi-Node-Wifi.menu.CPUFreq.160=160MHz (WiFi/BT) +BharatPi-Node-Wifi.menu.CPUFreq.160.build.f_cpu=160000000L +BharatPi-Node-Wifi.menu.CPUFreq.80=80MHz (WiFi/BT) +BharatPi-Node-Wifi.menu.CPUFreq.80.build.f_cpu=80000000L +BharatPi-Node-Wifi.menu.CPUFreq.40=40MHz (40MHz XTAL) +BharatPi-Node-Wifi.menu.CPUFreq.40.build.f_cpu=40000000L +BharatPi-Node-Wifi.menu.CPUFreq.26=26MHz (26MHz XTAL) +BharatPi-Node-Wifi.menu.CPUFreq.26.build.f_cpu=26000000L +BharatPi-Node-Wifi.menu.CPUFreq.20=20MHz (40MHz XTAL) +BharatPi-Node-Wifi.menu.CPUFreq.20.build.f_cpu=20000000L +BharatPi-Node-Wifi.menu.CPUFreq.13=13MHz (26MHz XTAL) +BharatPi-Node-Wifi.menu.CPUFreq.13.build.f_cpu=13000000L +BharatPi-Node-Wifi.menu.CPUFreq.10=10MHz (40MHz XTAL) +BharatPi-Node-Wifi.menu.CPUFreq.10.build.f_cpu=10000000L + +BharatPi-Node-Wifi.menu.FlashMode.qio=QIO +BharatPi-Node-Wifi.menu.FlashMode.qio.build.flash_mode=dio +BharatPi-Node-Wifi.menu.FlashMode.qio.build.boot=qio +BharatPi-Node-Wifi.menu.FlashMode.dio=DIO +BharatPi-Node-Wifi.menu.FlashMode.dio.build.flash_mode=dio +BharatPi-Node-Wifi.menu.FlashMode.dio.build.boot=dio + +BharatPi-Node-Wifi.menu.FlashFreq.80=80MHz +BharatPi-Node-Wifi.menu.FlashFreq.80.build.flash_freq=80m +BharatPi-Node-Wifi.menu.FlashFreq.40=40MHz +BharatPi-Node-Wifi.menu.FlashFreq.40.build.flash_freq=40m + +BharatPi-Node-Wifi.menu.FlashSize.4M=4MB (32Mb) +BharatPi-Node-Wifi.menu.FlashSize.4M.build.flash_size=4MB +BharatPi-Node-Wifi.menu.FlashSize.8M=8MB (64Mb) +BharatPi-Node-Wifi.menu.FlashSize.8M.build.flash_size=8MB +BharatPi-Node-Wifi.menu.FlashSize.8M.build.partitions=default_8MB +BharatPi-Node-Wifi.menu.FlashSize.16M=16MB (128Mb) +BharatPi-Node-Wifi.menu.FlashSize.16M.build.flash_size=16MB + +BharatPi-Node-Wifi.menu.UploadSpeed.921600=921600 +BharatPi-Node-Wifi.menu.UploadSpeed.921600.upload.speed=921600 +BharatPi-Node-Wifi.menu.UploadSpeed.115200=115200 +BharatPi-Node-Wifi.menu.UploadSpeed.115200.upload.speed=115200 +BharatPi-Node-Wifi.menu.UploadSpeed.256000.windows=256000 +BharatPi-Node-Wifi.menu.UploadSpeed.256000.upload.speed=256000 +BharatPi-Node-Wifi.menu.UploadSpeed.230400.windows.upload.speed=256000 +BharatPi-Node-Wifi.menu.UploadSpeed.230400=230400 +BharatPi-Node-Wifi.menu.UploadSpeed.230400.upload.speed=230400 +BharatPi-Node-Wifi.menu.UploadSpeed.460800.linux=460800 +BharatPi-Node-Wifi.menu.UploadSpeed.460800.macosx=460800 +BharatPi-Node-Wifi.menu.UploadSpeed.460800.upload.speed=460800 +BharatPi-Node-Wifi.menu.UploadSpeed.512000.windows=512000 +BharatPi-Node-Wifi.menu.UploadSpeed.512000.upload.speed=512000 + +BharatPi-Node-Wifi.menu.LoopCore.1=Core 1 +BharatPi-Node-Wifi.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +BharatPi-Node-Wifi.menu.LoopCore.0=Core 0 +BharatPi-Node-Wifi.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +BharatPi-Node-Wifi.menu.EventsCore.1=Core 1 +BharatPi-Node-Wifi.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +BharatPi-Node-Wifi.menu.EventsCore.0=Core 0 +BharatPi-Node-Wifi.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +BharatPi-Node-Wifi.menu.DebugLevel.none=None +BharatPi-Node-Wifi.menu.DebugLevel.none.build.code_debug=0 +BharatPi-Node-Wifi.menu.DebugLevel.error=Error +BharatPi-Node-Wifi.menu.DebugLevel.error.build.code_debug=1 +BharatPi-Node-Wifi.menu.DebugLevel.warn=Warn +BharatPi-Node-Wifi.menu.DebugLevel.warn.build.code_debug=2 +BharatPi-Node-Wifi.menu.DebugLevel.info=Info +BharatPi-Node-Wifi.menu.DebugLevel.info.build.code_debug=3 +BharatPi-Node-Wifi.menu.DebugLevel.debug=Debug +BharatPi-Node-Wifi.menu.DebugLevel.debug.build.code_debug=4 +BharatPi-Node-Wifi.menu.DebugLevel.verbose=Verbose +BharatPi-Node-Wifi.menu.DebugLevel.verbose.build.code_debug=5 + +BharatPi-Node-Wifi.menu.EraseFlash.none=Disabled +BharatPi-Node-Wifi.menu.EraseFlash.none.upload.erase_cmd= +BharatPi-Node-Wifi.menu.EraseFlash.all=Enabled +BharatPi-Node-Wifi.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +BharatPi-A7672S-4G.name=BharatPi A7672S 4G Module + +BharatPi-A7672S-4G.bootloader.tool=esptool_py +BharatPi-A7672S-4G.bootloader.tool.default=esptool_py + +BharatPi-A7672S-4G.upload.tool=esptool_py +BharatPi-A7672S-4G.upload.tool.default=esptool_py +BharatPi-A7672S-4G.upload.tool.network=esp_ota + +BharatPi-A7672S-4G.upload.maximum_size=1310720 +BharatPi-A7672S-4G.upload.maximum_data_size=327680 +BharatPi-A7672S-4G.upload.flags= +BharatPi-A7672S-4G.upload.extra_flags= + +BharatPi-A7672S-4G.serial.disableDTR=true +BharatPi-A7672S-4G.serial.disableRTS=true + +BharatPi-A7672S-4G.build.tarch=xtensa +BharatPi-A7672S-4G.build.bootloader_addr=0x1000 +BharatPi-A7672S-4G.build.target=esp32 +BharatPi-A7672S-4G.build.mcu=esp32 +BharatPi-A7672S-4G.build.core=esp32 +BharatPi-A7672S-4G.build.variant=BharatPi-A7672S-4G +BharatPi-A7672S-4G.build.board=BHARATPI_A7672S_4G + +BharatPi-A7672S-4G.build.f_cpu=240000000L +BharatPi-A7672S-4G.build.flash_size=4MB +BharatPi-A7672S-4G.build.flash_freq=40m +BharatPi-A7672S-4G.build.flash_mode=dio +BharatPi-A7672S-4G.build.boot=dio +BharatPi-A7672S-4G.build.partitions=default +BharatPi-A7672S-4G.build.defines= +BharatPi-A7672S-4G.build.loop_core= +BharatPi-A7672S-4G.build.event_core= + +BharatPi-A7672S-4G.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.default.build.partitions=default +BharatPi-A7672S-4G.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +BharatPi-A7672S-4G.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +BharatPi-A7672S-4G.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.minimal.build.partitions=minimal +BharatPi-A7672S-4G.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.no_ota.build.partitions=no_ota +BharatPi-A7672S-4G.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +BharatPi-A7672S-4G.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.huge_app.build.partitions=huge_app +BharatPi-A7672S-4G.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +BharatPi-A7672S-4G.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +BharatPi-A7672S-4G.menu.PartitionScheme.fatflash.build.partitions=ffat +BharatPi-A7672S-4G.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker=RainMaker +BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728 +BharatPi-A7672S-4G.menu.PartitionScheme.custom=Custom +BharatPi-A7672S-4G.menu.PartitionScheme.custom.build.partitions= +BharatPi-A7672S-4G.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +BharatPi-A7672S-4G.menu.CPUFreq.240=240MHz (WiFi/BT) +BharatPi-A7672S-4G.menu.CPUFreq.240.build.f_cpu=240000000L +BharatPi-A7672S-4G.menu.CPUFreq.160=160MHz (WiFi/BT) +BharatPi-A7672S-4G.menu.CPUFreq.160.build.f_cpu=160000000L +BharatPi-A7672S-4G.menu.CPUFreq.80=80MHz (WiFi/BT) +BharatPi-A7672S-4G.menu.CPUFreq.80.build.f_cpu=80000000L +BharatPi-A7672S-4G.menu.CPUFreq.40=40MHz (40MHz XTAL) +BharatPi-A7672S-4G.menu.CPUFreq.40.build.f_cpu=40000000L +BharatPi-A7672S-4G.menu.CPUFreq.26=26MHz (26MHz XTAL) +BharatPi-A7672S-4G.menu.CPUFreq.26.build.f_cpu=26000000L +BharatPi-A7672S-4G.menu.CPUFreq.20=20MHz (40MHz XTAL) +BharatPi-A7672S-4G.menu.CPUFreq.20.build.f_cpu=20000000L +BharatPi-A7672S-4G.menu.CPUFreq.13=13MHz (26MHz XTAL) +BharatPi-A7672S-4G.menu.CPUFreq.13.build.f_cpu=13000000L +BharatPi-A7672S-4G.menu.CPUFreq.10=10MHz (40MHz XTAL) +BharatPi-A7672S-4G.menu.CPUFreq.10.build.f_cpu=10000000L + +BharatPi-A7672S-4G.menu.FlashMode.qio=QIO +BharatPi-A7672S-4G.menu.FlashMode.qio.build.flash_mode=dio +BharatPi-A7672S-4G.menu.FlashMode.qio.build.boot=qio +BharatPi-A7672S-4G.menu.FlashMode.dio=DIO +BharatPi-A7672S-4G.menu.FlashMode.dio.build.flash_mode=dio +BharatPi-A7672S-4G.menu.FlashMode.dio.build.boot=dio + +BharatPi-A7672S-4G.menu.FlashFreq.80=80MHz +BharatPi-A7672S-4G.menu.FlashFreq.80.build.flash_freq=80m +BharatPi-A7672S-4G.menu.FlashFreq.40=40MHz +BharatPi-A7672S-4G.menu.FlashFreq.40.build.flash_freq=40m + +BharatPi-A7672S-4G.menu.FlashSize.4M=4MB (32Mb) +BharatPi-A7672S-4G.menu.FlashSize.4M.build.flash_size=4MB +BharatPi-A7672S-4G.menu.FlashSize.8M=8MB (64Mb) +BharatPi-A7672S-4G.menu.FlashSize.8M.build.flash_size=8MB +BharatPi-A7672S-4G.menu.FlashSize.8M.build.partitions=default_8MB +BharatPi-A7672S-4G.menu.FlashSize.16M=16MB (128Mb) +BharatPi-A7672S-4G.menu.FlashSize.16M.build.flash_size=16MB + +BharatPi-A7672S-4G.menu.UploadSpeed.921600=921600 +BharatPi-A7672S-4G.menu.UploadSpeed.921600.upload.speed=921600 +BharatPi-A7672S-4G.menu.UploadSpeed.115200=115200 +BharatPi-A7672S-4G.menu.UploadSpeed.115200.upload.speed=115200 +BharatPi-A7672S-4G.menu.UploadSpeed.256000.windows=256000 +BharatPi-A7672S-4G.menu.UploadSpeed.256000.upload.speed=256000 +BharatPi-A7672S-4G.menu.UploadSpeed.230400.windows.upload.speed=256000 +BharatPi-A7672S-4G.menu.UploadSpeed.230400=230400 +BharatPi-A7672S-4G.menu.UploadSpeed.230400.upload.speed=230400 +BharatPi-A7672S-4G.menu.UploadSpeed.460800.linux=460800 +BharatPi-A7672S-4G.menu.UploadSpeed.460800.macosx=460800 +BharatPi-A7672S-4G.menu.UploadSpeed.460800.upload.speed=460800 +BharatPi-A7672S-4G.menu.UploadSpeed.512000.windows=512000 +BharatPi-A7672S-4G.menu.UploadSpeed.512000.upload.speed=512000 + +BharatPi-A7672S-4G.menu.LoopCore.1=Core 1 +BharatPi-A7672S-4G.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +BharatPi-A7672S-4G.menu.LoopCore.0=Core 0 +BharatPi-A7672S-4G.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +BharatPi-A7672S-4G.menu.EventsCore.1=Core 1 +BharatPi-A7672S-4G.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +BharatPi-A7672S-4G.menu.EventsCore.0=Core 0 +BharatPi-A7672S-4G.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +BharatPi-A7672S-4G.menu.DebugLevel.none=None +BharatPi-A7672S-4G.menu.DebugLevel.none.build.code_debug=0 +BharatPi-A7672S-4G.menu.DebugLevel.error=Error +BharatPi-A7672S-4G.menu.DebugLevel.error.build.code_debug=1 +BharatPi-A7672S-4G.menu.DebugLevel.warn=Warn +BharatPi-A7672S-4G.menu.DebugLevel.warn.build.code_debug=2 +BharatPi-A7672S-4G.menu.DebugLevel.info=Info +BharatPi-A7672S-4G.menu.DebugLevel.info.build.code_debug=3 +BharatPi-A7672S-4G.menu.DebugLevel.debug=Debug +BharatPi-A7672S-4G.menu.DebugLevel.debug.build.code_debug=4 +BharatPi-A7672S-4G.menu.DebugLevel.verbose=Verbose +BharatPi-A7672S-4G.menu.DebugLevel.verbose.build.code_debug=5 + +BharatPi-A7672S-4G.menu.EraseFlash.none=Disabled +BharatPi-A7672S-4G.menu.EraseFlash.none.upload.erase_cmd= +BharatPi-A7672S-4G.menu.EraseFlash.all=Enabled +BharatPi-A7672S-4G.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +BharatPi-LoRa.name=BharatPi LoRa Module + +BharatPi-LoRa.bootloader.tool=esptool_py +BharatPi-LoRa.bootloader.tool.default=esptool_py + +BharatPi-LoRa.upload.tool=esptool_py +BharatPi-LoRa.upload.tool.default=esptool_py +BharatPi-LoRa.upload.tool.network=esp_ota + +BharatPi-LoRa.upload.maximum_size=1310720 +BharatPi-LoRa.upload.maximum_data_size=327680 +BharatPi-LoRa.upload.flags= +BharatPi-LoRa.upload.extra_flags= + +BharatPi-LoRa.serial.disableDTR=true +BharatPi-LoRa.serial.disableRTS=true + +BharatPi-LoRa.build.tarch=xtensa +BharatPi-LoRa.build.bootloader_addr=0x1000 +BharatPi-LoRa.build.target=esp32 +BharatPi-LoRa.build.mcu=esp32 +BharatPi-LoRa.build.core=esp32 +BharatPi-LoRa.build.variant=BharatPi-LoRa +BharatPi-LoRa.build.board=BHARATPI_LORA + +BharatPi-LoRa.build.f_cpu=240000000L +BharatPi-LoRa.build.flash_size=4MB +BharatPi-LoRa.build.flash_freq=40m +BharatPi-LoRa.build.flash_mode=dio +BharatPi-LoRa.build.boot=dio +BharatPi-LoRa.build.partitions=default +BharatPi-LoRa.build.defines= +BharatPi-LoRa.build.loop_core= +BharatPi-LoRa.build.event_core= + +BharatPi-LoRa.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.default.build.partitions=default +BharatPi-LoRa.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +BharatPi-LoRa.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +BharatPi-LoRa.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +BharatPi-LoRa.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +BharatPi-LoRa.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.minimal.build.partitions=minimal +BharatPi-LoRa.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.no_ota.build.partitions=no_ota +BharatPi-LoRa.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +BharatPi-LoRa.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +BharatPi-LoRa.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +BharatPi-LoRa.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +BharatPi-LoRa.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +BharatPi-LoRa.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +BharatPi-LoRa.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +BharatPi-LoRa.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +BharatPi-LoRa.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +BharatPi-LoRa.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.huge_app.build.partitions=huge_app +BharatPi-LoRa.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +BharatPi-LoRa.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +BharatPi-LoRa.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +BharatPi-LoRa.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +BharatPi-LoRa.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +BharatPi-LoRa.menu.PartitionScheme.fatflash.build.partitions=ffat +BharatPi-LoRa.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +BharatPi-LoRa.menu.PartitionScheme.rainmaker=RainMaker +BharatPi-LoRa.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +BharatPi-LoRa.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728 +BharatPi-LoRa.menu.PartitionScheme.custom=Custom +BharatPi-LoRa.menu.PartitionScheme.custom.build.partitions= +BharatPi-LoRa.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +BharatPi-LoRa.menu.CPUFreq.240=240MHz (WiFi/BT) +BharatPi-LoRa.menu.CPUFreq.240.build.f_cpu=240000000L +BharatPi-LoRa.menu.CPUFreq.160=160MHz (WiFi/BT) +BharatPi-LoRa.menu.CPUFreq.160.build.f_cpu=160000000L +BharatPi-LoRa.menu.CPUFreq.80=80MHz (WiFi/BT) +BharatPi-LoRa.menu.CPUFreq.80.build.f_cpu=80000000L +BharatPi-LoRa.menu.CPUFreq.40=40MHz (40MHz XTAL) +BharatPi-LoRa.menu.CPUFreq.40.build.f_cpu=40000000L +BharatPi-LoRa.menu.CPUFreq.26=26MHz (26MHz XTAL) +BharatPi-LoRa.menu.CPUFreq.26.build.f_cpu=26000000L +BharatPi-LoRa.menu.CPUFreq.20=20MHz (40MHz XTAL) +BharatPi-LoRa.menu.CPUFreq.20.build.f_cpu=20000000L +BharatPi-LoRa.menu.CPUFreq.13=13MHz (26MHz XTAL) +BharatPi-LoRa.menu.CPUFreq.13.build.f_cpu=13000000L +BharatPi-LoRa.menu.CPUFreq.10=10MHz (40MHz XTAL) +BharatPi-LoRa.menu.CPUFreq.10.build.f_cpu=10000000L + +BharatPi-LoRa.menu.FlashMode.qio=QIO +BharatPi-LoRa.menu.FlashMode.qio.build.flash_mode=dio +BharatPi-LoRa.menu.FlashMode.qio.build.boot=qio +BharatPi-LoRa.menu.FlashMode.dio=DIO +BharatPi-LoRa.menu.FlashMode.dio.build.flash_mode=dio +BharatPi-LoRa.menu.FlashMode.dio.build.boot=dio + +BharatPi-LoRa.menu.FlashFreq.80=80MHz +BharatPi-LoRa.menu.FlashFreq.80.build.flash_freq=80m +BharatPi-LoRa.menu.FlashFreq.40=40MHz +BharatPi-LoRa.menu.FlashFreq.40.build.flash_freq=40m + +BharatPi-LoRa.menu.FlashSize.4M=4MB (32Mb) +BharatPi-LoRa.menu.FlashSize.4M.build.flash_size=4MB +BharatPi-LoRa.menu.FlashSize.8M=8MB (64Mb) +BharatPi-LoRa.menu.FlashSize.8M.build.flash_size=8MB +BharatPi-LoRa.menu.FlashSize.8M.build.partitions=default_8MB +BharatPi-LoRa.menu.FlashSize.16M=16MB (128Mb) +BharatPi-LoRa.menu.FlashSize.16M.build.flash_size=16MB + +BharatPi-LoRa.menu.UploadSpeed.921600=921600 +BharatPi-LoRa.menu.UploadSpeed.921600.upload.speed=921600 +BharatPi-LoRa.menu.UploadSpeed.115200=115200 +BharatPi-LoRa.menu.UploadSpeed.115200.upload.speed=115200 +BharatPi-LoRa.menu.UploadSpeed.256000.windows=256000 +BharatPi-LoRa.menu.UploadSpeed.256000.upload.speed=256000 +BharatPi-LoRa.menu.UploadSpeed.230400.windows.upload.speed=256000 +BharatPi-LoRa.menu.UploadSpeed.230400=230400 +BharatPi-LoRa.menu.UploadSpeed.230400.upload.speed=230400 +BharatPi-LoRa.menu.UploadSpeed.460800.linux=460800 +BharatPi-LoRa.menu.UploadSpeed.460800.macosx=460800 +BharatPi-LoRa.menu.UploadSpeed.460800.upload.speed=460800 +BharatPi-LoRa.menu.UploadSpeed.512000.windows=512000 +BharatPi-LoRa.menu.UploadSpeed.512000.upload.speed=512000 + +BharatPi-LoRa.menu.LoopCore.1=Core 1 +BharatPi-LoRa.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +BharatPi-LoRa.menu.LoopCore.0=Core 0 +BharatPi-LoRa.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +BharatPi-LoRa.menu.EventsCore.1=Core 1 +BharatPi-LoRa.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +BharatPi-LoRa.menu.EventsCore.0=Core 0 +BharatPi-LoRa.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +BharatPi-LoRa.menu.DebugLevel.none=None +BharatPi-LoRa.menu.DebugLevel.none.build.code_debug=0 +BharatPi-LoRa.menu.DebugLevel.error=Error +BharatPi-LoRa.menu.DebugLevel.error.build.code_debug=1 +BharatPi-LoRa.menu.DebugLevel.warn=Warn +BharatPi-LoRa.menu.DebugLevel.warn.build.code_debug=2 +BharatPi-LoRa.menu.DebugLevel.info=Info +BharatPi-LoRa.menu.DebugLevel.info.build.code_debug=3 +BharatPi-LoRa.menu.DebugLevel.debug=Debug +BharatPi-LoRa.menu.DebugLevel.debug.build.code_debug=4 +BharatPi-LoRa.menu.DebugLevel.verbose=Verbose +BharatPi-LoRa.menu.DebugLevel.verbose.build.code_debug=5 + +BharatPi-LoRa.menu.EraseFlash.none=Disabled +BharatPi-LoRa.menu.EraseFlash.none.upload.erase_cmd= +BharatPi-LoRa.menu.EraseFlash.all=Enabled +BharatPi-LoRa.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_bling.name=UM BLING +um_bling.vid.0=0x303a +um_bling.pid.0=0x817F +um_bling.upload_port.0.vid=0x303a +um_bling.upload_port.0.pid=0x817F + +um_bling.bootloader.tool=esptool_py +um_bling.bootloader.tool.default=esptool_py + +um_bling.upload.tool=esptool_py +um_bling.upload.tool.default=esptool_py +um_bling.upload.tool.network=esp_ota + +um_bling.upload.maximum_size=1310720 +um_bling.upload.maximum_data_size=327680 +um_bling.upload.flags= +um_bling.upload.extra_flags= +um_bling.upload.use_1200bps_touch=false +um_bling.upload.wait_for_upload_port=false + +um_bling.serial.disableDTR=false +um_bling.serial.disableRTS=false + +um_bling.build.tarch=xtensa +um_bling.build.bootloader_addr=0x0 +um_bling.build.target=esp32s3 +um_bling.build.mcu=esp32s3 +um_bling.build.core=esp32 +um_bling.build.variant=um_bling +um_bling.build.board=BLING + +um_bling.build.usb_mode=1 +um_bling.build.cdc_on_boot=0 +um_bling.build.msc_on_boot=0 +um_bling.build.dfu_on_boot=0 +um_bling.build.f_cpu=240000000L +um_bling.build.flash_size=8MB +um_bling.build.flash_freq=80m +um_bling.build.flash_mode=dio +um_bling.build.boot=qio +um_bling.build.partitions=default +um_bling.build.defines= +um_bling.build.loop_core= +um_bling.build.event_core= +um_bling.build.flash_type=qio +um_bling.build.psram_type=qspi +um_bling.build.memory_type=qio_qspi + +um_bling.menu.LoopCore.1=Core 1 +um_bling.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_bling.menu.LoopCore.0=Core 0 +um_bling.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_bling.menu.EventsCore.1=Core 1 +um_bling.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_bling.menu.EventsCore.0=Core 0 +um_bling.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_bling.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_bling.menu.USBMode.hwcdc.build.usb_mode=1 +um_bling.menu.USBMode.default=USB-OTG (TinyUSB) +um_bling.menu.USBMode.default.build.usb_mode=0 + +um_bling.menu.CDCOnBoot.cdc=Enabled +um_bling.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_bling.menu.CDCOnBoot.default=Disabled +um_bling.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_bling.menu.MSCOnBoot.default=Disabled +um_bling.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_bling.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_bling.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_bling.menu.DFUOnBoot.default=Disabled +um_bling.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_bling.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_bling.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_bling.menu.UploadMode.default=UART0 / Hardware CDC +um_bling.menu.UploadMode.default.upload.use_1200bps_touch=false +um_bling.menu.UploadMode.default.upload.wait_for_upload_port=false +um_bling.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_bling.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_bling.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +um_bling.menu.PSRAM.enabled=Enabled +um_bling.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_bling.menu.PSRAM.disabled=Disabled +um_bling.menu.PSRAM.disabled.build.defines= + +um_bling.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +um_bling.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_bling.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_bling.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT) +um_bling.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_bling.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_bling.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_bling.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 + +um_bling.menu.CPUFreq.240=240MHz (WiFi) +um_bling.menu.CPUFreq.240.build.f_cpu=240000000L +um_bling.menu.CPUFreq.160=160MHz (WiFi) +um_bling.menu.CPUFreq.160.build.f_cpu=160000000L +um_bling.menu.CPUFreq.80=80MHz (WiFi) +um_bling.menu.CPUFreq.80.build.f_cpu=80000000L +um_bling.menu.CPUFreq.40=40MHz +um_bling.menu.CPUFreq.40.build.f_cpu=40000000L +um_bling.menu.CPUFreq.20=20MHz +um_bling.menu.CPUFreq.20.build.f_cpu=20000000L +um_bling.menu.CPUFreq.10=10MHz +um_bling.menu.CPUFreq.10.build.f_cpu=10000000L + +um_bling.menu.FlashMode.qio=QIO +um_bling.menu.FlashMode.qio.build.flash_mode=dio +um_bling.menu.FlashMode.qio.build.boot=qio +um_bling.menu.FlashMode.dio=DIO +um_bling.menu.FlashMode.dio.build.flash_mode=dio +um_bling.menu.FlashMode.dio.build.boot=dio + +um_bling.menu.UploadSpeed.921600=921600 +um_bling.menu.UploadSpeed.921600.upload.speed=921600 +um_bling.menu.UploadSpeed.115200=115200 +um_bling.menu.UploadSpeed.115200.upload.speed=115200 +um_bling.menu.UploadSpeed.256000.windows=256000 +um_bling.menu.UploadSpeed.256000.upload.speed=256000 +um_bling.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_bling.menu.UploadSpeed.230400=230400 +um_bling.menu.UploadSpeed.230400.upload.speed=230400 +um_bling.menu.UploadSpeed.460800.linux=460800 +um_bling.menu.UploadSpeed.460800.macosx=460800 +um_bling.menu.UploadSpeed.460800.upload.speed=460800 +um_bling.menu.UploadSpeed.512000.windows=512000 +um_bling.menu.UploadSpeed.512000.upload.speed=512000 + +um_bling.menu.DebugLevel.none=None +um_bling.menu.DebugLevel.none.build.code_debug=0 +um_bling.menu.DebugLevel.error=Error +um_bling.menu.DebugLevel.error.build.code_debug=1 +um_bling.menu.DebugLevel.warn=Warn +um_bling.menu.DebugLevel.warn.build.code_debug=2 +um_bling.menu.DebugLevel.info=Info +um_bling.menu.DebugLevel.info.build.code_debug=3 +um_bling.menu.DebugLevel.debug=Debug +um_bling.menu.DebugLevel.debug.build.code_debug=4 +um_bling.menu.DebugLevel.verbose=Verbose +um_bling.menu.DebugLevel.verbose.build.code_debug=5 + +um_bling.menu.EraseFlash.none=Disabled +um_bling.menu.EraseFlash.none.upload.erase_cmd= +um_bling.menu.EraseFlash.all=Enabled +um_bling.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_edges3_d.name=UM EdgeS3[D] +um_edges3_d.vid.0=0x303a +um_edges3_d.pid.0=0x82DC +um_edges3_d.upload_port.0.vid=0x303a +um_edges3_d.upload_port.0.pid=0x82DC + +um_edges3_d.bootloader.tool=esptool_py +um_edges3_d.bootloader.tool.default=esptool_py + +um_edges3_d.upload.tool=esptool_py +um_edges3_d.upload.tool.default=esptool_py +um_edges3_d.upload.tool.network=esp_ota + +um_edges3_d.upload.maximum_size=1310720 +um_edges3_d.upload.maximum_data_size=327680 +um_edges3_d.upload.flags= +um_edges3_d.upload.extra_flags= +um_edges3_d.upload.use_1200bps_touch=false +um_edges3_d.upload.wait_for_upload_port=false + +um_edges3_d.serial.disableDTR=false +um_edges3_d.serial.disableRTS=false + +um_edges3_d.build.tarch=xtensa +um_edges3_d.build.bootloader_addr=0x0 +um_edges3_d.build.target=esp32s3 +um_edges3_d.build.mcu=esp32s3 +um_edges3_d.build.core=esp32 +um_edges3_d.build.variant=um_edges3_d +um_edges3_d.build.board=EDGES3D + +um_edges3_d.build.usb_mode=1 +um_edges3_d.build.cdc_on_boot=1 +um_edges3_d.build.msc_on_boot=0 +um_edges3_d.build.dfu_on_boot=0 +um_edges3_d.build.f_cpu=240000000L +um_edges3_d.build.flash_size=8MB +um_edges3_d.build.flash_freq=80m +um_edges3_d.build.flash_mode=dio +um_edges3_d.build.boot=qio +um_edges3_d.build.partitions=default +um_edges3_d.build.defines= +um_edges3_d.build.loop_core= +um_edges3_d.build.event_core= +um_edges3_d.build.flash_type=qio +um_edges3_d.build.psram_type=qspi +um_edges3_d.build.memory_type=qio_qspi + +um_edges3_d.menu.LoopCore.1=Core 1 +um_edges3_d.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_edges3_d.menu.LoopCore.0=Core 0 +um_edges3_d.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_edges3_d.menu.EventsCore.1=Core 1 +um_edges3_d.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_edges3_d.menu.EventsCore.0=Core 0 +um_edges3_d.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_edges3_d.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_edges3_d.menu.USBMode.hwcdc.build.usb_mode=1 +um_edges3_d.menu.USBMode.default=USB-OTG (TinyUSB) +um_edges3_d.menu.USBMode.default.build.usb_mode=0 + +um_edges3_d.menu.CDCOnBoot.cdc=Enabled +um_edges3_d.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_edges3_d.menu.CDCOnBoot.default=Disabled +um_edges3_d.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_edges3_d.menu.MSCOnBoot.default=Disabled +um_edges3_d.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_edges3_d.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_edges3_d.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_edges3_d.menu.DFUOnBoot.default=Disabled +um_edges3_d.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_edges3_d.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_edges3_d.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_edges3_d.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_edges3_d.menu.UploadMode.default=UART0 / Hardware CDC +um_edges3_d.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_edges3_d.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_edges3_d.menu.UploadMode.default.upload.use_1200bps_touch=false +um_edges3_d.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_edges3_d.menu.PSRAM.enabled=Enabled +um_edges3_d.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_edges3_d.menu.PSRAM.disabled=Disabled +um_edges3_d.menu.PSRAM.disabled.build.defines= + +um_edges3_d.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +um_edges3_d.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_edges3_d.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +um_edges3_d.menu.CPUFreq.240=240MHz (WiFi) +um_edges3_d.menu.CPUFreq.240.build.f_cpu=240000000L +um_edges3_d.menu.CPUFreq.160=160MHz (WiFi) +um_edges3_d.menu.CPUFreq.160.build.f_cpu=160000000L +um_edges3_d.menu.CPUFreq.80=80MHz (WiFi) +um_edges3_d.menu.CPUFreq.80.build.f_cpu=80000000L +um_edges3_d.menu.CPUFreq.40=40MHz +um_edges3_d.menu.CPUFreq.40.build.f_cpu=40000000L +um_edges3_d.menu.CPUFreq.20=20MHz +um_edges3_d.menu.CPUFreq.20.build.f_cpu=20000000L +um_edges3_d.menu.CPUFreq.10=10MHz +um_edges3_d.menu.CPUFreq.10.build.f_cpu=10000000L + +um_edges3_d.menu.FlashMode.qio=QIO +um_edges3_d.menu.FlashMode.qio.build.flash_mode=dio +um_edges3_d.menu.FlashMode.qio.build.boot=qio +um_edges3_d.menu.FlashMode.dio=DIO +um_edges3_d.menu.FlashMode.dio.build.flash_mode=dio +um_edges3_d.menu.FlashMode.dio.build.boot=dio + +um_edges3_d.menu.UploadSpeed.921600=921600 +um_edges3_d.menu.UploadSpeed.921600.upload.speed=921600 +um_edges3_d.menu.UploadSpeed.115200=115200 +um_edges3_d.menu.UploadSpeed.115200.upload.speed=115200 +um_edges3_d.menu.UploadSpeed.256000.windows=256000 +um_edges3_d.menu.UploadSpeed.256000.upload.speed=256000 +um_edges3_d.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_edges3_d.menu.UploadSpeed.230400=230400 +um_edges3_d.menu.UploadSpeed.230400.upload.speed=230400 +um_edges3_d.menu.UploadSpeed.460800.linux=460800 +um_edges3_d.menu.UploadSpeed.460800.macosx=460800 +um_edges3_d.menu.UploadSpeed.460800.upload.speed=460800 +um_edges3_d.menu.UploadSpeed.512000.windows=512000 +um_edges3_d.menu.UploadSpeed.512000.upload.speed=512000 + +um_edges3_d.menu.DebugLevel.none=None +um_edges3_d.menu.DebugLevel.none.build.code_debug=0 +um_edges3_d.menu.DebugLevel.error=Error +um_edges3_d.menu.DebugLevel.error.build.code_debug=1 +um_edges3_d.menu.DebugLevel.warn=Warn +um_edges3_d.menu.DebugLevel.warn.build.code_debug=2 +um_edges3_d.menu.DebugLevel.info=Info +um_edges3_d.menu.DebugLevel.info.build.code_debug=3 +um_edges3_d.menu.DebugLevel.debug=Debug +um_edges3_d.menu.DebugLevel.debug.build.code_debug=4 +um_edges3_d.menu.DebugLevel.verbose=Verbose +um_edges3_d.menu.DebugLevel.verbose.build.code_debug=5 + +um_edges3_d.menu.EraseFlash.none=Disabled +um_edges3_d.menu.EraseFlash.none.upload.erase_cmd= +um_edges3_d.menu.EraseFlash.all=Enabled +um_edges3_d.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_feathers2.name=UM FeatherS2 +um_feathers2.vid.0=0x239A +um_feathers2.pid.0=0x80AB +um_feathers2.upload_port.0.vid=0x239A +um_feathers2.upload_port.0.pid=0x80AB + +um_feathers2.bootloader.tool=esptool_py +um_feathers2.bootloader.tool.default=esptool_py + +um_feathers2.upload.tool=esptool_py +um_feathers2.upload.tool.default=esptool_py +um_feathers2.upload.tool.network=esp_ota + +um_feathers2.upload.maximum_size=1310720 +um_feathers2.upload.maximum_data_size=327680 +um_feathers2.upload.flags= +um_feathers2.upload.extra_flags= +um_feathers2.upload.use_1200bps_touch=true +um_feathers2.upload.wait_for_upload_port=true + +um_feathers2.serial.disableDTR=false +um_feathers2.serial.disableRTS=false + +um_feathers2.build.tarch=xtensa +um_feathers2.build.bootloader_addr=0x1000 +um_feathers2.build.target=esp32s2 +um_feathers2.build.mcu=esp32s2 +um_feathers2.build.core=esp32 +um_feathers2.build.variant=um_feathers2 +um_feathers2.build.board=FEATHERS2 + +um_feathers2.build.cdc_on_boot=1 +um_feathers2.build.msc_on_boot=0 +um_feathers2.build.dfu_on_boot=0 +um_feathers2.build.f_cpu=240000000L +um_feathers2.build.flash_size=16MB +um_feathers2.build.flash_freq=80m +um_feathers2.build.flash_mode=dio +um_feathers2.build.boot=qio +um_feathers2.build.partitions=fatflash +um_feathers2.build.defines= + +um_feathers2.menu.CDCOnBoot.cdc=Enabled +um_feathers2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_feathers2.menu.CDCOnBoot.default=Disabled +um_feathers2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_feathers2.menu.MSCOnBoot.default=Disabled +um_feathers2.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_feathers2.menu.MSCOnBoot.msc=Enabled +um_feathers2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_feathers2.menu.DFUOnBoot.default=Disabled +um_feathers2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_feathers2.menu.DFUOnBoot.dfu=Enabled +um_feathers2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_feathers2.menu.PSRAM.enabled=Enabled +um_feathers2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_feathers2.menu.PSRAM.disabled=Disabled +um_feathers2.menu.PSRAM.disabled.build.defines= + +um_feathers2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +um_feathers2.menu.PartitionScheme.fatflash.build.partitions=ffat +um_feathers2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +um_feathers2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +um_feathers2.menu.PartitionScheme.default.build.partitions=default +um_feathers2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +um_feathers2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +um_feathers2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +um_feathers2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_feathers2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_feathers2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +um_feathers2.menu.PartitionScheme.minimal.build.partitions=minimal +um_feathers2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +um_feathers2.menu.PartitionScheme.no_ota.build.partitions=no_ota +um_feathers2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +um_feathers2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +um_feathers2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +um_feathers2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +um_feathers2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +um_feathers2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +um_feathers2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +um_feathers2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +um_feathers2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +um_feathers2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +um_feathers2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +um_feathers2.menu.PartitionScheme.huge_app.build.partitions=huge_app +um_feathers2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +um_feathers2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +um_feathers2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +um_feathers2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +um_feathers2.menu.CPUFreq.240=240MHz (WiFi) +um_feathers2.menu.CPUFreq.240.build.f_cpu=240000000L +um_feathers2.menu.CPUFreq.160=160MHz (WiFi) +um_feathers2.menu.CPUFreq.160.build.f_cpu=160000000L +um_feathers2.menu.CPUFreq.80=80MHz (WiFi) +um_feathers2.menu.CPUFreq.80.build.f_cpu=80000000L +um_feathers2.menu.CPUFreq.40=40MHz +um_feathers2.menu.CPUFreq.40.build.f_cpu=40000000L +um_feathers2.menu.CPUFreq.20=20MHz +um_feathers2.menu.CPUFreq.20.build.f_cpu=20000000L +um_feathers2.menu.CPUFreq.10=10MHz +um_feathers2.menu.CPUFreq.10.build.f_cpu=10000000L + +um_feathers2.menu.FlashSize.16M=16MB (128Mb) +um_feathers2.menu.FlashSize.16M.build.flash_size=16MB +um_feathers2.menu.FlashSize.4M=4MB (32Mb) +um_feathers2.menu.FlashSize.4M.build.flash_size=4MB +um_feathers2.menu.FlashSize.8M=8MB (64Mb) +um_feathers2.menu.FlashSize.8M.build.flash_size=8MB +um_feathers2.menu.FlashSize.2M=2MB (16Mb) +um_feathers2.menu.FlashSize.2M.build.flash_size=2MB + +um_feathers2.menu.UploadSpeed.921600=921600 +um_feathers2.menu.UploadSpeed.921600.upload.speed=921600 +um_feathers2.menu.UploadSpeed.115200=115200 +um_feathers2.menu.UploadSpeed.115200.upload.speed=115200 +um_feathers2.menu.UploadSpeed.256000.windows=256000 +um_feathers2.menu.UploadSpeed.256000.upload.speed=256000 +um_feathers2.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_feathers2.menu.UploadSpeed.230400=230400 +um_feathers2.menu.UploadSpeed.230400.upload.speed=230400 +um_feathers2.menu.UploadSpeed.460800.linux=460800 +um_feathers2.menu.UploadSpeed.460800.macosx=460800 +um_feathers2.menu.UploadSpeed.460800.upload.speed=460800 + +um_feathers2.menu.DebugLevel.none=None +um_feathers2.menu.DebugLevel.none.build.code_debug=0 +um_feathers2.menu.DebugLevel.error=Error +um_feathers2.menu.DebugLevel.error.build.code_debug=1 +um_feathers2.menu.DebugLevel.warn=Warn +um_feathers2.menu.DebugLevel.warn.build.code_debug=2 +um_feathers2.menu.DebugLevel.info=Info +um_feathers2.menu.DebugLevel.info.build.code_debug=3 +um_feathers2.menu.DebugLevel.debug=Debug +um_feathers2.menu.DebugLevel.debug.build.code_debug=4 +um_feathers2.menu.DebugLevel.verbose=Verbose +um_feathers2.menu.DebugLevel.verbose.build.code_debug=5 + +um_feathers2.menu.EraseFlash.none=Disabled +um_feathers2.menu.EraseFlash.none.upload.erase_cmd= +um_feathers2.menu.EraseFlash.all=Enabled +um_feathers2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_feathers2neo.name=UM FeatherS2 Neo +um_feathers2neo.vid.0=0x303a +um_feathers2neo.pid.0=0x80B4 +um_feathers2neo.upload_port.0.vid=0x303a +um_feathers2neo.upload_port.0.pid=0x80B4 + +um_feathers2neo.bootloader.tool=esptool_py +um_feathers2neo.bootloader.tool.default=esptool_py + +um_feathers2neo.upload.tool=esptool_py +um_feathers2neo.upload.tool.default=esptool_py +um_feathers2neo.upload.tool.network=esp_ota + +um_feathers2neo.upload.maximum_size=1310720 +um_feathers2neo.upload.maximum_data_size=327680 +um_feathers2neo.upload.flags= +um_feathers2neo.upload.extra_flags= +um_feathers2neo.upload.use_1200bps_touch=true +um_feathers2neo.upload.wait_for_upload_port=true + +um_feathers2neo.serial.disableDTR=false +um_feathers2neo.serial.disableRTS=false + +um_feathers2neo.build.tarch=xtensa +um_feathers2neo.build.bootloader_addr=0x1000 +um_feathers2neo.build.target=esp32s2 +um_feathers2neo.build.mcu=esp32s2 +um_feathers2neo.build.core=esp32 +um_feathers2neo.build.variant=um_feathers2neo +um_feathers2neo.build.board=FEATHERS2NEO + +um_feathers2neo.build.cdc_on_boot=1 +um_feathers2neo.build.msc_on_boot=0 +um_feathers2neo.build.dfu_on_boot=0 +um_feathers2neo.build.f_cpu=240000000L +um_feathers2neo.build.flash_size=4MB +um_feathers2neo.build.flash_freq=80m +um_feathers2neo.build.flash_mode=dio +um_feathers2neo.build.boot=qio +um_feathers2neo.build.partitions=default +um_feathers2neo.build.defines= + +um_feathers2neo.menu.CDCOnBoot.cdc=Enabled +um_feathers2neo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_feathers2neo.menu.CDCOnBoot.default=Disabled +um_feathers2neo.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_feathers2neo.menu.MSCOnBoot.default=Disabled +um_feathers2neo.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_feathers2neo.menu.MSCOnBoot.msc=Enabled +um_feathers2neo.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_feathers2neo.menu.DFUOnBoot.default=Disabled +um_feathers2neo.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_feathers2neo.menu.DFUOnBoot.dfu=Enabled +um_feathers2neo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_feathers2neo.menu.PSRAM.enabled=Enabled +um_feathers2neo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_feathers2neo.menu.PSRAM.disabled=Disabled +um_feathers2neo.menu.PSRAM.disabled.build.defines= + +um_feathers2neo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +um_feathers2neo.menu.PartitionScheme.default.build.partitions=default +um_feathers2neo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +um_feathers2neo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +um_feathers2neo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +um_feathers2neo.menu.PartitionScheme.minimal.build.partitions=minimal +um_feathers2neo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +um_feathers2neo.menu.PartitionScheme.no_ota.build.partitions=no_ota +um_feathers2neo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +um_feathers2neo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +um_feathers2neo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +um_feathers2neo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +um_feathers2neo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +um_feathers2neo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +um_feathers2neo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +um_feathers2neo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +um_feathers2neo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +um_feathers2neo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +um_feathers2neo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +um_feathers2neo.menu.PartitionScheme.huge_app.build.partitions=huge_app +um_feathers2neo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +um_feathers2neo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +um_feathers2neo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +um_feathers2neo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +um_feathers2neo.menu.CPUFreq.240=240MHz (WiFi) +um_feathers2neo.menu.CPUFreq.240.build.f_cpu=240000000L +um_feathers2neo.menu.CPUFreq.160=160MHz (WiFi) +um_feathers2neo.menu.CPUFreq.160.build.f_cpu=160000000L +um_feathers2neo.menu.CPUFreq.80=80MHz (WiFi) +um_feathers2neo.menu.CPUFreq.80.build.f_cpu=80000000L +um_feathers2neo.menu.CPUFreq.40=40MHz +um_feathers2neo.menu.CPUFreq.40.build.f_cpu=40000000L +um_feathers2neo.menu.CPUFreq.20=20MHz +um_feathers2neo.menu.CPUFreq.20.build.f_cpu=20000000L +um_feathers2neo.menu.CPUFreq.10=10MHz +um_feathers2neo.menu.CPUFreq.10.build.f_cpu=10000000L + +um_feathers2neo.menu.FlashSize.4M=4MB (32Mb) +um_feathers2neo.menu.FlashSize.4M.build.flash_size=4MB +um_feathers2neo.menu.FlashSize.2M=2MB (16Mb) +um_feathers2neo.menu.FlashSize.2M.build.flash_size=2MB + +um_feathers2neo.menu.UploadSpeed.921600=921600 +um_feathers2neo.menu.UploadSpeed.921600.upload.speed=921600 +um_feathers2neo.menu.UploadSpeed.115200=115200 +um_feathers2neo.menu.UploadSpeed.115200.upload.speed=115200 +um_feathers2neo.menu.UploadSpeed.256000.windows=256000 +um_feathers2neo.menu.UploadSpeed.256000.upload.speed=256000 +um_feathers2neo.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_feathers2neo.menu.UploadSpeed.230400=230400 +um_feathers2neo.menu.UploadSpeed.230400.upload.speed=230400 +um_feathers2neo.menu.UploadSpeed.460800.linux=460800 +um_feathers2neo.menu.UploadSpeed.460800.macosx=460800 +um_feathers2neo.menu.UploadSpeed.460800.upload.speed=460800 + +um_feathers2neo.menu.DebugLevel.none=None +um_feathers2neo.menu.DebugLevel.none.build.code_debug=0 +um_feathers2neo.menu.DebugLevel.error=Error +um_feathers2neo.menu.DebugLevel.error.build.code_debug=1 +um_feathers2neo.menu.DebugLevel.warn=Warn +um_feathers2neo.menu.DebugLevel.warn.build.code_debug=2 +um_feathers2neo.menu.DebugLevel.info=Info +um_feathers2neo.menu.DebugLevel.info.build.code_debug=3 +um_feathers2neo.menu.DebugLevel.debug=Debug +um_feathers2neo.menu.DebugLevel.debug.build.code_debug=4 +um_feathers2neo.menu.DebugLevel.verbose=Verbose +um_feathers2neo.menu.DebugLevel.verbose.build.code_debug=5 + +um_feathers2neo.menu.EraseFlash.none=Disabled +um_feathers2neo.menu.EraseFlash.none.upload.erase_cmd= +um_feathers2neo.menu.EraseFlash.all=Enabled +um_feathers2neo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_feathers3.name=UM FeatherS3 +um_feathers3.vid.0=0x303a +um_feathers3.pid.0=0x80D6 +um_feathers3.upload_port.0.vid=0x303a +um_feathers3.upload_port.0.pid=0x80D6 + +um_feathers3.bootloader.tool=esptool_py +um_feathers3.bootloader.tool.default=esptool_py + +um_feathers3.upload.tool=esptool_py +um_feathers3.upload.tool.default=esptool_py +um_feathers3.upload.tool.network=esp_ota + +um_feathers3.upload.maximum_size=1310720 +um_feathers3.upload.maximum_data_size=327680 +um_feathers3.upload.flags= +um_feathers3.upload.extra_flags= +um_feathers3.upload.use_1200bps_touch=false +um_feathers3.upload.wait_for_upload_port=false + +um_feathers3.serial.disableDTR=false +um_feathers3.serial.disableRTS=false + +um_feathers3.build.tarch=xtensa +um_feathers3.build.bootloader_addr=0x0 +um_feathers3.build.target=esp32s3 +um_feathers3.build.mcu=esp32s3 +um_feathers3.build.core=esp32 +um_feathers3.build.variant=um_feathers3 +um_feathers3.build.board=FEATHERS3 + +um_feathers3.build.usb_mode=1 +um_feathers3.build.cdc_on_boot=1 +um_feathers3.build.msc_on_boot=0 +um_feathers3.build.dfu_on_boot=0 +um_feathers3.build.f_cpu=240000000L +um_feathers3.build.flash_size=16MB +um_feathers3.build.flash_freq=80m +um_feathers3.build.flash_mode=dio +um_feathers3.build.boot=qio +um_feathers3.build.partitions=default +um_feathers3.build.defines= +um_feathers3.build.loop_core= +um_feathers3.build.event_core= +um_feathers3.build.flash_type=qio +um_feathers3.build.psram_type=qspi +um_feathers3.build.memory_type=qio_qspi + +um_feathers3.menu.LoopCore.1=Core 1 +um_feathers3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_feathers3.menu.LoopCore.0=Core 0 +um_feathers3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_feathers3.menu.EventsCore.1=Core 1 +um_feathers3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_feathers3.menu.EventsCore.0=Core 0 +um_feathers3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_feathers3.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_feathers3.menu.USBMode.hwcdc.build.usb_mode=1 +um_feathers3.menu.USBMode.default=USB-OTG (TinyUSB) +um_feathers3.menu.USBMode.default.build.usb_mode=0 + +um_feathers3.menu.CDCOnBoot.cdc=Enabled +um_feathers3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_feathers3.menu.CDCOnBoot.default=Disabled +um_feathers3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_feathers3.menu.MSCOnBoot.default=Disabled +um_feathers3.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_feathers3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_feathers3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_feathers3.menu.DFUOnBoot.default=Disabled +um_feathers3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_feathers3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_feathers3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_feathers3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_feathers3.menu.UploadMode.default=UART0 / Hardware CDC +um_feathers3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_feathers3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_feathers3.menu.UploadMode.default.upload.use_1200bps_touch=false +um_feathers3.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_feathers3.menu.PSRAM.enabled=Enabled +um_feathers3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_feathers3.menu.PSRAM.disabled=Disabled +um_feathers3.menu.PSRAM.disabled.build.defines= + +um_feathers3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +um_feathers3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +um_feathers3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +um_feathers3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT) +um_feathers3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_feathers3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_feathers3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_feathers3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +um_feathers3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +um_feathers3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +um_feathers3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +um_feathers3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +um_feathers3.menu.PartitionScheme.fatflash.build.partitions=ffat +um_feathers3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +um_feathers3.menu.CPUFreq.240=240MHz (WiFi) +um_feathers3.menu.CPUFreq.240.build.f_cpu=240000000L +um_feathers3.menu.CPUFreq.160=160MHz (WiFi) +um_feathers3.menu.CPUFreq.160.build.f_cpu=160000000L +um_feathers3.menu.CPUFreq.80=80MHz (WiFi) +um_feathers3.menu.CPUFreq.80.build.f_cpu=80000000L +um_feathers3.menu.CPUFreq.40=40MHz +um_feathers3.menu.CPUFreq.40.build.f_cpu=40000000L +um_feathers3.menu.CPUFreq.20=20MHz +um_feathers3.menu.CPUFreq.20.build.f_cpu=20000000L +um_feathers3.menu.CPUFreq.10=10MHz +um_feathers3.menu.CPUFreq.10.build.f_cpu=10000000L + +um_feathers3.menu.FlashMode.qio=QIO +um_feathers3.menu.FlashMode.qio.build.flash_mode=dio +um_feathers3.menu.FlashMode.qio.build.boot=qio +um_feathers3.menu.FlashMode.dio=DIO +um_feathers3.menu.FlashMode.dio.build.flash_mode=dio +um_feathers3.menu.FlashMode.dio.build.boot=dio + +um_feathers3.menu.UploadSpeed.921600=921600 +um_feathers3.menu.UploadSpeed.921600.upload.speed=921600 +um_feathers3.menu.UploadSpeed.115200=115200 +um_feathers3.menu.UploadSpeed.115200.upload.speed=115200 +um_feathers3.menu.UploadSpeed.256000.windows=256000 +um_feathers3.menu.UploadSpeed.256000.upload.speed=256000 +um_feathers3.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_feathers3.menu.UploadSpeed.230400=230400 +um_feathers3.menu.UploadSpeed.230400.upload.speed=230400 +um_feathers3.menu.UploadSpeed.460800.linux=460800 +um_feathers3.menu.UploadSpeed.460800.macosx=460800 +um_feathers3.menu.UploadSpeed.460800.upload.speed=460800 +um_feathers3.menu.UploadSpeed.512000.windows=512000 +um_feathers3.menu.UploadSpeed.512000.upload.speed=512000 + +um_feathers3.menu.DebugLevel.none=None +um_feathers3.menu.DebugLevel.none.build.code_debug=0 +um_feathers3.menu.DebugLevel.error=Error +um_feathers3.menu.DebugLevel.error.build.code_debug=1 +um_feathers3.menu.DebugLevel.warn=Warn +um_feathers3.menu.DebugLevel.warn.build.code_debug=2 +um_feathers3.menu.DebugLevel.info=Info +um_feathers3.menu.DebugLevel.info.build.code_debug=3 +um_feathers3.menu.DebugLevel.debug=Debug +um_feathers3.menu.DebugLevel.debug.build.code_debug=4 +um_feathers3.menu.DebugLevel.verbose=Verbose +um_feathers3.menu.DebugLevel.verbose.build.code_debug=5 + +um_feathers3.menu.EraseFlash.none=Disabled +um_feathers3.menu.EraseFlash.none.upload.erase_cmd= +um_feathers3.menu.EraseFlash.all=Enabled +um_feathers3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_feathers3neo.name=UM FeatherS3 Neo +um_feathers3neo.vid.0=0x303a +um_feathers3neo.pid.0=0x81FB +um_feathers3neo.upload_port.0.vid=0x303a +um_feathers3neo.upload_port.0.pid=0x81FB + +um_feathers3neo.bootloader.tool=esptool_py +um_feathers3neo.bootloader.tool.default=esptool_py + +um_feathers3neo.upload.tool=esptool_py +um_feathers3neo.upload.tool.default=esptool_py +um_feathers3neo.upload.tool.network=esp_ota + +um_feathers3neo.upload.maximum_size=1310720 +um_feathers3neo.upload.maximum_data_size=327680 +um_feathers3neo.upload.flags= +um_feathers3neo.upload.extra_flags= +um_feathers3neo.upload.use_1200bps_touch=false +um_feathers3neo.upload.wait_for_upload_port=false + +um_feathers3neo.serial.disableDTR=false +um_feathers3neo.serial.disableRTS=false + +um_feathers3neo.build.tarch=xtensa +um_feathers3neo.build.bootloader_addr=0x0 +um_feathers3neo.build.target=esp32s3 +um_feathers3neo.build.mcu=esp32s3 +um_feathers3neo.build.core=esp32 +um_feathers3neo.build.variant=um_feathers3neo +um_feathers3neo.build.board=FEATHERS3NEO + +um_feathers3neo.build.usb_mode=1 +um_feathers3neo.build.cdc_on_boot=1 +um_feathers3neo.build.msc_on_boot=0 +um_feathers3neo.build.dfu_on_boot=0 +um_feathers3neo.build.f_cpu=240000000L +um_feathers3neo.build.flash_size=8MB +um_feathers3neo.build.flash_freq=80m +um_feathers3neo.build.flash_mode=dio +um_feathers3neo.build.boot=qio +um_feathers3neo.build.partitions=default +um_feathers3neo.build.defines= +um_feathers3neo.build.loop_core= +um_feathers3neo.build.event_core= +um_feathers3neo.build.flash_type=qio +um_feathers3neo.build.psram_type=qspi +um_feathers3neo.build.memory_type=qio_qspi + +um_feathers3neo.menu.LoopCore.1=Core 1 +um_feathers3neo.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_feathers3neo.menu.LoopCore.0=Core 0 +um_feathers3neo.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_feathers3neo.menu.EventsCore.1=Core 1 +um_feathers3neo.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_feathers3neo.menu.EventsCore.0=Core 0 +um_feathers3neo.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_feathers3neo.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_feathers3neo.menu.USBMode.hwcdc.build.usb_mode=1 +um_feathers3neo.menu.USBMode.default=USB-OTG (TinyUSB) +um_feathers3neo.menu.USBMode.default.build.usb_mode=0 + +um_feathers3neo.menu.CDCOnBoot.cdc=Enabled +um_feathers3neo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_feathers3neo.menu.CDCOnBoot.default=Disabled +um_feathers3neo.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_feathers3neo.menu.MSCOnBoot.default=Disabled +um_feathers3neo.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_feathers3neo.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_feathers3neo.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_feathers3neo.menu.DFUOnBoot.default=Disabled +um_feathers3neo.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_feathers3neo.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_feathers3neo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_feathers3neo.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_feathers3neo.menu.UploadMode.default=UART0 / Hardware CDC +um_feathers3neo.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_feathers3neo.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_feathers3neo.menu.UploadMode.default.upload.use_1200bps_touch=false +um_feathers3neo.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_feathers3neo.menu.PSRAM.enabled=Enabled +um_feathers3neo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_feathers3neo.menu.PSRAM.disabled=Disabled +um_feathers3neo.menu.PSRAM.disabled.build.defines= + +um_feathers3neo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +um_feathers3neo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_feathers3neo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_feathers3neo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +um_feathers3neo.menu.PartitionScheme.minimal.build.partitions=minimal +um_feathers3neo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +um_feathers3neo.menu.PartitionScheme.no_ota.build.partitions=no_ota +um_feathers3neo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +um_feathers3neo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +um_feathers3neo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +um_feathers3neo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +um_feathers3neo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +um_feathers3neo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +um_feathers3neo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +um_feathers3neo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +um_feathers3neo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +um_feathers3neo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +um_feathers3neo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +um_feathers3neo.menu.PartitionScheme.huge_app.build.partitions=huge_app +um_feathers3neo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +um_feathers3neo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +um_feathers3neo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +um_feathers3neo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +um_feathers3neo.menu.CPUFreq.240=240MHz (WiFi) +um_feathers3neo.menu.CPUFreq.240.build.f_cpu=240000000L +um_feathers3neo.menu.CPUFreq.160=160MHz (WiFi) +um_feathers3neo.menu.CPUFreq.160.build.f_cpu=160000000L +um_feathers3neo.menu.CPUFreq.80=80MHz (WiFi) +um_feathers3neo.menu.CPUFreq.80.build.f_cpu=80000000L +um_feathers3neo.menu.CPUFreq.40=40MHz +um_feathers3neo.menu.CPUFreq.40.build.f_cpu=40000000L +um_feathers3neo.menu.CPUFreq.20=20MHz +um_feathers3neo.menu.CPUFreq.20.build.f_cpu=20000000L +um_feathers3neo.menu.CPUFreq.10=10MHz +um_feathers3neo.menu.CPUFreq.10.build.f_cpu=10000000L + +um_feathers3neo.menu.FlashMode.qio=QIO +um_feathers3neo.menu.FlashMode.qio.build.flash_mode=dio +um_feathers3neo.menu.FlashMode.qio.build.boot=qio +um_feathers3neo.menu.FlashMode.dio=DIO +um_feathers3neo.menu.FlashMode.dio.build.flash_mode=dio +um_feathers3neo.menu.FlashMode.dio.build.boot=dio + +um_feathers3neo.menu.UploadSpeed.921600=921600 +um_feathers3neo.menu.UploadSpeed.921600.upload.speed=921600 +um_feathers3neo.menu.UploadSpeed.115200=115200 +um_feathers3neo.menu.UploadSpeed.115200.upload.speed=115200 +um_feathers3neo.menu.UploadSpeed.256000.windows=256000 +um_feathers3neo.menu.UploadSpeed.256000.upload.speed=256000 +um_feathers3neo.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_feathers3neo.menu.UploadSpeed.230400=230400 +um_feathers3neo.menu.UploadSpeed.230400.upload.speed=230400 +um_feathers3neo.menu.UploadSpeed.460800.linux=460800 +um_feathers3neo.menu.UploadSpeed.460800.macosx=460800 +um_feathers3neo.menu.UploadSpeed.460800.upload.speed=460800 +um_feathers3neo.menu.UploadSpeed.512000.windows=512000 +um_feathers3neo.menu.UploadSpeed.512000.upload.speed=512000 + +um_feathers3neo.menu.DebugLevel.none=None +um_feathers3neo.menu.DebugLevel.none.build.code_debug=0 +um_feathers3neo.menu.DebugLevel.error=Error +um_feathers3neo.menu.DebugLevel.error.build.code_debug=1 +um_feathers3neo.menu.DebugLevel.warn=Warn +um_feathers3neo.menu.DebugLevel.warn.build.code_debug=2 +um_feathers3neo.menu.DebugLevel.info=Info +um_feathers3neo.menu.DebugLevel.info.build.code_debug=3 +um_feathers3neo.menu.DebugLevel.debug=Debug +um_feathers3neo.menu.DebugLevel.debug.build.code_debug=4 +um_feathers3neo.menu.DebugLevel.verbose=Verbose +um_feathers3neo.menu.DebugLevel.verbose.build.code_debug=5 + +um_feathers3neo.menu.EraseFlash.none=Disabled +um_feathers3neo.menu.EraseFlash.none.upload.erase_cmd= +um_feathers3neo.menu.EraseFlash.all=Enabled +um_feathers3neo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_nanos3.name=UM NanoS3 +um_nanos3.vid.0=0x303a +um_nanos3.pid.0=0x8179 +um_nanos3.upload_port.0.vid=0x303a +um_nanos3.upload_port.0.pid=0x8179 + +um_nanos3.bootloader.tool=esptool_py +um_nanos3.bootloader.tool.default=esptool_py + +um_nanos3.upload.tool=esptool_py +um_nanos3.upload.tool.default=esptool_py +um_nanos3.upload.tool.network=esp_ota + +um_nanos3.upload.maximum_size=1310720 +um_nanos3.upload.maximum_data_size=327680 +um_nanos3.upload.flags= +um_nanos3.upload.extra_flags= +um_nanos3.upload.use_1200bps_touch=false +um_nanos3.upload.wait_for_upload_port=false + +um_nanos3.serial.disableDTR=false +um_nanos3.serial.disableRTS=false + +um_nanos3.build.tarch=xtensa +um_nanos3.build.bootloader_addr=0x0 +um_nanos3.build.target=esp32s3 +um_nanos3.build.mcu=esp32s3 +um_nanos3.build.core=esp32 +um_nanos3.build.variant=um_nanos3 +um_nanos3.build.board=NANOS3 + +um_nanos3.build.usb_mode=1 +um_nanos3.build.cdc_on_boot=1 +um_nanos3.build.msc_on_boot=0 +um_nanos3.build.dfu_on_boot=0 +um_nanos3.build.f_cpu=240000000L +um_nanos3.build.flash_size=8MB +um_nanos3.build.flash_freq=80m +um_nanos3.build.flash_mode=dio +um_nanos3.build.boot=qio +um_nanos3.build.partitions=default +um_nanos3.build.defines= +um_nanos3.build.loop_core= +um_nanos3.build.event_core= +um_nanos3.build.flash_type=qio +um_nanos3.build.psram_type=qspi +um_nanos3.build.memory_type=qio_qspi + +um_nanos3.menu.LoopCore.1=Core 1 +um_nanos3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_nanos3.menu.LoopCore.0=Core 0 +um_nanos3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_nanos3.menu.EventsCore.1=Core 1 +um_nanos3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_nanos3.menu.EventsCore.0=Core 0 +um_nanos3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_nanos3.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_nanos3.menu.USBMode.hwcdc.build.usb_mode=1 +um_nanos3.menu.USBMode.default=USB-OTG (TinyUSB) +um_nanos3.menu.USBMode.default.build.usb_mode=0 + +um_nanos3.menu.CDCOnBoot.cdc=Enabled +um_nanos3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_nanos3.menu.CDCOnBoot.default=Disabled +um_nanos3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_nanos3.menu.MSCOnBoot.default=Disabled +um_nanos3.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_nanos3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_nanos3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_nanos3.menu.DFUOnBoot.default=Disabled +um_nanos3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_nanos3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_nanos3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_nanos3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_nanos3.menu.UploadMode.default=UART0 / Hardware CDC +um_nanos3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_nanos3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_nanos3.menu.UploadMode.default.upload.use_1200bps_touch=false +um_nanos3.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_nanos3.menu.PSRAM.enabled=Enabled +um_nanos3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_nanos3.menu.PSRAM.disabled=Disabled +um_nanos3.menu.PSRAM.disabled.build.defines= + +um_nanos3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +um_nanos3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_nanos3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_nanos3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT) +um_nanos3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_nanos3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_nanos3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_nanos3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 + +um_nanos3.menu.CPUFreq.240=240MHz (WiFi) +um_nanos3.menu.CPUFreq.240.build.f_cpu=240000000L +um_nanos3.menu.CPUFreq.160=160MHz (WiFi) +um_nanos3.menu.CPUFreq.160.build.f_cpu=160000000L +um_nanos3.menu.CPUFreq.80=80MHz (WiFi) +um_nanos3.menu.CPUFreq.80.build.f_cpu=80000000L +um_nanos3.menu.CPUFreq.40=40MHz +um_nanos3.menu.CPUFreq.40.build.f_cpu=40000000L +um_nanos3.menu.CPUFreq.20=20MHz +um_nanos3.menu.CPUFreq.20.build.f_cpu=20000000L +um_nanos3.menu.CPUFreq.10=10MHz +um_nanos3.menu.CPUFreq.10.build.f_cpu=10000000L + +um_nanos3.menu.FlashMode.qio=QIO +um_nanos3.menu.FlashMode.qio.build.flash_mode=dio +um_nanos3.menu.FlashMode.qio.build.boot=qio +um_nanos3.menu.FlashMode.dio=DIO +um_nanos3.menu.FlashMode.dio.build.flash_mode=dio +um_nanos3.menu.FlashMode.dio.build.boot=dio + +um_nanos3.menu.UploadSpeed.921600=921600 +um_nanos3.menu.UploadSpeed.921600.upload.speed=921600 +um_nanos3.menu.UploadSpeed.115200=115200 +um_nanos3.menu.UploadSpeed.115200.upload.speed=115200 +um_nanos3.menu.UploadSpeed.256000.windows=256000 +um_nanos3.menu.UploadSpeed.256000.upload.speed=256000 +um_nanos3.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_nanos3.menu.UploadSpeed.230400=230400 +um_nanos3.menu.UploadSpeed.230400.upload.speed=230400 +um_nanos3.menu.UploadSpeed.460800.linux=460800 +um_nanos3.menu.UploadSpeed.460800.macosx=460800 +um_nanos3.menu.UploadSpeed.460800.upload.speed=460800 +um_nanos3.menu.UploadSpeed.512000.windows=512000 +um_nanos3.menu.UploadSpeed.512000.upload.speed=512000 + +um_nanos3.menu.DebugLevel.none=None +um_nanos3.menu.DebugLevel.none.build.code_debug=0 +um_nanos3.menu.DebugLevel.error=Error +um_nanos3.menu.DebugLevel.error.build.code_debug=1 +um_nanos3.menu.DebugLevel.warn=Warn +um_nanos3.menu.DebugLevel.warn.build.code_debug=2 +um_nanos3.menu.DebugLevel.info=Info +um_nanos3.menu.DebugLevel.info.build.code_debug=3 +um_nanos3.menu.DebugLevel.debug=Debug +um_nanos3.menu.DebugLevel.debug.build.code_debug=4 +um_nanos3.menu.DebugLevel.verbose=Verbose +um_nanos3.menu.DebugLevel.verbose.build.code_debug=5 + +um_nanos3.menu.EraseFlash.none=Disabled +um_nanos3.menu.EraseFlash.none.upload.erase_cmd= +um_nanos3.menu.EraseFlash.all=Enabled +um_nanos3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_omgs3.name=UM OMGS3 +um_omgs3.vid.0=0x303a +um_omgs3.pid.0=0x8224 +um_omgs3.upload_port.0.vid=0x303a +um_omgs3.upload_port.0.pid=0x8224 + +um_omgs3.bootloader.tool=esptool_py +um_omgs3.bootloader.tool.default=esptool_py + +um_omgs3.upload.tool=esptool_py +um_omgs3.upload.tool.default=esptool_py +um_omgs3.upload.tool.network=esp_ota + +um_omgs3.upload.maximum_size=1310720 +um_omgs3.upload.maximum_data_size=327680 +um_omgs3.upload.flags= +um_omgs3.upload.extra_flags= +um_omgs3.upload.use_1200bps_touch=false +um_omgs3.upload.wait_for_upload_port=false + +um_omgs3.serial.disableDTR=false +um_omgs3.serial.disableRTS=false + +um_omgs3.build.tarch=xtensa +um_omgs3.build.bootloader_addr=0x0 +um_omgs3.build.target=esp32s3 +um_omgs3.build.mcu=esp32s3 +um_omgs3.build.core=esp32 +um_omgs3.build.variant=um_omgs3 +um_omgs3.build.board=OMGS3 + +um_omgs3.build.usb_mode=1 +um_omgs3.build.cdc_on_boot=1 +um_omgs3.build.msc_on_boot=0 +um_omgs3.build.dfu_on_boot=0 +um_omgs3.build.f_cpu=240000000L +um_omgs3.build.flash_size=8MB +um_omgs3.build.flash_freq=80m +um_omgs3.build.flash_mode=dio +um_omgs3.build.boot=qio +um_omgs3.build.partitions=default +um_omgs3.build.defines= +um_omgs3.build.loop_core= +um_omgs3.build.event_core= +um_omgs3.build.flash_type=qio +um_omgs3.build.psram_type=qspi +um_omgs3.build.memory_type=qio_qspi + +um_omgs3.menu.LoopCore.1=Core 1 +um_omgs3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_omgs3.menu.LoopCore.0=Core 0 +um_omgs3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_omgs3.menu.EventsCore.1=Core 1 +um_omgs3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_omgs3.menu.EventsCore.0=Core 0 +um_omgs3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_omgs3.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_omgs3.menu.USBMode.hwcdc.build.usb_mode=1 +um_omgs3.menu.USBMode.default=USB-OTG (TinyUSB) +um_omgs3.menu.USBMode.default.build.usb_mode=0 + +um_omgs3.menu.CDCOnBoot.cdc=Enabled +um_omgs3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_omgs3.menu.CDCOnBoot.default=Disabled +um_omgs3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_omgs3.menu.MSCOnBoot.default=Disabled +um_omgs3.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_omgs3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_omgs3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_omgs3.menu.DFUOnBoot.default=Disabled +um_omgs3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_omgs3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_omgs3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_omgs3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_omgs3.menu.UploadMode.default=UART0 / Hardware CDC +um_omgs3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_omgs3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_omgs3.menu.UploadMode.default.upload.use_1200bps_touch=false +um_omgs3.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_omgs3.menu.PSRAM.enabled=Enabled +um_omgs3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_omgs3.menu.PSRAM.disabled=Disabled +um_omgs3.menu.PSRAM.disabled.build.defines= + +um_omgs3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +um_omgs3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_omgs3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_omgs3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT) +um_omgs3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_omgs3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_omgs3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_omgs3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 + +um_omgs3.menu.CPUFreq.240=240MHz (WiFi) +um_omgs3.menu.CPUFreq.240.build.f_cpu=240000000L +um_omgs3.menu.CPUFreq.160=160MHz (WiFi) +um_omgs3.menu.CPUFreq.160.build.f_cpu=160000000L +um_omgs3.menu.CPUFreq.80=80MHz (WiFi) +um_omgs3.menu.CPUFreq.80.build.f_cpu=80000000L +um_omgs3.menu.CPUFreq.40=40MHz +um_omgs3.menu.CPUFreq.40.build.f_cpu=40000000L +um_omgs3.menu.CPUFreq.20=20MHz +um_omgs3.menu.CPUFreq.20.build.f_cpu=20000000L +um_omgs3.menu.CPUFreq.10=10MHz +um_omgs3.menu.CPUFreq.10.build.f_cpu=10000000L + +um_omgs3.menu.FlashMode.qio=QIO +um_omgs3.menu.FlashMode.qio.build.flash_mode=dio +um_omgs3.menu.FlashMode.qio.build.boot=qio +um_omgs3.menu.FlashMode.dio=DIO +um_omgs3.menu.FlashMode.dio.build.flash_mode=dio +um_omgs3.menu.FlashMode.dio.build.boot=dio + +um_omgs3.menu.UploadSpeed.921600=921600 +um_omgs3.menu.UploadSpeed.921600.upload.speed=921600 +um_omgs3.menu.UploadSpeed.115200=115200 +um_omgs3.menu.UploadSpeed.115200.upload.speed=115200 +um_omgs3.menu.UploadSpeed.256000.windows=256000 +um_omgs3.menu.UploadSpeed.256000.upload.speed=256000 +um_omgs3.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_omgs3.menu.UploadSpeed.230400=230400 +um_omgs3.menu.UploadSpeed.230400.upload.speed=230400 +um_omgs3.menu.UploadSpeed.460800.linux=460800 +um_omgs3.menu.UploadSpeed.460800.macosx=460800 +um_omgs3.menu.UploadSpeed.460800.upload.speed=460800 +um_omgs3.menu.UploadSpeed.512000.windows=512000 +um_omgs3.menu.UploadSpeed.512000.upload.speed=512000 + +um_omgs3.menu.DebugLevel.none=None +um_omgs3.menu.DebugLevel.none.build.code_debug=0 +um_omgs3.menu.DebugLevel.error=Error +um_omgs3.menu.DebugLevel.error.build.code_debug=1 +um_omgs3.menu.DebugLevel.warn=Warn +um_omgs3.menu.DebugLevel.warn.build.code_debug=2 +um_omgs3.menu.DebugLevel.info=Info +um_omgs3.menu.DebugLevel.info.build.code_debug=3 +um_omgs3.menu.DebugLevel.debug=Debug +um_omgs3.menu.DebugLevel.debug.build.code_debug=4 +um_omgs3.menu.DebugLevel.verbose=Verbose +um_omgs3.menu.DebugLevel.verbose.build.code_debug=5 + +um_omgs3.menu.EraseFlash.none=Disabled +um_omgs3.menu.EraseFlash.none.upload.erase_cmd= +um_omgs3.menu.EraseFlash.all=Enabled +um_omgs3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_pros3.name=UM PROS3 +um_pros3.vid.0=0x303a +um_pros3.pid.0=0x80D3 +um_pros3.upload_port.0.vid=0x303a +um_pros3.upload_port.0.pid=0x80D3 + +um_pros3.bootloader.tool=esptool_py +um_pros3.bootloader.tool.default=esptool_py + +um_pros3.upload.tool=esptool_py +um_pros3.upload.tool.default=esptool_py +um_pros3.upload.tool.network=esp_ota + +um_pros3.upload.maximum_size=1310720 +um_pros3.upload.maximum_data_size=327680 +um_pros3.upload.flags= +um_pros3.upload.extra_flags= +um_pros3.upload.use_1200bps_touch=false +um_pros3.upload.wait_for_upload_port=false + +um_pros3.serial.disableDTR=false +um_pros3.serial.disableRTS=false + +um_pros3.build.tarch=xtensa +um_pros3.build.bootloader_addr=0x0 +um_pros3.build.target=esp32s3 +um_pros3.build.mcu=esp32s3 +um_pros3.build.core=esp32 +um_pros3.build.variant=um_pros3 +um_pros3.build.board=PROS3 + +um_pros3.build.usb_mode=1 +um_pros3.build.cdc_on_boot=1 +um_pros3.build.msc_on_boot=0 +um_pros3.build.dfu_on_boot=0 +um_pros3.build.f_cpu=240000000L +um_pros3.build.flash_size=16MB +um_pros3.build.flash_freq=80m +um_pros3.build.flash_mode=dio +um_pros3.build.boot=qio +um_pros3.build.partitions=default +um_pros3.build.defines= +um_pros3.build.loop_core= +um_pros3.build.event_core= +um_pros3.build.flash_type=qio +um_pros3.build.psram_type=qspi +um_pros3.build.memory_type=qio_qspi + +um_pros3.menu.LoopCore.1=Core 1 +um_pros3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_pros3.menu.LoopCore.0=Core 0 +um_pros3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_pros3.menu.EventsCore.1=Core 1 +um_pros3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_pros3.menu.EventsCore.0=Core 0 +um_pros3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_pros3.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_pros3.menu.USBMode.hwcdc.build.usb_mode=1 +um_pros3.menu.USBMode.default=USB-OTG (TinyUSB) +um_pros3.menu.USBMode.default.build.usb_mode=0 + +um_pros3.menu.CDCOnBoot.cdc=Enabled +um_pros3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_pros3.menu.CDCOnBoot.default=Disabled +um_pros3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_pros3.menu.MSCOnBoot.default=Disabled +um_pros3.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_pros3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_pros3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_pros3.menu.DFUOnBoot.default=Disabled +um_pros3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_pros3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_pros3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_pros3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_pros3.menu.UploadMode.default=UART0 / Hardware CDC +um_pros3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_pros3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_pros3.menu.UploadMode.default.upload.use_1200bps_touch=false +um_pros3.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_pros3.menu.PSRAM.enabled=Enabled +um_pros3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_pros3.menu.PSRAM.disabled=Disabled +um_pros3.menu.PSRAM.disabled.build.defines= + +um_pros3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +um_pros3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +um_pros3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +um_pros3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT) +um_pros3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_pros3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_pros3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_pros3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +um_pros3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +um_pros3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +um_pros3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +um_pros3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +um_pros3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +um_pros3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +um_pros3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +um_pros3.menu.PartitionScheme.fatflash.build.partitions=ffat +um_pros3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +um_pros3.menu.CPUFreq.240=240MHz (WiFi) +um_pros3.menu.CPUFreq.240.build.f_cpu=240000000L +um_pros3.menu.CPUFreq.160=160MHz (WiFi) +um_pros3.menu.CPUFreq.160.build.f_cpu=160000000L +um_pros3.menu.CPUFreq.80=80MHz (WiFi) +um_pros3.menu.CPUFreq.80.build.f_cpu=80000000L +um_pros3.menu.CPUFreq.40=40MHz +um_pros3.menu.CPUFreq.40.build.f_cpu=40000000L +um_pros3.menu.CPUFreq.20=20MHz +um_pros3.menu.CPUFreq.20.build.f_cpu=20000000L +um_pros3.menu.CPUFreq.10=10MHz +um_pros3.menu.CPUFreq.10.build.f_cpu=10000000L + +um_pros3.menu.FlashMode.qio=QIO +um_pros3.menu.FlashMode.qio.build.flash_mode=dio +um_pros3.menu.FlashMode.qio.build.boot=qio +um_pros3.menu.FlashMode.dio=DIO +um_pros3.menu.FlashMode.dio.build.flash_mode=dio +um_pros3.menu.FlashMode.dio.build.boot=dio + +um_pros3.menu.UploadSpeed.921600=921600 +um_pros3.menu.UploadSpeed.921600.upload.speed=921600 +um_pros3.menu.UploadSpeed.115200=115200 +um_pros3.menu.UploadSpeed.115200.upload.speed=115200 +um_pros3.menu.UploadSpeed.256000.windows=256000 +um_pros3.menu.UploadSpeed.256000.upload.speed=256000 +um_pros3.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_pros3.menu.UploadSpeed.230400=230400 +um_pros3.menu.UploadSpeed.230400.upload.speed=230400 +um_pros3.menu.UploadSpeed.460800.linux=460800 +um_pros3.menu.UploadSpeed.460800.macosx=460800 +um_pros3.menu.UploadSpeed.460800.upload.speed=460800 +um_pros3.menu.UploadSpeed.512000.windows=512000 +um_pros3.menu.UploadSpeed.512000.upload.speed=512000 + +um_pros3.menu.DebugLevel.none=None +um_pros3.menu.DebugLevel.none.build.code_debug=0 +um_pros3.menu.DebugLevel.error=Error +um_pros3.menu.DebugLevel.error.build.code_debug=1 +um_pros3.menu.DebugLevel.warn=Warn +um_pros3.menu.DebugLevel.warn.build.code_debug=2 +um_pros3.menu.DebugLevel.info=Info +um_pros3.menu.DebugLevel.info.build.code_debug=3 +um_pros3.menu.DebugLevel.debug=Debug +um_pros3.menu.DebugLevel.debug.build.code_debug=4 +um_pros3.menu.DebugLevel.verbose=Verbose +um_pros3.menu.DebugLevel.verbose.build.code_debug=5 + +um_pros3.menu.EraseFlash.none=Disabled +um_pros3.menu.EraseFlash.none.upload.erase_cmd= +um_pros3.menu.EraseFlash.all=Enabled +um_pros3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_squixl.name=UM SQUIXL +um_squixl.vid.0=0x303a +um_squixl.pid.0=0x82DF +um_squixl.upload_port.0.vid=0x303a +um_squixl.upload_port.0.pid=0x82DF + +um_squixl.bootloader.tool=esptool_py +um_squixl.bootloader.tool.default=esptool_py + +um_squixl.upload.tool=esptool_py +um_squixl.upload.tool.default=esptool_py +um_squixl.upload.tool.network=esp_ota + +um_squixl.upload.maximum_size=1310720 +um_squixl.upload.maximum_data_size=327680 +um_squixl.upload.flags= +um_squixl.upload.extra_flags= +um_squixl.upload.use_1200bps_touch=false +um_squixl.upload.wait_for_upload_port=false + +um_squixl.serial.disableDTR=false +um_squixl.serial.disableRTS=false + +um_squixl.build.tarch=xtensa +um_squixl.build.bootloader_addr=0x0 +um_squixl.build.target=esp32s3 +um_squixl.build.mcu=esp32s3 +um_squixl.build.core=esp32 +um_squixl.build.variant=um_squixl +um_squixl.build.board=SQUIXL + +um_squixl.build.usb_mode=1 +um_squixl.build.cdc_on_boot=1 +um_squixl.build.msc_on_boot=0 +um_squixl.build.dfu_on_boot=0 +um_squixl.build.f_cpu=240000000L +um_squixl.build.flash_size=16MB +um_squixl.build.flash_freq=80m +um_squixl.build.flash_mode=dio +um_squixl.build.boot=qio +um_squixl.build.partitions=default +um_squixl.build.defines= +um_squixl.build.loop_core= +um_squixl.build.event_core= +um_squixl.build.flash_type=qio +um_squixl.build.psram_type=opi +um_squixl.build.memory_type=qio_opi + +um_squixl.menu.LoopCore.1=Core 1 +um_squixl.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_squixl.menu.LoopCore.0=Core 0 +um_squixl.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_squixl.menu.EventsCore.1=Core 1 +um_squixl.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_squixl.menu.EventsCore.0=Core 0 +um_squixl.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_squixl.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_squixl.menu.USBMode.hwcdc.build.usb_mode=1 +um_squixl.menu.USBMode.default=USB-OTG (TinyUSB) +um_squixl.menu.USBMode.default.build.usb_mode=0 + +um_squixl.menu.CDCOnBoot.cdc=Enabled +um_squixl.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_squixl.menu.CDCOnBoot.default=Disabled +um_squixl.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_squixl.menu.MSCOnBoot.default=Disabled +um_squixl.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_squixl.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_squixl.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_squixl.menu.DFUOnBoot.default=Disabled +um_squixl.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_squixl.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_squixl.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_squixl.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_squixl.menu.UploadMode.default=UART0 / Hardware CDC +um_squixl.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_squixl.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_squixl.menu.UploadMode.default.upload.use_1200bps_touch=false +um_squixl.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_squixl.menu.PSRAM.opi=OPI PSRAM +um_squixl.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +um_squixl.menu.PSRAM.opi.build.psram_type=opi + +um_squixl.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +um_squixl.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +um_squixl.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +um_squixl.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +um_squixl.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +um_squixl.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +um_squixl.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +um_squixl.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +um_squixl.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +um_squixl.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +um_squixl.menu.PartitionScheme.fatflash.build.partitions=ffat +um_squixl.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +um_squixl.menu.CPUFreq.240=240MHz (WiFi) +um_squixl.menu.CPUFreq.240.build.f_cpu=240000000L +um_squixl.menu.CPUFreq.160=160MHz (WiFi) +um_squixl.menu.CPUFreq.160.build.f_cpu=160000000L +um_squixl.menu.CPUFreq.80=80MHz (WiFi) +um_squixl.menu.CPUFreq.80.build.f_cpu=80000000L +um_squixl.menu.CPUFreq.40=40MHz +um_squixl.menu.CPUFreq.40.build.f_cpu=40000000L +um_squixl.menu.CPUFreq.20=20MHz +um_squixl.menu.CPUFreq.20.build.f_cpu=20000000L +um_squixl.menu.CPUFreq.10=10MHz +um_squixl.menu.CPUFreq.10.build.f_cpu=10000000L + +um_squixl.menu.FlashMode.qio=QIO +um_squixl.menu.FlashMode.qio.build.flash_mode=dio +um_squixl.menu.FlashMode.qio.build.boot=qio +um_squixl.menu.FlashMode.dio=DIO +um_squixl.menu.FlashMode.dio.build.flash_mode=dio +um_squixl.menu.FlashMode.dio.build.boot=dio + +um_squixl.menu.UploadSpeed.921600=921600 +um_squixl.menu.UploadSpeed.921600.upload.speed=921600 +um_squixl.menu.UploadSpeed.115200=115200 +um_squixl.menu.UploadSpeed.115200.upload.speed=115200 +um_squixl.menu.UploadSpeed.256000.windows=256000 +um_squixl.menu.UploadSpeed.256000.upload.speed=256000 +um_squixl.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_squixl.menu.UploadSpeed.230400=230400 +um_squixl.menu.UploadSpeed.230400.upload.speed=230400 +um_squixl.menu.UploadSpeed.460800.linux=460800 +um_squixl.menu.UploadSpeed.460800.macosx=460800 +um_squixl.menu.UploadSpeed.460800.upload.speed=460800 +um_squixl.menu.UploadSpeed.512000.windows=512000 +um_squixl.menu.UploadSpeed.512000.upload.speed=512000 + +um_squixl.menu.DebugLevel.none=None +um_squixl.menu.DebugLevel.none.build.code_debug=0 +um_squixl.menu.DebugLevel.error=Error +um_squixl.menu.DebugLevel.error.build.code_debug=1 +um_squixl.menu.DebugLevel.warn=Warn +um_squixl.menu.DebugLevel.warn.build.code_debug=2 +um_squixl.menu.DebugLevel.info=Info +um_squixl.menu.DebugLevel.info.build.code_debug=3 +um_squixl.menu.DebugLevel.debug=Debug +um_squixl.menu.DebugLevel.debug.build.code_debug=4 +um_squixl.menu.DebugLevel.verbose=Verbose +um_squixl.menu.DebugLevel.verbose.build.code_debug=5 + +um_squixl.menu.EraseFlash.none=Disabled +um_squixl.menu.EraseFlash.none.upload.erase_cmd= +um_squixl.menu.EraseFlash.all=Enabled +um_squixl.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_tinypico.name=UM TinyPICO + +um_tinypico.bootloader.tool=esptool_py +um_tinypico.bootloader.tool.default=esptool_py + +um_tinypico.upload.tool=esptool_py +um_tinypico.upload.tool.default=esptool_py +um_tinypico.upload.tool.network=esp_ota + +um_tinypico.upload.maximum_size=1310720 +um_tinypico.upload.maximum_data_size=327680 +um_tinypico.upload.flags= +um_tinypico.upload.extra_flags= + +um_tinypico.serial.disableDTR=true +um_tinypico.serial.disableRTS=true + +um_tinypico.build.tarch=xtensa +um_tinypico.build.bootloader_addr=0x1000 +um_tinypico.build.target=esp32 +um_tinypico.build.mcu=esp32 +um_tinypico.build.core=esp32 +um_tinypico.build.variant=um_tinypico +um_tinypico.build.board=TINYPICO + +um_tinypico.build.f_cpu=240000000L +um_tinypico.build.flash_size=4MB +um_tinypico.build.flash_freq=80m +um_tinypico.build.flash_mode=dio +um_tinypico.build.boot=dio +um_tinypico.build.partitions=default +um_tinypico.build.defines= + +um_tinypico.menu.PartitionScheme.default=Default +um_tinypico.menu.PartitionScheme.default.build.partitions=default +um_tinypico.menu.PartitionScheme.no_ota=No OTA (Large APP) +um_tinypico.menu.PartitionScheme.no_ota.build.partitions=no_ota +um_tinypico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +um_tinypico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +um_tinypico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +um_tinypico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +um_tinypico.menu.UploadSpeed.921600=921600 +um_tinypico.menu.UploadSpeed.921600.upload.speed=921600 +um_tinypico.menu.UploadSpeed.115200=115200 +um_tinypico.menu.UploadSpeed.115200.upload.speed=115200 +um_tinypico.menu.UploadSpeed.256000.windows=256000 +um_tinypico.menu.UploadSpeed.256000.upload.speed=256000 +um_tinypico.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_tinypico.menu.UploadSpeed.230400=230400 +um_tinypico.menu.UploadSpeed.230400.upload.speed=230400 +um_tinypico.menu.UploadSpeed.460800.linux=460800 +um_tinypico.menu.UploadSpeed.460800.macosx=460800 +um_tinypico.menu.UploadSpeed.460800.upload.speed=460800 +um_tinypico.menu.UploadSpeed.512000.windows=512000 +um_tinypico.menu.UploadSpeed.512000.upload.speed=512000 + +um_tinypico.menu.FlashMode.qio=QIO +um_tinypico.menu.FlashMode.qio.build.flash_mode=dio +um_tinypico.menu.FlashMode.qio.build.boot=qio +um_tinypico.menu.FlashMode.dio=DIO +um_tinypico.menu.FlashMode.dio.build.flash_mode=dio +um_tinypico.menu.FlashMode.dio.build.boot=dio + +um_tinypico.menu.FlashFreq.80=80MHz +um_tinypico.menu.FlashFreq.80.build.flash_freq=80m +um_tinypico.menu.FlashFreq.40=40MHz +um_tinypico.menu.FlashFreq.40.build.flash_freq=40m + +um_tinypico.menu.PSRAM.enabled=Enabled +um_tinypico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +um_tinypico.menu.PSRAM.enabled.build.extra_libs= +um_tinypico.menu.PSRAM.disabled=Disabled +um_tinypico.menu.PSRAM.disabled.build.defines= +um_tinypico.menu.PSRAM.disabled.build.extra_libs= + +um_tinypico.menu.DebugLevel.none=None +um_tinypico.menu.DebugLevel.none.build.code_debug=0 +um_tinypico.menu.DebugLevel.error=Error +um_tinypico.menu.DebugLevel.error.build.code_debug=1 +um_tinypico.menu.DebugLevel.warn=Warn +um_tinypico.menu.DebugLevel.warn.build.code_debug=2 +um_tinypico.menu.DebugLevel.info=Info +um_tinypico.menu.DebugLevel.info.build.code_debug=3 +um_tinypico.menu.DebugLevel.debug=Debug +um_tinypico.menu.DebugLevel.debug.build.code_debug=4 +um_tinypico.menu.DebugLevel.verbose=Verbose +um_tinypico.menu.DebugLevel.verbose.build.code_debug=5 + +um_tinypico.menu.EraseFlash.none=Disabled +um_tinypico.menu.EraseFlash.none.upload.erase_cmd= +um_tinypico.menu.EraseFlash.all=Enabled +um_tinypico.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_tinyc6.name=UM TinyC6 + +um_tinyc6.bootloader.tool=esptool_py +um_tinyc6.bootloader.tool.default=esptool_py + +um_tinyc6.upload.tool=esptool_py +um_tinyc6.upload.tool.default=esptool_py +um_tinyc6.upload.tool.network=esp_ota + +um_tinyc6.upload.maximum_size=1310720 +um_tinyc6.upload.maximum_data_size=327680 +um_tinyc6.upload.flags= +um_tinyc6.upload.extra_flags= +um_tinyc6.upload.use_1200bps_touch=false +um_tinyc6.upload.wait_for_upload_port=false + +um_tinyc6.serial.disableDTR=false +um_tinyc6.serial.disableRTS=false + +um_tinyc6.build.tarch=riscv32 +um_tinyc6.build.target=esp +um_tinyc6.build.mcu=esp32c6 +um_tinyc6.build.core=esp32 +um_tinyc6.build.variant=um_tinyc6 +um_tinyc6.build.board=TINYC6 +um_tinyc6.build.bootloader_addr=0x0 + +um_tinyc6.build.cdc_on_boot=1 +um_tinyc6.build.f_cpu=160000000L +um_tinyc6.build.flash_size=8MB +um_tinyc6.build.flash_freq=80m +um_tinyc6.build.flash_mode=qio +um_tinyc6.build.boot=qio +um_tinyc6.build.partitions=default +um_tinyc6.build.defines= + +## IDE 2.0 Seems to not update the value +um_tinyc6.menu.JTAGAdapter.default=Disabled +um_tinyc6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +um_tinyc6.menu.JTAGAdapter.builtin=Integrated USB JTAG +um_tinyc6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +um_tinyc6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +um_tinyc6.menu.JTAGAdapter.external=FTDI Adapter +um_tinyc6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +um_tinyc6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +um_tinyc6.menu.JTAGAdapter.bridge=ESP USB Bridge +um_tinyc6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +um_tinyc6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +um_tinyc6.menu.CDCOnBoot.cdc=Enabled +um_tinyc6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_tinyc6.menu.CDCOnBoot.default=Disabled +um_tinyc6.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_tinyc6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +um_tinyc6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_tinyc6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_tinyc6.menu.PartitionScheme.rainmaker=RainMaker 4MB +um_tinyc6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +um_tinyc6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +um_tinyc6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +um_tinyc6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +um_tinyc6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +um_tinyc6.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +um_tinyc6.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +um_tinyc6.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +um_tinyc6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +um_tinyc6.menu.PartitionScheme.zigbee.build.partitions=zigbee +um_tinyc6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +um_tinyc6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +um_tinyc6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +um_tinyc6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +um_tinyc6.menu.PartitionScheme.custom=Custom +um_tinyc6.menu.PartitionScheme.custom.build.partitions= +um_tinyc6.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +um_tinyc6.menu.CPUFreq.160=160MHz (WiFi) +um_tinyc6.menu.CPUFreq.160.build.f_cpu=160000000L +um_tinyc6.menu.CPUFreq.80=80MHz (WiFi) +um_tinyc6.menu.CPUFreq.80.build.f_cpu=80000000L +um_tinyc6.menu.CPUFreq.40=40MHz +um_tinyc6.menu.CPUFreq.40.build.f_cpu=40000000L +um_tinyc6.menu.CPUFreq.20=20MHz +um_tinyc6.menu.CPUFreq.20.build.f_cpu=20000000L +um_tinyc6.menu.CPUFreq.10=10MHz +um_tinyc6.menu.CPUFreq.10.build.f_cpu=10000000L + +um_tinyc6.menu.FlashMode.qio=QIO +um_tinyc6.menu.FlashMode.qio.build.flash_mode=dio +um_tinyc6.menu.FlashMode.qio.build.boot=qio +um_tinyc6.menu.FlashMode.dio=DIO +um_tinyc6.menu.FlashMode.dio.build.flash_mode=dio +um_tinyc6.menu.FlashMode.dio.build.boot=dio + +um_tinyc6.menu.FlashFreq.80=80MHz +um_tinyc6.menu.FlashFreq.80.build.flash_freq=80m +um_tinyc6.menu.FlashFreq.40=40MHz +um_tinyc6.menu.FlashFreq.40.build.flash_freq=40m + +um_tinyc6.menu.FlashSize.8M=8MB (64Mb) +um_tinyc6.menu.FlashSize.8M.build.flash_size=8MB + +um_tinyc6.menu.UploadSpeed.921600=921600 +um_tinyc6.menu.UploadSpeed.921600.upload.speed=921600 +um_tinyc6.menu.UploadSpeed.115200=115200 +um_tinyc6.menu.UploadSpeed.115200.upload.speed=115200 +um_tinyc6.menu.UploadSpeed.256000.windows=256000 +um_tinyc6.menu.UploadSpeed.256000.upload.speed=256000 +um_tinyc6.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_tinyc6.menu.UploadSpeed.230400=230400 +um_tinyc6.menu.UploadSpeed.230400.upload.speed=230400 +um_tinyc6.menu.UploadSpeed.460800.linux=460800 +um_tinyc6.menu.UploadSpeed.460800.macosx=460800 +um_tinyc6.menu.UploadSpeed.460800.upload.speed=460800 +um_tinyc6.menu.UploadSpeed.512000.windows=512000 +um_tinyc6.menu.UploadSpeed.512000.upload.speed=512000 + +um_tinyc6.menu.DebugLevel.none=None +um_tinyc6.menu.DebugLevel.none.build.code_debug=0 +um_tinyc6.menu.DebugLevel.error=Error +um_tinyc6.menu.DebugLevel.error.build.code_debug=1 +um_tinyc6.menu.DebugLevel.warn=Warn +um_tinyc6.menu.DebugLevel.warn.build.code_debug=2 +um_tinyc6.menu.DebugLevel.info=Info +um_tinyc6.menu.DebugLevel.info.build.code_debug=3 +um_tinyc6.menu.DebugLevel.debug=Debug +um_tinyc6.menu.DebugLevel.debug.build.code_debug=4 +um_tinyc6.menu.DebugLevel.verbose=Verbose +um_tinyc6.menu.DebugLevel.verbose.build.code_debug=5 + +um_tinyc6.menu.EraseFlash.none=Disabled +um_tinyc6.menu.EraseFlash.none.upload.erase_cmd= +um_tinyc6.menu.EraseFlash.all=Enabled +um_tinyc6.menu.EraseFlash.all.upload.erase_cmd=-e + +um_tinyc6.menu.ZigbeeMode.default=Disabled +um_tinyc6.menu.ZigbeeMode.default.build.zigbee_mode= +um_tinyc6.menu.ZigbeeMode.default.build.zigbee_libs= +um_tinyc6.menu.ZigbeeMode.ed=Zigbee ED (end device) +um_tinyc6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +um_tinyc6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +um_tinyc6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +um_tinyc6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +um_tinyc6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +um_tinys2.name=UM TinyS2 +um_tinys2.vid.0=0x303a +um_tinys2.pid.0=0x8001 +um_tinys2.upload_port.0.vid=0x303a +um_tinys2.upload_port.0.pid=0x8001 + +um_tinys2.bootloader.tool=esptool_py +um_tinys2.bootloader.tool.default=esptool_py + +um_tinys2.upload.tool=esptool_py +um_tinys2.upload.tool.default=esptool_py +um_tinys2.upload.tool.network=esp_ota + +um_tinys2.upload.maximum_size=1310720 +um_tinys2.upload.maximum_data_size=327680 +um_tinys2.upload.flags= +um_tinys2.upload.extra_flags= +um_tinys2.upload.use_1200bps_touch=true +um_tinys2.upload.wait_for_upload_port=true + +um_tinys2.serial.disableDTR=false +um_tinys2.serial.disableRTS=false + +um_tinys2.build.tarch=xtensa +um_tinys2.build.bootloader_addr=0x1000 +um_tinys2.build.target=esp32s2 +um_tinys2.build.mcu=esp32s2 +um_tinys2.build.core=esp32 +um_tinys2.build.variant=um_tinys2 +um_tinys2.build.board=TINYS2 + +um_tinys2.build.cdc_on_boot=1 +um_tinys2.build.msc_on_boot=0 +um_tinys2.build.dfu_on_boot=0 +um_tinys2.build.f_cpu=240000000L +um_tinys2.build.flash_size=4MB +um_tinys2.build.flash_freq=80m +um_tinys2.build.flash_mode=dio +um_tinys2.build.boot=qio +um_tinys2.build.partitions=default +um_tinys2.build.defines= + +um_tinys2.menu.CDCOnBoot.cdc=Enabled +um_tinys2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_tinys2.menu.CDCOnBoot.default=Disabled +um_tinys2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_tinys2.menu.MSCOnBoot.default=Disabled +um_tinys2.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_tinys2.menu.MSCOnBoot.msc=Enabled +um_tinys2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_tinys2.menu.DFUOnBoot.default=Disabled +um_tinys2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_tinys2.menu.DFUOnBoot.dfu=Enabled +um_tinys2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_tinys2.menu.PSRAM.enabled=Enabled +um_tinys2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_tinys2.menu.PSRAM.disabled=Disabled +um_tinys2.menu.PSRAM.disabled.build.defines= + +um_tinys2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +um_tinys2.menu.PartitionScheme.default.build.partitions=default +um_tinys2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +um_tinys2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +um_tinys2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +um_tinys2.menu.PartitionScheme.minimal.build.partitions=minimal +um_tinys2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +um_tinys2.menu.PartitionScheme.no_ota.build.partitions=no_ota +um_tinys2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +um_tinys2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +um_tinys2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +um_tinys2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +um_tinys2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +um_tinys2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +um_tinys2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +um_tinys2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +um_tinys2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +um_tinys2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +um_tinys2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +um_tinys2.menu.PartitionScheme.huge_app.build.partitions=huge_app +um_tinys2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +um_tinys2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +um_tinys2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +um_tinys2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +um_tinys2.menu.CPUFreq.240=240MHz (WiFi) +um_tinys2.menu.CPUFreq.240.build.f_cpu=240000000L +um_tinys2.menu.CPUFreq.160=160MHz (WiFi) +um_tinys2.menu.CPUFreq.160.build.f_cpu=160000000L +um_tinys2.menu.CPUFreq.80=80MHz (WiFi) +um_tinys2.menu.CPUFreq.80.build.f_cpu=80000000L +um_tinys2.menu.CPUFreq.40=40MHz +um_tinys2.menu.CPUFreq.40.build.f_cpu=40000000L +um_tinys2.menu.CPUFreq.20=20MHz +um_tinys2.menu.CPUFreq.20.build.f_cpu=20000000L +um_tinys2.menu.CPUFreq.10=10MHz +um_tinys2.menu.CPUFreq.10.build.f_cpu=10000000L + +um_tinys2.menu.FlashSize.4M=4MB (32Mb) +um_tinys2.menu.FlashSize.4M.build.flash_size=4MB +um_tinys2.menu.FlashSize.2M=2MB (16Mb) +um_tinys2.menu.FlashSize.2M.build.flash_size=2MB + +um_tinys2.menu.UploadSpeed.921600=921600 +um_tinys2.menu.UploadSpeed.921600.upload.speed=921600 +um_tinys2.menu.UploadSpeed.115200=115200 +um_tinys2.menu.UploadSpeed.115200.upload.speed=115200 +um_tinys2.menu.UploadSpeed.256000.windows=256000 +um_tinys2.menu.UploadSpeed.256000.upload.speed=256000 +um_tinys2.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_tinys2.menu.UploadSpeed.230400=230400 +um_tinys2.menu.UploadSpeed.230400.upload.speed=230400 +um_tinys2.menu.UploadSpeed.460800.linux=460800 +um_tinys2.menu.UploadSpeed.460800.macosx=460800 +um_tinys2.menu.UploadSpeed.460800.upload.speed=460800 + +um_tinys2.menu.DebugLevel.none=None +um_tinys2.menu.DebugLevel.none.build.code_debug=0 +um_tinys2.menu.DebugLevel.error=Error +um_tinys2.menu.DebugLevel.error.build.code_debug=1 +um_tinys2.menu.DebugLevel.warn=Warn +um_tinys2.menu.DebugLevel.warn.build.code_debug=2 +um_tinys2.menu.DebugLevel.info=Info +um_tinys2.menu.DebugLevel.info.build.code_debug=3 +um_tinys2.menu.DebugLevel.debug=Debug +um_tinys2.menu.DebugLevel.debug.build.code_debug=4 +um_tinys2.menu.DebugLevel.verbose=Verbose +um_tinys2.menu.DebugLevel.verbose.build.code_debug=5 + +um_tinys2.menu.EraseFlash.none=Disabled +um_tinys2.menu.EraseFlash.none.upload.erase_cmd= +um_tinys2.menu.EraseFlash.all=Enabled +um_tinys2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +um_tinys3.name=UM TinyS3 +um_tinys3.vid.0=0x303a +um_tinys3.pid.0=0x80D0 +um_tinys3.upload_port.0.vid=0x303a +um_tinys3.upload_port.0.pid=0x80D0 + +um_tinys3.bootloader.tool=esptool_py +um_tinys3.bootloader.tool.default=esptool_py + +um_tinys3.upload.tool=esptool_py +um_tinys3.upload.tool.default=esptool_py +um_tinys3.upload.tool.network=esp_ota + +um_tinys3.upload.maximum_size=1310720 +um_tinys3.upload.maximum_data_size=327680 +um_tinys3.upload.flags= +um_tinys3.upload.extra_flags= +um_tinys3.upload.use_1200bps_touch=false +um_tinys3.upload.wait_for_upload_port=false + +um_tinys3.serial.disableDTR=false +um_tinys3.serial.disableRTS=false + +um_tinys3.build.tarch=xtensa +um_tinys3.build.bootloader_addr=0x0 +um_tinys3.build.target=esp32s3 +um_tinys3.build.mcu=esp32s3 +um_tinys3.build.core=esp32 +um_tinys3.build.variant=um_tinys3 +um_tinys3.build.board=TINYS3 + +um_tinys3.build.usb_mode=1 +um_tinys3.build.cdc_on_boot=1 +um_tinys3.build.msc_on_boot=0 +um_tinys3.build.dfu_on_boot=0 +um_tinys3.build.f_cpu=240000000L +um_tinys3.build.flash_size=8MB +um_tinys3.build.flash_freq=80m +um_tinys3.build.flash_mode=dio +um_tinys3.build.boot=qio +um_tinys3.build.partitions=default +um_tinys3.build.defines= +um_tinys3.build.loop_core= +um_tinys3.build.event_core= +um_tinys3.build.flash_type=qio +um_tinys3.build.psram_type=qspi +um_tinys3.build.memory_type=qio_qspi + +um_tinys3.menu.LoopCore.1=Core 1 +um_tinys3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +um_tinys3.menu.LoopCore.0=Core 0 +um_tinys3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +um_tinys3.menu.EventsCore.1=Core 1 +um_tinys3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +um_tinys3.menu.EventsCore.0=Core 0 +um_tinys3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +um_tinys3.menu.USBMode.hwcdc=Hardware CDC and JTAG +um_tinys3.menu.USBMode.hwcdc.build.usb_mode=1 +um_tinys3.menu.USBMode.default=USB-OTG (TinyUSB) +um_tinys3.menu.USBMode.default.build.usb_mode=0 + +um_tinys3.menu.CDCOnBoot.cdc=Enabled +um_tinys3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +um_tinys3.menu.CDCOnBoot.default=Disabled +um_tinys3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +um_tinys3.menu.MSCOnBoot.default=Disabled +um_tinys3.menu.MSCOnBoot.default.build.msc_on_boot=0 +um_tinys3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +um_tinys3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +um_tinys3.menu.DFUOnBoot.default=Disabled +um_tinys3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +um_tinys3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +um_tinys3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +um_tinys3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +um_tinys3.menu.UploadMode.default=UART0 / Hardware CDC +um_tinys3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +um_tinys3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +um_tinys3.menu.UploadMode.default.upload.use_1200bps_touch=false +um_tinys3.menu.UploadMode.default.upload.wait_for_upload_port=false + +um_tinys3.menu.PSRAM.enabled=Enabled +um_tinys3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +um_tinys3.menu.PSRAM.disabled=Disabled +um_tinys3.menu.PSRAM.disabled.build.defines= + +um_tinys3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +um_tinys3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +um_tinys3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +um_tinys3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT) +um_tinys3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +um_tinys3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +um_tinys3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +um_tinys3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 + +um_tinys3.menu.CPUFreq.240=240MHz (WiFi) +um_tinys3.menu.CPUFreq.240.build.f_cpu=240000000L +um_tinys3.menu.CPUFreq.160=160MHz (WiFi) +um_tinys3.menu.CPUFreq.160.build.f_cpu=160000000L +um_tinys3.menu.CPUFreq.80=80MHz (WiFi) +um_tinys3.menu.CPUFreq.80.build.f_cpu=80000000L +um_tinys3.menu.CPUFreq.40=40MHz +um_tinys3.menu.CPUFreq.40.build.f_cpu=40000000L +um_tinys3.menu.CPUFreq.20=20MHz +um_tinys3.menu.CPUFreq.20.build.f_cpu=20000000L +um_tinys3.menu.CPUFreq.10=10MHz +um_tinys3.menu.CPUFreq.10.build.f_cpu=10000000L + +um_tinys3.menu.FlashMode.qio=QIO +um_tinys3.menu.FlashMode.qio.build.flash_mode=dio +um_tinys3.menu.FlashMode.qio.build.boot=qio +um_tinys3.menu.FlashMode.dio=DIO +um_tinys3.menu.FlashMode.dio.build.flash_mode=dio +um_tinys3.menu.FlashMode.dio.build.boot=dio + +um_tinys3.menu.UploadSpeed.921600=921600 +um_tinys3.menu.UploadSpeed.921600.upload.speed=921600 +um_tinys3.menu.UploadSpeed.115200=115200 +um_tinys3.menu.UploadSpeed.115200.upload.speed=115200 +um_tinys3.menu.UploadSpeed.256000.windows=256000 +um_tinys3.menu.UploadSpeed.256000.upload.speed=256000 +um_tinys3.menu.UploadSpeed.230400.windows.upload.speed=256000 +um_tinys3.menu.UploadSpeed.230400=230400 +um_tinys3.menu.UploadSpeed.230400.upload.speed=230400 +um_tinys3.menu.UploadSpeed.460800.linux=460800 +um_tinys3.menu.UploadSpeed.460800.macosx=460800 +um_tinys3.menu.UploadSpeed.460800.upload.speed=460800 +um_tinys3.menu.UploadSpeed.512000.windows=512000 +um_tinys3.menu.UploadSpeed.512000.upload.speed=512000 + +um_tinys3.menu.DebugLevel.none=None +um_tinys3.menu.DebugLevel.none.build.code_debug=0 +um_tinys3.menu.DebugLevel.error=Error +um_tinys3.menu.DebugLevel.error.build.code_debug=1 +um_tinys3.menu.DebugLevel.warn=Warn +um_tinys3.menu.DebugLevel.warn.build.code_debug=2 +um_tinys3.menu.DebugLevel.info=Info +um_tinys3.menu.DebugLevel.info.build.code_debug=3 +um_tinys3.menu.DebugLevel.debug=Debug +um_tinys3.menu.DebugLevel.debug.build.code_debug=4 +um_tinys3.menu.DebugLevel.verbose=Verbose +um_tinys3.menu.DebugLevel.verbose.build.code_debug=5 + +um_tinys3.menu.EraseFlash.none=Disabled +um_tinys3.menu.EraseFlash.none.upload.erase_cmd= +um_tinys3.menu.EraseFlash.all=Enabled +um_tinys3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +S_ODI_Ultra.name=S.ODI Ultra v1 + +S_ODI_Ultra.bootloader.tool=esptool_py +S_ODI_Ultra.bootloader.tool.default=esptool_py + +S_ODI_Ultra.upload.tool=esptool_py +S_ODI_Ultra.upload.tool.default=esptool_py +S_ODI_Ultra.upload.tool.network=esp_ota + +S_ODI_Ultra.upload.maximum_size=1310720 +S_ODI_Ultra.upload.maximum_data_size=327680 +S_ODI_Ultra.upload.wait_for_upload_port=true +S_ODI_Ultra.upload.flags= +S_ODI_Ultra.upload.extra_flags= + +S_ODI_Ultra.serial.disableDTR=true +S_ODI_Ultra.serial.disableRTS=true + +S_ODI_Ultra.build.tarch=xtensa +S_ODI_Ultra.build.bootloader_addr=0x1000 +S_ODI_Ultra.build.target=esp32 +S_ODI_Ultra.build.mcu=esp32 +S_ODI_Ultra.build.core=esp32 +S_ODI_Ultra.build.variant=S_ODI_Ultra_v1 +S_ODI_Ultra.build.board=ESP32_DEV + +S_ODI_Ultra.build.f_cpu=240000000L +S_ODI_Ultra.build.flash_mode=dio +S_ODI_Ultra.build.flash_size=4MB +S_ODI_Ultra.build.boot=dio +S_ODI_Ultra.build.partitions=default +S_ODI_Ultra.build.defines= + +S_ODI_Ultra.menu.FlashFreq.80=80MHz +S_ODI_Ultra.menu.FlashFreq.80.build.flash_freq=80m +S_ODI_Ultra.menu.FlashFreq.40=40MHz +S_ODI_Ultra.menu.FlashFreq.40.build.flash_freq=40m + +S_ODI_Ultra.menu.UploadSpeed.921600=921600 +S_ODI_Ultra.menu.UploadSpeed.921600.upload.speed=921600 +S_ODI_Ultra.menu.UploadSpeed.115200=115200 +S_ODI_Ultra.menu.UploadSpeed.115200.upload.speed=115200 +S_ODI_Ultra.menu.UploadSpeed.256000.windows=256000 +S_ODI_Ultra.menu.UploadSpeed.256000.upload.speed=256000 +S_ODI_Ultra.menu.UploadSpeed.230400.windows.upload.speed=256000 +S_ODI_Ultra.menu.UploadSpeed.230400=230400 +S_ODI_Ultra.menu.UploadSpeed.230400.upload.speed=230400 +S_ODI_Ultra.menu.UploadSpeed.460800.linux=460800 +S_ODI_Ultra.menu.UploadSpeed.460800.macosx=460800 +S_ODI_Ultra.menu.UploadSpeed.460800.upload.speed=460800 +S_ODI_Ultra.menu.UploadSpeed.512000.windows=512000 +S_ODI_Ultra.menu.UploadSpeed.512000.upload.speed=512000 + +S_ODI_Ultra.menu.DebugLevel.none=None +S_ODI_Ultra.menu.DebugLevel.none.build.code_debug=0 +S_ODI_Ultra.menu.DebugLevel.error=Error +S_ODI_Ultra.menu.DebugLevel.error.build.code_debug=1 +S_ODI_Ultra.menu.DebugLevel.warn=Warn +S_ODI_Ultra.menu.DebugLevel.warn.build.code_debug=2 +S_ODI_Ultra.menu.DebugLevel.info=Info +S_ODI_Ultra.menu.DebugLevel.info.build.code_debug=3 +S_ODI_Ultra.menu.DebugLevel.debug=Debug +S_ODI_Ultra.menu.DebugLevel.debug.build.code_debug=4 +S_ODI_Ultra.menu.DebugLevel.verbose=Verbose +S_ODI_Ultra.menu.DebugLevel.verbose.build.code_debug=5 + +S_ODI_Ultra.menu.EraseFlash.none=Disabled +S_ODI_Ultra.menu.EraseFlash.none.upload.erase_cmd= +S_ODI_Ultra.menu.EraseFlash.all=Enabled +S_ODI_Ultra.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lilygo_t_display.name=LilyGo T-Display + +lilygo_t_display.upload.tool=esptool_py +lilygo_t_display.upload.tool.default=esptool_py +lilygo_t_display.upload.tool.network=esp_ota +lilygo_t_display.upload.maximum_size=1310720 +lilygo_t_display.upload.maximum_data_size=327680 +lilygo_t_display.upload.wait_for_upload_port=true +lilygo_t_display.upload.speed=460800 +lilygo_t_display.upload.flags= +lilygo_t_display.upload.extra_flags= + +lilygo_t_display.bootloader.tool=esptool_py +lilygo_t_display.bootloader.tool.default=esptool_py + +lilygo_t_display.serial.disableDTR=true +lilygo_t_display.serial.disableRTS=true + +lilygo_t_display.build.tarch=xtensa +lilygo_t_display.build.bootloader_addr=0x1000 +lilygo_t_display.build.mcu=esp32 +lilygo_t_display.build.core=esp32 +lilygo_t_display.build.target=esp32 +lilygo_t_display.build.variant=lilygo_t_display +lilygo_t_display.build.board=LILYGO_T_DISPLAY + +lilygo_t_display.build.f_cpu=240000000L +lilygo_t_display.build.flash_size=4MB +lilygo_t_display.build.flash_freq=80m +lilygo_t_display.build.flash_mode=dio +lilygo_t_display.build.boot=dio +lilygo_t_display.build.partitions=default + +lilygo_t_display.menu.PSRAM.disabled=Disabled +lilygo_t_display.menu.PSRAM.disabled.build.defines= +lilygo_t_display.menu.PSRAM.enabled=Enabled +lilygo_t_display.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +lilygo_t_display.menu.PSRAM.enabled.build.extra_libs= + +lilygo_t_display.menu.LoopCore.1=Core 1 +lilygo_t_display.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lilygo_t_display.menu.LoopCore.0=Core 0 +lilygo_t_display.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lilygo_t_display.menu.EventsCore.1=Core 1 +lilygo_t_display.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lilygo_t_display.menu.EventsCore.0=Core 0 +lilygo_t_display.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lilygo_t_display.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lilygo_t_display.menu.PartitionScheme.default.build.partitions=default +lilygo_t_display.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lilygo_t_display.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lilygo_t_display.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +lilygo_t_display.menu.PartitionScheme.minimal.build.partitions=minimal +lilygo_t_display.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lilygo_t_display.menu.PartitionScheme.no_ota.build.partitions=no_ota +lilygo_t_display.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lilygo_t_display.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lilygo_t_display.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lilygo_t_display.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lilygo_t_display.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lilygo_t_display.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lilygo_t_display.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lilygo_t_display.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lilygo_t_display.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lilygo_t_display.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lilygo_t_display.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lilygo_t_display.menu.PartitionScheme.huge_app.build.partitions=huge_app +lilygo_t_display.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lilygo_t_display.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lilygo_t_display.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lilygo_t_display.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +lilygo_t_display.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +lilygo_t_display.menu.PartitionScheme.fatflash.build.partitions=ffat +lilygo_t_display.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +lilygo_t_display.menu.CPUFreq.240=240MHz (WiFi/BT) +lilygo_t_display.menu.CPUFreq.240.build.f_cpu=240000000L +lilygo_t_display.menu.CPUFreq.160=160MHz (WiFi/BT) +lilygo_t_display.menu.CPUFreq.160.build.f_cpu=160000000L +lilygo_t_display.menu.CPUFreq.80=80MHz (WiFi/BT) +lilygo_t_display.menu.CPUFreq.80.build.f_cpu=80000000L +lilygo_t_display.menu.CPUFreq.40=40MHz (40MHz XTAL) +lilygo_t_display.menu.CPUFreq.40.build.f_cpu=40000000L +lilygo_t_display.menu.CPUFreq.26=26MHz (26MHz XTAL) +lilygo_t_display.menu.CPUFreq.26.build.f_cpu=26000000L +lilygo_t_display.menu.CPUFreq.20=20MHz (40MHz XTAL) +lilygo_t_display.menu.CPUFreq.20.build.f_cpu=20000000L +lilygo_t_display.menu.CPUFreq.13=13MHz (26MHz XTAL) +lilygo_t_display.menu.CPUFreq.13.build.f_cpu=13000000L +lilygo_t_display.menu.CPUFreq.10=10MHz (40MHz XTAL) +lilygo_t_display.menu.CPUFreq.10.build.f_cpu=10000000L + +lilygo_t_display.menu.FlashMode.qio=QIO +lilygo_t_display.menu.FlashMode.qio.build.flash_mode=dio +lilygo_t_display.menu.FlashMode.qio.build.boot=qio +lilygo_t_display.menu.FlashMode.dio=DIO +lilygo_t_display.menu.FlashMode.dio.build.flash_mode=dio +lilygo_t_display.menu.FlashMode.dio.build.boot=dio + +lilygo_t_display.menu.FlashFreq.80=80MHz +lilygo_t_display.menu.FlashFreq.80.build.flash_freq=80m +lilygo_t_display.menu.FlashFreq.40=40MHz +lilygo_t_display.menu.FlashFreq.40.build.flash_freq=40m + +lilygo_t_display.menu.FlashSize.4M=4MB (32Mb) +lilygo_t_display.menu.FlashSize.4M.build.flash_size=4MB +lilygo_t_display.menu.FlashSize.16M=16MB (128Mb) +lilygo_t_display.menu.FlashSize.16M.build.flash_size=16MB + +lilygo_t_display.menu.UploadSpeed.921600=921600 +lilygo_t_display.menu.UploadSpeed.921600.upload.speed=921600 +lilygo_t_display.menu.UploadSpeed.115200=115200 +lilygo_t_display.menu.UploadSpeed.115200.upload.speed=115200 +lilygo_t_display.menu.UploadSpeed.256000.windows=256000 +lilygo_t_display.menu.UploadSpeed.256000.upload.speed=256000 +lilygo_t_display.menu.UploadSpeed.230400.windows.upload.speed=256000 +lilygo_t_display.menu.UploadSpeed.230400=230400 +lilygo_t_display.menu.UploadSpeed.230400.upload.speed=230400 +lilygo_t_display.menu.UploadSpeed.460800.linux=460800 +lilygo_t_display.menu.UploadSpeed.460800.macosx=460800 +lilygo_t_display.menu.UploadSpeed.460800.upload.speed=460800 +lilygo_t_display.menu.UploadSpeed.512000.windows=512000 +lilygo_t_display.menu.UploadSpeed.512000.upload.speed=512000 + +lilygo_t_display.menu.DebugLevel.none=None +lilygo_t_display.menu.DebugLevel.none.build.code_debug=0 +lilygo_t_display.menu.DebugLevel.error=Error +lilygo_t_display.menu.DebugLevel.error.build.code_debug=1 +lilygo_t_display.menu.DebugLevel.warn=Warn +lilygo_t_display.menu.DebugLevel.warn.build.code_debug=2 +lilygo_t_display.menu.DebugLevel.info=Info +lilygo_t_display.menu.DebugLevel.info.build.code_debug=3 +lilygo_t_display.menu.DebugLevel.debug=Debug +lilygo_t_display.menu.DebugLevel.debug.build.code_debug=4 +lilygo_t_display.menu.DebugLevel.verbose=Verbose +lilygo_t_display.menu.DebugLevel.verbose.build.code_debug=5 + +lilygo_t_display.menu.EraseFlash.none=Disabled +lilygo_t_display.menu.EraseFlash.none.upload.erase_cmd= +lilygo_t_display.menu.EraseFlash.all=Enabled +lilygo_t_display.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lilygo_t_display_s3.name=LilyGo T-Display-S3 + +lilygo_t_display_s3.bootloader.tool=esptool_py +lilygo_t_display_s3.bootloader.tool.default=esptool_py + +lilygo_t_display_s3.upload.tool=esptool_py +lilygo_t_display_s3.upload.tool.default=esptool_py +lilygo_t_display_s3.upload.tool.network=esp_ota + +lilygo_t_display_s3.upload.maximum_size=3145728 +lilygo_t_display_s3.upload.maximum_data_size=327680 +lilygo_t_display_s3.upload.speed=921600 +lilygo_t_display_s3.upload.flags= +lilygo_t_display_s3.upload.extra_flags= +lilygo_t_display_s3.upload.use_1200bps_touch=false +lilygo_t_display_s3.upload.wait_for_upload_port=false + +lilygo_t_display_s3.serial.disableDTR=false +lilygo_t_display_s3.serial.disableRTS=false + +lilygo_t_display_s3.build.tarch=xtensa +lilygo_t_display_s3.build.bootloader_addr=0x0 +lilygo_t_display_s3.build.target=esp32s3 +lilygo_t_display_s3.build.mcu=esp32s3 +lilygo_t_display_s3.build.core=esp32 +lilygo_t_display_s3.build.variant=lilygo_t_display_s3 +lilygo_t_display_s3.build.board=LILYGO_T_DISPLAY_S3 + +lilygo_t_display_s3.build.usb_mode=1 +lilygo_t_display_s3.build.cdc_on_boot=1 +lilygo_t_display_s3.build.msc_on_boot=0 +lilygo_t_display_s3.build.dfu_on_boot=0 +lilygo_t_display_s3.build.f_cpu=240000000L +lilygo_t_display_s3.build.flash_size=16MB +lilygo_t_display_s3.build.flash_freq=80m +lilygo_t_display_s3.build.flash_mode=dio +lilygo_t_display_s3.build.boot=qio +lilygo_t_display_s3.build.boot_freq=80m +lilygo_t_display_s3.build.partitions=app3M_fat9M_16MB +lilygo_t_display_s3.build.defines= +lilygo_t_display_s3.build.loop_core= +lilygo_t_display_s3.build.event_core= +lilygo_t_display_s3.build.psram_type=opi +lilygo_t_display_s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +lilygo_t_display_s3.menu.JTAGAdapter.default=Disabled +lilygo_t_display_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +lilygo_t_display_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +lilygo_t_display_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +lilygo_t_display_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +lilygo_t_display_s3.menu.LoopCore.1=Core 1 +lilygo_t_display_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lilygo_t_display_s3.menu.LoopCore.0=Core 0 +lilygo_t_display_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lilygo_t_display_s3.menu.EventsCore.1=Core 1 +lilygo_t_display_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lilygo_t_display_s3.menu.EventsCore.0=Core 0 +lilygo_t_display_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lilygo_t_display_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +lilygo_t_display_s3.menu.USBMode.hwcdc.build.usb_mode=1 +lilygo_t_display_s3.menu.USBMode.default=USB-OTG (TinyUSB) +lilygo_t_display_s3.menu.USBMode.default.build.usb_mode=0 + +lilygo_t_display_s3.menu.CDCOnBoot.cdc=Enabled +lilygo_t_display_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +lilygo_t_display_s3.menu.CDCOnBoot.default=Disabled +lilygo_t_display_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +lilygo_t_display_s3.menu.MSCOnBoot.default=Disabled +lilygo_t_display_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +lilygo_t_display_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lilygo_t_display_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lilygo_t_display_s3.menu.DFUOnBoot.default=Disabled +lilygo_t_display_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lilygo_t_display_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lilygo_t_display_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lilygo_t_display_s3.menu.UploadMode.default=UART0 / Hardware CDC +lilygo_t_display_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +lilygo_t_display_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +lilygo_t_display_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lilygo_t_display_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lilygo_t_display_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lilygo_t_display_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +lilygo_t_display_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lilygo_t_display_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +lilygo_t_display_s3.menu.DebugLevel.none=None +lilygo_t_display_s3.menu.DebugLevel.none.build.code_debug=0 +lilygo_t_display_s3.menu.DebugLevel.error=Error +lilygo_t_display_s3.menu.DebugLevel.error.build.code_debug=1 +lilygo_t_display_s3.menu.DebugLevel.warn=Warn +lilygo_t_display_s3.menu.DebugLevel.warn.build.code_debug=2 +lilygo_t_display_s3.menu.DebugLevel.info=Info +lilygo_t_display_s3.menu.DebugLevel.info.build.code_debug=3 +lilygo_t_display_s3.menu.DebugLevel.debug=Debug +lilygo_t_display_s3.menu.DebugLevel.debug.build.code_debug=4 +lilygo_t_display_s3.menu.DebugLevel.verbose=Verbose +lilygo_t_display_s3.menu.DebugLevel.verbose.build.code_debug=5 + +lilygo_t_display_s3.menu.EraseFlash.none=Disabled +lilygo_t_display_s3.menu.EraseFlash.none.upload.erase_cmd= +lilygo_t_display_s3.menu.EraseFlash.all=Enabled +lilygo_t_display_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lilygo_t_eth_lite.name=LilyGo T-ETH-Lite + +lilygo_t_eth_lite.bootloader.tool=esptool_py +lilygo_t_eth_lite.bootloader.tool.default=esptool_py + +lilygo_t_eth_lite.upload.tool=esptool_py +lilygo_t_eth_lite.upload.tool.default=esptool_py +lilygo_t_eth_lite.upload.tool.network=esp_ota + +lilygo_t_eth_lite.upload.maximum_size=3145728 +lilygo_t_eth_lite.upload.maximum_data_size=327680 +lilygo_t_eth_lite.upload.speed=921600 +lilygo_t_eth_lite.upload.flags= +lilygo_t_eth_lite.upload.extra_flags= +lilygo_t_eth_lite.upload.use_1200bps_touch=false +lilygo_t_eth_lite.upload.wait_for_upload_port=false + +lilygo_t_eth_lite.serial.disableDTR=false +lilygo_t_eth_lite.serial.disableRTS=false + +lilygo_t_eth_lite.build.tarch=xtensa +lilygo_t_eth_lite.build.bootloader_addr=0x0 +lilygo_t_eth_lite.build.target=esp32s3 +lilygo_t_eth_lite.build.mcu=esp32s3 +lilygo_t_eth_lite.build.core=esp32 +lilygo_t_eth_lite.build.variant=lilygo_t_eth_lite +lilygo_t_eth_lite.build.board=LILYGO_T_ETH_LITE + +lilygo_t_eth_lite.build.usb_mode=1 +lilygo_t_eth_lite.build.cdc_on_boot=0 +lilygo_t_eth_lite.build.msc_on_boot=0 +lilygo_t_eth_lite.build.dfu_on_boot=0 +lilygo_t_eth_lite.build.f_cpu=240000000L +lilygo_t_eth_lite.build.flash_size=16MB +lilygo_t_eth_lite.build.flash_freq=80m +lilygo_t_eth_lite.build.flash_mode=dio +lilygo_t_eth_lite.build.boot=qio +lilygo_t_eth_lite.build.boot_freq=80m +lilygo_t_eth_lite.build.partitions=app3M_fat9M_16MB +lilygo_t_eth_lite.build.defines= +lilygo_t_eth_lite.build.loop_core= +lilygo_t_eth_lite.build.event_core= +lilygo_t_eth_lite.build.psram_type=opi +lilygo_t_eth_lite.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +lilygo_t_eth_lite.menu.JTAGAdapter.default=Disabled +lilygo_t_eth_lite.menu.JTAGAdapter.default.build.copy_jtag_files=0 +lilygo_t_eth_lite.menu.JTAGAdapter.builtin=Integrated USB JTAG +lilygo_t_eth_lite.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +lilygo_t_eth_lite.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +lilygo_t_eth_lite.menu.LoopCore.1=Core 1 +lilygo_t_eth_lite.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lilygo_t_eth_lite.menu.LoopCore.0=Core 0 +lilygo_t_eth_lite.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lilygo_t_eth_lite.menu.EventsCore.1=Core 1 +lilygo_t_eth_lite.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lilygo_t_eth_lite.menu.EventsCore.0=Core 0 +lilygo_t_eth_lite.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lilygo_t_eth_lite.menu.USBMode.hwcdc=Hardware CDC and JTAG +lilygo_t_eth_lite.menu.USBMode.hwcdc.build.usb_mode=1 +lilygo_t_eth_lite.menu.USBMode.default=USB-OTG (TinyUSB) +lilygo_t_eth_lite.menu.USBMode.default.build.usb_mode=0 + +lilygo_t_eth_lite.menu.CDCOnBoot.default=Disabled +lilygo_t_eth_lite.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lilygo_t_eth_lite.menu.CDCOnBoot.cdc=Enabled +lilygo_t_eth_lite.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lilygo_t_eth_lite.menu.MSCOnBoot.default=Disabled +lilygo_t_eth_lite.menu.MSCOnBoot.default.build.msc_on_boot=0 +lilygo_t_eth_lite.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lilygo_t_eth_lite.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lilygo_t_eth_lite.menu.DFUOnBoot.default=Disabled +lilygo_t_eth_lite.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lilygo_t_eth_lite.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lilygo_t_eth_lite.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lilygo_t_eth_lite.menu.UploadMode.default=UART0 / Hardware CDC +lilygo_t_eth_lite.menu.UploadMode.default.upload.use_1200bps_touch=false +lilygo_t_eth_lite.menu.UploadMode.default.upload.wait_for_upload_port=false +lilygo_t_eth_lite.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lilygo_t_eth_lite.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lilygo_t_eth_lite.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker=RainMaker 4MB +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +lilygo_t_eth_lite.menu.DebugLevel.none=None +lilygo_t_eth_lite.menu.DebugLevel.none.build.code_debug=0 +lilygo_t_eth_lite.menu.DebugLevel.error=Error +lilygo_t_eth_lite.menu.DebugLevel.error.build.code_debug=1 +lilygo_t_eth_lite.menu.DebugLevel.warn=Warn +lilygo_t_eth_lite.menu.DebugLevel.warn.build.code_debug=2 +lilygo_t_eth_lite.menu.DebugLevel.info=Info +lilygo_t_eth_lite.menu.DebugLevel.info.build.code_debug=3 +lilygo_t_eth_lite.menu.DebugLevel.debug=Debug +lilygo_t_eth_lite.menu.DebugLevel.debug.build.code_debug=4 +lilygo_t_eth_lite.menu.DebugLevel.verbose=Verbose +lilygo_t_eth_lite.menu.DebugLevel.verbose.build.code_debug=5 + +lilygo_t_eth_lite.menu.EraseFlash.none=Disabled +lilygo_t_eth_lite.menu.EraseFlash.none.upload.erase_cmd= +lilygo_t_eth_lite.menu.EraseFlash.all=Enabled +lilygo_t_eth_lite.menu.EraseFlash.all.upload.erase_cmd=-e + + +############################################################## + +lilygo_t3s3.name=LilyGo T3-S3 + +lilygo_t3s3.upload.tool=esptool_py +lilygo_t3s3.upload.tool.default=esptool_py +lilygo_t3s3.upload.tool.network=esp_ota +lilygo_t3s3.upload.maximum_size=1310720 +lilygo_t3s3.upload.maximum_data_size=327680 +lilygo_t3s3.upload.wait_for_upload_port=false +lilygo_t3s3.upload.speed=460800 +lilygo_t3s3.upload.flags= +lilygo_t3s3.upload.extra_flags= + +lilygo_t3s3.bootloader.tool=esptool_py +lilygo_t3s3.bootloader.tool.default=esptool_py + +lilygo_t3s3.serial.disableDTR=true +lilygo_t3s3.serial.disableRTS=true + +lilygo_t3s3.build.tarch=xtensa +lilygo_t3s3.build.bootloader_addr=0x0 +lilygo_t3s3.build.mcu=esp32s3 +lilygo_t3s3.build.core=esp32 +lilygo_t3s3.build.target=esp32s3 +lilygo_t3s3.build.board=LILYGO_T3_S3 + +lilygo_t3s3.build.usb_mode=1 +lilygo_t3s3.build.cdc_on_boot=1 +lilygo_t3s3.build.msc_on_boot=0 +lilygo_t3s3.build.dfu_on_boot=0 + +lilygo_t3s3.build.f_cpu=240000000L +lilygo_t3s3.build.flash_size=4MB +lilygo_t3s3.build.flash_freq=80m +lilygo_t3s3.build.flash_mode=dio +lilygo_t3s3.build.boot=dio +lilygo_t3s3.build.partitions=default +lilygo_t3s3.build.defines= + +lilygo_t3s3.menu.PSRAM.disabled=Disabled +lilygo_t3s3.menu.PSRAM.disabled.build.defines= +lilygo_t3s3.menu.PSRAM.enabled=Enabled +lilygo_t3s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +lilygo_t3s3.menu.PSRAM.enabled.build.psram_type=qspi + +lilygo_t3s3.menu.LoopCore.1=Core 1 +lilygo_t3s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lilygo_t3s3.menu.LoopCore.0=Core 0 +lilygo_t3s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lilygo_t3s3.menu.EventsCore.1=Core 1 +lilygo_t3s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lilygo_t3s3.menu.EventsCore.0=Core 0 +lilygo_t3s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lilygo_t3s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +lilygo_t3s3.menu.USBMode.hwcdc.build.usb_mode=1 +lilygo_t3s3.menu.USBMode.default=USB-OTG (TinyUSB) +lilygo_t3s3.menu.USBMode.default.build.usb_mode=0 + +lilygo_t3s3.menu.CDCOnBoot.default=Disabled +lilygo_t3s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lilygo_t3s3.menu.CDCOnBoot.cdc=Enabled +lilygo_t3s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lilygo_t3s3.menu.MSCOnBoot.default=Disabled +lilygo_t3s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +lilygo_t3s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lilygo_t3s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lilygo_t3s3.menu.DFUOnBoot.default=Disabled +lilygo_t3s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lilygo_t3s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lilygo_t3s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lilygo_t3s3.menu.UploadMode.default=UART0 / Hardware CDC +lilygo_t3s3.menu.UploadMode.default.upload.use_1200bps_touch=false +lilygo_t3s3.menu.UploadMode.default.upload.wait_for_upload_port=false +lilygo_t3s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lilygo_t3s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lilygo_t3s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lilygo_t3s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.default.build.partitions=default +lilygo_t3s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lilygo_t3s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lilygo_t3s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.minimal.build.partitions=minimal +lilygo_t3s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +lilygo_t3s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lilygo_t3s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lilygo_t3s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lilygo_t3s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lilygo_t3s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lilygo_t3s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lilygo_t3s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lilygo_t3s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lilygo_t3s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lilygo_t3s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +lilygo_t3s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lilygo_t3s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lilygo_t3s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lilygo_t3s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +lilygo_t3s3.menu.CPUFreq.240=240MHz (WiFi/BT) +lilygo_t3s3.menu.CPUFreq.240.build.f_cpu=240000000L +lilygo_t3s3.menu.CPUFreq.160=160MHz (WiFi/BT) +lilygo_t3s3.menu.CPUFreq.160.build.f_cpu=160000000L +lilygo_t3s3.menu.CPUFreq.80=80MHz (WiFi/BT) +lilygo_t3s3.menu.CPUFreq.80.build.f_cpu=80000000L + +lilygo_t3s3.menu.FlashMode.qio=QIO +lilygo_t3s3.menu.FlashMode.qio.build.flash_mode=dio +lilygo_t3s3.menu.FlashMode.qio.build.boot=qio +lilygo_t3s3.menu.FlashMode.dio=DIO +lilygo_t3s3.menu.FlashMode.dio.build.flash_mode=dio +lilygo_t3s3.menu.FlashMode.dio.build.boot=dio + +lilygo_t3s3.menu.FlashFreq.80=80MHz +lilygo_t3s3.menu.FlashFreq.80.build.flash_freq=80m +lilygo_t3s3.menu.FlashFreq.40=40MHz +lilygo_t3s3.menu.FlashFreq.40.build.flash_freq=40m + +lilygo_t3s3.menu.UploadSpeed.921600=921600 +lilygo_t3s3.menu.UploadSpeed.921600.upload.speed=921600 +lilygo_t3s3.menu.UploadSpeed.115200=115200 +lilygo_t3s3.menu.UploadSpeed.115200.upload.speed=115200 +lilygo_t3s3.menu.UploadSpeed.256000.windows=256000 +lilygo_t3s3.menu.UploadSpeed.256000.upload.speed=256000 +lilygo_t3s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +lilygo_t3s3.menu.UploadSpeed.230400=230400 +lilygo_t3s3.menu.UploadSpeed.230400.upload.speed=230400 +lilygo_t3s3.menu.UploadSpeed.460800.linux=460800 +lilygo_t3s3.menu.UploadSpeed.460800.macosx=460800 +lilygo_t3s3.menu.UploadSpeed.460800.upload.speed=460800 +lilygo_t3s3.menu.UploadSpeed.512000.windows=512000 +lilygo_t3s3.menu.UploadSpeed.512000.upload.speed=512000 + +lilygo_t3s3.menu.DebugLevel.none=None +lilygo_t3s3.menu.DebugLevel.none.build.code_debug=0 +lilygo_t3s3.menu.DebugLevel.error=Error +lilygo_t3s3.menu.DebugLevel.error.build.code_debug=1 +lilygo_t3s3.menu.DebugLevel.warn=Warn +lilygo_t3s3.menu.DebugLevel.warn.build.code_debug=2 +lilygo_t3s3.menu.DebugLevel.info=Info +lilygo_t3s3.menu.DebugLevel.info.build.code_debug=3 +lilygo_t3s3.menu.DebugLevel.debug=Debug +lilygo_t3s3.menu.DebugLevel.debug.build.code_debug=4 +lilygo_t3s3.menu.DebugLevel.verbose=Verbose +lilygo_t3s3.menu.DebugLevel.verbose.build.code_debug=5 + +lilygo_t3s3.menu.EraseFlash.none=Disabled +lilygo_t3s3.menu.EraseFlash.none.upload.erase_cmd= +lilygo_t3s3.menu.EraseFlash.all=Enabled +lilygo_t3s3.menu.EraseFlash.all.upload.erase_cmd=-e + +lilygo_t3s3.menu.Revision.Radio_SX1262=Radio-SX1262 +lilygo_t3s3.menu.Revision.Radio_SX1262.build.board=LILYGO_T3S3_SX1262 +lilygo_t3s3.menu.Revision.Radio_SX1262.build.variant=lilygo_t3_s3_sx1262 + +lilygo_t3s3.menu.Revision.Radio_SX1276=Radio-SX1276 +lilygo_t3s3.menu.Revision.Radio_SX1276.build.board=LILYGO_T3S3_SX1276 +lilygo_t3s3.menu.Revision.Radio_SX1276.build.variant=lilygo_t3_s3_sx127x + +lilygo_t3s3.menu.Revision.Radio_SX1278=Radio-SX1278 +lilygo_t3s3.menu.Revision.Radio_SX1278.build.board=LILYGO_T3S3_SX1278 +lilygo_t3s3.menu.Revision.Radio_SX1278.build.variant=lilygo_t3_s3_sx127x + +lilygo_t3s3.menu.Revision.Radio_SX1280=Radio-SX1280 +lilygo_t3s3.menu.Revision.Radio_SX1280.build.board=LILYGO_T3S3_SX1280 +lilygo_t3s3.menu.Revision.Radio_SX1280.build.variant=lilygo_t3_s3_sx1280 + +lilygo_t3s3.menu.Revision.Radio_SX1280PA=Radio-SX1280PA +lilygo_t3s3.menu.Revision.Radio_SX1280PA.build.board=LILYGO_T3S3_SX1280PA +lilygo_t3s3.menu.Revision.Radio_SX1280PA.build.variant=lilygo_t3_s3_sx1280pa + +lilygo_t3s3.menu.Revision.Radio_LR1121=Radio-LR1121 +lilygo_t3s3.menu.Revision.Radio_LR1121.build.board=LILYGO_T3S3_LR1121 +lilygo_t3s3.menu.Revision.Radio_LR1121.build.variant=lilygo_t3_s3_lr1121 + +############################################################## + +twatchs3.name=LilyGo T-Watch-S3 + +twatchs3.bootloader.tool=esptool_py +twatchs3.bootloader.tool.default=esptool_py + +twatchs3.upload.tool=esptool_py +twatchs3.upload.tool.default=esptool_py +twatchs3.upload.tool.network=esp_ota + +twatchs3.upload.maximum_size=1310720 +twatchs3.upload.maximum_data_size=327680 +twatchs3.upload.flags= +twatchs3.upload.extra_flags= +twatchs3.upload.use_1200bps_touch=false +twatchs3.upload.wait_for_upload_port=false + +twatchs3.serial.disableDTR=false +twatchs3.serial.disableRTS=false + +twatchs3.build.tarch=xtensa +twatchs3.build.bootloader_addr=0x0 +twatchs3.build.target=esp32s3 +twatchs3.build.mcu=esp32s3 +twatchs3.build.core=esp32 +twatchs3.build.variant=lilygo_twatch_s3 +twatchs3.build.board=T_WATCH_S3 + +twatchs3.build.usb_mode=1 +twatchs3.build.cdc_on_boot=0 +twatchs3.build.msc_on_boot=0 +twatchs3.build.dfu_on_boot=0 +twatchs3.build.f_cpu=240000000L +twatchs3.build.flash_size=16MB +twatchs3.build.flash_freq=80m +twatchs3.build.flash_mode=dio +twatchs3.build.boot=qio +twatchs3.build.boot_freq=80m +twatchs3.build.partitions=app3M_fat9M_16MB +twatchs3.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_WATCH_S3 +twatchs3.build.loop_core= +twatchs3.build.event_core= +twatchs3.build.psram_type=opi +twatchs3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +twatchs3.menu.JTAGAdapter.default=Disabled +twatchs3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +twatchs3.menu.JTAGAdapter.builtin=Integrated USB JTAG +twatchs3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +twatchs3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +twatchs3.menu.LoopCore.1=Core 1 +twatchs3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +twatchs3.menu.LoopCore.0=Core 0 +twatchs3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +twatchs3.menu.EventsCore.1=Core 1 +twatchs3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +twatchs3.menu.EventsCore.0=Core 0 +twatchs3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +twatchs3.menu.USBMode.hwcdc=Hardware CDC and JTAG +twatchs3.menu.USBMode.hwcdc.build.usb_mode=1 +twatchs3.menu.USBMode.default=USB-OTG (TinyUSB) +twatchs3.menu.USBMode.default.build.usb_mode=0 + +twatchs3.menu.CDCOnBoot.default=Enabled +twatchs3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +twatchs3.menu.CDCOnBoot.cdc=Disabled +twatchs3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +twatchs3.menu.MSCOnBoot.default=Disabled +twatchs3.menu.MSCOnBoot.default.build.msc_on_boot=0 +twatchs3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +twatchs3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +twatchs3.menu.DFUOnBoot.default=Disabled +twatchs3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +twatchs3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +twatchs3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +twatchs3.menu.UploadMode.default=UART0 / Hardware CDC +twatchs3.menu.UploadMode.default.upload.use_1200bps_touch=false +twatchs3.menu.UploadMode.default.upload.wait_for_upload_port=false +twatchs3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +twatchs3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +twatchs3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +twatchs3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +twatchs3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +twatchs3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +twatchs3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +twatchs3.menu.PartitionScheme.fatflash.build.partitions=ffat +twatchs3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +twatchs3.menu.PartitionScheme.rainmaker=RainMaker +twatchs3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +twatchs3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +twatchs3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +twatchs3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +twatchs3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +twatchs3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +twatchs3.menu.PartitionScheme.custom=Custom +twatchs3.menu.PartitionScheme.custom.build.partitions= +twatchs3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +twatchs3.menu.CPUFreq.240=240MHz (WiFi) +twatchs3.menu.CPUFreq.240.build.f_cpu=240000000L +twatchs3.menu.CPUFreq.160=160MHz (WiFi) +twatchs3.menu.CPUFreq.160.build.f_cpu=160000000L +twatchs3.menu.CPUFreq.80=80MHz (WiFi) +twatchs3.menu.CPUFreq.80.build.f_cpu=80000000L +twatchs3.menu.CPUFreq.40=40MHz +twatchs3.menu.CPUFreq.40.build.f_cpu=40000000L +twatchs3.menu.CPUFreq.20=20MHz +twatchs3.menu.CPUFreq.20.build.f_cpu=20000000L +twatchs3.menu.CPUFreq.10=10MHz +twatchs3.menu.CPUFreq.10.build.f_cpu=10000000L + +twatchs3.menu.UploadSpeed.921600=921600 +twatchs3.menu.UploadSpeed.921600.upload.speed=921600 +twatchs3.menu.UploadSpeed.115200=115200 +twatchs3.menu.UploadSpeed.115200.upload.speed=115200 +twatchs3.menu.UploadSpeed.256000.windows=256000 +twatchs3.menu.UploadSpeed.256000.upload.speed=256000 +twatchs3.menu.UploadSpeed.230400.windows.upload.speed=256000 +twatchs3.menu.UploadSpeed.230400=230400 +twatchs3.menu.UploadSpeed.230400.upload.speed=230400 +twatchs3.menu.UploadSpeed.460800.linux=460800 +twatchs3.menu.UploadSpeed.460800.macosx=460800 +twatchs3.menu.UploadSpeed.460800.upload.speed=460800 +twatchs3.menu.UploadSpeed.512000.windows=512000 +twatchs3.menu.UploadSpeed.512000.upload.speed=512000 + +twatchs3.menu.DebugLevel.none=None +twatchs3.menu.DebugLevel.none.build.code_debug=0 +twatchs3.menu.DebugLevel.error=Error +twatchs3.menu.DebugLevel.error.build.code_debug=1 +twatchs3.menu.DebugLevel.warn=Warn +twatchs3.menu.DebugLevel.warn.build.code_debug=2 +twatchs3.menu.DebugLevel.info=Info +twatchs3.menu.DebugLevel.info.build.code_debug=3 +twatchs3.menu.DebugLevel.debug=Debug +twatchs3.menu.DebugLevel.debug.build.code_debug=4 +twatchs3.menu.DebugLevel.verbose=Verbose +twatchs3.menu.DebugLevel.verbose.build.code_debug=5 + +twatchs3.menu.EraseFlash.none=Disabled +twatchs3.menu.EraseFlash.none.upload.erase_cmd= +twatchs3.menu.EraseFlash.all=Enabled +twatchs3.menu.EraseFlash.all.upload.erase_cmd=-e + +twatchs3.menu.Revision.Radio_SX1262=Radio-SX1262 +twatchs3.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262 +twatchs3.menu.Revision.Radio_SX1280=Radio-SX1280 +twatchs3.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280 +twatchs3.menu.Revision.Radio_CC1101=Radio-CC1101 +twatchs3.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101 +twatchs3.menu.Revision.Radio_LR1121=Radio-LR1121 +twatchs3.menu.Revision.Radio_LR1121.build.board=LILYGO_LORA_LR1121 +twatchs3.menu.Revision.Radio_SI4432=Radio-SI4432 +twatchs3.menu.Revision.Radio_SI4432.build.board=LILYGO_LORA_SI4432 + +############################################################## + + +twatch_ultra.name=LilyGo T-Watch-Ultra + +twatch_ultra.bootloader.tool=esptool_py +twatch_ultra.bootloader.tool.default=esptool_py + +twatch_ultra.upload.tool=esptool_py +twatch_ultra.upload.tool.default=esptool_py +twatch_ultra.upload.tool.network=esp_ota + +twatch_ultra.upload.maximum_size=1310720 +twatch_ultra.upload.maximum_data_size=327680 +twatch_ultra.upload.flags= +twatch_ultra.upload.extra_flags= +twatch_ultra.upload.use_1200bps_touch=false +twatch_ultra.upload.wait_for_upload_port=false + +twatch_ultra.serial.disableDTR=false +twatch_ultra.serial.disableRTS=false + +twatch_ultra.build.tarch=xtensa +twatch_ultra.build.bootloader_addr=0x0 +twatch_ultra.build.target=esp32s3 +twatch_ultra.build.mcu=esp32s3 +twatch_ultra.build.core=esp32 +twatch_ultra.build.variant=lilygo_twatch_ultra +twatch_ultra.build.board=T_WATCH_S3_ULTRA + +twatch_ultra.build.usb_mode=1 +twatch_ultra.build.cdc_on_boot=1 +twatch_ultra.build.msc_on_boot=0 +twatch_ultra.build.dfu_on_boot=0 +twatch_ultra.build.f_cpu=240000000L +twatch_ultra.build.flash_size=16MB +twatch_ultra.build.flash_freq=80m +twatch_ultra.build.flash_mode=dio +twatch_ultra.build.boot=qio +twatch_ultra.build.boot_freq=80m +twatch_ultra.build.partitions=app3M_fat9M_16MB +twatch_ultra.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_WATCH_S3_ULTRA +twatch_ultra.build.loop_core= +twatch_ultra.build.event_core= +twatch_ultra.build.psram_type=qspi +twatch_ultra.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +twatch_ultra.menu.JTAGAdapter.default=Disabled +twatch_ultra.menu.JTAGAdapter.default.build.copy_jtag_files=0 +twatch_ultra.menu.JTAGAdapter.builtin=Integrated USB JTAG +twatch_ultra.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +twatch_ultra.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +twatch_ultra.menu.LoopCore.1=Core 1 +twatch_ultra.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +twatch_ultra.menu.LoopCore.0=Core 0 +twatch_ultra.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +twatch_ultra.menu.EventsCore.1=Core 1 +twatch_ultra.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +twatch_ultra.menu.EventsCore.0=Core 0 +twatch_ultra.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +twatch_ultra.menu.USBMode.hwcdc=Hardware CDC and JTAG +twatch_ultra.menu.USBMode.hwcdc.build.usb_mode=1 +twatch_ultra.menu.USBMode.default=USB-OTG (TinyUSB) +twatch_ultra.menu.USBMode.default.build.usb_mode=0 + +twatch_ultra.menu.CDCOnBoot.default=Enabled +twatch_ultra.menu.CDCOnBoot.default.build.cdc_on_boot=1 +twatch_ultra.menu.CDCOnBoot.cdc=Disabled +twatch_ultra.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +twatch_ultra.menu.MSCOnBoot.default=Disabled +twatch_ultra.menu.MSCOnBoot.default.build.msc_on_boot=0 +twatch_ultra.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +twatch_ultra.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +twatch_ultra.menu.DFUOnBoot.default=Disabled +twatch_ultra.menu.DFUOnBoot.default.build.dfu_on_boot=0 +twatch_ultra.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +twatch_ultra.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +twatch_ultra.menu.UploadMode.default=UART0 / Hardware CDC +twatch_ultra.menu.UploadMode.default.upload.use_1200bps_touch=false +twatch_ultra.menu.UploadMode.default.upload.wait_for_upload_port=false +twatch_ultra.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +twatch_ultra.menu.UploadMode.cdc.upload.use_1200bps_touch=true +twatch_ultra.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +twatch_ultra.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +twatch_ultra.menu.PartitionScheme.fatflash.build.partitions=ffat +twatch_ultra.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +twatch_ultra.menu.PartitionScheme.rainmaker=RainMaker +twatch_ultra.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +twatch_ultra.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +twatch_ultra.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +twatch_ultra.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +twatch_ultra.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +twatch_ultra.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +twatch_ultra.menu.PartitionScheme.custom=Custom +twatch_ultra.menu.PartitionScheme.custom.build.partitions= +twatch_ultra.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +twatch_ultra.menu.CPUFreq.240=240MHz (WiFi) +twatch_ultra.menu.CPUFreq.240.build.f_cpu=240000000L +twatch_ultra.menu.CPUFreq.160=160MHz (WiFi) +twatch_ultra.menu.CPUFreq.160.build.f_cpu=160000000L +twatch_ultra.menu.CPUFreq.80=80MHz (WiFi) +twatch_ultra.menu.CPUFreq.80.build.f_cpu=80000000L +twatch_ultra.menu.CPUFreq.40=40MHz +twatch_ultra.menu.CPUFreq.40.build.f_cpu=40000000L +twatch_ultra.menu.CPUFreq.20=20MHz +twatch_ultra.menu.CPUFreq.20.build.f_cpu=20000000L +twatch_ultra.menu.CPUFreq.10=10MHz +twatch_ultra.menu.CPUFreq.10.build.f_cpu=10000000L + +twatch_ultra.menu.UploadSpeed.921600=921600 +twatch_ultra.menu.UploadSpeed.921600.upload.speed=921600 +twatch_ultra.menu.UploadSpeed.115200=115200 +twatch_ultra.menu.UploadSpeed.115200.upload.speed=115200 +twatch_ultra.menu.UploadSpeed.256000.windows=256000 +twatch_ultra.menu.UploadSpeed.256000.upload.speed=256000 +twatch_ultra.menu.UploadSpeed.230400.windows.upload.speed=256000 +twatch_ultra.menu.UploadSpeed.230400=230400 +twatch_ultra.menu.UploadSpeed.230400.upload.speed=230400 +twatch_ultra.menu.UploadSpeed.460800.linux=460800 +twatch_ultra.menu.UploadSpeed.460800.macosx=460800 +twatch_ultra.menu.UploadSpeed.460800.upload.speed=460800 +twatch_ultra.menu.UploadSpeed.512000.windows=512000 +twatch_ultra.menu.UploadSpeed.512000.upload.speed=512000 + +twatch_ultra.menu.DebugLevel.none=None +twatch_ultra.menu.DebugLevel.none.build.code_debug=0 +twatch_ultra.menu.DebugLevel.error=Error +twatch_ultra.menu.DebugLevel.error.build.code_debug=1 +twatch_ultra.menu.DebugLevel.warn=Warn +twatch_ultra.menu.DebugLevel.warn.build.code_debug=2 +twatch_ultra.menu.DebugLevel.info=Info +twatch_ultra.menu.DebugLevel.info.build.code_debug=3 +twatch_ultra.menu.DebugLevel.debug=Debug +twatch_ultra.menu.DebugLevel.debug.build.code_debug=4 +twatch_ultra.menu.DebugLevel.verbose=Verbose +twatch_ultra.menu.DebugLevel.verbose.build.code_debug=5 + +twatch_ultra.menu.EraseFlash.none=Disabled +twatch_ultra.menu.EraseFlash.none.upload.erase_cmd= +twatch_ultra.menu.EraseFlash.all=Enabled +twatch_ultra.menu.EraseFlash.all.upload.erase_cmd=-e + +twatch_ultra.menu.Revision.Radio_SX1262=Radio-SX1262 +twatch_ultra.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262 +twatch_ultra.menu.Revision.Radio_SX1280=Radio-SX1280 +twatch_ultra.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280 +twatch_ultra.menu.Revision.Radio_CC1101=Radio-CC1101 +twatch_ultra.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101 +twatch_ultra.menu.Revision.Radio_LR1121=Radio-LR1121 +twatch_ultra.menu.Revision.Radio_LR1121.build.board=LILYGO_LORA_LR1121 +twatch_ultra.menu.Revision.Radio_SI4432=Radio-SI4432 +twatch_ultra.menu.Revision.Radio_SI4432.build.board=LILYGO_LORA_SI4432 + +############################################################## + +tlora_pager.name=LilyGo-T-LoRa-Pager + +tlora_pager.bootloader.tool=esptool_py +tlora_pager.bootloader.tool.default=esptool_py + +tlora_pager.upload.tool=esptool_py +tlora_pager.upload.tool.default=esptool_py +tlora_pager.upload.tool.network=esp_ota + +tlora_pager.upload.maximum_size=1310720 +tlora_pager.upload.maximum_data_size=327680 +tlora_pager.upload.flags= +tlora_pager.upload.extra_flags= +tlora_pager.upload.use_1200bps_touch=false +tlora_pager.upload.wait_for_upload_port=false + +tlora_pager.serial.disableDTR=false +tlora_pager.serial.disableRTS=false + +tlora_pager.build.tarch=xtensa +tlora_pager.build.bootloader_addr=0x0 +tlora_pager.build.target=esp32s3 +tlora_pager.build.mcu=esp32s3 +tlora_pager.build.core=esp32 +tlora_pager.build.variant=lilygo_tlora_pager +tlora_pager.build.board=T_LORA_PAGER + +tlora_pager.build.usb_mode=1 +tlora_pager.build.cdc_on_boot=1 +tlora_pager.build.msc_on_boot=0 +tlora_pager.build.dfu_on_boot=0 +tlora_pager.build.f_cpu=240000000L +tlora_pager.build.flash_size=16MB +tlora_pager.build.flash_freq=80m +tlora_pager.build.flash_mode=dio +tlora_pager.build.boot=qio +tlora_pager.build.boot_freq=80m +tlora_pager.build.partitions=app3M_fat9M_16MB +tlora_pager.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_LORA_PAGER +tlora_pager.build.loop_core= +tlora_pager.build.event_core= +tlora_pager.build.psram_type=qspi +tlora_pager.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +tlora_pager.menu.JTAGAdapter.default=Disabled +tlora_pager.menu.JTAGAdapter.default.build.copy_jtag_files=0 +tlora_pager.menu.JTAGAdapter.builtin=Integrated USB JTAG +tlora_pager.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +tlora_pager.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +tlora_pager.menu.LoopCore.1=Core 1 +tlora_pager.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +tlora_pager.menu.LoopCore.0=Core 0 +tlora_pager.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +tlora_pager.menu.EventsCore.1=Core 1 +tlora_pager.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +tlora_pager.menu.EventsCore.0=Core 0 +tlora_pager.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +tlora_pager.menu.USBMode.hwcdc=Hardware CDC and JTAG +tlora_pager.menu.USBMode.hwcdc.build.usb_mode=1 +tlora_pager.menu.USBMode.default=USB-OTG (TinyUSB) +tlora_pager.menu.USBMode.default.build.usb_mode=0 + +tlora_pager.menu.CDCOnBoot.default=Enabled +tlora_pager.menu.CDCOnBoot.default.build.cdc_on_boot=1 +tlora_pager.menu.CDCOnBoot.cdc=Disabled +tlora_pager.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +tlora_pager.menu.MSCOnBoot.default=Disabled +tlora_pager.menu.MSCOnBoot.default.build.msc_on_boot=0 +tlora_pager.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +tlora_pager.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +tlora_pager.menu.DFUOnBoot.default=Disabled +tlora_pager.menu.DFUOnBoot.default.build.dfu_on_boot=0 +tlora_pager.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +tlora_pager.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +tlora_pager.menu.UploadMode.default=UART0 / Hardware CDC +tlora_pager.menu.UploadMode.default.upload.use_1200bps_touch=false +tlora_pager.menu.UploadMode.default.upload.wait_for_upload_port=false +tlora_pager.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +tlora_pager.menu.UploadMode.cdc.upload.use_1200bps_touch=true +tlora_pager.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +tlora_pager.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +tlora_pager.menu.PartitionScheme.fatflash.build.partitions=ffat +tlora_pager.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +tlora_pager.menu.PartitionScheme.rainmaker=RainMaker +tlora_pager.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +tlora_pager.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728 +tlora_pager.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +tlora_pager.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +tlora_pager.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +tlora_pager.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +tlora_pager.menu.PartitionScheme.custom=Custom +tlora_pager.menu.PartitionScheme.custom.build.partitions= +tlora_pager.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +tlora_pager.menu.CPUFreq.240=240MHz (WiFi) +tlora_pager.menu.CPUFreq.240.build.f_cpu=240000000L +tlora_pager.menu.CPUFreq.160=160MHz (WiFi) +tlora_pager.menu.CPUFreq.160.build.f_cpu=160000000L +tlora_pager.menu.CPUFreq.80=80MHz (WiFi) +tlora_pager.menu.CPUFreq.80.build.f_cpu=80000000L +tlora_pager.menu.CPUFreq.40=40MHz +tlora_pager.menu.CPUFreq.40.build.f_cpu=40000000L +tlora_pager.menu.CPUFreq.20=20MHz +tlora_pager.menu.CPUFreq.20.build.f_cpu=20000000L +tlora_pager.menu.CPUFreq.10=10MHz +tlora_pager.menu.CPUFreq.10.build.f_cpu=10000000L + +tlora_pager.menu.UploadSpeed.921600=921600 +tlora_pager.menu.UploadSpeed.921600.upload.speed=921600 +tlora_pager.menu.UploadSpeed.115200=115200 +tlora_pager.menu.UploadSpeed.115200.upload.speed=115200 +tlora_pager.menu.UploadSpeed.256000.windows=256000 +tlora_pager.menu.UploadSpeed.256000.upload.speed=256000 +tlora_pager.menu.UploadSpeed.230400.windows.upload.speed=256000 +tlora_pager.menu.UploadSpeed.230400=230400 +tlora_pager.menu.UploadSpeed.230400.upload.speed=230400 +tlora_pager.menu.UploadSpeed.460800.linux=460800 +tlora_pager.menu.UploadSpeed.460800.macosx=460800 +tlora_pager.menu.UploadSpeed.460800.upload.speed=460800 +tlora_pager.menu.UploadSpeed.512000.windows=512000 +tlora_pager.menu.UploadSpeed.512000.upload.speed=512000 + +tlora_pager.menu.DebugLevel.none=None +tlora_pager.menu.DebugLevel.none.build.code_debug=0 +tlora_pager.menu.DebugLevel.error=Error +tlora_pager.menu.DebugLevel.error.build.code_debug=1 +tlora_pager.menu.DebugLevel.warn=Warn +tlora_pager.menu.DebugLevel.warn.build.code_debug=2 +tlora_pager.menu.DebugLevel.info=Info +tlora_pager.menu.DebugLevel.info.build.code_debug=3 +tlora_pager.menu.DebugLevel.debug=Debug +tlora_pager.menu.DebugLevel.debug.build.code_debug=4 +tlora_pager.menu.DebugLevel.verbose=Verbose +tlora_pager.menu.DebugLevel.verbose.build.code_debug=5 + +tlora_pager.menu.EraseFlash.none=Disabled +tlora_pager.menu.EraseFlash.none.upload.erase_cmd= +tlora_pager.menu.EraseFlash.all=Enabled +tlora_pager.menu.EraseFlash.all.upload.erase_cmd=-e + + +tlora_pager.menu.Revision.Radio_SX1262=Radio-SX1262 +tlora_pager.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262 +tlora_pager.menu.Revision.Radio_SX1280=Radio-SX1280 +tlora_pager.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280 +tlora_pager.menu.Revision.Radio_CC1101=Radio-CC1101 +tlora_pager.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101 +tlora_pager.menu.Revision.Radio_LR1121=Radio-LR1121 +tlora_pager.menu.Revision.Radio_LR1121.build.board=LILYGO_LORA_LR1121 +tlora_pager.menu.Revision.Radio_SI4432=Radio-SI4432 +tlora_pager.menu.Revision.Radio_SI4432.build.board=LILYGO_LORA_SI4432 + +############################################################## + +micros2.name=microS2 +micros2.vid.0=0x239A +micros2.pid.0=0x80C5 + +micros2.bootloader.tool=esptool_py +micros2.bootloader.tool.default=esptool_py + +micros2.upload.tool=esptool_py +micros2.upload.tool.default=esptool_py +micros2.upload.tool.network=esp_ota + +micros2.upload.maximum_size=1310720 +micros2.upload.maximum_data_size=327680 +micros2.upload.flags= +micros2.upload.extra_flags= +micros2.upload.use_1200bps_touch=true +micros2.upload.wait_for_upload_port=true + +micros2.serial.disableDTR=false +micros2.serial.disableRTS=false + +micros2.build.tarch=xtensa +micros2.build.bootloader_addr=0x1000 +micros2.build.target=esp32s2 +micros2.build.mcu=esp32s2 +micros2.build.core=esp32 +micros2.build.variant=micro_s2 +micros2.build.board=MICROS2 + +micros2.build.cdc_on_boot=1 +micros2.build.msc_on_boot=1 +micros2.build.dfu_on_boot=0 +micros2.build.f_cpu=240000000L +micros2.build.flash_size=16MB +micros2.build.flash_freq=80m +micros2.build.flash_mode=dio +micros2.build.boot=qio +micros2.build.partitions=fatflash +micros2.build.defines= + +micros2.menu.CDCOnBoot.cdc=Enabled +micros2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +micros2.menu.CDCOnBoot.default=Disabled +micros2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +micros2.menu.MSCOnBoot.msc=Enabled +micros2.menu.MSCOnBoot.msc.build.msc_on_boot=1 +micros2.menu.MSCOnBoot.default=Disabled +micros2.menu.MSCOnBoot.default.build.msc_on_boot=0 + +micros2.menu.DFUOnBoot.default=Disabled +micros2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +micros2.menu.DFUOnBoot.dfu=Enabled +micros2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +micros2.menu.PSRAM.enabled=Enabled +micros2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +micros2.menu.PSRAM.disabled=Disabled +micros2.menu.PSRAM.disabled.build.defines= + +micros2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +micros2.menu.PartitionScheme.fatflash.build.partitions=ffat +micros2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +micros2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +micros2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +micros2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +micros2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +micros2.menu.PartitionScheme.default.build.partitions=default +micros2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +micros2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +micros2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +micros2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +micros2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +micros2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +micros2.menu.PartitionScheme.minimal.build.partitions=minimal +micros2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +micros2.menu.PartitionScheme.no_ota.build.partitions=no_ota +micros2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +micros2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +micros2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +micros2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +micros2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +micros2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +micros2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +micros2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +micros2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +micros2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +micros2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +micros2.menu.PartitionScheme.huge_app.build.partitions=huge_app +micros2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +micros2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +micros2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +micros2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +micros2.menu.CPUFreq.240=240MHz (WiFi) +micros2.menu.CPUFreq.240.build.f_cpu=240000000L +micros2.menu.CPUFreq.160=160MHz (WiFi) +micros2.menu.CPUFreq.160.build.f_cpu=160000000L +micros2.menu.CPUFreq.80=80MHz (WiFi) +micros2.menu.CPUFreq.80.build.f_cpu=80000000L +micros2.menu.CPUFreq.40=40MHz +micros2.menu.CPUFreq.40.build.f_cpu=40000000L +micros2.menu.CPUFreq.20=20MHz +micros2.menu.CPUFreq.20.build.f_cpu=20000000L +micros2.menu.CPUFreq.10=10MHz +micros2.menu.CPUFreq.10.build.f_cpu=10000000L + +micros2.menu.FlashSize.16M=16MB (128Mb) +micros2.menu.FlashSize.16M.build.flash_size=16MB +micros2.menu.FlashSize.4M=4MB (32Mb) +micros2.menu.FlashSize.4M.build.flash_size=4MB +micros2.menu.FlashSize.8M=8MB (64Mb) +micros2.menu.FlashSize.8M.build.flash_size=8MB +micros2.menu.FlashSize.2M=2MB (16Mb) +micros2.menu.FlashSize.2M.build.flash_size=2MB + +micros2.menu.UploadSpeed.921600=921600 +micros2.menu.UploadSpeed.921600.upload.speed=921600 +micros2.menu.UploadSpeed.115200=115200 +micros2.menu.UploadSpeed.115200.upload.speed=115200 +micros2.menu.UploadSpeed.256000.windows=256000 +micros2.menu.UploadSpeed.256000.upload.speed=256000 +micros2.menu.UploadSpeed.230400.windows.upload.speed=256000 +micros2.menu.UploadSpeed.230400=230400 +micros2.menu.UploadSpeed.230400.upload.speed=230400 +micros2.menu.UploadSpeed.460800.linux=460800 +micros2.menu.UploadSpeed.460800.macosx=460800 +micros2.menu.UploadSpeed.460800.upload.speed=460800 + +micros2.menu.DebugLevel.none=None +micros2.menu.DebugLevel.none.build.code_debug=0 +micros2.menu.DebugLevel.error=Error +micros2.menu.DebugLevel.error.build.code_debug=1 +micros2.menu.DebugLevel.warn=Warn +micros2.menu.DebugLevel.warn.build.code_debug=2 +micros2.menu.DebugLevel.info=Info +micros2.menu.DebugLevel.info.build.code_debug=3 +micros2.menu.DebugLevel.debug=Debug +micros2.menu.DebugLevel.debug.build.code_debug=4 +micros2.menu.DebugLevel.verbose=Verbose +micros2.menu.DebugLevel.verbose.build.code_debug=5 + +micros2.menu.EraseFlash.none=Disabled +micros2.menu.EraseFlash.none.upload.erase_cmd= +micros2.menu.EraseFlash.all=Enabled +micros2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +magicbit.name=MagicBit + +magicbit.bootloader.tool=esptool_py +magicbit.bootloader.tool.default=esptool_py + +magicbit.upload.tool=esptool_py +magicbit.upload.tool.default=esptool_py +magicbit.upload.tool.network=esp_ota + +magicbit.upload.maximum_size=1310720 +magicbit.upload.maximum_data_size=327680 +magicbit.upload.flags= +magicbit.upload.extra_flags= + +magicbit.serial.disableDTR=true +magicbit.serial.disableRTS=true + +magicbit.build.tarch=xtensa +magicbit.build.bootloader_addr=0x1000 +magicbit.build.target=esp32 +magicbit.build.mcu=esp32 +magicbit.build.core=esp32 +magicbit.build.variant=magicbit +magicbit.build.board=ESP32_DEV + +magicbit.build.f_cpu=240000000L +magicbit.build.flash_size=4MB +magicbit.build.flash_freq=40m +magicbit.build.flash_mode=dio +magicbit.build.boot=dio +magicbit.build.partitions=default + +magicbit.menu.CPUFreq.240=240MHz (WiFi/BT) +magicbit.menu.CPUFreq.240.build.f_cpu=240000000L +magicbit.menu.CPUFreq.160=160MHz (WiFi/BT) +magicbit.menu.CPUFreq.160.build.f_cpu=160000000L +magicbit.menu.CPUFreq.80=80MHz (WiFi/BT) +magicbit.menu.CPUFreq.80.build.f_cpu=80000000L +magicbit.menu.CPUFreq.40=40MHz (40MHz XTAL) + +magicbit.menu.UploadSpeed.921600=921600 +magicbit.menu.UploadSpeed.921600.upload.speed=921600 +magicbit.menu.UploadSpeed.115200=115200 +magicbit.menu.UploadSpeed.115200.upload.speed=115200 + +magicbit.menu.DebugLevel.none=None +magicbit.menu.DebugLevel.none.build.code_debug=0 +magicbit.menu.DebugLevel.error=Error +magicbit.menu.DebugLevel.error.build.code_debug=1 +magicbit.menu.DebugLevel.warn=Warn +magicbit.menu.DebugLevel.warn.build.code_debug=2 +magicbit.menu.DebugLevel.info=Info +magicbit.menu.DebugLevel.info.build.code_debug=3 +magicbit.menu.DebugLevel.debug=Debug +magicbit.menu.DebugLevel.debug.build.code_debug=4 +magicbit.menu.DebugLevel.verbose=Verbose +magicbit.menu.DebugLevel.verbose.build.code_debug=5 + +magicbit.menu.EraseFlash.none=Disabled +magicbit.menu.EraseFlash.none.upload.erase_cmd= +magicbit.menu.EraseFlash.all=Enabled +magicbit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +turta_iot_node.name=Turta IoT Node + +turta_iot_node.bootloader.tool=esptool_py +turta_iot_node.bootloader.tool.default=esptool_py + +turta_iot_node.upload.tool=esptool_py +turta_iot_node.upload.tool.default=esptool_py +turta_iot_node.upload.tool.network=esp_ota + +turta_iot_node.upload.maximum_size=1310720 +turta_iot_node.upload.maximum_data_size=327680 +turta_iot_node.upload.flags= +turta_iot_node.upload.extra_flags= + +turta_iot_node.serial.disableDTR=true +turta_iot_node.serial.disableRTS=true + +turta_iot_node.build.tarch=xtensa +turta_iot_node.build.bootloader_addr=0x1000 +turta_iot_node.build.target=esp32 +turta_iot_node.build.mcu=esp32 +turta_iot_node.build.core=esp32 +turta_iot_node.build.variant=pico32 +turta_iot_node.build.board=ESP32_PICO + +turta_iot_node.build.f_cpu=240000000L +turta_iot_node.build.flash_size=4MB +turta_iot_node.build.flash_freq=80m +turta_iot_node.build.flash_mode=dio +turta_iot_node.build.boot=dio +turta_iot_node.build.partitions=default +turta_iot_node.build.defines= + +turta_iot_node.menu.UploadSpeed.921600=921600 +turta_iot_node.menu.UploadSpeed.921600.upload.speed=921600 +turta_iot_node.menu.UploadSpeed.115200=115200 +turta_iot_node.menu.UploadSpeed.115200.upload.speed=115200 + +turta_iot_node.menu.DebugLevel.none=None +turta_iot_node.menu.DebugLevel.none.build.code_debug=0 +turta_iot_node.menu.DebugLevel.error=Error +turta_iot_node.menu.DebugLevel.error.build.code_debug=1 +turta_iot_node.menu.DebugLevel.warn=Warn +turta_iot_node.menu.DebugLevel.warn.build.code_debug=2 +turta_iot_node.menu.DebugLevel.info=Info +turta_iot_node.menu.DebugLevel.info.build.code_debug=3 +turta_iot_node.menu.DebugLevel.debug=Debug +turta_iot_node.menu.DebugLevel.debug.build.code_debug=4 +turta_iot_node.menu.DebugLevel.verbose=Verbose +turta_iot_node.menu.DebugLevel.verbose.build.code_debug=5 + +turta_iot_node.menu.EraseFlash.none=Disabled +turta_iot_node.menu.EraseFlash.none.upload.erase_cmd= +turta_iot_node.menu.EraseFlash.all=Enabled +turta_iot_node.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ttgo-lora32.name=TTGO LoRa32-OLED + +ttgo-lora32.bootloader.tool=esptool_py +ttgo-lora32.bootloader.tool.default=esptool_py + +ttgo-lora32.upload.tool=esptool_py +ttgo-lora32.upload.tool.default=esptool_py +ttgo-lora32.upload.tool.network=esp_ota + +ttgo-lora32.upload.maximum_size=1310720 +ttgo-lora32.upload.maximum_data_size=294912 +ttgo-lora32.upload.flags= +ttgo-lora32.upload.extra_flags= + +ttgo-lora32.serial.disableDTR=true +ttgo-lora32.serial.disableRTS=true + +ttgo-lora32.build.tarch=xtensa +ttgo-lora32.build.bootloader_addr=0x1000 +ttgo-lora32.build.target=esp32 +ttgo-lora32.build.mcu=esp32 +ttgo-lora32.build.core=esp32 +ttgo-lora32.build.board=TTGO_LoRa32 + +ttgo-lora32.menu.Revision.TTGO_LoRa32_V1=TTGO LoRa32 V1 (No TFCard) +ttgo-lora32.menu.Revision.TTGO_LoRa32_V1.build.board=TTGO_LoRa32_V1 +ttgo-lora32.menu.Revision.TTGO_LoRa32_V1.build.variant=ttgo-lora32-v1 + +ttgo-lora32.menu.Revision.TTGO_LoRa32_V2=TTGO LoRa32 V2 +ttgo-lora32.menu.Revision.TTGO_LoRa32_V2.build.board=TTGO_LoRa32_V2 +ttgo-lora32.menu.Revision.TTGO_LoRa32_V2.build.variant=ttgo-lora32-v2 + +ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new=TTGO LoRa32 V2.1 (1.6.1) +ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new.build.board=TTGO_LoRa32_v21new +ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new.build.variant=ttgo-lora32-v21new + +ttgo-lora32.build.f_cpu=240000000L +ttgo-lora32.build.flash_mode=dio +ttgo-lora32.build.flash_size=4MB +ttgo-lora32.build.boot=dio +ttgo-lora32.build.partitions=default + +ttgo-lora32.menu.FlashFreq.80=80MHz +ttgo-lora32.menu.FlashFreq.80.build.flash_freq=80m +ttgo-lora32.menu.FlashFreq.40=40MHz +ttgo-lora32.menu.FlashFreq.40.build.flash_freq=40m + +ttgo-lora32.menu.UploadSpeed.921600=921600 +ttgo-lora32.menu.UploadSpeed.921600.upload.speed=921600 +ttgo-lora32.menu.UploadSpeed.115200=115200 +ttgo-lora32.menu.UploadSpeed.115200.upload.speed=115200 +ttgo-lora32.menu.UploadSpeed.256000.windows=256000 +ttgo-lora32.menu.UploadSpeed.256000.upload.speed=256000 +ttgo-lora32.menu.UploadSpeed.230400.windows.upload.speed=256000 +ttgo-lora32.menu.UploadSpeed.230400=230400 +ttgo-lora32.menu.UploadSpeed.230400.upload.speed=230400 +ttgo-lora32.menu.UploadSpeed.460800.linux=460800 +ttgo-lora32.menu.UploadSpeed.460800.macosx=460800 +ttgo-lora32.menu.UploadSpeed.460800.upload.speed=460800 +ttgo-lora32.menu.UploadSpeed.512000.windows=512000 +ttgo-lora32.menu.UploadSpeed.512000.upload.speed=512000 + +ttgo-lora32.menu.DebugLevel.none=None +ttgo-lora32.menu.DebugLevel.none.build.code_debug=0 +ttgo-lora32.menu.DebugLevel.error=Error +ttgo-lora32.menu.DebugLevel.error.build.code_debug=1 +ttgo-lora32.menu.DebugLevel.warn=Warn +ttgo-lora32.menu.DebugLevel.warn.build.code_debug=2 +ttgo-lora32.menu.DebugLevel.info=Info +ttgo-lora32.menu.DebugLevel.info.build.code_debug=3 +ttgo-lora32.menu.DebugLevel.debug=Debug +ttgo-lora32.menu.DebugLevel.debug.build.code_debug=4 +ttgo-lora32.menu.DebugLevel.verbose=Verbose +ttgo-lora32.menu.DebugLevel.verbose.build.code_debug=5 + +ttgo-lora32.menu.EraseFlash.none=Disabled +ttgo-lora32.menu.EraseFlash.none.upload.erase_cmd= +ttgo-lora32.menu.EraseFlash.all=Enabled +ttgo-lora32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ttgo-t1.name=TTGO T1 + +ttgo-t1.bootloader.tool=esptool_py +ttgo-t1.bootloader.tool.default=esptool_py + +ttgo-t1.upload.tool=esptool_py +ttgo-t1.upload.tool.default=esptool_py +ttgo-t1.upload.tool.network=esp_ota + +ttgo-t1.upload.maximum_size=1310720 +ttgo-t1.upload.maximum_data_size=327680 +ttgo-t1.upload.flags= +ttgo-t1.upload.extra_flags= + +ttgo-t1.serial.disableDTR=true +ttgo-t1.serial.disableRTS=true + +ttgo-t1.build.tarch=xtensa +ttgo-t1.build.bootloader_addr=0x1000 +ttgo-t1.build.target=esp32 +ttgo-t1.build.mcu=esp32 +ttgo-t1.build.core=esp32 +ttgo-t1.build.variant=ttgo-t1 +ttgo-t1.build.board=TTGO_T1 + +ttgo-t1.build.f_cpu=240000000L +ttgo-t1.build.flash_size=4MB +ttgo-t1.build.flash_freq=40m +ttgo-t1.build.flash_mode=dio +ttgo-t1.build.boot=dio +ttgo-t1.build.partitions=default +ttgo-t1.build.defines= + +ttgo-t1.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ttgo-t1.menu.PartitionScheme.default.build.partitions=default +ttgo-t1.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ttgo-t1.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ttgo-t1.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ttgo-t1.menu.PartitionScheme.minimal.build.partitions=minimal +ttgo-t1.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ttgo-t1.menu.PartitionScheme.no_ota.build.partitions=no_ota +ttgo-t1.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ttgo-t1.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ttgo-t1.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ttgo-t1.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ttgo-t1.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ttgo-t1.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ttgo-t1.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ttgo-t1.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ttgo-t1.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ttgo-t1.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ttgo-t1.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ttgo-t1.menu.PartitionScheme.huge_app.build.partitions=huge_app +ttgo-t1.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ttgo-t1.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ttgo-t1.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ttgo-t1.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ttgo-t1.menu.CPUFreq.240=240MHz (WiFi/BT) +ttgo-t1.menu.CPUFreq.240.build.f_cpu=240000000L +ttgo-t1.menu.CPUFreq.160=160MHz (WiFi/BT) +ttgo-t1.menu.CPUFreq.160.build.f_cpu=160000000L +ttgo-t1.menu.CPUFreq.80=80MHz (WiFi/BT) +ttgo-t1.menu.CPUFreq.80.build.f_cpu=80000000L +ttgo-t1.menu.CPUFreq.40=40MHz (40MHz XTAL) +ttgo-t1.menu.CPUFreq.40.build.f_cpu=40000000L +ttgo-t1.menu.CPUFreq.26=26MHz (26MHz XTAL) +ttgo-t1.menu.CPUFreq.26.build.f_cpu=26000000L +ttgo-t1.menu.CPUFreq.20=20MHz (40MHz XTAL) +ttgo-t1.menu.CPUFreq.20.build.f_cpu=20000000L +ttgo-t1.menu.CPUFreq.13=13MHz (26MHz XTAL) +ttgo-t1.menu.CPUFreq.13.build.f_cpu=13000000L +ttgo-t1.menu.CPUFreq.10=10MHz (40MHz XTAL) +ttgo-t1.menu.CPUFreq.10.build.f_cpu=10000000L + +ttgo-t1.menu.FlashMode.qio=QIO +ttgo-t1.menu.FlashMode.qio.build.flash_mode=dio +ttgo-t1.menu.FlashMode.qio.build.boot=qio +ttgo-t1.menu.FlashMode.dio=DIO +ttgo-t1.menu.FlashMode.dio.build.flash_mode=dio +ttgo-t1.menu.FlashMode.dio.build.boot=dio + +ttgo-t1.menu.FlashFreq.80=80MHz +ttgo-t1.menu.FlashFreq.80.build.flash_freq=80m +ttgo-t1.menu.FlashFreq.40=40MHz +ttgo-t1.menu.FlashFreq.40.build.flash_freq=40m + +ttgo-t1.menu.FlashSize.4M=4MB (32Mb) +ttgo-t1.menu.FlashSize.4M.build.flash_size=4MB +ttgo-t1.menu.FlashSize.2M=2MB (16Mb) +ttgo-t1.menu.FlashSize.2M.build.flash_size=2MB +ttgo-t1.menu.FlashSize.16M=16MB (128Mb) +ttgo-t1.menu.FlashSize.16M.build.flash_size=16MB + +ttgo-t1.menu.UploadSpeed.921600=921600 +ttgo-t1.menu.UploadSpeed.921600.upload.speed=921600 +ttgo-t1.menu.UploadSpeed.115200=115200 +ttgo-t1.menu.UploadSpeed.115200.upload.speed=115200 +ttgo-t1.menu.UploadSpeed.256000.windows=256000 +ttgo-t1.menu.UploadSpeed.256000.upload.speed=256000 +ttgo-t1.menu.UploadSpeed.230400.windows.upload.speed=256000 +ttgo-t1.menu.UploadSpeed.230400=230400 +ttgo-t1.menu.UploadSpeed.230400.upload.speed=230400 +ttgo-t1.menu.UploadSpeed.460800.linux=460800 +ttgo-t1.menu.UploadSpeed.460800.macosx=460800 +ttgo-t1.menu.UploadSpeed.460800.upload.speed=460800 +ttgo-t1.menu.UploadSpeed.512000.windows=512000 +ttgo-t1.menu.UploadSpeed.512000.upload.speed=512000 + +ttgo-t1.menu.DebugLevel.none=None +ttgo-t1.menu.DebugLevel.none.build.code_debug=0 +ttgo-t1.menu.DebugLevel.error=Error +ttgo-t1.menu.DebugLevel.error.build.code_debug=1 +ttgo-t1.menu.DebugLevel.warn=Warn +ttgo-t1.menu.DebugLevel.warn.build.code_debug=2 +ttgo-t1.menu.DebugLevel.info=Info +ttgo-t1.menu.DebugLevel.info.build.code_debug=3 +ttgo-t1.menu.DebugLevel.debug=Debug +ttgo-t1.menu.DebugLevel.debug.build.code_debug=4 +ttgo-t1.menu.DebugLevel.verbose=Verbose +ttgo-t1.menu.DebugLevel.verbose.build.code_debug=5 + +ttgo-t1.menu.EraseFlash.none=Disabled +ttgo-t1.menu.EraseFlash.none.upload.erase_cmd= +ttgo-t1.menu.EraseFlash.all=Enabled +ttgo-t1.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ttgo-t7-v13-mini32.name=TTGO T7 V1.3 Mini32 + +ttgo-t7-v13-mini32.bootloader.tool=esptool_py +ttgo-t7-v13-mini32.bootloader.tool.default=esptool_py + +ttgo-t7-v13-mini32.upload.tool=esptool_py +ttgo-t7-v13-mini32.upload.tool.default=esptool_py +ttgo-t7-v13-mini32.upload.tool.network=esp_ota + +ttgo-t7-v13-mini32.upload.maximum_size=1310720 +ttgo-t7-v13-mini32.upload.maximum_data_size=327680 +ttgo-t7-v13-mini32.upload.wait_for_upload_port=true +ttgo-t7-v13-mini32.upload.flags= +ttgo-t7-v13-mini32.upload.extra_flags= + +ttgo-t7-v13-mini32.serial.disableDTR=true +ttgo-t7-v13-mini32.serial.disableRTS=true + +ttgo-t7-v13-mini32.build.tarch=xtensa +ttgo-t7-v13-mini32.build.bootloader_addr=0x1000 +ttgo-t7-v13-mini32.build.target=esp32 +ttgo-t7-v13-mini32.build.mcu=esp32 +ttgo-t7-v13-mini32.build.core=esp32 +ttgo-t7-v13-mini32.build.variant=ttgo-t7-v13-mini32 +ttgo-t7-v13-mini32.build.board=TTGO_T7_V13_Mini32 + +ttgo-t7-v13-mini32.build.f_cpu=240000000L +ttgo-t7-v13-mini32.build.flash_size=4MB +ttgo-t7-v13-mini32.build.flash_freq=40m +ttgo-t7-v13-mini32.build.flash_mode=dio +ttgo-t7-v13-mini32.build.boot=dio +ttgo-t7-v13-mini32.build.partitions=default +ttgo-t7-v13-mini32.build.defines= + +ttgo-t7-v13-mini32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.default.build.partitions=default +ttgo-t7-v13-mini32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ttgo-t7-v13-mini32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.minimal.build.partitions=minimal +ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota.build.partitions=no_ota +ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app.build.partitions=huge_app +ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ttgo-t7-v13-mini32.menu.CPUFreq.240=240MHz (WiFi/BT) +ttgo-t7-v13-mini32.menu.CPUFreq.240.build.f_cpu=240000000L +ttgo-t7-v13-mini32.menu.CPUFreq.160=160MHz (WiFi/BT) +ttgo-t7-v13-mini32.menu.CPUFreq.160.build.f_cpu=160000000L +ttgo-t7-v13-mini32.menu.CPUFreq.80=80MHz (WiFi/BT) +ttgo-t7-v13-mini32.menu.CPUFreq.80.build.f_cpu=80000000L +ttgo-t7-v13-mini32.menu.CPUFreq.40=40MHz (40MHz XTAL) +ttgo-t7-v13-mini32.menu.CPUFreq.40.build.f_cpu=40000000L +ttgo-t7-v13-mini32.menu.CPUFreq.26=26MHz (26MHz XTAL) +ttgo-t7-v13-mini32.menu.CPUFreq.26.build.f_cpu=26000000L +ttgo-t7-v13-mini32.menu.CPUFreq.20=20MHz (40MHz XTAL) +ttgo-t7-v13-mini32.menu.CPUFreq.20.build.f_cpu=20000000L +ttgo-t7-v13-mini32.menu.CPUFreq.13=13MHz (26MHz XTAL) +ttgo-t7-v13-mini32.menu.CPUFreq.13.build.f_cpu=13000000L +ttgo-t7-v13-mini32.menu.CPUFreq.10=10MHz (40MHz XTAL) +ttgo-t7-v13-mini32.menu.CPUFreq.10.build.f_cpu=10000000L + +ttgo-t7-v13-mini32.menu.FlashMode.qio=QIO +ttgo-t7-v13-mini32.menu.FlashMode.qio.build.flash_mode=dio +ttgo-t7-v13-mini32.menu.FlashMode.qio.build.boot=qio +ttgo-t7-v13-mini32.menu.FlashMode.dio=DIO +ttgo-t7-v13-mini32.menu.FlashMode.dio.build.flash_mode=dio +ttgo-t7-v13-mini32.menu.FlashMode.dio.build.boot=dio + +ttgo-t7-v13-mini32.menu.FlashFreq.80=80MHz +ttgo-t7-v13-mini32.menu.FlashFreq.80.build.flash_freq=80m +ttgo-t7-v13-mini32.menu.FlashFreq.40=40MHz +ttgo-t7-v13-mini32.menu.FlashFreq.40.build.flash_freq=40m + +ttgo-t7-v13-mini32.menu.FlashSize.4M=4MB (32Mb) +ttgo-t7-v13-mini32.menu.FlashSize.4M.build.flash_size=4MB + +ttgo-t7-v13-mini32.menu.UploadSpeed.921600=921600 +ttgo-t7-v13-mini32.menu.UploadSpeed.921600.upload.speed=921600 +ttgo-t7-v13-mini32.menu.UploadSpeed.115200=115200 +ttgo-t7-v13-mini32.menu.UploadSpeed.115200.upload.speed=115200 +ttgo-t7-v13-mini32.menu.UploadSpeed.256000.windows=256000 +ttgo-t7-v13-mini32.menu.UploadSpeed.256000.upload.speed=256000 +ttgo-t7-v13-mini32.menu.UploadSpeed.230400.windows.upload.speed=256000 +ttgo-t7-v13-mini32.menu.UploadSpeed.230400=230400 +ttgo-t7-v13-mini32.menu.UploadSpeed.230400.upload.speed=230400 +ttgo-t7-v13-mini32.menu.UploadSpeed.460800.linux=460800 +ttgo-t7-v13-mini32.menu.UploadSpeed.460800.macosx=460800 +ttgo-t7-v13-mini32.menu.UploadSpeed.460800.upload.speed=460800 +ttgo-t7-v13-mini32.menu.UploadSpeed.512000.windows=512000 +ttgo-t7-v13-mini32.menu.UploadSpeed.512000.upload.speed=512000 + +ttgo-t7-v13-mini32.menu.DebugLevel.none=None +ttgo-t7-v13-mini32.menu.DebugLevel.none.build.code_debug=0 +ttgo-t7-v13-mini32.menu.DebugLevel.error=Error +ttgo-t7-v13-mini32.menu.DebugLevel.error.build.code_debug=1 +ttgo-t7-v13-mini32.menu.DebugLevel.warn=Warn +ttgo-t7-v13-mini32.menu.DebugLevel.warn.build.code_debug=2 +ttgo-t7-v13-mini32.menu.DebugLevel.info=Info +ttgo-t7-v13-mini32.menu.DebugLevel.info.build.code_debug=3 +ttgo-t7-v13-mini32.menu.DebugLevel.debug=Debug +ttgo-t7-v13-mini32.menu.DebugLevel.debug.build.code_debug=4 +ttgo-t7-v13-mini32.menu.DebugLevel.verbose=Verbose +ttgo-t7-v13-mini32.menu.DebugLevel.verbose.build.code_debug=5 + +ttgo-t7-v13-mini32.menu.EraseFlash.none=Disabled +ttgo-t7-v13-mini32.menu.EraseFlash.none.upload.erase_cmd= +ttgo-t7-v13-mini32.menu.EraseFlash.all=Enabled +ttgo-t7-v13-mini32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ttgo-t7-v14-mini32.name=TTGO T7 V1.4 Mini32 + +ttgo-t7-v14-mini32.bootloader.tool=esptool_py +ttgo-t7-v14-mini32.bootloader.tool.default=esptool_py + +ttgo-t7-v14-mini32.upload.tool=esptool_py +ttgo-t7-v14-mini32.upload.tool.default=esptool_py +ttgo-t7-v14-mini32.upload.tool.network=esp_ota + +ttgo-t7-v14-mini32.upload.maximum_size=1310720 +ttgo-t7-v14-mini32.upload.maximum_data_size=327680 +ttgo-t7-v14-mini32.upload.wait_for_upload_port=true +ttgo-t7-v14-mini32.upload.flags= +ttgo-t7-v14-mini32.upload.extra_flags= + +ttgo-t7-v14-mini32.serial.disableDTR=true +ttgo-t7-v14-mini32.serial.disableRTS=true + +ttgo-t7-v14-mini32.build.tarch=xtensa +ttgo-t7-v14-mini32.build.bootloader_addr=0x1000 +ttgo-t7-v14-mini32.build.target=esp32 +ttgo-t7-v14-mini32.build.mcu=esp32 +ttgo-t7-v14-mini32.build.core=esp32 +ttgo-t7-v14-mini32.build.variant=ttgo-t7-v14-mini32 +ttgo-t7-v14-mini32.build.board=TTGO_T7_V14_Mini32 + +ttgo-t7-v14-mini32.build.f_cpu=240000000L +ttgo-t7-v14-mini32.build.flash_size=4MB +ttgo-t7-v14-mini32.build.flash_freq=40m +ttgo-t7-v14-mini32.build.flash_mode=dio +ttgo-t7-v14-mini32.build.boot=dio +ttgo-t7-v14-mini32.build.partitions=default +ttgo-t7-v14-mini32.build.defines= + +ttgo-t7-v14-mini32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.default.build.partitions=default +ttgo-t7-v14-mini32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ttgo-t7-v14-mini32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.minimal.build.partitions=minimal +ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota.build.partitions=no_ota +ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app.build.partitions=huge_app +ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ttgo-t7-v14-mini32.menu.CPUFreq.240=240MHz (WiFi/BT) +ttgo-t7-v14-mini32.menu.CPUFreq.240.build.f_cpu=240000000L +ttgo-t7-v14-mini32.menu.CPUFreq.160=160MHz (WiFi/BT) +ttgo-t7-v14-mini32.menu.CPUFreq.160.build.f_cpu=160000000L +ttgo-t7-v14-mini32.menu.CPUFreq.80=80MHz (WiFi/BT) +ttgo-t7-v14-mini32.menu.CPUFreq.80.build.f_cpu=80000000L +ttgo-t7-v14-mini32.menu.CPUFreq.40=40MHz (40MHz XTAL) +ttgo-t7-v14-mini32.menu.CPUFreq.40.build.f_cpu=40000000L +ttgo-t7-v14-mini32.menu.CPUFreq.26=26MHz (26MHz XTAL) +ttgo-t7-v14-mini32.menu.CPUFreq.26.build.f_cpu=26000000L +ttgo-t7-v14-mini32.menu.CPUFreq.20=20MHz (40MHz XTAL) +ttgo-t7-v14-mini32.menu.CPUFreq.20.build.f_cpu=20000000L +ttgo-t7-v14-mini32.menu.CPUFreq.13=13MHz (26MHz XTAL) +ttgo-t7-v14-mini32.menu.CPUFreq.13.build.f_cpu=13000000L +ttgo-t7-v14-mini32.menu.CPUFreq.10=10MHz (40MHz XTAL) +ttgo-t7-v14-mini32.menu.CPUFreq.10.build.f_cpu=10000000L + +ttgo-t7-v14-mini32.menu.FlashMode.qio=QIO +ttgo-t7-v14-mini32.menu.FlashMode.qio.build.flash_mode=dio +ttgo-t7-v14-mini32.menu.FlashMode.qio.build.boot=qio +ttgo-t7-v14-mini32.menu.FlashMode.dio=DIO +ttgo-t7-v14-mini32.menu.FlashMode.dio.build.flash_mode=dio +ttgo-t7-v14-mini32.menu.FlashMode.dio.build.boot=dio + +ttgo-t7-v14-mini32.menu.FlashFreq.80=80MHz +ttgo-t7-v14-mini32.menu.FlashFreq.80.build.flash_freq=80m +ttgo-t7-v14-mini32.menu.FlashFreq.40=40MHz +ttgo-t7-v14-mini32.menu.FlashFreq.40.build.flash_freq=40m + +ttgo-t7-v14-mini32.menu.FlashSize.4M=4MB (32Mb) +ttgo-t7-v14-mini32.menu.FlashSize.4M.build.flash_size=4MB + +ttgo-t7-v14-mini32.menu.UploadSpeed.921600=921600 +ttgo-t7-v14-mini32.menu.UploadSpeed.921600.upload.speed=921600 +ttgo-t7-v14-mini32.menu.UploadSpeed.115200=115200 +ttgo-t7-v14-mini32.menu.UploadSpeed.115200.upload.speed=115200 +ttgo-t7-v14-mini32.menu.UploadSpeed.256000.windows=256000 +ttgo-t7-v14-mini32.menu.UploadSpeed.256000.upload.speed=256000 +ttgo-t7-v14-mini32.menu.UploadSpeed.230400.windows.upload.speed=256000 +ttgo-t7-v14-mini32.menu.UploadSpeed.230400=230400 +ttgo-t7-v14-mini32.menu.UploadSpeed.230400.upload.speed=230400 +ttgo-t7-v14-mini32.menu.UploadSpeed.460800.linux=460800 +ttgo-t7-v14-mini32.menu.UploadSpeed.460800.macosx=460800 +ttgo-t7-v14-mini32.menu.UploadSpeed.460800.upload.speed=460800 +ttgo-t7-v14-mini32.menu.UploadSpeed.512000.windows=512000 +ttgo-t7-v14-mini32.menu.UploadSpeed.512000.upload.speed=512000 + +ttgo-t7-v14-mini32.menu.DebugLevel.none=None +ttgo-t7-v14-mini32.menu.DebugLevel.none.build.code_debug=0 +ttgo-t7-v14-mini32.menu.DebugLevel.error=Error +ttgo-t7-v14-mini32.menu.DebugLevel.error.build.code_debug=1 +ttgo-t7-v14-mini32.menu.DebugLevel.warn=Warn +ttgo-t7-v14-mini32.menu.DebugLevel.warn.build.code_debug=2 +ttgo-t7-v14-mini32.menu.DebugLevel.info=Info +ttgo-t7-v14-mini32.menu.DebugLevel.info.build.code_debug=3 +ttgo-t7-v14-mini32.menu.DebugLevel.debug=Debug +ttgo-t7-v14-mini32.menu.DebugLevel.debug.build.code_debug=4 +ttgo-t7-v14-mini32.menu.DebugLevel.verbose=Verbose +ttgo-t7-v14-mini32.menu.DebugLevel.verbose.build.code_debug=5 + +ttgo-t7-v14-mini32.menu.EraseFlash.none=Disabled +ttgo-t7-v14-mini32.menu.EraseFlash.none.upload.erase_cmd= +ttgo-t7-v14-mini32.menu.EraseFlash.all=Enabled +ttgo-t7-v14-mini32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ttgo-t-oi-plus.name=TTGO T-OI PLUS RISC-V ESP32-C3 + +ttgo-t-oi-plus.bootloader.tool=esptool_py +ttgo-t-oi-plus.bootloader.tool.default=esptool_py + +ttgo-t-oi-plus.upload.tool=esptool_py +ttgo-t-oi-plus.upload.tool.default=esptool_py +ttgo-t-oi-plus.upload.tool.network=esp_ota + +ttgo-t-oi-plus.upload.maximum_size=1310720 +ttgo-t-oi-plus.upload.maximum_data_size=327680 +ttgo-t-oi-plus.upload.flags= +ttgo-t-oi-plus.upload.extra_flags= + +ttgo-t-oi-plus.serial.disableDTR=false +ttgo-t-oi-plus.serial.disableRTS=false + +ttgo-t-oi-plus.build.tarch=riscv32 +ttgo-t-oi-plus.build.target=esp +ttgo-t-oi-plus.build.mcu=esp32c3 +ttgo-t-oi-plus.build.core=esp32 +ttgo-t-oi-plus.build.variant=ttgo-t-oi-plus +ttgo-t-oi-plus.build.board=TTGO-T-OI-PLUS_DEV +ttgo-t-oi-plus.build.bootloader_addr=0x0 + +ttgo-t-oi-plus.build.cdc_on_boot=0 +ttgo-t-oi-plus.build.f_cpu=160000000L +ttgo-t-oi-plus.build.flash_size=4MB +ttgo-t-oi-plus.build.flash_freq=80m +ttgo-t-oi-plus.build.flash_mode=qio +ttgo-t-oi-plus.build.boot=qio +ttgo-t-oi-plus.build.partitions=default +ttgo-t-oi-plus.build.defines= + +ttgo-t-oi-plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.default.build.partitions=default +ttgo-t-oi-plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ttgo-t-oi-plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ttgo-t-oi-plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.minimal.build.partitions=minimal +ttgo-t-oi-plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.no_ota.build.partitions=no_ota +ttgo-t-oi-plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ttgo-t-oi-plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ttgo-t-oi-plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ttgo-t-oi-plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.huge_app.build.partitions=huge_app +ttgo-t-oi-plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ttgo-t-oi-plus.menu.CPUFreq.160=160MHz (WiFi) +ttgo-t-oi-plus.menu.CPUFreq.160.build.f_cpu=160000000L +ttgo-t-oi-plus.menu.CPUFreq.80=80MHz (WiFi) +ttgo-t-oi-plus.menu.CPUFreq.80.build.f_cpu=80000000L +ttgo-t-oi-plus.menu.CPUFreq.40=40MHz +ttgo-t-oi-plus.menu.CPUFreq.40.build.f_cpu=40000000L +ttgo-t-oi-plus.menu.CPUFreq.20=20MHz +ttgo-t-oi-plus.menu.CPUFreq.20.build.f_cpu=20000000L +ttgo-t-oi-plus.menu.CPUFreq.10=10MHz +ttgo-t-oi-plus.menu.CPUFreq.10.build.f_cpu=10000000L + +ttgo-t-oi-plus.menu.FlashMode.qio=QIO +ttgo-t-oi-plus.menu.FlashMode.qio.build.flash_mode=dio +ttgo-t-oi-plus.menu.FlashMode.qio.build.boot=qio +ttgo-t-oi-plus.menu.FlashMode.dio=DIO +ttgo-t-oi-plus.menu.FlashMode.dio.build.flash_mode=dio +ttgo-t-oi-plus.menu.FlashMode.dio.build.boot=dio + +ttgo-t-oi-plus.menu.FlashFreq.80=80MHz +ttgo-t-oi-plus.menu.FlashFreq.80.build.flash_freq=80m +ttgo-t-oi-plus.menu.FlashFreq.40=40MHz +ttgo-t-oi-plus.menu.FlashFreq.40.build.flash_freq=40m + +ttgo-t-oi-plus.menu.FlashSize.4M=4MB (32Mb) +ttgo-t-oi-plus.menu.FlashSize.4M.build.flash_size=4MB + +ttgo-t-oi-plus.menu.UploadSpeed.921600=921600 +ttgo-t-oi-plus.menu.UploadSpeed.921600.upload.speed=921600 +ttgo-t-oi-plus.menu.UploadSpeed.115200=115200 +ttgo-t-oi-plus.menu.UploadSpeed.115200.upload.speed=115200 +ttgo-t-oi-plus.menu.UploadSpeed.256000.windows=256000 +ttgo-t-oi-plus.menu.UploadSpeed.256000.upload.speed=256000 +ttgo-t-oi-plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +ttgo-t-oi-plus.menu.UploadSpeed.230400=230400 +ttgo-t-oi-plus.menu.UploadSpeed.230400.upload.speed=230400 +ttgo-t-oi-plus.menu.UploadSpeed.460800.linux=460800 +ttgo-t-oi-plus.menu.UploadSpeed.460800.macosx=460800 +ttgo-t-oi-plus.menu.UploadSpeed.460800.upload.speed=460800 +ttgo-t-oi-plus.menu.UploadSpeed.512000.windows=512000 +ttgo-t-oi-plus.menu.UploadSpeed.512000.upload.speed=512000 + +ttgo-t-oi-plus.menu.DebugLevel.none=None +ttgo-t-oi-plus.menu.DebugLevel.none.build.code_debug=0 +ttgo-t-oi-plus.menu.DebugLevel.error=Error +ttgo-t-oi-plus.menu.DebugLevel.error.build.code_debug=1 +ttgo-t-oi-plus.menu.DebugLevel.warn=Warn +ttgo-t-oi-plus.menu.DebugLevel.warn.build.code_debug=2 +ttgo-t-oi-plus.menu.DebugLevel.info=Info +ttgo-t-oi-plus.menu.DebugLevel.info.build.code_debug=3 +ttgo-t-oi-plus.menu.DebugLevel.debug=Debug +ttgo-t-oi-plus.menu.DebugLevel.debug.build.code_debug=4 +ttgo-t-oi-plus.menu.DebugLevel.verbose=Verbose +ttgo-t-oi-plus.menu.DebugLevel.verbose.build.code_debug=5 + +ttgo-t-oi-plus.menu.EraseFlash.none=Disabled +ttgo-t-oi-plus.menu.EraseFlash.none.upload.erase_cmd= +ttgo-t-oi-plus.menu.EraseFlash.all=Enabled +ttgo-t-oi-plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +cw02.name=XinaBox CW02 + +cw02.bootloader.tool=esptool_py +cw02.bootloader.tool.default=esptool_py + +cw02.upload.tool=esptool_py +cw02.upload.tool.default=esptool_py +cw02.upload.tool.network=esp_ota + +cw02.upload.maximum_size=1310720 +cw02.upload.maximum_data_size=294912 +cw02.upload.flags= +cw02.upload.extra_flags= + +cw02.serial.disableDTR=true +cw02.serial.disableRTS=true + +cw02.build.tarch=xtensa +cw02.build.bootloader_addr=0x1000 +cw02.build.target=esp32 +cw02.build.mcu=esp32 +cw02.build.core=esp32 +cw02.build.variant=xinabox +cw02.build.board=ESP32_DEV + +cw02.build.f_cpu=240000000L +cw02.build.flash_size=4MB +cw02.build.flash_freq=40m +cw02.build.flash_mode=dio +cw02.build.boot=dio +cw02.build.partitions=default + +cw02.menu.FlashMode.qio=QIO +cw02.menu.FlashMode.qio.build.flash_mode=dio +cw02.menu.FlashMode.qio.build.boot=qio +cw02.menu.FlashMode.dio=DIO +cw02.menu.FlashMode.dio.build.flash_mode=dio +cw02.menu.FlashMode.dio.build.boot=dio + +cw02.menu.FlashFreq.80=80MHz +cw02.menu.FlashFreq.80.build.flash_freq=80m +cw02.menu.FlashFreq.40=40MHz +cw02.menu.FlashFreq.40.build.flash_freq=40m + +cw02.menu.FlashSize.4M=4MB (32Mb) +cw02.menu.FlashSize.4M.build.flash_size=4MB +cw02.menu.FlashSize.2M=2MB (16Mb) +cw02.menu.FlashSize.2M.build.flash_size=2MB + +cw02.menu.UploadSpeed.921600=921600 +cw02.menu.UploadSpeed.921600.upload.speed=921600 +cw02.menu.UploadSpeed.115200=115200 +cw02.menu.UploadSpeed.115200.upload.speed=115200 +cw02.menu.UploadSpeed.256000.windows=256000 +cw02.menu.UploadSpeed.256000.upload.speed=256000 +cw02.menu.UploadSpeed.230400.windows.upload.speed=256000 +cw02.menu.UploadSpeed.230400=230400 +cw02.menu.UploadSpeed.230400.upload.speed=230400 +cw02.menu.UploadSpeed.460800.linux=460800 +cw02.menu.UploadSpeed.460800.macosx=460800 +cw02.menu.UploadSpeed.460800.upload.speed=460800 +cw02.menu.UploadSpeed.512000.windows=512000 +cw02.menu.UploadSpeed.512000.upload.speed=512000 + +cw02.menu.DebugLevel.none=None +cw02.menu.DebugLevel.none.build.code_debug=0 +cw02.menu.DebugLevel.error=Error +cw02.menu.DebugLevel.error.build.code_debug=1 +cw02.menu.DebugLevel.warn=Warn +cw02.menu.DebugLevel.warn.build.code_debug=2 +cw02.menu.DebugLevel.info=Info +cw02.menu.DebugLevel.info.build.code_debug=3 +cw02.menu.DebugLevel.debug=Debug +cw02.menu.DebugLevel.debug.build.code_debug=4 +cw02.menu.DebugLevel.verbose=Verbose +cw02.menu.DebugLevel.verbose.build.code_debug=5 + +cw02.menu.EraseFlash.none=Disabled +cw02.menu.EraseFlash.none.upload.erase_cmd= +cw02.menu.EraseFlash.all=Enabled +cw02.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32thing.name=SparkFun ESP32 Thing + +esp32thing.bootloader.tool=esptool_py +esp32thing.bootloader.tool.default=esptool_py + +esp32thing.upload.tool=esptool_py +esp32thing.upload.tool.default=esptool_py +esp32thing.upload.tool.network=esp_ota + +esp32thing.upload.maximum_size=1310720 +esp32thing.upload.maximum_data_size=327680 +esp32thing.upload.flags= +esp32thing.upload.extra_flags= + +esp32thing.serial.disableDTR=true +esp32thing.serial.disableRTS=true + +esp32thing.build.tarch=xtensa +esp32thing.build.bootloader_addr=0x1000 +esp32thing.build.target=esp32 +esp32thing.build.mcu=esp32 +esp32thing.build.core=esp32 +esp32thing.build.variant=esp32thing +esp32thing.build.board=ESP32_THING + +esp32thing.build.f_cpu=240000000L +esp32thing.build.flash_mode=dio +esp32thing.build.flash_size=4MB +esp32thing.build.boot=dio +esp32thing.build.partitions=default +esp32thing.build.defines= + +esp32thing.menu.FlashFreq.80=80MHz +esp32thing.menu.FlashFreq.80.build.flash_freq=80m +esp32thing.menu.FlashFreq.40=40MHz +esp32thing.menu.FlashFreq.40.build.flash_freq=40m + +esp32thing.menu.PartitionScheme.default=Default +esp32thing.menu.PartitionScheme.default.build.partitions=default +esp32thing.menu.PartitionScheme.no_ota=No OTA (Large APP) +esp32thing.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32thing.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32thing.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +esp32thing.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32thing.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32thing.menu.UploadSpeed.921600=921600 +esp32thing.menu.UploadSpeed.921600.upload.speed=921600 +esp32thing.menu.UploadSpeed.115200=115200 +esp32thing.menu.UploadSpeed.115200.upload.speed=115200 +esp32thing.menu.UploadSpeed.256000.windows=256000 +esp32thing.menu.UploadSpeed.256000.upload.speed=256000 +esp32thing.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32thing.menu.UploadSpeed.230400=230400 +esp32thing.menu.UploadSpeed.230400.upload.speed=230400 +esp32thing.menu.UploadSpeed.460800.linux=460800 +esp32thing.menu.UploadSpeed.460800.macosx=460800 +esp32thing.menu.UploadSpeed.460800.upload.speed=460800 +esp32thing.menu.UploadSpeed.512000.windows=512000 +esp32thing.menu.UploadSpeed.512000.upload.speed=512000 + +esp32thing.menu.DebugLevel.none=None +esp32thing.menu.DebugLevel.none.build.code_debug=0 +esp32thing.menu.DebugLevel.error=Error +esp32thing.menu.DebugLevel.error.build.code_debug=1 +esp32thing.menu.DebugLevel.warn=Warn +esp32thing.menu.DebugLevel.warn.build.code_debug=2 +esp32thing.menu.DebugLevel.info=Info +esp32thing.menu.DebugLevel.info.build.code_debug=3 +esp32thing.menu.DebugLevel.debug=Debug +esp32thing.menu.DebugLevel.debug.build.code_debug=4 +esp32thing.menu.DebugLevel.verbose=Verbose +esp32thing.menu.DebugLevel.verbose.build.code_debug=5 + +esp32thing.menu.EraseFlash.none=Disabled +esp32thing.menu.EraseFlash.none.upload.erase_cmd= +esp32thing.menu.EraseFlash.all=Enabled +esp32thing.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32thing_plus.name=SparkFun ESP32 Thing Plus + +esp32thing_plus.bootloader.tool=esptool_py +esp32thing_plus.bootloader.tool.default=esptool_py + +esp32thing_plus.upload.tool=esptool_py +esp32thing_plus.upload.tool.default=esptool_py +esp32thing_plus.upload.tool.network=esp_ota + +esp32thing_plus.upload.maximum_size=1310720 +esp32thing_plus.upload.maximum_data_size=327680 +esp32thing_plus.upload.wait_for_upload_port=true +esp32thing_plus.upload.flags= +esp32thing_plus.upload.extra_flags= + +esp32thing_plus.serial.disableDTR=true +esp32thing_plus.serial.disableRTS=true + +esp32thing_plus.build.tarch=xtensa +esp32thing_plus.build.bootloader_addr=0x1000 +esp32thing_plus.build.target=esp32 +esp32thing_plus.build.mcu=esp32 +esp32thing_plus.build.core=esp32 +esp32thing_plus.build.variant=esp32thing_plus +esp32thing_plus.build.board=ESP32_THING_PLUS + +esp32thing_plus.build.f_cpu=240000000L +esp32thing_plus.build.flash_mode=dio +esp32thing_plus.build.flash_size=16MB +esp32thing_plus.build.boot=dio +esp32thing_plus.build.partitions=default +esp32thing_plus.build.defines= + +esp32thing_plus.menu.FlashFreq.80=80MHz +esp32thing_plus.menu.FlashFreq.80.build.flash_freq=80m +esp32thing_plus.menu.FlashFreq.40=40MHz +esp32thing_plus.menu.FlashFreq.40.build.flash_freq=40m + +esp32thing_plus.menu.PartitionScheme.default=Default (6.25MB APP/OTA/3.43MB SPIFFS) +esp32thing_plus.menu.PartitionScheme.default.build.partitions=default_16MB +esp32thing_plus.menu.PartitionScheme.default.upload.maximum_size=6553600 +esp32thing_plus.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/OTA/6.93MB SPIFFS) +esp32thing_plus.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +esp32thing_plus.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 + +esp32thing_plus.menu.UploadSpeed.921600=921600 +esp32thing_plus.menu.UploadSpeed.921600.upload.speed=921600 +esp32thing_plus.menu.UploadSpeed.115200=115200 +esp32thing_plus.menu.UploadSpeed.115200.upload.speed=115200 +esp32thing_plus.menu.UploadSpeed.256000.windows=256000 +esp32thing_plus.menu.UploadSpeed.256000.upload.speed=256000 +esp32thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32thing_plus.menu.UploadSpeed.230400=230400 +esp32thing_plus.menu.UploadSpeed.230400.upload.speed=230400 +esp32thing_plus.menu.UploadSpeed.460800.linux=460800 +esp32thing_plus.menu.UploadSpeed.460800.macosx=460800 +esp32thing_plus.menu.UploadSpeed.460800.upload.speed=460800 +esp32thing_plus.menu.UploadSpeed.512000.windows=512000 +esp32thing_plus.menu.UploadSpeed.512000.upload.speed=512000 + +esp32thing_plus.menu.DebugLevel.none=None +esp32thing_plus.menu.DebugLevel.none.build.code_debug=0 +esp32thing_plus.menu.DebugLevel.error=Error +esp32thing_plus.menu.DebugLevel.error.build.code_debug=1 +esp32thing_plus.menu.DebugLevel.warn=Warn +esp32thing_plus.menu.DebugLevel.warn.build.code_debug=2 +esp32thing_plus.menu.DebugLevel.info=Info +esp32thing_plus.menu.DebugLevel.info.build.code_debug=3 +esp32thing_plus.menu.DebugLevel.debug=Debug +esp32thing_plus.menu.DebugLevel.debug.build.code_debug=4 +esp32thing_plus.menu.DebugLevel.verbose=Verbose +esp32thing_plus.menu.DebugLevel.verbose.build.code_debug=5 + +esp32thing_plus.menu.EraseFlash.none=Disabled +esp32thing_plus.menu.EraseFlash.none.upload.erase_cmd= +esp32thing_plus.menu.EraseFlash.all=Enabled +esp32thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32thing_plus_c.name=SparkFun ESP32 Thing Plus C + +esp32thing_plus_c.bootloader.tool=esptool_py +esp32thing_plus_c.bootloader.tool.default=esptool_py + +esp32thing_plus_c.upload.tool=esptool_py +esp32thing_plus_c.upload.tool.default=esptool_py +esp32thing_plus_c.upload.tool.network=esp_ota + +esp32thing_plus_c.upload.maximum_size=1310720 +esp32thing_plus_c.upload.maximum_data_size=327680 +esp32thing_plus_c.upload.wait_for_upload_port=true +esp32thing_plus_c.upload.flags= +esp32thing_plus_c.upload.extra_flags= + +esp32thing_plus_c.serial.disableDTR=true +esp32thing_plus_c.serial.disableRTS=true + +esp32thing_plus_c.build.tarch=xtensa +esp32thing_plus_c.build.bootloader_addr=0x1000 +esp32thing_plus_c.build.target=esp32 +esp32thing_plus_c.build.mcu=esp32 +esp32thing_plus_c.build.core=esp32 +esp32thing_plus_c.build.variant=esp32thing_plus_c +esp32thing_plus_c.build.board=ESP32_THING_PLUS_C + +esp32thing_plus_c.build.f_cpu=240000000L +esp32thing_plus_c.build.flash_mode=dio +esp32thing_plus_c.build.flash_size=16MB +esp32thing_plus_c.build.boot=dio +esp32thing_plus_c.build.partitions=default +esp32thing_plus_c.build.defines= + +esp32thing_plus_c.menu.FlashFreq.80=80MHz +esp32thing_plus_c.menu.FlashFreq.80.build.flash_freq=80m +esp32thing_plus_c.menu.FlashFreq.40=40MHz +esp32thing_plus_c.menu.FlashFreq.40.build.flash_freq=40m + +esp32thing_plus_c.menu.PartitionScheme.default=Default (6.25MB APP/OTA/3.43MB SPIFFS) +esp32thing_plus_c.menu.PartitionScheme.default.build.partitions=default_16MB +esp32thing_plus_c.menu.PartitionScheme.default.upload.maximum_size=6553600 +esp32thing_plus_c.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/OTA/6.93MB SPIFFS) +esp32thing_plus_c.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +esp32thing_plus_c.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 + +esp32thing_plus_c.menu.UploadSpeed.921600=921600 +esp32thing_plus_c.menu.UploadSpeed.921600.upload.speed=921600 +esp32thing_plus_c.menu.UploadSpeed.115200=115200 +esp32thing_plus_c.menu.UploadSpeed.115200.upload.speed=115200 +esp32thing_plus_c.menu.UploadSpeed.256000.windows=256000 +esp32thing_plus_c.menu.UploadSpeed.256000.upload.speed=256000 +esp32thing_plus_c.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32thing_plus_c.menu.UploadSpeed.230400=230400 +esp32thing_plus_c.menu.UploadSpeed.230400.upload.speed=230400 +esp32thing_plus_c.menu.UploadSpeed.460800.linux=460800 +esp32thing_plus_c.menu.UploadSpeed.460800.macosx=460800 +esp32thing_plus_c.menu.UploadSpeed.460800.upload.speed=460800 +esp32thing_plus_c.menu.UploadSpeed.512000.windows=512000 +esp32thing_plus_c.menu.UploadSpeed.512000.upload.speed=512000 + +esp32thing_plus_c.menu.DebugLevel.none=None +esp32thing_plus_c.menu.DebugLevel.none.build.code_debug=0 +esp32thing_plus_c.menu.DebugLevel.error=Error +esp32thing_plus_c.menu.DebugLevel.error.build.code_debug=1 +esp32thing_plus_c.menu.DebugLevel.warn=Warn +esp32thing_plus_c.menu.DebugLevel.warn.build.code_debug=2 +esp32thing_plus_c.menu.DebugLevel.info=Info +esp32thing_plus_c.menu.DebugLevel.info.build.code_debug=3 +esp32thing_plus_c.menu.DebugLevel.debug=Debug +esp32thing_plus_c.menu.DebugLevel.debug.build.code_debug=4 +esp32thing_plus_c.menu.DebugLevel.verbose=Verbose +esp32thing_plus_c.menu.DebugLevel.verbose.build.code_debug=5 + +esp32thing_plus_c.menu.EraseFlash.none=Disabled +esp32thing_plus_c.menu.EraseFlash.none.upload.erase_cmd= +esp32thing_plus_c.menu.EraseFlash.all=Enabled +esp32thing_plus_c.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sparkfun_esp32s2_thing_plus.name=SparkFun ESP32-S2 Thing Plus +sparkfun_esp32s2_thing_plus.vid.0=0x1B4F +sparkfun_esp32s2_thing_plus.pid.0=0x0027 + +sparkfun_esp32s2_thing_plus.bootloader.tool=esptool_py +sparkfun_esp32s2_thing_plus.bootloader.tool.default=esptool_py + +sparkfun_esp32s2_thing_plus.upload.tool=esptool_py +sparkfun_esp32s2_thing_plus.upload.tool.default=esptool_py +sparkfun_esp32s2_thing_plus.upload.tool.network=esp_ota + +sparkfun_esp32s2_thing_plus.upload.maximum_size=1310720 +sparkfun_esp32s2_thing_plus.upload.maximum_data_size=327680 +sparkfun_esp32s2_thing_plus.upload.flags= +sparkfun_esp32s2_thing_plus.upload.extra_flags= +sparkfun_esp32s2_thing_plus.upload.use_1200bps_touch=true +sparkfun_esp32s2_thing_plus.upload.wait_for_upload_port=true + +sparkfun_esp32s2_thing_plus.serial.disableDTR=false +sparkfun_esp32s2_thing_plus.serial.disableRTS=false + +sparkfun_esp32s2_thing_plus.build.tarch=xtensa +sparkfun_esp32s2_thing_plus.build.bootloader_addr=0x1000 +sparkfun_esp32s2_thing_plus.build.target=esp32s2 +sparkfun_esp32s2_thing_plus.build.mcu=esp32s2 +sparkfun_esp32s2_thing_plus.build.core=esp32 +sparkfun_esp32s2_thing_plus.build.variant=esp32s2thing_plus +sparkfun_esp32s2_thing_plus.build.board=ESP32S2_THING_PLUS + +sparkfun_esp32s2_thing_plus.build.cdc_on_boot=0 +sparkfun_esp32s2_thing_plus.build.msc_on_boot=0 +sparkfun_esp32s2_thing_plus.build.dfu_on_boot=0 +sparkfun_esp32s2_thing_plus.build.f_cpu=240000000L +sparkfun_esp32s2_thing_plus.build.flash_size=4MB +sparkfun_esp32s2_thing_plus.build.flash_freq=80m +sparkfun_esp32s2_thing_plus.build.flash_mode=qio +sparkfun_esp32s2_thing_plus.build.boot=qio +sparkfun_esp32s2_thing_plus.build.partitions=default +sparkfun_esp32s2_thing_plus.build.defines= + +sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.default=Disabled +sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=0 +sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.cdc=Enabled +sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.default=Disabled +sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.default.build.msc_on_boot=0 +sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.msc=Enabled +sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.default=Disabled +sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.default.build.dfu_on_boot=0 +sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.dfu=Enabled +sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +sparkfun_esp32s2_thing_plus.menu.PSRAM.disabled=Disabled +sparkfun_esp32s2_thing_plus.menu.PSRAM.disabled.build.defines= +sparkfun_esp32s2_thing_plus.menu.PSRAM.enabled=Enabled +sparkfun_esp32s2_thing_plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default.build.partitions=default +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash.build.partitions=ffat +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +sparkfun_esp32s2_thing_plus.menu.CPUFreq.240=240MHz (WiFi) +sparkfun_esp32s2_thing_plus.menu.CPUFreq.240.build.f_cpu=240000000L +sparkfun_esp32s2_thing_plus.menu.CPUFreq.160=160MHz (WiFi) +sparkfun_esp32s2_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_esp32s2_thing_plus.menu.CPUFreq.80=80MHz (WiFi) +sparkfun_esp32s2_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_esp32s2_thing_plus.menu.CPUFreq.40=40MHz +sparkfun_esp32s2_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_esp32s2_thing_plus.menu.CPUFreq.20=20MHz +sparkfun_esp32s2_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_esp32s2_thing_plus.menu.CPUFreq.10=10MHz +sparkfun_esp32s2_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_esp32s2_thing_plus.menu.FlashMode.qio=QIO +sparkfun_esp32s2_thing_plus.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_esp32s2_thing_plus.menu.FlashMode.qio.build.boot=qio +sparkfun_esp32s2_thing_plus.menu.FlashMode.dio=DIO +sparkfun_esp32s2_thing_plus.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_esp32s2_thing_plus.menu.FlashMode.dio.build.boot=dio + +sparkfun_esp32s2_thing_plus.menu.FlashFreq.80=80MHz +sparkfun_esp32s2_thing_plus.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_esp32s2_thing_plus.menu.FlashFreq.40=40MHz +sparkfun_esp32s2_thing_plus.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_esp32s2_thing_plus.menu.FlashSize.4M=4MB (32Mb) +sparkfun_esp32s2_thing_plus.menu.FlashSize.4M.build.flash_size=4MB +sparkfun_esp32s2_thing_plus.menu.FlashSize.8M=8MB (64Mb) +sparkfun_esp32s2_thing_plus.menu.FlashSize.8M.build.flash_size=8MB +sparkfun_esp32s2_thing_plus.menu.FlashSize.2M=2MB (16Mb) +sparkfun_esp32s2_thing_plus.menu.FlashSize.2M.build.flash_size=2MB +sparkfun_esp32s2_thing_plus.menu.FlashSize.16M=16MB (128Mb) +sparkfun_esp32s2_thing_plus.menu.FlashSize.16M.build.flash_size=16MB + +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.921600=921600 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.115200=115200 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.256000.windows=256000 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400=230400 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.linux=460800 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.macosx=460800 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.512000.windows=512000 +sparkfun_esp32s2_thing_plus.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_esp32s2_thing_plus.menu.DebugLevel.none=None +sparkfun_esp32s2_thing_plus.menu.DebugLevel.none.build.code_debug=0 +sparkfun_esp32s2_thing_plus.menu.DebugLevel.error=Error +sparkfun_esp32s2_thing_plus.menu.DebugLevel.error.build.code_debug=1 +sparkfun_esp32s2_thing_plus.menu.DebugLevel.warn=Warn +sparkfun_esp32s2_thing_plus.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_esp32s2_thing_plus.menu.DebugLevel.info=Info +sparkfun_esp32s2_thing_plus.menu.DebugLevel.info.build.code_debug=3 +sparkfun_esp32s2_thing_plus.menu.DebugLevel.debug=Debug +sparkfun_esp32s2_thing_plus.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_esp32s2_thing_plus.menu.DebugLevel.verbose=Verbose +sparkfun_esp32s2_thing_plus.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_esp32s2_thing_plus.menu.EraseFlash.none=Disabled +sparkfun_esp32s2_thing_plus.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_esp32s2_thing_plus.menu.EraseFlash.all=Enabled +sparkfun_esp32s2_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Sparkfun ESP32S3 Thing Plus + +sparkfun_esp32s3_thing_plus.name=SparkFun ESP32-S3 Thing Plus +sparkfun_esp32s3_thing_plus.bootloader.tool=esptool_py +sparkfun_esp32s3_thing_plus.bootloader.tool.default=esptool_py + +sparkfun_esp32s3_thing_plus.upload.tool=esptool_py +sparkfun_esp32s3_thing_plus.upload.tool.default=esptool_py +sparkfun_esp32s3_thing_plus.upload.tool.network=esp_ota + +sparkfun_esp32s3_thing_plus.upload.maximum_size=1310720 +sparkfun_esp32s3_thing_plus.upload.maximum_data_size=327680 +sparkfun_esp32s3_thing_plus.upload.flags= +sparkfun_esp32s3_thing_plus.upload.extra_flags= +sparkfun_esp32s3_thing_plus.upload.use_1200bps_touch=false +sparkfun_esp32s3_thing_plus.upload.wait_for_upload_port=false + +sparkfun_esp32s3_thing_plus.serial.disableDTR=false +sparkfun_esp32s3_thing_plus.serial.disableRTS=false + +sparkfun_esp32s3_thing_plus.build.tarch=xtensa +sparkfun_esp32s3_thing_plus.build.bootloader_addr=0x0 +sparkfun_esp32s3_thing_plus.build.target=esp32s3 +sparkfun_esp32s3_thing_plus.build.mcu=esp32s3 +sparkfun_esp32s3_thing_plus.build.core=esp32 +sparkfun_esp32s3_thing_plus.build.variant=sparkfun_esp32s3_thing_plus +sparkfun_esp32s3_thing_plus.build.board=SPARKFUN_ESP32S3_THING_PLUS + +sparkfun_esp32s3_thing_plus.build.usb_mode=1 +sparkfun_esp32s3_thing_plus.build.cdc_on_boot=0 +sparkfun_esp32s3_thing_plus.build.msc_on_boot=0 +sparkfun_esp32s3_thing_plus.build.dfu_on_boot=0 +sparkfun_esp32s3_thing_plus.build.f_cpu=240000000L +sparkfun_esp32s3_thing_plus.build.flash_size=4MB +sparkfun_esp32s3_thing_plus.build.flash_freq=80m +sparkfun_esp32s3_thing_plus.build.flash_mode=dio +sparkfun_esp32s3_thing_plus.build.boot=qio +sparkfun_esp32s3_thing_plus.build.boot_freq=80m +sparkfun_esp32s3_thing_plus.build.partitions=default +sparkfun_esp32s3_thing_plus.build.defines= +sparkfun_esp32s3_thing_plus.build.loop_core= +sparkfun_esp32s3_thing_plus.build.event_core= +sparkfun_esp32s3_thing_plus.build.psram_type=qspi +sparkfun_esp32s3_thing_plus.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.default=Disabled +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.default.build.copy_jtag_files=0 +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin=Integrated USB JTAG +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external=FTDI Adapter +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external.build.copy_jtag_files=1 +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge=ESP USB Bridge +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled=QSPI PSRAM +sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled.build.psram_type=qspi + +sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled=Disabled +sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled.build.defines= +sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled.build.psram_type=qspi +sparkfun_esp32s3_thing_plus.menu.PSRAM.opi=OPI PSRAM +sparkfun_esp32s3_thing_plus.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +sparkfun_esp32s3_thing_plus.menu.PSRAM.opi.build.psram_type=opi + +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio=QIO 80MHz +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.boot=qio +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.boot_freq=80m +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.flash_freq=80m +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120=QIO 120MHz +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.flash_mode=dio +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.boot=qio +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.boot_freq=120m +sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.flash_freq=80m +sparkfun_esp32s3_thing_plus.menu.FlashMode.dio=DIO 80MHz +sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.boot=dio +sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.boot_freq=80m +sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.flash_freq=80m + +sparkfun_esp32s3_thing_plus.menu.LoopCore.1=Core 1 +sparkfun_esp32s3_thing_plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sparkfun_esp32s3_thing_plus.menu.LoopCore.0=Core 0 +sparkfun_esp32s3_thing_plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sparkfun_esp32s3_thing_plus.menu.EventsCore.1=Core 1 +sparkfun_esp32s3_thing_plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sparkfun_esp32s3_thing_plus.menu.EventsCore.0=Core 0 +sparkfun_esp32s3_thing_plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sparkfun_esp32s3_thing_plus.menu.USBMode.default=Hardware CDC and JTAG +sparkfun_esp32s3_thing_plus.menu.USBMode.default.build.usb_mode=1 +sparkfun_esp32s3_thing_plus.menu.USBMode.hwcdc=USB-OTG (TinyUSB) +sparkfun_esp32s3_thing_plus.menu.USBMode.hwcdc.build.usb_mode=0 + +# sparkfun says to put that to Enabled but it fails +sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.default=Disabled +sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=0 +sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.cdc=Enabled +sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.default=Disabled +sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.default.build.msc_on_boot=0 +sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.default=Disabled +sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.default.build.dfu_on_boot=0 +sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +sparkfun_esp32s3_thing_plus.menu.UploadMode.default=UART0 / Hardware CDC +sparkfun_esp32s3_thing_plus.menu.UploadMode.default.upload.use_1200bps_touch=false +sparkfun_esp32s3_thing_plus.menu.UploadMode.default.upload.wait_for_upload_port=false +sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true +sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.default.build.partitions=default +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs.build.partitions=no_fs +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom=Custom +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom.build.partitions= +sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +sparkfun_esp32s3_thing_plus.menu.CPUFreq.240=240MHz (WiFi) +sparkfun_esp32s3_thing_plus.menu.CPUFreq.240.build.f_cpu=240000000L +sparkfun_esp32s3_thing_plus.menu.CPUFreq.160=160MHz (WiFi) +sparkfun_esp32s3_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_esp32s3_thing_plus.menu.CPUFreq.80=80MHz (WiFi) +sparkfun_esp32s3_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_esp32s3_thing_plus.menu.CPUFreq.40=40MHz +sparkfun_esp32s3_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_esp32s3_thing_plus.menu.CPUFreq.20=20MHz +sparkfun_esp32s3_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_esp32s3_thing_plus.menu.CPUFreq.10=10MHz +sparkfun_esp32s3_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.921600=921600 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.115200=115200 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.256000.windows=256000 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400=230400 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.linux=460800 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.macosx=460800 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.512000.windows=512000 +sparkfun_esp32s3_thing_plus.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_esp32s3_thing_plus.menu.DebugLevel.none=None +sparkfun_esp32s3_thing_plus.menu.DebugLevel.none.build.code_debug=0 +sparkfun_esp32s3_thing_plus.menu.DebugLevel.error=Error +sparkfun_esp32s3_thing_plus.menu.DebugLevel.error.build.code_debug=1 +sparkfun_esp32s3_thing_plus.menu.DebugLevel.warn=Warn +sparkfun_esp32s3_thing_plus.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_esp32s3_thing_plus.menu.DebugLevel.info=Info +sparkfun_esp32s3_thing_plus.menu.DebugLevel.info.build.code_debug=3 +sparkfun_esp32s3_thing_plus.menu.DebugLevel.debug=Debug +sparkfun_esp32s3_thing_plus.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_esp32s3_thing_plus.menu.DebugLevel.verbose=Verbose +sparkfun_esp32s3_thing_plus.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_esp32s3_thing_plus.menu.EraseFlash.none=Disabled +sparkfun_esp32s3_thing_plus.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_esp32s3_thing_plus.menu.EraseFlash.all=Enabled +sparkfun_esp32s3_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e + +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default=Disabled +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default.build.zigbee_mode= +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default.build.zigbee_libs= +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator) +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +sparkfun_esp32c6_thing_plus.name=SparkFun ESP32-C6 Thing Plus + +sparkfun_esp32c6_thing_plus.bootloader.tool=esptool_py +sparkfun_esp32c6_thing_plus.bootloader.tool.default=esptool_py + +sparkfun_esp32c6_thing_plus.upload.tool=esptool_py +sparkfun_esp32c6_thing_plus.upload.tool.default=esptool_py +sparkfun_esp32c6_thing_plus.upload.tool.network=esp_ota + +sparkfun_esp32c6_thing_plus.upload.maximum_size=1310720 +sparkfun_esp32c6_thing_plus.upload.maximum_data_size=327680 +sparkfun_esp32c6_thing_plus.upload.flags= +sparkfun_esp32c6_thing_plus.upload.extra_flags= +sparkfun_esp32c6_thing_plus.upload.use_1200bps_touch=false +sparkfun_esp32c6_thing_plus.upload.wait_for_upload_port=false + +sparkfun_esp32c6_thing_plus.serial.disableDTR=false +sparkfun_esp32c6_thing_plus.serial.disableRTS=false + +sparkfun_esp32c6_thing_plus.build.tarch=riscv32 +sparkfun_esp32c6_thing_plus.build.target=esp +sparkfun_esp32c6_thing_plus.build.mcu=esp32c6 +sparkfun_esp32c6_thing_plus.build.core=esp32 +sparkfun_esp32c6_thing_plus.build.variant=sparkfun_esp32c6_thing_plus +sparkfun_esp32c6_thing_plus.build.board=ESP32C6_THING_PLUS +sparkfun_esp32c6_thing_plus.build.bootloader_addr=0x0 + +sparkfun_esp32c6_thing_plus.build.cdc_on_boot=0 +sparkfun_esp32c6_thing_plus.build.f_cpu=160000000L +sparkfun_esp32c6_thing_plus.build.flash_size=4MB +sparkfun_esp32c6_thing_plus.build.flash_freq=80m +sparkfun_esp32c6_thing_plus.build.flash_mode=qio +sparkfun_esp32c6_thing_plus.build.boot=qio +sparkfun_esp32c6_thing_plus.build.partitions=default +sparkfun_esp32c6_thing_plus.build.defines= + +## IDE 2.0 Seems to not update the value +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.default=Disabled +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.default.build.copy_jtag_files=0 +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin=Integrated USB JTAG +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external=FTDI Adapter +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external.build.copy_jtag_files=1 +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge=ESP USB Bridge +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.default=Enabled +sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=1 +sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.cdc=Disabled +sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default.build.partitions=default +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash.build.partitions=ffat +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee.build.partitions=zigbee +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom=Custom +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom.build.partitions= +sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +sparkfun_esp32c6_thing_plus.menu.CPUFreq.160=160MHz (WiFi) +sparkfun_esp32c6_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_esp32c6_thing_plus.menu.CPUFreq.80=80MHz (WiFi) +sparkfun_esp32c6_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_esp32c6_thing_plus.menu.CPUFreq.40=40MHz +sparkfun_esp32c6_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_esp32c6_thing_plus.menu.CPUFreq.20=20MHz +sparkfun_esp32c6_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_esp32c6_thing_plus.menu.CPUFreq.10=10MHz +sparkfun_esp32c6_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_esp32c6_thing_plus.menu.FlashMode.qio=QIO +sparkfun_esp32c6_thing_plus.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_esp32c6_thing_plus.menu.FlashMode.qio.build.boot=qio +sparkfun_esp32c6_thing_plus.menu.FlashMode.dio=DIO +sparkfun_esp32c6_thing_plus.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_esp32c6_thing_plus.menu.FlashMode.dio.build.boot=dio + +sparkfun_esp32c6_thing_plus.menu.FlashFreq.80=80MHz +sparkfun_esp32c6_thing_plus.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_esp32c6_thing_plus.menu.FlashFreq.40=40MHz +sparkfun_esp32c6_thing_plus.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_esp32c6_thing_plus.menu.FlashSize.4M=4MB (32Mb) +sparkfun_esp32c6_thing_plus.menu.FlashSize.4M.build.flash_size=4MB +sparkfun_esp32c6_thing_plus.menu.FlashSize.8M=8MB (64Mb) +sparkfun_esp32c6_thing_plus.menu.FlashSize.8M.build.flash_size=8MB +sparkfun_esp32c6_thing_plus.menu.FlashSize.2M=2MB (16Mb) +sparkfun_esp32c6_thing_plus.menu.FlashSize.2M.build.flash_size=2MB +sparkfun_esp32c6_thing_plus.menu.FlashSize.16M=16MB (128Mb) +sparkfun_esp32c6_thing_plus.menu.FlashSize.16M.build.flash_size=16MB + +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.921600=921600 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.115200=115200 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.256000.windows=256000 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400=230400 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.linux=460800 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.macosx=460800 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.512000.windows=512000 +sparkfun_esp32c6_thing_plus.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_esp32c6_thing_plus.menu.DebugLevel.none=None +sparkfun_esp32c6_thing_plus.menu.DebugLevel.none.build.code_debug=0 +sparkfun_esp32c6_thing_plus.menu.DebugLevel.error=Error +sparkfun_esp32c6_thing_plus.menu.DebugLevel.error.build.code_debug=1 +sparkfun_esp32c6_thing_plus.menu.DebugLevel.warn=Warn +sparkfun_esp32c6_thing_plus.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_esp32c6_thing_plus.menu.DebugLevel.info=Info +sparkfun_esp32c6_thing_plus.menu.DebugLevel.info.build.code_debug=3 +sparkfun_esp32c6_thing_plus.menu.DebugLevel.debug=Debug +sparkfun_esp32c6_thing_plus.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_esp32c6_thing_plus.menu.DebugLevel.verbose=Verbose +sparkfun_esp32c6_thing_plus.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_esp32c6_thing_plus.menu.EraseFlash.none=Disabled +sparkfun_esp32c6_thing_plus.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_esp32c6_thing_plus.menu.EraseFlash.all=Enabled +sparkfun_esp32c6_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e + +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default=Disabled +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default.build.zigbee_mode= +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default.build.zigbee_libs= +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed=Zigbee ED (end device) +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +esp32micromod.name=SparkFun ESP32 MicroMod + +esp32micromod.bootloader.tool=esptool_py +esp32micromod.bootloader.tool.default=esptool_py + +esp32micromod.upload.tool=esptool_py +esp32micromod.upload.tool.default=esptool_py +esp32micromod.upload.tool.network=esp_ota + +esp32micromod.upload.maximum_size=1310720 +esp32micromod.upload.maximum_data_size=327680 +esp32micromod.upload.wait_for_upload_port=true +esp32micromod.upload.flags= +esp32micromod.upload.extra_flags= + +esp32micromod.serial.disableDTR=true +esp32micromod.serial.disableRTS=true + +esp32micromod.build.tarch=xtensa +esp32micromod.build.bootloader_addr=0x1000 +esp32micromod.build.target=esp32 +esp32micromod.build.mcu=esp32 +esp32micromod.build.core=esp32 +esp32micromod.build.variant=esp32micromod +esp32micromod.build.board=ESP32_MICROMOD + +esp32micromod.build.f_cpu=240000000L +esp32micromod.build.flash_size=4MB +esp32micromod.build.flash_freq=40m +esp32micromod.build.flash_mode=dio +esp32micromod.build.boot=dio +esp32micromod.build.partitions=default +esp32micromod.build.defines= + +esp32micromod.menu.PSRAM.disabled=Disabled +esp32micromod.menu.PSRAM.disabled.build.defines= +esp32micromod.menu.PSRAM.enabled=Enabled +esp32micromod.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue + +esp32micromod.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32micromod.menu.PartitionScheme.default.build.partitions=default +esp32micromod.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32micromod.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32micromod.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32micromod.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32micromod.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32micromod.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32micromod.menu.PartitionScheme.minimal.build.partitions=minimal +esp32micromod.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32micromod.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32micromod.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32micromod.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32micromod.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32micromod.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32micromod.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32micromod.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32micromod.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32micromod.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32micromod.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32micromod.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32micromod.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32micromod.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32micromod.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32micromod.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32micromod.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32micromod.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32micromod.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32micromod.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32micromod.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +esp32micromod.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32micromod.menu.CPUFreq.240.build.f_cpu=240000000L +esp32micromod.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32micromod.menu.CPUFreq.160.build.f_cpu=160000000L +esp32micromod.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32micromod.menu.CPUFreq.80.build.f_cpu=80000000L +esp32micromod.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32micromod.menu.CPUFreq.40.build.f_cpu=40000000L +esp32micromod.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32micromod.menu.CPUFreq.26.build.f_cpu=26000000L +esp32micromod.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32micromod.menu.CPUFreq.20.build.f_cpu=20000000L +esp32micromod.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32micromod.menu.CPUFreq.13.build.f_cpu=13000000L +esp32micromod.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32micromod.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32micromod.menu.FlashMode.qio=QIO +esp32micromod.menu.FlashMode.qio.build.flash_mode=dio +esp32micromod.menu.FlashMode.qio.build.boot=qio +esp32micromod.menu.FlashMode.dio=DIO +esp32micromod.menu.FlashMode.dio.build.flash_mode=dio +esp32micromod.menu.FlashMode.dio.build.boot=dio + +esp32micromod.menu.FlashFreq.80=80MHz +esp32micromod.menu.FlashFreq.80.build.flash_freq=80m +esp32micromod.menu.FlashFreq.40=40MHz +esp32micromod.menu.FlashFreq.40.build.flash_freq=40m + +esp32micromod.menu.FlashSize.4M=4MB (32Mb) +esp32micromod.menu.FlashSize.4M.build.flash_size=4MB +esp32micromod.menu.FlashSize.8M=8MB (64Mb) +esp32micromod.menu.FlashSize.8M.build.flash_size=8MB +esp32micromod.menu.FlashSize.2M=2MB (16Mb) +esp32micromod.menu.FlashSize.2M.build.flash_size=2MB +esp32micromod.menu.FlashSize.16M=16MB (128Mb) +esp32micromod.menu.FlashSize.16M.build.flash_size=16MB + +esp32micromod.menu.UploadSpeed.921600=921600 +esp32micromod.menu.UploadSpeed.921600.upload.speed=921600 +esp32micromod.menu.UploadSpeed.115200=115200 +esp32micromod.menu.UploadSpeed.115200.upload.speed=115200 +esp32micromod.menu.UploadSpeed.256000.windows=256000 +esp32micromod.menu.UploadSpeed.256000.upload.speed=256000 +esp32micromod.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32micromod.menu.UploadSpeed.230400=230400 +esp32micromod.menu.UploadSpeed.230400.upload.speed=230400 +esp32micromod.menu.UploadSpeed.460800.linux=460800 +esp32micromod.menu.UploadSpeed.460800.macosx=460800 +esp32micromod.menu.UploadSpeed.460800.upload.speed=460800 +esp32micromod.menu.UploadSpeed.512000.windows=512000 +esp32micromod.menu.UploadSpeed.512000.upload.speed=512000 + +esp32micromod.menu.DebugLevel.none=None +esp32micromod.menu.DebugLevel.none.build.code_debug=0 +esp32micromod.menu.DebugLevel.error=Error +esp32micromod.menu.DebugLevel.error.build.code_debug=1 +esp32micromod.menu.DebugLevel.warn=Warn +esp32micromod.menu.DebugLevel.warn.build.code_debug=2 +esp32micromod.menu.DebugLevel.info=Info +esp32micromod.menu.DebugLevel.info.build.code_debug=3 +esp32micromod.menu.DebugLevel.debug=Debug +esp32micromod.menu.DebugLevel.debug.build.code_debug=4 +esp32micromod.menu.DebugLevel.verbose=Verbose +esp32micromod.menu.DebugLevel.verbose.build.code_debug=5 + +esp32micromod.menu.EraseFlash.none=Disabled +esp32micromod.menu.EraseFlash.none.upload.erase_cmd= +esp32micromod.menu.EraseFlash.all=Enabled +esp32micromod.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sparkfun_lora_gateway_1-channel.name=SparkFun LoRa Gateway 1-Channel + +sparkfun_lora_gateway_1-channel.bootloader.tool=esptool_py +sparkfun_lora_gateway_1-channel.bootloader.tool.default=esptool_py + +sparkfun_lora_gateway_1-channel.upload.tool=esptool_py +sparkfun_lora_gateway_1-channel.upload.tool.default=esptool_py +sparkfun_lora_gateway_1-channel.upload.tool.network=esp_ota + +sparkfun_lora_gateway_1-channel.upload.maximum_size=1310720 +sparkfun_lora_gateway_1-channel.upload.maximum_data_size=294912 +sparkfun_lora_gateway_1-channel.upload.flags= +sparkfun_lora_gateway_1-channel.upload.extra_flags= + +sparkfun_lora_gateway_1-channel.serial.disableDTR=true +sparkfun_lora_gateway_1-channel.serial.disableRTS=true + +sparkfun_lora_gateway_1-channel.build.tarch=xtensa +sparkfun_lora_gateway_1-channel.build.bootloader_addr=0x1000 +sparkfun_lora_gateway_1-channel.build.target=esp32 +sparkfun_lora_gateway_1-channel.build.mcu=esp32 +sparkfun_lora_gateway_1-channel.build.core=esp32 +sparkfun_lora_gateway_1-channel.build.variant=sparkfun_lora_gateway_1-channel +sparkfun_lora_gateway_1-channel.build.board=ESP32_DEV + +sparkfun_lora_gateway_1-channel.build.f_cpu=240000000L +sparkfun_lora_gateway_1-channel.build.flash_size=4MB +sparkfun_lora_gateway_1-channel.build.flash_freq=40m +sparkfun_lora_gateway_1-channel.build.flash_mode=dio +sparkfun_lora_gateway_1-channel.build.boot=dio +sparkfun_lora_gateway_1-channel.build.partitions=default + +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default=Default +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default.build.partitions=default +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota=No OTA (Large APP) +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sparkfun_lora_gateway_1-channel.menu.FlashMode.qio=QIO +sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.boot=qio +sparkfun_lora_gateway_1-channel.menu.FlashMode.dio=DIO +sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.boot=dio + +sparkfun_lora_gateway_1-channel.menu.FlashFreq.80=80MHz +sparkfun_lora_gateway_1-channel.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_lora_gateway_1-channel.menu.FlashFreq.40=40MHz +sparkfun_lora_gateway_1-channel.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_lora_gateway_1-channel.menu.FlashSize.4M=4MB (32Mb) +sparkfun_lora_gateway_1-channel.menu.FlashSize.4M.build.flash_size=4MB + +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600=921600 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200=115200 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.windows=256000 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400=230400 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.linux=460800 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.macosx=460800 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.windows=512000 +sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_lora_gateway_1-channel.menu.DebugLevel.none=None +sparkfun_lora_gateway_1-channel.menu.DebugLevel.none.build.code_debug=0 +sparkfun_lora_gateway_1-channel.menu.DebugLevel.error=Error +sparkfun_lora_gateway_1-channel.menu.DebugLevel.error.build.code_debug=1 +sparkfun_lora_gateway_1-channel.menu.DebugLevel.warn=Warn +sparkfun_lora_gateway_1-channel.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_lora_gateway_1-channel.menu.DebugLevel.info=Info +sparkfun_lora_gateway_1-channel.menu.DebugLevel.info.build.code_debug=3 +sparkfun_lora_gateway_1-channel.menu.DebugLevel.debug=Debug +sparkfun_lora_gateway_1-channel.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_lora_gateway_1-channel.menu.DebugLevel.verbose=Verbose +sparkfun_lora_gateway_1-channel.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_lora_gateway_1-channel.menu.EraseFlash.none=Disabled +sparkfun_lora_gateway_1-channel.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_lora_gateway_1-channel.menu.EraseFlash.all=Enabled +sparkfun_lora_gateway_1-channel.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sparkfun_esp32_iot_redboard.name=SparkFun ESP32 IoT RedBoard + +sparkfun_esp32_iot_redboard.bootloader.tool=esptool_py +sparkfun_esp32_iot_redboard.bootloader.tool.default=esptool_py + +sparkfun_esp32_iot_redboard.upload.tool=esptool_py +sparkfun_esp32_iot_redboard.upload.tool.default=esptool_py +sparkfun_esp32_iot_redboard.upload.tool.network=esp_ota + +sparkfun_esp32_iot_redboard.upload.maximum_size=1310720 +sparkfun_esp32_iot_redboard.upload.maximum_data_size=327680 +sparkfun_esp32_iot_redboard.upload.flags= +sparkfun_esp32_iot_redboard.upload.extra_flags= + +sparkfun_esp32_iot_redboard.serial.disableDTR=true +sparkfun_esp32_iot_redboard.serial.disableRTS=true + +sparkfun_esp32_iot_redboard.build.tarch=xtensa +sparkfun_esp32_iot_redboard.build.bootloader_addr=0x1000 +sparkfun_esp32_iot_redboard.build.target=esp32 +sparkfun_esp32_iot_redboard.build.mcu=esp32 +sparkfun_esp32_iot_redboard.build.core=esp32 +sparkfun_esp32_iot_redboard.build.variant=sparkfun_esp32_iot_redboard +sparkfun_esp32_iot_redboard.build.board=ESP32_IOT_REDBOARD + +sparkfun_esp32_iot_redboard.build.f_cpu=240000000L +sparkfun_esp32_iot_redboard.build.flash_size=4MB +sparkfun_esp32_iot_redboard.build.flash_freq=40m +sparkfun_esp32_iot_redboard.build.flash_mode=dio +sparkfun_esp32_iot_redboard.build.boot=dio +sparkfun_esp32_iot_redboard.build.partitions=default +sparkfun_esp32_iot_redboard.build.defines= +sparkfun_esp32_iot_redboard.build.loop_core= +sparkfun_esp32_iot_redboard.build.event_core= + +sparkfun_esp32_iot_redboard.menu.PSRAM.disabled=Disabled +sparkfun_esp32_iot_redboard.menu.PSRAM.disabled.build.defines= +sparkfun_esp32_iot_redboard.menu.PSRAM.disabled.build.extra_libs= +sparkfun_esp32_iot_redboard.menu.PSRAM.enabled=Enabled +sparkfun_esp32_iot_redboard.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +sparkfun_esp32_iot_redboard.menu.PSRAM.enabled.build.extra_libs= + +sparkfun_esp32_iot_redboard.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.default.build.partitions=default +sparkfun_esp32_iot_redboard.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash.build.partitions=ffat +sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker=RainMaker 4MB +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +sparkfun_esp32_iot_redboard.menu.CPUFreq.240=240MHz (WiFi/BT) +sparkfun_esp32_iot_redboard.menu.CPUFreq.240.build.f_cpu=240000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.160=160MHz (WiFi/BT) +sparkfun_esp32_iot_redboard.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.80=80MHz (WiFi/BT) +sparkfun_esp32_iot_redboard.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.40=40MHz (40MHz XTAL) +sparkfun_esp32_iot_redboard.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.26=26MHz (26MHz XTAL) +sparkfun_esp32_iot_redboard.menu.CPUFreq.26.build.f_cpu=26000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.20=20MHz (40MHz XTAL) +sparkfun_esp32_iot_redboard.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.13=13MHz (26MHz XTAL) +sparkfun_esp32_iot_redboard.menu.CPUFreq.13.build.f_cpu=13000000L +sparkfun_esp32_iot_redboard.menu.CPUFreq.10=10MHz (40MHz XTAL) +sparkfun_esp32_iot_redboard.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_esp32_iot_redboard.menu.FlashMode.qio=QIO +sparkfun_esp32_iot_redboard.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_esp32_iot_redboard.menu.FlashMode.qio.build.boot=qio +sparkfun_esp32_iot_redboard.menu.FlashMode.dio=DIO +sparkfun_esp32_iot_redboard.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_esp32_iot_redboard.menu.FlashMode.dio.build.boot=dio + +sparkfun_esp32_iot_redboard.menu.FlashFreq.80=80MHz +sparkfun_esp32_iot_redboard.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_esp32_iot_redboard.menu.FlashFreq.40=40MHz +sparkfun_esp32_iot_redboard.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_esp32_iot_redboard.menu.FlashSize.4M=4MB (32Mb) +sparkfun_esp32_iot_redboard.menu.FlashSize.4M.build.flash_size=4MB +sparkfun_esp32_iot_redboard.menu.FlashSize.8M=8MB (64Mb) +sparkfun_esp32_iot_redboard.menu.FlashSize.8M.build.flash_size=8MB +sparkfun_esp32_iot_redboard.menu.FlashSize.2M=2MB (16Mb) +sparkfun_esp32_iot_redboard.menu.FlashSize.2M.build.flash_size=2MB +sparkfun_esp32_iot_redboard.menu.FlashSize.16M=16MB (128Mb) +sparkfun_esp32_iot_redboard.menu.FlashSize.16M.build.flash_size=16MB + +sparkfun_esp32_iot_redboard.menu.UploadSpeed.921600=921600 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.115200=115200 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.256000.windows=256000 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400=230400 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.linux=460800 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.macosx=460800 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.512000.windows=512000 +sparkfun_esp32_iot_redboard.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_esp32_iot_redboard.menu.LoopCore.1=Core 1 +sparkfun_esp32_iot_redboard.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sparkfun_esp32_iot_redboard.menu.LoopCore.0=Core 0 +sparkfun_esp32_iot_redboard.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sparkfun_esp32_iot_redboard.menu.EventsCore.1=Core 1 +sparkfun_esp32_iot_redboard.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sparkfun_esp32_iot_redboard.menu.EventsCore.0=Core 0 +sparkfun_esp32_iot_redboard.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sparkfun_esp32_iot_redboard.menu.DebugLevel.none=None +sparkfun_esp32_iot_redboard.menu.DebugLevel.none.build.code_debug=0 +sparkfun_esp32_iot_redboard.menu.DebugLevel.error=Error +sparkfun_esp32_iot_redboard.menu.DebugLevel.error.build.code_debug=1 +sparkfun_esp32_iot_redboard.menu.DebugLevel.warn=Warn +sparkfun_esp32_iot_redboard.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_esp32_iot_redboard.menu.DebugLevel.info=Info +sparkfun_esp32_iot_redboard.menu.DebugLevel.info.build.code_debug=3 +sparkfun_esp32_iot_redboard.menu.DebugLevel.debug=Debug +sparkfun_esp32_iot_redboard.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_esp32_iot_redboard.menu.DebugLevel.verbose=Verbose +sparkfun_esp32_iot_redboard.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_esp32_iot_redboard.menu.EraseFlash.none=Disabled +sparkfun_esp32_iot_redboard.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_esp32_iot_redboard.menu.EraseFlash.all=Enabled +sparkfun_esp32_iot_redboard.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sparkfun_esp32c6_qwiic_pocket.name=SparkFun ESP32-C6 Qwiic Pocket + +sparkfun_esp32c6_qwiic_pocket.bootloader.tool=esptool_py +sparkfun_esp32c6_qwiic_pocket.bootloader.tool.default=esptool_py + +sparkfun_esp32c6_qwiic_pocket.upload.tool=esptool_py +sparkfun_esp32c6_qwiic_pocket.upload.tool.default=esptool_py +sparkfun_esp32c6_qwiic_pocket.upload.tool.network=esp_ota + +sparkfun_esp32c6_qwiic_pocket.upload.maximum_size=1310720 +sparkfun_esp32c6_qwiic_pocket.upload.maximum_data_size=327680 +sparkfun_esp32c6_qwiic_pocket.upload.flags= +sparkfun_esp32c6_qwiic_pocket.upload.extra_flags= +sparkfun_esp32c6_qwiic_pocket.upload.use_1200bps_touch=false +sparkfun_esp32c6_qwiic_pocket.upload.wait_for_upload_port=false + +sparkfun_esp32c6_qwiic_pocket.serial.disableDTR=false +sparkfun_esp32c6_qwiic_pocket.serial.disableRTS=false + +sparkfun_esp32c6_qwiic_pocket.build.tarch=riscv32 +sparkfun_esp32c6_qwiic_pocket.build.target=esp +sparkfun_esp32c6_qwiic_pocket.build.mcu=esp32c6 +sparkfun_esp32c6_qwiic_pocket.build.core=esp32 +sparkfun_esp32c6_qwiic_pocket.build.variant=sparkfun_esp32c6_qwiic_pocket +sparkfun_esp32c6_qwiic_pocket.build.board=ESP32C6_QWIIC_POCKET +sparkfun_esp32c6_qwiic_pocket.build.bootloader_addr=0x0 + +sparkfun_esp32c6_qwiic_pocket.build.cdc_on_boot=0 +sparkfun_esp32c6_qwiic_pocket.build.f_cpu=160000000L +sparkfun_esp32c6_qwiic_pocket.build.flash_size=4MB +sparkfun_esp32c6_qwiic_pocket.build.flash_freq=80m +sparkfun_esp32c6_qwiic_pocket.build.flash_mode=qio +sparkfun_esp32c6_qwiic_pocket.build.boot=qio +sparkfun_esp32c6_qwiic_pocket.build.partitions=default +sparkfun_esp32c6_qwiic_pocket.build.defines= + +## IDE 2.0 Seems to not update the value +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.default=Disabled +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.default.build.copy_jtag_files=0 +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin=Integrated USB JTAG +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external=FTDI Adapter +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external.build.copy_jtag_files=1 +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge=ESP USB Bridge +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.default=Enabled +sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.default.build.cdc_on_boot=1 +sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.cdc=Disabled +sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default.build.partitions=default +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash.build.partitions=ffat +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker=RainMaker 4MB +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee.build.partitions=zigbee +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom=Custom +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom.build.partitions= +sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.160=160MHz (WiFi) +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.80=80MHz (WiFi) +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.40=40MHz +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.20=20MHz +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.10=10MHz +sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio=QIO +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio.build.boot=qio +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio=DIO +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio.build.boot=dio + +sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.80=80MHz +sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.40=40MHz +sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.4M=4MB (32Mb) +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.4M.build.flash_size=4MB +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.8M=8MB (64Mb) +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.8M.build.flash_size=8MB +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.2M=2MB (16Mb) +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.2M.build.flash_size=2MB +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.16M=16MB (128Mb) +sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.16M.build.flash_size=16MB + +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.921600=921600 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.115200=115200 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.256000.windows=256000 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400=230400 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.linux=460800 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.macosx=460800 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.512000.windows=512000 +sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.none=None +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.none.build.code_debug=0 +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.error=Error +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.error.build.code_debug=1 +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.warn=Warn +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.info=Info +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.info.build.code_debug=3 +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.debug=Debug +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.verbose=Verbose +sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.none=Disabled +sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.all=Enabled +sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.all.upload.erase_cmd=-e + +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default=Disabled +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default.build.zigbee_mode= +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default.build.zigbee_libs= +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed=Zigbee ED (end device) +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +# SparkFun Pro Micro ESP32C3 + +sparkfun_pro_micro_esp32c3.name=SparkFun Pro Micro - ESP32C3 +sparkfun_pro_micro_esp32c3.vid.0=0x1B4F +sparkfun_pro_micro_esp32c3.pid.0=0x0035 + +sparkfun_pro_micro_esp32c3.bootloader.tool=esptool_py +sparkfun_pro_micro_esp32c3.bootloader.tool.default=esptool_py + +sparkfun_pro_micro_esp32c3.upload.tool=esptool_py +sparkfun_pro_micro_esp32c3.upload.tool.default=esptool_py +sparkfun_pro_micro_esp32c3.upload.tool.network=esp_ota + +sparkfun_pro_micro_esp32c3.upload.maximum_size=1310720 +sparkfun_pro_micro_esp32c3.upload.maximum_data_size=327680 +sparkfun_pro_micro_esp32c3.upload.flags= +sparkfun_pro_micro_esp32c3.upload.extra_flags= +sparkfun_pro_micro_esp32c3.upload.use_1200bps_touch=false +sparkfun_pro_micro_esp32c3.upload.wait_for_upload_port=false + +sparkfun_pro_micro_esp32c3.serial.disableDTR=false +sparkfun_pro_micro_esp32c3.serial.disableRTS=false + +sparkfun_pro_micro_esp32c3.build.tarch=riscv32 +sparkfun_pro_micro_esp32c3.build.bootloader_addr=0x0 +sparkfun_pro_micro_esp32c3.build.target=esp +sparkfun_pro_micro_esp32c3.build.mcu=esp32c3 +sparkfun_pro_micro_esp32c3.build.core=esp32 +sparkfun_pro_micro_esp32c3.build.variant=sparkfun_pro_micro_esp32c3 +sparkfun_pro_micro_esp32c3.build.board=SPARKFUN_PRO_MICRO_ESP32C3 + +sparkfun_pro_micro_esp32c3.build.cdc_on_boot=1 +sparkfun_pro_micro_esp32c3.build.f_cpu=160000000L +sparkfun_pro_micro_esp32c3.build.flash_size=4MB +sparkfun_pro_micro_esp32c3.build.flash_freq=80m +sparkfun_pro_micro_esp32c3.build.flash_mode=dio +sparkfun_pro_micro_esp32c3.build.boot=qio +sparkfun_pro_micro_esp32c3.build.partitions=default +sparkfun_pro_micro_esp32c3.build.defines= + +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.default=Disabled +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external=FTDI Adapter +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.cdc=Enabled +sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.default=Enabled +sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.default.build.partitions=default +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sparkfun_pro_micro_esp32c3.menu.CPUFreq.160=160MHz (WiFi) +sparkfun_pro_micro_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L +sparkfun_pro_micro_esp32c3.menu.CPUFreq.80=80MHz (WiFi) +sparkfun_pro_micro_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L +sparkfun_pro_micro_esp32c3.menu.CPUFreq.40=40MHz +sparkfun_pro_micro_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L +sparkfun_pro_micro_esp32c3.menu.CPUFreq.20=20MHz +sparkfun_pro_micro_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L +sparkfun_pro_micro_esp32c3.menu.CPUFreq.10=10MHz +sparkfun_pro_micro_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +sparkfun_pro_micro_esp32c3.menu.FlashMode.qio=QIO +sparkfun_pro_micro_esp32c3.menu.FlashMode.qio.build.flash_mode=dio +sparkfun_pro_micro_esp32c3.menu.FlashMode.qio.build.boot=qio +sparkfun_pro_micro_esp32c3.menu.FlashMode.dio=DIO +sparkfun_pro_micro_esp32c3.menu.FlashMode.dio.build.flash_mode=dio +sparkfun_pro_micro_esp32c3.menu.FlashMode.dio.build.boot=dio +sparkfun_pro_micro_esp32c3.menu.FlashMode.qout=QOUT +sparkfun_pro_micro_esp32c3.menu.FlashMode.qout.build.flash_mode=dout +sparkfun_pro_micro_esp32c3.menu.FlashMode.qout.build.boot=qout +sparkfun_pro_micro_esp32c3.menu.FlashMode.dout=DOUT +sparkfun_pro_micro_esp32c3.menu.FlashMode.dout.build.flash_mode=dout +sparkfun_pro_micro_esp32c3.menu.FlashMode.dout.build.boot=dout + +sparkfun_pro_micro_esp32c3.menu.FlashFreq.80=80MHz +sparkfun_pro_micro_esp32c3.menu.FlashFreq.80.build.flash_freq=80m +sparkfun_pro_micro_esp32c3.menu.FlashFreq.40=40MHz +sparkfun_pro_micro_esp32c3.menu.FlashFreq.40.build.flash_freq=40m + +sparkfun_pro_micro_esp32c3.menu.FlashSize.4M=4MB (32Mb) +sparkfun_pro_micro_esp32c3.menu.FlashSize.4M.build.flash_size=4MB + +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.921600=921600 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.921600.upload.speed=921600 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.115200=115200 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.115200.upload.speed=115200 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.256000.windows=256000 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.256000.upload.speed=256000 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400=230400 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400.upload.speed=230400 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.linux=460800 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.macosx=460800 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.upload.speed=460800 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.512000.windows=512000 +sparkfun_pro_micro_esp32c3.menu.UploadSpeed.512000.upload.speed=512000 + +sparkfun_pro_micro_esp32c3.menu.DebugLevel.none=None +sparkfun_pro_micro_esp32c3.menu.DebugLevel.none.build.code_debug=0 +sparkfun_pro_micro_esp32c3.menu.DebugLevel.error=Error +sparkfun_pro_micro_esp32c3.menu.DebugLevel.error.build.code_debug=1 +sparkfun_pro_micro_esp32c3.menu.DebugLevel.warn=Warn +sparkfun_pro_micro_esp32c3.menu.DebugLevel.warn.build.code_debug=2 +sparkfun_pro_micro_esp32c3.menu.DebugLevel.info=Info +sparkfun_pro_micro_esp32c3.menu.DebugLevel.info.build.code_debug=3 +sparkfun_pro_micro_esp32c3.menu.DebugLevel.debug=Debug +sparkfun_pro_micro_esp32c3.menu.DebugLevel.debug.build.code_debug=4 +sparkfun_pro_micro_esp32c3.menu.DebugLevel.verbose=Verbose +sparkfun_pro_micro_esp32c3.menu.DebugLevel.verbose.build.code_debug=5 + +sparkfun_pro_micro_esp32c3.menu.EraseFlash.none=Disabled +sparkfun_pro_micro_esp32c3.menu.EraseFlash.none.upload.erase_cmd= +sparkfun_pro_micro_esp32c3.menu.EraseFlash.all=Enabled +sparkfun_pro_micro_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nina_w10.name=u-blox NINA-W10 series (ESP32) + +nina_w10.bootloader.tool=esptool_py +nina_w10.bootloader.tool.default=esptool_py + +nina_w10.upload.tool=esptool_py +nina_w10.upload.tool.default=esptool_py +nina_w10.upload.tool.network=esp_ota + +nina_w10.upload.maximum_size=1310720 +nina_w10.upload.maximum_data_size=327680 +nina_w10.upload.flags= +nina_w10.upload.extra_flags= + +nina_w10.serial.disableDTR=true +nina_w10.serial.disableRTS=true + +nina_w10.build.tarch=xtensa +nina_w10.build.bootloader_addr=0x1000 +nina_w10.build.target=esp32 +nina_w10.build.mcu=esp32 +nina_w10.build.core=esp32 +nina_w10.build.variant=nina_w10 +nina_w10.build.board=UBLOX_NINA_W10 +nina_w10.build.f_cpu=240000000L +nina_w10.build.boot=dio +nina_w10.build.partitions=minimal +nina_w10.build.flash_mode=dio +nina_w10.build.flash_size=2MB +nina_w10.build.flash_freq=40m +nina_w10.build.defines= +nina_w10.build.extra_libs= +nina_w10.build.loop_core= +nina_w10.build.event_core= + +nina_w10.menu.UploadSpeed.921600=921600 +nina_w10.menu.UploadSpeed.921600.upload.speed=921600 +nina_w10.menu.UploadSpeed.115200=115200 +nina_w10.menu.UploadSpeed.115200.upload.speed=115200 +nina_w10.menu.UploadSpeed.256000.windows=256000 +nina_w10.menu.UploadSpeed.256000.upload.speed=256000 +nina_w10.menu.UploadSpeed.230400.windows.upload.speed=256000 +nina_w10.menu.UploadSpeed.230400=230400 +nina_w10.menu.UploadSpeed.230400.upload.speed=230400 +nina_w10.menu.UploadSpeed.460800.linux=460800 +nina_w10.menu.UploadSpeed.460800.macosx=460800 +nina_w10.menu.UploadSpeed.460800.upload.speed=460800 +nina_w10.menu.UploadSpeed.512000.windows=512000 +nina_w10.menu.UploadSpeed.512000.upload.speed=512000 + +nina_w10.menu.FlashSize.2M=2MB (16Mb, NINA-W101/W102) +nina_w10.menu.FlashSize.2M.build.flash_size=2MB +nina_w10.menu.FlashSize.4M=4MB (32Mb, NINA-W106-00B) +nina_w10.menu.FlashSize.4M.build.flash_size=4MB +nina_w10.menu.FlashSize.8M=8MB (64Mb, NINA-W106-10B) +nina_w10.menu.FlashSize.8M.build.flash_size=8MB + +nina_w10.menu.FlashFreq.80=80MHz +nina_w10.menu.FlashFreq.80.build.flash_freq=80m +nina_w10.menu.FlashFreq.40=40MHz +nina_w10.menu.FlashFreq.40.build.flash_freq=40m + +nina_w10.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +nina_w10.menu.PartitionScheme.minimal.build.partitions=minimal +nina_w10.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +nina_w10.menu.PartitionScheme.default.build.partitions=default +nina_w10.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +nina_w10.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +nina_w10.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +nina_w10.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +nina_w10.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +nina_w10.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +nina_w10.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +nina_w10.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +nina_w10.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +nina_w10.menu.PartitionScheme.no_ota.build.partitions=no_ota +nina_w10.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +nina_w10.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +nina_w10.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +nina_w10.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +nina_w10.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +nina_w10.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +nina_w10.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +nina_w10.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +nina_w10.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +nina_w10.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +nina_w10.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +nina_w10.menu.PartitionScheme.huge_app.build.partitions=huge_app +nina_w10.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +nina_w10.menu.PartitionScheme.rainmaker=RainMaker 4MB +nina_w10.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +nina_w10.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +nina_w10.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +nina_w10.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +nina_w10.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +nina_w10.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +nina_w10.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +nina_w10.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +nina_w10.menu.CPUFreq.240=240MHz (WiFi/BT) +nina_w10.menu.CPUFreq.240.build.f_cpu=240000000L +nina_w10.menu.CPUFreq.160=160MHz (WiFi/BT) +nina_w10.menu.CPUFreq.160.build.f_cpu=160000000L +nina_w10.menu.CPUFreq.80=80MHz (WiFi/BT) +nina_w10.menu.CPUFreq.80.build.f_cpu=80000000L +nina_w10.menu.CPUFreq.40=40MHz (40MHz XTAL) +nina_w10.menu.CPUFreq.40.build.f_cpu=40000000L +nina_w10.menu.CPUFreq.26=26MHz (26MHz XTAL) +nina_w10.menu.CPUFreq.26.build.f_cpu=26000000L +nina_w10.menu.CPUFreq.20=20MHz (40MHz XTAL) +nina_w10.menu.CPUFreq.20.build.f_cpu=20000000L +nina_w10.menu.CPUFreq.13=13MHz (26MHz XTAL) +nina_w10.menu.CPUFreq.13.build.f_cpu=13000000L +nina_w10.menu.CPUFreq.10=10MHz (40MHz XTAL) +nina_w10.menu.CPUFreq.10.build.f_cpu=10000000L + +nina_w10.menu.LoopCore.1=Core 1 +nina_w10.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +nina_w10.menu.LoopCore.0=Core 0 +nina_w10.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +nina_w10.menu.EventsCore.1=Core 1 +nina_w10.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +nina_w10.menu.EventsCore.0=Core 0 +nina_w10.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +nina_w10.menu.DebugLevel.none=None +nina_w10.menu.DebugLevel.none.build.code_debug=0 +nina_w10.menu.DebugLevel.error=Error +nina_w10.menu.DebugLevel.error.build.code_debug=1 +nina_w10.menu.DebugLevel.warn=Warn +nina_w10.menu.DebugLevel.warn.build.code_debug=2 +nina_w10.menu.DebugLevel.info=Info +nina_w10.menu.DebugLevel.info.build.code_debug=3 +nina_w10.menu.DebugLevel.debug=Debug +nina_w10.menu.DebugLevel.debug.build.code_debug=4 +nina_w10.menu.DebugLevel.verbose=Verbose +nina_w10.menu.DebugLevel.verbose.build.code_debug=5 + +nina_w10.menu.EraseFlash.none=Disabled +nina_w10.menu.EraseFlash.none.upload.erase_cmd= +nina_w10.menu.EraseFlash.all=Enabled +nina_w10.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nora_w10.name=u-blox NORA-W10 series (ESP32-S3) + +nora_w10.bootloader.tool=esptool_py +nora_w10.bootloader.tool.default=esptool_py + +nora_w10.upload.tool=esptool_py +nora_w10.upload.tool.default=esptool_py +nora_w10.upload.tool.network=esp_ota + +nora_w10.upload.maximum_size=1310720 +nora_w10.upload.maximum_data_size=327680 +nora_w10.upload.flags= +nora_w10.upload.extra_flags= +nora_w10.upload.use_1200bps_touch=false +nora_w10.upload.wait_for_upload_port=false + +nora_w10.serial.disableDTR=false +nora_w10.serial.disableRTS=false + +nora_w10.build.tarch=xtensa +nora_w10.build.bootloader_addr=0x0 +nora_w10.build.target=esp32s3 +nora_w10.build.mcu=esp32s3 +nora_w10.build.core=esp32 +nora_w10.build.variant=nora_w10 +nora_w10.build.board=UBLOX_NORA_W10 + +nora_w10.build.usb_mode=1 +nora_w10.build.cdc_on_boot=0 +nora_w10.build.msc_on_boot=0 +nora_w10.build.dfu_on_boot=0 +nora_w10.build.f_cpu=240000000L +nora_w10.build.flash_size=4MB +nora_w10.build.flash_freq=80m +nora_w10.build.flash_mode=dio +nora_w10.build.boot=qio +nora_w10.build.boot_freq=80m +nora_w10.build.partitions=default +nora_w10.build.defines= +nora_w10.build.loop_core= +nora_w10.build.event_core= +nora_w10.build.psram_type=qspi +nora_w10.build.memory_type={build.boot}_{build.psram_type} + +nora_w10.menu.PSRAM.disabled=Disabled +nora_w10.menu.PSRAM.disabled.build.defines= +nora_w10.menu.PSRAM.disabled.build.psram_type=qspi +nora_w10.menu.PSRAM.enabled=QSPI PSRAM +nora_w10.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +nora_w10.menu.PSRAM.enabled.build.psram_type=qspi +nora_w10.menu.PSRAM.opi=OPI PSRAM +nora_w10.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +nora_w10.menu.PSRAM.opi.build.psram_type=opi + +nora_w10.menu.FlashMode.qio=QIO 80MHz +nora_w10.menu.FlashMode.qio.build.flash_mode=dio +nora_w10.menu.FlashMode.qio.build.boot=qio +nora_w10.menu.FlashMode.qio.build.boot_freq=80m +nora_w10.menu.FlashMode.qio.build.flash_freq=80m +nora_w10.menu.FlashMode.qio120=QIO 120MHz +nora_w10.menu.FlashMode.qio120.build.flash_mode=dio +nora_w10.menu.FlashMode.qio120.build.boot=qio +nora_w10.menu.FlashMode.qio120.build.boot_freq=120m +nora_w10.menu.FlashMode.qio120.build.flash_freq=80m +nora_w10.menu.FlashMode.dio=DIO 80MHz +nora_w10.menu.FlashMode.dio.build.flash_mode=dio +nora_w10.menu.FlashMode.dio.build.boot=dio +nora_w10.menu.FlashMode.dio.build.boot_freq=80m +nora_w10.menu.FlashMode.dio.build.flash_freq=80m +nora_w10.menu.FlashMode.opi=OPI 80MHz +nora_w10.menu.FlashMode.opi.build.flash_mode=dout +nora_w10.menu.FlashMode.opi.build.boot=opi +nora_w10.menu.FlashMode.opi.build.boot_freq=80m +nora_w10.menu.FlashMode.opi.build.flash_freq=80m + +nora_w10.menu.FlashSize.4M=4MB (32Mb) +nora_w10.menu.FlashSize.4M.build.flash_size=4MB +nora_w10.menu.FlashSize.8M=8MB (64Mb) +nora_w10.menu.FlashSize.8M.build.flash_size=8MB +#nora_w10.menu.FlashSize.16M=16MB (128Mb) +#nora_w10.menu.FlashSize.16M.build.flash_size=16MB +#nora_w10.menu.FlashSize.32M=32MB (256Mb) +#nora_w10.menu.FlashSize.32M.build.flash_size=32MB + +nora_w10.menu.LoopCore.1=Core 1 +nora_w10.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +nora_w10.menu.LoopCore.0=Core 0 +nora_w10.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +nora_w10.menu.EventsCore.1=Core 1 +nora_w10.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +nora_w10.menu.EventsCore.0=Core 0 +nora_w10.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +nora_w10.menu.USBMode.hwcdc=Hardware CDC and JTAG +nora_w10.menu.USBMode.hwcdc.build.usb_mode=1 +nora_w10.menu.USBMode.default=USB-OTG (TinyUSB) +nora_w10.menu.USBMode.default.build.usb_mode=0 + +nora_w10.menu.CDCOnBoot.default=Disabled +nora_w10.menu.CDCOnBoot.default.build.cdc_on_boot=0 +nora_w10.menu.CDCOnBoot.cdc=Enabled +nora_w10.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +nora_w10.menu.MSCOnBoot.default=Disabled +nora_w10.menu.MSCOnBoot.default.build.msc_on_boot=0 +nora_w10.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +nora_w10.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +nora_w10.menu.DFUOnBoot.default=Disabled +nora_w10.menu.DFUOnBoot.default.build.dfu_on_boot=0 +nora_w10.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +nora_w10.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +nora_w10.menu.UploadMode.default=UART0 / Hardware CDC +nora_w10.menu.UploadMode.default.upload.use_1200bps_touch=false +nora_w10.menu.UploadMode.default.upload.wait_for_upload_port=false +nora_w10.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +nora_w10.menu.UploadMode.cdc.upload.use_1200bps_touch=true +nora_w10.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +nora_w10.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +nora_w10.menu.PartitionScheme.default.build.partitions=default +nora_w10.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +nora_w10.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +nora_w10.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT) +nora_w10.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +nora_w10.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +nora_w10.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +nora_w10.menu.PartitionScheme.minimal.build.partitions=minimal +nora_w10.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +nora_w10.menu.PartitionScheme.no_ota.build.partitions=no_ota +nora_w10.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +nora_w10.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +nora_w10.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +nora_w10.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +nora_w10.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +nora_w10.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +nora_w10.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +nora_w10.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +nora_w10.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +nora_w10.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +nora_w10.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +nora_w10.menu.PartitionScheme.huge_app.build.partitions=huge_app +nora_w10.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +nora_w10.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +nora_w10.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +nora_w10.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +#nora_w10.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +#nora_w10.menu.PartitionScheme.fatflash.build.partitions=ffat +#nora_w10.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +nora_w10.menu.PartitionScheme.rainmaker=RainMaker 4MB +nora_w10.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +nora_w10.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +nora_w10.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +nora_w10.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +nora_w10.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +nora_w10.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +nora_w10.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +nora_w10.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +nora_w10.menu.CPUFreq.240=240MHz (WiFi) +nora_w10.menu.CPUFreq.240.build.f_cpu=240000000L +nora_w10.menu.CPUFreq.160=160MHz (WiFi) +nora_w10.menu.CPUFreq.160.build.f_cpu=160000000L +nora_w10.menu.CPUFreq.80=80MHz (WiFi) +nora_w10.menu.CPUFreq.80.build.f_cpu=80000000L +nora_w10.menu.CPUFreq.40=40MHz +nora_w10.menu.CPUFreq.40.build.f_cpu=40000000L +nora_w10.menu.CPUFreq.20=20MHz +nora_w10.menu.CPUFreq.20.build.f_cpu=20000000L +nora_w10.menu.CPUFreq.10=10MHz +nora_w10.menu.CPUFreq.10.build.f_cpu=10000000L + +nora_w10.menu.UploadSpeed.921600=921600 +nora_w10.menu.UploadSpeed.921600.upload.speed=921600 +nora_w10.menu.UploadSpeed.115200=115200 +nora_w10.menu.UploadSpeed.115200.upload.speed=115200 +nora_w10.menu.UploadSpeed.256000.windows=256000 +nora_w10.menu.UploadSpeed.256000.upload.speed=256000 +nora_w10.menu.UploadSpeed.230400.windows.upload.speed=256000 +nora_w10.menu.UploadSpeed.230400=230400 +nora_w10.menu.UploadSpeed.230400.upload.speed=230400 +nora_w10.menu.UploadSpeed.460800.linux=460800 +nora_w10.menu.UploadSpeed.460800.macosx=460800 +nora_w10.menu.UploadSpeed.460800.upload.speed=460800 +nora_w10.menu.UploadSpeed.512000.windows=512000 +nora_w10.menu.UploadSpeed.512000.upload.speed=512000 + +nora_w10.menu.DebugLevel.none=None +nora_w10.menu.DebugLevel.none.build.code_debug=0 +nora_w10.menu.DebugLevel.error=Error +nora_w10.menu.DebugLevel.error.build.code_debug=1 +nora_w10.menu.DebugLevel.warn=Warn +nora_w10.menu.DebugLevel.warn.build.code_debug=2 +nora_w10.menu.DebugLevel.info=Info +nora_w10.menu.DebugLevel.info.build.code_debug=3 +nora_w10.menu.DebugLevel.debug=Debug +nora_w10.menu.DebugLevel.debug.build.code_debug=4 +nora_w10.menu.DebugLevel.verbose=Verbose +nora_w10.menu.DebugLevel.verbose.build.code_debug=5 + +nora_w10.menu.EraseFlash.none=Disabled +nora_w10.menu.EraseFlash.none.upload.erase_cmd= +nora_w10.menu.EraseFlash.all=Enabled +nora_w10.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +widora-air.name=Widora AIR + +widora-air.bootloader.tool=esptool_py +widora-air.bootloader.tool.default=esptool_py + +widora-air.upload.tool=esptool_py +widora-air.upload.tool.default=esptool_py +widora-air.upload.tool.network=esp_ota + +widora-air.upload.maximum_size=1310720 +widora-air.upload.maximum_data_size=327680 +widora-air.upload.flags= +widora-air.upload.extra_flags= + +widora-air.serial.disableDTR=true +widora-air.serial.disableRTS=true + +widora-air.build.tarch=xtensa +widora-air.build.bootloader_addr=0x1000 +widora-air.build.target=esp32 +widora-air.build.mcu=esp32 +widora-air.build.core=esp32 +widora-air.build.variant=widora-air +widora-air.build.board=WIDORA_AIR + +widora-air.build.f_cpu=240000000L +widora-air.build.flash_mode=dio +widora-air.build.flash_size=16MB +widora-air.build.boot=dio +widora-air.build.partitions=default +widora-air.build.defines= + +widora-air.menu.FlashFreq.80=80MHz +widora-air.menu.FlashFreq.80.build.flash_freq=80m +widora-air.menu.FlashFreq.40=40MHz +widora-air.menu.FlashFreq.40.build.flash_freq=40m + +widora-air.menu.UploadSpeed.921600=921600 +widora-air.menu.UploadSpeed.921600.upload.speed=921600 +widora-air.menu.UploadSpeed.115200=115200 +widora-air.menu.UploadSpeed.115200.upload.speed=115200 +widora-air.menu.UploadSpeed.256000.windows=256000 +widora-air.menu.UploadSpeed.256000.upload.speed=256000 +widora-air.menu.UploadSpeed.230400.windows.upload.speed=256000 +widora-air.menu.UploadSpeed.230400=230400 +widora-air.menu.UploadSpeed.230400.upload.speed=230400 +widora-air.menu.UploadSpeed.460800.linux=460800 +widora-air.menu.UploadSpeed.460800.macosx=460800 +widora-air.menu.UploadSpeed.460800.upload.speed=460800 +widora-air.menu.UploadSpeed.512000.windows=512000 +widora-air.menu.UploadSpeed.512000.upload.speed=512000 + +widora-air.menu.DebugLevel.none=None +widora-air.menu.DebugLevel.none.build.code_debug=0 +widora-air.menu.DebugLevel.error=Error +widora-air.menu.DebugLevel.error.build.code_debug=1 +widora-air.menu.DebugLevel.warn=Warn +widora-air.menu.DebugLevel.warn.build.code_debug=2 +widora-air.menu.DebugLevel.info=Info +widora-air.menu.DebugLevel.info.build.code_debug=3 +widora-air.menu.DebugLevel.debug=Debug +widora-air.menu.DebugLevel.debug.build.code_debug=4 +widora-air.menu.DebugLevel.verbose=Verbose +widora-air.menu.DebugLevel.verbose.build.code_debug=5 + +widora-air.menu.EraseFlash.none=Disabled +widora-air.menu.EraseFlash.none.upload.erase_cmd= +widora-air.menu.EraseFlash.all=Enabled +widora-air.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp320.name=Electronic SweetPeas - ESP320 + +esp320.bootloader.tool=esptool_py +esp320.bootloader.tool.default=esptool_py + +esp320.upload.tool=esptool_py +esp320.upload.tool.default=esptool_py +esp320.upload.tool.network=esp_ota + +esp320.upload.maximum_size=1310720 +esp320.upload.maximum_data_size=327680 +esp320.upload.flags= +esp320.upload.extra_flags= + +esp320.serial.disableDTR=true +esp320.serial.disableRTS=true + +esp320.build.tarch=xtensa +esp320.build.bootloader_addr=0x1000 +esp320.build.target=esp32 +esp320.build.mcu=esp32 +esp320.build.core=esp32 +esp320.build.variant=esp320 +esp320.build.board=ESP320 + +esp320.build.f_cpu=240000000L +esp320.build.flash_mode=qio +esp320.build.flash_size=4MB +esp320.build.boot=dio +esp320.build.partitions=default +esp320.build.defines= + +esp320.menu.FlashFreq.80=80MHz +esp320.menu.FlashFreq.80.build.flash_freq=80m +esp320.menu.FlashFreq.40=40MHz +esp320.menu.FlashFreq.40.build.flash_freq=40m + +esp320.menu.UploadSpeed.921600=921600 +esp320.menu.UploadSpeed.921600.upload.speed=921600 +esp320.menu.UploadSpeed.115200=115200 +esp320.menu.UploadSpeed.115200.upload.speed=115200 +esp320.menu.UploadSpeed.256000.windows=256000 +esp320.menu.UploadSpeed.256000.upload.speed=256000 +esp320.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp320.menu.UploadSpeed.230400=230400 +esp320.menu.UploadSpeed.230400.upload.speed=230400 +esp320.menu.UploadSpeed.460800.linux=460800 +esp320.menu.UploadSpeed.460800.macosx=460800 +esp320.menu.UploadSpeed.460800.upload.speed=460800 +esp320.menu.UploadSpeed.512000.windows=512000 +esp320.menu.UploadSpeed.512000.upload.speed=512000 + +esp320.menu.DebugLevel.none=None +esp320.menu.DebugLevel.none.build.code_debug=0 +esp320.menu.DebugLevel.error=Error +esp320.menu.DebugLevel.error.build.code_debug=1 +esp320.menu.DebugLevel.warn=Warn +esp320.menu.DebugLevel.warn.build.code_debug=2 +esp320.menu.DebugLevel.info=Info +esp320.menu.DebugLevel.info.build.code_debug=3 +esp320.menu.DebugLevel.debug=Debug +esp320.menu.DebugLevel.debug.build.code_debug=4 +esp320.menu.DebugLevel.verbose=Verbose +esp320.menu.DebugLevel.verbose.build.code_debug=5 + +esp320.menu.EraseFlash.none=Disabled +esp320.menu.EraseFlash.none.upload.erase_cmd= +esp320.menu.EraseFlash.all=Enabled +esp320.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nano32.name=Nano32 + +nano32.bootloader.tool=esptool_py +nano32.bootloader.tool.default=esptool_py + +nano32.upload.tool=esptool_py +nano32.upload.tool.default=esptool_py +nano32.upload.tool.network=esp_ota + +nano32.upload.maximum_size=1310720 +nano32.upload.maximum_data_size=327680 +nano32.upload.flags= +nano32.upload.extra_flags= + +nano32.serial.disableDTR=true +nano32.serial.disableRTS=true + +nano32.build.tarch=xtensa +nano32.build.bootloader_addr=0x1000 +nano32.build.target=esp32 +nano32.build.mcu=esp32 +nano32.build.core=esp32 +nano32.build.variant=nano32 +nano32.build.board=NANO32 + +nano32.build.f_cpu=240000000L +nano32.build.flash_mode=dio +nano32.build.flash_size=4MB +nano32.build.boot=dio +nano32.build.partitions=default +nano32.build.defines= + +nano32.menu.FlashFreq.80=80MHz +nano32.menu.FlashFreq.80.build.flash_freq=80m +nano32.menu.FlashFreq.40=40MHz +nano32.menu.FlashFreq.40.build.flash_freq=40m + +nano32.menu.UploadSpeed.921600=921600 +nano32.menu.UploadSpeed.921600.upload.speed=921600 +nano32.menu.UploadSpeed.115200=115200 +nano32.menu.UploadSpeed.115200.upload.speed=115200 +nano32.menu.UploadSpeed.256000.windows=256000 +nano32.menu.UploadSpeed.256000.upload.speed=256000 +nano32.menu.UploadSpeed.230400.windows.upload.speed=256000 +nano32.menu.UploadSpeed.230400=230400 +nano32.menu.UploadSpeed.230400.upload.speed=230400 +nano32.menu.UploadSpeed.460800.linux=460800 +nano32.menu.UploadSpeed.460800.macosx=460800 +nano32.menu.UploadSpeed.460800.upload.speed=460800 +nano32.menu.UploadSpeed.512000.windows=512000 +nano32.menu.UploadSpeed.512000.upload.speed=512000 + +nano32.menu.DebugLevel.none=None +nano32.menu.DebugLevel.none.build.code_debug=0 +nano32.menu.DebugLevel.error=Error +nano32.menu.DebugLevel.error.build.code_debug=1 +nano32.menu.DebugLevel.warn=Warn +nano32.menu.DebugLevel.warn.build.code_debug=2 +nano32.menu.DebugLevel.info=Info +nano32.menu.DebugLevel.info.build.code_debug=3 +nano32.menu.DebugLevel.debug=Debug +nano32.menu.DebugLevel.debug.build.code_debug=4 +nano32.menu.DebugLevel.verbose=Verbose +nano32.menu.DebugLevel.verbose.build.code_debug=5 + +nano32.menu.EraseFlash.none=Disabled +nano32.menu.EraseFlash.none.upload.erase_cmd= +nano32.menu.EraseFlash.all=Enabled +nano32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +d32.name=LOLIN D32 + +d32.bootloader.tool=esptool_py +d32.bootloader.tool.default=esptool_py + +d32.upload.tool=esptool_py +d32.upload.tool.default=esptool_py +d32.upload.tool.network=esp_ota + +d32.upload.maximum_size=1310720 +d32.upload.maximum_data_size=327680 +d32.upload.flags= +d32.upload.extra_flags= + +d32.serial.disableDTR=true +d32.serial.disableRTS=true + +d32.build.tarch=xtensa +d32.build.bootloader_addr=0x1000 +d32.build.target=esp32 +d32.build.mcu=esp32 +d32.build.core=esp32 +d32.build.variant=d32 +d32.build.board=LOLIN_D32 + +d32.build.f_cpu=240000000L +d32.build.flash_size=4MB +d32.build.flash_freq=40m +d32.build.flash_mode=dio +d32.build.boot=dio +d32.build.partitions=default +d32.build.defines= + +d32.menu.PartitionScheme.default=Default +d32.menu.PartitionScheme.default.build.partitions=default +d32.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +d32.menu.PartitionScheme.minimal.build.partitions=minimal +d32.menu.PartitionScheme.no_ota=No OTA (Large APP) +d32.menu.PartitionScheme.no_ota.build.partitions=no_ota +d32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +d32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +d32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +d32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +d32.menu.FlashFreq.80=80MHz +d32.menu.FlashFreq.80.build.flash_freq=80m +d32.menu.FlashFreq.40=40MHz +d32.menu.FlashFreq.40.build.flash_freq=40m + +d32.menu.UploadSpeed.921600=921600 +d32.menu.UploadSpeed.921600.upload.speed=921600 +d32.menu.UploadSpeed.115200=115200 +d32.menu.UploadSpeed.115200.upload.speed=115200 +d32.menu.UploadSpeed.256000.windows=256000 +d32.menu.UploadSpeed.256000.upload.speed=256000 +d32.menu.UploadSpeed.230400.windows.upload.speed=256000 +d32.menu.UploadSpeed.230400=230400 +d32.menu.UploadSpeed.230400.upload.speed=230400 +d32.menu.UploadSpeed.460800.linux=460800 +d32.menu.UploadSpeed.460800.macosx=460800 +d32.menu.UploadSpeed.460800.upload.speed=460800 +d32.menu.UploadSpeed.512000.windows=512000 +d32.menu.UploadSpeed.512000.upload.speed=512000 + +d32.menu.DebugLevel.none=None +d32.menu.DebugLevel.none.build.code_debug=0 +d32.menu.DebugLevel.error=Error +d32.menu.DebugLevel.error.build.code_debug=1 +d32.menu.DebugLevel.warn=Warn +d32.menu.DebugLevel.warn.build.code_debug=2 +d32.menu.DebugLevel.info=Info +d32.menu.DebugLevel.info.build.code_debug=3 +d32.menu.DebugLevel.debug=Debug +d32.menu.DebugLevel.debug.build.code_debug=4 +d32.menu.DebugLevel.verbose=Verbose +d32.menu.DebugLevel.verbose.build.code_debug=5 + +d32.menu.EraseFlash.none=Disabled +d32.menu.EraseFlash.none.upload.erase_cmd= +d32.menu.EraseFlash.all=Enabled +d32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +d32_pro.name=LOLIN D32 PRO + +d32_pro.bootloader.tool=esptool_py +d32_pro.bootloader.tool.default=esptool_py + +d32_pro.upload.tool=esptool_py +d32_pro.upload.tool.default=esptool_py +d32_pro.upload.tool.network=esp_ota + +d32_pro.upload.maximum_size=1310720 +d32_pro.upload.maximum_data_size=327680 +d32_pro.upload.flags= +d32_pro.upload.extra_flags= + +d32_pro.serial.disableDTR=true +d32_pro.serial.disableRTS=true + +d32_pro.build.tarch=xtensa +d32_pro.build.bootloader_addr=0x1000 +d32_pro.build.target=esp32 +d32_pro.build.mcu=esp32 +d32_pro.build.core=esp32 +d32_pro.build.variant=d32_pro +d32_pro.build.board=LOLIN_D32_PRO + +d32_pro.build.f_cpu=240000000L +d32_pro.build.flash_size=4MB +d32_pro.build.flash_freq=40m +d32_pro.build.flash_mode=dio +d32_pro.build.boot=dio +d32_pro.build.partitions=default +d32_pro.build.defines= + +d32_pro.menu.PSRAM.disabled=Disabled +d32_pro.menu.PSRAM.disabled.build.defines= +d32_pro.menu.PSRAM.disabled.build.extra_libs= +d32_pro.menu.PSRAM.enabled=Enabled +d32_pro.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +d32_pro.menu.PSRAM.enabled.build.extra_libs= + +d32_pro.menu.PartitionScheme.default=Default +d32_pro.menu.PartitionScheme.default.build.partitions=default +d32_pro.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +d32_pro.menu.PartitionScheme.minimal.build.partitions=minimal +d32_pro.menu.PartitionScheme.no_ota=No OTA (Large APP) +d32_pro.menu.PartitionScheme.no_ota.build.partitions=no_ota +d32_pro.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +d32_pro.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +d32_pro.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +d32_pro.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +d32_pro.menu.FlashFreq.80=80MHz +d32_pro.menu.FlashFreq.80.build.flash_freq=80m +d32_pro.menu.FlashFreq.40=40MHz +d32_pro.menu.FlashFreq.40.build.flash_freq=40m + +d32_pro.menu.UploadSpeed.921600=921600 +d32_pro.menu.UploadSpeed.921600.upload.speed=921600 +d32_pro.menu.UploadSpeed.115200=115200 +d32_pro.menu.UploadSpeed.115200.upload.speed=115200 +d32_pro.menu.UploadSpeed.256000.windows=256000 +d32_pro.menu.UploadSpeed.256000.upload.speed=256000 +d32_pro.menu.UploadSpeed.230400.windows.upload.speed=256000 +d32_pro.menu.UploadSpeed.230400=230400 +d32_pro.menu.UploadSpeed.230400.upload.speed=230400 +d32_pro.menu.UploadSpeed.460800.linux=460800 +d32_pro.menu.UploadSpeed.460800.macosx=460800 +d32_pro.menu.UploadSpeed.460800.upload.speed=460800 +d32_pro.menu.UploadSpeed.512000.windows=512000 +d32_pro.menu.UploadSpeed.512000.upload.speed=512000 +d32_pro.menu.UploadSpeed.1500000=1500000 +d32_pro.menu.UploadSpeed.1500000.upload.speed=1500000 + +d32_pro.menu.DebugLevel.none=None +d32_pro.menu.DebugLevel.none.build.code_debug=0 +d32_pro.menu.DebugLevel.error=Error +d32_pro.menu.DebugLevel.error.build.code_debug=1 +d32_pro.menu.DebugLevel.warn=Warn +d32_pro.menu.DebugLevel.warn.build.code_debug=2 +d32_pro.menu.DebugLevel.info=Info +d32_pro.menu.DebugLevel.info.build.code_debug=3 +d32_pro.menu.DebugLevel.debug=Debug +d32_pro.menu.DebugLevel.debug.build.code_debug=4 +d32_pro.menu.DebugLevel.verbose=Verbose +d32_pro.menu.DebugLevel.verbose.build.code_debug=5 + +d32_pro.menu.EraseFlash.none=Disabled +d32_pro.menu.EraseFlash.none.upload.erase_cmd= +d32_pro.menu.EraseFlash.all=Enabled +d32_pro.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_c3_mini.name=LOLIN C3 Mini + +lolin_c3_mini.bootloader.tool=esptool_py +lolin_c3_mini.bootloader.tool.default=esptool_py + +lolin_c3_mini.upload.tool=esptool_py +lolin_c3_mini.upload.tool.default=esptool_py +lolin_c3_mini.upload.tool.network=esp_ota + +lolin_c3_mini.upload.maximum_size=1310720 +lolin_c3_mini.upload.maximum_data_size=327680 +lolin_c3_mini.upload.flags= +lolin_c3_mini.upload.extra_flags= +lolin_c3_mini.upload.use_1200bps_touch=false +lolin_c3_mini.upload.wait_for_upload_port=false + +lolin_c3_mini.serial.disableDTR=true +lolin_c3_mini.serial.disableRTS=true + +lolin_c3_mini.build.tarch=riscv32 +lolin_c3_mini.build.target=esp +lolin_c3_mini.build.mcu=esp32c3 +lolin_c3_mini.build.core=esp32 +lolin_c3_mini.build.variant=lolin_c3_mini +lolin_c3_mini.build.board=LOLIN_C3_MINI +lolin_c3_mini.build.bootloader_addr=0x0 + +lolin_c3_mini.build.cdc_on_boot=1 +lolin_c3_mini.build.f_cpu=160000000L +lolin_c3_mini.build.flash_size=4MB +lolin_c3_mini.build.flash_freq=80m +lolin_c3_mini.build.flash_mode=dio +lolin_c3_mini.build.boot=qio +lolin_c3_mini.build.partitions=default +lolin_c3_mini.build.defines= + +lolin_c3_mini.menu.CDCOnBoot.default=Enabled +lolin_c3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +lolin_c3_mini.menu.CDCOnBoot.dis_cdc=Disabled +lolin_c3_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +lolin_c3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_c3_mini.menu.PartitionScheme.default.build.partitions=default +lolin_c3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_c3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_c3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_c3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_c3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_c3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_c3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_c3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_c3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_c3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_c3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_c3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_c3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_c3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_c3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_c3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_c3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + + +lolin_c3_mini.menu.CPUFreq.160=160MHz (WiFi) +lolin_c3_mini.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_c3_mini.menu.CPUFreq.80=80MHz (WiFi) +lolin_c3_mini.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_c3_mini.menu.CPUFreq.40=40MHz +lolin_c3_mini.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_c3_mini.menu.CPUFreq.20=20MHz +lolin_c3_mini.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_c3_mini.menu.CPUFreq.10=10MHz +lolin_c3_mini.menu.CPUFreq.10.build.f_cpu=10000000L + + + +lolin_c3_mini.menu.FlashFreq.80=80MHz +lolin_c3_mini.menu.FlashFreq.80.build.flash_freq=80m +lolin_c3_mini.menu.FlashFreq.40=40MHz +lolin_c3_mini.menu.FlashFreq.40.build.flash_freq=40m + +lolin_c3_mini.menu.UploadSpeed.921600=921600 +lolin_c3_mini.menu.UploadSpeed.921600.upload.speed=921600 +lolin_c3_mini.menu.UploadSpeed.115200=115200 +lolin_c3_mini.menu.UploadSpeed.115200.upload.speed=115200 +lolin_c3_mini.menu.UploadSpeed.256000.windows=256000 +lolin_c3_mini.menu.UploadSpeed.256000.upload.speed=256000 +lolin_c3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_c3_mini.menu.UploadSpeed.230400=230400 +lolin_c3_mini.menu.UploadSpeed.230400.upload.speed=230400 +lolin_c3_mini.menu.UploadSpeed.460800.linux=460800 +lolin_c3_mini.menu.UploadSpeed.460800.macosx=460800 +lolin_c3_mini.menu.UploadSpeed.460800.upload.speed=460800 +lolin_c3_mini.menu.UploadSpeed.512000.windows=512000 +lolin_c3_mini.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_c3_mini.menu.DebugLevel.none=None +lolin_c3_mini.menu.DebugLevel.none.build.code_debug=0 +lolin_c3_mini.menu.DebugLevel.error=Error +lolin_c3_mini.menu.DebugLevel.error.build.code_debug=1 +lolin_c3_mini.menu.DebugLevel.warn=Warn +lolin_c3_mini.menu.DebugLevel.warn.build.code_debug=2 +lolin_c3_mini.menu.DebugLevel.info=Info +lolin_c3_mini.menu.DebugLevel.info.build.code_debug=3 +lolin_c3_mini.menu.DebugLevel.debug=Debug +lolin_c3_mini.menu.DebugLevel.debug.build.code_debug=4 +lolin_c3_mini.menu.DebugLevel.verbose=Verbose +lolin_c3_mini.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_c3_mini.menu.EraseFlash.none=Disabled +lolin_c3_mini.menu.EraseFlash.none.upload.erase_cmd= +lolin_c3_mini.menu.EraseFlash.all=Enabled +lolin_c3_mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_c3_pico.name=LOLIN C3 Pico + +lolin_c3_pico.bootloader.tool=esptool_py +lolin_c3_pico.bootloader.tool.default=esptool_py + +lolin_c3_pico.upload.tool=esptool_py +lolin_c3_pico.upload.tool.default=esptool_py +lolin_c3_pico.upload.tool.network=esp_ota + +lolin_c3_pico.upload.maximum_size=1310720 +lolin_c3_pico.upload.maximum_data_size=327680 +lolin_c3_pico.upload.flags= +lolin_c3_pico.upload.extra_flags= +lolin_c3_pico.upload.use_1200bps_touch=false +lolin_c3_pico.upload.wait_for_upload_port=false + +lolin_c3_pico.serial.disableDTR=true +lolin_c3_pico.serial.disableRTS=true + +lolin_c3_pico.build.tarch=riscv32 +lolin_c3_pico.build.target=esp +lolin_c3_pico.build.mcu=esp32c3 +lolin_c3_pico.build.core=esp32 +lolin_c3_pico.build.variant=lolin_c3_pico +lolin_c3_pico.build.board=LOLIN_C3_PICO +lolin_c3_pico.build.bootloader_addr=0x0 + +lolin_c3_pico.build.cdc_on_boot=1 +lolin_c3_pico.build.f_cpu=160000000L +lolin_c3_pico.build.flash_size=4MB +lolin_c3_pico.build.flash_freq=80m +lolin_c3_pico.build.flash_mode=dio +lolin_c3_pico.build.boot=qio +lolin_c3_pico.build.partitions=default +lolin_c3_pico.build.defines= + +lolin_c3_pico.menu.CDCOnBoot.default=Enabled +lolin_c3_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1 +lolin_c3_pico.menu.CDCOnBoot.dis_cdc=Disabled +lolin_c3_pico.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +lolin_c3_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_c3_pico.menu.PartitionScheme.default.build.partitions=default +lolin_c3_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_c3_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_c3_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_c3_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_c3_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_c3_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_c3_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_c3_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_c3_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_c3_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_c3_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_c3_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_c3_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_c3_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_c3_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_c3_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_c3_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +lolin_c3_pico.menu.CPUFreq.160=160MHz (WiFi) +lolin_c3_pico.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_c3_pico.menu.CPUFreq.80=80MHz (WiFi) +lolin_c3_pico.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_c3_pico.menu.CPUFreq.40=40MHz +lolin_c3_pico.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_c3_pico.menu.CPUFreq.20=20MHz +lolin_c3_pico.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_c3_pico.menu.CPUFreq.10=10MHz +lolin_c3_pico.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin_c3_pico.menu.FlashFreq.80=80MHz +lolin_c3_pico.menu.FlashFreq.80.build.flash_freq=80m +lolin_c3_pico.menu.FlashFreq.40=40MHz +lolin_c3_pico.menu.FlashFreq.40.build.flash_freq=40m + +lolin_c3_pico.menu.UploadSpeed.921600=921600 +lolin_c3_pico.menu.UploadSpeed.921600.upload.speed=921600 +lolin_c3_pico.menu.UploadSpeed.115200=115200 +lolin_c3_pico.menu.UploadSpeed.115200.upload.speed=115200 +lolin_c3_pico.menu.UploadSpeed.256000.windows=256000 +lolin_c3_pico.menu.UploadSpeed.256000.upload.speed=256000 +lolin_c3_pico.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_c3_pico.menu.UploadSpeed.230400=230400 +lolin_c3_pico.menu.UploadSpeed.230400.upload.speed=230400 +lolin_c3_pico.menu.UploadSpeed.460800.linux=460800 +lolin_c3_pico.menu.UploadSpeed.460800.macosx=460800 +lolin_c3_pico.menu.UploadSpeed.460800.upload.speed=460800 +lolin_c3_pico.menu.UploadSpeed.512000.windows=512000 +lolin_c3_pico.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_c3_pico.menu.DebugLevel.none=None +lolin_c3_pico.menu.DebugLevel.none.build.code_debug=0 +lolin_c3_pico.menu.DebugLevel.error=Error +lolin_c3_pico.menu.DebugLevel.error.build.code_debug=1 +lolin_c3_pico.menu.DebugLevel.warn=Warn +lolin_c3_pico.menu.DebugLevel.warn.build.code_debug=2 +lolin_c3_pico.menu.DebugLevel.info=Info +lolin_c3_pico.menu.DebugLevel.info.build.code_debug=3 +lolin_c3_pico.menu.DebugLevel.debug=Debug +lolin_c3_pico.menu.DebugLevel.debug.build.code_debug=4 +lolin_c3_pico.menu.DebugLevel.verbose=Verbose +lolin_c3_pico.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_c3_pico.menu.EraseFlash.none=Disabled +lolin_c3_pico.menu.EraseFlash.none.upload.erase_cmd= +lolin_c3_pico.menu.EraseFlash.all=Enabled +lolin_c3_pico.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s2_mini.name=LOLIN S2 Mini +lolin_s2_mini.vid.0=0x303a +lolin_s2_mini.pid.0=0x80C2 + +lolin_s2_mini.bootloader.tool=esptool_py +lolin_s2_mini.bootloader.tool.default=esptool_py + +lolin_s2_mini.upload.tool=esptool_py +lolin_s2_mini.upload.tool.default=esptool_py +lolin_s2_mini.upload.tool.network=esp_ota + +lolin_s2_mini.upload.maximum_size=1310720 +lolin_s2_mini.upload.maximum_data_size=327680 +lolin_s2_mini.upload.flags= +lolin_s2_mini.upload.extra_flags= +lolin_s2_mini.upload.use_1200bps_touch=true +lolin_s2_mini.upload.wait_for_upload_port=true +lolin_s2_mini.upload.speed=921600 + +lolin_s2_mini.serial.disableDTR=false +lolin_s2_mini.serial.disableRTS=false + +lolin_s2_mini.build.tarch=xtensa +lolin_s2_mini.build.bootloader_addr=0x1000 +lolin_s2_mini.build.target=esp32s2 +lolin_s2_mini.build.mcu=esp32s2 +lolin_s2_mini.build.core=esp32 +lolin_s2_mini.build.variant=lolin_s2_mini +lolin_s2_mini.build.board=LOLIN_S2_MINI + +lolin_s2_mini.build.cdc_on_boot=1 +lolin_s2_mini.build.msc_on_boot=1 +lolin_s2_mini.build.dfu_on_boot=1 +lolin_s2_mini.build.f_cpu=240000000L +lolin_s2_mini.build.flash_size=4MB +lolin_s2_mini.build.flash_freq=80m +lolin_s2_mini.build.flash_mode=dio +lolin_s2_mini.build.boot=qio +lolin_s2_mini.build.partitions=default +lolin_s2_mini.build.defines=-DBOARD_HAS_PSRAM + +lolin_s2_mini.menu.CDCOnBoot.default=Enabled +lolin_s2_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +lolin_s2_mini.menu.CDCOnBoot.dis_cdc=Disabled +lolin_s2_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +lolin_s2_mini.menu.MSCOnBoot.default=Disabled +lolin_s2_mini.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s2_mini.menu.MSCOnBoot.msc=Enabled +lolin_s2_mini.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s2_mini.menu.DFUOnBoot.default=Disabled +lolin_s2_mini.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s2_mini.menu.DFUOnBoot.dfu=Enabled +lolin_s2_mini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s2_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_s2_mini.menu.PartitionScheme.default.build.partitions=default +lolin_s2_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_s2_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_s2_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_s2_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_s2_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_s2_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_s2_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_s2_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_s2_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_s2_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_s2_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_s2_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_s2_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_s2_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_s2_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_s2_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_s2_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +lolin_s2_mini.menu.DebugLevel.none=None +lolin_s2_mini.menu.DebugLevel.none.build.code_debug=0 +lolin_s2_mini.menu.DebugLevel.error=Error +lolin_s2_mini.menu.DebugLevel.error.build.code_debug=1 +lolin_s2_mini.menu.DebugLevel.warn=Warn +lolin_s2_mini.menu.DebugLevel.warn.build.code_debug=2 +lolin_s2_mini.menu.DebugLevel.info=Info +lolin_s2_mini.menu.DebugLevel.info.build.code_debug=3 +lolin_s2_mini.menu.DebugLevel.debug=Debug +lolin_s2_mini.menu.DebugLevel.debug.build.code_debug=4 +lolin_s2_mini.menu.DebugLevel.verbose=Verbose +lolin_s2_mini.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s2_mini.menu.EraseFlash.none=Disabled +lolin_s2_mini.menu.EraseFlash.none.upload.erase_cmd= +lolin_s2_mini.menu.EraseFlash.all=Enabled +lolin_s2_mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s2_pico.name=LOLIN S2 PICO +lolin_s2_pico.vid.0=0x303a +lolin_s2_pico.pid.0=0x80C5 + +lolin_s2_pico.bootloader.tool=esptool_py +lolin_s2_pico.bootloader.tool.default=esptool_py + +lolin_s2_pico.upload.tool=esptool_py +lolin_s2_pico.upload.tool.default=esptool_py +lolin_s2_pico.upload.tool.network=esp_ota + +lolin_s2_pico.upload.maximum_size=1310720 +lolin_s2_pico.upload.maximum_data_size=327680 +lolin_s2_pico.upload.flags= +lolin_s2_pico.upload.extra_flags= +lolin_s2_pico.upload.use_1200bps_touch=true +lolin_s2_pico.upload.wait_for_upload_port=true +lolin_s2_pico.upload.speed=921600 + +lolin_s2_pico.serial.disableDTR=false +lolin_s2_pico.serial.disableRTS=false + +lolin_s2_pico.build.tarch=xtensa +lolin_s2_pico.build.bootloader_addr=0x1000 +lolin_s2_pico.build.target=esp32s2 +lolin_s2_pico.build.mcu=esp32s2 +lolin_s2_pico.build.core=esp32 +lolin_s2_pico.build.variant=lolin_s2_pico +lolin_s2_pico.build.board=LOLIN_S2_PICO + +lolin_s2_pico.build.cdc_on_boot=1 +lolin_s2_pico.build.msc_on_boot=1 +lolin_s2_pico.build.dfu_on_boot=1 +lolin_s2_pico.build.f_cpu=240000000L +lolin_s2_pico.build.flash_size=4MB +lolin_s2_pico.build.flash_freq=80m +lolin_s2_pico.build.flash_mode=dio +lolin_s2_pico.build.boot=qio +lolin_s2_pico.build.partitions=default +lolin_s2_pico.build.defines=-DBOARD_HAS_PSRAM + +lolin_s2_pico.menu.CDCOnBoot.default=Enabled +lolin_s2_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1 +lolin_s2_pico.menu.CDCOnBoot.dis_cdc=Disabled +lolin_s2_pico.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +lolin_s2_pico.menu.MSCOnBoot.default=Disabled +lolin_s2_pico.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s2_pico.menu.MSCOnBoot.msc=Enabled +lolin_s2_pico.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s2_pico.menu.DFUOnBoot.default=Disabled +lolin_s2_pico.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s2_pico.menu.DFUOnBoot.dfu=Enabled +lolin_s2_pico.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s2_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_s2_pico.menu.PartitionScheme.default.build.partitions=default +lolin_s2_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_s2_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_s2_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_s2_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_s2_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_s2_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_s2_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_s2_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_s2_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_s2_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_s2_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_s2_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_s2_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_s2_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_s2_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_s2_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_s2_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +lolin_s2_pico.menu.DebugLevel.none=None +lolin_s2_pico.menu.DebugLevel.none.build.code_debug=0 +lolin_s2_pico.menu.DebugLevel.error=Error +lolin_s2_pico.menu.DebugLevel.error.build.code_debug=1 +lolin_s2_pico.menu.DebugLevel.warn=Warn +lolin_s2_pico.menu.DebugLevel.warn.build.code_debug=2 +lolin_s2_pico.menu.DebugLevel.info=Info +lolin_s2_pico.menu.DebugLevel.info.build.code_debug=3 +lolin_s2_pico.menu.DebugLevel.debug=Debug +lolin_s2_pico.menu.DebugLevel.debug.build.code_debug=4 +lolin_s2_pico.menu.DebugLevel.verbose=Verbose +lolin_s2_pico.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s2_pico.menu.EraseFlash.none=Disabled +lolin_s2_pico.menu.EraseFlash.none.upload.erase_cmd= +lolin_s2_pico.menu.EraseFlash.all=Enabled +lolin_s2_pico.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s3.name=LOLIN S3 + +lolin_s3.bootloader.tool=esptool_py +lolin_s3.bootloader.tool.default=esptool_py + +lolin_s3.upload.tool=esptool_py +lolin_s3.upload.tool.default=esptool_py +lolin_s3.upload.tool.network=esp_ota + +lolin_s3.upload.maximum_size=1310720 +lolin_s3.upload.maximum_data_size=327680 +lolin_s3.upload.flags= +lolin_s3.upload.extra_flags= +lolin_s3.upload.use_1200bps_touch=false +lolin_s3.upload.wait_for_upload_port=false + +lolin_s3.serial.disableDTR=false +lolin_s3.serial.disableRTS=false + +lolin_s3.build.tarch=xtensa +lolin_s3.build.bootloader_addr=0x0 +lolin_s3.build.target=esp32s3 +lolin_s3.build.mcu=esp32s3 +lolin_s3.build.core=esp32 +lolin_s3.build.variant=lolin_s3 +lolin_s3.build.board=LOLIN_S3 + +lolin_s3.build.usb_mode=1 +lolin_s3.build.cdc_on_boot=0 +lolin_s3.build.msc_on_boot=0 +lolin_s3.build.dfu_on_boot=0 +lolin_s3.build.f_cpu=240000000L +lolin_s3.build.flash_size=16MB +lolin_s3.build.flash_freq=80m +lolin_s3.build.flash_mode=dio +lolin_s3.build.boot=qio +lolin_s3.build.boot_freq=80m +lolin_s3.build.partitions=default +lolin_s3.build.defines=-DBOARD_HAS_PSRAM +lolin_s3.build.loop_core= +lolin_s3.build.event_core= +lolin_s3.build.psram_type=opi +lolin_s3.build.memory_type={build.boot}_{build.psram_type} + +lolin_s3.menu.FlashMode.qio=QIO 80MHz +lolin_s3.menu.FlashMode.qio.build.flash_mode=dio +lolin_s3.menu.FlashMode.qio.build.boot=qio +lolin_s3.menu.FlashMode.qio.build.boot_freq=80m +lolin_s3.menu.FlashMode.qio.build.flash_freq=80m +lolin_s3.menu.FlashMode.qio120=QIO 120MHz +lolin_s3.menu.FlashMode.qio120.build.flash_mode=dio +lolin_s3.menu.FlashMode.qio120.build.boot=qio +lolin_s3.menu.FlashMode.qio120.build.boot_freq=120m +lolin_s3.menu.FlashMode.qio120.build.flash_freq=80m + +lolin_s3.menu.LoopCore.1=Core 1 +lolin_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lolin_s3.menu.LoopCore.0=Core 0 +lolin_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lolin_s3.menu.EventsCore.1=Core 1 +lolin_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lolin_s3.menu.EventsCore.0=Core 0 +lolin_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lolin_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +lolin_s3.menu.USBMode.hwcdc.build.usb_mode=1 +lolin_s3.menu.USBMode.default=USB-OTG (TinyUSB) +lolin_s3.menu.USBMode.default.build.usb_mode=0 + +lolin_s3.menu.CDCOnBoot.default=Disabled +lolin_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lolin_s3.menu.CDCOnBoot.cdc=Enabled +lolin_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lolin_s3.menu.MSCOnBoot.default=Disabled +lolin_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lolin_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s3.menu.DFUOnBoot.default=Disabled +lolin_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lolin_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s3.menu.UploadMode.default=UART0 / Hardware CDC +lolin_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +lolin_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +lolin_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lolin_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lolin_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lolin_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +lolin_s3.menu.PartitionScheme.fatflash.build.partitions=ffat +lolin_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lolin_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +lolin_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lolin_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lolin_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lolin_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lolin_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +lolin_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +lolin_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +lolin_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +lolin_s3.menu.CPUFreq.240=240MHz (WiFi) +lolin_s3.menu.CPUFreq.240.build.f_cpu=240000000L +lolin_s3.menu.CPUFreq.160=160MHz (WiFi) +lolin_s3.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_s3.menu.CPUFreq.80=80MHz (WiFi) +lolin_s3.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_s3.menu.CPUFreq.40=40MHz +lolin_s3.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_s3.menu.CPUFreq.20=20MHz +lolin_s3.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_s3.menu.CPUFreq.10=10MHz +lolin_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin_s3.menu.UploadSpeed.921600=921600 +lolin_s3.menu.UploadSpeed.921600.upload.speed=921600 +lolin_s3.menu.UploadSpeed.115200=115200 +lolin_s3.menu.UploadSpeed.115200.upload.speed=115200 +lolin_s3.menu.UploadSpeed.256000.windows=256000 +lolin_s3.menu.UploadSpeed.256000.upload.speed=256000 +lolin_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_s3.menu.UploadSpeed.230400=230400 +lolin_s3.menu.UploadSpeed.230400.upload.speed=230400 +lolin_s3.menu.UploadSpeed.460800.linux=460800 +lolin_s3.menu.UploadSpeed.460800.macosx=460800 +lolin_s3.menu.UploadSpeed.460800.upload.speed=460800 +lolin_s3.menu.UploadSpeed.512000.windows=512000 +lolin_s3.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_s3.menu.DebugLevel.none=None +lolin_s3.menu.DebugLevel.none.build.code_debug=0 +lolin_s3.menu.DebugLevel.error=Error +lolin_s3.menu.DebugLevel.error.build.code_debug=1 +lolin_s3.menu.DebugLevel.warn=Warn +lolin_s3.menu.DebugLevel.warn.build.code_debug=2 +lolin_s3.menu.DebugLevel.info=Info +lolin_s3.menu.DebugLevel.info.build.code_debug=3 +lolin_s3.menu.DebugLevel.debug=Debug +lolin_s3.menu.DebugLevel.debug.build.code_debug=4 +lolin_s3.menu.DebugLevel.verbose=Verbose +lolin_s3.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s3.menu.EraseFlash.none=Disabled +lolin_s3.menu.EraseFlash.none.upload.erase_cmd= +lolin_s3.menu.EraseFlash.all=Enabled +lolin_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s3_mini.name=LOLIN S3 Mini +lolin_s3_mini.vid.0=0x303a +lolin_s3_mini.pid.0=0x8167 + +lolin_s3_mini.bootloader.tool=esptool_py +lolin_s3_mini.bootloader.tool.default=esptool_py + +lolin_s3_mini.upload.tool=esptool_py +lolin_s3_mini.upload.tool.default=esptool_py +lolin_s3_mini.upload.tool.network=esp_ota + +lolin_s3_mini.upload.maximum_size=1310720 +lolin_s3_mini.upload.maximum_data_size=327680 +lolin_s3_mini.upload.flags= +lolin_s3_mini.upload.extra_flags= +lolin_s3_mini.upload.use_1200bps_touch=false +lolin_s3_mini.upload.wait_for_upload_port=false + +lolin_s3_mini.serial.disableDTR=false +lolin_s3_mini.serial.disableRTS=false + +lolin_s3_mini.build.tarch=xtensa +lolin_s3_mini.build.bootloader_addr=0x0 +lolin_s3_mini.build.target=esp32s3 +lolin_s3_mini.build.mcu=esp32s3 +lolin_s3_mini.build.core=esp32 +lolin_s3_mini.build.variant=lolin_s3_mini +lolin_s3_mini.build.board=LOLIN_S3_MINI + +lolin_s3_mini.build.usb_mode=1 +lolin_s3_mini.build.cdc_on_boot=0 +lolin_s3_mini.build.msc_on_boot=0 +lolin_s3_mini.build.dfu_on_boot=0 +lolin_s3_mini.build.f_cpu=240000000L +lolin_s3_mini.build.flash_size=4MB +lolin_s3_mini.build.flash_freq=80m +lolin_s3_mini.build.flash_mode=dio +lolin_s3_mini.build.boot=qio +lolin_s3_mini.build.boot_freq=80m +lolin_s3_mini.build.partitions=default +lolin_s3_mini.build.defines=-DBOARD_HAS_PSRAM +lolin_s3_mini.build.loop_core= +lolin_s3_mini.build.event_core= +lolin_s3_mini.build.psram_type=qspi +lolin_s3_mini.build.memory_type={build.boot}_{build.psram_type} + +lolin_s3_mini.menu.FlashMode.qio=QIO 80MHz +lolin_s3_mini.menu.FlashMode.qio.build.flash_mode=dio +lolin_s3_mini.menu.FlashMode.qio.build.boot=qio +lolin_s3_mini.menu.FlashMode.qio.build.boot_freq=80m +lolin_s3_mini.menu.FlashMode.qio.build.flash_freq=80m +lolin_s3_mini.menu.FlashMode.qio120=QIO 120MHz +lolin_s3_mini.menu.FlashMode.qio120.build.flash_mode=dio +lolin_s3_mini.menu.FlashMode.qio120.build.boot=qio +lolin_s3_mini.menu.FlashMode.qio120.build.boot_freq=120m +lolin_s3_mini.menu.FlashMode.qio120.build.flash_freq=80m + +lolin_s3_mini.menu.LoopCore.1=Core 1 +lolin_s3_mini.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lolin_s3_mini.menu.LoopCore.0=Core 0 +lolin_s3_mini.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lolin_s3_mini.menu.EventsCore.1=Core 1 +lolin_s3_mini.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lolin_s3_mini.menu.EventsCore.0=Core 0 +lolin_s3_mini.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lolin_s3_mini.menu.USBMode.hwcdc=Hardware CDC and JTAG +lolin_s3_mini.menu.USBMode.hwcdc.build.usb_mode=1 +lolin_s3_mini.menu.USBMode.default=USB-OTG (TinyUSB) +lolin_s3_mini.menu.USBMode.default.build.usb_mode=0 + +lolin_s3_mini.menu.CDCOnBoot.default=Disabled +lolin_s3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lolin_s3_mini.menu.CDCOnBoot.cdc=Enabled +lolin_s3_mini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lolin_s3_mini.menu.MSCOnBoot.default=Disabled +lolin_s3_mini.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s3_mini.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lolin_s3_mini.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s3_mini.menu.DFUOnBoot.default=Disabled +lolin_s3_mini.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s3_mini.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lolin_s3_mini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s3_mini.menu.UploadMode.default=UART0 / Hardware CDC +lolin_s3_mini.menu.UploadMode.default.upload.use_1200bps_touch=false +lolin_s3_mini.menu.UploadMode.default.upload.wait_for_upload_port=false +lolin_s3_mini.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lolin_s3_mini.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lolin_s3_mini.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lolin_s3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_s3_mini.menu.PartitionScheme.default.build.partitions=default +lolin_s3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_s3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_s3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_s3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_s3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_s3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_s3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_s3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_s3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_s3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_s3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_s3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_s3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_s3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_s3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_s3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_s3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lolin_s3_mini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lolin_s3_mini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lolin_s3_mini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +lolin_s3_mini.menu.PartitionScheme.rainmaker=RainMaker 4MB +lolin_s3_mini.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lolin_s3_mini.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +lolin_s3_mini.menu.CPUFreq.240=240MHz (WiFi) +lolin_s3_mini.menu.CPUFreq.240.build.f_cpu=240000000L +lolin_s3_mini.menu.CPUFreq.160=160MHz (WiFi) +lolin_s3_mini.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_s3_mini.menu.CPUFreq.80=80MHz (WiFi) +lolin_s3_mini.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_s3_mini.menu.CPUFreq.40=40MHz +lolin_s3_mini.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_s3_mini.menu.CPUFreq.20=20MHz +lolin_s3_mini.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_s3_mini.menu.CPUFreq.10=10MHz +lolin_s3_mini.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin_s3_mini.menu.UploadSpeed.921600=921600 +lolin_s3_mini.menu.UploadSpeed.921600.upload.speed=921600 +lolin_s3_mini.menu.UploadSpeed.115200=115200 +lolin_s3_mini.menu.UploadSpeed.115200.upload.speed=115200 +lolin_s3_mini.menu.UploadSpeed.256000.windows=256000 +lolin_s3_mini.menu.UploadSpeed.256000.upload.speed=256000 +lolin_s3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_s3_mini.menu.UploadSpeed.230400=230400 +lolin_s3_mini.menu.UploadSpeed.230400.upload.speed=230400 +lolin_s3_mini.menu.UploadSpeed.460800.linux=460800 +lolin_s3_mini.menu.UploadSpeed.460800.macosx=460800 +lolin_s3_mini.menu.UploadSpeed.460800.upload.speed=460800 +lolin_s3_mini.menu.UploadSpeed.512000.windows=512000 +lolin_s3_mini.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_s3_mini.menu.DebugLevel.none=None +lolin_s3_mini.menu.DebugLevel.none.build.code_debug=0 +lolin_s3_mini.menu.DebugLevel.error=Error +lolin_s3_mini.menu.DebugLevel.error.build.code_debug=1 +lolin_s3_mini.menu.DebugLevel.warn=Warn +lolin_s3_mini.menu.DebugLevel.warn.build.code_debug=2 +lolin_s3_mini.menu.DebugLevel.info=Info +lolin_s3_mini.menu.DebugLevel.info.build.code_debug=3 +lolin_s3_mini.menu.DebugLevel.debug=Debug +lolin_s3_mini.menu.DebugLevel.debug.build.code_debug=4 +lolin_s3_mini.menu.DebugLevel.verbose=Verbose +lolin_s3_mini.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s3_mini.menu.EraseFlash.none=Disabled +lolin_s3_mini.menu.EraseFlash.none.upload.erase_cmd= +lolin_s3_mini.menu.EraseFlash.all=Enabled +lolin_s3_mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s3_mini_pro.name=LOLIN S3 Mini Pro +lolin_s3_mini_pro.vid.0=0x303a +lolin_s3_mini_pro.pid.0=0x8216 + +lolin_s3_mini_pro.bootloader.tool=esptool_py +lolin_s3_mini_pro.bootloader.tool.default=esptool_py + +lolin_s3_mini_pro.upload.tool=esptool_py +lolin_s3_mini_pro.upload.tool.default=esptool_py +lolin_s3_mini_pro.upload.tool.network=esp_ota + +lolin_s3_mini_pro.upload.maximum_size=1310720 +lolin_s3_mini_pro.upload.maximum_data_size=327680 +lolin_s3_mini_pro.upload.flags= +lolin_s3_mini_pro.upload.extra_flags= +lolin_s3_mini_pro.upload.use_1200bps_touch=false +lolin_s3_mini_pro.upload.wait_for_upload_port=false + +lolin_s3_mini_pro.serial.disableDTR=false +lolin_s3_mini_pro.serial.disableRTS=false + +lolin_s3_mini_pro.build.tarch=xtensa +lolin_s3_mini_pro.build.bootloader_addr=0x0 +lolin_s3_mini_pro.build.target=esp32s3 +lolin_s3_mini_pro.build.mcu=esp32s3 +lolin_s3_mini_pro.build.core=esp32 +lolin_s3_mini_pro.build.variant=lolin_s3_mini_pro +lolin_s3_mini_pro.build.board=LOLIN_S3_MINI_PRO + +lolin_s3_mini_pro.build.usb_mode=1 +lolin_s3_mini_pro.build.cdc_on_boot=0 +lolin_s3_mini_pro.build.msc_on_boot=0 +lolin_s3_mini_pro.build.dfu_on_boot=0 +lolin_s3_mini_pro.build.f_cpu=240000000L +lolin_s3_mini_pro.build.flash_size=4MB +lolin_s3_mini_pro.build.flash_freq=80m +lolin_s3_mini_pro.build.flash_mode=dio +lolin_s3_mini_pro.build.boot=qio +lolin_s3_mini_pro.build.boot_freq=80m +lolin_s3_mini_pro.build.partitions=default +lolin_s3_mini_pro.build.defines=-DBOARD_HAS_PSRAM +lolin_s3_mini_pro.build.loop_core= +lolin_s3_mini_pro.build.event_core= +lolin_s3_mini_pro.build.psram_type=qspi +lolin_s3_mini_pro.build.memory_type={build.boot}_{build.psram_type} + +lolin_s3_mini_pro.menu.FlashMode.qio=QIO 80MHz +lolin_s3_mini_pro.menu.FlashMode.qio.build.flash_mode=dio +lolin_s3_mini_pro.menu.FlashMode.qio.build.boot=qio +lolin_s3_mini_pro.menu.FlashMode.qio.build.boot_freq=80m +lolin_s3_mini_pro.menu.FlashMode.qio.build.flash_freq=80m +lolin_s3_mini_pro.menu.FlashMode.qio120=QIO 120MHz +lolin_s3_mini_pro.menu.FlashMode.qio120.build.flash_mode=dio +lolin_s3_mini_pro.menu.FlashMode.qio120.build.boot=qio +lolin_s3_mini_pro.menu.FlashMode.qio120.build.boot_freq=120m +lolin_s3_mini_pro.menu.FlashMode.qio120.build.flash_freq=80m + +lolin_s3_mini_pro.menu.LoopCore.1=Core 1 +lolin_s3_mini_pro.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lolin_s3_mini_pro.menu.LoopCore.0=Core 0 +lolin_s3_mini_pro.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lolin_s3_mini_pro.menu.EventsCore.1=Core 1 +lolin_s3_mini_pro.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lolin_s3_mini_pro.menu.EventsCore.0=Core 0 +lolin_s3_mini_pro.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lolin_s3_mini_pro.menu.USBMode.hwcdc=Hardware CDC and JTAG +lolin_s3_mini_pro.menu.USBMode.hwcdc.build.usb_mode=1 +lolin_s3_mini_pro.menu.USBMode.default=USB-OTG (TinyUSB) +lolin_s3_mini_pro.menu.USBMode.default.build.usb_mode=0 + +lolin_s3_mini_pro.menu.CDCOnBoot.default=Disabled +lolin_s3_mini_pro.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lolin_s3_mini_pro.menu.CDCOnBoot.cdc=Enabled +lolin_s3_mini_pro.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lolin_s3_mini_pro.menu.MSCOnBoot.default=Disabled +lolin_s3_mini_pro.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s3_mini_pro.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lolin_s3_mini_pro.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s3_mini_pro.menu.DFUOnBoot.default=Disabled +lolin_s3_mini_pro.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s3_mini_pro.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lolin_s3_mini_pro.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s3_mini_pro.menu.UploadMode.default=UART0 / Hardware CDC +lolin_s3_mini_pro.menu.UploadMode.default.upload.use_1200bps_touch=false +lolin_s3_mini_pro.menu.UploadMode.default.upload.wait_for_upload_port=false +lolin_s3_mini_pro.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lolin_s3_mini_pro.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lolin_s3_mini_pro.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lolin_s3_mini_pro.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lolin_s3_mini_pro.menu.PartitionScheme.default.build.partitions=default +lolin_s3_mini_pro.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lolin_s3_mini_pro.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lolin_s3_mini_pro.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lolin_s3_mini_pro.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin_s3_mini_pro.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin_s3_mini_pro.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lolin_s3_mini_pro.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lolin_s3_mini_pro.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lolin_s3_mini_pro.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lolin_s3_mini_pro.menu.PartitionScheme.huge_app.build.partitions=huge_app +lolin_s3_mini_pro.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker=RainMaker 4MB +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +lolin_s3_mini_pro.menu.CPUFreq.240=240MHz (WiFi) +lolin_s3_mini_pro.menu.CPUFreq.240.build.f_cpu=240000000L +lolin_s3_mini_pro.menu.CPUFreq.160=160MHz (WiFi) +lolin_s3_mini_pro.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_s3_mini_pro.menu.CPUFreq.80=80MHz (WiFi) +lolin_s3_mini_pro.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_s3_mini_pro.menu.CPUFreq.40=40MHz +lolin_s3_mini_pro.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_s3_mini_pro.menu.CPUFreq.20=20MHz +lolin_s3_mini_pro.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_s3_mini_pro.menu.CPUFreq.10=10MHz +lolin_s3_mini_pro.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin_s3_mini_pro.menu.UploadSpeed.921600=921600 +lolin_s3_mini_pro.menu.UploadSpeed.921600.upload.speed=921600 +lolin_s3_mini_pro.menu.UploadSpeed.115200=115200 +lolin_s3_mini_pro.menu.UploadSpeed.115200.upload.speed=115200 +lolin_s3_mini_pro.menu.UploadSpeed.256000.windows=256000 +lolin_s3_mini_pro.menu.UploadSpeed.256000.upload.speed=256000 +lolin_s3_mini_pro.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_s3_mini_pro.menu.UploadSpeed.230400=230400 +lolin_s3_mini_pro.menu.UploadSpeed.230400.upload.speed=230400 +lolin_s3_mini_pro.menu.UploadSpeed.460800.linux=460800 +lolin_s3_mini_pro.menu.UploadSpeed.460800.macosx=460800 +lolin_s3_mini_pro.menu.UploadSpeed.460800.upload.speed=460800 +lolin_s3_mini_pro.menu.UploadSpeed.512000.windows=512000 +lolin_s3_mini_pro.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_s3_mini_pro.menu.DebugLevel.none=None +lolin_s3_mini_pro.menu.DebugLevel.none.build.code_debug=0 +lolin_s3_mini_pro.menu.DebugLevel.error=Error +lolin_s3_mini_pro.menu.DebugLevel.error.build.code_debug=1 +lolin_s3_mini_pro.menu.DebugLevel.warn=Warn +lolin_s3_mini_pro.menu.DebugLevel.warn.build.code_debug=2 +lolin_s3_mini_pro.menu.DebugLevel.info=Info +lolin_s3_mini_pro.menu.DebugLevel.info.build.code_debug=3 +lolin_s3_mini_pro.menu.DebugLevel.debug=Debug +lolin_s3_mini_pro.menu.DebugLevel.debug.build.code_debug=4 +lolin_s3_mini_pro.menu.DebugLevel.verbose=Verbose +lolin_s3_mini_pro.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s3_mini_pro.menu.EraseFlash.none=Disabled +lolin_s3_mini_pro.menu.EraseFlash.none.upload.erase_cmd= +lolin_s3_mini_pro.menu.EraseFlash.all=Enabled +lolin_s3_mini_pro.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin_s3_pro.name=LOLIN S3 Pro +lolin_s3_pro.vid.0=0x303a +lolin_s3_pro.pid.0=0x8161 + +lolin_s3_pro.bootloader.tool=esptool_py +lolin_s3_pro.bootloader.tool.default=esptool_py + +lolin_s3_pro.upload.tool=esptool_py +lolin_s3_pro.upload.tool.default=esptool_py +lolin_s3_pro.upload.tool.network=esp_ota + +lolin_s3_pro.upload.maximum_size=1310720 +lolin_s3_pro.upload.maximum_data_size=327680 +lolin_s3_pro.upload.flags= +lolin_s3_pro.upload.extra_flags= +lolin_s3_pro.upload.use_1200bps_touch=false +lolin_s3_pro.upload.wait_for_upload_port=false + +lolin_s3_pro.serial.disableDTR=false +lolin_s3_pro.serial.disableRTS=false + +lolin_s3_pro.build.tarch=xtensa +lolin_s3_pro.build.bootloader_addr=0x0 +lolin_s3_pro.build.target=esp32s3 +lolin_s3_pro.build.mcu=esp32s3 +lolin_s3_pro.build.core=esp32 +lolin_s3_pro.build.variant=lolin_s3_pro +lolin_s3_pro.build.board=LOLIN_S3_PRO + +lolin_s3_pro.build.usb_mode=1 +lolin_s3_pro.build.cdc_on_boot=0 +lolin_s3_pro.build.msc_on_boot=0 +lolin_s3_pro.build.dfu_on_boot=0 +lolin_s3_pro.build.f_cpu=240000000L +lolin_s3_pro.build.flash_size=16MB +lolin_s3_pro.build.flash_freq=80m +lolin_s3_pro.build.flash_mode=dio +lolin_s3_pro.build.boot=qio +lolin_s3_pro.build.boot_freq=80m +lolin_s3_pro.build.partitions=default +lolin_s3_pro.build.defines=-DBOARD_HAS_PSRAM +lolin_s3_pro.build.loop_core= +lolin_s3_pro.build.event_core= +lolin_s3_pro.build.psram_type=opi +lolin_s3_pro.build.memory_type={build.boot}_{build.psram_type} + +lolin_s3_pro.menu.FlashMode.qio=QIO 80MHz +lolin_s3_pro.menu.FlashMode.qio.build.flash_mode=dio +lolin_s3_pro.menu.FlashMode.qio.build.boot=qio +lolin_s3_pro.menu.FlashMode.qio.build.boot_freq=80m +lolin_s3_pro.menu.FlashMode.qio.build.flash_freq=80m +lolin_s3_pro.menu.FlashMode.qio120=QIO 120MHz +lolin_s3_pro.menu.FlashMode.qio120.build.flash_mode=dio +lolin_s3_pro.menu.FlashMode.qio120.build.boot=qio +lolin_s3_pro.menu.FlashMode.qio120.build.boot_freq=120m +lolin_s3_pro.menu.FlashMode.qio120.build.flash_freq=80m + +lolin_s3_pro.menu.LoopCore.1=Core 1 +lolin_s3_pro.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lolin_s3_pro.menu.LoopCore.0=Core 0 +lolin_s3_pro.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lolin_s3_pro.menu.EventsCore.1=Core 1 +lolin_s3_pro.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lolin_s3_pro.menu.EventsCore.0=Core 0 +lolin_s3_pro.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lolin_s3_pro.menu.USBMode.hwcdc=Hardware CDC and JTAG +lolin_s3_pro.menu.USBMode.hwcdc.build.usb_mode=1 +lolin_s3_pro.menu.USBMode.default=USB-OTG (TinyUSB) +lolin_s3_pro.menu.USBMode.default.build.usb_mode=0 + +lolin_s3_pro.menu.CDCOnBoot.default=Disabled +lolin_s3_pro.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lolin_s3_pro.menu.CDCOnBoot.cdc=Enabled +lolin_s3_pro.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lolin_s3_pro.menu.MSCOnBoot.default=Disabled +lolin_s3_pro.menu.MSCOnBoot.default.build.msc_on_boot=0 +lolin_s3_pro.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lolin_s3_pro.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lolin_s3_pro.menu.DFUOnBoot.default=Disabled +lolin_s3_pro.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lolin_s3_pro.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lolin_s3_pro.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lolin_s3_pro.menu.UploadMode.default=UART0 / Hardware CDC +lolin_s3_pro.menu.UploadMode.default.upload.use_1200bps_touch=false +lolin_s3_pro.menu.UploadMode.default.upload.wait_for_upload_port=false +lolin_s3_pro.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lolin_s3_pro.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lolin_s3_pro.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lolin_s3_pro.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +lolin_s3_pro.menu.PartitionScheme.fatflash.build.partitions=ffat +lolin_s3_pro.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lolin_s3_pro.menu.PartitionScheme.rainmaker=RainMaker 4MB +lolin_s3_pro.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lolin_s3_pro.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +lolin_s3_pro.menu.CPUFreq.240=240MHz (WiFi) +lolin_s3_pro.menu.CPUFreq.240.build.f_cpu=240000000L +lolin_s3_pro.menu.CPUFreq.160=160MHz (WiFi) +lolin_s3_pro.menu.CPUFreq.160.build.f_cpu=160000000L +lolin_s3_pro.menu.CPUFreq.80=80MHz (WiFi) +lolin_s3_pro.menu.CPUFreq.80.build.f_cpu=80000000L +lolin_s3_pro.menu.CPUFreq.40=40MHz +lolin_s3_pro.menu.CPUFreq.40.build.f_cpu=40000000L +lolin_s3_pro.menu.CPUFreq.20=20MHz +lolin_s3_pro.menu.CPUFreq.20.build.f_cpu=20000000L +lolin_s3_pro.menu.CPUFreq.10=10MHz +lolin_s3_pro.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin_s3_pro.menu.UploadSpeed.921600=921600 +lolin_s3_pro.menu.UploadSpeed.921600.upload.speed=921600 +lolin_s3_pro.menu.UploadSpeed.115200=115200 +lolin_s3_pro.menu.UploadSpeed.115200.upload.speed=115200 +lolin_s3_pro.menu.UploadSpeed.256000.windows=256000 +lolin_s3_pro.menu.UploadSpeed.256000.upload.speed=256000 +lolin_s3_pro.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin_s3_pro.menu.UploadSpeed.230400=230400 +lolin_s3_pro.menu.UploadSpeed.230400.upload.speed=230400 +lolin_s3_pro.menu.UploadSpeed.460800.linux=460800 +lolin_s3_pro.menu.UploadSpeed.460800.macosx=460800 +lolin_s3_pro.menu.UploadSpeed.460800.upload.speed=460800 +lolin_s3_pro.menu.UploadSpeed.512000.windows=512000 +lolin_s3_pro.menu.UploadSpeed.512000.upload.speed=512000 + +lolin_s3_pro.menu.DebugLevel.none=None +lolin_s3_pro.menu.DebugLevel.none.build.code_debug=0 +lolin_s3_pro.menu.DebugLevel.error=Error +lolin_s3_pro.menu.DebugLevel.error.build.code_debug=1 +lolin_s3_pro.menu.DebugLevel.warn=Warn +lolin_s3_pro.menu.DebugLevel.warn.build.code_debug=2 +lolin_s3_pro.menu.DebugLevel.info=Info +lolin_s3_pro.menu.DebugLevel.info.build.code_debug=3 +lolin_s3_pro.menu.DebugLevel.debug=Debug +lolin_s3_pro.menu.DebugLevel.debug.build.code_debug=4 +lolin_s3_pro.menu.DebugLevel.verbose=Verbose +lolin_s3_pro.menu.DebugLevel.verbose.build.code_debug=5 + +lolin_s3_pro.menu.EraseFlash.none=Disabled +lolin_s3_pro.menu.EraseFlash.none.upload.erase_cmd= +lolin_s3_pro.menu.EraseFlash.all=Enabled +lolin_s3_pro.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin32.name=WEMOS LOLIN32 + +lolin32.bootloader.tool=esptool_py +lolin32.bootloader.tool.default=esptool_py + +lolin32.upload.tool=esptool_py +lolin32.upload.tool.default=esptool_py +lolin32.upload.tool.network=esp_ota + +lolin32.upload.maximum_size=1310720 +lolin32.upload.maximum_data_size=327680 +lolin32.upload.flags= +lolin32.upload.extra_flags= + +lolin32.serial.disableDTR=true +lolin32.serial.disableRTS=true + +lolin32.build.tarch=xtensa +lolin32.build.bootloader_addr=0x1000 +lolin32.build.target=esp32 +lolin32.build.mcu=esp32 +lolin32.build.core=esp32 +lolin32.build.variant=lolin32 +lolin32.build.board=LOLIN32 + +lolin32.build.f_cpu=240000000L +lolin32.build.flash_mode=dio +lolin32.build.flash_size=4MB +lolin32.build.boot=dio +lolin32.build.partitions=default +lolin32.build.defines= + +lolin32.menu.FlashFreq.80=80MHz +lolin32.menu.FlashFreq.80.build.flash_freq=80m +lolin32.menu.FlashFreq.40=40MHz +lolin32.menu.FlashFreq.40.build.flash_freq=40m + +lolin32.menu.PartitionScheme.default=Default +lolin32.menu.PartitionScheme.default.build.partitions=default +lolin32.menu.PartitionScheme.no_ota=No OTA (Large APP) +lolin32.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +lolin32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lolin32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +lolin32.menu.CPUFreq.240=240MHz (WiFi/BT) +lolin32.menu.CPUFreq.240.build.f_cpu=240000000L +lolin32.menu.CPUFreq.160=160MHz (WiFi/BT) +lolin32.menu.CPUFreq.160.build.f_cpu=160000000L +lolin32.menu.CPUFreq.80=80MHz (WiFi/BT) +lolin32.menu.CPUFreq.80.build.f_cpu=80000000L +lolin32.menu.CPUFreq.40=40MHz (40MHz XTAL) +lolin32.menu.CPUFreq.40.build.f_cpu=40000000L +lolin32.menu.CPUFreq.26=26MHz (26MHz XTAL) +lolin32.menu.CPUFreq.26.build.f_cpu=26000000L +lolin32.menu.CPUFreq.20=20MHz (40MHz XTAL) +lolin32.menu.CPUFreq.20.build.f_cpu=20000000L +lolin32.menu.CPUFreq.13=13MHz (26MHz XTAL) +lolin32.menu.CPUFreq.13.build.f_cpu=13000000L +lolin32.menu.CPUFreq.10=10MHz (40MHz XTAL) +lolin32.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin32.menu.UploadSpeed.921600=921600 +lolin32.menu.UploadSpeed.921600.upload.speed=921600 +lolin32.menu.UploadSpeed.115200=115200 +lolin32.menu.UploadSpeed.115200.upload.speed=115200 +lolin32.menu.UploadSpeed.256000.windows=256000 +lolin32.menu.UploadSpeed.256000.upload.speed=256000 +lolin32.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin32.menu.UploadSpeed.230400=230400 +lolin32.menu.UploadSpeed.230400.upload.speed=230400 +lolin32.menu.UploadSpeed.460800.linux=460800 +lolin32.menu.UploadSpeed.460800.macosx=460800 +lolin32.menu.UploadSpeed.460800.upload.speed=460800 +lolin32.menu.UploadSpeed.512000.windows=512000 +lolin32.menu.UploadSpeed.512000.upload.speed=512000 + +lolin32.menu.DebugLevel.none=None +lolin32.menu.DebugLevel.none.build.code_debug=0 +lolin32.menu.DebugLevel.error=Error +lolin32.menu.DebugLevel.error.build.code_debug=1 +lolin32.menu.DebugLevel.warn=Warn +lolin32.menu.DebugLevel.warn.build.code_debug=2 +lolin32.menu.DebugLevel.info=Info +lolin32.menu.DebugLevel.info.build.code_debug=3 +lolin32.menu.DebugLevel.debug=Debug +lolin32.menu.DebugLevel.debug.build.code_debug=4 +lolin32.menu.DebugLevel.verbose=Verbose +lolin32.menu.DebugLevel.verbose.build.code_debug=5 + +lolin32.menu.EraseFlash.none=Disabled +lolin32.menu.EraseFlash.none.upload.erase_cmd= +lolin32.menu.EraseFlash.all=Enabled +lolin32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +viralink32g01.name=ViraLink Gate32-0.1 + +viralink32g01.bootloader.tool=esptool_py +viralink32g01.bootloader.tool.default=esptool_py + +viralink32g01.upload.tool=esptool_py +viralink32g01.upload.tool.default=esptool_py +viralink32g01.upload.tool.network=esp_ota + +viralink32g01.upload.maximum_size=1310720 +viralink32g01.upload.maximum_data_size=327680 +viralink32g01.upload.flags= +viralink32g01.upload.extra_flags= + +viralink32g01.serial.disableDTR=true +viralink32g01.serial.disableRTS=true + +viralink32g01.build.tarch=xtensa +viralink32g01.build.bootloader_addr=0x1000 +viralink32g01.build.target=esp32 +viralink32g01.build.mcu=esp32 +viralink32g01.build.core=esp32 +viralink32g01.build.variant=ViraLink-G0.1 +viralink32g01.build.board=VIRALINK_GATE32_01 + +viralink32g01.build.f_cpu=240000000L +viralink32g01.build.flash_mode=dio +viralink32g01.build.flash_size=4MB +viralink32g01.build.boot=dio +viralink32g01.build.partitions=default +viralink32g01.build.defines= + +viralink32g01.menu.FlashFreq.80=80MHz +viralink32g01.menu.FlashFreq.80.build.flash_freq=80m +viralink32g01.menu.FlashFreq.40=40MHz +viralink32g01.menu.FlashFreq.40.build.flash_freq=40m + +viralink32g01.menu.PartitionScheme.default=Default +viralink32g01.menu.PartitionScheme.default.build.partitions=default +viralink32g01.menu.PartitionScheme.no_ota=No OTA (Large APP) +viralink32g01.menu.PartitionScheme.no_ota.build.partitions=no_ota +viralink32g01.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +viralink32g01.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +viralink32g01.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +viralink32g01.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +viralink32g01.menu.CPUFreq.240=240MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.240.build.f_cpu=240000000L +viralink32g01.menu.CPUFreq.160=160MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.160.build.f_cpu=160000000L +viralink32g01.menu.CPUFreq.80=80MHz (WiFi/BT) +viralink32g01.menu.CPUFreq.80.build.f_cpu=80000000L +viralink32g01.menu.CPUFreq.40=40MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.40.build.f_cpu=40000000L +viralink32g01.menu.CPUFreq.26=26MHz (26MHz XTAL) +viralink32g01.menu.CPUFreq.26.build.f_cpu=26000000L +viralink32g01.menu.CPUFreq.20=20MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.20.build.f_cpu=20000000L +viralink32g01.menu.CPUFreq.13=13MHz (26MHz XTAL) +viralink32g01.menu.CPUFreq.13.build.f_cpu=13000000L +viralink32g01.menu.CPUFreq.10=10MHz (40MHz XTAL) +viralink32g01.menu.CPUFreq.10.build.f_cpu=10000000L + +viralink32g01.menu.UploadSpeed.921600=921600 +viralink32g01.menu.UploadSpeed.921600.upload.speed=921600 +viralink32g01.menu.UploadSpeed.115200=115200 +viralink32g01.menu.UploadSpeed.115200.upload.speed=115200 +viralink32g01.menu.UploadSpeed.256000.windows=256000 +viralink32g01.menu.UploadSpeed.256000.upload.speed=256000 +viralink32g01.menu.UploadSpeed.230400.windows.upload.speed=256000 +viralink32g01.menu.UploadSpeed.230400=230400 +viralink32g01.menu.UploadSpeed.230400.upload.speed=230400 +viralink32g01.menu.UploadSpeed.460800.linux=460800 +viralink32g01.menu.UploadSpeed.460800.macosx=460800 +viralink32g01.menu.UploadSpeed.460800.upload.speed=460800 +viralink32g01.menu.UploadSpeed.512000.windows=512000 +viralink32g01.menu.UploadSpeed.512000.upload.speed=512000 + +viralink32g01.menu.DebugLevel.none=None +viralink32g01.menu.DebugLevel.none.build.code_debug=0 +viralink32g01.menu.DebugLevel.error=Error +viralink32g01.menu.DebugLevel.error.build.code_debug=1 +viralink32g01.menu.DebugLevel.warn=Warn +viralink32g01.menu.DebugLevel.warn.build.code_debug=2 +viralink32g01.menu.DebugLevel.info=Info +viralink32g01.menu.DebugLevel.info.build.code_debug=3 +viralink32g01.menu.DebugLevel.debug=Debug +viralink32g01.menu.DebugLevel.debug.build.code_debug=4 +viralink32g01.menu.DebugLevel.verbose=Verbose +viralink32g01.menu.DebugLevel.verbose.build.code_debug=5 + +viralink32g01.menu.EraseFlash.none=Disabled +viralink32g01.menu.EraseFlash.none.upload.erase_cmd= +viralink32g01.menu.EraseFlash.all=Enabled +viralink32g01.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +viralink32g11.name=ViraLink Gate32-1.1 + +viralink32g11.bootloader.tool=esptool_py +viralink32g11.bootloader.tool.default=esptool_py + +viralink32g11.upload.tool=esptool_py +viralink32g11.upload.tool.default=esptool_py +viralink32g11.upload.tool.network=esp_ota + +viralink32g11.upload.maximum_size=1310720 +viralink32g11.upload.maximum_data_size=327680 +viralink32g11.upload.flags= +viralink32g11.upload.extra_flags= + +viralink32g11.serial.disableDTR=true +viralink32g11.serial.disableRTS=true + +viralink32g11.build.tarch=xtensa +viralink32g11.build.bootloader_addr=0x1000 +viralink32g11.build.target=esp32 +viralink32g11.build.mcu=esp32 +viralink32g11.build.core=esp32 +viralink32g11.build.variant=ViraLink-G1.1 +viralink32g11.build.board=VIRALINK_GATE32_11 + +viralink32g11.build.f_cpu=240000000L +viralink32g11.build.flash_mode=dio +viralink32g11.build.flash_size=4MB +viralink32g11.build.boot=dio +viralink32g11.build.partitions=default +viralink32g11.build.defines= + +viralink32g11.menu.FlashFreq.80=80MHz +viralink32g11.menu.FlashFreq.80.build.flash_freq=80m +viralink32g11.menu.FlashFreq.40=40MHz +viralink32g11.menu.FlashFreq.40.build.flash_freq=40m + +viralink32g11.menu.PartitionScheme.default=Default +viralink32g11.menu.PartitionScheme.default.build.partitions=default +viralink32g11.menu.PartitionScheme.no_ota=No OTA (Large APP) +viralink32g11.menu.PartitionScheme.no_ota.build.partitions=no_ota +viralink32g11.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +viralink32g11.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +viralink32g11.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +viralink32g11.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +viralink32g11.menu.CPUFreq.240=240MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.240.build.f_cpu=240000000L +viralink32g11.menu.CPUFreq.160=160MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.160.build.f_cpu=160000000L +viralink32g11.menu.CPUFreq.80=80MHz (WiFi/BT) +viralink32g11.menu.CPUFreq.80.build.f_cpu=80000000L +viralink32g11.menu.CPUFreq.40=40MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.40.build.f_cpu=40000000L +viralink32g11.menu.CPUFreq.26=26MHz (26MHz XTAL) +viralink32g11.menu.CPUFreq.26.build.f_cpu=26000000L +viralink32g11.menu.CPUFreq.20=20MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.20.build.f_cpu=20000000L +viralink32g11.menu.CPUFreq.13=13MHz (26MHz XTAL) +viralink32g11.menu.CPUFreq.13.build.f_cpu=13000000L +viralink32g11.menu.CPUFreq.10=10MHz (40MHz XTAL) +viralink32g11.menu.CPUFreq.10.build.f_cpu=10000000L + +viralink32g11.menu.UploadSpeed.921600=921600 +viralink32g11.menu.UploadSpeed.921600.upload.speed=921600 +viralink32g11.menu.UploadSpeed.115200=115200 +viralink32g11.menu.UploadSpeed.115200.upload.speed=115200 +viralink32g11.menu.UploadSpeed.256000.windows=256000 +viralink32g11.menu.UploadSpeed.256000.upload.speed=256000 +viralink32g11.menu.UploadSpeed.230400.windows.upload.speed=256000 +viralink32g11.menu.UploadSpeed.230400=230400 +viralink32g11.menu.UploadSpeed.230400.upload.speed=230400 +viralink32g11.menu.UploadSpeed.460800.linux=460800 +viralink32g11.menu.UploadSpeed.460800.macosx=460800 +viralink32g11.menu.UploadSpeed.460800.upload.speed=460800 +viralink32g11.menu.UploadSpeed.512000.windows=512000 +viralink32g11.menu.UploadSpeed.512000.upload.speed=512000 + +viralink32g11.menu.DebugLevel.none=None +viralink32g11.menu.DebugLevel.none.build.code_debug=0 +viralink32g11.menu.DebugLevel.error=Error +viralink32g11.menu.DebugLevel.error.build.code_debug=1 +viralink32g11.menu.DebugLevel.warn=Warn +viralink32g11.menu.DebugLevel.warn.build.code_debug=2 +viralink32g11.menu.DebugLevel.info=Info +viralink32g11.menu.DebugLevel.info.build.code_debug=3 +viralink32g11.menu.DebugLevel.debug=Debug +viralink32g11.menu.DebugLevel.debug.build.code_debug=4 +viralink32g11.menu.DebugLevel.verbose=Verbose +viralink32g11.menu.DebugLevel.verbose.build.code_debug=5 + +viralink32g11.menu.EraseFlash.none=Disabled +viralink32g11.menu.EraseFlash.none.upload.erase_cmd= +viralink32g11.menu.EraseFlash.all=Enabled +viralink32g11.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lolin32-lite.name=WEMOS LOLIN32 Lite + +lolin32-lite.bootloader.tool=esptool_py +lolin32-lite.bootloader.tool.default=esptool_py + +lolin32-lite.upload.tool=esptool_py +lolin32-lite.upload.tool.default=esptool_py +lolin32-lite.upload.tool.network=esp_ota + +lolin32-lite.upload.maximum_size=1310720 +lolin32-lite.upload.maximum_data_size=327680 +lolin32-lite.upload.wait_for_upload_port=true +lolin32-lite.upload.flags= +lolin32-lite.upload.extra_flags= + +lolin32-lite.serial.disableDTR=true +lolin32-lite.serial.disableRTS=true + +lolin32-lite.build.tarch=xtensa +lolin32-lite.build.bootloader_addr=0x1000 +lolin32-lite.build.target=esp32 +lolin32-lite.build.mcu=esp32 +lolin32-lite.build.core=esp32 +lolin32-lite.build.variant=lolin32-lite +lolin32-lite.build.board=LOLIN32_LITE + +lolin32-lite.build.f_cpu=240000000L +lolin32-lite.build.flash_mode=dio +lolin32-lite.build.flash_size=4MB +lolin32-lite.build.boot=dio +lolin32-lite.build.partitions=default +lolin32-lite.build.defines= + +lolin32-lite.menu.FlashFreq.80=80MHz +lolin32-lite.menu.FlashFreq.80.build.flash_freq=80m +lolin32-lite.menu.FlashFreq.40=40MHz +lolin32-lite.menu.FlashFreq.40.build.flash_freq=40m + +lolin32-lite.menu.PartitionScheme.default=Default +lolin32-lite.menu.PartitionScheme.default.build.partitions=default +lolin32-lite.menu.PartitionScheme.no_ota=No OTA (Large APP) +lolin32-lite.menu.PartitionScheme.no_ota.build.partitions=no_ota +lolin32-lite.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lolin32-lite.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +lolin32-lite.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lolin32-lite.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +lolin32-lite.menu.CPUFreq.240=240MHz (WiFi/BT) +lolin32-lite.menu.CPUFreq.240.build.f_cpu=240000000L +lolin32-lite.menu.CPUFreq.160=160MHz (WiFi/BT) +lolin32-lite.menu.CPUFreq.160.build.f_cpu=160000000L +lolin32-lite.menu.CPUFreq.80=80MHz (WiFi/BT) +lolin32-lite.menu.CPUFreq.80.build.f_cpu=80000000L +lolin32-lite.menu.CPUFreq.40=40MHz (40MHz XTAL) +lolin32-lite.menu.CPUFreq.40.build.f_cpu=40000000L +lolin32-lite.menu.CPUFreq.26=26MHz (26MHz XTAL) +lolin32-lite.menu.CPUFreq.26.build.f_cpu=26000000L +lolin32-lite.menu.CPUFreq.20=20MHz (40MHz XTAL) +lolin32-lite.menu.CPUFreq.20.build.f_cpu=20000000L +lolin32-lite.menu.CPUFreq.13=13MHz (26MHz XTAL) +lolin32-lite.menu.CPUFreq.13.build.f_cpu=13000000L +lolin32-lite.menu.CPUFreq.10=10MHz (40MHz XTAL) +lolin32-lite.menu.CPUFreq.10.build.f_cpu=10000000L + +lolin32-lite.menu.UploadSpeed.921600=921600 +lolin32-lite.menu.UploadSpeed.921600.upload.speed=921600 +lolin32-lite.menu.UploadSpeed.115200=115200 +lolin32-lite.menu.UploadSpeed.115200.upload.speed=115200 +lolin32-lite.menu.UploadSpeed.256000.windows=256000 +lolin32-lite.menu.UploadSpeed.256000.upload.speed=256000 +lolin32-lite.menu.UploadSpeed.230400.windows.upload.speed=256000 +lolin32-lite.menu.UploadSpeed.230400=230400 +lolin32-lite.menu.UploadSpeed.230400.upload.speed=230400 +lolin32-lite.menu.UploadSpeed.460800.linux=460800 +lolin32-lite.menu.UploadSpeed.460800.macosx=460800 +lolin32-lite.menu.UploadSpeed.460800.upload.speed=460800 +lolin32-lite.menu.UploadSpeed.512000.windows=512000 +lolin32-lite.menu.UploadSpeed.512000.upload.speed=512000 + +lolin32-lite.menu.DebugLevel.none=None +lolin32-lite.menu.DebugLevel.none.build.code_debug=0 +lolin32-lite.menu.DebugLevel.error=Error +lolin32-lite.menu.DebugLevel.error.build.code_debug=1 +lolin32-lite.menu.DebugLevel.warn=Warn +lolin32-lite.menu.DebugLevel.warn.build.code_debug=2 +lolin32-lite.menu.DebugLevel.info=Info +lolin32-lite.menu.DebugLevel.info.build.code_debug=3 +lolin32-lite.menu.DebugLevel.debug=Debug +lolin32-lite.menu.DebugLevel.debug.build.code_debug=4 +lolin32-lite.menu.DebugLevel.verbose=Verbose +lolin32-lite.menu.DebugLevel.verbose.build.code_debug=5 + +lolin32-lite.menu.EraseFlash.none=Disabled +lolin32-lite.menu.EraseFlash.none.upload.erase_cmd= +lolin32-lite.menu.EraseFlash.all=Enabled +lolin32-lite.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +pocket_32.name=Dongsen Tech Pocket 32 + +pocket_32.bootloader.tool=esptool_py +pocket_32.bootloader.tool.default=esptool_py + +pocket_32.upload.tool=esptool_py +pocket_32.upload.tool.default=esptool_py +pocket_32.upload.tool.network=esp_ota + +pocket_32.upload.maximum_size=1310720 +pocket_32.upload.maximum_data_size=327680 +pocket_32.upload.flags= +pocket_32.upload.extra_flags= + +pocket_32.serial.disableDTR=true +pocket_32.serial.disableRTS=true + +pocket_32.build.tarch=xtensa +pocket_32.build.bootloader_addr=0x1000 +pocket_32.build.target=esp32 +pocket_32.build.mcu=esp32 +pocket_32.build.core=esp32 +pocket_32.build.variant=pocket_32 +pocket_32.build.board=Pocket32 + +pocket_32.build.f_cpu=240000000L +pocket_32.build.flash_mode=dio +pocket_32.build.flash_size=4MB +pocket_32.build.boot=dio +pocket_32.build.partitions=default +pocket_32.build.defines= + +pocket_32.menu.FlashFreq.80=80MHz +pocket_32.menu.FlashFreq.80.build.flash_freq=80m +pocket_32.menu.FlashFreq.40=40MHz +pocket_32.menu.FlashFreq.40.build.flash_freq=40m + +pocket_32.menu.UploadSpeed.921600=921600 +pocket_32.menu.UploadSpeed.921600.upload.speed=921600 +pocket_32.menu.UploadSpeed.115200=115200 +pocket_32.menu.UploadSpeed.115200.upload.speed=115200 +pocket_32.menu.UploadSpeed.256000.windows=256000 +pocket_32.menu.UploadSpeed.256000.upload.speed=256000 +pocket_32.menu.UploadSpeed.230400.windows.upload.speed=256000 +pocket_32.menu.UploadSpeed.230400=230400 +pocket_32.menu.UploadSpeed.230400.upload.speed=230400 +pocket_32.menu.UploadSpeed.460800.linux=460800 +pocket_32.menu.UploadSpeed.460800.macosx=460800 +pocket_32.menu.UploadSpeed.460800.upload.speed=460800 +pocket_32.menu.UploadSpeed.512000.windows=512000 +pocket_32.menu.UploadSpeed.512000.upload.speed=512000 + +pocket_32.menu.DebugLevel.none=None +pocket_32.menu.DebugLevel.none.build.code_debug=0 +pocket_32.menu.DebugLevel.error=Error +pocket_32.menu.DebugLevel.error.build.code_debug=1 +pocket_32.menu.DebugLevel.warn=Warn +pocket_32.menu.DebugLevel.warn.build.code_debug=2 +pocket_32.menu.DebugLevel.info=Info +pocket_32.menu.DebugLevel.info.build.code_debug=3 +pocket_32.menu.DebugLevel.debug=Debug +pocket_32.menu.DebugLevel.debug.build.code_debug=4 +pocket_32.menu.DebugLevel.verbose=Verbose +pocket_32.menu.DebugLevel.verbose.build.code_debug=5 + +pocket_32.menu.EraseFlash.none=Disabled +pocket_32.menu.EraseFlash.none.upload.erase_cmd= +pocket_32.menu.EraseFlash.all=Enabled +pocket_32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +WeMosBat.name=WeMos WiFi&Bluetooth Battery + +WeMosBat.bootloader.tool=esptool_py +WeMosBat.bootloader.tool.default=esptool_py + +WeMosBat.upload.tool=esptool_py +WeMosBat.upload.tool.default=esptool_py +WeMosBat.upload.tool.network=esp_ota + +WeMosBat.upload.maximum_size=1310720 +WeMosBat.upload.maximum_data_size=327680 +WeMosBat.upload.flags= +WeMosBat.upload.extra_flags= + +WeMosBat.serial.disableDTR=true +WeMosBat.serial.disableRTS=true + +WeMosBat.build.tarch=xtensa +WeMosBat.build.bootloader_addr=0x1000 +WeMosBat.build.target=esp32 +WeMosBat.build.mcu=esp32 +WeMosBat.build.core=esp32 +WeMosBat.build.variant=pocket_32 +WeMosBat.build.board=Pocket32 + +WeMosBat.build.f_cpu=240000000L +WeMosBat.build.flash_mode=dio +WeMosBat.build.flash_size=4MB +WeMosBat.build.boot=dio +WeMosBat.build.partitions=default +WeMosBat.build.defines= + +WeMosBat.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +WeMosBat.menu.PartitionScheme.default.build.partitions=default +WeMosBat.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +WeMosBat.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +WeMosBat.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +WeMosBat.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +WeMosBat.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +WeMosBat.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +WeMosBat.menu.PartitionScheme.minimal.build.partitions=minimal +WeMosBat.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +WeMosBat.menu.PartitionScheme.no_ota.build.partitions=no_ota +WeMosBat.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +WeMosBat.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +WeMosBat.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +WeMosBat.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +WeMosBat.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +WeMosBat.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +WeMosBat.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +WeMosBat.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +WeMosBat.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +WeMosBat.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +WeMosBat.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +WeMosBat.menu.PartitionScheme.huge_app.build.partitions=huge_app +WeMosBat.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +WeMosBat.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +WeMosBat.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +WeMosBat.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +WeMosBat.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +WeMosBat.menu.PartitionScheme.fatflash.build.partitions=ffat +WeMosBat.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +WeMosBat.menu.PartitionScheme.rainmaker=RainMaker 4MB +WeMosBat.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +WeMosBat.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +WeMosBat.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +WeMosBat.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +WeMosBat.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +WeMosBat.menu.FlashFreq.80=80MHz +WeMosBat.menu.FlashFreq.80.build.flash_freq=80m +WeMosBat.menu.FlashFreq.40=40MHz +WeMosBat.menu.FlashFreq.40.build.flash_freq=40m + +WeMosBat.menu.UploadSpeed.921600=921600 +WeMosBat.menu.UploadSpeed.921600.upload.speed=921600 +WeMosBat.menu.UploadSpeed.115200=115200 +WeMosBat.menu.UploadSpeed.115200.upload.speed=115200 +WeMosBat.menu.UploadSpeed.256000.windows=256000 +WeMosBat.menu.UploadSpeed.256000.upload.speed=256000 +WeMosBat.menu.UploadSpeed.230400.windows.upload.speed=256000 +WeMosBat.menu.UploadSpeed.230400=230400 +WeMosBat.menu.UploadSpeed.230400.upload.speed=230400 +WeMosBat.menu.UploadSpeed.460800.linux=460800 +WeMosBat.menu.UploadSpeed.460800.macosx=460800 +WeMosBat.menu.UploadSpeed.460800.upload.speed=460800 +WeMosBat.menu.UploadSpeed.512000.windows=512000 +WeMosBat.menu.UploadSpeed.512000.upload.speed=512000 + +WeMosBat.menu.DebugLevel.none=None +WeMosBat.menu.DebugLevel.none.build.code_debug=0 +WeMosBat.menu.DebugLevel.error=Error +WeMosBat.menu.DebugLevel.error.build.code_debug=1 +WeMosBat.menu.DebugLevel.warn=Warn +WeMosBat.menu.DebugLevel.warn.build.code_debug=2 +WeMosBat.menu.DebugLevel.info=Info +WeMosBat.menu.DebugLevel.info.build.code_debug=3 +WeMosBat.menu.DebugLevel.debug=Debug +WeMosBat.menu.DebugLevel.debug.build.code_debug=4 +WeMosBat.menu.DebugLevel.verbose=Verbose +WeMosBat.menu.DebugLevel.verbose.build.code_debug=5 + +WeMosBat.menu.EraseFlash.none=Disabled +WeMosBat.menu.EraseFlash.none.upload.erase_cmd= +WeMosBat.menu.EraseFlash.all=Enabled +WeMosBat.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +espea32.name=ESPea32 + +espea32.bootloader.tool=esptool_py +espea32.bootloader.tool.default=esptool_py + +espea32.upload.tool=esptool_py +espea32.upload.tool.default=esptool_py +espea32.upload.tool.network=esp_ota + +espea32.upload.maximum_size=1310720 +espea32.upload.maximum_data_size=327680 +espea32.upload.flags= +espea32.upload.extra_flags= + +espea32.serial.disableDTR=true +espea32.serial.disableRTS=true + +espea32.build.tarch=xtensa +espea32.build.bootloader_addr=0x1000 +espea32.build.target=esp32 +espea32.build.mcu=esp32 +espea32.build.core=esp32 +espea32.build.variant=espea32 +espea32.build.board=ESPea32 + +espea32.build.f_cpu=240000000L +espea32.build.flash_mode=dio +espea32.build.flash_size=4MB +espea32.build.boot=dio +espea32.build.partitions=default +espea32.build.defines= + +espea32.menu.FlashFreq.80=80MHz +espea32.menu.FlashFreq.80.build.flash_freq=80m +espea32.menu.FlashFreq.40=40MHz +espea32.menu.FlashFreq.40.build.flash_freq=40m + +espea32.menu.UploadSpeed.921600=921600 +espea32.menu.UploadSpeed.921600.upload.speed=921600 +espea32.menu.UploadSpeed.115200=115200 +espea32.menu.UploadSpeed.115200.upload.speed=115200 +espea32.menu.UploadSpeed.256000.windows=256000 +espea32.menu.UploadSpeed.256000.upload.speed=256000 +espea32.menu.UploadSpeed.230400.windows.upload.speed=256000 +espea32.menu.UploadSpeed.230400=230400 +espea32.menu.UploadSpeed.230400.upload.speed=230400 +espea32.menu.UploadSpeed.460800.linux=460800 +espea32.menu.UploadSpeed.460800.macosx=460800 +espea32.menu.UploadSpeed.460800.upload.speed=460800 +espea32.menu.UploadSpeed.512000.windows=512000 +espea32.menu.UploadSpeed.512000.upload.speed=512000 + +espea32.menu.DebugLevel.none=None +espea32.menu.DebugLevel.none.build.code_debug=0 +espea32.menu.DebugLevel.error=Error +espea32.menu.DebugLevel.error.build.code_debug=1 +espea32.menu.DebugLevel.warn=Warn +espea32.menu.DebugLevel.warn.build.code_debug=2 +espea32.menu.DebugLevel.info=Info +espea32.menu.DebugLevel.info.build.code_debug=3 +espea32.menu.DebugLevel.debug=Debug +espea32.menu.DebugLevel.debug.build.code_debug=4 +espea32.menu.DebugLevel.verbose=Verbose +espea32.menu.DebugLevel.verbose.build.code_debug=5 + +espea32.menu.EraseFlash.none=Disabled +espea32.menu.EraseFlash.none.upload.erase_cmd= +espea32.menu.EraseFlash.all=Enabled +espea32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +quantum.name=Noduino Quantum + +quantum.bootloader.tool=esptool_py +quantum.bootloader.tool.default=esptool_py + +quantum.upload.tool=esptool_py +quantum.upload.tool.default=esptool_py +quantum.upload.tool.network=esp_ota + +quantum.upload.maximum_size=1310720 +quantum.upload.maximum_data_size=327680 +quantum.upload.flags= +quantum.upload.extra_flags= + +quantum.serial.disableDTR=true +quantum.serial.disableRTS=true + +quantum.build.tarch=xtensa +quantum.build.bootloader_addr=0x1000 +quantum.build.target=esp32 +quantum.build.mcu=esp32 +quantum.build.core=esp32 +quantum.build.variant=quantum +quantum.build.board=QUANTUM + +quantum.build.f_cpu=240000000L +quantum.build.flash_mode=qio +quantum.build.flash_size=16MB +quantum.build.boot=dio +quantum.build.partitions=default +quantum.build.defines= + +quantum.menu.FlashFreq.80=80MHz +quantum.menu.FlashFreq.80.build.flash_freq=80m +quantum.menu.FlashFreq.40=40MHz +quantum.menu.FlashFreq.40.build.flash_freq=40m + +quantum.menu.UploadSpeed.921600=921600 +quantum.menu.UploadSpeed.921600.upload.speed=921600 +quantum.menu.UploadSpeed.115200=115200 +quantum.menu.UploadSpeed.115200.upload.speed=115200 +quantum.menu.UploadSpeed.256000.windows=256000 +quantum.menu.UploadSpeed.256000.upload.speed=256000 +quantum.menu.UploadSpeed.230400.windows.upload.speed=256000 +quantum.menu.UploadSpeed.230400=230400 +quantum.menu.UploadSpeed.230400.upload.speed=230400 +quantum.menu.UploadSpeed.460800.linux=460800 +quantum.menu.UploadSpeed.460800.macosx=460800 +quantum.menu.UploadSpeed.460800.upload.speed=460800 +quantum.menu.UploadSpeed.512000.windows=512000 +quantum.menu.UploadSpeed.512000.upload.speed=512000 + +quantum.menu.DebugLevel.none=None +quantum.menu.DebugLevel.none.build.code_debug=0 +quantum.menu.DebugLevel.error=Error +quantum.menu.DebugLevel.error.build.code_debug=1 +quantum.menu.DebugLevel.warn=Warn +quantum.menu.DebugLevel.warn.build.code_debug=2 +quantum.menu.DebugLevel.info=Info +quantum.menu.DebugLevel.info.build.code_debug=3 +quantum.menu.DebugLevel.debug=Debug +quantum.menu.DebugLevel.debug.build.code_debug=4 +quantum.menu.DebugLevel.verbose=Verbose +quantum.menu.DebugLevel.verbose.build.code_debug=5 + +quantum.menu.EraseFlash.none=Disabled +quantum.menu.EraseFlash.none.upload.erase_cmd= +quantum.menu.EraseFlash.all=Enabled +quantum.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +node32s.name=Node32s + +node32s.bootloader.tool=esptool_py +node32s.bootloader.tool.default=esptool_py + +node32s.upload.tool=esptool_py +node32s.upload.tool.default=esptool_py +node32s.upload.tool.network=esp_ota + +node32s.upload.maximum_size=1310720 +node32s.upload.maximum_data_size=327680 +node32s.upload.flags= +node32s.upload.extra_flags= + +node32s.serial.disableDTR=true +node32s.serial.disableRTS=true + +node32s.build.tarch=xtensa +node32s.build.bootloader_addr=0x1000 +node32s.build.target=esp32 +node32s.build.mcu=esp32 +node32s.build.core=esp32 +node32s.build.variant=node32s +node32s.build.board=Node32s + +node32s.build.f_cpu=240000000L +node32s.build.flash_mode=dio +node32s.build.flash_size=4MB +node32s.build.boot=dio +node32s.build.partitions=default +node32s.build.defines= + +node32s.menu.PartitionScheme.default=Default +node32s.menu.PartitionScheme.default.build.partitions=default +node32s.menu.PartitionScheme.no_ota=No OTA (Large APP) +node32s.menu.PartitionScheme.no_ota.build.partitions=no_ota +node32s.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +node32s.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +node32s.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +node32s.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +node32s.menu.FlashFreq.80=80MHz +node32s.menu.FlashFreq.80.build.flash_freq=80m +node32s.menu.FlashFreq.40=40MHz +node32s.menu.FlashFreq.40.build.flash_freq=40m + +node32s.menu.UploadSpeed.921600=921600 +node32s.menu.UploadSpeed.921600.upload.speed=921600 +node32s.menu.UploadSpeed.115200=115200 +node32s.menu.UploadSpeed.115200.upload.speed=115200 +node32s.menu.UploadSpeed.256000.windows=256000 +node32s.menu.UploadSpeed.256000.upload.speed=256000 +node32s.menu.UploadSpeed.230400.windows.upload.speed=256000 +node32s.menu.UploadSpeed.230400=230400 +node32s.menu.UploadSpeed.230400.upload.speed=230400 +node32s.menu.UploadSpeed.460800.linux=460800 +node32s.menu.UploadSpeed.460800.macosx=460800 +node32s.menu.UploadSpeed.460800.upload.speed=460800 +node32s.menu.UploadSpeed.512000.windows=512000 +node32s.menu.UploadSpeed.512000.upload.speed=512000 + +node32s.menu.DebugLevel.none=None +node32s.menu.DebugLevel.none.build.code_debug=0 +node32s.menu.DebugLevel.error=Error +node32s.menu.DebugLevel.error.build.code_debug=1 +node32s.menu.DebugLevel.warn=Warn +node32s.menu.DebugLevel.warn.build.code_debug=2 +node32s.menu.DebugLevel.info=Info +node32s.menu.DebugLevel.info.build.code_debug=3 +node32s.menu.DebugLevel.debug=Debug +node32s.menu.DebugLevel.debug.build.code_debug=4 +node32s.menu.DebugLevel.verbose=Verbose +node32s.menu.DebugLevel.verbose.build.code_debug=5 + +node32s.menu.EraseFlash.none=Disabled +node32s.menu.EraseFlash.none.upload.erase_cmd= +node32s.menu.EraseFlash.all=Enabled +node32s.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +hornbill32dev.name=Hornbill ESP32 Dev + +hornbill32dev.bootloader.tool=esptool_py +hornbill32dev.bootloader.tool.default=esptool_py + +hornbill32dev.upload.tool=esptool_py +hornbill32dev.upload.tool.default=esptool_py +hornbill32dev.upload.tool.network=esp_ota + +hornbill32dev.upload.maximum_size=1310720 +hornbill32dev.upload.maximum_data_size=327680 +hornbill32dev.upload.flags= +hornbill32dev.upload.extra_flags= + +hornbill32dev.serial.disableDTR=true +hornbill32dev.serial.disableRTS=true + +hornbill32dev.build.tarch=xtensa +hornbill32dev.build.bootloader_addr=0x1000 +hornbill32dev.build.target=esp32 +hornbill32dev.build.mcu=esp32 +hornbill32dev.build.core=esp32 +hornbill32dev.build.variant=hornbill32dev +hornbill32dev.build.board=HORNBILL_ESP32_DEV + +hornbill32dev.build.f_cpu=240000000L +hornbill32dev.build.flash_mode=dio +hornbill32dev.build.flash_size=4MB +hornbill32dev.build.boot=dio +hornbill32dev.build.partitions=default +hornbill32dev.build.defines= + +hornbill32dev.menu.FlashFreq.80=80MHz +hornbill32dev.menu.FlashFreq.80.build.flash_freq=80m +hornbill32dev.menu.FlashFreq.40=40MHz +hornbill32dev.menu.FlashFreq.40.build.flash_freq=40m + +hornbill32dev.menu.UploadSpeed.921600=921600 +hornbill32dev.menu.UploadSpeed.921600.upload.speed=921600 +hornbill32dev.menu.UploadSpeed.115200=115200 +hornbill32dev.menu.UploadSpeed.115200.upload.speed=115200 +hornbill32dev.menu.UploadSpeed.256000.windows=256000 +hornbill32dev.menu.UploadSpeed.256000.upload.speed=256000 +hornbill32dev.menu.UploadSpeed.230400.windows.upload.speed=256000 +hornbill32dev.menu.UploadSpeed.230400=230400 +hornbill32dev.menu.UploadSpeed.230400.upload.speed=230400 +hornbill32dev.menu.UploadSpeed.460800.linux=460800 +hornbill32dev.menu.UploadSpeed.460800.macosx=460800 +hornbill32dev.menu.UploadSpeed.460800.upload.speed=460800 +hornbill32dev.menu.UploadSpeed.512000.windows=512000 +hornbill32dev.menu.UploadSpeed.512000.upload.speed=512000 + +hornbill32dev.menu.DebugLevel.none=None +hornbill32dev.menu.DebugLevel.none.build.code_debug=0 +hornbill32dev.menu.DebugLevel.error=Error +hornbill32dev.menu.DebugLevel.error.build.code_debug=1 +hornbill32dev.menu.DebugLevel.warn=Warn +hornbill32dev.menu.DebugLevel.warn.build.code_debug=2 +hornbill32dev.menu.DebugLevel.info=Info +hornbill32dev.menu.DebugLevel.info.build.code_debug=3 +hornbill32dev.menu.DebugLevel.debug=Debug +hornbill32dev.menu.DebugLevel.debug.build.code_debug=4 +hornbill32dev.menu.DebugLevel.verbose=Verbose +hornbill32dev.menu.DebugLevel.verbose.build.code_debug=5 + +hornbill32dev.menu.EraseFlash.none=Disabled +hornbill32dev.menu.EraseFlash.none.upload.erase_cmd= +hornbill32dev.menu.EraseFlash.all=Enabled +hornbill32dev.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +hornbill32minima.name=Hornbill ESP32 Minima + +hornbill32minima.bootloader.tool=esptool_py +hornbill32minima.bootloader.tool.default=esptool_py + +hornbill32minima.upload.tool=esptool_py +hornbill32minima.upload.tool.default=esptool_py +hornbill32minima.upload.tool.network=esp_ota + +hornbill32minima.upload.maximum_size=1310720 +hornbill32minima.upload.maximum_data_size=327680 +hornbill32minima.upload.flags= +hornbill32minima.upload.extra_flags= + +hornbill32minima.serial.disableDTR=true +hornbill32minima.serial.disableRTS=true + +hornbill32minima.build.tarch=xtensa +hornbill32minima.build.bootloader_addr=0x1000 +hornbill32minima.build.target=esp32 +hornbill32minima.build.mcu=esp32 +hornbill32minima.build.core=esp32 +hornbill32minima.build.variant=hornbill32minima +hornbill32minima.build.board=HORNBILL_ESP32_MINIMA +hornbill32minima.build.f_cpu=240000000L +hornbill32minima.build.flash_mode=dio +hornbill32minima.build.flash_size=4MB +hornbill32minima.build.boot=dio +hornbill32minima.build.partitions=default +hornbill32minima.build.defines= + +hornbill32minima.menu.FlashFreq.80=80MHz +hornbill32minima.menu.FlashFreq.80.build.flash_freq=80m +hornbill32minima.menu.FlashFreq.40=40MHz +hornbill32minima.menu.FlashFreq.40.build.flash_freq=40m + +hornbill32minima.menu.UploadSpeed.921600=921600 +hornbill32minima.menu.UploadSpeed.921600.upload.speed=921600 +hornbill32minima.menu.UploadSpeed.115200=115200 +hornbill32minima.menu.UploadSpeed.115200.upload.speed=115200 +hornbill32minima.menu.UploadSpeed.256000.windows=256000 +hornbill32minima.menu.UploadSpeed.256000.upload.speed=256000 +hornbill32minima.menu.UploadSpeed.230400.windows.upload.speed=256000 +hornbill32minima.menu.UploadSpeed.230400=230400 +hornbill32minima.menu.UploadSpeed.230400.upload.speed=230400 +hornbill32minima.menu.UploadSpeed.460800.linux=460800 +hornbill32minima.menu.UploadSpeed.460800.macosx=460800 +hornbill32minima.menu.UploadSpeed.460800.upload.speed=460800 +hornbill32minima.menu.UploadSpeed.512000.windows=512000 +hornbill32minima.menu.UploadSpeed.512000.upload.speed=512000 + +hornbill32minima.menu.DebugLevel.none=None +hornbill32minima.menu.DebugLevel.none.build.code_debug=0 +hornbill32minima.menu.DebugLevel.error=Error +hornbill32minima.menu.DebugLevel.error.build.code_debug=1 +hornbill32minima.menu.DebugLevel.warn=Warn +hornbill32minima.menu.DebugLevel.warn.build.code_debug=2 +hornbill32minima.menu.DebugLevel.info=Info +hornbill32minima.menu.DebugLevel.info.build.code_debug=3 +hornbill32minima.menu.DebugLevel.debug=Debug +hornbill32minima.menu.DebugLevel.debug.build.code_debug=4 +hornbill32minima.menu.DebugLevel.verbose=Verbose +hornbill32minima.menu.DebugLevel.verbose.build.code_debug=5 + +hornbill32minima.menu.EraseFlash.none=Disabled +hornbill32minima.menu.EraseFlash.none.upload.erase_cmd= +hornbill32minima.menu.EraseFlash.all=Enabled +hornbill32minima.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +dfrobot_beetle_esp32c3.name=DFRobot Beetle ESP32-C3 + +dfrobot_beetle_esp32c3.bootloader.tool=esptool_py +dfrobot_beetle_esp32c3.bootloader.tool.default=esptool_py + +dfrobot_beetle_esp32c3.upload.tool=esptool_py +dfrobot_beetle_esp32c3.upload.tool.default=esptool_py +dfrobot_beetle_esp32c3.upload.tool.network=esp_ota + +dfrobot_beetle_esp32c3.upload.maximum_size=1310720 +dfrobot_beetle_esp32c3.upload.maximum_data_size=327680 +dfrobot_beetle_esp32c3.upload.flags= +dfrobot_beetle_esp32c3.upload.extra_flags= +dfrobot_beetle_esp32c3.upload.use_1200bps_touch=false +dfrobot_beetle_esp32c3.upload.wait_for_upload_port=false + +dfrobot_beetle_esp32c3.serial.disableDTR=false +dfrobot_beetle_esp32c3.serial.disableRTS=false + +dfrobot_beetle_esp32c3.build.tarch=riscv32 +dfrobot_beetle_esp32c3.build.target=esp +dfrobot_beetle_esp32c3.build.mcu=esp32c3 +dfrobot_beetle_esp32c3.build.core=esp32 +dfrobot_beetle_esp32c3.build.variant=dfrobot_beetle_esp32c3 +#dfrobot_beetle_esp32c3.build.board=DFROBOT_BEETLE_ESP32_C3 +dfrobot_beetle_esp32c3.build.board=ESP32C3_DEV +dfrobot_beetle_esp32c3.build.bootloader_addr=0x0 + +dfrobot_beetle_esp32c3.build.cdc_on_boot=0 +dfrobot_beetle_esp32c3.build.f_cpu=160000000L +dfrobot_beetle_esp32c3.build.flash_size=4MB +dfrobot_beetle_esp32c3.build.flash_freq=80m +dfrobot_beetle_esp32c3.build.flash_mode=qio +dfrobot_beetle_esp32c3.build.boot=qio +dfrobot_beetle_esp32c3.build.partitions=default +dfrobot_beetle_esp32c3.build.defines= + +dfrobot_beetle_esp32c3.menu.CDCOnBoot.default=Disabled +dfrobot_beetle_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +dfrobot_beetle_esp32c3.menu.CDCOnBoot.cdc=Enabled +dfrobot_beetle_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +dfrobot_beetle_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.default.build.partitions=default +dfrobot_beetle_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_beetle_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +dfrobot_beetle_esp32c3.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_beetle_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_beetle_esp32c3.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_beetle_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_beetle_esp32c3.menu.CPUFreq.40=40MHz +dfrobot_beetle_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_beetle_esp32c3.menu.CPUFreq.20=20MHz +dfrobot_beetle_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_beetle_esp32c3.menu.CPUFreq.10=10MHz +dfrobot_beetle_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_beetle_esp32c3.menu.FlashMode.qio=QIO +dfrobot_beetle_esp32c3.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_beetle_esp32c3.menu.FlashMode.qio.build.boot=qio +dfrobot_beetle_esp32c3.menu.FlashMode.dio=DIO +dfrobot_beetle_esp32c3.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_beetle_esp32c3.menu.FlashMode.dio.build.boot=dio + +dfrobot_beetle_esp32c3.menu.FlashFreq.80=80MHz +dfrobot_beetle_esp32c3.menu.FlashFreq.80.build.flash_freq=80m +dfrobot_beetle_esp32c3.menu.FlashFreq.40=40MHz +dfrobot_beetle_esp32c3.menu.FlashFreq.40.build.flash_freq=40m + +dfrobot_beetle_esp32c3.menu.FlashSize.4M=4MB (32Mb) +dfrobot_beetle_esp32c3.menu.FlashSize.4M.build.flash_size=4MB + +dfrobot_beetle_esp32c3.menu.UploadSpeed.921600=921600 +dfrobot_beetle_esp32c3.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_beetle_esp32c3.menu.UploadSpeed.115200=115200 +dfrobot_beetle_esp32c3.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_beetle_esp32c3.menu.UploadSpeed.256000.windows=256000 +dfrobot_beetle_esp32c3.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_beetle_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_beetle_esp32c3.menu.UploadSpeed.230400=230400 +dfrobot_beetle_esp32c3.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.linux=460800 +dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.macosx=460800 +dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_beetle_esp32c3.menu.UploadSpeed.512000.windows=512000 +dfrobot_beetle_esp32c3.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_beetle_esp32c3.menu.DebugLevel.none=None +dfrobot_beetle_esp32c3.menu.DebugLevel.none.build.code_debug=0 +dfrobot_beetle_esp32c3.menu.DebugLevel.error=Error +dfrobot_beetle_esp32c3.menu.DebugLevel.error.build.code_debug=1 +dfrobot_beetle_esp32c3.menu.DebugLevel.warn=Warn +dfrobot_beetle_esp32c3.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_beetle_esp32c3.menu.DebugLevel.info=Info +dfrobot_beetle_esp32c3.menu.DebugLevel.info.build.code_debug=3 +dfrobot_beetle_esp32c3.menu.DebugLevel.debug=Debug +dfrobot_beetle_esp32c3.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_beetle_esp32c3.menu.DebugLevel.verbose=Verbose +dfrobot_beetle_esp32c3.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_beetle_esp32c3.menu.EraseFlash.none=Disabled +dfrobot_beetle_esp32c3.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_beetle_esp32c3.menu.EraseFlash.all=Enabled +dfrobot_beetle_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +dfrobot_beetle_esp32c6.name=DFRobot Beetle ESP32-C6 + +dfrobot_beetle_esp32c6.bootloader.tool=esptool_py +dfrobot_beetle_esp32c6.bootloader.tool.default=esptool_py + +dfrobot_beetle_esp32c6.upload.tool=esptool_py +dfrobot_beetle_esp32c6.upload.tool.default=esptool_py +dfrobot_beetle_esp32c6.upload.tool.network=esp_ota + +dfrobot_beetle_esp32c6.upload.maximum_size=1310720 +dfrobot_beetle_esp32c6.upload.maximum_data_size=327680 +dfrobot_beetle_esp32c6.upload.flags= +dfrobot_beetle_esp32c6.upload.extra_flags= +dfrobot_beetle_esp32c6.upload.use_1200bps_touch=false +dfrobot_beetle_esp32c6.upload.wait_for_upload_port=false + +dfrobot_beetle_esp32c6.serial.disableDTR=false +dfrobot_beetle_esp32c6.serial.disableRTS=false + +dfrobot_beetle_esp32c6.build.tarch=riscv32 +dfrobot_beetle_esp32c6.build.target=esp +dfrobot_beetle_esp32c6.build.mcu=esp32c6 +dfrobot_beetle_esp32c6.build.core=esp32 +dfrobot_beetle_esp32c6.build.variant=dfrobot_beetle_esp32c6 +dfrobot_beetle_esp32c6.build.board=DFROBOT_BEETLE_ESP32C6 +dfrobot_beetle_esp32c6.build.bootloader_addr=0x0 + +dfrobot_beetle_esp32c6.build.cdc_on_boot=0 +dfrobot_beetle_esp32c6.build.f_cpu=160000000L +dfrobot_beetle_esp32c6.build.flash_size=4MB +dfrobot_beetle_esp32c6.build.flash_freq=80m +dfrobot_beetle_esp32c6.build.flash_mode=qio +dfrobot_beetle_esp32c6.build.boot=qio +dfrobot_beetle_esp32c6.build.partitions=default +dfrobot_beetle_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +dfrobot_beetle_esp32c6.menu.JTAGAdapter.default=Disabled +dfrobot_beetle_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +dfrobot_beetle_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +dfrobot_beetle_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +dfrobot_beetle_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +dfrobot_beetle_esp32c6.menu.CDCOnBoot.default=Disabled +dfrobot_beetle_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +dfrobot_beetle_esp32c6.menu.CDCOnBoot.cdc=Enabled +dfrobot_beetle_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +dfrobot_beetle_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.default.build.partitions=default +dfrobot_beetle_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_beetle_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +dfrobot_beetle_esp32c6.menu.PartitionScheme.custom=Custom +dfrobot_beetle_esp32c6.menu.PartitionScheme.custom.build.partitions= +dfrobot_beetle_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +dfrobot_beetle_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_beetle_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_beetle_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_beetle_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_beetle_esp32c6.menu.CPUFreq.40=40MHz +dfrobot_beetle_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_beetle_esp32c6.menu.CPUFreq.20=20MHz +dfrobot_beetle_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_beetle_esp32c6.menu.CPUFreq.10=10MHz +dfrobot_beetle_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_beetle_esp32c6.menu.FlashMode.qio=QIO +dfrobot_beetle_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_beetle_esp32c6.menu.FlashMode.qio.build.boot=qio +dfrobot_beetle_esp32c6.menu.FlashMode.dio=DIO +dfrobot_beetle_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_beetle_esp32c6.menu.FlashMode.dio.build.boot=dio + +dfrobot_beetle_esp32c6.menu.FlashFreq.80=80MHz +dfrobot_beetle_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +dfrobot_beetle_esp32c6.menu.FlashFreq.40=40MHz +dfrobot_beetle_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +dfrobot_beetle_esp32c6.menu.FlashSize.4M=4MB (32Mb) +dfrobot_beetle_esp32c6.menu.FlashSize.4M.build.flash_size=4MB + +dfrobot_beetle_esp32c6.menu.UploadSpeed.921600=921600 +dfrobot_beetle_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_beetle_esp32c6.menu.UploadSpeed.115200=115200 +dfrobot_beetle_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_beetle_esp32c6.menu.UploadSpeed.256000.windows=256000 +dfrobot_beetle_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_beetle_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_beetle_esp32c6.menu.UploadSpeed.230400=230400 +dfrobot_beetle_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.linux=460800 +dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.macosx=460800 +dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_beetle_esp32c6.menu.UploadSpeed.512000.windows=512000 +dfrobot_beetle_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_beetle_esp32c6.menu.DebugLevel.none=None +dfrobot_beetle_esp32c6.menu.DebugLevel.none.build.code_debug=0 +dfrobot_beetle_esp32c6.menu.DebugLevel.error=Error +dfrobot_beetle_esp32c6.menu.DebugLevel.error.build.code_debug=1 +dfrobot_beetle_esp32c6.menu.DebugLevel.warn=Warn +dfrobot_beetle_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_beetle_esp32c6.menu.DebugLevel.info=Info +dfrobot_beetle_esp32c6.menu.DebugLevel.info.build.code_debug=3 +dfrobot_beetle_esp32c6.menu.DebugLevel.debug=Debug +dfrobot_beetle_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_beetle_esp32c6.menu.DebugLevel.verbose=Verbose +dfrobot_beetle_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_beetle_esp32c6.menu.EraseFlash.none=Disabled +dfrobot_beetle_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_beetle_esp32c6.menu.EraseFlash.all=Enabled +dfrobot_beetle_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +dfrobot_beetle_esp32c6.menu.ZigbeeMode.default=Disabled +dfrobot_beetle_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +dfrobot_beetle_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +dfrobot_firebeetle2_esp32e.name=FireBeetle 2 ESP32-E + +dfrobot_firebeetle2_esp32e.upload.tool=esptool_py +dfrobot_firebeetle2_esp32e.upload.tool.default=esptool_py +dfrobot_firebeetle2_esp32e.upload.maximum_size=1310720 +dfrobot_firebeetle2_esp32e.upload.maximum_data_size=327680 +dfrobot_firebeetle2_esp32e.upload.flags= +dfrobot_firebeetle2_esp32e.upload.extra_flags= + +dfrobot_firebeetle2_esp32e.serial.disableDTR=true +dfrobot_firebeetle2_esp32e.serial.disableRTS=true + +dfrobot_firebeetle2_esp32e.build.tarch=xtensa +dfrobot_firebeetle2_esp32e.build.bootloader_addr=0x1000 +dfrobot_firebeetle2_esp32e.build.target=esp32 +dfrobot_firebeetle2_esp32e.build.mcu=esp32 +dfrobot_firebeetle2_esp32e.build.core=esp32 +dfrobot_firebeetle2_esp32e.build.variant=dfrobot_firebeetle2_esp32e +dfrobot_firebeetle2_esp32e.build.board=DFROBOT_FIREBEETLE_2_ESP32E + +dfrobot_firebeetle2_esp32e.build.f_cpu=240000000L +dfrobot_firebeetle2_esp32e.build.flash_size=4MB +dfrobot_firebeetle2_esp32e.build.flash_freq=40m +dfrobot_firebeetle2_esp32e.build.flash_mode=dio +dfrobot_firebeetle2_esp32e.build.boot=dio +dfrobot_firebeetle2_esp32e.build.partitions=default +dfrobot_firebeetle2_esp32e.build.defines= +dfrobot_firebeetle2_esp32e.build.loop_core= +dfrobot_firebeetle2_esp32e.build.event_core= + +dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled=Disabled +dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled.build.defines= +dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled.build.extra_libs= +dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled=Enabled +dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled.build.extra_libs= + +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default.build.partitions=default +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash.build.partitions=ffat +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +dfrobot_firebeetle2_esp32e.menu.CPUFreq.240=240MHz (WiFi/BT) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.240.build.f_cpu=240000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.160=160MHz (WiFi/BT) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.80=80MHz (WiFi/BT) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.40=40MHz (40MHz XTAL) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.26=26MHz (26MHz XTAL) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.26.build.f_cpu=26000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.20=20MHz (40MHz XTAL) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.13=13MHz (26MHz XTAL) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.13.build.f_cpu=13000000L +dfrobot_firebeetle2_esp32e.menu.CPUFreq.10=10MHz (40MHz XTAL) +dfrobot_firebeetle2_esp32e.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_firebeetle2_esp32e.menu.FlashMode.qio=QIO +dfrobot_firebeetle2_esp32e.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_firebeetle2_esp32e.menu.FlashMode.qio.build.boot=qio +dfrobot_firebeetle2_esp32e.menu.FlashMode.dio=DIO +dfrobot_firebeetle2_esp32e.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_firebeetle2_esp32e.menu.FlashMode.dio.build.boot=dio + +dfrobot_firebeetle2_esp32e.menu.FlashFreq.80=80MHz +dfrobot_firebeetle2_esp32e.menu.FlashFreq.80.build.flash_freq=80m +dfrobot_firebeetle2_esp32e.menu.FlashFreq.40=40MHz +dfrobot_firebeetle2_esp32e.menu.FlashFreq.40.build.flash_freq=40m + +dfrobot_firebeetle2_esp32e.menu.FlashSize.4M=4MB (32Mb) +dfrobot_firebeetle2_esp32e.menu.FlashSize.4M.build.flash_size=4MB +dfrobot_firebeetle2_esp32e.menu.FlashSize.8M=8MB (64Mb) +dfrobot_firebeetle2_esp32e.menu.FlashSize.8M.build.flash_size=8MB +dfrobot_firebeetle2_esp32e.menu.FlashSize.2M=2MB (16Mb) +dfrobot_firebeetle2_esp32e.menu.FlashSize.2M.build.flash_size=2MB +dfrobot_firebeetle2_esp32e.menu.FlashSize.16M=16MB (128Mb) +dfrobot_firebeetle2_esp32e.menu.FlashSize.16M.build.flash_size=16MB + +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.921600=921600 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.115200=115200 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.256000.windows=256000 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400=230400 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.linux=460800 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.macosx=460800 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.512000.windows=512000 +dfrobot_firebeetle2_esp32e.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_firebeetle2_esp32e.menu.LoopCore.1=Core 1 +dfrobot_firebeetle2_esp32e.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +dfrobot_firebeetle2_esp32e.menu.LoopCore.0=Core 0 +dfrobot_firebeetle2_esp32e.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +dfrobot_firebeetle2_esp32e.menu.EventsCore.1=Core 1 +dfrobot_firebeetle2_esp32e.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +dfrobot_firebeetle2_esp32e.menu.EventsCore.0=Core 0 +dfrobot_firebeetle2_esp32e.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +dfrobot_firebeetle2_esp32e.menu.DebugLevel.none=None +dfrobot_firebeetle2_esp32e.menu.DebugLevel.none.build.code_debug=0 +dfrobot_firebeetle2_esp32e.menu.DebugLevel.error=Error +dfrobot_firebeetle2_esp32e.menu.DebugLevel.error.build.code_debug=1 +dfrobot_firebeetle2_esp32e.menu.DebugLevel.warn=Warn +dfrobot_firebeetle2_esp32e.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_firebeetle2_esp32e.menu.DebugLevel.info=Info +dfrobot_firebeetle2_esp32e.menu.DebugLevel.info.build.code_debug=3 +dfrobot_firebeetle2_esp32e.menu.DebugLevel.debug=Debug +dfrobot_firebeetle2_esp32e.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_firebeetle2_esp32e.menu.DebugLevel.verbose=Verbose +dfrobot_firebeetle2_esp32e.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_firebeetle2_esp32e.menu.EraseFlash.none=Disabled +dfrobot_firebeetle2_esp32e.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_firebeetle2_esp32e.menu.EraseFlash.all=Enabled +dfrobot_firebeetle2_esp32e.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +dfrobot_firebeetle2_esp32s3.name=DFRobot Firebeetle 2 ESP32-S3 + +dfrobot_firebeetle2_esp32s3.bootloader.tool=esptool_py +dfrobot_firebeetle2_esp32s3.bootloader.tool.default=esptool_py + +dfrobot_firebeetle2_esp32s3.upload.tool=esptool_py +dfrobot_firebeetle2_esp32s3.upload.tool.default=esptool_py +dfrobot_firebeetle2_esp32s3.upload.tool.network=esp_ota + +dfrobot_firebeetle2_esp32s3.upload.maximum_size=1310720 +dfrobot_firebeetle2_esp32s3.upload.maximum_data_size=327680 +dfrobot_firebeetle2_esp32s3.upload.flags= +dfrobot_firebeetle2_esp32s3.upload.extra_flags= +dfrobot_firebeetle2_esp32s3.upload.use_1200bps_touch=false +dfrobot_firebeetle2_esp32s3.upload.wait_for_upload_port=false + +dfrobot_firebeetle2_esp32s3.serial.disableDTR=false +dfrobot_firebeetle2_esp32s3.serial.disableRTS=false + +dfrobot_firebeetle2_esp32s3.build.tarch=xtensa +dfrobot_firebeetle2_esp32s3.build.bootloader_addr=0x0 +dfrobot_firebeetle2_esp32s3.build.target=esp32s3 +dfrobot_firebeetle2_esp32s3.build.mcu=esp32s3 +dfrobot_firebeetle2_esp32s3.build.core=esp32 +dfrobot_firebeetle2_esp32s3.build.variant=dfrobot_firebeetle2_esp32s3 +dfrobot_firebeetle2_esp32s3.build.board=ESP32S3_DEV +#dfrobot_firebeetle2_esp32s3.build.board=DFROBOT_FIREBEETLE_2_ESP32S3 + +dfrobot_firebeetle2_esp32s3.build.usb_mode=1 +dfrobot_firebeetle2_esp32s3.build.cdc_on_boot=0 +dfrobot_firebeetle2_esp32s3.build.msc_on_boot=0 +dfrobot_firebeetle2_esp32s3.build.dfu_on_boot=0 +dfrobot_firebeetle2_esp32s3.build.f_cpu=240000000L +dfrobot_firebeetle2_esp32s3.build.flash_size=4MB +dfrobot_firebeetle2_esp32s3.build.flash_freq=80m +dfrobot_firebeetle2_esp32s3.build.flash_mode=dio +dfrobot_firebeetle2_esp32s3.build.boot=qio +dfrobot_firebeetle2_esp32s3.build.boot_freq=80m +dfrobot_firebeetle2_esp32s3.build.partitions=default +dfrobot_firebeetle2_esp32s3.build.defines= +dfrobot_firebeetle2_esp32s3.build.loop_core= +dfrobot_firebeetle2_esp32s3.build.event_core= +dfrobot_firebeetle2_esp32s3.build.flash_type=qio +dfrobot_firebeetle2_esp32s3.build.psram_type=qspi +dfrobot_firebeetle2_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled=Disabled +dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled.build.defines= +dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi=OPI PSRAM +dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio=QIO 80MHz +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.boot=qio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_type=qio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120=QIO 120MHz +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.boot=qio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_type=qio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio=DIO 80MHz +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.boot=dio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_type=qio +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi=OPI 80MHz +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.boot=opi +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_freq=80m +dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_type=opi + +dfrobot_firebeetle2_esp32s3.menu.FlashSize.4M=4MB (32Mb) +dfrobot_firebeetle2_esp32s3.menu.FlashSize.4M.build.flash_size=4MB +dfrobot_firebeetle2_esp32s3.menu.FlashSize.8M=8MB (64Mb) +dfrobot_firebeetle2_esp32s3.menu.FlashSize.8M.build.flash_size=8MB +dfrobot_firebeetle2_esp32s3.menu.FlashSize.16M=16MB (128Mb) +dfrobot_firebeetle2_esp32s3.menu.FlashSize.16M.build.flash_size=16MB +#dfrobot_firebeetle2_esp32s3.menu.FlashSize.32M=32MB (256Mb) +#dfrobot_firebeetle2_esp32s3.menu.FlashSize.32M.build.flash_size=32MB + +dfrobot_firebeetle2_esp32s3.menu.LoopCore.1=Core 1 +dfrobot_firebeetle2_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +dfrobot_firebeetle2_esp32s3.menu.LoopCore.0=Core 0 +dfrobot_firebeetle2_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +dfrobot_firebeetle2_esp32s3.menu.EventsCore.1=Core 1 +dfrobot_firebeetle2_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +dfrobot_firebeetle2_esp32s3.menu.EventsCore.0=Core 0 +dfrobot_firebeetle2_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +dfrobot_firebeetle2_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +dfrobot_firebeetle2_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +dfrobot_firebeetle2_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +dfrobot_firebeetle2_esp32s3.menu.USBMode.default.build.usb_mode=0 + +dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.default=Disabled +dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.cdc=Enabled +dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.default=Disabled +dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.default=Disabled +dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +dfrobot_firebeetle2_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +dfrobot_firebeetle2_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +dfrobot_firebeetle2_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default.build.partitions=default +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.40=40MHz +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.20=20MHz +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.10=10MHz +dfrobot_firebeetle2_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.921600=921600 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.115200=115200 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.256000.windows=256000 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400=230400 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.linux=460800 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.macosx=460800 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.512000.windows=512000 +dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.none=None +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.none.build.code_debug=0 +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.error=Error +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.error.build.code_debug=1 +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.warn=Warn +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.info=Info +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.info.build.code_debug=3 +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.debug=Debug +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.verbose=Verbose +dfrobot_firebeetle2_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_firebeetle2_esp32s3.menu.EraseFlash.none=Disabled +dfrobot_firebeetle2_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_firebeetle2_esp32s3.menu.EraseFlash.all=Enabled +dfrobot_firebeetle2_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +dfrobot_firebeetle2_esp32c6.name=DFRobot FireBeetle 2 ESP32-C6 + +dfrobot_firebeetle2_esp32c6.bootloader.tool=esptool_py +dfrobot_firebeetle2_esp32c6.bootloader.tool.default=esptool_py + +dfrobot_firebeetle2_esp32c6.upload.tool=esptool_py +dfrobot_firebeetle2_esp32c6.upload.tool.default=esptool_py +dfrobot_firebeetle2_esp32c6.upload.tool.network=esp_ota + +dfrobot_firebeetle2_esp32c6.upload.maximum_size=1310720 +dfrobot_firebeetle2_esp32c6.upload.maximum_data_size=327680 +dfrobot_firebeetle2_esp32c6.upload.flags= +dfrobot_firebeetle2_esp32c6.upload.extra_flags= +dfrobot_firebeetle2_esp32c6.upload.use_1200bps_touch=false +dfrobot_firebeetle2_esp32c6.upload.wait_for_upload_port=false + +dfrobot_firebeetle2_esp32c6.serial.disableDTR=false +dfrobot_firebeetle2_esp32c6.serial.disableRTS=false + +dfrobot_firebeetle2_esp32c6.build.tarch=riscv32 +dfrobot_firebeetle2_esp32c6.build.target=esp +dfrobot_firebeetle2_esp32c6.build.mcu=esp32c6 +dfrobot_firebeetle2_esp32c6.build.core=esp32 +dfrobot_firebeetle2_esp32c6.build.variant=dfrobot_firebeetle2_esp32c6 +dfrobot_firebeetle2_esp32c6.build.board=DFROBOT_FIREBEETLE_2_ESP32C6 +dfrobot_firebeetle2_esp32c6.build.bootloader_addr=0x0 + +dfrobot_firebeetle2_esp32c6.build.cdc_on_boot=0 +dfrobot_firebeetle2_esp32c6.build.f_cpu=160000000L +dfrobot_firebeetle2_esp32c6.build.flash_size=4MB +dfrobot_firebeetle2_esp32c6.build.flash_freq=80m +dfrobot_firebeetle2_esp32c6.build.flash_mode=qio +dfrobot_firebeetle2_esp32c6.build.boot=qio +dfrobot_firebeetle2_esp32c6.build.partitions=default +dfrobot_firebeetle2_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.default=Disabled +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.default=Disabled +dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.cdc=Enabled +dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.default.build.partitions=default +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom=Custom +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom.build.partitions= +dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.40=40MHz +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.20=20MHz +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.10=10MHz +dfrobot_firebeetle2_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio=QIO +dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio.build.boot=qio +dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio=DIO +dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio.build.boot=dio + +dfrobot_firebeetle2_esp32c6.menu.FlashFreq.80=80MHz +dfrobot_firebeetle2_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +dfrobot_firebeetle2_esp32c6.menu.FlashFreq.40=40MHz +dfrobot_firebeetle2_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +dfrobot_firebeetle2_esp32c6.menu.FlashSize.4M=4MB (32Mb) +dfrobot_firebeetle2_esp32c6.menu.FlashSize.4M.build.flash_size=4MB + +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.921600=921600 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.115200=115200 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.256000.windows=256000 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400=230400 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.linux=460800 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.macosx=460800 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.512000.windows=512000 +dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.none=None +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.none.build.code_debug=0 +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.error=Error +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.error.build.code_debug=1 +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.warn=Warn +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.info=Info +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.info.build.code_debug=3 +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.debug=Debug +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.verbose=Verbose +dfrobot_firebeetle2_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_firebeetle2_esp32c6.menu.EraseFlash.none=Disabled +dfrobot_firebeetle2_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_firebeetle2_esp32c6.menu.EraseFlash.all=Enabled +dfrobot_firebeetle2_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default=Disabled +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +############################################################## + +# dfrobot Romeo ESP32-S3 +dfrobot_romeo_esp32s3.name=DFRobot Romeo ESP32-S3 + +dfrobot_romeo_esp32s3.bootloader.tool=esptool_py +dfrobot_romeo_esp32s3.bootloader.tool.default=esptool_py + +dfrobot_romeo_esp32s3.upload.tool=esptool_py +dfrobot_romeo_esp32s3.upload.tool.default=esptool_py +dfrobot_romeo_esp32s3.upload.tool.network=esp_ota + +dfrobot_romeo_esp32s3.upload.maximum_size=1310720 +dfrobot_romeo_esp32s3.upload.maximum_data_size=327680 +dfrobot_romeo_esp32s3.upload.flags= +dfrobot_romeo_esp32s3.upload.extra_flags= +dfrobot_romeo_esp32s3.upload.use_1200bps_touch=false +dfrobot_romeo_esp32s3.upload.wait_for_upload_port=false + +dfrobot_romeo_esp32s3.serial.disableDTR=false +dfrobot_romeo_esp32s3.serial.disableRTS=false + +dfrobot_romeo_esp32s3.build.tarch=xtensa +dfrobot_romeo_esp32s3.build.bootloader_addr=0x0 +dfrobot_romeo_esp32s3.build.target=esp32s3 +dfrobot_romeo_esp32s3.build.mcu=esp32s3 +dfrobot_romeo_esp32s3.build.core=esp32 +dfrobot_romeo_esp32s3.build.variant=dfrobot_romeo_esp32s3 +dfrobot_romeo_esp32s3.build.board=DFROBOT_ROMEO_ESP32S3 + + +dfrobot_romeo_esp32s3.build.usb_mode=1 +dfrobot_romeo_esp32s3.build.cdc_on_boot=0 +dfrobot_romeo_esp32s3.build.msc_on_boot=0 +dfrobot_romeo_esp32s3.build.dfu_on_boot=0 +dfrobot_romeo_esp32s3.build.f_cpu=240000000L +dfrobot_romeo_esp32s3.build.flash_size=16MB +dfrobot_romeo_esp32s3.build.flash_freq=80m +dfrobot_romeo_esp32s3.build.flash_mode=qio +dfrobot_romeo_esp32s3.build.boot=qio +dfrobot_romeo_esp32s3.build.boot_freq=80m +dfrobot_romeo_esp32s3.build.partitions=default +dfrobot_romeo_esp32s3.build.defines= +dfrobot_romeo_esp32s3.build.loop_core= +dfrobot_romeo_esp32s3.build.event_core= +dfrobot_romeo_esp32s3.build.flash_type=qio +dfrobot_romeo_esp32s3.build.psram_type=qspi +dfrobot_romeo_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +dfrobot_romeo_esp32s3.menu.PSRAM.opi=OPI PSRAM +dfrobot_romeo_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +dfrobot_romeo_esp32s3.menu.PSRAM.opi.build.psram_type=opi +dfrobot_romeo_esp32s3.menu.PSRAM.disabled=Disabled +dfrobot_romeo_esp32s3.menu.PSRAM.disabled.build.defines= +dfrobot_romeo_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +dfrobot_romeo_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +dfrobot_romeo_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +dfrobot_romeo_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi + + +dfrobot_romeo_esp32s3.menu.FlashMode.qio=QIO 80MHz +dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.boot=qio +dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_type=qio +dfrobot_romeo_esp32s3.menu.FlashMode.qio120=QIO 120MHz +dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.boot=qio +dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_type=qio +dfrobot_romeo_esp32s3.menu.FlashMode.dio=DIO 80MHz +dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.boot=dio +dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_type=qio +dfrobot_romeo_esp32s3.menu.FlashMode.opi=OPI 80MHz +dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.boot=opi +dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_freq=80m +dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_type=opi + +dfrobot_romeo_esp32s3.menu.FlashSize.16M=16MB (128Mb) +dfrobot_romeo_esp32s3.menu.FlashSize.16M.build.flash_size=16MB + + +dfrobot_romeo_esp32s3.menu.LoopCore.1=Core 1 +dfrobot_romeo_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +dfrobot_romeo_esp32s3.menu.LoopCore.0=Core 0 +dfrobot_romeo_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +dfrobot_romeo_esp32s3.menu.EventsCore.1=Core 1 +dfrobot_romeo_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +dfrobot_romeo_esp32s3.menu.EventsCore.0=Core 0 +dfrobot_romeo_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +dfrobot_romeo_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +dfrobot_romeo_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +dfrobot_romeo_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +dfrobot_romeo_esp32s3.menu.USBMode.default.build.usb_mode=0 + +dfrobot_romeo_esp32s3.menu.CDCOnBoot.cdc=Enabled +dfrobot_romeo_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +dfrobot_romeo_esp32s3.menu.CDCOnBoot.default=Disabled +dfrobot_romeo_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + + +dfrobot_romeo_esp32s3.menu.MSCOnBoot.default=Disabled +dfrobot_romeo_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +dfrobot_romeo_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +dfrobot_romeo_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +dfrobot_romeo_esp32s3.menu.DFUOnBoot.default=Disabled +dfrobot_romeo_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +dfrobot_romeo_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +dfrobot_romeo_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +dfrobot_romeo_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +dfrobot_romeo_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +dfrobot_romeo_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +dfrobot_romeo_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +dfrobot_romeo_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +dfrobot_romeo_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +dfrobot_romeo_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_romeo_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +dfrobot_romeo_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +dfrobot_romeo_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +dfrobot_romeo_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_romeo_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_romeo_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_romeo_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_romeo_esp32s3.menu.CPUFreq.40=40MHz +dfrobot_romeo_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_romeo_esp32s3.menu.CPUFreq.20=20MHz +dfrobot_romeo_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_romeo_esp32s3.menu.CPUFreq.10=10MHz +dfrobot_romeo_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_romeo_esp32s3.menu.UploadSpeed.921600=921600 +dfrobot_romeo_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_romeo_esp32s3.menu.UploadSpeed.115200=115200 +dfrobot_romeo_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_romeo_esp32s3.menu.UploadSpeed.256000.windows=256000 +dfrobot_romeo_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_romeo_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_romeo_esp32s3.menu.UploadSpeed.230400=230400 +dfrobot_romeo_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.linux=460800 +dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.macosx=460800 +dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_romeo_esp32s3.menu.UploadSpeed.512000.windows=512000 +dfrobot_romeo_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_romeo_esp32s3.menu.DebugLevel.none=None +dfrobot_romeo_esp32s3.menu.DebugLevel.none.build.code_debug=0 +dfrobot_romeo_esp32s3.menu.DebugLevel.error=Error +dfrobot_romeo_esp32s3.menu.DebugLevel.error.build.code_debug=1 +dfrobot_romeo_esp32s3.menu.DebugLevel.warn=Warn +dfrobot_romeo_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_romeo_esp32s3.menu.DebugLevel.info=Info +dfrobot_romeo_esp32s3.menu.DebugLevel.info.build.code_debug=3 +dfrobot_romeo_esp32s3.menu.DebugLevel.debug=Debug +dfrobot_romeo_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_romeo_esp32s3.menu.DebugLevel.verbose=Verbose +dfrobot_romeo_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_romeo_esp32s3.menu.EraseFlash.none=Disabled +dfrobot_romeo_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_romeo_esp32s3.menu.EraseFlash.all=Enabled +dfrobot_romeo_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +dfrobot_lorawan_esp32s3.name=DFRobot LoRaWAN ESP32-S3 +#dfrobot_lorawan_esp32s3.vid.0=0x303a +#dfrobot_lorawan_esp32s3.pid.0=0x1001 + +dfrobot_lorawan_esp32s3.bootloader.tool=esptool_py +dfrobot_lorawan_esp32s3.bootloader.tool.default=esptool_py + +dfrobot_lorawan_esp32s3.upload.tool=esptool_py +dfrobot_lorawan_esp32s3.upload.tool.default=esptool_py +dfrobot_lorawan_esp32s3.upload.tool.network=esp_ota + +dfrobot_lorawan_esp32s3.upload.speed=921600 +dfrobot_lorawan_esp32s3.upload.erase_cmd= +dfrobot_lorawan_esp32s3.upload.maximum_size=1310720 +dfrobot_lorawan_esp32s3.upload.maximum_data_size=327680 +dfrobot_lorawan_esp32s3.upload.flags= +dfrobot_lorawan_esp32s3.upload.extra_flags= +dfrobot_lorawan_esp32s3.upload.use_1200bps_touch=false +dfrobot_lorawan_esp32s3.upload.wait_for_upload_port=false + +dfrobot_lorawan_esp32s3.serial.disableDTR=false +dfrobot_lorawan_esp32s3.serial.disableRTS=false + +dfrobot_lorawan_esp32s3.build.tarch=xtensa +dfrobot_lorawan_esp32s3.build.bootloader_addr=0x0 +dfrobot_lorawan_esp32s3.build.target=esp32s3 +dfrobot_lorawan_esp32s3.build.mcu=esp32s3 +dfrobot_lorawan_esp32s3.build.core=esp32 +dfrobot_lorawan_esp32s3.build.variant=dfrobot_lorawan_esp32s3 +dfrobot_lorawan_esp32s3.build.board=DFROBOT_LORAWAN_ESP32S3 +dfrobot_lorawan_esp32s3.build.usb_mode=1 +dfrobot_lorawan_esp32s3.build.cdc_on_boot=1 +dfrobot_lorawan_esp32s3.build.msc_on_boot=0 +dfrobot_lorawan_esp32s3.build.dfu_on_boot=0 +dfrobot_lorawan_esp32s3.build.f_cpu=240000000L +dfrobot_lorawan_esp32s3.build.flash_size=4MB +dfrobot_lorawan_esp32s3.build.flash_freq=80m +dfrobot_lorawan_esp32s3.build.flash_mode=dio +dfrobot_lorawan_esp32s3.build.boot=qio +dfrobot_lorawan_esp32s3.build.boot_freq=80m +dfrobot_lorawan_esp32s3.build.partitions=default +dfrobot_lorawan_esp32s3.build.defines=-D{build.band} +dfrobot_lorawan_esp32s3.build.loop_core= +dfrobot_lorawan_esp32s3.build.event_core= +dfrobot_lorawan_esp32s3.build.psram_type=qspi +dfrobot_lorawan_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} +dfrobot_lorawan_esp32s3.build.region= + +dfrobot_lorawan_esp32s3.menu.FlashMode.qio=QIO 80MHz +dfrobot_lorawan_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +dfrobot_lorawan_esp32s3.menu.FlashMode.qio.build.boot=qio +dfrobot_lorawan_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +dfrobot_lorawan_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +dfrobot_lorawan_esp32s3.menu.FlashMode.qio.build.flash_type=qio +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120=QIO 120MHz +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120.build.boot=qio +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +dfrobot_lorawan_esp32s3.menu.FlashMode.qio120.build.flash_type=qio +dfrobot_lorawan_esp32s3.menu.FlashMode.dio=DIO 80MHz +dfrobot_lorawan_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +dfrobot_lorawan_esp32s3.menu.FlashMode.dio.build.boot=dio +dfrobot_lorawan_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +dfrobot_lorawan_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +dfrobot_lorawan_esp32s3.menu.FlashMode.dio.build.flash_type=qio + +dfrobot_lorawan_esp32s3.menu.FlashSize.4M=4MB (32Mb) +dfrobot_lorawan_esp32s3.menu.FlashSize.4M.build.flash_size=4MB + +dfrobot_lorawan_esp32s3.menu.LoopCore.1=Core 1 +dfrobot_lorawan_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +dfrobot_lorawan_esp32s3.menu.LoopCore.0=Core 0 +dfrobot_lorawan_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +dfrobot_lorawan_esp32s3.menu.EventsCore.1=Core 1 +dfrobot_lorawan_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +dfrobot_lorawan_esp32s3.menu.EventsCore.0=Core 0 +dfrobot_lorawan_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +dfrobot_lorawan_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +dfrobot_lorawan_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +dfrobot_lorawan_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +dfrobot_lorawan_esp32s3.menu.USBMode.default.build.usb_mode=0 + +dfrobot_lorawan_esp32s3.menu.CDCOnBoot.default=Disabled +dfrobot_lorawan_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +dfrobot_lorawan_esp32s3.menu.CDCOnBoot.cdc=Enabled +dfrobot_lorawan_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +dfrobot_lorawan_esp32s3.menu.MSCOnBoot.default=Disabled +dfrobot_lorawan_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +dfrobot_lorawan_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +dfrobot_lorawan_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +dfrobot_lorawan_esp32s3.menu.DFUOnBoot.default=Disabled +dfrobot_lorawan_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +dfrobot_lorawan_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +dfrobot_lorawan_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +dfrobot_lorawan_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +dfrobot_lorawan_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +dfrobot_lorawan_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +dfrobot_lorawan_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +dfrobot_lorawan_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +dfrobot_lorawan_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +dfrobot_lorawan_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.default.build.partitions=default +dfrobot_lorawan_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dfrobot_lorawan_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +dfrobot_lorawan_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +dfrobot_lorawan_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dfrobot_lorawan_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +dfrobot_lorawan_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dfrobot_lorawan_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dfrobot_lorawan_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +dfrobot_lorawan_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + + +dfrobot_lorawan_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +dfrobot_lorawan_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +dfrobot_lorawan_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +dfrobot_lorawan_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +dfrobot_lorawan_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +dfrobot_lorawan_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +dfrobot_lorawan_esp32s3.menu.CPUFreq.40=40MHz +dfrobot_lorawan_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +dfrobot_lorawan_esp32s3.menu.CPUFreq.20=20MHz +dfrobot_lorawan_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +dfrobot_lorawan_esp32s3.menu.CPUFreq.10=10MHz +dfrobot_lorawan_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +dfrobot_lorawan_esp32s3.menu.UploadSpeed.921600=921600 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.115200=115200 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.256000.windows=256000 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.230400=230400 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.460800.linux=460800 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.460800.macosx=460800 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.512000.windows=512000 +dfrobot_lorawan_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +dfrobot_lorawan_esp32s3.menu.DebugLevel.none=None +dfrobot_lorawan_esp32s3.menu.DebugLevel.none.build.code_debug=0 +dfrobot_lorawan_esp32s3.menu.DebugLevel.error=Error +dfrobot_lorawan_esp32s3.menu.DebugLevel.error.build.code_debug=1 +dfrobot_lorawan_esp32s3.menu.DebugLevel.warn=Warn +dfrobot_lorawan_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +dfrobot_lorawan_esp32s3.menu.DebugLevel.info=Info +dfrobot_lorawan_esp32s3.menu.DebugLevel.info.build.code_debug=3 +dfrobot_lorawan_esp32s3.menu.DebugLevel.debug=Debug +dfrobot_lorawan_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +dfrobot_lorawan_esp32s3.menu.DebugLevel.verbose=Verbose +dfrobot_lorawan_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +dfrobot_lorawan_esp32s3.menu.EraseFlash.none=Disabled +dfrobot_lorawan_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +dfrobot_lorawan_esp32s3.menu.EraseFlash.all=Enabled +dfrobot_lorawan_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.0=REGION_EU868 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.1=REGION_EU433 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.2=REGION_CN470 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.3=REGION_US915 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.4=REGION_AU915 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.5=REGION_CN779 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.6=REGION_AS923 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.7=REGION_KR920 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.8=REGION_IN865 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +dfrobot_lorawan_esp32s3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +############################################################## + +firebeetle32.name=FireBeetle-ESP32 + +firebeetle32.bootloader.tool=esptool_py +firebeetle32.bootloader.tool.default=esptool_py + +firebeetle32.upload.tool=esptool_py +firebeetle32.upload.tool.default=esptool_py +firebeetle32.upload.tool.network=esp_ota + +firebeetle32.upload.maximum_size=1310720 +firebeetle32.upload.maximum_data_size=327680 +firebeetle32.upload.flags= +firebeetle32.upload.extra_flags= + +firebeetle32.serial.disableDTR=true +firebeetle32.serial.disableRTS=true + +firebeetle32.build.tarch=xtensa +firebeetle32.build.bootloader_addr=0x1000 +firebeetle32.build.target=esp32 +firebeetle32.build.mcu=esp32 +firebeetle32.build.core=esp32 +firebeetle32.build.variant=firebeetle32 +firebeetle32.build.board=DFROBOT_FIREBEETLE_ESP32 + +firebeetle32.build.f_cpu=240000000L +firebeetle32.build.flash_mode=dio +firebeetle32.build.flash_size=4MB +firebeetle32.build.boot=dio +firebeetle32.build.partitions=default +firebeetle32.build.defines= + +firebeetle32.menu.FlashFreq.80=80MHz +firebeetle32.menu.FlashFreq.80.build.flash_freq=80m +firebeetle32.menu.FlashFreq.40=40MHz +firebeetle32.menu.FlashFreq.40.build.flash_freq=40m + +firebeetle32.menu.UploadSpeed.921600=921600 +firebeetle32.menu.UploadSpeed.921600.upload.speed=921600 +firebeetle32.menu.UploadSpeed.115200=115200 +firebeetle32.menu.UploadSpeed.115200.upload.speed=115200 +firebeetle32.menu.UploadSpeed.256000.windows=256000 +firebeetle32.menu.UploadSpeed.256000.upload.speed=256000 +firebeetle32.menu.UploadSpeed.230400.windows.upload.speed=256000 +firebeetle32.menu.UploadSpeed.230400=230400 +firebeetle32.menu.UploadSpeed.230400.upload.speed=230400 +firebeetle32.menu.UploadSpeed.460800.linux=460800 +firebeetle32.menu.UploadSpeed.460800.macosx=460800 +firebeetle32.menu.UploadSpeed.460800.upload.speed=460800 +firebeetle32.menu.UploadSpeed.512000.windows=512000 +firebeetle32.menu.UploadSpeed.512000.upload.speed=512000 + +firebeetle32.menu.DebugLevel.none=None +firebeetle32.menu.DebugLevel.none.build.code_debug=0 +firebeetle32.menu.DebugLevel.error=Error +firebeetle32.menu.DebugLevel.error.build.code_debug=1 +firebeetle32.menu.DebugLevel.warn=Warn +firebeetle32.menu.DebugLevel.warn.build.code_debug=2 +firebeetle32.menu.DebugLevel.info=Info +firebeetle32.menu.DebugLevel.info.build.code_debug=3 +firebeetle32.menu.DebugLevel.debug=Debug +firebeetle32.menu.DebugLevel.debug.build.code_debug=4 +firebeetle32.menu.DebugLevel.verbose=Verbose +firebeetle32.menu.DebugLevel.verbose.build.code_debug=5 + +firebeetle32.menu.EraseFlash.none=Disabled +firebeetle32.menu.EraseFlash.none.upload.erase_cmd= +firebeetle32.menu.EraseFlash.all=Enabled +firebeetle32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +intorobot-fig.name=IntoRobot Fig + +intorobot-fig.bootloader.tool=esptool_py +intorobot-fig.bootloader.tool.default=esptool_py + +intorobot-fig.upload.tool=esptool_py +intorobot-fig.upload.tool.default=esptool_py +intorobot-fig.upload.tool.network=esp_ota + +intorobot-fig.upload.maximum_size=1310720 +intorobot-fig.upload.maximum_data_size=327680 +intorobot-fig.upload.flags= +intorobot-fig.upload.extra_flags= + +intorobot-fig.serial.disableDTR=true +intorobot-fig.serial.disableRTS=true + +intorobot-fig.build.tarch=xtensa +intorobot-fig.build.bootloader_addr=0x1000 +intorobot-fig.build.target=esp32 +intorobot-fig.build.mcu=esp32 +intorobot-fig.build.core=esp32 +intorobot-fig.build.variant=intorobot-fig +intorobot-fig.build.board=INTOROBOT_ESP32_DEV + +intorobot-fig.build.f_cpu=240000000L +intorobot-fig.build.flash_mode=dio +intorobot-fig.build.flash_size=4MB +intorobot-fig.build.boot=dio +intorobot-fig.build.partitions=default +intorobot-fig.build.defines= + +intorobot-fig.menu.FlashFreq.80=80MHz +intorobot-fig.menu.FlashFreq.80.build.flash_freq=80m +intorobot-fig.menu.FlashFreq.40=40MHz +intorobot-fig.menu.FlashFreq.40.build.flash_freq=40m + +intorobot-fig.menu.UploadSpeed.921600=921600 +intorobot-fig.menu.UploadSpeed.921600.upload.speed=921600 +intorobot-fig.menu.UploadSpeed.115200=115200 +intorobot-fig.menu.UploadSpeed.115200.upload.speed=115200 +intorobot-fig.menu.UploadSpeed.256000.windows=256000 +intorobot-fig.menu.UploadSpeed.256000.upload.speed=256000 +intorobot-fig.menu.UploadSpeed.230400.windows.upload.speed=256000 +intorobot-fig.menu.UploadSpeed.230400=230400 +intorobot-fig.menu.UploadSpeed.230400.upload.speed=230400 +intorobot-fig.menu.UploadSpeed.460800.linux=460800 +intorobot-fig.menu.UploadSpeed.460800.macosx=460800 +intorobot-fig.menu.UploadSpeed.460800.upload.speed=460800 +intorobot-fig.menu.UploadSpeed.512000.windows=512000 +intorobot-fig.menu.UploadSpeed.512000.upload.speed=512000 + +intorobot-fig.menu.DebugLevel.none=None +intorobot-fig.menu.DebugLevel.none.build.code_debug=0 +intorobot-fig.menu.DebugLevel.error=Error +intorobot-fig.menu.DebugLevel.error.build.code_debug=1 +intorobot-fig.menu.DebugLevel.warn=Warn +intorobot-fig.menu.DebugLevel.warn.build.code_debug=2 +intorobot-fig.menu.DebugLevel.info=Info +intorobot-fig.menu.DebugLevel.info.build.code_debug=3 +intorobot-fig.menu.DebugLevel.debug=Debug +intorobot-fig.menu.DebugLevel.debug.build.code_debug=4 +intorobot-fig.menu.DebugLevel.verbose=Verbose +intorobot-fig.menu.DebugLevel.verbose.build.code_debug=5 + +intorobot-fig.menu.EraseFlash.none=Disabled +intorobot-fig.menu.EraseFlash.none.upload.erase_cmd= +intorobot-fig.menu.EraseFlash.all=Enabled +intorobot-fig.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +onehorse32dev.name=Onehorse ESP32 Dev Module + +onehorse32dev.bootloader.tool=esptool_py +onehorse32dev.bootloader.tool.default=esptool_py + +onehorse32dev.upload.tool=esptool_py +onehorse32dev.upload.tool.default=esptool_py +onehorse32dev.upload.tool.network=esp_ota + +onehorse32dev.upload.maximum_size=1310720 +onehorse32dev.upload.maximum_data_size=327680 +onehorse32dev.upload.flags= +onehorse32dev.upload.extra_flags= + +onehorse32dev.serial.disableDTR=true +onehorse32dev.serial.disableRTS=true + +onehorse32dev.build.tarch=xtensa +onehorse32dev.build.bootloader_addr=0x1000 +onehorse32dev.build.target=esp32 +onehorse32dev.build.mcu=esp32 +onehorse32dev.build.core=esp32 +onehorse32dev.build.variant=onehorse32dev +onehorse32dev.build.board=ONEHORSE_ESP32_DEV + +onehorse32dev.build.f_cpu=240000000L +onehorse32dev.build.flash_mode=dout +onehorse32dev.build.flash_size=4MB +onehorse32dev.build.boot=dio +onehorse32dev.build.partitions=default +onehorse32dev.build.defines= + +onehorse32dev.menu.FlashFreq.80=80MHz +onehorse32dev.menu.FlashFreq.80.build.flash_freq=80m +onehorse32dev.menu.FlashFreq.40=40MHz +onehorse32dev.menu.FlashFreq.40.build.flash_freq=40m + +onehorse32dev.menu.UploadSpeed.921600=921600 +onehorse32dev.menu.UploadSpeed.921600.upload.speed=921600 +onehorse32dev.menu.UploadSpeed.115200=115200 +onehorse32dev.menu.UploadSpeed.115200.upload.speed=115200 +onehorse32dev.menu.UploadSpeed.256000.windows=256000 +onehorse32dev.menu.UploadSpeed.256000.upload.speed=256000 +onehorse32dev.menu.UploadSpeed.230400.windows.upload.speed=256000 +onehorse32dev.menu.UploadSpeed.230400=230400 +onehorse32dev.menu.UploadSpeed.230400.upload.speed=230400 +onehorse32dev.menu.UploadSpeed.460800.linux=460800 +onehorse32dev.menu.UploadSpeed.460800.macosx=460800 +onehorse32dev.menu.UploadSpeed.460800.upload.speed=460800 +onehorse32dev.menu.UploadSpeed.512000.windows=512000 +onehorse32dev.menu.UploadSpeed.512000.upload.speed=512000 + +onehorse32dev.menu.DebugLevel.none=None +onehorse32dev.menu.DebugLevel.none.build.code_debug=0 +onehorse32dev.menu.DebugLevel.error=Error +onehorse32dev.menu.DebugLevel.error.build.code_debug=1 +onehorse32dev.menu.DebugLevel.warn=Warn +onehorse32dev.menu.DebugLevel.warn.build.code_debug=2 +onehorse32dev.menu.DebugLevel.info=Info +onehorse32dev.menu.DebugLevel.info.build.code_debug=3 +onehorse32dev.menu.DebugLevel.debug=Debug +onehorse32dev.menu.DebugLevel.debug.build.code_debug=4 +onehorse32dev.menu.DebugLevel.verbose=Verbose +onehorse32dev.menu.DebugLevel.verbose.build.code_debug=5 + +onehorse32dev.menu.EraseFlash.none=Disabled +onehorse32dev.menu.EraseFlash.none.upload.erase_cmd= +onehorse32dev.menu.EraseFlash.all=Enabled +onehorse32dev.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Adafruit Metro ESP32-S2 + +adafruit_metro_esp32s2.name=Adafruit Metro ESP32-S2 +adafruit_metro_esp32s2.vid.0=0x239A +adafruit_metro_esp32s2.pid.0=0x80DF +adafruit_metro_esp32s2.vid.1=0x239A +adafruit_metro_esp32s2.pid.1=0x00DF +adafruit_metro_esp32s2.vid.2=0x239A +adafruit_metro_esp32s2.pid.2=0x80E0 +adafruit_metro_esp32s2.upload_port.0.vid=0x239A +adafruit_metro_esp32s2.upload_port.0.pid=0x80DF +adafruit_metro_esp32s2.upload_port.1.vid=0x239A +adafruit_metro_esp32s2.upload_port.1.pid=0x00DF +adafruit_metro_esp32s2.upload_port.2.vid=0x239A +adafruit_metro_esp32s2.upload_port.2.pid=0x80E0 + +adafruit_metro_esp32s2.bootloader.tool=esptool_py +adafruit_metro_esp32s2.bootloader.tool.default=esptool_py + +adafruit_metro_esp32s2.upload.tool=esptool_py +adafruit_metro_esp32s2.upload.tool.default=esptool_py +adafruit_metro_esp32s2.upload.tool.network=esp_ota + +adafruit_metro_esp32s2.upload.maximum_size=1310720 +adafruit_metro_esp32s2.upload.maximum_data_size=327680 +adafruit_metro_esp32s2.upload.flags= +adafruit_metro_esp32s2.upload.extra_flags= +adafruit_metro_esp32s2.upload.use_1200bps_touch=true +adafruit_metro_esp32s2.upload.wait_for_upload_port=true + +adafruit_metro_esp32s2.serial.disableDTR=false +adafruit_metro_esp32s2.serial.disableRTS=false + +adafruit_metro_esp32s2.build.tarch=xtensa +adafruit_metro_esp32s2.build.bootloader_addr=0x1000 +adafruit_metro_esp32s2.build.target=esp32s2 +adafruit_metro_esp32s2.build.mcu=esp32s2 +adafruit_metro_esp32s2.build.core=esp32 +adafruit_metro_esp32s2.build.variant=adafruit_metro_esp32s2 +adafruit_metro_esp32s2.build.board=METRO_ESP32S2 + +adafruit_metro_esp32s2.build.cdc_on_boot=1 +adafruit_metro_esp32s2.build.msc_on_boot=0 +adafruit_metro_esp32s2.build.dfu_on_boot=0 +adafruit_metro_esp32s2.build.f_cpu=240000000L +adafruit_metro_esp32s2.build.flash_size=4MB +adafruit_metro_esp32s2.build.flash_freq=80m +adafruit_metro_esp32s2.build.flash_mode=dio +adafruit_metro_esp32s2.build.boot=qio +adafruit_metro_esp32s2.build.partitions=default +adafruit_metro_esp32s2.build.defines= + +adafruit_metro_esp32s2.menu.CDCOnBoot.cdc=Enabled +adafruit_metro_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_metro_esp32s2.menu.CDCOnBoot.default=Disabled +adafruit_metro_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_metro_esp32s2.menu.MSCOnBoot.default=Disabled +adafruit_metro_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_metro_esp32s2.menu.MSCOnBoot.msc=Enabled +adafruit_metro_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_metro_esp32s2.menu.DFUOnBoot.default=Disabled +adafruit_metro_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_metro_esp32s2.menu.DFUOnBoot.dfu=Enabled +adafruit_metro_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_metro_esp32s2.menu.UploadMode.cdc=Internal USB +adafruit_metro_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_metro_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_metro_esp32s2.menu.UploadMode.default=UART0 +adafruit_metro_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_metro_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_metro_esp32s2.menu.PSRAM.enabled=Enabled +adafruit_metro_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_metro_esp32s2.menu.PSRAM.disabled=Disabled +adafruit_metro_esp32s2.menu.PSRAM.disabled.build.defines= + +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_metro_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.default.build.partitions=default +adafruit_metro_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_metro_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_metro_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_metro_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_metro_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_metro_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_metro_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_metro_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_metro_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_metro_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_metro_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_metro_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_metro_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_metro_esp32s2.menu.CPUFreq.40=40MHz +adafruit_metro_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_metro_esp32s2.menu.CPUFreq.20=20MHz +adafruit_metro_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_metro_esp32s2.menu.CPUFreq.10=10MHz +adafruit_metro_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_metro_esp32s2.menu.FlashMode.qio=QIO +adafruit_metro_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_metro_esp32s2.menu.FlashMode.qio.build.boot=qio +adafruit_metro_esp32s2.menu.FlashMode.dio=DIO +adafruit_metro_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_metro_esp32s2.menu.FlashMode.dio.build.boot=dio + +adafruit_metro_esp32s2.menu.FlashFreq.80=80MHz +adafruit_metro_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_metro_esp32s2.menu.FlashFreq.40=40MHz +adafruit_metro_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_metro_esp32s2.menu.FlashSize.4M=4MB (32Mb) +adafruit_metro_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_metro_esp32s2.menu.UploadSpeed.921600=921600 +adafruit_metro_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_metro_esp32s2.menu.UploadSpeed.115200=115200 +adafruit_metro_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_metro_esp32s2.menu.UploadSpeed.256000.windows=256000 +adafruit_metro_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_metro_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_metro_esp32s2.menu.UploadSpeed.230400=230400 +adafruit_metro_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_metro_esp32s2.menu.UploadSpeed.460800.linux=460800 +adafruit_metro_esp32s2.menu.UploadSpeed.460800.macosx=460800 +adafruit_metro_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_metro_esp32s2.menu.UploadSpeed.512000.windows=512000 +adafruit_metro_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_metro_esp32s2.menu.DebugLevel.none=None +adafruit_metro_esp32s2.menu.DebugLevel.none.build.code_debug=0 +adafruit_metro_esp32s2.menu.DebugLevel.error=Error +adafruit_metro_esp32s2.menu.DebugLevel.error.build.code_debug=1 +adafruit_metro_esp32s2.menu.DebugLevel.warn=Warn +adafruit_metro_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_metro_esp32s2.menu.DebugLevel.info=Info +adafruit_metro_esp32s2.menu.DebugLevel.info.build.code_debug=3 +adafruit_metro_esp32s2.menu.DebugLevel.debug=Debug +adafruit_metro_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_metro_esp32s2.menu.DebugLevel.verbose=Verbose +adafruit_metro_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_metro_esp32s2.menu.EraseFlash.none=Disabled +adafruit_metro_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_metro_esp32s2.menu.EraseFlash.all=Enabled +adafruit_metro_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_metro_esp32s2.menu.ZigbeeMode.default=Disabled +adafruit_metro_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_metro_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_metro_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_metro_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_metro_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Metro ESP32-S3 + +adafruit_metro_esp32s3.name=Adafruit Metro ESP32-S3 +adafruit_metro_esp32s3.vid.0=0x239A +adafruit_metro_esp32s3.pid.0=0x8145 +adafruit_metro_esp32s3.vid.1=0x239A +adafruit_metro_esp32s3.pid.1=0x0145 +adafruit_metro_esp32s3.vid.2=0x239A +adafruit_metro_esp32s3.pid.2=0x8146 +adafruit_metro_esp32s3.upload_port.0.vid=0x239A +adafruit_metro_esp32s3.upload_port.0.pid=0x8145 +adafruit_metro_esp32s3.upload_port.1.vid=0x239A +adafruit_metro_esp32s3.upload_port.1.pid=0x0145 +adafruit_metro_esp32s3.upload_port.2.vid=0x239A +adafruit_metro_esp32s3.upload_port.2.pid=0x8146 + +adafruit_metro_esp32s3.bootloader.tool=esptool_py +adafruit_metro_esp32s3.bootloader.tool.default=esptool_py + +adafruit_metro_esp32s3.upload.tool=esptool_py +adafruit_metro_esp32s3.upload.tool.default=esptool_py +adafruit_metro_esp32s3.upload.tool.network=esp_ota + +adafruit_metro_esp32s3.upload.maximum_size=1310720 +adafruit_metro_esp32s3.upload.maximum_data_size=327680 +adafruit_metro_esp32s3.upload.flags= +adafruit_metro_esp32s3.upload.extra_flags= +adafruit_metro_esp32s3.upload.use_1200bps_touch=true +adafruit_metro_esp32s3.upload.wait_for_upload_port=true + +adafruit_metro_esp32s3.serial.disableDTR=false +adafruit_metro_esp32s3.serial.disableRTS=false + +adafruit_metro_esp32s3.build.tarch=xtensa +adafruit_metro_esp32s3.build.bootloader_addr=0x0 +adafruit_metro_esp32s3.build.target=esp32s3 +adafruit_metro_esp32s3.build.mcu=esp32s3 +adafruit_metro_esp32s3.build.core=esp32 +adafruit_metro_esp32s3.build.variant=adafruit_metro_esp32s3 +adafruit_metro_esp32s3.build.board=METRO_ESP32S3 + +adafruit_metro_esp32s3.build.usb_mode=0 +adafruit_metro_esp32s3.build.cdc_on_boot=1 +adafruit_metro_esp32s3.build.msc_on_boot=0 +adafruit_metro_esp32s3.build.dfu_on_boot=0 +adafruit_metro_esp32s3.build.f_cpu=240000000L +adafruit_metro_esp32s3.build.flash_size=16MB +adafruit_metro_esp32s3.build.flash_freq=80m +adafruit_metro_esp32s3.build.flash_mode=dio +adafruit_metro_esp32s3.build.boot=qio +adafruit_metro_esp32s3.build.partitions=default +adafruit_metro_esp32s3.build.defines= +adafruit_metro_esp32s3.build.loop_core= +adafruit_metro_esp32s3.build.event_core= +adafruit_metro_esp32s3.build.flash_type=qio +adafruit_metro_esp32s3.build.psram_type=opi +adafruit_metro_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_metro_esp32s3.menu.LoopCore.1=Core 1 +adafruit_metro_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_metro_esp32s3.menu.LoopCore.0=Core 0 +adafruit_metro_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_metro_esp32s3.menu.EventsCore.1=Core 1 +adafruit_metro_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_metro_esp32s3.menu.EventsCore.0=Core 0 +adafruit_metro_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_metro_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_metro_esp32s3.menu.USBMode.default.build.usb_mode=0 +adafruit_metro_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_metro_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_metro_esp32s3.menu.CDCOnBoot.cdc=Enabled +adafruit_metro_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_metro_esp32s3.menu.CDCOnBoot.default=Disabled +adafruit_metro_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_metro_esp32s3.menu.MSCOnBoot.default=Disabled +adafruit_metro_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_metro_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_metro_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_metro_esp32s3.menu.DFUOnBoot.default=Disabled +adafruit_metro_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_metro_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_metro_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_metro_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_metro_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_metro_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_metro_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_metro_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_metro_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_metro_esp32s3.menu.PSRAM.opi=OPI PSRAM +adafruit_metro_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_metro_esp32s3.menu.PSRAM.opi.build.psram_type=opi +adafruit_metro_esp32s3.menu.PSRAM.disabled=Disabled +adafruit_metro_esp32s3.menu.PSRAM.disabled.build.defines= +adafruit_metro_esp32s3.menu.PSRAM.disabled.build.psram_type=opi + +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FATFS) +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-16MB +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 16MB No OTA(4MB APP/11.6MB FATFS) +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-16MB-noota +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +adafruit_metro_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +adafruit_metro_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +adafruit_metro_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +adafruit_metro_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +adafruit_metro_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_metro_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +adafruit_metro_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_metro_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +adafruit_metro_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_metro_esp32s3.menu.CPUFreq.40=40MHz +adafruit_metro_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_metro_esp32s3.menu.CPUFreq.20=20MHz +adafruit_metro_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_metro_esp32s3.menu.CPUFreq.10=10MHz +adafruit_metro_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_metro_esp32s3.menu.FlashMode.qio=QIO 80MHz +adafruit_metro_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +adafruit_metro_esp32s3.menu.FlashMode.qio.build.boot=qio +adafruit_metro_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.qio120=QIO 120MHz +adafruit_metro_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_metro_esp32s3.menu.FlashMode.qio120.build.boot=qio +adafruit_metro_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_metro_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.dio=DIO 80MHz +adafruit_metro_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +adafruit_metro_esp32s3.menu.FlashMode.dio.build.boot=dio +adafruit_metro_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.opi=OPI 80MHz +adafruit_metro_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +adafruit_metro_esp32s3.menu.FlashMode.opi.build.boot=opi +adafruit_metro_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +adafruit_metro_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_metro_esp32s3.menu.FlashSize.16M=16MB (128Mb) +adafruit_metro_esp32s3.menu.FlashSize.16M.build.flash_size=16MB + +adafruit_metro_esp32s3.menu.UploadSpeed.921600=921600 +adafruit_metro_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_metro_esp32s3.menu.UploadSpeed.115200=115200 +adafruit_metro_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_metro_esp32s3.menu.UploadSpeed.256000.windows=256000 +adafruit_metro_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_metro_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_metro_esp32s3.menu.UploadSpeed.230400=230400 +adafruit_metro_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_metro_esp32s3.menu.UploadSpeed.460800.linux=460800 +adafruit_metro_esp32s3.menu.UploadSpeed.460800.macosx=460800 +adafruit_metro_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_metro_esp32s3.menu.UploadSpeed.512000.windows=512000 +adafruit_metro_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_metro_esp32s3.menu.DebugLevel.none=None +adafruit_metro_esp32s3.menu.DebugLevel.none.build.code_debug=0 +adafruit_metro_esp32s3.menu.DebugLevel.error=Error +adafruit_metro_esp32s3.menu.DebugLevel.error.build.code_debug=1 +adafruit_metro_esp32s3.menu.DebugLevel.warn=Warn +adafruit_metro_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +adafruit_metro_esp32s3.menu.DebugLevel.info=Info +adafruit_metro_esp32s3.menu.DebugLevel.info.build.code_debug=3 +adafruit_metro_esp32s3.menu.DebugLevel.debug=Debug +adafruit_metro_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +adafruit_metro_esp32s3.menu.DebugLevel.verbose=Verbose +adafruit_metro_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_metro_esp32s3.menu.EraseFlash.none=Disabled +adafruit_metro_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +adafruit_metro_esp32s3.menu.EraseFlash.all=Enabled +adafruit_metro_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_metro_esp32s3.menu.ZigbeeMode.default=Disabled +adafruit_metro_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_metro_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_metro_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_metro_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_metro_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit MagTag 2.9" + +adafruit_magtag29_esp32s2.name=Adafruit MagTag 2.9" +adafruit_magtag29_esp32s2.vid.0=0x239A +adafruit_magtag29_esp32s2.pid.0=0x80E5 +adafruit_magtag29_esp32s2.vid.1=0x239A +adafruit_magtag29_esp32s2.pid.1=0x00E5 +adafruit_magtag29_esp32s2.vid.2=0x239A +adafruit_magtag29_esp32s2.pid.2=0x80E6 +adafruit_magtag29_esp32s2.upload_port.0.vid=0x239A +adafruit_magtag29_esp32s2.upload_port.0.pid=0x80E5 +adafruit_magtag29_esp32s2.upload_port.1.vid=0x239A +adafruit_magtag29_esp32s2.upload_port.1.pid=0x00E5 +adafruit_magtag29_esp32s2.upload_port.2.vid=0x239A +adafruit_magtag29_esp32s2.upload_port.2.pid=0x80E6 + +adafruit_magtag29_esp32s2.bootloader.tool=esptool_py +adafruit_magtag29_esp32s2.bootloader.tool.default=esptool_py + +adafruit_magtag29_esp32s2.upload.tool=esptool_py +adafruit_magtag29_esp32s2.upload.tool.default=esptool_py +adafruit_magtag29_esp32s2.upload.tool.network=esp_ota + +adafruit_magtag29_esp32s2.upload.maximum_size=1310720 +adafruit_magtag29_esp32s2.upload.maximum_data_size=327680 +adafruit_magtag29_esp32s2.upload.flags= +adafruit_magtag29_esp32s2.upload.extra_flags= +adafruit_magtag29_esp32s2.upload.use_1200bps_touch=true +adafruit_magtag29_esp32s2.upload.wait_for_upload_port=true + +adafruit_magtag29_esp32s2.serial.disableDTR=false +adafruit_magtag29_esp32s2.serial.disableRTS=false + +adafruit_magtag29_esp32s2.build.tarch=xtensa +adafruit_magtag29_esp32s2.build.bootloader_addr=0x1000 +adafruit_magtag29_esp32s2.build.target=esp32s2 +adafruit_magtag29_esp32s2.build.mcu=esp32s2 +adafruit_magtag29_esp32s2.build.core=esp32 +adafruit_magtag29_esp32s2.build.variant=adafruit_magtag29_esp32s2 +adafruit_magtag29_esp32s2.build.board=MAGTAG29_ESP32S2 + +adafruit_magtag29_esp32s2.build.cdc_on_boot=1 +adafruit_magtag29_esp32s2.build.msc_on_boot=0 +adafruit_magtag29_esp32s2.build.dfu_on_boot=0 +adafruit_magtag29_esp32s2.build.f_cpu=240000000L +adafruit_magtag29_esp32s2.build.flash_size=4MB +adafruit_magtag29_esp32s2.build.flash_freq=80m +adafruit_magtag29_esp32s2.build.flash_mode=dio +adafruit_magtag29_esp32s2.build.boot=qio +adafruit_magtag29_esp32s2.build.partitions=default +adafruit_magtag29_esp32s2.build.defines= + +adafruit_magtag29_esp32s2.menu.CDCOnBoot.cdc=Enabled +adafruit_magtag29_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_magtag29_esp32s2.menu.CDCOnBoot.default=Disabled +adafruit_magtag29_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_magtag29_esp32s2.menu.MSCOnBoot.default=Disabled +adafruit_magtag29_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_magtag29_esp32s2.menu.MSCOnBoot.msc=Enabled +adafruit_magtag29_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_magtag29_esp32s2.menu.DFUOnBoot.default=Disabled +adafruit_magtag29_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_magtag29_esp32s2.menu.DFUOnBoot.dfu=Enabled +adafruit_magtag29_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_magtag29_esp32s2.menu.UploadMode.cdc=Internal USB +adafruit_magtag29_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_magtag29_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_magtag29_esp32s2.menu.UploadMode.default=UART0 +adafruit_magtag29_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_magtag29_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_magtag29_esp32s2.menu.PSRAM.enabled=Enabled +adafruit_magtag29_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_magtag29_esp32s2.menu.PSRAM.disabled=Disabled +adafruit_magtag29_esp32s2.menu.PSRAM.disabled.build.defines= + +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_magtag29_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.default.build.partitions=default +adafruit_magtag29_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_magtag29_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_magtag29_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_magtag29_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_magtag29_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_magtag29_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_magtag29_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_magtag29_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_magtag29_esp32s2.menu.CPUFreq.40=40MHz +adafruit_magtag29_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_magtag29_esp32s2.menu.CPUFreq.20=20MHz +adafruit_magtag29_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_magtag29_esp32s2.menu.CPUFreq.10=10MHz +adafruit_magtag29_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_magtag29_esp32s2.menu.FlashMode.qio=QIO +adafruit_magtag29_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_magtag29_esp32s2.menu.FlashMode.qio.build.boot=qio +adafruit_magtag29_esp32s2.menu.FlashMode.dio=DIO +adafruit_magtag29_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_magtag29_esp32s2.menu.FlashMode.dio.build.boot=dio + +adafruit_magtag29_esp32s2.menu.FlashFreq.80=80MHz +adafruit_magtag29_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_magtag29_esp32s2.menu.FlashFreq.40=40MHz +adafruit_magtag29_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_magtag29_esp32s2.menu.FlashSize.4M=4MB (32Mb) +adafruit_magtag29_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_magtag29_esp32s2.menu.UploadSpeed.921600=921600 +adafruit_magtag29_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_magtag29_esp32s2.menu.UploadSpeed.115200=115200 +adafruit_magtag29_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_magtag29_esp32s2.menu.UploadSpeed.256000.windows=256000 +adafruit_magtag29_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_magtag29_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_magtag29_esp32s2.menu.UploadSpeed.230400=230400 +adafruit_magtag29_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.linux=460800 +adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.macosx=460800 +adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_magtag29_esp32s2.menu.UploadSpeed.512000.windows=512000 +adafruit_magtag29_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_magtag29_esp32s2.menu.DebugLevel.none=None +adafruit_magtag29_esp32s2.menu.DebugLevel.none.build.code_debug=0 +adafruit_magtag29_esp32s2.menu.DebugLevel.error=Error +adafruit_magtag29_esp32s2.menu.DebugLevel.error.build.code_debug=1 +adafruit_magtag29_esp32s2.menu.DebugLevel.warn=Warn +adafruit_magtag29_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_magtag29_esp32s2.menu.DebugLevel.info=Info +adafruit_magtag29_esp32s2.menu.DebugLevel.info.build.code_debug=3 +adafruit_magtag29_esp32s2.menu.DebugLevel.debug=Debug +adafruit_magtag29_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_magtag29_esp32s2.menu.DebugLevel.verbose=Verbose +adafruit_magtag29_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_magtag29_esp32s2.menu.EraseFlash.none=Disabled +adafruit_magtag29_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_magtag29_esp32s2.menu.EraseFlash.all=Enabled +adafruit_magtag29_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_magtag29_esp32s2.menu.ZigbeeMode.default=Disabled +adafruit_magtag29_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_magtag29_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit FunHouse + +adafruit_funhouse_esp32s2.name=Adafruit FunHouse +adafruit_funhouse_esp32s2.vid.0=0x239A +adafruit_funhouse_esp32s2.pid.0=0x80F9 +adafruit_funhouse_esp32s2.vid.1=0x239A +adafruit_funhouse_esp32s2.pid.1=0x00F9 +adafruit_funhouse_esp32s2.vid.2=0x239A +adafruit_funhouse_esp32s2.pid.2=0x80FA +adafruit_funhouse_esp32s2.upload_port.0.vid=0x239A +adafruit_funhouse_esp32s2.upload_port.0.pid=0x80F9 +adafruit_funhouse_esp32s2.upload_port.1.vid=0x239A +adafruit_funhouse_esp32s2.upload_port.1.pid=0x00F9 +adafruit_funhouse_esp32s2.upload_port.2.vid=0x239A +adafruit_funhouse_esp32s2.upload_port.2.pid=0x80FA + +adafruit_funhouse_esp32s2.bootloader.tool=esptool_py +adafruit_funhouse_esp32s2.bootloader.tool.default=esptool_py + +adafruit_funhouse_esp32s2.upload.tool=esptool_py +adafruit_funhouse_esp32s2.upload.tool.default=esptool_py +adafruit_funhouse_esp32s2.upload.tool.network=esp_ota + +adafruit_funhouse_esp32s2.upload.maximum_size=1310720 +adafruit_funhouse_esp32s2.upload.maximum_data_size=327680 +adafruit_funhouse_esp32s2.upload.flags= +adafruit_funhouse_esp32s2.upload.extra_flags= +adafruit_funhouse_esp32s2.upload.use_1200bps_touch=true +adafruit_funhouse_esp32s2.upload.wait_for_upload_port=true + +adafruit_funhouse_esp32s2.serial.disableDTR=false +adafruit_funhouse_esp32s2.serial.disableRTS=false + +adafruit_funhouse_esp32s2.build.tarch=xtensa +adafruit_funhouse_esp32s2.build.bootloader_addr=0x1000 +adafruit_funhouse_esp32s2.build.target=esp32s2 +adafruit_funhouse_esp32s2.build.mcu=esp32s2 +adafruit_funhouse_esp32s2.build.core=esp32 +adafruit_funhouse_esp32s2.build.variant=adafruit_funhouse_esp32s2 +adafruit_funhouse_esp32s2.build.board=FUNHOUSE_ESP32S2 + +adafruit_funhouse_esp32s2.build.cdc_on_boot=1 +adafruit_funhouse_esp32s2.build.msc_on_boot=0 +adafruit_funhouse_esp32s2.build.dfu_on_boot=0 +adafruit_funhouse_esp32s2.build.f_cpu=240000000L +adafruit_funhouse_esp32s2.build.flash_size=4MB +adafruit_funhouse_esp32s2.build.flash_freq=80m +adafruit_funhouse_esp32s2.build.flash_mode=dio +adafruit_funhouse_esp32s2.build.boot=qio +adafruit_funhouse_esp32s2.build.partitions=default +adafruit_funhouse_esp32s2.build.defines= + +adafruit_funhouse_esp32s2.menu.CDCOnBoot.cdc=Enabled +adafruit_funhouse_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_funhouse_esp32s2.menu.CDCOnBoot.default=Disabled +adafruit_funhouse_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_funhouse_esp32s2.menu.MSCOnBoot.default=Disabled +adafruit_funhouse_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_funhouse_esp32s2.menu.MSCOnBoot.msc=Enabled +adafruit_funhouse_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_funhouse_esp32s2.menu.DFUOnBoot.default=Disabled +adafruit_funhouse_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_funhouse_esp32s2.menu.DFUOnBoot.dfu=Enabled +adafruit_funhouse_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_funhouse_esp32s2.menu.UploadMode.cdc=Internal USB +adafruit_funhouse_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_funhouse_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_funhouse_esp32s2.menu.UploadMode.default=UART0 +adafruit_funhouse_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_funhouse_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_funhouse_esp32s2.menu.PSRAM.enabled=Enabled +adafruit_funhouse_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_funhouse_esp32s2.menu.PSRAM.disabled=Disabled +adafruit_funhouse_esp32s2.menu.PSRAM.disabled.build.defines= + +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_funhouse_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.default.build.partitions=default +adafruit_funhouse_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_funhouse_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_funhouse_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_funhouse_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_funhouse_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_funhouse_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_funhouse_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_funhouse_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_funhouse_esp32s2.menu.CPUFreq.40=40MHz +adafruit_funhouse_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_funhouse_esp32s2.menu.CPUFreq.20=20MHz +adafruit_funhouse_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_funhouse_esp32s2.menu.CPUFreq.10=10MHz +adafruit_funhouse_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_funhouse_esp32s2.menu.FlashMode.qio=QIO +adafruit_funhouse_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_funhouse_esp32s2.menu.FlashMode.qio.build.boot=qio +adafruit_funhouse_esp32s2.menu.FlashMode.dio=DIO +adafruit_funhouse_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_funhouse_esp32s2.menu.FlashMode.dio.build.boot=dio + +adafruit_funhouse_esp32s2.menu.FlashFreq.80=80MHz +adafruit_funhouse_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_funhouse_esp32s2.menu.FlashFreq.40=40MHz +adafruit_funhouse_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_funhouse_esp32s2.menu.FlashSize.4M=4MB (32Mb) +adafruit_funhouse_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_funhouse_esp32s2.menu.UploadSpeed.921600=921600 +adafruit_funhouse_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_funhouse_esp32s2.menu.UploadSpeed.115200=115200 +adafruit_funhouse_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_funhouse_esp32s2.menu.UploadSpeed.256000.windows=256000 +adafruit_funhouse_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_funhouse_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_funhouse_esp32s2.menu.UploadSpeed.230400=230400 +adafruit_funhouse_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.linux=460800 +adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.macosx=460800 +adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_funhouse_esp32s2.menu.UploadSpeed.512000.windows=512000 +adafruit_funhouse_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_funhouse_esp32s2.menu.DebugLevel.none=None +adafruit_funhouse_esp32s2.menu.DebugLevel.none.build.code_debug=0 +adafruit_funhouse_esp32s2.menu.DebugLevel.error=Error +adafruit_funhouse_esp32s2.menu.DebugLevel.error.build.code_debug=1 +adafruit_funhouse_esp32s2.menu.DebugLevel.warn=Warn +adafruit_funhouse_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_funhouse_esp32s2.menu.DebugLevel.info=Info +adafruit_funhouse_esp32s2.menu.DebugLevel.info.build.code_debug=3 +adafruit_funhouse_esp32s2.menu.DebugLevel.debug=Debug +adafruit_funhouse_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_funhouse_esp32s2.menu.DebugLevel.verbose=Verbose +adafruit_funhouse_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_funhouse_esp32s2.menu.EraseFlash.none=Disabled +adafruit_funhouse_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_funhouse_esp32s2.menu.EraseFlash.all=Enabled +adafruit_funhouse_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_funhouse_esp32s2.menu.ZigbeeMode.default=Disabled +adafruit_funhouse_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_funhouse_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit ESP32 Feather + +featheresp32.name=Adafruit ESP32 Feather + +featheresp32.bootloader.tool=esptool_py +featheresp32.bootloader.tool.default=esptool_py + +featheresp32.upload.tool=esptool_py +featheresp32.upload.tool.default=esptool_py +featheresp32.upload.tool.network=esp_ota + +featheresp32.upload.maximum_size=1310720 +featheresp32.upload.maximum_data_size=327680 +featheresp32.upload.flags= +featheresp32.upload.extra_flags= + +featheresp32.serial.disableDTR=true +featheresp32.serial.disableRTS=true + +featheresp32.build.tarch=xtensa +featheresp32.build.bootloader_addr=0x1000 +featheresp32.build.target=esp32 +featheresp32.build.mcu=esp32 +featheresp32.build.core=esp32 +featheresp32.build.variant=feather_esp32 +featheresp32.build.board=FEATHER_ESP32 + +featheresp32.build.f_cpu=240000000L +featheresp32.build.flash_size=4MB +featheresp32.build.flash_freq=80m +featheresp32.build.flash_mode=dio +featheresp32.build.boot=dio +featheresp32.build.partitions=default +featheresp32.build.defines= +featheresp32.build.loop_core= +featheresp32.build.event_core= + +featheresp32.menu.LoopCore.1=Core 1 +featheresp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +featheresp32.menu.LoopCore.0=Core 0 +featheresp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +featheresp32.menu.EventsCore.1=Core 1 +featheresp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +featheresp32.menu.EventsCore.0=Core 0 +featheresp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +featheresp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +featheresp32.menu.PartitionScheme.default.build.partitions=default +featheresp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +featheresp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +featheresp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +featheresp32.menu.PartitionScheme.minimal.build.partitions=minimal +featheresp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +featheresp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +featheresp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +featheresp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +featheresp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +featheresp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +featheresp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +featheresp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +featheresp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +featheresp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +featheresp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +featheresp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +featheresp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +featheresp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +featheresp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +featheresp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +featheresp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +featheresp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +featheresp32.menu.CPUFreq.240=240MHz (WiFi/BT) +featheresp32.menu.CPUFreq.240.build.f_cpu=240000000L +featheresp32.menu.CPUFreq.160=160MHz (WiFi/BT) +featheresp32.menu.CPUFreq.160.build.f_cpu=160000000L +featheresp32.menu.CPUFreq.80=80MHz (WiFi/BT) +featheresp32.menu.CPUFreq.80.build.f_cpu=80000000L +featheresp32.menu.CPUFreq.40=40MHz +featheresp32.menu.CPUFreq.40.build.f_cpu=40000000L +featheresp32.menu.CPUFreq.20=20MHz +featheresp32.menu.CPUFreq.20.build.f_cpu=20000000L +featheresp32.menu.CPUFreq.10=10MHz +featheresp32.menu.CPUFreq.10.build.f_cpu=10000000L + +featheresp32.menu.FlashFreq.80=80MHz +featheresp32.menu.FlashFreq.80.build.flash_freq=80m +featheresp32.menu.FlashFreq.40=40MHz +featheresp32.menu.FlashFreq.40.build.flash_freq=40m + +featheresp32.menu.FlashSize.4M=4MB (32Mb) +featheresp32.menu.FlashSize.4M.build.flash_size=4MB + +featheresp32.menu.UploadSpeed.921600=921600 +featheresp32.menu.UploadSpeed.921600.upload.speed=921600 +featheresp32.menu.UploadSpeed.115200=115200 +featheresp32.menu.UploadSpeed.115200.upload.speed=115200 +featheresp32.menu.UploadSpeed.256000.windows=256000 +featheresp32.menu.UploadSpeed.256000.upload.speed=256000 +featheresp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +featheresp32.menu.UploadSpeed.230400=230400 +featheresp32.menu.UploadSpeed.230400.upload.speed=230400 +featheresp32.menu.UploadSpeed.460800.linux=460800 +featheresp32.menu.UploadSpeed.460800.macosx=460800 +featheresp32.menu.UploadSpeed.460800.upload.speed=460800 +featheresp32.menu.UploadSpeed.512000.windows=512000 +featheresp32.menu.UploadSpeed.512000.upload.speed=512000 + +featheresp32.menu.DebugLevel.none=None +featheresp32.menu.DebugLevel.none.build.code_debug=0 +featheresp32.menu.DebugLevel.error=Error +featheresp32.menu.DebugLevel.error.build.code_debug=1 +featheresp32.menu.DebugLevel.warn=Warn +featheresp32.menu.DebugLevel.warn.build.code_debug=2 +featheresp32.menu.DebugLevel.info=Info +featheresp32.menu.DebugLevel.info.build.code_debug=3 +featheresp32.menu.DebugLevel.debug=Debug +featheresp32.menu.DebugLevel.debug.build.code_debug=4 +featheresp32.menu.DebugLevel.verbose=Verbose +featheresp32.menu.DebugLevel.verbose.build.code_debug=5 + +featheresp32.menu.EraseFlash.none=Disabled +featheresp32.menu.EraseFlash.none.upload.erase_cmd= +featheresp32.menu.EraseFlash.all=Enabled +featheresp32.menu.EraseFlash.all.upload.erase_cmd=-e + +featheresp32.menu.ZigbeeMode.default=Disabled +featheresp32.menu.ZigbeeMode.default.build.zigbee_mode= +featheresp32.menu.ZigbeeMode.default.build.zigbee_libs= +featheresp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +featheresp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +featheresp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32 V2 + +adafruit_feather_esp32_v2.name=Adafruit Feather ESP32 V2 + +adafruit_feather_esp32_v2.bootloader.tool=esptool_py +adafruit_feather_esp32_v2.bootloader.tool.default=esptool_py + +adafruit_feather_esp32_v2.upload.tool=esptool_py +adafruit_feather_esp32_v2.upload.tool.default=esptool_py +adafruit_feather_esp32_v2.upload.tool.network=esp_ota + +adafruit_feather_esp32_v2.upload.maximum_size=1310720 +adafruit_feather_esp32_v2.upload.maximum_data_size=327680 +adafruit_feather_esp32_v2.upload.flags= +adafruit_feather_esp32_v2.upload.extra_flags= + +adafruit_feather_esp32_v2.serial.disableDTR=true +adafruit_feather_esp32_v2.serial.disableRTS=true + +adafruit_feather_esp32_v2.build.tarch=xtensa +adafruit_feather_esp32_v2.build.bootloader_addr=0x1000 +adafruit_feather_esp32_v2.build.target=esp32 +adafruit_feather_esp32_v2.build.mcu=esp32 +adafruit_feather_esp32_v2.build.core=esp32 +adafruit_feather_esp32_v2.build.variant=adafruit_feather_esp32_v2 +adafruit_feather_esp32_v2.build.board=ADAFRUIT_FEATHER_ESP32_V2 + +adafruit_feather_esp32_v2.build.f_cpu=240000000L +adafruit_feather_esp32_v2.build.flash_size=8MB +adafruit_feather_esp32_v2.build.flash_freq=80m +adafruit_feather_esp32_v2.build.flash_mode=dio +adafruit_feather_esp32_v2.build.boot=dio +adafruit_feather_esp32_v2.build.partitions=default +adafruit_feather_esp32_v2.build.defines= +adafruit_feather_esp32_v2.build.loop_core= +adafruit_feather_esp32_v2.build.event_core= + +adafruit_feather_esp32_v2.menu.LoopCore.1=Core 1 +adafruit_feather_esp32_v2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_feather_esp32_v2.menu.LoopCore.0=Core 0 +adafruit_feather_esp32_v2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_feather_esp32_v2.menu.EventsCore.1=Core 1 +adafruit_feather_esp32_v2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_feather_esp32_v2.menu.EventsCore.0=Core 0 +adafruit_feather_esp32_v2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_feather_esp32_v2.menu.PSRAM.enabled=Enabled +adafruit_feather_esp32_v2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +adafruit_feather_esp32_v2.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32_v2.menu.PSRAM.disabled.build.defines= + +adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP / 5.3MB SPIFFS) +adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB +adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720 + +adafruit_feather_esp32_v2.menu.CPUFreq.240=240MHz (WiFi/BT) +adafruit_feather_esp32_v2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32_v2.menu.CPUFreq.160=160MHz (WiFi/BT) +adafruit_feather_esp32_v2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32_v2.menu.CPUFreq.80=80MHz (WiFi/BT) +adafruit_feather_esp32_v2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32_v2.menu.CPUFreq.40=40MHz +adafruit_feather_esp32_v2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32_v2.menu.CPUFreq.20=20MHz +adafruit_feather_esp32_v2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32_v2.menu.CPUFreq.10=10MHz +adafruit_feather_esp32_v2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32_v2.menu.FlashFreq.80=80MHz +adafruit_feather_esp32_v2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_feather_esp32_v2.menu.FlashFreq.40=40MHz +adafruit_feather_esp32_v2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_feather_esp32_v2.menu.FlashSize.8M=8MB (64Mb) +adafruit_feather_esp32_v2.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_feather_esp32_v2.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32_v2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32_v2.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32_v2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32_v2.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32_v2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32_v2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32_v2.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32_v2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32_v2.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32_v2.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32_v2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32_v2.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32_v2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32_v2.menu.DebugLevel.none=None +adafruit_feather_esp32_v2.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32_v2.menu.DebugLevel.error=Error +adafruit_feather_esp32_v2.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32_v2.menu.DebugLevel.warn=Warn +adafruit_feather_esp32_v2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32_v2.menu.DebugLevel.info=Info +adafruit_feather_esp32_v2.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32_v2.menu.DebugLevel.debug=Debug +adafruit_feather_esp32_v2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32_v2.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32_v2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32_v2.menu.EraseFlash.none=Disabled +adafruit_feather_esp32_v2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32_v2.menu.EraseFlash.all=Enabled +adafruit_feather_esp32_v2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32_v2.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32_v2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32_v2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S2 + +adafruit_feather_esp32s2.name=Adafruit Feather ESP32-S2 +adafruit_feather_esp32s2.vid.0=0x239A +adafruit_feather_esp32s2.pid.0=0x80EB +adafruit_feather_esp32s2.vid.1=0x239A +adafruit_feather_esp32s2.pid.1=0x00EB +adafruit_feather_esp32s2.vid.2=0x239A +adafruit_feather_esp32s2.pid.2=0x80EC +adafruit_feather_esp32s2.upload_port.0.vid=0x239A +adafruit_feather_esp32s2.upload_port.0.pid=0x80EB +adafruit_feather_esp32s2.upload_port.1.vid=0x239A +adafruit_feather_esp32s2.upload_port.1.pid=0x00EB +adafruit_feather_esp32s2.upload_port.2.vid=0x239A +adafruit_feather_esp32s2.upload_port.2.pid=0x80EC + +adafruit_feather_esp32s2.bootloader.tool=esptool_py +adafruit_feather_esp32s2.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s2.upload.tool=esptool_py +adafruit_feather_esp32s2.upload.tool.default=esptool_py +adafruit_feather_esp32s2.upload.tool.network=esp_ota + +adafruit_feather_esp32s2.upload.maximum_size=1310720 +adafruit_feather_esp32s2.upload.maximum_data_size=327680 +adafruit_feather_esp32s2.upload.flags= +adafruit_feather_esp32s2.upload.extra_flags= +adafruit_feather_esp32s2.upload.use_1200bps_touch=true +adafruit_feather_esp32s2.upload.wait_for_upload_port=true + +adafruit_feather_esp32s2.serial.disableDTR=false +adafruit_feather_esp32s2.serial.disableRTS=false + +adafruit_feather_esp32s2.build.tarch=xtensa +adafruit_feather_esp32s2.build.bootloader_addr=0x1000 +adafruit_feather_esp32s2.build.target=esp32s2 +adafruit_feather_esp32s2.build.mcu=esp32s2 +adafruit_feather_esp32s2.build.core=esp32 +adafruit_feather_esp32s2.build.variant=adafruit_feather_esp32s2 +adafruit_feather_esp32s2.build.board=ADAFRUIT_FEATHER_ESP32S2 + +adafruit_feather_esp32s2.build.cdc_on_boot=1 +adafruit_feather_esp32s2.build.msc_on_boot=0 +adafruit_feather_esp32s2.build.dfu_on_boot=0 +adafruit_feather_esp32s2.build.f_cpu=240000000L +adafruit_feather_esp32s2.build.flash_size=4MB +adafruit_feather_esp32s2.build.flash_freq=80m +adafruit_feather_esp32s2.build.flash_mode=dio +adafruit_feather_esp32s2.build.boot=qio +adafruit_feather_esp32s2.build.partitions=default +adafruit_feather_esp32s2.build.defines= + +adafruit_feather_esp32s2.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s2.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s2.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s2.menu.MSCOnBoot.msc=Enabled +adafruit_feather_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s2.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s2.menu.DFUOnBoot.dfu=Enabled +adafruit_feather_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s2.menu.UploadMode.cdc=Internal USB +adafruit_feather_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s2.menu.UploadMode.default=UART0 +adafruit_feather_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s2.menu.PSRAM.enabled=Enabled +adafruit_feather_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s2.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s2.menu.PSRAM.disabled.build.defines= + +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s2.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s2.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s2.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s2.menu.FlashMode.qio=QIO +adafruit_feather_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s2.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s2.menu.FlashMode.dio=DIO +adafruit_feather_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s2.menu.FlashMode.dio.build.boot=dio + +adafruit_feather_esp32s2.menu.FlashFreq.80=80MHz +adafruit_feather_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_feather_esp32s2.menu.FlashFreq.40=40MHz +adafruit_feather_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_feather_esp32s2.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s2.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s2.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s2.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s2.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s2.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s2.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s2.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s2.menu.DebugLevel.none=None +adafruit_feather_esp32s2.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s2.menu.DebugLevel.error=Error +adafruit_feather_esp32s2.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s2.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s2.menu.DebugLevel.info=Info +adafruit_feather_esp32s2.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s2.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s2.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s2.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s2.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s2.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S2 TFT + +adafruit_feather_esp32s2_tft.name=Adafruit Feather ESP32-S2 TFT +adafruit_feather_esp32s2_tft.vid.0=0x239A +adafruit_feather_esp32s2_tft.pid.0=0x810F +adafruit_feather_esp32s2_tft.vid.1=0x239A +adafruit_feather_esp32s2_tft.pid.1=0x010F +adafruit_feather_esp32s2_tft.vid.2=0x239A +adafruit_feather_esp32s2_tft.pid.2=0x8110 +adafruit_feather_esp32s2_tft.upload_port.0.vid=0x239A +adafruit_feather_esp32s2_tft.upload_port.0.pid=0x810F +adafruit_feather_esp32s2_tft.upload_port.1.vid=0x239A +adafruit_feather_esp32s2_tft.upload_port.1.pid=0x010F +adafruit_feather_esp32s2_tft.upload_port.2.vid=0x239A +adafruit_feather_esp32s2_tft.upload_port.2.pid=0x8110 + +adafruit_feather_esp32s2_tft.bootloader.tool=esptool_py +adafruit_feather_esp32s2_tft.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s2_tft.upload.tool=esptool_py +adafruit_feather_esp32s2_tft.upload.tool.default=esptool_py +adafruit_feather_esp32s2_tft.upload.tool.network=esp_ota + +adafruit_feather_esp32s2_tft.upload.maximum_size=1310720 +adafruit_feather_esp32s2_tft.upload.maximum_data_size=327680 +adafruit_feather_esp32s2_tft.upload.flags= +adafruit_feather_esp32s2_tft.upload.extra_flags= +adafruit_feather_esp32s2_tft.upload.use_1200bps_touch=true +adafruit_feather_esp32s2_tft.upload.wait_for_upload_port=true + +adafruit_feather_esp32s2_tft.serial.disableDTR=false +adafruit_feather_esp32s2_tft.serial.disableRTS=false + +adafruit_feather_esp32s2_tft.build.tarch=xtensa +adafruit_feather_esp32s2_tft.build.bootloader_addr=0x1000 +adafruit_feather_esp32s2_tft.build.target=esp32s2 +adafruit_feather_esp32s2_tft.build.mcu=esp32s2 +adafruit_feather_esp32s2_tft.build.core=esp32 +adafruit_feather_esp32s2_tft.build.variant=adafruit_feather_esp32s2_tft +adafruit_feather_esp32s2_tft.build.board=ADAFRUIT_FEATHER_ESP32S2_TFT + +adafruit_feather_esp32s2_tft.build.cdc_on_boot=1 +adafruit_feather_esp32s2_tft.build.msc_on_boot=0 +adafruit_feather_esp32s2_tft.build.dfu_on_boot=0 +adafruit_feather_esp32s2_tft.build.f_cpu=240000000L +adafruit_feather_esp32s2_tft.build.flash_size=4MB +adafruit_feather_esp32s2_tft.build.flash_freq=80m +adafruit_feather_esp32s2_tft.build.flash_mode=dio +adafruit_feather_esp32s2_tft.build.boot=qio +adafruit_feather_esp32s2_tft.build.partitions=default +adafruit_feather_esp32s2_tft.build.defines= + +adafruit_feather_esp32s2_tft.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s2_tft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s2_tft.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s2_tft.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s2_tft.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s2_tft.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s2_tft.menu.MSCOnBoot.msc=Enabled +adafruit_feather_esp32s2_tft.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s2_tft.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s2_tft.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s2_tft.menu.DFUOnBoot.dfu=Enabled +adafruit_feather_esp32s2_tft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s2_tft.menu.UploadMode.cdc=Internal USB +adafruit_feather_esp32s2_tft.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s2_tft.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s2_tft.menu.UploadMode.default=UART0 +adafruit_feather_esp32s2_tft.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s2_tft.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s2_tft.menu.PSRAM.enabled=Enabled +adafruit_feather_esp32s2_tft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s2_tft.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s2_tft.menu.PSRAM.disabled.build.defines= + +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2_tft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s2_tft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s2_tft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s2_tft.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s2_tft.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s2_tft.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s2_tft.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s2_tft.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s2_tft.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s2_tft.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s2_tft.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s2_tft.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s2_tft.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s2_tft.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s2_tft.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s2_tft.menu.FlashMode.qio=QIO +adafruit_feather_esp32s2_tft.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s2_tft.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s2_tft.menu.FlashMode.dio=DIO +adafruit_feather_esp32s2_tft.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s2_tft.menu.FlashMode.dio.build.boot=dio + +adafruit_feather_esp32s2_tft.menu.FlashFreq.80=80MHz +adafruit_feather_esp32s2_tft.menu.FlashFreq.80.build.flash_freq=80m +adafruit_feather_esp32s2_tft.menu.FlashFreq.40=40MHz +adafruit_feather_esp32s2_tft.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_feather_esp32s2_tft.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s2_tft.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s2_tft.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s2_tft.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s2_tft.menu.DebugLevel.none=None +adafruit_feather_esp32s2_tft.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s2_tft.menu.DebugLevel.error=Error +adafruit_feather_esp32s2_tft.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s2_tft.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s2_tft.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s2_tft.menu.DebugLevel.info=Info +adafruit_feather_esp32s2_tft.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s2_tft.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s2_tft.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s2_tft.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s2_tft.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s2_tft.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s2_tft.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s2_tft.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s2_tft.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S2 Reverse TFT + +adafruit_feather_esp32s2_reversetft.name=Adafruit Feather ESP32-S2 Reverse TFT +adafruit_feather_esp32s2_reversetft.vid.0=0x239A +adafruit_feather_esp32s2_reversetft.pid.0=0x80ED +adafruit_feather_esp32s2_reversetft.vid.1=0x239A +adafruit_feather_esp32s2_reversetft.pid.1=0x00ED +adafruit_feather_esp32s2_reversetft.vid.2=0x239A +adafruit_feather_esp32s2_reversetft.pid.2=0x80EE +adafruit_feather_esp32s2_reversetft.upload_port.0.vid=0x239A +adafruit_feather_esp32s2_reversetft.upload_port.0.pid=0x80ED +adafruit_feather_esp32s2_reversetft.upload_port.1.vid=0x239A +adafruit_feather_esp32s2_reversetft.upload_port.1.pid=0x00ED +adafruit_feather_esp32s2_reversetft.upload_port.2.vid=0x239A +adafruit_feather_esp32s2_reversetft.upload_port.2.pid=0x80EE + +adafruit_feather_esp32s2_reversetft.bootloader.tool=esptool_py +adafruit_feather_esp32s2_reversetft.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s2_reversetft.upload.tool=esptool_py +adafruit_feather_esp32s2_reversetft.upload.tool.default=esptool_py +adafruit_feather_esp32s2_reversetft.upload.tool.network=esp_ota + +adafruit_feather_esp32s2_reversetft.upload.maximum_size=1310720 +adafruit_feather_esp32s2_reversetft.upload.maximum_data_size=327680 +adafruit_feather_esp32s2_reversetft.upload.flags= +adafruit_feather_esp32s2_reversetft.upload.extra_flags= +adafruit_feather_esp32s2_reversetft.upload.use_1200bps_touch=true +adafruit_feather_esp32s2_reversetft.upload.wait_for_upload_port=true + +adafruit_feather_esp32s2_reversetft.serial.disableDTR=false +adafruit_feather_esp32s2_reversetft.serial.disableRTS=false + +adafruit_feather_esp32s2_reversetft.build.tarch=xtensa +adafruit_feather_esp32s2_reversetft.build.bootloader_addr=0x1000 +adafruit_feather_esp32s2_reversetft.build.target=esp32s2 +adafruit_feather_esp32s2_reversetft.build.mcu=esp32s2 +adafruit_feather_esp32s2_reversetft.build.core=esp32 +adafruit_feather_esp32s2_reversetft.build.variant=adafruit_feather_esp32s2_reversetft +adafruit_feather_esp32s2_reversetft.build.board=ADAFRUIT_FEATHER_ESP32S2_REVTFT + +adafruit_feather_esp32s2_reversetft.build.cdc_on_boot=1 +adafruit_feather_esp32s2_reversetft.build.msc_on_boot=0 +adafruit_feather_esp32s2_reversetft.build.dfu_on_boot=0 +adafruit_feather_esp32s2_reversetft.build.f_cpu=240000000L +adafruit_feather_esp32s2_reversetft.build.flash_size=4MB +adafruit_feather_esp32s2_reversetft.build.flash_freq=80m +adafruit_feather_esp32s2_reversetft.build.flash_mode=dio +adafruit_feather_esp32s2_reversetft.build.boot=qio +adafruit_feather_esp32s2_reversetft.build.partitions=default +adafruit_feather_esp32s2_reversetft.build.defines= + +adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.msc=Enabled +adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.dfu=Enabled +adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc=Internal USB +adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s2_reversetft.menu.UploadMode.default=UART0 +adafruit_feather_esp32s2_reversetft.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s2_reversetft.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s2_reversetft.menu.PSRAM.enabled=Enabled +adafruit_feather_esp32s2_reversetft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s2_reversetft.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s2_reversetft.menu.PSRAM.disabled.build.defines= + +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s2_reversetft.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio=QIO +adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio=DIO +adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio.build.boot=dio + +adafruit_feather_esp32s2_reversetft.menu.FlashFreq.80=80MHz +adafruit_feather_esp32s2_reversetft.menu.FlashFreq.80.build.flash_freq=80m +adafruit_feather_esp32s2_reversetft.menu.FlashFreq.40=40MHz +adafruit_feather_esp32s2_reversetft.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_feather_esp32s2_reversetft.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s2_reversetft.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.none=None +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.error=Error +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.info=Info +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s2_reversetft.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s2_reversetft.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s2_reversetft.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s2_reversetft.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s2_reversetft.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S3 2MB PSRAM + +adafruit_feather_esp32s3.name=Adafruit Feather ESP32-S3 2MB PSRAM +adafruit_feather_esp32s3.vid.0=0x239A +adafruit_feather_esp32s3.pid.0=0x811B +adafruit_feather_esp32s3.vid.1=0x239A +adafruit_feather_esp32s3.pid.1=0x011B +adafruit_feather_esp32s3.vid.2=0x239A +adafruit_feather_esp32s3.pid.2=0x811C +adafruit_feather_esp32s3.upload_port.0.vid=0x239A +adafruit_feather_esp32s3.upload_port.0.pid=0x811B +adafruit_feather_esp32s3.upload_port.1.vid=0x239A +adafruit_feather_esp32s3.upload_port.1.pid=0x011B +adafruit_feather_esp32s3.upload_port.2.vid=0x239A +adafruit_feather_esp32s3.upload_port.2.pid=0x811C + +adafruit_feather_esp32s3.bootloader.tool=esptool_py +adafruit_feather_esp32s3.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s3.upload.tool=esptool_py +adafruit_feather_esp32s3.upload.tool.default=esptool_py +adafruit_feather_esp32s3.upload.tool.network=esp_ota + +adafruit_feather_esp32s3.upload.maximum_size=1310720 +adafruit_feather_esp32s3.upload.maximum_data_size=327680 +adafruit_feather_esp32s3.upload.flags= +adafruit_feather_esp32s3.upload.extra_flags= +adafruit_feather_esp32s3.upload.use_1200bps_touch=true +adafruit_feather_esp32s3.upload.wait_for_upload_port=true + +adafruit_feather_esp32s3.serial.disableDTR=false +adafruit_feather_esp32s3.serial.disableRTS=false + +adafruit_feather_esp32s3.build.tarch=xtensa +adafruit_feather_esp32s3.build.bootloader_addr=0x0 +adafruit_feather_esp32s3.build.target=esp32s3 +adafruit_feather_esp32s3.build.mcu=esp32s3 +adafruit_feather_esp32s3.build.core=esp32 +adafruit_feather_esp32s3.build.variant=adafruit_feather_esp32s3 +adafruit_feather_esp32s3.build.board=ADAFRUIT_FEATHER_ESP32S3 + +adafruit_feather_esp32s3.build.usb_mode=0 +adafruit_feather_esp32s3.build.cdc_on_boot=1 +adafruit_feather_esp32s3.build.msc_on_boot=0 +adafruit_feather_esp32s3.build.dfu_on_boot=0 +adafruit_feather_esp32s3.build.f_cpu=240000000L +adafruit_feather_esp32s3.build.flash_size=4MB +adafruit_feather_esp32s3.build.flash_freq=80m +adafruit_feather_esp32s3.build.flash_mode=dio +adafruit_feather_esp32s3.build.boot=qio +adafruit_feather_esp32s3.build.partitions=default +adafruit_feather_esp32s3.build.defines= +adafruit_feather_esp32s3.build.loop_core= +adafruit_feather_esp32s3.build.event_core= +adafruit_feather_esp32s3.build.flash_type=qio +adafruit_feather_esp32s3.build.psram_type=qspi +adafruit_feather_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_feather_esp32s3.menu.LoopCore.1=Core 1 +adafruit_feather_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_feather_esp32s3.menu.LoopCore.0=Core 0 +adafruit_feather_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_feather_esp32s3.menu.EventsCore.1=Core 1 +adafruit_feather_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_feather_esp32s3.menu.EventsCore.0=Core 0 +adafruit_feather_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_feather_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_feather_esp32s3.menu.USBMode.default.build.usb_mode=0 +adafruit_feather_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_feather_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_feather_esp32s3.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s3.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s3.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s3.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_feather_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_feather_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +adafruit_feather_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_feather_esp32s3.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s3.menu.PSRAM.disabled.build.defines= +adafruit_feather_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_feather_esp32s3.menu.PSRAM.opi=OPI PSRAM +adafruit_feather_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s3.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s3.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s3.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s3.menu.FlashMode.qio=QIO 80MHz +adafruit_feather_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s3.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.qio120=QIO 120MHz +adafruit_feather_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_feather_esp32s3.menu.FlashMode.qio120.build.boot=qio +adafruit_feather_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_feather_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.dio=DIO 80MHz +adafruit_feather_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s3.menu.FlashMode.dio.build.boot=dio +adafruit_feather_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.opi=OPI 80MHz +adafruit_feather_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +adafruit_feather_esp32s3.menu.FlashMode.opi.build.boot=opi +adafruit_feather_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +adafruit_feather_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_feather_esp32s3.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s3.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s3.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s3.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s3.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s3.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s3.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s3.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s3.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s3.menu.DebugLevel.none=None +adafruit_feather_esp32s3.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s3.menu.DebugLevel.error=Error +adafruit_feather_esp32s3.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s3.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s3.menu.DebugLevel.info=Info +adafruit_feather_esp32s3.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s3.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s3.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s3.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s3.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s3.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S3 No PSRAM + +adafruit_feather_esp32s3_nopsram.name=Adafruit Feather ESP32-S3 No PSRAM +adafruit_feather_esp32s3_nopsram.vid.0=0x239A +adafruit_feather_esp32s3_nopsram.pid.0=0x8113 +adafruit_feather_esp32s3_nopsram.vid.1=0x239A +adafruit_feather_esp32s3_nopsram.pid.1=0x0113 +adafruit_feather_esp32s3_nopsram.vid.2=0x239A +adafruit_feather_esp32s3_nopsram.pid.2=0x8114 +adafruit_feather_esp32s3_nopsram.upload_port.0.vid=0x239A +adafruit_feather_esp32s3_nopsram.upload_port.0.pid=0x8113 +adafruit_feather_esp32s3_nopsram.upload_port.1.vid=0x239A +adafruit_feather_esp32s3_nopsram.upload_port.1.pid=0x0113 +adafruit_feather_esp32s3_nopsram.upload_port.2.vid=0x239A +adafruit_feather_esp32s3_nopsram.upload_port.2.pid=0x8114 + +adafruit_feather_esp32s3_nopsram.bootloader.tool=esptool_py +adafruit_feather_esp32s3_nopsram.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s3_nopsram.upload.tool=esptool_py +adafruit_feather_esp32s3_nopsram.upload.tool.default=esptool_py +adafruit_feather_esp32s3_nopsram.upload.tool.network=esp_ota + +adafruit_feather_esp32s3_nopsram.upload.maximum_size=1310720 +adafruit_feather_esp32s3_nopsram.upload.maximum_data_size=327680 +adafruit_feather_esp32s3_nopsram.upload.flags= +adafruit_feather_esp32s3_nopsram.upload.extra_flags= +adafruit_feather_esp32s3_nopsram.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_nopsram.upload.wait_for_upload_port=true + +adafruit_feather_esp32s3_nopsram.serial.disableDTR=false +adafruit_feather_esp32s3_nopsram.serial.disableRTS=false + +adafruit_feather_esp32s3_nopsram.build.tarch=xtensa +adafruit_feather_esp32s3_nopsram.build.bootloader_addr=0x0 +adafruit_feather_esp32s3_nopsram.build.target=esp32s3 +adafruit_feather_esp32s3_nopsram.build.mcu=esp32s3 +adafruit_feather_esp32s3_nopsram.build.core=esp32 +adafruit_feather_esp32s3_nopsram.build.variant=adafruit_feather_esp32s3_nopsram +adafruit_feather_esp32s3_nopsram.build.board=ADAFRUIT_FEATHER_ESP32S3_NOPSRAM + +adafruit_feather_esp32s3_nopsram.build.usb_mode=0 +adafruit_feather_esp32s3_nopsram.build.cdc_on_boot=1 +adafruit_feather_esp32s3_nopsram.build.msc_on_boot=0 +adafruit_feather_esp32s3_nopsram.build.dfu_on_boot=0 +adafruit_feather_esp32s3_nopsram.build.f_cpu=240000000L +adafruit_feather_esp32s3_nopsram.build.flash_size=8MB +adafruit_feather_esp32s3_nopsram.build.flash_freq=80m +adafruit_feather_esp32s3_nopsram.build.flash_mode=dio +adafruit_feather_esp32s3_nopsram.build.boot=qio +adafruit_feather_esp32s3_nopsram.build.partitions=default +adafruit_feather_esp32s3_nopsram.build.defines= +adafruit_feather_esp32s3_nopsram.build.loop_core= +adafruit_feather_esp32s3_nopsram.build.event_core= +adafruit_feather_esp32s3_nopsram.build.flash_type=qio +adafruit_feather_esp32s3_nopsram.build.psram_type=qspi +adafruit_feather_esp32s3_nopsram.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_feather_esp32s3_nopsram.menu.LoopCore.1=Core 1 +adafruit_feather_esp32s3_nopsram.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_feather_esp32s3_nopsram.menu.LoopCore.0=Core 0 +adafruit_feather_esp32s3_nopsram.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_feather_esp32s3_nopsram.menu.EventsCore.1=Core 1 +adafruit_feather_esp32s3_nopsram.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_feather_esp32s3_nopsram.menu.EventsCore.0=Core 0 +adafruit_feather_esp32s3_nopsram.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_feather_esp32s3_nopsram.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_feather_esp32s3_nopsram.menu.USBMode.default.build.usb_mode=0 +adafruit_feather_esp32s3_nopsram.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_feather_esp32s3_nopsram.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s3_nopsram.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_feather_esp32s3_nopsram.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s3_nopsram.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS) +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS) +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s3_nopsram.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio=QIO 80MHz +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.boot_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.flash_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120=QIO 120MHz +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.boot=qio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio=DIO 80MHz +adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.boot=dio +adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.boot_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.flash_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi=OPI 80MHz +adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.flash_mode=dout +adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.boot=opi +adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.boot_freq=80m +adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_feather_esp32s3_nopsram.menu.FlashSize.8M=8MB (64Mb) +adafruit_feather_esp32s3_nopsram.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.none=None +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.error=Error +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.info=Info +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s3_nopsram.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s3_nopsram.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s3_nopsram.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s3_nopsram.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s3_nopsram.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S3 TFT + +adafruit_feather_esp32s3_tft.name=Adafruit Feather ESP32-S3 TFT +adafruit_feather_esp32s3_tft.vid.0=0x239A +adafruit_feather_esp32s3_tft.pid.0=0x811D +adafruit_feather_esp32s3_tft.vid.1=0x239A +adafruit_feather_esp32s3_tft.pid.1=0x011D +adafruit_feather_esp32s3_tft.vid.2=0x239A +adafruit_feather_esp32s3_tft.pid.2=0x811E +adafruit_feather_esp32s3_tft.upload_port.0.vid=0x239A +adafruit_feather_esp32s3_tft.upload_port.0.pid=0x811D +adafruit_feather_esp32s3_tft.upload_port.1.vid=0x239A +adafruit_feather_esp32s3_tft.upload_port.1.pid=0x011D +adafruit_feather_esp32s3_tft.upload_port.2.vid=0x239A +adafruit_feather_esp32s3_tft.upload_port.2.pid=0x811E + +adafruit_feather_esp32s3_tft.bootloader.tool=esptool_py +adafruit_feather_esp32s3_tft.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s3_tft.upload.tool=esptool_py +adafruit_feather_esp32s3_tft.upload.tool.default=esptool_py +adafruit_feather_esp32s3_tft.upload.tool.network=esp_ota + +adafruit_feather_esp32s3_tft.upload.maximum_size=1310720 +adafruit_feather_esp32s3_tft.upload.maximum_data_size=327680 +adafruit_feather_esp32s3_tft.upload.flags= +adafruit_feather_esp32s3_tft.upload.extra_flags= +adafruit_feather_esp32s3_tft.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_tft.upload.wait_for_upload_port=true + +adafruit_feather_esp32s3_tft.serial.disableDTR=false +adafruit_feather_esp32s3_tft.serial.disableRTS=false + +adafruit_feather_esp32s3_tft.build.tarch=xtensa +adafruit_feather_esp32s3_tft.build.bootloader_addr=0x0 +adafruit_feather_esp32s3_tft.build.target=esp32s3 +adafruit_feather_esp32s3_tft.build.mcu=esp32s3 +adafruit_feather_esp32s3_tft.build.core=esp32 +adafruit_feather_esp32s3_tft.build.variant=adafruit_feather_esp32s3_tft +adafruit_feather_esp32s3_tft.build.board=ADAFRUIT_FEATHER_ESP32S3_TFT + +adafruit_feather_esp32s3_tft.build.usb_mode=0 +adafruit_feather_esp32s3_tft.build.cdc_on_boot=1 +adafruit_feather_esp32s3_tft.build.msc_on_boot=0 +adafruit_feather_esp32s3_tft.build.dfu_on_boot=0 +adafruit_feather_esp32s3_tft.build.f_cpu=240000000L +adafruit_feather_esp32s3_tft.build.flash_size=4MB +adafruit_feather_esp32s3_tft.build.flash_freq=80m +adafruit_feather_esp32s3_tft.build.flash_mode=dio +adafruit_feather_esp32s3_tft.build.boot=qio +adafruit_feather_esp32s3_tft.build.partitions=default +adafruit_feather_esp32s3_tft.build.defines= +adafruit_feather_esp32s3_tft.build.loop_core= +adafruit_feather_esp32s3_tft.build.event_core= +adafruit_feather_esp32s3_tft.build.flash_type=qio +adafruit_feather_esp32s3_tft.build.psram_type=qspi +adafruit_feather_esp32s3_tft.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_feather_esp32s3_tft.menu.LoopCore.1=Core 1 +adafruit_feather_esp32s3_tft.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_feather_esp32s3_tft.menu.LoopCore.0=Core 0 +adafruit_feather_esp32s3_tft.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_feather_esp32s3_tft.menu.EventsCore.1=Core 1 +adafruit_feather_esp32s3_tft.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_feather_esp32s3_tft.menu.EventsCore.0=Core 0 +adafruit_feather_esp32s3_tft.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_feather_esp32s3_tft.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_feather_esp32s3_tft.menu.USBMode.default.build.usb_mode=0 +adafruit_feather_esp32s3_tft.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_feather_esp32s3_tft.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_feather_esp32s3_tft.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s3_tft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s3_tft.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s3_tft.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s3_tft.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s3_tft.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s3_tft.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_tft.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s3_tft.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s3_tft.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s3_tft.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_tft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s3_tft.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_feather_esp32s3_tft.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_tft.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s3_tft.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_feather_esp32s3_tft.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s3_tft.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s3_tft.menu.PSRAM.enabled=QSPI PSRAM +adafruit_feather_esp32s3_tft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3_tft.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_feather_esp32s3_tft.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s3_tft.menu.PSRAM.disabled.build.defines= +adafruit_feather_esp32s3_tft.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_feather_esp32s3_tft.menu.PSRAM.opi=OPI PSRAM +adafruit_feather_esp32s3_tft.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3_tft.menu.PSRAM.opi.build.psram_type=opi + +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_tft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s3_tft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s3_tft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s3_tft.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s3_tft.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s3_tft.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s3_tft.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s3_tft.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s3_tft.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s3_tft.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s3_tft.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s3_tft.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s3_tft.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s3_tft.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s3_tft.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s3_tft.menu.FlashMode.qio=QIO 80MHz +adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.boot_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.flash_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.qio120=QIO 120MHz +adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.boot=qio +adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.dio=DIO 80MHz +adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.boot=dio +adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.boot_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.flash_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.opi=OPI 80MHz +adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.flash_mode=dout +adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.boot=opi +adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.boot_freq=80m +adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_feather_esp32s3_tft.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s3_tft.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s3_tft.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s3_tft.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s3_tft.menu.DebugLevel.none=None +adafruit_feather_esp32s3_tft.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s3_tft.menu.DebugLevel.error=Error +adafruit_feather_esp32s3_tft.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s3_tft.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s3_tft.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s3_tft.menu.DebugLevel.info=Info +adafruit_feather_esp32s3_tft.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s3_tft.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s3_tft.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s3_tft.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s3_tft.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s3_tft.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s3_tft.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s3_tft.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s3_tft.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Feather ESP32-S3 Reverse TFT + +adafruit_feather_esp32s3_reversetft.name=Adafruit Feather ESP32-S3 Reverse TFT +adafruit_feather_esp32s3_reversetft.vid.0=0x239A +adafruit_feather_esp32s3_reversetft.pid.0=0x8123 +adafruit_feather_esp32s3_reversetft.vid.1=0x239A +adafruit_feather_esp32s3_reversetft.pid.1=0x0123 +adafruit_feather_esp32s3_reversetft.vid.2=0x239A +adafruit_feather_esp32s3_reversetft.pid.2=0x8124 +adafruit_feather_esp32s3_reversetft.upload_port.0.vid=0x239A +adafruit_feather_esp32s3_reversetft.upload_port.0.pid=0x8123 +adafruit_feather_esp32s3_reversetft.upload_port.1.vid=0x239A +adafruit_feather_esp32s3_reversetft.upload_port.1.pid=0x0123 +adafruit_feather_esp32s3_reversetft.upload_port.2.vid=0x239A +adafruit_feather_esp32s3_reversetft.upload_port.2.pid=0x8124 + +adafruit_feather_esp32s3_reversetft.bootloader.tool=esptool_py +adafruit_feather_esp32s3_reversetft.bootloader.tool.default=esptool_py + +adafruit_feather_esp32s3_reversetft.upload.tool=esptool_py +adafruit_feather_esp32s3_reversetft.upload.tool.default=esptool_py +adafruit_feather_esp32s3_reversetft.upload.tool.network=esp_ota + +adafruit_feather_esp32s3_reversetft.upload.maximum_size=1310720 +adafruit_feather_esp32s3_reversetft.upload.maximum_data_size=327680 +adafruit_feather_esp32s3_reversetft.upload.flags= +adafruit_feather_esp32s3_reversetft.upload.extra_flags= +adafruit_feather_esp32s3_reversetft.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_reversetft.upload.wait_for_upload_port=true + +adafruit_feather_esp32s3_reversetft.serial.disableDTR=false +adafruit_feather_esp32s3_reversetft.serial.disableRTS=false + +adafruit_feather_esp32s3_reversetft.build.tarch=xtensa +adafruit_feather_esp32s3_reversetft.build.bootloader_addr=0x0 +adafruit_feather_esp32s3_reversetft.build.target=esp32s3 +adafruit_feather_esp32s3_reversetft.build.mcu=esp32s3 +adafruit_feather_esp32s3_reversetft.build.core=esp32 +adafruit_feather_esp32s3_reversetft.build.variant=adafruit_feather_esp32s3_reversetft +adafruit_feather_esp32s3_reversetft.build.board=ADAFRUIT_FEATHER_ESP32S3_REVTFT + +adafruit_feather_esp32s3_reversetft.build.usb_mode=0 +adafruit_feather_esp32s3_reversetft.build.cdc_on_boot=1 +adafruit_feather_esp32s3_reversetft.build.msc_on_boot=0 +adafruit_feather_esp32s3_reversetft.build.dfu_on_boot=0 +adafruit_feather_esp32s3_reversetft.build.f_cpu=240000000L +adafruit_feather_esp32s3_reversetft.build.flash_size=4MB +adafruit_feather_esp32s3_reversetft.build.flash_freq=80m +adafruit_feather_esp32s3_reversetft.build.flash_mode=dio +adafruit_feather_esp32s3_reversetft.build.boot=qio +adafruit_feather_esp32s3_reversetft.build.partitions=default +adafruit_feather_esp32s3_reversetft.build.defines= +adafruit_feather_esp32s3_reversetft.build.loop_core= +adafruit_feather_esp32s3_reversetft.build.event_core= +adafruit_feather_esp32s3_reversetft.build.flash_type=qio +adafruit_feather_esp32s3_reversetft.build.psram_type=qspi +adafruit_feather_esp32s3_reversetft.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_feather_esp32s3_reversetft.menu.LoopCore.1=Core 1 +adafruit_feather_esp32s3_reversetft.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_feather_esp32s3_reversetft.menu.LoopCore.0=Core 0 +adafruit_feather_esp32s3_reversetft.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_feather_esp32s3_reversetft.menu.EventsCore.1=Core 1 +adafruit_feather_esp32s3_reversetft.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_feather_esp32s3_reversetft.menu.EventsCore.0=Core 0 +adafruit_feather_esp32s3_reversetft.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_feather_esp32s3_reversetft.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_feather_esp32s3_reversetft.menu.USBMode.default.build.usb_mode=0 +adafruit_feather_esp32s3_reversetft.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_feather_esp32s3_reversetft.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.default=Disabled +adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.default=Disabled +adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_feather_esp32s3_reversetft.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_feather_esp32s3_reversetft.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_feather_esp32s3_reversetft.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled=QSPI PSRAM +adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled=Disabled +adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled.build.defines= +adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi=OPI PSRAM +adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi.build.psram_type=opi + +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.240=240MHz (WiFi) +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.40=40MHz +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.20=20MHz +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.10=10MHz +adafruit_feather_esp32s3_reversetft.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio=QIO 80MHz +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.boot_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.flash_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120=QIO 120MHz +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.boot=qio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio=DIO 80MHz +adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.boot=dio +adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.boot_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.flash_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi=OPI 80MHz +adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.flash_mode=dout +adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.boot=opi +adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.boot_freq=80m +adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_feather_esp32s3_reversetft.menu.FlashSize.4M=4MB (32Mb) +adafruit_feather_esp32s3_reversetft.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.none=None +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.error=Error +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.warn=Warn +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.info=Info +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.debug=Debug +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32s3_reversetft.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32s3_reversetft.menu.EraseFlash.none=Disabled +adafruit_feather_esp32s3_reversetft.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32s3_reversetft.menu.EraseFlash.all=Enabled +adafruit_feather_esp32s3_reversetft.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################# +# Feather C6 + + +adafruit_feather_esp32c6.name=Adafruit Feather ESP32-C6 + +adafruit_feather_esp32c6.bootloader.tool=esptool_py +adafruit_feather_esp32c6.bootloader.tool.default=esptool_py + +adafruit_feather_esp32c6.upload.tool=esptool_py +adafruit_feather_esp32c6.upload.tool.default=esptool_py +adafruit_feather_esp32c6.upload.tool.network=esp_ota + +adafruit_feather_esp32c6.upload.maximum_size=1310720 +adafruit_feather_esp32c6.upload.maximum_data_size=327680 +adafruit_feather_esp32c6.upload.flags= +adafruit_feather_esp32c6.upload.extra_flags= +adafruit_feather_esp32c6.upload.use_1200bps_touch=false +adafruit_feather_esp32c6.upload.wait_for_upload_port=false + +adafruit_feather_esp32c6.serial.disableDTR=false +adafruit_feather_esp32c6.serial.disableRTS=false + +adafruit_feather_esp32c6.build.tarch=riscv32 +adafruit_feather_esp32c6.build.target=esp +adafruit_feather_esp32c6.build.mcu=esp32c6 +adafruit_feather_esp32c6.build.core=esp32 +adafruit_feather_esp32c6.build.variant=adafruit_feather_esp32c6 +adafruit_feather_esp32c6.build.board=ADAFRUIT_FEATHER_ESP32C6 +adafruit_feather_esp32c6.build.bootloader_addr=0x0 + +adafruit_feather_esp32c6.build.cdc_on_boot=0 +adafruit_feather_esp32c6.build.f_cpu=160000000L +adafruit_feather_esp32c6.build.flash_size=4MB +adafruit_feather_esp32c6.build.flash_freq=80m +adafruit_feather_esp32c6.build.flash_mode=qio +adafruit_feather_esp32c6.build.boot=qio +adafruit_feather_esp32c6.build.partitions=default +adafruit_feather_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +adafruit_feather_esp32c6.menu.JTAGAdapter.default=Disabled +adafruit_feather_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +adafruit_feather_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +adafruit_feather_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +adafruit_feather_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +adafruit_feather_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +adafruit_feather_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +adafruit_feather_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +adafruit_feather_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +adafruit_feather_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +adafruit_feather_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +adafruit_feather_esp32c6.menu.CDCOnBoot.default=Disabled +adafruit_feather_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +adafruit_feather_esp32c6.menu.CDCOnBoot.cdc=Enabled +adafruit_feather_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +adafruit_feather_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.default.build.partitions=default +adafruit_feather_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_feather_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_feather_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_feather_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_feather_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_feather_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_feather_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +adafruit_feather_esp32c6.menu.PartitionScheme.custom=Custom +adafruit_feather_esp32c6.menu.PartitionScheme.custom.build.partitions= +adafruit_feather_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +adafruit_feather_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +adafruit_feather_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_feather_esp32c6.menu.CPUFreq.120=120MHz (WiFi) +adafruit_feather_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L +adafruit_feather_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +adafruit_feather_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_feather_esp32c6.menu.CPUFreq.40=40MHz +adafruit_feather_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_feather_esp32c6.menu.CPUFreq.20=20MHz +adafruit_feather_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_feather_esp32c6.menu.CPUFreq.10=10MHz +adafruit_feather_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_feather_esp32c6.menu.FlashMode.qio=QIO +adafruit_feather_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +adafruit_feather_esp32c6.menu.FlashMode.qio.build.boot=qio +adafruit_feather_esp32c6.menu.FlashMode.dio=DIO +adafruit_feather_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +adafruit_feather_esp32c6.menu.FlashMode.dio.build.boot=dio + +adafruit_feather_esp32c6.menu.FlashFreq.80=80MHz +adafruit_feather_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +adafruit_feather_esp32c6.menu.FlashFreq.40=40MHz +adafruit_feather_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_feather_esp32c6.menu.UploadSpeed.921600=921600 +adafruit_feather_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_feather_esp32c6.menu.UploadSpeed.115200=115200 +adafruit_feather_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_feather_esp32c6.menu.UploadSpeed.256000.windows=256000 +adafruit_feather_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_feather_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_feather_esp32c6.menu.UploadSpeed.230400=230400 +adafruit_feather_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_feather_esp32c6.menu.UploadSpeed.460800.linux=460800 +adafruit_feather_esp32c6.menu.UploadSpeed.460800.macosx=460800 +adafruit_feather_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_feather_esp32c6.menu.UploadSpeed.512000.windows=512000 +adafruit_feather_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_feather_esp32c6.menu.DebugLevel.none=None +adafruit_feather_esp32c6.menu.DebugLevel.none.build.code_debug=0 +adafruit_feather_esp32c6.menu.DebugLevel.error=Error +adafruit_feather_esp32c6.menu.DebugLevel.error.build.code_debug=1 +adafruit_feather_esp32c6.menu.DebugLevel.warn=Warn +adafruit_feather_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +adafruit_feather_esp32c6.menu.DebugLevel.info=Info +adafruit_feather_esp32c6.menu.DebugLevel.info.build.code_debug=3 +adafruit_feather_esp32c6.menu.DebugLevel.debug=Debug +adafruit_feather_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +adafruit_feather_esp32c6.menu.DebugLevel.verbose=Verbose +adafruit_feather_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_feather_esp32c6.menu.EraseFlash.none=Disabled +adafruit_feather_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +adafruit_feather_esp32c6.menu.EraseFlash.all=Enabled +adafruit_feather_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_feather_esp32c6.menu.ZigbeeMode.default=Disabled +adafruit_feather_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_feather_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_feather_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +adafruit_feather_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +adafruit_feather_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +adafruit_feather_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_feather_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_feather_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## +# Adafruit QT Py ESP32 + +adafruit_qtpy_esp32_pico.name=Adafruit QT Py ESP32 + +adafruit_qtpy_esp32_pico.bootloader.tool=esptool_py +adafruit_qtpy_esp32_pico.bootloader.tool.default=esptool_py + +adafruit_qtpy_esp32_pico.upload.tool=esptool_py +adafruit_qtpy_esp32_pico.upload.tool.default=esptool_py +adafruit_qtpy_esp32_pico.upload.tool.network=esp_ota + +adafruit_qtpy_esp32_pico.upload.maximum_size=1310720 +adafruit_qtpy_esp32_pico.upload.maximum_data_size=327680 +adafruit_qtpy_esp32_pico.upload.flags= +adafruit_qtpy_esp32_pico.upload.extra_flags= + +adafruit_qtpy_esp32_pico.serial.disableDTR=true +adafruit_qtpy_esp32_pico.serial.disableRTS=true + +adafruit_qtpy_esp32_pico.build.tarch=xtensa +adafruit_qtpy_esp32_pico.build.bootloader_addr=0x1000 +adafruit_qtpy_esp32_pico.build.target=esp32 +adafruit_qtpy_esp32_pico.build.mcu=esp32 +adafruit_qtpy_esp32_pico.build.core=esp32 +adafruit_qtpy_esp32_pico.build.variant=adafruit_qtpy_esp32 +adafruit_qtpy_esp32_pico.build.board=ADAFRUIT_QTPY_ESP32_PICO + +adafruit_qtpy_esp32_pico.build.f_cpu=240000000L +adafruit_qtpy_esp32_pico.build.flash_size=8MB +adafruit_qtpy_esp32_pico.build.flash_freq=80m +adafruit_qtpy_esp32_pico.build.flash_mode=dio +adafruit_qtpy_esp32_pico.build.boot=dio +adafruit_qtpy_esp32_pico.build.partitions=default +adafruit_qtpy_esp32_pico.build.defines= +adafruit_qtpy_esp32_pico.build.loop_core= +adafruit_qtpy_esp32_pico.build.event_core= + +adafruit_qtpy_esp32_pico.menu.LoopCore.1=Core 1 +adafruit_qtpy_esp32_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_qtpy_esp32_pico.menu.LoopCore.0=Core 0 +adafruit_qtpy_esp32_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_qtpy_esp32_pico.menu.EventsCore.1=Core 1 +adafruit_qtpy_esp32_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_qtpy_esp32_pico.menu.EventsCore.0=Core 0 +adafruit_qtpy_esp32_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_qtpy_esp32_pico.menu.PSRAM.enabled=Enabled +adafruit_qtpy_esp32_pico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +adafruit_qtpy_esp32_pico.menu.PSRAM.disabled=Disabled +adafruit_qtpy_esp32_pico.menu.PSRAM.disabled.build.defines= + +adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP / 5.3MB SPIFFS) +adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB +adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720 + +adafruit_qtpy_esp32_pico.menu.CPUFreq.240=240MHz (WiFi/BT) +adafruit_qtpy_esp32_pico.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_qtpy_esp32_pico.menu.CPUFreq.160=160MHz (WiFi/BT) +adafruit_qtpy_esp32_pico.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qtpy_esp32_pico.menu.CPUFreq.80=80MHz (WiFi/BT) +adafruit_qtpy_esp32_pico.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qtpy_esp32_pico.menu.CPUFreq.40=40MHz +adafruit_qtpy_esp32_pico.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qtpy_esp32_pico.menu.CPUFreq.20=20MHz +adafruit_qtpy_esp32_pico.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qtpy_esp32_pico.menu.CPUFreq.10=10MHz +adafruit_qtpy_esp32_pico.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qtpy_esp32_pico.menu.FlashFreq.80=80MHz +adafruit_qtpy_esp32_pico.menu.FlashFreq.80.build.flash_freq=80m +adafruit_qtpy_esp32_pico.menu.FlashFreq.40=40MHz +adafruit_qtpy_esp32_pico.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_qtpy_esp32_pico.menu.FlashSize.8M=8MB (64Mb) +adafruit_qtpy_esp32_pico.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_qtpy_esp32_pico.menu.UploadSpeed.921600=921600 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.115200=115200 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.256000.windows=256000 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400=230400 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.linux=460800 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.macosx=460800 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.512000.windows=512000 +adafruit_qtpy_esp32_pico.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qtpy_esp32_pico.menu.DebugLevel.none=None +adafruit_qtpy_esp32_pico.menu.DebugLevel.none.build.code_debug=0 +adafruit_qtpy_esp32_pico.menu.DebugLevel.error=Error +adafruit_qtpy_esp32_pico.menu.DebugLevel.error.build.code_debug=1 +adafruit_qtpy_esp32_pico.menu.DebugLevel.warn=Warn +adafruit_qtpy_esp32_pico.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qtpy_esp32_pico.menu.DebugLevel.info=Info +adafruit_qtpy_esp32_pico.menu.DebugLevel.info.build.code_debug=3 +adafruit_qtpy_esp32_pico.menu.DebugLevel.debug=Debug +adafruit_qtpy_esp32_pico.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qtpy_esp32_pico.menu.DebugLevel.verbose=Verbose +adafruit_qtpy_esp32_pico.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qtpy_esp32_pico.menu.EraseFlash.none=Disabled +adafruit_qtpy_esp32_pico.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qtpy_esp32_pico.menu.EraseFlash.all=Enabled +adafruit_qtpy_esp32_pico.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default=Disabled +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit QT Py ESP32-C3 + +adafruit_qtpy_esp32c3.name=Adafruit QT Py ESP32-C3 + +adafruit_qtpy_esp32c3.bootloader.tool=esptool_py +adafruit_qtpy_esp32c3.bootloader.tool.default=esptool_py + +adafruit_qtpy_esp32c3.upload.tool=esptool_py +adafruit_qtpy_esp32c3.upload.tool.default=esptool_py +adafruit_qtpy_esp32c3.upload.tool.network=esp_ota + +adafruit_qtpy_esp32c3.upload.maximum_size=1310720 +adafruit_qtpy_esp32c3.upload.maximum_data_size=327680 +adafruit_qtpy_esp32c3.upload.flags= +adafruit_qtpy_esp32c3.upload.extra_flags= +adafruit_qtpy_esp32c3.upload.use_1200bps_touch=false +adafruit_qtpy_esp32c3.upload.wait_for_upload_port=false + +adafruit_qtpy_esp32c3.serial.disableDTR=false +adafruit_qtpy_esp32c3.serial.disableRTS=false + +adafruit_qtpy_esp32c3.build.tarch=riscv32 +adafruit_qtpy_esp32c3.build.bootloader_addr=0x0 +adafruit_qtpy_esp32c3.build.target=esp +adafruit_qtpy_esp32c3.build.mcu=esp32c3 +adafruit_qtpy_esp32c3.build.core=esp32 +adafruit_qtpy_esp32c3.build.variant=adafruit_qtpy_esp32c3 +adafruit_qtpy_esp32c3.build.board=ADAFRUIT_QTPY_ESP32C3 + +adafruit_qtpy_esp32c3.build.cdc_on_boot=1 +adafruit_qtpy_esp32c3.build.f_cpu=160000000L +adafruit_qtpy_esp32c3.build.flash_size=4MB +adafruit_qtpy_esp32c3.build.flash_freq=80m +adafruit_qtpy_esp32c3.build.flash_mode=dio +adafruit_qtpy_esp32c3.build.boot=qio +adafruit_qtpy_esp32c3.build.partitions=default +adafruit_qtpy_esp32c3.build.defines= + +adafruit_qtpy_esp32c3.menu.CDCOnBoot.cdc=Enabled +adafruit_qtpy_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_qtpy_esp32c3.menu.CDCOnBoot.default=Disabled +adafruit_qtpy_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_qtpy_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.default.build.partitions=default +adafruit_qtpy_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_qtpy_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_qtpy_esp32c3.menu.CPUFreq.160=160MHz (WiFi) +adafruit_qtpy_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qtpy_esp32c3.menu.CPUFreq.80=80MHz (WiFi) +adafruit_qtpy_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qtpy_esp32c3.menu.CPUFreq.40=40MHz +adafruit_qtpy_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qtpy_esp32c3.menu.CPUFreq.20=20MHz +adafruit_qtpy_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qtpy_esp32c3.menu.CPUFreq.10=10MHz +adafruit_qtpy_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qtpy_esp32c3.menu.FlashMode.qio=QIO +adafruit_qtpy_esp32c3.menu.FlashMode.qio.build.flash_mode=dio +adafruit_qtpy_esp32c3.menu.FlashMode.qio.build.boot=qio +adafruit_qtpy_esp32c3.menu.FlashMode.dio=DIO +adafruit_qtpy_esp32c3.menu.FlashMode.dio.build.flash_mode=dio +adafruit_qtpy_esp32c3.menu.FlashMode.dio.build.boot=dio + +adafruit_qtpy_esp32c3.menu.FlashFreq.80=80MHz +adafruit_qtpy_esp32c3.menu.FlashFreq.80.build.flash_freq=80m +adafruit_qtpy_esp32c3.menu.FlashFreq.40=40MHz +adafruit_qtpy_esp32c3.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_qtpy_esp32c3.menu.FlashSize.4M=4MB (32Mb) +adafruit_qtpy_esp32c3.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_qtpy_esp32c3.menu.UploadSpeed.921600=921600 +adafruit_qtpy_esp32c3.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qtpy_esp32c3.menu.UploadSpeed.115200=115200 +adafruit_qtpy_esp32c3.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qtpy_esp32c3.menu.UploadSpeed.256000.windows=256000 +adafruit_qtpy_esp32c3.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qtpy_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qtpy_esp32c3.menu.UploadSpeed.230400=230400 +adafruit_qtpy_esp32c3.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.linux=460800 +adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.macosx=460800 +adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qtpy_esp32c3.menu.UploadSpeed.512000.windows=512000 +adafruit_qtpy_esp32c3.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qtpy_esp32c3.menu.DebugLevel.none=None +adafruit_qtpy_esp32c3.menu.DebugLevel.none.build.code_debug=0 +adafruit_qtpy_esp32c3.menu.DebugLevel.error=Error +adafruit_qtpy_esp32c3.menu.DebugLevel.error.build.code_debug=1 +adafruit_qtpy_esp32c3.menu.DebugLevel.warn=Warn +adafruit_qtpy_esp32c3.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qtpy_esp32c3.menu.DebugLevel.info=Info +adafruit_qtpy_esp32c3.menu.DebugLevel.info.build.code_debug=3 +adafruit_qtpy_esp32c3.menu.DebugLevel.debug=Debug +adafruit_qtpy_esp32c3.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qtpy_esp32c3.menu.DebugLevel.verbose=Verbose +adafruit_qtpy_esp32c3.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qtpy_esp32c3.menu.EraseFlash.none=Disabled +adafruit_qtpy_esp32c3.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qtpy_esp32c3.menu.EraseFlash.all=Enabled +adafruit_qtpy_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qtpy_esp32c3.menu.ZigbeeMode.default=Disabled +adafruit_qtpy_esp32c3.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qtpy_esp32c3.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit QT Py ESP32-S2 + +adafruit_qtpy_esp32s2.name=Adafruit QT Py ESP32-S2 +adafruit_qtpy_esp32s2.vid.0=0x239A +adafruit_qtpy_esp32s2.pid.0=0x8111 +adafruit_qtpy_esp32s2.vid.1=0x239A +adafruit_qtpy_esp32s2.pid.1=0x0111 +adafruit_qtpy_esp32s2.vid.2=0x239A +adafruit_qtpy_esp32s2.pid.2=0x8112 +adafruit_qtpy_esp32s2.upload_port.0.vid=0x239A +adafruit_qtpy_esp32s2.upload_port.0.pid=0x8111 +adafruit_qtpy_esp32s2.upload_port.1.vid=0x239A +adafruit_qtpy_esp32s2.upload_port.1.pid=0x0111 +adafruit_qtpy_esp32s2.upload_port.2.vid=0x239A +adafruit_qtpy_esp32s2.upload_port.2.pid=0x8112 + +adafruit_qtpy_esp32s2.bootloader.tool=esptool_py +adafruit_qtpy_esp32s2.bootloader.tool.default=esptool_py + +adafruit_qtpy_esp32s2.upload.tool=esptool_py +adafruit_qtpy_esp32s2.upload.tool.default=esptool_py +adafruit_qtpy_esp32s2.upload.tool.network=esp_ota + +adafruit_qtpy_esp32s2.upload.maximum_size=1310720 +adafruit_qtpy_esp32s2.upload.maximum_data_size=327680 +adafruit_qtpy_esp32s2.upload.flags= +adafruit_qtpy_esp32s2.upload.extra_flags= +adafruit_qtpy_esp32s2.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s2.upload.wait_for_upload_port=true + +adafruit_qtpy_esp32s2.serial.disableDTR=false +adafruit_qtpy_esp32s2.serial.disableRTS=false + +adafruit_qtpy_esp32s2.build.tarch=xtensa +adafruit_qtpy_esp32s2.build.bootloader_addr=0x1000 +adafruit_qtpy_esp32s2.build.target=esp32s2 +adafruit_qtpy_esp32s2.build.mcu=esp32s2 +adafruit_qtpy_esp32s2.build.core=esp32 +adafruit_qtpy_esp32s2.build.variant=adafruit_qtpy_esp32s2 +adafruit_qtpy_esp32s2.build.board=ADAFRUIT_QTPY_ESP32S2 + +adafruit_qtpy_esp32s2.build.cdc_on_boot=1 +adafruit_qtpy_esp32s2.build.msc_on_boot=0 +adafruit_qtpy_esp32s2.build.dfu_on_boot=0 +adafruit_qtpy_esp32s2.build.f_cpu=240000000L +adafruit_qtpy_esp32s2.build.flash_size=4MB +adafruit_qtpy_esp32s2.build.flash_freq=80m +adafruit_qtpy_esp32s2.build.flash_mode=dio +adafruit_qtpy_esp32s2.build.boot=qio +adafruit_qtpy_esp32s2.build.partitions=default +adafruit_qtpy_esp32s2.build.defines= + +adafruit_qtpy_esp32s2.menu.CDCOnBoot.cdc=Enabled +adafruit_qtpy_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_qtpy_esp32s2.menu.CDCOnBoot.default=Disabled +adafruit_qtpy_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_qtpy_esp32s2.menu.MSCOnBoot.default=Disabled +adafruit_qtpy_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_qtpy_esp32s2.menu.MSCOnBoot.msc=Enabled +adafruit_qtpy_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_qtpy_esp32s2.menu.DFUOnBoot.default=Disabled +adafruit_qtpy_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_qtpy_esp32s2.menu.DFUOnBoot.dfu=Enabled +adafruit_qtpy_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_qtpy_esp32s2.menu.UploadMode.cdc=Internal USB +adafruit_qtpy_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_qtpy_esp32s2.menu.UploadMode.default=UART0 +adafruit_qtpy_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_qtpy_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_qtpy_esp32s2.menu.PSRAM.enabled=Enabled +adafruit_qtpy_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_qtpy_esp32s2.menu.PSRAM.disabled=Disabled +adafruit_qtpy_esp32s2.menu.PSRAM.disabled.build.defines= + +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.default.build.partitions=default +adafruit_qtpy_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_qtpy_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_qtpy_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_qtpy_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_qtpy_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_qtpy_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qtpy_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_qtpy_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qtpy_esp32s2.menu.CPUFreq.40=40MHz +adafruit_qtpy_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qtpy_esp32s2.menu.CPUFreq.20=20MHz +adafruit_qtpy_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qtpy_esp32s2.menu.CPUFreq.10=10MHz +adafruit_qtpy_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qtpy_esp32s2.menu.FlashMode.qio=QIO +adafruit_qtpy_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_qtpy_esp32s2.menu.FlashMode.qio.build.boot=qio +adafruit_qtpy_esp32s2.menu.FlashMode.dio=DIO +adafruit_qtpy_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_qtpy_esp32s2.menu.FlashMode.dio.build.boot=dio + +adafruit_qtpy_esp32s2.menu.FlashFreq.80=80MHz +adafruit_qtpy_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +adafruit_qtpy_esp32s2.menu.FlashFreq.40=40MHz +adafruit_qtpy_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_qtpy_esp32s2.menu.FlashSize.4M=4MB (32Mb) +adafruit_qtpy_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_qtpy_esp32s2.menu.UploadSpeed.921600=921600 +adafruit_qtpy_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qtpy_esp32s2.menu.UploadSpeed.115200=115200 +adafruit_qtpy_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qtpy_esp32s2.menu.UploadSpeed.256000.windows=256000 +adafruit_qtpy_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qtpy_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qtpy_esp32s2.menu.UploadSpeed.230400=230400 +adafruit_qtpy_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.linux=460800 +adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.macosx=460800 +adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qtpy_esp32s2.menu.UploadSpeed.512000.windows=512000 +adafruit_qtpy_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qtpy_esp32s2.menu.DebugLevel.none=None +adafruit_qtpy_esp32s2.menu.DebugLevel.none.build.code_debug=0 +adafruit_qtpy_esp32s2.menu.DebugLevel.error=Error +adafruit_qtpy_esp32s2.menu.DebugLevel.error.build.code_debug=1 +adafruit_qtpy_esp32s2.menu.DebugLevel.warn=Warn +adafruit_qtpy_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qtpy_esp32s2.menu.DebugLevel.info=Info +adafruit_qtpy_esp32s2.menu.DebugLevel.info.build.code_debug=3 +adafruit_qtpy_esp32s2.menu.DebugLevel.debug=Debug +adafruit_qtpy_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qtpy_esp32s2.menu.DebugLevel.verbose=Verbose +adafruit_qtpy_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qtpy_esp32s2.menu.EraseFlash.none=Disabled +adafruit_qtpy_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qtpy_esp32s2.menu.EraseFlash.all=Enabled +adafruit_qtpy_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qtpy_esp32s2.menu.ZigbeeMode.default=Disabled +adafruit_qtpy_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qtpy_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit QT Py ESP32-S3 No PSRAM + +adafruit_qtpy_esp32s3_nopsram.name=Adafruit QT Py ESP32-S3 No PSRAM +adafruit_qtpy_esp32s3_nopsram.vid.0=0x239A +adafruit_qtpy_esp32s3_nopsram.pid.0=0x8119 +adafruit_qtpy_esp32s3_nopsram.vid.1=0x239A +adafruit_qtpy_esp32s3_nopsram.pid.1=0x0119 +adafruit_qtpy_esp32s3_nopsram.vid.2=0x239A +adafruit_qtpy_esp32s3_nopsram.pid.2=0x811A +adafruit_qtpy_esp32s3_nopsram.upload_port.0.vid=0x239A +adafruit_qtpy_esp32s3_nopsram.upload_port.0.pid=0x8119 +adafruit_qtpy_esp32s3_nopsram.upload_port.1.vid=0x239A +adafruit_qtpy_esp32s3_nopsram.upload_port.1.pid=0x0119 +adafruit_qtpy_esp32s3_nopsram.upload_port.2.vid=0x239A +adafruit_qtpy_esp32s3_nopsram.upload_port.2.pid=0x811A + +adafruit_qtpy_esp32s3_nopsram.bootloader.tool=esptool_py +adafruit_qtpy_esp32s3_nopsram.bootloader.tool.default=esptool_py + +adafruit_qtpy_esp32s3_nopsram.upload.tool=esptool_py +adafruit_qtpy_esp32s3_nopsram.upload.tool.default=esptool_py +adafruit_qtpy_esp32s3_nopsram.upload.tool.network=esp_ota + +adafruit_qtpy_esp32s3_nopsram.upload.maximum_size=1310720 +adafruit_qtpy_esp32s3_nopsram.upload.maximum_data_size=327680 +adafruit_qtpy_esp32s3_nopsram.upload.flags= +adafruit_qtpy_esp32s3_nopsram.upload.extra_flags= +adafruit_qtpy_esp32s3_nopsram.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s3_nopsram.upload.wait_for_upload_port=true + +adafruit_qtpy_esp32s3_nopsram.serial.disableDTR=false +adafruit_qtpy_esp32s3_nopsram.serial.disableRTS=false + +adafruit_qtpy_esp32s3_nopsram.build.tarch=xtensa +adafruit_qtpy_esp32s3_nopsram.build.bootloader_addr=0x0 +adafruit_qtpy_esp32s3_nopsram.build.target=esp32s3 +adafruit_qtpy_esp32s3_nopsram.build.mcu=esp32s3 +adafruit_qtpy_esp32s3_nopsram.build.core=esp32 +adafruit_qtpy_esp32s3_nopsram.build.variant=adafruit_qtpy_esp32s3_nopsram +adafruit_qtpy_esp32s3_nopsram.build.board=ADAFRUIT_QTPY_ESP32S3_NOPSRAM + +adafruit_qtpy_esp32s3_nopsram.build.usb_mode=0 +adafruit_qtpy_esp32s3_nopsram.build.cdc_on_boot=1 +adafruit_qtpy_esp32s3_nopsram.build.msc_on_boot=0 +adafruit_qtpy_esp32s3_nopsram.build.dfu_on_boot=0 +adafruit_qtpy_esp32s3_nopsram.build.f_cpu=240000000L +adafruit_qtpy_esp32s3_nopsram.build.flash_size=8MB +adafruit_qtpy_esp32s3_nopsram.build.flash_freq=80m +adafruit_qtpy_esp32s3_nopsram.build.flash_mode=dio +adafruit_qtpy_esp32s3_nopsram.build.boot=qio +adafruit_qtpy_esp32s3_nopsram.build.partitions=default +adafruit_qtpy_esp32s3_nopsram.build.defines= +adafruit_qtpy_esp32s3_nopsram.build.loop_core= +adafruit_qtpy_esp32s3_nopsram.build.event_core= +adafruit_qtpy_esp32s3_nopsram.build.flash_type=qio +adafruit_qtpy_esp32s3_nopsram.build.psram_type=qspi +adafruit_qtpy_esp32s3_nopsram.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.1=Core 1 +adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.0=Core 0 +adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.1=Core 1 +adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.0=Core 0 +adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_qtpy_esp32s3_nopsram.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_qtpy_esp32s3_nopsram.menu.USBMode.default.build.usb_mode=0 +adafruit_qtpy_esp32s3_nopsram.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_qtpy_esp32s3_nopsram.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.cdc=Enabled +adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.default=Disabled +adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.default=Disabled +adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.default=Disabled +adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS) +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS) +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.240=240MHz (WiFi) +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.160=160MHz (WiFi) +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.80=80MHz (WiFi) +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.40=40MHz +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.20=20MHz +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.10=10MHz +adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio=QIO 80MHz +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.flash_mode=dio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.boot=qio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.boot_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.flash_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120=QIO 120MHz +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.boot=qio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio=DIO 80MHz +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.flash_mode=dio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.boot=dio +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.boot_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.flash_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi=OPI 80MHz +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.flash_mode=dout +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.boot=opi +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.boot_freq=80m +adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_qtpy_esp32s3_nopsram.menu.FlashSize.8M=8MB (64Mb) +adafruit_qtpy_esp32s3_nopsram.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.921600=921600 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.115200=115200 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.256000.windows=256000 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400=230400 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.linux=460800 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.macosx=460800 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.512000.windows=512000 +adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.none=None +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.none.build.code_debug=0 +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.error=Error +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.error.build.code_debug=1 +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.warn=Warn +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.info=Info +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.info.build.code_debug=3 +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.debug=Debug +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.verbose=Verbose +adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.none=Disabled +adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.all=Enabled +adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default=Disabled +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit QT Py ESP32-S3 (4M Flash 2M PSRAM) + +adafruit_qtpy_esp32s3_n4r2.name=Adafruit QT Py ESP32-S3 (4M Flash 2M PSRAM) +adafruit_qtpy_esp32s3_n4r2.vid.0=0x239A +adafruit_qtpy_esp32s3_n4r2.pid.0=0x8143 +adafruit_qtpy_esp32s3_n4r2.vid.1=0x239A +adafruit_qtpy_esp32s3_n4r2.pid.1=0x0143 +adafruit_qtpy_esp32s3_n4r2.vid.2=0x239A +adafruit_qtpy_esp32s3_n4r2.pid.2=0x8144 +adafruit_qtpy_esp32s3_n4r2.upload_port.0.vid=0x239A +adafruit_qtpy_esp32s3_n4r2.upload_port.0.pid=0x8143 +adafruit_qtpy_esp32s3_n4r2.upload_port.1.vid=0x239A +adafruit_qtpy_esp32s3_n4r2.upload_port.1.pid=0x0143 +adafruit_qtpy_esp32s3_n4r2.upload_port.2.vid=0x239A +adafruit_qtpy_esp32s3_n4r2.upload_port.2.pid=0x8144 + +adafruit_qtpy_esp32s3_n4r2.bootloader.tool=esptool_py +adafruit_qtpy_esp32s3_n4r2.bootloader.tool.default=esptool_py + +adafruit_qtpy_esp32s3_n4r2.upload.tool=esptool_py +adafruit_qtpy_esp32s3_n4r2.upload.tool.default=esptool_py +adafruit_qtpy_esp32s3_n4r2.upload.tool.network=esp_ota + +adafruit_qtpy_esp32s3_n4r2.upload.maximum_size=1310720 +adafruit_qtpy_esp32s3_n4r2.upload.maximum_data_size=327680 +adafruit_qtpy_esp32s3_n4r2.upload.flags= +adafruit_qtpy_esp32s3_n4r2.upload.extra_flags= +adafruit_qtpy_esp32s3_n4r2.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s3_n4r2.upload.wait_for_upload_port=true + +adafruit_qtpy_esp32s3_n4r2.serial.disableDTR=false +adafruit_qtpy_esp32s3_n4r2.serial.disableRTS=false + +adafruit_qtpy_esp32s3_n4r2.build.tarch=xtensa +adafruit_qtpy_esp32s3_n4r2.build.bootloader_addr=0x0 +adafruit_qtpy_esp32s3_n4r2.build.target=esp32s3 +adafruit_qtpy_esp32s3_n4r2.build.mcu=esp32s3 +adafruit_qtpy_esp32s3_n4r2.build.core=esp32 +adafruit_qtpy_esp32s3_n4r2.build.variant=adafruit_qtpy_esp32s3_n4r2 +adafruit_qtpy_esp32s3_n4r2.build.board=ADAFRUIT_QTPY_ESP32S3_N4R2 + +adafruit_qtpy_esp32s3_n4r2.build.usb_mode=0 +adafruit_qtpy_esp32s3_n4r2.build.cdc_on_boot=1 +adafruit_qtpy_esp32s3_n4r2.build.msc_on_boot=0 +adafruit_qtpy_esp32s3_n4r2.build.dfu_on_boot=0 +adafruit_qtpy_esp32s3_n4r2.build.f_cpu=240000000L +adafruit_qtpy_esp32s3_n4r2.build.flash_size=4MB +adafruit_qtpy_esp32s3_n4r2.build.flash_freq=80m +adafruit_qtpy_esp32s3_n4r2.build.flash_mode=dio +adafruit_qtpy_esp32s3_n4r2.build.boot=qio +adafruit_qtpy_esp32s3_n4r2.build.partitions=default +adafruit_qtpy_esp32s3_n4r2.build.defines= +adafruit_qtpy_esp32s3_n4r2.build.loop_core= +adafruit_qtpy_esp32s3_n4r2.build.event_core= +adafruit_qtpy_esp32s3_n4r2.build.flash_type=qio +adafruit_qtpy_esp32s3_n4r2.build.psram_type=qspi +adafruit_qtpy_esp32s3_n4r2.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.1=Core 1 +adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.0=Core 0 +adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.1=Core 1 +adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.0=Core 0 +adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_qtpy_esp32s3_n4r2.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_qtpy_esp32s3_n4r2.menu.USBMode.default.build.usb_mode=0 +adafruit_qtpy_esp32s3_n4r2.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_qtpy_esp32s3_n4r2.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.cdc=Enabled +adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.default=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.default=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.default=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled=QSPI PSRAM +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled.build.defines= +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi=OPI PSRAM +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi.build.psram_type=opi + +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.default.build.partitions=default +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.240=240MHz (WiFi) +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.160=160MHz (WiFi) +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.80=80MHz (WiFi) +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.40=40MHz +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.20=20MHz +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.10=10MHz +adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio=QIO 80MHz +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.flash_mode=dio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.boot=qio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.boot_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.flash_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120=QIO 120MHz +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.boot=qio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio=DIO 80MHz +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.flash_mode=dio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.boot=dio +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.boot_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.flash_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi=OPI 80MHz +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.flash_mode=dout +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.boot=opi +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.boot_freq=80m +adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_qtpy_esp32s3_n4r2.menu.FlashSize.4M=4MB (32Mb) +adafruit_qtpy_esp32s3_n4r2.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.921600=921600 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.115200=115200 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.256000.windows=256000 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400=230400 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.linux=460800 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.macosx=460800 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.512000.windows=512000 +adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.none=None +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.none.build.code_debug=0 +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.error=Error +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.error.build.code_debug=1 +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.warn=Warn +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.info=Info +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.info.build.code_debug=3 +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.debug=Debug +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.verbose=Verbose +adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.none=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.all=Enabled +adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default=Disabled +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit ItsyBitsy ESP32 + +adafruit_itsybitsy_esp32.name=Adafruit ItsyBitsy ESP32 + +adafruit_itsybitsy_esp32.bootloader.tool=esptool_py +adafruit_itsybitsy_esp32.bootloader.tool.default=esptool_py + +adafruit_itsybitsy_esp32.upload.tool=esptool_py +adafruit_itsybitsy_esp32.upload.tool.default=esptool_py +adafruit_itsybitsy_esp32.upload.tool.network=esp_ota + +adafruit_itsybitsy_esp32.upload.maximum_size=1310720 +adafruit_itsybitsy_esp32.upload.maximum_data_size=327680 +adafruit_itsybitsy_esp32.upload.flags= +adafruit_itsybitsy_esp32.upload.extra_flags= + +adafruit_itsybitsy_esp32.serial.disableDTR=true +adafruit_itsybitsy_esp32.serial.disableRTS=true + +adafruit_itsybitsy_esp32.build.tarch=xtensa +adafruit_itsybitsy_esp32.build.bootloader_addr=0x1000 +adafruit_itsybitsy_esp32.build.target=esp32 +adafruit_itsybitsy_esp32.build.mcu=esp32 +adafruit_itsybitsy_esp32.build.core=esp32 +adafruit_itsybitsy_esp32.build.variant=adafruit_itsybitsy_esp32 +adafruit_itsybitsy_esp32.build.board=ADAFRUIT_ITSYBITSY_ESP32 + +adafruit_itsybitsy_esp32.build.f_cpu=240000000L +adafruit_itsybitsy_esp32.build.flash_size=8MB +adafruit_itsybitsy_esp32.build.flash_freq=80m +adafruit_itsybitsy_esp32.build.flash_mode=dio +adafruit_itsybitsy_esp32.build.boot=dio +adafruit_itsybitsy_esp32.build.partitions=default +adafruit_itsybitsy_esp32.build.defines= +adafruit_itsybitsy_esp32.build.loop_core= +adafruit_itsybitsy_esp32.build.event_core= + +adafruit_itsybitsy_esp32.menu.LoopCore.1=Core 1 +adafruit_itsybitsy_esp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_itsybitsy_esp32.menu.LoopCore.0=Core 0 +adafruit_itsybitsy_esp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_itsybitsy_esp32.menu.EventsCore.1=Core 1 +adafruit_itsybitsy_esp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_itsybitsy_esp32.menu.EventsCore.0=Core 0 +adafruit_itsybitsy_esp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_itsybitsy_esp32.menu.PSRAM.enabled=Enabled +adafruit_itsybitsy_esp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +adafruit_itsybitsy_esp32.menu.PSRAM.disabled=Disabled +adafruit_itsybitsy_esp32.menu.PSRAM.disabled.build.defines= + +adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +adafruit_itsybitsy_esp32.menu.CPUFreq.240=240MHz (WiFi/BT) +adafruit_itsybitsy_esp32.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_itsybitsy_esp32.menu.CPUFreq.160=160MHz (WiFi/BT) +adafruit_itsybitsy_esp32.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_itsybitsy_esp32.menu.CPUFreq.80=80MHz (WiFi/BT) +adafruit_itsybitsy_esp32.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_itsybitsy_esp32.menu.CPUFreq.40=40MHz +adafruit_itsybitsy_esp32.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_itsybitsy_esp32.menu.CPUFreq.20=20MHz +adafruit_itsybitsy_esp32.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_itsybitsy_esp32.menu.CPUFreq.10=10MHz +adafruit_itsybitsy_esp32.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_itsybitsy_esp32.menu.FlashFreq.80=80MHz +adafruit_itsybitsy_esp32.menu.FlashFreq.80.build.flash_freq=80m +adafruit_itsybitsy_esp32.menu.FlashFreq.40=40MHz +adafruit_itsybitsy_esp32.menu.FlashFreq.40.build.flash_freq=40m + +adafruit_itsybitsy_esp32.menu.FlashSize.8M=8MB (64Mb) +adafruit_itsybitsy_esp32.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_itsybitsy_esp32.menu.UploadSpeed.921600=921600 +adafruit_itsybitsy_esp32.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_itsybitsy_esp32.menu.UploadSpeed.115200=115200 +adafruit_itsybitsy_esp32.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_itsybitsy_esp32.menu.UploadSpeed.256000.windows=256000 +adafruit_itsybitsy_esp32.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_itsybitsy_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_itsybitsy_esp32.menu.UploadSpeed.230400=230400 +adafruit_itsybitsy_esp32.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.linux=460800 +adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.macosx=460800 +adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_itsybitsy_esp32.menu.UploadSpeed.512000.windows=512000 +adafruit_itsybitsy_esp32.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_itsybitsy_esp32.menu.DebugLevel.none=None +adafruit_itsybitsy_esp32.menu.DebugLevel.none.build.code_debug=0 +adafruit_itsybitsy_esp32.menu.DebugLevel.error=Error +adafruit_itsybitsy_esp32.menu.DebugLevel.error.build.code_debug=1 +adafruit_itsybitsy_esp32.menu.DebugLevel.warn=Warn +adafruit_itsybitsy_esp32.menu.DebugLevel.warn.build.code_debug=2 +adafruit_itsybitsy_esp32.menu.DebugLevel.info=Info +adafruit_itsybitsy_esp32.menu.DebugLevel.info.build.code_debug=3 +adafruit_itsybitsy_esp32.menu.DebugLevel.debug=Debug +adafruit_itsybitsy_esp32.menu.DebugLevel.debug.build.code_debug=4 +adafruit_itsybitsy_esp32.menu.DebugLevel.verbose=Verbose +adafruit_itsybitsy_esp32.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_itsybitsy_esp32.menu.EraseFlash.none=Disabled +adafruit_itsybitsy_esp32.menu.EraseFlash.none.upload.erase_cmd= +adafruit_itsybitsy_esp32.menu.EraseFlash.all=Enabled +adafruit_itsybitsy_esp32.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_itsybitsy_esp32.menu.ZigbeeMode.default=Disabled +adafruit_itsybitsy_esp32.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_itsybitsy_esp32.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit MatrixPortal ESP32-S3 + +adafruit_matrixportal_esp32s3.name=Adafruit MatrixPortal ESP32-S3 +adafruit_matrixportal_esp32s3.vid.0=0x239A +adafruit_matrixportal_esp32s3.pid.0=0x8125 +adafruit_matrixportal_esp32s3.vid.1=0x239A +adafruit_matrixportal_esp32s3.pid.1=0x0125 +adafruit_matrixportal_esp32s3.vid.2=0x239A +adafruit_matrixportal_esp32s3.pid.2=0x8126 +adafruit_matrixportal_esp32s3.upload_port.0.vid=0x239A +adafruit_matrixportal_esp32s3.upload_port.0.pid=0x8125 +adafruit_matrixportal_esp32s3.upload_port.1.vid=0x239A +adafruit_matrixportal_esp32s3.upload_port.1.pid=0x0125 +adafruit_matrixportal_esp32s3.upload_port.2.vid=0x239A +adafruit_matrixportal_esp32s3.upload_port.2.pid=0x8126 + +adafruit_matrixportal_esp32s3.bootloader.tool=esptool_py +adafruit_matrixportal_esp32s3.bootloader.tool.default=esptool_py + +adafruit_matrixportal_esp32s3.upload.tool=esptool_py +adafruit_matrixportal_esp32s3.upload.tool.default=esptool_py +adafruit_matrixportal_esp32s3.upload.tool.network=esp_ota + +adafruit_matrixportal_esp32s3.upload.maximum_size=1310720 +adafruit_matrixportal_esp32s3.upload.maximum_data_size=327680 +adafruit_matrixportal_esp32s3.upload.flags= +adafruit_matrixportal_esp32s3.upload.extra_flags= +adafruit_matrixportal_esp32s3.upload.use_1200bps_touch=true +adafruit_matrixportal_esp32s3.upload.wait_for_upload_port=true + +adafruit_matrixportal_esp32s3.serial.disableDTR=false +adafruit_matrixportal_esp32s3.serial.disableRTS=false + +adafruit_matrixportal_esp32s3.build.tarch=xtensa +adafruit_matrixportal_esp32s3.build.bootloader_addr=0x0 +adafruit_matrixportal_esp32s3.build.target=esp32s3 +adafruit_matrixportal_esp32s3.build.mcu=esp32s3 +adafruit_matrixportal_esp32s3.build.core=esp32 +adafruit_matrixportal_esp32s3.build.variant=adafruit_matrixportal_esp32s3 +adafruit_matrixportal_esp32s3.build.board=ADAFRUIT_MATRIXPORTAL_ESP32S3 + +adafruit_matrixportal_esp32s3.build.usb_mode=0 +adafruit_matrixportal_esp32s3.build.cdc_on_boot=1 +adafruit_matrixportal_esp32s3.build.msc_on_boot=0 +adafruit_matrixportal_esp32s3.build.dfu_on_boot=0 +adafruit_matrixportal_esp32s3.build.f_cpu=240000000L +adafruit_matrixportal_esp32s3.build.flash_size=8MB +adafruit_matrixportal_esp32s3.build.flash_freq=80m +adafruit_matrixportal_esp32s3.build.flash_mode=dio +adafruit_matrixportal_esp32s3.build.boot=qio +adafruit_matrixportal_esp32s3.build.partitions=default +adafruit_matrixportal_esp32s3.build.defines= +adafruit_matrixportal_esp32s3.build.loop_core= +adafruit_matrixportal_esp32s3.build.event_core= +adafruit_matrixportal_esp32s3.build.flash_type=qio +adafruit_matrixportal_esp32s3.build.psram_type=qspi +adafruit_matrixportal_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_matrixportal_esp32s3.menu.LoopCore.1=Core 1 +adafruit_matrixportal_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_matrixportal_esp32s3.menu.LoopCore.0=Core 0 +adafruit_matrixportal_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_matrixportal_esp32s3.menu.EventsCore.1=Core 1 +adafruit_matrixportal_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_matrixportal_esp32s3.menu.EventsCore.0=Core 0 +adafruit_matrixportal_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_matrixportal_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_matrixportal_esp32s3.menu.USBMode.default.build.usb_mode=0 +adafruit_matrixportal_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_matrixportal_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_matrixportal_esp32s3.menu.CDCOnBoot.cdc=Enabled +adafruit_matrixportal_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_matrixportal_esp32s3.menu.CDCOnBoot.default=Disabled +adafruit_matrixportal_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_matrixportal_esp32s3.menu.MSCOnBoot.default=Disabled +adafruit_matrixportal_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_matrixportal_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_matrixportal_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_matrixportal_esp32s3.menu.DFUOnBoot.default=Disabled +adafruit_matrixportal_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_matrixportal_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_matrixportal_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_matrixportal_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_matrixportal_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_matrixportal_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_matrixportal_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_matrixportal_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_matrixportal_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_matrixportal_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +adafruit_matrixportal_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_matrixportal_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_matrixportal_esp32s3.menu.PSRAM.disabled=Disabled +adafruit_matrixportal_esp32s3.menu.PSRAM.disabled.build.defines= +adafruit_matrixportal_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_matrixportal_esp32s3.menu.PSRAM.opi=OPI PSRAM +adafruit_matrixportal_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_matrixportal_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS) +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS) +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +adafruit_matrixportal_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +adafruit_matrixportal_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_matrixportal_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +adafruit_matrixportal_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_matrixportal_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +adafruit_matrixportal_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_matrixportal_esp32s3.menu.CPUFreq.40=40MHz +adafruit_matrixportal_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_matrixportal_esp32s3.menu.CPUFreq.20=20MHz +adafruit_matrixportal_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_matrixportal_esp32s3.menu.CPUFreq.10=10MHz +adafruit_matrixportal_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_matrixportal_esp32s3.menu.FlashMode.qio=QIO 80MHz +adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.boot=qio +adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.qio120=QIO 120MHz +adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.boot=qio +adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.dio=DIO 80MHz +adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.boot=dio +adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.opi=OPI 80MHz +adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.boot=opi +adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_matrixportal_esp32s3.menu.FlashSize.8M=8MB (64Mb) +adafruit_matrixportal_esp32s3.menu.FlashSize.8M.build.flash_size=8MB + +adafruit_matrixportal_esp32s3.menu.UploadSpeed.921600=921600 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.115200=115200 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.256000.windows=256000 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400=230400 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.linux=460800 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.macosx=460800 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.512000.windows=512000 +adafruit_matrixportal_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_matrixportal_esp32s3.menu.DebugLevel.none=None +adafruit_matrixportal_esp32s3.menu.DebugLevel.none.build.code_debug=0 +adafruit_matrixportal_esp32s3.menu.DebugLevel.error=Error +adafruit_matrixportal_esp32s3.menu.DebugLevel.error.build.code_debug=1 +adafruit_matrixportal_esp32s3.menu.DebugLevel.warn=Warn +adafruit_matrixportal_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +adafruit_matrixportal_esp32s3.menu.DebugLevel.info=Info +adafruit_matrixportal_esp32s3.menu.DebugLevel.info.build.code_debug=3 +adafruit_matrixportal_esp32s3.menu.DebugLevel.debug=Debug +adafruit_matrixportal_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +adafruit_matrixportal_esp32s3.menu.DebugLevel.verbose=Verbose +adafruit_matrixportal_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_matrixportal_esp32s3.menu.EraseFlash.none=Disabled +adafruit_matrixportal_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +adafruit_matrixportal_esp32s3.menu.EraseFlash.all=Enabled +adafruit_matrixportal_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default=Disabled +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit pyCamera S3 + +adafruit_camera_esp32s3.name=Adafruit pyCamera S3 +adafruit_camera_esp32s3.vid.0=0x239A +adafruit_camera_esp32s3.pid.0=0x0117 +adafruit_camera_esp32s3.vid.1=0x239A +adafruit_camera_esp32s3.pid.1=0x8117 +adafruit_camera_esp32s3.vid.2=0x239A +adafruit_camera_esp32s3.pid.2=0x8118 +adafruit_camera_esp32s3.upload_port.0.vid=0x239A +adafruit_camera_esp32s3.upload_port.0.pid=0x0117 +adafruit_camera_esp32s3.upload_port.1.vid=0x239A +adafruit_camera_esp32s3.upload_port.1.pid=0x8117 +adafruit_camera_esp32s3.upload_port.2.vid=0x239A +adafruit_camera_esp32s3.upload_port.2.pid=0x8118 + +adafruit_camera_esp32s3.bootloader.tool=esptool_py +adafruit_camera_esp32s3.bootloader.tool.default=esptool_py + +adafruit_camera_esp32s3.upload.tool=esptool_py +adafruit_camera_esp32s3.upload.tool.default=esptool_py +adafruit_camera_esp32s3.upload.tool.network=esp_ota + +adafruit_camera_esp32s3.upload.maximum_size=1310720 +adafruit_camera_esp32s3.upload.maximum_data_size=327680 +adafruit_camera_esp32s3.upload.flags= +adafruit_camera_esp32s3.upload.extra_flags= +adafruit_camera_esp32s3.upload.use_1200bps_touch=true +adafruit_camera_esp32s3.upload.wait_for_upload_port=true + +adafruit_camera_esp32s3.serial.disableDTR=false +adafruit_camera_esp32s3.serial.disableRTS=false + +adafruit_camera_esp32s3.build.tarch=xtensa +adafruit_camera_esp32s3.build.bootloader_addr=0x0 +adafruit_camera_esp32s3.build.target=esp32s3 +adafruit_camera_esp32s3.build.mcu=esp32s3 +adafruit_camera_esp32s3.build.core=esp32 +adafruit_camera_esp32s3.build.variant=adafruit_camera_esp32s3 +adafruit_camera_esp32s3.build.board=ADAFRUIT_CAMERA_ESP32S3 + +adafruit_camera_esp32s3.build.usb_mode=0 +adafruit_camera_esp32s3.build.cdc_on_boot=1 +adafruit_camera_esp32s3.build.msc_on_boot=0 +adafruit_camera_esp32s3.build.dfu_on_boot=0 +adafruit_camera_esp32s3.build.f_cpu=240000000L +adafruit_camera_esp32s3.build.flash_size=4MB +adafruit_camera_esp32s3.build.flash_freq=80m +adafruit_camera_esp32s3.build.flash_mode=dio +adafruit_camera_esp32s3.build.boot=qio +adafruit_camera_esp32s3.build.partitions=default +adafruit_camera_esp32s3.build.defines= +adafruit_camera_esp32s3.build.loop_core= +adafruit_camera_esp32s3.build.event_core= +adafruit_camera_esp32s3.build.flash_type=qio +adafruit_camera_esp32s3.build.psram_type=qspi +adafruit_camera_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_camera_esp32s3.menu.LoopCore.1=Core 1 +adafruit_camera_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_camera_esp32s3.menu.LoopCore.0=Core 0 +adafruit_camera_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_camera_esp32s3.menu.EventsCore.1=Core 1 +adafruit_camera_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_camera_esp32s3.menu.EventsCore.0=Core 0 +adafruit_camera_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_camera_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_camera_esp32s3.menu.USBMode.default.build.usb_mode=0 +adafruit_camera_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_camera_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_camera_esp32s3.menu.CDCOnBoot.cdc=Enabled +adafruit_camera_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_camera_esp32s3.menu.CDCOnBoot.default=Disabled +adafruit_camera_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_camera_esp32s3.menu.MSCOnBoot.default=Disabled +adafruit_camera_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_camera_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_camera_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_camera_esp32s3.menu.DFUOnBoot.default=Disabled +adafruit_camera_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_camera_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_camera_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_camera_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_camera_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_camera_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_camera_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_camera_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_camera_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_camera_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +adafruit_camera_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +adafruit_camera_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +adafruit_camera_esp32s3.menu.PSRAM.disabled=Disabled +adafruit_camera_esp32s3.menu.PSRAM.disabled.build.defines= +adafruit_camera_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +adafruit_camera_esp32s3.menu.PSRAM.opi=OPI PSRAM +adafruit_camera_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_camera_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_camera_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.default.build.partitions=default +adafruit_camera_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +adafruit_camera_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +adafruit_camera_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +adafruit_camera_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +adafruit_camera_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +adafruit_camera_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +adafruit_camera_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +adafruit_camera_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +adafruit_camera_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_camera_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +adafruit_camera_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_camera_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +adafruit_camera_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_camera_esp32s3.menu.CPUFreq.40=40MHz +adafruit_camera_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_camera_esp32s3.menu.CPUFreq.20=20MHz +adafruit_camera_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_camera_esp32s3.menu.CPUFreq.10=10MHz +adafruit_camera_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_camera_esp32s3.menu.FlashMode.qio=QIO 80MHz +adafruit_camera_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +adafruit_camera_esp32s3.menu.FlashMode.qio.build.boot=qio +adafruit_camera_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.qio120=QIO 120MHz +adafruit_camera_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_camera_esp32s3.menu.FlashMode.qio120.build.boot=qio +adafruit_camera_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_camera_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.dio=DIO 80MHz +adafruit_camera_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +adafruit_camera_esp32s3.menu.FlashMode.dio.build.boot=dio +adafruit_camera_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.opi=OPI 80MHz +adafruit_camera_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +adafruit_camera_esp32s3.menu.FlashMode.opi.build.boot=opi +adafruit_camera_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +adafruit_camera_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_camera_esp32s3.menu.FlashSize.4M=4MB (32Mb) +adafruit_camera_esp32s3.menu.FlashSize.4M.build.flash_size=4MB + +adafruit_camera_esp32s3.menu.UploadSpeed.921600=921600 +adafruit_camera_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_camera_esp32s3.menu.UploadSpeed.115200=115200 +adafruit_camera_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_camera_esp32s3.menu.UploadSpeed.256000.windows=256000 +adafruit_camera_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_camera_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_camera_esp32s3.menu.UploadSpeed.230400=230400 +adafruit_camera_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_camera_esp32s3.menu.UploadSpeed.460800.linux=460800 +adafruit_camera_esp32s3.menu.UploadSpeed.460800.macosx=460800 +adafruit_camera_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_camera_esp32s3.menu.UploadSpeed.512000.windows=512000 +adafruit_camera_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_camera_esp32s3.menu.DebugLevel.none=None +adafruit_camera_esp32s3.menu.DebugLevel.none.build.code_debug=0 +adafruit_camera_esp32s3.menu.DebugLevel.error=Error +adafruit_camera_esp32s3.menu.DebugLevel.error.build.code_debug=1 +adafruit_camera_esp32s3.menu.DebugLevel.warn=Warn +adafruit_camera_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +adafruit_camera_esp32s3.menu.DebugLevel.info=Info +adafruit_camera_esp32s3.menu.DebugLevel.info.build.code_debug=3 +adafruit_camera_esp32s3.menu.DebugLevel.debug=Debug +adafruit_camera_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +adafruit_camera_esp32s3.menu.DebugLevel.verbose=Verbose +adafruit_camera_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_camera_esp32s3.menu.EraseFlash.none=Disabled +adafruit_camera_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +adafruit_camera_esp32s3.menu.EraseFlash.all=Enabled +adafruit_camera_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_camera_esp32s3.menu.ZigbeeMode.default=Disabled +adafruit_camera_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_camera_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_camera_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_camera_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_camera_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Qualia ESP32-S3 RGB666 + +adafruit_qualia_s3_rgb666.name=Adafruit Qualia ESP32-S3 RGB666 +adafruit_qualia_s3_rgb666.vid.0=0x239A +adafruit_qualia_s3_rgb666.pid.0=0x8147 +adafruit_qualia_s3_rgb666.vid.1=0x239A +adafruit_qualia_s3_rgb666.pid.1=0x0147 +adafruit_qualia_s3_rgb666.vid.2=0x239A +adafruit_qualia_s3_rgb666.pid.2=0x8148 +adafruit_qualia_s3_rgb666.upload_port.0.vid=0x239A +adafruit_qualia_s3_rgb666.upload_port.0.pid=0x8147 +adafruit_qualia_s3_rgb666.upload_port.1.vid=0x239A +adafruit_qualia_s3_rgb666.upload_port.1.pid=0x0147 +adafruit_qualia_s3_rgb666.upload_port.2.vid=0x239A +adafruit_qualia_s3_rgb666.upload_port.2.pid=0x8148 + +adafruit_qualia_s3_rgb666.bootloader.tool=esptool_py +adafruit_qualia_s3_rgb666.bootloader.tool.default=esptool_py + +adafruit_qualia_s3_rgb666.upload.tool=esptool_py +adafruit_qualia_s3_rgb666.upload.tool.default=esptool_py +adafruit_qualia_s3_rgb666.upload.tool.network=esp_ota + +adafruit_qualia_s3_rgb666.upload.maximum_size=1310720 +adafruit_qualia_s3_rgb666.upload.maximum_data_size=327680 +adafruit_qualia_s3_rgb666.upload.flags= +adafruit_qualia_s3_rgb666.upload.extra_flags= +adafruit_qualia_s3_rgb666.upload.use_1200bps_touch=true +adafruit_qualia_s3_rgb666.upload.wait_for_upload_port=true + +adafruit_qualia_s3_rgb666.serial.disableDTR=false +adafruit_qualia_s3_rgb666.serial.disableRTS=false + +adafruit_qualia_s3_rgb666.build.tarch=xtensa +adafruit_qualia_s3_rgb666.build.bootloader_addr=0x0 +adafruit_qualia_s3_rgb666.build.target=esp32s3 +adafruit_qualia_s3_rgb666.build.mcu=esp32s3 +adafruit_qualia_s3_rgb666.build.core=esp32 +adafruit_qualia_s3_rgb666.build.variant=adafruit_qualia_s3_rgb666 +adafruit_qualia_s3_rgb666.build.board=QUALIA_S3_RGB666 + +adafruit_qualia_s3_rgb666.build.usb_mode=0 +adafruit_qualia_s3_rgb666.build.cdc_on_boot=1 +adafruit_qualia_s3_rgb666.build.msc_on_boot=0 +adafruit_qualia_s3_rgb666.build.dfu_on_boot=0 +adafruit_qualia_s3_rgb666.build.f_cpu=240000000L +adafruit_qualia_s3_rgb666.build.flash_size=16MB +adafruit_qualia_s3_rgb666.build.flash_freq=80m +adafruit_qualia_s3_rgb666.build.flash_mode=dio +adafruit_qualia_s3_rgb666.build.boot=qio +adafruit_qualia_s3_rgb666.build.partitions=default +adafruit_qualia_s3_rgb666.build.defines= +adafruit_qualia_s3_rgb666.build.loop_core= +adafruit_qualia_s3_rgb666.build.event_core= +adafruit_qualia_s3_rgb666.build.flash_type=qio +adafruit_qualia_s3_rgb666.build.psram_type=opi +adafruit_qualia_s3_rgb666.build.memory_type={build.flash_type}_{build.psram_type} + +adafruit_qualia_s3_rgb666.menu.LoopCore.1=Core 1 +adafruit_qualia_s3_rgb666.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +adafruit_qualia_s3_rgb666.menu.LoopCore.0=Core 0 +adafruit_qualia_s3_rgb666.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +adafruit_qualia_s3_rgb666.menu.EventsCore.1=Core 1 +adafruit_qualia_s3_rgb666.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +adafruit_qualia_s3_rgb666.menu.EventsCore.0=Core 0 +adafruit_qualia_s3_rgb666.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +adafruit_qualia_s3_rgb666.menu.USBMode.default=USB-OTG (TinyUSB) +adafruit_qualia_s3_rgb666.menu.USBMode.default.build.usb_mode=0 +adafruit_qualia_s3_rgb666.menu.USBMode.hwcdc=Hardware CDC and JTAG +adafruit_qualia_s3_rgb666.menu.USBMode.hwcdc.build.usb_mode=1 + +adafruit_qualia_s3_rgb666.menu.CDCOnBoot.cdc=Enabled +adafruit_qualia_s3_rgb666.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +adafruit_qualia_s3_rgb666.menu.CDCOnBoot.default=Disabled +adafruit_qualia_s3_rgb666.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +adafruit_qualia_s3_rgb666.menu.MSCOnBoot.default=Disabled +adafruit_qualia_s3_rgb666.menu.MSCOnBoot.default.build.msc_on_boot=0 +adafruit_qualia_s3_rgb666.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +adafruit_qualia_s3_rgb666.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +adafruit_qualia_s3_rgb666.menu.DFUOnBoot.default=Disabled +adafruit_qualia_s3_rgb666.menu.DFUOnBoot.default.build.dfu_on_boot=0 +adafruit_qualia_s3_rgb666.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +adafruit_qualia_s3_rgb666.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +adafruit_qualia_s3_rgb666.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +adafruit_qualia_s3_rgb666.menu.UploadMode.cdc.upload.use_1200bps_touch=true +adafruit_qualia_s3_rgb666.menu.UploadMode.cdc.upload.wait_for_upload_port=true +adafruit_qualia_s3_rgb666.menu.UploadMode.default=UART0 / Hardware CDC +adafruit_qualia_s3_rgb666.menu.UploadMode.default.upload.use_1200bps_touch=false +adafruit_qualia_s3_rgb666.menu.UploadMode.default.upload.wait_for_upload_port=false + +adafruit_qualia_s3_rgb666.menu.PSRAM.opi=OPI PSRAM +adafruit_qualia_s3_rgb666.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +adafruit_qualia_s3_rgb666.menu.PSRAM.opi.build.psram_type=opi +adafruit_qualia_s3_rgb666.menu.PSRAM.disabled=Disabled +adafruit_qualia_s3_rgb666.menu.PSRAM.disabled.build.defines= +adafruit_qualia_s3_rgb666.menu.PSRAM.disabled.build.psram_type=opi + +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FATFS) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-16MB +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota=TinyUF2 16MB No OTA(4MB APP/11.6MB FATFS) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-16MB-noota +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash.build.partitions=ffat +adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +adafruit_qualia_s3_rgb666.menu.CPUFreq.240=240MHz (WiFi) +adafruit_qualia_s3_rgb666.menu.CPUFreq.240.build.f_cpu=240000000L +adafruit_qualia_s3_rgb666.menu.CPUFreq.160=160MHz (WiFi) +adafruit_qualia_s3_rgb666.menu.CPUFreq.160.build.f_cpu=160000000L +adafruit_qualia_s3_rgb666.menu.CPUFreq.80=80MHz (WiFi) +adafruit_qualia_s3_rgb666.menu.CPUFreq.80.build.f_cpu=80000000L +adafruit_qualia_s3_rgb666.menu.CPUFreq.40=40MHz +adafruit_qualia_s3_rgb666.menu.CPUFreq.40.build.f_cpu=40000000L +adafruit_qualia_s3_rgb666.menu.CPUFreq.20=20MHz +adafruit_qualia_s3_rgb666.menu.CPUFreq.20.build.f_cpu=20000000L +adafruit_qualia_s3_rgb666.menu.CPUFreq.10=10MHz +adafruit_qualia_s3_rgb666.menu.CPUFreq.10.build.f_cpu=10000000L + +adafruit_qualia_s3_rgb666.menu.FlashMode.qio=QIO 80MHz +adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.flash_mode=dio +adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.boot=qio +adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.boot_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.flash_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.qio120=QIO 120MHz +adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.flash_mode=dio +adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.boot=qio +adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.boot_freq=120m +adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.flash_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.dio=DIO 80MHz +adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.flash_mode=dio +adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.boot=dio +adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.boot_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.flash_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.opi=OPI 80MHz +adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.flash_mode=dout +adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.boot=opi +adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.boot_freq=80m +adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.flash_freq=80m + +adafruit_qualia_s3_rgb666.menu.FlashSize.16M=16MB (128Mb) +adafruit_qualia_s3_rgb666.menu.FlashSize.16M.build.flash_size=16MB + +adafruit_qualia_s3_rgb666.menu.UploadSpeed.921600=921600 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.921600.upload.speed=921600 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.115200=115200 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.115200.upload.speed=115200 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.256000.windows=256000 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.256000.upload.speed=256000 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400.windows.upload.speed=256000 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400=230400 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400.upload.speed=230400 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.linux=460800 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.macosx=460800 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.upload.speed=460800 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.512000.windows=512000 +adafruit_qualia_s3_rgb666.menu.UploadSpeed.512000.upload.speed=512000 + +adafruit_qualia_s3_rgb666.menu.DebugLevel.none=None +adafruit_qualia_s3_rgb666.menu.DebugLevel.none.build.code_debug=0 +adafruit_qualia_s3_rgb666.menu.DebugLevel.error=Error +adafruit_qualia_s3_rgb666.menu.DebugLevel.error.build.code_debug=1 +adafruit_qualia_s3_rgb666.menu.DebugLevel.warn=Warn +adafruit_qualia_s3_rgb666.menu.DebugLevel.warn.build.code_debug=2 +adafruit_qualia_s3_rgb666.menu.DebugLevel.info=Info +adafruit_qualia_s3_rgb666.menu.DebugLevel.info.build.code_debug=3 +adafruit_qualia_s3_rgb666.menu.DebugLevel.debug=Debug +adafruit_qualia_s3_rgb666.menu.DebugLevel.debug.build.code_debug=4 +adafruit_qualia_s3_rgb666.menu.DebugLevel.verbose=Verbose +adafruit_qualia_s3_rgb666.menu.DebugLevel.verbose.build.code_debug=5 + +adafruit_qualia_s3_rgb666.menu.EraseFlash.none=Disabled +adafruit_qualia_s3_rgb666.menu.EraseFlash.none.upload.erase_cmd= +adafruit_qualia_s3_rgb666.menu.EraseFlash.all=Enabled +adafruit_qualia_s3_rgb666.menu.EraseFlash.all.upload.erase_cmd=-e + +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default=Disabled +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default.build.zigbee_mode= +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default.build.zigbee_libs= +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Sparkle Motion w/ESP32 + +sparklemotion.name=Adafruit Sparkle Motion (ESP32) + +sparklemotion.bootloader.tool=esptool_py +sparklemotion.bootloader.tool.default=esptool_py + +sparklemotion.upload.tool=esptool_py +sparklemotion.upload.tool.default=esptool_py +sparklemotion.upload.tool.network=esp_ota + +sparklemotion.upload.maximum_size=1310720 +sparklemotion.upload.maximum_data_size=327680 +sparklemotion.upload.flags= +sparklemotion.upload.extra_flags= + +sparklemotion.serial.disableDTR=true +sparklemotion.serial.disableRTS=true + +sparklemotion.build.tarch=xtensa +sparklemotion.build.bootloader_addr=0x1000 +sparklemotion.build.target=esp32 +sparklemotion.build.mcu=esp32 +sparklemotion.build.core=esp32 +sparklemotion.build.variant=adafruit_sparklemotion_esp32 +sparklemotion.build.board=SPARKLEMOTION_ESP32 + +sparklemotion.build.f_cpu=240000000L +sparklemotion.build.flash_size=4MB +sparklemotion.build.flash_freq=80m +sparklemotion.build.flash_mode=dio +sparklemotion.build.boot=dio +sparklemotion.build.partitions=default +sparklemotion.build.defines= +sparklemotion.build.loop_core= +sparklemotion.build.event_core= + +sparklemotion.menu.LoopCore.1=Core 1 +sparklemotion.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sparklemotion.menu.LoopCore.0=Core 0 +sparklemotion.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sparklemotion.menu.EventsCore.1=Core 1 +sparklemotion.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sparklemotion.menu.EventsCore.0=Core 0 +sparklemotion.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sparklemotion.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparklemotion.menu.PartitionScheme.default.build.partitions=default +sparklemotion.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparklemotion.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparklemotion.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparklemotion.menu.PartitionScheme.minimal.build.partitions=minimal +sparklemotion.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparklemotion.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparklemotion.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparklemotion.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparklemotion.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparklemotion.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparklemotion.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparklemotion.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparklemotion.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparklemotion.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparklemotion.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparklemotion.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparklemotion.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparklemotion.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparklemotion.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparklemotion.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparklemotion.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparklemotion.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sparklemotion.menu.CPUFreq.240=240MHz (WiFi/BT) +sparklemotion.menu.CPUFreq.240.build.f_cpu=240000000L +sparklemotion.menu.CPUFreq.160=160MHz (WiFi/BT) +sparklemotion.menu.CPUFreq.160.build.f_cpu=160000000L +sparklemotion.menu.CPUFreq.80=80MHz (WiFi/BT) +sparklemotion.menu.CPUFreq.80.build.f_cpu=80000000L +sparklemotion.menu.CPUFreq.40=40MHz +sparklemotion.menu.CPUFreq.40.build.f_cpu=40000000L +sparklemotion.menu.CPUFreq.20=20MHz +sparklemotion.menu.CPUFreq.20.build.f_cpu=20000000L +sparklemotion.menu.CPUFreq.10=10MHz +sparklemotion.menu.CPUFreq.10.build.f_cpu=10000000L + +sparklemotion.menu.FlashFreq.80=80MHz +sparklemotion.menu.FlashFreq.80.build.flash_freq=80m +sparklemotion.menu.FlashFreq.40=40MHz +sparklemotion.menu.FlashFreq.40.build.flash_freq=40m + +sparklemotion.menu.FlashSize.4M=4MB (32Mb) +sparklemotion.menu.FlashSize.4M.build.flash_size=4MB + +sparklemotion.menu.UploadSpeed.921600=921600 +sparklemotion.menu.UploadSpeed.921600.upload.speed=921600 +sparklemotion.menu.UploadSpeed.115200=115200 +sparklemotion.menu.UploadSpeed.115200.upload.speed=115200 +sparklemotion.menu.UploadSpeed.256000.windows=256000 +sparklemotion.menu.UploadSpeed.256000.upload.speed=256000 +sparklemotion.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparklemotion.menu.UploadSpeed.230400=230400 +sparklemotion.menu.UploadSpeed.230400.upload.speed=230400 +sparklemotion.menu.UploadSpeed.460800.linux=460800 +sparklemotion.menu.UploadSpeed.460800.macosx=460800 +sparklemotion.menu.UploadSpeed.460800.upload.speed=460800 +sparklemotion.menu.UploadSpeed.512000.windows=512000 +sparklemotion.menu.UploadSpeed.512000.upload.speed=512000 + +sparklemotion.menu.DebugLevel.none=None +sparklemotion.menu.DebugLevel.none.build.code_debug=0 +sparklemotion.menu.DebugLevel.error=Error +sparklemotion.menu.DebugLevel.error.build.code_debug=1 +sparklemotion.menu.DebugLevel.warn=Warn +sparklemotion.menu.DebugLevel.warn.build.code_debug=2 +sparklemotion.menu.DebugLevel.info=Info +sparklemotion.menu.DebugLevel.info.build.code_debug=3 +sparklemotion.menu.DebugLevel.debug=Debug +sparklemotion.menu.DebugLevel.debug.build.code_debug=4 +sparklemotion.menu.DebugLevel.verbose=Verbose +sparklemotion.menu.DebugLevel.verbose.build.code_debug=5 + +sparklemotion.menu.EraseFlash.none=Disabled +sparklemotion.menu.EraseFlash.none.upload.erase_cmd= +sparklemotion.menu.EraseFlash.all=Enabled +sparklemotion.menu.EraseFlash.all.upload.erase_cmd=-e + +sparklemotion.menu.ZigbeeMode.default=Disabled +sparklemotion.menu.ZigbeeMode.default.build.zigbee_mode= +sparklemotion.menu.ZigbeeMode.default.build.zigbee_libs= +sparklemotion.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +sparklemotion.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparklemotion.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Sparkle Motion Mini w/ESP32 + +sparklemotionmini.name=Adafruit Sparkle Motion Mini (ESP32) + +sparklemotionmini.bootloader.tool=esptool_py +sparklemotionmini.bootloader.tool.default=esptool_py + +sparklemotionmini.upload.tool=esptool_py +sparklemotionmini.upload.tool.default=esptool_py +sparklemotionmini.upload.tool.network=esp_ota + +sparklemotionmini.upload.maximum_size=1310720 +sparklemotionmini.upload.maximum_data_size=327680 +sparklemotionmini.upload.flags= +sparklemotionmini.upload.extra_flags= + +sparklemotionmini.serial.disableDTR=true +sparklemotionmini.serial.disableRTS=true + +sparklemotionmini.build.tarch=xtensa +sparklemotionmini.build.bootloader_addr=0x1000 +sparklemotionmini.build.target=esp32 +sparklemotionmini.build.mcu=esp32 +sparklemotionmini.build.core=esp32 +sparklemotionmini.build.variant=adafruit_sparklemotionmini_esp32 +sparklemotionmini.build.board=SPARKLEMOTIONMINI_ESP32 + +sparklemotionmini.build.f_cpu=240000000L +sparklemotionmini.build.flash_size=4MB +sparklemotionmini.build.flash_freq=80m +sparklemotionmini.build.flash_mode=dio +sparklemotionmini.build.boot=dio +sparklemotionmini.build.partitions=default +sparklemotionmini.build.defines= +sparklemotionmini.build.loop_core= +sparklemotionmini.build.event_core= + +sparklemotionmini.menu.LoopCore.1=Core 1 +sparklemotionmini.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sparklemotionmini.menu.LoopCore.0=Core 0 +sparklemotionmini.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sparklemotionmini.menu.EventsCore.1=Core 1 +sparklemotionmini.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sparklemotionmini.menu.EventsCore.0=Core 0 +sparklemotionmini.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sparklemotionmini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparklemotionmini.menu.PartitionScheme.default.build.partitions=default +sparklemotionmini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparklemotionmini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparklemotionmini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparklemotionmini.menu.PartitionScheme.minimal.build.partitions=minimal +sparklemotionmini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparklemotionmini.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparklemotionmini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparklemotionmini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparklemotionmini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparklemotionmini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparklemotionmini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparklemotionmini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparklemotionmini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparklemotionmini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparklemotionmini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparklemotionmini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparklemotionmini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparklemotionmini.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparklemotionmini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparklemotionmini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparklemotionmini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparklemotionmini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sparklemotionmini.menu.CPUFreq.240=240MHz (WiFi/BT) +sparklemotionmini.menu.CPUFreq.240.build.f_cpu=240000000L +sparklemotionmini.menu.CPUFreq.160=160MHz (WiFi/BT) +sparklemotionmini.menu.CPUFreq.160.build.f_cpu=160000000L +sparklemotionmini.menu.CPUFreq.80=80MHz (WiFi/BT) +sparklemotionmini.menu.CPUFreq.80.build.f_cpu=80000000L +sparklemotionmini.menu.CPUFreq.40=40MHz +sparklemotionmini.menu.CPUFreq.40.build.f_cpu=40000000L +sparklemotionmini.menu.CPUFreq.20=20MHz +sparklemotionmini.menu.CPUFreq.20.build.f_cpu=20000000L +sparklemotionmini.menu.CPUFreq.10=10MHz +sparklemotionmini.menu.CPUFreq.10.build.f_cpu=10000000L + +sparklemotionmini.menu.FlashFreq.80=80MHz +sparklemotionmini.menu.FlashFreq.80.build.flash_freq=80m +sparklemotionmini.menu.FlashFreq.40=40MHz +sparklemotionmini.menu.FlashFreq.40.build.flash_freq=40m + +sparklemotionmini.menu.FlashSize.4M=4MB (32Mb) +sparklemotionmini.menu.FlashSize.4M.build.flash_size=4MB + +sparklemotionmini.menu.UploadSpeed.921600=921600 +sparklemotionmini.menu.UploadSpeed.921600.upload.speed=921600 +sparklemotionmini.menu.UploadSpeed.115200=115200 +sparklemotionmini.menu.UploadSpeed.115200.upload.speed=115200 +sparklemotionmini.menu.UploadSpeed.256000.windows=256000 +sparklemotionmini.menu.UploadSpeed.256000.upload.speed=256000 +sparklemotionmini.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparklemotionmini.menu.UploadSpeed.230400=230400 +sparklemotionmini.menu.UploadSpeed.230400.upload.speed=230400 +sparklemotionmini.menu.UploadSpeed.460800.linux=460800 +sparklemotionmini.menu.UploadSpeed.460800.macosx=460800 +sparklemotionmini.menu.UploadSpeed.460800.upload.speed=460800 +sparklemotionmini.menu.UploadSpeed.512000.windows=512000 +sparklemotionmini.menu.UploadSpeed.512000.upload.speed=512000 + +sparklemotionmini.menu.DebugLevel.none=None +sparklemotionmini.menu.DebugLevel.none.build.code_debug=0 +sparklemotionmini.menu.DebugLevel.error=Error +sparklemotionmini.menu.DebugLevel.error.build.code_debug=1 +sparklemotionmini.menu.DebugLevel.warn=Warn +sparklemotionmini.menu.DebugLevel.warn.build.code_debug=2 +sparklemotionmini.menu.DebugLevel.info=Info +sparklemotionmini.menu.DebugLevel.info.build.code_debug=3 +sparklemotionmini.menu.DebugLevel.debug=Debug +sparklemotionmini.menu.DebugLevel.debug.build.code_debug=4 +sparklemotionmini.menu.DebugLevel.verbose=Verbose +sparklemotionmini.menu.DebugLevel.verbose.build.code_debug=5 + +sparklemotionmini.menu.EraseFlash.none=Disabled +sparklemotionmini.menu.EraseFlash.none.upload.erase_cmd= +sparklemotionmini.menu.EraseFlash.all=Enabled +sparklemotionmini.menu.EraseFlash.all.upload.erase_cmd=-e + +sparklemotionmini.menu.ZigbeeMode.default=Disabled +sparklemotionmini.menu.ZigbeeMode.default.build.zigbee_mode= +sparklemotionmini.menu.ZigbeeMode.default.build.zigbee_libs= +sparklemotionmini.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +sparklemotionmini.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparklemotionmini.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## +# Adafruit Sparkle Motion Stick w/ESP32 + +sparklemotionstick.name=Adafruit Sparkle Motion Stick (ESP32) + +sparklemotionstick.bootloader.tool=esptool_py +sparklemotionstick.bootloader.tool.default=esptool_py + +sparklemotionstick.upload.tool=esptool_py +sparklemotionstick.upload.tool.default=esptool_py +sparklemotionstick.upload.tool.network=esp_ota + +sparklemotionstick.upload.maximum_size=1310720 +sparklemotionstick.upload.maximum_data_size=327680 +sparklemotionstick.upload.flags= +sparklemotionstick.upload.extra_flags= + +sparklemotionstick.serial.disableDTR=true +sparklemotionstick.serial.disableRTS=true + +sparklemotionstick.build.tarch=xtensa +sparklemotionstick.build.bootloader_addr=0x1000 +sparklemotionstick.build.target=esp32 +sparklemotionstick.build.mcu=esp32 +sparklemotionstick.build.core=esp32 +sparklemotionstick.build.variant=adafruit_sparklemotionstick_esp32 +sparklemotionstick.build.board=SPARKLEMOTIONSTICK_ESP32 + +sparklemotionstick.build.f_cpu=240000000L +sparklemotionstick.build.flash_size=4MB +sparklemotionstick.build.flash_freq=80m +sparklemotionstick.build.flash_mode=dio +sparklemotionstick.build.boot=dio +sparklemotionstick.build.partitions=default +sparklemotionstick.build.defines= +sparklemotionstick.build.loop_core= +sparklemotionstick.build.event_core= + +sparklemotionstick.menu.LoopCore.1=Core 1 +sparklemotionstick.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sparklemotionstick.menu.LoopCore.0=Core 0 +sparklemotionstick.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sparklemotionstick.menu.EventsCore.1=Core 1 +sparklemotionstick.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sparklemotionstick.menu.EventsCore.0=Core 0 +sparklemotionstick.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sparklemotionstick.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sparklemotionstick.menu.PartitionScheme.default.build.partitions=default +sparklemotionstick.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sparklemotionstick.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sparklemotionstick.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sparklemotionstick.menu.PartitionScheme.minimal.build.partitions=minimal +sparklemotionstick.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sparklemotionstick.menu.PartitionScheme.no_ota.build.partitions=no_ota +sparklemotionstick.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sparklemotionstick.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sparklemotionstick.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sparklemotionstick.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sparklemotionstick.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sparklemotionstick.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sparklemotionstick.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sparklemotionstick.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sparklemotionstick.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sparklemotionstick.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sparklemotionstick.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sparklemotionstick.menu.PartitionScheme.huge_app.build.partitions=huge_app +sparklemotionstick.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sparklemotionstick.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sparklemotionstick.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sparklemotionstick.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sparklemotionstick.menu.CPUFreq.240=240MHz (WiFi/BT) +sparklemotionstick.menu.CPUFreq.240.build.f_cpu=240000000L +sparklemotionstick.menu.CPUFreq.160=160MHz (WiFi/BT) +sparklemotionstick.menu.CPUFreq.160.build.f_cpu=160000000L +sparklemotionstick.menu.CPUFreq.80=80MHz (WiFi/BT) +sparklemotionstick.menu.CPUFreq.80.build.f_cpu=80000000L +sparklemotionstick.menu.CPUFreq.40=40MHz +sparklemotionstick.menu.CPUFreq.40.build.f_cpu=40000000L +sparklemotionstick.menu.CPUFreq.20=20MHz +sparklemotionstick.menu.CPUFreq.20.build.f_cpu=20000000L +sparklemotionstick.menu.CPUFreq.10=10MHz +sparklemotionstick.menu.CPUFreq.10.build.f_cpu=10000000L + +sparklemotionstick.menu.FlashFreq.80=80MHz +sparklemotionstick.menu.FlashFreq.80.build.flash_freq=80m +sparklemotionstick.menu.FlashFreq.40=40MHz +sparklemotionstick.menu.FlashFreq.40.build.flash_freq=40m + +sparklemotionstick.menu.FlashSize.4M=4MB (32Mb) +sparklemotionstick.menu.FlashSize.4M.build.flash_size=4MB + +sparklemotionstick.menu.UploadSpeed.921600=921600 +sparklemotionstick.menu.UploadSpeed.921600.upload.speed=921600 +sparklemotionstick.menu.UploadSpeed.115200=115200 +sparklemotionstick.menu.UploadSpeed.115200.upload.speed=115200 +sparklemotionstick.menu.UploadSpeed.256000.windows=256000 +sparklemotionstick.menu.UploadSpeed.256000.upload.speed=256000 +sparklemotionstick.menu.UploadSpeed.230400.windows.upload.speed=256000 +sparklemotionstick.menu.UploadSpeed.230400=230400 +sparklemotionstick.menu.UploadSpeed.230400.upload.speed=230400 +sparklemotionstick.menu.UploadSpeed.460800.linux=460800 +sparklemotionstick.menu.UploadSpeed.460800.macosx=460800 +sparklemotionstick.menu.UploadSpeed.460800.upload.speed=460800 +sparklemotionstick.menu.UploadSpeed.512000.windows=512000 +sparklemotionstick.menu.UploadSpeed.512000.upload.speed=512000 + +sparklemotionstick.menu.DebugLevel.none=None +sparklemotionstick.menu.DebugLevel.none.build.code_debug=0 +sparklemotionstick.menu.DebugLevel.error=Error +sparklemotionstick.menu.DebugLevel.error.build.code_debug=1 +sparklemotionstick.menu.DebugLevel.warn=Warn +sparklemotionstick.menu.DebugLevel.warn.build.code_debug=2 +sparklemotionstick.menu.DebugLevel.info=Info +sparklemotionstick.menu.DebugLevel.info.build.code_debug=3 +sparklemotionstick.menu.DebugLevel.debug=Debug +sparklemotionstick.menu.DebugLevel.debug.build.code_debug=4 +sparklemotionstick.menu.DebugLevel.verbose=Verbose +sparklemotionstick.menu.DebugLevel.verbose.build.code_debug=5 + +sparklemotionstick.menu.EraseFlash.none=Disabled +sparklemotionstick.menu.EraseFlash.none.upload.erase_cmd= +sparklemotionstick.menu.EraseFlash.all=Enabled +sparklemotionstick.menu.EraseFlash.all.upload.erase_cmd=-e + +sparklemotionstick.menu.ZigbeeMode.default=Disabled +sparklemotionstick.menu.ZigbeeMode.default.build.zigbee_mode= +sparklemotionstick.menu.ZigbeeMode.default.build.zigbee_libs= +sparklemotionstick.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +sparklemotionstick.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +sparklemotionstick.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +nodemcu-32s.name=NodeMCU-32S + +nodemcu-32s.bootloader.tool=esptool_py +nodemcu-32s.bootloader.tool.default=esptool_py + +nodemcu-32s.upload.tool=esptool_py +nodemcu-32s.upload.tool.default=esptool_py +nodemcu-32s.upload.tool.network=esp_ota + +nodemcu-32s.upload.maximum_size=1310720 +nodemcu-32s.upload.maximum_data_size=327680 +nodemcu-32s.upload.flags= +nodemcu-32s.upload.extra_flags= + +nodemcu-32s.serial.disableDTR=true +nodemcu-32s.serial.disableRTS=true + +nodemcu-32s.build.tarch=xtensa +nodemcu-32s.build.bootloader_addr=0x1000 +nodemcu-32s.build.target=esp32 +nodemcu-32s.build.mcu=esp32 +nodemcu-32s.build.core=esp32 +nodemcu-32s.build.variant=nodemcu-32s +nodemcu-32s.build.board=NODEMCU_32S + +nodemcu-32s.build.f_cpu=240000000L +nodemcu-32s.build.flash_mode=dio +nodemcu-32s.build.flash_size=4MB +nodemcu-32s.build.boot=dio +nodemcu-32s.build.partitions=default +nodemcu-32s.build.defines= + +nodemcu-32s.menu.FlashFreq.80=80MHz +nodemcu-32s.menu.FlashFreq.80.build.flash_freq=80m +nodemcu-32s.menu.FlashFreq.40=40MHz +nodemcu-32s.menu.FlashFreq.40.build.flash_freq=40m + +nodemcu-32s.menu.UploadSpeed.115200=115200 +nodemcu-32s.menu.UploadSpeed.115200.upload.speed=115200 +nodemcu-32s.menu.UploadSpeed.256000.windows=256000 +nodemcu-32s.menu.UploadSpeed.256000.upload.speed=256000 +nodemcu-32s.menu.UploadSpeed.230400.windows.upload.speed=256000 +nodemcu-32s.menu.UploadSpeed.230400=230400 +nodemcu-32s.menu.UploadSpeed.230400.upload.speed=230400 +nodemcu-32s.menu.UploadSpeed.512000.windows=512000 +nodemcu-32s.menu.UploadSpeed.512000.upload.speed=512000 +nodemcu-32s.menu.UploadSpeed.460800.linux=460800 +nodemcu-32s.menu.UploadSpeed.460800.macosx=460800 +nodemcu-32s.menu.UploadSpeed.460800.upload.speed=460800 +nodemcu-32s.menu.UploadSpeed.921600=921600 +nodemcu-32s.menu.UploadSpeed.921600.upload.speed=921600 + +nodemcu-32s.menu.DebugLevel.none=None +nodemcu-32s.menu.DebugLevel.none.build.code_debug=0 +nodemcu-32s.menu.DebugLevel.error=Error +nodemcu-32s.menu.DebugLevel.error.build.code_debug=1 +nodemcu-32s.menu.DebugLevel.warn=Warn +nodemcu-32s.menu.DebugLevel.warn.build.code_debug=2 +nodemcu-32s.menu.DebugLevel.info=Info +nodemcu-32s.menu.DebugLevel.info.build.code_debug=3 +nodemcu-32s.menu.DebugLevel.debug=Debug +nodemcu-32s.menu.DebugLevel.debug.build.code_debug=4 +nodemcu-32s.menu.DebugLevel.verbose=Verbose +nodemcu-32s.menu.DebugLevel.verbose.build.code_debug=5 + +nodemcu-32s.menu.EraseFlash.none=Disabled +nodemcu-32s.menu.EraseFlash.none.upload.erase_cmd= +nodemcu-32s.menu.EraseFlash.all=Enabled +nodemcu-32s.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nologo_esp32c3_super_mini.name=Nologo ESP32C3 Super Mini + +nologo_esp32c3_super_mini.upload.tool=esptool_py +nologo_esp32c3_super_mini.upload.tool.default=esptool_py +nologo_esp32c3_super_mini.upload.tool.network=esp_ota +nologo_esp32c3_super_mini.upload.maximum_size=1310720 +nologo_esp32c3_super_mini.upload.maximum_data_size=327680 +nologo_esp32c3_super_mini.upload.flags= +nologo_esp32c3_super_mini.upload.extra_flags= +nologo_esp32c3_super_mini.upload.use_1200bps_touch=false +nologo_esp32c3_super_mini.upload.wait_for_upload_port=false + +nologo_esp32c3_super_mini.serial.disableDTR=false +nologo_esp32c3_super_mini.serial.disableRTS=false + +nologo_esp32c3_super_mini.build.tarch=riscv32 +nologo_esp32c3_super_mini.build.target=esp +nologo_esp32c3_super_mini.build.mcu=esp32c3 +nologo_esp32c3_super_mini.build.core=esp32 +nologo_esp32c3_super_mini.build.variant=nologo_esp32c3_super_mini +nologo_esp32c3_super_mini.build.board=NOLOGO_ESP32C3_SUPER_MINI +nologo_esp32c3_super_mini.build.bootloader_addr=0x0 + +nologo_esp32c3_super_mini.build.usb_mode=1 +nologo_esp32c3_super_mini.build.cdc_on_boot=1 +nologo_esp32c3_super_mini.build.f_cpu=160000000L +nologo_esp32c3_super_mini.build.flash_size=4MB +nologo_esp32c3_super_mini.build.flash_freq=80m +nologo_esp32c3_super_mini.build.flash_mode=qio +nologo_esp32c3_super_mini.build.boot=qio +nologo_esp32c3_super_mini.build.partitions=default +nologo_esp32c3_super_mini.build.defines= + +nologo_esp32c3_super_mini.menu.USBMode.hwcdc=Hardware CDC and JTAG +nologo_esp32c3_super_mini.menu.USBMode.hwcdc.build.usb_mode=1 +nologo_esp32c3_super_mini.menu.USBMode.default=USB-OTG +nologo_esp32c3_super_mini.menu.USBMode.default.build.usb_mode=0 + +nologo_esp32c3_super_mini.menu.JTAGAdapter.default=Disabled +nologo_esp32c3_super_mini.menu.JTAGAdapter.default.build.copy_jtag_files=0 +nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin=Integrated USB JTAG +nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +nologo_esp32c3_super_mini.menu.JTAGAdapter.external=FTDI Adapter +nologo_esp32c3_super_mini.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +nologo_esp32c3_super_mini.menu.JTAGAdapter.external.build.copy_jtag_files=1 +nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge=ESP USB Bridge +nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +nologo_esp32c3_super_mini.menu.CDCOnBoot.default=Enabled +nologo_esp32c3_super_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +nologo_esp32c3_super_mini.menu.CDCOnBoot.cdc=Enabled +nologo_esp32c3_super_mini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +nologo_esp32c3_super_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.default.build.partitions=default +nologo_esp32c3_super_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +nologo_esp32c3_super_mini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.minimal.build.partitions=minimal +nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +nologo_esp32c3_super_mini.menu.CPUFreq.160=160MHz (WiFi) +nologo_esp32c3_super_mini.menu.CPUFreq.160.build.f_cpu=160000000L +nologo_esp32c3_super_mini.menu.CPUFreq.80=80MHz (WiFi) +nologo_esp32c3_super_mini.menu.CPUFreq.80.build.f_cpu=80000000L +nologo_esp32c3_super_mini.menu.CPUFreq.40=40MHz +nologo_esp32c3_super_mini.menu.CPUFreq.40.build.f_cpu=40000000L +nologo_esp32c3_super_mini.menu.CPUFreq.20=20MHz +nologo_esp32c3_super_mini.menu.CPUFreq.20.build.f_cpu=20000000L +nologo_esp32c3_super_mini.menu.CPUFreq.10=10MHz +nologo_esp32c3_super_mini.menu.CPUFreq.10.build.f_cpu=10000000L + +nologo_esp32c3_super_mini.menu.FlashMode.qio=QIO +nologo_esp32c3_super_mini.menu.FlashMode.qio.build.flash_mode=dio +nologo_esp32c3_super_mini.menu.FlashMode.qio.build.boot=qio +nologo_esp32c3_super_mini.menu.FlashMode.dio=DIO +nologo_esp32c3_super_mini.menu.FlashMode.dio.build.flash_mode=dio +nologo_esp32c3_super_mini.menu.FlashMode.dio.build.boot=dio + +nologo_esp32c3_super_mini.menu.FlashFreq.80=80MHz +nologo_esp32c3_super_mini.menu.FlashFreq.80.build.flash_freq=80m +nologo_esp32c3_super_mini.menu.FlashFreq.40=40MHz +nologo_esp32c3_super_mini.menu.FlashFreq.40.build.flash_freq=40m + +nologo_esp32c3_super_mini.menu.UploadSpeed.921600=921600 +nologo_esp32c3_super_mini.menu.UploadSpeed.921600.upload.speed=921600 +nologo_esp32c3_super_mini.menu.UploadSpeed.115200=115200 +nologo_esp32c3_super_mini.menu.UploadSpeed.115200.upload.speed=115200 +nologo_esp32c3_super_mini.menu.UploadSpeed.256000.windows=256000 +nologo_esp32c3_super_mini.menu.UploadSpeed.256000.upload.speed=256000 +nologo_esp32c3_super_mini.menu.UploadSpeed.230400.windows.upload.speed=256000 +nologo_esp32c3_super_mini.menu.UploadSpeed.230400=230400 +nologo_esp32c3_super_mini.menu.UploadSpeed.230400.upload.speed=230400 +nologo_esp32c3_super_mini.menu.UploadSpeed.460800.linux=460800 +nologo_esp32c3_super_mini.menu.UploadSpeed.460800.macosx=460800 +nologo_esp32c3_super_mini.menu.UploadSpeed.460800.upload.speed=460800 +nologo_esp32c3_super_mini.menu.UploadSpeed.512000.windows=512000 +nologo_esp32c3_super_mini.menu.UploadSpeed.512000.upload.speed=512000 + +nologo_esp32c3_super_mini.menu.DebugLevel.none=None +nologo_esp32c3_super_mini.menu.DebugLevel.none.build.code_debug=0 +nologo_esp32c3_super_mini.menu.DebugLevel.error=Error +nologo_esp32c3_super_mini.menu.DebugLevel.error.build.code_debug=1 +nologo_esp32c3_super_mini.menu.DebugLevel.warn=Warn +nologo_esp32c3_super_mini.menu.DebugLevel.warn.build.code_debug=2 +nologo_esp32c3_super_mini.menu.DebugLevel.info=Info +nologo_esp32c3_super_mini.menu.DebugLevel.info.build.code_debug=3 +nologo_esp32c3_super_mini.menu.DebugLevel.debug=Debug +nologo_esp32c3_super_mini.menu.DebugLevel.debug.build.code_debug=4 +nologo_esp32c3_super_mini.menu.DebugLevel.verbose=Verbose +nologo_esp32c3_super_mini.menu.DebugLevel.verbose.build.code_debug=5 + +nologo_esp32c3_super_mini.menu.EraseFlash.none=Disabled +nologo_esp32c3_super_mini.menu.EraseFlash.none.upload.erase_cmd= +nologo_esp32c3_super_mini.menu.EraseFlash.all=Enabled +nologo_esp32c3_super_mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nologo_esp32s3_pico.name=Nologo ESP32S3 Pico + +nologo_esp32s3_pico.bootloader.tool=esptool_py +nologo_esp32s3_pico.bootloader.tool.default=esptool_py + +nologo_esp32s3_pico.upload.tool=esptool_py +nologo_esp32s3_pico.upload.tool.default=esptool_py +nologo_esp32s3_pico.upload.tool.network=esp_ota + +nologo_esp32s3_pico.upload.maximum_size=1310720 +nologo_esp32s3_pico.upload.maximum_data_size=327680 +nologo_esp32s3_pico.upload.flags= +nologo_esp32s3_pico.upload.extra_flags= +nologo_esp32s3_pico.upload.use_1200bps_touch=false +nologo_esp32s3_pico.upload.wait_for_upload_port=false + +nologo_esp32s3_pico.serial.disableDTR=false +nologo_esp32s3_pico.serial.disableRTS=false + +nologo_esp32s3_pico.build.tarch=xtensa +nologo_esp32s3_pico.build.bootloader_addr=0x0 +nologo_esp32s3_pico.build.target=esp32s3 +nologo_esp32s3_pico.build.mcu=esp32s3 +nologo_esp32s3_pico.build.core=esp32 +nologo_esp32s3_pico.build.variant=nologo_esp32s3_pico +nologo_esp32s3_pico.build.board=NOLOGO_ESP32S3_PICO + +nologo_esp32s3_pico.build.usb_mode=1 +nologo_esp32s3_pico.build.cdc_on_boot=1 +nologo_esp32s3_pico.build.msc_on_boot=0 +nologo_esp32s3_pico.build.dfu_on_boot=0 +nologo_esp32s3_pico.build.f_cpu=240000000L +nologo_esp32s3_pico.build.flash_size=8MB +nologo_esp32s3_pico.build.flash_freq=80m +nologo_esp32s3_pico.build.flash_mode=dio +nologo_esp32s3_pico.build.boot=qio +nologo_esp32s3_pico.build.boot_freq=80m +nologo_esp32s3_pico.build.partitions=default +nologo_esp32s3_pico.build.defines= +nologo_esp32s3_pico.build.loop_core= +nologo_esp32s3_pico.build.event_core= +nologo_esp32s3_pico.build.psram_type=qspi +nologo_esp32s3_pico.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +nologo_esp32s3_pico.menu.JTAGAdapter.default=Disabled +nologo_esp32s3_pico.menu.JTAGAdapter.default.build.copy_jtag_files=0 +nologo_esp32s3_pico.menu.JTAGAdapter.builtin=Integrated USB JTAG +nologo_esp32s3_pico.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +nologo_esp32s3_pico.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +nologo_esp32s3_pico.menu.JTAGAdapter.external=FTDI Adapter +nologo_esp32s3_pico.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +nologo_esp32s3_pico.menu.JTAGAdapter.external.build.copy_jtag_files=1 +nologo_esp32s3_pico.menu.JTAGAdapter.bridge=ESP USB Bridge +nologo_esp32s3_pico.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +nologo_esp32s3_pico.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +nologo_esp32s3_pico.menu.PSRAM.disabled=Disabled +nologo_esp32s3_pico.menu.PSRAM.disabled.build.defines= +nologo_esp32s3_pico.menu.PSRAM.disabled.build.psram_type=qspi +nologo_esp32s3_pico.menu.PSRAM.enabled=QSPI PSRAM +nologo_esp32s3_pico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +nologo_esp32s3_pico.menu.PSRAM.enabled.build.psram_type=qspi +nologo_esp32s3_pico.menu.PSRAM.opi=OPI PSRAM +nologo_esp32s3_pico.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +nologo_esp32s3_pico.menu.PSRAM.opi.build.psram_type=opi + +nologo_esp32s3_pico.menu.FlashMode.qio=QIO 80MHz +nologo_esp32s3_pico.menu.FlashMode.qio.build.flash_mode=dio +nologo_esp32s3_pico.menu.FlashMode.qio.build.boot=qio +nologo_esp32s3_pico.menu.FlashMode.qio.build.boot_freq=80m +nologo_esp32s3_pico.menu.FlashMode.qio.build.flash_freq=80m +nologo_esp32s3_pico.menu.FlashMode.qio120=QIO 120MHz +nologo_esp32s3_pico.menu.FlashMode.qio120.build.flash_mode=dio +nologo_esp32s3_pico.menu.FlashMode.qio120.build.boot=qio +nologo_esp32s3_pico.menu.FlashMode.qio120.build.boot_freq=120m +nologo_esp32s3_pico.menu.FlashMode.qio120.build.flash_freq=80m +nologo_esp32s3_pico.menu.FlashMode.dio=DIO 80MHz +nologo_esp32s3_pico.menu.FlashMode.dio.build.flash_mode=dio +nologo_esp32s3_pico.menu.FlashMode.dio.build.boot=dio +nologo_esp32s3_pico.menu.FlashMode.dio.build.boot_freq=80m +nologo_esp32s3_pico.menu.FlashMode.dio.build.flash_freq=80m +nologo_esp32s3_pico.menu.FlashMode.opi=OPI 80MHz +nologo_esp32s3_pico.menu.FlashMode.opi.build.flash_mode=dout +nologo_esp32s3_pico.menu.FlashMode.opi.build.boot=opi +nologo_esp32s3_pico.menu.FlashMode.opi.build.boot_freq=80m +nologo_esp32s3_pico.menu.FlashMode.opi.build.flash_freq=80m + +nologo_esp32s3_pico.menu.FlashSize.8M=8MB (64Mb) +nologo_esp32s3_pico.menu.FlashSize.8M.build.flash_size=8MB +nologo_esp32s3_pico.menu.FlashSize.16M=16MB (128Mb) +nologo_esp32s3_pico.menu.FlashSize.16M.build.flash_size=16MB + +nologo_esp32s3_pico.menu.LoopCore.1=Core 1 +nologo_esp32s3_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +nologo_esp32s3_pico.menu.LoopCore.0=Core 0 +nologo_esp32s3_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +nologo_esp32s3_pico.menu.EventsCore.1=Core 1 +nologo_esp32s3_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +nologo_esp32s3_pico.menu.EventsCore.0=Core 0 +nologo_esp32s3_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +nologo_esp32s3_pico.menu.USBMode.hwcdc=Hardware CDC and JTAG +nologo_esp32s3_pico.menu.USBMode.hwcdc.build.usb_mode=1 +nologo_esp32s3_pico.menu.USBMode.default=USB-OTG (TinyUSB) +nologo_esp32s3_pico.menu.USBMode.default.build.usb_mode=0 + +nologo_esp32s3_pico.menu.CDCOnBoot.default=Enabled +nologo_esp32s3_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1 +nologo_esp32s3_pico.menu.CDCOnBoot.cdc=Enabled +nologo_esp32s3_pico.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +nologo_esp32s3_pico.menu.MSCOnBoot.default=Disabled +nologo_esp32s3_pico.menu.MSCOnBoot.default.build.msc_on_boot=0 +nologo_esp32s3_pico.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +nologo_esp32s3_pico.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +nologo_esp32s3_pico.menu.DFUOnBoot.default=Disabled +nologo_esp32s3_pico.menu.DFUOnBoot.default.build.dfu_on_boot=0 +nologo_esp32s3_pico.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +nologo_esp32s3_pico.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +nologo_esp32s3_pico.menu.UploadMode.default=UART0 / Hardware CDC +nologo_esp32s3_pico.menu.UploadMode.default.upload.use_1200bps_touch=false +nologo_esp32s3_pico.menu.UploadMode.default.upload.wait_for_upload_port=false +nologo_esp32s3_pico.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +nologo_esp32s3_pico.menu.UploadMode.cdc.upload.use_1200bps_touch=true +nologo_esp32s3_pico.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +nologo_esp32s3_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.default.build.partitions=default +nologo_esp32s3_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +nologo_esp32s3_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +nologo_esp32s3_pico.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +nologo_esp32s3_pico.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +nologo_esp32s3_pico.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.minimal.build.partitions=minimal +nologo_esp32s3_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota +nologo_esp32s3_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +nologo_esp32s3_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +nologo_esp32s3_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +nologo_esp32s3_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app +nologo_esp32s3_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +nologo_esp32s3_pico.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +nologo_esp32s3_pico.menu.PartitionScheme.fatflash.build.partitions=ffat +nologo_esp32s3_pico.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker=RainMaker 4MB +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +nologo_esp32s3_pico.menu.PartitionScheme.custom=Custom +nologo_esp32s3_pico.menu.PartitionScheme.custom.build.partitions= +nologo_esp32s3_pico.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +nologo_esp32s3_pico.menu.CPUFreq.240=240MHz (WiFi) +nologo_esp32s3_pico.menu.CPUFreq.240.build.f_cpu=240000000L +nologo_esp32s3_pico.menu.CPUFreq.160=160MHz (WiFi) +nologo_esp32s3_pico.menu.CPUFreq.160.build.f_cpu=160000000L +nologo_esp32s3_pico.menu.CPUFreq.80=80MHz (WiFi) +nologo_esp32s3_pico.menu.CPUFreq.80.build.f_cpu=80000000L +nologo_esp32s3_pico.menu.CPUFreq.40=40MHz +nologo_esp32s3_pico.menu.CPUFreq.40.build.f_cpu=40000000L +nologo_esp32s3_pico.menu.CPUFreq.20=20MHz +nologo_esp32s3_pico.menu.CPUFreq.20.build.f_cpu=20000000L +nologo_esp32s3_pico.menu.CPUFreq.10=10MHz +nologo_esp32s3_pico.menu.CPUFreq.10.build.f_cpu=10000000L + +nologo_esp32s3_pico.menu.UploadSpeed.921600=921600 +nologo_esp32s3_pico.menu.UploadSpeed.921600.upload.speed=921600 +nologo_esp32s3_pico.menu.UploadSpeed.115200=115200 +nologo_esp32s3_pico.menu.UploadSpeed.115200.upload.speed=115200 +nologo_esp32s3_pico.menu.UploadSpeed.256000.windows=256000 +nologo_esp32s3_pico.menu.UploadSpeed.256000.upload.speed=256000 +nologo_esp32s3_pico.menu.UploadSpeed.230400.windows.upload.speed=256000 +nologo_esp32s3_pico.menu.UploadSpeed.230400=230400 +nologo_esp32s3_pico.menu.UploadSpeed.230400.upload.speed=230400 +nologo_esp32s3_pico.menu.UploadSpeed.460800.linux=460800 +nologo_esp32s3_pico.menu.UploadSpeed.460800.macosx=460800 +nologo_esp32s3_pico.menu.UploadSpeed.460800.upload.speed=460800 +nologo_esp32s3_pico.menu.UploadSpeed.512000.windows=512000 +nologo_esp32s3_pico.menu.UploadSpeed.512000.upload.speed=512000 + +nologo_esp32s3_pico.menu.DebugLevel.none=None +nologo_esp32s3_pico.menu.DebugLevel.none.build.code_debug=0 +nologo_esp32s3_pico.menu.DebugLevel.error=Error +nologo_esp32s3_pico.menu.DebugLevel.error.build.code_debug=1 +nologo_esp32s3_pico.menu.DebugLevel.warn=Warn +nologo_esp32s3_pico.menu.DebugLevel.warn.build.code_debug=2 +nologo_esp32s3_pico.menu.DebugLevel.info=Info +nologo_esp32s3_pico.menu.DebugLevel.info.build.code_debug=3 +nologo_esp32s3_pico.menu.DebugLevel.debug=Debug +nologo_esp32s3_pico.menu.DebugLevel.debug.build.code_debug=4 +nologo_esp32s3_pico.menu.DebugLevel.verbose=Verbose +nologo_esp32s3_pico.menu.DebugLevel.verbose.build.code_debug=5 + +nologo_esp32s3_pico.menu.EraseFlash.none=Disabled +nologo_esp32s3_pico.menu.EraseFlash.none.upload.erase_cmd= +nologo_esp32s3_pico.menu.EraseFlash.all=Enabled +nologo_esp32s3_pico.menu.EraseFlash.all.upload.erase_cmd=-e + +nologo_esp32s3_pico.menu.ZigbeeMode.default=Disabled +nologo_esp32s3_pico.menu.ZigbeeMode.default.build.zigbee_mode= +nologo_esp32s3_pico.menu.ZigbeeMode.default.build.zigbee_libs= +nologo_esp32s3_pico.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +nologo_esp32s3_pico.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +nologo_esp32s3_pico.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +mhetesp32devkit.name=MH ET LIVE ESP32DevKIT + +mhetesp32devkit.bootloader.tool=esptool_py +mhetesp32devkit.bootloader.tool.default=esptool_py + +mhetesp32devkit.upload.tool=esptool_py +mhetesp32devkit.upload.tool.default=esptool_py +mhetesp32devkit.upload.tool.network=esp_ota + +mhetesp32devkit.upload.maximum_size=1310720 +mhetesp32devkit.upload.maximum_data_size=327680 +mhetesp32devkit.upload.flags= +mhetesp32devkit.upload.extra_flags= + +mhetesp32devkit.serial.disableDTR=true +mhetesp32devkit.serial.disableRTS=true + +mhetesp32devkit.build.tarch=xtensa +mhetesp32devkit.build.bootloader_addr=0x1000 +mhetesp32devkit.build.target=esp32 +mhetesp32devkit.build.mcu=esp32 +mhetesp32devkit.build.core=esp32 +mhetesp32devkit.build.variant=mhetesp32devkit +mhetesp32devkit.build.board=MH_ET_LIVE_ESP32DEVKIT + +mhetesp32devkit.build.f_cpu=240000000L +mhetesp32devkit.build.flash_mode=dio +mhetesp32devkit.build.flash_size=4MB +mhetesp32devkit.build.boot=dio +mhetesp32devkit.build.partitions=default +mhetesp32devkit.build.defines= + +mhetesp32devkit.menu.FlashFreq.80=80MHz +mhetesp32devkit.menu.FlashFreq.80.build.flash_freq=80m +mhetesp32devkit.menu.FlashFreq.40=40MHz +mhetesp32devkit.menu.FlashFreq.40.build.flash_freq=40m + +mhetesp32devkit.menu.PartitionScheme.default=Default +mhetesp32devkit.menu.PartitionScheme.default.build.partitions=default +mhetesp32devkit.menu.PartitionScheme.no_ota=No OTA (Large APP) +mhetesp32devkit.menu.PartitionScheme.no_ota.build.partitions=no_ota +mhetesp32devkit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +mhetesp32devkit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +mhetesp32devkit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +mhetesp32devkit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +mhetesp32devkit.menu.UploadSpeed.921600=921600 +mhetesp32devkit.menu.UploadSpeed.921600.upload.speed=921600 +mhetesp32devkit.menu.UploadSpeed.115200=115200 +mhetesp32devkit.menu.UploadSpeed.115200.upload.speed=115200 +mhetesp32devkit.menu.UploadSpeed.256000.windows=256000 +mhetesp32devkit.menu.UploadSpeed.256000.upload.speed=256000 +mhetesp32devkit.menu.UploadSpeed.230400.windows.upload.speed=256000 +mhetesp32devkit.menu.UploadSpeed.230400=230400 +mhetesp32devkit.menu.UploadSpeed.230400.upload.speed=230400 +mhetesp32devkit.menu.UploadSpeed.460800.linux=460800 +mhetesp32devkit.menu.UploadSpeed.460800.macosx=460800 +mhetesp32devkit.menu.UploadSpeed.460800.upload.speed=460800 +mhetesp32devkit.menu.UploadSpeed.512000.windows=512000 +mhetesp32devkit.menu.UploadSpeed.512000.upload.speed=512000 + +mhetesp32devkit.menu.DebugLevel.none=None +mhetesp32devkit.menu.DebugLevel.none.build.code_debug=0 +mhetesp32devkit.menu.DebugLevel.error=Error +mhetesp32devkit.menu.DebugLevel.error.build.code_debug=1 +mhetesp32devkit.menu.DebugLevel.warn=Warn +mhetesp32devkit.menu.DebugLevel.warn.build.code_debug=2 +mhetesp32devkit.menu.DebugLevel.info=Info +mhetesp32devkit.menu.DebugLevel.info.build.code_debug=3 +mhetesp32devkit.menu.DebugLevel.debug=Debug +mhetesp32devkit.menu.DebugLevel.debug.build.code_debug=4 +mhetesp32devkit.menu.DebugLevel.verbose=Verbose +mhetesp32devkit.menu.DebugLevel.verbose.build.code_debug=5 + +mhetesp32devkit.menu.EraseFlash.none=Disabled +mhetesp32devkit.menu.EraseFlash.none.upload.erase_cmd= +mhetesp32devkit.menu.EraseFlash.all=Enabled +mhetesp32devkit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +mhetesp32minikit.name=MH ET LIVE ESP32MiniKit + +mhetesp32minikit.bootloader.tool=esptool_py +mhetesp32minikit.bootloader.tool.default=esptool_py + +mhetesp32minikit.upload.tool=esptool_py +mhetesp32minikit.upload.tool.default=esptool_py +mhetesp32minikit.upload.tool.network=esp_ota + +mhetesp32minikit.upload.maximum_size=1310720 +mhetesp32minikit.upload.maximum_data_size=327680 +mhetesp32minikit.upload.flags= +mhetesp32minikit.upload.extra_flags= + +mhetesp32minikit.serial.disableDTR=true +mhetesp32minikit.serial.disableRTS=true + +mhetesp32minikit.build.tarch=xtensa +mhetesp32minikit.build.bootloader_addr=0x1000 +mhetesp32minikit.build.target=esp32 +mhetesp32minikit.build.mcu=esp32 +mhetesp32minikit.build.core=esp32 +mhetesp32minikit.build.variant=mhetesp32minikit +mhetesp32minikit.build.board=MH_ET_LIVE_ESP32MINIKIT + +mhetesp32minikit.build.f_cpu=240000000L +mhetesp32minikit.build.flash_mode=dio +mhetesp32minikit.build.flash_size=4MB +mhetesp32minikit.build.boot=dio +mhetesp32minikit.build.partitions=default +mhetesp32minikit.build.defines= + +mhetesp32minikit.menu.FlashFreq.80=80MHz +mhetesp32minikit.menu.FlashFreq.80.build.flash_freq=80m +mhetesp32minikit.menu.FlashFreq.40=40MHz +mhetesp32minikit.menu.FlashFreq.40.build.flash_freq=40m + +mhetesp32minikit.menu.PartitionScheme.default=Default with spiffs +mhetesp32minikit.menu.PartitionScheme.default.build.partitions=default +mhetesp32minikit.menu.PartitionScheme.defaultffat=Default with ffat +mhetesp32minikit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +mhetesp32minikit.menu.PartitionScheme.no_ota=No OTA (Large APP) +mhetesp32minikit.menu.PartitionScheme.no_ota.build.partitions=no_ota +mhetesp32minikit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +mhetesp32minikit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +mhetesp32minikit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +mhetesp32minikit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +mhetesp32minikit.menu.UploadSpeed.921600=921600 +mhetesp32minikit.menu.UploadSpeed.921600.upload.speed=921600 +mhetesp32minikit.menu.UploadSpeed.115200=115200 +mhetesp32minikit.menu.UploadSpeed.115200.upload.speed=115200 +mhetesp32minikit.menu.UploadSpeed.256000.windows=256000 +mhetesp32minikit.menu.UploadSpeed.256000.upload.speed=256000 +mhetesp32minikit.menu.UploadSpeed.230400.windows.upload.speed=256000 +mhetesp32minikit.menu.UploadSpeed.230400=230400 +mhetesp32minikit.menu.UploadSpeed.230400.upload.speed=230400 +mhetesp32minikit.menu.UploadSpeed.460800.linux=460800 +mhetesp32minikit.menu.UploadSpeed.460800.macosx=460800 +mhetesp32minikit.menu.UploadSpeed.460800.upload.speed=460800 +mhetesp32minikit.menu.UploadSpeed.512000.windows=512000 +mhetesp32minikit.menu.UploadSpeed.512000.upload.speed=512000 + +mhetesp32minikit.menu.DebugLevel.none=None +mhetesp32minikit.menu.DebugLevel.none.build.code_debug=0 +mhetesp32minikit.menu.DebugLevel.error=Error +mhetesp32minikit.menu.DebugLevel.error.build.code_debug=1 +mhetesp32minikit.menu.DebugLevel.warn=Warn +mhetesp32minikit.menu.DebugLevel.warn.build.code_debug=2 +mhetesp32minikit.menu.DebugLevel.info=Info +mhetesp32minikit.menu.DebugLevel.info.build.code_debug=3 +mhetesp32minikit.menu.DebugLevel.debug=Debug +mhetesp32minikit.menu.DebugLevel.debug.build.code_debug=4 +mhetesp32minikit.menu.DebugLevel.verbose=Verbose +mhetesp32minikit.menu.DebugLevel.verbose.build.code_debug=5 + +mhetesp32minikit.menu.EraseFlash.none=Disabled +mhetesp32minikit.menu.EraseFlash.none.upload.erase_cmd= +mhetesp32minikit.menu.EraseFlash.all=Enabled +mhetesp32minikit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32vn-iot-uno.name=ESP32vn IoT Uno + +esp32vn-iot-uno.bootloader.tool=esptool_py +esp32vn-iot-uno.bootloader.tool.default=esptool_py + +esp32vn-iot-uno.upload.tool=esptool_py +esp32vn-iot-uno.upload.tool.default=esptool_py +esp32vn-iot-uno.upload.tool.network=esp_ota + +esp32vn-iot-uno.upload.maximum_size=1310720 +esp32vn-iot-uno.upload.maximum_data_size=327680 +esp32vn-iot-uno.upload.flags= +esp32vn-iot-uno.upload.extra_flags= + +esp32vn-iot-uno.serial.disableDTR=true +esp32vn-iot-uno.serial.disableRTS=true + +esp32vn-iot-uno.build.tarch=xtensa +esp32vn-iot-uno.build.bootloader_addr=0x1000 +esp32vn-iot-uno.build.target=esp32 +esp32vn-iot-uno.build.mcu=esp32 +esp32vn-iot-uno.build.core=esp32 +esp32vn-iot-uno.build.variant=esp32vn-iot-uno +esp32vn-iot-uno.build.board=esp32vn_iot_uno + +esp32vn-iot-uno.build.f_cpu=240000000L +esp32vn-iot-uno.build.flash_mode=dio +esp32vn-iot-uno.build.flash_size=4MB +esp32vn-iot-uno.build.boot=dio +esp32vn-iot-uno.build.partitions=default +esp32vn-iot-uno.build.defines= + +esp32vn-iot-uno.menu.FlashFreq.80=80MHz +esp32vn-iot-uno.menu.FlashFreq.80.build.flash_freq=80m +esp32vn-iot-uno.menu.FlashFreq.40=40MHz +esp32vn-iot-uno.menu.FlashFreq.40.build.flash_freq=40m + +esp32vn-iot-uno.menu.UploadSpeed.921600=921600 +esp32vn-iot-uno.menu.UploadSpeed.921600.upload.speed=921600 +esp32vn-iot-uno.menu.UploadSpeed.115200=115200 +esp32vn-iot-uno.menu.UploadSpeed.115200.upload.speed=115200 +esp32vn-iot-uno.menu.UploadSpeed.256000.windows=256000 +esp32vn-iot-uno.menu.UploadSpeed.256000.upload.speed=256000 +esp32vn-iot-uno.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32vn-iot-uno.menu.UploadSpeed.230400=230400 +esp32vn-iot-uno.menu.UploadSpeed.230400.upload.speed=230400 +esp32vn-iot-uno.menu.UploadSpeed.460800.linux=460800 +esp32vn-iot-uno.menu.UploadSpeed.460800.macosx=460800 +esp32vn-iot-uno.menu.UploadSpeed.460800.upload.speed=460800 +esp32vn-iot-uno.menu.UploadSpeed.512000.windows=512000 +esp32vn-iot-uno.menu.UploadSpeed.512000.upload.speed=512000 + +esp32vn-iot-uno.menu.DebugLevel.none=None +esp32vn-iot-uno.menu.DebugLevel.none.build.code_debug=0 +esp32vn-iot-uno.menu.DebugLevel.error=Error +esp32vn-iot-uno.menu.DebugLevel.error.build.code_debug=1 +esp32vn-iot-uno.menu.DebugLevel.warn=Warn +esp32vn-iot-uno.menu.DebugLevel.warn.build.code_debug=2 +esp32vn-iot-uno.menu.DebugLevel.info=Info +esp32vn-iot-uno.menu.DebugLevel.info.build.code_debug=3 +esp32vn-iot-uno.menu.DebugLevel.debug=Debug +esp32vn-iot-uno.menu.DebugLevel.debug.build.code_debug=4 +esp32vn-iot-uno.menu.DebugLevel.verbose=Verbose +esp32vn-iot-uno.menu.DebugLevel.verbose.build.code_debug=5 + +esp32vn-iot-uno.menu.EraseFlash.none=Disabled +esp32vn-iot-uno.menu.EraseFlash.none.upload.erase_cmd= +esp32vn-iot-uno.menu.EraseFlash.all=Enabled +esp32vn-iot-uno.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32doit-devkit-v1.name=DOIT ESP32 DEVKIT V1 + +esp32doit-devkit-v1.bootloader.tool=esptool_py +esp32doit-devkit-v1.bootloader.tool.default=esptool_py + +esp32doit-devkit-v1.upload.tool=esptool_py +esp32doit-devkit-v1.upload.tool.default=esptool_py +esp32doit-devkit-v1.upload.tool.network=esp_ota + +esp32doit-devkit-v1.upload.maximum_size=1310720 +esp32doit-devkit-v1.upload.maximum_data_size=327680 +esp32doit-devkit-v1.upload.flags= +esp32doit-devkit-v1.upload.extra_flags= + +esp32doit-devkit-v1.serial.disableDTR=true +esp32doit-devkit-v1.serial.disableRTS=true + +esp32doit-devkit-v1.build.tarch=xtensa +esp32doit-devkit-v1.build.bootloader_addr=0x1000 +esp32doit-devkit-v1.build.target=esp32 +esp32doit-devkit-v1.build.mcu=esp32 +esp32doit-devkit-v1.build.core=esp32 +esp32doit-devkit-v1.build.variant=doitESP32devkitV1 +esp32doit-devkit-v1.build.board=ESP32_DEV + +esp32doit-devkit-v1.build.f_cpu=240000000L +esp32doit-devkit-v1.build.flash_mode=dio +esp32doit-devkit-v1.build.flash_size=4MB +esp32doit-devkit-v1.build.boot=dio +esp32doit-devkit-v1.build.partitions=default +esp32doit-devkit-v1.build.defines= + +esp32doit-devkit-v1.menu.FlashFreq.80=80MHz +esp32doit-devkit-v1.menu.FlashFreq.80.build.flash_freq=80m +esp32doit-devkit-v1.menu.FlashFreq.40=40MHz +esp32doit-devkit-v1.menu.FlashFreq.40.build.flash_freq=40m + +esp32doit-devkit-v1.menu.UploadSpeed.921600=921600 +esp32doit-devkit-v1.menu.UploadSpeed.921600.upload.speed=921600 +esp32doit-devkit-v1.menu.UploadSpeed.115200=115200 +esp32doit-devkit-v1.menu.UploadSpeed.115200.upload.speed=115200 +esp32doit-devkit-v1.menu.UploadSpeed.256000.windows=256000 +esp32doit-devkit-v1.menu.UploadSpeed.256000.upload.speed=256000 +esp32doit-devkit-v1.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32doit-devkit-v1.menu.UploadSpeed.230400=230400 +esp32doit-devkit-v1.menu.UploadSpeed.230400.upload.speed=230400 +esp32doit-devkit-v1.menu.UploadSpeed.460800.linux=460800 +esp32doit-devkit-v1.menu.UploadSpeed.460800.macosx=460800 +esp32doit-devkit-v1.menu.UploadSpeed.460800.upload.speed=460800 +esp32doit-devkit-v1.menu.UploadSpeed.512000.windows=512000 +esp32doit-devkit-v1.menu.UploadSpeed.512000.upload.speed=512000 + +esp32doit-devkit-v1.menu.DebugLevel.none=None +esp32doit-devkit-v1.menu.DebugLevel.none.build.code_debug=0 +esp32doit-devkit-v1.menu.DebugLevel.error=Error +esp32doit-devkit-v1.menu.DebugLevel.error.build.code_debug=1 +esp32doit-devkit-v1.menu.DebugLevel.warn=Warn +esp32doit-devkit-v1.menu.DebugLevel.warn.build.code_debug=2 +esp32doit-devkit-v1.menu.DebugLevel.info=Info +esp32doit-devkit-v1.menu.DebugLevel.info.build.code_debug=3 +esp32doit-devkit-v1.menu.DebugLevel.debug=Debug +esp32doit-devkit-v1.menu.DebugLevel.debug.build.code_debug=4 +esp32doit-devkit-v1.menu.DebugLevel.verbose=Verbose +esp32doit-devkit-v1.menu.DebugLevel.verbose.build.code_debug=5 + +esp32doit-devkit-v1.menu.EraseFlash.none=Disabled +esp32doit-devkit-v1.menu.EraseFlash.none.upload.erase_cmd= +esp32doit-devkit-v1.menu.EraseFlash.all=Enabled +esp32doit-devkit-v1.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32doit-espduino.name=DOIT ESPduino32 + +esp32doit-espduino.bootloader.tool=esptool_py +esp32doit-espduino.bootloader.tool.default=esptool_py + +esp32doit-espduino.upload.tool=esptool_py +esp32doit-espduino.upload.tool.default=esptool_py +esp32doit-espduino.upload.tool.network=esp_ota + +esp32doit-espduino.upload.maximum_size=1310720 +esp32doit-espduino.upload.maximum_data_size=327680 +esp32doit-espduino.upload.wait_for_upload_port=true +esp32doit-espduino.upload.flags= +esp32doit-espduino.upload.extra_flags= + +esp32doit-espduino.serial.disableDTR=true +esp32doit-espduino.serial.disableRTS=true + +esp32doit-espduino.build.tarch=xtensa +esp32doit-espduino.build.bootloader_addr=0x1000 +esp32doit-espduino.build.target=esp32 +esp32doit-espduino.build.mcu=esp32 +esp32doit-espduino.build.core=esp32 +esp32doit-espduino.build.variant=doitESPduino32 +esp32doit-espduino.build.board=ESP32_DEV + +esp32doit-espduino.build.f_cpu=240000000L +esp32doit-espduino.build.flash_mode=dio +esp32doit-espduino.build.flash_size=4MB +esp32doit-espduino.build.boot=dio +esp32doit-espduino.build.partitions=default +esp32doit-espduino.build.defines= + +esp32doit-espduino.menu.FlashFreq.80=80MHz +esp32doit-espduino.menu.FlashFreq.80.build.flash_freq=80m +esp32doit-espduino.menu.FlashFreq.40=40MHz +esp32doit-espduino.menu.FlashFreq.40.build.flash_freq=40m + +esp32doit-espduino.menu.PartitionScheme.default=Default +esp32doit-espduino.menu.PartitionScheme.default.build.partitions=default +esp32doit-espduino.menu.PartitionScheme.no_ota=No OTA (Large APP) +esp32doit-espduino.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32doit-espduino.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32doit-espduino.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +esp32doit-espduino.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32doit-espduino.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32doit-espduino.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32doit-espduino.menu.CPUFreq.240.build.f_cpu=240000000L +esp32doit-espduino.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32doit-espduino.menu.CPUFreq.160.build.f_cpu=160000000L +esp32doit-espduino.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32doit-espduino.menu.CPUFreq.80.build.f_cpu=80000000L +esp32doit-espduino.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32doit-espduino.menu.CPUFreq.40.build.f_cpu=40000000L +esp32doit-espduino.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32doit-espduino.menu.CPUFreq.26.build.f_cpu=26000000L +esp32doit-espduino.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32doit-espduino.menu.CPUFreq.20.build.f_cpu=20000000L +esp32doit-espduino.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32doit-espduino.menu.CPUFreq.13.build.f_cpu=13000000L +esp32doit-espduino.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32doit-espduino.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32doit-espduino.menu.UploadSpeed.921600=921600 +esp32doit-espduino.menu.UploadSpeed.921600.upload.speed=921600 +esp32doit-espduino.menu.UploadSpeed.115200=115200 +esp32doit-espduino.menu.UploadSpeed.115200.upload.speed=115200 +esp32doit-espduino.menu.UploadSpeed.256000.windows=256000 +esp32doit-espduino.menu.UploadSpeed.256000.upload.speed=256000 +esp32doit-espduino.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32doit-espduino.menu.UploadSpeed.230400=230400 +esp32doit-espduino.menu.UploadSpeed.230400.upload.speed=230400 +esp32doit-espduino.menu.UploadSpeed.460800.linux=460800 +esp32doit-espduino.menu.UploadSpeed.460800.macosx=460800 +esp32doit-espduino.menu.UploadSpeed.460800.upload.speed=460800 +esp32doit-espduino.menu.UploadSpeed.512000.windows=512000 +esp32doit-espduino.menu.UploadSpeed.512000.upload.speed=512000 + +esp32doit-espduino.menu.DebugLevel.none=None +esp32doit-espduino.menu.DebugLevel.none.build.code_debug=0 +esp32doit-espduino.menu.DebugLevel.error=Error +esp32doit-espduino.menu.DebugLevel.error.build.code_debug=1 +esp32doit-espduino.menu.DebugLevel.warn=Warn +esp32doit-espduino.menu.DebugLevel.warn.build.code_debug=2 +esp32doit-espduino.menu.DebugLevel.info=Info +esp32doit-espduino.menu.DebugLevel.info.build.code_debug=3 +esp32doit-espduino.menu.DebugLevel.debug=Debug +esp32doit-espduino.menu.DebugLevel.debug.build.code_debug=4 +esp32doit-espduino.menu.DebugLevel.verbose=Verbose +esp32doit-espduino.menu.DebugLevel.verbose.build.code_debug=5 + +esp32doit-espduino.menu.EraseFlash.none=Disabled +esp32doit-espduino.menu.EraseFlash.none.upload.erase_cmd= +esp32doit-espduino.menu.EraseFlash.all=Enabled +esp32doit-espduino.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-evb.name=OLIMEX ESP32-EVB + +esp32-evb.bootloader.tool=esptool_py +esp32-evb.bootloader.tool.default=esptool_py + +esp32-evb.upload.tool=esptool_py +esp32-evb.upload.tool.default=esptool_py +esp32-evb.upload.tool.network=esp_ota + +esp32-evb.upload.maximum_size=1310720 +esp32-evb.upload.maximum_data_size=327680 +esp32-evb.upload.flags= +esp32-evb.upload.extra_flags= + +esp32-evb.serial.disableDTR=true +esp32-evb.serial.disableRTS=true + +esp32-evb.build.tarch=xtensa +esp32-evb.build.bootloader_addr=0x1000 +esp32-evb.build.target=esp32 +esp32-evb.build.mcu=esp32 +esp32-evb.build.core=esp32 +esp32-evb.build.variant=esp32-evb +esp32-evb.build.board=ESP32_EVB + +esp32-evb.build.f_cpu=240000000L +esp32-evb.build.flash_mode=dio +esp32-evb.build.flash_size=4MB +esp32-evb.build.boot=dio +esp32-evb.build.partitions=default +esp32-evb.build.defines= + +esp32-evb.menu.FlashFreq.80=80MHz +esp32-evb.menu.FlashFreq.80.build.flash_freq=80m +esp32-evb.menu.FlashFreq.40=40MHz +esp32-evb.menu.FlashFreq.40.build.flash_freq=40m + +esp32-evb.menu.UploadSpeed.921600=921600 +esp32-evb.menu.UploadSpeed.921600.upload.speed=921600 +esp32-evb.menu.UploadSpeed.115200=115200 +esp32-evb.menu.UploadSpeed.115200.upload.speed=115200 +esp32-evb.menu.UploadSpeed.256000.windows=256000 +esp32-evb.menu.UploadSpeed.256000.upload.speed=256000 +esp32-evb.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-evb.menu.UploadSpeed.230400=230400 +esp32-evb.menu.UploadSpeed.230400.upload.speed=230400 +esp32-evb.menu.UploadSpeed.460800.linux=460800 +esp32-evb.menu.UploadSpeed.460800.macosx=460800 +esp32-evb.menu.UploadSpeed.460800.upload.speed=460800 +esp32-evb.menu.UploadSpeed.512000.windows=512000 +esp32-evb.menu.UploadSpeed.512000.upload.speed=512000 + +esp32-evb.menu.PartitionScheme.default=Default +esp32-evb.menu.PartitionScheme.default.build.partitions=default +esp32-evb.menu.PartitionScheme.no_ota=No OTA (Large APP) +esp32-evb.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-evb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-evb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +esp32-evb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-evb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32-evb.menu.DebugLevel.none=None +esp32-evb.menu.DebugLevel.none.build.code_debug=0 +esp32-evb.menu.DebugLevel.error=Error +esp32-evb.menu.DebugLevel.error.build.code_debug=1 +esp32-evb.menu.DebugLevel.warn=Warn +esp32-evb.menu.DebugLevel.warn.build.code_debug=2 +esp32-evb.menu.DebugLevel.info=Info +esp32-evb.menu.DebugLevel.info.build.code_debug=3 +esp32-evb.menu.DebugLevel.debug=Debug +esp32-evb.menu.DebugLevel.debug.build.code_debug=4 +esp32-evb.menu.DebugLevel.verbose=Verbose +esp32-evb.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-evb.menu.EraseFlash.none=Disabled +esp32-evb.menu.EraseFlash.none.upload.erase_cmd= +esp32-evb.menu.EraseFlash.all=Enabled +esp32-evb.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-gateway.name=OLIMEX ESP32-GATEWAY + +esp32-gateway.bootloader.tool=esptool_py +esp32-gateway.bootloader.tool.default=esptool_py + +esp32-gateway.upload.tool=esptool_py +esp32-gateway.upload.tool.default=esptool_py +esp32-gateway.upload.tool.network=esp_ota + +esp32-gateway.upload.maximum_size=1310720 +esp32-gateway.upload.maximum_data_size=327680 +esp32-gateway.upload.flags= +esp32-gateway.upload.extra_flags= + +esp32-gateway.serial.disableDTR=true +esp32-gateway.serial.disableRTS=true + +esp32-gateway.build.tarch=xtensa +esp32-gateway.build.bootloader_addr=0x1000 +esp32-gateway.build.target=esp32 +esp32-gateway.build.mcu=esp32 +esp32-gateway.build.core=esp32 +esp32-gateway.build.variant=esp32-gateway +esp32-gateway.build.board=ESP32_GATEWAY +esp32-gateway.menu.Revision.RevC=Revision C or older +esp32-gateway.menu.Revision.RevC.build.board=ESP32_GATEWAY_C +esp32-gateway.menu.Revision.RevE=Revision E +esp32-gateway.menu.Revision.RevE.build.board=ESP32_GATEWAY_E +esp32-gateway.menu.Revision.RevF=Revision F or newer +esp32-gateway.menu.Revision.RevF.build.board=ESP32_GATEWAY_F + +esp32-gateway.build.f_cpu=240000000L +esp32-gateway.build.flash_mode=dio +esp32-gateway.build.flash_size=4MB +esp32-gateway.build.boot=dio +esp32-gateway.build.partitions=default +esp32-gateway.build.defines= + +esp32-gateway.menu.FlashFreq.80=80MHz +esp32-gateway.menu.FlashFreq.80.build.flash_freq=80m +esp32-gateway.menu.FlashFreq.40=40MHz +esp32-gateway.menu.FlashFreq.40.build.flash_freq=40m + +esp32-gateway.menu.UploadSpeed.921600=921600 +esp32-gateway.menu.UploadSpeed.921600.upload.speed=921600 +esp32-gateway.menu.UploadSpeed.115200=115200 +esp32-gateway.menu.UploadSpeed.115200.upload.speed=115200 + +esp32-gateway.menu.PartitionScheme.default=Default +esp32-gateway.menu.PartitionScheme.default.build.partitions=default +esp32-gateway.menu.PartitionScheme.no_ota=No OTA (Large APP) +esp32-gateway.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-gateway.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-gateway.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +esp32-gateway.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-gateway.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32-gateway.menu.DebugLevel.none=None +esp32-gateway.menu.DebugLevel.none.build.code_debug=0 +esp32-gateway.menu.DebugLevel.error=Error +esp32-gateway.menu.DebugLevel.error.build.code_debug=1 +esp32-gateway.menu.DebugLevel.warn=Warn +esp32-gateway.menu.DebugLevel.warn.build.code_debug=2 +esp32-gateway.menu.DebugLevel.info=Info +esp32-gateway.menu.DebugLevel.info.build.code_debug=3 +esp32-gateway.menu.DebugLevel.debug=Debug +esp32-gateway.menu.DebugLevel.debug.build.code_debug=4 +esp32-gateway.menu.DebugLevel.verbose=Verbose +esp32-gateway.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-gateway.menu.EraseFlash.none=Disabled +esp32-gateway.menu.EraseFlash.none.upload.erase_cmd= +esp32-gateway.menu.EraseFlash.all=Enabled +esp32-gateway.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-poe.name=OLIMEX ESP32-POE + +esp32-poe.bootloader.tool=esptool_py +esp32-poe.bootloader.tool.default=esptool_py + +esp32-poe.upload.tool=esptool_py +esp32-poe.upload.tool.default=esptool_py +esp32-poe.upload.tool.network=esp_ota + +esp32-poe.upload.maximum_size=1310720 +esp32-poe.upload.maximum_data_size=327680 +esp32-poe.upload.flags= +esp32-poe.upload.extra_flags= + +esp32-poe.serial.disableDTR=true +esp32-poe.serial.disableRTS=true + +esp32-poe.build.tarch=xtensa +esp32-poe.build.bootloader_addr=0x1000 +esp32-poe.build.target=esp32 +esp32-poe.build.mcu=esp32 +esp32-poe.build.core=esp32 +esp32-poe.build.variant=esp32-poe +esp32-poe.build.board=ESP32_POE + +esp32-poe.build.f_cpu=240000000L +esp32-poe.build.flash_size=4MB +esp32-poe.build.flash_freq=40m +esp32-poe.build.flash_mode=dio +esp32-poe.build.boot=dio +esp32-poe.build.partitions=default +esp32-poe.build.defines= +esp32-poe.build.loop_core= +esp32-poe.build.event_core= + +esp32-poe.menu.PSRAM.disabled=Disabled (WROOM) +esp32-poe.menu.PSRAM.disabled.build.defines= +esp32-poe.menu.PSRAM.disabled.build.extra_libs= +esp32-poe.menu.PSRAM.enabled=Enabled (WROVER) +esp32-poe.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32-poe.menu.PSRAM.enabled.build.extra_libs= + +esp32-poe.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32-poe.menu.PartitionScheme.default.build.partitions=default +esp32-poe.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32-poe.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32-poe.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32-poe.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32-poe.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32-poe.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32-poe.menu.PartitionScheme.minimal.build.partitions=minimal +esp32-poe.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32-poe.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-poe.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-poe.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32-poe.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32-poe.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32-poe.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32-poe.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32-poe.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32-poe.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32-poe.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32-poe.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32-poe.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32-poe.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32-poe.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32-poe.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32-poe.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-poe.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32-poe.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32-poe.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32-poe.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32-poe.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32-poe.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32-poe.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32-poe.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32-poe.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32-poe.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32-poe.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32-poe.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32-poe.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32-poe.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32-poe.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32-poe.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32-poe.menu.PartitionScheme.custom=Custom +esp32-poe.menu.PartitionScheme.custom.build.partitions= +esp32-poe.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32-poe.menu.FlashMode.qio=QIO +esp32-poe.menu.FlashMode.qio.build.flash_mode=dio +esp32-poe.menu.FlashMode.qio.build.boot=qio +esp32-poe.menu.FlashMode.dio=DIO +esp32-poe.menu.FlashMode.dio.build.flash_mode=dio +esp32-poe.menu.FlashMode.dio.build.boot=dio + +esp32-poe.menu.FlashFreq.80=80MHz +esp32-poe.menu.FlashFreq.80.build.flash_freq=80m +esp32-poe.menu.FlashFreq.40=40MHz +esp32-poe.menu.FlashFreq.40.build.flash_freq=40m + +esp32-poe.menu.FlashSize.4M=4MB (32Mb) +esp32-poe.menu.FlashSize.4M.build.flash_size=4MB +esp32-poe.menu.FlashSize.16M=16MB (128Mb) +esp32-poe.menu.FlashSize.16M.build.flash_size=16MB + +esp32-poe.menu.UploadSpeed.921600=921600 +esp32-poe.menu.UploadSpeed.921600.upload.speed=921600 +esp32-poe.menu.UploadSpeed.115200=115200 +esp32-poe.menu.UploadSpeed.115200.upload.speed=115200 +esp32-poe.menu.UploadSpeed.256000.windows=256000 +esp32-poe.menu.UploadSpeed.256000.upload.speed=256000 +esp32-poe.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-poe.menu.UploadSpeed.230400=230400 +esp32-poe.menu.UploadSpeed.230400.upload.speed=230400 +esp32-poe.menu.UploadSpeed.460800.linux=460800 +esp32-poe.menu.UploadSpeed.460800.macosx=460800 +esp32-poe.menu.UploadSpeed.460800.upload.speed=460800 +esp32-poe.menu.UploadSpeed.512000.windows=512000 +esp32-poe.menu.UploadSpeed.512000.upload.speed=512000 + +esp32-poe.menu.DebugLevel.none=None +esp32-poe.menu.DebugLevel.none.build.code_debug=0 +esp32-poe.menu.DebugLevel.error=Error +esp32-poe.menu.DebugLevel.error.build.code_debug=1 +esp32-poe.menu.DebugLevel.warn=Warn +esp32-poe.menu.DebugLevel.warn.build.code_debug=2 +esp32-poe.menu.DebugLevel.info=Info +esp32-poe.menu.DebugLevel.info.build.code_debug=3 +esp32-poe.menu.DebugLevel.debug=Debug +esp32-poe.menu.DebugLevel.debug.build.code_debug=4 +esp32-poe.menu.DebugLevel.verbose=Verbose +esp32-poe.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-poe.menu.EraseFlash.none=Disabled +esp32-poe.menu.EraseFlash.none.upload.erase_cmd= +esp32-poe.menu.EraseFlash.all=Enabled +esp32-poe.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-poe-iso.name=OLIMEX ESP32-POE-ISO + +esp32-poe-iso.bootloader.tool=esptool_py +esp32-poe-iso.bootloader.tool.default=esptool_py + +esp32-poe-iso.upload.tool=esptool_py +esp32-poe-iso.upload.tool.default=esptool_py +esp32-poe-iso.upload.tool.network=esp_ota + +esp32-poe-iso.upload.maximum_size=1310720 +esp32-poe-iso.upload.maximum_data_size=327680 +esp32-poe-iso.upload.flags= +esp32-poe-iso.upload.extra_flags= + +esp32-poe-iso.serial.disableDTR=true +esp32-poe-iso.serial.disableRTS=true + +esp32-poe-iso.build.tarch=xtensa +esp32-poe-iso.build.bootloader_addr=0x1000 +esp32-poe-iso.build.target=esp32 +esp32-poe-iso.build.mcu=esp32 +esp32-poe-iso.build.core=esp32 +esp32-poe-iso.build.variant=esp32-poe-iso +esp32-poe-iso.build.board=ESP32_POE_ISO + +esp32-poe-iso.build.f_cpu=240000000L +esp32-poe-iso.build.flash_size=4MB +esp32-poe-iso.build.flash_freq=40m +esp32-poe-iso.build.flash_mode=dio +esp32-poe-iso.build.boot=dio +esp32-poe-iso.build.partitions=default +esp32-poe-iso.build.defines= +esp32-poe-iso.build.loop_core= +esp32-poe-iso.build.event_core= + +esp32-poe-iso.menu.PSRAM.disabled=Disabled (WROOM) +esp32-poe-iso.menu.PSRAM.disabled.build.defines= +esp32-poe-iso.menu.PSRAM.disabled.build.extra_libs= +esp32-poe-iso.menu.PSRAM.enabled=Enabled (WROVER) +esp32-poe-iso.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32-poe-iso.menu.PSRAM.enabled.build.extra_libs= + +esp32-poe-iso.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.default.build.partitions=default +esp32-poe-iso.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32-poe-iso.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32-poe-iso.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32-poe-iso.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32-poe-iso.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.minimal.build.partitions=minimal +esp32-poe-iso.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-poe-iso.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-poe-iso.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32-poe-iso.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32-poe-iso.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32-poe-iso.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32-poe-iso.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32-poe-iso.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32-poe-iso.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32-poe-iso.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32-poe-iso.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32-poe-iso.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32-poe-iso.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32-poe-iso.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-poe-iso.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32-poe-iso.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32-poe-iso.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32-poe-iso.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32-poe-iso.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32-poe-iso.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32-poe-iso.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32-poe-iso.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32-poe-iso.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32-poe-iso.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32-poe-iso.menu.PartitionScheme.custom=Custom +esp32-poe-iso.menu.PartitionScheme.custom.build.partitions= +esp32-poe-iso.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32-poe-iso.menu.FlashMode.qio=QIO +esp32-poe-iso.menu.FlashMode.qio.build.flash_mode=dio +esp32-poe-iso.menu.FlashMode.qio.build.boot=qio +esp32-poe-iso.menu.FlashMode.dio=DIO +esp32-poe-iso.menu.FlashMode.dio.build.flash_mode=dio +esp32-poe-iso.menu.FlashMode.dio.build.boot=dio + +esp32-poe-iso.menu.FlashFreq.80=80MHz +esp32-poe-iso.menu.FlashFreq.80.build.flash_freq=80m +esp32-poe-iso.menu.FlashFreq.40=40MHz +esp32-poe-iso.menu.FlashFreq.40.build.flash_freq=40m + +esp32-poe-iso.menu.FlashSize.4M=4MB (32Mb) +esp32-poe-iso.menu.FlashSize.4M.build.flash_size=4MB +esp32-poe-iso.menu.FlashSize.16M=16MB (128Mb) +esp32-poe-iso.menu.FlashSize.16M.build.flash_size=16MB + +esp32-poe-iso.menu.UploadSpeed.921600=921600 +esp32-poe-iso.menu.UploadSpeed.921600.upload.speed=921600 +esp32-poe-iso.menu.UploadSpeed.115200=115200 +esp32-poe-iso.menu.UploadSpeed.115200.upload.speed=115200 +esp32-poe-iso.menu.UploadSpeed.256000.windows=256000 +esp32-poe-iso.menu.UploadSpeed.256000.upload.speed=256000 +esp32-poe-iso.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-poe-iso.menu.UploadSpeed.230400=230400 +esp32-poe-iso.menu.UploadSpeed.230400.upload.speed=230400 +esp32-poe-iso.menu.UploadSpeed.460800.linux=460800 +esp32-poe-iso.menu.UploadSpeed.460800.macosx=460800 +esp32-poe-iso.menu.UploadSpeed.460800.upload.speed=460800 +esp32-poe-iso.menu.UploadSpeed.512000.windows=512000 +esp32-poe-iso.menu.UploadSpeed.512000.upload.speed=512000 + +esp32-poe-iso.menu.DebugLevel.none=None +esp32-poe-iso.menu.DebugLevel.none.build.code_debug=0 +esp32-poe-iso.menu.DebugLevel.error=Error +esp32-poe-iso.menu.DebugLevel.error.build.code_debug=1 +esp32-poe-iso.menu.DebugLevel.warn=Warn +esp32-poe-iso.menu.DebugLevel.warn.build.code_debug=2 +esp32-poe-iso.menu.DebugLevel.info=Info +esp32-poe-iso.menu.DebugLevel.info.build.code_debug=3 +esp32-poe-iso.menu.DebugLevel.debug=Debug +esp32-poe-iso.menu.DebugLevel.debug.build.code_debug=4 +esp32-poe-iso.menu.DebugLevel.verbose=Verbose +esp32-poe-iso.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-poe-iso.menu.EraseFlash.none=Disabled +esp32-poe-iso.menu.EraseFlash.none.upload.erase_cmd= +esp32-poe-iso.menu.EraseFlash.all=Enabled +esp32-poe-iso.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-devkitlipo.name=OLIMEX ESP32-DevKit-LiPo + +esp32-devkitlipo.bootloader.tool=esptool_py +esp32-devkitlipo.bootloader.tool.default=esptool_py + +esp32-devkitlipo.upload.tool=esptool_py +esp32-devkitlipo.upload.tool.default=esptool_py +esp32-devkitlipo.upload.tool.network=esp_ota + +esp32-devkitlipo.upload.maximum_size=1310720 +esp32-devkitlipo.upload.maximum_data_size=327680 +esp32-devkitlipo.upload.flags= +esp32-devkitlipo.upload.extra_flags= + +esp32-devkitlipo.serial.disableDTR=true +esp32-devkitlipo.serial.disableRTS=true + +esp32-devkitlipo.build.tarch=xtensa +esp32-devkitlipo.build.bootloader_addr=0x1000 +esp32-devkitlipo.build.target=esp32 +esp32-devkitlipo.build.mcu=esp32 +esp32-devkitlipo.build.core=esp32 +esp32-devkitlipo.build.variant=esp32-devkit-lipo +esp32-devkitlipo.build.board=ESP32_DEVKIT_LIPO + +esp32-devkitlipo.build.f_cpu=240000000L +esp32-devkitlipo.build.flash_size=4MB +esp32-devkitlipo.build.flash_freq=40m +esp32-devkitlipo.build.flash_mode=dio +esp32-devkitlipo.build.boot=dio +esp32-devkitlipo.build.partitions=default +esp32-devkitlipo.build.defines= + +esp32-devkitlipo.menu.PSRAM.disabled=Disabled (WROOM) +esp32-devkitlipo.menu.PSRAM.disabled.build.defines= +esp32-devkitlipo.menu.PSRAM.disabled.build.extra_libs= +esp32-devkitlipo.menu.PSRAM.enabled=Enabled (WROVER) +esp32-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32-devkitlipo.menu.PSRAM.enabled.build.extra_libs= + +esp32-devkitlipo.menu.PartitionScheme.default=Default +esp32-devkitlipo.menu.PartitionScheme.default.build.partitions=default +esp32-devkitlipo.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +esp32-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal +esp32-devkitlipo.menu.PartitionScheme.no_ota=No OTA (Large APP) +esp32-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA) +esp32-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +esp32-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +esp32-devkitlipo.menu.FlashMode.qio=QIO +esp32-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio +esp32-devkitlipo.menu.FlashMode.qio.build.boot=qio +esp32-devkitlipo.menu.FlashMode.dio=DIO +esp32-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio +esp32-devkitlipo.menu.FlashMode.dio.build.boot=dio + +esp32-devkitlipo.menu.FlashFreq.80=80MHz +esp32-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m +esp32-devkitlipo.menu.FlashFreq.40=40MHz +esp32-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m + +esp32-devkitlipo.menu.UploadSpeed.921600=921600 +esp32-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600 +esp32-devkitlipo.menu.UploadSpeed.115200=115200 +esp32-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200 +esp32-devkitlipo.menu.UploadSpeed.256000.windows=256000 +esp32-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000 +esp32-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-devkitlipo.menu.UploadSpeed.230400=230400 +esp32-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400 +esp32-devkitlipo.menu.UploadSpeed.460800.linux=460800 +esp32-devkitlipo.menu.UploadSpeed.460800.macosx=460800 +esp32-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800 +esp32-devkitlipo.menu.UploadSpeed.512000.windows=512000 +esp32-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000 + +esp32-devkitlipo.menu.DebugLevel.none=None +esp32-devkitlipo.menu.DebugLevel.none.build.code_debug=0 +esp32-devkitlipo.menu.DebugLevel.error=Error +esp32-devkitlipo.menu.DebugLevel.error.build.code_debug=1 +esp32-devkitlipo.menu.DebugLevel.warn=Warn +esp32-devkitlipo.menu.DebugLevel.warn.build.code_debug=2 +esp32-devkitlipo.menu.DebugLevel.info=Info +esp32-devkitlipo.menu.DebugLevel.info.build.code_debug=3 +esp32-devkitlipo.menu.DebugLevel.debug=Debug +esp32-devkitlipo.menu.DebugLevel.debug.build.code_debug=4 +esp32-devkitlipo.menu.DebugLevel.verbose=Verbose +esp32-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-devkitlipo.menu.EraseFlash.none=Disabled +esp32-devkitlipo.menu.EraseFlash.none.upload.erase_cmd= +esp32-devkitlipo.menu.EraseFlash.all=Enabled +esp32-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s2-devkitlipo.name=OLIMEX ESP32-S2-DevKit-Lipo + +esp32s2-devkitlipo.bootloader.tool=esptool_py +esp32s2-devkitlipo.bootloader.tool.default=esptool_py + +esp32s2-devkitlipo.upload.tool=esptool_py +esp32s2-devkitlipo.upload.tool.default=esptool_py +esp32s2-devkitlipo.upload.tool.network=esp_ota + +esp32s2-devkitlipo.upload.maximum_size=1310720 +esp32s2-devkitlipo.upload.maximum_data_size=327680 +esp32s2-devkitlipo.upload.flags= +esp32s2-devkitlipo.upload.extra_flags= +esp32s2-devkitlipo.upload.use_1200bps_touch=false +esp32s2-devkitlipo.upload.wait_for_upload_port=false + +esp32s2-devkitlipo.serial.disableDTR=false +esp32s2-devkitlipo.serial.disableRTS=false + +esp32s2-devkitlipo.build.tarch=xtensa +esp32s2-devkitlipo.build.bootloader_addr=0x1000 +esp32s2-devkitlipo.build.target=esp32s2 +esp32s2-devkitlipo.build.mcu=esp32s2 +esp32s2-devkitlipo.build.core=esp32 +esp32s2-devkitlipo.build.variant=esp32s2-devkit-lipo +esp32s2-devkitlipo.build.board=ESP32S2_DEVKIT_LIPO + +esp32s2-devkitlipo.build.cdc_on_boot=0 +esp32s2-devkitlipo.build.msc_on_boot=0 +esp32s2-devkitlipo.build.dfu_on_boot=0 +esp32s2-devkitlipo.build.f_cpu=240000000L +esp32s2-devkitlipo.build.flash_size=4MB +esp32s2-devkitlipo.build.flash_freq=80m +esp32s2-devkitlipo.build.flash_mode=dio +esp32s2-devkitlipo.build.boot=qio +esp32s2-devkitlipo.build.partitions=default +esp32s2-devkitlipo.build.defines= + +esp32s2-devkitlipo.menu.JTAGAdapter.default=Disabled +esp32s2-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s2-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter +esp32s2-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg +esp32s2-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s2-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s2-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg +esp32s2-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s2-devkitlipo.menu.CDCOnBoot.default=Disabled +esp32s2-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32s2-devkitlipo.menu.CDCOnBoot.cdc=Enabled +esp32s2-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32s2-devkitlipo.menu.MSCOnBoot.default=Disabled +esp32s2-devkitlipo.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s2-devkitlipo.menu.MSCOnBoot.msc=Enabled +esp32s2-devkitlipo.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s2-devkitlipo.menu.DFUOnBoot.default=Disabled +esp32s2-devkitlipo.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s2-devkitlipo.menu.DFUOnBoot.dfu=Enabled +esp32s2-devkitlipo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s2-devkitlipo.menu.UploadMode.default=UART0 +esp32s2-devkitlipo.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s2-devkitlipo.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s2-devkitlipo.menu.UploadMode.cdc=Internal USB +esp32s2-devkitlipo.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s2-devkitlipo.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s2-devkitlipo.menu.PSRAM.disabled=Disabled (WROOM) +esp32s2-devkitlipo.menu.PSRAM.disabled.build.defines= +esp32s2-devkitlipo.menu.PSRAM.enabled=Enabled (WROVER) +esp32s2-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32s2-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.default.build.partitions=default +esp32s2-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s2-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s2-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s2-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s2-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s2-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s2-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s2-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s2-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s2-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s2-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s2-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s2-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s2-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s2-devkitlipo.menu.PartitionScheme.custom=Custom +esp32s2-devkitlipo.menu.PartitionScheme.custom.build.partitions= +esp32s2-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s2-devkitlipo.menu.CPUFreq.240=240MHz (WiFi) +esp32s2-devkitlipo.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s2-devkitlipo.menu.CPUFreq.160=160MHz (WiFi) +esp32s2-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s2-devkitlipo.menu.CPUFreq.80=80MHz (WiFi) +esp32s2-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s2-devkitlipo.menu.CPUFreq.40=40MHz +esp32s2-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s2-devkitlipo.menu.CPUFreq.20=20MHz +esp32s2-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s2-devkitlipo.menu.CPUFreq.10=10MHz +esp32s2-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s2-devkitlipo.menu.FlashMode.qio=QIO +esp32s2-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio +esp32s2-devkitlipo.menu.FlashMode.qio.build.boot=qio +esp32s2-devkitlipo.menu.FlashMode.dio=DIO +esp32s2-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio +esp32s2-devkitlipo.menu.FlashMode.dio.build.boot=dio +esp32s2-devkitlipo.menu.FlashMode.qout=QOUT +esp32s2-devkitlipo.menu.FlashMode.qout.build.flash_mode=dout +esp32s2-devkitlipo.menu.FlashMode.qout.build.boot=qout +esp32s2-devkitlipo.menu.FlashMode.dout=DOUT +esp32s2-devkitlipo.menu.FlashMode.dout.build.flash_mode=dout +esp32s2-devkitlipo.menu.FlashMode.dout.build.boot=dout + +esp32s2-devkitlipo.menu.FlashFreq.80=80MHz +esp32s2-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m +esp32s2-devkitlipo.menu.FlashFreq.40=40MHz +esp32s2-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m + +esp32s2-devkitlipo.menu.FlashSize.4M=4MB (32Mb) +esp32s2-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB +esp32s2-devkitlipo.menu.FlashSize.8M=8MB (64Mb) +esp32s2-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB +esp32s2-devkitlipo.menu.FlashSize.2M=2MB (16Mb) +esp32s2-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB +esp32s2-devkitlipo.menu.FlashSize.16M=16MB (128Mb) +esp32s2-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB + +esp32s2-devkitlipo.menu.UploadSpeed.921600=921600 +esp32s2-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600 +esp32s2-devkitlipo.menu.UploadSpeed.115200=115200 +esp32s2-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200 +esp32s2-devkitlipo.menu.UploadSpeed.256000.windows=256000 +esp32s2-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000 +esp32s2-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s2-devkitlipo.menu.UploadSpeed.230400=230400 +esp32s2-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400 +esp32s2-devkitlipo.menu.UploadSpeed.460800.linux=460800 +esp32s2-devkitlipo.menu.UploadSpeed.460800.macosx=460800 +esp32s2-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800 +esp32s2-devkitlipo.menu.UploadSpeed.512000.windows=512000 +esp32s2-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s2-devkitlipo.menu.DebugLevel.none=None +esp32s2-devkitlipo.menu.DebugLevel.none.build.code_debug=0 +esp32s2-devkitlipo.menu.DebugLevel.error=Error +esp32s2-devkitlipo.menu.DebugLevel.error.build.code_debug=1 +esp32s2-devkitlipo.menu.DebugLevel.warn=Warn +esp32s2-devkitlipo.menu.DebugLevel.warn.build.code_debug=2 +esp32s2-devkitlipo.menu.DebugLevel.info=Info +esp32s2-devkitlipo.menu.DebugLevel.info.build.code_debug=3 +esp32s2-devkitlipo.menu.DebugLevel.debug=Debug +esp32s2-devkitlipo.menu.DebugLevel.debug.build.code_debug=4 +esp32s2-devkitlipo.menu.DebugLevel.verbose=Verbose +esp32s2-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s2-devkitlipo.menu.EraseFlash.none=Disabled +esp32s2-devkitlipo.menu.EraseFlash.none.upload.erase_cmd= +esp32s2-devkitlipo.menu.EraseFlash.all=Enabled +esp32s2-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s2-devkitlipo-usb.name=OLIMEX ESP32-S2-DevKit-Lipo-USB + +esp32s2-devkitlipo-usb.bootloader.tool=esptool_py +esp32s2-devkitlipo-usb.bootloader.tool.default=esptool_py + +esp32s2-devkitlipo-usb.upload.tool=esptool_py +esp32s2-devkitlipo-usb.upload.tool.default=esptool_py +esp32s2-devkitlipo-usb.upload.tool.network=esp_ota + +esp32s2-devkitlipo-usb.upload.maximum_size=1310720 +esp32s2-devkitlipo-usb.upload.maximum_data_size=327680 +esp32s2-devkitlipo-usb.upload.flags= +esp32s2-devkitlipo-usb.upload.extra_flags= +esp32s2-devkitlipo-usb.upload.use_1200bps_touch=false +esp32s2-devkitlipo-usb.upload.wait_for_upload_port=false + +esp32s2-devkitlipo-usb.serial.disableDTR=false +esp32s2-devkitlipo-usb.serial.disableRTS=false + +esp32s2-devkitlipo-usb.build.tarch=xtensa +esp32s2-devkitlipo-usb.build.bootloader_addr=0x1000 +esp32s2-devkitlipo-usb.build.target=esp32s2 +esp32s2-devkitlipo-usb.build.mcu=esp32s2 +esp32s2-devkitlipo-usb.build.core=esp32 +esp32s2-devkitlipo-usb.build.variant=esp32s2-devkit-lipo-usb +esp32s2-devkitlipo-usb.build.board=ESP32S2_DEVKIT_LIPO_USB + +esp32s2-devkitlipo-usb.build.cdc_on_boot=0 +esp32s2-devkitlipo-usb.build.msc_on_boot=0 +esp32s2-devkitlipo-usb.build.dfu_on_boot=0 +esp32s2-devkitlipo-usb.build.f_cpu=240000000L +esp32s2-devkitlipo-usb.build.flash_size=4MB +esp32s2-devkitlipo-usb.build.flash_freq=80m +esp32s2-devkitlipo-usb.build.flash_mode=dio +esp32s2-devkitlipo-usb.build.boot=qio +esp32s2-devkitlipo-usb.build.partitions=default +esp32s2-devkitlipo-usb.build.defines= + +esp32s2-devkitlipo-usb.menu.JTAGAdapter.default=Disabled +esp32s2-devkitlipo-usb.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s2-devkitlipo-usb.menu.JTAGAdapter.external=FTDI Adapter +esp32s2-devkitlipo-usb.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg +esp32s2-devkitlipo-usb.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg +esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s2-devkitlipo-usb.menu.CDCOnBoot.default=Enabled +esp32s2-devkitlipo-usb.menu.CDCOnBoot.default.build.cdc_on_boot=1 +esp32s2-devkitlipo-usb.menu.CDCOnBoot.cdc=Disabled +esp32s2-devkitlipo-usb.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +esp32s2-devkitlipo-usb.menu.MSCOnBoot.default=Disabled +esp32s2-devkitlipo-usb.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s2-devkitlipo-usb.menu.MSCOnBoot.msc=Enabled +esp32s2-devkitlipo-usb.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s2-devkitlipo-usb.menu.DFUOnBoot.default=Enabled +esp32s2-devkitlipo-usb.menu.DFUOnBoot.default.build.dfu_on_boot=1 +esp32s2-devkitlipo-usb.menu.DFUOnBoot.dfu=Disabled +esp32s2-devkitlipo-usb.menu.DFUOnBoot.dfu.build.dfu_on_boot=0 + +esp32s2-devkitlipo-usb.menu.UploadMode.default=Internal USB +esp32s2-devkitlipo-usb.menu.UploadMode.default.upload.use_1200bps_touch=true +esp32s2-devkitlipo-usb.menu.UploadMode.default.upload.wait_for_upload_port=true +esp32s2-devkitlipo-usb.menu.UploadMode.UART0=UART0 +esp32s2-devkitlipo-usb.menu.UploadMode.UART0.upload.use_1200bps_touch=false +esp32s2-devkitlipo-usb.menu.UploadMode.UART0.upload.wait_for_upload_port=false + +esp32s2-devkitlipo-usb.menu.PSRAM.disabled=Disabled (WROOM) +esp32s2-devkitlipo-usb.menu.PSRAM.disabled.build.defines= +esp32s2-devkitlipo-usb.menu.PSRAM.enabled=Enabled (WROVER) +esp32s2-devkitlipo-usb.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32s2-devkitlipo-usb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.default.build.partitions=default +esp32s2-devkitlipo-usb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s2-devkitlipo-usb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s2-devkitlipo-usb.menu.PartitionScheme.custom=Custom +esp32s2-devkitlipo-usb.menu.PartitionScheme.custom.build.partitions= +esp32s2-devkitlipo-usb.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s2-devkitlipo-usb.menu.CPUFreq.240=240MHz (WiFi) +esp32s2-devkitlipo-usb.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s2-devkitlipo-usb.menu.CPUFreq.160=160MHz (WiFi) +esp32s2-devkitlipo-usb.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s2-devkitlipo-usb.menu.CPUFreq.80=80MHz (WiFi) +esp32s2-devkitlipo-usb.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s2-devkitlipo-usb.menu.CPUFreq.40=40MHz +esp32s2-devkitlipo-usb.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s2-devkitlipo-usb.menu.CPUFreq.20=20MHz +esp32s2-devkitlipo-usb.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s2-devkitlipo-usb.menu.CPUFreq.10=10MHz +esp32s2-devkitlipo-usb.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s2-devkitlipo-usb.menu.FlashMode.qio=QIO +esp32s2-devkitlipo-usb.menu.FlashMode.qio.build.flash_mode=dio +esp32s2-devkitlipo-usb.menu.FlashMode.qio.build.boot=qio +esp32s2-devkitlipo-usb.menu.FlashMode.dio=DIO +esp32s2-devkitlipo-usb.menu.FlashMode.dio.build.flash_mode=dio +esp32s2-devkitlipo-usb.menu.FlashMode.dio.build.boot=dio +esp32s2-devkitlipo-usb.menu.FlashMode.qout=QOUT +esp32s2-devkitlipo-usb.menu.FlashMode.qout.build.flash_mode=dout +esp32s2-devkitlipo-usb.menu.FlashMode.qout.build.boot=qout +esp32s2-devkitlipo-usb.menu.FlashMode.dout=DOUT +esp32s2-devkitlipo-usb.menu.FlashMode.dout.build.flash_mode=dout +esp32s2-devkitlipo-usb.menu.FlashMode.dout.build.boot=dout + +esp32s2-devkitlipo-usb.menu.FlashFreq.80=80MHz +esp32s2-devkitlipo-usb.menu.FlashFreq.80.build.flash_freq=80m +esp32s2-devkitlipo-usb.menu.FlashFreq.40=40MHz +esp32s2-devkitlipo-usb.menu.FlashFreq.40.build.flash_freq=40m + +esp32s2-devkitlipo-usb.menu.FlashSize.4M=4MB (32Mb) +esp32s2-devkitlipo-usb.menu.FlashSize.4M.build.flash_size=4MB +esp32s2-devkitlipo-usb.menu.FlashSize.8M=8MB (64Mb) +esp32s2-devkitlipo-usb.menu.FlashSize.8M.build.flash_size=8MB +esp32s2-devkitlipo-usb.menu.FlashSize.2M=2MB (16Mb) +esp32s2-devkitlipo-usb.menu.FlashSize.2M.build.flash_size=2MB +esp32s2-devkitlipo-usb.menu.FlashSize.16M=16MB (128Mb) +esp32s2-devkitlipo-usb.menu.FlashSize.16M.build.flash_size=16MB + +esp32s2-devkitlipo-usb.menu.UploadSpeed.921600=921600 +esp32s2-devkitlipo-usb.menu.UploadSpeed.921600.upload.speed=921600 +esp32s2-devkitlipo-usb.menu.UploadSpeed.115200=115200 +esp32s2-devkitlipo-usb.menu.UploadSpeed.115200.upload.speed=115200 +esp32s2-devkitlipo-usb.menu.UploadSpeed.256000.windows=256000 +esp32s2-devkitlipo-usb.menu.UploadSpeed.256000.upload.speed=256000 +esp32s2-devkitlipo-usb.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s2-devkitlipo-usb.menu.UploadSpeed.230400=230400 +esp32s2-devkitlipo-usb.menu.UploadSpeed.230400.upload.speed=230400 +esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.linux=460800 +esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.macosx=460800 +esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.upload.speed=460800 +esp32s2-devkitlipo-usb.menu.UploadSpeed.512000.windows=512000 +esp32s2-devkitlipo-usb.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s2-devkitlipo-usb.menu.DebugLevel.none=None +esp32s2-devkitlipo-usb.menu.DebugLevel.none.build.code_debug=0 +esp32s2-devkitlipo-usb.menu.DebugLevel.error=Error +esp32s2-devkitlipo-usb.menu.DebugLevel.error.build.code_debug=1 +esp32s2-devkitlipo-usb.menu.DebugLevel.warn=Warn +esp32s2-devkitlipo-usb.menu.DebugLevel.warn.build.code_debug=2 +esp32s2-devkitlipo-usb.menu.DebugLevel.info=Info +esp32s2-devkitlipo-usb.menu.DebugLevel.info.build.code_debug=3 +esp32s2-devkitlipo-usb.menu.DebugLevel.debug=Debug +esp32s2-devkitlipo-usb.menu.DebugLevel.debug.build.code_debug=4 +esp32s2-devkitlipo-usb.menu.DebugLevel.verbose=Verbose +esp32s2-devkitlipo-usb.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s2-devkitlipo-usb.menu.EraseFlash.none=Disabled +esp32s2-devkitlipo-usb.menu.EraseFlash.none.upload.erase_cmd= +esp32s2-devkitlipo-usb.menu.EraseFlash.all=Enabled +esp32s2-devkitlipo-usb.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32s3-devkitlipo.name=OLIMEX ESP32-S3-DevKit-Lipo + +esp32s3-devkitlipo.bootloader.tool=esptool_py +esp32s3-devkitlipo.bootloader.tool.default=esptool_py + +esp32s3-devkitlipo.upload.tool=esptool_py +esp32s3-devkitlipo.upload.tool.default=esptool_py +esp32s3-devkitlipo.upload.tool.network=esp_ota + +esp32s3-devkitlipo.upload.maximum_size=1310720 +esp32s3-devkitlipo.upload.maximum_data_size=327680 +esp32s3-devkitlipo.upload.flags= +esp32s3-devkitlipo.upload.extra_flags= +esp32s3-devkitlipo.upload.use_1200bps_touch=false +esp32s3-devkitlipo.upload.wait_for_upload_port=false + +esp32s3-devkitlipo.serial.disableDTR=false +esp32s3-devkitlipo.serial.disableRTS=false + +esp32s3-devkitlipo.build.tarch=xtensa +esp32s3-devkitlipo.build.bootloader_addr=0x0 +esp32s3-devkitlipo.build.target=esp32s3 +esp32s3-devkitlipo.build.mcu=esp32s3 +esp32s3-devkitlipo.build.core=esp32 +esp32s3-devkitlipo.build.variant=esp32s3-devkit-lipo +esp32s3-devkitlipo.build.board=ESP32S3_DEVKIT_LIPO + +esp32s3-devkitlipo.build.usb_mode=1 +esp32s3-devkitlipo.build.cdc_on_boot=0 +esp32s3-devkitlipo.build.msc_on_boot=0 +esp32s3-devkitlipo.build.dfu_on_boot=0 +esp32s3-devkitlipo.build.f_cpu=240000000L +esp32s3-devkitlipo.build.flash_size=4MB +esp32s3-devkitlipo.build.flash_freq=80m +esp32s3-devkitlipo.build.flash_mode=dio +esp32s3-devkitlipo.build.boot=qio +esp32s3-devkitlipo.build.boot_freq=80m +esp32s3-devkitlipo.build.partitions=default +esp32s3-devkitlipo.build.defines= +esp32s3-devkitlipo.build.loop_core= +esp32s3-devkitlipo.build.event_core= +esp32s3-devkitlipo.build.psram_type=qspi +esp32s3-devkitlipo.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +esp32s3-devkitlipo.menu.JTAGAdapter.default=Disabled +esp32s3-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32s3-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32s3-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +esp32s3-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32s3-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter +esp32s3-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +esp32s3-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32s3-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32s3-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +esp32s3-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32s3-devkitlipo.menu.PSRAM.disabled=Disabled +esp32s3-devkitlipo.menu.PSRAM.disabled.build.defines= +esp32s3-devkitlipo.menu.PSRAM.disabled.build.psram_type=qspi +esp32s3-devkitlipo.menu.PSRAM.enabled=QSPI PSRAM +esp32s3-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +esp32s3-devkitlipo.menu.PSRAM.enabled.build.psram_type=qspi +esp32s3-devkitlipo.menu.PSRAM.opi=OPI PSRAM +esp32s3-devkitlipo.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +esp32s3-devkitlipo.menu.PSRAM.opi.build.psram_type=opi + +esp32s3-devkitlipo.menu.FlashMode.qio=QIO 80MHz +esp32s3-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio +esp32s3-devkitlipo.menu.FlashMode.qio.build.boot=qio +esp32s3-devkitlipo.menu.FlashMode.qio.build.boot_freq=80m +esp32s3-devkitlipo.menu.FlashMode.qio.build.flash_freq=80m +esp32s3-devkitlipo.menu.FlashMode.qio120=QIO 120MHz +esp32s3-devkitlipo.menu.FlashMode.qio120.build.flash_mode=dio +esp32s3-devkitlipo.menu.FlashMode.qio120.build.boot=qio +esp32s3-devkitlipo.menu.FlashMode.qio120.build.boot_freq=120m +esp32s3-devkitlipo.menu.FlashMode.qio120.build.flash_freq=80m +esp32s3-devkitlipo.menu.FlashMode.dio=DIO 80MHz +esp32s3-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio +esp32s3-devkitlipo.menu.FlashMode.dio.build.boot=dio +esp32s3-devkitlipo.menu.FlashMode.dio.build.boot_freq=80m +esp32s3-devkitlipo.menu.FlashMode.dio.build.flash_freq=80m +esp32s3-devkitlipo.menu.FlashMode.opi=OPI 80MHz +esp32s3-devkitlipo.menu.FlashMode.opi.build.flash_mode=dout +esp32s3-devkitlipo.menu.FlashMode.opi.build.boot=opi +esp32s3-devkitlipo.menu.FlashMode.opi.build.boot_freq=80m +esp32s3-devkitlipo.menu.FlashMode.opi.build.flash_freq=80m + +esp32s3-devkitlipo.menu.FlashSize.4M=4MB (32Mb) +esp32s3-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB +esp32s3-devkitlipo.menu.FlashSize.8M=8MB (64Mb) +esp32s3-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB +esp32s3-devkitlipo.menu.FlashSize.16M=16MB (128Mb) +esp32s3-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB +esp32s3-devkitlipo.menu.FlashSize.32M=32MB (256Mb) +esp32s3-devkitlipo.menu.FlashSize.32M.build.flash_size=32MB + +esp32s3-devkitlipo.menu.LoopCore.1=Core 1 +esp32s3-devkitlipo.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3-devkitlipo.menu.LoopCore.0=Core 0 +esp32s3-devkitlipo.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32s3-devkitlipo.menu.EventsCore.1=Core 1 +esp32s3-devkitlipo.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32s3-devkitlipo.menu.EventsCore.0=Core 0 +esp32s3-devkitlipo.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32s3-devkitlipo.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3-devkitlipo.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3-devkitlipo.menu.USBMode.default=USB-OTG (TinyUSB) +esp32s3-devkitlipo.menu.USBMode.default.build.usb_mode=0 + +esp32s3-devkitlipo.menu.CDCOnBoot.default=Disabled +esp32s3-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32s3-devkitlipo.menu.CDCOnBoot.cdc=Enabled +esp32s3-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32s3-devkitlipo.menu.MSCOnBoot.default=Disabled +esp32s3-devkitlipo.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3-devkitlipo.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3-devkitlipo.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3-devkitlipo.menu.DFUOnBoot.default=Disabled +esp32s3-devkitlipo.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3-devkitlipo.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3-devkitlipo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3-devkitlipo.menu.UploadMode.default=UART0 / Hardware CDC +esp32s3-devkitlipo.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s3-devkitlipo.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s3-devkitlipo.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32s3-devkitlipo.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s3-devkitlipo.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s3-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.default.build.partitions=default +esp32s3-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32s3-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal +esp32s3-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32s3-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32s3-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32s3-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32s3-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32s3-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32s3-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32s3-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +esp32s3-devkitlipo.menu.PartitionScheme.custom=Custom +esp32s3-devkitlipo.menu.PartitionScheme.custom.build.partitions= +esp32s3-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32s3-devkitlipo.menu.CPUFreq.240=240MHz (WiFi) +esp32s3-devkitlipo.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s3-devkitlipo.menu.CPUFreq.160=160MHz (WiFi) +esp32s3-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s3-devkitlipo.menu.CPUFreq.80=80MHz (WiFi) +esp32s3-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s3-devkitlipo.menu.CPUFreq.40=40MHz +esp32s3-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s3-devkitlipo.menu.CPUFreq.20=20MHz +esp32s3-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s3-devkitlipo.menu.CPUFreq.10=10MHz +esp32s3-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s3-devkitlipo.menu.UploadSpeed.921600=921600 +esp32s3-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600 +esp32s3-devkitlipo.menu.UploadSpeed.115200=115200 +esp32s3-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200 +esp32s3-devkitlipo.menu.UploadSpeed.256000.windows=256000 +esp32s3-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000 +esp32s3-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s3-devkitlipo.menu.UploadSpeed.230400=230400 +esp32s3-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400 +esp32s3-devkitlipo.menu.UploadSpeed.460800.linux=460800 +esp32s3-devkitlipo.menu.UploadSpeed.460800.macosx=460800 +esp32s3-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800 +esp32s3-devkitlipo.menu.UploadSpeed.512000.windows=512000 +esp32s3-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s3-devkitlipo.menu.DebugLevel.none=None +esp32s3-devkitlipo.menu.DebugLevel.none.build.code_debug=0 +esp32s3-devkitlipo.menu.DebugLevel.error=Error +esp32s3-devkitlipo.menu.DebugLevel.error.build.code_debug=1 +esp32s3-devkitlipo.menu.DebugLevel.warn=Warn +esp32s3-devkitlipo.menu.DebugLevel.warn.build.code_debug=2 +esp32s3-devkitlipo.menu.DebugLevel.info=Info +esp32s3-devkitlipo.menu.DebugLevel.info.build.code_debug=3 +esp32s3-devkitlipo.menu.DebugLevel.debug=Debug +esp32s3-devkitlipo.menu.DebugLevel.debug.build.code_debug=4 +esp32s3-devkitlipo.menu.DebugLevel.verbose=Verbose +esp32s3-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3-devkitlipo.menu.EraseFlash.none=Disabled +esp32s3-devkitlipo.menu.EraseFlash.none.upload.erase_cmd= +esp32s3-devkitlipo.menu.EraseFlash.all=Enabled +esp32s3-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32c3-devkitlipo.name=OLIMEX ESP32-C3-DevKit-Lipo + +esp32c3-devkitlipo.bootloader.tool=esptool_py +esp32c3-devkitlipo.bootloader.tool.default=esptool_py + +esp32c3-devkitlipo.upload.tool=esptool_py +esp32c3-devkitlipo.upload.tool.default=esptool_py +esp32c3-devkitlipo.upload.tool.network=esp_ota + +esp32c3-devkitlipo.upload.maximum_size=1310720 +esp32c3-devkitlipo.upload.maximum_data_size=327680 +esp32c3-devkitlipo.upload.flags= +esp32c3-devkitlipo.upload.extra_flags= +esp32c3-devkitlipo.upload.use_1200bps_touch=false +esp32c3-devkitlipo.upload.wait_for_upload_port=false + +esp32c3-devkitlipo.serial.disableDTR=false +esp32c3-devkitlipo.serial.disableRTS=false + +esp32c3-devkitlipo.build.tarch=riscv32 +esp32c3-devkitlipo.build.target=esp +esp32c3-devkitlipo.build.mcu=esp32c3 +esp32c3-devkitlipo.build.core=esp32 +esp32c3-devkitlipo.build.variant=esp32c3-devkit-lipo +esp32c3-devkitlipo.build.board=ESP32C3_DEVKIT_LIPO +esp32c3-devkitlipo.build.bootloader_addr=0x0 + +esp32c3-devkitlipo.build.cdc_on_boot=0 +esp32c3-devkitlipo.build.f_cpu=160000000L +esp32c3-devkitlipo.build.flash_size=4MB +esp32c3-devkitlipo.build.flash_freq=80m +esp32c3-devkitlipo.build.flash_mode=qio +esp32c3-devkitlipo.build.boot=qio +esp32c3-devkitlipo.build.partitions=default +esp32c3-devkitlipo.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c3-devkitlipo.menu.JTAGAdapter.default=Disabled +esp32c3-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c3-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c3-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +esp32c3-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c3-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter +esp32c3-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +esp32c3-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c3-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c3-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +esp32c3-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c3-devkitlipo.menu.CDCOnBoot.default=Disabled +esp32c3-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c3-devkitlipo.menu.CDCOnBoot.cdc=Enabled +esp32c3-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c3-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.default.build.partitions=default +esp32c3-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c3-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c3-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c3-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c3-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c3-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c3-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c3-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c3-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c3-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c3-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c3-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32c3-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32c3-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c3-devkitlipo.menu.PartitionScheme.custom=Custom +esp32c3-devkitlipo.menu.PartitionScheme.custom.build.partitions= +esp32c3-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32c3-devkitlipo.menu.CPUFreq.160=160MHz (WiFi) +esp32c3-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c3-devkitlipo.menu.CPUFreq.80=80MHz (WiFi) +esp32c3-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c3-devkitlipo.menu.CPUFreq.40=40MHz +esp32c3-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c3-devkitlipo.menu.CPUFreq.20=20MHz +esp32c3-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c3-devkitlipo.menu.CPUFreq.10=10MHz +esp32c3-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c3-devkitlipo.menu.FlashMode.qio=QIO +esp32c3-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio +esp32c3-devkitlipo.menu.FlashMode.qio.build.boot=qio +esp32c3-devkitlipo.menu.FlashMode.dio=DIO +esp32c3-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio +esp32c3-devkitlipo.menu.FlashMode.dio.build.boot=dio +esp32c3-devkitlipo.menu.FlashMode.qout=QOUT +esp32c3-devkitlipo.menu.FlashMode.qout.build.flash_mode=dout +esp32c3-devkitlipo.menu.FlashMode.qout.build.boot=qout +esp32c3-devkitlipo.menu.FlashMode.dout=DOUT +esp32c3-devkitlipo.menu.FlashMode.dout.build.flash_mode=dout +esp32c3-devkitlipo.menu.FlashMode.dout.build.boot=dout + +esp32c3-devkitlipo.menu.FlashFreq.80=80MHz +esp32c3-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m +esp32c3-devkitlipo.menu.FlashFreq.40=40MHz +esp32c3-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m + +esp32c3-devkitlipo.menu.FlashSize.4M=4MB (32Mb) +esp32c3-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB +esp32c3-devkitlipo.menu.FlashSize.8M=8MB (64Mb) +esp32c3-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB +esp32c3-devkitlipo.menu.FlashSize.2M=2MB (16Mb) +esp32c3-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB +esp32c3-devkitlipo.menu.FlashSize.16M=16MB (128Mb) +esp32c3-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB + +esp32c3-devkitlipo.menu.UploadSpeed.921600=921600 +esp32c3-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600 +esp32c3-devkitlipo.menu.UploadSpeed.115200=115200 +esp32c3-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200 +esp32c3-devkitlipo.menu.UploadSpeed.256000.windows=256000 +esp32c3-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000 +esp32c3-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c3-devkitlipo.menu.UploadSpeed.230400=230400 +esp32c3-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400 +esp32c3-devkitlipo.menu.UploadSpeed.460800.linux=460800 +esp32c3-devkitlipo.menu.UploadSpeed.460800.macosx=460800 +esp32c3-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800 +esp32c3-devkitlipo.menu.UploadSpeed.512000.windows=512000 +esp32c3-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c3-devkitlipo.menu.DebugLevel.none=None +esp32c3-devkitlipo.menu.DebugLevel.none.build.code_debug=0 +esp32c3-devkitlipo.menu.DebugLevel.error=Error +esp32c3-devkitlipo.menu.DebugLevel.error.build.code_debug=1 +esp32c3-devkitlipo.menu.DebugLevel.warn=Warn +esp32c3-devkitlipo.menu.DebugLevel.warn.build.code_debug=2 +esp32c3-devkitlipo.menu.DebugLevel.info=Info +esp32c3-devkitlipo.menu.DebugLevel.info.build.code_debug=3 +esp32c3-devkitlipo.menu.DebugLevel.debug=Debug +esp32c3-devkitlipo.menu.DebugLevel.debug.build.code_debug=4 +esp32c3-devkitlipo.menu.DebugLevel.verbose=Verbose +esp32c3-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c3-devkitlipo.menu.EraseFlash.none=Disabled +esp32c3-devkitlipo.menu.EraseFlash.none.upload.erase_cmd= +esp32c3-devkitlipo.menu.EraseFlash.all=Enabled +esp32c3-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32c6-evb.name=OLIMEX ESP32-C6-EVB + +esp32c6-evb.bootloader.tool=esptool_py +esp32c6-evb.bootloader.tool.default=esptool_py + +esp32c6-evb.upload.tool=esptool_py +esp32c6-evb.upload.tool.default=esptool_py +esp32c6-evb.upload.tool.network=esp_ota + +esp32c6-evb.upload.maximum_size=1310720 +esp32c6-evb.upload.maximum_data_size=327680 +esp32c6-evb.upload.flags= +esp32c6-evb.upload.extra_flags= +esp32c6-evb.upload.use_1200bps_touch=false +esp32c6-evb.upload.wait_for_upload_port=false + +esp32c6-evb.serial.disableDTR=false +esp32c6-evb.serial.disableRTS=false + +esp32c6-evb.build.tarch=riscv32 +esp32c6-evb.build.target=esp +esp32c6-evb.build.mcu=esp32c6 +esp32c6-evb.build.core=esp32 +esp32c6-evb.build.variant=esp32c6-evb +esp32c6-evb.build.board=ESP32C6_EVB +esp32c6-evb.build.bootloader_addr=0x0 + +esp32c6-evb.build.cdc_on_boot=0 +esp32c6-evb.build.f_cpu=160000000L +esp32c6-evb.build.flash_size=4MB +esp32c6-evb.build.flash_freq=80m +esp32c6-evb.build.flash_mode=qio +esp32c6-evb.build.boot=qio +esp32c6-evb.build.partitions=default +esp32c6-evb.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c6-evb.menu.JTAGAdapter.default=Disabled +esp32c6-evb.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c6-evb.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c6-evb.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +esp32c6-evb.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c6-evb.menu.JTAGAdapter.external=FTDI Adapter +esp32c6-evb.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +esp32c6-evb.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c6-evb.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c6-evb.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +esp32c6-evb.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c6-evb.menu.CDCOnBoot.default=Disabled +esp32c6-evb.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c6-evb.menu.CDCOnBoot.cdc=Enabled +esp32c6-evb.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c6-evb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c6-evb.menu.PartitionScheme.default.build.partitions=default +esp32c6-evb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c6-evb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c6-evb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c6-evb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c6-evb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c6-evb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c6-evb.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c6-evb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c6-evb.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c6-evb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c6-evb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c6-evb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c6-evb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c6-evb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c6-evb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c6-evb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c6-evb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c6-evb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c6-evb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c6-evb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c6-evb.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c6-evb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c6-evb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c6-evb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c6-evb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c6-evb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32c6-evb.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32c6-evb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32c6-evb.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c6-evb.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c6-evb.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c6-evb.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c6-evb.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c6-evb.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c6-evb.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c6-evb.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c6-evb.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c6-evb.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +esp32c6-evb.menu.PartitionScheme.zigbee.build.partitions=zigbee +esp32c6-evb.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +esp32c6-evb.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32c6-evb.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32c6-evb.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32c6-evb.menu.PartitionScheme.custom=Custom +esp32c6-evb.menu.PartitionScheme.custom.build.partitions= +esp32c6-evb.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32c6-evb.menu.CPUFreq.160=160MHz (WiFi) +esp32c6-evb.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c6-evb.menu.CPUFreq.80=80MHz (WiFi) +esp32c6-evb.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c6-evb.menu.CPUFreq.40=40MHz +esp32c6-evb.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c6-evb.menu.CPUFreq.20=20MHz +esp32c6-evb.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c6-evb.menu.CPUFreq.10=10MHz +esp32c6-evb.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c6-evb.menu.FlashMode.qio=QIO +esp32c6-evb.menu.FlashMode.qio.build.flash_mode=dio +esp32c6-evb.menu.FlashMode.qio.build.boot=qio +esp32c6-evb.menu.FlashMode.dio=DIO +esp32c6-evb.menu.FlashMode.dio.build.flash_mode=dio +esp32c6-evb.menu.FlashMode.dio.build.boot=dio + +esp32c6-evb.menu.FlashFreq.80=80MHz +esp32c6-evb.menu.FlashFreq.80.build.flash_freq=80m +esp32c6-evb.menu.FlashFreq.40=40MHz +esp32c6-evb.menu.FlashFreq.40.build.flash_freq=40m + +esp32c6-evb.menu.FlashSize.4M=4MB (32Mb) +esp32c6-evb.menu.FlashSize.4M.build.flash_size=4MB +esp32c6-evb.menu.FlashSize.8M=8MB (64Mb) +esp32c6-evb.menu.FlashSize.8M.build.flash_size=8MB +esp32c6-evb.menu.FlashSize.2M=2MB (16Mb) +esp32c6-evb.menu.FlashSize.2M.build.flash_size=2MB +esp32c6-evb.menu.FlashSize.16M=16MB (128Mb) +esp32c6-evb.menu.FlashSize.16M.build.flash_size=16MB + +esp32c6-evb.menu.UploadSpeed.921600=921600 +esp32c6-evb.menu.UploadSpeed.921600.upload.speed=921600 +esp32c6-evb.menu.UploadSpeed.115200=115200 +esp32c6-evb.menu.UploadSpeed.115200.upload.speed=115200 +esp32c6-evb.menu.UploadSpeed.256000.windows=256000 +esp32c6-evb.menu.UploadSpeed.256000.upload.speed=256000 +esp32c6-evb.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c6-evb.menu.UploadSpeed.230400=230400 +esp32c6-evb.menu.UploadSpeed.230400.upload.speed=230400 +esp32c6-evb.menu.UploadSpeed.460800.linux=460800 +esp32c6-evb.menu.UploadSpeed.460800.macosx=460800 +esp32c6-evb.menu.UploadSpeed.460800.upload.speed=460800 +esp32c6-evb.menu.UploadSpeed.512000.windows=512000 +esp32c6-evb.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c6-evb.menu.DebugLevel.none=None +esp32c6-evb.menu.DebugLevel.none.build.code_debug=0 +esp32c6-evb.menu.DebugLevel.error=Error +esp32c6-evb.menu.DebugLevel.error.build.code_debug=1 +esp32c6-evb.menu.DebugLevel.warn=Warn +esp32c6-evb.menu.DebugLevel.warn.build.code_debug=2 +esp32c6-evb.menu.DebugLevel.info=Info +esp32c6-evb.menu.DebugLevel.info.build.code_debug=3 +esp32c6-evb.menu.DebugLevel.debug=Debug +esp32c6-evb.menu.DebugLevel.debug.build.code_debug=4 +esp32c6-evb.menu.DebugLevel.verbose=Verbose +esp32c6-evb.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c6-evb.menu.EraseFlash.none=Disabled +esp32c6-evb.menu.EraseFlash.none.upload.erase_cmd= +esp32c6-evb.menu.EraseFlash.all=Enabled +esp32c6-evb.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32c6-evb.menu.ZigbeeMode.default=Disabled +esp32c6-evb.menu.ZigbeeMode.default.build.zigbee_mode= +esp32c6-evb.menu.ZigbeeMode.default.build.zigbee_libs= +esp32c6-evb.menu.ZigbeeMode.ed=Zigbee ED (end device) +esp32c6-evb.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32c6-evb.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +esp32c6-evb.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32c6-evb.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32c6-evb.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +esp32h2-devkitlipo.name=OLIMEX ESP32-H2-DevKit-LiPo + +esp32h2-devkitlipo.bootloader.tool=esptool_py +esp32h2-devkitlipo.bootloader.tool.default=esptool_py + +esp32h2-devkitlipo.upload.tool=esptool_py +esp32h2-devkitlipo.upload.tool.default=esptool_py +esp32h2-devkitlipo.upload.tool.network=esp_ota + +esp32h2-devkitlipo.upload.maximum_size=1310720 +esp32h2-devkitlipo.upload.maximum_data_size=327680 +esp32h2-devkitlipo.upload.flags= +esp32h2-devkitlipo.upload.extra_flags= +esp32h2-devkitlipo.upload.use_1200bps_touch=false +esp32h2-devkitlipo.upload.wait_for_upload_port=false + +esp32h2-devkitlipo.serial.disableDTR=false +esp32h2-devkitlipo.serial.disableRTS=false + +esp32h2-devkitlipo.build.tarch=riscv32 +esp32h2-devkitlipo.build.target=esp +esp32h2-devkitlipo.build.mcu=esp32h2 +esp32h2-devkitlipo.build.core=esp32 +esp32h2-devkitlipo.build.variant=esp32h2-devkit-lipo +esp32h2-devkitlipo.build.board=ESP32H2_DEVKIT_LIPO +esp32h2-devkitlipo.build.bootloader_addr=0x0 + +esp32h2-devkitlipo.build.cdc_on_boot=0 +esp32h2-devkitlipo.build.f_cpu=96000000L +esp32h2-devkitlipo.build.flash_size=4MB +esp32h2-devkitlipo.build.flash_freq=64m +esp32h2-devkitlipo.build.img_freq=48m +esp32h2-devkitlipo.build.flash_mode=qio +esp32h2-devkitlipo.build.boot=qio +esp32h2-devkitlipo.build.partitions=default +esp32h2-devkitlipo.build.defines= + +esp32h2-devkitlipo.menu.JTAGAdapter.default=Disabled +esp32h2-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32h2-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32h2-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg +esp32h2-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32h2-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter +esp32h2-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg +esp32h2-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32h2-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32h2-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg +esp32h2-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32h2-devkitlipo.menu.CDCOnBoot.default=Disabled +esp32h2-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32h2-devkitlipo.menu.CDCOnBoot.cdc=Enabled +esp32h2-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32h2-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.default.build.partitions=default +esp32h2-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32h2-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32h2-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32h2-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32h2-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal +esp32h2-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32h2-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32h2-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32h2-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32h2-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32h2-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32h2-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32h2-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32h2-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32h2-devkitlipo.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +esp32h2-devkitlipo.menu.PartitionScheme.zigbee.build.partitions=zigbee +esp32h2-devkitlipo.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32h2-devkitlipo.menu.PartitionScheme.custom=Custom +esp32h2-devkitlipo.menu.PartitionScheme.custom.build.partitions= +esp32h2-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32h2-devkitlipo.menu.FlashMode.qio=QIO +esp32h2-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio +esp32h2-devkitlipo.menu.FlashMode.qio.build.boot=qio +esp32h2-devkitlipo.menu.FlashMode.dio=DIO +esp32h2-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio +esp32h2-devkitlipo.menu.FlashMode.dio.build.boot=dio + +esp32h2-devkitlipo.menu.FlashFreq.64=64MHz +esp32h2-devkitlipo.menu.FlashFreq.64.build.flash_freq=64m +esp32h2-devkitlipo.menu.FlashFreq.64.build.img_freq=48m +#esp32h-devkitlipo2.menu.FlashFreq.32=32MHz +#esp32h-devkitlipo2.menu.FlashFreq.32.build.flash_freq=32m +#esp32h-devkitlipo2.menu.FlashFreq.32.build.img_freq=24m +esp32h2-devkitlipo.menu.FlashFreq.16=16MHz +esp32h2-devkitlipo.menu.FlashFreq.16.build.flash_freq=16m +esp32h2-devkitlipo.menu.FlashFreq.16.build.img_freq=12m + +esp32h2-devkitlipo.menu.FlashSize.4M=4MB (32Mb) +esp32h2-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB +esp32h2-devkitlipo.menu.FlashSize.8M=8MB (64Mb) +esp32h2-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB +esp32h2-devkitlipo.menu.FlashSize.2M=2MB (16Mb) +esp32h2-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB +esp32h2-devkitlipo.menu.FlashSize.16M=16MB (128Mb) +esp32h2-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB + +esp32h2-devkitlipo.menu.UploadSpeed.921600=921600 +esp32h2-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600 +esp32h2-devkitlipo.menu.UploadSpeed.115200=115200 +esp32h2-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200 +esp32h2-devkitlipo.menu.UploadSpeed.256000.windows=256000 +esp32h2-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000 +esp32h2-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32h2-devkitlipo.menu.UploadSpeed.230400=230400 +esp32h2-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400 +esp32h2-devkitlipo.menu.UploadSpeed.460800.linux=460800 +esp32h2-devkitlipo.menu.UploadSpeed.460800.macosx=460800 +esp32h2-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800 +esp32h2-devkitlipo.menu.UploadSpeed.512000.windows=512000 +esp32h2-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000 + +esp32h2-devkitlipo.menu.DebugLevel.none=None +esp32h2-devkitlipo.menu.DebugLevel.none.build.code_debug=0 +esp32h2-devkitlipo.menu.DebugLevel.error=Error +esp32h2-devkitlipo.menu.DebugLevel.error.build.code_debug=1 +esp32h2-devkitlipo.menu.DebugLevel.warn=Warn +esp32h2-devkitlipo.menu.DebugLevel.warn.build.code_debug=2 +esp32h2-devkitlipo.menu.DebugLevel.info=Info +esp32h2-devkitlipo.menu.DebugLevel.info.build.code_debug=3 +esp32h2-devkitlipo.menu.DebugLevel.debug=Debug +esp32h2-devkitlipo.menu.DebugLevel.debug.build.code_debug=4 +esp32h2-devkitlipo.menu.DebugLevel.verbose=Verbose +esp32h2-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5 + +esp32h2-devkitlipo.menu.EraseFlash.none=Disabled +esp32h2-devkitlipo.menu.EraseFlash.none.upload.erase_cmd= +esp32h2-devkitlipo.menu.EraseFlash.all=Enabled +esp32h2-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32h2-devkitlipo.menu.ZigbeeMode.default=Disabled +esp32h2-devkitlipo.menu.ZigbeeMode.default.build.zigbee_mode= +esp32h2-devkitlipo.menu.ZigbeeMode.default.build.zigbee_libs= +esp32h2-devkitlipo.menu.ZigbeeMode.ed=Zigbee ED (end device) +esp32h2-devkitlipo.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +esp32h2-devkitlipo.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +esp32h2-devkitlipo.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32h2-devkitlipo.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32h2-devkitlipo.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +esp32-sbc-fabgl.name=OLIMEX ESP32-SBC-FABGL + +esp32-sbc-fabgl.bootloader.tool=esptool_py +esp32-sbc-fabgl.bootloader.tool.default=esptool_py + +esp32-sbc-fabgl.upload.tool=esptool_py +esp32-sbc-fabgl.upload.tool.default=esptool_py +esp32-sbc-fabgl.upload.tool.network=esp_ota + +esp32-sbc-fabgl.upload.maximum_size=1310720 +esp32-sbc-fabgl.upload.maximum_data_size=327680 +esp32-sbc-fabgl.upload.flags= +esp32-sbc-fabgl.upload.extra_flags= + +esp32-sbc-fabgl.serial.disableDTR=true +esp32-sbc-fabgl.serial.disableRTS=true + +esp32-sbc-fabgl.build.tarch=xtensa +esp32-sbc-fabgl.build.bootloader_addr=0x1000 +esp32-sbc-fabgl.build.target=esp32 +esp32-sbc-fabgl.build.mcu=esp32 +esp32-sbc-fabgl.build.core=esp32 +esp32-sbc-fabgl.build.variant=esp32-sbc-fabgl +esp32-sbc-fabgl.build.board=ESP32_SBC_FABGL + +esp32-sbc-fabgl.build.f_cpu=240000000L +esp32-sbc-fabgl.build.flash_size=4MB +esp32-sbc-fabgl.build.flash_freq=40m +esp32-sbc-fabgl.build.flash_mode=dio +esp32-sbc-fabgl.build.boot=dio +esp32-sbc-fabgl.build.partitions=default +esp32-sbc-fabgl.build.defines= +esp32-sbc-fabgl.build.loop_core= +esp32-sbc-fabgl.build.event_core= + +## IDE 2.0 Seems to not update the value +esp32-sbc-fabgl.menu.JTAGAdapter.default=Disabled +esp32-sbc-fabgl.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32-sbc-fabgl.menu.JTAGAdapter.external=FTDI Adapter +esp32-sbc-fabgl.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg +esp32-sbc-fabgl.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32-sbc-fabgl.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32-sbc-fabgl.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg +esp32-sbc-fabgl.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32-sbc-fabgl.menu.PSRAM.enabled=Enabled +esp32-sbc-fabgl.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +esp32-sbc-fabgl.menu.PSRAM.enabled.build.extra_libs= +esp32-sbc-fabgl.menu.PSRAM.disabled=Disabled +esp32-sbc-fabgl.menu.PSRAM.disabled.build.defines= +esp32-sbc-fabgl.menu.PSRAM.disabled.build.extra_libs= + +esp32-sbc-fabgl.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.default.build.partitions=default +esp32-sbc-fabgl.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32-sbc-fabgl.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32-sbc-fabgl.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32-sbc-fabgl.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32-sbc-fabgl.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.minimal.build.partitions=minimal +esp32-sbc-fabgl.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32-sbc-fabgl.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32-sbc-fabgl.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32-sbc-fabgl.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32-sbc-fabgl.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32-sbc-fabgl.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32-sbc-fabgl.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +esp32-sbc-fabgl.menu.PartitionScheme.fatflash.build.partitions=ffat +esp32-sbc-fabgl.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +esp32-sbc-fabgl.menu.PartitionScheme.custom=Custom +esp32-sbc-fabgl.menu.PartitionScheme.custom.build.partitions= +esp32-sbc-fabgl.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +esp32-sbc-fabgl.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32-sbc-fabgl.menu.CPUFreq.240.build.f_cpu=240000000L +esp32-sbc-fabgl.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32-sbc-fabgl.menu.CPUFreq.160.build.f_cpu=160000000L +esp32-sbc-fabgl.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32-sbc-fabgl.menu.CPUFreq.80.build.f_cpu=80000000L +esp32-sbc-fabgl.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32-sbc-fabgl.menu.CPUFreq.40.build.f_cpu=40000000L +esp32-sbc-fabgl.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32-sbc-fabgl.menu.CPUFreq.26.build.f_cpu=26000000L +esp32-sbc-fabgl.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32-sbc-fabgl.menu.CPUFreq.20.build.f_cpu=20000000L +esp32-sbc-fabgl.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32-sbc-fabgl.menu.CPUFreq.13.build.f_cpu=13000000L +esp32-sbc-fabgl.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32-sbc-fabgl.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32-sbc-fabgl.menu.FlashMode.qio=QIO +esp32-sbc-fabgl.menu.FlashMode.qio.build.flash_mode=dio +esp32-sbc-fabgl.menu.FlashMode.qio.build.boot=qio +esp32-sbc-fabgl.menu.FlashMode.dio=DIO +esp32-sbc-fabgl.menu.FlashMode.dio.build.flash_mode=dio +esp32-sbc-fabgl.menu.FlashMode.dio.build.boot=dio + +esp32-sbc-fabgl.menu.FlashFreq.80=80MHz +esp32-sbc-fabgl.menu.FlashFreq.80.build.flash_freq=80m +esp32-sbc-fabgl.menu.FlashFreq.40=40MHz +esp32-sbc-fabgl.menu.FlashFreq.40.build.flash_freq=40m + +esp32-sbc-fabgl.menu.FlashSize.4M=4MB (32Mb) +esp32-sbc-fabgl.menu.FlashSize.4M.build.flash_size=4MB +esp32-sbc-fabgl.menu.FlashSize.8M=8MB (64Mb) +esp32-sbc-fabgl.menu.FlashSize.8M.build.flash_size=8MB +esp32-sbc-fabgl.menu.FlashSize.2M=2MB (16Mb) +esp32-sbc-fabgl.menu.FlashSize.2M.build.flash_size=2MB +esp32-sbc-fabgl.menu.FlashSize.16M=16MB (128Mb) +esp32-sbc-fabgl.menu.FlashSize.16M.build.flash_size=16MB + +esp32-sbc-fabgl.menu.UploadSpeed.921600=921600 +esp32-sbc-fabgl.menu.UploadSpeed.921600.upload.speed=921600 +esp32-sbc-fabgl.menu.UploadSpeed.115200=115200 +esp32-sbc-fabgl.menu.UploadSpeed.115200.upload.speed=115200 +esp32-sbc-fabgl.menu.UploadSpeed.256000.windows=256000 +esp32-sbc-fabgl.menu.UploadSpeed.256000.upload.speed=256000 +esp32-sbc-fabgl.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-sbc-fabgl.menu.UploadSpeed.230400=230400 +esp32-sbc-fabgl.menu.UploadSpeed.230400.upload.speed=230400 +esp32-sbc-fabgl.menu.UploadSpeed.460800.linux=460800 +esp32-sbc-fabgl.menu.UploadSpeed.460800.macosx=460800 +esp32-sbc-fabgl.menu.UploadSpeed.460800.upload.speed=460800 +esp32-sbc-fabgl.menu.UploadSpeed.512000.windows=512000 +esp32-sbc-fabgl.menu.UploadSpeed.512000.upload.speed=512000 + +esp32-sbc-fabgl.menu.LoopCore.1=Core 1 +esp32-sbc-fabgl.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32-sbc-fabgl.menu.LoopCore.0=Core 0 +esp32-sbc-fabgl.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32-sbc-fabgl.menu.EventsCore.1=Core 1 +esp32-sbc-fabgl.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32-sbc-fabgl.menu.EventsCore.0=Core 0 +esp32-sbc-fabgl.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32-sbc-fabgl.menu.DebugLevel.none=None +esp32-sbc-fabgl.menu.DebugLevel.none.build.code_debug=0 +esp32-sbc-fabgl.menu.DebugLevel.error=Error +esp32-sbc-fabgl.menu.DebugLevel.error.build.code_debug=1 +esp32-sbc-fabgl.menu.DebugLevel.warn=Warn +esp32-sbc-fabgl.menu.DebugLevel.warn.build.code_debug=2 +esp32-sbc-fabgl.menu.DebugLevel.info=Info +esp32-sbc-fabgl.menu.DebugLevel.info.build.code_debug=3 +esp32-sbc-fabgl.menu.DebugLevel.debug=Debug +esp32-sbc-fabgl.menu.DebugLevel.debug.build.code_debug=4 +esp32-sbc-fabgl.menu.DebugLevel.verbose=Verbose +esp32-sbc-fabgl.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-sbc-fabgl.menu.EraseFlash.none=Disabled +esp32-sbc-fabgl.menu.EraseFlash.none.upload.erase_cmd= +esp32-sbc-fabgl.menu.EraseFlash.all=Enabled +esp32-sbc-fabgl.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32-sbc-fabgl.menu.ZigbeeMode.default=Disabled +esp32-sbc-fabgl.menu.ZigbeeMode.default.build.zigbee_mode= +esp32-sbc-fabgl.menu.ZigbeeMode.default.build.zigbee_libs= +esp32-sbc-fabgl.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +esp32-sbc-fabgl.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +esp32-sbc-fabgl.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +espino32.name=ThaiEasyElec's ESPino32 + +espino32.bootloader.tool=esptool_py +espino32.bootloader.tool.default=esptool_py + +espino32.upload.tool=esptool_py +espino32.upload.tool.default=esptool_py +espino32.upload.tool.network=esp_ota + +espino32.upload.maximum_size=1310720 +espino32.upload.maximum_data_size=327680 +espino32.upload.flags= +espino32.upload.extra_flags= + +espino32.serial.disableDTR=true +espino32.serial.disableRTS=true + +espino32.build.tarch=xtensa +espino32.build.bootloader_addr=0x1000 +espino32.build.target=esp32 +espino32.build.mcu=esp32 +espino32.build.core=esp32 +espino32.build.variant=espino32 +espino32.build.board=ESPino32 + +espino32.build.f_cpu=240000000L +espino32.build.flash_mode=dio +espino32.build.flash_size=4MB +espino32.build.boot=dio +espino32.build.partitions=default +espino32.build.defines= + +espino32.menu.FlashFreq.80=80MHz +espino32.menu.FlashFreq.80.build.flash_freq=80m +espino32.menu.FlashFreq.40=40MHz +espino32.menu.FlashFreq.40.build.flash_freq=40m + +espino32.menu.UploadSpeed.921600=921600 +espino32.menu.UploadSpeed.921600.upload.speed=921600 +espino32.menu.UploadSpeed.115200=115200 +espino32.menu.UploadSpeed.115200.upload.speed=115200 +espino32.menu.UploadSpeed.256000.windows=256000 +espino32.menu.UploadSpeed.256000.upload.speed=256000 +espino32.menu.UploadSpeed.230400.windows.upload.speed=256000 +espino32.menu.UploadSpeed.230400=230400 +espino32.menu.UploadSpeed.230400.upload.speed=230400 +espino32.menu.UploadSpeed.460800.linux=460800 +espino32.menu.UploadSpeed.460800.macosx=460800 +espino32.menu.UploadSpeed.460800.upload.speed=460800 +espino32.menu.UploadSpeed.512000.windows=512000 +espino32.menu.UploadSpeed.512000.upload.speed=512000 + +espino32.menu.DebugLevel.none=None +espino32.menu.DebugLevel.none.build.code_debug=0 +espino32.menu.DebugLevel.error=Error +espino32.menu.DebugLevel.error.build.code_debug=1 +espino32.menu.DebugLevel.warn=Warn +espino32.menu.DebugLevel.warn.build.code_debug=2 +espino32.menu.DebugLevel.info=Info +espino32.menu.DebugLevel.info.build.code_debug=3 +espino32.menu.DebugLevel.debug=Debug +espino32.menu.DebugLevel.debug.build.code_debug=4 +espino32.menu.DebugLevel.verbose=Verbose +espino32.menu.DebugLevel.verbose.build.code_debug=5 + +espino32.menu.EraseFlash.none=Disabled +espino32.menu.EraseFlash.none.upload.erase_cmd= +espino32.menu.EraseFlash.all=Enabled +espino32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_core.name=M5Core + +m5stack_core.bootloader.tool=esptool_py +m5stack_core.bootloader.tool.default=esptool_py + +m5stack_core.upload.tool=esptool_py +m5stack_core.upload.tool.default=esptool_py +m5stack_core.upload.tool.network=esp_ota + +m5stack_core.upload.maximum_size=1310720 +m5stack_core.upload.maximum_data_size=327680 +m5stack_core.upload.flags= +m5stack_core.upload.extra_flags= + +m5stack_core.serial.disableDTR=true +m5stack_core.serial.disableRTS=true + +m5stack_core.build.tarch=xtensa +m5stack_core.build.bootloader_addr=0x1000 +m5stack_core.build.target=esp32 +m5stack_core.build.mcu=esp32 +m5stack_core.build.core=esp32 +m5stack_core.build.variant=m5stack_core +m5stack_core.build.board=M5STACK_CORE + +m5stack_core.build.f_cpu=240000000L +m5stack_core.build.flash_size=4MB +m5stack_core.build.flash_freq=80m +m5stack_core.build.flash_mode=dio +m5stack_core.build.boot=dio +m5stack_core.build.partitions=default +m5stack_core.build.defines= +m5stack_core.build.loop_core= +m5stack_core.build.event_core= + +m5stack_core.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_core.menu.PartitionScheme.default.build.partitions=default +m5stack_core.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_core.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_core.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_core.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_core.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_core.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_core.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_core.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_core.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_core.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_core.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_core.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_core.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_core.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_core.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_core.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_core.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_core.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_core.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_core.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_core.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_core.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_core.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_core.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_core.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_core.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_core.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_core.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_core.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_core.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_core.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_core.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_core.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_core.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_core.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_core.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_core.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_core.menu.PartitionScheme.custom=Custom +m5stack_core.menu.PartitionScheme.custom.build.partitions= +m5stack_core.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_core.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_core.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_core.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_core.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_core.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_core.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_core.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_core.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_core.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_core.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_core.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_core.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_core.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_core.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_core.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_core.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_core.menu.FlashMode.qio=QIO +m5stack_core.menu.FlashMode.qio.build.flash_mode=dio +m5stack_core.menu.FlashMode.qio.build.boot=qio +m5stack_core.menu.FlashMode.dio=DIO +m5stack_core.menu.FlashMode.dio.build.flash_mode=dio +m5stack_core.menu.FlashMode.dio.build.boot=dio +m5stack_core.menu.FlashMode.qout=QOUT +m5stack_core.menu.FlashMode.qout.build.flash_mode=dout +m5stack_core.menu.FlashMode.qout.build.boot=qout +m5stack_core.menu.FlashMode.dout=DOUT +m5stack_core.menu.FlashMode.dout.build.flash_mode=dout +m5stack_core.menu.FlashMode.dout.build.boot=dout + +m5stack_core.menu.FlashFreq.80=80MHz +m5stack_core.menu.FlashFreq.80.build.flash_freq=80m +m5stack_core.menu.FlashFreq.40=40MHz +m5stack_core.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_core.menu.FlashSize.4M=4MB (32Mb) +m5stack_core.menu.FlashSize.4M.build.flash_size=4MB +m5stack_core.menu.FlashSize.16M=16MB (128Mb) +m5stack_core.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_core.menu.UploadSpeed.1500000=1500000 +m5stack_core.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_core.menu.UploadSpeed.921600=921600 +m5stack_core.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_core.menu.UploadSpeed.115200=115200 +m5stack_core.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_core.menu.UploadSpeed.256000.windows=256000 +m5stack_core.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_core.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_core.menu.UploadSpeed.230400=230400 +m5stack_core.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_core.menu.UploadSpeed.460800.linux=460800 +m5stack_core.menu.UploadSpeed.460800.macosx=460800 +m5stack_core.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_core.menu.UploadSpeed.512000.windows=512000 +m5stack_core.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_core.menu.LoopCore.1=Core 1 +m5stack_core.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_core.menu.LoopCore.0=Core 0 +m5stack_core.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_core.menu.EventsCore.1=Core 1 +m5stack_core.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_core.menu.EventsCore.0=Core 0 +m5stack_core.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_core.menu.DebugLevel.none=None +m5stack_core.menu.DebugLevel.none.build.code_debug=0 +m5stack_core.menu.DebugLevel.error=Error +m5stack_core.menu.DebugLevel.error.build.code_debug=1 +m5stack_core.menu.DebugLevel.warn=Warn +m5stack_core.menu.DebugLevel.warn.build.code_debug=2 +m5stack_core.menu.DebugLevel.info=Info +m5stack_core.menu.DebugLevel.info.build.code_debug=3 +m5stack_core.menu.DebugLevel.debug=Debug +m5stack_core.menu.DebugLevel.debug.build.code_debug=4 +m5stack_core.menu.DebugLevel.verbose=Verbose +m5stack_core.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_core.menu.EraseFlash.none=Disabled +m5stack_core.menu.EraseFlash.none.upload.erase_cmd= +m5stack_core.menu.EraseFlash.all=Enabled +m5stack_core.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_fire.name=M5Fire + +m5stack_fire.bootloader.tool=esptool_py +m5stack_fire.bootloader.tool.default=esptool_py + +m5stack_fire.upload.tool=esptool_py +m5stack_fire.upload.tool.default=esptool_py +m5stack_fire.upload.tool.network=esp_ota + +m5stack_fire.upload.maximum_size=6553600 +m5stack_fire.upload.maximum_data_size=4521984 +m5stack_fire.upload.flags= +m5stack_fire.upload.extra_flags= + +m5stack_fire.serial.disableDTR=true +m5stack_fire.serial.disableRTS=true + +m5stack_fire.build.tarch=xtensa +m5stack_fire.build.bootloader_addr=0x1000 +m5stack_fire.build.target=esp32 +m5stack_fire.build.mcu=esp32 +m5stack_fire.build.core=esp32 +m5stack_fire.build.variant=m5stack_fire +m5stack_fire.build.board=M5STACK_FIRE + +m5stack_fire.build.f_cpu=240000000L +m5stack_fire.build.flash_size=16MB +m5stack_fire.build.flash_freq=80m +m5stack_fire.build.flash_mode=dio +m5stack_fire.build.boot=dio +m5stack_fire.build.partitions=default +m5stack_fire.build.defines= +m5stack_fire.build.loop_core= +m5stack_fire.build.event_core= + +m5stack_fire.menu.PSRAM.enabled=Enabled +m5stack_fire.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_fire.menu.PSRAM.enabled.build.extra_libs= +m5stack_fire.menu.PSRAM.disabled=Disabled +m5stack_fire.menu.PSRAM.disabled.build.defines= +m5stack_fire.menu.PSRAM.disabled.build.extra_libs= + +m5stack_fire.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_fire.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_fire.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_fire.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_fire.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_fire.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_fire.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_fire.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_fire.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_fire.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_fire.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_fire.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_fire.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_fire.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_fire.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_fire.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_fire.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_fire.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_fire.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_fire.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_fire.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_fire.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_fire.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_fire.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_fire.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_fire.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_fire.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_fire.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_fire.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_fire.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_fire.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_fire.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_fire.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_fire.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_fire.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_fire.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_fire.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_fire.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_fire.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_fire.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_fire.menu.PartitionScheme.custom=Custom +m5stack_fire.menu.PartitionScheme.custom.build.partitions= +m5stack_fire.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_fire.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_fire.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_fire.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_fire.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_fire.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_fire.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_fire.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_fire.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_fire.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_fire.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_fire.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_fire.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_fire.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_fire.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_fire.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_fire.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_fire.menu.FlashMode.qio=QIO +m5stack_fire.menu.FlashMode.qio.build.flash_mode=dio +m5stack_fire.menu.FlashMode.qio.build.boot=qio +m5stack_fire.menu.FlashMode.dio=DIO +m5stack_fire.menu.FlashMode.dio.build.flash_mode=dio +m5stack_fire.menu.FlashMode.dio.build.boot=dio +m5stack_fire.menu.FlashMode.qout=QOUT +m5stack_fire.menu.FlashMode.qout.build.flash_mode=dout +m5stack_fire.menu.FlashMode.qout.build.boot=qout +m5stack_fire.menu.FlashMode.dout=DOUT +m5stack_fire.menu.FlashMode.dout.build.flash_mode=dout +m5stack_fire.menu.FlashMode.dout.build.boot=dout + +m5stack_fire.menu.FlashFreq.80=80MHz +m5stack_fire.menu.FlashFreq.80.build.flash_freq=80m +m5stack_fire.menu.FlashFreq.40=40MHz +m5stack_fire.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_fire.menu.FlashSize.16M=16MB (128Mb) +m5stack_fire.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_fire.menu.UploadSpeed.1500000=1500000 +m5stack_fire.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_fire.menu.UploadSpeed.921600=921600 +m5stack_fire.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_fire.menu.UploadSpeed.115200=115200 +m5stack_fire.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_fire.menu.UploadSpeed.256000.windows=256000 +m5stack_fire.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_fire.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_fire.menu.UploadSpeed.230400=230400 +m5stack_fire.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_fire.menu.UploadSpeed.460800.linux=460800 +m5stack_fire.menu.UploadSpeed.460800.macosx=460800 +m5stack_fire.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_fire.menu.UploadSpeed.512000.windows=512000 +m5stack_fire.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_fire.menu.LoopCore.1=Core 1 +m5stack_fire.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_fire.menu.LoopCore.0=Core 0 +m5stack_fire.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_fire.menu.EventsCore.1=Core 1 +m5stack_fire.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_fire.menu.EventsCore.0=Core 0 +m5stack_fire.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_fire.menu.DebugLevel.none=None +m5stack_fire.menu.DebugLevel.none.build.code_debug=0 +m5stack_fire.menu.DebugLevel.error=Error +m5stack_fire.menu.DebugLevel.error.build.code_debug=1 +m5stack_fire.menu.DebugLevel.warn=Warn +m5stack_fire.menu.DebugLevel.warn.build.code_debug=2 +m5stack_fire.menu.DebugLevel.info=Info +m5stack_fire.menu.DebugLevel.info.build.code_debug=3 +m5stack_fire.menu.DebugLevel.debug=Debug +m5stack_fire.menu.DebugLevel.debug.build.code_debug=4 +m5stack_fire.menu.DebugLevel.verbose=Verbose +m5stack_fire.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_fire.menu.EraseFlash.none=Disabled +m5stack_fire.menu.EraseFlash.none.upload.erase_cmd= +m5stack_fire.menu.EraseFlash.all=Enabled +m5stack_fire.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_core2.name=M5Core2 + +m5stack_core2.bootloader.tool=esptool_py +m5stack_core2.bootloader.tool.default=esptool_py + +m5stack_core2.upload.tool=esptool_py +m5stack_core2.upload.tool.default=esptool_py +m5stack_core2.upload.tool.network=esp_ota + +m5stack_core2.upload.maximum_size=6553600 +m5stack_core2.upload.maximum_data_size=4521984 +m5stack_core2.upload.flags= +m5stack_core2.upload.extra_flags= + +m5stack_core2.serial.disableDTR=true +m5stack_core2.serial.disableRTS=true + +m5stack_core2.build.tarch=xtensa +m5stack_core2.build.bootloader_addr=0x1000 +m5stack_core2.build.target=esp32 +m5stack_core2.build.mcu=esp32 +m5stack_core2.build.core=esp32 +m5stack_core2.build.variant=m5stack_core2 +m5stack_core2.build.board=M5STACK_CORE2 + +m5stack_core2.build.f_cpu=240000000L +m5stack_core2.build.flash_size=16MB +m5stack_core2.build.flash_freq=80m +m5stack_core2.build.flash_mode=dio +m5stack_core2.build.boot=dio +m5stack_core2.build.partitions=default +m5stack_core2.build.defines= +m5stack_core2.build.loop_core= +m5stack_core2.build.event_core= + +m5stack_core2.menu.PSRAM.enabled=Enabled +m5stack_core2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_core2.menu.PSRAM.enabled.build.extra_libs= +m5stack_core2.menu.PSRAM.disabled=Disabled +m5stack_core2.menu.PSRAM.disabled.build.defines= +m5stack_core2.menu.PSRAM.disabled.build.extra_libs= + +m5stack_core2.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_core2.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_core2.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_core2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_core2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_core2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_core2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_core2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_core2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_core2.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_core2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_core2.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_core2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_core2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_core2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_core2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_core2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_core2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_core2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_core2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_core2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_core2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_core2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_core2.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_core2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_core2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_core2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_core2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_core2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_core2.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_core2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_core2.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_core2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_core2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_core2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_core2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_core2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_core2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_core2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_core2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_core2.menu.PartitionScheme.custom=Custom +m5stack_core2.menu.PartitionScheme.custom.build.partitions= +m5stack_core2.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_core2.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_core2.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_core2.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_core2.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_core2.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_core2.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_core2.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_core2.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_core2.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_core2.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_core2.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_core2.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_core2.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_core2.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_core2.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_core2.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_core2.menu.FlashMode.qio=QIO +m5stack_core2.menu.FlashMode.qio.build.flash_mode=dio +m5stack_core2.menu.FlashMode.qio.build.boot=qio +m5stack_core2.menu.FlashMode.dio=DIO +m5stack_core2.menu.FlashMode.dio.build.flash_mode=dio +m5stack_core2.menu.FlashMode.dio.build.boot=dio +m5stack_core2.menu.FlashMode.qout=QOUT +m5stack_core2.menu.FlashMode.qout.build.flash_mode=dout +m5stack_core2.menu.FlashMode.qout.build.boot=qout +m5stack_core2.menu.FlashMode.dout=DOUT +m5stack_core2.menu.FlashMode.dout.build.flash_mode=dout +m5stack_core2.menu.FlashMode.dout.build.boot=dout + +m5stack_core2.menu.FlashFreq.80=80MHz +m5stack_core2.menu.FlashFreq.80.build.flash_freq=80m +m5stack_core2.menu.FlashFreq.40=40MHz +m5stack_core2.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_core2.menu.FlashSize.16M=16MB (128Mb) +m5stack_core2.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_core2.menu.UploadSpeed.1500000=1500000 +m5stack_core2.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_core2.menu.UploadSpeed.921600=921600 +m5stack_core2.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_core2.menu.UploadSpeed.115200=115200 +m5stack_core2.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_core2.menu.UploadSpeed.256000.windows=256000 +m5stack_core2.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_core2.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_core2.menu.UploadSpeed.230400=230400 +m5stack_core2.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_core2.menu.UploadSpeed.460800.linux=460800 +m5stack_core2.menu.UploadSpeed.460800.macosx=460800 +m5stack_core2.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_core2.menu.UploadSpeed.512000.windows=512000 +m5stack_core2.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_core2.menu.LoopCore.1=Core 1 +m5stack_core2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_core2.menu.LoopCore.0=Core 0 +m5stack_core2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_core2.menu.EventsCore.1=Core 1 +m5stack_core2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_core2.menu.EventsCore.0=Core 0 +m5stack_core2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_core2.menu.DebugLevel.none=None +m5stack_core2.menu.DebugLevel.none.build.code_debug=0 +m5stack_core2.menu.DebugLevel.error=Error +m5stack_core2.menu.DebugLevel.error.build.code_debug=1 +m5stack_core2.menu.DebugLevel.warn=Warn +m5stack_core2.menu.DebugLevel.warn.build.code_debug=2 +m5stack_core2.menu.DebugLevel.info=Info +m5stack_core2.menu.DebugLevel.info.build.code_debug=3 +m5stack_core2.menu.DebugLevel.debug=Debug +m5stack_core2.menu.DebugLevel.debug.build.code_debug=4 +m5stack_core2.menu.DebugLevel.verbose=Verbose +m5stack_core2.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_core2.menu.EraseFlash.none=Disabled +m5stack_core2.menu.EraseFlash.none.upload.erase_cmd= +m5stack_core2.menu.EraseFlash.all=Enabled +m5stack_core2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_tough.name=M5Tough + +m5stack_tough.bootloader.tool=esptool_py +m5stack_tough.bootloader.tool.default=esptool_py + +m5stack_tough.upload.tool=esptool_py +m5stack_tough.upload.tool.default=esptool_py +m5stack_tough.upload.tool.network=esp_ota + +m5stack_tough.upload.maximum_size=6553600 +m5stack_tough.upload.maximum_data_size=4521984 +m5stack_tough.upload.flags= +m5stack_tough.upload.extra_flags= + +m5stack_tough.serial.disableDTR=true +m5stack_tough.serial.disableRTS=true + +m5stack_tough.build.tarch=xtensa +m5stack_tough.build.bootloader_addr=0x1000 +m5stack_tough.build.target=esp32 +m5stack_tough.build.mcu=esp32 +m5stack_tough.build.core=esp32 +m5stack_tough.build.variant=m5stack_tough +m5stack_tough.build.board=M5STACK_TOUGH + +m5stack_tough.build.f_cpu=240000000L +m5stack_tough.build.flash_size=16MB +m5stack_tough.build.flash_freq=80m +m5stack_tough.build.flash_mode=dio +m5stack_tough.build.boot=dio +m5stack_tough.build.partitions=default +m5stack_tough.build.defines= +m5stack_tough.build.loop_core= +m5stack_tough.build.event_core= + +m5stack_tough.menu.PSRAM.enabled=Enabled +m5stack_tough.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_tough.menu.PSRAM.enabled.build.extra_libs= +m5stack_tough.menu.PSRAM.disabled=Disabled +m5stack_tough.menu.PSRAM.disabled.build.defines= +m5stack_tough.menu.PSRAM.disabled.build.extra_libs= + +m5stack_tough.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_tough.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_tough.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_tough.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_tough.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_tough.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_tough.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_tough.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_tough.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_tough.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_tough.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_tough.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_tough.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_tough.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_tough.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_tough.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_tough.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_tough.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_tough.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_tough.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_tough.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_tough.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_tough.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_tough.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_tough.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_tough.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_tough.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_tough.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_tough.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_tough.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_tough.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_tough.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_tough.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_tough.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_tough.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_tough.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_tough.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_tough.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_tough.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_tough.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_tough.menu.PartitionScheme.custom=Custom +m5stack_tough.menu.PartitionScheme.custom.build.partitions= +m5stack_tough.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_tough.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_tough.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_tough.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_tough.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_tough.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_tough.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_tough.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_tough.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_tough.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_tough.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_tough.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_tough.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_tough.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_tough.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_tough.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_tough.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_tough.menu.FlashMode.qio=QIO +m5stack_tough.menu.FlashMode.qio.build.flash_mode=dio +m5stack_tough.menu.FlashMode.qio.build.boot=qio +m5stack_tough.menu.FlashMode.dio=DIO +m5stack_tough.menu.FlashMode.dio.build.flash_mode=dio +m5stack_tough.menu.FlashMode.dio.build.boot=dio +m5stack_tough.menu.FlashMode.qout=QOUT +m5stack_tough.menu.FlashMode.qout.build.flash_mode=dout +m5stack_tough.menu.FlashMode.qout.build.boot=qout +m5stack_tough.menu.FlashMode.dout=DOUT +m5stack_tough.menu.FlashMode.dout.build.flash_mode=dout +m5stack_tough.menu.FlashMode.dout.build.boot=dout + +m5stack_tough.menu.FlashFreq.80=80MHz +m5stack_tough.menu.FlashFreq.80.build.flash_freq=80m +m5stack_tough.menu.FlashFreq.40=40MHz +m5stack_tough.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_tough.menu.FlashSize.16M=16MB (128Mb) +m5stack_tough.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_tough.menu.UploadSpeed.1500000=1500000 +m5stack_tough.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_tough.menu.UploadSpeed.921600=921600 +m5stack_tough.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_tough.menu.UploadSpeed.115200=115200 +m5stack_tough.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_tough.menu.UploadSpeed.256000.windows=256000 +m5stack_tough.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_tough.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_tough.menu.UploadSpeed.230400=230400 +m5stack_tough.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_tough.menu.UploadSpeed.460800.linux=460800 +m5stack_tough.menu.UploadSpeed.460800.macosx=460800 +m5stack_tough.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_tough.menu.UploadSpeed.512000.windows=512000 +m5stack_tough.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_tough.menu.LoopCore.1=Core 1 +m5stack_tough.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_tough.menu.LoopCore.0=Core 0 +m5stack_tough.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_tough.menu.EventsCore.1=Core 1 +m5stack_tough.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_tough.menu.EventsCore.0=Core 0 +m5stack_tough.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_tough.menu.DebugLevel.none=None +m5stack_tough.menu.DebugLevel.none.build.code_debug=0 +m5stack_tough.menu.DebugLevel.error=Error +m5stack_tough.menu.DebugLevel.error.build.code_debug=1 +m5stack_tough.menu.DebugLevel.warn=Warn +m5stack_tough.menu.DebugLevel.warn.build.code_debug=2 +m5stack_tough.menu.DebugLevel.info=Info +m5stack_tough.menu.DebugLevel.info.build.code_debug=3 +m5stack_tough.menu.DebugLevel.debug=Debug +m5stack_tough.menu.DebugLevel.debug.build.code_debug=4 +m5stack_tough.menu.DebugLevel.verbose=Verbose +m5stack_tough.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_tough.menu.EraseFlash.none=Disabled +m5stack_tough.menu.EraseFlash.none.upload.erase_cmd= +m5stack_tough.menu.EraseFlash.all=Enabled +m5stack_tough.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_station.name=M5Station + +m5stack_station.bootloader.tool=esptool_py +m5stack_station.bootloader.tool.default=esptool_py + +m5stack_station.upload.tool=esptool_py +m5stack_station.upload.tool.default=esptool_py +m5stack_station.upload.tool.network=esp_ota + +m5stack_station.upload.maximum_size=6553600 +m5stack_station.upload.maximum_data_size=4521984 +m5stack_station.upload.flags= +m5stack_station.upload.extra_flags= + +m5stack_station.serial.disableDTR=true +m5stack_station.serial.disableRTS=true + +m5stack_station.build.tarch=xtensa +m5stack_station.build.bootloader_addr=0x1000 +m5stack_station.build.target=esp32 +m5stack_station.build.mcu=esp32 +m5stack_station.build.core=esp32 +m5stack_station.build.variant=m5stack_station +m5stack_station.build.board=M5STACK_STATION + +m5stack_station.build.f_cpu=240000000L +m5stack_station.build.flash_size=16MB +m5stack_station.build.flash_freq=80m +m5stack_station.build.flash_mode=dio +m5stack_station.build.boot=dio +m5stack_station.build.partitions=default +m5stack_station.build.defines= +m5stack_station.build.loop_core= +m5stack_station.build.event_core= + +m5stack_station.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_station.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_station.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_station.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_station.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_station.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_station.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_station.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_station.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_station.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_station.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_station.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_station.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_station.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_station.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_station.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_station.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_station.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_station.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_station.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_station.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_station.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_station.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_station.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_station.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_station.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_station.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_station.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_station.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_station.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_station.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_station.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_station.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_station.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_station.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_station.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_station.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_station.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_station.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_station.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_station.menu.PartitionScheme.custom=Custom +m5stack_station.menu.PartitionScheme.custom.build.partitions= +m5stack_station.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_station.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_station.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_station.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_station.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_station.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_station.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_station.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_station.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_station.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_station.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_station.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_station.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_station.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_station.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_station.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_station.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_station.menu.FlashMode.qio=QIO +m5stack_station.menu.FlashMode.qio.build.flash_mode=dio +m5stack_station.menu.FlashMode.qio.build.boot=qio +m5stack_station.menu.FlashMode.dio=DIO +m5stack_station.menu.FlashMode.dio.build.flash_mode=dio +m5stack_station.menu.FlashMode.dio.build.boot=dio +m5stack_station.menu.FlashMode.qout=QOUT +m5stack_station.menu.FlashMode.qout.build.flash_mode=dout +m5stack_station.menu.FlashMode.qout.build.boot=qout +m5stack_station.menu.FlashMode.dout=DOUT +m5stack_station.menu.FlashMode.dout.build.flash_mode=dout +m5stack_station.menu.FlashMode.dout.build.boot=dout + +m5stack_station.menu.FlashFreq.80=80MHz +m5stack_station.menu.FlashFreq.80.build.flash_freq=80m +m5stack_station.menu.FlashFreq.40=40MHz +m5stack_station.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_station.menu.FlashSize.16M=16MB (128Mb) +m5stack_station.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_station.menu.UploadSpeed.1500000=1500000 +m5stack_station.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_station.menu.UploadSpeed.921600=921600 +m5stack_station.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_station.menu.UploadSpeed.115200=115200 +m5stack_station.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_station.menu.UploadSpeed.256000.windows=256000 +m5stack_station.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_station.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_station.menu.UploadSpeed.230400=230400 +m5stack_station.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_station.menu.UploadSpeed.460800.linux=460800 +m5stack_station.menu.UploadSpeed.460800.macosx=460800 +m5stack_station.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_station.menu.UploadSpeed.512000.windows=512000 +m5stack_station.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_station.menu.LoopCore.1=Core 1 +m5stack_station.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_station.menu.LoopCore.0=Core 0 +m5stack_station.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_station.menu.EventsCore.1=Core 1 +m5stack_station.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_station.menu.EventsCore.0=Core 0 +m5stack_station.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_station.menu.DebugLevel.none=None +m5stack_station.menu.DebugLevel.none.build.code_debug=0 +m5stack_station.menu.DebugLevel.error=Error +m5stack_station.menu.DebugLevel.error.build.code_debug=1 +m5stack_station.menu.DebugLevel.warn=Warn +m5stack_station.menu.DebugLevel.warn.build.code_debug=2 +m5stack_station.menu.DebugLevel.info=Info +m5stack_station.menu.DebugLevel.info.build.code_debug=3 +m5stack_station.menu.DebugLevel.debug=Debug +m5stack_station.menu.DebugLevel.debug.build.code_debug=4 +m5stack_station.menu.DebugLevel.verbose=Verbose +m5stack_station.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_station.menu.EraseFlash.none=Disabled +m5stack_station.menu.EraseFlash.none.upload.erase_cmd= +m5stack_station.menu.EraseFlash.all=Enabled +m5stack_station.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_stickc.name=M5StickC + +m5stack_stickc.bootloader.tool=esptool_py +m5stack_stickc.bootloader.tool.default=esptool_py + +m5stack_stickc.upload.tool=esptool_py +m5stack_stickc.upload.tool.default=esptool_py +m5stack_stickc.upload.tool.network=esp_ota + +m5stack_stickc.upload.maximum_size=1310720 +m5stack_stickc.upload.maximum_data_size=327680 +m5stack_stickc.upload.flags= +m5stack_stickc.upload.extra_flags= + +m5stack_stickc.serial.disableDTR=true +m5stack_stickc.serial.disableRTS=true + +m5stack_stickc.build.tarch=xtensa +m5stack_stickc.build.bootloader_addr=0x1000 +m5stack_stickc.build.target=esp32 +m5stack_stickc.build.mcu=esp32 +m5stack_stickc.build.core=esp32 +m5stack_stickc.build.variant=m5stack_stickc +m5stack_stickc.build.board=M5STACK_STICKC + +m5stack_stickc.build.f_cpu=240000000L +m5stack_stickc.build.flash_size=4MB +m5stack_stickc.build.flash_freq=80m +m5stack_stickc.build.flash_mode=dio +m5stack_stickc.build.boot=dio +m5stack_stickc.build.partitions=huge_app +m5stack_stickc.build.defines= +m5stack_stickc.build.loop_core= +m5stack_stickc.build.event_core= + +m5stack_stickc.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stickc.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stickc.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stickc.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stickc.menu.PartitionScheme.default.build.partitions=default +m5stack_stickc.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stickc.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stickc.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stickc.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stickc.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stickc.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stickc.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stickc.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stickc.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stickc.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stickc.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stickc.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stickc.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stickc.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stickc.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stickc.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stickc.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stickc.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stickc.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_stickc.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_stickc.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_stickc.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_stickc.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_stickc.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_stickc.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_stickc.menu.PartitionScheme.custom=Custom +m5stack_stickc.menu.PartitionScheme.custom.build.partitions= +m5stack_stickc.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +m5stack_stickc.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_stickc.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_stickc.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_stickc.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stickc.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_stickc.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stickc.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_stickc.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stickc.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_stickc.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_stickc.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_stickc.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stickc.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_stickc.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_stickc.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_stickc.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stickc.menu.FlashMode.qio=QIO +m5stack_stickc.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stickc.menu.FlashMode.qio.build.boot=qio +m5stack_stickc.menu.FlashMode.dio=DIO +m5stack_stickc.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stickc.menu.FlashMode.dio.build.boot=dio +m5stack_stickc.menu.FlashMode.qout=QOUT +m5stack_stickc.menu.FlashMode.qout.build.flash_mode=dout +m5stack_stickc.menu.FlashMode.qout.build.boot=qout +m5stack_stickc.menu.FlashMode.dout=DOUT +m5stack_stickc.menu.FlashMode.dout.build.flash_mode=dout +m5stack_stickc.menu.FlashMode.dout.build.boot=dout + +m5stack_stickc.menu.FlashFreq.80=80MHz +m5stack_stickc.menu.FlashFreq.80.build.flash_freq=80m +m5stack_stickc.menu.FlashFreq.40=40MHz +m5stack_stickc.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_stickc.menu.FlashSize.4M=4MB (32Mb) +m5stack_stickc.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_stickc.menu.UploadSpeed.1500000=1500000 +m5stack_stickc.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_stickc.menu.UploadSpeed.750000=750000 +m5stack_stickc.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_stickc.menu.UploadSpeed.500000=500000 +m5stack_stickc.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_stickc.menu.UploadSpeed.250000=250000 +m5stack_stickc.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_stickc.menu.UploadSpeed.115200=115200 +m5stack_stickc.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_stickc.menu.LoopCore.1=Core 1 +m5stack_stickc.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_stickc.menu.LoopCore.0=Core 0 +m5stack_stickc.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_stickc.menu.EventsCore.1=Core 1 +m5stack_stickc.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_stickc.menu.EventsCore.0=Core 0 +m5stack_stickc.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_stickc.menu.DebugLevel.none=None +m5stack_stickc.menu.DebugLevel.none.build.code_debug=0 +m5stack_stickc.menu.DebugLevel.error=Error +m5stack_stickc.menu.DebugLevel.error.build.code_debug=1 +m5stack_stickc.menu.DebugLevel.warn=Warn +m5stack_stickc.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stickc.menu.DebugLevel.info=Info +m5stack_stickc.menu.DebugLevel.info.build.code_debug=3 +m5stack_stickc.menu.DebugLevel.debug=Debug +m5stack_stickc.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stickc.menu.DebugLevel.verbose=Verbose +m5stack_stickc.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stickc.menu.EraseFlash.none=Disabled +m5stack_stickc.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stickc.menu.EraseFlash.all=Enabled +m5stack_stickc.menu.EraseFlash.all.upload.erase_cmd=-e + + +############################################################## + +m5stack_stickc_plus.name=M5StickCPlus + +m5stack_stickc_plus.bootloader.tool=esptool_py +m5stack_stickc_plus.bootloader.tool.default=esptool_py + +m5stack_stickc_plus.upload.tool=esptool_py +m5stack_stickc_plus.upload.tool.default=esptool_py +m5stack_stickc_plus.upload.tool.network=esp_ota + +m5stack_stickc_plus.upload.maximum_size=1310720 +m5stack_stickc_plus.upload.maximum_data_size=327680 +m5stack_stickc_plus.upload.flags= +m5stack_stickc_plus.upload.extra_flags= + +m5stack_stickc_plus.serial.disableDTR=true +m5stack_stickc_plus.serial.disableRTS=true + +m5stack_stickc_plus.build.tarch=xtensa +m5stack_stickc_plus.build.bootloader_addr=0x1000 +m5stack_stickc_plus.build.target=esp32 +m5stack_stickc_plus.build.mcu=esp32 +m5stack_stickc_plus.build.core=esp32 +m5stack_stickc_plus.build.variant=m5stack_stickc_plus +m5stack_stickc_plus.build.board=M5STACK_STICKC_PLUS + +m5stack_stickc_plus.build.f_cpu=240000000L +m5stack_stickc_plus.build.flash_size=4MB +m5stack_stickc_plus.build.flash_freq=80m +m5stack_stickc_plus.build.flash_mode=dio +m5stack_stickc_plus.build.boot=dio +m5stack_stickc_plus.build.partitions=huge_app +m5stack_stickc_plus.build.defines= +m5stack_stickc_plus.build.loop_core= +m5stack_stickc_plus.build.event_core= + +m5stack_stickc_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stickc_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stickc_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.default.build.partitions=default +m5stack_stickc_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stickc_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stickc_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stickc_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stickc_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stickc_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stickc_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stickc_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stickc_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stickc_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stickc_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stickc_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stickc_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_stickc_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_stickc_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_stickc_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_stickc_plus.menu.PartitionScheme.custom=Custom +m5stack_stickc_plus.menu.PartitionScheme.custom.build.partitions= +m5stack_stickc_plus.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +m5stack_stickc_plus.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_stickc_plus.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_stickc_plus.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_stickc_plus.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stickc_plus.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_stickc_plus.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stickc_plus.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_stickc_plus.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stickc_plus.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_stickc_plus.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_stickc_plus.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_stickc_plus.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stickc_plus.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_stickc_plus.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_stickc_plus.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_stickc_plus.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stickc_plus.menu.FlashMode.qio=QIO +m5stack_stickc_plus.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stickc_plus.menu.FlashMode.qio.build.boot=qio +m5stack_stickc_plus.menu.FlashMode.dio=DIO +m5stack_stickc_plus.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stickc_plus.menu.FlashMode.dio.build.boot=dio +m5stack_stickc_plus.menu.FlashMode.qout=QOUT +m5stack_stickc_plus.menu.FlashMode.qout.build.flash_mode=dout +m5stack_stickc_plus.menu.FlashMode.qout.build.boot=qout +m5stack_stickc_plus.menu.FlashMode.dout=DOUT +m5stack_stickc_plus.menu.FlashMode.dout.build.flash_mode=dout +m5stack_stickc_plus.menu.FlashMode.dout.build.boot=dout + +m5stack_stickc_plus.menu.FlashFreq.80=80MHz +m5stack_stickc_plus.menu.FlashFreq.80.build.flash_freq=80m +m5stack_stickc_plus.menu.FlashFreq.40=40MHz +m5stack_stickc_plus.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_stickc_plus.menu.FlashSize.4M=4MB (32Mb) +m5stack_stickc_plus.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_stickc_plus.menu.UploadSpeed.1500000=1500000 +m5stack_stickc_plus.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_stickc_plus.menu.UploadSpeed.750000=750000 +m5stack_stickc_plus.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_stickc_plus.menu.UploadSpeed.500000=500000 +m5stack_stickc_plus.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_stickc_plus.menu.UploadSpeed.250000=250000 +m5stack_stickc_plus.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_stickc_plus.menu.UploadSpeed.115200=115200 +m5stack_stickc_plus.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_stickc_plus.menu.LoopCore.1=Core 1 +m5stack_stickc_plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_stickc_plus.menu.LoopCore.0=Core 0 +m5stack_stickc_plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_stickc_plus.menu.EventsCore.1=Core 1 +m5stack_stickc_plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_stickc_plus.menu.EventsCore.0=Core 0 +m5stack_stickc_plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_stickc_plus.menu.DebugLevel.none=None +m5stack_stickc_plus.menu.DebugLevel.none.build.code_debug=0 +m5stack_stickc_plus.menu.DebugLevel.error=Error +m5stack_stickc_plus.menu.DebugLevel.error.build.code_debug=1 +m5stack_stickc_plus.menu.DebugLevel.warn=Warn +m5stack_stickc_plus.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stickc_plus.menu.DebugLevel.info=Info +m5stack_stickc_plus.menu.DebugLevel.info.build.code_debug=3 +m5stack_stickc_plus.menu.DebugLevel.debug=Debug +m5stack_stickc_plus.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stickc_plus.menu.DebugLevel.verbose=Verbose +m5stack_stickc_plus.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stickc_plus.menu.EraseFlash.none=Disabled +m5stack_stickc_plus.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stickc_plus.menu.EraseFlash.all=Enabled +m5stack_stickc_plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_stickc_plus2.name=M5StickCPlus2 + +m5stack_stickc_plus2.bootloader.tool=esptool_py +m5stack_stickc_plus2.bootloader.tool.default=esptool_py + +m5stack_stickc_plus2.upload.tool=esptool_py +m5stack_stickc_plus2.upload.tool.default=esptool_py +m5stack_stickc_plus2.upload.tool.network=esp_ota + +m5stack_stickc_plus2.upload.maximum_size=3342336 +m5stack_stickc_plus2.upload.maximum_data_size=327680 +m5stack_stickc_plus2.upload.flags= +m5stack_stickc_plus2.upload.extra_flags= + +m5stack_stickc_plus2.serial.disableDTR=true +m5stack_stickc_plus2.serial.disableRTS=true + +m5stack_stickc_plus2.build.tarch=xtensa +m5stack_stickc_plus2.build.bootloader_addr=0x1000 +m5stack_stickc_plus2.build.target=esp32 +m5stack_stickc_plus2.build.mcu=esp32 +m5stack_stickc_plus2.build.core=esp32 +m5stack_stickc_plus2.build.variant=m5stack_stickc_plus2 +m5stack_stickc_plus2.build.board=M5STACK_STICKC_PLUS2 + +m5stack_stickc_plus2.build.f_cpu=240000000L +m5stack_stickc_plus2.build.flash_size=8MB +m5stack_stickc_plus2.build.flash_freq=80m +m5stack_stickc_plus2.build.flash_mode=dio +m5stack_stickc_plus2.build.boot=dio +m5stack_stickc_plus2.build.partitions=default_8MB +m5stack_stickc_plus2.build.defines= +m5stack_stickc_plus2.build.loop_core= +m5stack_stickc_plus2.build.event_core= + +m5stack_stickc_plus2.menu.PSRAM.enabled=Enabled +m5stack_stickc_plus2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_stickc_plus2.menu.PSRAM.enabled.build.extra_libs= +m5stack_stickc_plus2.menu.PSRAM.disabled=Disabled +m5stack_stickc_plus2.menu.PSRAM.disabled.build.defines= +m5stack_stickc_plus2.menu.PSRAM.disabled.build.extra_libs= + +m5stack_stickc_plus2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_stickc_plus2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_stickc_plus2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stickc_plus2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stickc_plus2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.default.build.partitions=default +m5stack_stickc_plus2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stickc_plus2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stickc_plus2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stickc_plus2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stickc_plus2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stickc_plus2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stickc_plus2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_stickc_plus2.menu.PartitionScheme.custom=Custom +m5stack_stickc_plus2.menu.PartitionScheme.custom.build.partitions= +m5stack_stickc_plus2.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +m5stack_stickc_plus2.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_stickc_plus2.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_stickc_plus2.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_stickc_plus2.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stickc_plus2.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_stickc_plus2.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stickc_plus2.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_stickc_plus2.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stickc_plus2.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_stickc_plus2.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_stickc_plus2.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_stickc_plus2.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stickc_plus2.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_stickc_plus2.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_stickc_plus2.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_stickc_plus2.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stickc_plus2.menu.FlashMode.qio=QIO +m5stack_stickc_plus2.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stickc_plus2.menu.FlashMode.qio.build.boot=qio +m5stack_stickc_plus2.menu.FlashMode.dio=DIO +m5stack_stickc_plus2.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stickc_plus2.menu.FlashMode.dio.build.boot=dio +m5stack_stickc_plus2.menu.FlashMode.qout=QOUT +m5stack_stickc_plus2.menu.FlashMode.qout.build.flash_mode=dout +m5stack_stickc_plus2.menu.FlashMode.qout.build.boot=qout +m5stack_stickc_plus2.menu.FlashMode.dout=DOUT +m5stack_stickc_plus2.menu.FlashMode.dout.build.flash_mode=dout +m5stack_stickc_plus2.menu.FlashMode.dout.build.boot=dout + +m5stack_stickc_plus2.menu.FlashFreq.80=80MHz +m5stack_stickc_plus2.menu.FlashFreq.80.build.flash_freq=80m +m5stack_stickc_plus2.menu.FlashFreq.40=40MHz +m5stack_stickc_plus2.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_stickc_plus2.menu.FlashSize.8M=8MB (64Mb) +m5stack_stickc_plus2.menu.FlashSize.8M.build.flash_size=8MB + +m5stack_stickc_plus2.menu.UploadSpeed.1500000=1500000 +m5stack_stickc_plus2.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_stickc_plus2.menu.UploadSpeed.750000=750000 +m5stack_stickc_plus2.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_stickc_plus2.menu.UploadSpeed.500000=500000 +m5stack_stickc_plus2.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_stickc_plus2.menu.UploadSpeed.250000=250000 +m5stack_stickc_plus2.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_stickc_plus2.menu.UploadSpeed.115200=115200 +m5stack_stickc_plus2.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_stickc_plus2.menu.LoopCore.1=Core 1 +m5stack_stickc_plus2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_stickc_plus2.menu.LoopCore.0=Core 0 +m5stack_stickc_plus2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_stickc_plus2.menu.EventsCore.1=Core 1 +m5stack_stickc_plus2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_stickc_plus2.menu.EventsCore.0=Core 0 +m5stack_stickc_plus2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_stickc_plus2.menu.DebugLevel.none=None +m5stack_stickc_plus2.menu.DebugLevel.none.build.code_debug=0 +m5stack_stickc_plus2.menu.DebugLevel.error=Error +m5stack_stickc_plus2.menu.DebugLevel.error.build.code_debug=1 +m5stack_stickc_plus2.menu.DebugLevel.warn=Warn +m5stack_stickc_plus2.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stickc_plus2.menu.DebugLevel.info=Info +m5stack_stickc_plus2.menu.DebugLevel.info.build.code_debug=3 +m5stack_stickc_plus2.menu.DebugLevel.debug=Debug +m5stack_stickc_plus2.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stickc_plus2.menu.DebugLevel.verbose=Verbose +m5stack_stickc_plus2.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stickc_plus2.menu.EraseFlash.none=Disabled +m5stack_stickc_plus2.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stickc_plus2.menu.EraseFlash.all=Enabled +m5stack_stickc_plus2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_atom.name=M5Atom + +m5stack_atom.bootloader.tool=esptool_py +m5stack_atom.bootloader.tool.default=esptool_py + +m5stack_atom.upload.tool=esptool_py +m5stack_atom.upload.tool.default=esptool_py +m5stack_atom.upload.tool.network=esp_ota + +m5stack_atom.upload.maximum_size=1310720 +m5stack_atom.upload.maximum_data_size=327680 +m5stack_atom.upload.flags= +m5stack_atom.upload.extra_flags= + +m5stack_atom.serial.disableDTR=true +m5stack_atom.serial.disableRTS=true + +m5stack_atom.build.tarch=xtensa +m5stack_atom.build.bootloader_addr=0x1000 +m5stack_atom.build.target=esp32 +m5stack_atom.build.mcu=esp32 +m5stack_atom.build.core=esp32 +m5stack_atom.build.variant=m5stack_atom +m5stack_atom.build.board=M5STACK_ATOM + +m5stack_atom.build.f_cpu=240000000L +m5stack_atom.build.flash_size=4MB +m5stack_atom.build.flash_freq=80m +m5stack_atom.build.flash_mode=dio +m5stack_atom.build.boot=dio +m5stack_atom.build.partitions=huge_app +m5stack_atom.build.defines= +m5stack_atom.build.loop_core= +m5stack_atom.build.event_core= + +m5stack_atom.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_atom.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_atom.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_atom.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_atom.menu.PartitionScheme.default.build.partitions=default +m5stack_atom.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_atom.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_atom.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_atom.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_atom.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_atom.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_atom.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_atom.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_atom.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_atom.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_atom.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_atom.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_atom.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_atom.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_atom.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_atom.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_atom.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_atom.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_atom.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_atom.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_atom.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_atom.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_atom.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_atom.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_atom.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_atom.menu.PartitionScheme.custom=Custom +m5stack_atom.menu.PartitionScheme.custom.build.partitions= +m5stack_atom.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +m5stack_atom.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_atom.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_atom.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_atom.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_atom.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_atom.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_atom.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_atom.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_atom.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_atom.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_atom.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_atom.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_atom.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_atom.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_atom.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_atom.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_atom.menu.FlashMode.qio=QIO +m5stack_atom.menu.FlashMode.qio.build.flash_mode=dio +m5stack_atom.menu.FlashMode.qio.build.boot=qio +m5stack_atom.menu.FlashMode.dio=DIO +m5stack_atom.menu.FlashMode.dio.build.flash_mode=dio +m5stack_atom.menu.FlashMode.dio.build.boot=dio +m5stack_atom.menu.FlashMode.qout=QOUT +m5stack_atom.menu.FlashMode.qout.build.flash_mode=dout +m5stack_atom.menu.FlashMode.qout.build.boot=qout +m5stack_atom.menu.FlashMode.dout=DOUT +m5stack_atom.menu.FlashMode.dout.build.flash_mode=dout +m5stack_atom.menu.FlashMode.dout.build.boot=dout + +m5stack_atom.menu.FlashFreq.80=80MHz +m5stack_atom.menu.FlashFreq.80.build.flash_freq=80m +m5stack_atom.menu.FlashFreq.40=40MHz +m5stack_atom.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_atom.menu.FlashSize.4M=4MB (32Mb) +m5stack_atom.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_atom.menu.UploadSpeed.1500000=1500000 +m5stack_atom.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_atom.menu.UploadSpeed.750000=750000 +m5stack_atom.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_atom.menu.UploadSpeed.500000=500000 +m5stack_atom.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_atom.menu.UploadSpeed.250000=250000 +m5stack_atom.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_atom.menu.UploadSpeed.115200=115200 +m5stack_atom.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_atom.menu.LoopCore.1=Core 1 +m5stack_atom.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_atom.menu.LoopCore.0=Core 0 +m5stack_atom.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_atom.menu.EventsCore.1=Core 1 +m5stack_atom.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_atom.menu.EventsCore.0=Core 0 +m5stack_atom.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_atom.menu.DebugLevel.none=None +m5stack_atom.menu.DebugLevel.none.build.code_debug=0 +m5stack_atom.menu.DebugLevel.error=Error +m5stack_atom.menu.DebugLevel.error.build.code_debug=1 +m5stack_atom.menu.DebugLevel.warn=Warn +m5stack_atom.menu.DebugLevel.warn.build.code_debug=2 +m5stack_atom.menu.DebugLevel.info=Info +m5stack_atom.menu.DebugLevel.info.build.code_debug=3 +m5stack_atom.menu.DebugLevel.debug=Debug +m5stack_atom.menu.DebugLevel.debug.build.code_debug=4 +m5stack_atom.menu.DebugLevel.verbose=Verbose +m5stack_atom.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_atom.menu.EraseFlash.none=Disabled +m5stack_atom.menu.EraseFlash.none.upload.erase_cmd= +m5stack_atom.menu.EraseFlash.all=Enabled +m5stack_atom.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_atoms3.name=M5AtomS3 +m5stack_atoms3.bootloader.tool=esptool_py +m5stack_atoms3.bootloader.tool.default=esptool_py + +m5stack_atoms3.upload.tool=esptool_py +m5stack_atoms3.upload.tool.default=esptool_py +m5stack_atoms3.upload.tool.network=esp_ota + +m5stack_atoms3.upload.maximum_size=1310720 +m5stack_atoms3.upload.maximum_data_size=327680 +m5stack_atoms3.upload.flags= +m5stack_atoms3.upload.extra_flags= +m5stack_atoms3.upload.use_1200bps_touch=false +m5stack_atoms3.upload.wait_for_upload_port=false + +m5stack_atoms3.serial.disableDTR=false +m5stack_atoms3.serial.disableRTS=false + +m5stack_atoms3.build.tarch=xtensa +m5stack_atoms3.build.bootloader_addr=0x0 +m5stack_atoms3.build.target=esp32s3 +m5stack_atoms3.build.mcu=esp32s3 +m5stack_atoms3.build.core=esp32 +m5stack_atoms3.build.variant=m5stack_atoms3 +m5stack_atoms3.build.board=M5STACK_ATOMS3 + +m5stack_atoms3.build.usb_mode=1 +m5stack_atoms3.build.cdc_on_boot=1 +m5stack_atoms3.build.msc_on_boot=0 +m5stack_atoms3.build.dfu_on_boot=0 +m5stack_atoms3.build.f_cpu=240000000L +m5stack_atoms3.build.flash_size=8MB +m5stack_atoms3.build.flash_freq=80m +m5stack_atoms3.build.flash_mode=dio +m5stack_atoms3.build.boot=qio +m5stack_atoms3.build.boot_freq=80m +m5stack_atoms3.build.partitions=default +m5stack_atoms3.build.defines= +m5stack_atoms3.build.loop_core= +m5stack_atoms3.build.event_core= +m5stack_atoms3.build.psram_type=qspi +m5stack_atoms3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_atoms3.menu.JTAGAdapter.default=Disabled +m5stack_atoms3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_atoms3.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_atoms3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_atoms3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_atoms3.menu.JTAGAdapter.external=FTDI Adapter +m5stack_atoms3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_atoms3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_atoms3.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_atoms3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_atoms3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_atoms3.menu.PSRAM.disabled=Disabled +m5stack_atoms3.menu.PSRAM.disabled.build.defines= +m5stack_atoms3.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_atoms3.menu.PSRAM.enabled=QSPI PSRAM +m5stack_atoms3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_atoms3.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_atoms3.menu.PSRAM.opi=OPI PSRAM +m5stack_atoms3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_atoms3.menu.PSRAM.opi.build.psram_type=opi + +m5stack_atoms3.menu.FlashMode.qio=QIO 80MHz +m5stack_atoms3.menu.FlashMode.qio.build.flash_mode=dio +m5stack_atoms3.menu.FlashMode.qio.build.boot=qio +m5stack_atoms3.menu.FlashMode.qio.build.boot_freq=80m +m5stack_atoms3.menu.FlashMode.qio.build.flash_freq=80m +m5stack_atoms3.menu.FlashMode.qio120=QIO 120MHz +m5stack_atoms3.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_atoms3.menu.FlashMode.qio120.build.boot=qio +m5stack_atoms3.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_atoms3.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_atoms3.menu.FlashMode.dio=DIO 80MHz +m5stack_atoms3.menu.FlashMode.dio.build.flash_mode=dio +m5stack_atoms3.menu.FlashMode.dio.build.boot=dio +m5stack_atoms3.menu.FlashMode.dio.build.boot_freq=80m +m5stack_atoms3.menu.FlashMode.dio.build.flash_freq=80m +m5stack_atoms3.menu.FlashMode.opi=OPI 80MHz +m5stack_atoms3.menu.FlashMode.opi.build.flash_mode=dout +m5stack_atoms3.menu.FlashMode.opi.build.boot=opi +m5stack_atoms3.menu.FlashMode.opi.build.boot_freq=80m +m5stack_atoms3.menu.FlashMode.opi.build.flash_freq=80m + + +m5stack_atoms3.menu.FlashSize.8M=8MB (64Mb) +m5stack_atoms3.menu.FlashSize.8M.build.flash_size=8MB + +m5stack_atoms3.menu.LoopCore.1=Core 1 +m5stack_atoms3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_atoms3.menu.LoopCore.0=Core 0 +m5stack_atoms3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_atoms3.menu.EventsCore.1=Core 1 +m5stack_atoms3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_atoms3.menu.EventsCore.0=Core 0 +m5stack_atoms3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_atoms3.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_atoms3.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_atoms3.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_atoms3.menu.USBMode.default.build.usb_mode=0 + +m5stack_atoms3.menu.CDCOnBoot.cdc=Enabled +m5stack_atoms3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_atoms3.menu.CDCOnBoot.default=Disabled +m5stack_atoms3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_atoms3.menu.MSCOnBoot.default=Disabled +m5stack_atoms3.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_atoms3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_atoms3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_atoms3.menu.DFUOnBoot.default=Disabled +m5stack_atoms3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_atoms3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_atoms3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_atoms3.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_atoms3.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_atoms3.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_atoms3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_atoms3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_atoms3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_atoms3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.default.build.partitions=default +m5stack_atoms3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_atoms3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_atoms3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_atoms3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_atoms3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_atoms3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_atoms3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_atoms3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_atoms3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_atoms3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_atoms3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_atoms3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_atoms3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_atoms3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_atoms3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_atoms3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_atoms3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_atoms3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_atoms3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_atoms3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_atoms3.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_atoms3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_atoms3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_atoms3.menu.PartitionScheme.custom=Custom +m5stack_atoms3.menu.PartitionScheme.custom.build.partitions= +m5stack_atoms3.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +m5stack_atoms3.menu.CPUFreq.240=240MHz (WiFi) +m5stack_atoms3.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_atoms3.menu.CPUFreq.160=160MHz (WiFi) +m5stack_atoms3.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_atoms3.menu.CPUFreq.80=80MHz (WiFi) +m5stack_atoms3.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_atoms3.menu.CPUFreq.40=40MHz +m5stack_atoms3.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_atoms3.menu.CPUFreq.20=20MHz +m5stack_atoms3.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_atoms3.menu.CPUFreq.10=10MHz +m5stack_atoms3.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_atoms3.menu.UploadSpeed.921600=921600 +m5stack_atoms3.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_atoms3.menu.UploadSpeed.115200=115200 +m5stack_atoms3.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_atoms3.menu.UploadSpeed.256000.windows=256000 +m5stack_atoms3.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_atoms3.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_atoms3.menu.UploadSpeed.230400=230400 +m5stack_atoms3.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_atoms3.menu.UploadSpeed.460800.linux=460800 +m5stack_atoms3.menu.UploadSpeed.460800.macosx=460800 +m5stack_atoms3.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_atoms3.menu.UploadSpeed.512000.windows=512000 +m5stack_atoms3.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_atoms3.menu.DebugLevel.none=None +m5stack_atoms3.menu.DebugLevel.none.build.code_debug=0 +m5stack_atoms3.menu.DebugLevel.error=Error +m5stack_atoms3.menu.DebugLevel.error.build.code_debug=1 +m5stack_atoms3.menu.DebugLevel.warn=Warn +m5stack_atoms3.menu.DebugLevel.warn.build.code_debug=2 +m5stack_atoms3.menu.DebugLevel.info=Info +m5stack_atoms3.menu.DebugLevel.info.build.code_debug=3 +m5stack_atoms3.menu.DebugLevel.debug=Debug +m5stack_atoms3.menu.DebugLevel.debug.build.code_debug=4 +m5stack_atoms3.menu.DebugLevel.verbose=Verbose +m5stack_atoms3.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_atoms3.menu.EraseFlash.none=Disabled +m5stack_atoms3.menu.EraseFlash.none.upload.erase_cmd= +m5stack_atoms3.menu.EraseFlash.all=Enabled +m5stack_atoms3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_cores3.name=M5CoreS3 +m5stack_cores3.bootloader.tool=esptool_py +m5stack_cores3.bootloader.tool.default=esptool_py + +m5stack_cores3.upload.tool=esptool_py +m5stack_cores3.upload.tool.default=esptool_py +m5stack_cores3.upload.tool.network=esp_ota + +m5stack_cores3.upload.maximum_size=1310720 +m5stack_cores3.upload.maximum_data_size=327680 +m5stack_cores3.upload.flags= +m5stack_cores3.upload.extra_flags= +m5stack_cores3.upload.use_1200bps_touch=false +m5stack_cores3.upload.wait_for_upload_port=false + +m5stack_cores3.serial.disableDTR=false +m5stack_cores3.serial.disableRTS=false + +m5stack_cores3.build.tarch=xtensa +m5stack_cores3.build.bootloader_addr=0x0 +m5stack_cores3.build.target=esp32s3 +m5stack_cores3.build.mcu=esp32s3 +m5stack_cores3.build.core=esp32 +m5stack_cores3.build.variant=m5stack_cores3 +m5stack_cores3.build.board=M5STACK_CORES3 + +m5stack_cores3.build.usb_mode=1 +m5stack_cores3.build.cdc_on_boot=1 +m5stack_cores3.build.msc_on_boot=0 +m5stack_cores3.build.dfu_on_boot=0 +m5stack_cores3.build.f_cpu=240000000L +m5stack_cores3.build.flash_size=16MB +m5stack_cores3.build.flash_freq=80m +m5stack_cores3.build.flash_mode=dio +m5stack_cores3.build.boot=qio +m5stack_cores3.build.boot_freq=80m +m5stack_cores3.build.partitions=default +m5stack_cores3.build.defines= +m5stack_cores3.build.loop_core= +m5stack_cores3.build.event_core= +m5stack_cores3.build.psram_type=qspi +m5stack_cores3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_cores3.menu.JTAGAdapter.default=Disabled +m5stack_cores3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_cores3.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_cores3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_cores3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_cores3.menu.JTAGAdapter.external=FTDI Adapter +m5stack_cores3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_cores3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_cores3.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_cores3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_cores3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_cores3.menu.PSRAM.enabled=QSPI PSRAM +m5stack_cores3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_cores3.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_cores3.menu.PSRAM.disabled=Disabled +m5stack_cores3.menu.PSRAM.disabled.build.defines= +m5stack_cores3.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_cores3.menu.PSRAM.opi=OPI PSRAM +m5stack_cores3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_cores3.menu.PSRAM.opi.build.psram_type=opi + +m5stack_cores3.menu.FlashMode.qio=QIO 80MHz +m5stack_cores3.menu.FlashMode.qio.build.flash_mode=dio +m5stack_cores3.menu.FlashMode.qio.build.boot=qio +m5stack_cores3.menu.FlashMode.qio.build.boot_freq=80m +m5stack_cores3.menu.FlashMode.qio.build.flash_freq=80m +m5stack_cores3.menu.FlashMode.qio120=QIO 120MHz +m5stack_cores3.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_cores3.menu.FlashMode.qio120.build.boot=qio +m5stack_cores3.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_cores3.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_cores3.menu.FlashMode.dio=DIO 80MHz +m5stack_cores3.menu.FlashMode.dio.build.flash_mode=dio +m5stack_cores3.menu.FlashMode.dio.build.boot=dio +m5stack_cores3.menu.FlashMode.dio.build.boot_freq=80m +m5stack_cores3.menu.FlashMode.dio.build.flash_freq=80m +m5stack_cores3.menu.FlashMode.opi=OPI 80MHz +m5stack_cores3.menu.FlashMode.opi.build.flash_mode=dout +m5stack_cores3.menu.FlashMode.opi.build.boot=opi +m5stack_cores3.menu.FlashMode.opi.build.boot_freq=80m +m5stack_cores3.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_cores3.menu.FlashSize.16M=16MB (128Mb) +m5stack_cores3.menu.FlashSize.16M.build.flash_size=16MB +m5stack_cores3.menu.FlashSize.32M=32MB (256Mb) +m5stack_cores3.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_cores3.menu.LoopCore.1=Core 1 +m5stack_cores3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_cores3.menu.LoopCore.0=Core 0 +m5stack_cores3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_cores3.menu.EventsCore.1=Core 1 +m5stack_cores3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_cores3.menu.EventsCore.0=Core 0 +m5stack_cores3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_cores3.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_cores3.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_cores3.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_cores3.menu.USBMode.default.build.usb_mode=0 + +m5stack_cores3.menu.CDCOnBoot.cdc=Enabled +m5stack_cores3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_cores3.menu.CDCOnBoot.default=Disabled +m5stack_cores3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_cores3.menu.MSCOnBoot.default=Disabled +m5stack_cores3.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_cores3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_cores3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_cores3.menu.DFUOnBoot.default=Disabled +m5stack_cores3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_cores3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_cores3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_cores3.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_cores3.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_cores3.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_cores3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_cores3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_cores3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_cores3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.default.build.partitions=default +m5stack_cores3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_cores3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_cores3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_cores3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_cores3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_cores3.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_cores3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_cores3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_cores3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_cores3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_cores3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_cores3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_cores3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_cores3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_cores3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_cores3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_cores3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_cores3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_cores3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_cores3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_cores3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_cores3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_cores3.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_cores3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_cores3.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_cores3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_cores3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_cores3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_cores3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_cores3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_cores3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_cores3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_cores3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_cores3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_cores3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_cores3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_cores3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_cores3.menu.PartitionScheme.custom=Custom +m5stack_cores3.menu.PartitionScheme.custom.build.partitions= +m5stack_cores3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_cores3.menu.PartitionScheme.factory_4apps=16MB+Factory (4x 3MB APP/2MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.factory_4apps.build.custom_partitions=m5stack_partitions_16MB_factory_4_apps +m5stack_cores3.menu.PartitionScheme.factory_4apps.upload.maximum_size=3145728 +m5stack_cores3.menu.PartitionScheme.factory_6apps=16MB+Factory (6x 2MB APP/2MB SPIFFS) +m5stack_cores3.menu.PartitionScheme.factory_6apps.build.custom_partitions=m5stack_partitions_16MB_factory_6_apps +m5stack_cores3.menu.PartitionScheme.factory_6apps.upload.maximum_size=2097152 + +m5stack_cores3.menu.CPUFreq.240=240MHz (WiFi) +m5stack_cores3.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_cores3.menu.CPUFreq.160=160MHz (WiFi) +m5stack_cores3.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_cores3.menu.CPUFreq.80=80MHz (WiFi) +m5stack_cores3.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_cores3.menu.CPUFreq.40=40MHz +m5stack_cores3.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_cores3.menu.CPUFreq.20=20MHz +m5stack_cores3.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_cores3.menu.CPUFreq.10=10MHz +m5stack_cores3.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_cores3.menu.UploadSpeed.921600=921600 +m5stack_cores3.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_cores3.menu.UploadSpeed.115200=115200 +m5stack_cores3.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_cores3.menu.UploadSpeed.256000.windows=256000 +m5stack_cores3.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_cores3.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_cores3.menu.UploadSpeed.230400=230400 +m5stack_cores3.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_cores3.menu.UploadSpeed.460800.linux=460800 +m5stack_cores3.menu.UploadSpeed.460800.macosx=460800 +m5stack_cores3.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_cores3.menu.UploadSpeed.512000.windows=512000 +m5stack_cores3.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_cores3.menu.DebugLevel.none=None +m5stack_cores3.menu.DebugLevel.none.build.code_debug=0 +m5stack_cores3.menu.DebugLevel.error=Error +m5stack_cores3.menu.DebugLevel.error.build.code_debug=1 +m5stack_cores3.menu.DebugLevel.warn=Warn +m5stack_cores3.menu.DebugLevel.warn.build.code_debug=2 +m5stack_cores3.menu.DebugLevel.info=Info +m5stack_cores3.menu.DebugLevel.info.build.code_debug=3 +m5stack_cores3.menu.DebugLevel.debug=Debug +m5stack_cores3.menu.DebugLevel.debug.build.code_debug=4 +m5stack_cores3.menu.DebugLevel.verbose=Verbose +m5stack_cores3.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_cores3.menu.EraseFlash.none=Disabled +m5stack_cores3.menu.EraseFlash.none.upload.erase_cmd= +m5stack_cores3.menu.EraseFlash.all=Enabled +m5stack_cores3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_tab5.name=M5Tab5 + +m5stack_tab5.bootloader.tool=esptool_py +m5stack_tab5.bootloader.tool.default=esptool_py + +m5stack_tab5.upload.tool=esptool_py +m5stack_tab5.upload.tool.default=esptool_py +m5stack_tab5.upload.tool.network=esp_ota + +m5stack_tab5.upload.maximum_size=1310720 +m5stack_tab5.upload.maximum_data_size=327680 +m5stack_tab5.upload.flags= +m5stack_tab5.upload.extra_flags= +m5stack_tab5.upload.use_1200bps_touch=false +m5stack_tab5.upload.wait_for_upload_port=false + +m5stack_tab5.serial.disableDTR=false +m5stack_tab5.serial.disableRTS=false + +m5stack_tab5.build.tarch=riscv32 +m5stack_tab5.build.target=esp +m5stack_tab5.build.mcu=esp32p4 +m5stack_tab5.build.core=esp32 +m5stack_tab5.build.variant=m5stack_tab5 +m5stack_tab5.build.chip_variant=esp32p4_es +m5stack_tab5.build.board=M5STACK_TAB5 +m5stack_tab5.build.bootloader_addr=0x2000 + +m5stack_tab5.build.usb_mode=0 +m5stack_tab5.build.cdc_on_boot=0 +m5stack_tab5.build.msc_on_boot=0 +m5stack_tab5.build.dfu_on_boot=0 +m5stack_tab5.build.f_cpu=360000000L +m5stack_tab5.build.flash_size=16MB +m5stack_tab5.build.flash_freq=80m +m5stack_tab5.build.img_freq=80m +m5stack_tab5.build.flash_mode=qio +m5stack_tab5.build.boot=qio +m5stack_tab5.build.partitions=default +m5stack_tab5.build.defines= + +m5stack_tab5.menu.ChipVariant.prev3=Before v3.00 +m5stack_tab5.menu.ChipVariant.prev3.build.chip_variant=esp32p4_es +m5stack_tab5.menu.ChipVariant.prev3.build.f_cpu=360000000L +m5stack_tab5.menu.ChipVariant.postv3=v3.00 or newer +m5stack_tab5.menu.ChipVariant.postv3.build.chip_variant=esp32p4 +m5stack_tab5.menu.ChipVariant.postv3.build.f_cpu=400000000L + +## IDE 2.0 Seems to not update the value +m5stack_tab5.menu.JTAGAdapter.default=Disabled +m5stack_tab5.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_tab5.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_tab5.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg +m5stack_tab5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_tab5.menu.JTAGAdapter.external=FTDI Adapter +m5stack_tab5.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg +m5stack_tab5.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_tab5.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_tab5.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg +m5stack_tab5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_tab5.menu.PSRAM.enabled=Enabled +m5stack_tab5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_tab5.menu.PSRAM.disabled=Disabled +m5stack_tab5.menu.PSRAM.disabled.build.defines= + +m5stack_tab5.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_tab5.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_tab5.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_tab5.menu.USBMode.default.build.usb_mode=0 + +m5stack_tab5.menu.CDCOnBoot.cdc=Enabled +m5stack_tab5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_tab5.menu.CDCOnBoot.default=Disabled +m5stack_tab5.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_tab5.menu.MSCOnBoot.default=Disabled +m5stack_tab5.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_tab5.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_tab5.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_tab5.menu.DFUOnBoot.default=Disabled +m5stack_tab5.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_tab5.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_tab5.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_tab5.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_tab5.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_tab5.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_tab5.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_tab5.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_tab5.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_tab5.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_tab5.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_tab5.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_tab5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_tab5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_tab5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_tab5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_tab5.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_tab5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +m5stack_tab5.menu.PartitionScheme.no_fs.build.partitions=no_fs +m5stack_tab5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +m5stack_tab5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_tab5.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_tab5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_tab5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_tab5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_tab5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_tab5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_tab5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_tab5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_tab5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_tab5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_tab5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_tab5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_tab5.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_tab5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_tab5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_tab5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_tab5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_tab5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_tab5.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_tab5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_tab5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_tab5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_tab5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_tab5.menu.PartitionScheme.custom=Custom +m5stack_tab5.menu.PartitionScheme.custom.build.partitions= +m5stack_tab5.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +## From https://docs.espressif.com/projects/esp-idf/en/latest/esp32p4/api-reference/kconfig.html#config-esp-default-cpu-freq-mhz +m5stack_tab5.menu.CPUFreq.360=360MHz +m5stack_tab5.menu.CPUFreq.360.build.f_cpu=360000000L +m5stack_tab5.menu.CPUFreq.40=40MHz +m5stack_tab5.menu.CPUFreq.40.build.f_cpu=40000000L + +m5stack_tab5.menu.FlashMode.qio=QIO +m5stack_tab5.menu.FlashMode.qio.build.flash_mode=dio +m5stack_tab5.menu.FlashMode.qio.build.boot=qio +m5stack_tab5.menu.FlashMode.dio=DIO +m5stack_tab5.menu.FlashMode.dio.build.flash_mode=dio +m5stack_tab5.menu.FlashMode.dio.build.boot=dio + +m5stack_tab5.menu.FlashFreq.80=80MHz +m5stack_tab5.menu.FlashFreq.80.build.flash_freq=80m +m5stack_tab5.menu.FlashFreq.40=40MHz +m5stack_tab5.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_tab5.menu.FlashSize.16M=16MB (128Mb) +m5stack_tab5.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_tab5.menu.UploadSpeed.921600=921600 +m5stack_tab5.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_tab5.menu.UploadSpeed.115200=115200 +m5stack_tab5.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_tab5.menu.UploadSpeed.256000.windows=256000 +m5stack_tab5.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_tab5.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_tab5.menu.UploadSpeed.230400=230400 +m5stack_tab5.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_tab5.menu.UploadSpeed.460800.linux=460800 +m5stack_tab5.menu.UploadSpeed.460800.macosx=460800 +m5stack_tab5.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_tab5.menu.UploadSpeed.512000.windows=512000 +m5stack_tab5.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_tab5.menu.DebugLevel.none=None +m5stack_tab5.menu.DebugLevel.none.build.code_debug=0 +m5stack_tab5.menu.DebugLevel.error=Error +m5stack_tab5.menu.DebugLevel.error.build.code_debug=1 +m5stack_tab5.menu.DebugLevel.warn=Warn +m5stack_tab5.menu.DebugLevel.warn.build.code_debug=2 +m5stack_tab5.menu.DebugLevel.info=Info +m5stack_tab5.menu.DebugLevel.info.build.code_debug=3 +m5stack_tab5.menu.DebugLevel.debug=Debug +m5stack_tab5.menu.DebugLevel.debug.build.code_debug=4 +m5stack_tab5.menu.DebugLevel.verbose=Verbose +m5stack_tab5.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_tab5.menu.EraseFlash.none=Disabled +m5stack_tab5.menu.EraseFlash.none.upload.erase_cmd= +m5stack_tab5.menu.EraseFlash.all=Enabled +m5stack_tab5.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +m5stack_timer_cam.name=M5TimerCAM + +m5stack_timer_cam.bootloader.tool=esptool_py +m5stack_timer_cam.bootloader.tool.default=esptool_py + +m5stack_timer_cam.upload.tool=esptool_py +m5stack_timer_cam.upload.tool.default=esptool_py +m5stack_timer_cam.upload.tool.network=esp_ota + +m5stack_timer_cam.upload.maximum_size=1310720 +m5stack_timer_cam.upload.maximum_data_size=327680 + +m5stack_timer_cam.upload.flags= +m5stack_timer_cam.upload.extra_flags= + +m5stack_timer_cam.serial.disableDTR=true +m5stack_timer_cam.serial.disableRTS=true + +m5stack_timer_cam.build.tarch=xtensa +m5stack_timer_cam.build.bootloader_addr=0x1000 +m5stack_timer_cam.build.target=esp32 +m5stack_timer_cam.build.mcu=esp32 +m5stack_timer_cam.build.core=esp32 +m5stack_timer_cam.build.variant=m5stack_timer_cam +m5stack_timer_cam.build.board=M5STACK_TIMER_CAM + +m5stack_timer_cam.build.f_cpu=240000000L +m5stack_timer_cam.build.flash_size=4MB +m5stack_timer_cam.build.flash_freq=80m +m5stack_timer_cam.build.flash_mode=dio +m5stack_timer_cam.build.boot=dio +m5stack_timer_cam.build.partitions=default +m5stack_timer_cam.build.defines= +m5stack_timer_cam.build.loop_core= +m5stack_timer_cam.build.event_core= + +m5stack_timer_cam.menu.PSRAM.enabled=Enabled +m5stack_timer_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_timer_cam.menu.PSRAM.enabled.build.extra_libs= +m5stack_timer_cam.menu.PSRAM.disabled=Disabled +m5stack_timer_cam.menu.PSRAM.disabled.build.defines= +m5stack_timer_cam.menu.PSRAM.disabled.build.extra_libs= + +m5stack_timer_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.default.build.partitions=default +m5stack_timer_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_timer_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_timer_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_timer_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_timer_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_timer_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_timer_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_timer_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_timer_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_timer_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_timer_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_timer_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_timer_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_timer_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_timer_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_timer_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_timer_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_timer_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +m5stack_timer_cam.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_timer_cam.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_timer_cam.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_timer_cam.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_timer_cam.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_timer_cam.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_timer_cam.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_timer_cam.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_timer_cam.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_timer_cam.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_timer_cam.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_timer_cam.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_timer_cam.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_timer_cam.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_timer_cam.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_timer_cam.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_timer_cam.menu.FlashMode.qio=QIO +m5stack_timer_cam.menu.FlashMode.qio.build.flash_mode=dio +m5stack_timer_cam.menu.FlashMode.qio.build.boot=qio +m5stack_timer_cam.menu.FlashMode.dio=DIO +m5stack_timer_cam.menu.FlashMode.dio.build.flash_mode=dio +m5stack_timer_cam.menu.FlashMode.dio.build.boot=dio +m5stack_timer_cam.menu.FlashMode.qout=QOUT +m5stack_timer_cam.menu.FlashMode.qout.build.flash_mode=dout +m5stack_timer_cam.menu.FlashMode.qout.build.boot=qout +m5stack_timer_cam.menu.FlashMode.dout=DOUT +m5stack_timer_cam.menu.FlashMode.dout.build.flash_mode=dout +m5stack_timer_cam.menu.FlashMode.dout.build.boot=dout + +m5stack_timer_cam.menu.FlashFreq.80=80MHz +m5stack_timer_cam.menu.FlashFreq.80.build.flash_freq=80m +m5stack_timer_cam.menu.FlashFreq.40=40MHz +m5stack_timer_cam.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_timer_cam.menu.FlashSize.4M=4MB (32Mb) +m5stack_timer_cam.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_timer_cam.menu.UploadSpeed.1500000=1500000 +m5stack_timer_cam.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_timer_cam.menu.UploadSpeed.750000=750000 +m5stack_timer_cam.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_timer_cam.menu.UploadSpeed.500000=500000 +m5stack_timer_cam.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_timer_cam.menu.UploadSpeed.250000=250000 +m5stack_timer_cam.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_timer_cam.menu.UploadSpeed.115200=115200 +m5stack_timer_cam.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_timer_cam.menu.LoopCore.1=Core 1 +m5stack_timer_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_timer_cam.menu.LoopCore.0=Core 0 +m5stack_timer_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_timer_cam.menu.EventsCore.1=Core 1 +m5stack_timer_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_timer_cam.menu.EventsCore.0=Core 0 +m5stack_timer_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_timer_cam.menu.DebugLevel.none=None +m5stack_timer_cam.menu.DebugLevel.none.build.code_debug=0 +m5stack_timer_cam.menu.DebugLevel.error=Error +m5stack_timer_cam.menu.DebugLevel.error.build.code_debug=1 +m5stack_timer_cam.menu.DebugLevel.warn=Warn +m5stack_timer_cam.menu.DebugLevel.warn.build.code_debug=2 +m5stack_timer_cam.menu.DebugLevel.info=Info +m5stack_timer_cam.menu.DebugLevel.info.build.code_debug=3 +m5stack_timer_cam.menu.DebugLevel.debug=Debug +m5stack_timer_cam.menu.DebugLevel.debug.build.code_debug=4 +m5stack_timer_cam.menu.DebugLevel.verbose=Verbose +m5stack_timer_cam.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_timer_cam.menu.EraseFlash.none=Disabled +m5stack_timer_cam.menu.EraseFlash.none.upload.erase_cmd= +m5stack_timer_cam.menu.EraseFlash.all=Enabled +m5stack_timer_cam.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +m5stack_unit_cam.name=M5UnitCAM + +m5stack_unit_cam.bootloader.tool=esptool_py +m5stack_unit_cam.bootloader.tool.default=esptool_py + +m5stack_unit_cam.upload.tool=esptool_py +m5stack_unit_cam.upload.tool.default=esptool_py +m5stack_unit_cam.upload.tool.network=esp_ota + +m5stack_unit_cam.upload.maximum_size=1310720 +m5stack_unit_cam.upload.maximum_data_size=327680 + +m5stack_unit_cam.upload.flags= +m5stack_unit_cam.upload.extra_flags= + +m5stack_unit_cam.serial.disableDTR=true +m5stack_unit_cam.serial.disableRTS=true + +m5stack_unit_cam.build.tarch=xtensa +m5stack_unit_cam.build.bootloader_addr=0x1000 +m5stack_unit_cam.build.target=esp32 +m5stack_unit_cam.build.mcu=esp32 +m5stack_unit_cam.build.core=esp32 +m5stack_unit_cam.build.variant=m5stack_unit_cam +m5stack_unit_cam.build.board=M5STACK_UNIT_CAM + +m5stack_unit_cam.build.f_cpu=240000000L +m5stack_unit_cam.build.flash_size=4MB +m5stack_unit_cam.build.flash_freq=80m +m5stack_unit_cam.build.flash_mode=dio +m5stack_unit_cam.build.boot=dio +m5stack_unit_cam.build.partitions=default +m5stack_unit_cam.build.defines= +m5stack_unit_cam.build.loop_core= +m5stack_unit_cam.build.event_core= + +m5stack_unit_cam.menu.PSRAM.enabled=Enabled +m5stack_unit_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_unit_cam.menu.PSRAM.enabled.build.extra_libs= +m5stack_unit_cam.menu.PSRAM.disabled=Disabled +m5stack_unit_cam.menu.PSRAM.disabled.build.defines= +m5stack_unit_cam.menu.PSRAM.disabled.build.extra_libs= + +m5stack_unit_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.default.build.partitions=default +m5stack_unit_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_unit_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_unit_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_unit_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_unit_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_unit_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_unit_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_unit_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_unit_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_unit_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_unit_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_unit_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_unit_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_unit_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_unit_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_unit_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_unit_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_unit_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +m5stack_unit_cam.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_unit_cam.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_unit_cam.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_unit_cam.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_unit_cam.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_unit_cam.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_unit_cam.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_unit_cam.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_unit_cam.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_unit_cam.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_unit_cam.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_unit_cam.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_unit_cam.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_unit_cam.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_unit_cam.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_unit_cam.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_unit_cam.menu.FlashMode.qio=QIO +m5stack_unit_cam.menu.FlashMode.qio.build.flash_mode=dio +m5stack_unit_cam.menu.FlashMode.qio.build.boot=qio +m5stack_unit_cam.menu.FlashMode.dio=DIO +m5stack_unit_cam.menu.FlashMode.dio.build.flash_mode=dio +m5stack_unit_cam.menu.FlashMode.dio.build.boot=dio +m5stack_unit_cam.menu.FlashMode.qout=QOUT +m5stack_unit_cam.menu.FlashMode.qout.build.flash_mode=dout +m5stack_unit_cam.menu.FlashMode.qout.build.boot=qout +m5stack_unit_cam.menu.FlashMode.dout=DOUT +m5stack_unit_cam.menu.FlashMode.dout.build.flash_mode=dout +m5stack_unit_cam.menu.FlashMode.dout.build.boot=dout + +m5stack_unit_cam.menu.FlashFreq.80=80MHz +m5stack_unit_cam.menu.FlashFreq.80.build.flash_freq=80m +m5stack_unit_cam.menu.FlashFreq.40=40MHz +m5stack_unit_cam.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_unit_cam.menu.FlashSize.4M=4MB (32Mb) +m5stack_unit_cam.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_unit_cam.menu.UploadSpeed.1500000=1500000 +m5stack_unit_cam.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_unit_cam.menu.UploadSpeed.750000=750000 +m5stack_unit_cam.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_unit_cam.menu.UploadSpeed.500000=500000 +m5stack_unit_cam.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_unit_cam.menu.UploadSpeed.250000=250000 +m5stack_unit_cam.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_unit_cam.menu.UploadSpeed.115200=115200 +m5stack_unit_cam.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_unit_cam.menu.LoopCore.1=Core 1 +m5stack_unit_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_unit_cam.menu.LoopCore.0=Core 0 +m5stack_unit_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_unit_cam.menu.EventsCore.1=Core 1 +m5stack_unit_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_unit_cam.menu.EventsCore.0=Core 0 +m5stack_unit_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_unit_cam.menu.DebugLevel.none=None +m5stack_unit_cam.menu.DebugLevel.none.build.code_debug=0 +m5stack_unit_cam.menu.DebugLevel.error=Error +m5stack_unit_cam.menu.DebugLevel.error.build.code_debug=1 +m5stack_unit_cam.menu.DebugLevel.warn=Warn +m5stack_unit_cam.menu.DebugLevel.warn.build.code_debug=2 +m5stack_unit_cam.menu.DebugLevel.info=Info +m5stack_unit_cam.menu.DebugLevel.info.build.code_debug=3 +m5stack_unit_cam.menu.DebugLevel.debug=Debug +m5stack_unit_cam.menu.DebugLevel.debug.build.code_debug=4 +m5stack_unit_cam.menu.DebugLevel.verbose=Verbose +m5stack_unit_cam.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_unit_cam.menu.EraseFlash.none=Disabled +m5stack_unit_cam.menu.EraseFlash.none.upload.erase_cmd= +m5stack_unit_cam.menu.EraseFlash.all=Enabled +m5stack_unit_cam.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +m5stack_unit_cams3.name=M5UnitCAMS3 +m5stack_unit_cams3.bootloader.tool=esptool_py +m5stack_unit_cams3.bootloader.tool.default=esptool_py + +m5stack_unit_cams3.upload.tool=esptool_py +m5stack_unit_cams3.upload.tool.default=esptool_py +m5stack_unit_cams3.upload.tool.network=esp_ota + +m5stack_unit_cams3.upload.maximum_size=1310720 +m5stack_unit_cams3.upload.maximum_data_size=327680 +m5stack_unit_cams3.upload.flags= +m5stack_unit_cams3.upload.extra_flags= +m5stack_unit_cams3.upload.use_1200bps_touch=false +m5stack_unit_cams3.upload.wait_for_upload_port=false + +m5stack_unit_cams3.serial.disableDTR=false +m5stack_unit_cams3.serial.disableRTS=false + +m5stack_unit_cams3.build.tarch=xtensa +m5stack_unit_cams3.build.bootloader_addr=0x0 +m5stack_unit_cams3.build.target=esp32s3 +m5stack_unit_cams3.build.mcu=esp32s3 +m5stack_unit_cams3.build.core=esp32 +m5stack_unit_cams3.build.variant=m5stack_unit_cams3 +m5stack_unit_cams3.build.board=M5STACK_UNIT_CAMS3 + +m5stack_unit_cams3.build.usb_mode=1 +m5stack_unit_cams3.build.cdc_on_boot=1 +m5stack_unit_cams3.build.msc_on_boot=0 +m5stack_unit_cams3.build.dfu_on_boot=0 +m5stack_unit_cams3.build.f_cpu=240000000L +m5stack_unit_cams3.build.flash_size=16MB +m5stack_unit_cams3.build.flash_freq=80m +m5stack_unit_cams3.build.flash_mode=dio +m5stack_unit_cams3.build.boot=qio +m5stack_unit_cams3.build.boot_freq=80m +m5stack_unit_cams3.build.partitions=default +m5stack_unit_cams3.build.defines= +m5stack_unit_cams3.build.loop_core= +m5stack_unit_cams3.build.event_core= +m5stack_unit_cams3.build.psram_type=qspi +m5stack_unit_cams3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_unit_cams3.menu.JTAGAdapter.default=Disabled +m5stack_unit_cams3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_unit_cams3.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_unit_cams3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_unit_cams3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_unit_cams3.menu.JTAGAdapter.external=FTDI Adapter +m5stack_unit_cams3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_unit_cams3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_unit_cams3.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_unit_cams3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_unit_cams3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_unit_cams3.menu.PSRAM.enabled=QSPI PSRAM +m5stack_unit_cams3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_unit_cams3.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_unit_cams3.menu.PSRAM.disabled=Disabled +m5stack_unit_cams3.menu.PSRAM.disabled.build.defines= +m5stack_unit_cams3.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_unit_cams3.menu.PSRAM.opi=OPI PSRAM +m5stack_unit_cams3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_unit_cams3.menu.PSRAM.opi.build.psram_type=opi + +m5stack_unit_cams3.menu.FlashMode.qio=QIO 80MHz +m5stack_unit_cams3.menu.FlashMode.qio.build.flash_mode=dio +m5stack_unit_cams3.menu.FlashMode.qio.build.boot=qio +m5stack_unit_cams3.menu.FlashMode.qio.build.boot_freq=80m +m5stack_unit_cams3.menu.FlashMode.qio.build.flash_freq=80m +m5stack_unit_cams3.menu.FlashMode.qio120=QIO 120MHz +m5stack_unit_cams3.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_unit_cams3.menu.FlashMode.qio120.build.boot=qio +m5stack_unit_cams3.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_unit_cams3.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_unit_cams3.menu.FlashMode.dio=DIO 80MHz +m5stack_unit_cams3.menu.FlashMode.dio.build.flash_mode=dio +m5stack_unit_cams3.menu.FlashMode.dio.build.boot=dio +m5stack_unit_cams3.menu.FlashMode.dio.build.boot_freq=80m +m5stack_unit_cams3.menu.FlashMode.dio.build.flash_freq=80m +m5stack_unit_cams3.menu.FlashMode.opi=OPI 80MHz +m5stack_unit_cams3.menu.FlashMode.opi.build.flash_mode=dout +m5stack_unit_cams3.menu.FlashMode.opi.build.boot=opi +m5stack_unit_cams3.menu.FlashMode.opi.build.boot_freq=80m +m5stack_unit_cams3.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_unit_cams3.menu.FlashSize.16M=16MB (128Mb) +m5stack_unit_cams3.menu.FlashSize.16M.build.flash_size=16MB +m5stack_unit_cams3.menu.FlashSize.32M=32MB (256Mb) +m5stack_unit_cams3.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_unit_cams3.menu.LoopCore.1=Core 1 +m5stack_unit_cams3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_unit_cams3.menu.LoopCore.0=Core 0 +m5stack_unit_cams3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_unit_cams3.menu.EventsCore.1=Core 1 +m5stack_unit_cams3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_unit_cams3.menu.EventsCore.0=Core 0 +m5stack_unit_cams3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_unit_cams3.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_unit_cams3.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_unit_cams3.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_unit_cams3.menu.USBMode.default.build.usb_mode=0 + +m5stack_unit_cams3.menu.CDCOnBoot.cdc=Enabled +m5stack_unit_cams3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_unit_cams3.menu.CDCOnBoot.default=Disabled +m5stack_unit_cams3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_unit_cams3.menu.MSCOnBoot.default=Disabled +m5stack_unit_cams3.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_unit_cams3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_unit_cams3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_unit_cams3.menu.DFUOnBoot.default=Disabled +m5stack_unit_cams3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_unit_cams3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_unit_cams3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_unit_cams3.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_unit_cams3.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_unit_cams3.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_unit_cams3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_unit_cams3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_unit_cams3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_unit_cams3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.default.build.partitions=default +m5stack_unit_cams3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_unit_cams3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_unit_cams3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_unit_cams3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_unit_cams3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_unit_cams3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_unit_cams3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_unit_cams3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_unit_cams3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_unit_cams3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_unit_cams3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_unit_cams3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_unit_cams3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_unit_cams3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_unit_cams3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_unit_cams3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_unit_cams3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_unit_cams3.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_unit_cams3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_unit_cams3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_unit_cams3.menu.PartitionScheme.custom=Custom +m5stack_unit_cams3.menu.PartitionScheme.custom.build.partitions= +m5stack_unit_cams3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_unit_cams3.menu.CPUFreq.240=240MHz (WiFi) +m5stack_unit_cams3.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_unit_cams3.menu.CPUFreq.160=160MHz (WiFi) +m5stack_unit_cams3.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_unit_cams3.menu.CPUFreq.80=80MHz (WiFi) +m5stack_unit_cams3.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_unit_cams3.menu.CPUFreq.40=40MHz +m5stack_unit_cams3.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_unit_cams3.menu.CPUFreq.20=20MHz +m5stack_unit_cams3.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_unit_cams3.menu.CPUFreq.10=10MHz +m5stack_unit_cams3.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_unit_cams3.menu.UploadSpeed.921600=921600 +m5stack_unit_cams3.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_unit_cams3.menu.UploadSpeed.115200=115200 +m5stack_unit_cams3.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_unit_cams3.menu.UploadSpeed.256000.windows=256000 +m5stack_unit_cams3.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_unit_cams3.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_unit_cams3.menu.UploadSpeed.230400=230400 +m5stack_unit_cams3.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_unit_cams3.menu.UploadSpeed.460800.linux=460800 +m5stack_unit_cams3.menu.UploadSpeed.460800.macosx=460800 +m5stack_unit_cams3.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_unit_cams3.menu.UploadSpeed.512000.windows=512000 +m5stack_unit_cams3.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_unit_cams3.menu.DebugLevel.none=None +m5stack_unit_cams3.menu.DebugLevel.none.build.code_debug=0 +m5stack_unit_cams3.menu.DebugLevel.error=Error +m5stack_unit_cams3.menu.DebugLevel.error.build.code_debug=1 +m5stack_unit_cams3.menu.DebugLevel.warn=Warn +m5stack_unit_cams3.menu.DebugLevel.warn.build.code_debug=2 +m5stack_unit_cams3.menu.DebugLevel.info=Info +m5stack_unit_cams3.menu.DebugLevel.info.build.code_debug=3 +m5stack_unit_cams3.menu.DebugLevel.debug=Debug +m5stack_unit_cams3.menu.DebugLevel.debug.build.code_debug=4 +m5stack_unit_cams3.menu.DebugLevel.verbose=Verbose +m5stack_unit_cams3.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_unit_cams3.menu.EraseFlash.none=Disabled +m5stack_unit_cams3.menu.EraseFlash.none.upload.erase_cmd= +m5stack_unit_cams3.menu.EraseFlash.all=Enabled +m5stack_unit_cams3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_poe_cam.name=M5PoECAM + +m5stack_poe_cam.bootloader.tool=esptool_py +m5stack_poe_cam.bootloader.tool.default=esptool_py + +m5stack_poe_cam.upload.tool=esptool_py +m5stack_poe_cam.upload.tool.default=esptool_py +m5stack_poe_cam.upload.tool.network=esp_ota + +m5stack_poe_cam.upload.maximum_size=1310720 +m5stack_poe_cam.upload.maximum_data_size=327680 + +m5stack_poe_cam.upload.flags= +m5stack_poe_cam.upload.extra_flags= + +m5stack_poe_cam.serial.disableDTR=true +m5stack_poe_cam.serial.disableRTS=true + +m5stack_poe_cam.build.tarch=xtensa +m5stack_poe_cam.build.bootloader_addr=0x1000 +m5stack_poe_cam.build.target=esp32 +m5stack_poe_cam.build.mcu=esp32 +m5stack_poe_cam.build.core=esp32 +m5stack_poe_cam.build.variant=m5stack_poe_cam +m5stack_poe_cam.build.board=M5STACK_POE_CAM + +m5stack_poe_cam.build.f_cpu=240000000L +m5stack_poe_cam.build.flash_size=4MB +m5stack_poe_cam.build.flash_freq=80m +m5stack_poe_cam.build.flash_mode=dio +m5stack_poe_cam.build.boot=dio +m5stack_poe_cam.build.partitions=default +m5stack_poe_cam.build.defines= +m5stack_poe_cam.build.loop_core= +m5stack_poe_cam.build.event_core= + +m5stack_poe_cam.menu.PSRAM.enabled=Enabled +m5stack_poe_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_poe_cam.menu.PSRAM.enabled.build.extra_libs= +m5stack_poe_cam.menu.PSRAM.disabled=Disabled +m5stack_poe_cam.menu.PSRAM.disabled.build.defines= +m5stack_poe_cam.menu.PSRAM.disabled.build.extra_libs= + +m5stack_poe_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.default.build.partitions=default +m5stack_poe_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_poe_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_poe_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_poe_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_poe_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_poe_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_poe_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_poe_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_poe_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_poe_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_poe_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_poe_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_poe_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_poe_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_poe_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_poe_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_poe_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_poe_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +m5stack_poe_cam.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_poe_cam.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_poe_cam.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_poe_cam.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_poe_cam.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_poe_cam.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_poe_cam.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_poe_cam.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_poe_cam.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_poe_cam.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_poe_cam.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_poe_cam.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_poe_cam.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_poe_cam.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_poe_cam.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_poe_cam.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_poe_cam.menu.FlashMode.qio=QIO +m5stack_poe_cam.menu.FlashMode.qio.build.flash_mode=dio +m5stack_poe_cam.menu.FlashMode.qio.build.boot=qio +m5stack_poe_cam.menu.FlashMode.dio=DIO +m5stack_poe_cam.menu.FlashMode.dio.build.flash_mode=dio +m5stack_poe_cam.menu.FlashMode.dio.build.boot=dio +m5stack_poe_cam.menu.FlashMode.qout=QOUT +m5stack_poe_cam.menu.FlashMode.qout.build.flash_mode=dout +m5stack_poe_cam.menu.FlashMode.qout.build.boot=qout +m5stack_poe_cam.menu.FlashMode.dout=DOUT +m5stack_poe_cam.menu.FlashMode.dout.build.flash_mode=dout +m5stack_poe_cam.menu.FlashMode.dout.build.boot=dout + +m5stack_poe_cam.menu.FlashFreq.80=80MHz +m5stack_poe_cam.menu.FlashFreq.80.build.flash_freq=80m +m5stack_poe_cam.menu.FlashFreq.40=40MHz +m5stack_poe_cam.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_poe_cam.menu.FlashSize.4M=4MB (32Mb) +m5stack_poe_cam.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_poe_cam.menu.UploadSpeed.1500000=1500000 +m5stack_poe_cam.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_poe_cam.menu.UploadSpeed.750000=750000 +m5stack_poe_cam.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_poe_cam.menu.UploadSpeed.500000=500000 +m5stack_poe_cam.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_poe_cam.menu.UploadSpeed.250000=250000 +m5stack_poe_cam.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_poe_cam.menu.UploadSpeed.115200=115200 +m5stack_poe_cam.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_poe_cam.menu.LoopCore.1=Core 1 +m5stack_poe_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_poe_cam.menu.LoopCore.0=Core 0 +m5stack_poe_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_poe_cam.menu.EventsCore.1=Core 1 +m5stack_poe_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_poe_cam.menu.EventsCore.0=Core 0 +m5stack_poe_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_poe_cam.menu.DebugLevel.none=None +m5stack_poe_cam.menu.DebugLevel.none.build.code_debug=0 +m5stack_poe_cam.menu.DebugLevel.error=Error +m5stack_poe_cam.menu.DebugLevel.error.build.code_debug=1 +m5stack_poe_cam.menu.DebugLevel.warn=Warn +m5stack_poe_cam.menu.DebugLevel.warn.build.code_debug=2 +m5stack_poe_cam.menu.DebugLevel.info=Info +m5stack_poe_cam.menu.DebugLevel.info.build.code_debug=3 +m5stack_poe_cam.menu.DebugLevel.debug=Debug +m5stack_poe_cam.menu.DebugLevel.debug.build.code_debug=4 +m5stack_poe_cam.menu.DebugLevel.verbose=Verbose +m5stack_poe_cam.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_poe_cam.menu.EraseFlash.none=Disabled +m5stack_poe_cam.menu.EraseFlash.none.upload.erase_cmd= +m5stack_poe_cam.menu.EraseFlash.all=Enabled +m5stack_poe_cam.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_paper.name=M5Paper + +m5stack_paper.bootloader.tool=esptool_py +m5stack_paper.bootloader.tool.default=esptool_py + +m5stack_paper.upload.tool=esptool_py +m5stack_paper.upload.tool.default=esptool_py +m5stack_paper.upload.tool.network=esp_ota + +m5stack_paper.upload.maximum_size=6553600 +m5stack_paper.upload.maximum_data_size=4521984 +m5stack_paper.upload.flags= +m5stack_paper.upload.extra_flags= + +m5stack_paper.serial.disableDTR=true +m5stack_paper.serial.disableRTS=true + +m5stack_paper.build.tarch=xtensa +m5stack_paper.build.bootloader_addr=0x1000 +m5stack_paper.build.target=esp32 +m5stack_paper.build.mcu=esp32 +m5stack_paper.build.core=esp32 +m5stack_paper.build.variant=m5stack_paper +m5stack_paper.build.board=M5STACK_PAPER + +m5stack_paper.build.f_cpu=240000000L +m5stack_paper.build.flash_size=16MB +m5stack_paper.build.flash_freq=80m +m5stack_paper.build.flash_mode=dio +m5stack_paper.build.boot=dio +m5stack_paper.build.partitions=default +m5stack_paper.build.defines= +m5stack_paper.build.loop_core= +m5stack_paper.build.event_core= + +m5stack_paper.menu.PSRAM.enabled=Enabled +m5stack_paper.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +m5stack_paper.menu.PSRAM.enabled.build.extra_libs= +m5stack_paper.menu.PSRAM.disabled=Disabled +m5stack_paper.menu.PSRAM.disabled.build.defines= +m5stack_paper.menu.PSRAM.disabled.build.extra_libs= + +m5stack_paper.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +m5stack_paper.menu.PartitionScheme.default.build.partitions=default_16MB +m5stack_paper.menu.PartitionScheme.default.upload.maximum_size=6553600 +m5stack_paper.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_paper.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_paper.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_paper.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_paper.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_paper.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_paper.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_paper.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_paper.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_paper.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_paper.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_paper.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_paper.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_paper.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_paper.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_paper.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_paper.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_paper.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_paper.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_paper.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_paper.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_paper.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_paper.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_paper.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_paper.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_paper.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_paper.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_paper.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_paper.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_paper.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_paper.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_paper.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_paper.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_paper.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_paper.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_paper.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_paper.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_paper.menu.PartitionScheme.custom=Custom +m5stack_paper.menu.PartitionScheme.custom.build.partitions= +m5stack_paper.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_paper.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_paper.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_paper.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_paper.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_paper.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_paper.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_paper.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_paper.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_paper.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_paper.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_paper.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_paper.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_paper.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_paper.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_paper.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_paper.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_paper.menu.FlashMode.qio=QIO +m5stack_paper.menu.FlashMode.qio.build.flash_mode=dio +m5stack_paper.menu.FlashMode.qio.build.boot=qio +m5stack_paper.menu.FlashMode.dio=DIO +m5stack_paper.menu.FlashMode.dio.build.flash_mode=dio +m5stack_paper.menu.FlashMode.dio.build.boot=dio +m5stack_paper.menu.FlashMode.qout=QOUT +m5stack_paper.menu.FlashMode.qout.build.flash_mode=dout +m5stack_paper.menu.FlashMode.qout.build.boot=qout +m5stack_paper.menu.FlashMode.dout=DOUT +m5stack_paper.menu.FlashMode.dout.build.flash_mode=dout +m5stack_paper.menu.FlashMode.dout.build.boot=dout + +m5stack_paper.menu.FlashFreq.80=80MHz +m5stack_paper.menu.FlashFreq.80.build.flash_freq=80m +m5stack_paper.menu.FlashFreq.40=40MHz +m5stack_paper.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_paper.menu.FlashSize.16M=16MB (128Mb) +m5stack_paper.menu.FlashSize.16M.build.flash_size=16MB + +m5stack_paper.menu.UploadSpeed.1500000=1500000 +m5stack_paper.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_paper.menu.UploadSpeed.921600=921600 +m5stack_paper.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_paper.menu.UploadSpeed.115200=115200 +m5stack_paper.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_paper.menu.UploadSpeed.256000.windows=256000 +m5stack_paper.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_paper.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_paper.menu.UploadSpeed.230400=230400 +m5stack_paper.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_paper.menu.UploadSpeed.460800.linux=460800 +m5stack_paper.menu.UploadSpeed.460800.macosx=460800 +m5stack_paper.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_paper.menu.UploadSpeed.512000.windows=512000 +m5stack_paper.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_paper.menu.LoopCore.1=Core 1 +m5stack_paper.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_paper.menu.LoopCore.0=Core 0 +m5stack_paper.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_paper.menu.EventsCore.1=Core 1 +m5stack_paper.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_paper.menu.EventsCore.0=Core 0 +m5stack_paper.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_paper.menu.DebugLevel.none=None +m5stack_paper.menu.DebugLevel.none.build.code_debug=0 +m5stack_paper.menu.DebugLevel.error=Error +m5stack_paper.menu.DebugLevel.error.build.code_debug=1 +m5stack_paper.menu.DebugLevel.warn=Warn +m5stack_paper.menu.DebugLevel.warn.build.code_debug=2 +m5stack_paper.menu.DebugLevel.info=Info +m5stack_paper.menu.DebugLevel.info.build.code_debug=3 +m5stack_paper.menu.DebugLevel.debug=Debug +m5stack_paper.menu.DebugLevel.debug.build.code_debug=4 +m5stack_paper.menu.DebugLevel.verbose=Verbose +m5stack_paper.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_paper.menu.EraseFlash.none=Disabled +m5stack_paper.menu.EraseFlash.none.upload.erase_cmd= +m5stack_paper.menu.EraseFlash.all=Enabled +m5stack_paper.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_coreink.name=M5CoreInk + +m5stack_coreink.bootloader.tool=esptool_py +m5stack_coreink.bootloader.tool.default=esptool_py + +m5stack_coreink.upload.tool=esptool_py +m5stack_coreink.upload.tool.default=esptool_py +m5stack_coreink.upload.tool.network=esp_ota + +m5stack_coreink.upload.maximum_size=1310720 +m5stack_coreink.upload.maximum_data_size=327680 +m5stack_coreink.upload.flags= +m5stack_coreink.upload.extra_flags= + +m5stack_coreink.serial.disableDTR=true +m5stack_coreink.serial.disableRTS=true + +m5stack_coreink.build.tarch=xtensa +m5stack_coreink.build.bootloader_addr=0x1000 +m5stack_coreink.build.target=esp32 +m5stack_coreink.build.mcu=esp32 +m5stack_coreink.build.core=esp32 +m5stack_coreink.build.variant=m5stack_coreink +m5stack_coreink.build.board=M5STACK_COREINK + +m5stack_coreink.build.f_cpu=240000000L +m5stack_coreink.build.flash_size=4MB +m5stack_coreink.build.flash_freq=80m +m5stack_coreink.build.flash_mode=dio +m5stack_coreink.build.boot=dio +m5stack_coreink.build.partitions=default +m5stack_coreink.build.defines= +m5stack_coreink.build.loop_core= +m5stack_coreink.build.event_core= + +m5stack_coreink.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_coreink.menu.PartitionScheme.default.build.partitions=default +m5stack_coreink.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_coreink.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_coreink.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_coreink.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_coreink.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_coreink.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_coreink.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_coreink.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_coreink.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_coreink.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_coreink.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_coreink.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_coreink.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_coreink.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_coreink.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_coreink.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_coreink.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_coreink.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_coreink.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_coreink.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_coreink.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_coreink.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_coreink.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_coreink.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_coreink.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_coreink.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_coreink.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_coreink.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_coreink.menu.PartitionScheme.custom=Custom +m5stack_coreink.menu.PartitionScheme.custom.build.partitions= +m5stack_coreink.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +m5stack_coreink.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_coreink.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_coreink.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_coreink.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_coreink.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_coreink.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_coreink.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_coreink.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_coreink.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_coreink.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_coreink.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_coreink.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_coreink.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_coreink.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_coreink.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_coreink.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_coreink.menu.FlashMode.qio=QIO +m5stack_coreink.menu.FlashMode.qio.build.flash_mode=dio +m5stack_coreink.menu.FlashMode.qio.build.boot=qio +m5stack_coreink.menu.FlashMode.dio=DIO +m5stack_coreink.menu.FlashMode.dio.build.flash_mode=dio +m5stack_coreink.menu.FlashMode.dio.build.boot=dio +m5stack_coreink.menu.FlashMode.qout=QOUT +m5stack_coreink.menu.FlashMode.qout.build.flash_mode=dout +m5stack_coreink.menu.FlashMode.qout.build.boot=qout +m5stack_coreink.menu.FlashMode.dout=DOUT +m5stack_coreink.menu.FlashMode.dout.build.flash_mode=dout +m5stack_coreink.menu.FlashMode.dout.build.boot=dout + +m5stack_coreink.menu.FlashFreq.80=80MHz +m5stack_coreink.menu.FlashFreq.80.build.flash_freq=80m +m5stack_coreink.menu.FlashFreq.40=40MHz +m5stack_coreink.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_coreink.menu.FlashSize.4M=4MB (32Mb) +m5stack_coreink.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_coreink.menu.UploadSpeed.1500000=1500000 +m5stack_coreink.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_coreink.menu.UploadSpeed.750000=750000 +m5stack_coreink.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_coreink.menu.UploadSpeed.500000=500000 +m5stack_coreink.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_coreink.menu.UploadSpeed.250000=250000 +m5stack_coreink.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_coreink.menu.UploadSpeed.115200=115200 +m5stack_coreink.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_coreink.menu.LoopCore.1=Core 1 +m5stack_coreink.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_coreink.menu.LoopCore.0=Core 0 +m5stack_coreink.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_coreink.menu.EventsCore.1=Core 1 +m5stack_coreink.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_coreink.menu.EventsCore.0=Core 0 +m5stack_coreink.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_coreink.menu.DebugLevel.none=None +m5stack_coreink.menu.DebugLevel.none.build.code_debug=0 +m5stack_coreink.menu.DebugLevel.error=Error +m5stack_coreink.menu.DebugLevel.error.build.code_debug=1 +m5stack_coreink.menu.DebugLevel.warn=Warn +m5stack_coreink.menu.DebugLevel.warn.build.code_debug=2 +m5stack_coreink.menu.DebugLevel.info=Info +m5stack_coreink.menu.DebugLevel.info.build.code_debug=3 +m5stack_coreink.menu.DebugLevel.debug=Debug +m5stack_coreink.menu.DebugLevel.debug.build.code_debug=4 +m5stack_coreink.menu.DebugLevel.verbose=Verbose +m5stack_coreink.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_coreink.menu.EraseFlash.none=Disabled +m5stack_coreink.menu.EraseFlash.none.upload.erase_cmd= +m5stack_coreink.menu.EraseFlash.all=Enabled +m5stack_coreink.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################### + +m5stack_stamp_pico.name=M5StampPico + +m5stack_stamp_pico.bootloader.tool=esptool_py +m5stack_stamp_pico.bootloader.tool.default=esptool_py + +m5stack_stamp_pico.upload.tool=esptool_py +m5stack_stamp_pico.upload.tool.default=esptool_py +m5stack_stamp_pico.upload.tool.network=esp_ota + +m5stack_stamp_pico.upload.maximum_size=1310720 +m5stack_stamp_pico.upload.maximum_data_size=327680 +m5stack_stamp_pico.upload.flags= +m5stack_stamp_pico.upload.extra_flags= + +m5stack_stamp_pico.serial.disableDTR=true +m5stack_stamp_pico.serial.disableRTS=true + +m5stack_stamp_pico.build.tarch=xtensa +m5stack_stamp_pico.build.bootloader_addr=0x1000 +m5stack_stamp_pico.build.target=esp32 +m5stack_stamp_pico.build.mcu=esp32 +m5stack_stamp_pico.build.core=esp32 +m5stack_stamp_pico.build.variant=m5stack_stamp_pico +m5stack_stamp_pico.build.board=M5STACK_STAMP_PICO + +m5stack_stamp_pico.build.f_cpu=240000000L +m5stack_stamp_pico.build.flash_size=4MB +m5stack_stamp_pico.build.flash_freq=80m +m5stack_stamp_pico.build.flash_mode=dio +m5stack_stamp_pico.build.boot=dio +m5stack_stamp_pico.build.partitions=default +m5stack_stamp_pico.build.defines= +m5stack_stamp_pico.build.loop_core= +m5stack_stamp_pico.build.event_core= + +m5stack_stamp_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.default.build.partitions=default +m5stack_stamp_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stamp_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stamp_pico.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stamp_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stamp_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stamp_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stamp_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stamp_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stamp_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stamp_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stamp_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stamp_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stamp_pico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stamp_pico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stamp_pico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_stamp_pico.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_stamp_pico.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_stamp_pico.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_stamp_pico.menu.PartitionScheme.custom=Custom +m5stack_stamp_pico.menu.PartitionScheme.custom.build.partitions= +m5stack_stamp_pico.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +m5stack_stamp_pico.menu.CPUFreq.240=240MHz (WiFi/BT) +m5stack_stamp_pico.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_stamp_pico.menu.CPUFreq.160=160MHz (WiFi/BT) +m5stack_stamp_pico.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stamp_pico.menu.CPUFreq.80=80MHz (WiFi/BT) +m5stack_stamp_pico.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stamp_pico.menu.CPUFreq.40=40MHz (40MHz XTAL) +m5stack_stamp_pico.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stamp_pico.menu.CPUFreq.26=26MHz (26MHz XTAL) +m5stack_stamp_pico.menu.CPUFreq.26.build.f_cpu=26000000L +m5stack_stamp_pico.menu.CPUFreq.20=20MHz (40MHz XTAL) +m5stack_stamp_pico.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stamp_pico.menu.CPUFreq.13=13MHz (26MHz XTAL) +m5stack_stamp_pico.menu.CPUFreq.13.build.f_cpu=13000000L +m5stack_stamp_pico.menu.CPUFreq.10=10MHz (40MHz XTAL) +m5stack_stamp_pico.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stamp_pico.menu.FlashMode.qio=QIO +m5stack_stamp_pico.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stamp_pico.menu.FlashMode.qio.build.boot=qio +m5stack_stamp_pico.menu.FlashMode.dio=DIO +m5stack_stamp_pico.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stamp_pico.menu.FlashMode.dio.build.boot=dio +m5stack_stamp_pico.menu.FlashMode.qout=QOUT +m5stack_stamp_pico.menu.FlashMode.qout.build.flash_mode=dout +m5stack_stamp_pico.menu.FlashMode.qout.build.boot=qout +m5stack_stamp_pico.menu.FlashMode.dout=DOUT +m5stack_stamp_pico.menu.FlashMode.dout.build.flash_mode=dout +m5stack_stamp_pico.menu.FlashMode.dout.build.boot=dout + +m5stack_stamp_pico.menu.FlashFreq.80=80MHz +m5stack_stamp_pico.menu.FlashFreq.80.build.flash_freq=80m +m5stack_stamp_pico.menu.FlashFreq.40=40MHz +m5stack_stamp_pico.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_stamp_pico.menu.FlashSize.4M=4MB (32Mb) +m5stack_stamp_pico.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_stamp_pico.menu.UploadSpeed.1500000=1500000 +m5stack_stamp_pico.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_stamp_pico.menu.UploadSpeed.750000=750000 +m5stack_stamp_pico.menu.UploadSpeed.750000.upload.speed=750000 +m5stack_stamp_pico.menu.UploadSpeed.500000=500000 +m5stack_stamp_pico.menu.UploadSpeed.500000.upload.speed=500000 +m5stack_stamp_pico.menu.UploadSpeed.250000=250000 +m5stack_stamp_pico.menu.UploadSpeed.250000.upload.speed=250000 +m5stack_stamp_pico.menu.UploadSpeed.115200=115200 +m5stack_stamp_pico.menu.UploadSpeed.115200.upload.speed=115200 + +m5stack_stamp_pico.menu.LoopCore.1=Core 1 +m5stack_stamp_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_stamp_pico.menu.LoopCore.0=Core 0 +m5stack_stamp_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_stamp_pico.menu.EventsCore.1=Core 1 +m5stack_stamp_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_stamp_pico.menu.EventsCore.0=Core 0 +m5stack_stamp_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_stamp_pico.menu.DebugLevel.none=None +m5stack_stamp_pico.menu.DebugLevel.none.build.code_debug=0 +m5stack_stamp_pico.menu.DebugLevel.error=Error +m5stack_stamp_pico.menu.DebugLevel.error.build.code_debug=1 +m5stack_stamp_pico.menu.DebugLevel.warn=Warn +m5stack_stamp_pico.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stamp_pico.menu.DebugLevel.info=Info +m5stack_stamp_pico.menu.DebugLevel.info.build.code_debug=3 +m5stack_stamp_pico.menu.DebugLevel.debug=Debug +m5stack_stamp_pico.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stamp_pico.menu.DebugLevel.verbose=Verbose +m5stack_stamp_pico.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stamp_pico.menu.EraseFlash.none=Disabled +m5stack_stamp_pico.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stamp_pico.menu.EraseFlash.all=Enabled +m5stack_stamp_pico.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_stamp_c3.name=M5StampC3 + +m5stack_stamp_c3.bootloader.tool=esptool_py +m5stack_stamp_c3.bootloader.tool.default=esptool_py + +m5stack_stamp_c3.upload.tool=esptool_py +m5stack_stamp_c3.upload.tool.default=esptool_py +m5stack_stamp_c3.upload.tool.network=esp_ota + +m5stack_stamp_c3.upload.maximum_size=1310720 +m5stack_stamp_c3.upload.maximum_data_size=327680 +m5stack_stamp_c3.upload.wait_for_upload_port=false +m5stack_stamp_c3.upload.flags= +m5stack_stamp_c3.upload.extra_flags= + +m5stack_stamp_c3.serial.disableDTR=false +m5stack_stamp_c3.serial.disableRTS=false + +m5stack_stamp_c3.build.tarch=riscv32 +m5stack_stamp_c3.build.target=esp +m5stack_stamp_c3.build.mcu=esp32c3 +m5stack_stamp_c3.build.core=esp32 +m5stack_stamp_c3.build.variant=m5stack_stamp_c3 +m5stack_stamp_c3.build.board=M5STACK_STAMP_C3 +m5stack_stamp_c3.build.bootloader_addr=0x0 + +m5stack_stamp_c3.build.cdc_on_boot=1 +m5stack_stamp_c3.build.f_cpu=160000000L +m5stack_stamp_c3.build.flash_size=4MB +m5stack_stamp_c3.build.flash_freq=80m +m5stack_stamp_c3.build.flash_mode=qio +m5stack_stamp_c3.build.boot=qio +m5stack_stamp_c3.build.partitions=default +m5stack_stamp_c3.build.defines= + +## IDE 2.0 Seems to not update the value +m5stack_stamp_c3.menu.JTAGAdapter.default=Disabled +m5stack_stamp_c3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_stamp_c3.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_stamp_c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +m5stack_stamp_c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_stamp_c3.menu.JTAGAdapter.external=FTDI Adapter +m5stack_stamp_c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +m5stack_stamp_c3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_stamp_c3.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_stamp_c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +m5stack_stamp_c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_stamp_c3.menu.CDCOnBoot.cdc=Enabled +m5stack_stamp_c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_stamp_c3.menu.CDCOnBoot.default=Disabled +m5stack_stamp_c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_stamp_c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.default.build.partitions=default +m5stack_stamp_c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stamp_c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stamp_c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stamp_c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stamp_c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stamp_c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stamp_c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stamp_c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stamp_c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stamp_c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stamp_c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stamp_c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stamp_c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stamp_c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stamp_c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + + +m5stack_stamp_c3.menu.CPUFreq.160=160MHz (WiFi) +m5stack_stamp_c3.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stamp_c3.menu.CPUFreq.80=80MHz (WiFi) +m5stack_stamp_c3.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stamp_c3.menu.CPUFreq.40=40MHz +m5stack_stamp_c3.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stamp_c3.menu.CPUFreq.20=20MHz +m5stack_stamp_c3.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stamp_c3.menu.CPUFreq.10=10MHz +m5stack_stamp_c3.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stamp_c3.menu.FlashMode.qio=QIO +m5stack_stamp_c3.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stamp_c3.menu.FlashMode.qio.build.boot=qio +m5stack_stamp_c3.menu.FlashMode.dio=DIO +m5stack_stamp_c3.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stamp_c3.menu.FlashMode.dio.build.boot=dio +m5stack_stamp_c3.menu.FlashMode.qout=QOUT +m5stack_stamp_c3.menu.FlashMode.qout.build.flash_mode=dout +m5stack_stamp_c3.menu.FlashMode.qout.build.boot=qout +m5stack_stamp_c3.menu.FlashMode.dout=DOUT +m5stack_stamp_c3.menu.FlashMode.dout.build.flash_mode=dout +m5stack_stamp_c3.menu.FlashMode.dout.build.boot=dout + +m5stack_stamp_c3.menu.FlashFreq.80=80MHz +m5stack_stamp_c3.menu.FlashFreq.80.build.flash_freq=80m +m5stack_stamp_c3.menu.FlashFreq.40=40MHz +m5stack_stamp_c3.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_stamp_c3.menu.FlashSize.4M=4MB (32Mb) +m5stack_stamp_c3.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_stamp_c3.menu.UploadSpeed.921600=921600 +m5stack_stamp_c3.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_stamp_c3.menu.UploadSpeed.115200=115200 +m5stack_stamp_c3.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_stamp_c3.menu.UploadSpeed.256000.windows=256000 +m5stack_stamp_c3.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_stamp_c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_stamp_c3.menu.UploadSpeed.230400=230400 +m5stack_stamp_c3.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_stamp_c3.menu.UploadSpeed.460800.linux=460800 +m5stack_stamp_c3.menu.UploadSpeed.460800.macosx=460800 +m5stack_stamp_c3.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_stamp_c3.menu.UploadSpeed.512000.windows=512000 +m5stack_stamp_c3.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_stamp_c3.menu.DebugLevel.none=None +m5stack_stamp_c3.menu.DebugLevel.none.build.code_debug=0 +m5stack_stamp_c3.menu.DebugLevel.error=Error +m5stack_stamp_c3.menu.DebugLevel.error.build.code_debug=1 +m5stack_stamp_c3.menu.DebugLevel.warn=Warn +m5stack_stamp_c3.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stamp_c3.menu.DebugLevel.info=Info +m5stack_stamp_c3.menu.DebugLevel.info.build.code_debug=3 +m5stack_stamp_c3.menu.DebugLevel.debug=Debug +m5stack_stamp_c3.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stamp_c3.menu.DebugLevel.verbose=Verbose +m5stack_stamp_c3.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stamp_c3.menu.EraseFlash.none=Disabled +m5stack_stamp_c3.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stamp_c3.menu.EraseFlash.all=Enabled +m5stack_stamp_c3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################### + +m5stack_stamp_s3.name=M5StampS3 +m5stack_stamp_s3.bootloader.tool=esptool_py +m5stack_stamp_s3.bootloader.tool.default=esptool_py + +m5stack_stamp_s3.upload.tool=esptool_py +m5stack_stamp_s3.upload.tool.default=esptool_py +m5stack_stamp_s3.upload.tool.network=esp_ota + +m5stack_stamp_s3.upload.maximum_size=1310720 +m5stack_stamp_s3.upload.maximum_data_size=327680 +m5stack_stamp_s3.upload.flags= +m5stack_stamp_s3.upload.extra_flags= +m5stack_stamp_s3.upload.use_1200bps_touch=false +m5stack_stamp_s3.upload.wait_for_upload_port=false + +m5stack_stamp_s3.serial.disableDTR=false +m5stack_stamp_s3.serial.disableRTS=false + +m5stack_stamp_s3.build.tarch=xtensa +m5stack_stamp_s3.build.bootloader_addr=0x0 +m5stack_stamp_s3.build.target=esp32s3 +m5stack_stamp_s3.build.mcu=esp32s3 +m5stack_stamp_s3.build.core=esp32 +m5stack_stamp_s3.build.variant=m5stack_stamp_s3 +m5stack_stamp_s3.build.board=M5STACK_STAMP_S3 + +m5stack_stamp_s3.build.usb_mode=1 +m5stack_stamp_s3.build.cdc_on_boot=1 +m5stack_stamp_s3.build.msc_on_boot=0 +m5stack_stamp_s3.build.dfu_on_boot=0 +m5stack_stamp_s3.build.f_cpu=240000000L +m5stack_stamp_s3.build.flash_size=8MB +m5stack_stamp_s3.build.flash_freq=80m +m5stack_stamp_s3.build.flash_mode=dio +m5stack_stamp_s3.build.boot=qio +m5stack_stamp_s3.build.boot_freq=80m +m5stack_stamp_s3.build.partitions=default_8MB +m5stack_stamp_s3.build.defines= +m5stack_stamp_s3.build.loop_core= +m5stack_stamp_s3.build.event_core= +m5stack_stamp_s3.build.psram_type=qspi +m5stack_stamp_s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_stamp_s3.menu.JTAGAdapter.default=Disabled +m5stack_stamp_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_stamp_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_stamp_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_stamp_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_stamp_s3.menu.JTAGAdapter.external=FTDI Adapter +m5stack_stamp_s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_stamp_s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_stamp_s3.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_stamp_s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_stamp_s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_stamp_s3.menu.PSRAM.disabled=Disabled +m5stack_stamp_s3.menu.PSRAM.disabled.build.defines= +m5stack_stamp_s3.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_stamp_s3.menu.PSRAM.enabled=QSPI PSRAM +m5stack_stamp_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_stamp_s3.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_stamp_s3.menu.PSRAM.opi=OPI PSRAM +m5stack_stamp_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_stamp_s3.menu.PSRAM.opi.build.psram_type=opi + +m5stack_stamp_s3.menu.FlashMode.qio=QIO 80MHz +m5stack_stamp_s3.menu.FlashMode.qio.build.flash_mode=dio +m5stack_stamp_s3.menu.FlashMode.qio.build.boot=qio +m5stack_stamp_s3.menu.FlashMode.qio.build.boot_freq=80m +m5stack_stamp_s3.menu.FlashMode.qio.build.flash_freq=80m +m5stack_stamp_s3.menu.FlashMode.qio120=QIO 120MHz +m5stack_stamp_s3.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_stamp_s3.menu.FlashMode.qio120.build.boot=qio +m5stack_stamp_s3.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_stamp_s3.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_stamp_s3.menu.FlashMode.dio=DIO 80MHz +m5stack_stamp_s3.menu.FlashMode.dio.build.flash_mode=dio +m5stack_stamp_s3.menu.FlashMode.dio.build.boot=dio +m5stack_stamp_s3.menu.FlashMode.dio.build.boot_freq=80m +m5stack_stamp_s3.menu.FlashMode.dio.build.flash_freq=80m +m5stack_stamp_s3.menu.FlashMode.opi=OPI 80MHz +m5stack_stamp_s3.menu.FlashMode.opi.build.flash_mode=dout +m5stack_stamp_s3.menu.FlashMode.opi.build.boot=opi +m5stack_stamp_s3.menu.FlashMode.opi.build.boot_freq=80m +m5stack_stamp_s3.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_stamp_s3.menu.FlashSize.4M=4MB (32Mb) +m5stack_stamp_s3.menu.FlashSize.4M.build.flash_size=4MB +m5stack_stamp_s3.menu.FlashSize.8M=8MB (64Mb) +m5stack_stamp_s3.menu.FlashSize.8M.build.flash_size=8MB +m5stack_stamp_s3.menu.FlashSize.16M=16MB (128Mb) +m5stack_stamp_s3.menu.FlashSize.16M.build.flash_size=16MB +m5stack_stamp_s3.menu.FlashSize.32M=32MB (256Mb) +m5stack_stamp_s3.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_stamp_s3.menu.LoopCore.1=Core 1 +m5stack_stamp_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_stamp_s3.menu.LoopCore.0=Core 0 +m5stack_stamp_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_stamp_s3.menu.EventsCore.1=Core 1 +m5stack_stamp_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_stamp_s3.menu.EventsCore.0=Core 0 +m5stack_stamp_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_stamp_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_stamp_s3.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_stamp_s3.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_stamp_s3.menu.USBMode.default.build.usb_mode=0 + +m5stack_stamp_s3.menu.CDCOnBoot.cdc=Enabled +m5stack_stamp_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_stamp_s3.menu.CDCOnBoot.default=Disabled +m5stack_stamp_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_stamp_s3.menu.MSCOnBoot.default=Disabled +m5stack_stamp_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_stamp_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_stamp_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_stamp_s3.menu.DFUOnBoot.default=Disabled +m5stack_stamp_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_stamp_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_stamp_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_stamp_s3.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_stamp_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_stamp_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_stamp_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_stamp_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_stamp_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_stamp_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.default.build.partitions=default +m5stack_stamp_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_stamp_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_stamp_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_stamp_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_stamp_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_stamp_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_stamp_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_stamp_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_stamp_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_stamp_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_stamp_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_stamp_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_stamp_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_stamp_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_stamp_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_stamp_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_stamp_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_stamp_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_stamp_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_stamp_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_stamp_s3.menu.PartitionScheme.custom=Custom +m5stack_stamp_s3.menu.PartitionScheme.custom.build.partitions= +m5stack_stamp_s3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_stamp_s3.menu.CPUFreq.240=240MHz (WiFi) +m5stack_stamp_s3.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_stamp_s3.menu.CPUFreq.160=160MHz (WiFi) +m5stack_stamp_s3.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_stamp_s3.menu.CPUFreq.80=80MHz (WiFi) +m5stack_stamp_s3.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_stamp_s3.menu.CPUFreq.40=40MHz +m5stack_stamp_s3.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_stamp_s3.menu.CPUFreq.20=20MHz +m5stack_stamp_s3.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_stamp_s3.menu.CPUFreq.10=10MHz +m5stack_stamp_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_stamp_s3.menu.UploadSpeed.921600=921600 +m5stack_stamp_s3.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_stamp_s3.menu.UploadSpeed.115200=115200 +m5stack_stamp_s3.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_stamp_s3.menu.UploadSpeed.256000.windows=256000 +m5stack_stamp_s3.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_stamp_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_stamp_s3.menu.UploadSpeed.230400=230400 +m5stack_stamp_s3.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_stamp_s3.menu.UploadSpeed.460800.linux=460800 +m5stack_stamp_s3.menu.UploadSpeed.460800.macosx=460800 +m5stack_stamp_s3.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_stamp_s3.menu.UploadSpeed.512000.windows=512000 +m5stack_stamp_s3.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_stamp_s3.menu.DebugLevel.none=None +m5stack_stamp_s3.menu.DebugLevel.none.build.code_debug=0 +m5stack_stamp_s3.menu.DebugLevel.error=Error +m5stack_stamp_s3.menu.DebugLevel.error.build.code_debug=1 +m5stack_stamp_s3.menu.DebugLevel.warn=Warn +m5stack_stamp_s3.menu.DebugLevel.warn.build.code_debug=2 +m5stack_stamp_s3.menu.DebugLevel.info=Info +m5stack_stamp_s3.menu.DebugLevel.info.build.code_debug=3 +m5stack_stamp_s3.menu.DebugLevel.debug=Debug +m5stack_stamp_s3.menu.DebugLevel.debug.build.code_debug=4 +m5stack_stamp_s3.menu.DebugLevel.verbose=Verbose +m5stack_stamp_s3.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_stamp_s3.menu.EraseFlash.none=Disabled +m5stack_stamp_s3.menu.EraseFlash.none.upload.erase_cmd= +m5stack_stamp_s3.menu.EraseFlash.all=Enabled +m5stack_stamp_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_capsule.name=M5Capsule +m5stack_capsule.bootloader.tool=esptool_py +m5stack_capsule.bootloader.tool.default=esptool_py + +m5stack_capsule.upload.tool=esptool_py +m5stack_capsule.upload.tool.default=esptool_py +m5stack_capsule.upload.tool.network=esp_ota + +m5stack_capsule.upload.maximum_size=1310720 +m5stack_capsule.upload.maximum_data_size=327680 +m5stack_capsule.upload.flags= +m5stack_capsule.upload.extra_flags= +m5stack_capsule.upload.use_1200bps_touch=false +m5stack_capsule.upload.wait_for_upload_port=false + +m5stack_capsule.serial.disableDTR=false +m5stack_capsule.serial.disableRTS=false + +m5stack_capsule.build.tarch=xtensa +m5stack_capsule.build.bootloader_addr=0x0 +m5stack_capsule.build.target=esp32s3 +m5stack_capsule.build.mcu=esp32s3 +m5stack_capsule.build.core=esp32 +m5stack_capsule.build.variant=m5stack_capsule +m5stack_capsule.build.board=M5STACK_CAPSULE + +m5stack_capsule.build.usb_mode=1 +m5stack_capsule.build.cdc_on_boot=1 +m5stack_capsule.build.msc_on_boot=0 +m5stack_capsule.build.dfu_on_boot=0 +m5stack_capsule.build.f_cpu=240000000L +m5stack_capsule.build.flash_size=8MB +m5stack_capsule.build.flash_freq=80m +m5stack_capsule.build.flash_mode=dio +m5stack_capsule.build.boot=qio +m5stack_capsule.build.boot_freq=80m +m5stack_capsule.build.partitions=default +m5stack_capsule.build.defines= +m5stack_capsule.build.loop_core= +m5stack_capsule.build.event_core= +m5stack_capsule.build.psram_type=qspi +m5stack_capsule.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_capsule.menu.JTAGAdapter.default=Disabled +m5stack_capsule.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_capsule.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_capsule.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_capsule.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_capsule.menu.JTAGAdapter.external=FTDI Adapter +m5stack_capsule.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_capsule.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_capsule.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_capsule.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_capsule.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_capsule.menu.PSRAM.disabled=Disabled +m5stack_capsule.menu.PSRAM.disabled.build.defines= +m5stack_capsule.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_capsule.menu.PSRAM.enabled=QSPI PSRAM +m5stack_capsule.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_capsule.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_capsule.menu.PSRAM.opi=OPI PSRAM +m5stack_capsule.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_capsule.menu.PSRAM.opi.build.psram_type=opi + +m5stack_capsule.menu.FlashMode.qio=QIO 80MHz +m5stack_capsule.menu.FlashMode.qio.build.flash_mode=dio +m5stack_capsule.menu.FlashMode.qio.build.boot=qio +m5stack_capsule.menu.FlashMode.qio.build.boot_freq=80m +m5stack_capsule.menu.FlashMode.qio.build.flash_freq=80m +m5stack_capsule.menu.FlashMode.qio120=QIO 120MHz +m5stack_capsule.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_capsule.menu.FlashMode.qio120.build.boot=qio +m5stack_capsule.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_capsule.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_capsule.menu.FlashMode.dio=DIO 80MHz +m5stack_capsule.menu.FlashMode.dio.build.flash_mode=dio +m5stack_capsule.menu.FlashMode.dio.build.boot=dio +m5stack_capsule.menu.FlashMode.dio.build.boot_freq=80m +m5stack_capsule.menu.FlashMode.dio.build.flash_freq=80m +m5stack_capsule.menu.FlashMode.opi=OPI 80MHz +m5stack_capsule.menu.FlashMode.opi.build.flash_mode=dout +m5stack_capsule.menu.FlashMode.opi.build.boot=opi +m5stack_capsule.menu.FlashMode.opi.build.boot_freq=80m +m5stack_capsule.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_capsule.menu.FlashSize.4M=4MB (32Mb) +m5stack_capsule.menu.FlashSize.4M.build.flash_size=4MB +m5stack_capsule.menu.FlashSize.8M=8MB (64Mb) +m5stack_capsule.menu.FlashSize.8M.build.flash_size=8MB +m5stack_capsule.menu.FlashSize.16M=16MB (128Mb) +m5stack_capsule.menu.FlashSize.16M.build.flash_size=16MB +m5stack_capsule.menu.FlashSize.32M=32MB (256Mb) +m5stack_capsule.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_capsule.menu.LoopCore.1=Core 1 +m5stack_capsule.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_capsule.menu.LoopCore.0=Core 0 +m5stack_capsule.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_capsule.menu.EventsCore.1=Core 1 +m5stack_capsule.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_capsule.menu.EventsCore.0=Core 0 +m5stack_capsule.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_capsule.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_capsule.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_capsule.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_capsule.menu.USBMode.default.build.usb_mode=0 + +m5stack_capsule.menu.CDCOnBoot.cdc=Enabled +m5stack_capsule.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_capsule.menu.CDCOnBoot.default=Disabled +m5stack_capsule.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_capsule.menu.MSCOnBoot.default=Disabled +m5stack_capsule.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_capsule.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_capsule.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_capsule.menu.DFUOnBoot.default=Disabled +m5stack_capsule.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_capsule.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_capsule.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_capsule.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_capsule.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_capsule.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_capsule.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_capsule.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_capsule.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_capsule.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_capsule.menu.PartitionScheme.default.build.partitions=default +m5stack_capsule.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_capsule.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_capsule.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_capsule.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_capsule.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_capsule.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_capsule.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_capsule.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_capsule.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_capsule.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_capsule.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_capsule.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_capsule.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_capsule.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_capsule.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_capsule.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_capsule.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_capsule.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_capsule.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_capsule.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_capsule.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_capsule.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_capsule.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_capsule.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_capsule.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_capsule.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_capsule.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_capsule.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_capsule.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_capsule.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_capsule.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_capsule.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_capsule.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_capsule.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_capsule.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_capsule.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_capsule.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_capsule.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_capsule.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_capsule.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_capsule.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_capsule.menu.PartitionScheme.custom=Custom +m5stack_capsule.menu.PartitionScheme.custom.build.partitions= +m5stack_capsule.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_capsule.menu.CPUFreq.240=240MHz (WiFi) +m5stack_capsule.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_capsule.menu.CPUFreq.160=160MHz (WiFi) +m5stack_capsule.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_capsule.menu.CPUFreq.80=80MHz (WiFi) +m5stack_capsule.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_capsule.menu.CPUFreq.40=40MHz +m5stack_capsule.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_capsule.menu.CPUFreq.20=20MHz +m5stack_capsule.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_capsule.menu.CPUFreq.10=10MHz +m5stack_capsule.menu.CPUFreq.10.build.f_cpu=10000000L + + +m5stack_capsule.menu.UploadSpeed.1500000=1500000 +m5stack_capsule.menu.UploadSpeed.1500000.upload.speed=1500000 +m5stack_capsule.menu.UploadSpeed.921600=921600 +m5stack_capsule.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_capsule.menu.UploadSpeed.115200=115200 +m5stack_capsule.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_capsule.menu.UploadSpeed.256000.windows=256000 +m5stack_capsule.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_capsule.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_capsule.menu.UploadSpeed.230400=230400 +m5stack_capsule.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_capsule.menu.UploadSpeed.460800.linux=460800 +m5stack_capsule.menu.UploadSpeed.460800.macosx=460800 +m5stack_capsule.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_capsule.menu.UploadSpeed.512000.windows=512000 +m5stack_capsule.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_capsule.menu.DebugLevel.none=None +m5stack_capsule.menu.DebugLevel.none.build.code_debug=0 +m5stack_capsule.menu.DebugLevel.error=Error +m5stack_capsule.menu.DebugLevel.error.build.code_debug=1 +m5stack_capsule.menu.DebugLevel.warn=Warn +m5stack_capsule.menu.DebugLevel.warn.build.code_debug=2 +m5stack_capsule.menu.DebugLevel.info=Info +m5stack_capsule.menu.DebugLevel.info.build.code_debug=3 +m5stack_capsule.menu.DebugLevel.debug=Debug +m5stack_capsule.menu.DebugLevel.debug.build.code_debug=4 +m5stack_capsule.menu.DebugLevel.verbose=Verbose +m5stack_capsule.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_capsule.menu.EraseFlash.none=Disabled +m5stack_capsule.menu.EraseFlash.none.upload.erase_cmd= +m5stack_capsule.menu.EraseFlash.all=Enabled +m5stack_capsule.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_cardputer.name=M5Cardputer +m5stack_cardputer.bootloader.tool=esptool_py +m5stack_cardputer.bootloader.tool.default=esptool_py + +m5stack_cardputer.upload.tool=esptool_py +m5stack_cardputer.upload.tool.default=esptool_py +m5stack_cardputer.upload.tool.network=esp_ota + +m5stack_cardputer.upload.maximum_size=1310720 +m5stack_cardputer.upload.maximum_data_size=327680 +m5stack_cardputer.upload.flags= +m5stack_cardputer.upload.extra_flags= +m5stack_cardputer.upload.use_1200bps_touch=false +m5stack_cardputer.upload.wait_for_upload_port=false + +m5stack_cardputer.serial.disableDTR=false +m5stack_cardputer.serial.disableRTS=false + +m5stack_cardputer.build.tarch=xtensa +m5stack_cardputer.build.bootloader_addr=0x0 +m5stack_cardputer.build.target=esp32s3 +m5stack_cardputer.build.mcu=esp32s3 +m5stack_cardputer.build.core=esp32 +m5stack_cardputer.build.variant=m5stack_cardputer +m5stack_cardputer.build.board=M5STACK_CARDPUTER + +m5stack_cardputer.build.usb_mode=1 +m5stack_cardputer.build.cdc_on_boot=1 +m5stack_cardputer.build.msc_on_boot=0 +m5stack_cardputer.build.dfu_on_boot=0 +m5stack_cardputer.build.f_cpu=240000000L +m5stack_cardputer.build.flash_size=8MB +m5stack_cardputer.build.flash_freq=80m +m5stack_cardputer.build.flash_mode=dio +m5stack_cardputer.build.boot=qio +m5stack_cardputer.build.boot_freq=80m +m5stack_cardputer.build.partitions=default +m5stack_cardputer.build.defines= +m5stack_cardputer.build.loop_core= +m5stack_cardputer.build.event_core= +m5stack_cardputer.build.psram_type=qspi +m5stack_cardputer.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_cardputer.menu.JTAGAdapter.default=Disabled +m5stack_cardputer.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_cardputer.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_cardputer.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_cardputer.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_cardputer.menu.JTAGAdapter.external=FTDI Adapter +m5stack_cardputer.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_cardputer.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_cardputer.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_cardputer.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_cardputer.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_cardputer.menu.PSRAM.disabled=Disabled +m5stack_cardputer.menu.PSRAM.disabled.build.defines= +m5stack_cardputer.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_cardputer.menu.PSRAM.enabled=QSPI PSRAM +m5stack_cardputer.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_cardputer.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_cardputer.menu.PSRAM.opi=OPI PSRAM +m5stack_cardputer.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_cardputer.menu.PSRAM.opi.build.psram_type=opi + +m5stack_cardputer.menu.FlashMode.qio=QIO 80MHz +m5stack_cardputer.menu.FlashMode.qio.build.flash_mode=dio +m5stack_cardputer.menu.FlashMode.qio.build.boot=qio +m5stack_cardputer.menu.FlashMode.qio.build.boot_freq=80m +m5stack_cardputer.menu.FlashMode.qio.build.flash_freq=80m +m5stack_cardputer.menu.FlashMode.qio120=QIO 120MHz +m5stack_cardputer.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_cardputer.menu.FlashMode.qio120.build.boot=qio +m5stack_cardputer.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_cardputer.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_cardputer.menu.FlashMode.dio=DIO 80MHz +m5stack_cardputer.menu.FlashMode.dio.build.flash_mode=dio +m5stack_cardputer.menu.FlashMode.dio.build.boot=dio +m5stack_cardputer.menu.FlashMode.dio.build.boot_freq=80m +m5stack_cardputer.menu.FlashMode.dio.build.flash_freq=80m +m5stack_cardputer.menu.FlashMode.opi=OPI 80MHz +m5stack_cardputer.menu.FlashMode.opi.build.flash_mode=dout +m5stack_cardputer.menu.FlashMode.opi.build.boot=opi +m5stack_cardputer.menu.FlashMode.opi.build.boot_freq=80m +m5stack_cardputer.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_cardputer.menu.FlashSize.4M=4MB (32Mb) +m5stack_cardputer.menu.FlashSize.4M.build.flash_size=4MB +m5stack_cardputer.menu.FlashSize.8M=8MB (64Mb) +m5stack_cardputer.menu.FlashSize.8M.build.flash_size=8MB +m5stack_cardputer.menu.FlashSize.16M=16MB (128Mb) +m5stack_cardputer.menu.FlashSize.16M.build.flash_size=16MB +m5stack_cardputer.menu.FlashSize.32M=32MB (256Mb) +m5stack_cardputer.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_cardputer.menu.LoopCore.1=Core 1 +m5stack_cardputer.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_cardputer.menu.LoopCore.0=Core 0 +m5stack_cardputer.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_cardputer.menu.EventsCore.1=Core 1 +m5stack_cardputer.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_cardputer.menu.EventsCore.0=Core 0 +m5stack_cardputer.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_cardputer.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_cardputer.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_cardputer.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_cardputer.menu.USBMode.default.build.usb_mode=0 + +m5stack_cardputer.menu.CDCOnBoot.cdc=Enabled +m5stack_cardputer.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_cardputer.menu.CDCOnBoot.default=Disabled +m5stack_cardputer.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_cardputer.menu.MSCOnBoot.default=Disabled +m5stack_cardputer.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_cardputer.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_cardputer.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_cardputer.menu.DFUOnBoot.default=Disabled +m5stack_cardputer.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_cardputer.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_cardputer.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_cardputer.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_cardputer.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_cardputer.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_cardputer.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_cardputer.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_cardputer.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_cardputer.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.default.build.partitions=default +m5stack_cardputer.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_cardputer.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_cardputer.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_cardputer.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_cardputer.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_cardputer.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_cardputer.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_cardputer.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_cardputer.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_cardputer.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_cardputer.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_cardputer.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_cardputer.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_cardputer.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_cardputer.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_cardputer.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_cardputer.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_cardputer.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_cardputer.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_cardputer.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_cardputer.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_cardputer.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_cardputer.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_cardputer.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_cardputer.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_cardputer.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_cardputer.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_cardputer.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_cardputer.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_cardputer.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_cardputer.menu.PartitionScheme.custom=Custom +m5stack_cardputer.menu.PartitionScheme.custom.build.partitions= +m5stack_cardputer.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_cardputer.menu.CPUFreq.240=240MHz (WiFi) +m5stack_cardputer.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_cardputer.menu.CPUFreq.160=160MHz (WiFi) +m5stack_cardputer.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_cardputer.menu.CPUFreq.80=80MHz (WiFi) +m5stack_cardputer.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_cardputer.menu.CPUFreq.40=40MHz +m5stack_cardputer.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_cardputer.menu.CPUFreq.20=20MHz +m5stack_cardputer.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_cardputer.menu.CPUFreq.10=10MHz +m5stack_cardputer.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_cardputer.menu.UploadSpeed.921600=921600 +m5stack_cardputer.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_cardputer.menu.UploadSpeed.115200=115200 +m5stack_cardputer.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_cardputer.menu.UploadSpeed.256000.windows=256000 +m5stack_cardputer.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_cardputer.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_cardputer.menu.UploadSpeed.230400=230400 +m5stack_cardputer.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_cardputer.menu.UploadSpeed.460800.linux=460800 +m5stack_cardputer.menu.UploadSpeed.460800.macosx=460800 +m5stack_cardputer.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_cardputer.menu.UploadSpeed.512000.windows=512000 +m5stack_cardputer.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_cardputer.menu.DebugLevel.none=None +m5stack_cardputer.menu.DebugLevel.none.build.code_debug=0 +m5stack_cardputer.menu.DebugLevel.error=Error +m5stack_cardputer.menu.DebugLevel.error.build.code_debug=1 +m5stack_cardputer.menu.DebugLevel.warn=Warn +m5stack_cardputer.menu.DebugLevel.warn.build.code_debug=2 +m5stack_cardputer.menu.DebugLevel.info=Info +m5stack_cardputer.menu.DebugLevel.info.build.code_debug=3 +m5stack_cardputer.menu.DebugLevel.debug=Debug +m5stack_cardputer.menu.DebugLevel.debug.build.code_debug=4 +m5stack_cardputer.menu.DebugLevel.verbose=Verbose +m5stack_cardputer.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_cardputer.menu.EraseFlash.none=Disabled +m5stack_cardputer.menu.EraseFlash.none.upload.erase_cmd= +m5stack_cardputer.menu.EraseFlash.all=Enabled +m5stack_cardputer.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_dial.name=M5Dial +m5stack_dial.bootloader.tool=esptool_py +m5stack_dial.bootloader.tool.default=esptool_py + +m5stack_dial.upload.tool=esptool_py +m5stack_dial.upload.tool.default=esptool_py +m5stack_dial.upload.tool.network=esp_ota + +m5stack_dial.upload.maximum_size=1310720 +m5stack_dial.upload.maximum_data_size=327680 +m5stack_dial.upload.flags= +m5stack_dial.upload.extra_flags= +m5stack_dial.upload.use_1200bps_touch=false +m5stack_dial.upload.wait_for_upload_port=false + +m5stack_dial.serial.disableDTR=false +m5stack_dial.serial.disableRTS=false + +m5stack_dial.build.tarch=xtensa +m5stack_dial.build.bootloader_addr=0x0 +m5stack_dial.build.target=esp32s3 +m5stack_dial.build.mcu=esp32s3 +m5stack_dial.build.core=esp32 +m5stack_dial.build.variant=m5stack_dial +m5stack_dial.build.board=M5STACK_DIAL + +m5stack_dial.build.usb_mode=1 +m5stack_dial.build.cdc_on_boot=1 +m5stack_dial.build.msc_on_boot=0 +m5stack_dial.build.dfu_on_boot=0 +m5stack_dial.build.f_cpu=240000000L +m5stack_dial.build.flash_size=8MB +m5stack_dial.build.flash_freq=80m +m5stack_dial.build.flash_mode=dio +m5stack_dial.build.boot=qio +m5stack_dial.build.boot_freq=80m +m5stack_dial.build.partitions=default_8MB +m5stack_dial.build.defines= +m5stack_dial.build.loop_core= +m5stack_dial.build.event_core= +m5stack_dial.build.psram_type=qspi +m5stack_dial.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_dial.menu.JTAGAdapter.default=Disabled +m5stack_dial.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_dial.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_dial.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_dial.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_dial.menu.JTAGAdapter.external=FTDI Adapter +m5stack_dial.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_dial.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_dial.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_dial.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_dial.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_dial.menu.PSRAM.disabled=Disabled +m5stack_dial.menu.PSRAM.disabled.build.defines= +m5stack_dial.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_dial.menu.PSRAM.enabled=QSPI PSRAM +m5stack_dial.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_dial.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_dial.menu.PSRAM.opi=OPI PSRAM +m5stack_dial.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_dial.menu.PSRAM.opi.build.psram_type=opi + +m5stack_dial.menu.FlashMode.qio=QIO 80MHz +m5stack_dial.menu.FlashMode.qio.build.flash_mode=dio +m5stack_dial.menu.FlashMode.qio.build.boot=qio +m5stack_dial.menu.FlashMode.qio.build.boot_freq=80m +m5stack_dial.menu.FlashMode.qio.build.flash_freq=80m +m5stack_dial.menu.FlashMode.qio120=QIO 120MHz +m5stack_dial.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_dial.menu.FlashMode.qio120.build.boot=qio +m5stack_dial.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_dial.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_dial.menu.FlashMode.dio=DIO 80MHz +m5stack_dial.menu.FlashMode.dio.build.flash_mode=dio +m5stack_dial.menu.FlashMode.dio.build.boot=dio +m5stack_dial.menu.FlashMode.dio.build.boot_freq=80m +m5stack_dial.menu.FlashMode.dio.build.flash_freq=80m +m5stack_dial.menu.FlashMode.opi=OPI 80MHz +m5stack_dial.menu.FlashMode.opi.build.flash_mode=dout +m5stack_dial.menu.FlashMode.opi.build.boot=opi +m5stack_dial.menu.FlashMode.opi.build.boot_freq=80m +m5stack_dial.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_dial.menu.FlashSize.4M=4MB (32Mb) +m5stack_dial.menu.FlashSize.4M.build.flash_size=4MB +m5stack_dial.menu.FlashSize.8M=8MB (64Mb) +m5stack_dial.menu.FlashSize.8M.build.flash_size=8MB +m5stack_dial.menu.FlashSize.16M=16MB (128Mb) +m5stack_dial.menu.FlashSize.16M.build.flash_size=16MB +m5stack_dial.menu.FlashSize.32M=32MB (256Mb) +m5stack_dial.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_dial.menu.LoopCore.1=Core 1 +m5stack_dial.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_dial.menu.LoopCore.0=Core 0 +m5stack_dial.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_dial.menu.EventsCore.1=Core 1 +m5stack_dial.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_dial.menu.EventsCore.0=Core 0 +m5stack_dial.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_dial.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_dial.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_dial.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_dial.menu.USBMode.default.build.usb_mode=0 + +m5stack_dial.menu.CDCOnBoot.cdc=Enabled +m5stack_dial.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_dial.menu.CDCOnBoot.default=Disabled +m5stack_dial.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_dial.menu.MSCOnBoot.default=Disabled +m5stack_dial.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_dial.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_dial.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_dial.menu.DFUOnBoot.default=Disabled +m5stack_dial.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_dial.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_dial.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_dial.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_dial.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_dial.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_dial.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_dial.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_dial.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_dial.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_dial.menu.PartitionScheme.default.build.partitions=default +m5stack_dial.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_dial.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_dial.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_dial.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_dial.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_dial.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_dial.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_dial.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_dial.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_dial.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_dial.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_dial.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_dial.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_dial.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_dial.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_dial.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_dial.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_dial.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_dial.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_dial.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_dial.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_dial.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_dial.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_dial.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_dial.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_dial.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_dial.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_dial.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_dial.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_dial.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_dial.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_dial.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_dial.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_dial.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_dial.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_dial.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_dial.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_dial.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_dial.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_dial.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_dial.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_dial.menu.PartitionScheme.custom=Custom +m5stack_dial.menu.PartitionScheme.custom.build.partitions= +m5stack_dial.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_dial.menu.CPUFreq.240=240MHz (WiFi) +m5stack_dial.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_dial.menu.CPUFreq.160=160MHz (WiFi) +m5stack_dial.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_dial.menu.CPUFreq.80=80MHz (WiFi) +m5stack_dial.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_dial.menu.CPUFreq.40=40MHz +m5stack_dial.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_dial.menu.CPUFreq.20=20MHz +m5stack_dial.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_dial.menu.CPUFreq.10=10MHz +m5stack_dial.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_dial.menu.UploadSpeed.921600=921600 +m5stack_dial.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_dial.menu.UploadSpeed.115200=115200 +m5stack_dial.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_dial.menu.UploadSpeed.256000.windows=256000 +m5stack_dial.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_dial.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_dial.menu.UploadSpeed.230400=230400 +m5stack_dial.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_dial.menu.UploadSpeed.460800.linux=460800 +m5stack_dial.menu.UploadSpeed.460800.macosx=460800 +m5stack_dial.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_dial.menu.UploadSpeed.512000.windows=512000 +m5stack_dial.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_dial.menu.DebugLevel.none=None +m5stack_dial.menu.DebugLevel.none.build.code_debug=0 +m5stack_dial.menu.DebugLevel.error=Error +m5stack_dial.menu.DebugLevel.error.build.code_debug=1 +m5stack_dial.menu.DebugLevel.warn=Warn +m5stack_dial.menu.DebugLevel.warn.build.code_debug=2 +m5stack_dial.menu.DebugLevel.info=Info +m5stack_dial.menu.DebugLevel.info.build.code_debug=3 +m5stack_dial.menu.DebugLevel.debug=Debug +m5stack_dial.menu.DebugLevel.debug.build.code_debug=4 +m5stack_dial.menu.DebugLevel.verbose=Verbose +m5stack_dial.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_dial.menu.EraseFlash.none=Disabled +m5stack_dial.menu.EraseFlash.none.upload.erase_cmd= +m5stack_dial.menu.EraseFlash.all=Enabled +m5stack_dial.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_dinmeter.name=M5DinMeter +m5stack_dinmeter.bootloader.tool=esptool_py +m5stack_dinmeter.bootloader.tool.default=esptool_py + +m5stack_dinmeter.upload.tool=esptool_py +m5stack_dinmeter.upload.tool.default=esptool_py +m5stack_dinmeter.upload.tool.network=esp_ota + +m5stack_dinmeter.upload.maximum_size=1310720 +m5stack_dinmeter.upload.maximum_data_size=327680 +m5stack_dinmeter.upload.flags= +m5stack_dinmeter.upload.extra_flags= +m5stack_dinmeter.upload.use_1200bps_touch=false +m5stack_dinmeter.upload.wait_for_upload_port=false + +m5stack_dinmeter.serial.disableDTR=false +m5stack_dinmeter.serial.disableRTS=false + +m5stack_dinmeter.build.tarch=xtensa +m5stack_dinmeter.build.bootloader_addr=0x0 +m5stack_dinmeter.build.target=esp32s3 +m5stack_dinmeter.build.mcu=esp32s3 +m5stack_dinmeter.build.core=esp32 +m5stack_dinmeter.build.variant=m5stack_dinmeter +m5stack_dinmeter.build.board=M5STACK_DINMETER + +m5stack_dinmeter.build.usb_mode=1 +m5stack_dinmeter.build.cdc_on_boot=1 +m5stack_dinmeter.build.msc_on_boot=0 +m5stack_dinmeter.build.dfu_on_boot=0 +m5stack_dinmeter.build.f_cpu=240000000L +m5stack_dinmeter.build.flash_size=8MB +m5stack_dinmeter.build.flash_freq=80m +m5stack_dinmeter.build.flash_mode=dio +m5stack_dinmeter.build.boot=qio +m5stack_dinmeter.build.boot_freq=80m +m5stack_dinmeter.build.partitions=default +m5stack_dinmeter.build.defines= +m5stack_dinmeter.build.loop_core= +m5stack_dinmeter.build.event_core= +m5stack_dinmeter.build.psram_type=qspi +m5stack_dinmeter.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +m5stack_dinmeter.menu.JTAGAdapter.default=Disabled +m5stack_dinmeter.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_dinmeter.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_dinmeter.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +m5stack_dinmeter.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_dinmeter.menu.JTAGAdapter.external=FTDI Adapter +m5stack_dinmeter.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +m5stack_dinmeter.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_dinmeter.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_dinmeter.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +m5stack_dinmeter.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_dinmeter.menu.PSRAM.disabled=Disabled +m5stack_dinmeter.menu.PSRAM.disabled.build.defines= +m5stack_dinmeter.menu.PSRAM.disabled.build.psram_type=qspi +m5stack_dinmeter.menu.PSRAM.enabled=QSPI PSRAM +m5stack_dinmeter.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +m5stack_dinmeter.menu.PSRAM.enabled.build.psram_type=qspi +m5stack_dinmeter.menu.PSRAM.opi=OPI PSRAM +m5stack_dinmeter.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +m5stack_dinmeter.menu.PSRAM.opi.build.psram_type=opi + +m5stack_dinmeter.menu.FlashMode.qio=QIO 80MHz +m5stack_dinmeter.menu.FlashMode.qio.build.flash_mode=dio +m5stack_dinmeter.menu.FlashMode.qio.build.boot=qio +m5stack_dinmeter.menu.FlashMode.qio.build.boot_freq=80m +m5stack_dinmeter.menu.FlashMode.qio.build.flash_freq=80m +m5stack_dinmeter.menu.FlashMode.qio120=QIO 120MHz +m5stack_dinmeter.menu.FlashMode.qio120.build.flash_mode=dio +m5stack_dinmeter.menu.FlashMode.qio120.build.boot=qio +m5stack_dinmeter.menu.FlashMode.qio120.build.boot_freq=120m +m5stack_dinmeter.menu.FlashMode.qio120.build.flash_freq=80m +m5stack_dinmeter.menu.FlashMode.dio=DIO 80MHz +m5stack_dinmeter.menu.FlashMode.dio.build.flash_mode=dio +m5stack_dinmeter.menu.FlashMode.dio.build.boot=dio +m5stack_dinmeter.menu.FlashMode.dio.build.boot_freq=80m +m5stack_dinmeter.menu.FlashMode.dio.build.flash_freq=80m +m5stack_dinmeter.menu.FlashMode.opi=OPI 80MHz +m5stack_dinmeter.menu.FlashMode.opi.build.flash_mode=dout +m5stack_dinmeter.menu.FlashMode.opi.build.boot=opi +m5stack_dinmeter.menu.FlashMode.opi.build.boot_freq=80m +m5stack_dinmeter.menu.FlashMode.opi.build.flash_freq=80m + +m5stack_dinmeter.menu.FlashSize.4M=4MB (32Mb) +m5stack_dinmeter.menu.FlashSize.4M.build.flash_size=4MB +m5stack_dinmeter.menu.FlashSize.8M=8MB (64Mb) +m5stack_dinmeter.menu.FlashSize.8M.build.flash_size=8MB +m5stack_dinmeter.menu.FlashSize.16M=16MB (128Mb) +m5stack_dinmeter.menu.FlashSize.16M.build.flash_size=16MB +m5stack_dinmeter.menu.FlashSize.32M=32MB (256Mb) +m5stack_dinmeter.menu.FlashSize.32M.build.flash_size=32MB + +m5stack_dinmeter.menu.LoopCore.1=Core 1 +m5stack_dinmeter.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +m5stack_dinmeter.menu.LoopCore.0=Core 0 +m5stack_dinmeter.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +m5stack_dinmeter.menu.EventsCore.1=Core 1 +m5stack_dinmeter.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +m5stack_dinmeter.menu.EventsCore.0=Core 0 +m5stack_dinmeter.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +m5stack_dinmeter.menu.USBMode.hwcdc=Hardware CDC and JTAG +m5stack_dinmeter.menu.USBMode.hwcdc.build.usb_mode=1 +m5stack_dinmeter.menu.USBMode.default=USB-OTG (TinyUSB) +m5stack_dinmeter.menu.USBMode.default.build.usb_mode=0 + +m5stack_dinmeter.menu.CDCOnBoot.cdc=Enabled +m5stack_dinmeter.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_dinmeter.menu.CDCOnBoot.default=Disabled +m5stack_dinmeter.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +m5stack_dinmeter.menu.MSCOnBoot.default=Disabled +m5stack_dinmeter.menu.MSCOnBoot.default.build.msc_on_boot=0 +m5stack_dinmeter.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +m5stack_dinmeter.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +m5stack_dinmeter.menu.DFUOnBoot.default=Disabled +m5stack_dinmeter.menu.DFUOnBoot.default.build.dfu_on_boot=0 +m5stack_dinmeter.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +m5stack_dinmeter.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +m5stack_dinmeter.menu.UploadMode.default=UART0 / Hardware CDC +m5stack_dinmeter.menu.UploadMode.default.upload.use_1200bps_touch=false +m5stack_dinmeter.menu.UploadMode.default.upload.wait_for_upload_port=false +m5stack_dinmeter.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +m5stack_dinmeter.menu.UploadMode.cdc.upload.use_1200bps_touch=true +m5stack_dinmeter.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +m5stack_dinmeter.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.default.build.partitions=default +m5stack_dinmeter.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_dinmeter.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +m5stack_dinmeter.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +m5stack_dinmeter.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.minimal.build.partitions=minimal +m5stack_dinmeter.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_dinmeter.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_dinmeter.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_dinmeter.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_dinmeter.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_dinmeter.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_dinmeter.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_dinmeter.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_dinmeter.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_dinmeter.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_dinmeter.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +m5stack_dinmeter.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +m5stack_dinmeter.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +m5stack_dinmeter.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.fatflash.build.partitions=ffat +m5stack_dinmeter.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +m5stack_dinmeter.menu.PartitionScheme.rainmaker=RainMaker 4MB +m5stack_dinmeter.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +m5stack_dinmeter.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +m5stack_dinmeter.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +m5stack_dinmeter.menu.PartitionScheme.custom=Custom +m5stack_dinmeter.menu.PartitionScheme.custom.build.partitions= +m5stack_dinmeter.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +m5stack_dinmeter.menu.CPUFreq.240=240MHz (WiFi) +m5stack_dinmeter.menu.CPUFreq.240.build.f_cpu=240000000L +m5stack_dinmeter.menu.CPUFreq.160=160MHz (WiFi) +m5stack_dinmeter.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_dinmeter.menu.CPUFreq.80=80MHz (WiFi) +m5stack_dinmeter.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_dinmeter.menu.CPUFreq.40=40MHz +m5stack_dinmeter.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_dinmeter.menu.CPUFreq.20=20MHz +m5stack_dinmeter.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_dinmeter.menu.CPUFreq.10=10MHz +m5stack_dinmeter.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_dinmeter.menu.UploadSpeed.921600=921600 +m5stack_dinmeter.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_dinmeter.menu.UploadSpeed.115200=115200 +m5stack_dinmeter.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_dinmeter.menu.UploadSpeed.256000.windows=256000 +m5stack_dinmeter.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_dinmeter.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_dinmeter.menu.UploadSpeed.230400=230400 +m5stack_dinmeter.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_dinmeter.menu.UploadSpeed.460800.linux=460800 +m5stack_dinmeter.menu.UploadSpeed.460800.macosx=460800 +m5stack_dinmeter.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_dinmeter.menu.UploadSpeed.512000.windows=512000 +m5stack_dinmeter.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_dinmeter.menu.DebugLevel.none=None +m5stack_dinmeter.menu.DebugLevel.none.build.code_debug=0 +m5stack_dinmeter.menu.DebugLevel.error=Error +m5stack_dinmeter.menu.DebugLevel.error.build.code_debug=1 +m5stack_dinmeter.menu.DebugLevel.warn=Warn +m5stack_dinmeter.menu.DebugLevel.warn.build.code_debug=2 +m5stack_dinmeter.menu.DebugLevel.info=Info +m5stack_dinmeter.menu.DebugLevel.info.build.code_debug=3 +m5stack_dinmeter.menu.DebugLevel.debug=Debug +m5stack_dinmeter.menu.DebugLevel.debug.build.code_debug=4 +m5stack_dinmeter.menu.DebugLevel.verbose=Verbose +m5stack_dinmeter.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_dinmeter.menu.EraseFlash.none=Disabled +m5stack_dinmeter.menu.EraseFlash.none.upload.erase_cmd= +m5stack_dinmeter.menu.EraseFlash.all=Enabled +m5stack_dinmeter.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +m5stack_nanoc6.name=M5NanoC6 + +m5stack_nanoc6.bootloader.tool=esptool_py +m5stack_nanoc6.bootloader.tool.default=esptool_py + +m5stack_nanoc6.upload.tool=esptool_py +m5stack_nanoc6.upload.tool.default=esptool_py +m5stack_nanoc6.upload.tool.network=esp_ota + +m5stack_nanoc6.upload.maximum_size=1310720 +m5stack_nanoc6.upload.maximum_data_size=327680 +m5stack_nanoc6.upload.flags= +m5stack_nanoc6.upload.extra_flags= +m5stack_nanoc6.upload.use_1200bps_touch=false +m5stack_nanoc6.upload.wait_for_upload_port=false + +m5stack_nanoc6.serial.disableDTR=false +m5stack_nanoc6.serial.disableRTS=false + +m5stack_nanoc6.build.tarch=riscv32 +m5stack_nanoc6.build.target=esp +m5stack_nanoc6.build.mcu=esp32c6 +m5stack_nanoc6.build.core=esp32 +m5stack_nanoc6.build.variant=m5stack_nanoc6 +m5stack_nanoc6.build.board=M5STACK_NANOC6 +m5stack_nanoc6.build.bootloader_addr=0x0 + +m5stack_nanoc6.build.cdc_on_boot=1 +m5stack_nanoc6.build.f_cpu=160000000L +m5stack_nanoc6.build.flash_size=4MB +m5stack_nanoc6.build.flash_freq=80m +m5stack_nanoc6.build.flash_mode=qio +m5stack_nanoc6.build.boot=qio +m5stack_nanoc6.build.partitions=default +m5stack_nanoc6.build.defines= + +## IDE 2.0 Seems to not update the value +m5stack_nanoc6.menu.JTAGAdapter.default=Disabled +m5stack_nanoc6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +m5stack_nanoc6.menu.JTAGAdapter.builtin=Integrated USB JTAG +m5stack_nanoc6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +m5stack_nanoc6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +m5stack_nanoc6.menu.JTAGAdapter.external=FTDI Adapter +m5stack_nanoc6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +m5stack_nanoc6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +m5stack_nanoc6.menu.JTAGAdapter.bridge=ESP USB Bridge +m5stack_nanoc6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +m5stack_nanoc6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +m5stack_nanoc6.menu.CDCOnBoot.cdc=Enabled +m5stack_nanoc6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +m5stack_nanoc6.menu.CDCOnBoot.default=Enabled +m5stack_nanoc6.menu.CDCOnBoot.default.build.cdc_on_boot=1 + +m5stack_nanoc6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +m5stack_nanoc6.menu.PartitionScheme.default.build.partitions=default +m5stack_nanoc6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +m5stack_nanoc6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +m5stack_nanoc6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +m5stack_nanoc6.menu.PartitionScheme.no_ota.build.partitions=no_ota +m5stack_nanoc6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +m5stack_nanoc6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +m5stack_nanoc6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +m5stack_nanoc6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +m5stack_nanoc6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +m5stack_nanoc6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +m5stack_nanoc6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +m5stack_nanoc6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +m5stack_nanoc6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +m5stack_nanoc6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +m5stack_nanoc6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +m5stack_nanoc6.menu.PartitionScheme.huge_app.build.partitions=huge_app +m5stack_nanoc6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +m5stack_nanoc6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +m5stack_nanoc6.menu.PartitionScheme.zigbee.build.partitions=zigbee +m5stack_nanoc6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +m5stack_nanoc6.menu.CPUFreq.160=160MHz (WiFi) +m5stack_nanoc6.menu.CPUFreq.160.build.f_cpu=160000000L +m5stack_nanoc6.menu.CPUFreq.80=80MHz (WiFi) +m5stack_nanoc6.menu.CPUFreq.80.build.f_cpu=80000000L +m5stack_nanoc6.menu.CPUFreq.40=40MHz +m5stack_nanoc6.menu.CPUFreq.40.build.f_cpu=40000000L +m5stack_nanoc6.menu.CPUFreq.20=20MHz +m5stack_nanoc6.menu.CPUFreq.20.build.f_cpu=20000000L +m5stack_nanoc6.menu.CPUFreq.10=10MHz +m5stack_nanoc6.menu.CPUFreq.10.build.f_cpu=10000000L + +m5stack_nanoc6.menu.FlashMode.qio=QIO +m5stack_nanoc6.menu.FlashMode.qio.build.flash_mode=dio +m5stack_nanoc6.menu.FlashMode.qio.build.boot=qio +m5stack_nanoc6.menu.FlashMode.dio=DIO +m5stack_nanoc6.menu.FlashMode.dio.build.flash_mode=dio +m5stack_nanoc6.menu.FlashMode.dio.build.boot=dio + +m5stack_nanoc6.menu.FlashFreq.80=80MHz +m5stack_nanoc6.menu.FlashFreq.80.build.flash_freq=80m +m5stack_nanoc6.menu.FlashFreq.40=40MHz +m5stack_nanoc6.menu.FlashFreq.40.build.flash_freq=40m + +m5stack_nanoc6.menu.FlashSize.4M=4MB (32Mb) +m5stack_nanoc6.menu.FlashSize.4M.build.flash_size=4MB + +m5stack_nanoc6.menu.UploadSpeed.921600=921600 +m5stack_nanoc6.menu.UploadSpeed.921600.upload.speed=921600 +m5stack_nanoc6.menu.UploadSpeed.115200=115200 +m5stack_nanoc6.menu.UploadSpeed.115200.upload.speed=115200 +m5stack_nanoc6.menu.UploadSpeed.256000.windows=256000 +m5stack_nanoc6.menu.UploadSpeed.256000.upload.speed=256000 +m5stack_nanoc6.menu.UploadSpeed.230400.windows.upload.speed=256000 +m5stack_nanoc6.menu.UploadSpeed.230400=230400 +m5stack_nanoc6.menu.UploadSpeed.230400.upload.speed=230400 +m5stack_nanoc6.menu.UploadSpeed.460800.linux=460800 +m5stack_nanoc6.menu.UploadSpeed.460800.macosx=460800 +m5stack_nanoc6.menu.UploadSpeed.460800.upload.speed=460800 +m5stack_nanoc6.menu.UploadSpeed.512000.windows=512000 +m5stack_nanoc6.menu.UploadSpeed.512000.upload.speed=512000 + +m5stack_nanoc6.menu.DebugLevel.none=None +m5stack_nanoc6.menu.DebugLevel.none.build.code_debug=0 +m5stack_nanoc6.menu.DebugLevel.error=Error +m5stack_nanoc6.menu.DebugLevel.error.build.code_debug=1 +m5stack_nanoc6.menu.DebugLevel.warn=Warn +m5stack_nanoc6.menu.DebugLevel.warn.build.code_debug=2 +m5stack_nanoc6.menu.DebugLevel.info=Info +m5stack_nanoc6.menu.DebugLevel.info.build.code_debug=3 +m5stack_nanoc6.menu.DebugLevel.debug=Debug +m5stack_nanoc6.menu.DebugLevel.debug.build.code_debug=4 +m5stack_nanoc6.menu.DebugLevel.verbose=Verbose +m5stack_nanoc6.menu.DebugLevel.verbose.build.code_debug=5 + +m5stack_nanoc6.menu.EraseFlash.none=Disabled +m5stack_nanoc6.menu.EraseFlash.none.upload.erase_cmd= +m5stack_nanoc6.menu.EraseFlash.all=Enabled +m5stack_nanoc6.menu.EraseFlash.all.upload.erase_cmd=-e + +m5stack_nanoc6.menu.ZigbeeMode.default=Disabled +m5stack_nanoc6.menu.ZigbeeMode.default.build.zigbee_mode= +m5stack_nanoc6.menu.ZigbeeMode.default.build.zigbee_libs= +m5stack_nanoc6.menu.ZigbeeMode.ed=Zigbee ED (end device) +m5stack_nanoc6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +m5stack_nanoc6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +m5stack_nanoc6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +m5stack_nanoc6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +m5stack_nanoc6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +odroid_esp32.name=ODROID ESP32 + +odroid_esp32.bootloader.tool=esptool_py +odroid_esp32.bootloader.tool.default=esptool_py + +odroid_esp32.upload.tool=esptool_py +odroid_esp32.upload.tool.default=esptool_py +odroid_esp32.upload.tool.network=esp_ota + +odroid_esp32.upload.maximum_size=1310720 +odroid_esp32.upload.maximum_data_size=327680 +odroid_esp32.upload.flags= +odroid_esp32.upload.extra_flags= + +odroid_esp32.serial.disableDTR=true +odroid_esp32.serial.disableRTS=true + +odroid_esp32.build.tarch=xtensa +odroid_esp32.build.bootloader_addr=0x1000 +odroid_esp32.build.target=esp32 +odroid_esp32.build.mcu=esp32 +odroid_esp32.build.core=esp32 +odroid_esp32.build.variant=odroid_esp32 +odroid_esp32.build.board=ODROID_ESP32 + +odroid_esp32.build.f_cpu=240000000L +odroid_esp32.build.flash_size=16MB +odroid_esp32.build.flash_mode=dio +odroid_esp32.build.boot=dio +odroid_esp32.build.partitions=default +odroid_esp32.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +odroid_esp32.build.extra_libs= + +odroid_esp32.menu.FlashMode.qio=QIO +odroid_esp32.menu.FlashMode.qio.build.flash_mode=dio +odroid_esp32.menu.FlashMode.qio.build.boot=qio +odroid_esp32.menu.FlashMode.dio=DIO +odroid_esp32.menu.FlashMode.dio.build.flash_mode=dio +odroid_esp32.menu.FlashMode.dio.build.boot=dio + +odroid_esp32.menu.FlashFreq.80=80MHz +odroid_esp32.menu.FlashFreq.80.build.flash_freq=80m +odroid_esp32.menu.FlashFreq.40=40MHz +odroid_esp32.menu.FlashFreq.40.build.flash_freq=40m + +odroid_esp32.menu.PartitionScheme.default=Default +odroid_esp32.menu.PartitionScheme.default.build.partitions=default +odroid_esp32.menu.PartitionScheme.no_ota=No OTA (Large APP) +odroid_esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +odroid_esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +odroid_esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +odroid_esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +odroid_esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +odroid_esp32.menu.UploadSpeed.921600=921600 +odroid_esp32.menu.UploadSpeed.921600.upload.speed=921600 +odroid_esp32.menu.UploadSpeed.115200=115200 +odroid_esp32.menu.UploadSpeed.115200.upload.speed=115200 +odroid_esp32.menu.UploadSpeed.256000.windows=256000 +odroid_esp32.menu.UploadSpeed.256000.upload.speed=256000 +odroid_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +odroid_esp32.menu.UploadSpeed.230400=230400 +odroid_esp32.menu.UploadSpeed.230400.upload.speed=230400 +odroid_esp32.menu.UploadSpeed.460800.linux=460800 +odroid_esp32.menu.UploadSpeed.460800.macosx=460800 +odroid_esp32.menu.UploadSpeed.460800.upload.speed=460800 +odroid_esp32.menu.UploadSpeed.512000.windows=512000 +odroid_esp32.menu.UploadSpeed.512000.upload.speed=512000 + +odroid_esp32.menu.DebugLevel.none=None +odroid_esp32.menu.DebugLevel.none.build.code_debug=0 +odroid_esp32.menu.DebugLevel.error=Error +odroid_esp32.menu.DebugLevel.error.build.code_debug=1 +odroid_esp32.menu.DebugLevel.warn=Warn +odroid_esp32.menu.DebugLevel.warn.build.code_debug=2 +odroid_esp32.menu.DebugLevel.info=Info +odroid_esp32.menu.DebugLevel.info.build.code_debug=3 +odroid_esp32.menu.DebugLevel.debug=Debug +odroid_esp32.menu.DebugLevel.debug.build.code_debug=4 +odroid_esp32.menu.DebugLevel.verbose=Verbose +odroid_esp32.menu.DebugLevel.verbose.build.code_debug=5 + +odroid_esp32.menu.EraseFlash.none=Disabled +odroid_esp32.menu.EraseFlash.none.upload.erase_cmd= +odroid_esp32.menu.EraseFlash.all=Enabled +odroid_esp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wifi_kit_32.name=Heltec WiFi Kit 32 + +heltec_wifi_kit_32.bootloader.tool=esptool_py +heltec_wifi_kit_32.bootloader.tool.default=esptool_py + +heltec_wifi_kit_32.upload.tool=esptool_py +heltec_wifi_kit_32.upload.tool.default=esptool_py +heltec_wifi_kit_32.upload.tool.network=esp_ota + +heltec_wifi_kit_32.upload.maximum_size=1310720 +heltec_wifi_kit_32.upload.maximum_data_size=327680 +heltec_wifi_kit_32.upload.flags= +heltec_wifi_kit_32.upload.extra_flags= + +heltec_wifi_kit_32.serial.disableDTR=true +heltec_wifi_kit_32.serial.disableRTS=true + +heltec_wifi_kit_32.build.tarch=xtensa +heltec_wifi_kit_32.build.bootloader_addr=0x1000 +heltec_wifi_kit_32.build.target=esp32 +heltec_wifi_kit_32.build.mcu=esp32 +heltec_wifi_kit_32.build.core=esp32 +heltec_wifi_kit_32.build.variant=heltec_wifi_kit_32 +heltec_wifi_kit_32.build.board=HELTEC_WIFI_KIT_32 + +heltec_wifi_kit_32.build.f_cpu=240000000L +heltec_wifi_kit_32.build.flash_size=4MB +heltec_wifi_kit_32.build.flash_freq=80m +heltec_wifi_kit_32.build.flash_mode=dio +heltec_wifi_kit_32.build.boot=dio +heltec_wifi_kit_32.build.partitions=default +heltec_wifi_kit_32.build.defines= +heltec_wifi_kit_32.build.band=LoRaWAN_NONE +heltec_wifi_kit_32.build.LoRaWanDebugLevel=0 + +heltec_wifi_kit_32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +heltec_wifi_kit_32.menu.PartitionScheme.default.build.partitions=default +heltec_wifi_kit_32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +heltec_wifi_kit_32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +heltec_wifi_kit_32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +heltec_wifi_kit_32.menu.PartitionScheme.no_ota.build.partitions=no_ota +heltec_wifi_kit_32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +heltec_wifi_kit_32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +heltec_wifi_kit_32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +heltec_wifi_kit_32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +heltec_wifi_kit_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +heltec_wifi_kit_32.menu.PartitionScheme.huge_app.build.partitions=huge_app +heltec_wifi_kit_32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +heltec_wifi_kit_32.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wifi_kit_32.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wifi_kit_32.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wifi_kit_32.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wifi_kit_32.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wifi_kit_32.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wifi_kit_32.menu.UploadSpeed.921600=921600 +heltec_wifi_kit_32.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wifi_kit_32.menu.UploadSpeed.115200=115200 +heltec_wifi_kit_32.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wifi_kit_32.menu.UploadSpeed.256000.windows=256000 +heltec_wifi_kit_32.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wifi_kit_32.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wifi_kit_32.menu.UploadSpeed.230400=230400 +heltec_wifi_kit_32.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wifi_kit_32.menu.UploadSpeed.460800.linux=460800 +heltec_wifi_kit_32.menu.UploadSpeed.460800.macosx=460800 +heltec_wifi_kit_32.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wifi_kit_32.menu.UploadSpeed.512000.windows=512000 +heltec_wifi_kit_32.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wifi_kit_32.menu.DebugLevel.none=None +heltec_wifi_kit_32.menu.DebugLevel.none.build.code_debug=0 +heltec_wifi_kit_32.menu.DebugLevel.error=Error +heltec_wifi_kit_32.menu.DebugLevel.error.build.code_debug=1 +heltec_wifi_kit_32.menu.DebugLevel.warn=Warn +heltec_wifi_kit_32.menu.DebugLevel.warn.build.code_debug=2 +heltec_wifi_kit_32.menu.DebugLevel.info=Info +heltec_wifi_kit_32.menu.DebugLevel.info.build.code_debug=3 +heltec_wifi_kit_32.menu.DebugLevel.debug=Debug +heltec_wifi_kit_32.menu.DebugLevel.debug.build.code_debug=4 +heltec_wifi_kit_32.menu.DebugLevel.verbose=Verbose +heltec_wifi_kit_32.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wifi_kit_32.menu.EraseFlash.none=Disabled +heltec_wifi_kit_32.menu.EraseFlash.none.upload.erase_cmd= +heltec_wifi_kit_32.menu.EraseFlash.all=Enabled +heltec_wifi_kit_32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wifi_kit_32_V3.name=Heltec WiFi Kit 32(V3) + +heltec_wifi_kit_32_V3.bootloader.tool=esptool_py +heltec_wifi_kit_32_V3.bootloader.tool.default=esptool_py + +heltec_wifi_kit_32_V3.upload.tool=esptool_py +heltec_wifi_kit_32_V3.upload.tool.default=esptool_py +heltec_wifi_kit_32_V3.upload.tool.network=esp_ota + +heltec_wifi_kit_32_V3.upload.maximum_size=3342336 +heltec_wifi_kit_32_V3.upload.maximum_data_size=327680 +heltec_wifi_kit_32_V3.upload.flags= +heltec_wifi_kit_32_V3.upload.extra_flags= +heltec_wifi_kit_32_V3.upload.use_1200bps_touch=false +heltec_wifi_kit_32_V3.upload.wait_for_upload_port=false + +heltec_wifi_kit_32_V3.serial.disableDTR=false +heltec_wifi_kit_32_V3.serial.disableRTS=false + +heltec_wifi_kit_32_V3.build.tarch=xtensa +heltec_wifi_kit_32_V3.build.bootloader_addr=0x0 +heltec_wifi_kit_32_V3.build.target=esp32s3 +heltec_wifi_kit_32_V3.build.mcu=esp32s3 +heltec_wifi_kit_32_V3.build.core=esp32 +heltec_wifi_kit_32_V3.build.variant=heltec_wifi_kit_32_V3 +heltec_wifi_kit_32_V3.build.board=HELTEC_WIFI_KIT_32_V3 + +heltec_wifi_kit_32_V3.build.usb_mode=1 +heltec_wifi_kit_32_V3.build.cdc_on_boot=0 +heltec_wifi_kit_32_V3.build.msc_on_boot=0 +heltec_wifi_kit_32_V3.build.dfu_on_boot=0 +heltec_wifi_kit_32_V3.build.f_cpu=240000000L +heltec_wifi_kit_32_V3.build.flash_size=8MB +heltec_wifi_kit_32_V3.build.flash_freq=80m +heltec_wifi_kit_32_V3.build.flash_mode=dio +heltec_wifi_kit_32_V3.build.boot=qio +heltec_wifi_kit_32_V3.build.boot_freq=80m +heltec_wifi_kit_32_V3.build.partitions=default_8MB +heltec_wifi_kit_32_V3.build.loop_core= +heltec_wifi_kit_32_V3.build.event_core= +heltec_wifi_kit_32_V3.build.psram_type=qspi +heltec_wifi_kit_32_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_wifi_kit_32_V3.menu.LoopCore.1=Core 1 +heltec_wifi_kit_32_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wifi_kit_32_V3.menu.LoopCore.0=Core 0 +heltec_wifi_kit_32_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wifi_kit_32_V3.menu.EventsCore.1=Core 1 +heltec_wifi_kit_32_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wifi_kit_32_V3.menu.EventsCore.0=Core 0 +heltec_wifi_kit_32_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wifi_kit_32_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_wifi_kit_32_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wifi_kit_32_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_wifi_kit_32_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wifi_kit_32_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_wifi_kit_32_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wifi_kit_32_V3.menu.CPUFreq.40=40MHz +heltec_wifi_kit_32_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wifi_kit_32_V3.menu.CPUFreq.20=20MHz +heltec_wifi_kit_32_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wifi_kit_32_V3.menu.CPUFreq.10=10MHz +heltec_wifi_kit_32_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wifi_kit_32_V3.menu.UploadSpeed.921600=921600 +heltec_wifi_kit_32_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wifi_kit_32_V3.menu.UploadSpeed.115200=115200 +heltec_wifi_kit_32_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wifi_kit_32_V3.menu.UploadSpeed.256000.windows=256000 +heltec_wifi_kit_32_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wifi_kit_32_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wifi_kit_32_V3.menu.UploadSpeed.230400=230400 +heltec_wifi_kit_32_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.linux=460800 +heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wifi_kit_32_V3.menu.UploadSpeed.512000.windows=512000 +heltec_wifi_kit_32_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wifi_kit_32_V3.menu.DebugLevel.none=None +heltec_wifi_kit_32_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_wifi_kit_32_V3.menu.DebugLevel.error=Error +heltec_wifi_kit_32_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_wifi_kit_32_V3.menu.DebugLevel.warn=Warn +heltec_wifi_kit_32_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_wifi_kit_32_V3.menu.DebugLevel.info=Info +heltec_wifi_kit_32_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_wifi_kit_32_V3.menu.DebugLevel.debug=Debug +heltec_wifi_kit_32_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_wifi_kit_32_V3.menu.DebugLevel.verbose=Verbose +heltec_wifi_kit_32_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wifi_kit_32_V3.menu.EraseFlash.none=Disabled +heltec_wifi_kit_32_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_wifi_kit_32_V3.menu.EraseFlash.all=Enabled +heltec_wifi_kit_32_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wifi_lora_32.name=Heltec WiFi LoRa 32 + +heltec_wifi_lora_32.bootloader.tool=esptool_py +heltec_wifi_lora_32.bootloader.tool.default=esptool_py + +heltec_wifi_lora_32.upload.tool=esptool_py +heltec_wifi_lora_32.upload.tool.default=esptool_py +heltec_wifi_lora_32.upload.tool.network=esp_ota + +heltec_wifi_lora_32.upload.maximum_size=1310720 +heltec_wifi_lora_32.upload.maximum_data_size=327680 +heltec_wifi_lora_32.upload.flags= +heltec_wifi_lora_32.upload.extra_flags= + +heltec_wifi_lora_32.serial.disableDTR=true +heltec_wifi_lora_32.serial.disableRTS=true + +heltec_wifi_lora_32.build.tarch=xtensa +heltec_wifi_lora_32.build.bootloader_addr=0x1000 +heltec_wifi_lora_32.build.target=esp32 +heltec_wifi_lora_32.build.mcu=esp32 +heltec_wifi_lora_32.build.core=esp32 +heltec_wifi_lora_32.build.variant=heltec_wifi_lora_32 +heltec_wifi_lora_32.build.board=HELTEC_WIFI_LORA_32 + +heltec_wifi_lora_32.build.f_cpu=240000000L +heltec_wifi_lora_32.build.flash_size=4MB +heltec_wifi_lora_32.build.flash_freq=80m +heltec_wifi_lora_32.build.flash_mode=dio +heltec_wifi_lora_32.build.boot=qio +heltec_wifi_lora_32.build.partitions=default +heltec_wifi_lora_32.build.psram= +heltec_wifi_lora_32.build.defines=-D{build.band} -DMCU_ESP32_D0 -DWIFI_LORA_32 -DHELTEC_BOARD=1 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} {build.psram} + +heltec_wifi_lora_32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +heltec_wifi_lora_32.menu.PartitionScheme.default.build.partitions=default +heltec_wifi_lora_32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +heltec_wifi_lora_32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +heltec_wifi_lora_32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +heltec_wifi_lora_32.menu.PartitionScheme.no_ota.build.partitions=no_ota +heltec_wifi_lora_32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +heltec_wifi_lora_32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +heltec_wifi_lora_32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +heltec_wifi_lora_32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +heltec_wifi_lora_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +heltec_wifi_lora_32.menu.PartitionScheme.huge_app.build.partitions=huge_app +heltec_wifi_lora_32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +heltec_wifi_lora_32.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wifi_lora_32.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wifi_lora_32.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wifi_lora_32.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wifi_lora_32.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wifi_lora_32.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wifi_lora_32.menu.UploadSpeed.921600=921600 +heltec_wifi_lora_32.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wifi_lora_32.menu.UploadSpeed.115200=115200 +heltec_wifi_lora_32.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wifi_lora_32.menu.UploadSpeed.256000.windows=256000 +heltec_wifi_lora_32.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wifi_lora_32.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wifi_lora_32.menu.UploadSpeed.230400=230400 +heltec_wifi_lora_32.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wifi_lora_32.menu.UploadSpeed.460800.linux=460800 +heltec_wifi_lora_32.menu.UploadSpeed.460800.macosx=460800 +heltec_wifi_lora_32.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wifi_lora_32.menu.UploadSpeed.512000.windows=512000 +heltec_wifi_lora_32.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wifi_lora_32.menu.DebugLevel.none=None +heltec_wifi_lora_32.menu.DebugLevel.none.build.code_debug=0 +heltec_wifi_lora_32.menu.DebugLevel.error=Error +heltec_wifi_lora_32.menu.DebugLevel.error.build.code_debug=1 +heltec_wifi_lora_32.menu.DebugLevel.warn=Warn +heltec_wifi_lora_32.menu.DebugLevel.warn.build.code_debug=2 +heltec_wifi_lora_32.menu.DebugLevel.info=Info +heltec_wifi_lora_32.menu.DebugLevel.info.build.code_debug=3 +heltec_wifi_lora_32.menu.DebugLevel.debug=Debug +heltec_wifi_lora_32.menu.DebugLevel.debug.build.code_debug=4 +heltec_wifi_lora_32.menu.DebugLevel.verbose=Verbose +heltec_wifi_lora_32.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wifi_lora_32.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wifi_lora_32.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wifi_lora_32.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wifi_lora_32.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wifi_lora_32.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wifi_lora_32.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wifi_lora_32.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wifi_lora_32.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wifi_lora_32.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wifi_lora_32.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wifi_lora_32.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wifi_lora_32.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wifi_lora_32.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wifi_lora_32.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wifi_lora_32.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wifi_lora_32.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wifi_lora_32.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wifi_lora_32.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wifi_lora_32.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wifi_lora_32.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.0=None +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.1=Freq +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wifi_lora_32.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + + +heltec_wifi_lora_32.menu.EraseFlash.none=Disabled +heltec_wifi_lora_32.menu.EraseFlash.none.upload.erase_cmd= +heltec_wifi_lora_32.menu.EraseFlash.all=Enabled +heltec_wifi_lora_32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wifi_lora_32_V2.name=Heltec WiFi LoRa 32(V2) + +heltec_wifi_lora_32_V2.bootloader.tool=esptool_py +heltec_wifi_lora_32_V2.bootloader.tool.default=esptool_py + +heltec_wifi_lora_32_V2.upload.tool=esptool_py +heltec_wifi_lora_32_V2.upload.tool.default=esptool_py +heltec_wifi_lora_32_V2.upload.tool.network=esp_ota + +heltec_wifi_lora_32_V2.upload.maximum_size=3342336 +heltec_wifi_lora_32_V2.upload.maximum_data_size=327680 +heltec_wifi_lora_32_V2.upload.flags= +heltec_wifi_lora_32_V2.upload.extra_flags= + +heltec_wifi_lora_32_V2.serial.disableDTR=true +heltec_wifi_lora_32_V2.serial.disableRTS=true + +heltec_wifi_lora_32_V2.build.tarch=xtensa +heltec_wifi_lora_32_V2.build.bootloader_addr=0x1000 +heltec_wifi_lora_32_V2.build.target=esp32 +heltec_wifi_lora_32_V2.build.mcu=esp32 +heltec_wifi_lora_32_V2.build.core=esp32 +heltec_wifi_lora_32_V2.build.variant=heltec_wifi_lora_32_V2 +heltec_wifi_lora_32_V2.build.board=HELTEC_WIFI_LORA_32_V2 + +heltec_wifi_lora_32_V2.build.f_cpu=240000000L +heltec_wifi_lora_32_V2.build.flash_size=8MB +heltec_wifi_lora_32_V2.build.flash_freq=80m +heltec_wifi_lora_32_V2.build.flash_mode=dio +heltec_wifi_lora_32_V2.build.boot=qio +heltec_wifi_lora_32_V2.build.partitions=default_8MB +heltec_wifi_lora_32_V2.build.psram= +heltec_wifi_lora_32_V2.build.defines=-D{build.band} -DMCU_ESP32_D0 -DWIFI_LORA_32_V2 -DHELTEC_BOARD=0 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} {build.psram} + +heltec_wifi_lora_32_V2.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wifi_lora_32_V2.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wifi_lora_32_V2.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wifi_lora_32_V2.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wifi_lora_32_V2.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wifi_lora_32_V2.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wifi_lora_32_V2.menu.UploadSpeed.921600=921600 +heltec_wifi_lora_32_V2.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wifi_lora_32_V2.menu.UploadSpeed.115200=115200 +heltec_wifi_lora_32_V2.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wifi_lora_32_V2.menu.UploadSpeed.256000.windows=256000 +heltec_wifi_lora_32_V2.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wifi_lora_32_V2.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wifi_lora_32_V2.menu.UploadSpeed.230400=230400 +heltec_wifi_lora_32_V2.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wifi_lora_32_V2.menu.UploadSpeed.460800.linux=460800 +heltec_wifi_lora_32_V2.menu.UploadSpeed.460800.macosx=460800 +heltec_wifi_lora_32_V2.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wifi_lora_32_V2.menu.UploadSpeed.512000.windows=512000 +heltec_wifi_lora_32_V2.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wifi_lora_32_V2.menu.DebugLevel.none=None +heltec_wifi_lora_32_V2.menu.DebugLevel.none.build.code_debug=0 +heltec_wifi_lora_32_V2.menu.DebugLevel.error=Error +heltec_wifi_lora_32_V2.menu.DebugLevel.error.build.code_debug=1 +heltec_wifi_lora_32_V2.menu.DebugLevel.warn=Warn +heltec_wifi_lora_32_V2.menu.DebugLevel.warn.build.code_debug=2 +heltec_wifi_lora_32_V2.menu.DebugLevel.info=Info +heltec_wifi_lora_32_V2.menu.DebugLevel.info.build.code_debug=3 +heltec_wifi_lora_32_V2.menu.DebugLevel.debug=Debug +heltec_wifi_lora_32_V2.menu.DebugLevel.debug.build.code_debug=4 +heltec_wifi_lora_32_V2.menu.DebugLevel.verbose=Verbose +heltec_wifi_lora_32_V2.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.0=None +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.1=Freq +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wifi_lora_32_V2.menu.EraseFlash.none=Disabled +heltec_wifi_lora_32_V2.menu.EraseFlash.none.upload.erase_cmd= +heltec_wifi_lora_32_V2.menu.EraseFlash.all=Enabled +heltec_wifi_lora_32_V2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wifi_lora_32_V3.name=Heltec WiFi LoRa 32(V3) + +heltec_wifi_lora_32_V3.bootloader.tool=esptool_py +heltec_wifi_lora_32_V3.bootloader.tool.default=esptool_py + +heltec_wifi_lora_32_V3.upload.tool=esptool_py +heltec_wifi_lora_32_V3.upload.tool.default=esptool_py +heltec_wifi_lora_32_V3.upload.tool.network=esp_ota + +heltec_wifi_lora_32_V3.upload.maximum_size=3342336 +heltec_wifi_lora_32_V3.upload.maximum_data_size=327680 +heltec_wifi_lora_32_V3.upload.flags= +heltec_wifi_lora_32_V3.upload.extra_flags= +heltec_wifi_lora_32_V3.upload.use_1200bps_touch=false +heltec_wifi_lora_32_V3.upload.wait_for_upload_port=false + +heltec_wifi_lora_32_V3.serial.disableDTR=false +heltec_wifi_lora_32_V3.serial.disableRTS=false + +heltec_wifi_lora_32_V3.build.tarch=xtensa +heltec_wifi_lora_32_V3.build.bootloader_addr=0x0 +heltec_wifi_lora_32_V3.build.target=esp32s3 +heltec_wifi_lora_32_V3.build.mcu=esp32s3 +heltec_wifi_lora_32_V3.build.core=esp32 +heltec_wifi_lora_32_V3.build.variant=heltec_wifi_lora_32_V3 +heltec_wifi_lora_32_V3.build.board=HELTEC_WIFI_LORA_32_V3 + +heltec_wifi_lora_32_V3.build.usb_mode=1 +heltec_wifi_lora_32_V3.build.cdc_on_boot=0 +heltec_wifi_lora_32_V3.build.msc_on_boot=0 +heltec_wifi_lora_32_V3.build.dfu_on_boot=0 +heltec_wifi_lora_32_V3.build.f_cpu=240000000L +heltec_wifi_lora_32_V3.build.flash_size=8MB +heltec_wifi_lora_32_V3.build.flash_freq=80m +heltec_wifi_lora_32_V3.build.flash_mode=dio +heltec_wifi_lora_32_V3.build.boot=qio +heltec_wifi_lora_32_V3.build.boot_freq=80m +heltec_wifi_lora_32_V3.build.partitions=default_8MB +heltec_wifi_lora_32_V3.build.loop_core= +heltec_wifi_lora_32_V3.build.event_core= +heltec_wifi_lora_32_V3.build.psram_type=qspi +heltec_wifi_lora_32_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_wifi_lora_32_V3.menu.LoopCore.1=Core 1 +heltec_wifi_lora_32_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wifi_lora_32_V3.menu.LoopCore.0=Core 0 +heltec_wifi_lora_32_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wifi_lora_32_V3.menu.EventsCore.1=Core 1 +heltec_wifi_lora_32_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wifi_lora_32_V3.menu.EventsCore.0=Core 0 +heltec_wifi_lora_32_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wifi_lora_32_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_wifi_lora_32_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wifi_lora_32_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_wifi_lora_32_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wifi_lora_32_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_wifi_lora_32_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wifi_lora_32_V3.menu.CPUFreq.40=40MHz +heltec_wifi_lora_32_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wifi_lora_32_V3.menu.CPUFreq.20=20MHz +heltec_wifi_lora_32_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wifi_lora_32_V3.menu.CPUFreq.10=10MHz +heltec_wifi_lora_32_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wifi_lora_32_V3.menu.UploadSpeed.921600=921600 +heltec_wifi_lora_32_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wifi_lora_32_V3.menu.UploadSpeed.115200=115200 +heltec_wifi_lora_32_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wifi_lora_32_V3.menu.UploadSpeed.256000.windows=256000 +heltec_wifi_lora_32_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wifi_lora_32_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wifi_lora_32_V3.menu.UploadSpeed.230400=230400 +heltec_wifi_lora_32_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.linux=460800 +heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wifi_lora_32_V3.menu.UploadSpeed.512000.windows=512000 +heltec_wifi_lora_32_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wifi_lora_32_V3.menu.DebugLevel.none=None +heltec_wifi_lora_32_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_wifi_lora_32_V3.menu.DebugLevel.error=Error +heltec_wifi_lora_32_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_wifi_lora_32_V3.menu.DebugLevel.warn=Warn +heltec_wifi_lora_32_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_wifi_lora_32_V3.menu.DebugLevel.info=Info +heltec_wifi_lora_32_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_wifi_lora_32_V3.menu.DebugLevel.debug=Debug +heltec_wifi_lora_32_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_wifi_lora_32_V3.menu.DebugLevel.verbose=Verbose +heltec_wifi_lora_32_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.0=None +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.1=Freq +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wifi_lora_32_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=30 -DWIFI_LORA_32_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wifi_lora_32_V3.menu.EraseFlash.none=Disabled +heltec_wifi_lora_32_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_wifi_lora_32_V3.menu.EraseFlash.all=Enabled +heltec_wifi_lora_32_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_stick_V3.name=Heltec Wireless Stick(V3) + +heltec_wireless_stick_V3.bootloader.tool=esptool_py +heltec_wireless_stick_V3.bootloader.tool.default=esptool_py + +heltec_wireless_stick_V3.upload.tool=esptool_py +heltec_wireless_stick_V3.upload.tool.default=esptool_py +heltec_wireless_stick_V3.upload.tool.network=esp_ota + +heltec_wireless_stick_V3.upload.maximum_size=3342336 +heltec_wireless_stick_V3.upload.maximum_data_size=327680 +heltec_wireless_stick_V3.upload.flags= +heltec_wireless_stick_V3.upload.extra_flags= +heltec_wireless_stick_V3.upload.use_1200bps_touch=false +heltec_wireless_stick_V3.upload.wait_for_upload_port=false + +heltec_wireless_stick_V3.serial.disableDTR=false +heltec_wireless_stick_V3.serial.disableRTS=false + +heltec_wireless_stick_V3.build.tarch=xtensa +heltec_wireless_stick_V3.build.bootloader_addr=0x0 +heltec_wireless_stick_V3.build.target=esp32s3 +heltec_wireless_stick_V3.build.mcu=esp32s3 +heltec_wireless_stick_V3.build.core=esp32 +heltec_wireless_stick_V3.build.variant=heltec_wireless_stick_v3 +heltec_wireless_stick_V3.build.board=HELTEC_WIRELESS_STICK_V3 + +heltec_wireless_stick_V3.build.usb_mode=1 +heltec_wireless_stick_V3.build.cdc_on_boot=0 +heltec_wireless_stick_V3.build.msc_on_boot=0 +heltec_wireless_stick_V3.build.dfu_on_boot=0 +heltec_wireless_stick_V3.build.f_cpu=240000000L +heltec_wireless_stick_V3.build.flash_size=8MB +heltec_wireless_stick_V3.build.flash_freq=80m +heltec_wireless_stick_V3.build.flash_mode=dio +heltec_wireless_stick_V3.build.boot=qio +heltec_wireless_stick_V3.build.boot_freq=80m +heltec_wireless_stick_V3.build.partitions=default_8MB +heltec_wireless_stick_V3.build.loop_core= +heltec_wireless_stick_V3.build.event_core= +heltec_wireless_stick_V3.build.psram_type=qspi +heltec_wireless_stick_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_wireless_stick_V3.menu.LoopCore.1=Core 1 +heltec_wireless_stick_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wireless_stick_V3.menu.LoopCore.0=Core 0 +heltec_wireless_stick_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wireless_stick_V3.menu.EventsCore.1=Core 1 +heltec_wireless_stick_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wireless_stick_V3.menu.EventsCore.0=Core 0 +heltec_wireless_stick_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wireless_stick_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_wireless_stick_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_stick_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_stick_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_stick_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_stick_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_stick_V3.menu.CPUFreq.40=40MHz +heltec_wireless_stick_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_stick_V3.menu.CPUFreq.20=20MHz +heltec_wireless_stick_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_stick_V3.menu.CPUFreq.10=10MHz +heltec_wireless_stick_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_stick_V3.menu.UploadSpeed.921600=921600 +heltec_wireless_stick_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_stick_V3.menu.UploadSpeed.115200=115200 +heltec_wireless_stick_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_stick_V3.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_stick_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_stick_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_stick_V3.menu.UploadSpeed.230400=230400 +heltec_wireless_stick_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_stick_V3.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_stick_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_stick_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_stick_V3.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_stick_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_stick_V3.menu.DebugLevel.none=None +heltec_wireless_stick_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_stick_V3.menu.DebugLevel.error=Error +heltec_wireless_stick_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_stick_V3.menu.DebugLevel.warn=Warn +heltec_wireless_stick_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_stick_V3.menu.DebugLevel.info=Info +heltec_wireless_stick_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_stick_V3.menu.DebugLevel.debug=Debug +heltec_wireless_stick_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_stick_V3.menu.DebugLevel.verbose=Verbose +heltec_wireless_stick_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_stick_V3.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_stick_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_stick_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.0=None +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wireless_stick_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=31 -DWIRELESS_STICK_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_stick_V3.menu.EraseFlash.none=Disabled +heltec_wireless_stick_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_stick_V3.menu.EraseFlash.all=Enabled +heltec_wireless_stick_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_stick_lite_V3.name=Heltec Wireless Stick Lite(V3) + +heltec_wireless_stick_lite_V3.bootloader.tool=esptool_py +heltec_wireless_stick_lite_V3.bootloader.tool.default=esptool_py + +heltec_wireless_stick_lite_V3.upload.tool=esptool_py +heltec_wireless_stick_lite_V3.upload.tool.default=esptool_py +heltec_wireless_stick_lite_V3.upload.tool.network=esp_ota + +heltec_wireless_stick_lite_V3.upload.maximum_size=3342336 +heltec_wireless_stick_lite_V3.upload.maximum_data_size=327680 +heltec_wireless_stick_lite_V3.upload.flags= +heltec_wireless_stick_lite_V3.upload.extra_flags= +heltec_wireless_stick_lite_V3.upload.use_1200bps_touch=false +heltec_wireless_stick_lite_V3.upload.wait_for_upload_port=false + +heltec_wireless_stick_lite_V3.serial.disableDTR=false +heltec_wireless_stick_lite_V3.serial.disableRTS=false + +heltec_wireless_stick_lite_V3.build.tarch=xtensa +heltec_wireless_stick_lite_V3.build.bootloader_addr=0x0 +heltec_wireless_stick_lite_V3.build.target=esp32s3 +heltec_wireless_stick_lite_V3.build.mcu=esp32s3 +heltec_wireless_stick_lite_V3.build.core=esp32 +heltec_wireless_stick_lite_V3.build.variant=heltec_wireless_stick_lite_v3 +heltec_wireless_stick_lite_V3.build.board=HELTEC_WIRELESS_STICK_LITE_V3 + +heltec_wireless_stick_lite_V3.build.usb_mode=1 +heltec_wireless_stick_lite_V3.build.cdc_on_boot=0 +heltec_wireless_stick_lite_V3.build.msc_on_boot=0 +heltec_wireless_stick_lite_V3.build.dfu_on_boot=0 +heltec_wireless_stick_lite_V3.build.f_cpu=240000000L +heltec_wireless_stick_lite_V3.build.flash_size=8MB +heltec_wireless_stick_lite_V3.build.flash_freq=80m +heltec_wireless_stick_lite_V3.build.flash_mode=dio +heltec_wireless_stick_lite_V3.build.boot=qio +heltec_wireless_stick_lite_V3.build.boot_freq=80m +heltec_wireless_stick_lite_V3.build.partitions=default_8MB +heltec_wireless_stick_lite_V3.build.loop_core= +heltec_wireless_stick_lite_V3.build.event_core= +heltec_wireless_stick_lite_V3.build.psram_type=qspi +heltec_wireless_stick_lite_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_wireless_stick_lite_V3.menu.LoopCore.1=Core 1 +heltec_wireless_stick_lite_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wireless_stick_lite_V3.menu.LoopCore.0=Core 0 +heltec_wireless_stick_lite_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wireless_stick_lite_V3.menu.EventsCore.1=Core 1 +heltec_wireless_stick_lite_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wireless_stick_lite_V3.menu.EventsCore.0=Core 0 +heltec_wireless_stick_lite_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wireless_stick_lite_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_wireless_stick_lite_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_stick_lite_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_stick_lite_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_stick_lite_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_stick_lite_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_stick_lite_V3.menu.CPUFreq.40=40MHz +heltec_wireless_stick_lite_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_stick_lite_V3.menu.CPUFreq.20=20MHz +heltec_wireless_stick_lite_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_stick_lite_V3.menu.CPUFreq.10=10MHz +heltec_wireless_stick_lite_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_stick_lite_V3.menu.UploadSpeed.921600=921600 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.115200=115200 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400=230400 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_stick_lite_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_stick_lite_V3.menu.DebugLevel.none=None +heltec_wireless_stick_lite_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_stick_lite_V3.menu.DebugLevel.error=Error +heltec_wireless_stick_lite_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_stick_lite_V3.menu.DebugLevel.warn=Warn +heltec_wireless_stick_lite_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_stick_lite_V3.menu.DebugLevel.info=Info +heltec_wireless_stick_lite_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_stick_lite_V3.menu.DebugLevel.debug=Debug +heltec_wireless_stick_lite_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_stick_lite_V3.menu.DebugLevel.verbose=Verbose +heltec_wireless_stick_lite_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.0=None +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wireless_stick_lite_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=32 -DWIRELESS_STICK_LITE_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_stick_lite_V3.menu.EraseFlash.none=Disabled +heltec_wireless_stick_lite_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_stick_lite_V3.menu.EraseFlash.all=Enabled +heltec_wireless_stick_lite_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_shell_V3.name=Heltec Wireless Shell (V3) + +heltec_wireless_shell_V3.bootloader.tool=esptool_py +heltec_wireless_shell_V3.bootloader.tool.default=esptool_py + +heltec_wireless_shell_V3.upload.tool=esptool_py +heltec_wireless_shell_V3.upload.tool.default=esptool_py +heltec_wireless_shell_V3.upload.tool.network=esp_ota + +heltec_wireless_shell_V3.upload.maximum_size=3342336 +heltec_wireless_shell_V3.upload.maximum_data_size=327680 +heltec_wireless_shell_V3.upload.flags= +heltec_wireless_shell_V3.upload.extra_flags= +heltec_wireless_shell_V3.upload.use_1200bps_touch=false +heltec_wireless_shell_V3.upload.wait_for_upload_port=false + +heltec_wireless_shell_V3.serial.disableDTR=false +heltec_wireless_shell_V3.serial.disableRTS=false + +heltec_wireless_shell_V3.build.tarch=xtensa +heltec_wireless_shell_V3.build.bootloader_addr=0x0 +heltec_wireless_shell_V3.build.target=esp32s3 +heltec_wireless_shell_V3.build.mcu=esp32s3 +heltec_wireless_shell_V3.build.core=esp32 +heltec_wireless_shell_V3.build.variant=heltec_wireless_shell_v3 +heltec_wireless_shell_V3.build.board=HELTEC_WIRELESS_SHELL_V3 + +heltec_wireless_shell_V3.build.usb_mode=1 +heltec_wireless_shell_V3.build.cdc_on_boot=0 +heltec_wireless_shell_V3.build.msc_on_boot=0 +heltec_wireless_shell_V3.build.dfu_on_boot=0 +heltec_wireless_shell_V3.build.f_cpu=240000000L +heltec_wireless_shell_V3.build.flash_size=8MB +heltec_wireless_shell_V3.build.flash_freq=80m +heltec_wireless_shell_V3.build.flash_mode=dio +heltec_wireless_shell_V3.build.boot=qio +heltec_wireless_shell_V3.build.boot_freq=80m +heltec_wireless_shell_V3.build.partitions=default_8MB +heltec_wireless_shell_V3.build.loop_core= +heltec_wireless_shell_V3.build.event_core= +heltec_wireless_shell_V3.build.psram_type=qspi +heltec_wireless_shell_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_wireless_shell_V3.menu.LoopCore.1=Core 1 +heltec_wireless_shell_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wireless_shell_V3.menu.LoopCore.0=Core 0 +heltec_wireless_shell_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wireless_shell_V3.menu.EventsCore.1=Core 1 +heltec_wireless_shell_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wireless_shell_V3.menu.EventsCore.0=Core 0 +heltec_wireless_shell_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wireless_shell_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_wireless_shell_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_shell_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_shell_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_shell_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_shell_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_shell_V3.menu.CPUFreq.40=40MHz +heltec_wireless_shell_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_shell_V3.menu.CPUFreq.20=20MHz +heltec_wireless_shell_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_shell_V3.menu.CPUFreq.10=10MHz +heltec_wireless_shell_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_shell_V3.menu.UploadSpeed.921600=921600 +heltec_wireless_shell_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_shell_V3.menu.UploadSpeed.115200=115200 +heltec_wireless_shell_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_shell_V3.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_shell_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_shell_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_shell_V3.menu.UploadSpeed.230400=230400 +heltec_wireless_shell_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_shell_V3.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_shell_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_shell_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_shell_V3.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_shell_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_shell_V3.menu.DebugLevel.none=None +heltec_wireless_shell_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_shell_V3.menu.DebugLevel.error=Error +heltec_wireless_shell_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_shell_V3.menu.DebugLevel.warn=Warn +heltec_wireless_shell_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_shell_V3.menu.DebugLevel.info=Info +heltec_wireless_shell_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_shell_V3.menu.DebugLevel.debug=Debug +heltec_wireless_shell_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_shell_V3.menu.DebugLevel.verbose=Verbose +heltec_wireless_shell_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_shell_V3.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_shell_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_shell_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.0=None +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wireless_shell_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=33 -DWIRELESS_SHELL_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_shell_V3.menu.EraseFlash.none=Disabled +heltec_wireless_shell_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_shell_V3.menu.EraseFlash.all=Enabled +heltec_wireless_shell_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_capsule_sensor_V3.name=Heltec Capsule Sensor (V3) + +heltec_capsule_sensor_V3.bootloader.tool=esptool_py +heltec_capsule_sensor_V3.bootloader.tool.default=esptool_py + +heltec_capsule_sensor_V3.upload.tool=esptool_py +heltec_capsule_sensor_V3.upload.tool.default=esptool_py +heltec_capsule_sensor_V3.upload.tool.network=esp_ota + +heltec_capsule_sensor_V3.upload.maximum_size=3342336 +heltec_capsule_sensor_V3.upload.maximum_data_size=327680 +heltec_capsule_sensor_V3.upload.flags= +heltec_capsule_sensor_V3.upload.extra_flags= +heltec_capsule_sensor_V3.upload.use_1200bps_touch=false +heltec_capsule_sensor_V3.upload.wait_for_upload_port=false + +heltec_capsule_sensor_V3.serial.disableDTR=false +heltec_capsule_sensor_V3.serial.disableRTS=false + +heltec_capsule_sensor_V3.build.tarch=xtensa +heltec_capsule_sensor_V3.build.bootloader_addr=0x0 +heltec_capsule_sensor_V3.build.target=esp32s3 +heltec_capsule_sensor_V3.build.mcu=esp32s3 +heltec_capsule_sensor_V3.build.core=esp32 +heltec_capsule_sensor_V3.build.variant=heltec_capsule_sensor_v3 +heltec_capsule_sensor_V3.build.board=HELTEC_CAPSULE_SENSOR_V3 + +heltec_capsule_sensor_V3.build.usb_mode=1 +heltec_capsule_sensor_V3.build.cdc_on_boot=0 +heltec_capsule_sensor_V3.build.msc_on_boot=0 +heltec_capsule_sensor_V3.build.dfu_on_boot=0 +heltec_capsule_sensor_V3.build.f_cpu=240000000L +heltec_capsule_sensor_V3.build.flash_size=8MB +heltec_capsule_sensor_V3.build.flash_freq=80m +heltec_capsule_sensor_V3.build.flash_mode=dio +heltec_capsule_sensor_V3.build.boot=qio +heltec_capsule_sensor_V3.build.boot_freq=80m +heltec_capsule_sensor_V3.build.partitions=partitions +heltec_capsule_sensor_V3.build.loop_core= +heltec_capsule_sensor_V3.build.event_core= +heltec_capsule_sensor_V3.build.psram_type=qspi +heltec_capsule_sensor_V3.build.memory_type={build.boot}_{build.psram_type} + +heltec_capsule_sensor_V3.menu.LoopCore.1=Core 1 +heltec_capsule_sensor_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_capsule_sensor_V3.menu.LoopCore.0=Core 0 +heltec_capsule_sensor_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_capsule_sensor_V3.menu.EventsCore.1=Core 1 +heltec_capsule_sensor_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_capsule_sensor_V3.menu.EventsCore.0=Core 0 +heltec_capsule_sensor_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_capsule_sensor_V3.menu.CPUFreq.240=240MHz (WiFi) +heltec_capsule_sensor_V3.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_capsule_sensor_V3.menu.CPUFreq.160=160MHz (WiFi) +heltec_capsule_sensor_V3.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_capsule_sensor_V3.menu.CPUFreq.80=80MHz (WiFi) +heltec_capsule_sensor_V3.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_capsule_sensor_V3.menu.CPUFreq.40=40MHz +heltec_capsule_sensor_V3.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_capsule_sensor_V3.menu.CPUFreq.20=20MHz +heltec_capsule_sensor_V3.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_capsule_sensor_V3.menu.CPUFreq.10=10MHz +heltec_capsule_sensor_V3.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_capsule_sensor_V3.menu.UploadSpeed.921600=921600 +heltec_capsule_sensor_V3.menu.UploadSpeed.921600.upload.speed=921600 +heltec_capsule_sensor_V3.menu.UploadSpeed.115200=115200 +heltec_capsule_sensor_V3.menu.UploadSpeed.115200.upload.speed=115200 +heltec_capsule_sensor_V3.menu.UploadSpeed.256000.windows=256000 +heltec_capsule_sensor_V3.menu.UploadSpeed.256000.upload.speed=256000 +heltec_capsule_sensor_V3.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_capsule_sensor_V3.menu.UploadSpeed.230400=230400 +heltec_capsule_sensor_V3.menu.UploadSpeed.230400.upload.speed=230400 +heltec_capsule_sensor_V3.menu.UploadSpeed.460800.linux=460800 +heltec_capsule_sensor_V3.menu.UploadSpeed.460800.macosx=460800 +heltec_capsule_sensor_V3.menu.UploadSpeed.460800.upload.speed=460800 +heltec_capsule_sensor_V3.menu.UploadSpeed.512000.windows=512000 +heltec_capsule_sensor_V3.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_capsule_sensor_V3.menu.DebugLevel.none=None +heltec_capsule_sensor_V3.menu.DebugLevel.none.build.code_debug=0 +heltec_capsule_sensor_V3.menu.DebugLevel.error=Error +heltec_capsule_sensor_V3.menu.DebugLevel.error.build.code_debug=1 +heltec_capsule_sensor_V3.menu.DebugLevel.warn=Warn +heltec_capsule_sensor_V3.menu.DebugLevel.warn.build.code_debug=2 +heltec_capsule_sensor_V3.menu.DebugLevel.info=Info +heltec_capsule_sensor_V3.menu.DebugLevel.info.build.code_debug=3 +heltec_capsule_sensor_V3.menu.DebugLevel.debug=Debug +heltec_capsule_sensor_V3.menu.DebugLevel.debug.build.code_debug=4 +heltec_capsule_sensor_V3.menu.DebugLevel.verbose=Verbose +heltec_capsule_sensor_V3.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.3=REGION_US915 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_capsule_sensor_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.0=None +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.1=Freq +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + + +heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.0=External 32K (default) +heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=1 +heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.1=Internal +heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=0 + +heltec_capsule_sensor_V3.menu.NetworkLogLevel.0=NONE +heltec_capsule_sensor_V3.menu.NetworkLogLevel.0.build.NetworkLogLevel=0 +heltec_capsule_sensor_V3.menu.NetworkLogLevel.1=ERROR +heltec_capsule_sensor_V3.menu.NetworkLogLevel.1.build.NetworkLogLevel=1 +heltec_capsule_sensor_V3.menu.NetworkLogLevel.2=WARN +heltec_capsule_sensor_V3.menu.NetworkLogLevel.2.build.NetworkLogLevel=2 +heltec_capsule_sensor_V3.menu.NetworkLogLevel.3=INFO +heltec_capsule_sensor_V3.menu.NetworkLogLevel.3.build.NetworkLogLevel=3 + +heltec_capsule_sensor_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=50 -DCAPSULE_SENSOR_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} -DNLOG_LOCAL_LEVEL={build.NetworkLogLevel} + +heltec_capsule_sensor_V3.menu.EraseFlash.none=Disabled +heltec_capsule_sensor_V3.menu.EraseFlash.none.upload.erase_cmd= +heltec_capsule_sensor_V3.menu.EraseFlash.all=Enabled +heltec_capsule_sensor_V3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################# + +heltec_wireless_paper.name=Heltec Wireless Paper + +heltec_wireless_paper.bootloader.tool=esptool_py +heltec_wireless_paper.bootloader.tool.default=esptool_py + +heltec_wireless_paper.upload.tool=esptool_py +heltec_wireless_paper.upload.tool.default=esptool_py +heltec_wireless_paper.upload.tool.network=esp_ota + +heltec_wireless_paper.upload.maximum_size=4026368 +heltec_wireless_paper.upload.maximum_data_size=327680 +heltec_wireless_paper.upload.flags= +heltec_wireless_paper.upload.extra_flags= +heltec_wireless_paper.upload.use_1200bps_touch=false +heltec_wireless_paper.upload.wait_for_upload_port=false + +heltec_wireless_paper.serial.disableDTR=false +heltec_wireless_paper.serial.disableRTS=false + +heltec_wireless_paper.build.tarch=xtensa +heltec_wireless_paper.build.bootloader_addr=0x0 +heltec_wireless_paper.build.target=esp32s3 +heltec_wireless_paper.build.mcu=esp32s3 +heltec_wireless_paper.build.core=esp32 +heltec_wireless_paper.build.variant=heltec_wireless_paper +heltec_wireless_paper.build.board=HELTEC_WIRELESS_PAPER + +heltec_wireless_paper.build.usb_mode=1 +heltec_wireless_paper.build.cdc_on_boot=0 +heltec_wireless_paper.build.msc_on_boot=0 +heltec_wireless_paper.build.dfu_on_boot=0 +heltec_wireless_paper.build.f_cpu=240000000L +heltec_wireless_paper.build.flash_size=8MB +heltec_wireless_paper.build.flash_freq=80m +heltec_wireless_paper.build.flash_mode=dio +heltec_wireless_paper.build.boot=qio +heltec_wireless_paper.build.boot_freq=80m +heltec_wireless_paper.build.partitions=default_8MB +heltec_wireless_paper.build.loop_core= +heltec_wireless_paper.build.event_core= +heltec_wireless_paper.build.psram_type=qspi +heltec_wireless_paper.build.memory_type={build.boot}_{build.psram_type} + +heltec_wireless_paper.menu.LoopCore.1=Core 1 +heltec_wireless_paper.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wireless_paper.menu.LoopCore.0=Core 0 +heltec_wireless_paper.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wireless_paper.menu.EventsCore.1=Core 1 +heltec_wireless_paper.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wireless_paper.menu.EventsCore.0=Core 0 +heltec_wireless_paper.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wireless_paper.menu.CPUFreq.240=240MHz (WiFi) +heltec_wireless_paper.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_paper.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_paper.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_paper.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_paper.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_paper.menu.CPUFreq.40=40MHz +heltec_wireless_paper.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_paper.menu.CPUFreq.20=20MHz +heltec_wireless_paper.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_paper.menu.CPUFreq.10=10MHz +heltec_wireless_paper.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_paper.menu.UploadSpeed.921600=921600 +heltec_wireless_paper.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_paper.menu.UploadSpeed.115200=115200 +heltec_wireless_paper.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_paper.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_paper.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_paper.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_paper.menu.UploadSpeed.230400=230400 +heltec_wireless_paper.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_paper.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_paper.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_paper.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_paper.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_paper.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_paper.menu.DebugLevel.none=None +heltec_wireless_paper.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_paper.menu.DebugLevel.error=Error +heltec_wireless_paper.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_paper.menu.DebugLevel.warn=Warn +heltec_wireless_paper.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_paper.menu.DebugLevel.info=Info +heltec_wireless_paper.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_paper.menu.DebugLevel.debug=Debug +heltec_wireless_paper.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_paper.menu.DebugLevel.verbose=Verbose +heltec_wireless_paper.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_paper.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_paper.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_paper.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_paper.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_paper.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_paper.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_paper.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_paper.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_paper.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_paper.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_paper.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_paper.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_paper.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_paper.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_paper.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_paper.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_paper.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_paper.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_paper.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_paper.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_paper.menu.LoRaWanDebugLevel.0=None +heltec_wireless_paper.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_paper.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_paper.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_paper.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_paper.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_paper.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_paper.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_paper.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_paper.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_paper.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_paper.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_paper.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wireless_paper.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wireless_paper.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wireless_paper.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wireless_paper.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=60 -DWIRELESS_PAPER -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_paper.menu.EraseFlash.none=Disabled +heltec_wireless_paper.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_paper.menu.EraseFlash.all=Enabled +heltec_wireless_paper.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_tracker.name=Heltec Wireless Tracker + +heltec_wireless_tracker.bootloader.tool=esptool_py +heltec_wireless_tracker.bootloader.tool.default=esptool_py + +heltec_wireless_tracker.upload.tool=esptool_py +heltec_wireless_tracker.upload.tool.default=esptool_py +heltec_wireless_tracker.upload.tool.network=esp_ota + +heltec_wireless_tracker.upload.maximum_size=3342336 +heltec_wireless_tracker.upload.maximum_data_size=327680 +heltec_wireless_tracker.upload.flags= +heltec_wireless_tracker.upload.extra_flags= +heltec_wireless_tracker.upload.use_1200bps_touch=false +heltec_wireless_tracker.upload.wait_for_upload_port=false + +heltec_wireless_tracker.serial.disableDTR=false +heltec_wireless_tracker.serial.disableRTS=false + +heltec_wireless_tracker.build.tarch=xtensa +heltec_wireless_tracker.build.bootloader_addr=0x0 +heltec_wireless_tracker.build.target=esp32s3 +heltec_wireless_tracker.build.mcu=esp32s3 +heltec_wireless_tracker.build.core=esp32 +heltec_wireless_tracker.build.variant=heltec_wireless_tracker +heltec_wireless_tracker.build.board=HELTEC_WIRELESS_TRACKER + +heltec_wireless_tracker.build.usb_mode=1 +heltec_wireless_tracker.build.cdc_on_boot=0 +heltec_wireless_tracker.build.msc_on_boot=0 +heltec_wireless_tracker.build.dfu_on_boot=0 +heltec_wireless_tracker.build.f_cpu=240000000L +heltec_wireless_tracker.build.flash_size=8MB +heltec_wireless_tracker.build.flash_freq=80m +heltec_wireless_tracker.build.flash_mode=dio +heltec_wireless_tracker.build.boot=qio +heltec_wireless_tracker.build.boot_freq=80m +heltec_wireless_tracker.build.partitions=default_8MB +heltec_wireless_tracker.build.loop_core= +heltec_wireless_tracker.build.event_core= +heltec_wireless_tracker.build.psram_type=qspi +heltec_wireless_tracker.build.memory_type={build.boot}_{build.psram_type} + +heltec_wireless_tracker.menu.LoopCore.1=Core 1 +heltec_wireless_tracker.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_wireless_tracker.menu.LoopCore.0=Core 0 +heltec_wireless_tracker.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_wireless_tracker.menu.EventsCore.1=Core 1 +heltec_wireless_tracker.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_wireless_tracker.menu.EventsCore.0=Core 0 +heltec_wireless_tracker.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_wireless_tracker.menu.USBMode.hwcdc=Hardware CDC and JTAG +heltec_wireless_tracker.menu.USBMode.hwcdc.build.usb_mode=1 +heltec_wireless_tracker.menu.USBMode.default=USB-OTG (TinyUSB) +heltec_wireless_tracker.menu.USBMode.default.build.usb_mode=0 + +heltec_wireless_tracker.menu.CDCOnBoot.default=Enabled +heltec_wireless_tracker.menu.CDCOnBoot.default.build.cdc_on_boot=1 +heltec_wireless_tracker.menu.CDCOnBoot.cdc=Disabled +heltec_wireless_tracker.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +heltec_wireless_tracker.menu.MSCOnBoot.default=Disabled +heltec_wireless_tracker.menu.MSCOnBoot.default.build.msc_on_boot=0 +heltec_wireless_tracker.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +heltec_wireless_tracker.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +heltec_wireless_tracker.menu.DFUOnBoot.default=Disabled +heltec_wireless_tracker.menu.DFUOnBoot.default.build.dfu_on_boot=0 +heltec_wireless_tracker.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +heltec_wireless_tracker.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +heltec_wireless_tracker.menu.UploadMode.default=UART0 / Hardware CDC +heltec_wireless_tracker.menu.UploadMode.default.upload.use_1200bps_touch=false +heltec_wireless_tracker.menu.UploadMode.default.upload.wait_for_upload_port=false +heltec_wireless_tracker.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +heltec_wireless_tracker.menu.UploadMode.cdc.upload.use_1200bps_touch=true +heltec_wireless_tracker.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +heltec_wireless_tracker.menu.CPUFreq.240=240MHz (WiFi) +heltec_wireless_tracker.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_tracker.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_tracker.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_tracker.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_tracker.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_tracker.menu.CPUFreq.40=40MHz +heltec_wireless_tracker.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_tracker.menu.CPUFreq.20=20MHz +heltec_wireless_tracker.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_tracker.menu.CPUFreq.10=10MHz +heltec_wireless_tracker.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_tracker.menu.UploadSpeed.921600=921600 +heltec_wireless_tracker.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_tracker.menu.UploadSpeed.115200=115200 +heltec_wireless_tracker.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_tracker.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_tracker.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_tracker.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_tracker.menu.UploadSpeed.230400=230400 +heltec_wireless_tracker.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_tracker.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_tracker.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_tracker.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_tracker.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_tracker.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_tracker.menu.DebugLevel.none=None +heltec_wireless_tracker.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_tracker.menu.DebugLevel.error=Error +heltec_wireless_tracker.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_tracker.menu.DebugLevel.warn=Warn +heltec_wireless_tracker.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_tracker.menu.DebugLevel.info=Info +heltec_wireless_tracker.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_tracker.menu.DebugLevel.debug=Debug +heltec_wireless_tracker.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_tracker.menu.DebugLevel.verbose=Verbose +heltec_wireless_tracker.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_tracker.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_tracker.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_tracker.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_tracker.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_tracker.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_tracker.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_tracker.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_tracker.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_tracker.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_tracker.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_tracker.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_tracker.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_tracker.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_tracker.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_tracker.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_tracker.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_tracker.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_tracker.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_tracker.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_tracker.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_tracker.menu.LoRaWanDebugLevel.0=None +heltec_wireless_tracker.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_tracker.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_tracker.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_tracker.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_tracker.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_tracker.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_tracker.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_tracker.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_tracker.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_tracker.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_tracker.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_tracker.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_wireless_tracker.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_wireless_tracker.menu.SLOW_CLK_TPYE.1=External 32K +heltec_wireless_tracker.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_wireless_tracker.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=34 -DWIRELESS_TRACKER -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_tracker.menu.EraseFlash.none=Disabled +heltec_wireless_tracker.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_tracker.menu.EraseFlash.all=Enabled +heltec_wireless_tracker.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_mini_shell.name=Heltec Wireless Mini Shell + +heltec_wireless_mini_shell.bootloader.tool=esptool_py +heltec_wireless_mini_shell.bootloader.tool.default=esptool_py + +heltec_wireless_mini_shell.upload.tool=esptool_py +heltec_wireless_mini_shell.upload.tool.default=esptool_py +heltec_wireless_mini_shell.upload.tool.network=esp_ota + +heltec_wireless_mini_shell.upload.maximum_size=1310720 +heltec_wireless_mini_shell.upload.maximum_data_size=327680 +heltec_wireless_mini_shell.upload.flags= +heltec_wireless_mini_shell.upload.extra_flags= +heltec_wireless_mini_shell.upload.use_1200bps_touch=false +heltec_wireless_mini_shell.upload.wait_for_upload_port=false + +heltec_wireless_mini_shell.serial.disableDTR=false +heltec_wireless_mini_shell.serial.disableRTS=false + +heltec_wireless_mini_shell.build.tarch=riscv32 +heltec_wireless_mini_shell.build.target=esp +heltec_wireless_mini_shell.build.mcu=esp32c3 +heltec_wireless_mini_shell.build.core=esp32 +heltec_wireless_mini_shell.build.variant=heltec_wireless_mini_shell +heltec_wireless_mini_shell.build.board=HELTEC_WIRELESS_MINI_SHELL +heltec_wireless_mini_shell.build.bootloader_addr=0x0 + +heltec_wireless_mini_shell.build.cdc_on_boot=0 +heltec_wireless_mini_shell.build.f_cpu=160000000L +heltec_wireless_mini_shell.build.flash_size=4MB +heltec_wireless_mini_shell.build.flash_freq=80m +heltec_wireless_mini_shell.build.flash_mode=dio +heltec_wireless_mini_shell.build.boot=qio +heltec_wireless_mini_shell.build.partitions=default + +heltec_wireless_mini_shell.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_mini_shell.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_mini_shell.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_mini_shell.menu.CPUFreq.160=160MHz (WiFi) +heltec_wireless_mini_shell.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_mini_shell.menu.CPUFreq.80=80MHz (WiFi) +heltec_wireless_mini_shell.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_wireless_mini_shell.menu.CPUFreq.40=40MHz +heltec_wireless_mini_shell.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_wireless_mini_shell.menu.CPUFreq.20=20MHz +heltec_wireless_mini_shell.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_wireless_mini_shell.menu.CPUFreq.10=10MHz +heltec_wireless_mini_shell.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_wireless_mini_shell.menu.UploadSpeed.921600=921600 +heltec_wireless_mini_shell.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_mini_shell.menu.UploadSpeed.115200=115200 +heltec_wireless_mini_shell.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_mini_shell.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_mini_shell.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_mini_shell.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_mini_shell.menu.UploadSpeed.230400=230400 +heltec_wireless_mini_shell.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_mini_shell.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_mini_shell.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_mini_shell.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_mini_shell.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_mini_shell.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_mini_shell.menu.DebugLevel.none=None +heltec_wireless_mini_shell.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_mini_shell.menu.DebugLevel.error=Error +heltec_wireless_mini_shell.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_mini_shell.menu.DebugLevel.warn=Warn +heltec_wireless_mini_shell.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_mini_shell.menu.DebugLevel.info=Info +heltec_wireless_mini_shell.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_mini_shell.menu.DebugLevel.debug=Debug +heltec_wireless_mini_shell.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_mini_shell.menu.DebugLevel.verbose=Verbose +heltec_wireless_mini_shell.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.0=None +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + + +heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_mini_shell.build.defines=-D{build.band} -DMCU_ESP32_C3 -DHELTEC_BOARD=70 -DWIRELESS_MINI_SHELL -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} +heltec_wireless_mini_shell.menu.EraseFlash.none=Disabled +heltec_wireless_mini_shell.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_mini_shell.menu.EraseFlash.all=Enabled +heltec_wireless_mini_shell.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_stick.name=Heltec Wireless Stick + +heltec_wireless_stick.bootloader.tool=esptool_py +heltec_wireless_stick.bootloader.tool.default=esptool_py + +heltec_wireless_stick.upload.tool=esptool_py +heltec_wireless_stick.upload.tool.default=esptool_py +heltec_wireless_stick.upload.tool.network=esp_ota + +heltec_wireless_stick.upload.maximum_size=3342336 +heltec_wireless_stick.upload.maximum_data_size=327680 +heltec_wireless_stick.upload.flags= +heltec_wireless_stick.upload.extra_flags= + +heltec_wireless_stick.serial.disableDTR=true +heltec_wireless_stick.serial.disableRTS=true + +heltec_wireless_stick.build.tarch=xtensa +heltec_wireless_stick.build.bootloader_addr=0x1000 +heltec_wireless_stick.build.target=esp32 +heltec_wireless_stick.build.mcu=esp32 +heltec_wireless_stick.build.core=esp32 +heltec_wireless_stick.build.variant=heltec_wireless_stick +heltec_wireless_stick.build.board=HELTEC_WIRELESS_STICK + +heltec_wireless_stick.build.f_cpu=240000000L +heltec_wireless_stick.build.flash_size=8MB +heltec_wireless_stick.build.flash_freq=80m +heltec_wireless_stick.build.flash_mode=dio +heltec_wireless_stick.build.boot=dio +heltec_wireless_stick.build.partitions=default_8MB +heltec_wireless_stick.build.build.psram= +heltec_wireless_stick.build.defines=-D{build.band} -DMCU_ESP32_D0 -DHELTEC_BOARD=2 -DWIRELESS_STICK -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX127X -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_stick.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wireless_stick.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_stick.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wireless_stick.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_stick.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wireless_stick.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wireless_stick.menu.UploadSpeed.921600=921600 +heltec_wireless_stick.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_stick.menu.UploadSpeed.115200=115200 +heltec_wireless_stick.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_stick.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_stick.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_stick.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_stick.menu.UploadSpeed.230400=230400 +heltec_wireless_stick.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_stick.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_stick.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_stick.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_stick.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_stick.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_stick.menu.DebugLevel.none=None +heltec_wireless_stick.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_stick.menu.DebugLevel.error=Error +heltec_wireless_stick.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_stick.menu.DebugLevel.warn=Warn +heltec_wireless_stick.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_stick.menu.DebugLevel.info=Info +heltec_wireless_stick.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_stick.menu.DebugLevel.debug=Debug +heltec_wireless_stick.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_stick.menu.DebugLevel.verbose=Verbose +heltec_wireless_stick.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_stick.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_stick.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_stick.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_stick.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_stick.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_stick.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_stick.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_stick.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_stick.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_stick.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_stick.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_stick.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_stick.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_stick.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_stick.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_stick.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_stick.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_stick.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_stick.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_stick.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_stick.menu.LoRaWanDebugLevel.0=None +heltec_wireless_stick.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_stick.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_stick.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_stick.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_stick.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_stick.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_stick.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_stick.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_stick.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_stick.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_stick.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_stick.menu.EraseFlash.none=Disabled +heltec_wireless_stick.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_stick.menu.EraseFlash.all=Enabled +heltec_wireless_stick.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_stick_lite.name=Heltec Wireless Stick Lite / Wireless Shell + +heltec_wireless_stick_lite.bootloader.tool=esptool_py +heltec_wireless_stick_lite.bootloader.tool.default=esptool_py + +heltec_wireless_stick_lite.upload.tool=esptool_py +heltec_wireless_stick_lite.upload.tool.default=esptool_py +heltec_wireless_stick_lite.upload.tool.network=esp_ota + +heltec_wireless_stick_lite.upload.maximum_size=1310720 +heltec_wireless_stick_lite.upload.maximum_data_size=327680 +heltec_wireless_stick_lite.upload.flags= +heltec_wireless_stick_lite.upload.extra_flags= + +heltec_wireless_stick_lite.serial.disableDTR=true +heltec_wireless_stick_lite.serial.disableRTS=true + +heltec_wireless_stick_lite.build.tarch=xtensa +heltec_wireless_stick_lite.build.bootloader_addr=0x1000 +heltec_wireless_stick_lite.build.target=esp32 +heltec_wireless_stick_lite.build.mcu=esp32 +heltec_wireless_stick_lite.build.core=esp32 +heltec_wireless_stick_lite.build.variant=heltec_wireless_stick_lite +heltec_wireless_stick_lite.build.board=HELTEC_WIRELESS_STICK_LITE + +heltec_wireless_stick_lite.build.f_cpu=240000000L +heltec_wireless_stick_lite.build.flash_size=4MB +heltec_wireless_stick_lite.build.flash_freq=80m +heltec_wireless_stick_lite.build.flash_mode=dio +heltec_wireless_stick_lite.build.boot=dio +heltec_wireless_stick_lite.build.partitions=default +heltec_wireless_stick_lite.build.psram= +heltec_wireless_stick_lite.build.defines=-D{build.band} -DMCU_ESP32_D0 -DHELTEC_BOARD=3 -DWIRELESS_STICK_LITE -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX127X -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_wireless_stick_lite.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wireless_stick_lite.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_stick_lite.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wireless_stick_lite.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_stick_lite.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wireless_stick_lite.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wireless_stick_lite.menu.UploadSpeed.921600=921600 +heltec_wireless_stick_lite.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_stick_lite.menu.UploadSpeed.115200=115200 +heltec_wireless_stick_lite.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_stick_lite.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_stick_lite.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_stick_lite.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_stick_lite.menu.UploadSpeed.230400=230400 +heltec_wireless_stick_lite.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_stick_lite.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_stick_lite.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_stick_lite.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_stick_lite.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_stick_lite.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_wireless_stick_lite.menu.DebugLevel.none=None +heltec_wireless_stick_lite.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_stick_lite.menu.DebugLevel.error=Error +heltec_wireless_stick_lite.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_stick_lite.menu.DebugLevel.warn=Warn +heltec_wireless_stick_lite.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_stick_lite.menu.DebugLevel.info=Info +heltec_wireless_stick_lite.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_stick_lite.menu.DebugLevel.debug=Debug +heltec_wireless_stick_lite.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_stick_lite.menu.DebugLevel.verbose=Verbose +heltec_wireless_stick_lite.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_stick_lite.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_stick_lite.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_stick_lite.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.0=None +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_stick_lite.menu.EraseFlash.none=Disabled +heltec_wireless_stick_lite.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_stick_lite.menu.EraseFlash.all=Enabled +heltec_wireless_stick_lite.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_wireless_bridge.name=Heltec Wireless Bridge + +heltec_wireless_bridge.bootloader.tool=esptool_py +heltec_wireless_bridge.bootloader.tool.default=esptool_py + +heltec_wireless_bridge.upload.tool=esptool_py +heltec_wireless_bridge.upload.tool.default=esptool_py +heltec_wireless_bridge.upload.tool.network=esp_ota + +heltec_wireless_bridge.upload.maximum_size=3342336 +heltec_wireless_bridge.upload.maximum_data_size=327680 +heltec_wireless_bridge.upload.wait_for_upload_port=true +heltec_wireless_bridge.upload.flags= +heltec_wireless_bridge.upload.extra_flags= + +heltec_wireless_bridge.serial.disableDTR=true +heltec_wireless_bridge.serial.disableRTS=true + +heltec_wireless_bridge.build.tarch=xtensa +heltec_wireless_bridge.build.bootloader_addr=0x1000 +heltec_wireless_bridge.build.target=esp32 +heltec_wireless_bridge.build.mcu=esp32 +heltec_wireless_bridge.build.core=esp32 +heltec_wireless_bridge.build.variant=heltec_wireless_bridge +heltec_wireless_bridge.build.board=HELTEC_WIRELESS_BRIDGE + +heltec_wireless_bridge.build.f_cpu=240000000L +heltec_wireless_bridge.build.flash_size=8MB +heltec_wireless_bridge.build.flash_freq=80m +heltec_wireless_bridge.build.flash_mode=dio +heltec_wireless_bridge.build.boot=dio +heltec_wireless_bridge.build.partitions=default_8MB +heltec_wireless_bridge.build.psram= +heltec_wireless_bridge.build.psram_type=qspi +heltec_wireless_bridge.build.memory_type={build.boot}_{build.psram_type} +heltec_wireless_bridge.build.defines=-D{build.band} {build.psram_val} -DMCU_ESP32_D0 -DWIRELESS_BRIDGE -DHELTEC_BOARD=4 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} {build.psram} + +heltec_wireless_bridge.menu.CPUFreq.240=240MHz (WiFi/BT) +heltec_wireless_bridge.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_wireless_bridge.menu.CPUFreq.160=160MHz (WiFi/BT) +heltec_wireless_bridge.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_wireless_bridge.menu.CPUFreq.80=80MHz (WiFi/BT) +heltec_wireless_bridge.menu.CPUFreq.80.build.f_cpu=80000000L + +heltec_wireless_bridge.menu.UploadSpeed.921600=921600 +heltec_wireless_bridge.menu.UploadSpeed.921600.upload.speed=921600 +heltec_wireless_bridge.menu.UploadSpeed.115200=115200 +heltec_wireless_bridge.menu.UploadSpeed.115200.upload.speed=115200 +heltec_wireless_bridge.menu.UploadSpeed.256000.windows=256000 +heltec_wireless_bridge.menu.UploadSpeed.256000.upload.speed=256000 +heltec_wireless_bridge.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_wireless_bridge.menu.UploadSpeed.230400=230400 +heltec_wireless_bridge.menu.UploadSpeed.230400.upload.speed=230400 +heltec_wireless_bridge.menu.UploadSpeed.460800.linux=460800 +heltec_wireless_bridge.menu.UploadSpeed.460800.macosx=460800 +heltec_wireless_bridge.menu.UploadSpeed.460800.upload.speed=460800 +heltec_wireless_bridge.menu.UploadSpeed.512000.windows=512000 +heltec_wireless_bridge.menu.UploadSpeed.512000.upload.speed=512000 + + +heltec_wireless_bridge.menu.PSRAM.disabled=Disabled +heltec_wireless_bridge.menu.PSRAM.disabled.build.psram_val= +heltec_wireless_bridge.menu.PSRAM.disabled.build.psram_type=qspi +heltec_wireless_bridge.menu.PSRAM.enabled=QSPI PSRAM +heltec_wireless_bridge.menu.PSRAM.enabled.build.psram_val=-DBOARD_HAS_PSRAM +heltec_wireless_bridge.menu.PSRAM.enabled.build.psram_type=qspi + +heltec_wireless_bridge.menu.DebugLevel.none=None +heltec_wireless_bridge.menu.DebugLevel.none.build.code_debug=0 +heltec_wireless_bridge.menu.DebugLevel.error=Error +heltec_wireless_bridge.menu.DebugLevel.error.build.code_debug=1 +heltec_wireless_bridge.menu.DebugLevel.warn=Warn +heltec_wireless_bridge.menu.DebugLevel.warn.build.code_debug=2 +heltec_wireless_bridge.menu.DebugLevel.info=Info +heltec_wireless_bridge.menu.DebugLevel.info.build.code_debug=3 +heltec_wireless_bridge.menu.DebugLevel.debug=Debug +heltec_wireless_bridge.menu.DebugLevel.debug.build.code_debug=4 +heltec_wireless_bridge.menu.DebugLevel.verbose=Verbose +heltec_wireless_bridge.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_wireless_bridge.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_wireless_bridge.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_wireless_bridge.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_wireless_bridge.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_wireless_bridge.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_wireless_bridge.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_wireless_bridge.menu.LORAWAN_REGION.3=REGION_US915 +heltec_wireless_bridge.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_wireless_bridge.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_wireless_bridge.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_wireless_bridge.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_wireless_bridge.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_wireless_bridge.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_wireless_bridge.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_wireless_bridge.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_wireless_bridge.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_wireless_bridge.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_wireless_bridge.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_wireless_bridge.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_wireless_bridge.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_wireless_bridge.menu.LoRaWanDebugLevel.0=None +heltec_wireless_bridge.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_wireless_bridge.menu.LoRaWanDebugLevel.1=Freq +heltec_wireless_bridge.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_wireless_bridge.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_wireless_bridge.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_wireless_bridge.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_wireless_bridge.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_wireless_bridge.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_wireless_bridge.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_wireless_bridge.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_wireless_bridge.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_wireless_bridge.menu.EraseFlash.none=Disabled +heltec_wireless_bridge.menu.EraseFlash.none.upload.erase_cmd= +heltec_wireless_bridge.menu.EraseFlash.all=Enabled +heltec_wireless_bridge.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################# + +heltec_ht_de01.name=Heltec E-Ink Driver + +heltec_ht_de01.bootloader.tool=esptool_py +heltec_ht_de01.bootloader.tool.default=esptool_py + +heltec_ht_de01.upload.tool=esptool_py +heltec_ht_de01.upload.tool.default=esptool_py +heltec_ht_de01.upload.tool.network=esp_ota + +heltec_ht_de01.upload.maximum_size=4026368 +heltec_ht_de01.upload.maximum_data_size=327680 +heltec_ht_de01.upload.flags= +heltec_ht_de01.upload.extra_flags= +heltec_ht_de01.upload.use_1200bps_touch=false +heltec_ht_de01.upload.wait_for_upload_port=false + +heltec_ht_de01.serial.disableDTR=false +heltec_ht_de01.serial.disableRTS=false + +heltec_ht_de01.build.tarch=xtensa +heltec_ht_de01.build.bootloader_addr=0x0 +heltec_ht_de01.build.target=esp32s3 +heltec_ht_de01.build.mcu=esp32s3 +heltec_ht_de01.build.core=esp32 +heltec_ht_de01.build.variant=heltec_ht_de01 +heltec_ht_de01.build.board=HT_DE01 + +heltec_ht_de01.build.usb_mode=1 +heltec_ht_de01.build.cdc_on_boot=0 +heltec_ht_de01.build.msc_on_boot=0 +heltec_ht_de01.build.dfu_on_boot=0 +heltec_ht_de01.build.f_cpu=240000000L +heltec_ht_de01.build.flash_size=8MB +heltec_ht_de01.build.flash_freq=80m +heltec_ht_de01.build.flash_mode=dio +heltec_ht_de01.build.boot=qio +heltec_ht_de01.build.boot_freq=80m +heltec_ht_de01.build.partitions=default_8MB +heltec_ht_de01.build.loop_core= +heltec_ht_de01.build.event_core= +heltec_ht_de01.build.psram_type=qspi +heltec_ht_de01.build.memory_type={build.boot}_{build.psram_type} + +heltec_ht_de01.menu.LoopCore.1=Core 1 +heltec_ht_de01.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_ht_de01.menu.LoopCore.0=Core 0 +heltec_ht_de01.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_ht_de01.menu.EventsCore.1=Core 1 +heltec_ht_de01.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_ht_de01.menu.EventsCore.0=Core 0 +heltec_ht_de01.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_ht_de01.menu.CPUFreq.240=240MHz (WiFi) +heltec_ht_de01.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_ht_de01.menu.CPUFreq.160=160MHz (WiFi) +heltec_ht_de01.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_ht_de01.menu.CPUFreq.80=80MHz (WiFi) +heltec_ht_de01.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_ht_de01.menu.CPUFreq.40=40MHz +heltec_ht_de01.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_ht_de01.menu.CPUFreq.20=20MHz +heltec_ht_de01.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_ht_de01.menu.CPUFreq.10=10MHz +heltec_ht_de01.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_ht_de01.menu.UploadSpeed.921600=921600 +heltec_ht_de01.menu.UploadSpeed.921600.upload.speed=921600 +heltec_ht_de01.menu.UploadSpeed.115200=115200 +heltec_ht_de01.menu.UploadSpeed.115200.upload.speed=115200 +heltec_ht_de01.menu.UploadSpeed.256000.windows=256000 +heltec_ht_de01.menu.UploadSpeed.256000.upload.speed=256000 +heltec_ht_de01.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_ht_de01.menu.UploadSpeed.230400=230400 +heltec_ht_de01.menu.UploadSpeed.230400.upload.speed=230400 +heltec_ht_de01.menu.UploadSpeed.460800.linux=460800 +heltec_ht_de01.menu.UploadSpeed.460800.macosx=460800 +heltec_ht_de01.menu.UploadSpeed.460800.upload.speed=460800 +heltec_ht_de01.menu.UploadSpeed.512000.windows=512000 +heltec_ht_de01.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_ht_de01.menu.DebugLevel.none=None +heltec_ht_de01.menu.DebugLevel.none.build.code_debug=0 +heltec_ht_de01.menu.DebugLevel.error=Error +heltec_ht_de01.menu.DebugLevel.error.build.code_debug=1 +heltec_ht_de01.menu.DebugLevel.warn=Warn +heltec_ht_de01.menu.DebugLevel.warn.build.code_debug=2 +heltec_ht_de01.menu.DebugLevel.info=Info +heltec_ht_de01.menu.DebugLevel.info.build.code_debug=3 +heltec_ht_de01.menu.DebugLevel.debug=Debug +heltec_ht_de01.menu.DebugLevel.debug.build.code_debug=4 +heltec_ht_de01.menu.DebugLevel.verbose=Verbose +heltec_ht_de01.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_ht_de01.menu.einksize.0=eink_150 +heltec_ht_de01.menu.einksize.0.build.einksize=150; +heltec_ht_de01.menu.einksize.1=eink_154 +heltec_ht_de01.menu.einksize.1.build.einksize=154; +heltec_ht_de01.menu.einksize.2=eink_213 +heltec_ht_de01.menu.einksize.2.build.einksize=213; +heltec_ht_de01.menu.einksize.3=eink_290 +heltec_ht_de01.menu.einksize.3.build.einksize=290; + +heltec_ht_de01.build.defines= -DEINK={build.einksize} -D{build.board} + +heltec_ht_de01.menu.EraseFlash.none=Disabled +heltec_ht_de01.menu.EraseFlash.none.upload.erase_cmd= +heltec_ht_de01.menu.EraseFlash.all=Enabled +heltec_ht_de01.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_vision_master_e290.name=Heltec Vision Master E290 + +heltec_vision_master_e290.bootloader.tool=esptool_py +heltec_vision_master_e290.bootloader.tool.default=esptool_py + +heltec_vision_master_e290.upload.tool=esptool_py +heltec_vision_master_e290.upload.tool.default=esptool_py +heltec_vision_master_e290.upload.tool.network=esp_ota + +heltec_vision_master_e290.upload.maximum_size=3342336 +heltec_vision_master_e290.upload.maximum_data_size=327680 +heltec_vision_master_e290.upload.flags= +heltec_vision_master_e290.upload.extra_flags= +heltec_vision_master_e290.upload.use_1200bps_touch=false +heltec_vision_master_e290.upload.wait_for_upload_port=false + +heltec_vision_master_e290.serial.disableDTR=false +heltec_vision_master_e290.serial.disableRTS=false + +heltec_vision_master_e290.build.tarch=xtensa +heltec_vision_master_e290.build.bootloader_addr=0x0 +heltec_vision_master_e290.build.target=esp32s3 +heltec_vision_master_e290.build.mcu=esp32s3 +heltec_vision_master_e290.build.core=esp32 +heltec_vision_master_e290.build.variant=heltec_vision_master_e290 +heltec_vision_master_e290.build.board=HELTEC_VISION_MASTER_E290 + +heltec_vision_master_e290.build.usb_mode=1 +heltec_vision_master_e290.build.cdc_on_boot=0 +heltec_vision_master_e290.build.msc_on_boot=0 +heltec_vision_master_e290.build.dfu_on_boot=0 +heltec_vision_master_e290.build.f_cpu=240000000L +heltec_vision_master_e290.build.flash_size=8MB +heltec_vision_master_e290.build.flash_freq=80m +heltec_vision_master_e290.build.flash_mode=dio +heltec_vision_master_e290.build.boot=qio +heltec_vision_master_e290.build.boot_freq=80m +heltec_vision_master_e290.build.partitions=default_8MB +heltec_vision_master_e290.build.loop_core= +heltec_vision_master_e290.build.event_core= +heltec_vision_master_e290.build.psram_type=qspi +heltec_vision_master_e290.build.memory_type={build.boot}_{build.psram_type} + +heltec_vision_master_e290.menu.LoopCore.1=Core 1 +heltec_vision_master_e290.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_vision_master_e290.menu.LoopCore.0=Core 0 +heltec_vision_master_e290.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_vision_master_e290.menu.EventsCore.1=Core 1 +heltec_vision_master_e290.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_vision_master_e290.menu.EventsCore.0=Core 0 +heltec_vision_master_e290.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_vision_master_e290.menu.USBMode.hwcdc=Hardware CDC and JTAG +heltec_vision_master_e290.menu.USBMode.hwcdc.build.usb_mode=1 +heltec_vision_master_e290.menu.USBMode.default=USB-OTG (TinyUSB) +heltec_vision_master_e290.menu.USBMode.default.build.usb_mode=0 + +heltec_vision_master_e290.menu.CDCOnBoot.default=Enabled +heltec_vision_master_e290.menu.CDCOnBoot.default.build.cdc_on_boot=1 +heltec_vision_master_e290.menu.CDCOnBoot.cdc=Disabled +heltec_vision_master_e290.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +heltec_vision_master_e290.menu.MSCOnBoot.default=Disabled +heltec_vision_master_e290.menu.MSCOnBoot.default.build.msc_on_boot=0 +heltec_vision_master_e290.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +heltec_vision_master_e290.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +heltec_vision_master_e290.menu.DFUOnBoot.default=Disabled +heltec_vision_master_e290.menu.DFUOnBoot.default.build.dfu_on_boot=0 +heltec_vision_master_e290.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +heltec_vision_master_e290.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +heltec_vision_master_e290.menu.UploadMode.default=UART0 / Hardware CDC +heltec_vision_master_e290.menu.UploadMode.default.upload.use_1200bps_touch=false +heltec_vision_master_e290.menu.UploadMode.default.upload.wait_for_upload_port=false +heltec_vision_master_e290.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +heltec_vision_master_e290.menu.UploadMode.cdc.upload.use_1200bps_touch=true +heltec_vision_master_e290.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +heltec_vision_master_e290.menu.CPUFreq.240=240MHz (WiFi) +heltec_vision_master_e290.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_vision_master_e290.menu.CPUFreq.160=160MHz (WiFi) +heltec_vision_master_e290.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_vision_master_e290.menu.CPUFreq.80=80MHz (WiFi) +heltec_vision_master_e290.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_vision_master_e290.menu.CPUFreq.40=40MHz +heltec_vision_master_e290.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_vision_master_e290.menu.CPUFreq.20=20MHz +heltec_vision_master_e290.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_vision_master_e290.menu.CPUFreq.10=10MHz +heltec_vision_master_e290.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_vision_master_e290.menu.UploadSpeed.921600=921600 +heltec_vision_master_e290.menu.UploadSpeed.921600.upload.speed=921600 +heltec_vision_master_e290.menu.UploadSpeed.115200=115200 +heltec_vision_master_e290.menu.UploadSpeed.115200.upload.speed=115200 +heltec_vision_master_e290.menu.UploadSpeed.256000.windows=256000 +heltec_vision_master_e290.menu.UploadSpeed.256000.upload.speed=256000 +heltec_vision_master_e290.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_vision_master_e290.menu.UploadSpeed.230400=230400 +heltec_vision_master_e290.menu.UploadSpeed.230400.upload.speed=230400 +heltec_vision_master_e290.menu.UploadSpeed.460800.linux=460800 +heltec_vision_master_e290.menu.UploadSpeed.460800.macosx=460800 +heltec_vision_master_e290.menu.UploadSpeed.460800.upload.speed=460800 +heltec_vision_master_e290.menu.UploadSpeed.512000.windows=512000 +heltec_vision_master_e290.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_vision_master_e290.menu.DebugLevel.none=None +heltec_vision_master_e290.menu.DebugLevel.none.build.code_debug=0 +heltec_vision_master_e290.menu.DebugLevel.error=Error +heltec_vision_master_e290.menu.DebugLevel.error.build.code_debug=1 +heltec_vision_master_e290.menu.DebugLevel.warn=Warn +heltec_vision_master_e290.menu.DebugLevel.warn.build.code_debug=2 +heltec_vision_master_e290.menu.DebugLevel.info=Info +heltec_vision_master_e290.menu.DebugLevel.info.build.code_debug=3 +heltec_vision_master_e290.menu.DebugLevel.debug=Debug +heltec_vision_master_e290.menu.DebugLevel.debug.build.code_debug=4 +heltec_vision_master_e290.menu.DebugLevel.verbose=Verbose +heltec_vision_master_e290.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_vision_master_e290.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_vision_master_e290.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_vision_master_e290.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_vision_master_e290.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_vision_master_e290.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_vision_master_e290.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_vision_master_e290.menu.LORAWAN_REGION.3=REGION_US915 +heltec_vision_master_e290.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_vision_master_e290.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_vision_master_e290.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_vision_master_e290.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_vision_master_e290.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_vision_master_e290.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_vision_master_e290.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_vision_master_e290.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_vision_master_e290.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_vision_master_e290.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_vision_master_e290.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_vision_master_e290.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_vision_master_e290.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_vision_master_e290.menu.LoRaWanDebugLevel.0=None +heltec_vision_master_e290.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_vision_master_e290.menu.LoRaWanDebugLevel.1=Freq +heltec_vision_master_e290.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_vision_master_e290.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_vision_master_e290.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_vision_master_e290.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_vision_master_e290.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_vision_master_e290.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_vision_master_e290.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_vision_master_e290.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_vision_master_e290.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_vision_master_e290.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_vision_master_e290.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_vision_master_e290.menu.SLOW_CLK_TPYE.1=External 32K +heltec_vision_master_e290.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_vision_master_e290.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=37 -DHELTEC_VISION_MASTER_E290 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_vision_master_e290.menu.EraseFlash.none=Disabled +heltec_vision_master_e290.menu.EraseFlash.none.upload.erase_cmd= +heltec_vision_master_e290.menu.EraseFlash.all=Enabled +heltec_vision_master_e290.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_vision_master_t190.name=Heltec Vision Master T190 + +heltec_vision_master_t190.bootloader.tool=esptool_py +heltec_vision_master_t190.bootloader.tool.default=esptool_py + +heltec_vision_master_t190.upload.tool=esptool_py +heltec_vision_master_t190.upload.tool.default=esptool_py +heltec_vision_master_t190.upload.tool.network=esp_ota + +heltec_vision_master_t190.upload.maximum_size=3342336 +heltec_vision_master_t190.upload.maximum_data_size=327680 +heltec_vision_master_t190.upload.flags= +heltec_vision_master_t190.upload.extra_flags= +heltec_vision_master_t190.upload.use_1200bps_touch=false +heltec_vision_master_t190.upload.wait_for_upload_port=false + +heltec_vision_master_t190.serial.disableDTR=false +heltec_vision_master_t190.serial.disableRTS=false + +heltec_vision_master_t190.build.tarch=xtensa +heltec_vision_master_t190.build.bootloader_addr=0x0 +heltec_vision_master_t190.build.target=esp32s3 +heltec_vision_master_t190.build.mcu=esp32s3 +heltec_vision_master_t190.build.core=esp32 +heltec_vision_master_t190.build.variant=heltec_vision_master_t190 +heltec_vision_master_t190.build.board=HELTEC_VISION_MASTER_T190 + +heltec_vision_master_t190.build.usb_mode=1 +heltec_vision_master_t190.build.cdc_on_boot=0 +heltec_vision_master_t190.build.msc_on_boot=0 +heltec_vision_master_t190.build.dfu_on_boot=0 +heltec_vision_master_t190.build.f_cpu=240000000L +heltec_vision_master_t190.build.flash_size=8MB +heltec_vision_master_t190.build.flash_freq=80m +heltec_vision_master_t190.build.flash_mode=dio +heltec_vision_master_t190.build.boot=qio +heltec_vision_master_t190.build.boot_freq=80m +heltec_vision_master_t190.build.partitions=default_8MB +heltec_vision_master_t190.build.loop_core= +heltec_vision_master_t190.build.event_core= +heltec_vision_master_t190.build.psram_type=qspi +heltec_vision_master_t190.build.memory_type={build.boot}_{build.psram_type} + +heltec_vision_master_t190.menu.LoopCore.1=Core 1 +heltec_vision_master_t190.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_vision_master_t190.menu.LoopCore.0=Core 0 +heltec_vision_master_t190.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_vision_master_t190.menu.EventsCore.1=Core 1 +heltec_vision_master_t190.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_vision_master_t190.menu.EventsCore.0=Core 0 +heltec_vision_master_t190.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_vision_master_t190.menu.USBMode.hwcdc=Hardware CDC and JTAG +heltec_vision_master_t190.menu.USBMode.hwcdc.build.usb_mode=1 +heltec_vision_master_t190.menu.USBMode.default=USB-OTG (TinyUSB) +heltec_vision_master_t190.menu.USBMode.default.build.usb_mode=0 + +heltec_vision_master_t190.menu.CDCOnBoot.default=Enabled +heltec_vision_master_t190.menu.CDCOnBoot.default.build.cdc_on_boot=1 +heltec_vision_master_t190.menu.CDCOnBoot.cdc=Disabled +heltec_vision_master_t190.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +heltec_vision_master_t190.menu.MSCOnBoot.default=Disabled +heltec_vision_master_t190.menu.MSCOnBoot.default.build.msc_on_boot=0 +heltec_vision_master_t190.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +heltec_vision_master_t190.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +heltec_vision_master_t190.menu.DFUOnBoot.default=Disabled +heltec_vision_master_t190.menu.DFUOnBoot.default.build.dfu_on_boot=0 +heltec_vision_master_t190.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +heltec_vision_master_t190.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +heltec_vision_master_t190.menu.UploadMode.default=UART0 / Hardware CDC +heltec_vision_master_t190.menu.UploadMode.default.upload.use_1200bps_touch=false +heltec_vision_master_t190.menu.UploadMode.default.upload.wait_for_upload_port=false +heltec_vision_master_t190.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +heltec_vision_master_t190.menu.UploadMode.cdc.upload.use_1200bps_touch=true +heltec_vision_master_t190.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +heltec_vision_master_t190.menu.CPUFreq.240=240MHz (WiFi) +heltec_vision_master_t190.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_vision_master_t190.menu.CPUFreq.160=160MHz (WiFi) +heltec_vision_master_t190.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_vision_master_t190.menu.CPUFreq.80=80MHz (WiFi) +heltec_vision_master_t190.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_vision_master_t190.menu.CPUFreq.40=40MHz +heltec_vision_master_t190.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_vision_master_t190.menu.CPUFreq.20=20MHz +heltec_vision_master_t190.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_vision_master_t190.menu.CPUFreq.10=10MHz +heltec_vision_master_t190.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_vision_master_t190.menu.UploadSpeed.921600=921600 +heltec_vision_master_t190.menu.UploadSpeed.921600.upload.speed=921600 +heltec_vision_master_t190.menu.UploadSpeed.115200=115200 +heltec_vision_master_t190.menu.UploadSpeed.115200.upload.speed=115200 +heltec_vision_master_t190.menu.UploadSpeed.256000.windows=256000 +heltec_vision_master_t190.menu.UploadSpeed.256000.upload.speed=256000 +heltec_vision_master_t190.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_vision_master_t190.menu.UploadSpeed.230400=230400 +heltec_vision_master_t190.menu.UploadSpeed.230400.upload.speed=230400 +heltec_vision_master_t190.menu.UploadSpeed.460800.linux=460800 +heltec_vision_master_t190.menu.UploadSpeed.460800.macosx=460800 +heltec_vision_master_t190.menu.UploadSpeed.460800.upload.speed=460800 +heltec_vision_master_t190.menu.UploadSpeed.512000.windows=512000 +heltec_vision_master_t190.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_vision_master_t190.menu.DebugLevel.none=None +heltec_vision_master_t190.menu.DebugLevel.none.build.code_debug=0 +heltec_vision_master_t190.menu.DebugLevel.error=Error +heltec_vision_master_t190.menu.DebugLevel.error.build.code_debug=1 +heltec_vision_master_t190.menu.DebugLevel.warn=Warn +heltec_vision_master_t190.menu.DebugLevel.warn.build.code_debug=2 +heltec_vision_master_t190.menu.DebugLevel.info=Info +heltec_vision_master_t190.menu.DebugLevel.info.build.code_debug=3 +heltec_vision_master_t190.menu.DebugLevel.debug=Debug +heltec_vision_master_t190.menu.DebugLevel.debug.build.code_debug=4 +heltec_vision_master_t190.menu.DebugLevel.verbose=Verbose +heltec_vision_master_t190.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_vision_master_t190.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_vision_master_t190.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_vision_master_t190.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_vision_master_t190.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_vision_master_t190.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_vision_master_t190.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_vision_master_t190.menu.LORAWAN_REGION.3=REGION_US915 +heltec_vision_master_t190.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_vision_master_t190.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_vision_master_t190.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_vision_master_t190.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_vision_master_t190.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_vision_master_t190.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_vision_master_t190.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_vision_master_t190.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_vision_master_t190.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_vision_master_t190.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_vision_master_t190.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_vision_master_t190.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_vision_master_t190.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_vision_master_t190.menu.LoRaWanDebugLevel.0=None +heltec_vision_master_t190.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_vision_master_t190.menu.LoRaWanDebugLevel.1=Freq +heltec_vision_master_t190.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_vision_master_t190.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_vision_master_t190.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_vision_master_t190.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_vision_master_t190.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_vision_master_t190.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_vision_master_t190.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_vision_master_t190.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_vision_master_t190.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_vision_master_t190.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_vision_master_t190.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_vision_master_t190.menu.SLOW_CLK_TPYE.1=External 32K +heltec_vision_master_t190.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_vision_master_t190.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=38 -DHELTEC_VISION_MASTER_T190 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_vision_master_t190.menu.EraseFlash.none=Disabled +heltec_vision_master_t190.menu.EraseFlash.none.upload.erase_cmd= +heltec_vision_master_t190.menu.EraseFlash.all=Enabled +heltec_vision_master_t190.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +heltec_vision_master_e_213.name=Heltec Vision Master E213 + +heltec_vision_master_e_213.bootloader.tool=esptool_py +heltec_vision_master_e_213.bootloader.tool.default=esptool_py + +heltec_vision_master_e_213.upload.tool=esptool_py +heltec_vision_master_e_213.upload.tool.default=esptool_py +heltec_vision_master_e_213.upload.tool.network=esp_ota + +heltec_vision_master_e_213.upload.maximum_size=3342336 +heltec_vision_master_e_213.upload.maximum_data_size=327680 +heltec_vision_master_e_213.upload.flags= +heltec_vision_master_e_213.upload.extra_flags= +heltec_vision_master_e_213.upload.use_1200bps_touch=false +heltec_vision_master_e_213.upload.wait_for_upload_port=false + +heltec_vision_master_e_213.serial.disableDTR=false +heltec_vision_master_e_213.serial.disableRTS=false + +heltec_vision_master_e_213.build.tarch=xtensa +heltec_vision_master_e_213.build.bootloader_addr=0x0 +heltec_vision_master_e_213.build.target=esp32s3 +heltec_vision_master_e_213.build.mcu=esp32s3 +heltec_vision_master_e_213.build.core=esp32 +heltec_vision_master_e_213.build.variant=heltec_vision_master_e_213 +heltec_vision_master_e_213.build.board=HELTEC_VISION_MASTER_E_213 + +heltec_vision_master_e_213.build.usb_mode=1 +heltec_vision_master_e_213.build.cdc_on_boot=0 +heltec_vision_master_e_213.build.msc_on_boot=0 +heltec_vision_master_e_213.build.dfu_on_boot=0 +heltec_vision_master_e_213.build.f_cpu=240000000L +heltec_vision_master_e_213.build.flash_size=8MB +heltec_vision_master_e_213.build.flash_freq=80m +heltec_vision_master_e_213.build.flash_mode=dio +heltec_vision_master_e_213.build.boot=qio +heltec_vision_master_e_213.build.boot_freq=80m +heltec_vision_master_e_213.build.partitions=default_8MB +heltec_vision_master_e_213.build.loop_core= +heltec_vision_master_e_213.build.event_core= +heltec_vision_master_e_213.build.psram_type=qspi +heltec_vision_master_e_213.build.memory_type={build.boot}_{build.psram_type} + +heltec_vision_master_e_213.menu.LoopCore.1=Core 1 +heltec_vision_master_e_213.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +heltec_vision_master_e_213.menu.LoopCore.0=Core 0 +heltec_vision_master_e_213.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +heltec_vision_master_e_213.menu.EventsCore.1=Core 1 +heltec_vision_master_e_213.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +heltec_vision_master_e_213.menu.EventsCore.0=Core 0 +heltec_vision_master_e_213.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +heltec_vision_master_e_213.menu.USBMode.hwcdc=Hardware CDC and JTAG +heltec_vision_master_e_213.menu.USBMode.hwcdc.build.usb_mode=1 +heltec_vision_master_e_213.menu.USBMode.default=USB-OTG (TinyUSB) +heltec_vision_master_e_213.menu.USBMode.default.build.usb_mode=0 + +heltec_vision_master_e_213.menu.CDCOnBoot.default=Enabled +heltec_vision_master_e_213.menu.CDCOnBoot.default.build.cdc_on_boot=1 +heltec_vision_master_e_213.menu.CDCOnBoot.cdc=Disabled +heltec_vision_master_e_213.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +heltec_vision_master_e_213.menu.MSCOnBoot.default=Disabled +heltec_vision_master_e_213.menu.MSCOnBoot.default.build.msc_on_boot=0 +heltec_vision_master_e_213.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +heltec_vision_master_e_213.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +heltec_vision_master_e_213.menu.DFUOnBoot.default=Disabled +heltec_vision_master_e_213.menu.DFUOnBoot.default.build.dfu_on_boot=0 +heltec_vision_master_e_213.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +heltec_vision_master_e_213.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +heltec_vision_master_e_213.menu.UploadMode.default=UART0 / Hardware CDC +heltec_vision_master_e_213.menu.UploadMode.default.upload.use_1200bps_touch=false +heltec_vision_master_e_213.menu.UploadMode.default.upload.wait_for_upload_port=false +heltec_vision_master_e_213.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +heltec_vision_master_e_213.menu.UploadMode.cdc.upload.use_1200bps_touch=true +heltec_vision_master_e_213.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +heltec_vision_master_e_213.menu.CPUFreq.240=240MHz (WiFi) +heltec_vision_master_e_213.menu.CPUFreq.240.build.f_cpu=240000000L +heltec_vision_master_e_213.menu.CPUFreq.160=160MHz (WiFi) +heltec_vision_master_e_213.menu.CPUFreq.160.build.f_cpu=160000000L +heltec_vision_master_e_213.menu.CPUFreq.80=80MHz (WiFi) +heltec_vision_master_e_213.menu.CPUFreq.80.build.f_cpu=80000000L +heltec_vision_master_e_213.menu.CPUFreq.40=40MHz +heltec_vision_master_e_213.menu.CPUFreq.40.build.f_cpu=40000000L +heltec_vision_master_e_213.menu.CPUFreq.20=20MHz +heltec_vision_master_e_213.menu.CPUFreq.20.build.f_cpu=20000000L +heltec_vision_master_e_213.menu.CPUFreq.10=10MHz +heltec_vision_master_e_213.menu.CPUFreq.10.build.f_cpu=10000000L + +heltec_vision_master_e_213.menu.UploadSpeed.921600=921600 +heltec_vision_master_e_213.menu.UploadSpeed.921600.upload.speed=921600 +heltec_vision_master_e_213.menu.UploadSpeed.115200=115200 +heltec_vision_master_e_213.menu.UploadSpeed.115200.upload.speed=115200 +heltec_vision_master_e_213.menu.UploadSpeed.256000.windows=256000 +heltec_vision_master_e_213.menu.UploadSpeed.256000.upload.speed=256000 +heltec_vision_master_e_213.menu.UploadSpeed.230400.windows.upload.speed=256000 +heltec_vision_master_e_213.menu.UploadSpeed.230400=230400 +heltec_vision_master_e_213.menu.UploadSpeed.230400.upload.speed=230400 +heltec_vision_master_e_213.menu.UploadSpeed.460800.linux=460800 +heltec_vision_master_e_213.menu.UploadSpeed.460800.macosx=460800 +heltec_vision_master_e_213.menu.UploadSpeed.460800.upload.speed=460800 +heltec_vision_master_e_213.menu.UploadSpeed.512000.windows=512000 +heltec_vision_master_e_213.menu.UploadSpeed.512000.upload.speed=512000 + +heltec_vision_master_e_213.menu.DebugLevel.none=None +heltec_vision_master_e_213.menu.DebugLevel.none.build.code_debug=0 +heltec_vision_master_e_213.menu.DebugLevel.error=Error +heltec_vision_master_e_213.menu.DebugLevel.error.build.code_debug=1 +heltec_vision_master_e_213.menu.DebugLevel.warn=Warn +heltec_vision_master_e_213.menu.DebugLevel.warn.build.code_debug=2 +heltec_vision_master_e_213.menu.DebugLevel.info=Info +heltec_vision_master_e_213.menu.DebugLevel.info.build.code_debug=3 +heltec_vision_master_e_213.menu.DebugLevel.debug=Debug +heltec_vision_master_e_213.menu.DebugLevel.debug.build.code_debug=4 +heltec_vision_master_e_213.menu.DebugLevel.verbose=Verbose +heltec_vision_master_e_213.menu.DebugLevel.verbose.build.code_debug=5 + +heltec_vision_master_e_213.menu.LORAWAN_REGION.0=REGION_EU868 +heltec_vision_master_e_213.menu.LORAWAN_REGION.0.build.band=REGION_EU868 +heltec_vision_master_e_213.menu.LORAWAN_REGION.1=REGION_EU433 +heltec_vision_master_e_213.menu.LORAWAN_REGION.1.build.band=REGION_EU433 +heltec_vision_master_e_213.menu.LORAWAN_REGION.2=REGION_CN470 +heltec_vision_master_e_213.menu.LORAWAN_REGION.2.build.band=REGION_CN470 +heltec_vision_master_e_213.menu.LORAWAN_REGION.3=REGION_US915 +heltec_vision_master_e_213.menu.LORAWAN_REGION.3.build.band=REGION_US915 +heltec_vision_master_e_213.menu.LORAWAN_REGION.4=REGION_AU915 +heltec_vision_master_e_213.menu.LORAWAN_REGION.4.build.band=REGION_AU915 +heltec_vision_master_e_213.menu.LORAWAN_REGION.5=REGION_CN779 +heltec_vision_master_e_213.menu.LORAWAN_REGION.5.build.band=REGION_CN779 +heltec_vision_master_e_213.menu.LORAWAN_REGION.6=REGION_AS923 +heltec_vision_master_e_213.menu.LORAWAN_REGION.6.build.band=REGION_AS923 +heltec_vision_master_e_213.menu.LORAWAN_REGION.7=REGION_KR920 +heltec_vision_master_e_213.menu.LORAWAN_REGION.7.build.band=REGION_KR920 +heltec_vision_master_e_213.menu.LORAWAN_REGION.8=REGION_IN865 +heltec_vision_master_e_213.menu.LORAWAN_REGION.8.build.band=REGION_IN865 +heltec_vision_master_e_213.menu.LORAWAN_REGION.9=REGION_US915_HYBRID +heltec_vision_master_e_213.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID + +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.0=None +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0 +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.1=Freq +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1 +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.2=Freq && DIO +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2 +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.3=Freq && DIO && PW +heltec_vision_master_e_213.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3 + +heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.0=CUSTOM +heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0 +heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.1=Generate By ChipID +heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1 + +heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default) +heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8 +heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L) +heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16 + +heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.0=Internal (default) +heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0 +heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.1=External 32K +heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1 + +heltec_vision_master_e_213.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=36 -DHELTEC_VISION_MASTER_E_213 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} + +heltec_vision_master_e_213.menu.EraseFlash.none=Disabled +heltec_vision_master_e_213.menu.EraseFlash.none.upload.erase_cmd= +heltec_vision_master_e_213.menu.EraseFlash.all=Enabled +heltec_vision_master_e_213.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +espectro32.name=ESPectro32 + +espectro32.bootloader.tool=esptool_py +espectro32.bootloader.tool.default=esptool_py + +espectro32.upload.tool=esptool_py +espectro32.upload.tool.default=esptool_py +espectro32.upload.tool.network=esp_ota + +espectro32.upload.maximum_size=1310720 +espectro32.upload.maximum_data_size=327680 +espectro32.upload.flags= +espectro32.upload.extra_flags= + +espectro32.serial.disableDTR=true +espectro32.serial.disableRTS=true + +espectro32.build.tarch=xtensa +espectro32.build.bootloader_addr=0x1000 +espectro32.build.target=esp32 +espectro32.build.mcu=esp32 +espectro32.build.core=esp32 +espectro32.build.variant=espectro32 +espectro32.build.board=ESPECTRO32 + +espectro32.build.f_cpu=240000000L +espectro32.build.flash_size=4MB +espectro32.build.flash_mode=dio +espectro32.build.boot=dio +espectro32.build.partitions=default +espectro32.build.defines= + +espectro32.menu.FlashMode.qio=QIO +espectro32.menu.FlashMode.qio.build.flash_mode=dio +espectro32.menu.FlashMode.qio.build.boot=qio +espectro32.menu.FlashMode.dio=DIO +espectro32.menu.FlashMode.dio.build.flash_mode=dio +espectro32.menu.FlashMode.dio.build.boot=dio + +espectro32.menu.FlashFreq.80=80MHz +espectro32.menu.FlashFreq.80.build.flash_freq=80m +espectro32.menu.FlashFreq.40=40MHz +espectro32.menu.FlashFreq.40.build.flash_freq=40m + +espectro32.menu.FlashSize.4M=4MB (32Mb) +espectro32.menu.FlashSize.4M.build.flash_size=4MB +espectro32.menu.FlashSize.2M=2MB (16Mb) +espectro32.menu.FlashSize.2M.build.flash_size=2MB + +espectro32.menu.UploadSpeed.921600=921600 +espectro32.menu.UploadSpeed.921600.upload.speed=921600 +espectro32.menu.UploadSpeed.115200=115200 +espectro32.menu.UploadSpeed.115200.upload.speed=115200 +espectro32.menu.UploadSpeed.256000.windows=256000 +espectro32.menu.UploadSpeed.256000.upload.speed=256000 +espectro32.menu.UploadSpeed.230400.windows.upload.speed=256000 +espectro32.menu.UploadSpeed.230400=230400 +espectro32.menu.UploadSpeed.230400.upload.speed=230400 +espectro32.menu.UploadSpeed.460800.linux=460800 +espectro32.menu.UploadSpeed.460800.macosx=460800 +espectro32.menu.UploadSpeed.460800.upload.speed=460800 +espectro32.menu.UploadSpeed.512000.windows=512000 +espectro32.menu.UploadSpeed.512000.upload.speed=512000 + +espectro32.menu.DebugLevel.none=None +espectro32.menu.DebugLevel.none.build.code_debug=0 +espectro32.menu.DebugLevel.error=Error +espectro32.menu.DebugLevel.error.build.code_debug=1 +espectro32.menu.DebugLevel.warn=Warn +espectro32.menu.DebugLevel.warn.build.code_debug=2 +espectro32.menu.DebugLevel.info=Info +espectro32.menu.DebugLevel.info.build.code_debug=3 +espectro32.menu.DebugLevel.debug=Debug +espectro32.menu.DebugLevel.debug.build.code_debug=4 +espectro32.menu.DebugLevel.verbose=Verbose +espectro32.menu.DebugLevel.verbose.build.code_debug=5 + +espectro32.menu.EraseFlash.none=Disabled +espectro32.menu.EraseFlash.none.upload.erase_cmd= +espectro32.menu.EraseFlash.all=Enabled +espectro32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +CoreESP32.name=Microduino-CoreESP32 + +CoreESP32.bootloader.tool=esptool_py +CoreESP32.bootloader.tool.default=esptool_py + +CoreESP32.upload.tool=esptool_py +CoreESP32.upload.tool.default=esptool_py +CoreESP32.upload.tool.network=esp_ota + +CoreESP32.upload.maximum_size=1310720 +CoreESP32.upload.maximum_data_size=327680 +CoreESP32.upload.flags= +CoreESP32.upload.extra_flags= + +CoreESP32.serial.disableDTR=false +CoreESP32.serial.disableRTS=false + +CoreESP32.build.tarch=xtensa +CoreESP32.build.bootloader_addr=0x1000 +CoreESP32.build.target=esp32 +CoreESP32.build.mcu=esp32 +CoreESP32.build.core=esp32 +CoreESP32.build.variant=Microduino-esp32 +CoreESP32.build.board=CoreESP32 + +CoreESP32.build.f_cpu=240000000L +CoreESP32.build.flash_mode=dio +CoreESP32.build.flash_size=4MB +CoreESP32.build.boot=dio +CoreESP32.build.partitions=default +CoreESP32.build.defines= + +CoreESP32.menu.PSRAM.disabled=Disabled +CoreESP32.menu.PSRAM.disabled.build.defines= +CoreESP32.menu.PSRAM.disabled.build.extra_libs= +CoreESP32.menu.PSRAM.enabled=Enabled +CoreESP32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +CoreESP32.menu.PSRAM.enabled.build.extra_libs= + +CoreESP32.menu.PartitionScheme.default=Default +CoreESP32.menu.PartitionScheme.default.build.partitions=default +CoreESP32.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +CoreESP32.menu.PartitionScheme.minimal.build.partitions=minimal +CoreESP32.menu.PartitionScheme.no_ota=No OTA (Large APP) +CoreESP32.menu.PartitionScheme.no_ota.build.partitions=no_ota +CoreESP32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +CoreESP32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +CoreESP32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +CoreESP32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +CoreESP32.menu.PartitionScheme.fatflash=16M Fat +CoreESP32.menu.PartitionScheme.fatflash.build.partitions=ffat + +CoreESP32.menu.FlashFreq.80=80MHz +CoreESP32.menu.FlashFreq.80.build.flash_freq=80m +CoreESP32.menu.FlashFreq.40=40MHz +CoreESP32.menu.FlashFreq.40.build.flash_freq=40m + +CoreESP32.menu.UploadSpeed.921600=921600 +CoreESP32.menu.UploadSpeed.921600.upload.speed=921600 +CoreESP32.menu.UploadSpeed.115200=115200 +CoreESP32.menu.UploadSpeed.115200.upload.speed=115200 +CoreESP32.menu.UploadSpeed.256000.windows=256000 +CoreESP32.menu.UploadSpeed.256000.upload.speed=256000 +CoreESP32.menu.UploadSpeed.230400.windows.upload.speed=256000 +CoreESP32.menu.UploadSpeed.230400=230400 +CoreESP32.menu.UploadSpeed.230400.upload.speed=230400 +CoreESP32.menu.UploadSpeed.460800.linux=460800 +CoreESP32.menu.UploadSpeed.460800.macosx=460800 +CoreESP32.menu.UploadSpeed.460800.upload.speed=460800 +CoreESP32.menu.UploadSpeed.512000.windows=512000 +CoreESP32.menu.UploadSpeed.512000.upload.speed=512000 + +CoreESP32.menu.DebugLevel.none=None +CoreESP32.menu.DebugLevel.none.build.code_debug=0 +CoreESP32.menu.DebugLevel.error=Error +CoreESP32.menu.DebugLevel.error.build.code_debug=1 +CoreESP32.menu.DebugLevel.warn=Warn +CoreESP32.menu.DebugLevel.warn.build.code_debug=2 +CoreESP32.menu.DebugLevel.info=Info +CoreESP32.menu.DebugLevel.info.build.code_debug=3 +CoreESP32.menu.DebugLevel.debug=Debug +CoreESP32.menu.DebugLevel.debug.build.code_debug=4 +CoreESP32.menu.DebugLevel.verbose=Verbose +CoreESP32.menu.DebugLevel.verbose.build.code_debug=5 + +CoreESP32.menu.EraseFlash.none=Disabled +CoreESP32.menu.EraseFlash.none.upload.erase_cmd= +CoreESP32.menu.EraseFlash.all=Enabled +CoreESP32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +alksesp32.name=ALKS ESP32 + +alksesp32.bootloader.tool=esptool_py +alksesp32.bootloader.tool.default=esptool_py + +alksesp32.upload.tool=esptool_py +alksesp32.upload.tool.default=esptool_py +alksesp32.upload.tool.network=esp_ota + +alksesp32.upload.maximum_size=1310720 +alksesp32.upload.maximum_data_size=327680 +alksesp32.upload.flags= +alksesp32.upload.extra_flags= + +alksesp32.serial.disableDTR=true +alksesp32.serial.disableRTS=true + +alksesp32.build.tarch=xtensa +alksesp32.build.bootloader_addr=0x1000 +alksesp32.build.target=esp32 +alksesp32.build.mcu=esp32 +alksesp32.build.core=esp32 +alksesp32.build.variant=alksesp32 +alksesp32.build.board=ALKS + +alksesp32.build.f_cpu=240000000L +alksesp32.build.flash_size=4MB +alksesp32.build.flash_freq=40m +alksesp32.build.flash_mode=dio +alksesp32.build.boot=dio +alksesp32.build.partitions=default +alksesp32.build.defines= + +alksesp32.menu.PSRAM.disabled=Disabled +alksesp32.menu.PSRAM.disabled.build.defines= +alksesp32.menu.PSRAM.disabled.build.extra_libs= +alksesp32.menu.PSRAM.enabled=Enabled +alksesp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +alksesp32.menu.PSRAM.enabled.build.extra_libs= + +alksesp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +alksesp32.menu.PartitionScheme.default.build.partitions=default +alksesp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +alksesp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +alksesp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +alksesp32.menu.PartitionScheme.minimal.build.partitions=minimal +alksesp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +alksesp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +alksesp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +alksesp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +alksesp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +alksesp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +alksesp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +alksesp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +alksesp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +alksesp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +alksesp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +alksesp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +alksesp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +alksesp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +alksesp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +alksesp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +alksesp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +alksesp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +alksesp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +alksesp32.menu.PartitionScheme.fatflash.build.partitions=ffat + +alksesp32.menu.CPUFreq.240=240MHz (WiFi/BT) +alksesp32.menu.CPUFreq.240.build.f_cpu=240000000L +alksesp32.menu.CPUFreq.160=160MHz (WiFi/BT) +alksesp32.menu.CPUFreq.160.build.f_cpu=160000000L +alksesp32.menu.CPUFreq.80=80MHz (WiFi/BT) +alksesp32.menu.CPUFreq.80.build.f_cpu=80000000L +alksesp32.menu.CPUFreq.40=40MHz (40MHz XTAL) +alksesp32.menu.CPUFreq.40.build.f_cpu=40000000L +alksesp32.menu.CPUFreq.26=26MHz (26MHz XTAL) +alksesp32.menu.CPUFreq.26.build.f_cpu=26000000L +alksesp32.menu.CPUFreq.20=20MHz (40MHz XTAL) +alksesp32.menu.CPUFreq.20.build.f_cpu=20000000L +alksesp32.menu.CPUFreq.13=13MHz (26MHz XTAL) +alksesp32.menu.CPUFreq.13.build.f_cpu=13000000L +alksesp32.menu.CPUFreq.10=10MHz (40MHz XTAL) +alksesp32.menu.CPUFreq.10.build.f_cpu=10000000L + +alksesp32.menu.FlashMode.qio=QIO +alksesp32.menu.FlashMode.qio.build.flash_mode=dio +alksesp32.menu.FlashMode.qio.build.boot=qio +alksesp32.menu.FlashMode.dio=DIO +alksesp32.menu.FlashMode.dio.build.flash_mode=dio +alksesp32.menu.FlashMode.dio.build.boot=dio + +alksesp32.menu.FlashFreq.80=80MHz +alksesp32.menu.FlashFreq.80.build.flash_freq=80m +alksesp32.menu.FlashFreq.40=40MHz +alksesp32.menu.FlashFreq.40.build.flash_freq=40m + +alksesp32.menu.FlashSize.4M=4MB (32Mb) +alksesp32.menu.FlashSize.4M.build.flash_size=4MB +alksesp32.menu.FlashSize.2M=2MB (16Mb) +alksesp32.menu.FlashSize.2M.build.flash_size=2MB +alksesp32.menu.FlashSize.16M=16MB (128Mb) +alksesp32.menu.FlashSize.16M.build.flash_size=16MB + +alksesp32.menu.UploadSpeed.921600=921600 +alksesp32.menu.UploadSpeed.921600.upload.speed=921600 +alksesp32.menu.UploadSpeed.115200=115200 +alksesp32.menu.UploadSpeed.115200.upload.speed=115200 +alksesp32.menu.UploadSpeed.256000.windows=256000 +alksesp32.menu.UploadSpeed.256000.upload.speed=256000 +alksesp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +alksesp32.menu.UploadSpeed.230400=230400 +alksesp32.menu.UploadSpeed.230400.upload.speed=230400 +alksesp32.menu.UploadSpeed.460800.linux=460800 +alksesp32.menu.UploadSpeed.460800.macosx=460800 +alksesp32.menu.UploadSpeed.460800.upload.speed=460800 +alksesp32.menu.UploadSpeed.512000.windows=512000 +alksesp32.menu.UploadSpeed.512000.upload.speed=512000 + +alksesp32.menu.DebugLevel.none=None +alksesp32.menu.DebugLevel.none.build.code_debug=0 +alksesp32.menu.DebugLevel.error=Error +alksesp32.menu.DebugLevel.error.build.code_debug=1 +alksesp32.menu.DebugLevel.warn=Warn +alksesp32.menu.DebugLevel.warn.build.code_debug=2 +alksesp32.menu.DebugLevel.info=Info +alksesp32.menu.DebugLevel.info.build.code_debug=3 +alksesp32.menu.DebugLevel.debug=Debug +alksesp32.menu.DebugLevel.debug.build.code_debug=4 +alksesp32.menu.DebugLevel.verbose=Verbose +alksesp32.menu.DebugLevel.verbose.build.code_debug=5 + +alksesp32.menu.EraseFlash.none=Disabled +alksesp32.menu.EraseFlash.none.upload.erase_cmd= +alksesp32.menu.EraseFlash.all=Enabled +alksesp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wipy3.name=WiPy 3.0 + +wipy3.bootloader.tool=esptool_py +wipy3.bootloader.tool.default=esptool_py + +wipy3.upload.tool=esptool_py +wipy3.upload.tool.default=esptool_py +wipy3.upload.tool.network=esp_ota + +wipy3.upload.maximum_size=1310720 +wipy3.upload.maximum_data_size=294912 +wipy3.upload.flags= +wipy3.upload.extra_flags= + +wipy3.serial.disableDTR=true +wipy3.serial.disableRTS=true + +wipy3.build.tarch=xtensa +wipy3.build.bootloader_addr=0x1000 +wipy3.build.target=esp32 +wipy3.build.mcu=esp32 +wipy3.build.core=esp32 +wipy3.build.variant=wipy3 +wipy3.build.board=WIPY3 + +wipy3.build.f_cpu=240000000L +wipy3.build.flash_mode=dio +wipy3.build.flash_size=8MB +wipy3.build.boot=dio +wipy3.build.partitions=default +wipy3.build.defines= + +wipy3.menu.FlashFreq.80=80MHz +wipy3.menu.FlashFreq.80.build.flash_freq=80m +wipy3.menu.FlashFreq.40=40MHz +wipy3.menu.FlashFreq.40.build.flash_freq=40m + +wipy3.menu.UploadSpeed.921600=921600 +wipy3.menu.UploadSpeed.921600.upload.speed=921600 +wipy3.menu.UploadSpeed.115200=115200 +wipy3.menu.UploadSpeed.115200.upload.speed=115200 +wipy3.menu.UploadSpeed.256000.windows=256000 +wipy3.menu.UploadSpeed.256000.upload.speed=256000 +wipy3.menu.UploadSpeed.230400.windows.upload.speed=256000 +wipy3.menu.UploadSpeed.230400=230400 +wipy3.menu.UploadSpeed.230400.upload.speed=230400 +wipy3.menu.UploadSpeed.460800.linux=460800 +wipy3.menu.UploadSpeed.460800.macosx=460800 +wipy3.menu.UploadSpeed.460800.upload.speed=460800 +wipy3.menu.UploadSpeed.512000.windows=512000 +wipy3.menu.UploadSpeed.512000.upload.speed=512000 + +wipy3.menu.DebugLevel.none=None +wipy3.menu.DebugLevel.none.build.code_debug=0 +wipy3.menu.DebugLevel.error=Error +wipy3.menu.DebugLevel.error.build.code_debug=1 +wipy3.menu.DebugLevel.warn=Warn +wipy3.menu.DebugLevel.warn.build.code_debug=2 +wipy3.menu.DebugLevel.info=Info +wipy3.menu.DebugLevel.info.build.code_debug=3 +wipy3.menu.DebugLevel.debug=Debug +wipy3.menu.DebugLevel.debug.build.code_debug=4 +wipy3.menu.DebugLevel.verbose=Verbose +wipy3.menu.DebugLevel.verbose.build.code_debug=5 + +wipy3.menu.EraseFlash.none=Disabled +wipy3.menu.EraseFlash.none.upload.erase_cmd= +wipy3.menu.EraseFlash.all=Enabled +wipy3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wt32-eth01.name=WT32-ETH01 Ethernet Module + +wt32-eth01.bootloader.tool=esptool_py +wt32-eth01.bootloader.tool.default=esptool_py + +wt32-eth01.upload.tool=esptool_py +wt32-eth01.upload.tool.default=esptool_py +wt32-eth01.upload.tool.network=esp_ota + +wt32-eth01.upload.maximum_size=8388608 +wt32-eth01.upload.maximum_data_size=327680 +wt32-eth01.upload.flags= +wt32-eth01.upload.extra_flags= + +wt32-eth01.serial.disableDTR=true +wt32-eth01.serial.disableRTS=true + +wt32-eth01.build.tarch=xtensa +wt32-eth01.build.bootloader_addr=0x1000 +wt32-eth01.build.target=esp32 +wt32-eth01.build.mcu=esp32 +wt32-eth01.build.core=esp32 +wt32-eth01.build.variant=wt32-eth01 +wt32-eth01.build.board=WT32_ETH01 + +wt32-eth01.build.f_cpu=240000000L +wt32-eth01.build.flash_size=4MB +wt32-eth01.build.flash_freq=40m +wt32-eth01.build.flash_mode=dio +wt32-eth01.build.boot=dio +wt32-eth01.build.partitions=default +wt32-eth01.build.defines= +wt32-eth01.build.extra_libs= + +wt32-eth01.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +wt32-eth01.menu.PartitionScheme.default.build.partitions=default +wt32-eth01.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +wt32-eth01.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +wt32-eth01.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +wt32-eth01.menu.PartitionScheme.minimal.build.partitions=minimal +wt32-eth01.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +wt32-eth01.menu.PartitionScheme.no_ota.build.partitions=no_ota +wt32-eth01.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +wt32-eth01.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +wt32-eth01.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +wt32-eth01.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +wt32-eth01.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +wt32-eth01.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +wt32-eth01.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +wt32-eth01.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +wt32-eth01.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +wt32-eth01.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +wt32-eth01.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +wt32-eth01.menu.PartitionScheme.huge_app.build.partitions=huge_app +wt32-eth01.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +wt32-eth01.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +wt32-eth01.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +wt32-eth01.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +wt32-eth01.menu.FlashMode.qio=QIO +wt32-eth01.menu.FlashMode.qio.build.flash_mode=dio +wt32-eth01.menu.FlashMode.qio.build.boot=qio +wt32-eth01.menu.FlashMode.dio=DIO +wt32-eth01.menu.FlashMode.dio.build.flash_mode=dio +wt32-eth01.menu.FlashMode.dio.build.boot=dio + +wt32-eth01.menu.FlashFreq.80=80MHz +wt32-eth01.menu.FlashFreq.80.build.flash_freq=80m +wt32-eth01.menu.FlashFreq.40=40MHz +wt32-eth01.menu.FlashFreq.40.build.flash_freq=40m + +wt32-eth01.menu.UploadSpeed.921600=921600 +wt32-eth01.menu.UploadSpeed.921600.upload.speed=921600 +wt32-eth01.menu.UploadSpeed.115200=115200 +wt32-eth01.menu.UploadSpeed.115200.upload.speed=115200 +wt32-eth01.menu.UploadSpeed.256000.windows=256000 +wt32-eth01.menu.UploadSpeed.256000.upload.speed=256000 +wt32-eth01.menu.UploadSpeed.230400.windows.upload.speed=256000 +wt32-eth01.menu.UploadSpeed.230400=230400 +wt32-eth01.menu.UploadSpeed.230400.upload.speed=230400 +wt32-eth01.menu.UploadSpeed.460800.linux=460800 +wt32-eth01.menu.UploadSpeed.460800.macosx=460800 +wt32-eth01.menu.UploadSpeed.460800.upload.speed=460800 +wt32-eth01.menu.UploadSpeed.512000.windows=512000 +wt32-eth01.menu.UploadSpeed.512000.upload.speed=512000 + +wt32-eth01.menu.DebugLevel.none=None +wt32-eth01.menu.DebugLevel.none.build.code_debug=0 +wt32-eth01.menu.DebugLevel.error=Error +wt32-eth01.menu.DebugLevel.error.build.code_debug=1 +wt32-eth01.menu.DebugLevel.warn=Warn +wt32-eth01.menu.DebugLevel.warn.build.code_debug=2 +wt32-eth01.menu.DebugLevel.info=Info +wt32-eth01.menu.DebugLevel.info.build.code_debug=3 +wt32-eth01.menu.DebugLevel.debug=Debug +wt32-eth01.menu.DebugLevel.debug.build.code_debug=4 +wt32-eth01.menu.DebugLevel.verbose=Verbose +wt32-eth01.menu.DebugLevel.verbose.build.code_debug=5 + +wt32-eth01.menu.EraseFlash.none=Disabled +wt32-eth01.menu.EraseFlash.none.upload.erase_cmd= +wt32-eth01.menu.EraseFlash.all=Enabled +wt32-eth01.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wt32-sc01-plus.name=WT32-SC01 PLUS +wt32-sc01-plus.vid.0=0x303a +wt32-sc01-plus.pid.0=0x80D0 + +wt32-sc01-plus.bootloader.tool=esptool_py +wt32-sc01-plus.bootloader.tool.default=esptool_py + +wt32-sc01-plus.upload.tool=esptool_py +wt32-sc01-plus.upload.tool.default=esptool_py +wt32-sc01-plus.upload.tool.network=esp_ota + +wt32-sc01-plus.upload.maximum_size=1310720 +wt32-sc01-plus.upload.maximum_data_size=327680 +wt32-sc01-plus.upload.flags= +wt32-sc01-plus.upload.extra_flags= +wt32-sc01-plus.upload.use_1200bps_touch=false +wt32-sc01-plus.upload.wait_for_upload_port=false + +wt32-sc01-plus.serial.disableDTR=false +wt32-sc01-plus.serial.disableRTS=false + +wt32-sc01-plus.build.tarch=xtensa +wt32-sc01-plus.build.bootloader_addr=0x0 +wt32-sc01-plus.build.target=esp32s3 +wt32-sc01-plus.build.mcu=esp32s3 +wt32-sc01-plus.build.core=esp32 +wt32-sc01-plus.build.variant=wt32-sc01-plus +wt32-sc01-plus.build.board=WT32_SC01_PLUS + +wt32-sc01-plus.build.usb_mode=1 +wt32-sc01-plus.build.cdc_on_boot=1 +wt32-sc01-plus.build.msc_on_boot=0 +wt32-sc01-plus.build.dfu_on_boot=0 +wt32-sc01-plus.build.f_cpu=240000000L +wt32-sc01-plus.build.flash_size=16MB +wt32-sc01-plus.build.flash_freq=80m +wt32-sc01-plus.build.flash_mode=dio +wt32-sc01-plus.build.boot=qio +wt32-sc01-plus.build.partitions=default +wt32-sc01-plus.build.defines= +wt32-sc01-plus.build.loop_core= +wt32-sc01-plus.build.event_core= +wt32-sc01-plus.build.flash_type=qio +wt32-sc01-plus.build.psram_type=qspi +wt32-sc01-plus.build.memory_type=qio_qspi + +wt32-sc01-plus.menu.LoopCore.1=Core 1 +wt32-sc01-plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +wt32-sc01-plus.menu.LoopCore.0=Core 0 +wt32-sc01-plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +wt32-sc01-plus.menu.EventsCore.1=Core 1 +wt32-sc01-plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +wt32-sc01-plus.menu.EventsCore.0=Core 0 +wt32-sc01-plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +wt32-sc01-plus.menu.USBMode.hwcdc=Hardware CDC and JTAG +wt32-sc01-plus.menu.USBMode.hwcdc.build.usb_mode=1 +wt32-sc01-plus.menu.USBMode.default=USB-OTG (TinyUSB) +wt32-sc01-plus.menu.USBMode.default.build.usb_mode=0 + +wt32-sc01-plus.menu.CDCOnBoot.cdc=Enabled +wt32-sc01-plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +wt32-sc01-plus.menu.CDCOnBoot.default=Disabled +wt32-sc01-plus.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +wt32-sc01-plus.menu.MSCOnBoot.default=Disabled +wt32-sc01-plus.menu.MSCOnBoot.default.build.msc_on_boot=0 +wt32-sc01-plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +wt32-sc01-plus.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +wt32-sc01-plus.menu.DFUOnBoot.default=Disabled +wt32-sc01-plus.menu.DFUOnBoot.default.build.dfu_on_boot=0 +wt32-sc01-plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +wt32-sc01-plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +wt32-sc01-plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true +wt32-sc01-plus.menu.UploadMode.default=UART0 / Hardware CDC +wt32-sc01-plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +wt32-sc01-plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true +wt32-sc01-plus.menu.UploadMode.default.upload.use_1200bps_touch=false +wt32-sc01-plus.menu.UploadMode.default.upload.wait_for_upload_port=false + +wt32-sc01-plus.menu.PSRAM.enabled=Enabled +wt32-sc01-plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +wt32-sc01-plus.menu.PSRAM.disabled=Disabled +wt32-sc01-plus.menu.PSRAM.disabled.build.defines= + +wt32-sc01-plus.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +wt32-sc01-plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +wt32-sc01-plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +wt32-sc01-plus.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT) +wt32-sc01-plus.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +wt32-sc01-plus.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +wt32-sc01-plus.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +wt32-sc01-plus.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 + +wt32-sc01-plus.menu.CPUFreq.240=240MHz (WiFi) +wt32-sc01-plus.menu.CPUFreq.240.build.f_cpu=240000000L +wt32-sc01-plus.menu.CPUFreq.160=160MHz (WiFi) +wt32-sc01-plus.menu.CPUFreq.160.build.f_cpu=160000000L +wt32-sc01-plus.menu.CPUFreq.80=80MHz (WiFi) +wt32-sc01-plus.menu.CPUFreq.80.build.f_cpu=80000000L +wt32-sc01-plus.menu.CPUFreq.40=40MHz +wt32-sc01-plus.menu.CPUFreq.40.build.f_cpu=40000000L +wt32-sc01-plus.menu.CPUFreq.20=20MHz +wt32-sc01-plus.menu.CPUFreq.20.build.f_cpu=20000000L +wt32-sc01-plus.menu.CPUFreq.10=10MHz +wt32-sc01-plus.menu.CPUFreq.10.build.f_cpu=10000000L + +wt32-sc01-plus.menu.FlashMode.qio=QIO +wt32-sc01-plus.menu.FlashMode.qio.build.flash_mode=dio +wt32-sc01-plus.menu.FlashMode.qio.build.boot=qio +wt32-sc01-plus.menu.FlashMode.dio=DIO +wt32-sc01-plus.menu.FlashMode.dio.build.flash_mode=dio +wt32-sc01-plus.menu.FlashMode.dio.build.boot=dio + +wt32-sc01-plus.menu.UploadSpeed.921600=921600 +wt32-sc01-plus.menu.UploadSpeed.921600.upload.speed=921600 +wt32-sc01-plus.menu.UploadSpeed.115200=115200 +wt32-sc01-plus.menu.UploadSpeed.115200.upload.speed=115200 +wt32-sc01-plus.menu.UploadSpeed.256000.windows=256000 +wt32-sc01-plus.menu.UploadSpeed.256000.upload.speed=256000 +wt32-sc01-plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +wt32-sc01-plus.menu.UploadSpeed.230400=230400 +wt32-sc01-plus.menu.UploadSpeed.230400.upload.speed=230400 +wt32-sc01-plus.menu.UploadSpeed.460800.linux=460800 +wt32-sc01-plus.menu.UploadSpeed.460800.macosx=460800 +wt32-sc01-plus.menu.UploadSpeed.460800.upload.speed=460800 +wt32-sc01-plus.menu.UploadSpeed.512000.windows=512000 +wt32-sc01-plus.menu.UploadSpeed.512000.upload.speed=512000 + +wt32-sc01-plus.menu.DebugLevel.none=None +wt32-sc01-plus.menu.DebugLevel.none.build.code_debug=0 +wt32-sc01-plus.menu.DebugLevel.error=Error +wt32-sc01-plus.menu.DebugLevel.error.build.code_debug=1 +wt32-sc01-plus.menu.DebugLevel.warn=Warn +wt32-sc01-plus.menu.DebugLevel.warn.build.code_debug=2 +wt32-sc01-plus.menu.DebugLevel.info=Info +wt32-sc01-plus.menu.DebugLevel.info.build.code_debug=3 +wt32-sc01-plus.menu.DebugLevel.debug=Debug +wt32-sc01-plus.menu.DebugLevel.debug.build.code_debug=4 +wt32-sc01-plus.menu.DebugLevel.verbose=Verbose +wt32-sc01-plus.menu.DebugLevel.verbose.build.code_debug=5 + +wt32-sc01-plus.menu.EraseFlash.none=Disabled +wt32-sc01-plus.menu.EraseFlash.none.upload.erase_cmd= +wt32-sc01-plus.menu.EraseFlash.all=Enabled +wt32-sc01-plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +bpi-bit.name=BPI-BIT + +bpi-bit.bootloader.tool=esptool_py +bpi-bit.bootloader.tool.default=esptool_py + +bpi-bit.upload.tool=esptool_py +bpi-bit.upload.tool.default=esptool_py +bpi-bit.upload.tool.network=esp_ota + +bpi-bit.upload.maximum_size=1310720 +bpi-bit.upload.maximum_data_size=294912 +bpi-bit.upload.flags= +bpi-bit.upload.extra_flags= + +bpi-bit.serial.disableDTR=true +bpi-bit.serial.disableRTS=true + +bpi-bit.build.tarch=xtensa +bpi-bit.build.bootloader_addr=0x1000 +bpi-bit.build.target=esp32 +bpi-bit.build.mcu=esp32 +bpi-bit.build.core=esp32 +bpi-bit.build.variant=bpi-bit +bpi-bit.build.board=BPI_BIT + +bpi-bit.build.f_cpu=160000000L +bpi-bit.build.flash_mode=dio +bpi-bit.build.flash_size=4MB +bpi-bit.build.boot=dio +bpi-bit.build.partitions=default + +bpi-bit.menu.FlashFreq.80=80MHz +bpi-bit.menu.FlashFreq.80.build.flash_freq=80m +bpi-bit.menu.FlashFreq.40=40MHz +bpi-bit.menu.FlashFreq.40.build.flash_freq=40m + +bpi-bit.menu.UploadSpeed.921600=921600 +bpi-bit.menu.UploadSpeed.921600.upload.speed=921600 +bpi-bit.menu.UploadSpeed.115200=115200 +bpi-bit.menu.UploadSpeed.115200.upload.speed=115200 +bpi-bit.menu.UploadSpeed.256000.windows=256000 +bpi-bit.menu.UploadSpeed.256000.upload.speed=256000 +bpi-bit.menu.UploadSpeed.230400.windows.upload.speed=256000 +bpi-bit.menu.UploadSpeed.230400=230400 +bpi-bit.menu.UploadSpeed.230400.upload.speed=230400 +bpi-bit.menu.UploadSpeed.460800.linux=460800 +bpi-bit.menu.UploadSpeed.460800.macosx=460800 +bpi-bit.menu.UploadSpeed.460800.upload.speed=460800 +bpi-bit.menu.UploadSpeed.512000.windows=512000 +bpi-bit.menu.UploadSpeed.512000.upload.speed=512000 + +bpi-bit.menu.DebugLevel.none=None +bpi-bit.menu.DebugLevel.none.build.code_debug=0 +bpi-bit.menu.DebugLevel.error=Error +bpi-bit.menu.DebugLevel.error.build.code_debug=1 +bpi-bit.menu.DebugLevel.warn=Warn +bpi-bit.menu.DebugLevel.warn.build.code_debug=2 +bpi-bit.menu.DebugLevel.info=Info +bpi-bit.menu.DebugLevel.info.build.code_debug=3 +bpi-bit.menu.DebugLevel.debug=Debug +bpi-bit.menu.DebugLevel.debug.build.code_debug=4 +bpi-bit.menu.DebugLevel.verbose=Verbose +bpi-bit.menu.DebugLevel.verbose.build.code_debug=5 + +bpi-bit.menu.EraseFlash.none=Disabled +bpi-bit.menu.EraseFlash.none.upload.erase_cmd= +bpi-bit.menu.EraseFlash.all=Enabled +bpi-bit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +bpi_leaf_s3.name=BPI-Leaf-S3 +bpi_leaf_s3.vid.0=0x303a +bpi_leaf_s3.pid.0=0x80df + +bpi_leaf_s3.bootloader.tool=esptool_py +bpi_leaf_s3.bootloader.tool.default=esptool_py + +bpi_leaf_s3.upload.tool=esptool_py +bpi_leaf_s3.upload.tool.default=esptool_py +bpi_leaf_s3.upload.tool.network=esp_ota + +bpi_leaf_s3.upload.maximum_size=1310720 +bpi_leaf_s3.upload.maximum_data_size=327680 +bpi_leaf_s3.upload.flags= +bpi_leaf_s3.upload.extra_flags= +bpi_leaf_s3.upload.use_1200bps_touch=false +bpi_leaf_s3.upload.wait_for_upload_port=false + +bpi_leaf_s3.serial.disableDTR=false +bpi_leaf_s3.serial.disableRTS=false + +bpi_leaf_s3.build.tarch=xtensa +bpi_leaf_s3.build.bootloader_addr=0x0 +bpi_leaf_s3.build.target=esp32s3 +bpi_leaf_s3.build.mcu=esp32s3 +bpi_leaf_s3.build.core=esp32 +bpi_leaf_s3.build.variant=bpi_leaf_s3 +bpi_leaf_s3.build.board=BPI_LEAF_S3 + +bpi_leaf_s3.build.usb_mode=1 +bpi_leaf_s3.build.cdc_on_boot=0 +bpi_leaf_s3.build.msc_on_boot=0 +bpi_leaf_s3.build.dfu_on_boot=0 +bpi_leaf_s3.build.f_cpu=240000000L +bpi_leaf_s3.build.flash_size=8MB +bpi_leaf_s3.build.flash_freq=80m +bpi_leaf_s3.build.flash_mode=dio +bpi_leaf_s3.build.boot=qio +bpi_leaf_s3.build.boot_freq=80m +bpi_leaf_s3.build.partitions=default +bpi_leaf_s3.build.defines= +bpi_leaf_s3.build.loop_core= +bpi_leaf_s3.build.event_core= +bpi_leaf_s3.build.psram_type=qspi +bpi_leaf_s3.build.memory_type={build.boot}_{build.psram_type} + +bpi_leaf_s3.menu.PSRAM.enabled=QSPI PSRAM +bpi_leaf_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +bpi_leaf_s3.menu.PSRAM.enabled.build.psram_type=qspi +bpi_leaf_s3.menu.PSRAM.disabled=Disabled +bpi_leaf_s3.menu.PSRAM.disabled.build.defines= +bpi_leaf_s3.menu.PSRAM.disabled.build.psram_type=qspi +bpi_leaf_s3.menu.PSRAM.opi=OPI PSRAM +bpi_leaf_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +bpi_leaf_s3.menu.PSRAM.opi.build.psram_type=opi + +bpi_leaf_s3.menu.FlashMode.qio=QIO 80MHz +bpi_leaf_s3.menu.FlashMode.qio.build.flash_mode=dio +bpi_leaf_s3.menu.FlashMode.qio.build.boot=qio +bpi_leaf_s3.menu.FlashMode.qio.build.boot_freq=80m +bpi_leaf_s3.menu.FlashMode.qio.build.flash_freq=80m +bpi_leaf_s3.menu.FlashMode.qio120=QIO 120MHz +bpi_leaf_s3.menu.FlashMode.qio120.build.flash_mode=dio +bpi_leaf_s3.menu.FlashMode.qio120.build.boot=qio +bpi_leaf_s3.menu.FlashMode.qio120.build.boot_freq=120m +bpi_leaf_s3.menu.FlashMode.qio120.build.flash_freq=80m +bpi_leaf_s3.menu.FlashMode.dio=DIO 80MHz +bpi_leaf_s3.menu.FlashMode.dio.build.flash_mode=dio +bpi_leaf_s3.menu.FlashMode.dio.build.boot=dio +bpi_leaf_s3.menu.FlashMode.dio.build.boot_freq=80m +bpi_leaf_s3.menu.FlashMode.dio.build.flash_freq=80m +bpi_leaf_s3.menu.FlashMode.opi=OPI 80MHz +bpi_leaf_s3.menu.FlashMode.opi.build.flash_mode=dout +bpi_leaf_s3.menu.FlashMode.opi.build.boot=opi +bpi_leaf_s3.menu.FlashMode.opi.build.boot_freq=80m +bpi_leaf_s3.menu.FlashMode.opi.build.flash_freq=80m + +bpi_leaf_s3.menu.FlashSize.8M=8MB (64Mb) +bpi_leaf_s3.menu.FlashSize.8M.build.flash_size=8MB +bpi_leaf_s3.menu.FlashSize.4M=4MB (32Mb) +bpi_leaf_s3.menu.FlashSize.4M.build.flash_size=4MB +bpi_leaf_s3.menu.FlashSize.16M=16MB (128Mb) +bpi_leaf_s3.menu.FlashSize.16M.build.flash_size=16MB +#bpi_leaf_s3.menu.FlashSize.32M=32MB (256Mb) +#bpi_leaf_s3.menu.FlashSize.32M.build.flash_size=32MB + +bpi_leaf_s3.menu.LoopCore.1=Core 1 +bpi_leaf_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +bpi_leaf_s3.menu.LoopCore.0=Core 0 +bpi_leaf_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +bpi_leaf_s3.menu.EventsCore.1=Core 1 +bpi_leaf_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +bpi_leaf_s3.menu.EventsCore.0=Core 0 +bpi_leaf_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +bpi_leaf_s3.menu.USBMode.default=USB-OTG (TinyUSB) +bpi_leaf_s3.menu.USBMode.default.build.usb_mode=0 +bpi_leaf_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +bpi_leaf_s3.menu.USBMode.hwcdc.build.usb_mode=1 + +bpi_leaf_s3.menu.CDCOnBoot.cdc=Enabled +bpi_leaf_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +bpi_leaf_s3.menu.CDCOnBoot.default=Disabled +bpi_leaf_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +bpi_leaf_s3.menu.MSCOnBoot.default=Disabled +bpi_leaf_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +bpi_leaf_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +bpi_leaf_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +bpi_leaf_s3.menu.DFUOnBoot.default=Disabled +bpi_leaf_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +bpi_leaf_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +bpi_leaf_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +bpi_leaf_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +bpi_leaf_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +bpi_leaf_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +bpi_leaf_s3.menu.UploadMode.default=UART0 / Hardware CDC +bpi_leaf_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +bpi_leaf_s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +bpi_leaf_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +bpi_leaf_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +bpi_leaf_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.default.build.partitions=default +bpi_leaf_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +bpi_leaf_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +bpi_leaf_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.minimal.build.partitions=minimal +bpi_leaf_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +bpi_leaf_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +bpi_leaf_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +bpi_leaf_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +bpi_leaf_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +bpi_leaf_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +bpi_leaf_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +bpi_leaf_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +bpi_leaf_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +bpi_leaf_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +bpi_leaf_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +bpi_leaf_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +bpi_leaf_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +bpi_leaf_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +bpi_leaf_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +bpi_leaf_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +bpi_leaf_s3.menu.PartitionScheme.fatflash.build.partitions=ffat +bpi_leaf_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +bpi_leaf_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +bpi_leaf_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +bpi_leaf_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +bpi_leaf_s3.menu.CPUFreq.240=240MHz (WiFi) +bpi_leaf_s3.menu.CPUFreq.240.build.f_cpu=240000000L +bpi_leaf_s3.menu.CPUFreq.160=160MHz (WiFi) +bpi_leaf_s3.menu.CPUFreq.160.build.f_cpu=160000000L +bpi_leaf_s3.menu.CPUFreq.80=80MHz (WiFi) +bpi_leaf_s3.menu.CPUFreq.80.build.f_cpu=80000000L +bpi_leaf_s3.menu.CPUFreq.40=40MHz +bpi_leaf_s3.menu.CPUFreq.40.build.f_cpu=40000000L +bpi_leaf_s3.menu.CPUFreq.20=20MHz +bpi_leaf_s3.menu.CPUFreq.20.build.f_cpu=20000000L +bpi_leaf_s3.menu.CPUFreq.10=10MHz +bpi_leaf_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +bpi_leaf_s3.menu.UploadSpeed.921600=921600 +bpi_leaf_s3.menu.UploadSpeed.921600.upload.speed=921600 +bpi_leaf_s3.menu.UploadSpeed.115200=115200 +bpi_leaf_s3.menu.UploadSpeed.115200.upload.speed=115200 +bpi_leaf_s3.menu.UploadSpeed.256000.windows=256000 +bpi_leaf_s3.menu.UploadSpeed.256000.upload.speed=256000 +bpi_leaf_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +bpi_leaf_s3.menu.UploadSpeed.230400=230400 +bpi_leaf_s3.menu.UploadSpeed.230400.upload.speed=230400 +bpi_leaf_s3.menu.UploadSpeed.460800.linux=460800 +bpi_leaf_s3.menu.UploadSpeed.460800.macosx=460800 +bpi_leaf_s3.menu.UploadSpeed.460800.upload.speed=460800 +bpi_leaf_s3.menu.UploadSpeed.512000.windows=512000 +bpi_leaf_s3.menu.UploadSpeed.512000.upload.speed=512000 + +bpi_leaf_s3.menu.DebugLevel.none=None +bpi_leaf_s3.menu.DebugLevel.none.build.code_debug=0 +bpi_leaf_s3.menu.DebugLevel.error=Error +bpi_leaf_s3.menu.DebugLevel.error.build.code_debug=1 +bpi_leaf_s3.menu.DebugLevel.warn=Warn +bpi_leaf_s3.menu.DebugLevel.warn.build.code_debug=2 +bpi_leaf_s3.menu.DebugLevel.info=Info +bpi_leaf_s3.menu.DebugLevel.info.build.code_debug=3 +bpi_leaf_s3.menu.DebugLevel.debug=Debug +bpi_leaf_s3.menu.DebugLevel.debug.build.code_debug=4 +bpi_leaf_s3.menu.DebugLevel.verbose=Verbose +bpi_leaf_s3.menu.DebugLevel.verbose.build.code_debug=5 + +bpi_leaf_s3.menu.EraseFlash.none=Disabled +bpi_leaf_s3.menu.EraseFlash.none.upload.erase_cmd= +bpi_leaf_s3.menu.EraseFlash.all=Enabled +bpi_leaf_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wesp32.name=Silicognition wESP32 + +wesp32.bootloader.tool=esptool_py +wesp32.bootloader.tool.default=esptool_py + +wesp32.upload.tool=esptool_py +wesp32.upload.tool.default=esptool_py +wesp32.upload.tool.network=esp_ota + +wesp32.upload.maximum_size=1310720 +wesp32.upload.maximum_data_size=327680 +wesp32.upload.flags= +wesp32.upload.extra_flags= + +wesp32.serial.disableDTR=true +wesp32.serial.disableRTS=true + +wesp32.build.tarch=xtensa +wesp32.build.bootloader_addr=0x1000 +wesp32.build.target=esp32 +wesp32.build.mcu=esp32 +wesp32.build.core=esp32 +wesp32.build.variant=wesp32 +wesp32.build.board=WESP32 + +wesp32.build.f_cpu=240000000L +wesp32.build.flash_mode=dio +wesp32.build.flash_size=16MB +wesp32.build.boot=dio +wesp32.build.partitions=default +wesp32.build.defines= + +wesp32.menu.FlashFreq.80=80MHz +wesp32.menu.FlashFreq.80.build.flash_freq=80m +wesp32.menu.FlashFreq.40=40MHz +wesp32.menu.FlashFreq.40.build.flash_freq=40m + +wesp32.menu.FlashSize.default=16MB (128Mb) rev 7+ +wesp32.menu.FlashSize.default.build.flash_size=16MB +wesp32.menu.FlashSize.default_4m_flash=4MB (32Mb) rev 5 and below +wesp32.menu.FlashSize.default_4m_flash.build.flash_size=4MB + +wesp32.menu.PartitionScheme.default=16M OTA with large SPIFFS (4.5MB APP/6.8MB SPIFFS) +wesp32.menu.PartitionScheme.default.build.partitions=large_spiffs_16MB +wesp32.menu.PartitionScheme.default.upload.maximum_size=4718592 +wesp32.menu.PartitionScheme.default_large_app=16M large OTA app with SPIFFS (6.2MB APP/3.3MB SPIFFS) +wesp32.menu.PartitionScheme.default_large_app.build.partitions=default_16MB +wesp32.menu.PartitionScheme.default_large_app.upload.maximum_size=6553600 +wesp32.menu.PartitionScheme.default_fatfs=16M OTA with large FATFS (3MB APP/9.8MB FATFS) +wesp32.menu.PartitionScheme.default_fatfs.build.partitions=app3M_fat9M_16MB +wesp32.menu.PartitionScheme.default_fatfs.upload.maximum_size=3145728 +wesp32.menu.PartitionScheme.default_4m_flash=4M OTA app with SPIFFS (1.25MB APP/1.3MB SPIFFS) +wesp32.menu.PartitionScheme.default_4m_flash.build.partitions=default + +wesp32.menu.UploadSpeed.921600=921600 +wesp32.menu.UploadSpeed.921600.upload.speed=921600 +wesp32.menu.UploadSpeed.115200=115200 +wesp32.menu.UploadSpeed.115200.upload.speed=115200 +wesp32.menu.UploadSpeed.256000.windows=256000 +wesp32.menu.UploadSpeed.256000.upload.speed=256000 +wesp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +wesp32.menu.UploadSpeed.230400=230400 +wesp32.menu.UploadSpeed.230400.upload.speed=230400 +wesp32.menu.UploadSpeed.460800.linux=460800 +wesp32.menu.UploadSpeed.460800.macosx=460800 +wesp32.menu.UploadSpeed.460800.upload.speed=460800 +wesp32.menu.UploadSpeed.512000.windows=512000 +wesp32.menu.UploadSpeed.512000.upload.speed=512000 + +wesp32.menu.DebugLevel.none=None +wesp32.menu.DebugLevel.none.build.code_debug=0 +wesp32.menu.DebugLevel.error=Error +wesp32.menu.DebugLevel.error.build.code_debug=1 +wesp32.menu.DebugLevel.warn=Warn +wesp32.menu.DebugLevel.warn.build.code_debug=2 +wesp32.menu.DebugLevel.info=Info +wesp32.menu.DebugLevel.info.build.code_debug=3 +wesp32.menu.DebugLevel.debug=Debug +wesp32.menu.DebugLevel.debug.build.code_debug=4 +wesp32.menu.DebugLevel.verbose=Verbose +wesp32.menu.DebugLevel.verbose.build.code_debug=5 + +wesp32.menu.EraseFlash.none=Disabled +wesp32.menu.EraseFlash.none.upload.erase_cmd= +wesp32.menu.EraseFlash.all=Enabled +wesp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +mant1s.name=Silicognition ManT1S + +mant1s.bootloader.tool=esptool_py +mant1s.bootloader.tool.default=esptool_py + +mant1s.upload.tool=esptool_py +mant1s.upload.tool.default=esptool_py +mant1s.upload.tool.network=esp_ota + +mant1s.upload.maximum_size=1310720 +mant1s.upload.maximum_data_size=2424832 +mant1s.upload.flags= +mant1s.upload.extra_flags= + +mant1s.serial.disableDTR=true +mant1s.serial.disableRTS=true + +mant1s.build.tarch=xtensa +mant1s.build.bootloader_addr=0x1000 +mant1s.build.target=esp32 +mant1s.build.mcu=esp32 +mant1s.build.core=esp32 +mant1s.build.variant=mant1s +mant1s.build.board=MANT1S + +mant1s.build.f_cpu=240000000L +mant1s.build.flash_mode=dio +mant1s.build.flash_size=8MB +mant1s.build.boot=dio +mant1s.build.partitions=default +mant1s.build.defines= + +mant1s.menu.FlashFreq.80=80MHz +mant1s.menu.FlashFreq.80.build.flash_freq=80m +mant1s.menu.FlashFreq.40=40MHz +mant1s.menu.FlashFreq.40.build.flash_freq=40m + +mant1s.menu.PSRAM.enabled=Enabled +mant1s.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +mant1s.menu.PSRAM.enabled.build.extra_libs= +mant1s.menu.PSRAM.disabled=Disabled +mant1s.menu.PSRAM.disabled.build.defines= +mant1s.menu.PSRAM.disabled.build.extra_libs= + +mant1s.menu.PartitionScheme.default=8M OTA with large SPIFFS (1.25MB APP/5.3MB SPIFFS) +mant1s.menu.PartitionScheme.default.build.partitions=large_spiffs_8MB +mant1s.menu.PartitionScheme.default_large_app=8M large OTA app with SPIFFS (3MB APP/1.5MB SPIFFS) +mant1s.menu.PartitionScheme.default_large_app.build.partitions=default_8MB +mant1s.menu.PartitionScheme.default_large_app.upload.maximum_size=3342336 +mant1s.menu.PartitionScheme.default_fatfs=8M OTA with large FATFS (1.25MB APP/5.3MB FATFS) +mant1s.menu.PartitionScheme.default_fatfs.build.partitions=large_ffat_8MB +mant1s.menu.PartitionScheme.default_large_app_fatfs=8M large OTA app with FATFS (3MB APP/1.5MB FATFS) +mant1s.menu.PartitionScheme.default_large_app_fatfs.build.partitions=default_ffat_8MB +mant1s.menu.PartitionScheme.default_large_app_fatfs.upload.maximum_size=3342336 + +mant1s.menu.UploadSpeed.921600=921600 +mant1s.menu.UploadSpeed.921600.upload.speed=921600 +mant1s.menu.UploadSpeed.115200=115200 +mant1s.menu.UploadSpeed.115200.upload.speed=115200 +mant1s.menu.UploadSpeed.256000.windows=256000 +mant1s.menu.UploadSpeed.256000.upload.speed=256000 +mant1s.menu.UploadSpeed.230400.windows.upload.speed=256000 +mant1s.menu.UploadSpeed.230400=230400 +mant1s.menu.UploadSpeed.230400.upload.speed=230400 +mant1s.menu.UploadSpeed.460800.linux=460800 +mant1s.menu.UploadSpeed.460800.macosx=460800 +mant1s.menu.UploadSpeed.460800.upload.speed=460800 +mant1s.menu.UploadSpeed.512000.windows=512000 +mant1s.menu.UploadSpeed.512000.upload.speed=512000 + +mant1s.menu.DebugLevel.none=None +mant1s.menu.DebugLevel.none.build.code_debug=0 +mant1s.menu.DebugLevel.error=Error +mant1s.menu.DebugLevel.error.build.code_debug=1 +mant1s.menu.DebugLevel.warn=Warn +mant1s.menu.DebugLevel.warn.build.code_debug=2 +mant1s.menu.DebugLevel.info=Info +mant1s.menu.DebugLevel.info.build.code_debug=3 +mant1s.menu.DebugLevel.debug=Debug +mant1s.menu.DebugLevel.debug.build.code_debug=4 +mant1s.menu.DebugLevel.verbose=Verbose +mant1s.menu.DebugLevel.verbose.build.code_debug=5 + +mant1s.menu.EraseFlash.none=Disabled +mant1s.menu.EraseFlash.none.upload.erase_cmd= +mant1s.menu.EraseFlash.all=Enabled +mant1s.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +t-beam.name=T-Beam + +t-beam.bootloader.tool=esptool_py +t-beam.bootloader.tool.default=esptool_py + +t-beam.upload.tool=esptool_py +t-beam.upload.tool.default=esptool_py +t-beam.upload.tool.network=esp_ota + +t-beam.upload.maximum_size=1310720 +t-beam.upload.maximum_data_size=327680 +t-beam.upload.flags= +t-beam.upload.extra_flags= + +t-beam.serial.disableDTR=true +t-beam.serial.disableRTS=true + +t-beam.build.tarch=xtensa +t-beam.build.bootloader_addr=0x1000 +t-beam.build.target=esp32 +t-beam.build.mcu=esp32 +t-beam.build.core=esp32 +t-beam.build.variant=tbeam +t-beam.build.board=TBeam + +t-beam.menu.Revision.Radio_SX1262=Radio-SX1262 +t-beam.menu.Revision.Radio_SX1262.build.board=TBEAM_USE_RADIO_SX1262 +t-beam.menu.Revision.Radio_SX1276=Radio-SX1276 +t-beam.menu.Revision.Radio_SX1276.build.board=TBEAM_USE_RADIO_SX1276 +t-beam.menu.Revision.Radio_SX1278=Radio-SX1278 +t-beam.menu.Revision.Radio_SX1278.build.board=TBEAM_USE_RADIO_SX1278 +t-beam.menu.Revision.Radio_SX1280=Radio-SX1280 +t-beam.menu.Revision.Radio_SX1280.build.board=TBEAM_USE_RADIO_SX1280 +t-beam.menu.Revision.Radio_SX1268=Radio-SX1268 +t-beam.menu.Revision.Radio_SX1268.build.board=TBEAM_USE_RADIO_SX1268 + +t-beam.build.f_cpu=240000000L +t-beam.build.flash_mode=dio +t-beam.build.flash_size=4MB +t-beam.build.boot=dio +t-beam.build.partitions=default + +t-beam.menu.PSRAM.disabled=Disabled +t-beam.menu.PSRAM.disabled.build.defines= +t-beam.menu.PSRAM.disabled.build.extra_libs= +t-beam.menu.PSRAM.enabled=Enabled +t-beam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +t-beam.menu.PSRAM.enabled.build.extra_libs= + +t-beam.menu.FlashFreq.80=80MHz +t-beam.menu.FlashFreq.80.build.flash_freq=80m +t-beam.menu.FlashFreq.40=40MHz +t-beam.menu.FlashFreq.40.build.flash_freq=40m + +t-beam.menu.UploadSpeed.921600=921600 +t-beam.menu.UploadSpeed.921600.upload.speed=921600 +t-beam.menu.UploadSpeed.115200=115200 +t-beam.menu.UploadSpeed.115200.upload.speed=115200 +t-beam.menu.UploadSpeed.256000.windows=256000 +t-beam.menu.UploadSpeed.256000.upload.speed=256000 +t-beam.menu.UploadSpeed.230400.windows.upload.speed=256000 +t-beam.menu.UploadSpeed.230400=230400 +t-beam.menu.UploadSpeed.230400.upload.speed=230400 +t-beam.menu.UploadSpeed.460800.linux=460800 +t-beam.menu.UploadSpeed.460800.macosx=460800 +t-beam.menu.UploadSpeed.460800.upload.speed=460800 +t-beam.menu.UploadSpeed.512000.windows=512000 +t-beam.menu.UploadSpeed.512000.upload.speed=512000 + +t-beam.menu.DebugLevel.none=None +t-beam.menu.DebugLevel.none.build.code_debug=0 +t-beam.menu.DebugLevel.error=Error +t-beam.menu.DebugLevel.error.build.code_debug=1 +t-beam.menu.DebugLevel.warn=Warn +t-beam.menu.DebugLevel.warn.build.code_debug=2 +t-beam.menu.DebugLevel.info=Info +t-beam.menu.DebugLevel.info.build.code_debug=3 +t-beam.menu.DebugLevel.debug=Debug +t-beam.menu.DebugLevel.debug.build.code_debug=4 +t-beam.menu.DebugLevel.verbose=Verbose +t-beam.menu.DebugLevel.verbose.build.code_debug=5 + +t-beam.menu.EraseFlash.none=Disabled +t-beam.menu.EraseFlash.none.upload.erase_cmd= +t-beam.menu.EraseFlash.all=Enabled +t-beam.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +d-duino-32.name=D-duino-32 + +d-duino-32.bootloader.tool=esptool_py +d-duino-32.bootloader.tool.default=esptool_py + +d-duino-32.upload.tool=esptool_py +d-duino-32.upload.tool.default=esptool_py +d-duino-32.upload.tool.network=esp_ota + +d-duino-32.upload.maximum_size=1310720 +d-duino-32.upload.maximum_data_size=327680 +d-duino-32.upload.flags= +d-duino-32.upload.extra_flags= + +d-duino-32.serial.disableDTR=true +d-duino-32.serial.disableRTS=true + +d-duino-32.build.tarch=xtensa +d-duino-32.build.bootloader_addr=0x1000 +d-duino-32.build.target=esp32 +d-duino-32.build.mcu=esp32 +d-duino-32.build.core=esp32 +d-duino-32.build.variant=d-duino-32 +d-duino-32.build.board=D_Duino_32 + +d-duino-32.build.f_cpu=240000000L +d-duino-32.build.flash_size=4MB +d-duino-32.build.flash_freq=40m +d-duino-32.build.flash_mode=dio +d-duino-32.build.boot=dio +d-duino-32.build.partitions=default +d-duino-32.build.defines= + +d-duino-32.menu.PartitionScheme.default=Default +d-duino-32.menu.PartitionScheme.default.build.partitions=default +d-duino-32.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +d-duino-32.menu.PartitionScheme.minimal.build.partitions=minimal +d-duino-32.menu.PartitionScheme.no_ota=No OTA (Large APP) +d-duino-32.menu.PartitionScheme.no_ota.build.partitions=no_ota +d-duino-32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +d-duino-32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +d-duino-32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +d-duino-32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +d-duino-32.menu.PartitionScheme.fatflash=16M Fat +d-duino-32.menu.PartitionScheme.fatflash.build.partitions=ffat + +d-duino-32.menu.FlashFreq.80=80MHz +d-duino-32.menu.FlashFreq.80.build.flash_freq=80m +d-duino-32.menu.FlashFreq.40=40MHz +d-duino-32.menu.FlashFreq.40.build.flash_freq=40m + +d-duino-32.menu.UploadSpeed.921600=921600 +d-duino-32.menu.UploadSpeed.921600.upload.speed=921600 +d-duino-32.menu.UploadSpeed.115200=115200 +d-duino-32.menu.UploadSpeed.115200.upload.speed=115200 +d-duino-32.menu.UploadSpeed.256000.windows=256000 +d-duino-32.menu.UploadSpeed.256000.upload.speed=256000 +d-duino-32.menu.UploadSpeed.230400.windows.upload.speed=256000 +d-duino-32.menu.UploadSpeed.230400=230400 +d-duino-32.menu.UploadSpeed.230400.upload.speed=230400 +d-duino-32.menu.UploadSpeed.460800.linux=460800 +d-duino-32.menu.UploadSpeed.460800.macosx=460800 +d-duino-32.menu.UploadSpeed.460800.upload.speed=460800 +d-duino-32.menu.UploadSpeed.512000.windows=512000 +d-duino-32.menu.UploadSpeed.512000.upload.speed=512000 + +d-duino-32.menu.DebugLevel.none=None +d-duino-32.menu.DebugLevel.none.build.code_debug=0 +d-duino-32.menu.DebugLevel.error=Error +d-duino-32.menu.DebugLevel.error.build.code_debug=1 +d-duino-32.menu.DebugLevel.warn=Warn +d-duino-32.menu.DebugLevel.warn.build.code_debug=2 +d-duino-32.menu.DebugLevel.info=Info +d-duino-32.menu.DebugLevel.info.build.code_debug=3 +d-duino-32.menu.DebugLevel.debug=Debug +d-duino-32.menu.DebugLevel.debug.build.code_debug=4 +d-duino-32.menu.DebugLevel.verbose=Verbose +d-duino-32.menu.DebugLevel.verbose.build.code_debug=5 + +d-duino-32.menu.EraseFlash.none=Disabled +d-duino-32.menu.EraseFlash.none.upload.erase_cmd= +d-duino-32.menu.EraseFlash.all=Enabled +d-duino-32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lopy.name=LoPy + +lopy.bootloader.tool=esptool_py +lopy.bootloader.tool.default=esptool_py + +lopy.upload.tool=esptool_py +lopy.upload.tool.default=esptool_py +lopy.upload.tool.network=esp_ota + +lopy.upload.maximum_size=1310720 +lopy.upload.maximum_data_size=327680 +lopy.upload.flags= +lopy.upload.extra_flags= + +lopy.serial.disableDTR=true +lopy.serial.disableRTS=true + +lopy.build.tarch=xtensa +lopy.build.bootloader_addr=0x1000 +lopy.build.target=esp32 +lopy.build.mcu=esp32 +lopy.build.core=esp32 +lopy.build.variant=lopy +lopy.build.board=LoPy + +lopy.build.f_cpu=240000000L +lopy.build.flash_mode=dio +lopy.build.flash_size=4MB +lopy.build.boot=dio +lopy.build.partitions=default + +lopy.menu.FlashFreq.80=80MHz +lopy.menu.FlashFreq.80.build.flash_freq=80m +lopy.menu.FlashFreq.40=40MHz +lopy.menu.FlashFreq.40.build.flash_freq=40m + +lopy.menu.UploadSpeed.921600=921600 +lopy.menu.UploadSpeed.921600.upload.speed=921600 +lopy.menu.UploadSpeed.115200=115200 +lopy.menu.UploadSpeed.115200.upload.speed=115200 +lopy.menu.UploadSpeed.256000.windows=256000 +lopy.menu.UploadSpeed.256000.upload.speed=256000 +lopy.menu.UploadSpeed.230400.windows.upload.speed=256000 +lopy.menu.UploadSpeed.230400=230400 +lopy.menu.UploadSpeed.230400.upload.speed=230400 +lopy.menu.UploadSpeed.460800.linux=460800 +lopy.menu.UploadSpeed.460800.macosx=460800 +lopy.menu.UploadSpeed.460800.upload.speed=460800 +lopy.menu.UploadSpeed.512000.windows=512000 +lopy.menu.UploadSpeed.512000.upload.speed=512000 + +lopy.menu.DebugLevel.none=None +lopy.menu.DebugLevel.none.build.code_debug=0 +lopy.menu.DebugLevel.error=Error +lopy.menu.DebugLevel.error.build.code_debug=1 +lopy.menu.DebugLevel.warn=Warn +lopy.menu.DebugLevel.warn.build.code_debug=2 +lopy.menu.DebugLevel.info=Info +lopy.menu.DebugLevel.info.build.code_debug=3 +lopy.menu.DebugLevel.debug=Debug +lopy.menu.DebugLevel.debug.build.code_debug=4 +lopy.menu.DebugLevel.verbose=Verbose +lopy.menu.DebugLevel.verbose.build.code_debug=5 + +lopy.menu.EraseFlash.none=Disabled +lopy.menu.EraseFlash.none.upload.erase_cmd= +lopy.menu.EraseFlash.all=Enabled +lopy.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lopy4.name=LoPy4 + +lopy4.bootloader.tool=esptool_py +lopy4.bootloader.tool.default=esptool_py + +lopy4.upload.tool=esptool_py +lopy4.upload.tool.default=esptool_py +lopy4.upload.tool.network=esp_ota + +lopy4.upload.maximum_size=1310720 +lopy4.upload.maximum_data_size=327680 +lopy4.upload.flags= +lopy4.upload.extra_flags= + +lopy4.serial.disableDTR=true +lopy4.serial.disableRTS=true + +lopy4.build.tarch=xtensa +lopy4.build.bootloader_addr=0x1000 +lopy4.build.target=esp32 +lopy4.build.mcu=esp32 +lopy4.build.core=esp32 +lopy4.build.variant=lopy4 +lopy4.build.board=LoPy4 + +lopy4.build.f_cpu=240000000L +lopy4.build.flash_mode=dio +lopy4.build.flash_size=4MB +lopy4.build.boot=dio +lopy4.build.partitions=default + +lopy4.menu.PSRAM.disabled=Disabled +lopy4.menu.PSRAM.disabled.build.defines= +lopy4.menu.PSRAM.disabled.build.extra_libs= +lopy4.menu.PSRAM.enabled=Enabled +lopy4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +lopy4.menu.PSRAM.enabled.build.extra_libs= + +lopy4.menu.FlashFreq.80=80MHz +lopy4.menu.FlashFreq.80.build.flash_freq=80m +lopy4.menu.FlashFreq.40=40MHz +lopy4.menu.FlashFreq.40.build.flash_freq=40m + +lopy4.menu.UploadSpeed.921600=921600 +lopy4.menu.UploadSpeed.921600.upload.speed=921600 +lopy4.menu.UploadSpeed.115200=115200 +lopy4.menu.UploadSpeed.115200.upload.speed=115200 +lopy4.menu.UploadSpeed.256000.windows=256000 +lopy4.menu.UploadSpeed.256000.upload.speed=256000 +lopy4.menu.UploadSpeed.230400.windows.upload.speed=256000 +lopy4.menu.UploadSpeed.230400=230400 +lopy4.menu.UploadSpeed.230400.upload.speed=230400 +lopy4.menu.UploadSpeed.460800.linux=460800 +lopy4.menu.UploadSpeed.460800.macosx=460800 +lopy4.menu.UploadSpeed.460800.upload.speed=460800 +lopy4.menu.UploadSpeed.512000.windows=512000 +lopy4.menu.UploadSpeed.512000.upload.speed=512000 + +lopy4.menu.DebugLevel.none=None +lopy4.menu.DebugLevel.none.build.code_debug=0 +lopy4.menu.DebugLevel.error=Error +lopy4.menu.DebugLevel.error.build.code_debug=1 +lopy4.menu.DebugLevel.warn=Warn +lopy4.menu.DebugLevel.warn.build.code_debug=2 +lopy4.menu.DebugLevel.info=Info +lopy4.menu.DebugLevel.info.build.code_debug=3 +lopy4.menu.DebugLevel.debug=Debug +lopy4.menu.DebugLevel.debug.build.code_debug=4 +lopy4.menu.DebugLevel.verbose=Verbose +lopy4.menu.DebugLevel.verbose.build.code_debug=5 + +lopy4.menu.EraseFlash.none=Disabled +lopy4.menu.EraseFlash.none.upload.erase_cmd= +lopy4.menu.EraseFlash.all=Enabled +lopy4.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +oroca_edubot.name=OROCA EduBot + +oroca_edubot.bootloader.tool=esptool_py +oroca_edubot.bootloader.tool.default=esptool_py + +oroca_edubot.upload.tool=esptool_py +oroca_edubot.upload.tool.default=esptool_py +oroca_edubot.upload.tool.network=esp_ota + +oroca_edubot.upload.maximum_size=3145728 +oroca_edubot.upload.maximum_data_size=327680 +oroca_edubot.upload.flags= +oroca_edubot.upload.extra_flags= + +oroca_edubot.serial.disableDTR=true +oroca_edubot.serial.disableRTS=true + +oroca_edubot.build.tarch=xtensa +oroca_edubot.build.bootloader_addr=0x1000 +oroca_edubot.build.target=esp32 +oroca_edubot.build.mcu=esp32 +oroca_edubot.build.core=esp32 +oroca_edubot.build.variant=oroca_edubot +oroca_edubot.build.board=OROCA_EDUBOT + +oroca_edubot.build.f_cpu=240000000L +oroca_edubot.build.flash_mode=dio +oroca_edubot.build.flash_size=4MB +oroca_edubot.build.boot=dio +oroca_edubot.build.partitions=huge_app +oroca_edubot.build.defines= + +oroca_edubot.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA) +oroca_edubot.menu.PartitionScheme.huge_app.build.partitions=huge_app +oroca_edubot.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +oroca_edubot.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +oroca_edubot.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +oroca_edubot.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +oroca_edubot.menu.FlashFreq.80=80MHz +oroca_edubot.menu.FlashFreq.80.build.flash_freq=80m +oroca_edubot.menu.FlashFreq.40=40MHz +oroca_edubot.menu.FlashFreq.40.build.flash_freq=40m + +oroca_edubot.menu.UploadSpeed.921600=921600 +oroca_edubot.menu.UploadSpeed.921600.upload.speed=921600 +oroca_edubot.menu.UploadSpeed.115200=115200 +oroca_edubot.menu.UploadSpeed.115200.upload.speed=115200 +oroca_edubot.menu.UploadSpeed.256000.windows=256000 +oroca_edubot.menu.UploadSpeed.256000.upload.speed=256000 +oroca_edubot.menu.UploadSpeed.230400.windows.upload.speed=256000 +oroca_edubot.menu.UploadSpeed.230400=230400 +oroca_edubot.menu.UploadSpeed.230400.upload.speed=230400 +oroca_edubot.menu.UploadSpeed.460800.linux=460800 +oroca_edubot.menu.UploadSpeed.460800.macosx=460800 +oroca_edubot.menu.UploadSpeed.460800.upload.speed=460800 +oroca_edubot.menu.UploadSpeed.512000.windows=512000 +oroca_edubot.menu.UploadSpeed.512000.upload.speed=512000 + +oroca_edubot.menu.DebugLevel.none=None +oroca_edubot.menu.DebugLevel.none.build.code_debug=0 +oroca_edubot.menu.DebugLevel.error=Error +oroca_edubot.menu.DebugLevel.error.build.code_debug=1 +oroca_edubot.menu.DebugLevel.warn=Warn +oroca_edubot.menu.DebugLevel.warn.build.code_debug=2 +oroca_edubot.menu.DebugLevel.info=Info +oroca_edubot.menu.DebugLevel.info.build.code_debug=3 +oroca_edubot.menu.DebugLevel.debug=Debug +oroca_edubot.menu.DebugLevel.debug.build.code_debug=4 +oroca_edubot.menu.DebugLevel.verbose=Verbose +oroca_edubot.menu.DebugLevel.verbose.build.code_debug=5 + +oroca_edubot.menu.EraseFlash.none=Disabled +oroca_edubot.menu.EraseFlash.none.upload.erase_cmd= +oroca_edubot.menu.EraseFlash.all=Enabled +oroca_edubot.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +fm-devkit.name=ESP32 FM DevKit + +fm-devkit.upload.tool=esptool_py +fm-devkit.upload.tool.default=esptool_py +fm-devkit.upload.tool.network=esp_ota + +fm-devkit.upload.maximum_size=1310720 +fm-devkit.upload.maximum_data_size=327680 +fm-devkit.upload.flags= +fm-devkit.upload.extra_flags= + +fm-devkit.serial.disableDTR=true +fm-devkit.serial.disableRTS=true + +fm-devkit.build.tarch=xtensa +fm-devkit.build.bootloader_addr=0x1000 +fm-devkit.build.target=esp32 +fm-devkit.build.mcu=esp32 +fm-devkit.build.core=esp32 +fm-devkit.build.variant=fm-devkit +fm-devkit.build.board=fm_devkit + +fm-devkit.build.f_cpu=240000000L +fm-devkit.build.flash_size=4MB +fm-devkit.build.flash_freq=80m +fm-devkit.build.flash_mode=dio +fm-devkit.build.boot=dio +fm-devkit.build.partitions=default +fm-devkit.build.defines= + +fm-devkit.menu.UploadSpeed.921600=921600 +fm-devkit.menu.UploadSpeed.921600.upload.speed=921600 +fm-devkit.menu.UploadSpeed.115200=115200 +fm-devkit.menu.UploadSpeed.115200.upload.speed=115200 +fm-devkit.menu.UploadSpeed.256000.windows=256000 +fm-devkit.menu.UploadSpeed.256000.upload.speed=256000 +fm-devkit.menu.UploadSpeed.230400.windows.upload.speed=256000 +fm-devkit.menu.UploadSpeed.230400=230400 +fm-devkit.menu.UploadSpeed.230400.upload.speed=230400 +fm-devkit.menu.UploadSpeed.460800.linux=460800 +fm-devkit.menu.UploadSpeed.460800.macosx=460800 +fm-devkit.menu.UploadSpeed.460800.upload.speed=460800 +fm-devkit.menu.UploadSpeed.512000.windows=512000 +fm-devkit.menu.UploadSpeed.512000.upload.speed=512000 + +fm-devkit.menu.DebugLevel.none=None +fm-devkit.menu.DebugLevel.none.build.code_debug=0 +fm-devkit.menu.DebugLevel.error=Error +fm-devkit.menu.DebugLevel.error.build.code_debug=1 +fm-devkit.menu.DebugLevel.warn=Warn +fm-devkit.menu.DebugLevel.warn.build.code_debug=2 +fm-devkit.menu.DebugLevel.info=Info +fm-devkit.menu.DebugLevel.info.build.code_debug=3 +fm-devkit.menu.DebugLevel.debug=Debug +fm-devkit.menu.DebugLevel.debug.build.code_debug=4 +fm-devkit.menu.DebugLevel.verbose=Verbose +fm-devkit.menu.DebugLevel.verbose.build.code_debug=5 + +fm-devkit.menu.EraseFlash.none=Disabled +fm-devkit.menu.EraseFlash.none.upload.erase_cmd= +fm-devkit.menu.EraseFlash.all=Enabled +fm-devkit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +### Fri3d Badge 2024 (ESP32-S3-WROOM-1) + +fri3d_2024_esp32s3.name=Fri3d Badge 2024 (ESP32-S3-WROOM-1) + +fri3d_2024_esp32s3.bootloader.tool=esptool_py +fri3d_2024_esp32s3.bootloader.tool.default=esptool_py + +fri3d_2024_esp32s3.upload.tool=esptool_py +fri3d_2024_esp32s3.upload.tool.default=esptool_py +fri3d_2024_esp32s3.upload.tool.network=esp_ota + +fri3d_2024_esp32s3.upload.maximum_size=1310720 +fri3d_2024_esp32s3.upload.maximum_data_size=327680 +fri3d_2024_esp32s3.upload.flags= +fri3d_2024_esp32s3.upload.extra_flags= +fri3d_2024_esp32s3.upload.use_1200bps_touch=false +fri3d_2024_esp32s3.upload.wait_for_upload_port=false + +fri3d_2024_esp32s3.serial.disableDTR=false +fri3d_2024_esp32s3.serial.disableRTS=false + +fri3d_2024_esp32s3.build.tarch=xtensa +fri3d_2024_esp32s3.build.bootloader_addr=0x0 +fri3d_2024_esp32s3.build.target=esp32s3 +fri3d_2024_esp32s3.build.mcu=esp32s3 +fri3d_2024_esp32s3.build.core=esp32 +fri3d_2024_esp32s3.build.variant=fri3d_2024_esp32s3 +fri3d_2024_esp32s3.build.board=FRI3D_2024_ESP32S3 + +fri3d_2024_esp32s3.build.usb_mode=1 +fri3d_2024_esp32s3.build.cdc_on_boot=0 +fri3d_2024_esp32s3.build.msc_on_boot=0 +fri3d_2024_esp32s3.build.dfu_on_boot=0 +fri3d_2024_esp32s3.build.f_cpu=240000000L +fri3d_2024_esp32s3.build.flash_size=16MB +fri3d_2024_esp32s3.build.flash_freq=80m +fri3d_2024_esp32s3.build.flash_mode=dio +fri3d_2024_esp32s3.build.boot=qio +fri3d_2024_esp32s3.build.boot_freq=80m +fri3d_2024_esp32s3.build.partitions=default +fri3d_2024_esp32s3.build.defines= +fri3d_2024_esp32s3.build.loop_core= +fri3d_2024_esp32s3.build.event_core= +fri3d_2024_esp32s3.build.psram_type=opi +fri3d_2024_esp32s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +fri3d_2024_esp32s3.menu.JTAGAdapter.default=Disabled +fri3d_2024_esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +fri3d_2024_esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +fri3d_2024_esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +fri3d_2024_esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +fri3d_2024_esp32s3.menu.JTAGAdapter.external=FTDI Adapter +fri3d_2024_esp32s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +fri3d_2024_esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +fri3d_2024_esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge +fri3d_2024_esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +fri3d_2024_esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +fri3d_2024_esp32s3.menu.PSRAM.default=OPI PSRAM +fri3d_2024_esp32s3.menu.PSRAM.default.build.defines=-DBOARD_HAS_PSRAM +fri3d_2024_esp32s3.menu.PSRAM.default.build.psram_type=opi +fri3d_2024_esp32s3.menu.PSRAM.disabled=Disabled +fri3d_2024_esp32s3.menu.PSRAM.disabled.build.defines= +fri3d_2024_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi + +fri3d_2024_esp32s3.menu.FlashMode.qio=QIO 80MHz +fri3d_2024_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +fri3d_2024_esp32s3.menu.FlashMode.qio.build.boot=qio +fri3d_2024_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.qio120=QIO 120MHz +fri3d_2024_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +fri3d_2024_esp32s3.menu.FlashMode.qio120.build.boot=qio +fri3d_2024_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +fri3d_2024_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.dio=DIO 80MHz +fri3d_2024_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +fri3d_2024_esp32s3.menu.FlashMode.dio.build.boot=dio +fri3d_2024_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.opi=OPI 80MHz +fri3d_2024_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +fri3d_2024_esp32s3.menu.FlashMode.opi.build.boot=opi +fri3d_2024_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +fri3d_2024_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +fri3d_2024_esp32s3.menu.FlashSize.default=16MB (128Mb) +fri3d_2024_esp32s3.menu.FlashSize.default.build.flash_size=16MB + +fri3d_2024_esp32s3.menu.LoopCore.1=Core 1 +fri3d_2024_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +fri3d_2024_esp32s3.menu.LoopCore.0=Core 0 +fri3d_2024_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +fri3d_2024_esp32s3.menu.EventsCore.1=Core 1 +fri3d_2024_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +fri3d_2024_esp32s3.menu.EventsCore.0=Core 0 +fri3d_2024_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +fri3d_2024_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +fri3d_2024_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +fri3d_2024_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +fri3d_2024_esp32s3.menu.USBMode.default.build.usb_mode=0 + +fri3d_2024_esp32s3.menu.CDCOnBoot.default=Enabled +fri3d_2024_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +fri3d_2024_esp32s3.menu.CDCOnBoot.disabled=Disabled +fri3d_2024_esp32s3.menu.CDCOnBoot.disabled.build.cdc_on_boot=0 + +fri3d_2024_esp32s3.menu.MSCOnBoot.default=Disabled +fri3d_2024_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +fri3d_2024_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +fri3d_2024_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +fri3d_2024_esp32s3.menu.DFUOnBoot.default=Disabled +fri3d_2024_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +fri3d_2024_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +fri3d_2024_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +fri3d_2024_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +fri3d_2024_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +fri3d_2024_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +fri3d_2024_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +fri3d_2024_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +fri3d_2024_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +fri3d_2024_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.default.build.partitions=default +fri3d_2024_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +fri3d_2024_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +fri3d_2024_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +fri3d_2024_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +fri3d_2024_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +fri3d_2024_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +fri3d_2024_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +fri3d_2024_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +fri3d_2024_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +fri3d_2024_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker=RainMaker +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +fri3d_2024_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +fri3d_2024_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +fri3d_2024_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +fri3d_2024_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +fri3d_2024_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +fri3d_2024_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +fri3d_2024_esp32s3.menu.CPUFreq.40=40MHz +fri3d_2024_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +fri3d_2024_esp32s3.menu.CPUFreq.20=20MHz +fri3d_2024_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +fri3d_2024_esp32s3.menu.CPUFreq.10=10MHz +fri3d_2024_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +fri3d_2024_esp32s3.menu.UploadSpeed.921600=921600 +fri3d_2024_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +fri3d_2024_esp32s3.menu.UploadSpeed.115200=115200 +fri3d_2024_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +fri3d_2024_esp32s3.menu.UploadSpeed.256000.windows=256000 +fri3d_2024_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +fri3d_2024_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +fri3d_2024_esp32s3.menu.UploadSpeed.230400=230400 +fri3d_2024_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +fri3d_2024_esp32s3.menu.UploadSpeed.460800.linux=460800 +fri3d_2024_esp32s3.menu.UploadSpeed.460800.macosx=460800 +fri3d_2024_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +fri3d_2024_esp32s3.menu.UploadSpeed.512000.windows=512000 +fri3d_2024_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +fri3d_2024_esp32s3.menu.DebugLevel.none=None +fri3d_2024_esp32s3.menu.DebugLevel.none.build.code_debug=0 +fri3d_2024_esp32s3.menu.DebugLevel.error=Error +fri3d_2024_esp32s3.menu.DebugLevel.error.build.code_debug=1 +fri3d_2024_esp32s3.menu.DebugLevel.warn=Warn +fri3d_2024_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +fri3d_2024_esp32s3.menu.DebugLevel.info=Info +fri3d_2024_esp32s3.menu.DebugLevel.info.build.code_debug=3 +fri3d_2024_esp32s3.menu.DebugLevel.debug=Debug +fri3d_2024_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +fri3d_2024_esp32s3.menu.DebugLevel.verbose=Verbose +fri3d_2024_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +fri3d_2024_esp32s3.menu.EraseFlash.none=Disabled +fri3d_2024_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +fri3d_2024_esp32s3.menu.EraseFlash.all=Enabled +fri3d_2024_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +frogboard.name=Frog Board ESP32 + +frogboard.bootloader.tool=esptool_py +frogboard.bootloader.tool.default=esptool_py + +frogboard.upload.tool=esptool_py +frogboard.upload.tool.default=esptool_py +frogboard.upload.tool.network=esp_ota + +frogboard.upload.maximum_size=1310720 +frogboard.upload.maximum_data_size=327680 +frogboard.upload.flags= +frogboard.upload.extra_flags= + +frogboard.serial.disableDTR=true +frogboard.serial.disableRTS=true + +frogboard.build.tarch=xtensa +frogboard.build.bootloader_addr=0x1000 +frogboard.build.target=esp32 +frogboard.build.mcu=esp32 +frogboard.build.core=esp32 +frogboard.build.variant=frog32 +frogboard.build.board=FROG_ESP32 +frogboard.build.f_cpu=240000000L +frogboard.build.flash_size=4MB +frogboard.build.flash_freq=40m +frogboard.build.flash_mode=dio +frogboard.build.boot=dio +frogboard.build.partitions=default +frogboard.build.defines= + +frogboard.menu.PSRAM.disabled=Disabled +frogboard.menu.PSRAM.disabled.build.defines= +frogboard.menu.PSRAM.disabled.build.extra_libs= +frogboard.menu.PSRAM.enabled=Enabled +frogboard.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +frogboard.menu.PSRAM.enabled.build.extra_libs= + +frogboard.menu.PartitionScheme.default=Default +frogboard.menu.PartitionScheme.default.build.partitions=default +frogboard.menu.PartitionScheme.minimal=Minimal (2MB FLASH) +frogboard.menu.PartitionScheme.minimal.build.partitions=minimal +frogboard.menu.PartitionScheme.no_ota=No OTA (Large APP) +frogboard.menu.PartitionScheme.no_ota.build.partitions=no_ota +frogboard.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +frogboard.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +frogboard.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +frogboard.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +frogboard.menu.FlashMode.qio=QIO +frogboard.menu.FlashMode.qio.build.flash_mode=dio +frogboard.menu.FlashMode.qio.build.boot=qio +frogboard.menu.FlashMode.dio=DIO +frogboard.menu.FlashMode.dio.build.flash_mode=dio +frogboard.menu.FlashMode.dio.build.boot=dio +frogboard.menu.FlashFreq.80=80MHz +frogboard.menu.FlashFreq.80.build.flash_freq=80m +frogboard.menu.FlashFreq.40=40MHz +frogboard.menu.FlashFreq.40.build.flash_freq=40m +frogboard.menu.FlashSize.4M=4MB (32Mb) +frogboard.menu.FlashSize.4M.build.flash_size=4MB +frogboard.menu.FlashSize.2M=2MB (16Mb) +frogboard.menu.FlashSize.2M.build.flash_size=2MB + +frogboard.menu.UploadSpeed.921600=921600 +frogboard.menu.UploadSpeed.921600.upload.speed=921600 +frogboard.menu.UploadSpeed.115200=115200 +frogboard.menu.UploadSpeed.115200.upload.speed=115200 +frogboard.menu.UploadSpeed.256000.windows=256000 +frogboard.menu.UploadSpeed.256000.upload.speed=256000 +frogboard.menu.UploadSpeed.230400.windows.upload.speed=256000 +frogboard.menu.UploadSpeed.230400=230400 +frogboard.menu.UploadSpeed.230400.upload.speed=230400 +frogboard.menu.UploadSpeed.460800.linux=460800 +frogboard.menu.UploadSpeed.460800.macosx=460800 +frogboard.menu.UploadSpeed.460800.upload.speed=460800 +frogboard.menu.UploadSpeed.512000.windows=512000 +frogboard.menu.UploadSpeed.512000.upload.speed=512000 + +frogboard.menu.DebugLevel.none=None +frogboard.menu.DebugLevel.none.build.code_debug=0 +frogboard.menu.DebugLevel.error=Error +frogboard.menu.DebugLevel.error.build.code_debug=1 +frogboard.menu.DebugLevel.warn=Warn +frogboard.menu.DebugLevel.warn.build.code_debug=2 +frogboard.menu.DebugLevel.info=Info +frogboard.menu.DebugLevel.info.build.code_debug=3 +frogboard.menu.DebugLevel.debug=Debug +frogboard.menu.DebugLevel.debug.build.code_debug=4 +frogboard.menu.DebugLevel.verbose=Verbose +frogboard.menu.DebugLevel.verbose.build.code_debug=5 + +frogboard.menu.EraseFlash.none=Disabled +frogboard.menu.EraseFlash.none.upload.erase_cmd= +frogboard.menu.EraseFlash.all=Enabled +frogboard.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32cam.name=AI Thinker ESP32-CAM + +esp32cam.bootloader.tool=esptool_py +esp32cam.bootloader.tool.default=esptool_py + +esp32cam.upload.tool=esptool_py +esp32cam.upload.tool.default=esptool_py +esp32cam.upload.tool.network=esp_ota + +esp32cam.upload.maximum_size=3145728 +esp32cam.upload.maximum_data_size=327680 +esp32cam.upload.flags= +esp32cam.upload.extra_flags= +esp32cam.upload.speed=460800 + +esp32cam.serial.disableDTR=true +esp32cam.serial.disableRTS=true + +esp32cam.build.tarch=xtensa +esp32cam.build.bootloader_addr=0x1000 +esp32cam.build.target=esp32 +esp32cam.build.mcu=esp32 +esp32cam.build.core=esp32 +esp32cam.build.variant=esp32 +esp32cam.build.board=ESP32_DEV +esp32cam.build.flash_size=4MB +esp32cam.build.partitions=huge_app +esp32cam.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +esp32cam.build.extra_libs= +esp32cam.build.code_debug=0 + +esp32cam.menu.CPUFreq.240=240MHz (WiFi/BT) +esp32cam.menu.CPUFreq.240.build.f_cpu=240000000L +esp32cam.menu.CPUFreq.160=160MHz (WiFi/BT) +esp32cam.menu.CPUFreq.160.build.f_cpu=160000000L +esp32cam.menu.CPUFreq.80=80MHz (WiFi/BT) +esp32cam.menu.CPUFreq.80.build.f_cpu=80000000L +esp32cam.menu.CPUFreq.40=40MHz (40MHz XTAL) +esp32cam.menu.CPUFreq.40.build.f_cpu=40000000L +esp32cam.menu.CPUFreq.26=26MHz (26MHz XTAL) +esp32cam.menu.CPUFreq.26.build.f_cpu=26000000L +esp32cam.menu.CPUFreq.20=20MHz (40MHz XTAL) +esp32cam.menu.CPUFreq.20.build.f_cpu=20000000L +esp32cam.menu.CPUFreq.13=13MHz (26MHz XTAL) +esp32cam.menu.CPUFreq.13.build.f_cpu=13000000L +esp32cam.menu.CPUFreq.10=10MHz (40MHz XTAL) +esp32cam.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32cam.menu.FlashMode.qio=QIO +esp32cam.menu.FlashMode.qio.build.flash_mode=dio +esp32cam.menu.FlashMode.qio.build.boot=qio +esp32cam.menu.FlashMode.dio=DIO +esp32cam.menu.FlashMode.dio.build.flash_mode=dio +esp32cam.menu.FlashMode.dio.build.boot=dio + +esp32cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32cam.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32cam.menu.PartitionScheme.default=Regular 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32cam.menu.PartitionScheme.default.build.partitions=default +esp32cam.menu.PartitionScheme.defaultffat=Regular 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32cam.menu.PartitionScheme.minimal.build.partitions=minimal +esp32cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32cam.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 + +esp32cam.menu.FlashFreq.80=80MHz +esp32cam.menu.FlashFreq.80.build.flash_freq=80m +esp32cam.menu.FlashFreq.40=40MHz +esp32cam.menu.FlashFreq.40.build.flash_freq=40m + +esp32cam.menu.DebugLevel.none=None +esp32cam.menu.DebugLevel.none.build.code_debug=0 +esp32cam.menu.DebugLevel.error=Error +esp32cam.menu.DebugLevel.error.build.code_debug=1 +esp32cam.menu.DebugLevel.warn=Warn +esp32cam.menu.DebugLevel.warn.build.code_debug=2 +esp32cam.menu.DebugLevel.info=Info +esp32cam.menu.DebugLevel.info.build.code_debug=3 +esp32cam.menu.DebugLevel.debug=Debug +esp32cam.menu.DebugLevel.debug.build.code_debug=4 +esp32cam.menu.DebugLevel.verbose=Verbose +esp32cam.menu.DebugLevel.verbose.build.code_debug=5 + +esp32cam.menu.EraseFlash.none=Disabled +esp32cam.menu.EraseFlash.none.upload.erase_cmd= +esp32cam.menu.EraseFlash.all=Enabled +esp32cam.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +twatch.name=TTGO T-Watch + +twatch.bootloader.tool=esptool_py +twatch.bootloader.tool.default=esptool_py + +twatch.upload.tool=esptool_py +twatch.upload.tool.default=esptool_py +twatch.upload.tool.network=esp_ota + +twatch.upload.maximum_size=6553600 +twatch.upload.maximum_data_size=4521984 +twatch.upload.wait_for_upload_port=true +twatch.upload.flags= +twatch.upload.extra_flags= + +twatch.serial.disableDTR=true +twatch.serial.disableRTS=true + +twatch.build.tarch=xtensa +twatch.build.bootloader_addr=0x1000 +twatch.build.target=esp32 +twatch.build.mcu=esp32 +twatch.build.core=esp32 +twatch.build.variant=twatch +twatch.build.board=TWatch + +twatch.menu.Revision.TWATCH_BASE=T-Watch Base +twatch.menu.Revision.TWATCH_BASE.build.board=TWATCH_BASE +twatch.menu.Revision.TWATCH_2020_V1=T-Watch-2020-V1 +twatch.menu.Revision.TWATCH_2020_V1.build.board=TWATCH_2020_V1 +twatch.menu.Revision.TWATCH_2020_V2=T-Watch-2020-V2 +twatch.menu.Revision.TWATCH_2020_V2.build.board=TWATCH_2020_V2 +twatch.menu.Revision.TWATCH_2020_V3=T-Watch-2020-V3 +twatch.menu.Revision.TWATCH_2020_V3.build.board=TWATCH_2020_V3 + +twatch.build.f_cpu=240000000L +twatch.build.flash_size=16MB +twatch.build.flash_freq=80m +twatch.build.flash_mode=dio +twatch.build.boot=dio +twatch.build.partitions=default_16MB +twatch.build.defines= + +twatch.menu.PSRAM.enabled=Enabled +twatch.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +twatch.menu.PSRAM.enabled.build.extra_libs= +twatch.menu.PSRAM.disabled=Disabled +twatch.menu.PSRAM.disabled.build.defines= +twatch.menu.PSRAM.disabled.build.extra_libs= + +twatch.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS) +twatch.menu.PartitionScheme.default.build.partitions=default_16MB +twatch.menu.PartitionScheme.default.upload.maximum_size=6553600 +twatch.menu.PartitionScheme.large_spiffs=Large SPIFFS (7 MB) +twatch.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +twatch.menu.PartitionScheme.large_spiffs.upload.maximum_size=4685824 + +twatch.menu.UploadSpeed.2000000=2000000 +twatch.menu.UploadSpeed.2000000.upload.speed=2000000 +twatch.menu.UploadSpeed.1152000=1152000 +twatch.menu.UploadSpeed.1152000.upload.speed=1152000 +twatch.menu.UploadSpeed.921600=921600 +twatch.menu.UploadSpeed.921600.upload.speed=921600 +twatch.menu.UploadSpeed.115200=115200 +twatch.menu.UploadSpeed.115200.upload.speed=115200 +twatch.menu.UploadSpeed.256000.windows=256000 +twatch.menu.UploadSpeed.256000.upload.speed=256000 +twatch.menu.UploadSpeed.230400.windows.upload.speed=256000 +twatch.menu.UploadSpeed.230400=230400 +twatch.menu.UploadSpeed.230400.upload.speed=230400 +twatch.menu.UploadSpeed.460800.linux=460800 +twatch.menu.UploadSpeed.460800.macosx=460800 +twatch.menu.UploadSpeed.460800.upload.speed=460800 +twatch.menu.UploadSpeed.512000.windows=512000 +twatch.menu.UploadSpeed.512000.upload.speed=512000 + +twatch.menu.DebugLevel.none=None +twatch.menu.DebugLevel.none.build.code_debug=0 +twatch.menu.DebugLevel.error=Error +twatch.menu.DebugLevel.error.build.code_debug=1 +twatch.menu.DebugLevel.warn=Warn +twatch.menu.DebugLevel.warn.build.code_debug=2 +twatch.menu.DebugLevel.info=Info +twatch.menu.DebugLevel.info.build.code_debug=3 +twatch.menu.DebugLevel.debug=Debug +twatch.menu.DebugLevel.debug.build.code_debug=4 +twatch.menu.DebugLevel.verbose=Verbose +twatch.menu.DebugLevel.verbose.build.code_debug=5 + +twatch.menu.EraseFlash.none=Disabled +twatch.menu.EraseFlash.none.upload.erase_cmd= +twatch.menu.EraseFlash.all=Enabled +twatch.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +d1_mini32.name=WEMOS D1 MINI ESP32 + +d1_mini32.bootloader.tool=esptool_py +d1_mini32.bootloader.tool.default=esptool_py + +d1_mini32.upload.tool=esptool_py +d1_mini32.upload.tool.default=esptool_py +d1_mini32.upload.tool.network=esp_ota + +d1_mini32.upload.maximum_size=1310720 +d1_mini32.upload.maximum_data_size=327680 +d1_mini32.upload.flags= +d1_mini32.upload.extra_flags= + +d1_mini32.serial.disableDTR=true +d1_mini32.serial.disableRTS=true + +d1_mini32.build.tarch=xtensa +d1_mini32.build.bootloader_addr=0x1000 +d1_mini32.build.target=esp32 +d1_mini32.build.mcu=esp32 +d1_mini32.build.core=esp32 +d1_mini32.build.variant=d1_mini32 +d1_mini32.build.board=D1_MINI32 + +d1_mini32.build.f_cpu=240000000L +d1_mini32.build.flash_mode=dio +d1_mini32.build.flash_size=4MB +d1_mini32.build.boot=dio +d1_mini32.build.partitions=default +d1_mini32.build.defines= + +d1_mini32.menu.FlashFreq.80=80MHz +d1_mini32.menu.FlashFreq.80.build.flash_freq=80m +d1_mini32.menu.FlashFreq.40=40MHz +d1_mini32.menu.FlashFreq.40.build.flash_freq=40m + +d1_mini32.menu.PartitionScheme.default=Default +d1_mini32.menu.PartitionScheme.default.build.partitions=default +d1_mini32.menu.PartitionScheme.no_ota=No OTA (Large APP) +d1_mini32.menu.PartitionScheme.no_ota.build.partitions=no_ota +d1_mini32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +d1_mini32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +d1_mini32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +d1_mini32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +d1_mini32.menu.CPUFreq.240=240MHz (WiFi/BT) +d1_mini32.menu.CPUFreq.240.build.f_cpu=240000000L +d1_mini32.menu.CPUFreq.160=160MHz (WiFi/BT) +d1_mini32.menu.CPUFreq.160.build.f_cpu=160000000L +d1_mini32.menu.CPUFreq.80=80MHz (WiFi/BT) +d1_mini32.menu.CPUFreq.80.build.f_cpu=80000000L +d1_mini32.menu.CPUFreq.40=40MHz (40MHz XTAL) +d1_mini32.menu.CPUFreq.40.build.f_cpu=40000000L +d1_mini32.menu.CPUFreq.26=26MHz (26MHz XTAL) +d1_mini32.menu.CPUFreq.26.build.f_cpu=26000000L +d1_mini32.menu.CPUFreq.20=20MHz (40MHz XTAL) +d1_mini32.menu.CPUFreq.20.build.f_cpu=20000000L +d1_mini32.menu.CPUFreq.13=13MHz (26MHz XTAL) +d1_mini32.menu.CPUFreq.13.build.f_cpu=13000000L +d1_mini32.menu.CPUFreq.10=10MHz (40MHz XTAL) +d1_mini32.menu.CPUFreq.10.build.f_cpu=10000000L + +d1_mini32.menu.UploadSpeed.921600=921600 +d1_mini32.menu.UploadSpeed.921600.upload.speed=921600 +d1_mini32.menu.UploadSpeed.115200=115200 +d1_mini32.menu.UploadSpeed.115200.upload.speed=115200 +d1_mini32.menu.UploadSpeed.256000.windows=256000 +d1_mini32.menu.UploadSpeed.256000.upload.speed=256000 +d1_mini32.menu.UploadSpeed.230400.windows.upload.speed=256000 +d1_mini32.menu.UploadSpeed.230400=230400 +d1_mini32.menu.UploadSpeed.230400.upload.speed=230400 +d1_mini32.menu.UploadSpeed.460800.linux=460800 +d1_mini32.menu.UploadSpeed.460800.macosx=460800 +d1_mini32.menu.UploadSpeed.460800.upload.speed=460800 +d1_mini32.menu.UploadSpeed.512000.windows=512000 +d1_mini32.menu.UploadSpeed.512000.upload.speed=512000 + +d1_mini32.menu.DebugLevel.none=None +d1_mini32.menu.DebugLevel.none.build.code_debug=0 +d1_mini32.menu.DebugLevel.error=Error +d1_mini32.menu.DebugLevel.error.build.code_debug=1 +d1_mini32.menu.DebugLevel.warn=Warn +d1_mini32.menu.DebugLevel.warn.build.code_debug=2 +d1_mini32.menu.DebugLevel.info=Info +d1_mini32.menu.DebugLevel.info.build.code_debug=3 +d1_mini32.menu.DebugLevel.debug=Debug +d1_mini32.menu.DebugLevel.debug.build.code_debug=4 +d1_mini32.menu.DebugLevel.verbose=Verbose +d1_mini32.menu.DebugLevel.verbose.build.code_debug=5 + +d1_mini32.menu.EraseFlash.none=Disabled +d1_mini32.menu.EraseFlash.none.upload.erase_cmd= +d1_mini32.menu.EraseFlash.all=Enabled +d1_mini32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +d1_uno32.name=WEMOS D1 R32 + +d1_uno32.bootloader.tool=esptool_py +d1_uno32.bootloader.tool.default=esptool_py + +d1_uno32.upload.tool=esptool_py +d1_uno32.upload.tool.default=esptool_py +d1_uno32.upload.tool.network=esp_ota + +d1_uno32.upload.maximum_size=1310720 +d1_uno32.upload.maximum_data_size=327680 +d1_uno32.upload.flags= +d1_uno32.upload.extra_flags= + +d1_uno32.serial.disableDTR=true +d1_uno32.serial.disableRTS=true + +d1_uno32.build.tarch=xtensa +d1_uno32.build.bootloader_addr=0x1000 +d1_uno32.build.target=esp32 +d1_uno32.build.mcu=esp32 +d1_uno32.build.core=esp32 +d1_uno32.build.variant=d1_uno32 +d1_uno32.build.board=D1_UNO32 + +d1_uno32.build.f_cpu=240000000L +d1_uno32.build.flash_mode=dio +d1_uno32.build.flash_size=4MB +d1_uno32.build.boot=dio +d1_uno32.build.partitions=default +d1_uno32.build.defines= + +d1_uno32.menu.FlashFreq.80=80MHz +d1_uno32.menu.FlashFreq.80.build.flash_freq=80m +d1_uno32.menu.FlashFreq.40=40MHz +d1_uno32.menu.FlashFreq.40.build.flash_freq=40m + +d1_uno32.menu.PartitionScheme.default=Default +d1_uno32.menu.PartitionScheme.default.build.partitions=default +d1_uno32.menu.PartitionScheme.no_ota=No OTA (Large APP) +d1_uno32.menu.PartitionScheme.no_ota.build.partitions=no_ota +d1_uno32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +d1_uno32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +d1_uno32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +d1_uno32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +d1_uno32.menu.CPUFreq.240=240MHz (WiFi/BT) +d1_uno32.menu.CPUFreq.240.build.f_cpu=240000000L +d1_uno32.menu.CPUFreq.160=160MHz (WiFi/BT) +d1_uno32.menu.CPUFreq.160.build.f_cpu=160000000L +d1_uno32.menu.CPUFreq.80=80MHz (WiFi/BT) +d1_uno32.menu.CPUFreq.80.build.f_cpu=80000000L +d1_uno32.menu.CPUFreq.40=40MHz (40MHz XTAL) +d1_uno32.menu.CPUFreq.40.build.f_cpu=40000000L +d1_uno32.menu.CPUFreq.26=26MHz (26MHz XTAL) +d1_uno32.menu.CPUFreq.26.build.f_cpu=26000000L +d1_uno32.menu.CPUFreq.20=20MHz (40MHz XTAL) +d1_uno32.menu.CPUFreq.20.build.f_cpu=20000000L +d1_uno32.menu.CPUFreq.13=13MHz (26MHz XTAL) +d1_uno32.menu.CPUFreq.13.build.f_cpu=13000000L +d1_uno32.menu.CPUFreq.10=10MHz (40MHz XTAL) +d1_uno32.menu.CPUFreq.10.build.f_cpu=10000000L + +d1_uno32.menu.UploadSpeed.921600=921600 +d1_uno32.menu.UploadSpeed.921600.upload.speed=921600 +d1_uno32.menu.UploadSpeed.115200=115200 +d1_uno32.menu.UploadSpeed.115200.upload.speed=115200 +d1_uno32.menu.UploadSpeed.256000.windows=256000 +d1_uno32.menu.UploadSpeed.256000.upload.speed=256000 +d1_uno32.menu.UploadSpeed.230400.windows.upload.speed=256000 +d1_uno32.menu.UploadSpeed.230400=230400 +d1_uno32.menu.UploadSpeed.230400.upload.speed=230400 +d1_uno32.menu.UploadSpeed.460800.linux=460800 +d1_uno32.menu.UploadSpeed.460800.macosx=460800 +d1_uno32.menu.UploadSpeed.460800.upload.speed=460800 +d1_uno32.menu.UploadSpeed.512000.windows=512000 +d1_uno32.menu.UploadSpeed.512000.upload.speed=512000 + +d1_uno32.menu.DebugLevel.none=None +d1_uno32.menu.DebugLevel.none.build.code_debug=0 +d1_uno32.menu.DebugLevel.error=Error +d1_uno32.menu.DebugLevel.error.build.code_debug=1 +d1_uno32.menu.DebugLevel.warn=Warn +d1_uno32.menu.DebugLevel.warn.build.code_debug=2 +d1_uno32.menu.DebugLevel.info=Info +d1_uno32.menu.DebugLevel.info.build.code_debug=3 +d1_uno32.menu.DebugLevel.debug=Debug +d1_uno32.menu.DebugLevel.debug.build.code_debug=4 +d1_uno32.menu.DebugLevel.verbose=Verbose +d1_uno32.menu.DebugLevel.verbose.build.code_debug=5 + +d1_uno32.menu.EraseFlash.none=Disabled +d1_uno32.menu.EraseFlash.none.upload.erase_cmd= +d1_uno32.menu.EraseFlash.all=Enabled +d1_uno32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +gpy.name=Pycom GPy + +gpy.bootloader.tool=esptool_py +gpy.bootloader.tool.default=esptool_py + +gpy.upload.tool=esptool_py +gpy.upload.tool.default=esptool_py +gpy.upload.tool.network=esp_ota + +gpy.upload.maximum_size=1310720 +gpy.upload.maximum_data_size=327680 +gpy.upload.flags= +gpy.upload.extra_flags= + +gpy.serial.disableDTR=true +gpy.serial.disableRTS=true + +gpy.build.tarch=xtensa +gpy.build.bootloader_addr=0x1000 +gpy.build.target=esp32 +gpy.build.mcu=esp32 +gpy.build.core=esp32 +gpy.build.variant=gpy +gpy.build.board=PYCOM_GPY + +gpy.build.f_cpu=240000000L +gpy.build.flash_mode=dio +gpy.build.flash_size=8MB +gpy.build.boot=dio +gpy.build.partitions=default + +gpy.menu.FlashFreq.80=80MHz +gpy.menu.FlashFreq.80.build.flash_freq=80m +gpy.menu.FlashFreq.40=40MHz +gpy.menu.FlashFreq.40.build.flash_freq=40m + +gpy.menu.UploadSpeed.921600=921600 +gpy.menu.UploadSpeed.921600.upload.speed=921600 +gpy.menu.UploadSpeed.115200=115200 +gpy.menu.UploadSpeed.115200.upload.speed=115200 +gpy.menu.UploadSpeed.256000.windows=256000 +gpy.menu.UploadSpeed.256000.upload.speed=256000 +gpy.menu.UploadSpeed.230400.windows.upload.speed=256000 +gpy.menu.UploadSpeed.230400=230400 +gpy.menu.UploadSpeed.230400.upload.speed=230400 +gpy.menu.UploadSpeed.460800.linux=460800 +gpy.menu.UploadSpeed.460800.macosx=460800 +gpy.menu.UploadSpeed.460800.upload.speed=460800 +gpy.menu.UploadSpeed.512000.windows=512000 +gpy.menu.UploadSpeed.512000.upload.speed=512000 + +gpy.menu.DebugLevel.none=None +gpy.menu.DebugLevel.none.build.code_debug=0 +gpy.menu.DebugLevel.error=Error +gpy.menu.DebugLevel.error.build.code_debug=1 +gpy.menu.DebugLevel.warn=Warn +gpy.menu.DebugLevel.warn.build.code_debug=2 +gpy.menu.DebugLevel.info=Info +gpy.menu.DebugLevel.info.build.code_debug=3 +gpy.menu.DebugLevel.debug=Debug +gpy.menu.DebugLevel.debug.build.code_debug=4 +gpy.menu.DebugLevel.verbose=Verbose +gpy.menu.DebugLevel.verbose.build.code_debug=5 + +gpy.menu.EraseFlash.none=Disabled +gpy.menu.EraseFlash.none.upload.erase_cmd= +gpy.menu.EraseFlash.all=Enabled +gpy.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +vintlabs-devkit-v1.name=VintLabs ESP32 Devkit + +vintlabs-devkit-v1.bootloader.tool=esptool_py +vintlabs-devkit-v1.bootloader.tool.default=esptool_py + +vintlabs-devkit-v1.upload.tool=esptool_py +vintlabs-devkit-v1.upload.tool.default=esptool_py +vintlabs-devkit-v1.upload.tool.network=esp_ota + +vintlabs-devkit-v1.upload.maximum_size=1310720 +vintlabs-devkit-v1.upload.maximum_data_size=327680 +vintlabs-devkit-v1.upload.flags= +vintlabs-devkit-v1.upload.extra_flags= + +vintlabs-devkit-v1.serial.disableDTR=true +vintlabs-devkit-v1.serial.disableRTS=true + +vintlabs-devkit-v1.build.tarch=xtensa +vintlabs-devkit-v1.build.bootloader_addr=0x1000 +vintlabs-devkit-v1.build.target=esp32 +vintlabs-devkit-v1.build.mcu=esp32 +vintlabs-devkit-v1.build.core=esp32 +vintlabs-devkit-v1.build.variant=vintlabsdevkitv1 +vintlabs-devkit-v1.build.board=ESP32_DEV + +vintlabs-devkit-v1.build.f_cpu=240000000L +vintlabs-devkit-v1.build.flash_mode=dio +vintlabs-devkit-v1.build.flash_size=4MB +vintlabs-devkit-v1.build.boot=dio +vintlabs-devkit-v1.build.partitions=default +vintlabs-devkit-v1.build.defines= + +vintlabs-devkit-v1.menu.FlashFreq.80=80MHz +vintlabs-devkit-v1.menu.FlashFreq.80.build.flash_freq=80m +vintlabs-devkit-v1.menu.FlashFreq.40=40MHz +vintlabs-devkit-v1.menu.FlashFreq.40.build.flash_freq=40m + +vintlabs-devkit-v1.menu.UploadSpeed.2000000=2000000 +vintlabs-devkit-v1.menu.UploadSpeed.2000000.upload.speed=2000000 +vintlabs-devkit-v1.menu.UploadSpeed.921600=921600 +vintlabs-devkit-v1.menu.UploadSpeed.921600.upload.speed=921600 +vintlabs-devkit-v1.menu.UploadSpeed.115200=115200 +vintlabs-devkit-v1.menu.UploadSpeed.115200.upload.speed=115200 +vintlabs-devkit-v1.menu.UploadSpeed.256000.windows=256000 +vintlabs-devkit-v1.menu.UploadSpeed.256000.upload.speed=256000 +vintlabs-devkit-v1.menu.UploadSpeed.230400.windows.upload.speed=256000 +vintlabs-devkit-v1.menu.UploadSpeed.230400=230400 +vintlabs-devkit-v1.menu.UploadSpeed.230400.upload.speed=230400 +vintlabs-devkit-v1.menu.UploadSpeed.460800.linux=460800 +vintlabs-devkit-v1.menu.UploadSpeed.460800.macosx=460800 +vintlabs-devkit-v1.menu.UploadSpeed.460800.upload.speed=460800 +vintlabs-devkit-v1.menu.UploadSpeed.512000.windows=512000 +vintlabs-devkit-v1.menu.UploadSpeed.512000.upload.speed=512000 + +vintlabs-devkit-v1.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.default.build.partitions=default +vintlabs-devkit-v1.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +vintlabs-devkit-v1.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +vintlabs-devkit-v1.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +vintlabs-devkit-v1.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +vintlabs-devkit-v1.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.minimal.build.partitions=minimal +vintlabs-devkit-v1.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.no_ota.build.partitions=no_ota +vintlabs-devkit-v1.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +vintlabs-devkit-v1.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +vintlabs-devkit-v1.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +vintlabs-devkit-v1.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +vintlabs-devkit-v1.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +vintlabs-devkit-v1.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +vintlabs-devkit-v1.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +vintlabs-devkit-v1.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +vintlabs-devkit-v1.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +vintlabs-devkit-v1.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.huge_app.build.partitions=huge_app +vintlabs-devkit-v1.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +vintlabs-devkit-v1.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +vintlabs-devkit-v1.menu.PartitionScheme.fatflash.build.partitions=ffat +vintlabs-devkit-v1.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +vintlabs-devkit-v1.menu.FlashSize.4M=4MB (32Mb) +vintlabs-devkit-v1.menu.FlashSize.4M.build.flash_size=4MB +vintlabs-devkit-v1.menu.FlashSize.8M=8MB (64Mb) +vintlabs-devkit-v1.menu.FlashSize.8M.build.flash_size=8MB +vintlabs-devkit-v1.menu.FlashSize.2M=2MB (16Mb) +vintlabs-devkit-v1.menu.FlashSize.2M.build.flash_size=2MB +vintlabs-devkit-v1.menu.FlashSize.16M=16MB (128Mb) +vintlabs-devkit-v1.menu.FlashSize.16M.build.flash_size=16MB + +vintlabs-devkit-v1.menu.DebugLevel.none=None +vintlabs-devkit-v1.menu.DebugLevel.none.build.code_debug=0 +vintlabs-devkit-v1.menu.DebugLevel.error=Error +vintlabs-devkit-v1.menu.DebugLevel.error.build.code_debug=1 +vintlabs-devkit-v1.menu.DebugLevel.warn=Warn +vintlabs-devkit-v1.menu.DebugLevel.warn.build.code_debug=2 +vintlabs-devkit-v1.menu.DebugLevel.info=Info +vintlabs-devkit-v1.menu.DebugLevel.info.build.code_debug=3 +vintlabs-devkit-v1.menu.DebugLevel.debug=Debug +vintlabs-devkit-v1.menu.DebugLevel.debug.build.code_debug=4 +vintlabs-devkit-v1.menu.DebugLevel.verbose=Verbose +vintlabs-devkit-v1.menu.DebugLevel.verbose.build.code_debug=5 + +vintlabs-devkit-v1.menu.EraseFlash.none=Disabled +vintlabs-devkit-v1.menu.EraseFlash.none.upload.erase_cmd= +vintlabs-devkit-v1.menu.EraseFlash.all=Enabled +vintlabs-devkit-v1.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +honeylemon.name=HONEYLemon + +honeylemon.bootloader.tool=esptool_py +honeylemon.bootloader.tool.default=esptool_py + +honeylemon.upload.tool=esptool_py +honeylemon.upload.tool.default=esptool_py +honeylemon.upload.tool.network=esp_ota + +honeylemon.upload.maximum_size=1310720 +honeylemon.upload.maximum_data_size=327680 +honeylemon.upload.flags= +honeylemon.upload.extra_flags= + +honeylemon.serial.disableDTR=true +honeylemon.serial.disableRTS=true + +honeylemon.build.tarch=xtensa +honeylemon.build.bootloader_addr=0x1000 +honeylemon.build.target=esp32 +honeylemon.build.mcu=esp32 +honeylemon.build.core=esp32 +honeylemon.build.variant=honeylemon +honeylemon.build.board=HONEYLEMON + +honeylemon.build.f_cpu=240000000L +honeylemon.build.flash_mode=dio +honeylemon.build.flash_size=4MB +honeylemon.build.boot=dio +honeylemon.build.partitions=default +honeylemon.build.defines= + +honeylemon.menu.FlashFreq.80=80MHz +honeylemon.menu.FlashFreq.80.build.flash_freq=80m +honeylemon.menu.FlashFreq.40=40MHz +honeylemon.menu.FlashFreq.40.build.flash_freq=40m + +honeylemon.menu.UploadSpeed.921600=921600 +honeylemon.menu.UploadSpeed.921600.upload.speed=921600 +honeylemon.menu.UploadSpeed.115200=115200 +honeylemon.menu.UploadSpeed.115200.upload.speed=115200 +honeylemon.menu.UploadSpeed.256000.windows=256000 +honeylemon.menu.UploadSpeed.256000.upload.speed=256000 +honeylemon.menu.UploadSpeed.230400.windows.upload.speed=256000 +honeylemon.menu.UploadSpeed.230400=230400 +honeylemon.menu.UploadSpeed.230400.upload.speed=230400 +honeylemon.menu.UploadSpeed.460800.linux=460800 +honeylemon.menu.UploadSpeed.460800.macosx=460800 +honeylemon.menu.UploadSpeed.460800.upload.speed=460800 +honeylemon.menu.UploadSpeed.512000.windows=512000 +honeylemon.menu.UploadSpeed.512000.upload.speed=512000 + +honeylemon.menu.DebugLevel.none=None +honeylemon.menu.DebugLevel.none.build.code_debug=0 +honeylemon.menu.DebugLevel.error=Error +honeylemon.menu.DebugLevel.error.build.code_debug=1 +honeylemon.menu.DebugLevel.warn=Warn +honeylemon.menu.DebugLevel.warn.build.code_debug=2 +honeylemon.menu.DebugLevel.info=Info +honeylemon.menu.DebugLevel.info.build.code_debug=3 +honeylemon.menu.DebugLevel.debug=Debug +honeylemon.menu.DebugLevel.debug.build.code_debug=4 +honeylemon.menu.DebugLevel.verbose=Verbose +honeylemon.menu.DebugLevel.verbose.build.code_debug=5 + +honeylemon.menu.EraseFlash.none=Disabled +honeylemon.menu.EraseFlash.none.upload.erase_cmd= +honeylemon.menu.EraseFlash.all=Enabled +honeylemon.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +mgbot-iotik32a.name=MGBOT IOTIK 32A + +mgbot-iotik32a.bootloader.tool=esptool_py +mgbot-iotik32a.bootloader.tool.default=esptool_py + +mgbot-iotik32a.upload.tool=esptool_py +mgbot-iotik32a.upload.tool.default=esptool_py +mgbot-iotik32a.upload.tool.network=esp_ota + +mgbot-iotik32a.upload.maximum_size=1310720 +mgbot-iotik32a.upload.maximum_data_size=327680 +mgbot-iotik32a.upload.flags= +mgbot-iotik32a.upload.extra_flags= + +mgbot-iotik32a.serial.disableDTR=true +mgbot-iotik32a.serial.disableRTS=true + +mgbot-iotik32a.build.tarch=xtensa +mgbot-iotik32a.build.bootloader_addr=0x1000 +mgbot-iotik32a.build.target=esp32 +mgbot-iotik32a.build.mcu=esp32 +mgbot-iotik32a.build.core=esp32 +mgbot-iotik32a.build.variant=mgbot-iotik32a +mgbot-iotik32a.build.board=MGBOT_IOTIK32A + +mgbot-iotik32a.build.f_cpu=240000000L +mgbot-iotik32a.build.flash_size=4MB +mgbot-iotik32a.build.flash_freq=40m +mgbot-iotik32a.build.flash_mode=dio +mgbot-iotik32a.build.boot=dio +mgbot-iotik32a.build.partitions=default +mgbot-iotik32a.build.defines= + +mgbot-iotik32a.menu.PSRAM.disabled=Disabled +mgbot-iotik32a.menu.PSRAM.disabled.build.defines= +mgbot-iotik32a.menu.PSRAM.disabled.build.extra_libs= +mgbot-iotik32a.menu.PSRAM.enabled=Enabled +mgbot-iotik32a.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +mgbot-iotik32a.menu.PSRAM.enabled.build.extra_libs= + +mgbot-iotik32a.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.default.build.partitions=default +mgbot-iotik32a.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +mgbot-iotik32a.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +mgbot-iotik32a.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +mgbot-iotik32a.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +mgbot-iotik32a.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.minimal.build.partitions=minimal +mgbot-iotik32a.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.no_ota.build.partitions=no_ota +mgbot-iotik32a.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +mgbot-iotik32a.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +mgbot-iotik32a.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +mgbot-iotik32a.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +mgbot-iotik32a.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +mgbot-iotik32a.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +mgbot-iotik32a.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +mgbot-iotik32a.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +mgbot-iotik32a.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +mgbot-iotik32a.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.huge_app.build.partitions=huge_app +mgbot-iotik32a.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +mgbot-iotik32a.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +mgbot-iotik32a.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +mgbot-iotik32a.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +mgbot-iotik32a.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +mgbot-iotik32a.menu.PartitionScheme.fatflash.build.partitions=ffat +mgbot-iotik32a.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +mgbot-iotik32a.menu.CPUFreq.240=240MHz (WiFi/BT) +mgbot-iotik32a.menu.CPUFreq.240.build.f_cpu=240000000L +mgbot-iotik32a.menu.CPUFreq.160=160MHz (WiFi/BT) +mgbot-iotik32a.menu.CPUFreq.160.build.f_cpu=160000000L +mgbot-iotik32a.menu.CPUFreq.80=80MHz (WiFi/BT) +mgbot-iotik32a.menu.CPUFreq.80.build.f_cpu=80000000L +mgbot-iotik32a.menu.CPUFreq.40=40MHz (40MHz XTAL) +mgbot-iotik32a.menu.CPUFreq.40.build.f_cpu=40000000L +mgbot-iotik32a.menu.CPUFreq.26=26MHz (26MHz XTAL) +mgbot-iotik32a.menu.CPUFreq.26.build.f_cpu=26000000L +mgbot-iotik32a.menu.CPUFreq.20=20MHz (40MHz XTAL) +mgbot-iotik32a.menu.CPUFreq.20.build.f_cpu=20000000L +mgbot-iotik32a.menu.CPUFreq.13=13MHz (26MHz XTAL) +mgbot-iotik32a.menu.CPUFreq.13.build.f_cpu=13000000L +mgbot-iotik32a.menu.CPUFreq.10=10MHz (40MHz XTAL) +mgbot-iotik32a.menu.CPUFreq.10.build.f_cpu=10000000L + +mgbot-iotik32a.menu.FlashMode.qio=QIO +mgbot-iotik32a.menu.FlashMode.qio.build.flash_mode=dio +mgbot-iotik32a.menu.FlashMode.qio.build.boot=qio +mgbot-iotik32a.menu.FlashMode.dio=DIO +mgbot-iotik32a.menu.FlashMode.dio.build.flash_mode=dio +mgbot-iotik32a.menu.FlashMode.dio.build.boot=dio + +mgbot-iotik32a.menu.FlashFreq.80=80MHz +mgbot-iotik32a.menu.FlashFreq.80.build.flash_freq=80m +mgbot-iotik32a.menu.FlashFreq.40=40MHz +mgbot-iotik32a.menu.FlashFreq.40.build.flash_freq=40m + +mgbot-iotik32a.menu.FlashSize.4M=4MB (32Mb) +mgbot-iotik32a.menu.FlashSize.4M.build.flash_size=4MB +mgbot-iotik32a.menu.FlashSize.8M=8MB (64Mb) +mgbot-iotik32a.menu.FlashSize.8M.build.flash_size=8MB +mgbot-iotik32a.menu.FlashSize.2M=2MB (16Mb) +mgbot-iotik32a.menu.FlashSize.2M.build.flash_size=2MB +mgbot-iotik32a.menu.FlashSize.16M=16MB (128Mb) +mgbot-iotik32a.menu.FlashSize.16M.build.flash_size=16MB + +mgbot-iotik32a.menu.UploadSpeed.921600=921600 +mgbot-iotik32a.menu.UploadSpeed.921600.upload.speed=921600 +mgbot-iotik32a.menu.UploadSpeed.115200=115200 +mgbot-iotik32a.menu.UploadSpeed.115200.upload.speed=115200 +mgbot-iotik32a.menu.UploadSpeed.256000.windows=256000 +mgbot-iotik32a.menu.UploadSpeed.256000.upload.speed=256000 +mgbot-iotik32a.menu.UploadSpeed.230400.windows.upload.speed=256000 +mgbot-iotik32a.menu.UploadSpeed.230400=230400 +mgbot-iotik32a.menu.UploadSpeed.230400.upload.speed=230400 +mgbot-iotik32a.menu.UploadSpeed.460800.linux=460800 +mgbot-iotik32a.menu.UploadSpeed.460800.macosx=460800 +mgbot-iotik32a.menu.UploadSpeed.460800.upload.speed=460800 +mgbot-iotik32a.menu.UploadSpeed.512000.windows=512000 +mgbot-iotik32a.menu.UploadSpeed.512000.upload.speed=512000 + +mgbot-iotik32a.menu.DebugLevel.none=None +mgbot-iotik32a.menu.DebugLevel.none.build.code_debug=0 +mgbot-iotik32a.menu.DebugLevel.error=Error +mgbot-iotik32a.menu.DebugLevel.error.build.code_debug=1 +mgbot-iotik32a.menu.DebugLevel.warn=Warn +mgbot-iotik32a.menu.DebugLevel.warn.build.code_debug=2 +mgbot-iotik32a.menu.DebugLevel.info=Info +mgbot-iotik32a.menu.DebugLevel.info.build.code_debug=3 +mgbot-iotik32a.menu.DebugLevel.debug=Debug +mgbot-iotik32a.menu.DebugLevel.debug.build.code_debug=4 +mgbot-iotik32a.menu.DebugLevel.verbose=Verbose +mgbot-iotik32a.menu.DebugLevel.verbose.build.code_debug=5 + +mgbot-iotik32a.menu.EraseFlash.none=Disabled +mgbot-iotik32a.menu.EraseFlash.none.upload.erase_cmd= +mgbot-iotik32a.menu.EraseFlash.all=Enabled +mgbot-iotik32a.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +mgbot-iotik32b.name=MGBOT IOTIK 32B + +mgbot-iotik32b.bootloader.tool=esptool_py +mgbot-iotik32b.bootloader.tool.default=esptool_py + +mgbot-iotik32b.upload.tool=esptool_py +mgbot-iotik32b.upload.tool.default=esptool_py +mgbot-iotik32b.upload.tool.network=esp_ota + +mgbot-iotik32b.upload.maximum_size=1310720 +mgbot-iotik32b.upload.maximum_data_size=327680 +mgbot-iotik32b.upload.flags= +mgbot-iotik32b.upload.extra_flags= + +mgbot-iotik32b.serial.disableDTR=true +mgbot-iotik32b.serial.disableRTS=true + +mgbot-iotik32b.build.tarch=xtensa +mgbot-iotik32b.build.bootloader_addr=0x1000 +mgbot-iotik32b.build.target=esp32 +mgbot-iotik32b.build.mcu=esp32 +mgbot-iotik32b.build.core=esp32 +mgbot-iotik32b.build.variant=mgbot-iotik32b +mgbot-iotik32b.build.board=MGBOT_IOTIK32B + +mgbot-iotik32b.build.f_cpu=240000000L +mgbot-iotik32b.build.flash_size=4MB +mgbot-iotik32b.build.flash_freq=40m +mgbot-iotik32b.build.flash_mode=dio +mgbot-iotik32b.build.boot=dio +mgbot-iotik32b.build.partitions=default +mgbot-iotik32b.build.defines= + +mgbot-iotik32b.menu.PSRAM.disabled=Disabled +mgbot-iotik32b.menu.PSRAM.disabled.build.defines= +mgbot-iotik32b.menu.PSRAM.disabled.build.extra_libs= +mgbot-iotik32b.menu.PSRAM.enabled=Enabled +mgbot-iotik32b.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +mgbot-iotik32b.menu.PSRAM.enabled.build.extra_libs= + +mgbot-iotik32b.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.default.build.partitions=default +mgbot-iotik32b.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +mgbot-iotik32b.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +mgbot-iotik32b.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +mgbot-iotik32b.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +mgbot-iotik32b.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.minimal.build.partitions=minimal +mgbot-iotik32b.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.no_ota.build.partitions=no_ota +mgbot-iotik32b.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +mgbot-iotik32b.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +mgbot-iotik32b.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +mgbot-iotik32b.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +mgbot-iotik32b.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +mgbot-iotik32b.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +mgbot-iotik32b.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +mgbot-iotik32b.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +mgbot-iotik32b.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +mgbot-iotik32b.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.huge_app.build.partitions=huge_app +mgbot-iotik32b.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +mgbot-iotik32b.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +mgbot-iotik32b.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +mgbot-iotik32b.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +mgbot-iotik32b.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +mgbot-iotik32b.menu.PartitionScheme.fatflash.build.partitions=ffat +mgbot-iotik32b.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +mgbot-iotik32b.menu.CPUFreq.240=240MHz (WiFi/BT) +mgbot-iotik32b.menu.CPUFreq.240.build.f_cpu=240000000L +mgbot-iotik32b.menu.CPUFreq.160=160MHz (WiFi/BT) +mgbot-iotik32b.menu.CPUFreq.160.build.f_cpu=160000000L +mgbot-iotik32b.menu.CPUFreq.80=80MHz (WiFi/BT) +mgbot-iotik32b.menu.CPUFreq.80.build.f_cpu=80000000L +mgbot-iotik32b.menu.CPUFreq.40=40MHz (40MHz XTAL) +mgbot-iotik32b.menu.CPUFreq.40.build.f_cpu=40000000L +mgbot-iotik32b.menu.CPUFreq.26=26MHz (26MHz XTAL) +mgbot-iotik32b.menu.CPUFreq.26.build.f_cpu=26000000L +mgbot-iotik32b.menu.CPUFreq.20=20MHz (40MHz XTAL) +mgbot-iotik32b.menu.CPUFreq.20.build.f_cpu=20000000L +mgbot-iotik32b.menu.CPUFreq.13=13MHz (26MHz XTAL) +mgbot-iotik32b.menu.CPUFreq.13.build.f_cpu=13000000L +mgbot-iotik32b.menu.CPUFreq.10=10MHz (40MHz XTAL) +mgbot-iotik32b.menu.CPUFreq.10.build.f_cpu=10000000L + +mgbot-iotik32b.menu.FlashMode.qio=QIO +mgbot-iotik32b.menu.FlashMode.qio.build.flash_mode=dio +mgbot-iotik32b.menu.FlashMode.qio.build.boot=qio +mgbot-iotik32b.menu.FlashMode.dio=DIO +mgbot-iotik32b.menu.FlashMode.dio.build.flash_mode=dio +mgbot-iotik32b.menu.FlashMode.dio.build.boot=dio + +mgbot-iotik32b.menu.FlashFreq.80=80MHz +mgbot-iotik32b.menu.FlashFreq.80.build.flash_freq=80m +mgbot-iotik32b.menu.FlashFreq.40=40MHz +mgbot-iotik32b.menu.FlashFreq.40.build.flash_freq=40m + +mgbot-iotik32b.menu.FlashSize.4M=4MB (32Mb) +mgbot-iotik32b.menu.FlashSize.4M.build.flash_size=4MB +mgbot-iotik32b.menu.FlashSize.8M=8MB (64Mb) +mgbot-iotik32b.menu.FlashSize.8M.build.flash_size=8MB +mgbot-iotik32b.menu.FlashSize.2M=2MB (16Mb) +mgbot-iotik32b.menu.FlashSize.2M.build.flash_size=2MB +mgbot-iotik32b.menu.FlashSize.16M=16MB (128Mb) +mgbot-iotik32b.menu.FlashSize.16M.build.flash_size=16MB + +mgbot-iotik32b.menu.UploadSpeed.921600=921600 +mgbot-iotik32b.menu.UploadSpeed.921600.upload.speed=921600 +mgbot-iotik32b.menu.UploadSpeed.115200=115200 +mgbot-iotik32b.menu.UploadSpeed.115200.upload.speed=115200 +mgbot-iotik32b.menu.UploadSpeed.256000.windows=256000 +mgbot-iotik32b.menu.UploadSpeed.256000.upload.speed=256000 +mgbot-iotik32b.menu.UploadSpeed.230400.windows.upload.speed=256000 +mgbot-iotik32b.menu.UploadSpeed.230400=230400 +mgbot-iotik32b.menu.UploadSpeed.230400.upload.speed=230400 +mgbot-iotik32b.menu.UploadSpeed.460800.linux=460800 +mgbot-iotik32b.menu.UploadSpeed.460800.macosx=460800 +mgbot-iotik32b.menu.UploadSpeed.460800.upload.speed=460800 +mgbot-iotik32b.menu.UploadSpeed.512000.windows=512000 +mgbot-iotik32b.menu.UploadSpeed.512000.upload.speed=512000 + +mgbot-iotik32b.menu.DebugLevel.none=None +mgbot-iotik32b.menu.DebugLevel.none.build.code_debug=0 +mgbot-iotik32b.menu.DebugLevel.error=Error +mgbot-iotik32b.menu.DebugLevel.error.build.code_debug=1 +mgbot-iotik32b.menu.DebugLevel.warn=Warn +mgbot-iotik32b.menu.DebugLevel.warn.build.code_debug=2 +mgbot-iotik32b.menu.DebugLevel.info=Info +mgbot-iotik32b.menu.DebugLevel.info.build.code_debug=3 +mgbot-iotik32b.menu.DebugLevel.debug=Debug +mgbot-iotik32b.menu.DebugLevel.debug.build.code_debug=4 +mgbot-iotik32b.menu.DebugLevel.verbose=Verbose +mgbot-iotik32b.menu.DebugLevel.verbose.build.code_debug=5 + +mgbot-iotik32b.menu.EraseFlash.none=Disabled +mgbot-iotik32b.menu.EraseFlash.none.upload.erase_cmd= +mgbot-iotik32b.menu.EraseFlash.all=Enabled +mgbot-iotik32b.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +piranha_esp-32.name=Piranha ESP-32 + +piranha_esp-32.bootloader.tool=esptool_py +piranha_esp-32.bootloader.tool.default=esptool_py + +piranha_esp-32.upload.tool=esptool_py +piranha_esp-32.upload.tool.default=esptool_py +piranha_esp-32.upload.tool.network=esp_ota + +piranha_esp-32.upload.maximum_size=1310720 +piranha_esp-32.upload.maximum_data_size=327680 +piranha_esp-32.upload.flags= +piranha_esp-32.upload.extra_flags= + +piranha_esp-32.serial.disableDTR=true +piranha_esp-32.serial.disableRTS=true + +piranha_esp-32.build.tarch=xtensa +piranha_esp-32.build.bootloader_addr=0x1000 +piranha_esp-32.build.target=esp32 +piranha_esp-32.build.mcu=esp32 +piranha_esp-32.build.core=esp32 +piranha_esp-32.build.variant=piranha_esp-32 +piranha_esp-32.build.board=Piranha + +piranha_esp-32.build.f_cpu=240000000L +piranha_esp-32.build.flash_mode=dio +piranha_esp-32.build.flash_size=4MB +piranha_esp-32.build.boot=dio +piranha_esp-32.build.partitions=default +piranha_esp-32.build.defines= + +piranha_esp-32.menu.PartitionScheme.default=Default +piranha_esp-32.menu.PartitionScheme.default.build.partitions=default +piranha_esp-32.menu.PartitionScheme.no_ota=No OTA (Large APP) +piranha_esp-32.menu.PartitionScheme.no_ota.build.partitions=no_ota +piranha_esp-32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +piranha_esp-32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +piranha_esp-32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +piranha_esp-32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +piranha_esp-32.menu.FlashFreq.80=80MHz +piranha_esp-32.menu.FlashFreq.80.build.flash_freq=80m +piranha_esp-32.menu.FlashFreq.40=40MHz +piranha_esp-32.menu.FlashFreq.40.build.flash_freq=40m + +piranha_esp-32.menu.UploadSpeed.921600=921600 +piranha_esp-32.menu.UploadSpeed.921600.upload.speed=921600 +piranha_esp-32.menu.UploadSpeed.115200=115200 +piranha_esp-32.menu.UploadSpeed.115200.upload.speed=115200 +piranha_esp-32.menu.UploadSpeed.256000.windows=256000 +piranha_esp-32.menu.UploadSpeed.256000.upload.speed=256000 +piranha_esp-32.menu.UploadSpeed.230400.windows.upload.speed=256000 +piranha_esp-32.menu.UploadSpeed.230400=230400 +piranha_esp-32.menu.UploadSpeed.230400.upload.speed=230400 +piranha_esp-32.menu.UploadSpeed.460800.linux=460800 +piranha_esp-32.menu.UploadSpeed.460800.macosx=460800 +piranha_esp-32.menu.UploadSpeed.460800.upload.speed=460800 +piranha_esp-32.menu.UploadSpeed.512000.windows=512000 +piranha_esp-32.menu.UploadSpeed.512000.upload.speed=512000 + +piranha_esp-32.menu.DebugLevel.none=None +piranha_esp-32.menu.DebugLevel.none.build.code_debug=0 +piranha_esp-32.menu.DebugLevel.error=Error +piranha_esp-32.menu.DebugLevel.error.build.code_debug=1 +piranha_esp-32.menu.DebugLevel.warn=Warn +piranha_esp-32.menu.DebugLevel.warn.build.code_debug=2 +piranha_esp-32.menu.DebugLevel.info=Info +piranha_esp-32.menu.DebugLevel.info.build.code_debug=3 +piranha_esp-32.menu.DebugLevel.debug=Debug +piranha_esp-32.menu.DebugLevel.debug.build.code_debug=4 +piranha_esp-32.menu.DebugLevel.verbose=Verbose +piranha_esp-32.menu.DebugLevel.verbose.build.code_debug=5 + +piranha_esp-32.menu.EraseFlash.none=Disabled +piranha_esp-32.menu.EraseFlash.none.upload.erase_cmd= +piranha_esp-32.menu.EraseFlash.all=Enabled +piranha_esp-32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +metro_esp-32.name=Metro ESP-32 + +metro_esp-32.bootloader.tool=esptool_py +metro_esp-32.bootloader.tool.default=esptool_py + +metro_esp-32.upload.tool=esptool_py +metro_esp-32.upload.tool.default=esptool_py +metro_esp-32.upload.tool.network=esp_ota + +metro_esp-32.upload.maximum_size=1310720 +metro_esp-32.upload.maximum_data_size=327680 +metro_esp-32.upload.flags= +metro_esp-32.upload.extra_flags= + +metro_esp-32.serial.disableDTR=true +metro_esp-32.serial.disableRTS=true + +metro_esp-32.build.tarch=xtensa +metro_esp-32.build.bootloader_addr=0x1000 +metro_esp-32.build.target=esp32 +metro_esp-32.build.mcu=esp32 +metro_esp-32.build.core=esp32 +metro_esp-32.build.variant=metro_esp-32 +metro_esp-32.build.board=Metro + +metro_esp-32.build.f_cpu=240000000L +metro_esp-32.build.flash_mode=dio +metro_esp-32.build.flash_size=4MB +metro_esp-32.build.boot=dio +metro_esp-32.build.partitions=default +metro_esp-32.build.defines= + +metro_esp-32.menu.PartitionScheme.default=Default +metro_esp-32.menu.PartitionScheme.default.build.partitions=default +metro_esp-32.menu.PartitionScheme.no_ota=No OTA (Large APP) +metro_esp-32.menu.PartitionScheme.no_ota.build.partitions=no_ota +metro_esp-32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +metro_esp-32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +metro_esp-32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +metro_esp-32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +metro_esp-32.menu.FlashFreq.80=80MHz +metro_esp-32.menu.FlashFreq.80.build.flash_freq=80m +metro_esp-32.menu.FlashFreq.40=40MHz +metro_esp-32.menu.FlashFreq.40.build.flash_freq=40m + +metro_esp-32.menu.UploadSpeed.921600=921600 +metro_esp-32.menu.UploadSpeed.921600.upload.speed=921600 +metro_esp-32.menu.UploadSpeed.115200=115200 +metro_esp-32.menu.UploadSpeed.115200.upload.speed=115200 +metro_esp-32.menu.UploadSpeed.256000.windows=256000 +metro_esp-32.menu.UploadSpeed.256000.upload.speed=256000 +metro_esp-32.menu.UploadSpeed.230400.windows.upload.speed=256000 +metro_esp-32.menu.UploadSpeed.230400=230400 +metro_esp-32.menu.UploadSpeed.230400.upload.speed=230400 +metro_esp-32.menu.UploadSpeed.460800.linux=460800 +metro_esp-32.menu.UploadSpeed.460800.macosx=460800 +metro_esp-32.menu.UploadSpeed.460800.upload.speed=460800 +metro_esp-32.menu.UploadSpeed.512000.windows=512000 +metro_esp-32.menu.UploadSpeed.512000.upload.speed=512000 + +metro_esp-32.menu.DebugLevel.none=None +metro_esp-32.menu.DebugLevel.none.build.code_debug=0 +metro_esp-32.menu.DebugLevel.error=Error +metro_esp-32.menu.DebugLevel.error.build.code_debug=1 +metro_esp-32.menu.DebugLevel.warn=Warn +metro_esp-32.menu.DebugLevel.warn.build.code_debug=2 +metro_esp-32.menu.DebugLevel.info=Info +metro_esp-32.menu.DebugLevel.info.build.code_debug=3 +metro_esp-32.menu.DebugLevel.debug=Debug +metro_esp-32.menu.DebugLevel.debug.build.code_debug=4 +metro_esp-32.menu.DebugLevel.verbose=Verbose +metro_esp-32.menu.DebugLevel.verbose.build.code_debug=5 + +metro_esp-32.menu.EraseFlash.none=Disabled +metro_esp-32.menu.EraseFlash.none.upload.erase_cmd= +metro_esp-32.menu.EraseFlash.all=Enabled +metro_esp-32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sensesiot_weizen.name=Senses's WEIZEN + +sensesiot_weizen.bootloader.tool=esptool_py +sensesiot_weizen.bootloader.tool.default=esptool_py + +sensesiot_weizen.upload.tool=esptool_py +sensesiot_weizen.upload.tool.default=esptool_py +sensesiot_weizen.upload.tool.network=esp_ota + +sensesiot_weizen.upload.maximum_size=1310720 +sensesiot_weizen.upload.maximum_data_size=327680 +sensesiot_weizen.upload.flags= +sensesiot_weizen.upload.extra_flags= + +sensesiot_weizen.serial.disableDTR=true +sensesiot_weizen.serial.disableRTS=true + +sensesiot_weizen.build.tarch=xtensa +sensesiot_weizen.build.bootloader_addr=0x1000 +sensesiot_weizen.build.target=esp32 +sensesiot_weizen.build.mcu=esp32 +sensesiot_weizen.build.core=esp32 +sensesiot_weizen.build.variant=esp32 +sensesiot_weizen.build.board=sensesiot_weizen + +sensesiot_weizen.build.f_cpu=240000000L +sensesiot_weizen.build.flash_mode=dio +sensesiot_weizen.build.flash_size=4MB +sensesiot_weizen.build.boot=dio +sensesiot_weizen.build.partitions=default +sensesiot_weizen.build.defines= + +sensesiot_weizen.menu.FlashFreq.80=80MHz +sensesiot_weizen.menu.FlashFreq.80.build.flash_freq=80m +sensesiot_weizen.menu.FlashFreq.40=40MHz +sensesiot_weizen.menu.FlashFreq.40.build.flash_freq=40m + +sensesiot_weizen.menu.UploadSpeed.921600=921600 +sensesiot_weizen.menu.UploadSpeed.921600.upload.speed=921600 +sensesiot_weizen.menu.UploadSpeed.115200=115200 +sensesiot_weizen.menu.UploadSpeed.115200.upload.speed=115200 +sensesiot_weizen.menu.UploadSpeed.256000.windows=256000 +sensesiot_weizen.menu.UploadSpeed.256000.upload.speed=256000 +sensesiot_weizen.menu.UploadSpeed.230400.windows.upload.speed=256000 +sensesiot_weizen.menu.UploadSpeed.230400=230400 +sensesiot_weizen.menu.UploadSpeed.230400.upload.speed=230400 +sensesiot_weizen.menu.UploadSpeed.460800.linux=460800 +sensesiot_weizen.menu.UploadSpeed.460800.macosx=460800 +sensesiot_weizen.menu.UploadSpeed.460800.upload.speed=460800 +sensesiot_weizen.menu.UploadSpeed.512000.windows=512000 +sensesiot_weizen.menu.UploadSpeed.512000.upload.speed=512000 + +sensesiot_weizen.menu.DebugLevel.none=None +sensesiot_weizen.menu.DebugLevel.none.build.code_debug=0 +sensesiot_weizen.menu.DebugLevel.error=Error +sensesiot_weizen.menu.DebugLevel.error.build.code_debug=1 +sensesiot_weizen.menu.DebugLevel.warn=Warn +sensesiot_weizen.menu.DebugLevel.warn.build.code_debug=2 +sensesiot_weizen.menu.DebugLevel.info=Info +sensesiot_weizen.menu.DebugLevel.info.build.code_debug=3 +sensesiot_weizen.menu.DebugLevel.debug=Debug +sensesiot_weizen.menu.DebugLevel.debug.build.code_debug=4 +sensesiot_weizen.menu.DebugLevel.verbose=Verbose +sensesiot_weizen.menu.DebugLevel.verbose.build.code_debug=5 + +sensesiot_weizen.menu.EraseFlash.none=Disabled +sensesiot_weizen.menu.EraseFlash.none.upload.erase_cmd= +sensesiot_weizen.menu.EraseFlash.all=Enabled +sensesiot_weizen.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +kits-edu.name=KITS ESP32 EDU + +kits-edu.bootloader.tool=esptool_py +kits-edu.bootloader.tool.default=esptool_py + +kits-edu.upload.tool=esptool_py +kits-edu.upload.tool.default=esptool_py +kits-edu.upload.tool.network=esp_ota + +kits-edu.upload.maximum_size=1310720 +kits-edu.upload.maximum_data_size=327680 +kits-edu.upload.wait_for_upload_port=true +kits-edu.upload.flags= +kits-edu.upload.extra_flags= + +kits-edu.serial.disableDTR=true +kits-edu.serial.disableRTS=true + +kits-edu.build.tarch=xtensa +kits-edu.build.bootloader_addr=0x1000 +kits-edu.build.target=esp32 +kits-edu.build.mcu=esp32 +kits-edu.build.core=esp32 +kits-edu.build.variant=pico32 +kits-edu.build.board=ESP32_PICO + +kits-edu.build.f_cpu=240000000L +kits-edu.build.flash_size=4MB +kits-edu.build.flash_freq=80m +kits-edu.build.flash_mode=dio +kits-edu.build.boot=dio +kits-edu.build.partitions=default +kits-edu.build.defines= + +kits-edu.menu.PartitionScheme.default=Default +kits-edu.menu.PartitionScheme.default.build.partitions=default +kits-edu.menu.PartitionScheme.no_ota=No OTA (Large APP) +kits-edu.menu.PartitionScheme.no_ota.build.partitions=no_ota +kits-edu.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +kits-edu.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +kits-edu.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +kits-edu.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +kits-edu.menu.UploadSpeed.921600=921600 +kits-edu.menu.UploadSpeed.921600.upload.speed=921600 +kits-edu.menu.UploadSpeed.115200=115200 +kits-edu.menu.UploadSpeed.115200.upload.speed=115200 +kits-edu.menu.UploadSpeed.256000.windows=256000 +kits-edu.menu.UploadSpeed.256000.upload.speed=256000 +kits-edu.menu.UploadSpeed.230400.windows.upload.speed=256000 +kits-edu.menu.UploadSpeed.230400=230400 +kits-edu.menu.UploadSpeed.230400.upload.speed=230400 +kits-edu.menu.UploadSpeed.460800.linux=460800 +kits-edu.menu.UploadSpeed.460800.macosx=460800 +kits-edu.menu.UploadSpeed.460800.upload.speed=460800 +kits-edu.menu.UploadSpeed.512000.windows=512000 +kits-edu.menu.UploadSpeed.512000.upload.speed=512000 + +kits-edu.menu.DebugLevel.none=None +kits-edu.menu.DebugLevel.none.build.code_debug=0 +kits-edu.menu.DebugLevel.error=Error +kits-edu.menu.DebugLevel.error.build.code_debug=1 +kits-edu.menu.DebugLevel.warn=Warn +kits-edu.menu.DebugLevel.warn.build.code_debug=2 +kits-edu.menu.DebugLevel.info=Info +kits-edu.menu.DebugLevel.info.build.code_debug=3 +kits-edu.menu.DebugLevel.debug=Debug +kits-edu.menu.DebugLevel.debug.build.code_debug=4 +kits-edu.menu.DebugLevel.verbose=Verbose +kits-edu.menu.DebugLevel.verbose.build.code_debug=5 + +kits-edu.menu.EraseFlash.none=Disabled +kits-edu.menu.EraseFlash.none.upload.erase_cmd= +kits-edu.menu.EraseFlash.all=Enabled +kits-edu.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +mPython.name=Labplus mPython +mPython.bootloader.tool=esptool_py +mPython.bootloader.tool.default=esptool_py + +mPython.upload.tool=esptool_py +mPython.upload.tool.default=esptool_py +mPython.upload.tool.network=esp_ota + +mPython.upload.maximum_size=1310720 +mPython.upload.maximum_data_size=327680 +mPython.upload.flags= +mPython.upload.extra_flags= + +mPython.serial.disableDTR=true +mPython.serial.disableRTS=true + +mPython.build.tarch=xtensa +mPython.build.bootloader_addr=0x1000 +mPython.build.target=esp32 +mPython.build.mcu=esp32 +mPython.build.core=esp32 +mPython.build.variant=mpython +mPython.build.board=ESP32_DEV + +mPython.build.f_cpu=240000000L +mPython.build.flash_size=8MB +mPython.build.flash_freq=40m +mPython.build.flash_mode=dio +mPython.build.boot=dio +mPython.build.partitions=huge_app +mPython.build.defines= + +mPython.menu.PSRAM.disabled=Disabled +mPython.menu.PSRAM.disabled.build.defines= +mPython.menu.PSRAM.disabled.build.extra_libs= +mPython.menu.PSRAM.enabled=Enabled +mPython.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +mPython.menu.PSRAM.enabled.build.extra_libs= + +mPython.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +mPython.menu.PartitionScheme.huge_app.build.partitions=huge_app +mPython.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +mPython.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +mPython.menu.PartitionScheme.default.build.partitions=default +mPython.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +mPython.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +mPython.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +mPython.menu.PartitionScheme.minimal.build.partitions=minimal +mPython.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +mPython.menu.PartitionScheme.no_ota.build.partitions=no_ota +mPython.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +mPython.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +mPython.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +mPython.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +mPython.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +mPython.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +mPython.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +mPython.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +mPython.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +mPython.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +mPython.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +mPython.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +mPython.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +mPython.menu.CPUFreq.240=240MHz (WiFi/BT) +mPython.menu.CPUFreq.240.build.f_cpu=240000000L + +mPython.menu.FlashMode.qio=QIO +mPython.menu.FlashMode.qio.build.flash_mode=dio +mPython.menu.FlashMode.qio.build.boot=qio +mPython.menu.FlashMode.dio=DIO +mPython.menu.FlashMode.dio.build.flash_mode=dio +mPython.menu.FlashMode.dio.build.boot=dio + +mPython.menu.FlashFreq.80=80MHz +mPython.menu.FlashFreq.80.build.flash_freq=80m +mPython.menu.FlashFreq.40=40MHz +mPython.menu.FlashFreq.40.build.flash_freq=40m + +mPython.menu.FlashSize.8M=8MB (64Mb) +mPython.menu.FlashSize.8M.build.flash_size=8MB + +mPython.menu.UploadSpeed.921600=921600 +mPython.menu.UploadSpeed.921600.upload.speed=921600 +mPython.menu.UploadSpeed.115200=115200 +mPython.menu.UploadSpeed.115200.upload.speed=115200 +mPython.menu.UploadSpeed.256000.windows=256000 +mPython.menu.UploadSpeed.256000.upload.speed=256000 +mPython.menu.UploadSpeed.230400.windows.upload.speed=256000 +mPython.menu.UploadSpeed.230400=230400 +mPython.menu.UploadSpeed.230400.upload.speed=230400 +mPython.menu.UploadSpeed.460800.linux=460800 +mPython.menu.UploadSpeed.460800.macosx=460800 +mPython.menu.UploadSpeed.460800.upload.speed=460800 +mPython.menu.UploadSpeed.512000.windows=512000 +mPython.menu.UploadSpeed.512000.upload.speed=512000 + +mPython.menu.DebugLevel.none=None +mPython.menu.DebugLevel.none.build.code_debug=0 +mPython.menu.DebugLevel.error=Error +mPython.menu.DebugLevel.error.build.code_debug=1 +mPython.menu.DebugLevel.warn=Warn +mPython.menu.DebugLevel.warn.build.code_debug=2 +mPython.menu.DebugLevel.info=Info +mPython.menu.DebugLevel.info.build.code_debug=3 +mPython.menu.DebugLevel.debug=Debug +mPython.menu.DebugLevel.debug.build.code_debug=4 +mPython.menu.DebugLevel.verbose=Verbose +mPython.menu.DebugLevel.verbose.build.code_debug=5 + +mPython.menu.EraseFlash.none=Disabled +mPython.menu.EraseFlash.none.upload.erase_cmd= +mPython.menu.EraseFlash.all=Enabled +mPython.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +OpenKB.name=INEX OpenKB + +OpenKB.bootloader.tool=esptool_py +OpenKB.bootloader.tool.default=esptool_py + +OpenKB.upload.tool=esptool_py +OpenKB.upload.tool.default=esptool_py +OpenKB.upload.tool.network=esp_ota + +OpenKB.upload.maximum_size=1310720 +OpenKB.upload.maximum_data_size=327680 +OpenKB.upload.wait_for_upload_port=true +OpenKB.upload.flags= +OpenKB.upload.extra_flags= + +OpenKB.serial.disableDTR=true +OpenKB.serial.disableRTS=true + +OpenKB.build.tarch=xtensa +OpenKB.build.bootloader_addr=0x1000 +OpenKB.build.target=esp32 +OpenKB.build.mcu=esp32 +OpenKB.build.core=esp32 +OpenKB.build.variant=openkb +OpenKB.build.board=openkb + +OpenKB.build.f_cpu=240000000L +OpenKB.build.flash_mode=dio +OpenKB.build.flash_size=4MB +OpenKB.build.boot=dio +OpenKB.build.partitions=default +OpenKB.build.defines= + +OpenKB.menu.FlashFreq.80=80MHz +OpenKB.menu.FlashFreq.80.build.flash_freq=80m +OpenKB.menu.FlashFreq.40=40MHz +OpenKB.menu.FlashFreq.40.build.flash_freq=40m + +OpenKB.menu.UploadSpeed.921600=921600 +OpenKB.menu.UploadSpeed.921600.upload.speed=921600 +OpenKB.menu.UploadSpeed.115200=115200 +OpenKB.menu.UploadSpeed.115200.upload.speed=115200 +OpenKB.menu.UploadSpeed.256000.windows=256000 +OpenKB.menu.UploadSpeed.256000.upload.speed=256000 +OpenKB.menu.UploadSpeed.230400.windows.upload.speed=256000 +OpenKB.menu.UploadSpeed.230400=230400 +OpenKB.menu.UploadSpeed.230400.upload.speed=230400 +OpenKB.menu.UploadSpeed.460800.linux=460800 +OpenKB.menu.UploadSpeed.460800.macosx=460800 +OpenKB.menu.UploadSpeed.460800.upload.speed=460800 +OpenKB.menu.UploadSpeed.512000.windows=512000 +OpenKB.menu.UploadSpeed.512000.upload.speed=512000 + +OpenKB.menu.DebugLevel.none=None +OpenKB.menu.DebugLevel.none.build.code_debug=0 +OpenKB.menu.DebugLevel.error=Error +OpenKB.menu.DebugLevel.error.build.code_debug=1 +OpenKB.menu.DebugLevel.warn=Warn +OpenKB.menu.DebugLevel.warn.build.code_debug=2 +OpenKB.menu.DebugLevel.info=Info +OpenKB.menu.DebugLevel.info.build.code_debug=3 +OpenKB.menu.DebugLevel.debug=Debug +OpenKB.menu.DebugLevel.debug.build.code_debug=4 +OpenKB.menu.DebugLevel.verbose=Verbose +OpenKB.menu.DebugLevel.verbose.build.code_debug=5 + +OpenKB.menu.EraseFlash.none=Disabled +OpenKB.menu.EraseFlash.none.upload.erase_cmd= +OpenKB.menu.EraseFlash.all=Enabled +OpenKB.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wifiduino32.name=WiFiduino32 + +wifiduino32.bootloader.tool=esptool_py +wifiduino32.bootloader.tool.default=esptool_py + +wifiduino32.upload.tool=esptool_py +wifiduino32.upload.tool.default=esptool_py +wifiduino32.upload.tool.network=esp_ota + +wifiduino32.upload.maximum_size=1310720 +wifiduino32.upload.maximum_data_size=327680 +wifiduino32.upload.wait_for_upload_port=true +wifiduino32.upload.flags= +wifiduino32.upload.extra_flags= + +wifiduino32.serial.disableDTR=true +wifiduino32.serial.disableRTS=true + +wifiduino32.build.tarch=xtensa +wifiduino32.build.bootloader_addr=0x1000 +wifiduino32.build.target=esp32 +wifiduino32.build.mcu=esp32 +wifiduino32.build.core=esp32 +wifiduino32.build.variant=wifiduino32 +wifiduino32.build.board=Wifiduino32 + +wifiduino32.build.f_cpu=240000000L +wifiduino32.build.flash_mode=dio +wifiduino32.build.flash_size=4MB +wifiduino32.build.boot=dio +wifiduino32.build.partitions=default +wifiduino32.build.defines= + +wifiduino32.menu.PartitionScheme.default=Default +wifiduino32.menu.PartitionScheme.default.build.partitions=default +wifiduino32.menu.PartitionScheme.no_ota=No OTA (Large APP) +wifiduino32.menu.PartitionScheme.no_ota.build.partitions=no_ota +wifiduino32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +wifiduino32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +wifiduino32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +wifiduino32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +wifiduino32.menu.FlashFreq.80=80MHz +wifiduino32.menu.FlashFreq.80.build.flash_freq=80m +wifiduino32.menu.FlashFreq.40=40MHz +wifiduino32.menu.FlashFreq.40.build.flash_freq=40m + +wifiduino32.menu.UploadSpeed.921600=921600 +wifiduino32.menu.UploadSpeed.921600.upload.speed=921600 +wifiduino32.menu.UploadSpeed.115200=115200 +wifiduino32.menu.UploadSpeed.115200.upload.speed=115200 +wifiduino32.menu.UploadSpeed.256000.windows=256000 +wifiduino32.menu.UploadSpeed.256000.upload.speed=256000 +wifiduino32.menu.UploadSpeed.230400.windows.upload.speed=256000 +wifiduino32.menu.UploadSpeed.230400=230400 +wifiduino32.menu.UploadSpeed.230400.upload.speed=230400 +wifiduino32.menu.UploadSpeed.460800.linux=460800 +wifiduino32.menu.UploadSpeed.460800.macosx=460800 +wifiduino32.menu.UploadSpeed.460800.upload.speed=460800 +wifiduino32.menu.UploadSpeed.512000.windows=512000 +wifiduino32.menu.UploadSpeed.512000.upload.speed=512000 + +wifiduino32.menu.DebugLevel.none=None +wifiduino32.menu.DebugLevel.none.build.code_debug=0 +wifiduino32.menu.DebugLevel.error=Error +wifiduino32.menu.DebugLevel.error.build.code_debug=1 +wifiduino32.menu.DebugLevel.warn=Warn +wifiduino32.menu.DebugLevel.warn.build.code_debug=2 +wifiduino32.menu.DebugLevel.info=Info +wifiduino32.menu.DebugLevel.info.build.code_debug=3 +wifiduino32.menu.DebugLevel.debug=Debug +wifiduino32.menu.DebugLevel.debug.build.code_debug=4 +wifiduino32.menu.DebugLevel.verbose=Verbose +wifiduino32.menu.DebugLevel.verbose.build.code_debug=5 + +wifiduino32.menu.EraseFlash.none=Disabled +wifiduino32.menu.EraseFlash.none.upload.erase_cmd= +wifiduino32.menu.EraseFlash.all=Enabled +wifiduino32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wifiduino32c3.name=WiFiduinoV2 + +wifiduino32c3.bootloader.tool=esptool_py +wifiduino32c3.bootloader.tool.default=esptool_py + +wifiduino32c3.upload.tool=esptool_py +wifiduino32c3.upload.tool.default=esptool_py +wifiduino32c3.upload.tool.network=esp_ota + +wifiduino32c3.upload.maximum_size=1310720 +wifiduino32c3.upload.maximum_data_size=327680 +wifiduino32c3.upload.flags= +wifiduino32c3.upload.extra_flags= +wifiduino32c3.upload.use_1200bps_touch=false +wifiduino32c3.upload.wait_for_upload_port=false + +wifiduino32c3.serial.disableDTR=false +wifiduino32c3.serial.disableRTS=false + +wifiduino32c3.build.tarch=riscv32 +wifiduino32c3.build.target=esp +wifiduino32c3.build.mcu=esp32c3 +wifiduino32c3.build.core=esp32 +wifiduino32c3.build.variant=wifiduinov2 +wifiduino32c3.build.board=WIFIDUINOV2 +wifiduino32c3.build.bootloader_addr=0x0 + +wifiduino32c3.build.cdc_on_boot=0 +wifiduino32c3.build.f_cpu=160000000L +wifiduino32c3.build.flash_size=4MB +wifiduino32c3.build.flash_freq=80m +wifiduino32c3.build.flash_mode=dio +wifiduino32c3.build.boot=dio +wifiduino32c3.build.partitions=no_ota +wifiduino32c3.build.defines= + +wifiduino32c3.menu.CDCOnBoot.default=Disabled +wifiduino32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +wifiduino32c3.menu.CDCOnBoot.cdc=Enabled +wifiduino32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +wifiduino32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +wifiduino32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +wifiduino32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +wifiduino32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +wifiduino32c3.menu.PartitionScheme.default.build.partitions=default +wifiduino32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +wifiduino32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +wifiduino32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +wifiduino32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +wifiduino32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +wifiduino32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +wifiduino32c3.menu.PartitionScheme.minimal.build.partitions=minimal +wifiduino32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +wifiduino32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +wifiduino32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +wifiduino32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +wifiduino32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +wifiduino32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +wifiduino32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +wifiduino32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +wifiduino32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +wifiduino32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +wifiduino32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +wifiduino32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +wifiduino32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +wifiduino32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +wifiduino32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +wifiduino32c3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +wifiduino32c3.menu.PartitionScheme.fatflash.build.partitions=ffat +wifiduino32c3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +wifiduino32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB +wifiduino32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +wifiduino32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +wifiduino32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +wifiduino32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +wifiduino32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +wifiduino32c3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +wifiduino32c3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +wifiduino32c3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +wifiduino32c3.menu.CPUFreq.160=160MHz (WiFi) +wifiduino32c3.menu.CPUFreq.160.build.f_cpu=160000000L +wifiduino32c3.menu.CPUFreq.80=80MHz (WiFi) +wifiduino32c3.menu.CPUFreq.80.build.f_cpu=80000000L +wifiduino32c3.menu.CPUFreq.40=40MHz +wifiduino32c3.menu.CPUFreq.40.build.f_cpu=40000000L +wifiduino32c3.menu.CPUFreq.20=20MHz +wifiduino32c3.menu.CPUFreq.20.build.f_cpu=20000000L +wifiduino32c3.menu.CPUFreq.10=10MHz +wifiduino32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +wifiduino32c3.menu.FlashMode.dio=DIO +wifiduino32c3.menu.FlashMode.dio.build.flash_mode=dio +wifiduino32c3.menu.FlashMode.dio.build.boot=dio +wifiduino32c3.menu.FlashMode.qio=QIO +wifiduino32c3.menu.FlashMode.qio.build.flash_mode=dio +wifiduino32c3.menu.FlashMode.qio.build.boot=qio + +wifiduino32c3.menu.FlashFreq.80=80MHz +wifiduino32c3.menu.FlashFreq.80.build.flash_freq=80m +wifiduino32c3.menu.FlashFreq.40=40MHz +wifiduino32c3.menu.FlashFreq.40.build.flash_freq=40m + +wifiduino32c3.menu.FlashSize.4M=4MB (32Mb) +wifiduino32c3.menu.FlashSize.4M.build.flash_size=4MB +wifiduino32c3.menu.FlashSize.8M=8MB (64Mb) +wifiduino32c3.menu.FlashSize.8M.build.flash_size=8MB +wifiduino32c3.menu.FlashSize.2M=2MB (16Mb) +wifiduino32c3.menu.FlashSize.2M.build.flash_size=2MB +wifiduino32c3.menu.FlashSize.16M=16MB (128Mb) +wifiduino32c3.menu.FlashSize.16M.build.flash_size=16MB + +wifiduino32c3.menu.UploadSpeed.921600=921600 +wifiduino32c3.menu.UploadSpeed.921600.upload.speed=921600 +wifiduino32c3.menu.UploadSpeed.115200=115200 +wifiduino32c3.menu.UploadSpeed.115200.upload.speed=115200 +wifiduino32c3.menu.UploadSpeed.256000.windows=256000 +wifiduino32c3.menu.UploadSpeed.256000.upload.speed=256000 +wifiduino32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +wifiduino32c3.menu.UploadSpeed.230400=230400 +wifiduino32c3.menu.UploadSpeed.230400.upload.speed=230400 +wifiduino32c3.menu.UploadSpeed.460800.linux=460800 +wifiduino32c3.menu.UploadSpeed.460800.macosx=460800 +wifiduino32c3.menu.UploadSpeed.460800.upload.speed=460800 +wifiduino32c3.menu.UploadSpeed.512000.windows=512000 +wifiduino32c3.menu.UploadSpeed.512000.upload.speed=512000 + +wifiduino32c3.menu.DebugLevel.none=None +wifiduino32c3.menu.DebugLevel.none.build.code_debug=0 +wifiduino32c3.menu.DebugLevel.error=Error +wifiduino32c3.menu.DebugLevel.error.build.code_debug=1 +wifiduino32c3.menu.DebugLevel.warn=Warn +wifiduino32c3.menu.DebugLevel.warn.build.code_debug=2 +wifiduino32c3.menu.DebugLevel.info=Info +wifiduino32c3.menu.DebugLevel.info.build.code_debug=3 +wifiduino32c3.menu.DebugLevel.debug=Debug +wifiduino32c3.menu.DebugLevel.debug.build.code_debug=4 +wifiduino32c3.menu.DebugLevel.verbose=Verbose +wifiduino32c3.menu.DebugLevel.verbose.build.code_debug=5 + +wifiduino32c3.menu.EraseFlash.none=Disabled +wifiduino32c3.menu.EraseFlash.none.upload.erase_cmd= +wifiduino32c3.menu.EraseFlash.all=Enabled +wifiduino32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +wifiduino32s3.name=WiFiduino32S3 + +wifiduino32s3.bootloader.tool=esptool_py +wifiduino32s3.bootloader.tool.default=esptool_py + +wifiduino32s3.upload.tool=esptool_py +wifiduino32s3.upload.tool.default=esptool_py +wifiduino32s3.upload.tool.network=esp_ota + +wifiduino32s3.upload.maximum_size=1310720 +wifiduino32s3.upload.maximum_data_size=327680 +wifiduino32s3.upload.flags= +wifiduino32s3.upload.extra_flags= +wifiduino32s3.upload.use_1200bps_touch=false +wifiduino32s3.upload.wait_for_upload_port=false + +wifiduino32s3.serial.disableDTR=false +wifiduino32s3.serial.disableRTS=false + +wifiduino32s3.build.tarch=xtensa +wifiduino32s3.build.bootloader_addr=0x0 +wifiduino32s3.build.target=esp32s3 +wifiduino32s3.build.mcu=esp32s3 +wifiduino32s3.build.core=esp32 +wifiduino32s3.build.variant=wifiduino32s3 +wifiduino32s3.build.board=WIFIDUINO32S3 + +wifiduino32s3.build.usb_mode=1 +wifiduino32s3.build.cdc_on_boot=0 +wifiduino32s3.build.msc_on_boot=0 +wifiduino32s3.build.dfu_on_boot=0 +wifiduino32s3.build.f_cpu=240000000L +wifiduino32s3.build.flash_size=16MB +wifiduino32s3.build.flash_freq=80m +wifiduino32s3.build.flash_mode=dio +wifiduino32s3.build.boot=qio +wifiduino32s3.build.boot_freq=80m +wifiduino32s3.build.partitions=app3M_fat9M_16MB +wifiduino32s3.build.defines= +wifiduino32s3.build.loop_core= +wifiduino32s3.build.event_core= +wifiduino32s3.build.psram_type=opi +wifiduino32s3.build.memory_type={build.boot}_{build.psram_type} + +wifiduino32s3.menu.PSRAM.opi=OPI PSRAM +wifiduino32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +wifiduino32s3.menu.PSRAM.opi.build.psram_type=opi +wifiduino32s3.menu.PSRAM.disabled=Disabled +wifiduino32s3.menu.PSRAM.disabled.build.defines= +wifiduino32s3.menu.PSRAM.disabled.build.psram_type=qspi +wifiduino32s3.menu.PSRAM.enabled=QSPI PSRAM +wifiduino32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +wifiduino32s3.menu.PSRAM.enabled.build.psram_type=qspi + +wifiduino32s3.menu.FlashMode.qio=QIO 80MHz +wifiduino32s3.menu.FlashMode.qio.build.flash_mode=dio +wifiduino32s3.menu.FlashMode.qio.build.boot=qio +wifiduino32s3.menu.FlashMode.qio.build.boot_freq=80m +wifiduino32s3.menu.FlashMode.qio.build.flash_freq=80m +wifiduino32s3.menu.FlashMode.qio120=QIO 120MHz +wifiduino32s3.menu.FlashMode.qio120.build.flash_mode=dio +wifiduino32s3.menu.FlashMode.qio120.build.boot=qio +wifiduino32s3.menu.FlashMode.qio120.build.boot_freq=120m +wifiduino32s3.menu.FlashMode.qio120.build.flash_freq=80m +wifiduino32s3.menu.FlashMode.dio=DIO 80MHz +wifiduino32s3.menu.FlashMode.dio.build.flash_mode=dio +wifiduino32s3.menu.FlashMode.dio.build.boot=dio +wifiduino32s3.menu.FlashMode.dio.build.boot_freq=80m +wifiduino32s3.menu.FlashMode.dio.build.flash_freq=80m +wifiduino32s3.menu.FlashMode.opi=OPI 80MHz +wifiduino32s3.menu.FlashMode.opi.build.flash_mode=dout +wifiduino32s3.menu.FlashMode.opi.build.boot=opi +wifiduino32s3.menu.FlashMode.opi.build.boot_freq=80m +wifiduino32s3.menu.FlashMode.opi.build.flash_freq=80m + +wifiduino32s3.menu.FlashSize.16M=16MB (128Mb) +wifiduino32s3.menu.FlashSize.16M.build.flash_size=16MB +wifiduino32s3.menu.FlashSize.8M=8MB (64Mb) +wifiduino32s3.menu.FlashSize.8M.build.flash_size=8MB +#wifiduino32s3.menu.FlashSize.32M=32MB (256Mb) +#wifiduino32s3.menu.FlashSize.32M.build.flash_size=32MB + +wifiduino32s3.menu.LoopCore.1=Core 1 +wifiduino32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +wifiduino32s3.menu.LoopCore.0=Core 0 +wifiduino32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +wifiduino32s3.menu.EventsCore.1=Core 1 +wifiduino32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +wifiduino32s3.menu.EventsCore.0=Core 0 +wifiduino32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +wifiduino32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +wifiduino32s3.menu.USBMode.hwcdc.build.usb_mode=1 +wifiduino32s3.menu.USBMode.default=USB-OTG (TinyUSB) +wifiduino32s3.menu.USBMode.default.build.usb_mode=0 + +wifiduino32s3.menu.CDCOnBoot.default=Disabled +wifiduino32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +wifiduino32s3.menu.CDCOnBoot.cdc=Enabled +wifiduino32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +wifiduino32s3.menu.MSCOnBoot.default=Disabled +wifiduino32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +wifiduino32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +wifiduino32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +wifiduino32s3.menu.DFUOnBoot.default=Disabled +wifiduino32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +wifiduino32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +wifiduino32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +wifiduino32s3.menu.UploadMode.default=UART0 / Hardware CDC +wifiduino32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +wifiduino32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +wifiduino32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +wifiduino32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +wifiduino32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +wifiduino32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +wifiduino32s3.menu.PartitionScheme.default.build.partitions=default +wifiduino32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +wifiduino32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +wifiduino32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +wifiduino32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +wifiduino32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +wifiduino32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +wifiduino32s3.menu.PartitionScheme.minimal.build.partitions=minimal +wifiduino32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +wifiduino32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +wifiduino32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +wifiduino32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +wifiduino32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +wifiduino32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +wifiduino32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +wifiduino32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +wifiduino32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +wifiduino32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +wifiduino32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +wifiduino32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +wifiduino32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +wifiduino32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +wifiduino32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +wifiduino32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +wifiduino32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +wifiduino32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +wifiduino32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +wifiduino32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +wifiduino32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +wifiduino32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +wifiduino32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +wifiduino32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +wifiduino32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +wifiduino32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +wifiduino32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +wifiduino32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +wifiduino32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +wifiduino32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +wifiduino32s3.menu.CPUFreq.240=240MHz (WiFi) +wifiduino32s3.menu.CPUFreq.240.build.f_cpu=240000000L +wifiduino32s3.menu.CPUFreq.160=160MHz (WiFi) +wifiduino32s3.menu.CPUFreq.160.build.f_cpu=160000000L +wifiduino32s3.menu.CPUFreq.80=80MHz (WiFi) +wifiduino32s3.menu.CPUFreq.80.build.f_cpu=80000000L +wifiduino32s3.menu.CPUFreq.40=40MHz +wifiduino32s3.menu.CPUFreq.40.build.f_cpu=40000000L +wifiduino32s3.menu.CPUFreq.20=20MHz +wifiduino32s3.menu.CPUFreq.20.build.f_cpu=20000000L +wifiduino32s3.menu.CPUFreq.10=10MHz +wifiduino32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +wifiduino32s3.menu.UploadSpeed.921600=921600 +wifiduino32s3.menu.UploadSpeed.921600.upload.speed=921600 +wifiduino32s3.menu.UploadSpeed.115200=115200 +wifiduino32s3.menu.UploadSpeed.115200.upload.speed=115200 +wifiduino32s3.menu.UploadSpeed.256000.windows=256000 +wifiduino32s3.menu.UploadSpeed.256000.upload.speed=256000 +wifiduino32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +wifiduino32s3.menu.UploadSpeed.230400=230400 +wifiduino32s3.menu.UploadSpeed.230400.upload.speed=230400 +wifiduino32s3.menu.UploadSpeed.460800.linux=460800 +wifiduino32s3.menu.UploadSpeed.460800.macosx=460800 +wifiduino32s3.menu.UploadSpeed.460800.upload.speed=460800 +wifiduino32s3.menu.UploadSpeed.512000.windows=512000 +wifiduino32s3.menu.UploadSpeed.512000.upload.speed=512000 + +wifiduino32s3.menu.DebugLevel.none=None +wifiduino32s3.menu.DebugLevel.none.build.code_debug=0 +wifiduino32s3.menu.DebugLevel.error=Error +wifiduino32s3.menu.DebugLevel.error.build.code_debug=1 +wifiduino32s3.menu.DebugLevel.warn=Warn +wifiduino32s3.menu.DebugLevel.warn.build.code_debug=2 +wifiduino32s3.menu.DebugLevel.info=Info +wifiduino32s3.menu.DebugLevel.info.build.code_debug=3 +wifiduino32s3.menu.DebugLevel.debug=Debug +wifiduino32s3.menu.DebugLevel.debug.build.code_debug=4 +wifiduino32s3.menu.DebugLevel.verbose=Verbose +wifiduino32s3.menu.DebugLevel.verbose.build.code_debug=5 + +wifiduino32s3.menu.EraseFlash.none=Disabled +wifiduino32s3.menu.EraseFlash.none.upload.erase_cmd= +wifiduino32s3.menu.EraseFlash.all=Enabled +wifiduino32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +imbrios-logsens-v1p1.name=IMBRIOS LOGSENS_V1P1 + +imbrios-logsens-v1p1.bootloader.tool=esptool_py +imbrios-logsens-v1p1.bootloader.tool.default=esptool_py + +imbrios-logsens-v1p1.upload.tool=esptool_py +imbrios-logsens-v1p1.upload.tool.default=esptool_py +imbrios-logsens-v1p1.upload.tool.network=esp_ota + +imbrios-logsens-v1p1.upload.maximum_size=1310720 +imbrios-logsens-v1p1.upload.maximum_data_size=327680 +imbrios-logsens-v1p1.upload.wait_for_upload_port=true +imbrios-logsens-v1p1.upload.flags= +imbrios-logsens-v1p1.upload.extra_flags= + +imbrios-logsens-v1p1.serial.disableDTR=true +imbrios-logsens-v1p1.serial.disableRTS=true + +imbrios-logsens-v1p1.build.tarch=xtensa +imbrios-logsens-v1p1.build.bootloader_addr=0x1000 +imbrios-logsens-v1p1.build.target=esp32 +imbrios-logsens-v1p1.build.mcu=esp32 +imbrios-logsens-v1p1.build.core=esp32 +imbrios-logsens-v1p1.build.variant=imbrios-logsens-v1p1 +imbrios-logsens-v1p1.build.board=IMBRIOS_LOGSENS_V1P1 + +imbrios-logsens-v1p1.build.f_cpu=240000000L +imbrios-logsens-v1p1.build.flash_mode=dio +imbrios-logsens-v1p1.build.flash_size=4MB +imbrios-logsens-v1p1.build.boot=dio +imbrios-logsens-v1p1.build.partitions=default +imbrios-logsens-v1p1.build.defines= + +imbrios-logsens-v1p1.menu.FlashFreq.80=80MHz +imbrios-logsens-v1p1.menu.FlashFreq.80.build.flash_freq=80m +imbrios-logsens-v1p1.menu.FlashFreq.40=40MHz +imbrios-logsens-v1p1.menu.FlashFreq.40.build.flash_freq=40m + +imbrios-logsens-v1p1.menu.PartitionScheme.default=Default +imbrios-logsens-v1p1.menu.PartitionScheme.default.build.partitions=default +imbrios-logsens-v1p1.menu.PartitionScheme.no_ota=No OTA (Large APP) +imbrios-logsens-v1p1.menu.PartitionScheme.no_ota.build.partitions=no_ota +imbrios-logsens-v1p1.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +imbrios-logsens-v1p1.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +imbrios-logsens-v1p1.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +imbrios-logsens-v1p1.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +imbrios-logsens-v1p1.menu.CPUFreq.240=240MHz (WiFi/BT) +imbrios-logsens-v1p1.menu.CPUFreq.240.build.f_cpu=240000000L +imbrios-logsens-v1p1.menu.CPUFreq.160=160MHz (WiFi/BT) +imbrios-logsens-v1p1.menu.CPUFreq.160.build.f_cpu=160000000L +imbrios-logsens-v1p1.menu.CPUFreq.80=80MHz (WiFi/BT) +imbrios-logsens-v1p1.menu.CPUFreq.80.build.f_cpu=80000000L +imbrios-logsens-v1p1.menu.CPUFreq.40=40MHz (40MHz XTAL) +imbrios-logsens-v1p1.menu.CPUFreq.40.build.f_cpu=40000000L +imbrios-logsens-v1p1.menu.CPUFreq.26=26MHz (26MHz XTAL) +imbrios-logsens-v1p1.menu.CPUFreq.26.build.f_cpu=26000000L +imbrios-logsens-v1p1.menu.CPUFreq.20=20MHz (40MHz XTAL) +imbrios-logsens-v1p1.menu.CPUFreq.20.build.f_cpu=20000000L +imbrios-logsens-v1p1.menu.CPUFreq.13=13MHz (26MHz XTAL) +imbrios-logsens-v1p1.menu.CPUFreq.13.build.f_cpu=13000000L +imbrios-logsens-v1p1.menu.CPUFreq.10=10MHz (40MHz XTAL) +imbrios-logsens-v1p1.menu.CPUFreq.10.build.f_cpu=10000000L + +imbrios-logsens-v1p1.menu.UploadSpeed.921600=921600 +imbrios-logsens-v1p1.menu.UploadSpeed.921600.upload.speed=921600 +imbrios-logsens-v1p1.menu.UploadSpeed.115200=115200 +imbrios-logsens-v1p1.menu.UploadSpeed.115200.upload.speed=115200 +imbrios-logsens-v1p1.menu.UploadSpeed.256000.windows=256000 +imbrios-logsens-v1p1.menu.UploadSpeed.256000.upload.speed=256000 +imbrios-logsens-v1p1.menu.UploadSpeed.230400.windows.upload.speed=256000 +imbrios-logsens-v1p1.menu.UploadSpeed.230400=230400 +imbrios-logsens-v1p1.menu.UploadSpeed.230400.upload.speed=230400 +imbrios-logsens-v1p1.menu.UploadSpeed.460800.linux=460800 +imbrios-logsens-v1p1.menu.UploadSpeed.460800.macosx=460800 +imbrios-logsens-v1p1.menu.UploadSpeed.460800.upload.speed=460800 +imbrios-logsens-v1p1.menu.UploadSpeed.512000.windows=512000 +imbrios-logsens-v1p1.menu.UploadSpeed.512000.upload.speed=512000 + +imbrios-logsens-v1p1.menu.DebugLevel.none=None +imbrios-logsens-v1p1.menu.DebugLevel.none.build.code_debug=0 +imbrios-logsens-v1p1.menu.DebugLevel.error=Error +imbrios-logsens-v1p1.menu.DebugLevel.error.build.code_debug=1 +imbrios-logsens-v1p1.menu.DebugLevel.warn=Warn +imbrios-logsens-v1p1.menu.DebugLevel.warn.build.code_debug=2 +imbrios-logsens-v1p1.menu.DebugLevel.info=Info +imbrios-logsens-v1p1.menu.DebugLevel.info.build.code_debug=3 +imbrios-logsens-v1p1.menu.DebugLevel.debug=Debug +imbrios-logsens-v1p1.menu.DebugLevel.debug.build.code_debug=4 +imbrios-logsens-v1p1.menu.DebugLevel.verbose=Verbose +imbrios-logsens-v1p1.menu.DebugLevel.verbose.build.code_debug=5 + +imbrios-logsens-v1p1.menu.EraseFlash.none=Disabled +imbrios-logsens-v1p1.menu.EraseFlash.none.upload.erase_cmd= +imbrios-logsens-v1p1.menu.EraseFlash.all=Enabled +imbrios-logsens-v1p1.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +healthypi4.name=ProtoCentral HealthyPi 4 + +healthypi4.bootloader.tool=esptool_py +healthypi4.bootloader.tool.default=esptool_py + +healthypi4.upload.tool=esptool_py +healthypi4.upload.tool.default=esptool_py +healthypi4.upload.tool.network=esp_ota + +healthypi4.upload.maximum_size=1310720 +healthypi4.upload.maximum_data_size=327680 +healthypi4.upload.wait_for_upload_port=true +healthypi4.upload.flags= +healthypi4.upload.extra_flags= + +healthypi4.serial.disableDTR=true +healthypi4.serial.disableRTS=true + +healthypi4.build.tarch=xtensa +healthypi4.build.bootloader_addr=0x1000 +healthypi4.build.target=esp32 +healthypi4.build.mcu=esp32 +healthypi4.build.core=esp32 +healthypi4.build.variant=healthypi4 +healthypi4.build.board=HEALTHYPI_4 + +healthypi4.build.f_cpu=240000000L +healthypi4.build.flash_mode=dio +healthypi4.build.flash_size=4MB +healthypi4.build.boot=dio +healthypi4.build.partitions=min_spiffs +healthypi4.build.defines= + +healthypi4.menu.FlashFreq.80=80MHz +healthypi4.menu.FlashFreq.80.build.flash_freq=80m +healthypi4.menu.FlashFreq.40=40MHz +healthypi4.menu.FlashFreq.40.build.flash_freq=40m + +healthypi4.menu.PartitionScheme.default=Default +healthypi4.menu.PartitionScheme.default.build.partitions=default +healthypi4.menu.PartitionScheme.no_ota=No OTA (Large APP) +healthypi4.menu.PartitionScheme.no_ota.build.partitions=no_ota +healthypi4.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +healthypi4.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +healthypi4.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +healthypi4.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +healthypi4.menu.UploadSpeed.921600=921600 +healthypi4.menu.UploadSpeed.921600.upload.speed=921600 +healthypi4.menu.UploadSpeed.115200=115200 +healthypi4.menu.UploadSpeed.115200.upload.speed=115200 +healthypi4.menu.UploadSpeed.256000.windows=256000 +healthypi4.menu.UploadSpeed.256000.upload.speed=256000 +healthypi4.menu.UploadSpeed.230400.windows.upload.speed=256000 +healthypi4.menu.UploadSpeed.230400=230400 +healthypi4.menu.UploadSpeed.230400.upload.speed=230400 +healthypi4.menu.UploadSpeed.460800.linux=460800 +healthypi4.menu.UploadSpeed.460800.macosx=460800 +healthypi4.menu.UploadSpeed.460800.upload.speed=460800 +healthypi4.menu.UploadSpeed.512000.windows=512000 +healthypi4.menu.UploadSpeed.512000.upload.speed=512000 + +healthypi4.menu.DebugLevel.none=None +healthypi4.menu.DebugLevel.none.build.code_debug=0 +healthypi4.menu.DebugLevel.error=Error +healthypi4.menu.DebugLevel.error.build.code_debug=1 +healthypi4.menu.DebugLevel.warn=Warn +healthypi4.menu.DebugLevel.warn.build.code_debug=2 +healthypi4.menu.DebugLevel.info=Info +healthypi4.menu.DebugLevel.info.build.code_debug=3 +healthypi4.menu.DebugLevel.debug=Debug +healthypi4.menu.DebugLevel.debug.build.code_debug=4 +healthypi4.menu.DebugLevel.verbose=Verbose +healthypi4.menu.DebugLevel.verbose.build.code_debug=5 + +healthypi4.menu.EraseFlash.none=Disabled +healthypi4.menu.EraseFlash.none.upload.erase_cmd= +healthypi4.menu.EraseFlash.all=Enabled +healthypi4.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ET-Board.name=ET-Board + +ET-Board.bootloader.tool=esptool_py +ET-Board.bootloader.tool.default=esptool_py + +ET-Board.upload.tool=esptool_py +ET-Board.upload.tool.default=esptool_py +ET-Board.upload.tool.network=esp_ota + +ET-Board.upload.maximum_size=1310720 +ET-Board.upload.maximum_data_size=327680 +ET-Board.upload.wait_for_upload_port=true +ET-Board.upload.flags= +ET-Board.upload.extra_flags= + +ET-Board.serial.disableDTR=true +ET-Board.serial.disableRTS=true + +ET-Board.build.tarch=xtensa +ET-Board.build.bootloader_addr=0x1000 +ET-Board.build.target=esp32 +ET-Board.build.mcu=esp32 +ET-Board.build.core=esp32 +ET-Board.build.variant=ET-Board +ET-Board.build.board=ET-Board +ET-Board.build.f_cpu=240000000L +ET-Board.build.flash_mode=dio +ET-Board.build.flash_size=4MB +ET-Board.build.boot=dio +ET-Board.build.partitions=default +ET-Board.build.defines= + +ET-Board.menu.PartitionScheme.default=Default +ET-Board.menu.PartitionScheme.default.build.partitions=default +ET-Board.menu.PartitionScheme.no_ota=No OTA (Large APP) +ET-Board.menu.PartitionScheme.no_ota.build.partitions=no_ota +ET-Board.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ET-Board.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +ET-Board.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ET-Board.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ET-Board.menu.FlashFreq.80=80MHz +ET-Board.menu.FlashFreq.80.build.flash_freq=80m +ET-Board.menu.FlashFreq.40=40MHz +ET-Board.menu.FlashFreq.40.build.flash_freq=40m + +ET-Board.menu.UploadSpeed.921600=921600 +ET-Board.menu.UploadSpeed.921600.upload.speed=921600 +ET-Board.menu.UploadSpeed.115200=115200 +ET-Board.menu.UploadSpeed.115200.upload.speed=115200 +ET-Board.menu.UploadSpeed.256000.windows=256000 +ET-Board.menu.UploadSpeed.256000.upload.speed=256000 +ET-Board.menu.UploadSpeed.230400.windows.upload.speed=256000 +ET-Board.menu.UploadSpeed.230400=230400 +ET-Board.menu.UploadSpeed.230400.upload.speed=230400 +ET-Board.menu.UploadSpeed.460800.linux=460800 +ET-Board.menu.UploadSpeed.460800.macosx=460800 +ET-Board.menu.UploadSpeed.460800.upload.speed=460800 +ET-Board.menu.UploadSpeed.512000.windows=512000 +ET-Board.menu.UploadSpeed.512000.upload.speed=512000 + +ET-Board.menu.DebugLevel.none=None +ET-Board.menu.DebugLevel.none.build.code_debug=0 +ET-Board.menu.DebugLevel.error=Error +ET-Board.menu.DebugLevel.error.build.code_debug=1 +ET-Board.menu.DebugLevel.warn=Warn +ET-Board.menu.DebugLevel.warn.build.code_debug=2 +ET-Board.menu.DebugLevel.info=Info +ET-Board.menu.DebugLevel.info.build.code_debug=3 +ET-Board.menu.DebugLevel.debug=Debug +ET-Board.menu.DebugLevel.debug.build.code_debug=4 +ET-Board.menu.DebugLevel.verbose=Verbose +ET-Board.menu.DebugLevel.verbose.build.code_debug=5 + +ET-Board.menu.EraseFlash.none=Disabled +ET-Board.menu.EraseFlash.none.upload.erase_cmd= +ET-Board.menu.EraseFlash.all=Enabled +ET-Board.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +ch_denky.name=Denky + +ch_denky.bootloader.tool=esptool_py +ch_denky.bootloader.tool.default=esptool_py + +ch_denky.upload.tool=esptool_py +ch_denky.upload.tool.default=esptool_py +ch_denky.upload.tool.network=esp_ota + +ch_denky.upload.maximum_size=1310720 +ch_denky.upload.maximum_data_size=327680 +ch_denky.upload.flags= +ch_denky.upload.extra_flags= + +ch_denky.serial.disableDTR=true +ch_denky.serial.disableRTS=true + +ch_denky.build.tarch=xtensa +ch_denky.build.bootloader_addr=0x1000 +ch_denky.build.target=esp32 +ch_denky.build.mcu=esp32 +ch_denky.build.core=esp32 +ch_denky.build.variant=ch_denky +ch_denky.build.board=DENKY + +ch_denky.build.f_cpu=240000000L +ch_denky.build.flash_size=4MB +ch_denky.build.flash_freq=80m +ch_denky.build.flash_mode=dio +ch_denky.build.boot=dio +ch_denky.build.partitions=default +ch_denky.build.defines= + +ch_denky.menu.Revision.denkyd4=PICO-V3-02 +ch_denky.menu.Revision.denkyd4.build.board=DENKY_PICOV3 +ch_denky.menu.Revision.denkyd4.build.flash_size=8MB +ch_denky.menu.Revision.denky32=WROOM32 +ch_denky.menu.Revision.denky32.build.board=DENKY_WROOM32 +ch_denky.menu.Revision.denky32.build.flash_size=4MB + +ch_denky.menu.PartitionScheme.default=Default +ch_denky.menu.PartitionScheme.default.build.partitions=default +ch_denky.menu.PartitionScheme.no_ota=No OTA (Large APP) +ch_denky.menu.PartitionScheme.no_ota.build.partitions=no_ota +ch_denky.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ch_denky.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +ch_denky.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ch_denky.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +ch_denky.menu.UploadSpeed.921600=921600 +ch_denky.menu.UploadSpeed.921600.upload.speed=921600 +ch_denky.menu.UploadSpeed.115200=115200 +ch_denky.menu.UploadSpeed.115200.upload.speed=115200 +ch_denky.menu.UploadSpeed.256000.windows=256000 +ch_denky.menu.UploadSpeed.256000.upload.speed=256000 +ch_denky.menu.UploadSpeed.230400.windows.upload.speed=256000 +ch_denky.menu.UploadSpeed.230400=230400 +ch_denky.menu.UploadSpeed.230400.upload.speed=230400 +ch_denky.menu.UploadSpeed.460800.linux=460800 +ch_denky.menu.UploadSpeed.460800.macosx=460800 +ch_denky.menu.UploadSpeed.460800.upload.speed=460800 +ch_denky.menu.UploadSpeed.512000.windows=512000 +ch_denky.menu.UploadSpeed.512000.upload.speed=512000 + +ch_denky.menu.PSRAM.enabled=Enabled +ch_denky.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +ch_denky.menu.PSRAM.enabled.build.extra_libs= +ch_denky.menu.PSRAM.disabled=Disabled +ch_denky.menu.PSRAM.disabled.build.defines= +ch_denky.menu.PSRAM.disabled.build.extra_libs= + +ch_denky.menu.DebugLevel.none=None +ch_denky.menu.DebugLevel.none.build.code_debug=0 +ch_denky.menu.DebugLevel.error=Error +ch_denky.menu.DebugLevel.error.build.code_debug=1 +ch_denky.menu.DebugLevel.warn=Warn +ch_denky.menu.DebugLevel.warn.build.code_debug=2 +ch_denky.menu.DebugLevel.info=Info +ch_denky.menu.DebugLevel.info.build.code_debug=3 +ch_denky.menu.DebugLevel.debug=Debug +ch_denky.menu.DebugLevel.debug.build.code_debug=4 +ch_denky.menu.DebugLevel.verbose=Verbose +ch_denky.menu.DebugLevel.verbose.build.code_debug=5 + +ch_denky.menu.EraseFlash.none=Disabled +ch_denky.menu.EraseFlash.none.upload.erase_cmd= +ch_denky.menu.EraseFlash.all=Enabled +ch_denky.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +uPesy_wrover.name=uPesy ESP32 Wrover DevKit + +uPesy_wrover.bootloader.tool=esptool_py +uPesy_wrover.bootloader.tool.default=esptool_py + +uPesy_wrover.upload.tool=esptool_py +uPesy_wrover.upload.tool.default=esptool_py +uPesy_wrover.upload.tool.network=esp_ota + +uPesy_wrover.upload.maximum_size=1310720 +uPesy_wrover.upload.maximum_data_size=327680 +uPesy_wrover.upload.flags= +uPesy_wrover.upload.extra_flags= + +uPesy_wrover.serial.disableDTR=true +uPesy_wrover.serial.disableRTS=true + +uPesy_wrover.build.tarch=xtensa +uPesy_wrover.build.bootloader_addr=0x1000 +uPesy_wrover.build.target=esp32 +uPesy_wrover.build.mcu=esp32 +uPesy_wrover.build.core=esp32 +uPesy_wrover.build.variant=uPesy_esp32_wrover_devkit +uPesy_wrover.build.board=UPESY_WROVER + +uPesy_wrover.build.f_cpu=240000000L +uPesy_wrover.build.flash_size=4MB +uPesy_wrover.build.flash_freq=80m +uPesy_wrover.build.flash_mode=dio +uPesy_wrover.build.boot=dio +uPesy_wrover.build.partitions=default +uPesy_wrover.build.defines= + +uPesy_wrover.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +uPesy_wrover.menu.PartitionScheme.default.build.partitions=default +uPesy_wrover.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +uPesy_wrover.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +uPesy_wrover.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +uPesy_wrover.menu.PartitionScheme.minimal.build.partitions=minimal +uPesy_wrover.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +uPesy_wrover.menu.PartitionScheme.no_ota.build.partitions=no_ota +uPesy_wrover.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +uPesy_wrover.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +uPesy_wrover.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +uPesy_wrover.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +uPesy_wrover.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +uPesy_wrover.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +uPesy_wrover.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +uPesy_wrover.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +uPesy_wrover.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +uPesy_wrover.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +uPesy_wrover.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +uPesy_wrover.menu.PartitionScheme.huge_app.build.partitions=huge_app +uPesy_wrover.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +uPesy_wrover.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +uPesy_wrover.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +uPesy_wrover.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +uPesy_wrover.menu.CPUFreq.240=240MHz +uPesy_wrover.menu.CPUFreq.240.build.f_cpu=240000000L +uPesy_wrover.menu.CPUFreq.160=160MHz +uPesy_wrover.menu.CPUFreq.160.build.f_cpu=160000000L + +uPesy_wrover.menu.UploadSpeed.921600=921600 +uPesy_wrover.menu.UploadSpeed.921600.upload.speed=921600 +uPesy_wrover.menu.UploadSpeed.512000.windows=512000 +uPesy_wrover.menu.UploadSpeed.512000.upload.speed=512000 +uPesy_wrover.menu.UploadSpeed.460800.linux=460800 +uPesy_wrover.menu.UploadSpeed.460800.macosx=460800 +uPesy_wrover.menu.UploadSpeed.460800.upload.speed=460800 +uPesy_wrover.menu.UploadSpeed.256000.windows=256000 +uPesy_wrover.menu.UploadSpeed.256000.upload.speed=256000 +uPesy_wrover.menu.UploadSpeed.230400.windows.upload.speed=256000 +uPesy_wrover.menu.UploadSpeed.230400=230400 +uPesy_wrover.menu.UploadSpeed.230400.upload.speed=230400 +uPesy_wrover.menu.UploadSpeed.115200=115200 +uPesy_wrover.menu.UploadSpeed.115200.upload.speed=115200 + +uPesy_wrover.menu.FlashMode.qio=QIO +uPesy_wrover.menu.FlashMode.qio.build.flash_mode=dio +uPesy_wrover.menu.FlashMode.qio.build.boot=qio +uPesy_wrover.menu.FlashMode.dio=DIO +uPesy_wrover.menu.FlashMode.dio.build.flash_mode=dio +uPesy_wrover.menu.FlashMode.dio.build.boot=dio + +uPesy_wrover.menu.FlashFreq.80=80MHz +uPesy_wrover.menu.FlashFreq.80.build.flash_freq=80m +uPesy_wrover.menu.FlashFreq.40=40MHz +uPesy_wrover.menu.FlashFreq.40.build.flash_freq=40m + +uPesy_wrover.menu.PSRAM.enabled=Enabled +uPesy_wrover.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +uPesy_wrover.menu.PSRAM.enabled.build.extra_libs= +uPesy_wrover.menu.PSRAM.disabled=Disabled +uPesy_wrover.menu.PSRAM.disabled.build.defines= +uPesy_wrover.menu.PSRAM.disabled.build.extra_libs= + +uPesy_wrover.menu.DebugLevel.none=None +uPesy_wrover.menu.DebugLevel.none.build.code_debug=0 +uPesy_wrover.menu.DebugLevel.error=Error +uPesy_wrover.menu.DebugLevel.error.build.code_debug=1 +uPesy_wrover.menu.DebugLevel.warn=Warn +uPesy_wrover.menu.DebugLevel.warn.build.code_debug=2 +uPesy_wrover.menu.DebugLevel.info=Info +uPesy_wrover.menu.DebugLevel.info.build.code_debug=3 +uPesy_wrover.menu.DebugLevel.debug=Debug +uPesy_wrover.menu.DebugLevel.debug.build.code_debug=4 +uPesy_wrover.menu.DebugLevel.verbose=Verbose +uPesy_wrover.menu.DebugLevel.verbose.build.code_debug=5 + +uPesy_wrover.menu.EraseFlash.none=Disabled +uPesy_wrover.menu.EraseFlash.none.upload.erase_cmd= +uPesy_wrover.menu.EraseFlash.all=Enabled +uPesy_wrover.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +uPesy_wroom.name=uPesy ESP32 Wroom DevKit + +uPesy_wroom.bootloader.tool=esptool_py +uPesy_wroom.bootloader.tool.default=esptool_py + +uPesy_wroom.upload.tool=esptool_py +uPesy_wroom.upload.tool.default=esptool_py +uPesy_wroom.upload.tool.network=esp_ota + +uPesy_wroom.upload.maximum_size=1310720 +uPesy_wroom.upload.maximum_data_size=327680 +uPesy_wroom.upload.flags= +uPesy_wroom.upload.extra_flags= + +uPesy_wroom.serial.disableDTR=true +uPesy_wroom.serial.disableRTS=true + +uPesy_wroom.build.tarch=xtensa +uPesy_wroom.build.bootloader_addr=0x1000 +uPesy_wroom.build.target=esp32 +uPesy_wroom.build.mcu=esp32 +uPesy_wroom.build.core=esp32 +uPesy_wroom.build.variant=uPesy_esp32_wroom_devkit +uPesy_wroom.build.board=UPESY_WROOM + +uPesy_wroom.build.f_cpu=240000000L +uPesy_wroom.build.flash_size=4MB +uPesy_wroom.build.flash_freq=80m +uPesy_wroom.build.flash_mode=dio +uPesy_wroom.build.boot=dio +uPesy_wroom.build.partitions=default +uPesy_wroom.build.defines= + +uPesy_wroom.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +uPesy_wroom.menu.PartitionScheme.default.build.partitions=default +uPesy_wroom.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +uPesy_wroom.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +uPesy_wroom.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +uPesy_wroom.menu.PartitionScheme.minimal.build.partitions=minimal +uPesy_wroom.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +uPesy_wroom.menu.PartitionScheme.no_ota.build.partitions=no_ota +uPesy_wroom.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +uPesy_wroom.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +uPesy_wroom.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +uPesy_wroom.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +uPesy_wroom.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +uPesy_wroom.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +uPesy_wroom.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +uPesy_wroom.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +uPesy_wroom.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +uPesy_wroom.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +uPesy_wroom.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +uPesy_wroom.menu.PartitionScheme.huge_app.build.partitions=huge_app +uPesy_wroom.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +uPesy_wroom.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +uPesy_wroom.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +uPesy_wroom.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +uPesy_wroom.menu.CPUFreq.240=240MHz +uPesy_wroom.menu.CPUFreq.240.build.f_cpu=240000000L +uPesy_wroom.menu.CPUFreq.160=160MHz +uPesy_wroom.menu.CPUFreq.160.build.f_cpu=160000000L + +uPesy_wroom.menu.UploadSpeed.921600=921600 +uPesy_wroom.menu.UploadSpeed.921600.upload.speed=921600 +uPesy_wroom.menu.UploadSpeed.512000.windows=512000 +uPesy_wroom.menu.UploadSpeed.512000.upload.speed=512000 +uPesy_wroom.menu.UploadSpeed.460800.linux=460800 +uPesy_wroom.menu.UploadSpeed.460800.macosx=460800 +uPesy_wroom.menu.UploadSpeed.460800.upload.speed=460800 +uPesy_wroom.menu.UploadSpeed.256000.windows=256000 +uPesy_wroom.menu.UploadSpeed.256000.upload.speed=256000 +uPesy_wroom.menu.UploadSpeed.230400.windows.upload.speed=256000 +uPesy_wroom.menu.UploadSpeed.230400=230400 +uPesy_wroom.menu.UploadSpeed.230400.upload.speed=230400 +uPesy_wroom.menu.UploadSpeed.115200=115200 +uPesy_wroom.menu.UploadSpeed.115200.upload.speed=115200 + +uPesy_wroom.menu.FlashMode.qio=QIO +uPesy_wroom.menu.FlashMode.qio.build.flash_mode=dio +uPesy_wroom.menu.FlashMode.qio.build.boot=qio +uPesy_wroom.menu.FlashMode.dio=DIO +uPesy_wroom.menu.FlashMode.dio.build.flash_mode=dio +uPesy_wroom.menu.FlashMode.dio.build.boot=dio + +uPesy_wroom.menu.FlashFreq.80=80MHz +uPesy_wroom.menu.FlashFreq.80.build.flash_freq=80m +uPesy_wroom.menu.FlashFreq.40=40MHz +uPesy_wroom.menu.FlashFreq.40.build.flash_freq=40m + +uPesy_wroom.menu.DebugLevel.none=None +uPesy_wroom.menu.DebugLevel.none.build.code_debug=0 +uPesy_wroom.menu.DebugLevel.error=Error +uPesy_wroom.menu.DebugLevel.error.build.code_debug=1 +uPesy_wroom.menu.DebugLevel.warn=Warn +uPesy_wroom.menu.DebugLevel.warn.build.code_debug=2 +uPesy_wroom.menu.DebugLevel.info=Info +uPesy_wroom.menu.DebugLevel.info.build.code_debug=3 +uPesy_wroom.menu.DebugLevel.debug=Debug +uPesy_wroom.menu.DebugLevel.debug.build.code_debug=4 +uPesy_wroom.menu.DebugLevel.verbose=Verbose +uPesy_wroom.menu.DebugLevel.verbose.build.code_debug=5 + +uPesy_wroom.menu.EraseFlash.none=Disabled +uPesy_wroom.menu.EraseFlash.none.upload.erase_cmd= +uPesy_wroom.menu.EraseFlash.all=Enabled +uPesy_wroom.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +uPesy_edu_esp32.name=uPesy EDU ESP32 + +uPesy_edu_esp32.bootloader.tool=esptool_py +uPesy_edu_esp32.bootloader.tool.default=esptool_py + +uPesy_edu_esp32.upload.tool=esptool_py +uPesy_edu_esp32.upload.tool.default=esptool_py +uPesy_edu_esp32.upload.tool.network=esp_ota + +uPesy_edu_esp32.upload.maximum_size=1310720 +uPesy_edu_esp32.upload.maximum_data_size=327680 +uPesy_edu_esp32.upload.flags= +uPesy_edu_esp32.upload.extra_flags= + +uPesy_edu_esp32.serial.disableDTR=true +uPesy_edu_esp32.serial.disableRTS=true + +uPesy_edu_esp32.build.tarch=xtensa +uPesy_edu_esp32.build.bootloader_addr=0x1000 +uPesy_edu_esp32.build.target=esp32 +uPesy_edu_esp32.build.mcu=esp32 +uPesy_edu_esp32.build.core=esp32 +uPesy_edu_esp32.build.variant=uPesy_edu_esp32 +uPesy_edu_esp32.build.board=UPESY_EDU_ESP32 + +uPesy_edu_esp32.build.f_cpu=240000000L +uPesy_edu_esp32.build.flash_size=4MB +uPesy_edu_esp32.build.flash_freq=80m +uPesy_edu_esp32.build.flash_mode=dio +uPesy_edu_esp32.build.boot=dio +uPesy_edu_esp32.build.partitions=default +uPesy_edu_esp32.build.defines= + +uPesy_edu_esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.default.build.partitions=default +uPesy_edu_esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +uPesy_edu_esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +uPesy_edu_esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.minimal.build.partitions=minimal +uPesy_edu_esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +uPesy_edu_esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +uPesy_edu_esp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +uPesy_edu_esp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +uPesy_edu_esp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +uPesy_edu_esp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +uPesy_edu_esp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +uPesy_edu_esp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +uPesy_edu_esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +uPesy_edu_esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +uPesy_edu_esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +uPesy_edu_esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +uPesy_edu_esp32.menu.CPUFreq.240=240MHz +uPesy_edu_esp32.menu.CPUFreq.240.build.f_cpu=240000000L +uPesy_edu_esp32.menu.CPUFreq.160=160MHz +uPesy_edu_esp32.menu.CPUFreq.160.build.f_cpu=160000000L + +uPesy_edu_esp32.menu.UploadSpeed.921600=921600 +uPesy_edu_esp32.menu.UploadSpeed.921600.upload.speed=921600 +uPesy_edu_esp32.menu.UploadSpeed.512000.windows=512000 +uPesy_edu_esp32.menu.UploadSpeed.512000.upload.speed=512000 +uPesy_edu_esp32.menu.UploadSpeed.460800.linux=460800 +uPesy_edu_esp32.menu.UploadSpeed.460800.macosx=460800 +uPesy_edu_esp32.menu.UploadSpeed.460800.upload.speed=460800 +uPesy_edu_esp32.menu.UploadSpeed.256000.windows=256000 +uPesy_edu_esp32.menu.UploadSpeed.256000.upload.speed=256000 +uPesy_edu_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +uPesy_edu_esp32.menu.UploadSpeed.230400=230400 +uPesy_edu_esp32.menu.UploadSpeed.230400.upload.speed=230400 +uPesy_edu_esp32.menu.UploadSpeed.115200=115200 +uPesy_edu_esp32.menu.UploadSpeed.115200.upload.speed=115200 + +uPesy_edu_esp32.menu.FlashMode.qio=QIO +uPesy_edu_esp32.menu.FlashMode.qio.build.flash_mode=dio +uPesy_edu_esp32.menu.FlashMode.qio.build.boot=qio +uPesy_edu_esp32.menu.FlashMode.dio=DIO +uPesy_edu_esp32.menu.FlashMode.dio.build.flash_mode=dio +uPesy_edu_esp32.menu.FlashMode.dio.build.boot=dio + +uPesy_edu_esp32.menu.FlashFreq.80=80MHz +uPesy_edu_esp32.menu.FlashFreq.80.build.flash_freq=80m +uPesy_edu_esp32.menu.FlashFreq.40=40MHz +uPesy_edu_esp32.menu.FlashFreq.40.build.flash_freq=40m + +uPesy_edu_esp32.menu.DebugLevel.none=None +uPesy_edu_esp32.menu.DebugLevel.none.build.code_debug=0 +uPesy_edu_esp32.menu.DebugLevel.error=Error +uPesy_edu_esp32.menu.DebugLevel.error.build.code_debug=1 +uPesy_edu_esp32.menu.DebugLevel.warn=Warn +uPesy_edu_esp32.menu.DebugLevel.warn.build.code_debug=2 +uPesy_edu_esp32.menu.DebugLevel.info=Info +uPesy_edu_esp32.menu.DebugLevel.info.build.code_debug=3 +uPesy_edu_esp32.menu.DebugLevel.debug=Debug +uPesy_edu_esp32.menu.DebugLevel.debug.build.code_debug=4 +uPesy_edu_esp32.menu.DebugLevel.verbose=Verbose +uPesy_edu_esp32.menu.DebugLevel.verbose.build.code_debug=5 + +uPesy_edu_esp32.menu.EraseFlash.none=Disabled +uPesy_edu_esp32.menu.EraseFlash.none.upload.erase_cmd= +uPesy_edu_esp32.menu.EraseFlash.all=Enabled +uPesy_edu_esp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +upesy_esp32c3_basic.name=uPesy ESP32C3 Basic +upesy_esp32c3_basic.vid.0=0x303a +upesy_esp32c3_basic.pid.0=0x8195 + +upesy_esp32c3_basic.bootloader.tool=esptool_py +upesy_esp32c3_basic.bootloader.tool.default=esptool_py + +upesy_esp32c3_basic.upload.tool=esptool_py +upesy_esp32c3_basic.upload.tool.default=esptool_py +upesy_esp32c3_basic.upload.tool.network=esp_ota + +upesy_esp32c3_basic.upload.maximum_size=1310720 +upesy_esp32c3_basic.upload.maximum_data_size=327680 +upesy_esp32c3_basic.upload.flags= +upesy_esp32c3_basic.upload.extra_flags= +upesy_esp32c3_basic.upload.use_1200bps_touch=false +upesy_esp32c3_basic.upload.wait_for_upload_port=false + +upesy_esp32c3_basic.serial.disableDTR=true +upesy_esp32c3_basic.serial.disableRTS=true + +upesy_esp32c3_basic.build.tarch=riscv32 +upesy_esp32c3_basic.build.target=esp +upesy_esp32c3_basic.build.mcu=esp32c3 +upesy_esp32c3_basic.build.core=esp32 +upesy_esp32c3_basic.build.variant=uPesy_esp32c3_basic +upesy_esp32c3_basic.build.board=UPESY_ESP32C3_BASIC +upesy_esp32c3_basic.build.bootloader_addr=0x0 + +upesy_esp32c3_basic.build.cdc_on_boot=1 +upesy_esp32c3_basic.build.f_cpu=160000000L +upesy_esp32c3_basic.build.flash_size=4MB +upesy_esp32c3_basic.build.flash_freq=80m +upesy_esp32c3_basic.build.flash_mode=dio +upesy_esp32c3_basic.build.boot=qio +upesy_esp32c3_basic.build.partitions=default +upesy_esp32c3_basic.build.defines= + +upesy_esp32c3_basic.menu.CDCOnBoot.default=Enabled +upesy_esp32c3_basic.menu.CDCOnBoot.default.build.cdc_on_boot=1 +upesy_esp32c3_basic.menu.CDCOnBoot.dis_cdc=Disabled +upesy_esp32c3_basic.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +upesy_esp32c3_basic.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +upesy_esp32c3_basic.menu.PartitionScheme.default.build.partitions=default +upesy_esp32c3_basic.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +upesy_esp32c3_basic.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +upesy_esp32c3_basic.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +upesy_esp32c3_basic.menu.PartitionScheme.no_ota.build.partitions=no_ota +upesy_esp32c3_basic.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +upesy_esp32c3_basic.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +upesy_esp32c3_basic.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +upesy_esp32c3_basic.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +upesy_esp32c3_basic.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +upesy_esp32c3_basic.menu.PartitionScheme.huge_app.build.partitions=huge_app +upesy_esp32c3_basic.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +upesy_esp32c3_basic.menu.CPUFreq.160=160MHz (WiFi) +upesy_esp32c3_basic.menu.CPUFreq.160.build.f_cpu=160000000L +upesy_esp32c3_basic.menu.CPUFreq.80=80MHz (WiFi) +upesy_esp32c3_basic.menu.CPUFreq.80.build.f_cpu=80000000L +upesy_esp32c3_basic.menu.CPUFreq.40=40MHz +upesy_esp32c3_basic.menu.CPUFreq.40.build.f_cpu=40000000L +upesy_esp32c3_basic.menu.CPUFreq.20=20MHz +upesy_esp32c3_basic.menu.CPUFreq.20.build.f_cpu=20000000L +upesy_esp32c3_basic.menu.CPUFreq.10=10MHz +upesy_esp32c3_basic.menu.CPUFreq.10.build.f_cpu=10000000L + +upesy_esp32c3_basic.menu.FlashFreq.80=80MHz +upesy_esp32c3_basic.menu.FlashFreq.80.build.flash_freq=80m +upesy_esp32c3_basic.menu.FlashFreq.40=40MHz +upesy_esp32c3_basic.menu.FlashFreq.40.build.flash_freq=40m + +upesy_esp32c3_basic.menu.UploadSpeed.921600=921600 +upesy_esp32c3_basic.menu.UploadSpeed.921600.upload.speed=921600 +upesy_esp32c3_basic.menu.UploadSpeed.115200=115200 +upesy_esp32c3_basic.menu.UploadSpeed.115200.upload.speed=115200 +upesy_esp32c3_basic.menu.UploadSpeed.256000.windows=256000 +upesy_esp32c3_basic.menu.UploadSpeed.256000.upload.speed=256000 +upesy_esp32c3_basic.menu.UploadSpeed.230400.windows.upload.speed=256000 +upesy_esp32c3_basic.menu.UploadSpeed.230400=230400 +upesy_esp32c3_basic.menu.UploadSpeed.230400.upload.speed=230400 +upesy_esp32c3_basic.menu.UploadSpeed.460800.linux=460800 +upesy_esp32c3_basic.menu.UploadSpeed.460800.macosx=460800 +upesy_esp32c3_basic.menu.UploadSpeed.460800.upload.speed=460800 +upesy_esp32c3_basic.menu.UploadSpeed.512000.windows=512000 +upesy_esp32c3_basic.menu.UploadSpeed.512000.upload.speed=512000 + +upesy_esp32c3_basic.menu.DebugLevel.none=None +upesy_esp32c3_basic.menu.DebugLevel.none.build.code_debug=0 +upesy_esp32c3_basic.menu.DebugLevel.error=Error +upesy_esp32c3_basic.menu.DebugLevel.error.build.code_debug=1 +upesy_esp32c3_basic.menu.DebugLevel.warn=Warn +upesy_esp32c3_basic.menu.DebugLevel.warn.build.code_debug=2 +upesy_esp32c3_basic.menu.DebugLevel.info=Info +upesy_esp32c3_basic.menu.DebugLevel.info.build.code_debug=3 +upesy_esp32c3_basic.menu.DebugLevel.debug=Debug +upesy_esp32c3_basic.menu.DebugLevel.debug.build.code_debug=4 +upesy_esp32c3_basic.menu.DebugLevel.verbose=Verbose +upesy_esp32c3_basic.menu.DebugLevel.verbose.build.code_debug=5 + +upesy_esp32c3_basic.menu.EraseFlash.none=Disabled +upesy_esp32c3_basic.menu.EraseFlash.none.upload.erase_cmd= +upesy_esp32c3_basic.menu.EraseFlash.all=Enabled +upesy_esp32c3_basic.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +upesy_esp32c3_mini.name=uPesy ESP32C3 Mini +upesy_esp32c3_mini.vid.0=0x303a +upesy_esp32c3_mini.pid.0=0x819B + +upesy_esp32c3_mini.bootloader.tool=esptool_py +upesy_esp32c3_mini.bootloader.tool.default=esptool_py + +upesy_esp32c3_mini.upload.tool=esptool_py +upesy_esp32c3_mini.upload.tool.default=esptool_py +upesy_esp32c3_mini.upload.tool.network=esp_ota + +upesy_esp32c3_mini.upload.maximum_size=1310720 +upesy_esp32c3_mini.upload.maximum_data_size=327680 +upesy_esp32c3_mini.upload.flags= +upesy_esp32c3_mini.upload.extra_flags= +upesy_esp32c3_mini.upload.use_1200bps_touch=false +upesy_esp32c3_mini.upload.wait_for_upload_port=false + +upesy_esp32c3_mini.serial.disableDTR=true +upesy_esp32c3_mini.serial.disableRTS=true + +upesy_esp32c3_mini.build.tarch=riscv32 +upesy_esp32c3_mini.build.target=esp +upesy_esp32c3_mini.build.mcu=esp32c3 +upesy_esp32c3_mini.build.core=esp32 +upesy_esp32c3_mini.build.variant=uPesy_esp32c3_mini +upesy_esp32c3_mini.build.board=UPESY_ESP32C3_MINI +upesy_esp32c3_mini.build.bootloader_addr=0x0 + +upesy_esp32c3_mini.build.cdc_on_boot=1 +upesy_esp32c3_mini.build.f_cpu=160000000L +upesy_esp32c3_mini.build.flash_size=4MB +upesy_esp32c3_mini.build.flash_freq=80m +upesy_esp32c3_mini.build.flash_mode=dio +upesy_esp32c3_mini.build.boot=qio +upesy_esp32c3_mini.build.partitions=default +upesy_esp32c3_mini.build.defines= + +upesy_esp32c3_mini.menu.CDCOnBoot.default=Enabled +upesy_esp32c3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +upesy_esp32c3_mini.menu.CDCOnBoot.dis_cdc=Disabled +upesy_esp32c3_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +upesy_esp32c3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +upesy_esp32c3_mini.menu.PartitionScheme.default.build.partitions=default +upesy_esp32c3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +upesy_esp32c3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +upesy_esp32c3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +upesy_esp32c3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +upesy_esp32c3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +upesy_esp32c3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +upesy_esp32c3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +upesy_esp32c3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +upesy_esp32c3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +upesy_esp32c3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +upesy_esp32c3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +upesy_esp32c3_mini.menu.CPUFreq.160=160MHz (WiFi) +upesy_esp32c3_mini.menu.CPUFreq.160.build.f_cpu=160000000L +upesy_esp32c3_mini.menu.CPUFreq.80=80MHz (WiFi) +upesy_esp32c3_mini.menu.CPUFreq.80.build.f_cpu=80000000L +upesy_esp32c3_mini.menu.CPUFreq.40=40MHz +upesy_esp32c3_mini.menu.CPUFreq.40.build.f_cpu=40000000L +upesy_esp32c3_mini.menu.CPUFreq.20=20MHz +upesy_esp32c3_mini.menu.CPUFreq.20.build.f_cpu=20000000L +upesy_esp32c3_mini.menu.CPUFreq.10=10MHz +upesy_esp32c3_mini.menu.CPUFreq.10.build.f_cpu=10000000L + +upesy_esp32c3_mini.menu.FlashFreq.80=80MHz +upesy_esp32c3_mini.menu.FlashFreq.80.build.flash_freq=80m +upesy_esp32c3_mini.menu.FlashFreq.40=40MHz +upesy_esp32c3_mini.menu.FlashFreq.40.build.flash_freq=40m + +upesy_esp32c3_mini.menu.UploadSpeed.921600=921600 +upesy_esp32c3_mini.menu.UploadSpeed.921600.upload.speed=921600 +upesy_esp32c3_mini.menu.UploadSpeed.115200=115200 +upesy_esp32c3_mini.menu.UploadSpeed.115200.upload.speed=115200 +upesy_esp32c3_mini.menu.UploadSpeed.256000.windows=256000 +upesy_esp32c3_mini.menu.UploadSpeed.256000.upload.speed=256000 +upesy_esp32c3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000 +upesy_esp32c3_mini.menu.UploadSpeed.230400=230400 +upesy_esp32c3_mini.menu.UploadSpeed.230400.upload.speed=230400 +upesy_esp32c3_mini.menu.UploadSpeed.460800.linux=460800 +upesy_esp32c3_mini.menu.UploadSpeed.460800.macosx=460800 +upesy_esp32c3_mini.menu.UploadSpeed.460800.upload.speed=460800 +upesy_esp32c3_mini.menu.UploadSpeed.512000.windows=512000 +upesy_esp32c3_mini.menu.UploadSpeed.512000.upload.speed=512000 + +upesy_esp32c3_mini.menu.DebugLevel.none=None +upesy_esp32c3_mini.menu.DebugLevel.none.build.code_debug=0 +upesy_esp32c3_mini.menu.DebugLevel.error=Error +upesy_esp32c3_mini.menu.DebugLevel.error.build.code_debug=1 +upesy_esp32c3_mini.menu.DebugLevel.warn=Warn +upesy_esp32c3_mini.menu.DebugLevel.warn.build.code_debug=2 +upesy_esp32c3_mini.menu.DebugLevel.info=Info +upesy_esp32c3_mini.menu.DebugLevel.info.build.code_debug=3 +upesy_esp32c3_mini.menu.DebugLevel.debug=Debug +upesy_esp32c3_mini.menu.DebugLevel.debug.build.code_debug=4 +upesy_esp32c3_mini.menu.DebugLevel.verbose=Verbose +upesy_esp32c3_mini.menu.DebugLevel.verbose.build.code_debug=5 + +upesy_esp32c3_mini.menu.EraseFlash.none=Disabled +upesy_esp32c3_mini.menu.EraseFlash.none.upload.erase_cmd= +upesy_esp32c3_mini.menu.EraseFlash.all=Enabled +upesy_esp32c3_mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +upesy_esp32s3_basic.name=uPesy ESP32S3 Basic +upesy_esp32s3_basic.vid.0=0x303a +upesy_esp32s3_basic.pid.0=0x8192 + +upesy_esp32s3_basic.bootloader.tool=esptool_py +upesy_esp32s3_basic.bootloader.tool.default=esptool_py + +upesy_esp32s3_basic.upload.tool=esptool_py +upesy_esp32s3_basic.upload.tool.default=esptool_py +upesy_esp32s3_basic.upload.tool.network=esp_ota + +upesy_esp32s3_basic.upload.maximum_size=1310720 +upesy_esp32s3_basic.upload.maximum_data_size=327680 +upesy_esp32s3_basic.upload.flags= +upesy_esp32s3_basic.upload.extra_flags= +upesy_esp32s3_basic.upload.use_1200bps_touch=false +upesy_esp32s3_basic.upload.wait_for_upload_port=false + +upesy_esp32s3_basic.serial.disableDTR=false +upesy_esp32s3_basic.serial.disableRTS=false + +upesy_esp32s3_basic.build.tarch=xtensa +upesy_esp32s3_basic.build.bootloader_addr=0x0 +upesy_esp32s3_basic.build.target=esp32s3 +upesy_esp32s3_basic.build.mcu=esp32s3 +upesy_esp32s3_basic.build.core=esp32 +upesy_esp32s3_basic.build.variant=uPesy_esp32s3_basic +upesy_esp32s3_basic.build.board=UPESY_ESP32S3_BASIC + +upesy_esp32s3_basic.build.usb_mode=1 +upesy_esp32s3_basic.build.cdc_on_boot=0 +upesy_esp32s3_basic.build.msc_on_boot=0 +upesy_esp32s3_basic.build.dfu_on_boot=0 +upesy_esp32s3_basic.build.f_cpu=240000000L +upesy_esp32s3_basic.build.flash_size=16MB +upesy_esp32s3_basic.build.flash_freq=80m +upesy_esp32s3_basic.build.flash_mode=dio +upesy_esp32s3_basic.build.boot=qio +upesy_esp32s3_basic.build.boot_freq=80m +upesy_esp32s3_basic.build.partitions=default +upesy_esp32s3_basic.build.defines=-DBOARD_HAS_PSRAM +upesy_esp32s3_basic.build.loop_core= +upesy_esp32s3_basic.build.event_core= +upesy_esp32s3_basic.build.psram_type=opi +upesy_esp32s3_basic.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +upesy_esp32s3_basic.menu.JTAGAdapter.default=Disabled +upesy_esp32s3_basic.menu.JTAGAdapter.default.build.copy_jtag_files=0 +upesy_esp32s3_basic.menu.JTAGAdapter.builtin=Integrated USB JTAG +upesy_esp32s3_basic.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +upesy_esp32s3_basic.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +upesy_esp32s3_basic.menu.JTAGAdapter.external=FTDI Adapter +upesy_esp32s3_basic.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +upesy_esp32s3_basic.menu.JTAGAdapter.external.build.copy_jtag_files=1 +upesy_esp32s3_basic.menu.JTAGAdapter.bridge=ESP USB Bridge +upesy_esp32s3_basic.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +upesy_esp32s3_basic.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +upesy_esp32s3_basic.menu.FlashMode.qio=QIO 80MHz +upesy_esp32s3_basic.menu.FlashMode.qio.build.flash_mode=dio +upesy_esp32s3_basic.menu.FlashMode.qio.build.boot=qio +upesy_esp32s3_basic.menu.FlashMode.qio.build.boot_freq=80m +upesy_esp32s3_basic.menu.FlashMode.qio.build.flash_freq=80m +upesy_esp32s3_basic.menu.FlashMode.qio120=QIO 120MHz +upesy_esp32s3_basic.menu.FlashMode.qio120.build.flash_mode=dio +upesy_esp32s3_basic.menu.FlashMode.qio120.build.boot=qio +upesy_esp32s3_basic.menu.FlashMode.qio120.build.boot_freq=120m +upesy_esp32s3_basic.menu.FlashMode.qio120.build.flash_freq=80m + +upesy_esp32s3_basic.menu.LoopCore.1=Core 1 +upesy_esp32s3_basic.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +upesy_esp32s3_basic.menu.LoopCore.0=Core 0 +upesy_esp32s3_basic.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +upesy_esp32s3_basic.menu.EventsCore.1=Core 1 +upesy_esp32s3_basic.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +upesy_esp32s3_basic.menu.EventsCore.0=Core 0 +upesy_esp32s3_basic.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +upesy_esp32s3_basic.menu.USBMode.hwcdc=Hardware CDC and JTAG +upesy_esp32s3_basic.menu.USBMode.hwcdc.build.usb_mode=1 +upesy_esp32s3_basic.menu.USBMode.default=USB-OTG (TinyUSB) +upesy_esp32s3_basic.menu.USBMode.default.build.usb_mode=0 + +upesy_esp32s3_basic.menu.CDCOnBoot.default=Disabled +upesy_esp32s3_basic.menu.CDCOnBoot.default.build.cdc_on_boot=0 +upesy_esp32s3_basic.menu.CDCOnBoot.cdc=Enabled +upesy_esp32s3_basic.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +upesy_esp32s3_basic.menu.MSCOnBoot.default=Disabled +upesy_esp32s3_basic.menu.MSCOnBoot.default.build.msc_on_boot=0 +upesy_esp32s3_basic.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +upesy_esp32s3_basic.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +upesy_esp32s3_basic.menu.DFUOnBoot.default=Disabled +upesy_esp32s3_basic.menu.DFUOnBoot.default.build.dfu_on_boot=0 +upesy_esp32s3_basic.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +upesy_esp32s3_basic.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +upesy_esp32s3_basic.menu.UploadMode.default=UART0 / Hardware CDC +upesy_esp32s3_basic.menu.UploadMode.default.upload.use_1200bps_touch=false +upesy_esp32s3_basic.menu.UploadMode.default.upload.wait_for_upload_port=false +upesy_esp32s3_basic.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +upesy_esp32s3_basic.menu.UploadMode.cdc.upload.use_1200bps_touch=true +upesy_esp32s3_basic.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +upesy_esp32s3_basic.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +upesy_esp32s3_basic.menu.PartitionScheme.fatflash.build.partitions=ffat +upesy_esp32s3_basic.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +upesy_esp32s3_basic.menu.CPUFreq.240=240MHz (WiFi) +upesy_esp32s3_basic.menu.CPUFreq.240.build.f_cpu=240000000L +upesy_esp32s3_basic.menu.CPUFreq.160=160MHz (WiFi) +upesy_esp32s3_basic.menu.CPUFreq.160.build.f_cpu=160000000L +upesy_esp32s3_basic.menu.CPUFreq.80=80MHz (WiFi) +upesy_esp32s3_basic.menu.CPUFreq.80.build.f_cpu=80000000L +upesy_esp32s3_basic.menu.CPUFreq.40=40MHz +upesy_esp32s3_basic.menu.CPUFreq.40.build.f_cpu=40000000L +upesy_esp32s3_basic.menu.CPUFreq.20=20MHz +upesy_esp32s3_basic.menu.CPUFreq.20.build.f_cpu=20000000L +upesy_esp32s3_basic.menu.CPUFreq.10=10MHz +upesy_esp32s3_basic.menu.CPUFreq.10.build.f_cpu=10000000L + +upesy_esp32s3_basic.menu.UploadSpeed.921600=921600 +upesy_esp32s3_basic.menu.UploadSpeed.921600.upload.speed=921600 +upesy_esp32s3_basic.menu.UploadSpeed.115200=115200 +upesy_esp32s3_basic.menu.UploadSpeed.115200.upload.speed=115200 +upesy_esp32s3_basic.menu.UploadSpeed.256000.windows=256000 +upesy_esp32s3_basic.menu.UploadSpeed.256000.upload.speed=256000 +upesy_esp32s3_basic.menu.UploadSpeed.230400.windows.upload.speed=256000 +upesy_esp32s3_basic.menu.UploadSpeed.230400=230400 +upesy_esp32s3_basic.menu.UploadSpeed.230400.upload.speed=230400 +upesy_esp32s3_basic.menu.UploadSpeed.460800.linux=460800 +upesy_esp32s3_basic.menu.UploadSpeed.460800.macosx=460800 +upesy_esp32s3_basic.menu.UploadSpeed.460800.upload.speed=460800 +upesy_esp32s3_basic.menu.UploadSpeed.512000.windows=512000 +upesy_esp32s3_basic.menu.UploadSpeed.512000.upload.speed=512000 + +upesy_esp32s3_basic.menu.DebugLevel.none=None +upesy_esp32s3_basic.menu.DebugLevel.none.build.code_debug=0 +upesy_esp32s3_basic.menu.DebugLevel.error=Error +upesy_esp32s3_basic.menu.DebugLevel.error.build.code_debug=1 +upesy_esp32s3_basic.menu.DebugLevel.warn=Warn +upesy_esp32s3_basic.menu.DebugLevel.warn.build.code_debug=2 +upesy_esp32s3_basic.menu.DebugLevel.info=Info +upesy_esp32s3_basic.menu.DebugLevel.info.build.code_debug=3 +upesy_esp32s3_basic.menu.DebugLevel.debug=Debug +upesy_esp32s3_basic.menu.DebugLevel.debug.build.code_debug=4 +upesy_esp32s3_basic.menu.DebugLevel.verbose=Verbose +upesy_esp32s3_basic.menu.DebugLevel.verbose.build.code_debug=5 + +upesy_esp32s3_basic.menu.EraseFlash.none=Disabled +upesy_esp32s3_basic.menu.EraseFlash.none.upload.erase_cmd= +upesy_esp32s3_basic.menu.EraseFlash.all=Enabled +upesy_esp32s3_basic.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +kb32.name=KB32-FT + +kb32.bootloader.tool=esptool_py +kb32.bootloader.tool.default=esptool_py + +kb32.upload.tool=esptool_py +kb32.upload.tool.default=esptool_py +kb32.upload.tool.network=esp_ota + +kb32.upload.maximum_size=1310720 +kb32.upload.maximum_data_size=327680 +kb32.upload.flags= +kb32.upload.extra_flags= + +kb32.serial.disableDTR=true +kb32.serial.disableRTS=true + +kb32.build.tarch=xtensa +kb32.build.bootloader_addr=0x1000 +kb32.build.target=esp32 +kb32.build.mcu=esp32 +kb32.build.core=esp32 +kb32.build.variant=esp32 +kb32.build.board=ESP32_DEV + +kb32.build.f_cpu=240000000L +kb32.build.flash_size=4MB +kb32.build.flash_freq=40m +kb32.build.flash_mode=dio +kb32.build.boot=dio +kb32.build.partitions=default +kb32.build.defines= +kb32.build.loop_core= +kb32.build.event_core= + +kb32.menu.PSRAM.disabled=Disabled +kb32.menu.PSRAM.disabled.build.defines= +kb32.menu.PSRAM.disabled.build.extra_libs= +kb32.menu.PSRAM.enabled=Enabled +kb32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +kb32.menu.PSRAM.enabled.build.extra_libs= + +kb32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +kb32.menu.PartitionScheme.default.build.partitions=default +kb32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +kb32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +kb32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +kb32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +kb32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +kb32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +kb32.menu.PartitionScheme.minimal.build.partitions=minimal +kb32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +kb32.menu.PartitionScheme.no_ota.build.partitions=no_ota +kb32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +kb32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +kb32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +kb32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +kb32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +kb32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +kb32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +kb32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +kb32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +kb32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +kb32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +kb32.menu.PartitionScheme.huge_app.build.partitions=huge_app +kb32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +kb32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +kb32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +kb32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +kb32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +kb32.menu.PartitionScheme.fatflash.build.partitions=ffat +kb32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +kb32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +kb32.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +kb32.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +kb32.menu.PartitionScheme.rainmaker=RainMaker 4MB +kb32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +kb32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +kb32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +kb32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +kb32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +kb32.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +kb32.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +kb32.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +kb32.menu.CPUFreq.240=240MHz (WiFi/BT) +kb32.menu.CPUFreq.240.build.f_cpu=240000000L +kb32.menu.CPUFreq.160=160MHz (WiFi/BT) +kb32.menu.CPUFreq.160.build.f_cpu=160000000L +kb32.menu.CPUFreq.80=80MHz (WiFi/BT) +kb32.menu.CPUFreq.80.build.f_cpu=80000000L +kb32.menu.CPUFreq.40=40MHz (40MHz XTAL) +kb32.menu.CPUFreq.40.build.f_cpu=40000000L +kb32.menu.CPUFreq.26=26MHz (26MHz XTAL) +kb32.menu.CPUFreq.26.build.f_cpu=26000000L +kb32.menu.CPUFreq.20=20MHz (40MHz XTAL) +kb32.menu.CPUFreq.20.build.f_cpu=20000000L +kb32.menu.CPUFreq.13=13MHz (26MHz XTAL) +kb32.menu.CPUFreq.13.build.f_cpu=13000000L +kb32.menu.CPUFreq.10=10MHz (40MHz XTAL) +kb32.menu.CPUFreq.10.build.f_cpu=10000000L + +kb32.menu.FlashMode.qio=QIO +kb32.menu.FlashMode.qio.build.flash_mode=dio +kb32.menu.FlashMode.qio.build.boot=qio +kb32.menu.FlashMode.dio=DIO +kb32.menu.FlashMode.dio.build.flash_mode=dio +kb32.menu.FlashMode.dio.build.boot=dio + +kb32.menu.FlashFreq.80=80MHz +kb32.menu.FlashFreq.80.build.flash_freq=80m +kb32.menu.FlashFreq.40=40MHz +kb32.menu.FlashFreq.40.build.flash_freq=40m + +kb32.menu.FlashSize.4M=4MB (32Mb) +kb32.menu.FlashSize.4M.build.flash_size=4MB +kb32.menu.FlashSize.8M=8MB (64Mb) +kb32.menu.FlashSize.8M.build.flash_size=8MB +kb32.menu.FlashSize.2M=2MB (16Mb) +kb32.menu.FlashSize.2M.build.flash_size=2MB +kb32.menu.FlashSize.16M=16MB (128Mb) +kb32.menu.FlashSize.16M.build.flash_size=16MB + +kb32.menu.UploadSpeed.921600=921600 +kb32.menu.UploadSpeed.921600.upload.speed=921600 +kb32.menu.UploadSpeed.115200=115200 +kb32.menu.UploadSpeed.115200.upload.speed=115200 +kb32.menu.UploadSpeed.256000.windows=256000 +kb32.menu.UploadSpeed.256000.upload.speed=256000 +kb32.menu.UploadSpeed.230400.windows.upload.speed=256000 +kb32.menu.UploadSpeed.230400=230400 +kb32.menu.UploadSpeed.230400.upload.speed=230400 +kb32.menu.UploadSpeed.460800.linux=460800 +kb32.menu.UploadSpeed.460800.macosx=460800 +kb32.menu.UploadSpeed.460800.upload.speed=460800 +kb32.menu.UploadSpeed.512000.windows=512000 +kb32.menu.UploadSpeed.512000.upload.speed=512000 + +kb32.menu.LoopCore.1=Core 1 +kb32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +kb32.menu.LoopCore.0=Core 0 +kb32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +kb32.menu.EventsCore.1=Core 1 +kb32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +kb32.menu.EventsCore.0=Core 0 +kb32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +kb32.menu.DebugLevel.none=None +kb32.menu.DebugLevel.none.build.code_debug=0 +kb32.menu.DebugLevel.error=Error +kb32.menu.DebugLevel.error.build.code_debug=1 +kb32.menu.DebugLevel.warn=Warn +kb32.menu.DebugLevel.warn.build.code_debug=2 +kb32.menu.DebugLevel.info=Info +kb32.menu.DebugLevel.info.build.code_debug=3 +kb32.menu.DebugLevel.debug=Debug +kb32.menu.DebugLevel.debug.build.code_debug=4 +kb32.menu.DebugLevel.verbose=Verbose +kb32.menu.DebugLevel.verbose.build.code_debug=5 + +kb32.menu.EraseFlash.none=Disabled +kb32.menu.EraseFlash.none.upload.erase_cmd= +kb32.menu.EraseFlash.all=Enabled +kb32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapkart.name=Deneyap Kart + +deneyapkart.bootloader.tool=esptool_py +deneyapkart.bootloader.tool.default=esptool_py + +deneyapkart.upload.tool=esptool_py +deneyapkart.upload.tool.default=esptool_py +deneyapkart.upload.tool.network=esp_ota + +deneyapkart.upload.maximum_size=1310720 +deneyapkart.upload.maximum_data_size=327680 +deneyapkart.upload.flags= +deneyapkart.upload.extra_flags= + +deneyapkart.serial.disableDTR=true +deneyapkart.serial.disableRTS=true + +deneyapkart.build.tarch=xtensa +deneyapkart.build.bootloader_addr=0x1000 +deneyapkart.build.target=esp32 +deneyapkart.build.mcu=esp32 +deneyapkart.build.core=esp32 +deneyapkart.build.variant=deneyapkart +deneyapkart.build.board=DYDK + +deneyapkart.build.f_cpu=240000000L +deneyapkart.build.flash_size=4MB +deneyapkart.build.flash_freq=80m +deneyapkart.build.flash_mode=dio +deneyapkart.build.boot=qio +deneyapkart.build.partitions=default +deneyapkart.build.defines= +deneyapkart.build.loop_core= +deneyapkart.build.event_core= + +## IDE 2.0 Seems to not update the value +deneyapkart.menu.JTAGAdapter.default=Disabled +deneyapkart.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapkart.menu.JTAGAdapter.external=FTDI Adapter +deneyapkart.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg +deneyapkart.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapkart.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapkart.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg +deneyapkart.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapkart.menu.PSRAM.enabled=Enabled +deneyapkart.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +deneyapkart.menu.PSRAM.enabled.build.extra_libs= +deneyapkart.menu.PSRAM.disabled=Disabled +deneyapkart.menu.PSRAM.disabled.build.defines= +deneyapkart.menu.PSRAM.disabled.build.extra_libs= + +deneyapkart.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapkart.menu.PartitionScheme.default.build.partitions=default +deneyapkart.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapkart.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapkart.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapkart.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapkart.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapkart.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapkart.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapkart.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapkart.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapkart.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapkart.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapkart.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapkart.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapkart.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapkart.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapkart.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapkart.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapkart.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapkart.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapkart.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapkart.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapkart.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapkart.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapkart.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapkart.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapkart.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapkart.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapkart.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapkart.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapkart.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapkart.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapkart.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapkart.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapkart.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapkart.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapkart.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapkart.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapkart.menu.CPUFreq.240=240MHz (WiFi/BT) +deneyapkart.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapkart.menu.CPUFreq.160=160MHz (WiFi/BT) +deneyapkart.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapkart.menu.CPUFreq.80=80MHz (WiFi/BT) +deneyapkart.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapkart.menu.CPUFreq.40=40MHz (40MHz XTAL) +deneyapkart.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapkart.menu.CPUFreq.26=26MHz (26MHz XTAL) +deneyapkart.menu.CPUFreq.26.build.f_cpu=26000000L +deneyapkart.menu.CPUFreq.20=20MHz (40MHz XTAL) +deneyapkart.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapkart.menu.CPUFreq.13=13MHz (26MHz XTAL) +deneyapkart.menu.CPUFreq.13.build.f_cpu=13000000L +deneyapkart.menu.CPUFreq.10=10MHz (40MHz XTAL) +deneyapkart.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapkart.menu.FlashMode.qio=QIO +deneyapkart.menu.FlashMode.qio.build.flash_mode=dio +deneyapkart.menu.FlashMode.qio.build.boot=qio +deneyapkart.menu.FlashMode.dio=DIO +deneyapkart.menu.FlashMode.dio.build.flash_mode=dio +deneyapkart.menu.FlashMode.dio.build.boot=dio + +deneyapkart.menu.FlashFreq.80=80MHz +deneyapkart.menu.FlashFreq.80.build.flash_freq=80m +deneyapkart.menu.FlashFreq.40=40MHz +deneyapkart.menu.FlashFreq.40.build.flash_freq=40m + +deneyapkart.menu.FlashSize.4M=4MB (32Mb) +deneyapkart.menu.FlashSize.4M.build.flash_size=4MB +deneyapkart.menu.FlashSize.8M=8MB (64Mb) +deneyapkart.menu.FlashSize.8M.build.flash_size=8MB +deneyapkart.menu.FlashSize.2M=2MB (16Mb) +deneyapkart.menu.FlashSize.2M.build.flash_size=2MB +deneyapkart.menu.FlashSize.16M=16MB (128Mb) +deneyapkart.menu.FlashSize.16M.build.flash_size=16MB + +deneyapkart.menu.UploadSpeed.921600=921600 +deneyapkart.menu.UploadSpeed.921600.upload.speed=921600 +deneyapkart.menu.UploadSpeed.115200=115200 +deneyapkart.menu.UploadSpeed.115200.upload.speed=115200 +deneyapkart.menu.UploadSpeed.256000.windows=256000 +deneyapkart.menu.UploadSpeed.256000.upload.speed=256000 +deneyapkart.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapkart.menu.UploadSpeed.230400=230400 +deneyapkart.menu.UploadSpeed.230400.upload.speed=230400 +deneyapkart.menu.UploadSpeed.460800.linux=460800 +deneyapkart.menu.UploadSpeed.460800.macosx=460800 +deneyapkart.menu.UploadSpeed.460800.upload.speed=460800 +deneyapkart.menu.UploadSpeed.512000.windows=512000 +deneyapkart.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapkart.menu.LoopCore.1=Core 1 +deneyapkart.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +deneyapkart.menu.LoopCore.0=Core 0 +deneyapkart.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +deneyapkart.menu.EventsCore.1=Core 1 +deneyapkart.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +deneyapkart.menu.EventsCore.0=Core 0 +deneyapkart.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +deneyapkart.menu.DebugLevel.none=None +deneyapkart.menu.DebugLevel.none.build.code_debug=0 +deneyapkart.menu.DebugLevel.error=Error +deneyapkart.menu.DebugLevel.error.build.code_debug=1 +deneyapkart.menu.DebugLevel.warn=Warn +deneyapkart.menu.DebugLevel.warn.build.code_debug=2 +deneyapkart.menu.DebugLevel.info=Info +deneyapkart.menu.DebugLevel.info.build.code_debug=3 +deneyapkart.menu.DebugLevel.debug=Debug +deneyapkart.menu.DebugLevel.debug.build.code_debug=4 +deneyapkart.menu.DebugLevel.verbose=Verbose +deneyapkart.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapkart.menu.EraseFlash.none=Disabled +deneyapkart.menu.EraseFlash.none.upload.erase_cmd= +deneyapkart.menu.EraseFlash.all=Enabled +deneyapkart.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapkartv2.name=Deneyap Kart v2 + +deneyapkartv2.vid.0=0x303a +deneyapkartv2.pid.0=0x82EB + +deneyapkartv2.bootloader.tool=esptool_py +deneyapkartv2.bootloader.tool.default=esptool_py + +deneyapkartv2.upload.tool=esptool_py +deneyapkartv2.upload.tool.default=esptool_py +deneyapkartv2.upload.tool.network=esp_ota + +deneyapkartv2.upload.maximum_size=1310720 +deneyapkartv2.upload.maximum_data_size=327680 +deneyapkartv2.upload.flags= +deneyapkartv2.upload.extra_flags= +deneyapkartv2.upload.use_1200bps_touch=false +deneyapkartv2.upload.wait_for_upload_port=false + +deneyapkartv2.serial.disableDTR=false +deneyapkartv2.serial.disableRTS=false + +deneyapkartv2.build.tarch=xtensa +deneyapkartv2.build.bootloader_addr=0x0 +deneyapkartv2.build.target=esp32s3 +deneyapkartv2.build.mcu=esp32s3 +deneyapkartv2.build.core=esp32 +deneyapkartv2.build.variant=deneyapkartv2 +deneyapkartv2.build.board=DYDKV2 + +deneyapkartv2.build.usb_mode=1 +deneyapkartv2.build.cdc_on_boot=1 +deneyapkartv2.build.msc_on_boot=0 +deneyapkartv2.build.dfu_on_boot=0 +deneyapkartv2.build.f_cpu=240000000L +deneyapkartv2.build.flash_size=4MB +deneyapkartv2.build.flash_freq=80m +deneyapkartv2.build.flash_mode=dio +deneyapkartv2.build.boot=qio +deneyapkartv2.build.boot_freq=80m +deneyapkartv2.build.partitions=default +deneyapkartv2.build.defines=-DBOARD_HAS_PSRAM +deneyapkartv2.build.loop_core= +deneyapkartv2.build.event_core= +deneyapkartv2.build.psram_type=opi +deneyapkartv2.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +deneyapkartv2.menu.JTAGAdapter.default=Disabled +deneyapkartv2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapkartv2.menu.JTAGAdapter.builtin=Integrated USB JTAG +deneyapkartv2.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +deneyapkartv2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +deneyapkartv2.menu.JTAGAdapter.external=FTDI Adapter +deneyapkartv2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +deneyapkartv2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapkartv2.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapkartv2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +deneyapkartv2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapkartv2.menu.PSRAM.opi=OPI PSRAM +deneyapkartv2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +deneyapkartv2.menu.PSRAM.opi.build.psram_type=opi +deneyapkartv2.menu.PSRAM.disabled=Disabled +deneyapkartv2.menu.PSRAM.disabled.build.defines= +deneyapkartv2.menu.PSRAM.disabled.build.psram_type=qspi + +deneyapkartv2.menu.FlashMode.qio=QIO 80MHz +deneyapkartv2.menu.FlashMode.qio.build.flash_mode=dio +deneyapkartv2.menu.FlashMode.qio.build.boot=qio +deneyapkartv2.menu.FlashMode.qio.build.boot_freq=80m +deneyapkartv2.menu.FlashMode.qio.build.flash_freq=80m +deneyapkartv2.menu.FlashMode.qio120=QIO 120MHz +deneyapkartv2.menu.FlashMode.qio120.build.flash_mode=dio +deneyapkartv2.menu.FlashMode.qio120.build.boot=qio +deneyapkartv2.menu.FlashMode.qio120.build.boot_freq=120m +deneyapkartv2.menu.FlashMode.qio120.build.flash_freq=80m +deneyapkartv2.menu.FlashMode.dio=DIO 80MHz +deneyapkartv2.menu.FlashMode.dio.build.flash_mode=dio +deneyapkartv2.menu.FlashMode.dio.build.boot=dio +deneyapkartv2.menu.FlashMode.dio.build.boot_freq=80m +deneyapkartv2.menu.FlashMode.dio.build.flash_freq=80m +deneyapkartv2.menu.FlashMode.opi=OPI 80MHz +deneyapkartv2.menu.FlashMode.opi.build.flash_mode=dout +deneyapkartv2.menu.FlashMode.opi.build.boot=opi +deneyapkartv2.menu.FlashMode.opi.build.boot_freq=80m +deneyapkartv2.menu.FlashMode.opi.build.flash_freq=80m + +deneyapkartv2.menu.FlashSize.4M=4MB (32Mb) +deneyapkartv2.menu.FlashSize.4M.build.flash_size=4MB + +deneyapkartv2.menu.LoopCore.1=Core 1 +deneyapkartv2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +deneyapkartv2.menu.LoopCore.0=Core 0 +deneyapkartv2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +deneyapkartv2.menu.EventsCore.1=Core 1 +deneyapkartv2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +deneyapkartv2.menu.EventsCore.0=Core 0 +deneyapkartv2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +deneyapkartv2.menu.USBMode.hwcdc=Hardware CDC and JTAG +deneyapkartv2.menu.USBMode.hwcdc.build.usb_mode=1 +deneyapkartv2.menu.USBMode.default=USB-OTG (TinyUSB) +deneyapkartv2.menu.USBMode.default.build.usb_mode=0 + +deneyapkartv2.menu.CDCOnBoot.cdc=Enabled +deneyapkartv2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +deneyapkartv2.menu.CDCOnBoot.default=Disabled +deneyapkartv2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +deneyapkartv2.menu.MSCOnBoot.default=Disabled +deneyapkartv2.menu.MSCOnBoot.default.build.msc_on_boot=0 +deneyapkartv2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +deneyapkartv2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +deneyapkartv2.menu.DFUOnBoot.default=Disabled +deneyapkartv2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +deneyapkartv2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +deneyapkartv2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +deneyapkartv2.menu.UploadMode.default=UART0 / Hardware CDC +deneyapkartv2.menu.UploadMode.default.upload.use_1200bps_touch=false +deneyapkartv2.menu.UploadMode.default.upload.wait_for_upload_port=false +deneyapkartv2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +deneyapkartv2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +deneyapkartv2.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +deneyapkartv2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapkartv2.menu.PartitionScheme.default.build.partitions=default +deneyapkartv2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapkartv2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapkartv2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapkartv2.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapkartv2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +deneyapkartv2.menu.PartitionScheme.no_fs.build.partitions=no_fs +deneyapkartv2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +deneyapkartv2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapkartv2.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapkartv2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapkartv2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapkartv2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapkartv2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapkartv2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapkartv2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapkartv2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapkartv2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapkartv2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapkartv2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapkartv2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapkartv2.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapkartv2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapkartv2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapkartv2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapkartv2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapkartv2.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapkartv2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapkartv2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapkartv2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapkartv2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapkartv2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapkartv2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +deneyapkartv2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +deneyapkartv2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +deneyapkartv2.menu.PartitionScheme.custom=Custom +deneyapkartv2.menu.PartitionScheme.custom.build.partitions= +deneyapkartv2.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +deneyapkartv2.menu.CPUFreq.240=240MHz (WiFi) +deneyapkartv2.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapkartv2.menu.CPUFreq.160=160MHz (WiFi) +deneyapkartv2.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapkartv2.menu.CPUFreq.80=80MHz (WiFi) +deneyapkartv2.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapkartv2.menu.CPUFreq.40=40MHz +deneyapkartv2.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapkartv2.menu.CPUFreq.20=20MHz +deneyapkartv2.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapkartv2.menu.CPUFreq.10=10MHz +deneyapkartv2.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapkartv2.menu.UploadSpeed.921600=921600 +deneyapkartv2.menu.UploadSpeed.921600.upload.speed=921600 +deneyapkartv2.menu.UploadSpeed.115200=115200 +deneyapkartv2.menu.UploadSpeed.115200.upload.speed=115200 +deneyapkartv2.menu.UploadSpeed.256000.windows=256000 +deneyapkartv2.menu.UploadSpeed.256000.upload.speed=256000 +deneyapkartv2.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapkartv2.menu.UploadSpeed.230400=230400 +deneyapkartv2.menu.UploadSpeed.230400.upload.speed=230400 +deneyapkartv2.menu.UploadSpeed.460800.linux=460800 +deneyapkartv2.menu.UploadSpeed.460800.macosx=460800 +deneyapkartv2.menu.UploadSpeed.460800.upload.speed=460800 +deneyapkartv2.menu.UploadSpeed.512000.windows=512000 +deneyapkartv2.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapkartv2.menu.DebugLevel.none=None +deneyapkartv2.menu.DebugLevel.none.build.code_debug=0 +deneyapkartv2.menu.DebugLevel.error=Error +deneyapkartv2.menu.DebugLevel.error.build.code_debug=1 +deneyapkartv2.menu.DebugLevel.warn=Warn +deneyapkartv2.menu.DebugLevel.warn.build.code_debug=2 +deneyapkartv2.menu.DebugLevel.info=Info +deneyapkartv2.menu.DebugLevel.info.build.code_debug=3 +deneyapkartv2.menu.DebugLevel.debug=Debug +deneyapkartv2.menu.DebugLevel.debug.build.code_debug=4 +deneyapkartv2.menu.DebugLevel.verbose=Verbose +deneyapkartv2.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapkartv2.menu.EraseFlash.none=Disabled +deneyapkartv2.menu.EraseFlash.none.upload.erase_cmd= +deneyapkartv2.menu.EraseFlash.all=Enabled +deneyapkartv2.menu.EraseFlash.all.upload.erase_cmd=-e + +deneyapkartv2.menu.ZigbeeMode.default=Disabled +deneyapkartv2.menu.ZigbeeMode.default.build.zigbee_mode= +deneyapkartv2.menu.ZigbeeMode.default.build.zigbee_libs= +deneyapkartv2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +deneyapkartv2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +deneyapkartv2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +deneyapkart1A.name=Deneyap Kart 1A + +deneyapkart1A.bootloader.tool=esptool_py +deneyapkart1A.bootloader.tool.default=esptool_py + +deneyapkart1A.upload.tool=esptool_py +deneyapkart1A.upload.tool.default=esptool_py +deneyapkart1A.upload.tool.network=esp_ota + +deneyapkart1A.upload.maximum_size=1310720 +deneyapkart1A.upload.maximum_data_size=327680 +deneyapkart1A.upload.flags= +deneyapkart1A.upload.extra_flags= + +deneyapkart1A.serial.disableDTR=true +deneyapkart1A.serial.disableRTS=true + +deneyapkart1A.build.tarch=xtensa +deneyapkart1A.build.bootloader_addr=0x1000 +deneyapkart1A.build.target=esp32 +deneyapkart1A.build.mcu=esp32 +deneyapkart1A.build.core=esp32 +deneyapkart1A.build.variant=deneyapkart1A +deneyapkart1A.build.board=DYDK1A + +deneyapkart1A.build.f_cpu=240000000L +deneyapkart1A.build.flash_size=4MB +deneyapkart1A.build.flash_freq=80m +deneyapkart1A.build.flash_mode=dio +deneyapkart1A.build.boot=qio +deneyapkart1A.build.partitions=default +deneyapkart1A.build.defines= +deneyapkart1A.build.loop_core= +deneyapkart1A.build.event_core= + +## IDE 2.0 Seems to not update the value +deneyapkart1A.menu.JTAGAdapter.default=Disabled +deneyapkart1A.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapkart1A.menu.JTAGAdapter.external=FTDI Adapter +deneyapkart1A.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg +deneyapkart1A.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapkart1A.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapkart1A.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg +deneyapkart1A.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapkart1A.menu.PSRAM.enabled=Enabled +deneyapkart1A.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +deneyapkart1A.menu.PSRAM.enabled.build.extra_libs= +deneyapkart1A.menu.PSRAM.disabled=Disabled +deneyapkart1A.menu.PSRAM.disabled.build.defines= +deneyapkart1A.menu.PSRAM.disabled.build.extra_libs= + +deneyapkart1A.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapkart1A.menu.PartitionScheme.default.build.partitions=default +deneyapkart1A.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapkart1A.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapkart1A.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapkart1A.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapkart1A.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapkart1A.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapkart1A.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapkart1A.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapkart1A.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapkart1A.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapkart1A.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapkart1A.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapkart1A.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapkart1A.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapkart1A.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapkart1A.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapkart1A.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapkart1A.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapkart1A.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapkart1A.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapkart1A.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapkart1A.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapkart1A.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapkart1A.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapkart1A.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapkart1A.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapkart1A.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapkart1A.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapkart1A.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapkart1A.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapkart1A.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapkart1A.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapkart1A.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapkart1A.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapkart1A.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapkart1A.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapkart1A.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapkart1A.menu.CPUFreq.240=240MHz (WiFi/BT) +deneyapkart1A.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapkart1A.menu.CPUFreq.160=160MHz (WiFi/BT) +deneyapkart1A.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapkart1A.menu.CPUFreq.80=80MHz (WiFi/BT) +deneyapkart1A.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapkart1A.menu.CPUFreq.40=40MHz (40MHz XTAL) +deneyapkart1A.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapkart1A.menu.CPUFreq.26=26MHz (26MHz XTAL) +deneyapkart1A.menu.CPUFreq.26.build.f_cpu=26000000L +deneyapkart1A.menu.CPUFreq.20=20MHz (40MHz XTAL) +deneyapkart1A.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapkart1A.menu.CPUFreq.13=13MHz (26MHz XTAL) +deneyapkart1A.menu.CPUFreq.13.build.f_cpu=13000000L +deneyapkart1A.menu.CPUFreq.10=10MHz (40MHz XTAL) +deneyapkart1A.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapkart1A.menu.FlashMode.qio=QIO +deneyapkart1A.menu.FlashMode.qio.build.flash_mode=dio +deneyapkart1A.menu.FlashMode.qio.build.boot=qio +deneyapkart1A.menu.FlashMode.dio=DIO +deneyapkart1A.menu.FlashMode.dio.build.flash_mode=dio +deneyapkart1A.menu.FlashMode.dio.build.boot=dio + +deneyapkart1A.menu.FlashFreq.80=80MHz +deneyapkart1A.menu.FlashFreq.80.build.flash_freq=80m +deneyapkart1A.menu.FlashFreq.40=40MHz +deneyapkart1A.menu.FlashFreq.40.build.flash_freq=40m + +deneyapkart1A.menu.FlashSize.4M=4MB (32Mb) +deneyapkart1A.menu.FlashSize.4M.build.flash_size=4MB +deneyapkart1A.menu.FlashSize.8M=8MB (64Mb) +deneyapkart1A.menu.FlashSize.8M.build.flash_size=8MB +deneyapkart1A.menu.FlashSize.2M=2MB (16Mb) +deneyapkart1A.menu.FlashSize.2M.build.flash_size=2MB +deneyapkart1A.menu.FlashSize.16M=16MB (128Mb) +deneyapkart1A.menu.FlashSize.16M.build.flash_size=16MB + +deneyapkart1A.menu.UploadSpeed.921600=921600 +deneyapkart1A.menu.UploadSpeed.921600.upload.speed=921600 +deneyapkart1A.menu.UploadSpeed.115200=115200 +deneyapkart1A.menu.UploadSpeed.115200.upload.speed=115200 +deneyapkart1A.menu.UploadSpeed.256000.windows=256000 +deneyapkart1A.menu.UploadSpeed.256000.upload.speed=256000 +deneyapkart1A.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapkart1A.menu.UploadSpeed.230400=230400 +deneyapkart1A.menu.UploadSpeed.230400.upload.speed=230400 +deneyapkart1A.menu.UploadSpeed.460800.linux=460800 +deneyapkart1A.menu.UploadSpeed.460800.macosx=460800 +deneyapkart1A.menu.UploadSpeed.460800.upload.speed=460800 +deneyapkart1A.menu.UploadSpeed.512000.windows=512000 +deneyapkart1A.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapkart1A.menu.LoopCore.1=Core 1 +deneyapkart1A.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +deneyapkart1A.menu.LoopCore.0=Core 0 +deneyapkart1A.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +deneyapkart1A.menu.EventsCore.1=Core 1 +deneyapkart1A.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +deneyapkart1A.menu.EventsCore.0=Core 0 +deneyapkart1A.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +deneyapkart1A.menu.DebugLevel.none=None +deneyapkart1A.menu.DebugLevel.none.build.code_debug=0 +deneyapkart1A.menu.DebugLevel.error=Error +deneyapkart1A.menu.DebugLevel.error.build.code_debug=1 +deneyapkart1A.menu.DebugLevel.warn=Warn +deneyapkart1A.menu.DebugLevel.warn.build.code_debug=2 +deneyapkart1A.menu.DebugLevel.info=Info +deneyapkart1A.menu.DebugLevel.info.build.code_debug=3 +deneyapkart1A.menu.DebugLevel.debug=Debug +deneyapkart1A.menu.DebugLevel.debug.build.code_debug=4 +deneyapkart1A.menu.DebugLevel.verbose=Verbose +deneyapkart1A.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapkart1A.menu.EraseFlash.none=Disabled +deneyapkart1A.menu.EraseFlash.none.upload.erase_cmd= +deneyapkart1A.menu.EraseFlash.all=Enabled +deneyapkart1A.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapkart1Av2.name=Deneyap Kart 1A v2 + +deneyapkart1Av2.vid.0=0x303a +deneyapkart1Av2.pid.0=0x8147 + +deneyapkart1Av2.bootloader.tool=esptool_py +deneyapkart1Av2.bootloader.tool.default=esptool_py + +deneyapkart1Av2.upload.tool=esptool_py +deneyapkart1Av2.upload.tool.default=esptool_py +deneyapkart1Av2.upload.tool.network=esp_ota + +deneyapkart1Av2.upload.maximum_size=1310720 +deneyapkart1Av2.upload.maximum_data_size=327680 +deneyapkart1Av2.upload.flags= +deneyapkart1Av2.upload.extra_flags= +deneyapkart1Av2.upload.use_1200bps_touch=false +deneyapkart1Av2.upload.wait_for_upload_port=false + +deneyapkart1Av2.serial.disableDTR=false +deneyapkart1Av2.serial.disableRTS=false + +deneyapkart1Av2.build.tarch=xtensa +deneyapkart1Av2.build.bootloader_addr=0x0 +deneyapkart1Av2.build.target=esp32s3 +deneyapkart1Av2.build.mcu=esp32s3 +deneyapkart1Av2.build.core=esp32 +deneyapkart1Av2.build.variant=deneyapkart1Av2 +deneyapkart1Av2.build.board=DYDK1Av2 + +deneyapkart1Av2.build.usb_mode=1 +deneyapkart1Av2.build.cdc_on_boot=1 +deneyapkart1Av2.build.msc_on_boot=0 +deneyapkart1Av2.build.dfu_on_boot=0 +deneyapkart1Av2.build.f_cpu=240000000L +deneyapkart1Av2.build.flash_size=4MB +deneyapkart1Av2.build.flash_freq=80m +deneyapkart1Av2.build.flash_mode=dio +deneyapkart1Av2.build.boot=qio +deneyapkart1Av2.build.boot_freq=80m +deneyapkart1Av2.build.partitions=default +deneyapkart1Av2.build.defines=-DBOARD_HAS_PSRAM +deneyapkart1Av2.build.loop_core= +deneyapkart1Av2.build.event_core= +deneyapkart1Av2.build.psram_type=opi +deneyapkart1Av2.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +deneyapkart1Av2.menu.JTAGAdapter.default=Disabled +deneyapkart1Av2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapkart1Av2.menu.JTAGAdapter.builtin=Integrated USB JTAG +deneyapkart1Av2.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +deneyapkart1Av2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +deneyapkart1Av2.menu.JTAGAdapter.external=FTDI Adapter +deneyapkart1Av2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +deneyapkart1Av2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapkart1Av2.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapkart1Av2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +deneyapkart1Av2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapkart1Av2.menu.PSRAM.opi=OPI PSRAM +deneyapkart1Av2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +deneyapkart1Av2.menu.PSRAM.opi.build.psram_type=opi +deneyapkart1Av2.menu.PSRAM.disabled=Disabled +deneyapkart1Av2.menu.PSRAM.disabled.build.defines= +deneyapkart1Av2.menu.PSRAM.disabled.build.psram_type=qspi +deneyapkart1Av2.menu.PSRAM.enabled=QSPI PSRAM +deneyapkart1Av2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +deneyapkart1Av2.menu.PSRAM.enabled.build.psram_type=qspi + +deneyapkart1Av2.menu.FlashMode.qio=QIO 80MHz +deneyapkart1Av2.menu.FlashMode.qio.build.flash_mode=dio +deneyapkart1Av2.menu.FlashMode.qio.build.boot=qio +deneyapkart1Av2.menu.FlashMode.qio.build.boot_freq=80m +deneyapkart1Av2.menu.FlashMode.qio.build.flash_freq=80m +deneyapkart1Av2.menu.FlashMode.qio120=QIO 120MHz +deneyapkart1Av2.menu.FlashMode.qio120.build.flash_mode=dio +deneyapkart1Av2.menu.FlashMode.qio120.build.boot=qio +deneyapkart1Av2.menu.FlashMode.qio120.build.boot_freq=120m +deneyapkart1Av2.menu.FlashMode.qio120.build.flash_freq=80m +deneyapkart1Av2.menu.FlashMode.dio=DIO 80MHz +deneyapkart1Av2.menu.FlashMode.dio.build.flash_mode=dio +deneyapkart1Av2.menu.FlashMode.dio.build.boot=dio +deneyapkart1Av2.menu.FlashMode.dio.build.boot_freq=80m +deneyapkart1Av2.menu.FlashMode.dio.build.flash_freq=80m +deneyapkart1Av2.menu.FlashMode.opi=OPI 80MHz +deneyapkart1Av2.menu.FlashMode.opi.build.flash_mode=dout +deneyapkart1Av2.menu.FlashMode.opi.build.boot=opi +deneyapkart1Av2.menu.FlashMode.opi.build.boot_freq=80m +deneyapkart1Av2.menu.FlashMode.opi.build.flash_freq=80m + +deneyapkart1Av2.menu.FlashSize.4M=4MB (32Mb) +deneyapkart1Av2.menu.FlashSize.4M.build.flash_size=4MB +deneyapkart1Av2.menu.FlashSize.8M=8MB (64Mb) +deneyapkart1Av2.menu.FlashSize.8M.build.flash_size=8MB +deneyapkart1Av2.menu.FlashSize.16M=16MB (128Mb) +deneyapkart1Av2.menu.FlashSize.16M.build.flash_size=16MB +#deneyapkart1Av2.menu.FlashSize.32M=32MB (256Mb) +#deneyapkart1Av2.menu.FlashSize.32M.build.flash_size=32MB + +deneyapkart1Av2.menu.LoopCore.1=Core 1 +deneyapkart1Av2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +deneyapkart1Av2.menu.LoopCore.0=Core 0 +deneyapkart1Av2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +deneyapkart1Av2.menu.EventsCore.1=Core 1 +deneyapkart1Av2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +deneyapkart1Av2.menu.EventsCore.0=Core 0 +deneyapkart1Av2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +deneyapkart1Av2.menu.USBMode.hwcdc=Hardware CDC and JTAG +deneyapkart1Av2.menu.USBMode.hwcdc.build.usb_mode=1 +deneyapkart1Av2.menu.USBMode.default=USB-OTG (TinyUSB) +deneyapkart1Av2.menu.USBMode.default.build.usb_mode=0 + +deneyapkart1Av2.menu.CDCOnBoot.cdc=Enabled +deneyapkart1Av2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +deneyapkart1Av2.menu.CDCOnBoot.default=Disabled +deneyapkart1Av2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +deneyapkart1Av2.menu.MSCOnBoot.default=Disabled +deneyapkart1Av2.menu.MSCOnBoot.default.build.msc_on_boot=0 +deneyapkart1Av2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +deneyapkart1Av2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +deneyapkart1Av2.menu.DFUOnBoot.default=Disabled +deneyapkart1Av2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +deneyapkart1Av2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +deneyapkart1Av2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +deneyapkart1Av2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +deneyapkart1Av2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +deneyapkart1Av2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +deneyapkart1Av2.menu.UploadMode.default=UART0 / Hardware CDC +deneyapkart1Av2.menu.UploadMode.default.upload.use_1200bps_touch=false +deneyapkart1Av2.menu.UploadMode.default.upload.wait_for_upload_port=false + +deneyapkart1Av2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.default.build.partitions=default +deneyapkart1Av2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapkart1Av2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapkart1Av2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapkart1Av2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapkart1Av2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapkart1Av2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapkart1Av2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapkart1Av2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapkart1Av2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapkart1Av2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapkart1Av2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapkart1Av2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapkart1Av2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapkart1Av2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapkart1Av2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapkart1Av2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapkart1Av2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapkart1Av2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapkart1Av2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapkart1Av2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapkart1Av2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapkart1Av2.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapkart1Av2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapkart1Av2.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapkart1Av2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapkart1Av2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapkart1Av2.menu.CPUFreq.240=240MHz (WiFi) +deneyapkart1Av2.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapkart1Av2.menu.CPUFreq.160=160MHz (WiFi) +deneyapkart1Av2.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapkart1Av2.menu.CPUFreq.80=80MHz (WiFi) +deneyapkart1Av2.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapkart1Av2.menu.CPUFreq.40=40MHz +deneyapkart1Av2.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapkart1Av2.menu.CPUFreq.20=20MHz +deneyapkart1Av2.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapkart1Av2.menu.CPUFreq.10=10MHz +deneyapkart1Av2.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapkart1Av2.menu.UploadSpeed.921600=921600 +deneyapkart1Av2.menu.UploadSpeed.921600.upload.speed=921600 +deneyapkart1Av2.menu.UploadSpeed.115200=115200 +deneyapkart1Av2.menu.UploadSpeed.115200.upload.speed=115200 +deneyapkart1Av2.menu.UploadSpeed.256000.windows=256000 +deneyapkart1Av2.menu.UploadSpeed.256000.upload.speed=256000 +deneyapkart1Av2.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapkart1Av2.menu.UploadSpeed.230400=230400 +deneyapkart1Av2.menu.UploadSpeed.230400.upload.speed=230400 +deneyapkart1Av2.menu.UploadSpeed.460800.linux=460800 +deneyapkart1Av2.menu.UploadSpeed.460800.macosx=460800 +deneyapkart1Av2.menu.UploadSpeed.460800.upload.speed=460800 +deneyapkart1Av2.menu.UploadSpeed.512000.windows=512000 +deneyapkart1Av2.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapkart1Av2.menu.DebugLevel.none=None +deneyapkart1Av2.menu.DebugLevel.none.build.code_debug=0 +deneyapkart1Av2.menu.DebugLevel.error=Error +deneyapkart1Av2.menu.DebugLevel.error.build.code_debug=1 +deneyapkart1Av2.menu.DebugLevel.warn=Warn +deneyapkart1Av2.menu.DebugLevel.warn.build.code_debug=2 +deneyapkart1Av2.menu.DebugLevel.info=Info +deneyapkart1Av2.menu.DebugLevel.info.build.code_debug=3 +deneyapkart1Av2.menu.DebugLevel.debug=Debug +deneyapkart1Av2.menu.DebugLevel.debug.build.code_debug=4 +deneyapkart1Av2.menu.DebugLevel.verbose=Verbose +deneyapkart1Av2.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapkart1Av2.menu.EraseFlash.none=Disabled +deneyapkart1Av2.menu.EraseFlash.none.upload.erase_cmd= +deneyapkart1Av2.menu.EraseFlash.all=Enabled +deneyapkart1Av2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapmini.name=Deneyap Mini + +deneyapmini.vid.0=0x303a +deneyapmini.pid.0=0x8141 + +deneyapmini.bootloader.tool=esptool_py +deneyapmini.bootloader.tool.default=esptool_py + +deneyapmini.upload.tool=esptool_py +deneyapmini.upload.tool.default=esptool_py +deneyapmini.upload.tool.network=esp_ota + +deneyapmini.upload.maximum_size=1310720 +deneyapmini.upload.maximum_data_size=327680 +deneyapmini.upload.flags= +deneyapmini.upload.extra_flags= +deneyapmini.upload.use_1200bps_touch=false +deneyapmini.upload.wait_for_upload_port=false + +deneyapmini.serial.disableDTR=false +deneyapmini.serial.disableRTS=false + +deneyapmini.build.tarch=xtensa +deneyapmini.build.bootloader_addr=0x1000 +deneyapmini.build.target=esp32s2 +deneyapmini.build.mcu=esp32s2 +deneyapmini.build.core=esp32 +deneyapmini.build.variant=deneyapmini +deneyapmini.build.board=DYM + +deneyapmini.build.cdc_on_boot=1 +deneyapmini.build.msc_on_boot=0 +deneyapmini.build.dfu_on_boot=0 +deneyapmini.build.f_cpu=240000000L +deneyapmini.build.flash_size=4MB +deneyapmini.build.flash_freq=80m +deneyapmini.build.flash_mode=dio +deneyapmini.build.boot=qio +deneyapmini.build.partitions=default +deneyapmini.build.defines= + +## IDE 2.0 Seems to not update the value +deneyapmini.menu.JTAGAdapter.default=Disabled +deneyapmini.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapmini.menu.JTAGAdapter.external=FTDI Adapter +deneyapmini.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg +deneyapmini.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapmini.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapmini.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg +deneyapmini.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapmini.menu.CDCOnBoot.cdc=Enabled +deneyapmini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +deneyapmini.menu.CDCOnBoot.default=Disabled +deneyapmini.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +deneyapmini.menu.MSCOnBoot.default=Disabled +deneyapmini.menu.MSCOnBoot.default.build.msc_on_boot=0 +deneyapmini.menu.MSCOnBoot.msc=Enabled +deneyapmini.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +deneyapmini.menu.DFUOnBoot.default=Disabled +deneyapmini.menu.DFUOnBoot.default.build.dfu_on_boot=0 +deneyapmini.menu.DFUOnBoot.dfu=Enabled +deneyapmini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +deneyapmini.menu.UploadMode.cdc=Internal USB +deneyapmini.menu.UploadMode.cdc.upload.use_1200bps_touch=true +deneyapmini.menu.UploadMode.cdc.upload.wait_for_upload_port=true +deneyapmini.menu.UploadMode.default=UART0 +deneyapmini.menu.UploadMode.default.upload.use_1200bps_touch=false +deneyapmini.menu.UploadMode.default.upload.wait_for_upload_port=false + +deneyapmini.menu.PSRAM.disabled=Disabled +deneyapmini.menu.PSRAM.disabled.build.defines= +deneyapmini.menu.PSRAM.enabled=Enabled +deneyapmini.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +deneyapmini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapmini.menu.PartitionScheme.default.build.partitions=default +deneyapmini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapmini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapmini.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapmini.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapmini.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapmini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapmini.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapmini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapmini.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapmini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapmini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapmini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapmini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapmini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapmini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapmini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapmini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapmini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapmini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapmini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapmini.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapmini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapmini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapmini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapmini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapmini.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapmini.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapmini.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapmini.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapmini.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapmini.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapmini.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapmini.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapmini.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapmini.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapmini.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapmini.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapmini.menu.CPUFreq.240=240MHz (WiFi) +deneyapmini.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapmini.menu.CPUFreq.160=160MHz (WiFi) +deneyapmini.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapmini.menu.CPUFreq.80=80MHz (WiFi) +deneyapmini.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapmini.menu.CPUFreq.40=40MHz +deneyapmini.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapmini.menu.CPUFreq.20=20MHz +deneyapmini.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapmini.menu.CPUFreq.10=10MHz +deneyapmini.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapmini.menu.FlashMode.qio=QIO +deneyapmini.menu.FlashMode.qio.build.flash_mode=dio +deneyapmini.menu.FlashMode.qio.build.boot=qio +deneyapmini.menu.FlashMode.dio=DIO +deneyapmini.menu.FlashMode.dio.build.flash_mode=dio +deneyapmini.menu.FlashMode.dio.build.boot=dio + +deneyapmini.menu.FlashFreq.80=80MHz +deneyapmini.menu.FlashFreq.80.build.flash_freq=80m +deneyapmini.menu.FlashFreq.40=40MHz +deneyapmini.menu.FlashFreq.40.build.flash_freq=40m + +deneyapmini.menu.FlashSize.4M=4MB (32Mb) +deneyapmini.menu.FlashSize.4M.build.flash_size=4MB +deneyapmini.menu.FlashSize.8M=8MB (64Mb) +deneyapmini.menu.FlashSize.8M.build.flash_size=8MB +deneyapmini.menu.FlashSize.2M=2MB (16Mb) +deneyapmini.menu.FlashSize.2M.build.flash_size=2MB +deneyapmini.menu.FlashSize.16M=16MB (128Mb) +deneyapmini.menu.FlashSize.16M.build.flash_size=16MB + +deneyapmini.menu.UploadSpeed.921600=921600 +deneyapmini.menu.UploadSpeed.921600.upload.speed=921600 +deneyapmini.menu.UploadSpeed.115200=115200 +deneyapmini.menu.UploadSpeed.115200.upload.speed=115200 +deneyapmini.menu.UploadSpeed.256000.windows=256000 +deneyapmini.menu.UploadSpeed.256000.upload.speed=256000 +deneyapmini.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapmini.menu.UploadSpeed.230400=230400 +deneyapmini.menu.UploadSpeed.230400.upload.speed=230400 +deneyapmini.menu.UploadSpeed.460800.linux=460800 +deneyapmini.menu.UploadSpeed.460800.macosx=460800 +deneyapmini.menu.UploadSpeed.460800.upload.speed=460800 +deneyapmini.menu.UploadSpeed.512000.windows=512000 +deneyapmini.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapmini.menu.DebugLevel.none=None +deneyapmini.menu.DebugLevel.none.build.code_debug=0 +deneyapmini.menu.DebugLevel.error=Error +deneyapmini.menu.DebugLevel.error.build.code_debug=1 +deneyapmini.menu.DebugLevel.warn=Warn +deneyapmini.menu.DebugLevel.warn.build.code_debug=2 +deneyapmini.menu.DebugLevel.info=Info +deneyapmini.menu.DebugLevel.info.build.code_debug=3 +deneyapmini.menu.DebugLevel.debug=Debug +deneyapmini.menu.DebugLevel.debug.build.code_debug=4 +deneyapmini.menu.DebugLevel.verbose=Verbose +deneyapmini.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapmini.menu.EraseFlash.none=Disabled +deneyapmini.menu.EraseFlash.none.upload.erase_cmd= +deneyapmini.menu.EraseFlash.all=Enabled +deneyapmini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapminiv2.name=Deneyap Mini v2 + +deneyapminiv2.vid.0=0x303a +deneyapminiv2.pid.0=0x8144 + +deneyapminiv2.bootloader.tool=esptool_py +deneyapminiv2.bootloader.tool.default=esptool_py + +deneyapminiv2.upload.tool=esptool_py +deneyapminiv2.upload.tool.default=esptool_py +deneyapminiv2.upload.tool.network=esp_ota + +deneyapminiv2.upload.maximum_size=1310720 +deneyapminiv2.upload.maximum_data_size=327680 +deneyapminiv2.upload.flags= +deneyapminiv2.upload.extra_flags= +deneyapminiv2.upload.use_1200bps_touch=false +deneyapminiv2.upload.wait_for_upload_port=false + +deneyapminiv2.serial.disableDTR=false +deneyapminiv2.serial.disableRTS=false + +deneyapminiv2.build.tarch=xtensa +deneyapminiv2.build.bootloader_addr=0x1000 +deneyapminiv2.build.target=esp32s2 +deneyapminiv2.build.mcu=esp32s2 +deneyapminiv2.build.core=esp32 +deneyapminiv2.build.variant=deneyapminiv2 +deneyapminiv2.build.board=DYMv2 + +deneyapminiv2.build.cdc_on_boot=1 +deneyapminiv2.build.msc_on_boot=0 +deneyapminiv2.build.dfu_on_boot=0 +deneyapminiv2.build.f_cpu=240000000L +deneyapminiv2.build.flash_size=4MB +deneyapminiv2.build.flash_freq=80m +deneyapminiv2.build.flash_mode=dio +deneyapminiv2.build.boot=qio +deneyapminiv2.build.partitions=default +deneyapminiv2.build.defines=-DBOARD_HAS_PSRAM + +## IDE 2.0 Seems to not update the value +deneyapminiv2.menu.JTAGAdapter.default=Disabled +deneyapminiv2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapminiv2.menu.JTAGAdapter.external=FTDI Adapter +deneyapminiv2.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg +deneyapminiv2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapminiv2.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapminiv2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg +deneyapminiv2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapminiv2.menu.CDCOnBoot.cdc=Enabled +deneyapminiv2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +deneyapminiv2.menu.CDCOnBoot.default=Disabled +deneyapminiv2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +deneyapminiv2.menu.MSCOnBoot.default=Disabled +deneyapminiv2.menu.MSCOnBoot.default.build.msc_on_boot=0 +deneyapminiv2.menu.MSCOnBoot.msc=Enabled +deneyapminiv2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +deneyapminiv2.menu.DFUOnBoot.default=Disabled +deneyapminiv2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +deneyapminiv2.menu.DFUOnBoot.dfu=Enabled +deneyapminiv2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +deneyapminiv2.menu.UploadMode.cdc=Internal USB +deneyapminiv2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +deneyapminiv2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +deneyapminiv2.menu.UploadMode.default=UART0 +deneyapminiv2.menu.UploadMode.default.upload.use_1200bps_touch=false +deneyapminiv2.menu.UploadMode.default.upload.wait_for_upload_port=false + +deneyapminiv2.menu.PSRAM.enabled=Enabled +deneyapminiv2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +deneyapminiv2.menu.PSRAM.disabled=Disabled +deneyapminiv2.menu.PSRAM.disabled.build.defines= + +deneyapminiv2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapminiv2.menu.PartitionScheme.default.build.partitions=default +deneyapminiv2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapminiv2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapminiv2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapminiv2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapminiv2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapminiv2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapminiv2.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapminiv2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapminiv2.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapminiv2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapminiv2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapminiv2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapminiv2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapminiv2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapminiv2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapminiv2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapminiv2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapminiv2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapminiv2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapminiv2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapminiv2.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapminiv2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapminiv2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapminiv2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapminiv2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapminiv2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapminiv2.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapminiv2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapminiv2.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapminiv2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapminiv2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapminiv2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapminiv2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapminiv2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapminiv2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapminiv2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapminiv2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapminiv2.menu.CPUFreq.240=240MHz (WiFi) +deneyapminiv2.menu.CPUFreq.240.build.f_cpu=240000000L +deneyapminiv2.menu.CPUFreq.160=160MHz (WiFi) +deneyapminiv2.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapminiv2.menu.CPUFreq.80=80MHz (WiFi) +deneyapminiv2.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapminiv2.menu.CPUFreq.40=40MHz +deneyapminiv2.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapminiv2.menu.CPUFreq.20=20MHz +deneyapminiv2.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapminiv2.menu.CPUFreq.10=10MHz +deneyapminiv2.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapminiv2.menu.FlashMode.qio=QIO +deneyapminiv2.menu.FlashMode.qio.build.flash_mode=dio +deneyapminiv2.menu.FlashMode.qio.build.boot=qio +deneyapminiv2.menu.FlashMode.dio=DIO +deneyapminiv2.menu.FlashMode.dio.build.flash_mode=dio +deneyapminiv2.menu.FlashMode.dio.build.boot=dio + +deneyapminiv2.menu.FlashFreq.80=80MHz +deneyapminiv2.menu.FlashFreq.80.build.flash_freq=80m +deneyapminiv2.menu.FlashFreq.40=40MHz +deneyapminiv2.menu.FlashFreq.40.build.flash_freq=40m + +deneyapminiv2.menu.FlashSize.4M=4MB (32Mb) +deneyapminiv2.menu.FlashSize.4M.build.flash_size=4MB +deneyapminiv2.menu.FlashSize.8M=8MB (64Mb) +deneyapminiv2.menu.FlashSize.8M.build.flash_size=8MB +deneyapminiv2.menu.FlashSize.2M=2MB (16Mb) +deneyapminiv2.menu.FlashSize.2M.build.flash_size=2MB +deneyapminiv2.menu.FlashSize.16M=16MB (128Mb) +deneyapminiv2.menu.FlashSize.16M.build.flash_size=16MB + +deneyapminiv2.menu.UploadSpeed.921600=921600 +deneyapminiv2.menu.UploadSpeed.921600.upload.speed=921600 +deneyapminiv2.menu.UploadSpeed.115200=115200 +deneyapminiv2.menu.UploadSpeed.115200.upload.speed=115200 +deneyapminiv2.menu.UploadSpeed.256000.windows=256000 +deneyapminiv2.menu.UploadSpeed.256000.upload.speed=256000 +deneyapminiv2.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapminiv2.menu.UploadSpeed.230400=230400 +deneyapminiv2.menu.UploadSpeed.230400.upload.speed=230400 +deneyapminiv2.menu.UploadSpeed.460800.linux=460800 +deneyapminiv2.menu.UploadSpeed.460800.macosx=460800 +deneyapminiv2.menu.UploadSpeed.460800.upload.speed=460800 +deneyapminiv2.menu.UploadSpeed.512000.windows=512000 +deneyapminiv2.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapminiv2.menu.DebugLevel.none=None +deneyapminiv2.menu.DebugLevel.none.build.code_debug=0 +deneyapminiv2.menu.DebugLevel.error=Error +deneyapminiv2.menu.DebugLevel.error.build.code_debug=1 +deneyapminiv2.menu.DebugLevel.warn=Warn +deneyapminiv2.menu.DebugLevel.warn.build.code_debug=2 +deneyapminiv2.menu.DebugLevel.info=Info +deneyapminiv2.menu.DebugLevel.info.build.code_debug=3 +deneyapminiv2.menu.DebugLevel.debug=Debug +deneyapminiv2.menu.DebugLevel.debug.build.code_debug=4 +deneyapminiv2.menu.DebugLevel.verbose=Verbose +deneyapminiv2.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapminiv2.menu.EraseFlash.none=Disabled +deneyapminiv2.menu.EraseFlash.none.upload.erase_cmd= +deneyapminiv2.menu.EraseFlash.all=Enabled +deneyapminiv2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +deneyapkartg.name=Deneyap Kart G + +deneyapkartg.vid.0=0x303a +deneyapkartg.pid.0=0x814A + +deneyapkartg.bootloader.tool=esptool_py +deneyapkartg.bootloader.tool.default=esptool_py + +deneyapkartg.upload.tool=esptool_py +deneyapkartg.upload.tool.default=esptool_py +deneyapkartg.upload.tool.network=esp_ota + +deneyapkartg.upload.maximum_size=1310720 +deneyapkartg.upload.maximum_data_size=327680 +deneyapkartg.upload.flags= +deneyapkartg.upload.extra_flags= +deneyapkartg.upload.use_1200bps_touch=false +deneyapkartg.upload.wait_for_upload_port=false + +deneyapkartg.serial.disableDTR=false +deneyapkartg.serial.disableRTS=false + +deneyapkartg.build.tarch=riscv32 +deneyapkartg.build.target=esp +deneyapkartg.build.mcu=esp32c3 +deneyapkartg.build.core=esp32 +deneyapkartg.build.variant=deneyapkartg +deneyapkartg.build.board=DYG +deneyapkartg.build.bootloader_addr=0x0 + +deneyapkartg.build.cdc_on_boot=1 +deneyapkartg.build.f_cpu=160000000L +deneyapkartg.build.flash_size=4MB +deneyapkartg.build.flash_freq=80m +deneyapkartg.build.flash_mode=dio +deneyapkartg.build.boot=qio +deneyapkartg.build.partitions=default +deneyapkartg.build.defines= + +## IDE 2.0 Seems to not update the value +deneyapkartg.menu.JTAGAdapter.default=Disabled +deneyapkartg.menu.JTAGAdapter.default.build.copy_jtag_files=0 +deneyapkartg.menu.JTAGAdapter.builtin=Integrated USB JTAG +deneyapkartg.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +deneyapkartg.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +deneyapkartg.menu.JTAGAdapter.external=FTDI Adapter +deneyapkartg.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +deneyapkartg.menu.JTAGAdapter.external.build.copy_jtag_files=1 +deneyapkartg.menu.JTAGAdapter.bridge=ESP USB Bridge +deneyapkartg.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +deneyapkartg.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +deneyapkartg.menu.CDCOnBoot.cdc=Enabled +deneyapkartg.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +deneyapkartg.menu.CDCOnBoot.default=Disabled +deneyapkartg.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +deneyapkartg.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +deneyapkartg.menu.PartitionScheme.default.build.partitions=default +deneyapkartg.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +deneyapkartg.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +deneyapkartg.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +deneyapkartg.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +deneyapkartg.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +deneyapkartg.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +deneyapkartg.menu.PartitionScheme.minimal.build.partitions=minimal +deneyapkartg.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +deneyapkartg.menu.PartitionScheme.no_ota.build.partitions=no_ota +deneyapkartg.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +deneyapkartg.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +deneyapkartg.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +deneyapkartg.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +deneyapkartg.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +deneyapkartg.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +deneyapkartg.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +deneyapkartg.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +deneyapkartg.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +deneyapkartg.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +deneyapkartg.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +deneyapkartg.menu.PartitionScheme.huge_app.build.partitions=huge_app +deneyapkartg.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +deneyapkartg.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +deneyapkartg.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +deneyapkartg.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +deneyapkartg.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +deneyapkartg.menu.PartitionScheme.fatflash.build.partitions=ffat +deneyapkartg.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +deneyapkartg.menu.PartitionScheme.rainmaker=RainMaker 4MB +deneyapkartg.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +deneyapkartg.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +deneyapkartg.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +deneyapkartg.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +deneyapkartg.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +deneyapkartg.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +deneyapkartg.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +deneyapkartg.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +deneyapkartg.menu.CPUFreq.160=160MHz (WiFi) +deneyapkartg.menu.CPUFreq.160.build.f_cpu=160000000L +deneyapkartg.menu.CPUFreq.80=80MHz (WiFi) +deneyapkartg.menu.CPUFreq.80.build.f_cpu=80000000L +deneyapkartg.menu.CPUFreq.40=40MHz +deneyapkartg.menu.CPUFreq.40.build.f_cpu=40000000L +deneyapkartg.menu.CPUFreq.20=20MHz +deneyapkartg.menu.CPUFreq.20.build.f_cpu=20000000L +deneyapkartg.menu.CPUFreq.10=10MHz +deneyapkartg.menu.CPUFreq.10.build.f_cpu=10000000L + +deneyapkartg.menu.FlashMode.qio=QIO +deneyapkartg.menu.FlashMode.qio.build.flash_mode=dio +deneyapkartg.menu.FlashMode.qio.build.boot=qio +deneyapkartg.menu.FlashMode.dio=DIO +deneyapkartg.menu.FlashMode.dio.build.flash_mode=dio +deneyapkartg.menu.FlashMode.dio.build.boot=dio + +deneyapkartg.menu.FlashFreq.80=80MHz +deneyapkartg.menu.FlashFreq.80.build.flash_freq=80m +deneyapkartg.menu.FlashFreq.40=40MHz +deneyapkartg.menu.FlashFreq.40.build.flash_freq=40m + +deneyapkartg.menu.FlashSize.4M=4MB (32Mb) +deneyapkartg.menu.FlashSize.4M.build.flash_size=4MB +deneyapkartg.menu.FlashSize.8M=8MB (64Mb) +deneyapkartg.menu.FlashSize.8M.build.flash_size=8MB +deneyapkartg.menu.FlashSize.2M=2MB (16Mb) +deneyapkartg.menu.FlashSize.2M.build.flash_size=2MB +deneyapkartg.menu.FlashSize.16M=16MB (128Mb) +deneyapkartg.menu.FlashSize.16M.build.flash_size=16MB + +deneyapkartg.menu.UploadSpeed.921600=921600 +deneyapkartg.menu.UploadSpeed.921600.upload.speed=921600 +deneyapkartg.menu.UploadSpeed.115200=115200 +deneyapkartg.menu.UploadSpeed.115200.upload.speed=115200 +deneyapkartg.menu.UploadSpeed.256000.windows=256000 +deneyapkartg.menu.UploadSpeed.256000.upload.speed=256000 +deneyapkartg.menu.UploadSpeed.230400.windows.upload.speed=256000 +deneyapkartg.menu.UploadSpeed.230400=230400 +deneyapkartg.menu.UploadSpeed.230400.upload.speed=230400 +deneyapkartg.menu.UploadSpeed.460800.linux=460800 +deneyapkartg.menu.UploadSpeed.460800.macosx=460800 +deneyapkartg.menu.UploadSpeed.460800.upload.speed=460800 +deneyapkartg.menu.UploadSpeed.512000.windows=512000 +deneyapkartg.menu.UploadSpeed.512000.upload.speed=512000 + +deneyapkartg.menu.DebugLevel.none=None +deneyapkartg.menu.DebugLevel.none.build.code_debug=0 +deneyapkartg.menu.DebugLevel.error=Error +deneyapkartg.menu.DebugLevel.error.build.code_debug=1 +deneyapkartg.menu.DebugLevel.warn=Warn +deneyapkartg.menu.DebugLevel.warn.build.code_debug=2 +deneyapkartg.menu.DebugLevel.info=Info +deneyapkartg.menu.DebugLevel.info.build.code_debug=3 +deneyapkartg.menu.DebugLevel.debug=Debug +deneyapkartg.menu.DebugLevel.debug.build.code_debug=4 +deneyapkartg.menu.DebugLevel.verbose=Verbose +deneyapkartg.menu.DebugLevel.verbose.build.code_debug=5 + +deneyapkartg.menu.EraseFlash.none=Disabled +deneyapkartg.menu.EraseFlash.none.upload.erase_cmd= +deneyapkartg.menu.EraseFlash.all=Enabled +deneyapkartg.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-trueverit-iot-driver.name=Trueverit ESP32 Universal IoT Driver + +esp32-trueverit-iot-driver.bootloader.tool=esptool_py +esp32-trueverit-iot-driver.bootloader.tool.default=esptool_py + +esp32-trueverit-iot-driver.upload.tool=esptool_py +esp32-trueverit-iot-driver.upload.tool.default=esptool_py +esp32-trueverit-iot-driver.upload.tool.network=esp_ota + +esp32-trueverit-iot-driver.upload.maximum_size=1310720 +esp32-trueverit-iot-driver.upload.maximum_data_size=327680 +esp32-trueverit-iot-driver.upload.flags= +esp32-trueverit-iot-driver.upload.extra_flags= + +esp32-trueverit-iot-driver.serial.disableDTR=true +esp32-trueverit-iot-driver.serial.disableRTS=true + +esp32-trueverit-iot-driver.build.tarch=xtensa +esp32-trueverit-iot-driver.build.bootloader_addr=0x1000 +esp32-trueverit-iot-driver.build.target=esp32 +esp32-trueverit-iot-driver.build.mcu=esp32 +esp32-trueverit-iot-driver.build.core=esp32 +esp32-trueverit-iot-driver.build.variant=esp32-trueverit-iot-driver +esp32-trueverit-iot-driver.build.board=Trueverit_ESP32_Universal_IoT_Driver + +esp32-trueverit-iot-driver.build.f_cpu=240000000L +esp32-trueverit-iot-driver.build.flash_mode=dio +esp32-trueverit-iot-driver.build.flash_size=4MB +esp32-trueverit-iot-driver.build.boot=dio +esp32-trueverit-iot-driver.build.partitions=default +esp32-trueverit-iot-driver.build.defines= + +esp32-trueverit-iot-driver.menu.FlashFreq.80=80MHz +esp32-trueverit-iot-driver.menu.FlashFreq.80.build.flash_freq=80m +esp32-trueverit-iot-driver.menu.FlashFreq.40=40MHz +esp32-trueverit-iot-driver.menu.FlashFreq.40.build.flash_freq=40m + +esp32-trueverit-iot-driver.menu.UploadSpeed.115200=115200 +esp32-trueverit-iot-driver.menu.UploadSpeed.115200.upload.speed=115200 +esp32-trueverit-iot-driver.menu.UploadSpeed.256000.windows=256000 +esp32-trueverit-iot-driver.menu.UploadSpeed.256000.upload.speed=256000 +esp32-trueverit-iot-driver.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-trueverit-iot-driver.menu.UploadSpeed.230400=230400 +esp32-trueverit-iot-driver.menu.UploadSpeed.230400.upload.speed=230400 +esp32-trueverit-iot-driver.menu.UploadSpeed.460800.linux=460800 +esp32-trueverit-iot-driver.menu.UploadSpeed.460800.macosx=460800 +esp32-trueverit-iot-driver.menu.UploadSpeed.460800.upload.speed=460800 + +esp32-trueverit-iot-driver.menu.DebugLevel.none=None +esp32-trueverit-iot-driver.menu.DebugLevel.none.build.code_debug=0 +esp32-trueverit-iot-driver.menu.DebugLevel.error=Error +esp32-trueverit-iot-driver.menu.DebugLevel.error.build.code_debug=1 +esp32-trueverit-iot-driver.menu.DebugLevel.warn=Warn +esp32-trueverit-iot-driver.menu.DebugLevel.warn.build.code_debug=2 +esp32-trueverit-iot-driver.menu.DebugLevel.info=Info +esp32-trueverit-iot-driver.menu.DebugLevel.info.build.code_debug=3 +esp32-trueverit-iot-driver.menu.DebugLevel.debug=Debug +esp32-trueverit-iot-driver.menu.DebugLevel.debug.build.code_debug=4 +esp32-trueverit-iot-driver.menu.DebugLevel.verbose=Verbose +esp32-trueverit-iot-driver.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-trueverit-iot-driver.menu.EraseFlash.none=Disabled +esp32-trueverit-iot-driver.menu.EraseFlash.none.upload.erase_cmd= +esp32-trueverit-iot-driver.menu.EraseFlash.all=Enabled +esp32-trueverit-iot-driver.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32-trueverit-iot-driver-mkii.name=Trueverit ESP32 Universal IoT Driver MK II + +esp32-trueverit-iot-driver-mkii.bootloader.tool=esptool_py +esp32-trueverit-iot-driver-mkii.bootloader.tool.default=esptool_py + +esp32-trueverit-iot-driver-mkii.upload.tool=esptool_py +esp32-trueverit-iot-driver-mkii.upload.tool.default=esptool_py +esp32-trueverit-iot-driver-mkii.upload.tool.network=esp_ota + +esp32-trueverit-iot-driver-mkii.upload.maximum_size=1310720 +esp32-trueverit-iot-driver-mkii.upload.maximum_data_size=327680 +esp32-trueverit-iot-driver-mkii.upload.flags= +esp32-trueverit-iot-driver-mkii.upload.extra_flags= + +esp32-trueverit-iot-driver-mkii.serial.disableDTR=true +esp32-trueverit-iot-driver-mkii.serial.disableRTS=true + +esp32-trueverit-iot-driver-mkii.build.tarch=xtensa +esp32-trueverit-iot-driver-mkii.build.bootloader_addr=0x1000 +esp32-trueverit-iot-driver-mkii.build.target=esp32 +esp32-trueverit-iot-driver-mkii.build.mcu=esp32 +esp32-trueverit-iot-driver-mkii.build.core=esp32 +esp32-trueverit-iot-driver-mkii.build.variant=esp32-trueverit-iot-driver-mkii +esp32-trueverit-iot-driver-mkii.build.board=Trueverit_ESP32_Universal_IoT_Driver_MK_II + +esp32-trueverit-iot-driver-mkii.build.f_cpu=240000000L +esp32-trueverit-iot-driver-mkii.build.flash_mode=dio +esp32-trueverit-iot-driver-mkii.build.flash_size=4MB +esp32-trueverit-iot-driver-mkii.build.boot=dio +esp32-trueverit-iot-driver-mkii.build.partitions=default +esp32-trueverit-iot-driver-mkii.build.defines= + +esp32-trueverit-iot-driver-mkii.menu.FlashFreq.80=80MHz +esp32-trueverit-iot-driver-mkii.menu.FlashFreq.80.build.flash_freq=80m +esp32-trueverit-iot-driver-mkii.menu.FlashFreq.40=40MHz +esp32-trueverit-iot-driver-mkii.menu.FlashFreq.40.build.flash_freq=40m + +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.115200=115200 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.115200.upload.speed=115200 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.256000.windows=256000 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.256000.upload.speed=256000 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400=230400 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400.upload.speed=230400 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.linux=460800 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.macosx=460800 +esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.upload.speed=460800 + +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.none=None +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.none.build.code_debug=0 +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.error=Error +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.error.build.code_debug=1 +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.warn=Warn +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.warn.build.code_debug=2 +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.info=Info +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.info.build.code_debug=3 +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.debug=Debug +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.debug.build.code_debug=4 +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.verbose=Verbose +esp32-trueverit-iot-driver-mkii.menu.DebugLevel.verbose.build.code_debug=5 + +esp32-trueverit-iot-driver-mkii.menu.EraseFlash.none=Disabled +esp32-trueverit-iot-driver-mkii.menu.EraseFlash.none.upload.erase_cmd= +esp32-trueverit-iot-driver-mkii.menu.EraseFlash.all=Enabled +esp32-trueverit-iot-driver-mkii.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +atmegazero_esp32s2.name=ATMegaZero ESP32-S2 +atmegazero_esp32s2.vid.0=0x239A +atmegazero_esp32s2.pid.0=0x800A + +atmegazero_esp32s2.bootloader.tool=esptool_py +atmegazero_esp32s2.bootloader.tool.default=esptool_py + +atmegazero_esp32s2.upload.tool=esptool_py +atmegazero_esp32s2.upload.tool.default=esptool_py +atmegazero_esp32s2.upload.tool.network=esp_ota + +atmegazero_esp32s2.upload.maximum_size=1310720 +atmegazero_esp32s2.upload.maximum_data_size=327680 +atmegazero_esp32s2.upload.flags= +atmegazero_esp32s2.upload.extra_flags= +atmegazero_esp32s2.upload.use_1200bps_touch=true +atmegazero_esp32s2.upload.wait_for_upload_port=true + +atmegazero_esp32s2.serial.disableDTR=false +atmegazero_esp32s2.serial.disableRTS=false + +atmegazero_esp32s2.build.tarch=xtensa +atmegazero_esp32s2.build.bootloader_addr=0x1000 +atmegazero_esp32s2.build.target=esp32s2 +atmegazero_esp32s2.build.mcu=esp32s2 +atmegazero_esp32s2.build.core=esp32 +atmegazero_esp32s2.build.variant=atmegazero_esp32s2 +atmegazero_esp32s2.build.board=atmegazero_esp32s2 + +atmegazero_esp32s2.build.cdc_on_boot=1 +atmegazero_esp32s2.build.msc_on_boot=0 +atmegazero_esp32s2.build.dfu_on_boot=0 +atmegazero_esp32s2.build.serial=0 +atmegazero_esp32s2.build.f_cpu=240000000L +atmegazero_esp32s2.build.flash_size=16MB +atmegazero_esp32s2.build.flash_freq=40m +atmegazero_esp32s2.build.flash_mode=qio +atmegazero_esp32s2.build.boot=qio +atmegazero_esp32s2.build.partitions=default +atmegazero_esp32s2.build.defines= + +atmegazero_esp32s2.menu.CDCOnBoot.cdc=Enabled +atmegazero_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +atmegazero_esp32s2.menu.CDCOnBoot.default=Disabled +atmegazero_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +atmegazero_esp32s2.menu.MSCOnBoot.default=Disabled +atmegazero_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +atmegazero_esp32s2.menu.MSCOnBoot.msc=Enabled +atmegazero_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +atmegazero_esp32s2.menu.DFUOnBoot.default=Disabled +atmegazero_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +atmegazero_esp32s2.menu.DFUOnBoot.dfu=Enabled +atmegazero_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +atmegazero_esp32s2.menu.PSRAM.disabled=Disabled +atmegazero_esp32s2.menu.PSRAM.disabled.build.defines= +atmegazero_esp32s2.menu.PSRAM.enabled=Enabled +atmegazero_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +atmegazero_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FFAT) +atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-16MB-tinyuf2 +atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +atmegazero_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.default.build.partitions=default +atmegazero_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +atmegazero_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +atmegazero_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +atmegazero_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +atmegazero_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +atmegazero_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +atmegazero_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +atmegazero_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +atmegazero_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +atmegazero_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +atmegazero_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +atmegazero_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +atmegazero_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +atmegazero_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +atmegazero_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +atmegazero_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +atmegazero_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +atmegazero_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +atmegazero_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat +atmegazero_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +atmegazero_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +atmegazero_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +atmegazero_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +atmegazero_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +atmegazero_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +atmegazero_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +atmegazero_esp32s2.menu.CPUFreq.40=40MHz +atmegazero_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +atmegazero_esp32s2.menu.CPUFreq.20=20MHz +atmegazero_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +atmegazero_esp32s2.menu.CPUFreq.10=10MHz +atmegazero_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +atmegazero_esp32s2.menu.FlashMode.qio=QIO +atmegazero_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +atmegazero_esp32s2.menu.FlashMode.qio.build.boot=qio +atmegazero_esp32s2.menu.FlashMode.dio=DIO +atmegazero_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +atmegazero_esp32s2.menu.FlashMode.dio.build.boot=dio + +atmegazero_esp32s2.menu.FlashFreq.80=80MHz +atmegazero_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +atmegazero_esp32s2.menu.FlashFreq.40=40MHz +atmegazero_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +atmegazero_esp32s2.menu.FlashSize.4M=4MB (32Mb) +atmegazero_esp32s2.menu.FlashSize.4M.build.flash_size=4MB +atmegazero_esp32s2.menu.FlashSize.8M=8MB (64Mb) +atmegazero_esp32s2.menu.FlashSize.8M.build.flash_size=8MB +atmegazero_esp32s2.menu.FlashSize.2M=2MB (16Mb) +atmegazero_esp32s2.menu.FlashSize.2M.build.flash_size=2MB +atmegazero_esp32s2.menu.FlashSize.16M=16MB (128Mb) +atmegazero_esp32s2.menu.FlashSize.16M.build.flash_size=16MB + +atmegazero_esp32s2.menu.UploadSpeed.921600=921600 +atmegazero_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +atmegazero_esp32s2.menu.UploadSpeed.115200=115200 +atmegazero_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +atmegazero_esp32s2.menu.UploadSpeed.256000.windows=256000 +atmegazero_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +atmegazero_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +atmegazero_esp32s2.menu.UploadSpeed.230400=230400 +atmegazero_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +atmegazero_esp32s2.menu.UploadSpeed.460800.linux=460800 +atmegazero_esp32s2.menu.UploadSpeed.460800.macosx=460800 +atmegazero_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +atmegazero_esp32s2.menu.UploadSpeed.512000.windows=512000 +atmegazero_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +atmegazero_esp32s2.menu.DebugLevel.none=None +atmegazero_esp32s2.menu.DebugLevel.none.build.code_debug=0 +atmegazero_esp32s2.menu.DebugLevel.error=Error +atmegazero_esp32s2.menu.DebugLevel.error.build.code_debug=1 +atmegazero_esp32s2.menu.DebugLevel.warn=Warn +atmegazero_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +atmegazero_esp32s2.menu.DebugLevel.info=Info +atmegazero_esp32s2.menu.DebugLevel.info.build.code_debug=3 +atmegazero_esp32s2.menu.DebugLevel.debug=Debug +atmegazero_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +atmegazero_esp32s2.menu.DebugLevel.verbose=Verbose +atmegazero_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +atmegazero_esp32s2.menu.EraseFlash.none=Disabled +atmegazero_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +atmegazero_esp32s2.menu.EraseFlash.all=Enabled +atmegazero_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +franzininho_wifi_esp32s2.name=Franzininho WiFi +franzininho_wifi_esp32s2.vid.0=0x303A +franzininho_wifi_esp32s2.pid.0=0x80A9 + +franzininho_wifi_esp32s2.bootloader.tool=esptool_py +franzininho_wifi_esp32s2.bootloader.tool.default=esptool_py + +franzininho_wifi_esp32s2.upload.tool=esptool_py +franzininho_wifi_esp32s2.upload.tool.default=esptool_py +franzininho_wifi_esp32s2.upload.tool.network=esp_ota + +franzininho_wifi_esp32s2.upload.maximum_size=1310720 +franzininho_wifi_esp32s2.upload.maximum_data_size=327680 +franzininho_wifi_esp32s2.upload.flags= +franzininho_wifi_esp32s2.upload.extra_flags= +franzininho_wifi_esp32s2.upload.use_1200bps_touch=true +franzininho_wifi_esp32s2.upload.wait_for_upload_port=true +franzininho_wifi_esp32s2.upload.speed=921600 + +franzininho_wifi_esp32s2.serial.disableDTR=false +franzininho_wifi_esp32s2.serial.disableRTS=false + +franzininho_wifi_esp32s2.build.tarch=xtensa +franzininho_wifi_esp32s2.build.bootloader_addr=0x1000 +franzininho_wifi_esp32s2.build.target=esp32s2 +franzininho_wifi_esp32s2.build.mcu=esp32s2 +franzininho_wifi_esp32s2.build.core=esp32 +franzininho_wifi_esp32s2.build.variant=franzininho_wifi_esp32s2 +franzininho_wifi_esp32s2.build.board=FRANZININHO_WIFI + +franzininho_wifi_esp32s2.build.cdc_on_boot=1 +franzininho_wifi_esp32s2.build.msc_on_boot=0 +franzininho_wifi_esp32s2.build.dfu_on_boot=0 +franzininho_wifi_esp32s2.build.f_cpu=240000000L +franzininho_wifi_esp32s2.build.flash_size=4MB +franzininho_wifi_esp32s2.build.flash_freq=80m +franzininho_wifi_esp32s2.build.flash_mode=dio +franzininho_wifi_esp32s2.build.boot=qio +franzininho_wifi_esp32s2.build.partitions=default +franzininho_wifi_esp32s2.build.defines= + +franzininho_wifi_esp32s2.menu.PSRAM.disabled=Disabled +franzininho_wifi_esp32s2.menu.PSRAM.disabled.build.defines= +franzininho_wifi_esp32s2.menu.PSRAM.enabled=Enabled +franzininho_wifi_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +franzininho_wifi_esp32s2.menu.FlashSize.4M=4MB (32Mb) +franzininho_wifi_esp32s2.menu.FlashSize.4M.build.flash_size=4MB +franzininho_wifi_esp32s2.menu.FlashSize.8M=8MB (64Mb) +franzininho_wifi_esp32s2.menu.FlashSize.8M.build.flash_size=8MB +franzininho_wifi_esp32s2.menu.FlashSize.16M=16MB (128Mb) +franzininho_wifi_esp32s2.menu.FlashSize.16M.build.flash_size=16MB + +franzininho_wifi_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.default.build.partitions=default +franzininho_wifi_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +franzininho_wifi_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat +franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +franzininho_wifi_esp32s2.menu.DebugLevel.none=None +franzininho_wifi_esp32s2.menu.DebugLevel.none.build.code_debug=0 +franzininho_wifi_esp32s2.menu.DebugLevel.error=Error +franzininho_wifi_esp32s2.menu.DebugLevel.error.build.code_debug=1 +franzininho_wifi_esp32s2.menu.DebugLevel.warn=Warn +franzininho_wifi_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +franzininho_wifi_esp32s2.menu.DebugLevel.info=Info +franzininho_wifi_esp32s2.menu.DebugLevel.info.build.code_debug=3 +franzininho_wifi_esp32s2.menu.DebugLevel.debug=Debug +franzininho_wifi_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +franzininho_wifi_esp32s2.menu.DebugLevel.verbose=Verbose +franzininho_wifi_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +franzininho_wifi_esp32s2.menu.EraseFlash.none=Disabled +franzininho_wifi_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +franzininho_wifi_esp32s2.menu.EraseFlash.all=Enabled +franzininho_wifi_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +franzininho_wifi_msc_esp32s2.name=Franzininho WiFi MSC +franzininho_wifi_msc_esp32s2.vid.0=0x303A +franzininho_wifi_msc_esp32s2.pid.0=0x80A9 + +franzininho_wifi_msc_esp32s2.bootloader.tool=esptool_py +franzininho_wifi_msc_esp32s2.bootloader.tool.default=esptool_py + +franzininho_wifi_msc_esp32s2.upload.tool=esptool_py +franzininho_wifi_msc_esp32s2.upload.tool.default=esptool_py +franzininho_wifi_msc_esp32s2.upload.tool.network=esp_ota + +franzininho_wifi_msc_esp32s2.upload.maximum_size=1310720 +franzininho_wifi_msc_esp32s2.upload.maximum_data_size=327680 +franzininho_wifi_msc_esp32s2.upload.flags= +franzininho_wifi_msc_esp32s2.upload.extra_flags= +franzininho_wifi_msc_esp32s2.upload.use_1200bps_touch=true +franzininho_wifi_msc_esp32s2.upload.wait_for_upload_port=true +franzininho_wifi_msc_esp32s2.upload.speed=921600 + +franzininho_wifi_msc_esp32s2.serial.disableDTR=false +franzininho_wifi_msc_esp32s2.serial.disableRTS=false + +franzininho_wifi_msc_esp32s2.build.tarch=xtensa +franzininho_wifi_msc_esp32s2.build.bootloader_addr=0x1000 +franzininho_wifi_msc_esp32s2.build.target=esp32s2 +franzininho_wifi_msc_esp32s2.build.mcu=esp32s2 +franzininho_wifi_msc_esp32s2.build.core=esp32 +franzininho_wifi_msc_esp32s2.build.variant=franzininho_wifi_msc_esp32s2 +franzininho_wifi_msc_esp32s2.build.board=FRANZININHO_WIFI_MSC + +franzininho_wifi_msc_esp32s2.build.cdc_on_boot=1 +franzininho_wifi_msc_esp32s2.build.msc_on_boot=1 +franzininho_wifi_msc_esp32s2.build.dfu_on_boot=1 +franzininho_wifi_msc_esp32s2.build.f_cpu=240000000L +franzininho_wifi_msc_esp32s2.build.flash_size=4MB +franzininho_wifi_msc_esp32s2.build.flash_freq=80m +franzininho_wifi_msc_esp32s2.build.flash_mode=dio +franzininho_wifi_msc_esp32s2.build.boot=qio +franzininho_wifi_msc_esp32s2.build.partitions=default +franzininho_wifi_msc_esp32s2.build.defines= + +franzininho_wifi_msc_esp32s2.menu.PSRAM.disabled=Disabled +franzininho_wifi_msc_esp32s2.menu.PSRAM.disabled.build.defines= +franzininho_wifi_msc_esp32s2.menu.PSRAM.enabled=Enabled +franzininho_wifi_msc_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +franzininho_wifi_msc_esp32s2.menu.FlashSize.4M=4MB (32Mb) +franzininho_wifi_msc_esp32s2.menu.FlashSize.4M.build.flash_size=4MB +franzininho_wifi_msc_esp32s2.menu.FlashSize.8M=8MB (64Mb) +franzininho_wifi_msc_esp32s2.menu.FlashSize.8M.build.flash_size=8MB +franzininho_wifi_msc_esp32s2.menu.FlashSize.16M=16MB (128Mb) +franzininho_wifi_msc_esp32s2.menu.FlashSize.16M.build.flash_size=16MB + +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default.build.partitions=default +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +franzininho_wifi_msc_esp32s2.menu.DebugLevel.none=None +franzininho_wifi_msc_esp32s2.menu.DebugLevel.none.build.code_debug=0 +franzininho_wifi_msc_esp32s2.menu.DebugLevel.error=Error +franzininho_wifi_msc_esp32s2.menu.DebugLevel.error.build.code_debug=1 +franzininho_wifi_msc_esp32s2.menu.DebugLevel.warn=Warn +franzininho_wifi_msc_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +franzininho_wifi_msc_esp32s2.menu.DebugLevel.info=Info +franzininho_wifi_msc_esp32s2.menu.DebugLevel.info.build.code_debug=3 +franzininho_wifi_msc_esp32s2.menu.DebugLevel.debug=Debug +franzininho_wifi_msc_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +franzininho_wifi_msc_esp32s2.menu.DebugLevel.verbose=Verbose +franzininho_wifi_msc_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +franzininho_wifi_msc_esp32s2.menu.EraseFlash.none=Disabled +franzininho_wifi_msc_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +franzininho_wifi_msc_esp32s2.menu.EraseFlash.all=Enabled +franzininho_wifi_msc_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +tamc_termod_s3.name=TAMC Termod S3 + +tamc_termod_s3.bootloader.tool=esptool_py +tamc_termod_s3.bootloader.tool.default=esptool_py + +tamc_termod_s3.upload.tool=esptool_py +tamc_termod_s3.upload.tool.default=esptool_py +tamc_termod_s3.upload.tool.network=esp_ota + +tamc_termod_s3.upload.maximum_size=1310720 +tamc_termod_s3.upload.maximum_data_size=327680 +tamc_termod_s3.upload.flags= +tamc_termod_s3.upload.extra_flags= +tamc_termod_s3.upload.use_1200bps_touch=false +tamc_termod_s3.upload.wait_for_upload_port=false + +tamc_termod_s3.serial.disableDTR=false +tamc_termod_s3.serial.disableRTS=false + +tamc_termod_s3.build.tarch=xtensa +tamc_termod_s3.build.bootloader_addr=0x0 +tamc_termod_s3.build.target=esp32s3 +tamc_termod_s3.build.mcu=esp32s3 +tamc_termod_s3.build.core=esp32 +tamc_termod_s3.build.variant=tamc_termod_s3 +tamc_termod_s3.build.board=TAMC_TERMOD_S3 + +tamc_termod_s3.build.usb_mode=1 +tamc_termod_s3.build.cdc_on_boot=1 +tamc_termod_s3.build.msc_on_boot=0 +tamc_termod_s3.build.dfu_on_boot=0 +tamc_termod_s3.build.f_cpu=240000000L +tamc_termod_s3.build.flash_size=8MB +tamc_termod_s3.build.flash_freq=80m +tamc_termod_s3.build.flash_mode=dio +tamc_termod_s3.build.boot=qio +tamc_termod_s3.build.boot_freq=80m +tamc_termod_s3.build.partitions=default +tamc_termod_s3.build.defines= +tamc_termod_s3.build.loop_core= +tamc_termod_s3.build.event_core= +tamc_termod_s3.build.psram_type=qspi +tamc_termod_s3.build.memory_type={build.boot}_{build.psram_type} + +tamc_termod_s3.menu.PSRAM.enabled=QSPI PSRAM +tamc_termod_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +tamc_termod_s3.menu.PSRAM.enabled.build.psram_type=qspi +tamc_termod_s3.menu.PSRAM.disabled=Disabled +tamc_termod_s3.menu.PSRAM.disabled.build.defines= +tamc_termod_s3.menu.PSRAM.disabled.build.psram_type=qspi +tamc_termod_s3.menu.PSRAM.opi=OPI PSRAM +tamc_termod_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +tamc_termod_s3.menu.PSRAM.opi.build.psram_type=opi + +tamc_termod_s3.menu.FlashMode.qio=QIO 80MHz +tamc_termod_s3.menu.FlashMode.qio.build.flash_mode=dio +tamc_termod_s3.menu.FlashMode.qio.build.boot=qio +tamc_termod_s3.menu.FlashMode.qio.build.boot_freq=80m +tamc_termod_s3.menu.FlashMode.qio.build.flash_freq=80m +tamc_termod_s3.menu.FlashMode.qio120=QIO 120MHz +tamc_termod_s3.menu.FlashMode.qio120.build.flash_mode=dio +tamc_termod_s3.menu.FlashMode.qio120.build.boot=qio +tamc_termod_s3.menu.FlashMode.qio120.build.boot_freq=120m +tamc_termod_s3.menu.FlashMode.qio120.build.flash_freq=80m +tamc_termod_s3.menu.FlashMode.dio=DIO 80MHz +tamc_termod_s3.menu.FlashMode.dio.build.flash_mode=dio +tamc_termod_s3.menu.FlashMode.dio.build.boot=dio +tamc_termod_s3.menu.FlashMode.dio.build.boot_freq=80m +tamc_termod_s3.menu.FlashMode.dio.build.flash_freq=80m +tamc_termod_s3.menu.FlashMode.opi=OPI 80MHz +tamc_termod_s3.menu.FlashMode.opi.build.flash_mode=dout +tamc_termod_s3.menu.FlashMode.opi.build.boot=opi +tamc_termod_s3.menu.FlashMode.opi.build.boot_freq=80m +tamc_termod_s3.menu.FlashMode.opi.build.flash_freq=80m + +tamc_termod_s3.menu.FlashSize.4M=4MB (32Mb) +tamc_termod_s3.menu.FlashSize.4M.build.flash_size=4MB +tamc_termod_s3.menu.FlashSize.8M=8MB (64Mb) +tamc_termod_s3.menu.FlashSize.8M.build.flash_size=8MB +tamc_termod_s3.menu.FlashSize.16M=16MB (128Mb) +tamc_termod_s3.menu.FlashSize.16M.build.flash_size=16MB + +tamc_termod_s3.menu.LoopCore.1=Core 1 +tamc_termod_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +tamc_termod_s3.menu.LoopCore.0=Core 0 +tamc_termod_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +tamc_termod_s3.menu.EventsCore.1=Core 1 +tamc_termod_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +tamc_termod_s3.menu.EventsCore.0=Core 0 +tamc_termod_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +tamc_termod_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +tamc_termod_s3.menu.USBMode.hwcdc.build.usb_mode=1 +tamc_termod_s3.menu.USBMode.default=USB-OTG (TinyUSB) +tamc_termod_s3.menu.USBMode.default.build.usb_mode=0 + +tamc_termod_s3.menu.CDCOnBoot.cdc=Enabled +tamc_termod_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +tamc_termod_s3.menu.CDCOnBoot.default=Disabled +tamc_termod_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +tamc_termod_s3.menu.MSCOnBoot.default=Disabled +tamc_termod_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +tamc_termod_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +tamc_termod_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +tamc_termod_s3.menu.DFUOnBoot.default=Disabled +tamc_termod_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +tamc_termod_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +tamc_termod_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +tamc_termod_s3.menu.UploadMode.default=UART0 / Hardware CDC +tamc_termod_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +tamc_termod_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +tamc_termod_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +tamc_termod_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +tamc_termod_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +tamc_termod_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.default.build.partitions=default +tamc_termod_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +tamc_termod_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +tamc_termod_s3.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT) +tamc_termod_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +tamc_termod_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +tamc_termod_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.minimal.build.partitions=minimal +tamc_termod_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +tamc_termod_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +tamc_termod_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +tamc_termod_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +tamc_termod_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +tamc_termod_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +tamc_termod_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +tamc_termod_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +tamc_termod_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +tamc_termod_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +tamc_termod_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +tamc_termod_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +tamc_termod_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +tamc_termod_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +tamc_termod_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +tamc_termod_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +tamc_termod_s3.menu.PartitionScheme.fatflash.build.partitions=ffat +tamc_termod_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +tamc_termod_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +tamc_termod_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +tamc_termod_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +tamc_termod_s3.menu.CPUFreq.240=240MHz (WiFi) +tamc_termod_s3.menu.CPUFreq.240.build.f_cpu=240000000L +tamc_termod_s3.menu.CPUFreq.160=160MHz (WiFi) +tamc_termod_s3.menu.CPUFreq.160.build.f_cpu=160000000L +tamc_termod_s3.menu.CPUFreq.80=80MHz (WiFi) +tamc_termod_s3.menu.CPUFreq.80.build.f_cpu=80000000L +tamc_termod_s3.menu.CPUFreq.40=40MHz +tamc_termod_s3.menu.CPUFreq.40.build.f_cpu=40000000L +tamc_termod_s3.menu.CPUFreq.20=20MHz +tamc_termod_s3.menu.CPUFreq.20.build.f_cpu=20000000L +tamc_termod_s3.menu.CPUFreq.10=10MHz +tamc_termod_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +tamc_termod_s3.menu.UploadSpeed.921600=921600 +tamc_termod_s3.menu.UploadSpeed.921600.upload.speed=921600 +tamc_termod_s3.menu.UploadSpeed.115200=115200 +tamc_termod_s3.menu.UploadSpeed.115200.upload.speed=115200 +tamc_termod_s3.menu.UploadSpeed.256000.windows=256000 +tamc_termod_s3.menu.UploadSpeed.256000.upload.speed=256000 +tamc_termod_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +tamc_termod_s3.menu.UploadSpeed.230400=230400 +tamc_termod_s3.menu.UploadSpeed.230400.upload.speed=230400 +tamc_termod_s3.menu.UploadSpeed.460800.linux=460800 +tamc_termod_s3.menu.UploadSpeed.460800.macosx=460800 +tamc_termod_s3.menu.UploadSpeed.460800.upload.speed=460800 +tamc_termod_s3.menu.UploadSpeed.512000.windows=512000 +tamc_termod_s3.menu.UploadSpeed.512000.upload.speed=512000 + +tamc_termod_s3.menu.DebugLevel.none=None +tamc_termod_s3.menu.DebugLevel.none.build.code_debug=0 +tamc_termod_s3.menu.DebugLevel.error=Error +tamc_termod_s3.menu.DebugLevel.error.build.code_debug=1 +tamc_termod_s3.menu.DebugLevel.warn=Warn +tamc_termod_s3.menu.DebugLevel.warn.build.code_debug=2 +tamc_termod_s3.menu.DebugLevel.info=Info +tamc_termod_s3.menu.DebugLevel.info.build.code_debug=3 +tamc_termod_s3.menu.DebugLevel.debug=Debug +tamc_termod_s3.menu.DebugLevel.debug.build.code_debug=4 +tamc_termod_s3.menu.DebugLevel.verbose=Verbose +tamc_termod_s3.menu.DebugLevel.verbose.build.code_debug=5 + +tamc_termod_s3.menu.EraseFlash.none=Disabled +tamc_termod_s3.menu.EraseFlash.none.upload.erase_cmd= +tamc_termod_s3.menu.EraseFlash.all=Enabled +tamc_termod_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +dpu_esp32.name=DPU ESP32 + +dpu_esp32.bootloader.tool=esptool_py +dpu_esp32.bootloader.tool.default=esptool_py + +dpu_esp32.upload.tool=esptool_py +dpu_esp32.upload.tool.default=esptool_py +dpu_esp32.upload.tool.network=esp_ota + +dpu_esp32.upload.maximum_size=3342336 +dpu_esp32.upload.maximum_data_size=327680 +dpu_esp32.upload.flags= +dpu_esp32.upload.extra_flags= + +dpu_esp32.serial.disableDTR=true +dpu_esp32.serial.disableRTS=true + +dpu_esp32.build.tarch=xtensa +dpu_esp32.build.bootloader_addr=0x1000 +dpu_esp32.build.target=esp32 +dpu_esp32.build.mcu=esp32 +dpu_esp32.build.core=esp32 +dpu_esp32.build.variant=dpu_esp32 +dpu_esp32.build.board=DPU_ESP32 + +dpu_esp32.build.f_cpu=240000000L +dpu_esp32.build.flash_size=8MB +dpu_esp32.build.flash_freq=40m +dpu_esp32.build.flash_mode=dio +dpu_esp32.build.boot=dio +dpu_esp32.build.partitions=default_8MB +dpu_esp32.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +dpu_esp32.build.extra_libs= + +dpu_esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +dpu_esp32.menu.PartitionScheme.default.build.partitions=default +dpu_esp32.menu.PartitionScheme.default.upload.maximum_size=1310720 +dpu_esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +dpu_esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +dpu_esp32.menu.PartitionScheme.defaultffat.upload.maximum_size=1310720 +dpu_esp32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +dpu_esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +dpu_esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +dpu_esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +dpu_esp32.menu.PartitionScheme.minimal.build.partitions=minimal +dpu_esp32.menu.PartitionScheme.minimal.upload.maximum_size=1310720 +dpu_esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +dpu_esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +dpu_esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +dpu_esp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +dpu_esp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +dpu_esp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +dpu_esp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +dpu_esp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +dpu_esp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +dpu_esp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +dpu_esp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +dpu_esp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +dpu_esp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +dpu_esp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +dpu_esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +dpu_esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +dpu_esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +dpu_esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +dpu_esp32.menu.FlashMode.qio=QIO +dpu_esp32.menu.FlashMode.qio.build.flash_mode=dio +dpu_esp32.menu.FlashMode.qio.build.boot=qio +dpu_esp32.menu.FlashMode.dio=DIO +dpu_esp32.menu.FlashMode.dio.build.flash_mode=dio +dpu_esp32.menu.FlashMode.dio.build.boot=dio + +dpu_esp32.menu.FlashFreq.80=80MHz +dpu_esp32.menu.FlashFreq.80.build.flash_freq=80m +dpu_esp32.menu.FlashFreq.40=40MHz +dpu_esp32.menu.FlashFreq.40.build.flash_freq=40m + +dpu_esp32.menu.UploadSpeed.921600=921600 +dpu_esp32.menu.UploadSpeed.921600.upload.speed=921600 +dpu_esp32.menu.UploadSpeed.115200=115200 +dpu_esp32.menu.UploadSpeed.115200.upload.speed=115200 +dpu_esp32.menu.UploadSpeed.256000.windows=256000 +dpu_esp32.menu.UploadSpeed.256000.upload.speed=256000 +dpu_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +dpu_esp32.menu.UploadSpeed.230400=230400 +dpu_esp32.menu.UploadSpeed.230400.upload.speed=230400 +dpu_esp32.menu.UploadSpeed.460800.linux=460800 +dpu_esp32.menu.UploadSpeed.460800.macosx=460800 +dpu_esp32.menu.UploadSpeed.460800.upload.speed=460800 +dpu_esp32.menu.UploadSpeed.512000.windows=512000 +dpu_esp32.menu.UploadSpeed.512000.upload.speed=512000 + +dpu_esp32.menu.DebugLevel.none=None +dpu_esp32.menu.DebugLevel.none.build.code_debug=0 +dpu_esp32.menu.DebugLevel.error=Error +dpu_esp32.menu.DebugLevel.error.build.code_debug=1 +dpu_esp32.menu.DebugLevel.warn=Warn +dpu_esp32.menu.DebugLevel.warn.build.code_debug=2 +dpu_esp32.menu.DebugLevel.info=Info +dpu_esp32.menu.DebugLevel.info.build.code_debug=3 +dpu_esp32.menu.DebugLevel.debug=Debug +dpu_esp32.menu.DebugLevel.debug.build.code_debug=4 +dpu_esp32.menu.DebugLevel.verbose=Verbose +dpu_esp32.menu.DebugLevel.verbose.build.code_debug=5 + +dpu_esp32.menu.EraseFlash.none=Disabled +dpu_esp32.menu.EraseFlash.none.upload.erase_cmd= +dpu_esp32.menu.EraseFlash.all=Enabled +dpu_esp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +sonoff_dualr3.name=Sonoff DUALR3 + +sonoff_dualr3.bootloader.tool=esptool_py +sonoff_dualr3.bootloader.tool.default=esptool_py + +sonoff_dualr3.upload.tool=esptool_py +sonoff_dualr3.upload.tool.default=esptool_py +sonoff_dualr3.upload.tool.network=esp_ota + +sonoff_dualr3.upload.maximum_size=1310720 +sonoff_dualr3.upload.maximum_data_size=327680 +sonoff_dualr3.upload.flags= +sonoff_dualr3.upload.extra_flags= + +sonoff_dualr3.serial.disableDTR=true +sonoff_dualr3.serial.disableRTS=true + +sonoff_dualr3.build.tarch=xtensa +sonoff_dualr3.build.bootloader_addr=0x1000 +sonoff_dualr3.build.target=esp32 +sonoff_dualr3.build.mcu=esp32 +sonoff_dualr3.build.core=esp32 +sonoff_dualr3.build.variant=esp32 +sonoff_dualr3.build.board=SONOFF_DUALR3 + +sonoff_dualr3.build.f_cpu=240000000L +sonoff_dualr3.build.flash_size=4MB +sonoff_dualr3.build.flash_freq=40m +sonoff_dualr3.build.flash_mode=dio +sonoff_dualr3.build.boot=dio +sonoff_dualr3.build.partitions=rainmaker +sonoff_dualr3.build.defines= +sonoff_dualr3.build.loop_core= +sonoff_dualr3.build.event_core= + +sonoff_dualr3.menu.PartitionScheme.rainmaker=RainMaker 4MB +sonoff_dualr3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +sonoff_dualr3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +sonoff_dualr3.menu.CPUFreq.240=240MHz (WiFi/BT) +sonoff_dualr3.menu.CPUFreq.240.build.f_cpu=240000000L +sonoff_dualr3.menu.CPUFreq.160=160MHz (WiFi/BT) +sonoff_dualr3.menu.CPUFreq.160.build.f_cpu=160000000L +sonoff_dualr3.menu.CPUFreq.80=80MHz (WiFi/BT) +sonoff_dualr3.menu.CPUFreq.80.build.f_cpu=80000000L +sonoff_dualr3.menu.CPUFreq.40=40MHz (40MHz XTAL) +sonoff_dualr3.menu.CPUFreq.40.build.f_cpu=40000000L +sonoff_dualr3.menu.CPUFreq.26=26MHz (26MHz XTAL) +sonoff_dualr3.menu.CPUFreq.26.build.f_cpu=26000000L +sonoff_dualr3.menu.CPUFreq.20=20MHz (40MHz XTAL) +sonoff_dualr3.menu.CPUFreq.20.build.f_cpu=20000000L +sonoff_dualr3.menu.CPUFreq.13=13MHz (26MHz XTAL) +sonoff_dualr3.menu.CPUFreq.13.build.f_cpu=13000000L +sonoff_dualr3.menu.CPUFreq.10=10MHz (40MHz XTAL) +sonoff_dualr3.menu.CPUFreq.10.build.f_cpu=10000000L + +sonoff_dualr3.menu.FlashMode.qio=QIO +sonoff_dualr3.menu.FlashMode.qio.build.flash_mode=dio +sonoff_dualr3.menu.FlashMode.qio.build.boot=qio +sonoff_dualr3.menu.FlashMode.dio=DIO +sonoff_dualr3.menu.FlashMode.dio.build.flash_mode=dio +sonoff_dualr3.menu.FlashMode.dio.build.boot=dio + +sonoff_dualr3.menu.FlashFreq.80=80MHz +sonoff_dualr3.menu.FlashFreq.80.build.flash_freq=80m +sonoff_dualr3.menu.FlashFreq.40=40MHz +sonoff_dualr3.menu.FlashFreq.40.build.flash_freq=40m + +sonoff_dualr3.menu.FlashSize.4M=4MB (32Mb) +sonoff_dualr3.menu.FlashSize.4M.build.flash_size=4MB + +sonoff_dualr3.menu.UploadSpeed.921600=921600 +sonoff_dualr3.menu.UploadSpeed.921600.upload.speed=921600 +sonoff_dualr3.menu.UploadSpeed.115200=115200 +sonoff_dualr3.menu.UploadSpeed.115200.upload.speed=115200 +sonoff_dualr3.menu.UploadSpeed.256000.windows=256000 +sonoff_dualr3.menu.UploadSpeed.256000.upload.speed=256000 +sonoff_dualr3.menu.UploadSpeed.230400.windows.upload.speed=256000 +sonoff_dualr3.menu.UploadSpeed.230400=230400 +sonoff_dualr3.menu.UploadSpeed.230400.upload.speed=230400 +sonoff_dualr3.menu.UploadSpeed.460800.linux=460800 +sonoff_dualr3.menu.UploadSpeed.460800.macosx=460800 +sonoff_dualr3.menu.UploadSpeed.460800.upload.speed=460800 +sonoff_dualr3.menu.UploadSpeed.512000.windows=512000 +sonoff_dualr3.menu.UploadSpeed.512000.upload.speed=512000 + +sonoff_dualr3.menu.DebugLevel.none=None +sonoff_dualr3.menu.DebugLevel.none.build.code_debug=0 +sonoff_dualr3.menu.DebugLevel.error=Error +sonoff_dualr3.menu.DebugLevel.error.build.code_debug=1 +sonoff_dualr3.menu.DebugLevel.warn=Warn +sonoff_dualr3.menu.DebugLevel.warn.build.code_debug=2 +sonoff_dualr3.menu.DebugLevel.info=Info +sonoff_dualr3.menu.DebugLevel.info.build.code_debug=3 +sonoff_dualr3.menu.DebugLevel.debug=Debug +sonoff_dualr3.menu.DebugLevel.debug.build.code_debug=4 +sonoff_dualr3.menu.DebugLevel.verbose=Verbose +sonoff_dualr3.menu.DebugLevel.verbose.build.code_debug=5 + +sonoff_dualr3.menu.EraseFlash.none=Disabled +sonoff_dualr3.menu.EraseFlash.none.upload.erase_cmd= +sonoff_dualr3.menu.EraseFlash.all=Enabled +sonoff_dualr3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +lionbit.name=Lion:Bit Dev Board + +lionbit.bootloader.tool=esptool_py +lionbit.bootloader.tool.default=esptool_py + +lionbit.upload.tool=esptool_py +lionbit.upload.tool.default=esptool_py +lionbit.upload.tool.network=esp_ota + +lionbit.upload.maximum_size=1310720 +lionbit.upload.maximum_data_size=327680 +lionbit.upload.flags= +lionbit.upload.extra_flags= + +lionbit.serial.disableDTR=true +lionbit.serial.disableRTS=true + +lionbit.build.tarch=xtensa +lionbit.build.bootloader_addr=0x1000 +lionbit.build.target=esp32 +lionbit.build.mcu=esp32 +lionbit.build.core=esp32 +lionbit.build.variant=lionbit +lionbit.build.board=Lion:Bit_Dev_Board + +lionbit.build.f_cpu=240000000L +lionbit.build.flash_size=4MB +lionbit.build.flash_freq=80m +lionbit.build.flash_mode=dio +lionbit.build.boot=dio +lionbit.build.partitions=default +lionbit.build.defines= +lionbit.build.loop_core= +lionbit.build.event_core= + + +lionbit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lionbit.menu.PartitionScheme.default.build.partitions=default +lionbit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lionbit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lionbit.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +lionbit.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +lionbit.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +lionbit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +lionbit.menu.PartitionScheme.minimal.build.partitions=minimal +lionbit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lionbit.menu.PartitionScheme.no_ota.build.partitions=no_ota +lionbit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lionbit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lionbit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lionbit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lionbit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lionbit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lionbit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lionbit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lionbit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lionbit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lionbit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lionbit.menu.PartitionScheme.huge_app.build.partitions=huge_app +lionbit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lionbit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lionbit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lionbit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +lionbit.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +lionbit.menu.PartitionScheme.fatflash.build.partitions=ffat +lionbit.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +lionbit.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lionbit.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lionbit.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lionbit.menu.PartitionScheme.rainmaker=RainMaker 4MB +lionbit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lionbit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lionbit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lionbit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lionbit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +lionbit.menu.CPUFreq.240=240MHz (WiFi/BT) +lionbit.menu.CPUFreq.240.build.f_cpu=240000000L +lionbit.menu.CPUFreq.160=160MHz (WiFi/BT) +lionbit.menu.CPUFreq.160.build.f_cpu=160000000L +lionbit.menu.CPUFreq.80=80MHz (WiFi/BT) +lionbit.menu.CPUFreq.80.build.f_cpu=80000000L +lionbit.menu.CPUFreq.40=40MHz (40MHz XTAL) +lionbit.menu.CPUFreq.40.build.f_cpu=40000000L +lionbit.menu.CPUFreq.26=26MHz (26MHz XTAL) +lionbit.menu.CPUFreq.26.build.f_cpu=26000000L +lionbit.menu.CPUFreq.20=20MHz (40MHz XTAL) +lionbit.menu.CPUFreq.20.build.f_cpu=20000000L +lionbit.menu.CPUFreq.13=13MHz (26MHz XTAL) +lionbit.menu.CPUFreq.13.build.f_cpu=13000000L +lionbit.menu.CPUFreq.10=10MHz (40MHz XTAL) +lionbit.menu.CPUFreq.10.build.f_cpu=10000000L + + +lionbit.menu.FlashMode.dio=DIO +lionbit.menu.FlashMode.dio.build.flash_mode=dio +lionbit.menu.FlashMode.dio.build.boot=dio +lionbit.menu.FlashMode.qio=QIO +lionbit.menu.FlashMode.qio.build.flash_mode=dio +lionbit.menu.FlashMode.qio.build.boot=qio + +lionbit.menu.FlashFreq.80=80MHz +lionbit.menu.FlashFreq.80.build.flash_freq=80m +lionbit.menu.FlashFreq.40=40MHz +lionbit.menu.FlashFreq.40.build.flash_freq=40m + +lionbit.menu.FlashSize.4M=4MB (32Mb) +lionbit.menu.FlashSize.4M.build.flash_size=4MB + + + +lionbit.menu.UploadSpeed.115200=115200 +lionbit.menu.UploadSpeed.115200.upload.speed=115200 +lionbit.menu.UploadSpeed.256000.windows=256000 +lionbit.menu.UploadSpeed.256000.upload.speed=256000 +lionbit.menu.UploadSpeed.230400.windows.upload.speed=256000 +lionbit.menu.UploadSpeed.230400=230400 +lionbit.menu.UploadSpeed.230400.upload.speed=230400 +lionbit.menu.UploadSpeed.460800.linux=460800 +lionbit.menu.UploadSpeed.460800.macosx=460800 +lionbit.menu.UploadSpeed.460800.upload.speed=460800 + + +lionbit.menu.LoopCore.1=Core 1 +lionbit.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lionbit.menu.LoopCore.0=Core 0 +lionbit.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lionbit.menu.EventsCore.1=Core 1 +lionbit.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lionbit.menu.EventsCore.0=Core 0 +lionbit.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lionbit.menu.DebugLevel.none=None +lionbit.menu.DebugLevel.none.build.code_debug=0 +lionbit.menu.DebugLevel.error=Error +lionbit.menu.DebugLevel.error.build.code_debug=1 +lionbit.menu.DebugLevel.warn=Warn +lionbit.menu.DebugLevel.warn.build.code_debug=2 +lionbit.menu.DebugLevel.info=Info +lionbit.menu.DebugLevel.info.build.code_debug=3 +lionbit.menu.DebugLevel.debug=Debug +lionbit.menu.DebugLevel.debug.build.code_debug=4 +lionbit.menu.DebugLevel.verbose=Verbose +lionbit.menu.DebugLevel.verbose.build.code_debug=5 + +lionbit.menu.EraseFlash.none=Disabled +lionbit.menu.EraseFlash.none.upload.erase_cmd= +lionbit.menu.EraseFlash.all=Enabled +lionbit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +watchy.name=Watchy + +watchy.bootloader.tool=esptool_py +watchy.bootloader.tool.default=esptool_py + +watchy.upload.tool=esptool_py +watchy.upload.tool.default=esptool_py +watchy.upload.tool.network=esp_ota + +watchy.upload.maximum_size=1310720 +watchy.upload.maximum_data_size=327680 +watchy.upload.flags= +watchy.upload.extra_flags= + +watchy.serial.disableDTR=true +watchy.serial.disableRTS=true + +watchy.build.tarch=xtensa +watchy.build.bootloader_addr=0x1000 +watchy.build.target=esp32 +watchy.build.mcu=esp32 +watchy.build.core=esp32 +watchy.build.variant=watchy +watchy.build.board=WATCHY + +watchy.build.f_cpu=240000000L +watchy.build.flash_size=4MB +watchy.build.flash_freq=80m +watchy.build.flash_mode=dio +watchy.build.boot=qio +watchy.build.partitions=min_spiffs +watchy.build.defines= + +watchy.menu.Revision.v10=Watchy v1.0 +watchy.menu.Revision.v10.build.board=WATCHY_V10 +watchy.menu.Revision.v15=Watchy v1.5 +watchy.menu.Revision.v15.build.board=WATCHY_V15 +watchy.menu.Revision.v20=Watchy v2.0 +watchy.menu.Revision.v20.build.board=WATCHY_V20 + +watchy.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +watchy.menu.PartitionScheme.huge_app.build.partitions=huge_app +watchy.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +watchy.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +watchy.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +watchy.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +watchy.menu.UploadSpeed.921600=921600 +watchy.menu.UploadSpeed.921600.upload.speed=921600 +watchy.menu.UploadSpeed.115200=115200 +watchy.menu.UploadSpeed.115200.upload.speed=115200 +watchy.menu.UploadSpeed.256000.windows=256000 +watchy.menu.UploadSpeed.256000.upload.speed=256000 +watchy.menu.UploadSpeed.230400.windows.upload.speed=256000 +watchy.menu.UploadSpeed.230400=230400 +watchy.menu.UploadSpeed.230400.upload.speed=230400 +watchy.menu.UploadSpeed.460800.linux=460800 +watchy.menu.UploadSpeed.460800.macosx=460800 +watchy.menu.UploadSpeed.460800.upload.speed=460800 +watchy.menu.UploadSpeed.512000.windows=512000 +watchy.menu.UploadSpeed.512000.upload.speed=512000 + +watchy.menu.DebugLevel.none=None +watchy.menu.DebugLevel.none.build.code_debug=0 +watchy.menu.DebugLevel.error=Error +watchy.menu.DebugLevel.error.build.code_debug=1 +watchy.menu.DebugLevel.warn=Warn +watchy.menu.DebugLevel.warn.build.code_debug=2 +watchy.menu.DebugLevel.info=Info +watchy.menu.DebugLevel.info.build.code_debug=3 +watchy.menu.DebugLevel.debug=Debug +watchy.menu.DebugLevel.debug.build.code_debug=4 +watchy.menu.DebugLevel.verbose=Verbose +watchy.menu.DebugLevel.verbose.build.code_debug=5 + +watchy.menu.EraseFlash.none=Disabled +watchy.menu.EraseFlash.none.upload.erase_cmd= +watchy.menu.EraseFlash.all=Enabled +watchy.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +AirM2M_CORE_ESP32C3.name=AirM2M_CORE_ESP32C3 + +AirM2M_CORE_ESP32C3.upload.tool=esptool_py +AirM2M_CORE_ESP32C3.upload.tool.default=esptool_py +AirM2M_CORE_ESP32C3.upload.tool.network=esp_ota +AirM2M_CORE_ESP32C3.upload.maximum_size=1310720 +AirM2M_CORE_ESP32C3.upload.maximum_data_size=327680 +AirM2M_CORE_ESP32C3.upload.flags= +AirM2M_CORE_ESP32C3.upload.extra_flags= +AirM2M_CORE_ESP32C3.upload.use_1200bps_touch=false +AirM2M_CORE_ESP32C3.upload.wait_for_upload_port=false + +AirM2M_CORE_ESP32C3.serial.disableDTR=false +AirM2M_CORE_ESP32C3.serial.disableRTS=false + +AirM2M_CORE_ESP32C3.build.tarch=riscv32 +AirM2M_CORE_ESP32C3.build.target=esp +AirM2M_CORE_ESP32C3.build.mcu=esp32c3 +AirM2M_CORE_ESP32C3.build.core=esp32 +AirM2M_CORE_ESP32C3.build.variant=AirM2M_CORE_ESP32C3 +AirM2M_CORE_ESP32C3.build.board=AirM2M_CORE_ESP32C3 +AirM2M_CORE_ESP32C3.build.bootloader_addr=0x0 + +AirM2M_CORE_ESP32C3.build.cdc_on_boot=0 +AirM2M_CORE_ESP32C3.build.f_cpu=160000000L +AirM2M_CORE_ESP32C3.build.flash_size=4MB +AirM2M_CORE_ESP32C3.build.flash_freq=80m +AirM2M_CORE_ESP32C3.build.flash_mode=dio +AirM2M_CORE_ESP32C3.build.boot=dio +AirM2M_CORE_ESP32C3.build.partitions=default +AirM2M_CORE_ESP32C3.build.defines= + +AirM2M_CORE_ESP32C3.menu.CDCOnBoot.default=Disabled +AirM2M_CORE_ESP32C3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +AirM2M_CORE_ESP32C3.menu.CDCOnBoot.cdc=Enabled +AirM2M_CORE_ESP32C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +AirM2M_CORE_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.default.build.partitions=default +AirM2M_CORE_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +AirM2M_CORE_ESP32C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.minimal.build.partitions=minimal +AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +AirM2M_CORE_ESP32C3.menu.CPUFreq.160=160MHz (WiFi) +AirM2M_CORE_ESP32C3.menu.CPUFreq.160.build.f_cpu=160000000L +AirM2M_CORE_ESP32C3.menu.CPUFreq.80=80MHz (WiFi) +AirM2M_CORE_ESP32C3.menu.CPUFreq.80.build.f_cpu=80000000L +AirM2M_CORE_ESP32C3.menu.CPUFreq.40=40MHz +AirM2M_CORE_ESP32C3.menu.CPUFreq.40.build.f_cpu=40000000L +AirM2M_CORE_ESP32C3.menu.CPUFreq.20=20MHz +AirM2M_CORE_ESP32C3.menu.CPUFreq.20.build.f_cpu=20000000L +AirM2M_CORE_ESP32C3.menu.CPUFreq.10=10MHz +AirM2M_CORE_ESP32C3.menu.CPUFreq.10.build.f_cpu=10000000L + +AirM2M_CORE_ESP32C3.menu.FlashFreq.80=80MHz +AirM2M_CORE_ESP32C3.menu.FlashFreq.80.build.flash_freq=80m +AirM2M_CORE_ESP32C3.menu.FlashFreq.40=40MHz +AirM2M_CORE_ESP32C3.menu.FlashFreq.40.build.flash_freq=40m + +AirM2M_CORE_ESP32C3.menu.UploadSpeed.921600=921600 +AirM2M_CORE_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600 +AirM2M_CORE_ESP32C3.menu.UploadSpeed.115200=115200 +AirM2M_CORE_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200 +AirM2M_CORE_ESP32C3.menu.UploadSpeed.1152000=1152000 +AirM2M_CORE_ESP32C3.menu.UploadSpeed.1152000.upload.speed=1152000 + + +AirM2M_CORE_ESP32C3.menu.DebugLevel.none=None +AirM2M_CORE_ESP32C3.menu.DebugLevel.none.build.code_debug=0 +AirM2M_CORE_ESP32C3.menu.DebugLevel.error=Error +AirM2M_CORE_ESP32C3.menu.DebugLevel.error.build.code_debug=1 +AirM2M_CORE_ESP32C3.menu.DebugLevel.warn=Warn +AirM2M_CORE_ESP32C3.menu.DebugLevel.warn.build.code_debug=2 +AirM2M_CORE_ESP32C3.menu.DebugLevel.info=Info +AirM2M_CORE_ESP32C3.menu.DebugLevel.info.build.code_debug=3 +AirM2M_CORE_ESP32C3.menu.DebugLevel.debug=Debug +AirM2M_CORE_ESP32C3.menu.DebugLevel.debug.build.code_debug=4 +AirM2M_CORE_ESP32C3.menu.DebugLevel.verbose=Verbose +AirM2M_CORE_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5 + +AirM2M_CORE_ESP32C3.menu.EraseFlash.none=Disabled +AirM2M_CORE_ESP32C3.menu.EraseFlash.none.upload.erase_cmd= +AirM2M_CORE_ESP32C3.menu.EraseFlash.all=Enabled +AirM2M_CORE_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################# + + +XIAO_ESP32C3.name=XIAO_ESP32C3 +XIAO_ESP32C3.vid.0=0x2886 +XIAO_ESP32C3.pid.0=0x0046 + +XIAO_ESP32C3.bootloader.tool=esptool_py +XIAO_ESP32C3.bootloader.tool.default=esptool_py + +XIAO_ESP32C3.upload.tool=esptool_py +XIAO_ESP32C3.upload.tool.default=esptool_py +XIAO_ESP32C3.upload.tool.network=esp_ota + +XIAO_ESP32C3.upload.maximum_size=1310720 +XIAO_ESP32C3.upload.maximum_data_size=327680 +XIAO_ESP32C3.upload.flags= +XIAO_ESP32C3.upload.extra_flags= +XIAO_ESP32C3.upload.use_1200bps_touch=false +XIAO_ESP32C3.upload.wait_for_upload_port=false + +XIAO_ESP32C3.serial.disableDTR=false +XIAO_ESP32C3.serial.disableRTS=false + +XIAO_ESP32C3.build.tarch=riscv32 +XIAO_ESP32C3.build.target=esp +XIAO_ESP32C3.build.mcu=esp32c3 +XIAO_ESP32C3.build.core=esp32 +XIAO_ESP32C3.build.variant=XIAO_ESP32C3 +XIAO_ESP32C3.build.board=XIAO_ESP32C3 +XIAO_ESP32C3.build.bootloader_addr=0x0 + +XIAO_ESP32C3.build.cdc_on_boot=1 +XIAO_ESP32C3.build.f_cpu=160000000L +XIAO_ESP32C3.build.flash_size=4MB +XIAO_ESP32C3.build.flash_freq=80m +XIAO_ESP32C3.build.flash_mode=qio +XIAO_ESP32C3.build.boot=qio +XIAO_ESP32C3.build.partitions=default +XIAO_ESP32C3.build.defines= + +XIAO_ESP32C3.menu.CDCOnBoot.default=Enabled +XIAO_ESP32C3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +XIAO_ESP32C3.menu.CDCOnBoot.cdc=Disabled +XIAO_ESP32C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +XIAO_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.default.build.partitions=default +XIAO_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +XIAO_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +XIAO_ESP32C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +XIAO_ESP32C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +XIAO_ESP32C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.minimal.build.partitions=minimal +XIAO_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +XIAO_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +XIAO_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +XIAO_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +XIAO_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +XIAO_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +XIAO_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +XIAO_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +XIAO_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +XIAO_ESP32C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +XIAO_ESP32C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +XIAO_ESP32C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +XIAO_ESP32C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +XIAO_ESP32C3.menu.PartitionScheme.fatflash.build.partitions=ffat +XIAO_ESP32C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +XIAO_ESP32C3.menu.PartitionScheme.rainmaker=RainMaker 4MB +XIAO_ESP32C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +XIAO_ESP32C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +XIAO_ESP32C3.menu.CPUFreq.160=160MHz (WiFi) +XIAO_ESP32C3.menu.CPUFreq.160.build.f_cpu=160000000L +XIAO_ESP32C3.menu.CPUFreq.80=80MHz (WiFi) +XIAO_ESP32C3.menu.CPUFreq.80.build.f_cpu=80000000L +XIAO_ESP32C3.menu.CPUFreq.40=40MHz +XIAO_ESP32C3.menu.CPUFreq.40.build.f_cpu=40000000L +XIAO_ESP32C3.menu.CPUFreq.20=20MHz +XIAO_ESP32C3.menu.CPUFreq.20.build.f_cpu=20000000L +XIAO_ESP32C3.menu.CPUFreq.10=10MHz +XIAO_ESP32C3.menu.CPUFreq.10.build.f_cpu=10000000L + +XIAO_ESP32C3.menu.FlashMode.qio=QIO +XIAO_ESP32C3.menu.FlashMode.qio.build.flash_mode=dio +XIAO_ESP32C3.menu.FlashMode.qio.build.boot=qio +XIAO_ESP32C3.menu.FlashMode.dio=DIO +XIAO_ESP32C3.menu.FlashMode.dio.build.flash_mode=dio +XIAO_ESP32C3.menu.FlashMode.dio.build.boot=dio + +XIAO_ESP32C3.menu.FlashFreq.80=80MHz +XIAO_ESP32C3.menu.FlashFreq.80.build.flash_freq=80m +XIAO_ESP32C3.menu.FlashFreq.40=40MHz +XIAO_ESP32C3.menu.FlashFreq.40.build.flash_freq=40m + +XIAO_ESP32C3.menu.FlashSize.4M=4MB (32Mb) +XIAO_ESP32C3.menu.FlashSize.4M.build.flash_size=4MB +XIAO_ESP32C3.menu.FlashSize.8M=8MB (64Mb) +XIAO_ESP32C3.menu.FlashSize.8M.build.flash_size=8MB +XIAO_ESP32C3.menu.FlashSize.2M=2MB (16Mb) +XIAO_ESP32C3.menu.FlashSize.2M.build.flash_size=2MB +XIAO_ESP32C3.menu.FlashSize.16M=16MB (128Mb) +XIAO_ESP32C3.menu.FlashSize.16M.build.flash_size=16MB + +XIAO_ESP32C3.menu.UploadSpeed.921600=921600 +XIAO_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600 +XIAO_ESP32C3.menu.UploadSpeed.115200=115200 +XIAO_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200 +XIAO_ESP32C3.menu.UploadSpeed.256000.windows=256000 +XIAO_ESP32C3.menu.UploadSpeed.256000.upload.speed=256000 +XIAO_ESP32C3.menu.UploadSpeed.230400.windows.upload.speed=256000 +XIAO_ESP32C3.menu.UploadSpeed.230400=230400 +XIAO_ESP32C3.menu.UploadSpeed.230400.upload.speed=230400 +XIAO_ESP32C3.menu.UploadSpeed.460800.linux=460800 +XIAO_ESP32C3.menu.UploadSpeed.460800.macosx=460800 +XIAO_ESP32C3.menu.UploadSpeed.460800.upload.speed=460800 +XIAO_ESP32C3.menu.UploadSpeed.512000.windows=512000 +XIAO_ESP32C3.menu.UploadSpeed.512000.upload.speed=512000 + +XIAO_ESP32C3.menu.DebugLevel.none=None +XIAO_ESP32C3.menu.DebugLevel.none.build.code_debug=0 +XIAO_ESP32C3.menu.DebugLevel.error=Error +XIAO_ESP32C3.menu.DebugLevel.error.build.code_debug=1 +XIAO_ESP32C3.menu.DebugLevel.warn=Warn +XIAO_ESP32C3.menu.DebugLevel.warn.build.code_debug=2 +XIAO_ESP32C3.menu.DebugLevel.info=Info +XIAO_ESP32C3.menu.DebugLevel.info.build.code_debug=3 +XIAO_ESP32C3.menu.DebugLevel.debug=Debug +XIAO_ESP32C3.menu.DebugLevel.debug.build.code_debug=4 +XIAO_ESP32C3.menu.DebugLevel.verbose=Verbose +XIAO_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5 + +XIAO_ESP32C3.menu.EraseFlash.none=Disabled +XIAO_ESP32C3.menu.EraseFlash.none.upload.erase_cmd= +XIAO_ESP32C3.menu.EraseFlash.all=Enabled +XIAO_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +XIAO_ESP32C5.name=XIAO_ESP32C5 + +XIAO_ESP32C5.vid.0=0x2886 +XIAO_ESP32C5.pid.0=0x0067 + +XIAO_ESP32C5.bootloader.tool=esptool_py +XIAO_ESP32C5.bootloader.tool.default=esptool_py + +XIAO_ESP32C5.upload.tool=esptool_py +XIAO_ESP32C5.upload.tool.default=esptool_py +XIAO_ESP32C5.upload.tool.network=esp_ota + +XIAO_ESP32C5.upload.maximum_size=1310720 +XIAO_ESP32C5.upload.maximum_data_size=327680 +XIAO_ESP32C5.upload.flags= +XIAO_ESP32C5.upload.extra_flags= +XIAO_ESP32C5.upload.use_1200bps_touch=false +XIAO_ESP32C5.upload.wait_for_upload_port=false + +XIAO_ESP32C5.serial.disableDTR=false +XIAO_ESP32C5.serial.disableRTS=false + +XIAO_ESP32C5.build.tarch=riscv32 +XIAO_ESP32C5.build.target=esp +XIAO_ESP32C5.build.mcu=esp32c5 +XIAO_ESP32C5.build.core=esp32 +XIAO_ESP32C5.build.variant=XIAO_ESP32C5 +XIAO_ESP32C5.build.board=XIAO_ESP32C5 +XIAO_ESP32C5.build.bootloader_addr=0x2000 + +XIAO_ESP32C5.build.cdc_on_boot=1 +XIAO_ESP32C5.build.f_cpu=240000000L +XIAO_ESP32C5.build.flash_size=8MB +XIAO_ESP32C5.build.flash_freq=80m +XIAO_ESP32C5.build.flash_mode=qio +XIAO_ESP32C5.build.boot=qio +XIAO_ESP32C5.build.partitions=default_8MB +XIAO_ESP32C5.build.defines= + +## IDE 2.0 Seems to not update the value +XIAO_ESP32C5.menu.JTAGAdapter.default=Disabled +XIAO_ESP32C5.menu.JTAGAdapter.default.build.copy_jtag_files=0 +XIAO_ESP32C5.menu.JTAGAdapter.builtin=Integrated USB JTAG +XIAO_ESP32C5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg +XIAO_ESP32C5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +XIAO_ESP32C5.menu.JTAGAdapter.external=FTDI Adapter +XIAO_ESP32C5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg +XIAO_ESP32C5.menu.JTAGAdapter.external.build.copy_jtag_files=1 +XIAO_ESP32C5.menu.JTAGAdapter.bridge=ESP USB Bridge +XIAO_ESP32C5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg +XIAO_ESP32C5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +XIAO_ESP32C5.menu.PSRAM.disabled=Disabled +XIAO_ESP32C5.menu.PSRAM.disabled.build.defines= +XIAO_ESP32C5.menu.PSRAM.enabled=Enabled +XIAO_ESP32C5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +XIAO_ESP32C5.menu.CDCOnBoot.cdc=Enabled +XIAO_ESP32C5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +XIAO_ESP32C5.menu.CDCOnBoot.default=Disabled +XIAO_ESP32C5.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +XIAO_ESP32C5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +XIAO_ESP32C5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +XIAO_ESP32C5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.default.build.partitions=default +XIAO_ESP32C5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +XIAO_ESP32C5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +XIAO_ESP32C5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.minimal.build.partitions=minimal +XIAO_ESP32C5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.no_ota.build.partitions=no_ota +XIAO_ESP32C5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +XIAO_ESP32C5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +XIAO_ESP32C5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +XIAO_ESP32C5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +XIAO_ESP32C5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +XIAO_ESP32C5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +XIAO_ESP32C5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +XIAO_ESP32C5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +XIAO_ESP32C5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +XIAO_ESP32C5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.huge_app.build.partitions=huge_app +XIAO_ESP32C5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +XIAO_ESP32C5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +XIAO_ESP32C5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +XIAO_ESP32C5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +XIAO_ESP32C5.menu.PartitionScheme.rainmaker=RainMaker 4MB +XIAO_ESP32C5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +XIAO_ESP32C5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +XIAO_ESP32C5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480 +XIAO_ESP32C5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +XIAO_ESP32C5.menu.PartitionScheme.zigbee.build.partitions=zigbee +XIAO_ESP32C5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +XIAO_ESP32C5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +XIAO_ESP32C5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +XIAO_ESP32C5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +XIAO_ESP32C5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 + +XIAO_ESP32C5.menu.CPUFreq.240=240MHz (WiFi) +XIAO_ESP32C5.menu.CPUFreq.240.build.f_cpu=240000000L +XIAO_ESP32C5.menu.CPUFreq.160=160MHz (WiFi) +XIAO_ESP32C5.menu.CPUFreq.160.build.f_cpu=160000000L +XIAO_ESP32C5.menu.CPUFreq.80=80MHz (WiFi) +XIAO_ESP32C5.menu.CPUFreq.80.build.f_cpu=80000000L +XIAO_ESP32C5.menu.CPUFreq.40=40MHz +XIAO_ESP32C5.menu.CPUFreq.40.build.f_cpu=40000000L +XIAO_ESP32C5.menu.CPUFreq.20=20MHz +XIAO_ESP32C5.menu.CPUFreq.20.build.f_cpu=20000000L +XIAO_ESP32C5.menu.CPUFreq.10=10MHz +XIAO_ESP32C5.menu.CPUFreq.10.build.f_cpu=10000000L + +XIAO_ESP32C5.menu.FlashMode.qio=QIO +XIAO_ESP32C5.menu.FlashMode.qio.build.flash_mode=dio +XIAO_ESP32C5.menu.FlashMode.qio.build.boot=qio +XIAO_ESP32C5.menu.FlashMode.dio=DIO +XIAO_ESP32C5.menu.FlashMode.dio.build.flash_mode=dio +XIAO_ESP32C5.menu.FlashMode.dio.build.boot=dio + +XIAO_ESP32C5.menu.FlashFreq.80=80MHz +XIAO_ESP32C5.menu.FlashFreq.80.build.flash_freq=80m +XIAO_ESP32C5.menu.FlashFreq.40=40MHz +XIAO_ESP32C5.menu.FlashFreq.40.build.flash_freq=40m + +XIAO_ESP32C5.menu.FlashSize.8M=8MB (64Mb) +XIAO_ESP32C5.menu.FlashSize.8M.build.flash_size=8MB + +XIAO_ESP32C5.menu.UploadSpeed.921600=921600 +XIAO_ESP32C5.menu.UploadSpeed.921600.upload.speed=921600 +XIAO_ESP32C5.menu.UploadSpeed.115200=115200 +XIAO_ESP32C5.menu.UploadSpeed.115200.upload.speed=115200 +XIAO_ESP32C5.menu.UploadSpeed.256000.windows=256000 +XIAO_ESP32C5.menu.UploadSpeed.256000.upload.speed=256000 +XIAO_ESP32C5.menu.UploadSpeed.230400.windows.upload.speed=256000 +XIAO_ESP32C5.menu.UploadSpeed.230400=230400 +XIAO_ESP32C5.menu.UploadSpeed.230400.upload.speed=230400 +XIAO_ESP32C5.menu.UploadSpeed.460800.linux=460800 +XIAO_ESP32C5.menu.UploadSpeed.460800.macosx=460800 +XIAO_ESP32C5.menu.UploadSpeed.460800.upload.speed=460800 +XIAO_ESP32C5.menu.UploadSpeed.512000.windows=512000 +XIAO_ESP32C5.menu.UploadSpeed.512000.upload.speed=512000 + +XIAO_ESP32C5.menu.DebugLevel.none=None +XIAO_ESP32C5.menu.DebugLevel.none.build.code_debug=0 +XIAO_ESP32C5.menu.DebugLevel.error=Error +XIAO_ESP32C5.menu.DebugLevel.error.build.code_debug=1 +XIAO_ESP32C5.menu.DebugLevel.warn=Warn +XIAO_ESP32C5.menu.DebugLevel.warn.build.code_debug=2 +XIAO_ESP32C5.menu.DebugLevel.info=Info +XIAO_ESP32C5.menu.DebugLevel.info.build.code_debug=3 +XIAO_ESP32C5.menu.DebugLevel.debug=Debug +XIAO_ESP32C5.menu.DebugLevel.debug.build.code_debug=4 +XIAO_ESP32C5.menu.DebugLevel.verbose=Verbose +XIAO_ESP32C5.menu.DebugLevel.verbose.build.code_debug=5 + +XIAO_ESP32C5.menu.EraseFlash.none=Disabled +XIAO_ESP32C5.menu.EraseFlash.none.upload.erase_cmd= +XIAO_ESP32C5.menu.EraseFlash.all=Enabled +XIAO_ESP32C5.menu.EraseFlash.all.upload.erase_cmd=-e + +XIAO_ESP32C5.menu.ZigbeeMode.default=Disabled +XIAO_ESP32C5.menu.ZigbeeMode.default.build.zigbee_mode= +XIAO_ESP32C5.menu.ZigbeeMode.default.build.zigbee_libs= +XIAO_ESP32C5.menu.ZigbeeMode.ed=Zigbee ED (end device) +XIAO_ESP32C5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +XIAO_ESP32C5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +XIAO_ESP32C5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +XIAO_ESP32C5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +XIAO_ESP32C5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +XIAO_ESP32C5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +XIAO_ESP32C5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +XIAO_ESP32C5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +XIAO_ESP32C5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +XIAO_ESP32C5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +XIAO_ESP32C5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## + +XIAO_ESP32C6.name=XIAO_ESP32C6 + +XIAO_ESP32C6.bootloader.tool=esptool_py +XIAO_ESP32C6.bootloader.tool.default=esptool_py + +XIAO_ESP32C6.upload.tool=esptool_py +XIAO_ESP32C6.upload.tool.default=esptool_py +XIAO_ESP32C6.upload.tool.network=esp_ota + +XIAO_ESP32C6.upload.maximum_size=1310720 +XIAO_ESP32C6.upload.maximum_data_size=327680 +XIAO_ESP32C6.upload.flags= +XIAO_ESP32C6.upload.extra_flags= +XIAO_ESP32C6.upload.use_1200bps_touch=false +XIAO_ESP32C6.upload.wait_for_upload_port=false + +XIAO_ESP32C6.serial.disableDTR=false +XIAO_ESP32C6.serial.disableRTS=false + +XIAO_ESP32C6.build.tarch=riscv32 +XIAO_ESP32C6.build.target=esp +XIAO_ESP32C6.build.mcu=esp32c6 +XIAO_ESP32C6.build.core=esp32 +XIAO_ESP32C6.build.variant=XIAO_ESP32C6 +XIAO_ESP32C6.build.board=XIAO_ESP32C6 +XIAO_ESP32C6.build.bootloader_addr=0x0 + +XIAO_ESP32C6.build.cdc_on_boot=1 +XIAO_ESP32C6.build.f_cpu=160000000L +XIAO_ESP32C6.build.flash_size=4MB +XIAO_ESP32C6.build.flash_freq=80m +XIAO_ESP32C6.build.flash_mode=qio +XIAO_ESP32C6.build.boot=qio +XIAO_ESP32C6.build.partitions=default +XIAO_ESP32C6.build.defines= + +## IDE 2.0 Seems to not update the value +XIAO_ESP32C6.menu.JTAGAdapter.default=Disabled +XIAO_ESP32C6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +XIAO_ESP32C6.menu.JTAGAdapter.builtin=Integrated USB JTAG +XIAO_ESP32C6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +XIAO_ESP32C6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +XIAO_ESP32C6.menu.JTAGAdapter.external=FTDI Adapter +XIAO_ESP32C6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +XIAO_ESP32C6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +XIAO_ESP32C6.menu.JTAGAdapter.bridge=ESP USB Bridge +XIAO_ESP32C6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +XIAO_ESP32C6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +XIAO_ESP32C6.menu.CDCOnBoot.cdc=Enabled +XIAO_ESP32C6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +XIAO_ESP32C6.menu.CDCOnBoot.default=Disabled +XIAO_ESP32C6.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +XIAO_ESP32C6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +XIAO_ESP32C6.menu.PartitionScheme.default.build.partitions=default +XIAO_ESP32C6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +XIAO_ESP32C6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +XIAO_ESP32C6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +XIAO_ESP32C6.menu.PartitionScheme.no_ota.build.partitions=no_ota +XIAO_ESP32C6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +XIAO_ESP32C6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +XIAO_ESP32C6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +XIAO_ESP32C6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +XIAO_ESP32C6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +XIAO_ESP32C6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +XIAO_ESP32C6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +XIAO_ESP32C6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +XIAO_ESP32C6.menu.PartitionScheme.huge_app.build.partitions=huge_app +XIAO_ESP32C6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +XIAO_ESP32C6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +XIAO_ESP32C6.menu.PartitionScheme.zigbee.build.partitions=zigbee +XIAO_ESP32C6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +XIAO_ESP32C6.menu.CPUFreq.160=160MHz (WiFi) +XIAO_ESP32C6.menu.CPUFreq.160.build.f_cpu=160000000L +XIAO_ESP32C6.menu.CPUFreq.80=80MHz (WiFi) +XIAO_ESP32C6.menu.CPUFreq.80.build.f_cpu=80000000L +XIAO_ESP32C6.menu.CPUFreq.40=40MHz +XIAO_ESP32C6.menu.CPUFreq.40.build.f_cpu=40000000L +XIAO_ESP32C6.menu.CPUFreq.20=20MHz +XIAO_ESP32C6.menu.CPUFreq.20.build.f_cpu=20000000L +XIAO_ESP32C6.menu.CPUFreq.10=10MHz +XIAO_ESP32C6.menu.CPUFreq.10.build.f_cpu=10000000L + +XIAO_ESP32C6.menu.FlashMode.qio=QIO +XIAO_ESP32C6.menu.FlashMode.qio.build.flash_mode=dio +XIAO_ESP32C6.menu.FlashMode.qio.build.boot=qio +XIAO_ESP32C6.menu.FlashMode.dio=DIO +XIAO_ESP32C6.menu.FlashMode.dio.build.flash_mode=dio +XIAO_ESP32C6.menu.FlashMode.dio.build.boot=dio + +XIAO_ESP32C6.menu.FlashFreq.80=80MHz +XIAO_ESP32C6.menu.FlashFreq.80.build.flash_freq=80m +XIAO_ESP32C6.menu.FlashFreq.40=40MHz +XIAO_ESP32C6.menu.FlashFreq.40.build.flash_freq=40m + +XIAO_ESP32C6.menu.FlashSize.4M=4MB (32Mb) +XIAO_ESP32C6.menu.FlashSize.4M.build.flash_size=4MB + +XIAO_ESP32C6.menu.UploadSpeed.921600=921600 +XIAO_ESP32C6.menu.UploadSpeed.921600.upload.speed=921600 +XIAO_ESP32C6.menu.UploadSpeed.115200=115200 +XIAO_ESP32C6.menu.UploadSpeed.115200.upload.speed=115200 +XIAO_ESP32C6.menu.UploadSpeed.256000.windows=256000 +XIAO_ESP32C6.menu.UploadSpeed.256000.upload.speed=256000 +XIAO_ESP32C6.menu.UploadSpeed.230400.windows.upload.speed=256000 +XIAO_ESP32C6.menu.UploadSpeed.230400=230400 +XIAO_ESP32C6.menu.UploadSpeed.230400.upload.speed=230400 +XIAO_ESP32C6.menu.UploadSpeed.460800.linux=460800 +XIAO_ESP32C6.menu.UploadSpeed.460800.macosx=460800 +XIAO_ESP32C6.menu.UploadSpeed.460800.upload.speed=460800 +XIAO_ESP32C6.menu.UploadSpeed.512000.windows=512000 +XIAO_ESP32C6.menu.UploadSpeed.512000.upload.speed=512000 + +XIAO_ESP32C6.menu.DebugLevel.none=None +XIAO_ESP32C6.menu.DebugLevel.none.build.code_debug=0 +XIAO_ESP32C6.menu.DebugLevel.error=Error +XIAO_ESP32C6.menu.DebugLevel.error.build.code_debug=1 +XIAO_ESP32C6.menu.DebugLevel.warn=Warn +XIAO_ESP32C6.menu.DebugLevel.warn.build.code_debug=2 +XIAO_ESP32C6.menu.DebugLevel.info=Info +XIAO_ESP32C6.menu.DebugLevel.info.build.code_debug=3 +XIAO_ESP32C6.menu.DebugLevel.debug=Debug +XIAO_ESP32C6.menu.DebugLevel.debug.build.code_debug=4 +XIAO_ESP32C6.menu.DebugLevel.verbose=Verbose +XIAO_ESP32C6.menu.DebugLevel.verbose.build.code_debug=5 + +XIAO_ESP32C6.menu.EraseFlash.none=Disabled +XIAO_ESP32C6.menu.EraseFlash.none.upload.erase_cmd= +XIAO_ESP32C6.menu.EraseFlash.all=Enabled +XIAO_ESP32C6.menu.EraseFlash.all.upload.erase_cmd=-e + +XIAO_ESP32C6.menu.ZigbeeMode.default=Disabled +XIAO_ESP32C6.menu.ZigbeeMode.default.build.zigbee_mode= +XIAO_ESP32C6.menu.ZigbeeMode.default.build.zigbee_libs= +XIAO_ESP32C6.menu.ZigbeeMode.ed=Zigbee ED (end device) +XIAO_ESP32C6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +XIAO_ESP32C6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +XIAO_ESP32C6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +XIAO_ESP32C6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +XIAO_ESP32C6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +XIAO_ESP32S3.name=XIAO_ESP32S3 +XIAO_ESP32S3.vid.0=0x2886 +XIAO_ESP32S3.pid.0=0x0056 +XIAO_ESP32S3.vid.1=0x2886 +XIAO_ESP32S3.pid.1=0x8056 + +XIAO_ESP32S3.bootloader.tool=esptool_py +XIAO_ESP32S3.bootloader.tool.default=esptool_py + +XIAO_ESP32S3.upload.tool=esptool_py +XIAO_ESP32S3.upload.tool.default=esptool_py +XIAO_ESP32S3.upload.tool.network=esp_ota + +XIAO_ESP32S3.upload.maximum_size=1310720 +XIAO_ESP32S3.upload.maximum_data_size=327680 +XIAO_ESP32S3.upload.flags= +XIAO_ESP32S3.upload.extra_flags= +XIAO_ESP32S3.upload.use_1200bps_touch=false +XIAO_ESP32S3.upload.wait_for_upload_port=false + +XIAO_ESP32S3.serial.disableDTR=false +XIAO_ESP32S3.serial.disableRTS=false + +XIAO_ESP32S3.build.tarch=xtensa +XIAO_ESP32S3.build.bootloader_addr=0x0 +XIAO_ESP32S3.build.target=esp32s3 +XIAO_ESP32S3.build.mcu=esp32s3 +XIAO_ESP32S3.build.core=esp32 +XIAO_ESP32S3.build.variant=XIAO_ESP32S3 +XIAO_ESP32S3.build.board=XIAO_ESP32S3 + +XIAO_ESP32S3.build.usb_mode=0 +XIAO_ESP32S3.build.cdc_on_boot=1 +XIAO_ESP32S3.build.msc_on_boot=0 +XIAO_ESP32S3.build.dfu_on_boot=0 +XIAO_ESP32S3.build.f_cpu=240000000L +XIAO_ESP32S3.build.flash_size=8MB +XIAO_ESP32S3.build.flash_freq=80m +XIAO_ESP32S3.build.flash_mode=dio +XIAO_ESP32S3.build.boot=qio +XIAO_ESP32S3.build.boot_freq=80m +XIAO_ESP32S3.build.partitions=default_8MB +XIAO_ESP32S3.build.defines= +XIAO_ESP32S3.build.loop_core= +XIAO_ESP32S3.build.event_core= +XIAO_ESP32S3.build.psram_type=qspi +XIAO_ESP32S3.build.memory_type={build.boot}_{build.psram_type} + +XIAO_ESP32S3.menu.JTAGAdapter.default=Disabled +XIAO_ESP32S3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +XIAO_ESP32S3.menu.JTAGAdapter.builtin=Integrated USB JTAG +XIAO_ESP32S3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +XIAO_ESP32S3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +XIAO_ESP32S3.menu.JTAGAdapter.external=FTDI Adapter +XIAO_ESP32S3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +XIAO_ESP32S3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +XIAO_ESP32S3.menu.JTAGAdapter.bridge=ESP USB Bridge +XIAO_ESP32S3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +XIAO_ESP32S3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +XIAO_ESP32S3.menu.PSRAM.disabled=Disabled +XIAO_ESP32S3.menu.PSRAM.disabled.build.defines= +XIAO_ESP32S3.menu.PSRAM.disabled.build.psram_type=qspi +XIAO_ESP32S3.menu.PSRAM.opi=OPI PSRAM +XIAO_ESP32S3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +XIAO_ESP32S3.menu.PSRAM.opi.build.psram_type=opi + +XIAO_ESP32S3.menu.FlashMode.qio=QIO 80MHz +XIAO_ESP32S3.menu.FlashMode.qio.build.flash_mode=dio +XIAO_ESP32S3.menu.FlashMode.qio.build.boot=qio +XIAO_ESP32S3.menu.FlashMode.qio.build.boot_freq=80m +XIAO_ESP32S3.menu.FlashMode.qio.build.flash_freq=80m +XIAO_ESP32S3.menu.FlashMode.dio=DIO 80MHz +XIAO_ESP32S3.menu.FlashMode.dio.build.flash_mode=dio +XIAO_ESP32S3.menu.FlashMode.dio.build.boot=dio +XIAO_ESP32S3.menu.FlashMode.dio.build.boot_freq=80m +XIAO_ESP32S3.menu.FlashMode.dio.build.flash_freq=80m + +XIAO_ESP32S3.menu.FlashSize.8M=8MB (64Mb) +XIAO_ESP32S3.menu.FlashSize.8M.build.flash_size=8MB + +XIAO_ESP32S3.menu.LoopCore.1=Core 1 +XIAO_ESP32S3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +XIAO_ESP32S3.menu.LoopCore.0=Core 0 +XIAO_ESP32S3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +XIAO_ESP32S3.menu.EventsCore.1=Core 1 +XIAO_ESP32S3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +XIAO_ESP32S3.menu.EventsCore.0=Core 0 +XIAO_ESP32S3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +XIAO_ESP32S3.menu.USBMode.hwcdc=Hardware CDC and JTAG +XIAO_ESP32S3.menu.USBMode.hwcdc.build.usb_mode=1 +XIAO_ESP32S3.menu.USBMode.default=USB-OTG (TinyUSB) +XIAO_ESP32S3.menu.USBMode.default.build.usb_mode=0 + +XIAO_ESP32S3.menu.CDCOnBoot.default=Enabled +XIAO_ESP32S3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +XIAO_ESP32S3.menu.CDCOnBoot.cdc=Disabled +XIAO_ESP32S3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +XIAO_ESP32S3.menu.MSCOnBoot.default=Disabled +XIAO_ESP32S3.menu.MSCOnBoot.default.build.msc_on_boot=0 +XIAO_ESP32S3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +XIAO_ESP32S3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +XIAO_ESP32S3.menu.DFUOnBoot.default=Disabled +XIAO_ESP32S3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +XIAO_ESP32S3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +XIAO_ESP32S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +XIAO_ESP32S3.menu.UploadMode.default=UART0 / Hardware CDC +XIAO_ESP32S3.menu.UploadMode.default.upload.use_1200bps_touch=false +XIAO_ESP32S3.menu.UploadMode.default.upload.wait_for_upload_port=false +XIAO_ESP32S3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +XIAO_ESP32S3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +XIAO_ESP32S3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +XIAO_ESP32S3.menu.PartitionScheme.default_8MB=Default with spiffs (3MB APP/1.5MB SPIFFS) +XIAO_ESP32S3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +XIAO_ESP32S3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT) +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FFAT) +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +XIAO_ESP32S3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" + + +XIAO_ESP32S3.menu.CPUFreq.240=240MHz (WiFi) +XIAO_ESP32S3.menu.CPUFreq.240.build.f_cpu=240000000L +XIAO_ESP32S3.menu.CPUFreq.160=160MHz (WiFi) +XIAO_ESP32S3.menu.CPUFreq.160.build.f_cpu=160000000L +XIAO_ESP32S3.menu.CPUFreq.80=80MHz (WiFi) +XIAO_ESP32S3.menu.CPUFreq.80.build.f_cpu=80000000L +XIAO_ESP32S3.menu.CPUFreq.40=40MHz +XIAO_ESP32S3.menu.CPUFreq.40.build.f_cpu=40000000L +XIAO_ESP32S3.menu.CPUFreq.20=20MHz +XIAO_ESP32S3.menu.CPUFreq.20.build.f_cpu=20000000L +XIAO_ESP32S3.menu.CPUFreq.10=10MHz +XIAO_ESP32S3.menu.CPUFreq.10.build.f_cpu=10000000L + +XIAO_ESP32S3.menu.UploadSpeed.921600=921600 +XIAO_ESP32S3.menu.UploadSpeed.921600.upload.speed=921600 +XIAO_ESP32S3.menu.UploadSpeed.115200=115200 +XIAO_ESP32S3.menu.UploadSpeed.115200.upload.speed=115200 +XIAO_ESP32S3.menu.UploadSpeed.256000.windows=256000 +XIAO_ESP32S3.menu.UploadSpeed.256000.upload.speed=256000 +XIAO_ESP32S3.menu.UploadSpeed.230400.windows.upload.speed=256000 +XIAO_ESP32S3.menu.UploadSpeed.230400=230400 +XIAO_ESP32S3.menu.UploadSpeed.230400.upload.speed=230400 +XIAO_ESP32S3.menu.UploadSpeed.460800.linux=460800 +XIAO_ESP32S3.menu.UploadSpeed.460800.macosx=460800 +XIAO_ESP32S3.menu.UploadSpeed.460800.upload.speed=460800 +XIAO_ESP32S3.menu.UploadSpeed.512000.windows=512000 +XIAO_ESP32S3.menu.UploadSpeed.512000.upload.speed=512000 + +XIAO_ESP32S3.menu.DebugLevel.none=None +XIAO_ESP32S3.menu.DebugLevel.none.build.code_debug=0 +XIAO_ESP32S3.menu.DebugLevel.error=Error +XIAO_ESP32S3.menu.DebugLevel.error.build.code_debug=1 +XIAO_ESP32S3.menu.DebugLevel.warn=Warn +XIAO_ESP32S3.menu.DebugLevel.warn.build.code_debug=2 +XIAO_ESP32S3.menu.DebugLevel.info=Info +XIAO_ESP32S3.menu.DebugLevel.info.build.code_debug=3 +XIAO_ESP32S3.menu.DebugLevel.debug=Debug +XIAO_ESP32S3.menu.DebugLevel.debug.build.code_debug=4 +XIAO_ESP32S3.menu.DebugLevel.verbose=Verbose +XIAO_ESP32S3.menu.DebugLevel.verbose.build.code_debug=5 + +XIAO_ESP32S3.menu.EraseFlash.none=Disabled +XIAO_ESP32S3.menu.EraseFlash.none.upload.erase_cmd= +XIAO_ESP32S3.menu.EraseFlash.all=Enabled +XIAO_ESP32S3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +XIAO_ESP32S3_Plus.name=XIAO_ESP32S3_PLUS +XIAO_ESP32S3_Plus.vid.0=0x2886 +XIAO_ESP32S3_Plus.pid.0=0x0063 +XIAO_ESP32S3_Plus.vid.1=0x2886 +XIAO_ESP32S3_Plus.pid.1=0x8063 + +XIAO_ESP32S3_Plus.bootloader.tool=esptool_py +XIAO_ESP32S3_Plus.bootloader.tool.default=esptool_py + +XIAO_ESP32S3_Plus.upload.tool=esptool_py +XIAO_ESP32S3_Plus.upload.tool.default=esptool_py +XIAO_ESP32S3_Plus.upload.tool.network=esp_ota + +XIAO_ESP32S3_Plus.upload.maximum_size=1310720 +XIAO_ESP32S3_Plus.upload.maximum_data_size=327680 +XIAO_ESP32S3_Plus.upload.flags= +XIAO_ESP32S3_Plus.upload.extra_flags= +XIAO_ESP32S3_Plus.upload.use_1200bps_touch=false +XIAO_ESP32S3_Plus.upload.wait_for_upload_port=false + +XIAO_ESP32S3_Plus.serial.disableDTR=false +XIAO_ESP32S3_Plus.serial.disableRTS=false + +XIAO_ESP32S3_Plus.build.tarch=xtensa +XIAO_ESP32S3_Plus.build.bootloader_addr=0x0 +XIAO_ESP32S3_Plus.build.target=esp32s3 +XIAO_ESP32S3_Plus.build.mcu=esp32s3 +XIAO_ESP32S3_Plus.build.core=esp32 +XIAO_ESP32S3_Plus.build.variant=XIAO_ESP32S3_Plus +XIAO_ESP32S3_Plus.build.board=XIAO_ESP32S3_PLUS + +XIAO_ESP32S3_Plus.build.usb_mode=0 +XIAO_ESP32S3_Plus.build.cdc_on_boot=1 +XIAO_ESP32S3_Plus.build.msc_on_boot=0 +XIAO_ESP32S3_Plus.build.dfu_on_boot=0 +XIAO_ESP32S3_Plus.build.f_cpu=240000000L +XIAO_ESP32S3_Plus.build.flash_size=16MB +XIAO_ESP32S3_Plus.build.flash_freq=80m +XIAO_ESP32S3_Plus.build.flash_mode=dio +XIAO_ESP32S3_Plus.build.boot=qio +XIAO_ESP32S3_Plus.build.boot_freq=80m +XIAO_ESP32S3_Plus.build.partitions=ffat +XIAO_ESP32S3_Plus.build.defines= +XIAO_ESP32S3_Plus.build.loop_core= +XIAO_ESP32S3_Plus.build.event_core= +XIAO_ESP32S3_Plus.build.psram_type=qspi +XIAO_ESP32S3_Plus.build.memory_type={build.boot}_{build.psram_type} + +XIAO_ESP32S3_Plus.menu.JTAGAdapter.default=Disabled +XIAO_ESP32S3_Plus.menu.JTAGAdapter.default.build.copy_jtag_files=0 +XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin=Integrated USB JTAG +XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +XIAO_ESP32S3_Plus.menu.JTAGAdapter.external=FTDI Adapter +XIAO_ESP32S3_Plus.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +XIAO_ESP32S3_Plus.menu.JTAGAdapter.external.build.copy_jtag_files=1 +XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge=ESP USB Bridge +XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +XIAO_ESP32S3_Plus.menu.PSRAM.disabled=Disabled +XIAO_ESP32S3_Plus.menu.PSRAM.disabled.build.defines= +XIAO_ESP32S3_Plus.menu.PSRAM.disabled.build.psram_type=qspi +XIAO_ESP32S3_Plus.menu.PSRAM.opi=OPI PSRAM +XIAO_ESP32S3_Plus.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +XIAO_ESP32S3_Plus.menu.PSRAM.opi.build.psram_type=opi + +XIAO_ESP32S3_Plus.menu.FlashMode.qio=QIO 80MHz +XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.flash_mode=dio +XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.boot=qio +XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.boot_freq=80m +XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.flash_freq=80m +XIAO_ESP32S3_Plus.menu.FlashMode.dio=DIO 80MHz +XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.flash_mode=dio +XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.boot=dio +XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.boot_freq=80m +XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.flash_freq=80m + +XIAO_ESP32S3_Plus.menu.FlashSize.16M=16MB (128Mb) +XIAO_ESP32S3_Plus.menu.FlashSize.16M.build.flash_size=16MB + +XIAO_ESP32S3_Plus.menu.LoopCore.1=Core 1 +XIAO_ESP32S3_Plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +XIAO_ESP32S3_Plus.menu.LoopCore.0=Core 0 +XIAO_ESP32S3_Plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +XIAO_ESP32S3_Plus.menu.EventsCore.1=Core 1 +XIAO_ESP32S3_Plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +XIAO_ESP32S3_Plus.menu.EventsCore.0=Core 0 +XIAO_ESP32S3_Plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +XIAO_ESP32S3_Plus.menu.USBMode.hwcdc=Hardware CDC and JTAG +XIAO_ESP32S3_Plus.menu.USBMode.hwcdc.build.usb_mode=1 +XIAO_ESP32S3_Plus.menu.USBMode.default=USB-OTG (TinyUSB) +XIAO_ESP32S3_Plus.menu.USBMode.default.build.usb_mode=0 + +XIAO_ESP32S3_Plus.menu.CDCOnBoot.default=Enabled +XIAO_ESP32S3_Plus.menu.CDCOnBoot.default.build.cdc_on_boot=1 +XIAO_ESP32S3_Plus.menu.CDCOnBoot.cdc=Disabled +XIAO_ESP32S3_Plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +XIAO_ESP32S3_Plus.menu.MSCOnBoot.default=Disabled +XIAO_ESP32S3_Plus.menu.MSCOnBoot.default.build.msc_on_boot=0 +XIAO_ESP32S3_Plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +XIAO_ESP32S3_Plus.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +XIAO_ESP32S3_Plus.menu.DFUOnBoot.default=Disabled +XIAO_ESP32S3_Plus.menu.DFUOnBoot.default.build.dfu_on_boot=0 +XIAO_ESP32S3_Plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +XIAO_ESP32S3_Plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +XIAO_ESP32S3_Plus.menu.UploadMode.default=UART0 / Hardware CDC +XIAO_ESP32S3_Plus.menu.UploadMode.default.upload.use_1200bps_touch=false +XIAO_ESP32S3_Plus.menu.UploadMode.default.upload.wait_for_upload_port=false +XIAO_ESP32S3_Plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +XIAO_ESP32S3_Plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true +XIAO_ESP32S3_Plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash.build.partitions=ffat +XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB=Default with spiffs (3MB APP/1.5MB SPIFFS) +XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 +XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT) +XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB +XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" + +XIAO_ESP32S3_Plus.menu.CPUFreq.240=240MHz (WiFi) +XIAO_ESP32S3_Plus.menu.CPUFreq.240.build.f_cpu=240000000L +XIAO_ESP32S3_Plus.menu.CPUFreq.160=160MHz (WiFi) +XIAO_ESP32S3_Plus.menu.CPUFreq.160.build.f_cpu=160000000L +XIAO_ESP32S3_Plus.menu.CPUFreq.80=80MHz (WiFi) +XIAO_ESP32S3_Plus.menu.CPUFreq.80.build.f_cpu=80000000L +XIAO_ESP32S3_Plus.menu.CPUFreq.40=40MHz +XIAO_ESP32S3_Plus.menu.CPUFreq.40.build.f_cpu=40000000L +XIAO_ESP32S3_Plus.menu.CPUFreq.20=20MHz +XIAO_ESP32S3_Plus.menu.CPUFreq.20.build.f_cpu=20000000L +XIAO_ESP32S3_Plus.menu.CPUFreq.10=10MHz +XIAO_ESP32S3_Plus.menu.CPUFreq.10.build.f_cpu=10000000L + +XIAO_ESP32S3_Plus.menu.UploadSpeed.921600=921600 +XIAO_ESP32S3_Plus.menu.UploadSpeed.921600.upload.speed=921600 +XIAO_ESP32S3_Plus.menu.UploadSpeed.115200=115200 +XIAO_ESP32S3_Plus.menu.UploadSpeed.115200.upload.speed=115200 +XIAO_ESP32S3_Plus.menu.UploadSpeed.256000.windows=256000 +XIAO_ESP32S3_Plus.menu.UploadSpeed.256000.upload.speed=256000 +XIAO_ESP32S3_Plus.menu.UploadSpeed.230400.windows.upload.speed=256000 +XIAO_ESP32S3_Plus.menu.UploadSpeed.230400=230400 +XIAO_ESP32S3_Plus.menu.UploadSpeed.230400.upload.speed=230400 +XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.linux=460800 +XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.macosx=460800 +XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.upload.speed=460800 +XIAO_ESP32S3_Plus.menu.UploadSpeed.512000.windows=512000 +XIAO_ESP32S3_Plus.menu.UploadSpeed.512000.upload.speed=512000 + +XIAO_ESP32S3_Plus.menu.DebugLevel.none=None +XIAO_ESP32S3_Plus.menu.DebugLevel.none.build.code_debug=0 +XIAO_ESP32S3_Plus.menu.DebugLevel.error=Error +XIAO_ESP32S3_Plus.menu.DebugLevel.error.build.code_debug=1 +XIAO_ESP32S3_Plus.menu.DebugLevel.warn=Warn +XIAO_ESP32S3_Plus.menu.DebugLevel.warn.build.code_debug=2 +XIAO_ESP32S3_Plus.menu.DebugLevel.info=Info +XIAO_ESP32S3_Plus.menu.DebugLevel.info.build.code_debug=3 +XIAO_ESP32S3_Plus.menu.DebugLevel.debug=Debug +XIAO_ESP32S3_Plus.menu.DebugLevel.debug.build.code_debug=4 +XIAO_ESP32S3_Plus.menu.DebugLevel.verbose=Verbose +XIAO_ESP32S3_Plus.menu.DebugLevel.verbose.build.code_debug=5 + +XIAO_ESP32S3_Plus.menu.EraseFlash.none=Disabled +XIAO_ESP32S3_Plus.menu.EraseFlash.none.upload.erase_cmd= +XIAO_ESP32S3_Plus.menu.EraseFlash.all=Enabled +XIAO_ESP32S3_Plus.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +connaxio_espoir.name=Connaxio's Espoir +connaxio_espoir.vid.0=0x10C4 +connaxio_espoir.pid.0=0x8D9A + +connaxio_espoir.bootloader.tool=esptool_py +connaxio_espoir.bootloader.tool.default=esptool_py + +connaxio_espoir.upload.tool=esptool_py +connaxio_espoir.upload.tool.default=esptool_py +connaxio_espoir.upload.tool.network=esp_ota + +connaxio_espoir.upload.maximum_size=1310720 +connaxio_espoir.upload.maximum_data_size=327680 +connaxio_espoir.upload.flags= +connaxio_espoir.upload.extra_flags= + +connaxio_espoir.serial.disableDTR=true +connaxio_espoir.serial.disableRTS=true + +connaxio_espoir.build.tarch=xtensa +connaxio_espoir.build.bootloader_addr=0x1000 +connaxio_espoir.build.target=esp32 +connaxio_espoir.build.mcu=esp32 +connaxio_espoir.build.core=esp32 +connaxio_espoir.build.variant=connaxio_espoir +connaxio_espoir.build.board=connaxio_espoir + +connaxio_espoir.build.f_cpu=240000000L +connaxio_espoir.build.flash_size=4MB +connaxio_espoir.build.flash_freq=80m +connaxio_espoir.build.flash_mode=dio +connaxio_espoir.build.boot=dio +connaxio_espoir.build.partitions=default +connaxio_espoir.build.defines= +connaxio_espoir.build.loop_core= +connaxio_espoir.build.event_core= + +connaxio_espoir.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +connaxio_espoir.menu.PartitionScheme.default.build.partitions=default +connaxio_espoir.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +connaxio_espoir.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +connaxio_espoir.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +connaxio_espoir.menu.PartitionScheme.minimal.build.partitions=minimal +connaxio_espoir.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +connaxio_espoir.menu.PartitionScheme.no_ota.build.partitions=no_ota +connaxio_espoir.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +connaxio_espoir.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +connaxio_espoir.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +connaxio_espoir.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +connaxio_espoir.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +connaxio_espoir.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +connaxio_espoir.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +connaxio_espoir.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +connaxio_espoir.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +connaxio_espoir.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +connaxio_espoir.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +connaxio_espoir.menu.PartitionScheme.huge_app.build.partitions=huge_app +connaxio_espoir.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +connaxio_espoir.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +connaxio_espoir.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +connaxio_espoir.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +connaxio_espoir.menu.PartitionScheme.rainmaker=RainMaker 4MB +connaxio_espoir.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +connaxio_espoir.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +connaxio_espoir.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +connaxio_espoir.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +connaxio_espoir.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +connaxio_espoir.menu.CPUFreq.240=240MHz (WiFi/BT) +connaxio_espoir.menu.CPUFreq.240.build.f_cpu=240000000L +connaxio_espoir.menu.CPUFreq.160=160MHz (WiFi/BT) +connaxio_espoir.menu.CPUFreq.160.build.f_cpu=160000000L +connaxio_espoir.menu.CPUFreq.80=80MHz (WiFi/BT) +connaxio_espoir.menu.CPUFreq.80.build.f_cpu=80000000L +connaxio_espoir.menu.CPUFreq.40=40MHz +connaxio_espoir.menu.CPUFreq.40.build.f_cpu=40000000L +connaxio_espoir.menu.CPUFreq.20=20MHz +connaxio_espoir.menu.CPUFreq.20.build.f_cpu=20000000L +connaxio_espoir.menu.CPUFreq.10=10MHz +connaxio_espoir.menu.CPUFreq.10.build.f_cpu=10000000L + +connaxio_espoir.menu.FlashFreq.80=80MHz +connaxio_espoir.menu.FlashFreq.80.build.flash_freq=80m +connaxio_espoir.menu.FlashFreq.40=40MHz +connaxio_espoir.menu.FlashFreq.40.build.flash_freq=40m + +connaxio_espoir.menu.UploadSpeed.921600=921600 +connaxio_espoir.menu.UploadSpeed.921600.upload.speed=921600 +connaxio_espoir.menu.UploadSpeed.512000.windows=512000 +connaxio_espoir.menu.UploadSpeed.512000.upload.speed=512000 +connaxio_espoir.menu.UploadSpeed.460800.linux=460800 +connaxio_espoir.menu.UploadSpeed.460800.macosx=460800 +connaxio_espoir.menu.UploadSpeed.460800.upload.speed=460800 +connaxio_espoir.menu.UploadSpeed.256000.windows=256000 +connaxio_espoir.menu.UploadSpeed.256000.upload.speed=256000 +connaxio_espoir.menu.UploadSpeed.230400.windows.upload.speed=256000 +connaxio_espoir.menu.UploadSpeed.230400=230400 +connaxio_espoir.menu.UploadSpeed.230400.upload.speed=230400 +connaxio_espoir.menu.UploadSpeed.115200=115200 +connaxio_espoir.menu.UploadSpeed.115200.upload.speed=115200 + +connaxio_espoir.menu.DebugLevel.none=None +connaxio_espoir.menu.DebugLevel.none.build.code_debug=0 +connaxio_espoir.menu.DebugLevel.error=Error +connaxio_espoir.menu.DebugLevel.error.build.code_debug=1 +connaxio_espoir.menu.DebugLevel.warn=Warn +connaxio_espoir.menu.DebugLevel.warn.build.code_debug=2 +connaxio_espoir.menu.DebugLevel.info=Info +connaxio_espoir.menu.DebugLevel.info.build.code_debug=3 +connaxio_espoir.menu.DebugLevel.debug=Debug +connaxio_espoir.menu.DebugLevel.debug.build.code_debug=4 +connaxio_espoir.menu.DebugLevel.verbose=Verbose +connaxio_espoir.menu.DebugLevel.verbose.build.code_debug=5 + +connaxio_espoir.menu.EraseFlash.none=Disabled +connaxio_espoir.menu.EraseFlash.none.upload.erase_cmd= +connaxio_espoir.menu.EraseFlash.all=Enabled +connaxio_espoir.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +aw2eth.name=CNRS AW2ETH + +aw2eth.bootloader.tool=esptool_py +aw2eth.bootloader.tool.default=esptool_py + +aw2eth.upload.tool=esptool_py +aw2eth.upload.tool.default=esptool_py +aw2eth.upload.tool.network=esp_ota + +aw2eth.upload.maximum_size=1310720 +aw2eth.upload.maximum_data_size=327680 +aw2eth.upload.flags= +aw2eth.upload.extra_flags= + +aw2eth.serial.disableDTR=true +aw2eth.serial.disableRTS=true + +aw2eth.build.tarch=xtensa +aw2eth.build.bootloader_addr=0x1000 +aw2eth.build.target=esp32 +aw2eth.build.mcu=esp32 +aw2eth.build.core=esp32 +aw2eth.build.variant=cnrs_aw2eth +aw2eth.build.board=ESP32_PICO + +aw2eth.build.f_cpu=240000000L +aw2eth.build.flash_size=4MB +aw2eth.build.flash_freq=80m +aw2eth.build.flash_mode=dio +aw2eth.build.boot=dio +aw2eth.build.partitions=default +aw2eth.build.defines= + +aw2eth.menu.PartitionScheme.default=Default +aw2eth.menu.PartitionScheme.default.build.partitions=default +aw2eth.menu.PartitionScheme.no_ota=No OTA (Large APP) +aw2eth.menu.PartitionScheme.no_ota.build.partitions=no_ota +aw2eth.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +aw2eth.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +aw2eth.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +aw2eth.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +aw2eth.menu.UploadSpeed.921600=921600 +aw2eth.menu.UploadSpeed.921600.upload.speed=921600 +aw2eth.menu.UploadSpeed.115200=115200 +aw2eth.menu.UploadSpeed.115200.upload.speed=115200 +aw2eth.menu.UploadSpeed.256000.windows=256000 +aw2eth.menu.UploadSpeed.256000.upload.speed=256000 +aw2eth.menu.UploadSpeed.230400.windows.upload.speed=256000 +aw2eth.menu.UploadSpeed.230400=230400 +aw2eth.menu.UploadSpeed.230400.upload.speed=230400 +aw2eth.menu.UploadSpeed.460800.linux=460800 +aw2eth.menu.UploadSpeed.460800.macosx=460800 +aw2eth.menu.UploadSpeed.460800.upload.speed=460800 +aw2eth.menu.UploadSpeed.512000.windows=512000 +aw2eth.menu.UploadSpeed.512000.upload.speed=512000 + +aw2eth.menu.DebugLevel.none=None +aw2eth.menu.DebugLevel.none.build.code_debug=0 +aw2eth.menu.DebugLevel.error=Error +aw2eth.menu.DebugLevel.error.build.code_debug=1 +aw2eth.menu.DebugLevel.warn=Warn +aw2eth.menu.DebugLevel.warn.build.code_debug=2 +aw2eth.menu.DebugLevel.info=Info +aw2eth.menu.DebugLevel.info.build.code_debug=3 +aw2eth.menu.DebugLevel.debug=Debug +aw2eth.menu.DebugLevel.debug.build.code_debug=4 +aw2eth.menu.DebugLevel.verbose=Verbose +aw2eth.menu.DebugLevel.verbose.build.code_debug=5 + +aw2eth.menu.EraseFlash.none=Disabled +aw2eth.menu.EraseFlash.none.upload.erase_cmd= +aw2eth.menu.EraseFlash.all=Enabled +aw2eth.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +department_of_alchemy_minimain_esp32s2.name=Department of Alchemy MiniMain ESP32-S2 +department_of_alchemy_minimain_esp32s2.vid.0=0x303A +department_of_alchemy_minimain_esp32s2.pid.0=0x80FF + +department_of_alchemy_minimain_esp32s2.bootloader.tool=esptool_py +department_of_alchemy_minimain_esp32s2.bootloader.tool.default=esptool_py + +department_of_alchemy_minimain_esp32s2.upload.tool=esptool_py +department_of_alchemy_minimain_esp32s2.upload.tool.default=esptool_py +department_of_alchemy_minimain_esp32s2.upload.tool.network=esp_ota + +department_of_alchemy_minimain_esp32s2.upload.maximum_size=1310720 +department_of_alchemy_minimain_esp32s2.upload.maximum_data_size=327680 +department_of_alchemy_minimain_esp32s2.upload.flags= +department_of_alchemy_minimain_esp32s2.upload.extra_flags= +department_of_alchemy_minimain_esp32s2.upload.use_1200bps_touch=true +department_of_alchemy_minimain_esp32s2.upload.wait_for_upload_port=true + +department_of_alchemy_minimain_esp32s2.serial.disableDTR=false +department_of_alchemy_minimain_esp32s2.serial.disableRTS=false + +department_of_alchemy_minimain_esp32s2.build.tarch=xtensa +department_of_alchemy_minimain_esp32s2.build.bootloader_addr=0x1000 +department_of_alchemy_minimain_esp32s2.build.target=esp32s2 +department_of_alchemy_minimain_esp32s2.build.mcu=esp32s2 +department_of_alchemy_minimain_esp32s2.build.core=esp32 +department_of_alchemy_minimain_esp32s2.build.variant=department_of_alchemy_minimain_esp32s2 +department_of_alchemy_minimain_esp32s2.build.board=DEPARTMENT_OF_ALCHEMY_MINIMAIN_ESP32S2 + +department_of_alchemy_minimain_esp32s2.build.cdc_on_boot=1 +department_of_alchemy_minimain_esp32s2.build.msc_on_boot=0 +department_of_alchemy_minimain_esp32s2.build.dfu_on_boot=0 +department_of_alchemy_minimain_esp32s2.build.f_cpu=240000000L +department_of_alchemy_minimain_esp32s2.build.flash_size=4MB +department_of_alchemy_minimain_esp32s2.build.flash_freq=80m +department_of_alchemy_minimain_esp32s2.build.flash_mode=qio +department_of_alchemy_minimain_esp32s2.build.boot=qio +department_of_alchemy_minimain_esp32s2.build.partitions=default +department_of_alchemy_minimain_esp32s2.build.defines= + +department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.cdc=Enabled +department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.default=Disabled +department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.default=Disabled +department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 +department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.msc=Enabled +department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.default=Disabled +department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.dfu=Enabled +department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc=Internal USB +department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +department_of_alchemy_minimain_esp32s2.menu.UploadMode.default=UART0 +department_of_alchemy_minimain_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +department_of_alchemy_minimain_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +department_of_alchemy_minimain_esp32s2.menu.PSRAM.enabled=Enabled +department_of_alchemy_minimain_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +department_of_alchemy_minimain_esp32s2.menu.PSRAM.disabled=Disabled +department_of_alchemy_minimain_esp32s2.menu.PSRAM.disabled.build.defines= + +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FFAT) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-4MB-tinyuf2 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.default.build.partitions=default +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.40=40MHz +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.20=20MHz +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.10=10MHz +department_of_alchemy_minimain_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio=QIO +department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio.build.boot=qio +department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio=DIO +department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio.build.boot=dio + +department_of_alchemy_minimain_esp32s2.menu.FlashFreq.80=80MHz +department_of_alchemy_minimain_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +department_of_alchemy_minimain_esp32s2.menu.FlashFreq.40=40MHz +department_of_alchemy_minimain_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +department_of_alchemy_minimain_esp32s2.menu.FlashSize.4M=4MB (32Mb) +department_of_alchemy_minimain_esp32s2.menu.FlashSize.4M.build.flash_size=4MB +department_of_alchemy_minimain_esp32s2.menu.FlashSize.8M=8MB (64Mb) +department_of_alchemy_minimain_esp32s2.menu.FlashSize.8M.build.flash_size=8MB +department_of_alchemy_minimain_esp32s2.menu.FlashSize.2M=2MB (16Mb) +department_of_alchemy_minimain_esp32s2.menu.FlashSize.2M.build.flash_size=2MB +department_of_alchemy_minimain_esp32s2.menu.FlashSize.16M=16MB (128Mb) +department_of_alchemy_minimain_esp32s2.menu.FlashSize.16M.build.flash_size=16MB + +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.921600=921600 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.115200=115200 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.256000.windows=256000 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400=230400 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.linux=460800 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.macosx=460800 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.512000.windows=512000 +department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.none=None +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.none.build.code_debug=0 +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.error=Error +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.error.build.code_debug=1 +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.warn=Warn +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.info=Info +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.info.build.code_debug=3 +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.debug=Debug +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.verbose=Verbose +department_of_alchemy_minimain_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +department_of_alchemy_minimain_esp32s2.menu.EraseFlash.none=Disabled +department_of_alchemy_minimain_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +department_of_alchemy_minimain_esp32s2.menu.EraseFlash.all=Enabled +department_of_alchemy_minimain_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +Bee_Data_Logger.name=Bee Data Logger +Bee_Data_Logger.vid.0=0x303a +Bee_Data_Logger.pid.0=0x815C +Bee_Data_Logger.upload_port.0.vid=0x303a +Bee_Data_Logger.upload_port.0.pid=0x815C + +Bee_Data_Logger.bootloader.tool=esptool_py +Bee_Data_Logger.bootloader.tool.default=esptool_py + +Bee_Data_Logger.upload.tool=esptool_py +Bee_Data_Logger.upload.tool.default=esptool_py +Bee_Data_Logger.upload.tool.network=esp_ota + +Bee_Data_Logger.upload.maximum_size=1310720 +Bee_Data_Logger.upload.maximum_data_size=327680 +Bee_Data_Logger.upload.flags= +Bee_Data_Logger.upload.extra_flags= +Bee_Data_Logger.upload.use_1200bps_touch=true +Bee_Data_Logger.upload.wait_for_upload_port=true +Bee_Data_Logger.upload.speed=921600 + +Bee_Data_Logger.serial.disableDTR=false +Bee_Data_Logger.serial.disableRTS=false + +Bee_Data_Logger.build.tarch=xtensa +Bee_Data_Logger.build.bootloader_addr=0x0 +Bee_Data_Logger.build.target=esp32s3 +Bee_Data_Logger.build.mcu=esp32s3 +Bee_Data_Logger.build.core=esp32 +Bee_Data_Logger.build.variant=Bee_Data_Logger +Bee_Data_Logger.build.board=BEE_DATA_LOGGER + +Bee_Data_Logger.build.cdc_on_boot=1 +Bee_Data_Logger.build.msc_on_boot=1 +Bee_Data_Logger.build.dfu_on_boot=1 +Bee_Data_Logger.build.f_cpu=240000000L +Bee_Data_Logger.build.flash_size=8MB +Bee_Data_Logger.build.flash_freq=80m +Bee_Data_Logger.build.flash_mode=dio +Bee_Data_Logger.build.loop_core=-DARDUINO_RUNNING_CORE=1 +Bee_Data_Logger.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +Bee_Data_Logger.build.boot=qio +Bee_Data_Logger.build.partitions=default +Bee_Data_Logger.build.defines= + +Bee_Data_Logger.menu.CDCOnBoot.default=Enabled +Bee_Data_Logger.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Bee_Data_Logger.menu.CDCOnBoot.dis_cdc=Disabled +Bee_Data_Logger.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +Bee_Data_Logger.menu.MSCOnBoot.default=Disabled +Bee_Data_Logger.menu.MSCOnBoot.default.build.msc_on_boot=0 +Bee_Data_Logger.menu.MSCOnBoot.msc=Enabled +Bee_Data_Logger.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +Bee_Data_Logger.menu.DFUOnBoot.default=Disabled +Bee_Data_Logger.menu.DFUOnBoot.default.build.dfu_on_boot=0 +Bee_Data_Logger.menu.DFUOnBoot.dfu=Enabled +Bee_Data_Logger.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +Bee_Data_Logger.menu.USBMode.default=USB-OTG +Bee_Data_Logger.menu.USBMode.default.build.usb_mode=0 +Bee_Data_Logger.menu.USBMode.default.upload.use_1200bps_touch=true +Bee_Data_Logger.menu.USBMode.default.upload.wait_for_upload_port=true +Bee_Data_Logger.menu.USBMode.hwcdc=Hardware CDC and JTAG +Bee_Data_Logger.menu.USBMode.hwcdc.build.usb_mode=1 +Bee_Data_Logger.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +Bee_Data_Logger.menu.USBMode.hwcdc.upload.wait_for_upload_port=false + +Bee_Data_Logger.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Bee_Data_Logger.menu.PartitionScheme.default.build.partitions=default +Bee_Data_Logger.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Bee_Data_Logger.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Bee_Data_Logger.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Bee_Data_Logger.menu.PartitionScheme.no_ota.build.partitions=no_ota +Bee_Data_Logger.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Bee_Data_Logger.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Bee_Data_Logger.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Bee_Data_Logger.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Bee_Data_Logger.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Bee_Data_Logger.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Bee_Data_Logger.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Bee_Data_Logger.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Bee_Data_Logger.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Bee_Data_Logger.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Bee_Data_Logger.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Bee_Data_Logger.menu.PartitionScheme.huge_app.build.partitions=huge_app +Bee_Data_Logger.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +Bee_Data_Logger.menu.DebugLevel.none=None +Bee_Data_Logger.menu.DebugLevel.none.build.code_debug=0 +Bee_Data_Logger.menu.DebugLevel.error=Error +Bee_Data_Logger.menu.DebugLevel.error.build.code_debug=1 +Bee_Data_Logger.menu.DebugLevel.warn=Warn +Bee_Data_Logger.menu.DebugLevel.warn.build.code_debug=2 +Bee_Data_Logger.menu.DebugLevel.info=Info +Bee_Data_Logger.menu.DebugLevel.info.build.code_debug=3 +Bee_Data_Logger.menu.DebugLevel.debug=Debug +Bee_Data_Logger.menu.DebugLevel.debug.build.code_debug=4 +Bee_Data_Logger.menu.DebugLevel.verbose=Verbose +Bee_Data_Logger.menu.DebugLevel.verbose.build.code_debug=5 + +Bee_Data_Logger.menu.EraseFlash.none=Disabled +Bee_Data_Logger.menu.EraseFlash.none.upload.erase_cmd= +Bee_Data_Logger.menu.EraseFlash.all=Enabled +Bee_Data_Logger.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################ + +Bee_Motion_S3.name=Bee Motion S3 +Bee_Motion_S3.vid.0=0x303a +Bee_Motion_S3.pid.0=0x8113 +Bee_Motion_S3.upload_port.0.vid=0x303a +Bee_Motion_S3.upload_port.0.pid=0x8113 + +Bee_Motion_S3.bootloader.tool=esptool_py +Bee_Motion_S3.bootloader.tool.default=esptool_py + +Bee_Motion_S3.upload.tool=esptool_py +Bee_Motion_S3.upload.tool.default=esptool_py +Bee_Motion_S3.upload.tool.network=esp_ota + +Bee_Motion_S3.upload.maximum_size=1310720 +Bee_Motion_S3.upload.maximum_data_size=327680 +Bee_Motion_S3.upload.flags= +Bee_Motion_S3.upload.extra_flags= +Bee_Motion_S3.upload.use_1200bps_touch=true +Bee_Motion_S3.upload.wait_for_upload_port=true +Bee_Motion_S3.upload.speed=921600 + +Bee_Motion_S3.serial.disableDTR=false +Bee_Motion_S3.serial.disableRTS=false + +Bee_Motion_S3.build.tarch=xtensa +Bee_Motion_S3.build.bootloader_addr=0x0 +Bee_Motion_S3.build.target=esp32s3 +Bee_Motion_S3.build.mcu=esp32s3 +Bee_Motion_S3.build.core=esp32 +Bee_Motion_S3.build.variant=Bee_Motion_S3 +Bee_Motion_S3.build.board=BeeMotionS3 + +Bee_Motion_S3.build.cdc_on_boot=1 +Bee_Motion_S3.build.msc_on_boot=1 +Bee_Motion_S3.build.dfu_on_boot=1 +Bee_Motion_S3.build.f_cpu=240000000L +Bee_Motion_S3.build.flash_size=8MB +Bee_Motion_S3.build.flash_freq=80m +Bee_Motion_S3.build.flash_mode=dio +Bee_Motion_S3.build.partitions=default_8MB +Bee_Motion_S3.build.defines= +Bee_Motion_S3.build.loop_core=-DARDUINO_RUNNING_CORE=1 +Bee_Motion_S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +Bee_Motion_S3.build.boot=qio +Bee_Motion_S3.build.partitions=default +Bee_Motion_S3.build.defines= + +Bee_Motion_S3.menu.CDCOnBoot.default=Enabled +Bee_Motion_S3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Bee_Motion_S3.menu.CDCOnBoot.dis_cdc=Disabled +Bee_Motion_S3.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +Bee_Motion_S3.menu.MSCOnBoot.default=Disabled +Bee_Motion_S3.menu.MSCOnBoot.default.build.msc_on_boot=0 +Bee_Motion_S3.menu.MSCOnBoot.msc=Enabled +Bee_Motion_S3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +Bee_Motion_S3.menu.DFUOnBoot.default=Disabled +Bee_Motion_S3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +Bee_Motion_S3.menu.DFUOnBoot.dfu=Enabled +Bee_Motion_S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +Bee_Motion_S3.menu.USBMode.default=USB-OTG +Bee_Motion_S3.menu.USBMode.default.build.usb_mode=0 +Bee_Motion_S3.menu.USBMode.default.upload.use_1200bps_touch=true +Bee_Motion_S3.menu.USBMode.default.upload.wait_for_upload_port=true +Bee_Motion_S3.menu.USBMode.hwcdc=Hardware CDC and JTAG +Bee_Motion_S3.menu.USBMode.hwcdc.build.usb_mode=1 +Bee_Motion_S3.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +Bee_Motion_S3.menu.USBMode.hwcdc.upload.wait_for_upload_port=false + +Bee_Motion_S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Bee_Motion_S3.menu.PartitionScheme.default.build.partitions=default +Bee_Motion_S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Bee_Motion_S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Bee_Motion_S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Bee_Motion_S3.menu.PartitionScheme.no_ota.build.partitions=no_ota +Bee_Motion_S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Bee_Motion_S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Bee_Motion_S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Bee_Motion_S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Bee_Motion_S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Bee_Motion_S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Bee_Motion_S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Bee_Motion_S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Bee_Motion_S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Bee_Motion_S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Bee_Motion_S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Bee_Motion_S3.menu.PartitionScheme.huge_app.build.partitions=huge_app +Bee_Motion_S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +Bee_Motion_S3.menu.DebugLevel.none=None +Bee_Motion_S3.menu.DebugLevel.none.build.code_debug=0 +Bee_Motion_S3.menu.DebugLevel.error=Error +Bee_Motion_S3.menu.DebugLevel.error.build.code_debug=1 +Bee_Motion_S3.menu.DebugLevel.warn=Warn +Bee_Motion_S3.menu.DebugLevel.warn.build.code_debug=2 +Bee_Motion_S3.menu.DebugLevel.info=Info +Bee_Motion_S3.menu.DebugLevel.info.build.code_debug=3 +Bee_Motion_S3.menu.DebugLevel.debug=Debug +Bee_Motion_S3.menu.DebugLevel.debug.build.code_debug=4 +Bee_Motion_S3.menu.DebugLevel.verbose=Verbose +Bee_Motion_S3.menu.DebugLevel.verbose.build.code_debug=5 + +Bee_Motion_S3.menu.EraseFlash.none=Disabled +Bee_Motion_S3.menu.EraseFlash.none.upload.erase_cmd= +Bee_Motion_S3.menu.EraseFlash.all=Enabled +Bee_Motion_S3.menu.EraseFlash.all.upload.erase_cmd=-e + +######################################################################## + +Bee_Motion.name=Bee Motion +Bee_Motion.vid.0=0x303a +Bee_Motion.pid.0=0x810D +Bee_Motion.vid.upload_port.0.vid=0x303a +Bee_Motion.pid.upload_port.0.pid=0x810D + +Bee_Motion.bootloader.tool=esptool_py +Bee_Motion.bootloader.tool.default=esptool_py + +Bee_Motion.upload.tool=esptool_py +Bee_Motion.upload.tool.default=esptool_py +Bee_Motion.upload.tool.network=esp_ota + +Bee_Motion.upload.maximum_size=1310720 +Bee_Motion.upload.maximum_data_size=327680 +Bee_Motion.upload.flags= +Bee_Motion.upload.extra_flags= +Bee_Motion.upload.use_1200bps_touch=true +Bee_Motion.upload.wait_for_upload_port=true +Bee_Motion.upload.speed=921600 + +Bee_Motion.serial.disableDTR=false +Bee_Motion.serial.disableRTS=false + +Bee_Motion.build.tarch=xtensa +Bee_Motion.build.bootloader_addr=0x1000 +Bee_Motion.build.target=esp32s2 +Bee_Motion.build.mcu=esp32s2 +Bee_Motion.build.core=esp32 +Bee_Motion.build.variant=Bee_Motion +Bee_Motion.build.board=Bee_Motion + +Bee_Motion.build.cdc_on_boot=1 +Bee_Motion.build.msc_on_boot=1 +Bee_Motion.build.dfu_on_boot=1 +Bee_Motion.build.f_cpu=240000000L +Bee_Motion.build.flash_size=4MB +Bee_Motion.build.flash_freq=80m +Bee_Motion.build.flash_mode=dio +Bee_Motion.build.boot=qio +Bee_Motion.build.partitions=default +Bee_Motion.build.defines= + +Bee_Motion.menu.CDCOnBoot.default=Enabled +Bee_Motion.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Bee_Motion.menu.CDCOnBoot.dis_cdc=Disabled +Bee_Motion.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +Bee_Motion.menu.MSCOnBoot.default=Disabled +Bee_Motion.menu.MSCOnBoot.default.build.msc_on_boot=0 +Bee_Motion.menu.MSCOnBoot.msc=Enabled +Bee_Motion.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +Bee_Motion.menu.DFUOnBoot.default=Disabled +Bee_Motion.menu.DFUOnBoot.default.build.dfu_on_boot=0 +Bee_Motion.menu.DFUOnBoot.dfu=Enabled +Bee_Motion.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +Bee_Motion.menu.USBMode.default=USB-OTG +Bee_Motion.menu.USBMode.default.build.usb_mode=0 +Bee_Motion.menu.USBMode.default.upload.use_1200bps_touch=true +Bee_Motion.menu.USBMode.default.upload.wait_for_upload_port=true +Bee_Motion.menu.USBMode.hwcdc=Hardware CDC and JTAG +Bee_Motion.menu.USBMode.hwcdc.build.usb_mode=1 +Bee_Motion.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +Bee_Motion.menu.USBMode.hwcdc.upload.wait_for_upload_port=false + +Bee_Motion.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Bee_Motion.menu.PartitionScheme.default.build.partitions=default +Bee_Motion.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Bee_Motion.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Bee_Motion.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Bee_Motion.menu.PartitionScheme.no_ota.build.partitions=no_ota +Bee_Motion.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Bee_Motion.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Bee_Motion.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Bee_Motion.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Bee_Motion.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Bee_Motion.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Bee_Motion.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Bee_Motion.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Bee_Motion.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Bee_Motion.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Bee_Motion.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Bee_Motion.menu.PartitionScheme.huge_app.build.partitions=huge_app +Bee_Motion.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +Bee_Motion.menu.DebugLevel.none=None +Bee_Motion.menu.DebugLevel.none.build.code_debug=0 +Bee_Motion.menu.DebugLevel.error=Error +Bee_Motion.menu.DebugLevel.error.build.code_debug=1 +Bee_Motion.menu.DebugLevel.warn=Warn +Bee_Motion.menu.DebugLevel.warn.build.code_debug=2 +Bee_Motion.menu.DebugLevel.info=Info +Bee_Motion.menu.DebugLevel.info.build.code_debug=3 +Bee_Motion.menu.DebugLevel.debug=Debug +Bee_Motion.menu.DebugLevel.debug.build.code_debug=4 +Bee_Motion.menu.DebugLevel.verbose=Verbose +Bee_Motion.menu.DebugLevel.verbose.build.code_debug=5 + +Bee_Motion.menu.EraseFlash.none=Disabled +Bee_Motion.menu.EraseFlash.none.upload.erase_cmd= +Bee_Motion.menu.EraseFlash.all=Enabled +Bee_Motion.menu.EraseFlash.all.upload.erase_cmd=-e + +##################################################################### + +Bee_Motion_Mini.name=Bee Motion Mini + +Bee_Motion_Mini.bootloader.tool=esptool_py +Bee_Motion_Mini.bootloader.tool.default=esptool_py + +Bee_Motion_Mini.upload.tool=esptool_py +Bee_Motion_Mini.upload.tool.default=esptool_py +Bee_Motion_Mini.upload.tool.network=esp_ota + +Bee_Motion_Mini.upload.maximum_size=1310720 +Bee_Motion_Mini.upload.maximum_data_size=327680 +Bee_Motion_Mini.upload.flags= +Bee_Motion_Mini.upload.extra_flags= +Bee_Motion_Mini.upload.use_1200bps_touch=false +Bee_Motion_Mini.upload.wait_for_upload_port=false + +Bee_Motion_Mini.serial.disableDTR=true +Bee_Motion_Mini.serial.disableRTS=true + +Bee_Motion_Mini.build.tarch=riscv32 +Bee_Motion_Mini.build.target=esp +Bee_Motion_Mini.build.mcu=esp32c3 +Bee_Motion_Mini.build.core=esp32 +Bee_Motion_Mini.build.variant=Bee_Motion_Mini +Bee_Motion_Mini.build.board=Bee_Motion_Mini +Bee_Motion_Mini.build.bootloader_addr=0x0 + +Bee_Motion_Mini.build.cdc_on_boot=1 +Bee_Motion_Mini.build.f_cpu=160000000L +Bee_Motion_Mini.build.flash_size=4MB +Bee_Motion_Mini.build.flash_freq=80m +Bee_Motion_Mini.build.flash_mode=dio +Bee_Motion_Mini.build.boot=qio +Bee_Motion_Mini.build.partitions=default +Bee_Motion_Mini.build.defines= + +Bee_Motion_Mini.menu.CDCOnBoot.default=Enabled +Bee_Motion_Mini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Bee_Motion_Mini.menu.CDCOnBoot.dis_cdc=Disabled +Bee_Motion_Mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +Bee_Motion_Mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Bee_Motion_Mini.menu.PartitionScheme.default.build.partitions=default +Bee_Motion_Mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Bee_Motion_Mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Bee_Motion_Mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Bee_Motion_Mini.menu.PartitionScheme.no_ota.build.partitions=no_ota +Bee_Motion_Mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Bee_Motion_Mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Bee_Motion_Mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Bee_Motion_Mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Bee_Motion_Mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Bee_Motion_Mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Bee_Motion_Mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Bee_Motion_Mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Bee_Motion_Mini.menu.PartitionScheme.huge_app.build.partitions=huge_app +Bee_Motion_Mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +Bee_Motion_Mini.menu.CPUFreq.160=160MHz (WiFi) +Bee_Motion_Mini.menu.CPUFreq.160.build.f_cpu=160000000L +Bee_Motion_Mini.menu.CPUFreq.80=80MHz (WiFi) +Bee_Motion_Mini.menu.CPUFreq.80.build.f_cpu=80000000L +Bee_Motion_Mini.menu.CPUFreq.40=40MHz +Bee_Motion_Mini.menu.CPUFreq.40.build.f_cpu=40000000L +Bee_Motion_Mini.menu.CPUFreq.20=20MHz +Bee_Motion_Mini.menu.CPUFreq.20.build.f_cpu=20000000L +Bee_Motion_Mini.menu.CPUFreq.10=10MHz +Bee_Motion_Mini.menu.CPUFreq.10.build.f_cpu=10000000L + +Bee_Motion_Mini.menu.FlashFreq.80=80MHz +Bee_Motion_Mini.menu.FlashFreq.80.build.flash_freq=80m +Bee_Motion_Mini.menu.FlashFreq.40=40MHz +Bee_Motion_Mini.menu.FlashFreq.40.build.flash_freq=40m + +Bee_Motion_Mini.menu.UploadSpeed.921600=921600 +Bee_Motion_Mini.menu.UploadSpeed.921600.upload.speed=921600 +Bee_Motion_Mini.menu.UploadSpeed.115200=115200 +Bee_Motion_Mini.menu.UploadSpeed.115200.upload.speed=115200 +Bee_Motion_Mini.menu.UploadSpeed.256000.windows=256000 +Bee_Motion_Mini.menu.UploadSpeed.256000.upload.speed=256000 +Bee_Motion_Mini.menu.UploadSpeed.230400.windows.upload.speed=256000 +Bee_Motion_Mini.menu.UploadSpeed.230400=230400 +Bee_Motion_Mini.menu.UploadSpeed.230400.upload.speed=230400 +Bee_Motion_Mini.menu.UploadSpeed.460800.linux=460800 +Bee_Motion_Mini.menu.UploadSpeed.460800.macosx=460800 +Bee_Motion_Mini.menu.UploadSpeed.460800.upload.speed=460800 +Bee_Motion_Mini.menu.UploadSpeed.512000.windows=512000 +Bee_Motion_Mini.menu.UploadSpeed.512000.upload.speed=512000 + +Bee_Motion_Mini.menu.DebugLevel.none=None +Bee_Motion_Mini.menu.DebugLevel.none.build.code_debug=0 +Bee_Motion_Mini.menu.DebugLevel.error=Error +Bee_Motion_Mini.menu.DebugLevel.error.build.code_debug=1 +Bee_Motion_Mini.menu.DebugLevel.warn=Warn +Bee_Motion_Mini.menu.DebugLevel.warn.build.code_debug=2 +Bee_Motion_Mini.menu.DebugLevel.info=Info +Bee_Motion_Mini.menu.DebugLevel.info.build.code_debug=3 +Bee_Motion_Mini.menu.DebugLevel.debug=Debug +Bee_Motion_Mini.menu.DebugLevel.debug.build.code_debug=4 +Bee_Motion_Mini.menu.DebugLevel.verbose=Verbose +Bee_Motion_Mini.menu.DebugLevel.verbose.build.code_debug=5 + +Bee_Motion_Mini.menu.EraseFlash.none=Disabled +Bee_Motion_Mini.menu.EraseFlash.none.upload.erase_cmd= +Bee_Motion_Mini.menu.EraseFlash.all=Enabled +Bee_Motion_Mini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################### + +Bee_S3.name=Bee S3 +Bee_S3.vid.0=0x303a +Bee_S3.pid.0=0x8110 +Bee_S3.vid.upload_port.0.vid=0x303a +Bee_S3.pid.upload_port.0.pid=0x8110 + +Bee_S3.bootloader.tool=esptool_py +Bee_S3.bootloader.tool.default=esptool_py + +Bee_S3.upload.tool=esptool_py +Bee_S3.upload.tool.default=esptool_py +Bee_S3.upload.tool.network=esp_ota + +Bee_S3.upload.maximum_size=1310720 +Bee_S3.upload.maximum_data_size=327680 +Bee_S3.upload.flags= +Bee_S3.upload.extra_flags= +Bee_S3.upload.use_1200bps_touch=false +Bee_S3.upload.wait_for_upload_port=false + +Bee_S3.serial.disableDTR=false +Bee_S3.serial.disableRTS=false + +Bee_S3.build.tarch=xtensa +Bee_S3.build.bootloader_addr=0x0 +Bee_S3.build.target=esp32s3 +Bee_S3.build.mcu=esp32s3 +Bee_S3.build.core=esp32 +Bee_S3.build.variant=Bee_S3 +Bee_S3.build.board=Bee_S3 + +Bee_S3.build.usb_mode=1 +Bee_S3.build.cdc_on_boot=1 +Bee_S3.build.msc_on_boot=0 +Bee_S3.build.dfu_on_boot=0 +Bee_S3.build.f_cpu=240000000L +Bee_S3.build.flash_size=8MB +Bee_S3.build.flash_freq=80m +Bee_S3.build.flash_mode=dio +Bee_S3.build.boot=qio +Bee_S3.build.partitions=default_8MB +Bee_S3.build.defines= +Bee_S3.build.loop_core=-DARDUINO_RUNNING_CORE=1 +Bee_S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +Bee_S3.menu.USBMode.default=USB-OTG +Bee_S3.menu.USBMode.default.build.usb_mode=0 +Bee_S3.menu.USBMode.default.upload.use_1200bps_touch=true +Bee_S3.menu.USBMode.default.upload.wait_for_upload_port=true +Bee_S3.menu.USBMode.hwcdc=Hardware CDC and JTAG +Bee_S3.menu.USBMode.hwcdc.build.usb_mode=1 +Bee_S3.menu.USBMode.hwcdc.upload.use_1200bps_touch=false +Bee_S3.menu.USBMode.hwcdc.upload.wait_for_upload_port=false + +Bee_S3.menu.CDCOnBoot.cdc=Enabled +Bee_S3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +Bee_S3.menu.CDCOnBoot.default=Disabled +Bee_S3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +Bee_S3.menu.MSCOnBoot.default=Disabled +Bee_S3.menu.MSCOnBoot.default.build.msc_on_boot=0 +Bee_S3.menu.MSCOnBoot.msc=Enabled +Bee_S3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +Bee_S3.menu.DFUOnBoot.default=Disabled +Bee_S3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +Bee_S3.menu.DFUOnBoot.dfu=Enabled +Bee_S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +Bee_S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Bee_S3.menu.PartitionScheme.default.build.partitions=default +Bee_S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Bee_S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Bee_S3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +Bee_S3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +Bee_S3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +Bee_S3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +Bee_S3.menu.PartitionScheme.minimal.build.partitions=minimal +Bee_S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Bee_S3.menu.PartitionScheme.no_ota.build.partitions=no_ota +Bee_S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Bee_S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Bee_S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Bee_S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Bee_S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Bee_S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Bee_S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Bee_S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Bee_S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Bee_S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Bee_S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Bee_S3.menu.PartitionScheme.huge_app.build.partitions=huge_app +Bee_S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Bee_S3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +Bee_S3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +Bee_S3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +Bee_S3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +Bee_S3.menu.PartitionScheme.fatflash.build.partitions=ffat +Bee_S3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +Bee_S3.menu.CPUFreq.240=240MHz (WiFi) +Bee_S3.menu.CPUFreq.240.build.f_cpu=240000000L +Bee_S3.menu.CPUFreq.160=160MHz (WiFi) +Bee_S3.menu.CPUFreq.160.build.f_cpu=160000000L +Bee_S3.menu.CPUFreq.80=80MHz (WiFi) +Bee_S3.menu.CPUFreq.80.build.f_cpu=80000000L +Bee_S3.menu.CPUFreq.40=40MHz +Bee_S3.menu.CPUFreq.40.build.f_cpu=40000000L +Bee_S3.menu.CPUFreq.20=20MHz +Bee_S3.menu.CPUFreq.20.build.f_cpu=20000000L +Bee_S3.menu.CPUFreq.10=10MHz +Bee_S3.menu.CPUFreq.10.build.f_cpu=10000000L + +Bee_S3.menu.FlashFreq.80=80MHz +Bee_S3.menu.FlashFreq.80.build.flash_freq=80m +Bee_S3.menu.FlashFreq.40=40MHz +Bee_S3.menu.FlashFreq.40.build.flash_freq=40m + +Bee_S3.menu.UploadSpeed.921600=921600 +Bee_S3.menu.UploadSpeed.921600.upload.speed=921600 +Bee_S3.menu.UploadSpeed.115200=115200 +Bee_S3.menu.UploadSpeed.115200.upload.speed=115200 +Bee_S3.menu.UploadSpeed.256000.windows=256000 +Bee_S3.menu.UploadSpeed.256000.upload.speed=256000 +Bee_S3.menu.UploadSpeed.230400.windows.upload.speed=256000 +Bee_S3.menu.UploadSpeed.230400=230400 +Bee_S3.menu.UploadSpeed.230400.upload.speed=230400 +Bee_S3.menu.UploadSpeed.460800.linux=460800 +Bee_S3.menu.UploadSpeed.460800.macosx=460800 +Bee_S3.menu.UploadSpeed.460800.upload.speed=460800 +Bee_S3.menu.UploadSpeed.512000.windows=512000 +Bee_S3.menu.UploadSpeed.512000.upload.speed=512000 + +Bee_S3.menu.DebugLevel.none=None +Bee_S3.menu.DebugLevel.none.build.code_debug=0 +Bee_S3.menu.DebugLevel.error=Error +Bee_S3.menu.DebugLevel.error.build.code_debug=1 +Bee_S3.menu.DebugLevel.warn=Warn +Bee_S3.menu.DebugLevel.warn.build.code_debug=2 +Bee_S3.menu.DebugLevel.info=Info +Bee_S3.menu.DebugLevel.info.build.code_debug=3 +Bee_S3.menu.DebugLevel.debug=Debug +Bee_S3.menu.DebugLevel.debug.build.code_debug=4 +Bee_S3.menu.DebugLevel.verbose=Verbose +Bee_S3.menu.DebugLevel.verbose.build.code_debug=5 + +Bee_S3.menu.EraseFlash.none=Disabled +Bee_S3.menu.EraseFlash.none.upload.erase_cmd= +Bee_S3.menu.EraseFlash.all=Enabled +Bee_S3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +unphone7.name=unPhone 7 + +unphone7.bootloader.tool=esptool_py +unphone7.bootloader.tool.default=esptool_py + +unphone7.upload.tool=esptool_py +unphone7.upload.tool.default=esptool_py +unphone7.upload.tool.network=esp_ota + +unphone7.upload.maximum_size=1310720 +unphone7.upload.maximum_data_size=327680 +unphone7.upload.flags= +unphone7.upload.extra_flags= + +unphone7.serial.disableDTR=true +unphone7.serial.disableRTS=true + +unphone7.build.tarch=xtensa +unphone7.build.bootloader_addr=0x1000 +unphone7.build.target=esp32 +unphone7.build.mcu=esp32 +unphone7.build.core=esp32 +unphone7.build.variant=feather_esp32 +unphone7.build.board=FEATHER_ESP32 + +unphone7.build.f_cpu=240000000L +unphone7.build.flash_mode=dio +unphone7.build.flash_size=4MB +unphone7.build.boot=dio +unphone7.build.partitions=default +unphone7.build.defines=-DUNPHONE_SPIN=7 + +unphone7.menu.FlashFreq.80=80MHz +unphone7.menu.FlashFreq.80.build.flash_freq=80m +unphone7.menu.FlashFreq.40=40MHz +unphone7.menu.FlashFreq.40.build.flash_freq=40m + +unphone7.menu.UploadSpeed.921600=921600 +unphone7.menu.UploadSpeed.921600.upload.speed=921600 +unphone7.menu.UploadSpeed.115200=115200 +unphone7.menu.UploadSpeed.115200.upload.speed=115200 +unphone7.menu.UploadSpeed.256000.windows=256000 +unphone7.menu.UploadSpeed.256000.upload.speed=256000 +unphone7.menu.UploadSpeed.230400.windows.upload.speed=256000 +unphone7.menu.UploadSpeed.230400=230400 +unphone7.menu.UploadSpeed.230400.upload.speed=230400 +unphone7.menu.UploadSpeed.460800.linux=460800 +unphone7.menu.UploadSpeed.460800.macosx=460800 +unphone7.menu.UploadSpeed.460800.upload.speed=460800 +unphone7.menu.UploadSpeed.512000.windows=512000 +unphone7.menu.UploadSpeed.512000.upload.speed=512000 + +unphone7.menu.DebugLevel.none=None +unphone7.menu.DebugLevel.none.build.code_debug=0 +unphone7.menu.DebugLevel.error=Error +unphone7.menu.DebugLevel.error.build.code_debug=1 +unphone7.menu.DebugLevel.warn=Warn +unphone7.menu.DebugLevel.warn.build.code_debug=2 +unphone7.menu.DebugLevel.info=Info +unphone7.menu.DebugLevel.info.build.code_debug=3 +unphone7.menu.DebugLevel.debug=Debug +unphone7.menu.DebugLevel.debug.build.code_debug=4 +unphone7.menu.DebugLevel.verbose=Verbose +unphone7.menu.DebugLevel.verbose.build.code_debug=5 + +unphone7.menu.PartitionScheme.default=Default +unphone7.menu.PartitionScheme.default.build.partitions=default +unphone7.menu.PartitionScheme.no_ota=No OTA (Large APP) +unphone7.menu.PartitionScheme.no_ota.build.partitions=no_ota +unphone7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +unphone7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA) +unphone7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +unphone7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +unphone7.menu.EraseFlash.none=Disabled +unphone7.menu.EraseFlash.none.upload.erase_cmd= +unphone7.menu.EraseFlash.all=Enabled +unphone7.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +unphone8.name=unPhone 8 +unphone8.vid.0=0x16D0 +unphone8.pid.0=0x1178 + +unphone8.bootloader.tool=esptool_py +unphone8.bootloader.tool.default=esptool_py + +unphone8.upload.tool=esptool_py +unphone8.upload.tool.default=esptool_py +unphone8.upload.tool.network=esp_ota + +unphone8.upload.maximum_size=8323072 +unphone8.upload.maximum_data_size=2424832 +unphone8.upload.flags= +unphone8.upload.extra_flags= +unphone8.upload.use_1200bps_touch=false +unphone8.upload.wait_for_upload_port=false + +unphone8.serial.disableDTR=false +unphone8.serial.disableRTS=false + +unphone8.build.tarch=xtensa +unphone8.build.bootloader_addr=0x0 +unphone8.build.target=esp32s3 +unphone8.build.mcu=esp32s3 +unphone8.build.core=esp32 +unphone8.build.variant=unphone8 +unphone8.build.board=unphone8 + +unphone8.build.usb_mode=1 +unphone8.build.cdc_on_boot=0 +unphone8.build.msc_on_boot=0 +unphone8.build.dfu_on_boot=0 +unphone8.build.f_cpu=240000000L +unphone8.build.flash_size=8MB +unphone8.build.flash_freq=80m +unphone8.build.flash_mode=dio +unphone8.build.boot=qio +unphone8.build.boot_freq=80m +unphone8.build.partitions=default_8MB +unphone8.build.defines=-DBOARD_HAS_PSRAM -DUNPHONE_SPIN=8 +unphone8.build.loop_core=-DARDUINO_RUNNING_CORE=1 +unphone8.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +unphone8.build.flash_type=qio +unphone8.build.psram_type=qspi +unphone8.build.memory_type={build.flash_type}_{build.psram_type} + +unphone8.menu.USBMode.default=Hardware CDC and JTAG +unphone8.menu.USBMode.default.build.usb_mode=1 +unphone8.menu.USBMode.hwcdc=USB-OTG (TinyUSB) +unphone8.menu.USBMode.hwcdc.build.usb_mode=0 + +unphone8.menu.CDCOnBoot.default=Disabled +unphone8.menu.CDCOnBoot.default.build.cdc_on_boot=0 +unphone8.menu.CDCOnBoot.cdc=Enabled +unphone8.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +unphone8.menu.MSCOnBoot.default=Disabled +unphone8.menu.MSCOnBoot.default.build.msc_on_boot=0 +unphone8.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +unphone8.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +unphone8.menu.DFUOnBoot.default=Disabled +unphone8.menu.DFUOnBoot.default.build.dfu_on_boot=0 +unphone8.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +unphone8.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +unphone8.menu.UploadMode.default=UART0 / Hardware CDC +unphone8.menu.UploadMode.default.upload.use_1200bps_touch=false +unphone8.menu.UploadMode.default.upload.wait_for_upload_port=false +unphone8.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +unphone8.menu.UploadMode.cdc.upload.use_1200bps_touch=true +unphone8.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +unphone8.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +unphone8.menu.PartitionScheme.default.build.partitions=default +unphone8.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +unphone8.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +unphone8.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +unphone8.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +unphone8.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +unphone8.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +unphone8.menu.PartitionScheme.minimal.build.partitions=minimal +unphone8.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +unphone8.menu.PartitionScheme.no_ota.build.partitions=no_ota +unphone8.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +unphone8.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +unphone8.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +unphone8.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +unphone8.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +unphone8.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +unphone8.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +unphone8.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +unphone8.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +unphone8.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +unphone8.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +unphone8.menu.PartitionScheme.huge_app.build.partitions=huge_app +unphone8.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +unphone8.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +unphone8.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +unphone8.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +unphone8.menu.PartitionScheme.rainmaker=RainMaker 4MB +unphone8.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +unphone8.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +unphone8.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +unphone8.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +unphone8.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +unphone8.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +unphone8.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +unphone8.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +unphone8.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +unphone8.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB + +unphone8.menu.CPUFreq.240=240MHz (WiFi) +unphone8.menu.CPUFreq.240.build.f_cpu=240000000L +unphone8.menu.CPUFreq.160=160MHz (WiFi) +unphone8.menu.CPUFreq.160.build.f_cpu=160000000L +unphone8.menu.CPUFreq.80=80MHz (WiFi) +unphone8.menu.CPUFreq.80.build.f_cpu=80000000L +unphone8.menu.CPUFreq.40=40MHz +unphone8.menu.CPUFreq.40.build.f_cpu=40000000L +unphone8.menu.CPUFreq.20=20MHz +unphone8.menu.CPUFreq.20.build.f_cpu=20000000L +unphone8.menu.CPUFreq.10=10MHz +unphone8.menu.CPUFreq.10.build.f_cpu=10000000L + +unphone8.menu.UploadSpeed.921600=921600 +unphone8.menu.UploadSpeed.921600.upload.speed=921600 +unphone8.menu.UploadSpeed.115200=115200 +unphone8.menu.UploadSpeed.115200.upload.speed=115200 +unphone8.menu.UploadSpeed.256000.windows=256000 +unphone8.menu.UploadSpeed.256000.upload.speed=256000 +unphone8.menu.UploadSpeed.230400.windows.upload.speed=256000 +unphone8.menu.UploadSpeed.230400=230400 +unphone8.menu.UploadSpeed.230400.upload.speed=230400 +unphone8.menu.UploadSpeed.460800.linux=460800 +unphone8.menu.UploadSpeed.460800.macosx=460800 +unphone8.menu.UploadSpeed.460800.upload.speed=460800 +unphone8.menu.UploadSpeed.512000.windows=512000 +unphone8.menu.UploadSpeed.512000.upload.speed=512000 + +unphone8.menu.DebugLevel.none=None +unphone8.menu.DebugLevel.none.build.code_debug=0 +unphone8.menu.DebugLevel.error=Error +unphone8.menu.DebugLevel.error.build.code_debug=1 +unphone8.menu.DebugLevel.warn=Warn +unphone8.menu.DebugLevel.warn.build.code_debug=2 +unphone8.menu.DebugLevel.info=Info +unphone8.menu.DebugLevel.info.build.code_debug=3 +unphone8.menu.DebugLevel.debug=Debug +unphone8.menu.DebugLevel.debug.build.code_debug=4 +unphone8.menu.DebugLevel.verbose=Verbose +unphone8.menu.DebugLevel.verbose.build.code_debug=5 + +############################################################# + +unphone9.name=unPhone 9 +unphone9.vid.0=0x16D0 +unphone9.pid.0=0x1178 + +unphone9.bootloader.tool=esptool_py +unphone9.bootloader.tool.default=esptool_py + +unphone9.upload.tool=esptool_py +unphone9.upload.tool.default=esptool_py +unphone9.upload.tool.network=esp_ota + +unphone9.upload.maximum_size=8323072 +unphone9.upload.maximum_data_size=8716288 +unphone9.upload.flags= +unphone9.upload.extra_flags= +unphone9.upload.use_1200bps_touch=false +unphone9.upload.wait_for_upload_port=false + +unphone9.serial.disableDTR=false +unphone9.serial.disableRTS=false + +unphone9.build.tarch=xtensa +unphone9.build.bootloader_addr=0x0 +unphone9.build.target=esp32s3 +unphone9.build.mcu=esp32s3 +unphone9.build.core=esp32 +unphone9.build.variant=unphone9 +unphone9.build.board=unphone9 + +unphone9.build.usb_mode=1 +unphone9.build.cdc_on_boot=1 +unphone9.build.msc_on_boot=0 +unphone9.build.dfu_on_boot=0 +unphone9.build.f_cpu=240000000L +unphone9.build.flash_size=8MB +unphone9.build.flash_freq=80m +unphone9.build.flash_mode=dio +unphone9.build.boot=qio +unphone9.build.boot_freq=80m +unphone9.build.partitions=default_8MB +unphone9.build.defines=-DBOARD_HAS_PSRAM -DUNPHONE_SPIN=9 +unphone9.build.loop_core=-DARDUINO_RUNNING_CORE=1 +unphone9.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +unphone9.build.flash_type=qio +unphone9.build.psram_type=qspi +unphone9.build.memory_type={build.flash_type}_{build.psram_type} + +unphone9.menu.USBMode.default=Hardware CDC and JTAG +unphone9.menu.USBMode.default.build.usb_mode=1 +unphone9.menu.USBMode.hwcdc=USB-OTG (TinyUSB) +unphone9.menu.USBMode.hwcdc.build.usb_mode=0 + +unphone9.menu.CDCOnBoot.default=Enabled +unphone9.menu.CDCOnBoot.default.build.cdc_on_boot=1 +unphone9.menu.CDCOnBoot.cdc=Disabled +unphone9.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +unphone9.menu.MSCOnBoot.default=Disabled +unphone9.menu.MSCOnBoot.default.build.msc_on_boot=0 +unphone9.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +unphone9.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +unphone9.menu.DFUOnBoot.default=Disabled +unphone9.menu.DFUOnBoot.default.build.dfu_on_boot=0 +unphone9.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +unphone9.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +unphone9.menu.UploadMode.default=UART0 / Hardware CDC +unphone9.menu.UploadMode.default.upload.use_1200bps_touch=false +unphone9.menu.UploadMode.default.upload.wait_for_upload_port=false +unphone9.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +unphone9.menu.UploadMode.cdc.upload.use_1200bps_touch=true +unphone9.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +unphone9.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +unphone9.menu.PartitionScheme.default.build.partitions=default +unphone9.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +unphone9.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +unphone9.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +unphone9.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +unphone9.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +unphone9.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +unphone9.menu.PartitionScheme.minimal.build.partitions=minimal +unphone9.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +unphone9.menu.PartitionScheme.no_ota.build.partitions=no_ota +unphone9.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +unphone9.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +unphone9.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +unphone9.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +unphone9.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +unphone9.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +unphone9.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +unphone9.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +unphone9.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +unphone9.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +unphone9.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +unphone9.menu.PartitionScheme.huge_app.build.partitions=huge_app +unphone9.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +unphone9.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +unphone9.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +unphone9.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +unphone9.menu.PartitionScheme.rainmaker=RainMaker 4MB +unphone9.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +unphone9.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +unphone9.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +unphone9.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +unphone9.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +unphone9.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +unphone9.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +unphone9.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +unphone9.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +unphone9.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB + +unphone9.menu.CPUFreq.240=240MHz (WiFi) +unphone9.menu.CPUFreq.240.build.f_cpu=240000000L +unphone9.menu.CPUFreq.160=160MHz (WiFi) +unphone9.menu.CPUFreq.160.build.f_cpu=160000000L +unphone9.menu.CPUFreq.80=80MHz (WiFi) +unphone9.menu.CPUFreq.80.build.f_cpu=80000000L +unphone9.menu.CPUFreq.40=40MHz +unphone9.menu.CPUFreq.40.build.f_cpu=40000000L +unphone9.menu.CPUFreq.20=20MHz +unphone9.menu.CPUFreq.20.build.f_cpu=20000000L +unphone9.menu.CPUFreq.10=10MHz +unphone9.menu.CPUFreq.10.build.f_cpu=10000000L + +unphone9.menu.UploadSpeed.921600=921600 +unphone9.menu.UploadSpeed.921600.upload.speed=921600 +unphone9.menu.UploadSpeed.115200=115200 +unphone9.menu.UploadSpeed.115200.upload.speed=115200 +unphone9.menu.UploadSpeed.256000.windows=256000 +unphone9.menu.UploadSpeed.256000.upload.speed=256000 +unphone9.menu.UploadSpeed.230400.windows.upload.speed=256000 +unphone9.menu.UploadSpeed.230400=230400 +unphone9.menu.UploadSpeed.230400.upload.speed=230400 +unphone9.menu.UploadSpeed.460800.linux=460800 +unphone9.menu.UploadSpeed.460800.macosx=460800 +unphone9.menu.UploadSpeed.460800.upload.speed=460800 +unphone9.menu.UploadSpeed.512000.windows=512000 +unphone9.menu.UploadSpeed.512000.upload.speed=512000 + +unphone9.menu.DebugLevel.none=None +unphone9.menu.DebugLevel.none.build.code_debug=0 +unphone9.menu.DebugLevel.error=Error +unphone9.menu.DebugLevel.error.build.code_debug=1 +unphone9.menu.DebugLevel.warn=Warn +unphone9.menu.DebugLevel.warn.build.code_debug=2 +unphone9.menu.DebugLevel.info=Info +unphone9.menu.DebugLevel.info.build.code_debug=3 +unphone9.menu.DebugLevel.debug=Debug +unphone9.menu.DebugLevel.debug.build.code_debug=4 +unphone9.menu.DebugLevel.verbose=Verbose +unphone9.menu.DebugLevel.verbose.build.code_debug=5 + +unphone9.menu.EraseFlash.none=Disabled +unphone9.menu.EraseFlash.none.upload.erase_cmd= +unphone9.menu.EraseFlash.all=Enabled +unphone9.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################### +# Cytron Maker Feather AIoT S3 + +cytron_maker_feather_aiot_s3.name=Cytron Maker Feather AIoT S3 +cytron_maker_feather_aiot_s3.vid.0=0x303a +cytron_maker_feather_aiot_s3.pid.0=0x80f8 + +cytron_maker_feather_aiot_s3.bootloader.tool=esptool_py +cytron_maker_feather_aiot_s3.bootloader.tool.default=esptool_py + +cytron_maker_feather_aiot_s3.upload.tool=esptool_py +cytron_maker_feather_aiot_s3.upload.tool.default=esptool_py +cytron_maker_feather_aiot_s3.upload.tool.network=esp_ota + +cytron_maker_feather_aiot_s3.upload.maximum_size=1310720 +cytron_maker_feather_aiot_s3.upload.maximum_data_size=327680 +cytron_maker_feather_aiot_s3.upload.flags= +cytron_maker_feather_aiot_s3.upload.extra_flags= +cytron_maker_feather_aiot_s3.upload.use_1200bps_touch=true +cytron_maker_feather_aiot_s3.upload.wait_for_upload_port=true + +cytron_maker_feather_aiot_s3.serial.disableDTR=false +cytron_maker_feather_aiot_s3.serial.disableRTS=false + +cytron_maker_feather_aiot_s3.build.tarch=xtensa +cytron_maker_feather_aiot_s3.build.bootloader_addr=0x0 +cytron_maker_feather_aiot_s3.build.target=esp32s3 +cytron_maker_feather_aiot_s3.build.mcu=esp32s3 +cytron_maker_feather_aiot_s3.build.core=esp32 +cytron_maker_feather_aiot_s3.build.variant=cytron_maker_feather_aiot_s3 +cytron_maker_feather_aiot_s3.build.board=CYTRON_MAKER_FEATHER_AIOT_S3 + +cytron_maker_feather_aiot_s3.build.usb_mode=0 +cytron_maker_feather_aiot_s3.build.cdc_on_boot=1 +cytron_maker_feather_aiot_s3.build.msc_on_boot=0 +cytron_maker_feather_aiot_s3.build.dfu_on_boot=0 +cytron_maker_feather_aiot_s3.build.f_cpu=240000000L +cytron_maker_feather_aiot_s3.build.flash_size=8MB +cytron_maker_feather_aiot_s3.build.flash_freq=80m +cytron_maker_feather_aiot_s3.build.flash_mode=dio +cytron_maker_feather_aiot_s3.build.boot=qio +cytron_maker_feather_aiot_s3.build.partitions=default +cytron_maker_feather_aiot_s3.build.defines= +cytron_maker_feather_aiot_s3.build.loop_core= +cytron_maker_feather_aiot_s3.build.event_core= +cytron_maker_feather_aiot_s3.build.flash_type=qio +cytron_maker_feather_aiot_s3.build.psram_type=opi +cytron_maker_feather_aiot_s3.build.memory_type={build.flash_type}_{build.psram_type} + +cytron_maker_feather_aiot_s3.menu.LoopCore.1=Core 1 +cytron_maker_feather_aiot_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +cytron_maker_feather_aiot_s3.menu.LoopCore.0=Core 0 +cytron_maker_feather_aiot_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +cytron_maker_feather_aiot_s3.menu.EventsCore.1=Core 1 +cytron_maker_feather_aiot_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +cytron_maker_feather_aiot_s3.menu.EventsCore.0=Core 0 +cytron_maker_feather_aiot_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +cytron_maker_feather_aiot_s3.menu.USBMode.default=USB-OTG (TinyUSB) +cytron_maker_feather_aiot_s3.menu.USBMode.default.build.usb_mode=0 +cytron_maker_feather_aiot_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +cytron_maker_feather_aiot_s3.menu.USBMode.hwcdc.build.usb_mode=1 + +cytron_maker_feather_aiot_s3.menu.CDCOnBoot.cdc=Enabled +cytron_maker_feather_aiot_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +cytron_maker_feather_aiot_s3.menu.CDCOnBoot.default=Disabled +cytron_maker_feather_aiot_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +cytron_maker_feather_aiot_s3.menu.MSCOnBoot.default=Disabled +cytron_maker_feather_aiot_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +cytron_maker_feather_aiot_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +cytron_maker_feather_aiot_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +cytron_maker_feather_aiot_s3.menu.DFUOnBoot.default=Disabled +cytron_maker_feather_aiot_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +cytron_maker_feather_aiot_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +cytron_maker_feather_aiot_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +cytron_maker_feather_aiot_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +cytron_maker_feather_aiot_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +cytron_maker_feather_aiot_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +cytron_maker_feather_aiot_s3.menu.UploadMode.default=UART0 / Hardware CDC +cytron_maker_feather_aiot_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +cytron_maker_feather_aiot_s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +cytron_maker_feather_aiot_s3.menu.PSRAM.opi=OPI PSRAM +cytron_maker_feather_aiot_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +cytron_maker_feather_aiot_s3.menu.PSRAM.opi.build.psram_type=opi +cytron_maker_feather_aiot_s3.menu.PSRAM.enabled=QSPI PSRAM +cytron_maker_feather_aiot_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +cytron_maker_feather_aiot_s3.menu.PSRAM.enabled.build.psram_type=qspi +cytron_maker_feather_aiot_s3.menu.PSRAM.disabled=Disabled +cytron_maker_feather_aiot_s3.menu.PSRAM.disabled.build.defines= +cytron_maker_feather_aiot_s3.menu.PSRAM.disabled.build.psram_type=qspi + +cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT) +cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB-tinyuf2 +cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +cytron_maker_feather_aiot_s3.menu.CPUFreq.240=240MHz (WiFi) +cytron_maker_feather_aiot_s3.menu.CPUFreq.240.build.f_cpu=240000000L +cytron_maker_feather_aiot_s3.menu.CPUFreq.160=160MHz (WiFi) +cytron_maker_feather_aiot_s3.menu.CPUFreq.160.build.f_cpu=160000000L +cytron_maker_feather_aiot_s3.menu.CPUFreq.80=80MHz (WiFi) +cytron_maker_feather_aiot_s3.menu.CPUFreq.80.build.f_cpu=80000000L +cytron_maker_feather_aiot_s3.menu.CPUFreq.40=40MHz +cytron_maker_feather_aiot_s3.menu.CPUFreq.40.build.f_cpu=40000000L +cytron_maker_feather_aiot_s3.menu.CPUFreq.20=20MHz +cytron_maker_feather_aiot_s3.menu.CPUFreq.20.build.f_cpu=20000000L +cytron_maker_feather_aiot_s3.menu.CPUFreq.10=10MHz +cytron_maker_feather_aiot_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +cytron_maker_feather_aiot_s3.menu.FlashMode.qio=QIO 80MHz +cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.flash_mode=dio +cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.boot=qio +cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.boot_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.flash_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.qio120=QIO 120MHz +cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.flash_mode=dio +cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.boot=qio +cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.boot_freq=120m +cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.flash_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.dio=DIO 80MHz +cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.flash_mode=dio +cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.boot=dio +cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.boot_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.flash_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.opi=OPI 80MHz +cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.flash_mode=dout +cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.boot=opi +cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.boot_freq=80m +cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.flash_freq=80m + +cytron_maker_feather_aiot_s3.menu.FlashSize.8M=8MB (64Mb) +cytron_maker_feather_aiot_s3.menu.FlashSize.8M.build.flash_size=8MB + +cytron_maker_feather_aiot_s3.menu.UploadSpeed.921600=921600 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.921600.upload.speed=921600 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.115200=115200 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.115200.upload.speed=115200 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.256000.windows=256000 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.256000.upload.speed=256000 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400=230400 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400.upload.speed=230400 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.linux=460800 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.macosx=460800 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.upload.speed=460800 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.512000.windows=512000 +cytron_maker_feather_aiot_s3.menu.UploadSpeed.512000.upload.speed=512000 + +cytron_maker_feather_aiot_s3.menu.DebugLevel.none=None +cytron_maker_feather_aiot_s3.menu.DebugLevel.none.build.code_debug=0 +cytron_maker_feather_aiot_s3.menu.DebugLevel.error=Error +cytron_maker_feather_aiot_s3.menu.DebugLevel.error.build.code_debug=1 +cytron_maker_feather_aiot_s3.menu.DebugLevel.warn=Warn +cytron_maker_feather_aiot_s3.menu.DebugLevel.warn.build.code_debug=2 +cytron_maker_feather_aiot_s3.menu.DebugLevel.info=Info +cytron_maker_feather_aiot_s3.menu.DebugLevel.info.build.code_debug=3 +cytron_maker_feather_aiot_s3.menu.DebugLevel.debug=Debug +cytron_maker_feather_aiot_s3.menu.DebugLevel.debug.build.code_debug=4 +cytron_maker_feather_aiot_s3.menu.DebugLevel.verbose=Verbose +cytron_maker_feather_aiot_s3.menu.DebugLevel.verbose.build.code_debug=5 + +cytron_maker_feather_aiot_s3.menu.EraseFlash.none=Disabled +cytron_maker_feather_aiot_s3.menu.EraseFlash.none.upload.erase_cmd= +cytron_maker_feather_aiot_s3.menu.EraseFlash.all=Enabled +cytron_maker_feather_aiot_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# RedPill(+) ESP32-S3 + +redpill_esp32s3.name=RedPill(+) ESP32-S3 + +redpill_esp32s3.bootloader.tool=esptool_py +redpill_esp32s3.bootloader.tool.default=esptool_py + +redpill_esp32s3.upload.tool=esptool_py +redpill_esp32s3.upload.tool.default=esptool_py +redpill_esp32s3.upload.tool.network=esp_ota + +redpill_esp32s3.upload.maximum_size=1310720 +redpill_esp32s3.upload.maximum_data_size=327680 +redpill_esp32s3.upload.flags= +redpill_esp32s3.upload.extra_flags= +redpill_esp32s3.upload.use_1200bps_touch=true +redpill_esp32s3.upload.wait_for_upload_port=true + +redpill_esp32s3.serial.disableDTR=false +redpill_esp32s3.serial.disableRTS=false + +redpill_esp32s3.build.tarch=xtensa +redpill_esp32s3.build.bootloader_addr=0x0 +redpill_esp32s3.build.target=esp32s3 +redpill_esp32s3.build.mcu=esp32s3 +redpill_esp32s3.build.core=esp32 +redpill_esp32s3.build.variant=redpill_esp32s3 +redpill_esp32s3.build.board=REDPILL_ESP32S3 + +redpill_esp32s3.build.usb_mode=0 +redpill_esp32s3.build.cdc_on_boot=1 +redpill_esp32s3.build.msc_on_boot=0 +redpill_esp32s3.build.dfu_on_boot=0 +redpill_esp32s3.build.f_cpu=240000000L +redpill_esp32s3.build.flash_size=8MB +redpill_esp32s3.build.flash_freq=80m +redpill_esp32s3.build.flash_mode=dio +redpill_esp32s3.build.boot=qio +redpill_esp32s3.build.partitions=default +redpill_esp32s3.build.defines= +redpill_esp32s3.build.loop_core= +redpill_esp32s3.build.event_core= +redpill_esp32s3.build.flash_type=qio +redpill_esp32s3.build.psram_type=qspi +redpill_esp32s3.build.memory_type={build.flash_type}_{build.psram_type} + +redpill_esp32s3.menu.LoopCore.1=Core 1 +redpill_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +redpill_esp32s3.menu.LoopCore.0=Core 0 +redpill_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +redpill_esp32s3.menu.EventsCore.1=Core 1 +redpill_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +redpill_esp32s3.menu.EventsCore.0=Core 0 +redpill_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +redpill_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +redpill_esp32s3.menu.USBMode.default.build.usb_mode=0 +redpill_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +redpill_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 + +redpill_esp32s3.menu.CDCOnBoot.cdc=Enabled +redpill_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +redpill_esp32s3.menu.CDCOnBoot.default=Disabled +redpill_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +redpill_esp32s3.menu.MSCOnBoot.default=Disabled +redpill_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +redpill_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +redpill_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +redpill_esp32s3.menu.DFUOnBoot.default=Disabled +redpill_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +redpill_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +redpill_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +redpill_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +redpill_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +redpill_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +redpill_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +redpill_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +redpill_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +redpill_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +redpill_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +redpill_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +redpill_esp32s3.menu.PSRAM.disabled=Disabled +redpill_esp32s3.menu.PSRAM.disabled.build.defines= +redpill_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +redpill_esp32s3.menu.PSRAM.opi=OPI PSRAM +redpill_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +redpill_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +redpill_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT) +redpill_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +redpill_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB-tinyuf2 +redpill_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +redpill_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +redpill_esp32s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +redpill_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +redpill_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 + +redpill_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +redpill_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +redpill_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +redpill_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +redpill_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +redpill_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +redpill_esp32s3.menu.CPUFreq.40=40MHz +redpill_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +redpill_esp32s3.menu.CPUFreq.20=20MHz +redpill_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +redpill_esp32s3.menu.CPUFreq.10=10MHz +redpill_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +redpill_esp32s3.menu.FlashMode.qio=QIO 80MHz +redpill_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +redpill_esp32s3.menu.FlashMode.qio.build.boot=qio +redpill_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +redpill_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +redpill_esp32s3.menu.FlashMode.qio120=QIO 120MHz +redpill_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +redpill_esp32s3.menu.FlashMode.qio120.build.boot=qio +redpill_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +redpill_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +redpill_esp32s3.menu.FlashMode.dio=DIO 80MHz +redpill_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +redpill_esp32s3.menu.FlashMode.dio.build.boot=dio +redpill_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +redpill_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +redpill_esp32s3.menu.FlashMode.opi=OPI 80MHz +redpill_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +redpill_esp32s3.menu.FlashMode.opi.build.boot=opi +redpill_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +redpill_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +redpill_esp32s3.menu.FlashSize.8M=8MB (64Mb) +redpill_esp32s3.menu.FlashSize.8M.build.flash_size=8MB + +redpill_esp32s3.menu.UploadSpeed.921600=921600 +redpill_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +redpill_esp32s3.menu.UploadSpeed.115200=115200 +redpill_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +redpill_esp32s3.menu.UploadSpeed.256000.windows=256000 +redpill_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +redpill_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +redpill_esp32s3.menu.UploadSpeed.230400=230400 +redpill_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +redpill_esp32s3.menu.UploadSpeed.460800.linux=460800 +redpill_esp32s3.menu.UploadSpeed.460800.macosx=460800 +redpill_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +redpill_esp32s3.menu.UploadSpeed.512000.windows=512000 +redpill_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +redpill_esp32s3.menu.DebugLevel.none=None +redpill_esp32s3.menu.DebugLevel.none.build.code_debug=0 +redpill_esp32s3.menu.DebugLevel.error=Error +redpill_esp32s3.menu.DebugLevel.error.build.code_debug=1 +redpill_esp32s3.menu.DebugLevel.warn=Warn +redpill_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +redpill_esp32s3.menu.DebugLevel.info=Info +redpill_esp32s3.menu.DebugLevel.info.build.code_debug=3 +redpill_esp32s3.menu.DebugLevel.debug=Debug +redpill_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +redpill_esp32s3.menu.DebugLevel.verbose=Verbose +redpill_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +redpill_esp32s3.menu.EraseFlash.none=Disabled +redpill_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +redpill_esp32s3.menu.EraseFlash.all=Enabled +redpill_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +esp32c3m1IKit.name=ESP-C3-M1-I-Kit + +esp32c3m1IKit.bootloader.tool=esptool_py +esp32c3m1IKit.bootloader.tool.default=esptool_py + +esp32c3m1IKit.upload.tool=esptool_py +esp32c3m1IKit.upload.tool.default=esptool_py +esp32c3m1IKit.upload.tool.network=esp_ota + +esp32c3m1IKit.upload.maximum_size=1310720 +esp32c3m1IKit.upload.maximum_data_size=327680 +esp32c3m1IKit.upload.flags= +esp32c3m1IKit.upload.extra_flags= +esp32c3m1IKit.upload.use_1200bps_touch=false +esp32c3m1IKit.upload.wait_for_upload_port=false + +esp32c3m1IKit.serial.disableDTR=false +esp32c3m1IKit.serial.disableRTS=false + +esp32c3m1IKit.build.tarch=riscv32 +esp32c3m1IKit.build.target=esp +esp32c3m1IKit.build.mcu=esp32c3 +esp32c3m1IKit.build.core=esp32 +esp32c3m1IKit.build.variant=esp_c3_m1_i_kit +esp32c3m1IKit.build.board=ESP32C3_M1_I_KIT +esp32c3m1IKit.build.bootloader_addr=0x0 + +esp32c3m1IKit.build.cdc_on_boot=0 +esp32c3m1IKit.build.f_cpu=160000000L +esp32c3m1IKit.build.flash_size=4MB +esp32c3m1IKit.build.flash_freq=80m +esp32c3m1IKit.build.flash_mode=qio +esp32c3m1IKit.build.boot=qio +esp32c3m1IKit.build.partitions=default +esp32c3m1IKit.build.defines= + +esp32c3m1IKit.menu.CDCOnBoot.default=Disabled +esp32c3m1IKit.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c3m1IKit.menu.CDCOnBoot.cdc=Enabled +esp32c3m1IKit.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c3m1IKit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.default.build.partitions=default +esp32c3m1IKit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c3m1IKit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c3m1IKit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c3m1IKit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c3m1IKit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c3m1IKit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c3m1IKit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c3m1IKit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c3m1IKit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c3m1IKit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c3m1IKit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c3m1IKit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c3m1IKit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c3m1IKit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c3m1IKit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c3m1IKit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +esp32c3m1IKit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c3m1IKit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c3m1IKit.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c3m1IKit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c3m1IKit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +esp32c3m1IKit.menu.CPUFreq.160=160MHz (WiFi) +esp32c3m1IKit.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c3m1IKit.menu.CPUFreq.80=80MHz (WiFi) +esp32c3m1IKit.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c3m1IKit.menu.CPUFreq.40=40MHz +esp32c3m1IKit.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c3m1IKit.menu.CPUFreq.20=20MHz +esp32c3m1IKit.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c3m1IKit.menu.CPUFreq.10=10MHz +esp32c3m1IKit.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c3m1IKit.menu.UploadSpeed.921600=921600 +esp32c3m1IKit.menu.UploadSpeed.921600.upload.speed=921600 +esp32c3m1IKit.menu.UploadSpeed.115200=115200 +esp32c3m1IKit.menu.UploadSpeed.115200.upload.speed=115200 +esp32c3m1IKit.menu.UploadSpeed.256000.windows=256000 +esp32c3m1IKit.menu.UploadSpeed.256000.upload.speed=256000 +esp32c3m1IKit.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c3m1IKit.menu.UploadSpeed.230400=230400 +esp32c3m1IKit.menu.UploadSpeed.230400.upload.speed=230400 +esp32c3m1IKit.menu.UploadSpeed.460800.linux=460800 +esp32c3m1IKit.menu.UploadSpeed.460800.macosx=460800 +esp32c3m1IKit.menu.UploadSpeed.460800.upload.speed=460800 +esp32c3m1IKit.menu.UploadSpeed.512000.windows=512000 +esp32c3m1IKit.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c3m1IKit.menu.DebugLevel.none=None +esp32c3m1IKit.menu.DebugLevel.none.build.code_debug=0 +esp32c3m1IKit.menu.DebugLevel.error=Error +esp32c3m1IKit.menu.DebugLevel.error.build.code_debug=1 +esp32c3m1IKit.menu.DebugLevel.warn=Warn +esp32c3m1IKit.menu.DebugLevel.warn.build.code_debug=2 +esp32c3m1IKit.menu.DebugLevel.info=Info +esp32c3m1IKit.menu.DebugLevel.info.build.code_debug=3 +esp32c3m1IKit.menu.DebugLevel.debug=Debug +esp32c3m1IKit.menu.DebugLevel.debug.build.code_debug=4 +esp32c3m1IKit.menu.DebugLevel.verbose=Verbose +esp32c3m1IKit.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c3m1IKit.menu.EraseFlash.none=Disabled +esp32c3m1IKit.menu.EraseFlash.none.upload.erase_cmd= +esp32c3m1IKit.menu.EraseFlash.all=Enabled +esp32c3m1IKit.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +roboheart_hercules.name=RoboHeart Hercules + +roboheart_hercules.upload.tool=esptool_py +roboheart_hercules.upload.tool.default=esptool_py +roboheart_hercules.upload.maximum_size=1310720 +roboheart_hercules.upload.maximum_data_size=327680 +roboheart_hercules.upload.wait_for_upload_port=true +roboheart_hercules.upload.flags= +roboheart_hercules.upload.extra_flags= + +roboheart_hercules.serial.disableDTR=true +roboheart_hercules.serial.disableRTS=true + +roboheart_hercules.build.tarch=xtensa +roboheart_hercules.build.bootloader_addr=0x1000 +roboheart_hercules.build.target=esp32 +roboheart_hercules.build.mcu=esp32 +roboheart_hercules.build.core=esp32 +roboheart_hercules.build.variant=roboheart_hercules +roboheart_hercules.build.board=roboheart_hercules + +roboheart_hercules.build.f_cpu=240000000L +roboheart_hercules.build.flash_size=4MB +roboheart_hercules.build.flash_freq=40m +roboheart_hercules.build.flash_mode=dio +roboheart_hercules.build.boot=dio +roboheart_hercules.build.partitions=default +roboheart_hercules.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +roboheart_hercules.build.extra_libs= + +roboheart_hercules.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +roboheart_hercules.menu.PartitionScheme.default.build.partitions=default +roboheart_hercules.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +roboheart_hercules.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +roboheart_hercules.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT) +roboheart_hercules.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +roboheart_hercules.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +roboheart_hercules.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +roboheart_hercules.menu.PartitionScheme.minimal.build.partitions=minimal +roboheart_hercules.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +roboheart_hercules.menu.PartitionScheme.no_ota.build.partitions=no_ota +roboheart_hercules.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +roboheart_hercules.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +roboheart_hercules.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +roboheart_hercules.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +roboheart_hercules.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +roboheart_hercules.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +roboheart_hercules.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +roboheart_hercules.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +roboheart_hercules.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +roboheart_hercules.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +roboheart_hercules.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +roboheart_hercules.menu.PartitionScheme.huge_app.build.partitions=huge_app +roboheart_hercules.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +roboheart_hercules.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +roboheart_hercules.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +roboheart_hercules.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +roboheart_hercules.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +roboheart_hercules.menu.PartitionScheme.fatflash.build.partitions=ffat +roboheart_hercules.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +roboheart_hercules.menu.PartitionScheme.rainmaker=RainMaker 4MB +roboheart_hercules.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +roboheart_hercules.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +roboheart_hercules.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +roboheart_hercules.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +roboheart_hercules.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +roboheart_hercules.menu.CPUFreq.240=240MHz (WiFi/BT) +roboheart_hercules.menu.CPUFreq.240.build.f_cpu=240000000L +roboheart_hercules.menu.CPUFreq.160=160MHz (WiFi/BT) +roboheart_hercules.menu.CPUFreq.160.build.f_cpu=160000000L +roboheart_hercules.menu.CPUFreq.80=80MHz (WiFi/BT) +roboheart_hercules.menu.CPUFreq.80.build.f_cpu=80000000L +roboheart_hercules.menu.CPUFreq.40=40MHz +roboheart_hercules.menu.CPUFreq.40.build.f_cpu=40000000L +roboheart_hercules.menu.CPUFreq.20=20MHz +roboheart_hercules.menu.CPUFreq.20.build.f_cpu=20000000L +roboheart_hercules.menu.CPUFreq.10=10MHz +roboheart_hercules.menu.CPUFreq.10.build.f_cpu=10000000L + +roboheart_hercules.menu.FlashMode.qio=QIO +roboheart_hercules.menu.FlashMode.qio.build.flash_mode=dio +roboheart_hercules.menu.FlashMode.qio.build.boot=qio +roboheart_hercules.menu.FlashMode.dio=DIO +roboheart_hercules.menu.FlashMode.dio.build.flash_mode=dio +roboheart_hercules.menu.FlashMode.dio.build.boot=dio + +roboheart_hercules.menu.FlashFreq.80=80MHz +roboheart_hercules.menu.FlashFreq.80.build.flash_freq=80m +roboheart_hercules.menu.FlashFreq.40=40MHz +roboheart_hercules.menu.FlashFreq.40.build.flash_freq=40m + +roboheart_hercules.menu.UploadSpeed.921600=921600 +roboheart_hercules.menu.UploadSpeed.921600.upload.speed=921600 +roboheart_hercules.menu.UploadSpeed.115200=115200 +roboheart_hercules.menu.UploadSpeed.115200.upload.speed=115200 +roboheart_hercules.menu.UploadSpeed.256000.windows=256000 +roboheart_hercules.menu.UploadSpeed.256000.upload.speed=256000 +roboheart_hercules.menu.UploadSpeed.230400.windows.upload.speed=256000 +roboheart_hercules.menu.UploadSpeed.230400=230400 +roboheart_hercules.menu.UploadSpeed.230400.upload.speed=230400 +roboheart_hercules.menu.UploadSpeed.460800.linux=460800 +roboheart_hercules.menu.UploadSpeed.460800.macosx=460800 +roboheart_hercules.menu.UploadSpeed.460800.upload.speed=460800 +roboheart_hercules.menu.UploadSpeed.512000.windows=512000 +roboheart_hercules.menu.UploadSpeed.512000.upload.speed=512000 + +roboheart_hercules.menu.DebugLevel.none=None +roboheart_hercules.menu.DebugLevel.none.build.code_debug=0 +roboheart_hercules.menu.DebugLevel.error=Error +roboheart_hercules.menu.DebugLevel.error.build.code_debug=1 +roboheart_hercules.menu.DebugLevel.warn=Warn +roboheart_hercules.menu.DebugLevel.warn.build.code_debug=2 +roboheart_hercules.menu.DebugLevel.info=Info +roboheart_hercules.menu.DebugLevel.info.build.code_debug=3 +roboheart_hercules.menu.DebugLevel.debug=Debug +roboheart_hercules.menu.DebugLevel.debug.build.code_debug=4 +roboheart_hercules.menu.DebugLevel.verbose=Verbose +roboheart_hercules.menu.DebugLevel.verbose.build.code_debug=5 + +roboheart_hercules.menu.EraseFlash.none=Disabled +roboheart_hercules.menu.EraseFlash.none.upload.erase_cmd= +roboheart_hercules.menu.EraseFlash.all=Enabled +roboheart_hercules.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +VALTRACK_V4_VTS_ESP32_C3.name=VALTRACK_V4_VTS_ESP32_C3 + +VALTRACK_V4_VTS_ESP32_C3.bootloader.tool=esptool_py +VALTRACK_V4_VTS_ESP32_C3.bootloader.tool.default=esptool_py + +VALTRACK_V4_VTS_ESP32_C3.upload.tool=esptool_py +VALTRACK_V4_VTS_ESP32_C3.upload.tool.default=esptool_py +VALTRACK_V4_VTS_ESP32_C3.upload.tool.network=esp_ota + +VALTRACK_V4_VTS_ESP32_C3.upload.maximum_size=1310720 +VALTRACK_V4_VTS_ESP32_C3.upload.maximum_data_size=327680 +VALTRACK_V4_VTS_ESP32_C3.upload.flags= +VALTRACK_V4_VTS_ESP32_C3.upload.extra_flags= +VALTRACK_V4_VTS_ESP32_C3.upload.use_1200bps_touch=false +VALTRACK_V4_VTS_ESP32_C3.upload.wait_for_upload_port=false + +VALTRACK_V4_VTS_ESP32_C3.serial.disableDTR=false +VALTRACK_V4_VTS_ESP32_C3.serial.disableRTS=false + +VALTRACK_V4_VTS_ESP32_C3.build.tarch=riscv32 +VALTRACK_V4_VTS_ESP32_C3.build.target=esp +VALTRACK_V4_VTS_ESP32_C3.build.mcu=esp32c3 +VALTRACK_V4_VTS_ESP32_C3.build.core=esp32 +VALTRACK_V4_VTS_ESP32_C3.build.variant=VALTRACK_V4_VTS_ESP32_C3 +VALTRACK_V4_VTS_ESP32_C3.build.board=VALTRACK_V4_VTS_ESP32_C3 +VALTRACK_V4_VTS_ESP32_C3.build.bootloader_addr=0x0 + +VALTRACK_V4_VTS_ESP32_C3.build.cdc_on_boot=1 +VALTRACK_V4_VTS_ESP32_C3.build.f_cpu=160000000L +VALTRACK_V4_VTS_ESP32_C3.build.flash_size=4MB +VALTRACK_V4_VTS_ESP32_C3.build.flash_freq=80m +VALTRACK_V4_VTS_ESP32_C3.build.flash_mode=qio +VALTRACK_V4_VTS_ESP32_C3.build.boot=qio +VALTRACK_V4_VTS_ESP32_C3.build.partitions=default +VALTRACK_V4_VTS_ESP32_C3.build.defines= + +VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.default=Enabled +VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.cdc=Disabled +VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default.build.partitions=default +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.minimal.build.partitions=minimal +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash.build.partitions=ffat +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.160=160MHz (WiFi) +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.160.build.f_cpu=160000000L +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.80=80MHz (WiFi) +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.80.build.f_cpu=80000000L +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.40=40MHz +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.40.build.f_cpu=40000000L +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.20=20MHz +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.20.build.f_cpu=20000000L +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.10=10MHz +VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.10.build.f_cpu=10000000L + +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio=QIO +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio.build.flash_mode=dio +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio.build.boot=qio +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio=DIO +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio.build.flash_mode=dio +VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio.build.boot=dio + +VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.80=80MHz +VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.80.build.flash_freq=80m +VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.40=40MHz +VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.40.build.flash_freq=40m + +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.4M=4MB (32Mb) +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.4M.build.flash_size=4MB +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.8M=8MB (64Mb) +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.8M.build.flash_size=8MB +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.2M=2MB (16Mb) +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.2M.build.flash_size=2MB +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.16M=16MB (128Mb) +VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.16M.build.flash_size=16MB + +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.921600=921600 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.921600.upload.speed=921600 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.115200=115200 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.115200.upload.speed=115200 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.256000.windows=256000 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.256000.upload.speed=256000 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400.windows.upload.speed=256000 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400=230400 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400.upload.speed=230400 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.linux=460800 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.macosx=460800 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.upload.speed=460800 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.512000.windows=512000 +VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.512000.upload.speed=512000 + +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.none=None +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.none.build.code_debug=0 +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.error=Error +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.error.build.code_debug=1 +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.warn=Warn +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.warn.build.code_debug=2 +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.info=Info +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.info.build.code_debug=3 +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.debug=Debug +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.debug.build.code_debug=4 +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.verbose=Verbose +VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.verbose.build.code_debug=5 + +VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.none=Disabled +VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.none.upload.erase_cmd= +VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.all=Enabled +VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +VALTRACK_V4_MFW_ESP32_C3.name=VALTRACK_V4_MFW_ESP32_C3 + +VALTRACK_V4_MFW_ESP32_C3.bootloader.tool=esptool_py +VALTRACK_V4_MFW_ESP32_C3.bootloader.tool.default=esptool_py + +VALTRACK_V4_MFW_ESP32_C3.upload.tool=esptool_py +VALTRACK_V4_MFW_ESP32_C3.upload.tool.default=esptool_py +VALTRACK_V4_MFW_ESP32_C3.upload.tool.network=esp_ota + +VALTRACK_V4_MFW_ESP32_C3.upload.maximum_size=1310720 +VALTRACK_V4_MFW_ESP32_C3.upload.maximum_data_size=327680 +VALTRACK_V4_MFW_ESP32_C3.upload.flags= +VALTRACK_V4_MFW_ESP32_C3.upload.extra_flags= +VALTRACK_V4_MFW_ESP32_C3.upload.use_1200bps_touch=false +VALTRACK_V4_MFW_ESP32_C3.upload.wait_for_upload_port=false + +VALTRACK_V4_MFW_ESP32_C3.serial.disableDTR=false +VALTRACK_V4_MFW_ESP32_C3.serial.disableRTS=false + +VALTRACK_V4_MFW_ESP32_C3.build.tarch=riscv32 +VALTRACK_V4_MFW_ESP32_C3.build.target=esp +VALTRACK_V4_MFW_ESP32_C3.build.mcu=esp32c3 +VALTRACK_V4_MFW_ESP32_C3.build.core=esp32 +VALTRACK_V4_MFW_ESP32_C3.build.variant=VALTRACK_V4_MFW_ESP32_C3 +VALTRACK_V4_MFW_ESP32_C3.build.board=VALTRACK_V4_MFW_ESP32_C3 +VALTRACK_V4_MFW_ESP32_C3.build.bootloader_addr=0x0 + +VALTRACK_V4_MFW_ESP32_C3.build.cdc_on_boot=1 +VALTRACK_V4_MFW_ESP32_C3.build.f_cpu=160000000L +VALTRACK_V4_MFW_ESP32_C3.build.flash_size=4MB +VALTRACK_V4_MFW_ESP32_C3.build.flash_freq=80m +VALTRACK_V4_MFW_ESP32_C3.build.flash_mode=qio +VALTRACK_V4_MFW_ESP32_C3.build.boot=qio +VALTRACK_V4_MFW_ESP32_C3.build.partitions=default +VALTRACK_V4_MFW_ESP32_C3.build.defines= + +VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.default=Enabled +VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.cdc=Disabled +VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default.build.partitions=default +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.minimal.build.partitions=minimal +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash.build.partitions=ffat +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.160=160MHz (WiFi) +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.160.build.f_cpu=160000000L +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.80=80MHz (WiFi) +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.80.build.f_cpu=80000000L +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.40=40MHz +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.40.build.f_cpu=40000000L +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.20=20MHz +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.20.build.f_cpu=20000000L +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.10=10MHz +VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.10.build.f_cpu=10000000L + +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio=QIO +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio.build.flash_mode=dio +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio.build.boot=qio +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio=DIO +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio.build.flash_mode=dio +VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio.build.boot=dio + +VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.80=80MHz +VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.80.build.flash_freq=80m +VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.40=40MHz +VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.40.build.flash_freq=40m + +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.4M=4MB (32Mb) +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.4M.build.flash_size=4MB +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.8M=8MB (64Mb) +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.8M.build.flash_size=8MB +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.2M=2MB (16Mb) +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.2M.build.flash_size=2MB +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.16M=16MB (128Mb) +VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.16M.build.flash_size=16MB + +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.921600=921600 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.921600.upload.speed=921600 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.115200=115200 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.115200.upload.speed=115200 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.256000.windows=256000 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.256000.upload.speed=256000 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400.windows.upload.speed=256000 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400=230400 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400.upload.speed=230400 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.linux=460800 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.macosx=460800 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.upload.speed=460800 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.512000.windows=512000 +VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.512000.upload.speed=512000 + +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.none=None +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.none.build.code_debug=0 +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.error=Error +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.error.build.code_debug=1 +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.warn=Warn +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.warn.build.code_debug=2 +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.info=Info +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.info.build.code_debug=3 +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.debug=Debug +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.debug.build.code_debug=4 +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.verbose=Verbose +VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.verbose.build.code_debug=5 + +VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.none=Disabled +VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.none.upload.erase_cmd= +VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.all=Enabled +VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +Edgebox-ESP-100.name=Edgebox-ESP-100 + +Edgebox-ESP-100.bootloader.tool=esptool_py +Edgebox-ESP-100.bootloader.tool.default=esptool_py + +Edgebox-ESP-100.upload.tool=esptool_py +Edgebox-ESP-100.upload.tool.default=esptool_py +Edgebox-ESP-100.upload.tool.network=esp_ota + +Edgebox-ESP-100.upload.maximum_size=1310720 +Edgebox-ESP-100.upload.maximum_data_size=327680 +Edgebox-ESP-100.upload.flags= +Edgebox-ESP-100.upload.extra_flags= +Edgebox-ESP-100.upload.use_1200bps_touch=false +Edgebox-ESP-100.upload.wait_for_upload_port=false + +Edgebox-ESP-100.serial.disableDTR=false +Edgebox-ESP-100.serial.disableRTS=false + +Edgebox-ESP-100.build.tarch=xtensa +Edgebox-ESP-100.build.bootloader_addr=0x0 +Edgebox-ESP-100.build.target=esp32s3 +Edgebox-ESP-100.build.mcu=esp32s3 +Edgebox-ESP-100.build.core=esp32 +Edgebox-ESP-100.build.variant=Edgebox-ESP-100 +Edgebox-ESP-100.build.board=Edgebox-ESP-100 + +Edgebox-ESP-100.build.usb_mode=1 +Edgebox-ESP-100.build.cdc_on_boot=0 +Edgebox-ESP-100.build.msc_on_boot=0 +Edgebox-ESP-100.build.dfu_on_boot=0 +Edgebox-ESP-100.build.f_cpu=240000000L +Edgebox-ESP-100.build.flash_size=4MB +Edgebox-ESP-100.build.flash_freq=80m +Edgebox-ESP-100.build.flash_mode=dio +Edgebox-ESP-100.build.boot=qio +Edgebox-ESP-100.build.boot_freq=80m +Edgebox-ESP-100.build.partitions=default +Edgebox-ESP-100.build.defines= +Edgebox-ESP-100.build.loop_core= +Edgebox-ESP-100.build.event_core= +Edgebox-ESP-100.build.psram_type=qspi +Edgebox-ESP-100.build.memory_type={build.boot}_{build.psram_type} + +Edgebox-ESP-100.menu.PSRAM.disabled=Disabled +Edgebox-ESP-100.menu.PSRAM.disabled.build.defines= +Edgebox-ESP-100.menu.PSRAM.disabled.build.psram_type=qspi +Edgebox-ESP-100.menu.PSRAM.enabled=QSPI PSRAM +Edgebox-ESP-100.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +Edgebox-ESP-100.menu.PSRAM.enabled.build.psram_type=qspi +Edgebox-ESP-100.menu.PSRAM.opi=OPI PSRAM +Edgebox-ESP-100.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +Edgebox-ESP-100.menu.PSRAM.opi.build.psram_type=opi + +Edgebox-ESP-100.menu.FlashMode.qio=QIO 80MHz +Edgebox-ESP-100.menu.FlashMode.qio.build.flash_mode=dio +Edgebox-ESP-100.menu.FlashMode.qio.build.boot=qio +Edgebox-ESP-100.menu.FlashMode.qio.build.boot_freq=80m +Edgebox-ESP-100.menu.FlashMode.qio.build.flash_freq=80m +Edgebox-ESP-100.menu.FlashMode.qio120=QIO 120MHz +Edgebox-ESP-100.menu.FlashMode.qio120.build.flash_mode=dio +Edgebox-ESP-100.menu.FlashMode.qio120.build.boot=qio +Edgebox-ESP-100.menu.FlashMode.qio120.build.boot_freq=120m +Edgebox-ESP-100.menu.FlashMode.qio120.build.flash_freq=80m +Edgebox-ESP-100.menu.FlashMode.dio=DIO 80MHz +Edgebox-ESP-100.menu.FlashMode.dio.build.flash_mode=dio +Edgebox-ESP-100.menu.FlashMode.dio.build.boot=dio +Edgebox-ESP-100.menu.FlashMode.dio.build.boot_freq=80m +Edgebox-ESP-100.menu.FlashMode.dio.build.flash_freq=80m +Edgebox-ESP-100.menu.FlashMode.opi=OPI 80MHz +Edgebox-ESP-100.menu.FlashMode.opi.build.flash_mode=dout +Edgebox-ESP-100.menu.FlashMode.opi.build.boot=opi +Edgebox-ESP-100.menu.FlashMode.opi.build.boot_freq=80m +Edgebox-ESP-100.menu.FlashMode.opi.build.flash_freq=80m + +Edgebox-ESP-100.menu.FlashSize.4M=4MB (32Mb) +Edgebox-ESP-100.menu.FlashSize.4M.build.flash_size=4MB +Edgebox-ESP-100.menu.FlashSize.8M=8MB (64Mb) +Edgebox-ESP-100.menu.FlashSize.8M.build.flash_size=8MB +Edgebox-ESP-100.menu.FlashSize.16M=16MB (128Mb) +Edgebox-ESP-100.menu.FlashSize.16M.build.flash_size=16MB +#Edgebox-ESP-100.menu.FlashSize.32M=32MB (256Mb) +#Edgebox-ESP-100.menu.FlashSize.32M.build.flash_size=32MB + +Edgebox-ESP-100.menu.LoopCore.1=Core 1 +Edgebox-ESP-100.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +Edgebox-ESP-100.menu.LoopCore.0=Core 0 +Edgebox-ESP-100.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +Edgebox-ESP-100.menu.EventsCore.1=Core 1 +Edgebox-ESP-100.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +Edgebox-ESP-100.menu.EventsCore.0=Core 0 +Edgebox-ESP-100.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +Edgebox-ESP-100.menu.USBMode.default=Hardware CDC and JTAG +Edgebox-ESP-100.menu.USBMode.default.build.usb_mode=1 +Edgebox-ESP-100.menu.USBMode.hwcdc=USB-OTG (TinyUSB) +Edgebox-ESP-100.menu.USBMode.hwcdc.build.usb_mode=0 + +Edgebox-ESP-100.menu.CDCOnBoot.default=Disabled +Edgebox-ESP-100.menu.CDCOnBoot.default.build.cdc_on_boot=0 +Edgebox-ESP-100.menu.CDCOnBoot.cdc=Enabled +Edgebox-ESP-100.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +Edgebox-ESP-100.menu.MSCOnBoot.default=Disabled +Edgebox-ESP-100.menu.MSCOnBoot.default.build.msc_on_boot=0 +Edgebox-ESP-100.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +Edgebox-ESP-100.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +Edgebox-ESP-100.menu.DFUOnBoot.default=Disabled +Edgebox-ESP-100.menu.DFUOnBoot.default.build.dfu_on_boot=0 +Edgebox-ESP-100.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +Edgebox-ESP-100.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +Edgebox-ESP-100.menu.UploadMode.default=UART0 / Hardware CDC +Edgebox-ESP-100.menu.UploadMode.default.upload.use_1200bps_touch=false +Edgebox-ESP-100.menu.UploadMode.default.upload.wait_for_upload_port=false +Edgebox-ESP-100.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +Edgebox-ESP-100.menu.UploadMode.cdc.upload.use_1200bps_touch=true +Edgebox-ESP-100.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +Edgebox-ESP-100.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.default.build.partitions=default +Edgebox-ESP-100.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Edgebox-ESP-100.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Edgebox-ESP-100.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +Edgebox-ESP-100.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +Edgebox-ESP-100.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.minimal.build.partitions=minimal +Edgebox-ESP-100.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.no_ota.build.partitions=no_ota +Edgebox-ESP-100.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Edgebox-ESP-100.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Edgebox-ESP-100.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Edgebox-ESP-100.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Edgebox-ESP-100.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Edgebox-ESP-100.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Edgebox-ESP-100.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.huge_app.build.partitions=huge_app +Edgebox-ESP-100.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Edgebox-ESP-100.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +Edgebox-ESP-100.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +Edgebox-ESP-100.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +Edgebox-ESP-100.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +Edgebox-ESP-100.menu.PartitionScheme.fatflash.build.partitions=ffat +Edgebox-ESP-100.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +Edgebox-ESP-100.menu.PartitionScheme.rainmaker=RainMaker 4MB +Edgebox-ESP-100.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +Edgebox-ESP-100.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +Edgebox-ESP-100.menu.CPUFreq.240=240MHz (WiFi) +Edgebox-ESP-100.menu.CPUFreq.240.build.f_cpu=240000000L +Edgebox-ESP-100.menu.CPUFreq.160=160MHz (WiFi) +Edgebox-ESP-100.menu.CPUFreq.160.build.f_cpu=160000000L +Edgebox-ESP-100.menu.CPUFreq.80=80MHz (WiFi) +Edgebox-ESP-100.menu.CPUFreq.80.build.f_cpu=80000000L +Edgebox-ESP-100.menu.CPUFreq.40=40MHz +Edgebox-ESP-100.menu.CPUFreq.40.build.f_cpu=40000000L +Edgebox-ESP-100.menu.CPUFreq.20=20MHz +Edgebox-ESP-100.menu.CPUFreq.20.build.f_cpu=20000000L +Edgebox-ESP-100.menu.CPUFreq.10=10MHz +Edgebox-ESP-100.menu.CPUFreq.10.build.f_cpu=10000000L + +Edgebox-ESP-100.menu.UploadSpeed.921600=921600 +Edgebox-ESP-100.menu.UploadSpeed.921600.upload.speed=921600 +Edgebox-ESP-100.menu.UploadSpeed.115200=115200 +Edgebox-ESP-100.menu.UploadSpeed.115200.upload.speed=115200 +Edgebox-ESP-100.menu.UploadSpeed.256000.windows=256000 +Edgebox-ESP-100.menu.UploadSpeed.256000.upload.speed=256000 +Edgebox-ESP-100.menu.UploadSpeed.230400.windows.upload.speed=256000 +Edgebox-ESP-100.menu.UploadSpeed.230400=230400 +Edgebox-ESP-100.menu.UploadSpeed.230400.upload.speed=230400 +Edgebox-ESP-100.menu.UploadSpeed.460800.linux=460800 +Edgebox-ESP-100.menu.UploadSpeed.460800.macosx=460800 +Edgebox-ESP-100.menu.UploadSpeed.460800.upload.speed=460800 +Edgebox-ESP-100.menu.UploadSpeed.512000.windows=512000 +Edgebox-ESP-100.menu.UploadSpeed.512000.upload.speed=512000 + +Edgebox-ESP-100.menu.DebugLevel.none=None +Edgebox-ESP-100.menu.DebugLevel.none.build.code_debug=0 +Edgebox-ESP-100.menu.DebugLevel.error=Error +Edgebox-ESP-100.menu.DebugLevel.error.build.code_debug=1 +Edgebox-ESP-100.menu.DebugLevel.warn=Warn +Edgebox-ESP-100.menu.DebugLevel.warn.build.code_debug=2 +Edgebox-ESP-100.menu.DebugLevel.info=Info +Edgebox-ESP-100.menu.DebugLevel.info.build.code_debug=3 +Edgebox-ESP-100.menu.DebugLevel.debug=Debug +Edgebox-ESP-100.menu.DebugLevel.debug.build.code_debug=4 +Edgebox-ESP-100.menu.DebugLevel.verbose=Verbose +Edgebox-ESP-100.menu.DebugLevel.verbose.build.code_debug=5 + +Edgebox-ESP-100.menu.EraseFlash.none=Disabled +Edgebox-ESP-100.menu.EraseFlash.none.upload.erase_cmd= +Edgebox-ESP-100.menu.EraseFlash.all=Enabled +Edgebox-ESP-100.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +crabik_slot_esp32_s3.name=Crabik Slot ESP32-S3 + +crabik_slot_esp32_s3.bootloader.tool=esptool_py +crabik_slot_esp32_s3.bootloader.tool.default=esptool_py + +crabik_slot_esp32_s3.upload.tool=esptool_py +crabik_slot_esp32_s3.upload.tool.default=esptool_py +crabik_slot_esp32_s3.upload.tool.network=esp_ota + +crabik_slot_esp32_s3.upload.maximum_size=1310720 +crabik_slot_esp32_s3.upload.maximum_data_size=327680 +crabik_slot_esp32_s3.upload.speed=921600 +crabik_slot_esp32_s3.upload.flags= +crabik_slot_esp32_s3.upload.extra_flags= +crabik_slot_esp32_s3.upload.use_1200bps_touch=false +crabik_slot_esp32_s3.upload.wait_for_upload_port=false + +crabik_slot_esp32_s3.serial.disableDTR=false +crabik_slot_esp32_s3.serial.disableRTS=false + +crabik_slot_esp32_s3.build.tarch=xtensa +crabik_slot_esp32_s3.build.bootloader_addr=0x0 +crabik_slot_esp32_s3.build.target=esp32s3 +crabik_slot_esp32_s3.build.mcu=esp32s3 +crabik_slot_esp32_s3.build.core=esp32 +crabik_slot_esp32_s3.build.variant=crabik_slot_esp32_s3 +crabik_slot_esp32_s3.build.board=CRABIK_SLOT_ESP32_S3 + +crabik_slot_esp32_s3.build.usb_mode=0 +crabik_slot_esp32_s3.build.cdc_on_boot=0 +crabik_slot_esp32_s3.build.msc_on_boot=0 +crabik_slot_esp32_s3.build.dfu_on_boot=0 +crabik_slot_esp32_s3.build.f_cpu=240000000L +crabik_slot_esp32_s3.build.flash_size=8MB +crabik_slot_esp32_s3.build.flash_freq=80m +crabik_slot_esp32_s3.build.flash_mode=dio +crabik_slot_esp32_s3.build.boot=qio +crabik_slot_esp32_s3.build.partitions=default +crabik_slot_esp32_s3.build.defines= +crabik_slot_esp32_s3.build.memory_type=qio_qspi +crabik_slot_esp32_s3.build.loop_core= +crabik_slot_esp32_s3.build.event_core= + +## IDE 2.0 Seems to not update the value +crabik_slot_esp32_s3.menu.JTAGAdapter.default=Disabled +crabik_slot_esp32_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +crabik_slot_esp32_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +crabik_slot_esp32_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +crabik_slot_esp32_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 + +crabik_slot_esp32_s3.menu.LoopCore.1=Core 1 +crabik_slot_esp32_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +crabik_slot_esp32_s3.menu.LoopCore.0=Core 0 +crabik_slot_esp32_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +crabik_slot_esp32_s3.menu.EventsCore.1=Core 1 +crabik_slot_esp32_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +crabik_slot_esp32_s3.menu.EventsCore.0=Core 0 +crabik_slot_esp32_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +crabik_slot_esp32_s3.menu.CDCOnBoot.default=Enabled (Requires Hardware CDC and JTAG Mode) +crabik_slot_esp32_s3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +crabik_slot_esp32_s3.menu.CDCOnBoot.discdc=Disabled +crabik_slot_esp32_s3.menu.CDCOnBoot.discdc.build.cdc_on_boot=0 + +crabik_slot_esp32_s3.menu.MSCOnBoot.default=Disabled +crabik_slot_esp32_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +crabik_slot_esp32_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +crabik_slot_esp32_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +crabik_slot_esp32_s3.menu.USBMode.default=Hardware CDC and JTAG +crabik_slot_esp32_s3.menu.USBMode.default.build.usb_mode=1 +crabik_slot_esp32_s3.menu.USBMode.default.build.cdc_on_boot=1 +crabik_slot_esp32_s3.menu.USBMode.usbotg=USB-OTG +crabik_slot_esp32_s3.menu.USBMode.usbotg.build.usb_mode=0 +crabik_slot_esp32_s3.menu.USBMode.usbotg.build.cdc_on_boot=0 + +crabik_slot_esp32_s3.menu.UploadMode.default=UART0 / Hardware CDC +crabik_slot_esp32_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +crabik_slot_esp32_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +crabik_slot_esp32_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +crabik_slot_esp32_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +crabik_slot_esp32_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +crabik_slot_esp32_s3.menu.CPUFreq.240=240MHz (WiFi) +crabik_slot_esp32_s3.menu.CPUFreq.240.build.f_cpu=240000000L +crabik_slot_esp32_s3.menu.CPUFreq.160=160MHz (WiFi) +crabik_slot_esp32_s3.menu.CPUFreq.160.build.f_cpu=160000000L +crabik_slot_esp32_s3.menu.CPUFreq.80=80MHz (WiFi) +crabik_slot_esp32_s3.menu.CPUFreq.80.build.f_cpu=80000000L + +crabik_slot_esp32_s3.menu.PartitionScheme.default=8M Flash (3MB APP/1.5MB FATFS) +crabik_slot_esp32_s3.menu.PartitionScheme.default.build.partitions=default_8MB +crabik_slot_esp32_s3.menu.PartitionScheme.default.upload.maximum_size=3342336 +crabik_slot_esp32_s3.menu.PartitionScheme.default_4MB=4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +crabik_slot_esp32_s3.menu.PartitionScheme.default_4MB.build.partitions=default +crabik_slot_esp32_s3.menu.PartitionScheme.defaultffat=4MB with ffat (1.2MB APP/1.5MB FATFS) +crabik_slot_esp32_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +crabik_slot_esp32_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +crabik_slot_esp32_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +crabik_slot_esp32_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 + +crabik_slot_esp32_s3.menu.UploadSpeed.921600=921600 +crabik_slot_esp32_s3.menu.UploadSpeed.921600.upload.speed=921600 +crabik_slot_esp32_s3.menu.UploadSpeed.115200=115200 +crabik_slot_esp32_s3.menu.UploadSpeed.115200.upload.speed=115200 +crabik_slot_esp32_s3.menu.UploadSpeed.256000.windows=256000 +crabik_slot_esp32_s3.menu.UploadSpeed.256000.upload.speed=256000 +crabik_slot_esp32_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +crabik_slot_esp32_s3.menu.UploadSpeed.230400=230400 +crabik_slot_esp32_s3.menu.UploadSpeed.230400.upload.speed=230400 +crabik_slot_esp32_s3.menu.UploadSpeed.460800.linux=460800 +crabik_slot_esp32_s3.menu.UploadSpeed.460800.macosx=460800 +crabik_slot_esp32_s3.menu.UploadSpeed.460800.upload.speed=460800 +crabik_slot_esp32_s3.menu.UploadSpeed.512000.windows=512000 +crabik_slot_esp32_s3.menu.UploadSpeed.512000.upload.speed=512000 + +crabik_slot_esp32_s3.menu.DebugLevel.none=None +crabik_slot_esp32_s3.menu.DebugLevel.none.build.code_debug=0 +crabik_slot_esp32_s3.menu.DebugLevel.error=Error +crabik_slot_esp32_s3.menu.DebugLevel.error.build.code_debug=1 +crabik_slot_esp32_s3.menu.DebugLevel.warn=Warn +crabik_slot_esp32_s3.menu.DebugLevel.warn.build.code_debug=2 +crabik_slot_esp32_s3.menu.DebugLevel.info=Info +crabik_slot_esp32_s3.menu.DebugLevel.info.build.code_debug=3 +crabik_slot_esp32_s3.menu.DebugLevel.debug=Debug +crabik_slot_esp32_s3.menu.DebugLevel.debug.build.code_debug=4 +crabik_slot_esp32_s3.menu.DebugLevel.verbose=Verbose +crabik_slot_esp32_s3.menu.DebugLevel.verbose.build.code_debug=5 + +crabik_slot_esp32_s3.menu.EraseFlash.none=Disabled +crabik_slot_esp32_s3.menu.EraseFlash.none.upload.erase_cmd= +crabik_slot_esp32_s3.menu.EraseFlash.all=Enabled +crabik_slot_esp32_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +nebulas3.name=Nebula S3 + +nebulas3.bootloader.tool=esptool_py +nebulas3.bootloader.tool.default=esptool_py + +nebulas3.upload.tool=esptool_py +nebulas3.upload.tool.default=esptool_py +nebulas3.upload.tool.network=esp_ota + +nebulas3.upload.maximum_size=1310720 +nebulas3.upload.maximum_data_size=327680 +nebulas3.upload.flags= +nebulas3.upload.extra_flags= +nebulas3.upload.use_1200bps_touch=false +nebulas3.upload.wait_for_upload_port=false + +nebulas3.serial.disableDTR=false +nebulas3.serial.disableRTS=false + +nebulas3.build.tarch=xtensa +nebulas3.build.bootloader_addr=0x0 +nebulas3.build.target=esp32s3 +nebulas3.build.mcu=esp32s3 +nebulas3.build.core=esp32 +nebulas3.build.variant=Nebula_S3 +nebulas3.build.board=NEBULAS3 + +nebulas3.build.usb_mode=1 +nebulas3.build.cdc_on_boot=0 +nebulas3.build.msc_on_boot=0 +nebulas3.build.dfu_on_boot=0 +nebulas3.build.f_cpu=240000000L +nebulas3.build.flash_size=4MB +nebulas3.build.flash_freq=80m +nebulas3.build.flash_mode=dio +nebulas3.build.boot=qio +nebulas3.build.boot_freq=80m +nebulas3.build.partitions=default +nebulas3.build.defines= +nebulas3.build.loop_core= +nebulas3.build.event_core= +nebulas3.build.psram_type=qspi +nebulas3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +nebulas3.menu.JTAGAdapter.default=Disabled +nebulas3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +nebulas3.menu.JTAGAdapter.builtin=Integrated USB JTAG +nebulas3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +nebulas3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +nebulas3.menu.JTAGAdapter.external=FTDI Adapter +nebulas3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +nebulas3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +nebulas3.menu.JTAGAdapter.bridge=ESP USB Bridge +nebulas3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +nebulas3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +nebulas3.menu.PSRAM.disabled=Disabled +nebulas3.menu.PSRAM.disabled.build.defines= +nebulas3.menu.PSRAM.disabled.build.psram_type=qspi +nebulas3.menu.PSRAM.enabled=QSPI PSRAM +nebulas3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +nebulas3.menu.PSRAM.enabled.build.psram_type=qspi +nebulas3.menu.PSRAM.opi=OPI PSRAM +nebulas3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +nebulas3.menu.PSRAM.opi.build.psram_type=opi + +nebulas3.menu.FlashMode.qio=QIO 80MHz +nebulas3.menu.FlashMode.qio.build.flash_mode=dio +nebulas3.menu.FlashMode.qio.build.boot=qio +nebulas3.menu.FlashMode.qio.build.boot_freq=80m +nebulas3.menu.FlashMode.qio.build.flash_freq=80m +nebulas3.menu.FlashMode.qio120=QIO 120MHz +nebulas3.menu.FlashMode.qio120.build.flash_mode=dio +nebulas3.menu.FlashMode.qio120.build.boot=qio +nebulas3.menu.FlashMode.qio120.build.boot_freq=120m +nebulas3.menu.FlashMode.qio120.build.flash_freq=80m +nebulas3.menu.FlashMode.dio=DIO 80MHz +nebulas3.menu.FlashMode.dio.build.flash_mode=dio +nebulas3.menu.FlashMode.dio.build.boot=dio +nebulas3.menu.FlashMode.dio.build.boot_freq=80m +nebulas3.menu.FlashMode.dio.build.flash_freq=80m +nebulas3.menu.FlashMode.opi=OPI 80MHz +nebulas3.menu.FlashMode.opi.build.flash_mode=dout +nebulas3.menu.FlashMode.opi.build.boot=opi +nebulas3.menu.FlashMode.opi.build.boot_freq=80m +nebulas3.menu.FlashMode.opi.build.flash_freq=80m + +nebulas3.menu.FlashSize.4M=4MB (32Mb) +nebulas3.menu.FlashSize.4M.build.flash_size=4MB +nebulas3.menu.FlashSize.8M=8MB (64Mb) +nebulas3.menu.FlashSize.8M.build.flash_size=8MB +nebulas3.menu.FlashSize.16M=16MB (128Mb) +nebulas3.menu.FlashSize.16M.build.flash_size=16MB + +nebulas3.menu.LoopCore.1=Core 1 +nebulas3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +nebulas3.menu.LoopCore.0=Core 0 +nebulas3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +nebulas3.menu.EventsCore.1=Core 1 +nebulas3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +nebulas3.menu.EventsCore.0=Core 0 +nebulas3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +nebulas3.menu.USBMode.hwcdc=Hardware CDC and JTAG +nebulas3.menu.USBMode.hwcdc.build.usb_mode=1 +nebulas3.menu.USBMode.default=USB-OTG (TinyUSB) +nebulas3.menu.USBMode.default.build.usb_mode=0 + +nebulas3.menu.CDCOnBoot.default= Enabled +nebulas3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +nebulas3.menu.CDCOnBoot.cdc=Disabled +nebulas3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +nebulas3.menu.MSCOnBoot.default=Disabled +nebulas3.menu.MSCOnBoot.default.build.msc_on_boot=0 +nebulas3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +nebulas3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +nebulas3.menu.DFUOnBoot.default=Disabled +nebulas3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +nebulas3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +nebulas3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +nebulas3.menu.UploadMode.default=UART0 / Hardware CDC +nebulas3.menu.UploadMode.default.upload.use_1200bps_touch=false +nebulas3.menu.UploadMode.default.upload.wait_for_upload_port=false +nebulas3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +nebulas3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +nebulas3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +nebulas3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +nebulas3.menu.PartitionScheme.default.build.partitions=default +nebulas3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +nebulas3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +nebulas3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +nebulas3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +nebulas3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +nebulas3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +nebulas3.menu.PartitionScheme.minimal.build.partitions=minimal +nebulas3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +nebulas3.menu.PartitionScheme.no_ota.build.partitions=no_ota +nebulas3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +nebulas3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +nebulas3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +nebulas3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +nebulas3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +nebulas3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +nebulas3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +nebulas3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +nebulas3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +nebulas3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +nebulas3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +nebulas3.menu.PartitionScheme.huge_app.build.partitions=huge_app +nebulas3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +nebulas3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +nebulas3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +nebulas3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +nebulas3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +nebulas3.menu.PartitionScheme.fatflash.build.partitions=ffat +nebulas3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +nebulas3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +nebulas3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +nebulas3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +nebulas3.menu.PartitionScheme.rainmaker=RainMaker 4MB +nebulas3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +nebulas3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +nebulas3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +nebulas3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +nebulas3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +nebulas3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +nebulas3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +nebulas3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +nebulas3.menu.CPUFreq.240=240MHz (WiFi) +nebulas3.menu.CPUFreq.240.build.f_cpu=240000000L +nebulas3.menu.CPUFreq.160=160MHz (WiFi) +nebulas3.menu.CPUFreq.160.build.f_cpu=160000000L +nebulas3.menu.CPUFreq.80=80MHz (WiFi) +nebulas3.menu.CPUFreq.80.build.f_cpu=80000000L +nebulas3.menu.CPUFreq.40=40MHz +nebulas3.menu.CPUFreq.40.build.f_cpu=40000000L +nebulas3.menu.CPUFreq.20=20MHz +nebulas3.menu.CPUFreq.20.build.f_cpu=20000000L +nebulas3.menu.CPUFreq.10=10MHz +nebulas3.menu.CPUFreq.10.build.f_cpu=10000000L + +nebulas3.menu.UploadSpeed.921600=921600 +nebulas3.menu.UploadSpeed.921600.upload.speed=921600 +nebulas3.menu.UploadSpeed.115200=115200 +nebulas3.menu.UploadSpeed.115200.upload.speed=115200 +nebulas3.menu.UploadSpeed.256000.windows=256000 +nebulas3.menu.UploadSpeed.256000.upload.speed=256000 +nebulas3.menu.UploadSpeed.230400.windows.upload.speed=256000 +nebulas3.menu.UploadSpeed.230400=230400 +nebulas3.menu.UploadSpeed.230400.upload.speed=230400 +nebulas3.menu.UploadSpeed.460800.linux=460800 +nebulas3.menu.UploadSpeed.460800.macosx=460800 +nebulas3.menu.UploadSpeed.460800.upload.speed=460800 +nebulas3.menu.UploadSpeed.512000.windows=512000 +nebulas3.menu.UploadSpeed.512000.upload.speed=512000 + +nebulas3.menu.DebugLevel.none=None +nebulas3.menu.DebugLevel.none.build.code_debug=0 +nebulas3.menu.DebugLevel.error=Error +nebulas3.menu.DebugLevel.error.build.code_debug=1 +nebulas3.menu.DebugLevel.warn=Warn +nebulas3.menu.DebugLevel.warn.build.code_debug=2 +nebulas3.menu.DebugLevel.info=Info +nebulas3.menu.DebugLevel.info.build.code_debug=3 +nebulas3.menu.DebugLevel.debug=Debug +nebulas3.menu.DebugLevel.debug.build.code_debug=4 +nebulas3.menu.DebugLevel.verbose=Verbose +nebulas3.menu.DebugLevel.verbose.build.code_debug=5 + +nebulas3.menu.EraseFlash.none=Disabled +nebulas3.menu.EraseFlash.none.upload.erase_cmd= +nebulas3.menu.EraseFlash.all=Enabled +nebulas3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +lionbits3.name=Lion:Bit S3 STEM Dev Board + +lionbits3.bootloader.tool=esptool_py +lionbits3.bootloader.tool.default=esptool_py + +lionbits3.upload.tool=esptool_py +lionbits3.upload.tool.default=esptool_py +lionbits3.upload.tool.network=esp_ota + +lionbits3.upload.maximum_size=1310720 +lionbits3.upload.maximum_data_size=327680 +lionbits3.upload.flags= +lionbits3.upload.extra_flags= +lionbits3.upload.use_1200bps_touch=false +lionbits3.upload.wait_for_upload_port=false + +lionbits3.serial.disableDTR=false +lionbits3.serial.disableRTS=false + +lionbits3.build.tarch=xtensa +lionbits3.build.bootloader_addr=0x0 +lionbits3.build.target=esp32s3 +lionbits3.build.mcu=esp32s3 +lionbits3.build.core=esp32 +lionbits3.build.variant=lionbits3 +lionbits3.build.board=LIONBITS3_DEV + + +lionbits3.build.usb_mode=1 +lionbits3.build.cdc_on_boot=0 +lionbits3.build.msc_on_boot=0 +lionbits3.build.dfu_on_boot=0 +lionbits3.build.f_cpu=240000000L +lionbits3.build.flash_size=4MB +lionbits3.build.flash_freq=80m +lionbits3.build.flash_mode=dio +lionbits3.build.boot=qio +lionbits3.build.boot_freq=80m +lionbits3.build.partitions=default +lionbits3.build.defines= +lionbits3.build.loop_core= +lionbits3.build.event_core= +lionbits3.build.psram_type=qspi +lionbits3.build.memory_type={build.boot}_{build.psram_type} + + +lionbits3.menu.JTAGAdapter.default=Disabled +lionbits3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +lionbits3.menu.JTAGAdapter.builtin=Integrated USB JTAG +lionbits3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +lionbits3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +lionbits3.menu.JTAGAdapter.external=FTDI Adapter +lionbits3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +lionbits3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +lionbits3.menu.JTAGAdapter.bridge=ESP USB Bridge +lionbits3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +lionbits3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +lionbits3.menu.PSRAM.disabled=Disabled +lionbits3.menu.PSRAM.disabled.build.defines= +lionbits3.menu.PSRAM.disabled.build.psram_type=qspi +lionbits3.menu.PSRAM.enabled=QSPI PSRAM +lionbits3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +lionbits3.menu.PSRAM.enabled.build.psram_type=qspi +lionbits3.menu.PSRAM.opi=OPI PSRAM +lionbits3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +lionbits3.menu.PSRAM.opi.build.psram_type=opi + +lionbits3.menu.FlashMode.qio=QIO 80MHz +lionbits3.menu.FlashMode.qio.build.flash_mode=dio +lionbits3.menu.FlashMode.qio.build.boot=qio +lionbits3.menu.FlashMode.qio.build.boot_freq=80m +lionbits3.menu.FlashMode.qio.build.flash_freq=80m +lionbits3.menu.FlashMode.qio120=QIO 120MHz +lionbits3.menu.FlashMode.qio120.build.flash_mode=dio +lionbits3.menu.FlashMode.qio120.build.boot=qio +lionbits3.menu.FlashMode.qio120.build.boot_freq=120m +lionbits3.menu.FlashMode.qio120.build.flash_freq=80m +lionbits3.menu.FlashMode.dio=DIO 80MHz +lionbits3.menu.FlashMode.dio.build.flash_mode=dio +lionbits3.menu.FlashMode.dio.build.boot=dio +lionbits3.menu.FlashMode.dio.build.boot_freq=80m +lionbits3.menu.FlashMode.dio.build.flash_freq=80m +lionbits3.menu.FlashMode.opi=OPI 80MHz +lionbits3.menu.FlashMode.opi.build.flash_mode=dout +lionbits3.menu.FlashMode.opi.build.boot=opi +lionbits3.menu.FlashMode.opi.build.boot_freq=80m +lionbits3.menu.FlashMode.opi.build.flash_freq=80m + +lionbits3.menu.FlashSize.4M=4MB (32Mb) +lionbits3.menu.FlashSize.4M.build.flash_size=4MB +lionbits3.menu.FlashSize.8M=8MB (64Mb) +lionbits3.menu.FlashSize.8M.build.flash_size=8MB +lionbits3.menu.FlashSize.16M=16MB (128Mb) +lionbits3.menu.FlashSize.16M.build.flash_size=16MB +#lionbits3.menu.FlashSize.32M=32MB (256Mb) +#lionbits3.menu.FlashSize.32M.build.flash_size=32MB + +lionbits3.menu.LoopCore.1=Core 1 +lionbits3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +lionbits3.menu.LoopCore.0=Core 0 +lionbits3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +lionbits3.menu.EventsCore.1=Core 1 +lionbits3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +lionbits3.menu.EventsCore.0=Core 0 +lionbits3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +lionbits3.menu.USBMode.hwcdc=Hardware CDC and JTAG +lionbits3.menu.USBMode.hwcdc.build.usb_mode=1 +lionbits3.menu.USBMode.default=USB-OTG (TinyUSB) +lionbits3.menu.USBMode.default.build.usb_mode=0 + +lionbits3.menu.CDCOnBoot.default=Disabled +lionbits3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +lionbits3.menu.CDCOnBoot.cdc=Enabled +lionbits3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +lionbits3.menu.MSCOnBoot.default=Disabled +lionbits3.menu.MSCOnBoot.default.build.msc_on_boot=0 +lionbits3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +lionbits3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +lionbits3.menu.DFUOnBoot.default=Disabled +lionbits3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +lionbits3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +lionbits3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +lionbits3.menu.UploadMode.default=UART0 / Hardware CDC +lionbits3.menu.UploadMode.default.upload.use_1200bps_touch=false +lionbits3.menu.UploadMode.default.upload.wait_for_upload_port=false +lionbits3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +lionbits3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +lionbits3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +lionbits3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +lionbits3.menu.PartitionScheme.default.build.partitions=default +lionbits3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +lionbits3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +lionbits3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +lionbits3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +lionbits3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +lionbits3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +lionbits3.menu.PartitionScheme.minimal.build.partitions=minimal +lionbits3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +lionbits3.menu.PartitionScheme.no_ota.build.partitions=no_ota +lionbits3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +lionbits3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +lionbits3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +lionbits3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +lionbits3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +lionbits3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +lionbits3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +lionbits3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +lionbits3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +lionbits3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +lionbits3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +lionbits3.menu.PartitionScheme.huge_app.build.partitions=huge_app +lionbits3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +lionbits3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +lionbits3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +lionbits3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +lionbits3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +lionbits3.menu.PartitionScheme.fatflash.build.partitions=ffat +lionbits3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +lionbits3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +lionbits3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +lionbits3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +lionbits3.menu.PartitionScheme.rainmaker=RainMaker 4MB +lionbits3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +lionbits3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +lionbits3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +lionbits3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +lionbits3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +lionbits3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +lionbits3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +lionbits3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +lionbits3.menu.CPUFreq.240=240MHz (WiFi) +lionbits3.menu.CPUFreq.240.build.f_cpu=240000000L +lionbits3.menu.CPUFreq.160=160MHz (WiFi) +lionbits3.menu.CPUFreq.160.build.f_cpu=160000000L +lionbits3.menu.CPUFreq.80=80MHz (WiFi) +lionbits3.menu.CPUFreq.80.build.f_cpu=80000000L +lionbits3.menu.CPUFreq.40=40MHz +lionbits3.menu.CPUFreq.40.build.f_cpu=40000000L +lionbits3.menu.CPUFreq.20=20MHz +lionbits3.menu.CPUFreq.20.build.f_cpu=20000000L +lionbits3.menu.CPUFreq.10=10MHz +lionbits3.menu.CPUFreq.10.build.f_cpu=10000000L + +lionbits3.menu.UploadSpeed.921600=921600 +lionbits3.menu.UploadSpeed.921600.upload.speed=921600 +lionbits3.menu.UploadSpeed.115200=115200 +lionbits3.menu.UploadSpeed.115200.upload.speed=115200 +lionbits3.menu.UploadSpeed.256000.windows=256000 +lionbits3.menu.UploadSpeed.256000.upload.speed=256000 +lionbits3.menu.UploadSpeed.230400.windows.upload.speed=256000 +lionbits3.menu.UploadSpeed.230400=230400 +lionbits3.menu.UploadSpeed.230400.upload.speed=230400 +lionbits3.menu.UploadSpeed.460800.linux=460800 +lionbits3.menu.UploadSpeed.460800.macosx=460800 +lionbits3.menu.UploadSpeed.460800.upload.speed=460800 +lionbits3.menu.UploadSpeed.512000.windows=512000 +lionbits3.menu.UploadSpeed.512000.upload.speed=512000 + +lionbits3.menu.DebugLevel.none=None +lionbits3.menu.DebugLevel.none.build.code_debug=0 +lionbits3.menu.DebugLevel.error=Error +lionbits3.menu.DebugLevel.error.build.code_debug=1 +lionbits3.menu.DebugLevel.warn=Warn +lionbits3.menu.DebugLevel.warn.build.code_debug=2 +lionbits3.menu.DebugLevel.info=Info +lionbits3.menu.DebugLevel.info.build.code_debug=3 +lionbits3.menu.DebugLevel.debug=Debug +lionbits3.menu.DebugLevel.debug.build.code_debug=4 +lionbits3.menu.DebugLevel.verbose=Verbose +lionbits3.menu.DebugLevel.verbose.build.code_debug=5 + +lionbits3.menu.EraseFlash.none=Disabled +lionbits3.menu.EraseFlash.none.upload.erase_cmd= +lionbits3.menu.EraseFlash.all=Enabled +lionbits3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +gen4-ESP32-S3R8n16.name=4D Systems gen4-ESP32 Modules (ESP32-S3) + +gen4-ESP32-S3R8n16.bootloader.tool=esptool_py +gen4-ESP32-S3R8n16.bootloader.tool.default=esptool_py + +gen4-ESP32-S3R8n16.upload.tool=esptool_py +gen4-ESP32-S3R8n16.upload.tool.default=esptool_py +gen4-ESP32-S3R8n16.upload.tool.network=esp_ota + +gen4-ESP32-S3R8n16.upload.maximum_size=1310720 +gen4-ESP32-S3R8n16.upload.maximum_data_size=327680 +gen4-ESP32-S3R8n16.upload.flags= +gen4-ESP32-S3R8n16.upload.extra_flags= +gen4-ESP32-S3R8n16.upload.use_1200bps_touch=false +gen4-ESP32-S3R8n16.upload.wait_for_upload_port=false + +gen4-ESP32-S3R8n16.serial.disableDTR=false +gen4-ESP32-S3R8n16.serial.disableRTS=false + +gen4-ESP32-S3R8n16.build.tarch=xtensa +gen4-ESP32-S3R8n16.build.bootloader_addr=0x0 +gen4-ESP32-S3R8n16.build.target=esp32s3 +gen4-ESP32-S3R8n16.build.mcu=esp32s3 +gen4-ESP32-S3R8n16.build.core=esp32 +gen4-ESP32-S3R8n16.build.variant=esp32_s3r8n16 +gen4-ESP32-S3R8n16.build.board=ESP32_S3R8N16 + +gen4-ESP32-S3R8n16.build.usb_mode=1 +gen4-ESP32-S3R8n16.build.cdc_on_boot=1 +gen4-ESP32-S3R8n16.build.msc_on_boot=0 +gen4-ESP32-S3R8n16.build.dfu_on_boot=0 +gen4-ESP32-S3R8n16.build.f_cpu=240000000L +gen4-ESP32-S3R8n16.build.flash_size=16MB (128Mb) +gen4-ESP32-S3R8n16.build.flash_freq=80m +gen4-ESP32-S3R8n16.build.flash_mode=dio +gen4-ESP32-S3R8n16.build.boot=qio +gen4-ESP32-S3R8n16.build.boot_freq=80m +gen4-ESP32-S3R8n16.build.partitions=default +gen4-ESP32-S3R8n16.build.defines=-DBOARD_HAS_PSRAM -D{build.board} -D{build.DisplayModel} +gen4-ESP32-S3R8n16.build.loop_core= +gen4-ESP32-S3R8n16.build.event_core= +gen4-ESP32-S3R8n16.build.psram_type=opi +gen4-ESP32-S3R8n16.build.memory_type={build.boot}_{build.psram_type} + + +gen4-ESP32-S3R8n16.menu.FlashSize.16M=16MB (128Mb) +gen4-ESP32-S3R8n16.menu.FlashSize.16M.build.flash_size=16MB +gen4-ESP32-S3R8n16.menu.FlashSize.32M=32MB (256Mb) +gen4-ESP32-S3R8n16.menu.FlashSize.32M.build.flash_size=32MB + +gen4-ESP32-S3R8n16.menu.LoopCore.1=Core 1 +gen4-ESP32-S3R8n16.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +gen4-ESP32-S3R8n16.menu.LoopCore.0=Core 0 +gen4-ESP32-S3R8n16.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +gen4-ESP32-S3R8n16.menu.EventsCore.1=Core 1 +gen4-ESP32-S3R8n16.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +gen4-ESP32-S3R8n16.menu.EventsCore.0=Core 0 +gen4-ESP32-S3R8n16.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +gen4-ESP32-S3R8n16.menu.USBMode.default=Hardware CDC and JTAG +gen4-ESP32-S3R8n16.menu.USBMode.default.build.usb_mode=1 +gen4-ESP32-S3R8n16.menu.USBMode.hwcdc=USB-OTG (TinyUSB) +gen4-ESP32-S3R8n16.menu.USBMode.hwcdc.build.usb_mode=0 + +gen4-ESP32-S3R8n16.menu.CDCOnBoot.cdc=Enabled +gen4-ESP32-S3R8n16.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +gen4-ESP32-S3R8n16.menu.CDCOnBoot.default=Disabled +gen4-ESP32-S3R8n16.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +gen4-ESP32-S3R8n16.menu.MSCOnBoot.default=Disabled +gen4-ESP32-S3R8n16.menu.MSCOnBoot.default.build.msc_on_boot=0 +gen4-ESP32-S3R8n16.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +gen4-ESP32-S3R8n16.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +gen4-ESP32-S3R8n16.menu.DFUOnBoot.default=Disabled +gen4-ESP32-S3R8n16.menu.DFUOnBoot.default.build.dfu_on_boot=0 +gen4-ESP32-S3R8n16.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +gen4-ESP32-S3R8n16.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +gen4-ESP32-S3R8n16.menu.UploadMode.default=UART0 / Hardware CDC +gen4-ESP32-S3R8n16.menu.UploadMode.default.upload.use_1200bps_touch=false +gen4-ESP32-S3R8n16.menu.UploadMode.default.upload.wait_for_upload_port=false +gen4-ESP32-S3R8n16.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +gen4-ESP32-S3R8n16.menu.UploadMode.cdc.upload.use_1200bps_touch=true +gen4-ESP32-S3R8n16.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1=Small App w/ OTA + Huge FS (2MB APP/2MB OTA/12MB SPIFFS) +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1.build.custom_partitions=gen4esp32_2MBapp_2MBota_12MBspiffs +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1.upload.maximum_size=2097152 +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2=Medium App w/ OTA + Large FS (4MB APP/4MB OTA/7MB SPIFFS) +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2.build.custom_partitions=gen4esp32_4MBapp_4MBota_7MBspiffs +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2.upload.maximum_size=4718592 +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3=Large App w/ OTA (8MB APP/8MB OTA) +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3.build.custom_partitions=gen4esp32_8MBapp_8MBota +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3.upload.maximum_size=8323072 +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4=Huge App (16MB APP) +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4.build.custom_partitions=gen4esp32_16MBapp +gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4.upload.maximum_size=16646144 +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +gen4-ESP32-S3R8n16.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +gen4-ESP32-S3R8n16.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +gen4-ESP32-S3R8n16.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +gen4-ESP32-S3R8n16.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 + +gen4-ESP32-S3R8n16.menu.CPUFreq.240=240MHz (WiFi) +gen4-ESP32-S3R8n16.menu.CPUFreq.240.build.f_cpu=240000000L +gen4-ESP32-S3R8n16.menu.CPUFreq.160=160MHz (WiFi) +gen4-ESP32-S3R8n16.menu.CPUFreq.160.build.f_cpu=160000000L +gen4-ESP32-S3R8n16.menu.CPUFreq.80=80MHz (WiFi) +gen4-ESP32-S3R8n16.menu.CPUFreq.80.build.f_cpu=80000000L +gen4-ESP32-S3R8n16.menu.CPUFreq.40=40MHz +gen4-ESP32-S3R8n16.menu.CPUFreq.40.build.f_cpu=40000000L +gen4-ESP32-S3R8n16.menu.CPUFreq.20=20MHz +gen4-ESP32-S3R8n16.menu.CPUFreq.20.build.f_cpu=20000000L +gen4-ESP32-S3R8n16.menu.CPUFreq.10=10MHz +gen4-ESP32-S3R8n16.menu.CPUFreq.10.build.f_cpu=10000000L + +gen4-ESP32-S3R8n16.menu.UploadSpeed.921600=921600 +gen4-ESP32-S3R8n16.menu.UploadSpeed.921600.upload.speed=921600 +gen4-ESP32-S3R8n16.menu.UploadSpeed.115200=115200 +gen4-ESP32-S3R8n16.menu.UploadSpeed.115200.upload.speed=115200 +gen4-ESP32-S3R8n16.menu.UploadSpeed.256000.windows=256000 +gen4-ESP32-S3R8n16.menu.UploadSpeed.256000.upload.speed=256000 +gen4-ESP32-S3R8n16.menu.UploadSpeed.230400.windows.upload.speed=256000 +gen4-ESP32-S3R8n16.menu.UploadSpeed.230400=230400 +gen4-ESP32-S3R8n16.menu.UploadSpeed.230400.upload.speed=230400 +gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.linux=460800 +gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.macosx=460800 +gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.upload.speed=460800 +gen4-ESP32-S3R8n16.menu.UploadSpeed.512000.windows=512000 +gen4-ESP32-S3R8n16.menu.UploadSpeed.512000.upload.speed=512000 + +gen4-ESP32-S3R8n16.menu.DebugLevel.none=None +gen4-ESP32-S3R8n16.menu.DebugLevel.none.build.code_debug=0 +gen4-ESP32-S3R8n16.menu.DebugLevel.error=Error +gen4-ESP32-S3R8n16.menu.DebugLevel.error.build.code_debug=1 +gen4-ESP32-S3R8n16.menu.DebugLevel.warn=Warn +gen4-ESP32-S3R8n16.menu.DebugLevel.warn.build.code_debug=2 +gen4-ESP32-S3R8n16.menu.DebugLevel.info=Info +gen4-ESP32-S3R8n16.menu.DebugLevel.info.build.code_debug=3 +gen4-ESP32-S3R8n16.menu.DebugLevel.debug=Debug +gen4-ESP32-S3R8n16.menu.DebugLevel.debug.build.code_debug=4 +gen4-ESP32-S3R8n16.menu.DebugLevel.verbose=Verbose +gen4-ESP32-S3R8n16.menu.DebugLevel.verbose.build.code_debug=5 + +gen4-ESP32-S3R8n16.menu.EraseFlash.none=Disabled +gen4-ESP32-S3R8n16.menu.EraseFlash.none.upload.erase_cmd= +gen4-ESP32-S3R8n16.menu.EraseFlash.all=Enabled +gen4-ESP32-S3R8n16.menu.EraseFlash.all.upload.erase_cmd=-e + +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24=gen4-ESP32-24 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24.build.DisplayModel=ESP32S3_24 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24t=gen4-ESP32-24T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24t.build.DisplayModel=ESP32S3_24T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24ct=gen4-ESP32-24CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24ct.build.DisplayModel=ESP32S3_24CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24ct_clb=gen4-ESP32-24CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_24ct_clb.build.DisplayModel=ESP32S3_24CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28=gen4-ESP32-28 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28.build.DisplayModel=ESP32S3_28 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28t=gen4-ESP32-28T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28t.build.DisplayModel=ESP32S3_28T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28ct=gen4-ESP32-28CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28ct.build.DisplayModel=ESP32S3_28CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28ct_clb=gen4-ESP32-28CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_28ct_clb.build.DisplayModel=ESP32S3_28CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32=gen4-ESP32-32 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32.build.DisplayModel=ESP32S3_32 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32t=gen4-ESP32-32T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32t.build.DisplayModel=ESP32S3_32T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32ct=gen4-ESP32-32CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32ct.build.DisplayModel=ESP32S3_32CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32ct_clb=gen4-ESP32-32CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_32ct_clb.build.DisplayModel=ESP32S3_32CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35=gen4-ESP32-35 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35.build.DisplayModel=ESP32S3_35 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35t=gen4-ESP32-35T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35t.build.DisplayModel=ESP32S3_35T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35ct=gen4-ESP32-35CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35ct.build.DisplayModel=ESP32S3_35CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35ct_clb=gen4-ESP32-35CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_35ct_clb.build.DisplayModel=ESP32S3_35CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43_qspi=gen4-ESP32Q-43 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43_qspi.build.DisplayModel=ESP32S3_Q43 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43t_qspi=gen4-ESP32Q-43T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43t_qspi.build.DisplayModel=ESP32S3_Q43T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_qspi=gen4-ESP32Q-43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_qspi.build.DisplayModel=ESP32S3_Q43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_clb_qspi=gen4-ESP32Q-43CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_clb_qspi.build.DisplayModel=ESP32S3_Q43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43=gen4-ESP32-43 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43.build.DisplayModel=ESP32S3_43 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43t=gen4-ESP32-43T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43t.build.DisplayModel=ESP32S3_43T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct=gen4-ESP32-43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct.build.DisplayModel=ESP32S3_43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_clb=gen4-ESP32-43CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_43ct_clb.build.DisplayModel=ESP32S3_43CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50=gen4-ESP32-50 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50.build.DisplayModel=ESP32S3_50 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50t=gen4-ESP32-50T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50t.build.DisplayModel=ESP32S3_50T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50ct=gen4-ESP32-50CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50ct.build.DisplayModel=ESP32S3_50CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50ct_clb=gen4-ESP32-50CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_50ct_clb.build.DisplayModel=ESP32S3_50CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70=gen4-ESP32-70 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70.build.DisplayModel=ESP32S3_70 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70t=gen4-ESP32-70T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70t.build.DisplayModel=ESP32S3_70T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70ct=gen4-ESP32-70CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70ct.build.DisplayModel=ESP32S3_70CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70ct_clb=gen4-ESP32-70CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_70ct_clb.build.DisplayModel=ESP32S3_70CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90=ESP32-90 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90.build.DisplayModel=ESP32S3_90 +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90t=ESP32-90T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90t.build.DisplayModel=ESP32S3_90T +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90ct=ESP32-90CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90ct.build.DisplayModel=ESP32S3_90CT +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90ct_clb=ESP32-90CT-CLB +gen4-ESP32-S3R8n16.menu.DisplayModel.esp32s3_90ct_clb.build.DisplayModel=ESP32S3_90CT + + +############################################################## +# Namino Rosso + +namino_rosso.name=Namino Rosso + +namino_rosso.bootloader.tool=esptool_py +namino_rosso.bootloader.tool.default=esptool_py + +namino_rosso.upload.tool=esptool_py +namino_rosso.upload.tool.default=esptool_py +namino_rosso.upload.tool.network=esp_ota + +namino_rosso.upload.maximum_size=1310720 +namino_rosso.upload.maximum_data_size=327680 +namino_rosso.upload.flags= +namino_rosso.upload.extra_flags= +namino_rosso.upload.use_1200bps_touch=true +namino_rosso.upload.wait_for_upload_port=true + +namino_rosso.serial.disableDTR=false +namino_rosso.serial.disableRTS=false + +namino_rosso.build.tarch=xtensa +namino_rosso.build.bootloader_addr=0x0 +namino_rosso.build.target=esp32s3 +namino_rosso.build.mcu=esp32s3 +namino_rosso.build.core=esp32 +namino_rosso.build.variant=namino_rosso +namino_rosso.build.board=NAMINO_ROSSO + +namino_rosso.build.usb_mode=0 +namino_rosso.build.cdc_on_boot=1 +namino_rosso.build.msc_on_boot=0 +namino_rosso.build.dfu_on_boot=0 +namino_rosso.build.f_cpu=240000000L +namino_rosso.build.flash_size=4MB +namino_rosso.build.flash_freq=80m +namino_rosso.build.flash_mode=dio +namino_rosso.build.boot=qio +namino_rosso.build.partitions=default +namino_rosso.build.defines= +namino_rosso.build.loop_core= +namino_rosso.build.event_core= +namino_rosso.build.flash_type=qio +namino_rosso.build.psram_type=qspi +namino_rosso.build.memory_type={build.flash_type}_{build.psram_type} + +namino_rosso.menu.LoopCore.1=Core 1 +namino_rosso.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +namino_rosso.menu.LoopCore.0=Core 0 +namino_rosso.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +namino_rosso.menu.EventsCore.1=Core 1 +namino_rosso.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +namino_rosso.menu.EventsCore.0=Core 0 +namino_rosso.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +namino_rosso.menu.USBMode.default=USB-OTG (TinyUSB) +namino_rosso.menu.USBMode.default.build.usb_mode=0 +namino_rosso.menu.USBMode.hwcdc=Hardware CDC and JTAG +namino_rosso.menu.USBMode.hwcdc.build.usb_mode=1 + +namino_rosso.menu.CDCOnBoot.cdc=Enabled +namino_rosso.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +namino_rosso.menu.CDCOnBoot.default=Disabled +namino_rosso.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +namino_rosso.menu.MSCOnBoot.default=Disabled +namino_rosso.menu.MSCOnBoot.default.build.msc_on_boot=0 +namino_rosso.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +namino_rosso.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +namino_rosso.menu.DFUOnBoot.default=Disabled +namino_rosso.menu.DFUOnBoot.default.build.dfu_on_boot=0 +namino_rosso.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +namino_rosso.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +namino_rosso.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +namino_rosso.menu.UploadMode.cdc.upload.use_1200bps_touch=true +namino_rosso.menu.UploadMode.cdc.upload.wait_for_upload_port=true +namino_rosso.menu.UploadMode.default=UART0 / Hardware CDC +namino_rosso.menu.UploadMode.default.upload.use_1200bps_touch=false +namino_rosso.menu.UploadMode.default.upload.wait_for_upload_port=false + +namino_rosso.menu.PSRAM.disabled=Disabled +namino_rosso.menu.PSRAM.disabled.build.defines= +namino_rosso.menu.PSRAM.disabled.build.psram_type=qspi +namino_rosso.menu.PSRAM.enabled=QSPI PSRAM +namino_rosso.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +namino_rosso.menu.PSRAM.enabled.build.psram_type=qspi +namino_rosso.menu.PSRAM.opi=OPI PSRAM +namino_rosso.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +namino_rosso.menu.PSRAM.opi.build.psram_type=opi + +namino_rosso.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +namino_rosso.menu.PartitionScheme.default.build.partitions=default +namino_rosso.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +namino_rosso.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +namino_rosso.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +namino_rosso.menu.PartitionScheme.minimal.build.partitions=minimal +namino_rosso.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +namino_rosso.menu.PartitionScheme.no_ota.build.partitions=no_ota +namino_rosso.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +namino_rosso.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +namino_rosso.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +namino_rosso.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +namino_rosso.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +namino_rosso.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +namino_rosso.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +namino_rosso.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +namino_rosso.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +namino_rosso.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +namino_rosso.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +namino_rosso.menu.PartitionScheme.huge_app.build.partitions=huge_app +namino_rosso.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +namino_rosso.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +namino_rosso.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +namino_rosso.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +namino_rosso.menu.CPUFreq.240=240MHz (WiFi) +namino_rosso.menu.CPUFreq.240.build.f_cpu=240000000L +namino_rosso.menu.CPUFreq.160=160MHz (WiFi) +namino_rosso.menu.CPUFreq.160.build.f_cpu=160000000L +namino_rosso.menu.CPUFreq.80=80MHz (WiFi) +namino_rosso.menu.CPUFreq.80.build.f_cpu=80000000L +namino_rosso.menu.CPUFreq.40=40MHz +namino_rosso.menu.CPUFreq.40.build.f_cpu=40000000L +namino_rosso.menu.CPUFreq.20=20MHz +namino_rosso.menu.CPUFreq.20.build.f_cpu=20000000L +namino_rosso.menu.CPUFreq.10=10MHz +namino_rosso.menu.CPUFreq.10.build.f_cpu=10000000L + +namino_rosso.menu.FlashMode.qio=QIO 80MHz +namino_rosso.menu.FlashMode.qio.build.flash_mode=dio +namino_rosso.menu.FlashMode.qio.build.boot=qio +namino_rosso.menu.FlashMode.qio.build.boot_freq=80m +namino_rosso.menu.FlashMode.qio.build.flash_freq=80m +namino_rosso.menu.FlashMode.qio120=QIO 120MHz +namino_rosso.menu.FlashMode.qio120.build.flash_mode=dio +namino_rosso.menu.FlashMode.qio120.build.boot=qio +namino_rosso.menu.FlashMode.qio120.build.boot_freq=120m +namino_rosso.menu.FlashMode.qio120.build.flash_freq=80m +namino_rosso.menu.FlashMode.dio=DIO 80MHz +namino_rosso.menu.FlashMode.dio.build.flash_mode=dio +namino_rosso.menu.FlashMode.dio.build.boot=dio +namino_rosso.menu.FlashMode.dio.build.boot_freq=80m +namino_rosso.menu.FlashMode.dio.build.flash_freq=80m +namino_rosso.menu.FlashMode.opi=OPI 80MHz +namino_rosso.menu.FlashMode.opi.build.flash_mode=dout +namino_rosso.menu.FlashMode.opi.build.boot=opi +namino_rosso.menu.FlashMode.opi.build.boot_freq=80m +namino_rosso.menu.FlashMode.opi.build.flash_freq=80m + +namino_rosso.menu.FlashSize.4M=4MB (32Mb) +namino_rosso.menu.FlashSize.4M.build.flash_size=4MB + +namino_rosso.menu.UploadSpeed.921600=921600 +namino_rosso.menu.UploadSpeed.921600.upload.speed=921600 +namino_rosso.menu.UploadSpeed.115200=115200 +namino_rosso.menu.UploadSpeed.115200.upload.speed=115200 +namino_rosso.menu.UploadSpeed.256000.windows=256000 +namino_rosso.menu.UploadSpeed.256000.upload.speed=256000 +namino_rosso.menu.UploadSpeed.230400.windows.upload.speed=256000 +namino_rosso.menu.UploadSpeed.230400=230400 +namino_rosso.menu.UploadSpeed.230400.upload.speed=230400 +namino_rosso.menu.UploadSpeed.460800.linux=460800 +namino_rosso.menu.UploadSpeed.460800.macosx=460800 +namino_rosso.menu.UploadSpeed.460800.upload.speed=460800 +namino_rosso.menu.UploadSpeed.512000.windows=512000 +namino_rosso.menu.UploadSpeed.512000.upload.speed=512000 + +namino_rosso.menu.DebugLevel.none=None +namino_rosso.menu.DebugLevel.none.build.code_debug=0 +namino_rosso.menu.DebugLevel.error=Error +namino_rosso.menu.DebugLevel.error.build.code_debug=1 +namino_rosso.menu.DebugLevel.warn=Warn +namino_rosso.menu.DebugLevel.warn.build.code_debug=2 +namino_rosso.menu.DebugLevel.info=Info +namino_rosso.menu.DebugLevel.info.build.code_debug=3 +namino_rosso.menu.DebugLevel.debug=Debug +namino_rosso.menu.DebugLevel.debug.build.code_debug=4 +namino_rosso.menu.DebugLevel.verbose=Verbose +namino_rosso.menu.DebugLevel.verbose.build.code_debug=5 + +namino_rosso.menu.EraseFlash.none=Disabled +namino_rosso.menu.EraseFlash.none.upload.erase_cmd= +namino_rosso.menu.EraseFlash.all=Enabled +namino_rosso.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Namino Arancio + +namino_arancio.name=Namino Arancio + +namino_arancio.bootloader.tool=esptool_py +namino_arancio.bootloader.tool.default=esptool_py + +namino_arancio.upload.tool=esptool_py +namino_arancio.upload.tool.default=esptool_py +namino_arancio.upload.tool.network=esp_ota + +namino_arancio.upload.maximum_size=1310720 +namino_arancio.upload.maximum_data_size=327680 +namino_arancio.upload.flags= +namino_arancio.upload.extra_flags= +namino_arancio.upload.use_1200bps_touch=true +namino_arancio.upload.wait_for_upload_port=true + +namino_arancio.serial.disableDTR=false +namino_arancio.serial.disableRTS=false + +namino_arancio.build.tarch=xtensa +namino_arancio.build.bootloader_addr=0x0 +namino_arancio.build.target=esp32s3 +namino_arancio.build.mcu=esp32s3 +namino_arancio.build.core=esp32 +namino_arancio.build.variant=namino_arancio +namino_arancio.build.board=NAMINO_ARANCIO + +namino_arancio.build.usb_mode=0 +namino_arancio.build.cdc_on_boot=1 +namino_arancio.build.msc_on_boot=0 +namino_arancio.build.dfu_on_boot=0 +namino_arancio.build.f_cpu=240000000L +namino_arancio.build.flash_size=4MB +namino_arancio.build.flash_freq=80m +namino_arancio.build.flash_mode=dio +namino_arancio.build.boot=qio +namino_arancio.build.partitions=default +namino_arancio.build.defines= +namino_arancio.build.loop_core= +namino_arancio.build.event_core= +namino_arancio.build.flash_type=qio +namino_arancio.build.psram_type=qspi +namino_arancio.build.memory_type={build.flash_type}_{build.psram_type} + +namino_arancio.menu.LoopCore.1=Core 1 +namino_arancio.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +namino_arancio.menu.LoopCore.0=Core 0 +namino_arancio.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +namino_arancio.menu.EventsCore.1=Core 1 +namino_arancio.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +namino_arancio.menu.EventsCore.0=Core 0 +namino_arancio.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +namino_arancio.menu.USBMode.default=USB-OTG (TinyUSB) +namino_arancio.menu.USBMode.default.build.usb_mode=0 +namino_arancio.menu.USBMode.hwcdc=Hardware CDC and JTAG +namino_arancio.menu.USBMode.hwcdc.build.usb_mode=1 + +namino_arancio.menu.CDCOnBoot.cdc=Enabled +namino_arancio.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +namino_arancio.menu.CDCOnBoot.default=Disabled +namino_arancio.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +namino_arancio.menu.MSCOnBoot.default=Disabled +namino_arancio.menu.MSCOnBoot.default.build.msc_on_boot=0 +namino_arancio.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +namino_arancio.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +namino_arancio.menu.DFUOnBoot.default=Disabled +namino_arancio.menu.DFUOnBoot.default.build.dfu_on_boot=0 +namino_arancio.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +namino_arancio.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +namino_arancio.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +namino_arancio.menu.UploadMode.cdc.upload.use_1200bps_touch=true +namino_arancio.menu.UploadMode.cdc.upload.wait_for_upload_port=true +namino_arancio.menu.UploadMode.default=UART0 / Hardware CDC +namino_arancio.menu.UploadMode.default.upload.use_1200bps_touch=false +namino_arancio.menu.UploadMode.default.upload.wait_for_upload_port=false + +namino_arancio.menu.PSRAM.disabled=Disabled +namino_arancio.menu.PSRAM.disabled.build.defines= +namino_arancio.menu.PSRAM.disabled.build.psram_type=qspi +namino_arancio.menu.PSRAM.enabled=QSPI PSRAM +namino_arancio.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +namino_arancio.menu.PSRAM.enabled.build.psram_type=qspi +namino_arancio.menu.PSRAM.opi=OPI PSRAM +namino_arancio.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +namino_arancio.menu.PSRAM.opi.build.psram_type=opi + +namino_arancio.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +namino_arancio.menu.PartitionScheme.default.build.partitions=default +namino_arancio.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +namino_arancio.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +namino_arancio.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +namino_arancio.menu.PartitionScheme.minimal.build.partitions=minimal +namino_arancio.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +namino_arancio.menu.PartitionScheme.no_ota.build.partitions=no_ota +namino_arancio.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +namino_arancio.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +namino_arancio.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +namino_arancio.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +namino_arancio.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +namino_arancio.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +namino_arancio.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +namino_arancio.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +namino_arancio.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +namino_arancio.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +namino_arancio.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +namino_arancio.menu.PartitionScheme.huge_app.build.partitions=huge_app +namino_arancio.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +namino_arancio.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +namino_arancio.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +namino_arancio.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +namino_arancio.menu.CPUFreq.240=240MHz (WiFi) +namino_arancio.menu.CPUFreq.240.build.f_cpu=240000000L +namino_arancio.menu.CPUFreq.160=160MHz (WiFi) +namino_arancio.menu.CPUFreq.160.build.f_cpu=160000000L +namino_arancio.menu.CPUFreq.80=80MHz (WiFi) +namino_arancio.menu.CPUFreq.80.build.f_cpu=80000000L +namino_arancio.menu.CPUFreq.40=40MHz +namino_arancio.menu.CPUFreq.40.build.f_cpu=40000000L +namino_arancio.menu.CPUFreq.20=20MHz +namino_arancio.menu.CPUFreq.20.build.f_cpu=20000000L +namino_arancio.menu.CPUFreq.10=10MHz +namino_arancio.menu.CPUFreq.10.build.f_cpu=10000000L + +namino_arancio.menu.FlashMode.qio=QIO 80MHz +namino_arancio.menu.FlashMode.qio.build.flash_mode=dio +namino_arancio.menu.FlashMode.qio.build.boot=qio +namino_arancio.menu.FlashMode.qio.build.boot_freq=80m +namino_arancio.menu.FlashMode.qio.build.flash_freq=80m +namino_arancio.menu.FlashMode.qio120=QIO 120MHz +namino_arancio.menu.FlashMode.qio120.build.flash_mode=dio +namino_arancio.menu.FlashMode.qio120.build.boot=qio +namino_arancio.menu.FlashMode.qio120.build.boot_freq=120m +namino_arancio.menu.FlashMode.qio120.build.flash_freq=80m +namino_arancio.menu.FlashMode.dio=DIO 80MHz +namino_arancio.menu.FlashMode.dio.build.flash_mode=dio +namino_arancio.menu.FlashMode.dio.build.boot=dio +namino_arancio.menu.FlashMode.dio.build.boot_freq=80m +namino_arancio.menu.FlashMode.dio.build.flash_freq=80m +namino_arancio.menu.FlashMode.opi=OPI 80MHz +namino_arancio.menu.FlashMode.opi.build.flash_mode=dout +namino_arancio.menu.FlashMode.opi.build.boot=opi +namino_arancio.menu.FlashMode.opi.build.boot_freq=80m +namino_arancio.menu.FlashMode.opi.build.flash_freq=80m + +namino_arancio.menu.FlashSize.4M=4MB (32Mb) +namino_arancio.menu.FlashSize.4M.build.flash_size=4MB + +namino_arancio.menu.UploadSpeed.921600=921600 +namino_arancio.menu.UploadSpeed.921600.upload.speed=921600 +namino_arancio.menu.UploadSpeed.115200=115200 +namino_arancio.menu.UploadSpeed.115200.upload.speed=115200 +namino_arancio.menu.UploadSpeed.256000.windows=256000 +namino_arancio.menu.UploadSpeed.256000.upload.speed=256000 +namino_arancio.menu.UploadSpeed.230400.windows.upload.speed=256000 +namino_arancio.menu.UploadSpeed.230400=230400 +namino_arancio.menu.UploadSpeed.230400.upload.speed=230400 +namino_arancio.menu.UploadSpeed.460800.linux=460800 +namino_arancio.menu.UploadSpeed.460800.macosx=460800 +namino_arancio.menu.UploadSpeed.460800.upload.speed=460800 +namino_arancio.menu.UploadSpeed.512000.windows=512000 +namino_arancio.menu.UploadSpeed.512000.upload.speed=512000 + +namino_arancio.menu.DebugLevel.none=None +namino_arancio.menu.DebugLevel.none.build.code_debug=0 +namino_arancio.menu.DebugLevel.error=Error +namino_arancio.menu.DebugLevel.error.build.code_debug=1 +namino_arancio.menu.DebugLevel.warn=Warn +namino_arancio.menu.DebugLevel.warn.build.code_debug=2 +namino_arancio.menu.DebugLevel.info=Info +namino_arancio.menu.DebugLevel.info.build.code_debug=3 +namino_arancio.menu.DebugLevel.debug=Debug +namino_arancio.menu.DebugLevel.debug.build.code_debug=4 +namino_arancio.menu.DebugLevel.verbose=Verbose +namino_arancio.menu.DebugLevel.verbose.build.code_debug=5 + +namino_arancio.menu.EraseFlash.none=Disabled +namino_arancio.menu.EraseFlash.none.upload.erase_cmd= +namino_arancio.menu.EraseFlash.all=Enabled +namino_arancio.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Namino Bianco + +namino_bianco.name=Namino Bianco + +namino_bianco.bootloader.tool=esptool_py +namino_bianco.bootloader.tool.default=esptool_py + +namino_bianco.upload.tool=esptool_py +namino_bianco.upload.tool.default=esptool_py +namino_bianco.upload.tool.network=esp_ota + +namino_bianco.upload.maximum_size=1310720 +namino_bianco.upload.maximum_data_size=327680 +namino_bianco.upload.flags= +namino_bianco.upload.extra_flags= +namino_bianco.upload.use_1200bps_touch=true +namino_bianco.upload.wait_for_upload_port=true + +namino_bianco.serial.disableDTR=false +namino_bianco.serial.disableRTS=false + +namino_bianco.build.tarch=xtensa +namino_bianco.build.bootloader_addr=0x0 +namino_bianco.build.target=esp32s3 +namino_bianco.build.mcu=esp32s3 +namino_bianco.build.core=esp32 +namino_bianco.build.variant=namino_bianco +namino_bianco.build.board=NAMINO_BIANCO + +namino_bianco.build.usb_mode=0 +namino_bianco.build.cdc_on_boot=1 +namino_bianco.build.msc_on_boot=0 +namino_bianco.build.dfu_on_boot=0 +namino_bianco.build.f_cpu=240000000L +namino_bianco.build.flash_size=4MB +namino_bianco.build.flash_freq=80m +namino_bianco.build.flash_mode=dio +namino_bianco.build.boot=qio +namino_bianco.build.partitions=default +namino_bianco.build.defines= +namino_bianco.build.loop_core= +namino_bianco.build.event_core= +namino_bianco.build.flash_type=qio +namino_bianco.build.psram_type=qspi +namino_bianco.build.memory_type={build.flash_type}_{build.psram_type} + +namino_bianco.menu.LoopCore.1=Core 1 +namino_bianco.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +namino_bianco.menu.LoopCore.0=Core 0 +namino_bianco.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +namino_bianco.menu.EventsCore.1=Core 1 +namino_bianco.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +namino_bianco.menu.EventsCore.0=Core 0 +namino_bianco.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +namino_bianco.menu.USBMode.default=USB-OTG (TinyUSB) +namino_bianco.menu.USBMode.default.build.usb_mode=0 +namino_bianco.menu.USBMode.hwcdc=Hardware CDC and JTAG +namino_bianco.menu.USBMode.hwcdc.build.usb_mode=1 + +namino_bianco.menu.CDCOnBoot.cdc=Enabled +namino_bianco.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +namino_bianco.menu.CDCOnBoot.default=Disabled +namino_bianco.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +namino_bianco.menu.MSCOnBoot.default=Disabled +namino_bianco.menu.MSCOnBoot.default.build.msc_on_boot=0 +namino_bianco.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +namino_bianco.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +namino_bianco.menu.DFUOnBoot.default=Disabled +namino_bianco.menu.DFUOnBoot.default.build.dfu_on_boot=0 +namino_bianco.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +namino_bianco.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +namino_bianco.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +namino_bianco.menu.UploadMode.cdc.upload.use_1200bps_touch=true +namino_bianco.menu.UploadMode.cdc.upload.wait_for_upload_port=true +namino_bianco.menu.UploadMode.default=UART0 / Hardware CDC +namino_bianco.menu.UploadMode.default.upload.use_1200bps_touch=false +namino_bianco.menu.UploadMode.default.upload.wait_for_upload_port=false + +namino_bianco.menu.PSRAM.disabled=Disabled +namino_bianco.menu.PSRAM.disabled.build.defines= +namino_bianco.menu.PSRAM.disabled.build.psram_type=qspi +namino_bianco.menu.PSRAM.enabled=QSPI PSRAM +namino_bianco.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +namino_bianco.menu.PSRAM.enabled.build.psram_type=qspi +namino_bianco.menu.PSRAM.opi=OPI PSRAM +namino_bianco.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +namino_bianco.menu.PSRAM.opi.build.psram_type=opi + +namino_bianco.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +namino_bianco.menu.PartitionScheme.default.build.partitions=default +namino_bianco.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +namino_bianco.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +namino_bianco.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +namino_bianco.menu.PartitionScheme.minimal.build.partitions=minimal +namino_bianco.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +namino_bianco.menu.PartitionScheme.no_ota.build.partitions=no_ota +namino_bianco.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +namino_bianco.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +namino_bianco.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +namino_bianco.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +namino_bianco.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +namino_bianco.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +namino_bianco.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +namino_bianco.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +namino_bianco.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +namino_bianco.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +namino_bianco.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +namino_bianco.menu.PartitionScheme.huge_app.build.partitions=huge_app +namino_bianco.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +namino_bianco.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +namino_bianco.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +namino_bianco.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +namino_bianco.menu.CPUFreq.240=240MHz (WiFi) +namino_bianco.menu.CPUFreq.240.build.f_cpu=240000000L +namino_bianco.menu.CPUFreq.160=160MHz (WiFi) +namino_bianco.menu.CPUFreq.160.build.f_cpu=160000000L +namino_bianco.menu.CPUFreq.80=80MHz (WiFi) +namino_bianco.menu.CPUFreq.80.build.f_cpu=80000000L +namino_bianco.menu.CPUFreq.40=40MHz +namino_bianco.menu.CPUFreq.40.build.f_cpu=40000000L +namino_bianco.menu.CPUFreq.20=20MHz +namino_bianco.menu.CPUFreq.20.build.f_cpu=20000000L +namino_bianco.menu.CPUFreq.10=10MHz +namino_bianco.menu.CPUFreq.10.build.f_cpu=10000000L + +namino_bianco.menu.FlashMode.qio=QIO 80MHz +namino_bianco.menu.FlashMode.qio.build.flash_mode=dio +namino_bianco.menu.FlashMode.qio.build.boot=qio +namino_bianco.menu.FlashMode.qio.build.boot_freq=80m +namino_bianco.menu.FlashMode.qio.build.flash_freq=80m +namino_bianco.menu.FlashMode.qio120=QIO 120MHz +namino_bianco.menu.FlashMode.qio120.build.flash_mode=dio +namino_bianco.menu.FlashMode.qio120.build.boot=qio +namino_bianco.menu.FlashMode.qio120.build.boot_freq=120m +namino_bianco.menu.FlashMode.qio120.build.flash_freq=80m +namino_bianco.menu.FlashMode.dio=DIO 80MHz +namino_bianco.menu.FlashMode.dio.build.flash_mode=dio +namino_bianco.menu.FlashMode.dio.build.boot=dio +namino_bianco.menu.FlashMode.dio.build.boot_freq=80m +namino_bianco.menu.FlashMode.dio.build.flash_freq=80m +namino_bianco.menu.FlashMode.opi=OPI 80MHz +namino_bianco.menu.FlashMode.opi.build.flash_mode=dout +namino_bianco.menu.FlashMode.opi.build.boot=opi +namino_bianco.menu.FlashMode.opi.build.boot_freq=80m +namino_bianco.menu.FlashMode.opi.build.flash_freq=80m + +namino_bianco.menu.FlashSize.4M=4MB (32Mb) +namino_bianco.menu.FlashSize.4M.build.flash_size=4MB + +namino_bianco.menu.UploadSpeed.921600=921600 +namino_bianco.menu.UploadSpeed.921600.upload.speed=921600 +namino_bianco.menu.UploadSpeed.115200=115200 +namino_bianco.menu.UploadSpeed.115200.upload.speed=115200 +namino_bianco.menu.UploadSpeed.256000.windows=256000 +namino_bianco.menu.UploadSpeed.256000.upload.speed=256000 +namino_bianco.menu.UploadSpeed.230400.windows.upload.speed=256000 +namino_bianco.menu.UploadSpeed.230400=230400 +namino_bianco.menu.UploadSpeed.230400.upload.speed=230400 +namino_bianco.menu.UploadSpeed.460800.linux=460800 +namino_bianco.menu.UploadSpeed.460800.macosx=460800 +namino_bianco.menu.UploadSpeed.460800.upload.speed=460800 +namino_bianco.menu.UploadSpeed.512000.windows=512000 +namino_bianco.menu.UploadSpeed.512000.upload.speed=512000 + +namino_bianco.menu.DebugLevel.none=None +namino_bianco.menu.DebugLevel.none.build.code_debug=0 +namino_bianco.menu.DebugLevel.error=Error +namino_bianco.menu.DebugLevel.error.build.code_debug=1 +namino_bianco.menu.DebugLevel.warn=Warn +namino_bianco.menu.DebugLevel.warn.build.code_debug=2 +namino_bianco.menu.DebugLevel.info=Info +namino_bianco.menu.DebugLevel.info.build.code_debug=3 +namino_bianco.menu.DebugLevel.debug=Debug +namino_bianco.menu.DebugLevel.debug.build.code_debug=4 +namino_bianco.menu.DebugLevel.verbose=Verbose +namino_bianco.menu.DebugLevel.verbose.build.code_debug=5 + +namino_bianco.menu.EraseFlash.none=Disabled +namino_bianco.menu.EraseFlash.none.upload.erase_cmd= +namino_bianco.menu.EraseFlash.all=Enabled +namino_bianco.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# IOXESP32, IOXESP32U + +ioxesp32.name=IOXESP32 + +ioxesp32.bootloader.tool=esptool_py +ioxesp32.bootloader.tool.default=esptool_py + +ioxesp32.upload.tool=esptool_py +ioxesp32.upload.tool.default=esptool_py +ioxesp32.upload.tool.network=esp_ota + +ioxesp32.upload.maximum_size=1310720 +ioxesp32.upload.maximum_data_size=327680 +ioxesp32.upload.flags= +ioxesp32.upload.extra_flags= + +ioxesp32.serial.disableDTR=true +ioxesp32.serial.disableRTS=true + +ioxesp32.build.tarch=xtensa +ioxesp32.build.bootloader_addr=0x1000 +ioxesp32.build.target=esp32 +ioxesp32.build.mcu=esp32 +ioxesp32.build.core=esp32 +ioxesp32.build.variant=ioxesp32 +ioxesp32.build.board=IOXESP32 + +ioxesp32.build.f_cpu=240000000L +ioxesp32.build.flash_mode=dio +ioxesp32.build.flash_size=4MB +ioxesp32.build.flash_freq=40m +ioxesp32.build.boot=dio +ioxesp32.build.partitions=default +ioxesp32.build.defines= +ioxesp32.build.extra_libs= + +ioxesp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ioxesp32.menu.PartitionScheme.default.build.partitions=default +ioxesp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ioxesp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ioxesp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ioxesp32.menu.PartitionScheme.minimal.build.partitions=minimal +ioxesp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ioxesp32.menu.PartitionScheme.no_ota.build.partitions=no_ota +ioxesp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ioxesp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ioxesp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ioxesp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ioxesp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ioxesp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ioxesp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ioxesp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ioxesp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ioxesp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ioxesp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ioxesp32.menu.PartitionScheme.huge_app.build.partitions=huge_app +ioxesp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ioxesp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ioxesp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ioxesp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +ioxesp32.menu.PartitionScheme.rainmaker=RainMaker 4MB +ioxesp32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +ioxesp32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +ioxesp32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +ioxesp32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +ioxesp32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +ioxesp32.menu.FlashFreq.80=80MHz +ioxesp32.menu.FlashFreq.80.build.flash_freq=80m +ioxesp32.menu.FlashFreq.40=40MHz +ioxesp32.menu.FlashFreq.40.build.flash_freq=40m + +ioxesp32.menu.UploadSpeed.921600=921600 +ioxesp32.menu.UploadSpeed.921600.upload.speed=921600 +ioxesp32.menu.UploadSpeed.115200=115200 +ioxesp32.menu.UploadSpeed.115200.upload.speed=115200 +ioxesp32.menu.UploadSpeed.256000.windows=256000 +ioxesp32.menu.UploadSpeed.256000.upload.speed=256000 +ioxesp32.menu.UploadSpeed.230400.windows.upload.speed=256000 +ioxesp32.menu.UploadSpeed.230400=230400 +ioxesp32.menu.UploadSpeed.230400.upload.speed=230400 +ioxesp32.menu.UploadSpeed.460800.linux=460800 +ioxesp32.menu.UploadSpeed.460800.macosx=460800 +ioxesp32.menu.UploadSpeed.460800.upload.speed=460800 +ioxesp32.menu.UploadSpeed.512000.windows=512000 +ioxesp32.menu.UploadSpeed.512000.upload.speed=512000 + +ioxesp32.menu.DebugLevel.none=None +ioxesp32.menu.DebugLevel.none.build.code_debug=0 +ioxesp32.menu.DebugLevel.error=Error +ioxesp32.menu.DebugLevel.error.build.code_debug=1 +ioxesp32.menu.DebugLevel.warn=Warn +ioxesp32.menu.DebugLevel.warn.build.code_debug=2 +ioxesp32.menu.DebugLevel.info=Info +ioxesp32.menu.DebugLevel.info.build.code_debug=3 +ioxesp32.menu.DebugLevel.debug=Debug +ioxesp32.menu.DebugLevel.debug.build.code_debug=4 +ioxesp32.menu.DebugLevel.verbose=Verbose +ioxesp32.menu.DebugLevel.verbose.build.code_debug=5 + +ioxesp32.menu.EraseFlash.none=Disabled +ioxesp32.menu.EraseFlash.none.upload.erase_cmd= +ioxesp32.menu.EraseFlash.all=Enabled +ioxesp32.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# IOXESP32PS + +ioxesp32ps.name=IOXESP32PS + +ioxesp32ps.bootloader.tool=esptool_py +ioxesp32ps.bootloader.tool.default=esptool_py + +ioxesp32ps.upload.tool=esptool_py +ioxesp32ps.upload.tool.default=esptool_py +ioxesp32ps.upload.tool.network=esp_ota + +ioxesp32ps.upload.maximum_size=1310720 +ioxesp32ps.upload.maximum_data_size=327680 +ioxesp32ps.upload.flags= +ioxesp32ps.upload.extra_flags= + +ioxesp32ps.serial.disableDTR=true +ioxesp32ps.serial.disableRTS=true + +ioxesp32ps.build.tarch=xtensa +ioxesp32ps.build.bootloader_addr=0x1000 +ioxesp32ps.build.target=esp32 +ioxesp32ps.build.mcu=esp32 +ioxesp32ps.build.core=esp32 +ioxesp32ps.build.variant=ioxesp32 +ioxesp32ps.build.board=IOXESP32PS + +ioxesp32ps.build.f_cpu=240000000L +ioxesp32ps.build.flash_mode=dio +ioxesp32ps.build.flash_size=4MB +ioxesp32ps.build.flash_freq=40m +ioxesp32ps.build.boot=dio +ioxesp32ps.build.partitions=default +ioxesp32ps.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +ioxesp32ps.build.extra_libs= + +ioxesp32ps.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ioxesp32ps.menu.PartitionScheme.default.build.partitions=default +ioxesp32ps.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ioxesp32ps.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ioxesp32ps.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ioxesp32ps.menu.PartitionScheme.minimal.build.partitions=minimal +ioxesp32ps.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ioxesp32ps.menu.PartitionScheme.no_ota.build.partitions=no_ota +ioxesp32ps.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ioxesp32ps.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ioxesp32ps.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ioxesp32ps.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ioxesp32ps.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ioxesp32ps.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ioxesp32ps.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ioxesp32ps.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ioxesp32ps.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ioxesp32ps.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ioxesp32ps.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ioxesp32ps.menu.PartitionScheme.huge_app.build.partitions=huge_app +ioxesp32ps.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ioxesp32ps.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ioxesp32ps.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ioxesp32ps.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +ioxesp32ps.menu.PartitionScheme.rainmaker=RainMaker 4MB +ioxesp32ps.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +ioxesp32ps.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +ioxesp32ps.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +ioxesp32ps.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +ioxesp32ps.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +ioxesp32ps.menu.FlashFreq.80=80MHz +ioxesp32ps.menu.FlashFreq.80.build.flash_freq=80m +ioxesp32ps.menu.FlashFreq.40=40MHz +ioxesp32ps.menu.FlashFreq.40.build.flash_freq=40m + +ioxesp32ps.menu.UploadSpeed.921600=921600 +ioxesp32ps.menu.UploadSpeed.921600.upload.speed=921600 +ioxesp32ps.menu.UploadSpeed.115200=115200 +ioxesp32ps.menu.UploadSpeed.115200.upload.speed=115200 +ioxesp32ps.menu.UploadSpeed.256000.windows=256000 +ioxesp32ps.menu.UploadSpeed.256000.upload.speed=256000 +ioxesp32ps.menu.UploadSpeed.230400.windows.upload.speed=256000 +ioxesp32ps.menu.UploadSpeed.230400=230400 +ioxesp32ps.menu.UploadSpeed.230400.upload.speed=230400 +ioxesp32ps.menu.UploadSpeed.460800.linux=460800 +ioxesp32ps.menu.UploadSpeed.460800.macosx=460800 +ioxesp32ps.menu.UploadSpeed.460800.upload.speed=460800 +ioxesp32ps.menu.UploadSpeed.512000.windows=512000 +ioxesp32ps.menu.UploadSpeed.512000.upload.speed=512000 + +ioxesp32ps.menu.DebugLevel.none=None +ioxesp32ps.menu.DebugLevel.none.build.code_debug=0 +ioxesp32ps.menu.DebugLevel.error=Error +ioxesp32ps.menu.DebugLevel.error.build.code_debug=1 +ioxesp32ps.menu.DebugLevel.warn=Warn +ioxesp32ps.menu.DebugLevel.warn.build.code_debug=2 +ioxesp32ps.menu.DebugLevel.info=Info +ioxesp32ps.menu.DebugLevel.info.build.code_debug=3 +ioxesp32ps.menu.DebugLevel.debug=Debug +ioxesp32ps.menu.DebugLevel.debug.build.code_debug=4 +ioxesp32ps.menu.DebugLevel.verbose=Verbose +ioxesp32ps.menu.DebugLevel.verbose.build.code_debug=5 + +ioxesp32ps.menu.EraseFlash.none=Disabled +ioxesp32ps.menu.EraseFlash.none.upload.erase_cmd= +ioxesp32ps.menu.EraseFlash.all=Enabled +ioxesp32ps.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# IOXESP32-C6 + +ioxesp32c6.name=IOXESP32-C6 + +ioxesp32c6.bootloader.tool=esptool_py +ioxesp32c6.bootloader.tool.default=esptool_py + +ioxesp32c6.upload.tool=esptool_py +ioxesp32c6.upload.tool.default=esptool_py +ioxesp32c6.upload.tool.network=esp_ota + +ioxesp32c6.upload.maximum_size=1310720 +ioxesp32c6.upload.maximum_data_size=327680 +ioxesp32c6.upload.flags= +ioxesp32c6.upload.extra_flags= +ioxesp32c6.upload.use_1200bps_touch=false +ioxesp32c6.upload.wait_for_upload_port=false + +ioxesp32c6.serial.disableDTR=false +ioxesp32c6.serial.disableRTS=false + +ioxesp32c6.build.tarch=riscv32 +ioxesp32c6.build.target=esp +ioxesp32c6.build.mcu=esp32c6 +ioxesp32c6.build.core=esp32 +ioxesp32c6.build.variant=ioxesp32c6 +ioxesp32c6.build.board=ESP32C6_DEV +ioxesp32c6.build.bootloader_addr=0x0 + +ioxesp32c6.build.cdc_on_boot=0 +ioxesp32c6.build.f_cpu=160000000L +ioxesp32c6.build.flash_size=4MB +ioxesp32c6.build.flash_freq=80m +ioxesp32c6.build.flash_mode=qio +ioxesp32c6.build.boot=qio +ioxesp32c6.build.partitions=default +ioxesp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +ioxesp32c6.menu.JTAGAdapter.default=Disabled +ioxesp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +ioxesp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +ioxesp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +ioxesp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +ioxesp32c6.menu.JTAGAdapter.external=FTDI Adapter +ioxesp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +ioxesp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +ioxesp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +ioxesp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +ioxesp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +ioxesp32c6.menu.CDCOnBoot.default=Disabled +ioxesp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +ioxesp32c6.menu.CDCOnBoot.cdc=Enabled +ioxesp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +ioxesp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ioxesp32c6.menu.PartitionScheme.default.build.partitions=default +ioxesp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ioxesp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ioxesp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +ioxesp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +ioxesp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +ioxesp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs +ioxesp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +ioxesp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ioxesp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +ioxesp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ioxesp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ioxesp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ioxesp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ioxesp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ioxesp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ioxesp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ioxesp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ioxesp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ioxesp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ioxesp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ioxesp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +ioxesp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ioxesp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ioxesp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ioxesp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +ioxesp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +ioxesp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +ioxesp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +ioxesp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +ioxesp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +ioxesp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +ioxesp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +ioxesp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +ioxesp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +ioxesp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +ioxesp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +ioxesp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +ioxesp32c6.menu.PartitionScheme.custom=Custom +ioxesp32c6.menu.PartitionScheme.custom.build.partitions= +ioxesp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +ioxesp32c6.menu.CPUFreq.160=160MHz (WiFi) +ioxesp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +ioxesp32c6.menu.CPUFreq.120=120MHz (WiFi) +ioxesp32c6.menu.CPUFreq.120.build.f_cpu=120000000L +ioxesp32c6.menu.CPUFreq.80=80MHz (WiFi) +ioxesp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +ioxesp32c6.menu.CPUFreq.40=40MHz +ioxesp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +ioxesp32c6.menu.CPUFreq.20=20MHz +ioxesp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +ioxesp32c6.menu.CPUFreq.10=10MHz +ioxesp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +ioxesp32c6.menu.FlashMode.qio=QIO +ioxesp32c6.menu.FlashMode.qio.build.flash_mode=dio +ioxesp32c6.menu.FlashMode.qio.build.boot=qio +ioxesp32c6.menu.FlashMode.dio=DIO +ioxesp32c6.menu.FlashMode.dio.build.flash_mode=dio +ioxesp32c6.menu.FlashMode.dio.build.boot=dio + +ioxesp32c6.menu.FlashFreq.80=80MHz +ioxesp32c6.menu.FlashFreq.80.build.flash_freq=80m +ioxesp32c6.menu.FlashFreq.40=40MHz +ioxesp32c6.menu.FlashFreq.40.build.flash_freq=40m + +ioxesp32c6.menu.UploadSpeed.921600=921600 +ioxesp32c6.menu.UploadSpeed.921600.upload.speed=921600 +ioxesp32c6.menu.UploadSpeed.115200=115200 +ioxesp32c6.menu.UploadSpeed.115200.upload.speed=115200 +ioxesp32c6.menu.UploadSpeed.256000.windows=256000 +ioxesp32c6.menu.UploadSpeed.256000.upload.speed=256000 +ioxesp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +ioxesp32c6.menu.UploadSpeed.230400=230400 +ioxesp32c6.menu.UploadSpeed.230400.upload.speed=230400 +ioxesp32c6.menu.UploadSpeed.460800.linux=460800 +ioxesp32c6.menu.UploadSpeed.460800.macosx=460800 +ioxesp32c6.menu.UploadSpeed.460800.upload.speed=460800 +ioxesp32c6.menu.UploadSpeed.512000.windows=512000 +ioxesp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +ioxesp32c6.menu.DebugLevel.none=None +ioxesp32c6.menu.DebugLevel.none.build.code_debug=0 +ioxesp32c6.menu.DebugLevel.error=Error +ioxesp32c6.menu.DebugLevel.error.build.code_debug=1 +ioxesp32c6.menu.DebugLevel.warn=Warn +ioxesp32c6.menu.DebugLevel.warn.build.code_debug=2 +ioxesp32c6.menu.DebugLevel.info=Info +ioxesp32c6.menu.DebugLevel.info.build.code_debug=3 +ioxesp32c6.menu.DebugLevel.debug=Debug +ioxesp32c6.menu.DebugLevel.debug.build.code_debug=4 +ioxesp32c6.menu.DebugLevel.verbose=Verbose +ioxesp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +ioxesp32c6.menu.EraseFlash.none=Disabled +ioxesp32c6.menu.EraseFlash.none.upload.erase_cmd= +ioxesp32c6.menu.EraseFlash.all=Enabled +ioxesp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +ioxesp32c6.menu.ZigbeeMode.default=Disabled +ioxesp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +ioxesp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +ioxesp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +ioxesp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +ioxesp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +ioxesp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator) +ioxesp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +ioxesp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## +# ATD1.47-S3 + +atd147_s3.name=ATD1.47-S3 + +atd147_s3.bootloader.tool=esptool_py +atd147_s3.bootloader.tool.default=esptool_py + +atd147_s3.upload.tool=esptool_py +atd147_s3.upload.tool.default=esptool_py +atd147_s3.upload.tool.network=esp_ota + +atd147_s3.upload.maximum_size=1310720 +atd147_s3.upload.maximum_data_size=327680 +atd147_s3.upload.flags= +atd147_s3.upload.extra_flags= +atd147_s3.upload.use_1200bps_touch=false +atd147_s3.upload.wait_for_upload_port=false + +atd147_s3.serial.disableDTR=false +atd147_s3.serial.disableRTS=false + +atd147_s3.build.tarch=xtensa +atd147_s3.build.bootloader_addr=0x0 +atd147_s3.build.target=esp32s3 +atd147_s3.build.mcu=esp32s3 +atd147_s3.build.core=esp32 +atd147_s3.build.variant=atd147_s3 +atd147_s3.build.board=ATD143_S3 + +atd147_s3.build.usb_mode=1 +atd147_s3.build.cdc_on_boot=0 +atd147_s3.build.msc_on_boot=0 +atd147_s3.build.dfu_on_boot=0 +atd147_s3.build.f_cpu=240000000L +atd147_s3.build.flash_size=8MB +atd147_s3.build.flash_freq=80m +atd147_s3.build.flash_mode=dio +atd147_s3.build.boot=qio +atd147_s3.build.boot_freq=80m +atd147_s3.build.partitions=default_8MB +atd147_s3.build.defines= +atd147_s3.build.loop_core= +atd147_s3.build.event_core= +atd147_s3.build.psram_type=opi +atd147_s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +atd147_s3.menu.JTAGAdapter.default=Disabled +atd147_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +atd147_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +atd147_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +atd147_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +atd147_s3.menu.JTAGAdapter.external=FTDI Adapter +atd147_s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +atd147_s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +atd147_s3.menu.JTAGAdapter.bridge=ESP USB Bridge +atd147_s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +atd147_s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +atd147_s3.menu.PSRAM.disabled=Disabled +atd147_s3.menu.PSRAM.disabled.build.defines= +atd147_s3.menu.PSRAM.disabled.build.psram_type=opi +atd147_s3.menu.PSRAM.enabled=Enable +atd147_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +atd147_s3.menu.PSRAM.enabled.build.psram_type=opi + +atd147_s3.menu.LoopCore.1=Core 1 +atd147_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +atd147_s3.menu.LoopCore.0=Core 0 +atd147_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +atd147_s3.menu.EventsCore.1=Core 1 +atd147_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +atd147_s3.menu.EventsCore.0=Core 0 +atd147_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +atd147_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +atd147_s3.menu.USBMode.hwcdc.build.usb_mode=1 +atd147_s3.menu.USBMode.default=USB-OTG (TinyUSB) +atd147_s3.menu.USBMode.default.build.usb_mode=0 + +atd147_s3.menu.CDCOnBoot.default=Disabled +atd147_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +atd147_s3.menu.CDCOnBoot.cdc=Enabled +atd147_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +atd147_s3.menu.MSCOnBoot.default=Disabled +atd147_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +atd147_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +atd147_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +atd147_s3.menu.DFUOnBoot.default=Disabled +atd147_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +atd147_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +atd147_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +atd147_s3.menu.UploadMode.default=UART0 / Hardware CDC +atd147_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +atd147_s3.menu.UploadMode.default.upload.wait_for_upload_port=false +atd147_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +atd147_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +atd147_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +atd147_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +atd147_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +atd147_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +atd147_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +atd147_s3.menu.PartitionScheme.minimal.build.partitions=minimal +atd147_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +atd147_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +atd147_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +atd147_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +atd147_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +atd147_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +atd147_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +atd147_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +atd147_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +atd147_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +atd147_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +atd147_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +atd147_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +atd147_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +atd147_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +atd147_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +atd147_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +atd147_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +atd147_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +atd147_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +atd147_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +atd147_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +atd147_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +atd147_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +atd147_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +atd147_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +atd147_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +atd147_s3.menu.CPUFreq.240=240MHz (WiFi) +atd147_s3.menu.CPUFreq.240.build.f_cpu=240000000L +atd147_s3.menu.CPUFreq.160=160MHz (WiFi) +atd147_s3.menu.CPUFreq.160.build.f_cpu=160000000L +atd147_s3.menu.CPUFreq.80=80MHz (WiFi) +atd147_s3.menu.CPUFreq.80.build.f_cpu=80000000L +atd147_s3.menu.CPUFreq.40=40MHz +atd147_s3.menu.CPUFreq.40.build.f_cpu=40000000L +atd147_s3.menu.CPUFreq.20=20MHz +atd147_s3.menu.CPUFreq.20.build.f_cpu=20000000L +atd147_s3.menu.CPUFreq.10=10MHz +atd147_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +atd147_s3.menu.UploadSpeed.921600=921600 +atd147_s3.menu.UploadSpeed.921600.upload.speed=921600 +atd147_s3.menu.UploadSpeed.115200=115200 +atd147_s3.menu.UploadSpeed.115200.upload.speed=115200 +atd147_s3.menu.UploadSpeed.256000.windows=256000 +atd147_s3.menu.UploadSpeed.256000.upload.speed=256000 +atd147_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +atd147_s3.menu.UploadSpeed.230400=230400 +atd147_s3.menu.UploadSpeed.230400.upload.speed=230400 +atd147_s3.menu.UploadSpeed.460800.linux=460800 +atd147_s3.menu.UploadSpeed.460800.macosx=460800 +atd147_s3.menu.UploadSpeed.460800.upload.speed=460800 +atd147_s3.menu.UploadSpeed.512000.windows=512000 +atd147_s3.menu.UploadSpeed.512000.upload.speed=512000 + +atd147_s3.menu.DebugLevel.none=None +atd147_s3.menu.DebugLevel.none.build.code_debug=0 +atd147_s3.menu.DebugLevel.error=Error +atd147_s3.menu.DebugLevel.error.build.code_debug=1 +atd147_s3.menu.DebugLevel.warn=Warn +atd147_s3.menu.DebugLevel.warn.build.code_debug=2 +atd147_s3.menu.DebugLevel.info=Info +atd147_s3.menu.DebugLevel.info.build.code_debug=3 +atd147_s3.menu.DebugLevel.debug=Debug +atd147_s3.menu.DebugLevel.debug.build.code_debug=4 +atd147_s3.menu.DebugLevel.verbose=Verbose +atd147_s3.menu.DebugLevel.verbose.build.code_debug=5 + +atd147_s3.menu.EraseFlash.none=Disabled +atd147_s3.menu.EraseFlash.none.upload.erase_cmd= +atd147_s3.menu.EraseFlash.all=Enabled +atd147_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# ATD3.5-S3 + +atd35s3.name=ATD3.5-S3 + +atd35s3.bootloader.tool=esptool_py +atd35s3.bootloader.tool.default=esptool_py + +atd35s3.upload.tool=esptool_py +atd35s3.upload.tool.default=esptool_py +atd35s3.upload.tool.network=esp_ota + +atd35s3.upload.maximum_size=1310720 +atd35s3.upload.maximum_data_size=327680 +atd35s3.upload.flags= +atd35s3.upload.extra_flags= +atd35s3.upload.use_1200bps_touch=false +atd35s3.upload.wait_for_upload_port=false + +atd35s3.serial.disableDTR=false +atd35s3.serial.disableRTS=false + +atd35s3.build.tarch=xtensa +atd35s3.build.bootloader_addr=0x0 +atd35s3.build.target=esp32s3 +atd35s3.build.mcu=esp32s3 +atd35s3.build.core=esp32 +atd35s3.build.variant=atd35s3 +atd35s3.build.board=ATD143_S3 + +atd35s3.build.usb_mode=1 +atd35s3.build.cdc_on_boot=0 +atd35s3.build.msc_on_boot=0 +atd35s3.build.dfu_on_boot=0 +atd35s3.build.f_cpu=240000000L +atd35s3.build.flash_size=8MB +atd35s3.build.flash_freq=80m +atd35s3.build.flash_mode=dio +atd35s3.build.boot=qio +atd35s3.build.boot_freq=80m +atd35s3.build.partitions=default_8MB +atd35s3.build.defines= +atd35s3.build.loop_core= +atd35s3.build.event_core= +atd35s3.build.psram_type=opi +atd35s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +atd35s3.menu.JTAGAdapter.default=Disabled +atd35s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +atd35s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +atd35s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +atd35s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +atd35s3.menu.JTAGAdapter.external=FTDI Adapter +atd35s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +atd35s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +atd35s3.menu.JTAGAdapter.bridge=ESP USB Bridge +atd35s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +atd35s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +atd35s3.menu.PSRAM.disabled=Disabled +atd35s3.menu.PSRAM.disabled.build.defines= +atd35s3.menu.PSRAM.disabled.build.psram_type=opi +atd35s3.menu.PSRAM.enabled=Enable +atd35s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +atd35s3.menu.PSRAM.enabled.build.psram_type=opi + +atd35s3.menu.LoopCore.1=Core 1 +atd35s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +atd35s3.menu.LoopCore.0=Core 0 +atd35s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +atd35s3.menu.EventsCore.1=Core 1 +atd35s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +atd35s3.menu.EventsCore.0=Core 0 +atd35s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +atd35s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +atd35s3.menu.USBMode.hwcdc.build.usb_mode=1 +atd35s3.menu.USBMode.default=USB-OTG (TinyUSB) +atd35s3.menu.USBMode.default.build.usb_mode=0 + +atd35s3.menu.CDCOnBoot.default=Disabled +atd35s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +atd35s3.menu.CDCOnBoot.cdc=Enabled +atd35s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +atd35s3.menu.MSCOnBoot.default=Disabled +atd35s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +atd35s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +atd35s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +atd35s3.menu.DFUOnBoot.default=Disabled +atd35s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +atd35s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +atd35s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +atd35s3.menu.UploadMode.default=UART0 / Hardware CDC +atd35s3.menu.UploadMode.default.upload.use_1200bps_touch=false +atd35s3.menu.UploadMode.default.upload.wait_for_upload_port=false +atd35s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +atd35s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +atd35s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +atd35s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +atd35s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +atd35s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +atd35s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +atd35s3.menu.PartitionScheme.minimal.build.partitions=minimal +atd35s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +atd35s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +atd35s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +atd35s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +atd35s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +atd35s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +atd35s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +atd35s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +atd35s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +atd35s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +atd35s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +atd35s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +atd35s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +atd35s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +atd35s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +atd35s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +atd35s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +atd35s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +atd35s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +atd35s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +atd35s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +atd35s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +atd35s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +atd35s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +atd35s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +atd35s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +atd35s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +atd35s3.menu.CPUFreq.240=240MHz (WiFi) +atd35s3.menu.CPUFreq.240.build.f_cpu=240000000L +atd35s3.menu.CPUFreq.160=160MHz (WiFi) +atd35s3.menu.CPUFreq.160.build.f_cpu=160000000L +atd35s3.menu.CPUFreq.80=80MHz (WiFi) +atd35s3.menu.CPUFreq.80.build.f_cpu=80000000L +atd35s3.menu.CPUFreq.40=40MHz +atd35s3.menu.CPUFreq.40.build.f_cpu=40000000L +atd35s3.menu.CPUFreq.20=20MHz +atd35s3.menu.CPUFreq.20.build.f_cpu=20000000L +atd35s3.menu.CPUFreq.10=10MHz +atd35s3.menu.CPUFreq.10.build.f_cpu=10000000L + +atd35s3.menu.UploadSpeed.921600=921600 +atd35s3.menu.UploadSpeed.921600.upload.speed=921600 +atd35s3.menu.UploadSpeed.115200=115200 +atd35s3.menu.UploadSpeed.115200.upload.speed=115200 +atd35s3.menu.UploadSpeed.256000.windows=256000 +atd35s3.menu.UploadSpeed.256000.upload.speed=256000 +atd35s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +atd35s3.menu.UploadSpeed.230400=230400 +atd35s3.menu.UploadSpeed.230400.upload.speed=230400 +atd35s3.menu.UploadSpeed.460800.linux=460800 +atd35s3.menu.UploadSpeed.460800.macosx=460800 +atd35s3.menu.UploadSpeed.460800.upload.speed=460800 +atd35s3.menu.UploadSpeed.512000.windows=512000 +atd35s3.menu.UploadSpeed.512000.upload.speed=512000 + +atd35s3.menu.DebugLevel.none=None +atd35s3.menu.DebugLevel.none.build.code_debug=0 +atd35s3.menu.DebugLevel.error=Error +atd35s3.menu.DebugLevel.error.build.code_debug=1 +atd35s3.menu.DebugLevel.warn=Warn +atd35s3.menu.DebugLevel.warn.build.code_debug=2 +atd35s3.menu.DebugLevel.info=Info +atd35s3.menu.DebugLevel.info.build.code_debug=3 +atd35s3.menu.DebugLevel.debug=Debug +atd35s3.menu.DebugLevel.debug.build.code_debug=4 +atd35s3.menu.DebugLevel.verbose=Verbose +atd35s3.menu.DebugLevel.verbose.build.code_debug=5 + +atd35s3.menu.EraseFlash.none=Disabled +atd35s3.menu.EraseFlash.none.upload.erase_cmd= +atd35s3.menu.EraseFlash.all=Enabled +atd35s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# ESP32-S3 PowerFeather + +esp32s3_powerfeather.name=ESP32-S3 PowerFeather +esp32s3_powerfeather.vid.0=0x303a +esp32s3_powerfeather.pid.0=0x81BB + +esp32s3_powerfeather.bootloader.tool=esptool_py +esp32s3_powerfeather.bootloader.tool.default=esptool_py + +esp32s3_powerfeather.upload.tool=esptool_py +esp32s3_powerfeather.upload.tool.default=esptool_py +esp32s3_powerfeather.upload.tool.network=esp_ota + +esp32s3_powerfeather.upload.maximum_size=1310720 +esp32s3_powerfeather.upload.maximum_data_size=327680 +esp32s3_powerfeather.upload.flags= +esp32s3_powerfeather.upload.extra_flags= +esp32s3_powerfeather.upload.use_1200bps_touch=false +esp32s3_powerfeather.upload.wait_for_upload_port=false + +esp32s3_powerfeather.serial.disableDTR=false +esp32s3_powerfeather.serial.disableRTS=false + +esp32s3_powerfeather.build.tarch=xtensa +esp32s3_powerfeather.build.bootloader_addr=0x0 +esp32s3_powerfeather.build.target=esp32s3 +esp32s3_powerfeather.build.mcu=esp32s3 +esp32s3_powerfeather.build.core=esp32 +esp32s3_powerfeather.build.variant=esp32s3_powerfeather +esp32s3_powerfeather.build.board=ESP32S3_POWERFEATHER + +esp32s3_powerfeather.build.usb_mode=1 +esp32s3_powerfeather.build.cdc_on_boot=1 +esp32s3_powerfeather.build.msc_on_boot=0 +esp32s3_powerfeather.build.dfu_on_boot=0 +esp32s3_powerfeather.build.f_cpu=240000000L +esp32s3_powerfeather.build.flash_size=8MB +esp32s3_powerfeather.build.flash_freq=80m +esp32s3_powerfeather.build.flash_mode=dio +esp32s3_powerfeather.build.boot=qio +esp32s3_powerfeather.build.boot_freq=80m +esp32s3_powerfeather.build.partitions=default_8MB +esp32s3_powerfeather.build.defines= +esp32s3_powerfeather.build.loop_core= +esp32s3_powerfeather.build.event_core= +esp32s3_powerfeather.build.flash_type=qio +esp32s3_powerfeather.build.psram_type=qspi +esp32s3_powerfeather.build.memory_type={build.flash_type}_{build.psram_type} + +esp32s3_powerfeather.menu.PSRAM.disabled=Disabled +esp32s3_powerfeather.menu.PSRAM.disabled.build.defines= +esp32s3_powerfeather.menu.PSRAM.disabled.build.psram_type=qspi +esp32s3_powerfeather.menu.PSRAM.enabled=QSPI PSRAM +esp32s3_powerfeather.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +esp32s3_powerfeather.menu.PSRAM.enabled.build.psram_type=qspi + +esp32s3_powerfeather.menu.FlashMode.qio=QIO 80MHz +esp32s3_powerfeather.menu.FlashMode.qio.build.flash_mode=dio +esp32s3_powerfeather.menu.FlashMode.qio.build.boot=qio +esp32s3_powerfeather.menu.FlashMode.qio.build.boot_freq=80m +esp32s3_powerfeather.menu.FlashMode.qio.build.flash_freq=80m +esp32s3_powerfeather.menu.FlashMode.qio120=QIO 120MHz +esp32s3_powerfeather.menu.FlashMode.qio120.build.flash_mode=dio +esp32s3_powerfeather.menu.FlashMode.qio120.build.boot=qio +esp32s3_powerfeather.menu.FlashMode.qio120.build.boot_freq=120m +esp32s3_powerfeather.menu.FlashMode.qio120.build.flash_freq=80m +esp32s3_powerfeather.menu.FlashMode.dio=DIO 80MHz +esp32s3_powerfeather.menu.FlashMode.dio.build.flash_mode=dio +esp32s3_powerfeather.menu.FlashMode.dio.build.boot=dio +esp32s3_powerfeather.menu.FlashMode.dio.build.boot_freq=80m +esp32s3_powerfeather.menu.FlashMode.dio.build.flash_freq=80m + +esp32s3_powerfeather.menu.LoopCore.1=Core 1 +esp32s3_powerfeather.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +esp32s3_powerfeather.menu.LoopCore.0=Core 0 +esp32s3_powerfeather.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +esp32s3_powerfeather.menu.EventsCore.1=Core 1 +esp32s3_powerfeather.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +esp32s3_powerfeather.menu.EventsCore.0=Core 0 +esp32s3_powerfeather.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +esp32s3_powerfeather.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32s3_powerfeather.menu.USBMode.hwcdc.build.usb_mode=1 +esp32s3_powerfeather.menu.USBMode.default=USB-OTG (TinyUSB) +esp32s3_powerfeather.menu.USBMode.default.build.usb_mode=0 + +esp32s3_powerfeather.menu.CDCOnBoot.cdc=Enabled +esp32s3_powerfeather.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +esp32s3_powerfeather.menu.CDCOnBoot.default=Disabled +esp32s3_powerfeather.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +esp32s3_powerfeather.menu.MSCOnBoot.default=Disabled +esp32s3_powerfeather.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32s3_powerfeather.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32s3_powerfeather.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32s3_powerfeather.menu.DFUOnBoot.default=Disabled +esp32s3_powerfeather.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32s3_powerfeather.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32s3_powerfeather.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32s3_powerfeather.menu.UploadMode.default=UART0 / Hardware CDC +esp32s3_powerfeather.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32s3_powerfeather.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32s3_powerfeather.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32s3_powerfeather.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32s3_powerfeather.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32s3_powerfeather.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32s3_powerfeather.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32s3_powerfeather.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB=8M with ffat (3MB APP/1.5MB FATFS) +esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB +esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336 +esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP/5.3MB SPIFFS) +esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB +esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720 +esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB=Large FFAT (1.2MB APP/5.3MB FATFS) +esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB.build.partitions=large_ffat_8MB +esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB.upload.maximum_size=1310720 +esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +esp32s3_powerfeather.menu.CPUFreq.240=240MHz (WiFi) +esp32s3_powerfeather.menu.CPUFreq.240.build.f_cpu=240000000L +esp32s3_powerfeather.menu.CPUFreq.160=160MHz (WiFi) +esp32s3_powerfeather.menu.CPUFreq.160.build.f_cpu=160000000L +esp32s3_powerfeather.menu.CPUFreq.80=80MHz (WiFi) +esp32s3_powerfeather.menu.CPUFreq.80.build.f_cpu=80000000L +esp32s3_powerfeather.menu.CPUFreq.40=40MHz +esp32s3_powerfeather.menu.CPUFreq.40.build.f_cpu=40000000L +esp32s3_powerfeather.menu.CPUFreq.20=20MHz +esp32s3_powerfeather.menu.CPUFreq.20.build.f_cpu=20000000L +esp32s3_powerfeather.menu.CPUFreq.10=10MHz +esp32s3_powerfeather.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32s3_powerfeather.menu.UploadSpeed.921600=921600 +esp32s3_powerfeather.menu.UploadSpeed.921600.upload.speed=921600 +esp32s3_powerfeather.menu.UploadSpeed.115200=115200 +esp32s3_powerfeather.menu.UploadSpeed.115200.upload.speed=115200 +esp32s3_powerfeather.menu.UploadSpeed.256000.windows=256000 +esp32s3_powerfeather.menu.UploadSpeed.256000.upload.speed=256000 +esp32s3_powerfeather.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32s3_powerfeather.menu.UploadSpeed.230400=230400 +esp32s3_powerfeather.menu.UploadSpeed.230400.upload.speed=230400 +esp32s3_powerfeather.menu.UploadSpeed.460800.linux=460800 +esp32s3_powerfeather.menu.UploadSpeed.460800.macosx=460800 +esp32s3_powerfeather.menu.UploadSpeed.460800.upload.speed=460800 +esp32s3_powerfeather.menu.UploadSpeed.512000.windows=512000 +esp32s3_powerfeather.menu.UploadSpeed.512000.upload.speed=512000 + +esp32s3_powerfeather.menu.DebugLevel.none=None +esp32s3_powerfeather.menu.DebugLevel.none.build.code_debug=0 +esp32s3_powerfeather.menu.DebugLevel.error=Error +esp32s3_powerfeather.menu.DebugLevel.error.build.code_debug=1 +esp32s3_powerfeather.menu.DebugLevel.warn=Warn +esp32s3_powerfeather.menu.DebugLevel.warn.build.code_debug=2 +esp32s3_powerfeather.menu.DebugLevel.info=Info +esp32s3_powerfeather.menu.DebugLevel.info.build.code_debug=3 +esp32s3_powerfeather.menu.DebugLevel.debug=Debug +esp32s3_powerfeather.menu.DebugLevel.debug.build.code_debug=4 +esp32s3_powerfeather.menu.DebugLevel.verbose=Verbose +esp32s3_powerfeather.menu.DebugLevel.verbose.build.code_debug=5 + +esp32s3_powerfeather.menu.EraseFlash.none=Disabled +esp32s3_powerfeather.menu.EraseFlash.none.upload.erase_cmd= +esp32s3_powerfeather.menu.EraseFlash.all=Enabled +esp32s3_powerfeather.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# senseBox MCU ESP32-S2 + +sensebox_mcu_esp32s2.name=senseBox MCU-S2 ESP32-S2 +sensebox_mcu_esp32s2.vid.0=0x303A +sensebox_mcu_esp32s2.pid.0=0x81B8 +sensebox_mcu_esp32s2.vid.1=0x303A +sensebox_mcu_esp32s2.pid.1=0x81B9 +sensebox_mcu_esp32s2.vid.2=0x303A +sensebox_mcu_esp32s2.pid.2=0x81BA + +sensebox_mcu_esp32s2.bootloader.tool=esptool_py +sensebox_mcu_esp32s2.bootloader.tool.default=esptool_py + +sensebox_mcu_esp32s2.upload.tool=esptool_py +sensebox_mcu_esp32s2.upload.tool.default=esptool_py +sensebox_mcu_esp32s2.upload.tool.network=esp_ota + +sensebox_mcu_esp32s2.upload.maximum_size=1310720 +sensebox_mcu_esp32s2.upload.maximum_data_size=327680 +sensebox_mcu_esp32s2.upload.flags= +sensebox_mcu_esp32s2.upload.extra_flags= +sensebox_mcu_esp32s2.upload.use_1200bps_touch=true +sensebox_mcu_esp32s2.upload.wait_for_upload_port=true + +sensebox_mcu_esp32s2.serial.disableDTR=false +sensebox_mcu_esp32s2.serial.disableRTS=false + +sensebox_mcu_esp32s2.build.tarch=xtensa +sensebox_mcu_esp32s2.build.bootloader_addr=0x1000 +sensebox_mcu_esp32s2.build.target=esp32s2 +sensebox_mcu_esp32s2.build.mcu=esp32s2 +sensebox_mcu_esp32s2.build.core=esp32 +sensebox_mcu_esp32s2.build.variant=sensebox_mcu_esp32s2 +sensebox_mcu_esp32s2.build.board=SENSEBOX_MCU_ESP32S2 + +sensebox_mcu_esp32s2.build.cdc_on_boot=1 +sensebox_mcu_esp32s2.build.msc_on_boot=1 +sensebox_mcu_esp32s2.build.dfu_on_boot=0 +sensebox_mcu_esp32s2.build.f_cpu=240000000L +sensebox_mcu_esp32s2.build.flash_size=4MB +sensebox_mcu_esp32s2.build.flash_freq=80m +sensebox_mcu_esp32s2.build.flash_mode=dio +sensebox_mcu_esp32s2.build.boot=qio +sensebox_mcu_esp32s2.build.partitions=default +sensebox_mcu_esp32s2.build.defines= + +sensebox_mcu_esp32s2.menu.CDCOnBoot.cdc=Enabled +sensebox_mcu_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +sensebox_mcu_esp32s2.menu.CDCOnBoot.default=Disabled +sensebox_mcu_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +sensebox_mcu_esp32s2.menu.MSCOnBoot.msc=Enabled +sensebox_mcu_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1 +sensebox_mcu_esp32s2.menu.MSCOnBoot.default=Disabled +sensebox_mcu_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0 + +sensebox_mcu_esp32s2.menu.DFUOnBoot.default=Disabled +sensebox_mcu_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +sensebox_mcu_esp32s2.menu.DFUOnBoot.dfu=Enabled +sensebox_mcu_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +sensebox_mcu_esp32s2.menu.UploadMode.cdc=Internal USB +sensebox_mcu_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +sensebox_mcu_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true +sensebox_mcu_esp32s2.menu.UploadMode.default=UART0 +sensebox_mcu_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false +sensebox_mcu_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false + +sensebox_mcu_esp32s2.menu.PSRAM.enabled=Enabled +sensebox_mcu_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +sensebox_mcu_esp32s2.menu.PSRAM.disabled=Disabled +sensebox_mcu_esp32s2.menu.PSRAM.disabled.build.defines= + +sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-4MB-tinyuf2 +sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" 0x170000 "{runtime.platform.path}/variants/{build.variant}/APOTA.bin" +sensebox_mcu_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.default.build.partitions=default +sensebox_mcu_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +sensebox_mcu_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal +sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota +sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app +sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +sensebox_mcu_esp32s2.menu.CPUFreq.240=240MHz (WiFi) +sensebox_mcu_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L +sensebox_mcu_esp32s2.menu.CPUFreq.160=160MHz (WiFi) +sensebox_mcu_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L +sensebox_mcu_esp32s2.menu.CPUFreq.80=80MHz (WiFi) +sensebox_mcu_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L +sensebox_mcu_esp32s2.menu.CPUFreq.40=40MHz +sensebox_mcu_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L +sensebox_mcu_esp32s2.menu.CPUFreq.20=20MHz +sensebox_mcu_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L +sensebox_mcu_esp32s2.menu.CPUFreq.10=10MHz +sensebox_mcu_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L + +sensebox_mcu_esp32s2.menu.FlashMode.qio=QIO +sensebox_mcu_esp32s2.menu.FlashMode.qio.build.flash_mode=dio +sensebox_mcu_esp32s2.menu.FlashMode.qio.build.boot=qio +sensebox_mcu_esp32s2.menu.FlashMode.dio=DIO +sensebox_mcu_esp32s2.menu.FlashMode.dio.build.flash_mode=dio +sensebox_mcu_esp32s2.menu.FlashMode.dio.build.boot=dio +sensebox_mcu_esp32s2.menu.FlashMode.qout=QOUT +sensebox_mcu_esp32s2.menu.FlashMode.qout.build.flash_mode=dout +sensebox_mcu_esp32s2.menu.FlashMode.qout.build.boot=qout +sensebox_mcu_esp32s2.menu.FlashMode.dout=DOUT +sensebox_mcu_esp32s2.menu.FlashMode.dout.build.flash_mode=dout +sensebox_mcu_esp32s2.menu.FlashMode.dout.build.boot=dout + +sensebox_mcu_esp32s2.menu.FlashFreq.80=80MHz +sensebox_mcu_esp32s2.menu.FlashFreq.80.build.flash_freq=80m +sensebox_mcu_esp32s2.menu.FlashFreq.40=40MHz +sensebox_mcu_esp32s2.menu.FlashFreq.40.build.flash_freq=40m + +sensebox_mcu_esp32s2.menu.FlashSize.4M=4MB (32Mb) +sensebox_mcu_esp32s2.menu.FlashSize.4M.build.flash_size=4MB + +sensebox_mcu_esp32s2.menu.UploadSpeed.921600=921600 +sensebox_mcu_esp32s2.menu.UploadSpeed.921600.upload.speed=921600 +sensebox_mcu_esp32s2.menu.UploadSpeed.115200=115200 +sensebox_mcu_esp32s2.menu.UploadSpeed.115200.upload.speed=115200 +sensebox_mcu_esp32s2.menu.UploadSpeed.256000.windows=256000 +sensebox_mcu_esp32s2.menu.UploadSpeed.256000.upload.speed=256000 +sensebox_mcu_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000 +sensebox_mcu_esp32s2.menu.UploadSpeed.230400=230400 +sensebox_mcu_esp32s2.menu.UploadSpeed.230400.upload.speed=230400 +sensebox_mcu_esp32s2.menu.UploadSpeed.460800.linux=460800 +sensebox_mcu_esp32s2.menu.UploadSpeed.460800.macosx=460800 +sensebox_mcu_esp32s2.menu.UploadSpeed.460800.upload.speed=460800 +sensebox_mcu_esp32s2.menu.UploadSpeed.512000.windows=512000 +sensebox_mcu_esp32s2.menu.UploadSpeed.512000.upload.speed=512000 + +sensebox_mcu_esp32s2.menu.DebugLevel.none=None +sensebox_mcu_esp32s2.menu.DebugLevel.none.build.code_debug=0 +sensebox_mcu_esp32s2.menu.DebugLevel.error=Error +sensebox_mcu_esp32s2.menu.DebugLevel.error.build.code_debug=1 +sensebox_mcu_esp32s2.menu.DebugLevel.warn=Warn +sensebox_mcu_esp32s2.menu.DebugLevel.warn.build.code_debug=2 +sensebox_mcu_esp32s2.menu.DebugLevel.info=Info +sensebox_mcu_esp32s2.menu.DebugLevel.info.build.code_debug=3 +sensebox_mcu_esp32s2.menu.DebugLevel.debug=Debug +sensebox_mcu_esp32s2.menu.DebugLevel.debug.build.code_debug=4 +sensebox_mcu_esp32s2.menu.DebugLevel.verbose=Verbose +sensebox_mcu_esp32s2.menu.DebugLevel.verbose.build.code_debug=5 + +sensebox_mcu_esp32s2.menu.EraseFlash.none=Disabled +sensebox_mcu_esp32s2.menu.EraseFlash.none.upload.erase_cmd= +sensebox_mcu_esp32s2.menu.EraseFlash.all=Enabled +sensebox_mcu_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# senseBox Eye + +sensebox_eye.name=senseBox Eye +sensebox_eye.vid.0=0x303A +sensebox_eye.pid.0=0x82D1 +sensebox_eye.vid.1=0x303A +sensebox_eye.pid.1=0x82D2 +sensebox_eye.vid.2=0x303A +sensebox_eye.pid.2=0x82D3 + +sensebox_eye.bootloader.tool=esptool_py +sensebox_eye.bootloader.tool.default=esptool_py + +sensebox_eye.upload.tool=esptool_py +sensebox_eye.upload.tool.default=esptool_py +sensebox_eye.upload.tool.network=esp_ota + +sensebox_eye.upload.maximum_size=1310720 +sensebox_eye.upload.maximum_data_size=327680 +sensebox_eye.upload.flags= +sensebox_eye.upload.extra_flags= +sensebox_eye.upload.use_1200bps_touch=false +sensebox_eye.upload.wait_for_upload_port=false + +sensebox_eye.serial.disableDTR=false +sensebox_eye.serial.disableRTS=false + +sensebox_eye.build.tarch=xtensa +sensebox_eye.build.bootloader_addr=0x0 +sensebox_eye.build.target=esp32s3 +sensebox_eye.build.mcu=esp32s3 +sensebox_eye.build.core=esp32 +sensebox_eye.build.variant=sensebox_eye +sensebox_eye.build.board=SENSEBOX_EYE + +sensebox_eye.build.usb_mode=0 +sensebox_eye.build.cdc_on_boot=1 +sensebox_eye.build.msc_on_boot=1 +sensebox_eye.build.dfu_on_boot=0 +sensebox_eye.build.f_cpu=240000000L +sensebox_eye.build.flash_size=16MB (128Mb) +sensebox_eye.build.flash_freq=80m +sensebox_eye.build.flash_mode=dio +sensebox_eye.build.boot=qio +sensebox_eye.build.boot_freq=80m +sensebox_eye.build.partitions=tinyuf2 +sensebox_eye.build.defines= +sensebox_eye.build.loop_core= +sensebox_eye.build.event_core= +sensebox_eye.build.psram_type=qspi +sensebox_eye.build.memory_type={build.boot}_{build.psram_type} + +sensebox_eye.menu.JTAGAdapter.default=Disabled +sensebox_eye.menu.JTAGAdapter.default.build.copy_jtag_files=0 +sensebox_eye.menu.JTAGAdapter.builtin=Integrated USB JTAG +sensebox_eye.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +sensebox_eye.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +sensebox_eye.menu.JTAGAdapter.external=FTDI Adapter +sensebox_eye.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +sensebox_eye.menu.JTAGAdapter.external.build.copy_jtag_files=1 +sensebox_eye.menu.JTAGAdapter.bridge=ESP USB Bridge +sensebox_eye.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +sensebox_eye.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +sensebox_eye.menu.PSRAM.opi=OPI PSRAM +sensebox_eye.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +sensebox_eye.menu.PSRAM.opi.build.psram_type=opi +sensebox_eye.menu.PSRAM.disabled=Disabled +sensebox_eye.menu.PSRAM.disabled.build.defines= +sensebox_eye.menu.PSRAM.disabled.build.psram_type=qspi + +sensebox_eye.menu.FlashMode.qio=QIO 80MHz +sensebox_eye.menu.FlashMode.qio.build.flash_mode=dio +sensebox_eye.menu.FlashMode.qio.build.boot=qio +sensebox_eye.menu.FlashMode.qio.build.boot_freq=80m +sensebox_eye.menu.FlashMode.qio.build.flash_freq=80m +sensebox_eye.menu.FlashMode.dio=DIO 80MHz +sensebox_eye.menu.FlashMode.dio.build.flash_mode=dio +sensebox_eye.menu.FlashMode.dio.build.boot=dio +sensebox_eye.menu.FlashMode.dio.build.boot_freq=80m +sensebox_eye.menu.FlashMode.dio.build.flash_freq=80m + +sensebox_eye.menu.FlashSize.16M=16MB (128Mb) +sensebox_eye.menu.FlashSize.16M.build.flash_size=16MB + +sensebox_eye.menu.LoopCore.1=Core 1 +sensebox_eye.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +sensebox_eye.menu.LoopCore.0=Core 0 +sensebox_eye.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +sensebox_eye.menu.EventsCore.1=Core 1 +sensebox_eye.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +sensebox_eye.menu.EventsCore.0=Core 0 +sensebox_eye.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +sensebox_eye.menu.USBMode.default=USB-OTG (TinyUSB) +sensebox_eye.menu.USBMode.default.build.usb_mode=0 +sensebox_eye.menu.USBMode.hwcdc=Hardware CDC and JTAG +sensebox_eye.menu.USBMode.hwcdc.build.usb_mode=1 + +sensebox_eye.menu.CDCOnBoot.default=Enabled +sensebox_eye.menu.CDCOnBoot.default.build.cdc_on_boot=1 +sensebox_eye.menu.CDCOnBoot.cdc=Disabled +sensebox_eye.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +sensebox_eye.menu.MSCOnBoot.default=Enabled (Requires USB-OTG Mode) +sensebox_eye.menu.MSCOnBoot.default.build.msc_on_boot=1 +sensebox_eye.menu.MSCOnBoot.msc=Disabled +sensebox_eye.menu.MSCOnBoot.msc.build.msc_on_boot=0 + +sensebox_eye.menu.DFUOnBoot.default=Disabled +sensebox_eye.menu.DFUOnBoot.default.build.dfu_on_boot=0 +sensebox_eye.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +sensebox_eye.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +sensebox_eye.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +sensebox_eye.menu.UploadMode.cdc.upload.use_1200bps_touch=true +sensebox_eye.menu.UploadMode.cdc.upload.wait_for_upload_port=true +sensebox_eye.menu.UploadMode.default=UART0 / Hardware CDC +sensebox_eye.menu.UploadMode.default.upload.use_1200bps_touch=false +sensebox_eye.menu.UploadMode.default.upload.wait_for_upload_port=false + +sensebox_eye.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT) +sensebox_eye.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +sensebox_eye.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-16MB-tinyuf2 +sensebox_eye.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +sensebox_eye.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" 0x210000 "{runtime.platform.path}/variants/{build.variant}/APOTA.bin" +sensebox_eye.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +sensebox_eye.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +sensebox_eye.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +sensebox_eye.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +sensebox_eye.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +sensebox_eye.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +sensebox_eye.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +sensebox_eye.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +sensebox_eye.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +sensebox_eye.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +sensebox_eye.menu.PartitionScheme.fatflash.build.partitions=ffat +sensebox_eye.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +sensebox_eye.menu.PartitionScheme.gen4esp32scheme4=Huge App (16MB APP) +sensebox_eye.menu.PartitionScheme.gen4esp32scheme4.build.custom_partitions=gen4esp32_16MBapp +sensebox_eye.menu.PartitionScheme.gen4esp32scheme4.upload.maximum_size=16646144 + +sensebox_eye.menu.CPUFreq.240=240MHz (WiFi) +sensebox_eye.menu.CPUFreq.240.build.f_cpu=240000000L +sensebox_eye.menu.CPUFreq.160=160MHz (WiFi) +sensebox_eye.menu.CPUFreq.160.build.f_cpu=160000000L +sensebox_eye.menu.CPUFreq.80=80MHz (WiFi) +sensebox_eye.menu.CPUFreq.80.build.f_cpu=80000000L +sensebox_eye.menu.CPUFreq.40=40MHz +sensebox_eye.menu.CPUFreq.40.build.f_cpu=40000000L +sensebox_eye.menu.CPUFreq.20=20MHz +sensebox_eye.menu.CPUFreq.20.build.f_cpu=20000000L +sensebox_eye.menu.CPUFreq.10=10MHz +sensebox_eye.menu.CPUFreq.10.build.f_cpu=10000000L + +sensebox_eye.menu.UploadSpeed.921600=921600 +sensebox_eye.menu.UploadSpeed.921600.upload.speed=921600 +sensebox_eye.menu.UploadSpeed.115200=115200 +sensebox_eye.menu.UploadSpeed.115200.upload.speed=115200 +sensebox_eye.menu.UploadSpeed.256000.windows=256000 +sensebox_eye.menu.UploadSpeed.256000.upload.speed=256000 +sensebox_eye.menu.UploadSpeed.230400.windows.upload.speed=256000 +sensebox_eye.menu.UploadSpeed.230400=230400 +sensebox_eye.menu.UploadSpeed.230400.upload.speed=230400 +sensebox_eye.menu.UploadSpeed.460800.linux=460800 +sensebox_eye.menu.UploadSpeed.460800.macosx=460800 +sensebox_eye.menu.UploadSpeed.460800.upload.speed=460800 +sensebox_eye.menu.UploadSpeed.512000.windows=512000 +sensebox_eye.menu.UploadSpeed.512000.upload.speed=512000 + +sensebox_eye.menu.DebugLevel.none=None +sensebox_eye.menu.DebugLevel.none.build.code_debug=0 +sensebox_eye.menu.DebugLevel.error=Error +sensebox_eye.menu.DebugLevel.error.build.code_debug=1 +sensebox_eye.menu.DebugLevel.warn=Warn +sensebox_eye.menu.DebugLevel.warn.build.code_debug=2 +sensebox_eye.menu.DebugLevel.info=Info +sensebox_eye.menu.DebugLevel.info.build.code_debug=3 +sensebox_eye.menu.DebugLevel.debug=Debug +sensebox_eye.menu.DebugLevel.debug.build.code_debug=4 +sensebox_eye.menu.DebugLevel.verbose=Verbose +sensebox_eye.menu.DebugLevel.verbose.build.code_debug=5 + +sensebox_eye.menu.EraseFlash.none=Disabled +sensebox_eye.menu.EraseFlash.none.upload.erase_cmd= +sensebox_eye.menu.EraseFlash.all=Enabled +sensebox_eye.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +nano_nora.name=Arduino Nano ESP32 +nano_nora.vid.0=0x2341 +nano_nora.pid.0=0x0070 +nano_nora.upload_port.0.vid=0x2341 +nano_nora.upload_port.0.pid=0x0070 + +nano_nora.bootloader.tool=esptool_py +nano_nora.bootloader.tool.default=esptool_py + +nano_nora.upload.tool=dfu-util +nano_nora.upload.tool.default=dfu-util +nano_nora.upload.tool.network=esp_ota +nano_nora.upload.protocol=serial +nano_nora.upload.maximum_size=3145728 +nano_nora.upload.maximum_data_size=327680 +nano_nora.upload.flags= +nano_nora.upload.extra_flags= +nano_nora.upload.use_1200bps_touch=false +nano_nora.upload.wait_for_upload_port=false + +nano_nora.serial.disableDTR=false +nano_nora.serial.disableRTS=false + +nano_nora.build.tarch=xtensa +nano_nora.build.bootloader_addr=0x0 +nano_nora.build.target=esp32s3 +nano_nora.build.mcu=esp32s3 +nano_nora.build.core=esp32 +nano_nora.build.variant=arduino_nano_nora +nano_nora.build.board=NANO_ESP32 +nano_nora.build.code_debug=0 + +nano_nora.build.usb_mode=0 +nano_nora.build.cdc_on_boot=1 +nano_nora.build.msc_on_boot=0 +nano_nora.build.dfu_on_boot=1 +nano_nora.build.f_cpu=240000000L +nano_nora.build.flash_size=16MB +nano_nora.build.flash_freq=80m +nano_nora.build.flash_mode=dio +nano_nora.build.boot=qio +nano_nora.build.boot_freq=80m +nano_nora.build.partitions=app3M_fat9M_fact512k_16MB +nano_nora.build.defines=-DBOARD_HAS_PIN_REMAP {build.disable_pin_remap} -DBOARD_HAS_PSRAM '-DUSB_MANUFACTURER="Arduino"' '-DUSB_PRODUCT="Nano ESP32"' +nano_nora.build.loop_core=-DARDUINO_RUNNING_CORE=1 +nano_nora.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +nano_nora.build.psram_type=opi +nano_nora.build.memory_type={build.boot}_{build.psram_type} +nano_nora.build.disable_pin_remap= + +nano_nora.debug_config.nano_nora.cortex-debug.custom.name=Arduino on Nano ESP32 +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 2 +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.1=monitor reset halt +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.2=monitor gdb_sync +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.3=interrupt +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync +nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.2=interrupt +nano_nora.debug.additional_config=debug_config.nano_nora + +nano_nora.tools.esptool_py.program.pattern_args=--chip {build.mcu} --port "{serial.port}" --before default-reset --after hard-reset write-flash -z --flash-mode {build.flash_mode} --flash-freq {build.flash_freq} --flash-size {build.flash_size} {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0xf70000 "{build.variant.path}/extra/nora_recovery/nora_recovery.ino.bin" 0x10000 "{build.path}/{build.project_name}.bin" +nano_nora.tools.esptool_py.erase.pattern_args=--chip {build.mcu} --port "{serial.port}" --before default-reset --after hard-reset erase-flash + +nano_nora.debug.executable= + +nano_nora.menu.PartitionScheme.default=With FAT partition (default) +nano_nora.menu.PartitionScheme.spiffs=With SPIFFS partition (advanced) +nano_nora.menu.PartitionScheme.spiffs.build.partitions=app3M_spiffs9M_fact512k_16MB + +nano_nora.menu.PinNumbers.default=By Arduino pin (default) +nano_nora.menu.PinNumbers.byGPIONumber=By GPIO number (legacy) +nano_nora.menu.PinNumbers.byGPIONumber.build.disable_pin_remap=-DBOARD_USES_HW_GPIO_NUMBERS + +nano_nora.menu.USBMode.default=Normal mode (TinyUSB) +nano_nora.menu.USBMode.hwcdc=Debug mode (Hardware CDC) +nano_nora.menu.USBMode.hwcdc.build.usb_mode=1 +nano_nora.menu.USBMode.hwcdc.debug.executable={build.path}/{build.project_name}.elf + +nano_nora.menu.DebugLevel.none=None +nano_nora.menu.DebugLevel.none.build.code_debug=0 +nano_nora.menu.DebugLevel.error=Error +nano_nora.menu.DebugLevel.error.build.code_debug=1 +nano_nora.menu.DebugLevel.warn=Warn +nano_nora.menu.DebugLevel.warn.build.code_debug=2 +nano_nora.menu.DebugLevel.info=Info +nano_nora.menu.DebugLevel.info.build.code_debug=3 +nano_nora.menu.DebugLevel.debug=Debug +nano_nora.menu.DebugLevel.debug.build.code_debug=4 +nano_nora.menu.DebugLevel.verbose=Verbose +nano_nora.menu.DebugLevel.verbose.build.code_debug=5 + +############################################################## + +makergo_c3_supermini.name=MakerGO ESP32 C3 SuperMini + +makergo_c3_supermini.bootloader.tool=esptool_py +makergo_c3_supermini.bootloader.tool.default=esptool_py + +makergo_c3_supermini.upload.tool=esptool_py +makergo_c3_supermini.upload.tool.default=esptool_py +makergo_c3_supermini.upload.tool.network=esp_ota + +makergo_c3_supermini.upload.maximum_size=1310720 +makergo_c3_supermini.upload.maximum_data_size=327680 +makergo_c3_supermini.upload.flags= +makergo_c3_supermini.upload.extra_flags= +makergo_c3_supermini.upload.use_1200bps_touch=false +makergo_c3_supermini.upload.wait_for_upload_port=false + +makergo_c3_supermini.serial.disableDTR=true +makergo_c3_supermini.serial.disableRTS=true + +makergo_c3_supermini.build.tarch=riscv32 +makergo_c3_supermini.build.target=esp +makergo_c3_supermini.build.mcu=esp32c3 +makergo_c3_supermini.build.core=esp32 +makergo_c3_supermini.build.variant=makergo_c3_supermini +makergo_c3_supermini.build.board=MAKERGO_C3_SUPERMINI +makergo_c3_supermini.build.bootloader_addr=0x0 + +makergo_c3_supermini.build.cdc_on_boot=1 +makergo_c3_supermini.build.f_cpu=160000000L +makergo_c3_supermini.build.flash_size=4MB +makergo_c3_supermini.build.flash_freq=80m +makergo_c3_supermini.build.flash_mode=dio +makergo_c3_supermini.build.boot=qio +makergo_c3_supermini.build.partitions=default +makergo_c3_supermini.build.defines= + +makergo_c3_supermini.menu.CDCOnBoot.default=Enabled +makergo_c3_supermini.menu.CDCOnBoot.default.build.cdc_on_boot=1 +makergo_c3_supermini.menu.CDCOnBoot.dis_cdc=Disabled +makergo_c3_supermini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0 + +makergo_c3_supermini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +makergo_c3_supermini.menu.PartitionScheme.default.build.partitions=default +makergo_c3_supermini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +makergo_c3_supermini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +makergo_c3_supermini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +makergo_c3_supermini.menu.PartitionScheme.no_ota.build.partitions=no_ota +makergo_c3_supermini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +makergo_c3_supermini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +makergo_c3_supermini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +makergo_c3_supermini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +makergo_c3_supermini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +makergo_c3_supermini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +makergo_c3_supermini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +makergo_c3_supermini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +makergo_c3_supermini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +makergo_c3_supermini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +makergo_c3_supermini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +makergo_c3_supermini.menu.PartitionScheme.huge_app.build.partitions=huge_app +makergo_c3_supermini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + + +makergo_c3_supermini.menu.CPUFreq.160=160MHz (WiFi) +makergo_c3_supermini.menu.CPUFreq.160.build.f_cpu=160000000L +makergo_c3_supermini.menu.CPUFreq.80=80MHz (WiFi) +makergo_c3_supermini.menu.CPUFreq.80.build.f_cpu=80000000L +makergo_c3_supermini.menu.CPUFreq.40=40MHz +makergo_c3_supermini.menu.CPUFreq.40.build.f_cpu=40000000L +makergo_c3_supermini.menu.CPUFreq.20=20MHz +makergo_c3_supermini.menu.CPUFreq.20.build.f_cpu=20000000L +makergo_c3_supermini.menu.CPUFreq.10=10MHz +makergo_c3_supermini.menu.CPUFreq.10.build.f_cpu=10000000L + + +makergo_c3_supermini.menu.FlashFreq.80=80MHz +makergo_c3_supermini.menu.FlashFreq.80.build.flash_freq=80m +makergo_c3_supermini.menu.FlashFreq.40=40MHz +makergo_c3_supermini.menu.FlashFreq.40.build.flash_freq=40m + +makergo_c3_supermini.menu.UploadSpeed.921600=921600 +makergo_c3_supermini.menu.UploadSpeed.921600.upload.speed=921600 +makergo_c3_supermini.menu.UploadSpeed.115200=115200 +makergo_c3_supermini.menu.UploadSpeed.115200.upload.speed=115200 +makergo_c3_supermini.menu.UploadSpeed.256000.windows=256000 +makergo_c3_supermini.menu.UploadSpeed.256000.upload.speed=256000 +makergo_c3_supermini.menu.UploadSpeed.230400.windows.upload.speed=256000 +makergo_c3_supermini.menu.UploadSpeed.230400=230400 +makergo_c3_supermini.menu.UploadSpeed.230400.upload.speed=230400 +makergo_c3_supermini.menu.UploadSpeed.460800.linux=460800 +makergo_c3_supermini.menu.UploadSpeed.460800.macosx=460800 +makergo_c3_supermini.menu.UploadSpeed.460800.upload.speed=460800 +makergo_c3_supermini.menu.UploadSpeed.512000.windows=512000 +makergo_c3_supermini.menu.UploadSpeed.512000.upload.speed=512000 + +makergo_c3_supermini.menu.DebugLevel.none=None +makergo_c3_supermini.menu.DebugLevel.none.build.code_debug=0 +makergo_c3_supermini.menu.DebugLevel.error=Error +makergo_c3_supermini.menu.DebugLevel.error.build.code_debug=1 +makergo_c3_supermini.menu.DebugLevel.warn=Warn +makergo_c3_supermini.menu.DebugLevel.warn.build.code_debug=2 +makergo_c3_supermini.menu.DebugLevel.info=Info +makergo_c3_supermini.menu.DebugLevel.info.build.code_debug=3 +makergo_c3_supermini.menu.DebugLevel.debug=Debug +makergo_c3_supermini.menu.DebugLevel.debug.build.code_debug=4 +makergo_c3_supermini.menu.DebugLevel.verbose=Verbose +makergo_c3_supermini.menu.DebugLevel.verbose.build.code_debug=5 + +makergo_c3_supermini.menu.EraseFlash.none=Disabled +makergo_c3_supermini.menu.EraseFlash.none.upload.erase_cmd= +makergo_c3_supermini.menu.EraseFlash.all=Enabled +makergo_c3_supermini.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +makergo_c6_supermini.name=MakerGO ESP32 C6 SuperMini + +makergo_c6_supermini.bootloader.tool=esptool_py +makergo_c6_supermini.bootloader.tool.default=esptool_py + +makergo_c6_supermini.upload.tool=esptool_py +makergo_c6_supermini.upload.tool.default=esptool_py +makergo_c6_supermini.upload.tool.network=esp_ota + +makergo_c6_supermini.upload.maximum_size=1310720 +makergo_c6_supermini.upload.maximum_data_size=327680 +makergo_c6_supermini.upload.flags= +makergo_c6_supermini.upload.extra_flags= +makergo_c6_supermini.upload.use_1200bps_touch=false +makergo_c6_supermini.upload.wait_for_upload_port=false + +makergo_c6_supermini.serial.disableDTR=false +makergo_c6_supermini.serial.disableRTS=false + +makergo_c6_supermini.build.tarch=riscv32 +makergo_c6_supermini.build.target=esp +makergo_c6_supermini.build.mcu=esp32c6 +makergo_c6_supermini.build.core=esp32 +makergo_c6_supermini.build.variant=makergo_c6_supermini +makergo_c6_supermini.build.board=MAKERGO_C6_SUPERMINI +makergo_c6_supermini.build.bootloader_addr=0x0 + +makergo_c6_supermini.build.cdc_on_boot=0 +makergo_c6_supermini.build.f_cpu=160000000L +makergo_c6_supermini.build.flash_size=4MB +makergo_c6_supermini.build.flash_freq=80m +makergo_c6_supermini.build.flash_mode=qio +makergo_c6_supermini.build.boot=qio +makergo_c6_supermini.build.partitions=default +makergo_c6_supermini.build.defines= + +## IDE 2.0 Seems to not update the value +makergo_c6_supermini.menu.JTAGAdapter.default=Disabled +makergo_c6_supermini.menu.JTAGAdapter.default.build.copy_jtag_files=0 +makergo_c6_supermini.menu.JTAGAdapter.builtin=Integrated USB JTAG +makergo_c6_supermini.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +makergo_c6_supermini.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +makergo_c6_supermini.menu.JTAGAdapter.external=FTDI Adapter +makergo_c6_supermini.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +makergo_c6_supermini.menu.JTAGAdapter.external.build.copy_jtag_files=1 +makergo_c6_supermini.menu.JTAGAdapter.bridge=ESP USB Bridge +makergo_c6_supermini.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +makergo_c6_supermini.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +makergo_c6_supermini.menu.CDCOnBoot.default=Disabled +makergo_c6_supermini.menu.CDCOnBoot.default.build.cdc_on_boot=0 +makergo_c6_supermini.menu.CDCOnBoot.cdc=Enabled +makergo_c6_supermini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +makergo_c6_supermini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.default.build.partitions=default +makergo_c6_supermini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +makergo_c6_supermini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +makergo_c6_supermini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.minimal.build.partitions=minimal +makergo_c6_supermini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.no_ota.build.partitions=no_ota +makergo_c6_supermini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +makergo_c6_supermini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +makergo_c6_supermini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +makergo_c6_supermini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +makergo_c6_supermini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +makergo_c6_supermini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +makergo_c6_supermini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +makergo_c6_supermini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +makergo_c6_supermini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +makergo_c6_supermini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.huge_app.build.partitions=huge_app +makergo_c6_supermini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +makergo_c6_supermini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +makergo_c6_supermini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +makergo_c6_supermini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +makergo_c6_supermini.menu.PartitionScheme.rainmaker=RainMaker 4MB +makergo_c6_supermini.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +makergo_c6_supermini.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +makergo_c6_supermini.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +makergo_c6_supermini.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +makergo_c6_supermini.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +makergo_c6_supermini.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +makergo_c6_supermini.menu.PartitionScheme.zigbee.build.partitions=zigbee +makergo_c6_supermini.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +makergo_c6_supermini.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +makergo_c6_supermini.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +makergo_c6_supermini.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +makergo_c6_supermini.menu.PartitionScheme.custom=Custom +makergo_c6_supermini.menu.PartitionScheme.custom.build.partitions= +makergo_c6_supermini.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +makergo_c6_supermini.menu.CPUFreq.160=160MHz (WiFi) +makergo_c6_supermini.menu.CPUFreq.160.build.f_cpu=160000000L +makergo_c6_supermini.menu.CPUFreq.80=80MHz (WiFi) +makergo_c6_supermini.menu.CPUFreq.80.build.f_cpu=80000000L +makergo_c6_supermini.menu.CPUFreq.40=40MHz +makergo_c6_supermini.menu.CPUFreq.40.build.f_cpu=40000000L +makergo_c6_supermini.menu.CPUFreq.20=20MHz +makergo_c6_supermini.menu.CPUFreq.20.build.f_cpu=20000000L +makergo_c6_supermini.menu.CPUFreq.10=10MHz +makergo_c6_supermini.menu.CPUFreq.10.build.f_cpu=10000000L + +makergo_c6_supermini.menu.FlashMode.qio=QIO +makergo_c6_supermini.menu.FlashMode.qio.build.flash_mode=dio +makergo_c6_supermini.menu.FlashMode.qio.build.boot=qio +makergo_c6_supermini.menu.FlashMode.dio=DIO +makergo_c6_supermini.menu.FlashMode.dio.build.flash_mode=dio +makergo_c6_supermini.menu.FlashMode.dio.build.boot=dio + +makergo_c6_supermini.menu.FlashFreq.80=80MHz +makergo_c6_supermini.menu.FlashFreq.80.build.flash_freq=80m +makergo_c6_supermini.menu.FlashFreq.40=40MHz +makergo_c6_supermini.menu.FlashFreq.40.build.flash_freq=40m + +makergo_c6_supermini.menu.FlashSize.4M=4MB (32Mb) +makergo_c6_supermini.menu.FlashSize.4M.build.flash_size=4MB + +makergo_c6_supermini.menu.UploadSpeed.921600=921600 +makergo_c6_supermini.menu.UploadSpeed.921600.upload.speed=921600 +makergo_c6_supermini.menu.UploadSpeed.115200=115200 +makergo_c6_supermini.menu.UploadSpeed.115200.upload.speed=115200 +makergo_c6_supermini.menu.UploadSpeed.256000.windows=256000 +makergo_c6_supermini.menu.UploadSpeed.256000.upload.speed=256000 +makergo_c6_supermini.menu.UploadSpeed.230400.windows.upload.speed=256000 +makergo_c6_supermini.menu.UploadSpeed.230400=230400 +makergo_c6_supermini.menu.UploadSpeed.230400.upload.speed=230400 +makergo_c6_supermini.menu.UploadSpeed.460800.linux=460800 +makergo_c6_supermini.menu.UploadSpeed.460800.macosx=460800 +makergo_c6_supermini.menu.UploadSpeed.460800.upload.speed=460800 +makergo_c6_supermini.menu.UploadSpeed.512000.windows=512000 +makergo_c6_supermini.menu.UploadSpeed.512000.upload.speed=512000 + +makergo_c6_supermini.menu.DebugLevel.none=None +makergo_c6_supermini.menu.DebugLevel.none.build.code_debug=0 +makergo_c6_supermini.menu.DebugLevel.error=Error +makergo_c6_supermini.menu.DebugLevel.error.build.code_debug=1 +makergo_c6_supermini.menu.DebugLevel.warn=Warn +makergo_c6_supermini.menu.DebugLevel.warn.build.code_debug=2 +makergo_c6_supermini.menu.DebugLevel.info=Info +makergo_c6_supermini.menu.DebugLevel.info.build.code_debug=3 +makergo_c6_supermini.menu.DebugLevel.debug=Debug +makergo_c6_supermini.menu.DebugLevel.debug.build.code_debug=4 +makergo_c6_supermini.menu.DebugLevel.verbose=Verbose +makergo_c6_supermini.menu.DebugLevel.verbose.build.code_debug=5 + +makergo_c6_supermini.menu.EraseFlash.none=Disabled +makergo_c6_supermini.menu.EraseFlash.none.upload.erase_cmd= +makergo_c6_supermini.menu.EraseFlash.all=Enabled +makergo_c6_supermini.menu.EraseFlash.all.upload.erase_cmd=-e + +makergo_c6_supermini.menu.ZigbeeMode.default=Disabled +makergo_c6_supermini.menu.ZigbeeMode.default.build.zigbee_mode= +makergo_c6_supermini.menu.ZigbeeMode.default.build.zigbee_libs= +makergo_c6_supermini.menu.ZigbeeMode.ed=Zigbee ED (end device) +makergo_c6_supermini.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +makergo_c6_supermini.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +makergo_c6_supermini.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +makergo_c6_supermini.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +makergo_c6_supermini.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## +# ThingPulse ePulse Feather + +epulse_feather.name=ThingPulse ePulse Feather + +epulse_feather.bootloader.tool=esptool_py +epulse_feather.bootloader.tool.default=esptool_py + +epulse_feather.upload.tool=esptool_py +epulse_feather.upload.tool.default=esptool_py +epulse_feather.upload.tool.network=esp_ota + +epulse_feather.upload.maximum_size=1310720 +epulse_feather.upload.maximum_data_size=327680 +epulse_feather.upload.flags= +epulse_feather.upload.extra_flags= + +epulse_feather.serial.disableDTR=true +epulse_feather.serial.disableRTS=true + +epulse_feather.build.tarch=xtensa +epulse_feather.build.bootloader_addr=0x1000 +epulse_feather.build.target=esp32 +epulse_feather.build.mcu=esp32 +epulse_feather.build.core=esp32 +epulse_feather.build.variant=thingpulse_epulse_feather +epulse_feather.build.board=THINGPULSE_EPULSE_FEATHER + +epulse_feather.build.f_cpu=240000000L +epulse_feather.build.flash_size=8MB +epulse_feather.build.flash_freq=80m +epulse_feather.build.flash_mode=dio +epulse_feather.build.boot=dio +epulse_feather.build.partitions=default_8MB +epulse_feather.build.defines= +epulse_feather.build.loop_core= +epulse_feather.build.event_core= + +epulse_feather.menu.PSRAM.enabled=Enabled +epulse_feather.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +epulse_feather.menu.PSRAM.disabled=Disabled +epulse_feather.menu.PSRAM.disabled.build.defines= + +epulse_feather.menu.LoopCore.1=Core 1 +epulse_feather.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +epulse_feather.menu.LoopCore.0=Core 0 +epulse_feather.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +epulse_feather.menu.EventsCore.1=Core 1 +epulse_feather.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +epulse_feather.menu.EventsCore.0=Core 0 +epulse_feather.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +epulse_feather.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +epulse_feather.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +epulse_feather.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +epulse_feather.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +epulse_feather.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +epulse_feather.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +epulse_feather.menu.CPUFreq.240=240MHz (WiFi/BT) +epulse_feather.menu.CPUFreq.240.build.f_cpu=240000000L +epulse_feather.menu.CPUFreq.160=160MHz (WiFi/BT) +epulse_feather.menu.CPUFreq.160.build.f_cpu=160000000L +epulse_feather.menu.CPUFreq.80=80MHz (WiFi/BT) +epulse_feather.menu.CPUFreq.80.build.f_cpu=80000000L +epulse_feather.menu.CPUFreq.40=40MHz +epulse_feather.menu.CPUFreq.40.build.f_cpu=40000000L +epulse_feather.menu.CPUFreq.20=20MHz +epulse_feather.menu.CPUFreq.20.build.f_cpu=20000000L +epulse_feather.menu.CPUFreq.10=10MHz +epulse_feather.menu.CPUFreq.10.build.f_cpu=10000000L + +epulse_feather.menu.FlashFreq.80=80MHz +epulse_feather.menu.FlashFreq.80.build.flash_freq=80m +epulse_feather.menu.FlashFreq.40=40MHz +epulse_feather.menu.FlashFreq.40.build.flash_freq=40m + +epulse_feather.menu.UploadSpeed.921600=921600 +epulse_feather.menu.UploadSpeed.921600.upload.speed=921600 +epulse_feather.menu.UploadSpeed.115200=115200 +epulse_feather.menu.UploadSpeed.115200.upload.speed=115200 +epulse_feather.menu.UploadSpeed.256000.windows=256000 +epulse_feather.menu.UploadSpeed.256000.upload.speed=256000 +epulse_feather.menu.UploadSpeed.230400.windows.upload.speed=256000 +epulse_feather.menu.UploadSpeed.230400=230400 +epulse_feather.menu.UploadSpeed.230400.upload.speed=230400 +epulse_feather.menu.UploadSpeed.460800.linux=460800 +epulse_feather.menu.UploadSpeed.460800.macosx=460800 +epulse_feather.menu.UploadSpeed.460800.upload.speed=460800 +epulse_feather.menu.UploadSpeed.512000.windows=512000 +epulse_feather.menu.UploadSpeed.512000.upload.speed=512000 + +epulse_feather.menu.DebugLevel.none=None +epulse_feather.menu.DebugLevel.none.build.code_debug=0 +epulse_feather.menu.DebugLevel.error=Error +epulse_feather.menu.DebugLevel.error.build.code_debug=1 +epulse_feather.menu.DebugLevel.warn=Warn +epulse_feather.menu.DebugLevel.warn.build.code_debug=2 +epulse_feather.menu.DebugLevel.info=Info +epulse_feather.menu.DebugLevel.info.build.code_debug=3 +epulse_feather.menu.DebugLevel.debug=Debug +epulse_feather.menu.DebugLevel.debug.build.code_debug=4 +epulse_feather.menu.DebugLevel.verbose=Verbose +epulse_feather.menu.DebugLevel.verbose.build.code_debug=5 + +epulse_feather.menu.EraseFlash.none=Disabled +epulse_feather.menu.EraseFlash.none.upload.erase_cmd= +epulse_feather.menu.EraseFlash.all=Enabled +epulse_feather.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# ThingPulse ePulse Feather C6 + +epulse_feather_c6.name=ThingPulse ePulse Feather C6 + +epulse_feather_c6.bootloader.tool=esptool_py +epulse_feather_c6.bootloader.tool.default=esptool_py + +epulse_feather_c6.upload.tool=esptool_py +epulse_feather_c6.upload.tool.default=esptool_py +epulse_feather_c6.upload.tool.network=esp_ota + +epulse_feather_c6.upload.maximum_size=1310720 +epulse_feather_c6.upload.maximum_data_size=327680 +epulse_feather_c6.upload.flags= +epulse_feather_c6.upload.extra_flags= +epulse_feather_c6.upload.use_1200bps_touch=false +epulse_feather_c6.upload.wait_for_upload_port=false + +epulse_feather_c6.serial.disableDTR=false +epulse_feather_c6.serial.disableRTS=false + +epulse_feather_c6.build.tarch=riscv32 +epulse_feather_c6.build.target=esp +epulse_feather_c6.build.mcu=esp32c6 +epulse_feather_c6.build.core=esp32 +epulse_feather_c6.build.variant=thingpulse_epulse_feather_c6 +epulse_feather_c6.build.board=THINGPULSE_EPULSE_FEATHER_C6 +epulse_feather_c6.build.bootloader_addr=0x0 + +epulse_feather_c6.build.cdc_on_boot=0 +epulse_feather_c6.build.f_cpu=160000000L +epulse_feather_c6.build.flash_size=4MB +epulse_feather_c6.build.flash_freq=80m +epulse_feather_c6.build.flash_mode=qio +epulse_feather_c6.build.boot=qio +epulse_feather_c6.build.partitions=default +epulse_feather_c6.build.defines= + +epulse_feather_c6.menu.JTAGAdapter.default=Disabled +epulse_feather_c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +epulse_feather_c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +epulse_feather_c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +epulse_feather_c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +epulse_feather_c6.menu.JTAGAdapter.external=FTDI Adapter +epulse_feather_c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +epulse_feather_c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +epulse_feather_c6.menu.JTAGAdapter.bridge=ESP USB Bridge +epulse_feather_c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +epulse_feather_c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +epulse_feather_c6.menu.CDCOnBoot.default=Disabled +epulse_feather_c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +epulse_feather_c6.menu.CDCOnBoot.cdc=Enabled +epulse_feather_c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +epulse_feather_c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.default.build.partitions=default +epulse_feather_c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +epulse_feather_c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +epulse_feather_c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.minimal.build.partitions=minimal +epulse_feather_c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +epulse_feather_c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +epulse_feather_c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +epulse_feather_c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +epulse_feather_c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +epulse_feather_c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +epulse_feather_c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +epulse_feather_c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +epulse_feather_c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +epulse_feather_c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +epulse_feather_c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +epulse_feather_c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +epulse_feather_c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +epulse_feather_c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +epulse_feather_c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +epulse_feather_c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +epulse_feather_c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +epulse_feather_c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +epulse_feather_c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +epulse_feather_c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +epulse_feather_c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +epulse_feather_c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +epulse_feather_c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +epulse_feather_c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +epulse_feather_c6.menu.PartitionScheme.custom=Custom +epulse_feather_c6.menu.PartitionScheme.custom.build.partitions= +epulse_feather_c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +epulse_feather_c6.menu.CPUFreq.160=160MHz (WiFi) +epulse_feather_c6.menu.CPUFreq.160.build.f_cpu=160000000L +epulse_feather_c6.menu.CPUFreq.120=120MHz (WiFi) +epulse_feather_c6.menu.CPUFreq.120.build.f_cpu=120000000L +epulse_feather_c6.menu.CPUFreq.80=80MHz (WiFi) +epulse_feather_c6.menu.CPUFreq.80.build.f_cpu=80000000L +epulse_feather_c6.menu.CPUFreq.40=40MHz +epulse_feather_c6.menu.CPUFreq.40.build.f_cpu=40000000L +epulse_feather_c6.menu.CPUFreq.20=20MHz +epulse_feather_c6.menu.CPUFreq.20.build.f_cpu=20000000L +epulse_feather_c6.menu.CPUFreq.10=10MHz +epulse_feather_c6.menu.CPUFreq.10.build.f_cpu=10000000L + +epulse_feather_c6.menu.FlashMode.qio=QIO +epulse_feather_c6.menu.FlashMode.qio.build.flash_mode=dio +epulse_feather_c6.menu.FlashMode.qio.build.boot=qio +epulse_feather_c6.menu.FlashMode.dio=DIO +epulse_feather_c6.menu.FlashMode.dio.build.flash_mode=dio +epulse_feather_c6.menu.FlashMode.dio.build.boot=dio + +epulse_feather_c6.menu.FlashFreq.80=80MHz +epulse_feather_c6.menu.FlashFreq.80.build.flash_freq=80m +epulse_feather_c6.menu.FlashFreq.40=40MHz +epulse_feather_c6.menu.FlashFreq.40.build.flash_freq=40m + +epulse_feather_c6.menu.FlashSize.4M=4MB (32Mb) +epulse_feather_c6.menu.FlashSize.4M.build.flash_size=4MB +epulse_feather_c6.menu.FlashSize.2M=2MB (16Mb) +epulse_feather_c6.menu.FlashSize.2M.build.flash_size=2MB + +epulse_feather_c6.menu.UploadSpeed.921600=921600 +epulse_feather_c6.menu.UploadSpeed.921600.upload.speed=921600 +epulse_feather_c6.menu.UploadSpeed.115200=115200 +epulse_feather_c6.menu.UploadSpeed.115200.upload.speed=115200 +epulse_feather_c6.menu.UploadSpeed.256000.windows=256000 +epulse_feather_c6.menu.UploadSpeed.256000.upload.speed=256000 +epulse_feather_c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +epulse_feather_c6.menu.UploadSpeed.230400=230400 +epulse_feather_c6.menu.UploadSpeed.230400.upload.speed=230400 +epulse_feather_c6.menu.UploadSpeed.460800.linux=460800 +epulse_feather_c6.menu.UploadSpeed.460800.macosx=460800 +epulse_feather_c6.menu.UploadSpeed.460800.upload.speed=460800 +epulse_feather_c6.menu.UploadSpeed.512000.windows=512000 +epulse_feather_c6.menu.UploadSpeed.512000.upload.speed=512000 + +epulse_feather_c6.menu.DebugLevel.none=None +epulse_feather_c6.menu.DebugLevel.none.build.code_debug=0 +epulse_feather_c6.menu.DebugLevel.error=Error +epulse_feather_c6.menu.DebugLevel.error.build.code_debug=1 +epulse_feather_c6.menu.DebugLevel.warn=Warn +epulse_feather_c6.menu.DebugLevel.warn.build.code_debug=2 +epulse_feather_c6.menu.DebugLevel.info=Info +epulse_feather_c6.menu.DebugLevel.info.build.code_debug=3 +epulse_feather_c6.menu.DebugLevel.debug=Debug +epulse_feather_c6.menu.DebugLevel.debug.build.code_debug=4 +epulse_feather_c6.menu.DebugLevel.verbose=Verbose +epulse_feather_c6.menu.DebugLevel.verbose.build.code_debug=5 + +epulse_feather_c6.menu.EraseFlash.none=Disabled +epulse_feather_c6.menu.EraseFlash.none.upload.erase_cmd= +epulse_feather_c6.menu.EraseFlash.all=Enabled +epulse_feather_c6.menu.EraseFlash.all.upload.erase_cmd=-e + +epulse_feather_c6.menu.ZigbeeMode.default=Disabled +epulse_feather_c6.menu.ZigbeeMode.default.build.zigbee_mode= +epulse_feather_c6.menu.ZigbeeMode.default.build.zigbee_libs= +epulse_feather_c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +epulse_feather_c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +epulse_feather_c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +epulse_feather_c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +epulse_feather_c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +epulse_feather_c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +Geekble_ESP32C3.name=Geekble Mini ESP32-C3 + +Geekble_ESP32C3.bootloader.tool=esptool_py +Geekble_ESP32C3.bootloader.tool.default=esptool_py + +Geekble_ESP32C3.upload.tool=esptool_py +Geekble_ESP32C3.upload.tool.default=esptool_py +Geekble_ESP32C3.upload.tool.network=esp_ota + +Geekble_ESP32C3.upload.maximum_size=1310720 +Geekble_ESP32C3.upload.maximum_data_size=327680 +Geekble_ESP32C3.upload.flags= +Geekble_ESP32C3.upload.extra_flags= +Geekble_ESP32C3.upload.use_1200bps_touch=false +Geekble_ESP32C3.upload.wait_for_upload_port=false + +Geekble_ESP32C3.serial.disableDTR=true +Geekble_ESP32C3.serial.disableRTS=true + +Geekble_ESP32C3.build.tarch=riscv32 +Geekble_ESP32C3.build.target=esp +Geekble_ESP32C3.build.mcu=esp32c3 +Geekble_ESP32C3.build.core=esp32 +Geekble_ESP32C3.build.variant=Geekble_ESP32C3 +Geekble_ESP32C3.build.board=GEEKBLE_ESP32C3 +Geekble_ESP32C3.build.bootloader_addr=0x0 + +Geekble_ESP32C3.build.cdc_on_boot=1 +Geekble_ESP32C3.build.f_cpu=160000000L +Geekble_ESP32C3.build.flash_size=4MB +Geekble_ESP32C3.build.flash_freq=80m +Geekble_ESP32C3.build.flash_mode=dio +Geekble_ESP32C3.build.boot=qio +Geekble_ESP32C3.build.partitions=default +Geekble_ESP32C3.build.defines= + +Geekble_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Geekble_ESP32C3.menu.PartitionScheme.default.build.partitions=default +Geekble_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Geekble_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Geekble_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Geekble_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +Geekble_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Geekble_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Geekble_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Geekble_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Geekble_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Geekble_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Geekble_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Geekble_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Geekble_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +Geekble_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +Geekble_ESP32C3.menu.UploadSpeed.921600=921600 (Default) +Geekble_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600 +Geekble_ESP32C3.menu.UploadSpeed.115200=115200 +Geekble_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200 +Geekble_ESP32C3.menu.UploadSpeed.256000.windows=256000 +Geekble_ESP32C3.menu.UploadSpeed.256000.upload.speed=256000 +Geekble_ESP32C3.menu.UploadSpeed.230400.windows.upload.speed=256000 +Geekble_ESP32C3.menu.UploadSpeed.230400=230400 +Geekble_ESP32C3.menu.UploadSpeed.230400.upload.speed=230400 +Geekble_ESP32C3.menu.UploadSpeed.460800.linux=460800 +Geekble_ESP32C3.menu.UploadSpeed.460800.macosx=460800 +Geekble_ESP32C3.menu.UploadSpeed.460800.upload.speed=460800 +Geekble_ESP32C3.menu.UploadSpeed.512000.windows=512000 +Geekble_ESP32C3.menu.UploadSpeed.512000.upload.speed=512000 + +Geekble_ESP32C3.menu.DebugLevel.none=None +Geekble_ESP32C3.menu.DebugLevel.none.build.code_debug=0 +Geekble_ESP32C3.menu.DebugLevel.error=Error +Geekble_ESP32C3.menu.DebugLevel.error.build.code_debug=1 +Geekble_ESP32C3.menu.DebugLevel.warn=Warn +Geekble_ESP32C3.menu.DebugLevel.warn.build.code_debug=2 +Geekble_ESP32C3.menu.DebugLevel.info=Info +Geekble_ESP32C3.menu.DebugLevel.info.build.code_debug=3 +Geekble_ESP32C3.menu.DebugLevel.debug=Debug +Geekble_ESP32C3.menu.DebugLevel.debug.build.code_debug=4 +Geekble_ESP32C3.menu.DebugLevel.verbose=Verbose +Geekble_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5 + +Geekble_ESP32C3.menu.EraseFlash.none=Disabled +Geekble_ESP32C3.menu.EraseFlash.none.upload.erase_cmd= +Geekble_ESP32C3.menu.EraseFlash.all=Enabled +Geekble_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +Geekble_Nano_ESP32S3.name=Geekble nano ESP32-S3 +Geekble_Nano_ESP32S3.vid.0=0x303a +Geekble_Nano_ESP32S3.pid.0= 0x82C5 +Geekble_Nano_ESP32S3.upload_port.0.vid=0x303a +Geekble_Nano_ESP32S3.upload_port.0.pid= 0x82C5 + +Geekble_Nano_ESP32S3.bootloader.tool=esptool_py +Geekble_Nano_ESP32S3.bootloader.tool.default=esptool_py + +Geekble_Nano_ESP32S3.upload.tool=esptool_py +Geekble_Nano_ESP32S3.upload.tool.default=esptool_py +Geekble_Nano_ESP32S3.upload.tool.network=esp_ota + +Geekble_Nano_ESP32S3.upload.maximum_size=1310720 +Geekble_Nano_ESP32S3.upload.maximum_data_size=327680 +Geekble_Nano_ESP32S3.upload.speed=921600 +Geekble_Nano_ESP32S3.upload.flags= +Geekble_Nano_ESP32S3.upload.extra_flags= +Geekble_Nano_ESP32S3.upload.use_1200bps_touch=false +Geekble_Nano_ESP32S3.upload.wait_for_upload_port=false + +Geekble_Nano_ESP32S3.serial.disableDTR=false +Geekble_Nano_ESP32S3.serial.disableRTS=false + +Geekble_Nano_ESP32S3.build.tarch=xtensa +Geekble_Nano_ESP32S3.build.bootloader_addr=0x0 +Geekble_Nano_ESP32S3.build.target=esp32s3 +Geekble_Nano_ESP32S3.build.mcu=esp32s3 +Geekble_Nano_ESP32S3.build.core=esp32 +Geekble_Nano_ESP32S3.build.variant=Geekble_Nano_ESP32S3 +Geekble_Nano_ESP32S3.build.board=GEEKBLE_NANO_ESP32S3 + +Geekble_Nano_ESP32S3.build.usb_mode=1 +Geekble_Nano_ESP32S3.build.cdc_on_boot=1 +Geekble_Nano_ESP32S3.build.msc_on_boot=0 +Geekble_Nano_ESP32S3.build.dfu_on_boot=0 +Geekble_Nano_ESP32S3.build.f_cpu=240000000L +Geekble_Nano_ESP32S3.build.flash_size=4MB +Geekble_Nano_ESP32S3.build.flash_freq=80m +Geekble_Nano_ESP32S3.build.flash_mode=dio +Geekble_Nano_ESP32S3.build.boot=qio +Geekble_Nano_ESP32S3.build.partitions=default +Geekble_Nano_ESP32S3.build.defines= +Geekble_Nano_ESP32S3.build.memory_type=qio_qspi +Geekble_Nano_ESP32S3.build.loop_core=-DARDUINO_RUNNING_CORE=1 +Geekble_Nano_ESP32S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +Geekble_Nano_ESP32S3.menu.USBMode.default=USB-OTG (TinyUSB) +Geekble_Nano_ESP32S3.menu.USBMode.default.build.usb_mode=0 +Geekble_Nano_ESP32S3.menu.USBMode.default.build.cdc_on_boot=1 +Geekble_Nano_ESP32S3.menu.USBMode.hwcdc=Hardware CDC and JTAG +Geekble_Nano_ESP32S3.menu.USBMode.hwcdc.build.usb_mode=1 +Geekble_Nano_ESP32S3.menu.USBMode.hwcdc.build.cdc_on_boot=1 + +Geekble_Nano_ESP32S3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +Geekble_Nano_ESP32S3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +Geekble_Nano_ESP32S3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +Geekble_Nano_ESP32S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.default.build.partitions=default +Geekble_Nano_ESP32S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota.build.partitions=no_ota +Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app.build.partitions=huge_app +Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker=RainMaker 4MB +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs.build.custom_partitions=ota_nofs_4MB +Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app.build.custom_partitions=max_app_4MB +Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app.upload.maximum_size=4063232 +Geekble_Nano_ESP32S3.menu.PartitionScheme.custom=Custom +Geekble_Nano_ESP32S3.menu.PartitionScheme.custom.build.partitions= +Geekble_Nano_ESP32S3.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +Geekble_Nano_ESP32S3.menu.PSRAM.disabled=Disabled +Geekble_Nano_ESP32S3.menu.PSRAM.disabled.build.defines= +Geekble_Nano_ESP32S3.menu.PSRAM.disabled.build.psram_type=qspi +Geekble_Nano_ESP32S3.menu.PSRAM.enabled=Enabled +Geekble_Nano_ESP32S3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +Geekble_Nano_ESP32S3.menu.PSRAM.enabled.build.psram_type=qspi + +Geekble_Nano_ESP32S3.menu.DebugLevel.none=None +Geekble_Nano_ESP32S3.menu.DebugLevel.none.build.code_debug=0 +Geekble_Nano_ESP32S3.menu.DebugLevel.error=Error +Geekble_Nano_ESP32S3.menu.DebugLevel.error.build.code_debug=1 +Geekble_Nano_ESP32S3.menu.DebugLevel.warn=Warn +Geekble_Nano_ESP32S3.menu.DebugLevel.warn.build.code_debug=2 +Geekble_Nano_ESP32S3.menu.DebugLevel.info=Info +Geekble_Nano_ESP32S3.menu.DebugLevel.info.build.code_debug=3 +Geekble_Nano_ESP32S3.menu.DebugLevel.debug=Debug +Geekble_Nano_ESP32S3.menu.DebugLevel.debug.build.code_debug=4 +Geekble_Nano_ESP32S3.menu.DebugLevel.verbose=Verbose +Geekble_Nano_ESP32S3.menu.DebugLevel.verbose.build.code_debug=5 + +Geekble_Nano_ESP32S3.menu.EraseFlash.none=Disabled +Geekble_Nano_ESP32S3.menu.EraseFlash.none.upload.erase_cmd= +Geekble_Nano_ESP32S3.menu.EraseFlash.all=Enabled +Geekble_Nano_ESP32S3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_zero.name=Waveshare ESP32-S3-Zero +waveshare_esp32_s3_zero.vid.0=0x303a +waveshare_esp32_s3_zero.pid.0=0x822B +waveshare_esp32_s3_zero.upload_port.0.vid=0x303a +waveshare_esp32_s3_zero.upload_port.0.pid=0x822B + +waveshare_esp32_s3_zero.bootloader.tool=esptool_py +waveshare_esp32_s3_zero.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_zero.upload.tool=esptool_py +waveshare_esp32_s3_zero.upload.tool.default=esptool_py +waveshare_esp32_s3_zero.upload.tool.network=esp_ota + +waveshare_esp32_s3_zero.upload.maximum_size=1310720 + +waveshare_esp32_s3_zero.upload.maximum_data_size=327680 +waveshare_esp32_s3_zero.upload.flags= +waveshare_esp32_s3_zero.upload.extra_flags= +waveshare_esp32_s3_zero.upload.use_1200bps_touch=false +waveshare_esp32_s3_zero.upload.wait_for_upload_port=false + +waveshare_esp32_s3_zero.serial.disableDTR=false +waveshare_esp32_s3_zero.serial.disableRTS=false + +waveshare_esp32_s3_zero.build.tarch=xtensa +waveshare_esp32_s3_zero.build.bootloader_addr=0x0 +waveshare_esp32_s3_zero.build.target=esp32s3 +waveshare_esp32_s3_zero.build.mcu=esp32s3 +waveshare_esp32_s3_zero.build.core=esp32 +waveshare_esp32_s3_zero.build.variant=waveshare_esp32_s3_zero +waveshare_esp32_s3_zero.build.board=WAVESHARE_ESP32_S3_ZERO + +waveshare_esp32_s3_zero.build.usb_mode=1 +waveshare_esp32_s3_zero.build.cdc_on_boot=0 +waveshare_esp32_s3_zero.build.msc_on_boot=0 +waveshare_esp32_s3_zero.build.dfu_on_boot=0 +waveshare_esp32_s3_zero.build.f_cpu=240000000L +waveshare_esp32_s3_zero.build.flash_size=4MB +waveshare_esp32_s3_zero.build.flash_freq=80m +waveshare_esp32_s3_zero.build.flash_mode=dio +waveshare_esp32_s3_zero.build.boot=qio +waveshare_esp32_s3_zero.build.boot_freq=80m +waveshare_esp32_s3_zero.build.partitions=default +waveshare_esp32_s3_zero.build.defines= +waveshare_esp32_s3_zero.build.loop_core= +waveshare_esp32_s3_zero.build.event_core= +waveshare_esp32_s3_zero.build.psram_type=qspi +waveshare_esp32_s3_zero.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_zero.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_zero.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_zero.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_zero.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_zero.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_zero.menu.PSRAM.enabled.build.psram_type=qspi + +waveshare_esp32_s3_zero.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_zero.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_zero.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_zero.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_zero.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_zero.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_zero.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_zero.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_zero.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_zero.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_zero.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_zero.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_zero.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_zero.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_zero.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_zero.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_zero.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_zero.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_zero.menu.CDCOnBoot.default=Enabled +waveshare_esp32_s3_zero.menu.CDCOnBoot.default.build.cdc_on_boot=1 +waveshare_esp32_s3_zero.menu.CDCOnBoot.cdc=Disabled +waveshare_esp32_s3_zero.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +waveshare_esp32_s3_zero.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_zero.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_zero.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_zero.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_zero.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_zero.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_zero.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_zero.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_zero.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_zero.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_zero.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_zero.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_zero.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_zero.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_zero.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_zero.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs.build.custom_partitions=ota_nofs_4MB +waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_zero.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_zero.menu.PartitionScheme.all_app.build.custom_partitions=max_app_4MB +waveshare_esp32_s3_zero.menu.PartitionScheme.all_app.upload.maximum_size=4063232 +waveshare_esp32_s3_zero.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_zero.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_zero.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +waveshare_esp32_s3_zero.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_zero.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_zero.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_zero.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_zero.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_zero.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_zero.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_zero.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_zero.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_zero.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_zero.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_zero.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_zero.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_zero.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_zero.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_zero.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_zero.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_zero.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_zero.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_zero.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_zero.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_zero.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_zero.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_zero.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_zero.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_zero.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_zero.menu.DebugLevel.none=None +waveshare_esp32_s3_zero.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_zero.menu.DebugLevel.error=Error +waveshare_esp32_s3_zero.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_zero.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_zero.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_zero.menu.DebugLevel.info=Info +waveshare_esp32_s3_zero.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_zero.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_zero.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_zero.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_zero.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_zero.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_zero.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_zero.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_zero.menu.EraseFlash.all.upload.erase_cmd=-e + +###################################################### + +ws_esp32_s3_matrix.name=Waveshare ESP32-S3-Matrix +ws_esp32_s3_matrix.vid.0=0x303a +ws_esp32_s3_matrix.pid.0=0x81FB +ws_esp32_s3_matrix.upload_port.0.vid=0x303a +ws_esp32_s3_matrix.upload_port.0.pid=0x81FB + +ws_esp32_s3_matrix.bootloader.tool=esptool_py +ws_esp32_s3_matrix.bootloader.tool.default=esptool_py + +ws_esp32_s3_matrix.upload.tool=esptool_py +ws_esp32_s3_matrix.upload.tool.default=esptool_py +ws_esp32_s3_matrix.upload.tool.network=esp_ota + +ws_esp32_s3_matrix.upload.maximum_size=1310720 + +ws_esp32_s3_matrix.upload.maximum_data_size=327680 +ws_esp32_s3_matrix.upload.flags= +ws_esp32_s3_matrix.upload.extra_flags= +ws_esp32_s3_matrix.upload.use_1200bps_touch=false +ws_esp32_s3_matrix.upload.wait_for_upload_port=false + +ws_esp32_s3_matrix.serial.disableDTR=false +ws_esp32_s3_matrix.serial.disableRTS=false + +ws_esp32_s3_matrix.build.tarch=xtensa +ws_esp32_s3_matrix.build.bootloader_addr=0x0 +ws_esp32_s3_matrix.build.target=esp32s3 +ws_esp32_s3_matrix.build.mcu=esp32s3 +ws_esp32_s3_matrix.build.core=esp32 +ws_esp32_s3_matrix.build.variant=ws_esp32_s3_matrix +ws_esp32_s3_matrix.build.board=WS_ESP32_S3_MATRIX + +ws_esp32_s3_matrix.build.usb_mode=1 +ws_esp32_s3_matrix.build.cdc_on_boot=0 +ws_esp32_s3_matrix.build.msc_on_boot=0 +ws_esp32_s3_matrix.build.dfu_on_boot=0 +ws_esp32_s3_matrix.build.f_cpu=240000000L +ws_esp32_s3_matrix.build.flash_size=4MB +ws_esp32_s3_matrix.build.flash_freq=80m +ws_esp32_s3_matrix.build.flash_mode=dio +ws_esp32_s3_matrix.build.boot=qio +ws_esp32_s3_matrix.build.boot_freq=80m +ws_esp32_s3_matrix.build.partitions=default +ws_esp32_s3_matrix.build.defines= +ws_esp32_s3_matrix.build.loop_core= +ws_esp32_s3_matrix.build.event_core= +ws_esp32_s3_matrix.build.psram_type=qspi +ws_esp32_s3_matrix.build.memory_type={build.boot}_{build.psram_type} + +ws_esp32_s3_matrix.menu.PSRAM.disabled=Disabled +ws_esp32_s3_matrix.menu.PSRAM.disabled.build.defines= +ws_esp32_s3_matrix.menu.PSRAM.disabled.build.psram_type=qspi +ws_esp32_s3_matrix.menu.PSRAM.enabled=Enabled +ws_esp32_s3_matrix.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +ws_esp32_s3_matrix.menu.PSRAM.enabled.build.psram_type=qspi + +ws_esp32_s3_matrix.menu.FlashMode.qio=QIO 80MHz +ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_mode=dio +ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot=qio +ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot_freq=80m +ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_freq=80m +ws_esp32_s3_matrix.menu.FlashMode.qio120=QIO 120MHz +ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_mode=dio +ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot=qio +ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot_freq=120m +ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_freq=80m + +ws_esp32_s3_matrix.menu.FlashSize.4M=4MB (32Mb) +ws_esp32_s3_matrix.menu.FlashSize.4M.build.flash_size=4MB + +ws_esp32_s3_matrix.menu.LoopCore.1=Core 1 +ws_esp32_s3_matrix.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +ws_esp32_s3_matrix.menu.LoopCore.0=Core 0 +ws_esp32_s3_matrix.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +ws_esp32_s3_matrix.menu.EventsCore.1=Core 1 +ws_esp32_s3_matrix.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +ws_esp32_s3_matrix.menu.EventsCore.0=Core 0 +ws_esp32_s3_matrix.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +ws_esp32_s3_matrix.menu.USBMode.hwcdc=Hardware CDC and JTAG +ws_esp32_s3_matrix.menu.USBMode.hwcdc.build.usb_mode=1 +ws_esp32_s3_matrix.menu.USBMode.default=USB-OTG (TinyUSB) +ws_esp32_s3_matrix.menu.USBMode.default.build.usb_mode=0 + +ws_esp32_s3_matrix.menu.CDCOnBoot.default=Disabled +ws_esp32_s3_matrix.menu.CDCOnBoot.default.build.cdc_on_boot=0 +ws_esp32_s3_matrix.menu.CDCOnBoot.cdc=Enabled +ws_esp32_s3_matrix.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +ws_esp32_s3_matrix.menu.MSCOnBoot.default=Disabled +ws_esp32_s3_matrix.menu.MSCOnBoot.default.build.msc_on_boot=0 +ws_esp32_s3_matrix.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +ws_esp32_s3_matrix.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +ws_esp32_s3_matrix.menu.DFUOnBoot.default=Disabled +ws_esp32_s3_matrix.menu.DFUOnBoot.default.build.dfu_on_boot=0 +ws_esp32_s3_matrix.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +ws_esp32_s3_matrix.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +ws_esp32_s3_matrix.menu.UploadMode.default=UART0 / Hardware CDC +ws_esp32_s3_matrix.menu.UploadMode.default.upload.use_1200bps_touch=false +ws_esp32_s3_matrix.menu.UploadMode.default.upload.wait_for_upload_port=false +ws_esp32_s3_matrix.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.use_1200bps_touch=true +ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +ws_esp32_s3_matrix.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +ws_esp32_s3_matrix.menu.PartitionScheme.default.build.partitions=default +ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +ws_esp32_s3_matrix.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.build.partitions=no_ota +ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +ws_esp32_s3_matrix.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.build.partitions=huge_app +ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker=RainMaker 4MB +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +ws_esp32_s3_matrix.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +ws_esp32_s3_matrix.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +ws_esp32_s3_matrix.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +ws_esp32_s3_matrix.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +ws_esp32_s3_matrix.menu.PartitionScheme.custom=Custom +ws_esp32_s3_matrix.menu.PartitionScheme.custom.build.partitions= +ws_esp32_s3_matrix.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +ws_esp32_s3_matrix.menu.CPUFreq.240=240MHz (WiFi) +ws_esp32_s3_matrix.menu.CPUFreq.240.build.f_cpu=240000000L +ws_esp32_s3_matrix.menu.CPUFreq.160=160MHz (WiFi) +ws_esp32_s3_matrix.menu.CPUFreq.160.build.f_cpu=160000000L +ws_esp32_s3_matrix.menu.CPUFreq.80=80MHz (WiFi) +ws_esp32_s3_matrix.menu.CPUFreq.80.build.f_cpu=80000000L +ws_esp32_s3_matrix.menu.CPUFreq.40=40MHz +ws_esp32_s3_matrix.menu.CPUFreq.40.build.f_cpu=40000000L +ws_esp32_s3_matrix.menu.CPUFreq.20=20MHz +ws_esp32_s3_matrix.menu.CPUFreq.20.build.f_cpu=20000000L +ws_esp32_s3_matrix.menu.CPUFreq.10=10MHz +ws_esp32_s3_matrix.menu.CPUFreq.10.build.f_cpu=10000000L + +ws_esp32_s3_matrix.menu.UploadSpeed.921600=921600 +ws_esp32_s3_matrix.menu.UploadSpeed.921600.upload.speed=921600 +ws_esp32_s3_matrix.menu.UploadSpeed.115200=115200 +ws_esp32_s3_matrix.menu.UploadSpeed.115200.upload.speed=115200 +ws_esp32_s3_matrix.menu.UploadSpeed.256000.windows=256000 +ws_esp32_s3_matrix.menu.UploadSpeed.256000.upload.speed=256000 +ws_esp32_s3_matrix.menu.UploadSpeed.230400.windows.upload.speed=256000 +ws_esp32_s3_matrix.menu.UploadSpeed.230400=230400 +ws_esp32_s3_matrix.menu.UploadSpeed.230400.upload.speed=230400 +ws_esp32_s3_matrix.menu.UploadSpeed.460800.linux=460800 +ws_esp32_s3_matrix.menu.UploadSpeed.460800.macosx=460800 +ws_esp32_s3_matrix.menu.UploadSpeed.460800.upload.speed=460800 +ws_esp32_s3_matrix.menu.UploadSpeed.512000.windows=512000 +ws_esp32_s3_matrix.menu.UploadSpeed.512000.upload.speed=512000 + +ws_esp32_s3_matrix.menu.DebugLevel.none=None +ws_esp32_s3_matrix.menu.DebugLevel.none.build.code_debug=0 +ws_esp32_s3_matrix.menu.DebugLevel.error=Error +ws_esp32_s3_matrix.menu.DebugLevel.error.build.code_debug=1 +ws_esp32_s3_matrix.menu.DebugLevel.warn=Warn +ws_esp32_s3_matrix.menu.DebugLevel.warn.build.code_debug=2 +ws_esp32_s3_matrix.menu.DebugLevel.info=Info +ws_esp32_s3_matrix.menu.DebugLevel.info.build.code_debug=3 +ws_esp32_s3_matrix.menu.DebugLevel.debug=Debug +ws_esp32_s3_matrix.menu.DebugLevel.debug.build.code_debug=4 +ws_esp32_s3_matrix.menu.DebugLevel.verbose=Verbose +ws_esp32_s3_matrix.menu.DebugLevel.verbose.build.code_debug=5 + +ws_esp32_s3_matrix.menu.EraseFlash.none=Disabled +ws_esp32_s3_matrix.menu.EraseFlash.none.upload.erase_cmd= +ws_esp32_s3_matrix.menu.EraseFlash.all=Enabled +ws_esp32_s3_matrix.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_169.name=Waveshare ESP32-S3-Touch-LCD-1.69 +waveshare_esp32_s3_touch_lcd_169.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_169.pid.0=0x821E +waveshare_esp32_s3_touch_lcd_169.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_169.upload_port.0.pid=0x821E + +waveshare_esp32_s3_touch_lcd_169.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_169.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_169.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_169.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_169.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_169.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_169.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_169.upload.flags= +waveshare_esp32_s3_touch_lcd_169.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_169.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_169.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_169.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_169.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_169.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_169.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_169.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_169.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_169.build.core=esp32 +waveshare_esp32_s3_touch_lcd_169.build.variant=waveshare_esp32_s3_touch_lcd_169 +waveshare_esp32_s3_touch_lcd_169.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_169 + +waveshare_esp32_s3_touch_lcd_169.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_169.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_169.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_169.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_169.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_169.build.boot=qio +waveshare_esp32_s3_touch_lcd_169.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_169.build.partitions=default +waveshare_esp32_s3_touch_lcd_169.build.defines= +waveshare_esp32_s3_touch_lcd_169.build.loop_core= +waveshare_esp32_s3_touch_lcd_169.build.event_core= +waveshare_esp32_s3_touch_lcd_169.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_169.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_169.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_169.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_169.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_169.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_amoled_18.name=Waveshare ESP32-S3-Touch-AMOLED-1.8 +waveshare_esp32_s3_touch_amoled_18.vid.0=0x303a +waveshare_esp32_s3_touch_amoled_18.pid.0=0x8255 +waveshare_esp32_s3_touch_amoled_18.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_amoled_18.upload_port.0.pid=0x8255 + +waveshare_esp32_s3_touch_amoled_18.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_18.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_18.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_18.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_18.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_18.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_18.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_18.upload.flags= +waveshare_esp32_s3_touch_amoled_18.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_18.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_18.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_18.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_18.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_18.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_18.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_18.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_18.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_18.build.core=esp32 +waveshare_esp32_s3_touch_amoled_18.build.variant=waveshare_esp32_s3_touch_amoled_18 +waveshare_esp32_s3_touch_amoled_18.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_18 + +waveshare_esp32_s3_touch_amoled_18.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_18.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_18.build.flash_size=16MB +waveshare_esp32_s3_touch_amoled_18.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_18.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_18.build.boot=qio +waveshare_esp32_s3_touch_amoled_18.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_18.build.partitions=default +waveshare_esp32_s3_touch_amoled_18.build.defines= +waveshare_esp32_s3_touch_amoled_18.build.loop_core= +waveshare_esp32_s3_touch_amoled_18.build.event_core= +waveshare_esp32_s3_touch_amoled_18.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_18.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_18.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_18.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_18.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_18.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_amoled_206.name=Waveshare ESP32-S3-Touch-AMOLED-2.06 + +waveshare_esp32_s3_touch_amoled_206.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_206.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_206.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_206.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_206.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_206.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_206.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_206.upload.flags= +waveshare_esp32_s3_touch_amoled_206.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_206.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_206.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_206.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_206.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_206.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_206.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_206.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_206.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_206.build.core=esp32 +waveshare_esp32_s3_touch_amoled_206.build.variant=waveshare_esp32_s3_touch_amoled_206 +waveshare_esp32_s3_touch_amoled_206.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_206 + +waveshare_esp32_s3_touch_amoled_206.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_206.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_206.build.flash_size=32MB + +waveshare_esp32_s3_touch_amoled_206.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_206.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_206.build.boot=qio +waveshare_esp32_s3_touch_amoled_206.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_206.build.partitions=default +waveshare_esp32_s3_touch_amoled_206.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_206.build.loop_core= +waveshare_esp32_s3_touch_amoled_206.build.event_core= +waveshare_esp32_s3_touch_amoled_206.build.psram_type=opi +waveshare_esp32_s3_touch_amoled_206.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_206.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_206.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_206.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_206.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_206.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_206.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_206.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_206.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_206.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_206.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_206.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_206.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_206.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_206.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_206.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_206.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_206.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_206.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_206.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_206.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_206.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_206.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_206.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_206.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_206.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.default_32MB=Default 32MB with spiffs (12.5MB APP/6.75MB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.default_32MB.build.partitions=default_32MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.max_app_32MB=Max APP 32MB (31.4 MB) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.max_app_32MB.build.custom_partitions=max_app_32MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.max_app_32MB.upload.maximum_size=33423360 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_206.menu.PartitionScheme.custom.upload.maximum_size=33554432 + +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_206.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_206.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_206.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_206.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_206.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_206.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_206.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_lcd_169.name=Waveshare ESP32-S3-LCD-1.69 +waveshare_esp32_s3_lcd_169.vid.0=0x303a +waveshare_esp32_s3_lcd_169.pid.0=0x8221 +waveshare_esp32_s3_lcd_169.upload_port.0.vid=0x303a +waveshare_esp32_s3_lcd_169.upload_port.0.pid=0x8221 + +waveshare_esp32_s3_lcd_169.bootloader.tool=esptool_py +waveshare_esp32_s3_lcd_169.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_lcd_169.upload.tool=esptool_py +waveshare_esp32_s3_lcd_169.upload.tool.default=esptool_py +waveshare_esp32_s3_lcd_169.upload.tool.network=esp_ota + +waveshare_esp32_s3_lcd_169.upload.maximum_size=1310720 + +waveshare_esp32_s3_lcd_169.upload.maximum_data_size=327680 +waveshare_esp32_s3_lcd_169.upload.flags= +waveshare_esp32_s3_lcd_169.upload.extra_flags= +waveshare_esp32_s3_lcd_169.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_169.upload.wait_for_upload_port=false + +waveshare_esp32_s3_lcd_169.serial.disableDTR=false +waveshare_esp32_s3_lcd_169.serial.disableRTS=false + +waveshare_esp32_s3_lcd_169.build.tarch=xtensa +waveshare_esp32_s3_lcd_169.build.bootloader_addr=0x0 +waveshare_esp32_s3_lcd_169.build.target=esp32s3 +waveshare_esp32_s3_lcd_169.build.mcu=esp32s3 +waveshare_esp32_s3_lcd_169.build.core=esp32 +waveshare_esp32_s3_lcd_169.build.variant=waveshare_esp32_s3_lcd_169 +waveshare_esp32_s3_lcd_169.build.board=WAVESHARE_ESP32_S3_LCD_169 + +waveshare_esp32_s3_lcd_169.build.usb_mode=1 +waveshare_esp32_s3_lcd_169.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_169.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_169.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_169.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_169.build.flash_size=16MB +waveshare_esp32_s3_lcd_169.build.flash_freq=80m +waveshare_esp32_s3_lcd_169.build.flash_mode=dio +waveshare_esp32_s3_lcd_169.build.boot=qio +waveshare_esp32_s3_lcd_169.build.boot_freq=80m +waveshare_esp32_s3_lcd_169.build.partitions=default +waveshare_esp32_s3_lcd_169.build.defines= +waveshare_esp32_s3_lcd_169.build.loop_core= +waveshare_esp32_s3_lcd_169.build.event_core= +waveshare_esp32_s3_lcd_169.build.psram_type=qspi +waveshare_esp32_s3_lcd_169.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_lcd_169.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_lcd_169.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_169.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_lcd_169.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_169.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_lcd_169.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_169.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_lcd_169.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_169.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_lcd_169.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_lcd_169.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_lcd_169.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_lcd_169.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_lcd_169.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_169.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_lcd_169.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_lcd_169.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_169.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_lcd_169.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_lcd_169.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_lcd_169.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_lcd_169.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_lcd_169.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_lcd_169.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_lcd_169.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_lcd_169.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_lcd_169.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_lcd_169.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_lcd_169.menu.DebugLevel.none=None +waveshare_esp32_s3_lcd_169.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_lcd_169.menu.DebugLevel.error=Error +waveshare_esp32_s3_lcd_169.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_lcd_169.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_lcd_169.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_lcd_169.menu.DebugLevel.info=Info +waveshare_esp32_s3_lcd_169.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_lcd_169.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_lcd_169.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_lcd_169.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_lcd_169.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_lcd_169.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_lcd_169.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_lcd_169.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_lcd_169.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32s3_touch_lcd_128.name=Waveshare ESP32S3 Touch LCD 128 + +waveshare_esp32s3_touch_lcd_128.upload.tool=esptool_py +waveshare_esp32s3_touch_lcd_128.upload.tool.default=esptool_py +waveshare_esp32s3_touch_lcd_128.upload.tool.network=esp_ota +waveshare_esp32s3_touch_lcd_128.upload.maximum_size=16777216 +waveshare_esp32s3_touch_lcd_128.upload.maximum_data_size=327680 +waveshare_esp32s3_touch_lcd_128.upload.wait_for_upload_port=false +waveshare_esp32s3_touch_lcd_128.upload.speed=460800 +waveshare_esp32s3_touch_lcd_128.upload.flags= +waveshare_esp32s3_touch_lcd_128.upload.extra_flags= + +waveshare_esp32s3_touch_lcd_128.bootloader.tool=esptool_py +waveshare_esp32s3_touch_lcd_128.bootloader.tool.default=esptool_py + +waveshare_esp32s3_touch_lcd_128.serial.disableDTR=true +waveshare_esp32s3_touch_lcd_128.serial.disableRTS=true + +waveshare_esp32s3_touch_lcd_128.build.tarch=xtensa +waveshare_esp32s3_touch_lcd_128.build.bootloader_addr=0x0 +waveshare_esp32s3_touch_lcd_128.build.mcu=esp32s3 +waveshare_esp32s3_touch_lcd_128.build.core=esp32 +waveshare_esp32s3_touch_lcd_128.build.target=esp32s3 +waveshare_esp32s3_touch_lcd_128.build.variant=waveshare_esp32s3_touch_lcd_128 +waveshare_esp32s3_touch_lcd_128.build.board=WAVESHARE_ESP32S3_TOUCH_LCD_128 + +waveshare_esp32s3_touch_lcd_128.build.usb_mode=1 +waveshare_esp32s3_touch_lcd_128.build.cdc_on_boot=1 +waveshare_esp32s3_touch_lcd_128.build.msc_on_boot=0 +waveshare_esp32s3_touch_lcd_128.build.dfu_on_boot=0 + +waveshare_esp32s3_touch_lcd_128.build.f_cpu=240000000L +waveshare_esp32s3_touch_lcd_128.build.flash_size=16MB +waveshare_esp32s3_touch_lcd_128.build.flash_freq=80m +waveshare_esp32s3_touch_lcd_128.build.flash_mode=dio +waveshare_esp32s3_touch_lcd_128.build.boot=dio +waveshare_esp32s3_touch_lcd_128.build.partitions=default + +waveshare_esp32s3_touch_lcd_128.menu.PSRAM.disabled=Disabled +waveshare_esp32s3_touch_lcd_128.menu.PSRAM.disabled.build.defines= +waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled=Enabled +waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled.build.psram_type=qspi + +waveshare_esp32s3_touch_lcd_128.menu.LoopCore.1=Core 1 +waveshare_esp32s3_touch_lcd_128.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32s3_touch_lcd_128.menu.LoopCore.0=Core 0 +waveshare_esp32s3_touch_lcd_128.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32s3_touch_lcd_128.menu.EventsCore.1=Core 1 +waveshare_esp32s3_touch_lcd_128.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32s3_touch_lcd_128.menu.EventsCore.0=Core 0 +waveshare_esp32s3_touch_lcd_128.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 + +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.240=240MHz (WiFi/BT) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.160=160MHz (WiFi/BT) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.80=80MHz (WiFi/BT) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.40=40MHz (40MHz XTAL) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.26=26MHz (26MHz XTAL) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.26.build.f_cpu=26000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.20=20MHz (40MHz XTAL) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.13=13MHz (26MHz XTAL) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.13.build.f_cpu=13000000L +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.10=10MHz (40MHz XTAL) +waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio=QIO +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio.build.boot=qio +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio=DIO +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio.build.boot=dio + +waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.80=80MHz +waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.80.build.flash_freq=80m +waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.40=40MHz +waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.40.build.flash_freq=40m + +waveshare_esp32s3_touch_lcd_128.menu.FlashSize.16M=16MB (128Mb) +waveshare_esp32s3_touch_lcd_128.menu.FlashSize.16M.build.flash_size=16MB + +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.921600=921600 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.115200=115200 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400=230400 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.none=None +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.error=Error +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.warn=Warn +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.info=Info +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.debug=Debug +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.verbose=Verbose +waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.none=Disabled +waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.all=Enabled +waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_c3_zero.name=Waveshare ESP32-C3-Zero + +waveshare_esp32_c3_zero.bootloader.tool=esptool_py +waveshare_esp32_c3_zero.bootloader.tool.default=esptool_py + +waveshare_esp32_c3_zero.upload.tool=esptool_py +waveshare_esp32_c3_zero.upload.tool.default=esptool_py +waveshare_esp32_c3_zero.upload.tool.network=esp_ota + +waveshare_esp32_c3_zero.upload.maximum_size=1310720 +waveshare_esp32_c3_zero.upload.maximum_data_size=327680 +waveshare_esp32_c3_zero.upload.flags= +waveshare_esp32_c3_zero.upload.extra_flags= +waveshare_esp32_c3_zero.upload.use_1200bps_touch=false +waveshare_esp32_c3_zero.upload.wait_for_upload_port=false + +waveshare_esp32_c3_zero.serial.disableDTR=false +waveshare_esp32_c3_zero.serial.disableRTS=false + +waveshare_esp32_c3_zero.build.tarch=riscv32 +waveshare_esp32_c3_zero.build.target=esp +waveshare_esp32_c3_zero.build.mcu=esp32c3 +waveshare_esp32_c3_zero.build.core=esp32 +waveshare_esp32_c3_zero.build.variant=waveshare_esp32_c3_zero +waveshare_esp32_c3_zero.build.board=WAVESHARE_ESP32_C3_ZERO +waveshare_esp32_c3_zero.build.bootloader_addr=0x0 + +waveshare_esp32_c3_zero.build.cdc_on_boot=1 +waveshare_esp32_c3_zero.build.f_cpu=160000000L +waveshare_esp32_c3_zero.build.flash_size=4MB +waveshare_esp32_c3_zero.build.flash_freq=80m +waveshare_esp32_c3_zero.build.flash_mode=qio +waveshare_esp32_c3_zero.build.boot=qio +waveshare_esp32_c3_zero.build.partitions=default +waveshare_esp32_c3_zero.build.defines= + +## IDE 2.0 Seems to not update the value +waveshare_esp32_c3_zero.menu.JTAGAdapter.default=Disabled +waveshare_esp32_c3_zero.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_c3_zero.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_c3_zero.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +waveshare_esp32_c3_zero.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_c3_zero.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_c3_zero.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +waveshare_esp32_c3_zero.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_c3_zero.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_c3_zero.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +waveshare_esp32_c3_zero.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_c3_zero.menu.CDCOnBoot.default=Enabled +waveshare_esp32_c3_zero.menu.CDCOnBoot.default.build.cdc_on_boot=1 +waveshare_esp32_c3_zero.menu.CDCOnBoot.cdc=Disabled +waveshare_esp32_c3_zero.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +waveshare_esp32_c3_zero.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_c3_zero.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_c3_zero.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_c3_zero.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_c3_zero.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_c3_zero.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_c3_zero.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_c3_zero.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_c3_zero.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_c3_zero.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_c3_zero.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_c3_zero.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_c3_zero.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_c3_zero.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_c3_zero.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_c3_zero.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_c3_zero.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_c3_zero.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_c3_zero.menu.PartitionScheme.custom=Custom +waveshare_esp32_c3_zero.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_c3_zero.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +waveshare_esp32_c3_zero.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_c3_zero.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_c3_zero.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_c3_zero.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_c3_zero.menu.CPUFreq.40=40MHz +waveshare_esp32_c3_zero.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_c3_zero.menu.CPUFreq.20=20MHz +waveshare_esp32_c3_zero.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_c3_zero.menu.CPUFreq.10=10MHz +waveshare_esp32_c3_zero.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_c3_zero.menu.FlashMode.qio=QIO +waveshare_esp32_c3_zero.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_c3_zero.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_c3_zero.menu.FlashMode.dio=DIO +waveshare_esp32_c3_zero.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_c3_zero.menu.FlashMode.dio.build.boot=dio + +waveshare_esp32_c3_zero.menu.FlashFreq.80=80MHz +waveshare_esp32_c3_zero.menu.FlashFreq.80.build.flash_freq=80m +waveshare_esp32_c3_zero.menu.FlashFreq.40=40MHz +waveshare_esp32_c3_zero.menu.FlashFreq.40.build.flash_freq=40m + +waveshare_esp32_c3_zero.menu.FlashSize.4M=4MB (32Mb) +waveshare_esp32_c3_zero.menu.FlashSize.4M.build.flash_size=4MB + +waveshare_esp32_c3_zero.menu.UploadSpeed.921600=921600 +waveshare_esp32_c3_zero.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_c3_zero.menu.UploadSpeed.115200=115200 +waveshare_esp32_c3_zero.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_c3_zero.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_c3_zero.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_c3_zero.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_c3_zero.menu.UploadSpeed.230400=230400 +waveshare_esp32_c3_zero.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_c3_zero.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_c3_zero.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_c3_zero.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_c3_zero.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_c3_zero.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_c3_zero.menu.DebugLevel.none=None +waveshare_esp32_c3_zero.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_c3_zero.menu.DebugLevel.error=Error +waveshare_esp32_c3_zero.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_c3_zero.menu.DebugLevel.warn=Warn +waveshare_esp32_c3_zero.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_c3_zero.menu.DebugLevel.info=Info +waveshare_esp32_c3_zero.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_c3_zero.menu.DebugLevel.debug=Debug +waveshare_esp32_c3_zero.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_c3_zero.menu.DebugLevel.verbose=Verbose +waveshare_esp32_c3_zero.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_c3_zero.menu.EraseFlash.none=Disabled +waveshare_esp32_c3_zero.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_c3_zero.menu.EraseFlash.all=Enabled +waveshare_esp32_c3_zero.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_c3_zero.menu.ZigbeeMode.default=Disabled +waveshare_esp32_c3_zero.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_c3_zero.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_c3_zero.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_c3_zero.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_c3_zero.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_c6_zero.name=Waveshare ESP32-C6-Zero + +waveshare_esp32_c6_zero.bootloader.tool=esptool_py +waveshare_esp32_c6_zero.bootloader.tool.default=esptool_py + +waveshare_esp32_c6_zero.upload.tool=esptool_py +waveshare_esp32_c6_zero.upload.tool.default=esptool_py +waveshare_esp32_c6_zero.upload.tool.network=esp_ota + +waveshare_esp32_c6_zero.upload.maximum_size=1310720 +waveshare_esp32_c6_zero.upload.maximum_data_size=327680 +waveshare_esp32_c6_zero.upload.flags= +waveshare_esp32_c6_zero.upload.extra_flags= +waveshare_esp32_c6_zero.upload.use_1200bps_touch=false +waveshare_esp32_c6_zero.upload.wait_for_upload_port=false + +waveshare_esp32_c6_zero.serial.disableDTR=false +waveshare_esp32_c6_zero.serial.disableRTS=false + +waveshare_esp32_c6_zero.build.tarch=riscv32 +waveshare_esp32_c6_zero.build.target=esp +waveshare_esp32_c6_zero.build.mcu=esp32c6 +waveshare_esp32_c6_zero.build.core=esp32 +waveshare_esp32_c6_zero.build.variant=waveshare_esp32_c6_zero +waveshare_esp32_c6_zero.build.board=WAVESHARE_ESP32_C6_ZERO +waveshare_esp32_c6_zero.build.bootloader_addr=0x0 + +waveshare_esp32_c6_zero.build.cdc_on_boot=0 +waveshare_esp32_c6_zero.build.f_cpu=160000000L +waveshare_esp32_c6_zero.build.flash_size=4MB +waveshare_esp32_c6_zero.build.flash_freq=80m +waveshare_esp32_c6_zero.build.flash_mode=qio +waveshare_esp32_c6_zero.build.boot=qio +waveshare_esp32_c6_zero.build.partitions=default +waveshare_esp32_c6_zero.build.defines= + +## IDE 2.0 Seems to not update the value +waveshare_esp32_c6_zero.menu.JTAGAdapter.default=Disabled +waveshare_esp32_c6_zero.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_c6_zero.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_c6_zero.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +waveshare_esp32_c6_zero.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_c6_zero.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_c6_zero.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +waveshare_esp32_c6_zero.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_c6_zero.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_c6_zero.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +waveshare_esp32_c6_zero.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_c6_zero.menu.CDCOnBoot.default=Enabled +waveshare_esp32_c6_zero.menu.CDCOnBoot.default.build.cdc_on_boot=1 +waveshare_esp32_c6_zero.menu.CDCOnBoot.cdc=Disabled +waveshare_esp32_c6_zero.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +waveshare_esp32_c6_zero.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_c6_zero.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_c6_zero.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_c6_zero.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_c6_zero.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_c6_zero.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_c6_zero.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_c6_zero.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_c6_zero.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +waveshare_esp32_c6_zero.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_c6_zero.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_c6_zero.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee.build.partitions=zigbee +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_c6_zero.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_c6_zero.menu.PartitionScheme.custom=Custom +waveshare_esp32_c6_zero.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_c6_zero.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +waveshare_esp32_c6_zero.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_c6_zero.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_c6_zero.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_c6_zero.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_c6_zero.menu.CPUFreq.40=40MHz +waveshare_esp32_c6_zero.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_c6_zero.menu.CPUFreq.20=20MHz +waveshare_esp32_c6_zero.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_c6_zero.menu.CPUFreq.10=10MHz +waveshare_esp32_c6_zero.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_c6_zero.menu.FlashMode.qio=QIO +waveshare_esp32_c6_zero.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_c6_zero.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_c6_zero.menu.FlashMode.dio=DIO +waveshare_esp32_c6_zero.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_c6_zero.menu.FlashMode.dio.build.boot=dio + +waveshare_esp32_c6_zero.menu.FlashFreq.80=80MHz +waveshare_esp32_c6_zero.menu.FlashFreq.80.build.flash_freq=80m +waveshare_esp32_c6_zero.menu.FlashFreq.40=40MHz +waveshare_esp32_c6_zero.menu.FlashFreq.40.build.flash_freq=40m + +waveshare_esp32_c6_zero.menu.FlashSize.4M=4MB (32Mb) +waveshare_esp32_c6_zero.menu.FlashSize.4M.build.flash_size=4MB + +waveshare_esp32_c6_zero.menu.UploadSpeed.921600=921600 +waveshare_esp32_c6_zero.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_c6_zero.menu.UploadSpeed.115200=115200 +waveshare_esp32_c6_zero.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_c6_zero.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_c6_zero.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_c6_zero.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_c6_zero.menu.UploadSpeed.230400=230400 +waveshare_esp32_c6_zero.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_c6_zero.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_c6_zero.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_c6_zero.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_c6_zero.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_c6_zero.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_c6_zero.menu.DebugLevel.none=None +waveshare_esp32_c6_zero.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_c6_zero.menu.DebugLevel.error=Error +waveshare_esp32_c6_zero.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_c6_zero.menu.DebugLevel.warn=Warn +waveshare_esp32_c6_zero.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_c6_zero.menu.DebugLevel.info=Info +waveshare_esp32_c6_zero.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_c6_zero.menu.DebugLevel.debug=Debug +waveshare_esp32_c6_zero.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_c6_zero.menu.DebugLevel.verbose=Verbose +waveshare_esp32_c6_zero.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_c6_zero.menu.EraseFlash.none=Disabled +waveshare_esp32_c6_zero.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_c6_zero.menu.EraseFlash.all=Enabled +waveshare_esp32_c6_zero.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_c6_zero.menu.ZigbeeMode.default=Disabled +waveshare_esp32_c6_zero.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_c6_zero.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_c6_zero.menu.ZigbeeMode.ed=Zigbee ED (end device) +waveshare_esp32_c6_zero.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +waveshare_esp32_c6_zero.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +waveshare_esp32_c6_zero.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_c6_zero.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_c6_zero.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +weact_studio_esp32c3.name=WeAct Studio ESP32C3 + +weact_studio_esp32c3.upload.tool=esptool_py +weact_studio_esp32c3.upload.tool.default=esptool_py +weact_studio_esp32c3.upload.tool.network=esp_ota +weact_studio_esp32c3.upload.maximum_size=1310720 +weact_studio_esp32c3.upload.maximum_data_size=327680 +weact_studio_esp32c3.upload.flags= +weact_studio_esp32c3.upload.extra_flags= +weact_studio_esp32c3.upload.use_1200bps_touch=false +weact_studio_esp32c3.upload.wait_for_upload_port=false + +weact_studio_esp32c3.serial.disableDTR=false +weact_studio_esp32c3.serial.disableRTS=false + +weact_studio_esp32c3.build.tarch=riscv32 +weact_studio_esp32c3.build.target=esp +weact_studio_esp32c3.build.mcu=esp32c3 +weact_studio_esp32c3.build.core=esp32 +weact_studio_esp32c3.build.variant=weact_studio_esp32c3 +weact_studio_esp32c3.build.board=WEACT_STUDIO_ESP32C3 +weact_studio_esp32c3.build.bootloader_addr=0x0 + +weact_studio_esp32c3.build.usb_mode=1 +weact_studio_esp32c3.build.cdc_on_boot=1 +weact_studio_esp32c3.build.f_cpu=160000000L +weact_studio_esp32c3.build.flash_size=4MB +weact_studio_esp32c3.build.flash_freq=80m +weact_studio_esp32c3.build.flash_mode=qio +weact_studio_esp32c3.build.boot=qio +weact_studio_esp32c3.build.partitions=default +weact_studio_esp32c3.build.defines= + +weact_studio_esp32c3.menu.USBMode.hwcdc=Hardware CDC and JTAG +weact_studio_esp32c3.menu.USBMode.hwcdc.build.usb_mode=1 +weact_studio_esp32c3.menu.USBMode.default=USB-OTG +weact_studio_esp32c3.menu.USBMode.default.build.usb_mode=0 + +weact_studio_esp32c3.menu.JTAGAdapter.default=Disabled +weact_studio_esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +weact_studio_esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG +weact_studio_esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +weact_studio_esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +weact_studio_esp32c3.menu.JTAGAdapter.external=FTDI Adapter +weact_studio_esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +weact_studio_esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +weact_studio_esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge +weact_studio_esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +weact_studio_esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +weact_studio_esp32c3.menu.CDCOnBoot.default=Enabled +weact_studio_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +weact_studio_esp32c3.menu.CDCOnBoot.cdc=Enabled +weact_studio_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +weact_studio_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +weact_studio_esp32c3.menu.PartitionScheme.default.build.partitions=default +weact_studio_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +weact_studio_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +weact_studio_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +weact_studio_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal +weact_studio_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +weact_studio_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota +weact_studio_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +weact_studio_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +weact_studio_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +weact_studio_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +weact_studio_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +weact_studio_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +weact_studio_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +weact_studio_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +weact_studio_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app +weact_studio_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 + +weact_studio_esp32c3.menu.CPUFreq.160=160MHz (WiFi) +weact_studio_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L +weact_studio_esp32c3.menu.CPUFreq.80=80MHz (WiFi) +weact_studio_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L +weact_studio_esp32c3.menu.CPUFreq.40=40MHz +weact_studio_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L +weact_studio_esp32c3.menu.CPUFreq.20=20MHz +weact_studio_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L +weact_studio_esp32c3.menu.CPUFreq.10=10MHz +weact_studio_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L + +weact_studio_esp32c3.menu.FlashMode.qio=QIO +weact_studio_esp32c3.menu.FlashMode.qio.build.flash_mode=dio +weact_studio_esp32c3.menu.FlashMode.qio.build.boot=qio +weact_studio_esp32c3.menu.FlashMode.dio=DIO +weact_studio_esp32c3.menu.FlashMode.dio.build.flash_mode=dio +weact_studio_esp32c3.menu.FlashMode.dio.build.boot=dio + +weact_studio_esp32c3.menu.FlashFreq.80=80MHz +weact_studio_esp32c3.menu.FlashFreq.80.build.flash_freq=80m +weact_studio_esp32c3.menu.FlashFreq.40=40MHz +weact_studio_esp32c3.menu.FlashFreq.40.build.flash_freq=40m + +weact_studio_esp32c3.menu.UploadSpeed.921600=921600 +weact_studio_esp32c3.menu.UploadSpeed.921600.upload.speed=921600 +weact_studio_esp32c3.menu.UploadSpeed.115200=115200 +weact_studio_esp32c3.menu.UploadSpeed.115200.upload.speed=115200 +weact_studio_esp32c3.menu.UploadSpeed.256000.windows=256000 +weact_studio_esp32c3.menu.UploadSpeed.256000.upload.speed=256000 +weact_studio_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000 +weact_studio_esp32c3.menu.UploadSpeed.230400=230400 +weact_studio_esp32c3.menu.UploadSpeed.230400.upload.speed=230400 +weact_studio_esp32c3.menu.UploadSpeed.460800.linux=460800 +weact_studio_esp32c3.menu.UploadSpeed.460800.macosx=460800 +weact_studio_esp32c3.menu.UploadSpeed.460800.upload.speed=460800 +weact_studio_esp32c3.menu.UploadSpeed.512000.windows=512000 +weact_studio_esp32c3.menu.UploadSpeed.512000.upload.speed=512000 + +weact_studio_esp32c3.menu.DebugLevel.none=None +weact_studio_esp32c3.menu.DebugLevel.none.build.code_debug=0 +weact_studio_esp32c3.menu.DebugLevel.error=Error +weact_studio_esp32c3.menu.DebugLevel.error.build.code_debug=1 +weact_studio_esp32c3.menu.DebugLevel.warn=Warn +weact_studio_esp32c3.menu.DebugLevel.warn.build.code_debug=2 +weact_studio_esp32c3.menu.DebugLevel.info=Info +weact_studio_esp32c3.menu.DebugLevel.info.build.code_debug=3 +weact_studio_esp32c3.menu.DebugLevel.debug=Debug +weact_studio_esp32c3.menu.DebugLevel.debug.build.code_debug=4 +weact_studio_esp32c3.menu.DebugLevel.verbose=Verbose +weact_studio_esp32c3.menu.DebugLevel.verbose.build.code_debug=5 + +weact_studio_esp32c3.menu.EraseFlash.none=Disabled +weact_studio_esp32c3.menu.EraseFlash.none.upload.erase_cmd= +weact_studio_esp32c3.menu.EraseFlash.all=Enabled +weact_studio_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +aslcanx2.name=AutosportLabs ESP-CAN-X2 + +aslcanx2.bootloader.tool=esptool_py +aslcanx2.bootloader.tool.default=esptool_py + +aslcanx2.upload.tool=esptool_py +aslcanx2.upload.tool.default=esptool_py +aslcanx2.upload.tool.network=esp_ota + +aslcanx2.upload.maximum_size=1310720 +aslcanx2.upload.maximum_data_size=327680 +aslcanx2.upload.flags= +aslcanx2.upload.extra_flags= +aslcanx2.upload.use_1200bps_touch=false +aslcanx2.upload.wait_for_upload_port=false + +aslcanx2.serial.disableDTR=false +aslcanx2.serial.disableRTS=false + +aslcanx2.build.tarch=xtensa +aslcanx2.build.bootloader_addr=0x0 +aslcanx2.build.target=esp32s3 +aslcanx2.build.mcu=esp32s3 +aslcanx2.build.core=esp32 +aslcanx2.build.variant=aslcanx2 +aslcanx2.build.board=ASL_CAN_X2 + +aslcanx2.build.usb_mode=1 +aslcanx2.build.cdc_on_boot=0 +aslcanx2.build.msc_on_boot=0 +aslcanx2.build.dfu_on_boot=0 +aslcanx2.build.f_cpu=240000000L +aslcanx2.build.flash_size=8MB +aslcanx2.build.flash_freq=80m +aslcanx2.build.flash_mode=dio +aslcanx2.build.boot=qio +aslcanx2.build.boot_freq=80m +aslcanx2.build.partitions=default_8MB +aslcanx2.build.defines= +aslcanx2.build.loop_core= +aslcanx2.build.event_core= +aslcanx2.build.psram_type=qspi +aslcanx2.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +aslcanx2.menu.JTAGAdapter.default=Disabled +aslcanx2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +aslcanx2.menu.JTAGAdapter.builtin=Integrated USB JTAG +aslcanx2.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +aslcanx2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +aslcanx2.menu.JTAGAdapter.external=FTDI Adapter +aslcanx2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +aslcanx2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +aslcanx2.menu.JTAGAdapter.bridge=ESP USB Bridge +aslcanx2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +aslcanx2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +aslcanx2.menu.PSRAM.disabled=Disabled +aslcanx2.menu.PSRAM.disabled.build.defines= +aslcanx2.menu.PSRAM.disabled.build.psram_type=qspi +aslcanx2.menu.PSRAM.opi=OPI PSRAM +aslcanx2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +aslcanx2.menu.PSRAM.opi.build.psram_type=opi + +aslcanx2.menu.FlashMode.qio=QIO 80MHz +aslcanx2.menu.FlashMode.qio.build.flash_mode=dio +aslcanx2.menu.FlashMode.qio.build.boot=qio +aslcanx2.menu.FlashMode.qio.build.boot_freq=80m +aslcanx2.menu.FlashMode.qio.build.flash_freq=80m +aslcanx2.menu.FlashMode.qio120=QIO 120MHz +aslcanx2.menu.FlashMode.qio120.build.flash_mode=dio +aslcanx2.menu.FlashMode.qio120.build.boot=qio +aslcanx2.menu.FlashMode.qio120.build.boot_freq=120m +aslcanx2.menu.FlashMode.qio120.build.flash_freq=80m +aslcanx2.menu.FlashMode.dio=DIO 80MHz +aslcanx2.menu.FlashMode.dio.build.flash_mode=dio +aslcanx2.menu.FlashMode.dio.build.boot=dio +aslcanx2.menu.FlashMode.dio.build.boot_freq=80m +aslcanx2.menu.FlashMode.dio.build.flash_freq=80m +aslcanx2.menu.FlashMode.opi=OPI 80MHz +aslcanx2.menu.FlashMode.opi.build.flash_mode=dout +aslcanx2.menu.FlashMode.opi.build.boot=opi +aslcanx2.menu.FlashMode.opi.build.boot_freq=80m +aslcanx2.menu.FlashMode.opi.build.flash_freq=80m + +aslcanx2.menu.LoopCore.1=Core 1 +aslcanx2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +aslcanx2.menu.LoopCore.0=Core 0 +aslcanx2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +aslcanx2.menu.EventsCore.1=Core 1 +aslcanx2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +aslcanx2.menu.EventsCore.0=Core 0 +aslcanx2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +aslcanx2.menu.USBMode.hwcdc=Hardware CDC and JTAG +aslcanx2.menu.USBMode.hwcdc.build.usb_mode=1 +aslcanx2.menu.USBMode.default=USB-OTG (TinyUSB) +aslcanx2.menu.USBMode.default.build.usb_mode=0 + +aslcanx2.menu.CDCOnBoot.default=Enabled +aslcanx2.menu.CDCOnBoot.default.build.cdc_on_boot=1 +aslcanx2.menu.CDCOnBoot.cdc=Disabled +aslcanx2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +aslcanx2.menu.MSCOnBoot.default=Disabled +aslcanx2.menu.MSCOnBoot.default.build.msc_on_boot=0 +aslcanx2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +aslcanx2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +aslcanx2.menu.DFUOnBoot.default=Disabled +aslcanx2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +aslcanx2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +aslcanx2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +aslcanx2.menu.UploadMode.default=UART0 / Hardware CDC +aslcanx2.menu.UploadMode.default.upload.use_1200bps_touch=false +aslcanx2.menu.UploadMode.default.upload.wait_for_upload_port=false +aslcanx2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +aslcanx2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +aslcanx2.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +aslcanx2.menu.PartitionScheme.default=Default with spiffs (3MB APP/1.5MB SPIFFS) +aslcanx2.menu.PartitionScheme.default.build.partitions=default_8MB +aslcanx2.menu.PartitionScheme.default.upload.maximum_size=3342336 +aslcanx2.menu.PartitionScheme.defaultffat=Default with ffat (3MB APP/1.5MB FATFS) +aslcanx2.menu.PartitionScheme.defaultffat.build.partitions=default_8MB_ffat +aslcanx2.menu.PartitionScheme.defaultffat.upload.maximum_size=3342336 +aslcanx2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +aslcanx2.menu.PartitionScheme.minimal.build.partitions=minimal +aslcanx2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +aslcanx2.menu.PartitionScheme.no_ota.build.partitions=no_ota +aslcanx2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +aslcanx2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +aslcanx2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +aslcanx2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +aslcanx2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +aslcanx2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +aslcanx2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +aslcanx2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +aslcanx2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +aslcanx2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +aslcanx2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +aslcanx2.menu.PartitionScheme.huge_app.build.partitions=huge_app +aslcanx2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +aslcanx2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +aslcanx2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +aslcanx2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +aslcanx2.menu.PartitionScheme.rainmaker=RainMaker 4MB +aslcanx2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +aslcanx2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +aslcanx2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +aslcanx2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +aslcanx2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +aslcanx2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +aslcanx2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +aslcanx2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 + +aslcanx2.menu.CPUFreq.240=240MHz (WiFi) +aslcanx2.menu.CPUFreq.240.build.f_cpu=240000000L +aslcanx2.menu.CPUFreq.160=160MHz (WiFi) +aslcanx2.menu.CPUFreq.160.build.f_cpu=160000000L +aslcanx2.menu.CPUFreq.80=80MHz (WiFi) +aslcanx2.menu.CPUFreq.80.build.f_cpu=80000000L +aslcanx2.menu.CPUFreq.40=40MHz +aslcanx2.menu.CPUFreq.40.build.f_cpu=40000000L +aslcanx2.menu.CPUFreq.20=20MHz +aslcanx2.menu.CPUFreq.20.build.f_cpu=20000000L +aslcanx2.menu.CPUFreq.10=10MHz +aslcanx2.menu.CPUFreq.10.build.f_cpu=10000000L + +aslcanx2.menu.UploadSpeed.921600=921600 +aslcanx2.menu.UploadSpeed.921600.upload.speed=921600 +aslcanx2.menu.UploadSpeed.115200=115200 +aslcanx2.menu.UploadSpeed.115200.upload.speed=115200 +aslcanx2.menu.UploadSpeed.256000.windows=256000 +aslcanx2.menu.UploadSpeed.256000.upload.speed=256000 +aslcanx2.menu.UploadSpeed.230400.windows.upload.speed=256000 +aslcanx2.menu.UploadSpeed.230400=230400 +aslcanx2.menu.UploadSpeed.230400.upload.speed=230400 +aslcanx2.menu.UploadSpeed.460800.linux=460800 +aslcanx2.menu.UploadSpeed.460800.macosx=460800 +aslcanx2.menu.UploadSpeed.460800.upload.speed=460800 +aslcanx2.menu.UploadSpeed.512000.windows=512000 +aslcanx2.menu.UploadSpeed.512000.upload.speed=512000 + +aslcanx2.menu.DebugLevel.none=None +aslcanx2.menu.DebugLevel.none.build.code_debug=0 +aslcanx2.menu.DebugLevel.error=Error +aslcanx2.menu.DebugLevel.error.build.code_debug=1 +aslcanx2.menu.DebugLevel.warn=Warn +aslcanx2.menu.DebugLevel.warn.build.code_debug=2 +aslcanx2.menu.DebugLevel.info=Info +aslcanx2.menu.DebugLevel.info.build.code_debug=3 +aslcanx2.menu.DebugLevel.debug=Debug +aslcanx2.menu.DebugLevel.debug.build.code_debug=4 +aslcanx2.menu.DebugLevel.verbose=Verbose +aslcanx2.menu.DebugLevel.verbose.build.code_debug=5 + +aslcanx2.menu.EraseFlash.none=Disabled +aslcanx2.menu.EraseFlash.none.upload.erase_cmd= +aslcanx2.menu.EraseFlash.all=Enabled +aslcanx2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +walter.name=DPTechnics Walter + +walter.bootloader.tool=esptool_py +walter.bootloader.tool.default=esptool_py + +walter.upload.tool=esptool_py +walter.upload.tool.default=esptool_py +walter.upload.tool.network=esp_ota + +walter.upload.maximum_size=1310720 +walter.upload.maximum_data_size=327680 +walter.upload.flags= +walter.upload.extra_flags= +walter.upload.use_1200bps_touch=false +walter.upload.wait_for_upload_port=false + +walter.serial.disableDTR=false +walter.serial.disableRTS=false + +walter.build.tarch=xtensa +walter.build.bootloader_addr=0x0 +walter.build.target=esp32s3 +walter.build.mcu=esp32s3 +walter.build.core=esp32 +walter.build.variant=walter +walter.build.board=DPTECHNICS_WALTER + +walter.build.usb_mode=1 +walter.build.cdc_on_boot=1 +walter.build.msc_on_boot=0 +walter.build.dfu_on_boot=0 +walter.build.f_cpu=240000000L +walter.build.flash_size=16MB +walter.build.flash_freq=80m +walter.build.flash_mode=dio +walter.build.boot=qio +walter.build.boot_freq=80m +walter.build.partitions=default +walter.build.defines= +walter.build.loop_core= +walter.build.event_core= +walter.build.psram_type=qspi +walter.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +walter.menu.JTAGAdapter.default=Disabled +walter.menu.JTAGAdapter.default.build.copy_jtag_files=0 +walter.menu.JTAGAdapter.builtin=Integrated USB JTAG +walter.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +walter.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +walter.menu.JTAGAdapter.external=FTDI Adapter +walter.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +walter.menu.JTAGAdapter.external.build.copy_jtag_files=1 +walter.menu.JTAGAdapter.bridge=ESP USB Bridge +walter.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +walter.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +walter.menu.PSRAM.enabled=QSPI PSRAM +walter.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +walter.menu.PSRAM.enabled.build.psram_type=qspi +walter.menu.PSRAM.disabled=Disabled +walter.menu.PSRAM.disabled.build.defines= +walter.menu.PSRAM.disabled.build.psram_type=qspi + +walter.menu.FlashMode.qio=QIO 80MHz +walter.menu.FlashMode.qio.build.flash_mode=dio +walter.menu.FlashMode.qio.build.boot=qio +walter.menu.FlashMode.qio.build.boot_freq=80m +walter.menu.FlashMode.qio.build.flash_freq=80m +walter.menu.FlashMode.dio=DIO 80MHz +walter.menu.FlashMode.dio.build.flash_mode=dio +walter.menu.FlashMode.dio.build.boot=dio +walter.menu.FlashMode.dio.build.boot_freq=80m +walter.menu.FlashMode.dio.build.flash_freq=80m + +walter.menu.FlashSize.16M=16MB (128Mb) +walter.menu.FlashSize.16M.build.flash_size=16MB + +walter.menu.LoopCore.1=Core 1 +walter.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +walter.menu.LoopCore.0=Core 0 +walter.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +walter.menu.EventsCore.1=Core 1 +walter.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +walter.menu.EventsCore.0=Core 0 +walter.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +walter.menu.USBMode.hwcdc=Hardware CDC and JTAG +walter.menu.USBMode.hwcdc.build.usb_mode=1 +walter.menu.USBMode.default=USB-OTG (TinyUSB) +walter.menu.USBMode.default.build.usb_mode=0 + +walter.menu.CDCOnBoot.cdc=Enabled +walter.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +walter.menu.CDCOnBoot.default=Disabled +walter.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +walter.menu.MSCOnBoot.default=Disabled +walter.menu.MSCOnBoot.default.build.msc_on_boot=0 +walter.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +walter.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +walter.menu.DFUOnBoot.default=Disabled +walter.menu.DFUOnBoot.default.build.dfu_on_boot=0 +walter.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +walter.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +walter.menu.UploadMode.default=UART0 / Hardware CDC +walter.menu.UploadMode.default.upload.use_1200bps_touch=false +walter.menu.UploadMode.default.upload.wait_for_upload_port=false +walter.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +walter.menu.UploadMode.cdc.upload.use_1200bps_touch=true +walter.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +walter.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +walter.menu.PartitionScheme.fatflash.build.partitions=ffat +walter.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +walter.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +walter.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +walter.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +walter.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +walter.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +walter.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 + +walter.menu.CPUFreq.240=240MHz (WiFi) +walter.menu.CPUFreq.240.build.f_cpu=240000000L +walter.menu.CPUFreq.160=160MHz (WiFi) +walter.menu.CPUFreq.160.build.f_cpu=160000000L +walter.menu.CPUFreq.80=80MHz (WiFi) +walter.menu.CPUFreq.80.build.f_cpu=80000000L +walter.menu.CPUFreq.40=40MHz +walter.menu.CPUFreq.40.build.f_cpu=40000000L +walter.menu.CPUFreq.20=20MHz +walter.menu.CPUFreq.20.build.f_cpu=20000000L +walter.menu.CPUFreq.10=10MHz +walter.menu.CPUFreq.10.build.f_cpu=10000000L + +walter.menu.UploadSpeed.921600=921600 +walter.menu.UploadSpeed.921600.upload.speed=921600 +walter.menu.UploadSpeed.115200=115200 +walter.menu.UploadSpeed.115200.upload.speed=115200 +walter.menu.UploadSpeed.256000.windows=256000 +walter.menu.UploadSpeed.256000.upload.speed=256000 +walter.menu.UploadSpeed.230400.windows.upload.speed=256000 +walter.menu.UploadSpeed.230400=230400 +walter.menu.UploadSpeed.230400.upload.speed=230400 +walter.menu.UploadSpeed.460800.linux=460800 +walter.menu.UploadSpeed.460800.macosx=460800 +walter.menu.UploadSpeed.460800.upload.speed=460800 +walter.menu.UploadSpeed.512000.windows=512000 +walter.menu.UploadSpeed.512000.upload.speed=512000 + +walter.menu.DebugLevel.none=None +walter.menu.DebugLevel.none.build.code_debug=0 +walter.menu.DebugLevel.error=Error +walter.menu.DebugLevel.error.build.code_debug=1 +walter.menu.DebugLevel.warn=Warn +walter.menu.DebugLevel.warn.build.code_debug=2 +walter.menu.DebugLevel.info=Info +walter.menu.DebugLevel.info.build.code_debug=3 +walter.menu.DebugLevel.debug=Debug +walter.menu.DebugLevel.debug.build.code_debug=4 +walter.menu.DebugLevel.verbose=Verbose +walter.menu.DebugLevel.verbose.build.code_debug=5 + +walter.menu.EraseFlash.none=Disabled +walter.menu.EraseFlash.none.upload.erase_cmd= +walter.menu.EraseFlash.all=Enabled +walter.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +elecrow_crowpanel_7.name=Elecrow CrowPanel 7.0P + +elecrow_crowpanel_7.upload.tool=esptool_py +elecrow_crowpanel_7.upload.tool.default=esptool_py +elecrow_crowpanel_7.upload.tool.network=esp_ota +elecrow_crowpanel_7.upload.maximum_size=1310720 +elecrow_crowpanel_7.upload.maximum_data_size=327680 +elecrow_crowpanel_7.upload.wait_for_upload_port=false +elecrow_crowpanel_7.upload.speed=460800 +elecrow_crowpanel_7.upload.flags= +elecrow_crowpanel_7.upload.extra_flags= + +elecrow_crowpanel_7.bootloader.tool=esptool_py +elecrow_crowpanel_7.bootloader.tool.default=esptool_py + +elecrow_crowpanel_7.serial.disableDTR=true +elecrow_crowpanel_7.serial.disableRTS=true + +elecrow_crowpanel_7.build.tarch=xtensa +elecrow_crowpanel_7.build.bootloader_addr=0x0 +elecrow_crowpanel_7.build.mcu=esp32s3 +elecrow_crowpanel_7.build.core=esp32 +elecrow_crowpanel_7.build.target=esp32s3 +elecrow_crowpanel_7.build.variant=elecrow_crowpanel_7 +elecrow_crowpanel_7.build.board=ELECROW_CROWPANEL_7 + +elecrow_crowpanel_7.build.usb_mode=1 +elecrow_crowpanel_7.build.cdc_on_boot=1 +elecrow_crowpanel_7.build.msc_on_boot=0 +elecrow_crowpanel_7.build.dfu_on_boot=0 + +elecrow_crowpanel_7.build.f_cpu=240000000L +elecrow_crowpanel_7.build.flash_size=4MB +elecrow_crowpanel_7.build.flash_freq=80m +elecrow_crowpanel_7.build.flash_mode=dio +elecrow_crowpanel_7.build.boot=dio +elecrow_crowpanel_7.build.partitions=default + +elecrow_crowpanel_7.menu.PSRAM.disabled=Disabled +elecrow_crowpanel_7.menu.PSRAM.disabled.build.defines= +elecrow_crowpanel_7.menu.PSRAM.enabled=Enabled +elecrow_crowpanel_7.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +elecrow_crowpanel_7.menu.PSRAM.enabled.build.psram_type=opi + +elecrow_crowpanel_7.menu.LoopCore.1=Core 1 +elecrow_crowpanel_7.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +elecrow_crowpanel_7.menu.LoopCore.0=Core 0 +elecrow_crowpanel_7.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +elecrow_crowpanel_7.menu.EventsCore.1=Core 1 +elecrow_crowpanel_7.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +elecrow_crowpanel_7.menu.EventsCore.0=Core 0 +elecrow_crowpanel_7.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +elecrow_crowpanel_7.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.default.build.partitions=default +elecrow_crowpanel_7.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +elecrow_crowpanel_7.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +elecrow_crowpanel_7.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.minimal.build.partitions=minimal +elecrow_crowpanel_7.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.no_ota.build.partitions=no_ota +elecrow_crowpanel_7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +elecrow_crowpanel_7.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +elecrow_crowpanel_7.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +elecrow_crowpanel_7.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.huge_app.build.partitions=huge_app +elecrow_crowpanel_7.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +elecrow_crowpanel_7.menu.CPUFreq.240=240MHz (WiFi/BT) +elecrow_crowpanel_7.menu.CPUFreq.240.build.f_cpu=240000000L +elecrow_crowpanel_7.menu.CPUFreq.160=160MHz (WiFi/BT) +elecrow_crowpanel_7.menu.CPUFreq.160.build.f_cpu=160000000L +elecrow_crowpanel_7.menu.CPUFreq.80=80MHz (WiFi/BT) +elecrow_crowpanel_7.menu.CPUFreq.80.build.f_cpu=80000000L +elecrow_crowpanel_7.menu.CPUFreq.40=40MHz (40MHz XTAL) +elecrow_crowpanel_7.menu.CPUFreq.40.build.f_cpu=40000000L +elecrow_crowpanel_7.menu.CPUFreq.26=26MHz (26MHz XTAL) +elecrow_crowpanel_7.menu.CPUFreq.26.build.f_cpu=26000000L +elecrow_crowpanel_7.menu.CPUFreq.20=20MHz (40MHz XTAL) +elecrow_crowpanel_7.menu.CPUFreq.20.build.f_cpu=20000000L +elecrow_crowpanel_7.menu.CPUFreq.13=13MHz (26MHz XTAL) +elecrow_crowpanel_7.menu.CPUFreq.13.build.f_cpu=13000000L +elecrow_crowpanel_7.menu.CPUFreq.10=10MHz (40MHz XTAL) +elecrow_crowpanel_7.menu.CPUFreq.10.build.f_cpu=10000000L + +elecrow_crowpanel_7.menu.FlashMode.qio=QIO +elecrow_crowpanel_7.menu.FlashMode.qio.build.flash_mode=dio +elecrow_crowpanel_7.menu.FlashMode.qio.build.boot=qio +elecrow_crowpanel_7.menu.FlashMode.dio=DIO +elecrow_crowpanel_7.menu.FlashMode.dio.build.flash_mode=dio +elecrow_crowpanel_7.menu.FlashMode.dio.build.boot=dio + +elecrow_crowpanel_7.menu.FlashFreq.80=80MHz +elecrow_crowpanel_7.menu.FlashFreq.80.build.flash_freq=80m +elecrow_crowpanel_7.menu.FlashFreq.40=40MHz +elecrow_crowpanel_7.menu.FlashFreq.40.build.flash_freq=40m + +elecrow_crowpanel_7.menu.FlashSize.4MB=4MB (32Mb) +elecrow_crowpanel_7.menu.FlashSize.4MB.build.flash_size=4MB + +elecrow_crowpanel_7.menu.UploadSpeed.921600=921600 +elecrow_crowpanel_7.menu.UploadSpeed.921600.upload.speed=921600 +elecrow_crowpanel_7.menu.UploadSpeed.115200=115200 +elecrow_crowpanel_7.menu.UploadSpeed.115200.upload.speed=115200 +elecrow_crowpanel_7.menu.UploadSpeed.256000.windows=256000 +elecrow_crowpanel_7.menu.UploadSpeed.256000.upload.speed=256000 +elecrow_crowpanel_7.menu.UploadSpeed.230400.windows.upload.speed=256000 +elecrow_crowpanel_7.menu.UploadSpeed.230400=230400 +elecrow_crowpanel_7.menu.UploadSpeed.230400.upload.speed=230400 +elecrow_crowpanel_7.menu.UploadSpeed.460800.linux=460800 +elecrow_crowpanel_7.menu.UploadSpeed.460800.macosx=460800 +elecrow_crowpanel_7.menu.UploadSpeed.460800.upload.speed=460800 +elecrow_crowpanel_7.menu.UploadSpeed.512000.windows=512000 +elecrow_crowpanel_7.menu.UploadSpeed.512000.upload.speed=512000 + +elecrow_crowpanel_7.menu.DebugLevel.none=None +elecrow_crowpanel_7.menu.DebugLevel.none.build.code_debug=0 +elecrow_crowpanel_7.menu.DebugLevel.error=Error +elecrow_crowpanel_7.menu.DebugLevel.error.build.code_debug=1 +elecrow_crowpanel_7.menu.DebugLevel.warn=Warn +elecrow_crowpanel_7.menu.DebugLevel.warn.build.code_debug=2 +elecrow_crowpanel_7.menu.DebugLevel.info=Info +elecrow_crowpanel_7.menu.DebugLevel.info.build.code_debug=3 +elecrow_crowpanel_7.menu.DebugLevel.debug=Debug +elecrow_crowpanel_7.menu.DebugLevel.debug.build.code_debug=4 +elecrow_crowpanel_7.menu.DebugLevel.verbose=Verbose +elecrow_crowpanel_7.menu.DebugLevel.verbose.build.code_debug=5 + +elecrow_crowpanel_7.menu.EraseFlash.none=Disabled +elecrow_crowpanel_7.menu.EraseFlash.none.upload.erase_cmd= +elecrow_crowpanel_7.menu.EraseFlash.all=Enabled +elecrow_crowpanel_7.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +circuitart_zero_s3.name=CircuitART Zero S3 +circuitart_zero_s3.vid.0=0x303a +circuitart_zero_s3.pid.0=0x80DB + +circuitart_zero_s3.bootloader.tool=esptool_py +circuitart_zero_s3.bootloader.tool.default=esptool_py + +circuitart_zero_s3.upload.tool=esptool_py +circuitart_zero_s3.upload.tool.default=esptool_py +circuitart_zero_s3.upload.tool.network=esp_ota + +circuitart_zero_s3.upload.maximum_size=1310720 +circuitart_zero_s3.upload.maximum_data_size=327680 +circuitart_zero_s3.upload.flags= +circuitart_zero_s3.upload.extra_flags= +circuitart_zero_s3.upload.use_1200bps_touch=false +circuitart_zero_s3.upload.wait_for_upload_port=false + +circuitart_zero_s3.serial.disableDTR=false +circuitart_zero_s3.serial.disableRTS=false + +circuitart_zero_s3.build.tarch=xtensa +circuitart_zero_s3.build.bootloader_addr=0x0 +circuitart_zero_s3.build.target=esp32s3 +circuitart_zero_s3.build.mcu=esp32s3 +circuitart_zero_s3.build.core=esp32 +circuitart_zero_s3.build.variant=circuitart_zero_s3 +circuitart_zero_s3.build.board=CIRCUITART_ZERO_S3 + +circuitart_zero_s3.build.usb_mode=1 +circuitart_zero_s3.build.cdc_on_boot=0 +circuitart_zero_s3.build.msc_on_boot=0 +circuitart_zero_s3.build.dfu_on_boot=0 +circuitart_zero_s3.build.f_cpu=240000000L +circuitart_zero_s3.build.flash_size=16MB +circuitart_zero_s3.build.flash_freq=80m +circuitart_zero_s3.build.flash_mode=dio +circuitart_zero_s3.build.boot=qio +circuitart_zero_s3.build.partitions=default +circuitart_zero_s3.build.defines= +circuitart_zero_s3.build.loop_core= +circuitart_zero_s3.build.event_core= +circuitart_zero_s3.build.flash_type=qio +circuitart_zero_s3.build.psram_type=qspi +circuitart_zero_s3.build.memory_type=qio_qspi + +circuitart_zero_s3.menu.LoopCore.1=Core 1 +circuitart_zero_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +circuitart_zero_s3.menu.LoopCore.0=Core 0 +circuitart_zero_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +circuitart_zero_s3.menu.EventsCore.1=Core 1 +circuitart_zero_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +circuitart_zero_s3.menu.EventsCore.0=Core 0 +circuitart_zero_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +circuitart_zero_s3.menu.USBMode.default=USB-OTG (TinyUSB) +circuitart_zero_s3.menu.USBMode.default.build.usb_mode=0 +circuitart_zero_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +circuitart_zero_s3.menu.USBMode.hwcdc.build.usb_mode=1 + +circuitart_zero_s3.menu.CDCOnBoot.cdc=Enabled +circuitart_zero_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +circuitart_zero_s3.menu.CDCOnBoot.default=Disabled +circuitart_zero_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +circuitart_zero_s3.menu.MSCOnBoot.default=Disabled +circuitart_zero_s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +circuitart_zero_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +circuitart_zero_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +circuitart_zero_s3.menu.DFUOnBoot.default=Disabled +circuitart_zero_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +circuitart_zero_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +circuitart_zero_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +circuitart_zero_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +circuitart_zero_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +circuitart_zero_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +circuitart_zero_s3.menu.UploadMode.default=UART0 / Hardware CDC +circuitart_zero_s3.menu.UploadMode.default.upload.use_1200bps_touch=false +circuitart_zero_s3.menu.UploadMode.default.upload.wait_for_upload_port=false + +circuitart_zero_s3.menu.PSRAM.enabled=Enabled +circuitart_zero_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +circuitart_zero_s3.menu.PSRAM.disabled=Disabled +circuitart_zero_s3.menu.PSRAM.disabled.build.defines= + +circuitart_zero_s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +circuitart_zero_s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +circuitart_zero_s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +circuitart_zero_s3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT) +circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2 +circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2 +circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +circuitart_zero_s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +circuitart_zero_s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +circuitart_zero_s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +circuitart_zero_s3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +circuitart_zero_s3.menu.PartitionScheme.fatflash.build.partitions=ffat +circuitart_zero_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +circuitart_zero_s3.menu.CPUFreq.240=240MHz (WiFi) +circuitart_zero_s3.menu.CPUFreq.240.build.f_cpu=240000000L +circuitart_zero_s3.menu.CPUFreq.160=160MHz (WiFi) +circuitart_zero_s3.menu.CPUFreq.160.build.f_cpu=160000000L +circuitart_zero_s3.menu.CPUFreq.80=80MHz (WiFi) +circuitart_zero_s3.menu.CPUFreq.80.build.f_cpu=80000000L +circuitart_zero_s3.menu.CPUFreq.40=40MHz +circuitart_zero_s3.menu.CPUFreq.40.build.f_cpu=40000000L +circuitart_zero_s3.menu.CPUFreq.20=20MHz +circuitart_zero_s3.menu.CPUFreq.20.build.f_cpu=20000000L +circuitart_zero_s3.menu.CPUFreq.10=10MHz +circuitart_zero_s3.menu.CPUFreq.10.build.f_cpu=10000000L + +circuitart_zero_s3.menu.FlashMode.qio=QIO +circuitart_zero_s3.menu.FlashMode.qio.build.flash_mode=dio +circuitart_zero_s3.menu.FlashMode.qio.build.boot=qio +circuitart_zero_s3.menu.FlashMode.dio=DIO +circuitart_zero_s3.menu.FlashMode.dio.build.flash_mode=dio +circuitart_zero_s3.menu.FlashMode.dio.build.boot=dio + +circuitart_zero_s3.menu.UploadSpeed.921600=921600 +circuitart_zero_s3.menu.UploadSpeed.921600.upload.speed=921600 +circuitart_zero_s3.menu.UploadSpeed.115200=115200 +circuitart_zero_s3.menu.UploadSpeed.115200.upload.speed=115200 +circuitart_zero_s3.menu.UploadSpeed.256000.windows=256000 +circuitart_zero_s3.menu.UploadSpeed.256000.upload.speed=256000 +circuitart_zero_s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +circuitart_zero_s3.menu.UploadSpeed.230400=230400 +circuitart_zero_s3.menu.UploadSpeed.230400.upload.speed=230400 +circuitart_zero_s3.menu.UploadSpeed.460800.linux=460800 +circuitart_zero_s3.menu.UploadSpeed.460800.macosx=460800 +circuitart_zero_s3.menu.UploadSpeed.460800.upload.speed=460800 +circuitart_zero_s3.menu.UploadSpeed.512000.windows=512000 +circuitart_zero_s3.menu.UploadSpeed.512000.upload.speed=512000 + +circuitart_zero_s3.menu.DebugLevel.none=None +circuitart_zero_s3.menu.DebugLevel.none.build.code_debug=0 +circuitart_zero_s3.menu.DebugLevel.error=Error +circuitart_zero_s3.menu.DebugLevel.error.build.code_debug=1 +circuitart_zero_s3.menu.DebugLevel.warn=Warn +circuitart_zero_s3.menu.DebugLevel.warn.build.code_debug=2 +circuitart_zero_s3.menu.DebugLevel.info=Info +circuitart_zero_s3.menu.DebugLevel.info.build.code_debug=3 +circuitart_zero_s3.menu.DebugLevel.debug=Debug +circuitart_zero_s3.menu.DebugLevel.debug.build.code_debug=4 +circuitart_zero_s3.menu.DebugLevel.verbose=Verbose +circuitart_zero_s3.menu.DebugLevel.verbose.build.code_debug=5 + +circuitart_zero_s3.menu.EraseFlash.none=Disabled +circuitart_zero_s3.menu.EraseFlash.none.upload.erase_cmd= +circuitart_zero_s3.menu.EraseFlash.all=Enabled +circuitart_zero_s3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +# Alfredo NoU3 + +alfredo-nou3.name=Alfredo NoU3 +alfredo-nou3.vid.0=0xAFD0 +alfredo-nou3.pid.0=0x0003 +alfredo-nou3.upload_port.0.vid=0xAFD0 +alfredo-nou3.upload_port.0.pid=0x0003 + +alfredo-nou3.bootloader.tool=esptool_py +alfredo-nou3.bootloader.tool.default=esptool_py + +alfredo-nou3.upload.tool=esptool_py +alfredo-nou3.upload.tool.default=esptool_py +alfredo-nou3.upload.tool.network=esp_ota + +alfredo-nou3.upload.maximum_size=3342336 +alfredo-nou3.upload.maximum_data_size=327680 +alfredo-nou3.upload.flags= +alfredo-nou3.upload.extra_flags= +alfredo-nou3.upload.use_1200bps_touch=true +alfredo-nou3.upload.wait_for_upload_port=true + +alfredo-nou3.serial.disableDTR=false +alfredo-nou3.serial.disableRTS=false + +alfredo-nou3.build.tarch=xtensa +alfredo-nou3.build.bootloader_addr=0x0 +alfredo-nou3.build.target=esp32s3 +alfredo-nou3.build.mcu=esp32s3 +alfredo-nou3.build.core=esp32 +alfredo-nou3.build.variant=alfredo-nou3 +alfredo-nou3.build.board=ALFREDO_NOU3 + +alfredo-nou3.build.usb_mode=0 +alfredo-nou3.build.cdc_on_boot=1 +alfredo-nou3.build.msc_on_boot=0 +alfredo-nou3.build.dfu_on_boot=0 +alfredo-nou3.build.f_cpu=240000000L +alfredo-nou3.build.flash_size=8MB +alfredo-nou3.build.flash_freq=80m +alfredo-nou3.build.flash_mode=dio +alfredo-nou3.build.boot=qio +alfredo-nou3.build.partitions=default +alfredo-nou3.build.defines= +alfredo-nou3.build.loop_core= +alfredo-nou3.build.event_core= +alfredo-nou3.build.flash_type=qio +alfredo-nou3.build.psram_type=qspi +alfredo-nou3.build.memory_type={build.flash_type}_{build.psram_type} + +alfredo-nou3.menu.LoopCore.1=Core 1 +alfredo-nou3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +alfredo-nou3.menu.LoopCore.0=Core 0 +alfredo-nou3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +alfredo-nou3.menu.EventsCore.1=Core 1 +alfredo-nou3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +alfredo-nou3.menu.EventsCore.0=Core 0 +alfredo-nou3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +alfredo-nou3.menu.USBMode.default=USB-OTG (TinyUSB) +alfredo-nou3.menu.USBMode.default.build.usb_mode=0 +alfredo-nou3.menu.USBMode.hwcdc=Hardware CDC and JTAG +alfredo-nou3.menu.USBMode.hwcdc.build.usb_mode=1 + +alfredo-nou3.menu.CDCOnBoot.cdc=Enabled +alfredo-nou3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +alfredo-nou3.menu.CDCOnBoot.default=Disabled +alfredo-nou3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +alfredo-nou3.menu.MSCOnBoot.default=Disabled +alfredo-nou3.menu.MSCOnBoot.default.build.msc_on_boot=0 +alfredo-nou3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +alfredo-nou3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +alfredo-nou3.menu.DFUOnBoot.default=Disabled +alfredo-nou3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +alfredo-nou3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +alfredo-nou3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +alfredo-nou3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +alfredo-nou3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +alfredo-nou3.menu.UploadMode.cdc.upload.wait_for_upload_port=true +alfredo-nou3.menu.UploadMode.default=UART0 / Hardware CDC +alfredo-nou3.menu.UploadMode.default.upload.use_1200bps_touch=false +alfredo-nou3.menu.UploadMode.default.upload.wait_for_upload_port=false + +alfredo-nou3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS) +alfredo-nou3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +alfredo-nou3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +alfredo-nou3.menu.PartitionScheme.big_8MB=Max App (8MB APP) +alfredo-nou3.menu.PartitionScheme.big_8MB.build.partitions=max_app_8MB +alfredo-nou3.menu.PartitionScheme.big_8MB.upload.maximum_size=8257536 + +alfredo-nou3.menu.CPUFreq.240=240MHz (WiFi) +alfredo-nou3.menu.CPUFreq.240.build.f_cpu=240000000L +alfredo-nou3.menu.CPUFreq.160=160MHz (WiFi) +alfredo-nou3.menu.CPUFreq.160.build.f_cpu=160000000L +alfredo-nou3.menu.CPUFreq.80=80MHz (WiFi) +alfredo-nou3.menu.CPUFreq.80.build.f_cpu=80000000L +alfredo-nou3.menu.CPUFreq.40=40MHz +alfredo-nou3.menu.CPUFreq.40.build.f_cpu=40000000L +alfredo-nou3.menu.CPUFreq.20=20MHz +alfredo-nou3.menu.CPUFreq.20.build.f_cpu=20000000L +alfredo-nou3.menu.CPUFreq.10=10MHz +alfredo-nou3.menu.CPUFreq.10.build.f_cpu=10000000L + +alfredo-nou3.menu.FlashMode.qio=QIO 80MHz +alfredo-nou3.menu.FlashMode.qio.build.flash_mode=dio +alfredo-nou3.menu.FlashMode.qio.build.boot=qio +alfredo-nou3.menu.FlashMode.qio.build.boot_freq=80m +alfredo-nou3.menu.FlashMode.qio.build.flash_freq=80m +alfredo-nou3.menu.FlashMode.qio120=QIO 120MHz +alfredo-nou3.menu.FlashMode.qio120.build.flash_mode=dio +alfredo-nou3.menu.FlashMode.qio120.build.boot=qio +alfredo-nou3.menu.FlashMode.qio120.build.boot_freq=120m +alfredo-nou3.menu.FlashMode.qio120.build.flash_freq=80m +alfredo-nou3.menu.FlashMode.dio=DIO 80MHz +alfredo-nou3.menu.FlashMode.dio.build.flash_mode=dio +alfredo-nou3.menu.FlashMode.dio.build.boot=dio +alfredo-nou3.menu.FlashMode.dio.build.boot_freq=80m +alfredo-nou3.menu.FlashMode.dio.build.flash_freq=80m +alfredo-nou3.menu.FlashMode.opi=OPI 80MHz +alfredo-nou3.menu.FlashMode.opi.build.flash_mode=dout +alfredo-nou3.menu.FlashMode.opi.build.boot=opi +alfredo-nou3.menu.FlashMode.opi.build.boot_freq=80m +alfredo-nou3.menu.FlashMode.opi.build.flash_freq=80m + +alfredo-nou3.menu.FlashSize.8M=8MB (64Mb) +alfredo-nou3.menu.FlashSize.8M.build.flash_size=8MB + +alfredo-nou3.menu.UploadSpeed.921600=921600 +alfredo-nou3.menu.UploadSpeed.921600.upload.speed=921600 +alfredo-nou3.menu.UploadSpeed.512000.windows=512000 +alfredo-nou3.menu.UploadSpeed.512000.upload.speed=512000 +alfredo-nou3.menu.UploadSpeed.460800.linux=460800 +alfredo-nou3.menu.UploadSpeed.460800.macosx=460800 +alfredo-nou3.menu.UploadSpeed.460800.upload.speed=460800 +alfredo-nou3.menu.UploadSpeed.256000.windows=256000 +alfredo-nou3.menu.UploadSpeed.256000.upload.speed=256000 +alfredo-nou3.menu.UploadSpeed.230400.windows.upload.speed=256000 +alfredo-nou3.menu.UploadSpeed.230400=230400 +alfredo-nou3.menu.UploadSpeed.230400.upload.speed=230400 +alfredo-nou3.menu.UploadSpeed.115200=115200 +alfredo-nou3.menu.UploadSpeed.115200.upload.speed=115200 + +alfredo-nou3.menu.DebugLevel.none=None +alfredo-nou3.menu.DebugLevel.none.build.code_debug=0 +alfredo-nou3.menu.DebugLevel.error=Error +alfredo-nou3.menu.DebugLevel.error.build.code_debug=1 +alfredo-nou3.menu.DebugLevel.warn=Warn +alfredo-nou3.menu.DebugLevel.warn.build.code_debug=2 +alfredo-nou3.menu.DebugLevel.info=Info +alfredo-nou3.menu.DebugLevel.info.build.code_debug=3 +alfredo-nou3.menu.DebugLevel.debug=Debug +alfredo-nou3.menu.DebugLevel.debug.build.code_debug=4 +alfredo-nou3.menu.DebugLevel.verbose=Verbose +alfredo-nou3.menu.DebugLevel.verbose.build.code_debug=5 + +alfredo-nou3.menu.EraseFlash.none=Disabled +alfredo-nou3.menu.EraseFlash.none.upload.erase_cmd= +alfredo-nou3.menu.EraseFlash.all=Enabled +alfredo-nou3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +codecell.name=CodeCell C3 + +codecell.bootloader.tool=esptool_py +codecell.bootloader.tool.default=esptool_py + +codecell.upload.tool=esptool_py +codecell.upload.tool.default=esptool_py +codecell.upload.tool.network=esp_ota + +codecell.upload.maximum_size=1310720 +codecell.upload.maximum_data_size=327680 +codecell.upload.flags= +codecell.upload.extra_flags= +codecell.upload.use_1200bps_touch=false +codecell.upload.wait_for_upload_port=false + +codecell.serial.disableDTR=false +codecell.serial.disableRTS=false + +codecell.build.tarch=riscv32 +codecell.build.target=esp +codecell.build.mcu=esp32c3 +codecell.build.core=esp32 +codecell.build.variant=codecell +codecell.build.board=CODECELLC3 +codecell.build.bootloader_addr=0x0 + +codecell.build.cdc_on_boot=1 +codecell.build.f_cpu=160000000L +codecell.build.flash_size=4MB +codecell.build.flash_freq=80m +codecell.build.flash_mode=qio +codecell.build.boot=qio +codecell.build.partitions=default +codecell.build.defines= + + +codecell.menu.JTAGAdapter.default=Disabled +codecell.menu.JTAGAdapter.default.build.copy_jtag_files=0 +codecell.menu.JTAGAdapter.builtin=Integrated USB JTAG +codecell.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg +codecell.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +codecell.menu.JTAGAdapter.external=FTDI Adapter +codecell.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg +codecell.menu.JTAGAdapter.external.build.copy_jtag_files=1 +codecell.menu.JTAGAdapter.bridge=ESP USB Bridge +codecell.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg +codecell.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +codecell.menu.CDCOnBoot.default=Enabled +codecell.menu.CDCOnBoot.default.build.cdc_on_boot=0 +codecell.menu.CDCOnBoot.cdc=Enabled +codecell.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +codecell.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +codecell.menu.PartitionScheme.default.build.partitions=default +codecell.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +codecell.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +codecell.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +codecell.menu.PartitionScheme.minimal.build.partitions=minimal +codecell.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +codecell.menu.PartitionScheme.no_fs.build.partitions=no_fs +codecell.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +codecell.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +codecell.menu.PartitionScheme.no_ota.build.partitions=no_ota +codecell.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +codecell.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +codecell.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +codecell.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +codecell.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +codecell.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +codecell.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +codecell.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +codecell.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +codecell.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +codecell.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +codecell.menu.PartitionScheme.huge_app.build.partitions=huge_app +codecell.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +codecell.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +codecell.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +codecell.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +codecell.menu.PartitionScheme.rainmaker=RainMaker 4MB +codecell.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +codecell.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +codecell.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +codecell.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +codecell.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +codecell.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +codecell.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +codecell.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +codecell.menu.PartitionScheme.custom=Custom +codecell.menu.PartitionScheme.custom.build.partitions= +codecell.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +codecell.menu.CPUFreq.160=160MHz (WiFi) +codecell.menu.CPUFreq.160.build.f_cpu=160000000L +codecell.menu.CPUFreq.80=80MHz (WiFi) +codecell.menu.CPUFreq.80.build.f_cpu=80000000L +codecell.menu.CPUFreq.40=40MHz +codecell.menu.CPUFreq.40.build.f_cpu=40000000L +codecell.menu.CPUFreq.20=20MHz +codecell.menu.CPUFreq.20.build.f_cpu=20000000L +codecell.menu.CPUFreq.10=10MHz +codecell.menu.CPUFreq.10.build.f_cpu=10000000L + +codecell.menu.FlashMode.qio=QIO +codecell.menu.FlashMode.qio.build.flash_mode=dio +codecell.menu.FlashMode.qio.build.boot=qio +codecell.menu.FlashMode.dio=DIO +codecell.menu.FlashMode.dio.build.flash_mode=dio +codecell.menu.FlashMode.dio.build.boot=dio + +codecell.menu.FlashFreq.80=80MHz +codecell.menu.FlashFreq.80.build.flash_freq=80m +codecell.menu.FlashFreq.40=40MHz +codecell.menu.FlashFreq.40.build.flash_freq=40m + +codecell.menu.FlashSize.4M=4MB (32Mb) +codecell.menu.FlashSize.4M.build.flash_size=4MB + +codecell.menu.UploadSpeed.921600=921600 +codecell.menu.UploadSpeed.921600.upload.speed=921600 +codecell.menu.UploadSpeed.115200=115200 +codecell.menu.UploadSpeed.115200.upload.speed=115200 +codecell.menu.UploadSpeed.256000.windows=256000 +codecell.menu.UploadSpeed.256000.upload.speed=256000 +codecell.menu.UploadSpeed.230400.windows.upload.speed=256000 +codecell.menu.UploadSpeed.230400=230400 +codecell.menu.UploadSpeed.230400.upload.speed=230400 +codecell.menu.UploadSpeed.460800.linux=460800 +codecell.menu.UploadSpeed.460800.macosx=460800 +codecell.menu.UploadSpeed.460800.upload.speed=460800 +codecell.menu.UploadSpeed.512000.windows=512000 +codecell.menu.UploadSpeed.512000.upload.speed=512000 + +codecell.menu.DebugLevel.none=None +codecell.menu.DebugLevel.none.build.code_debug=0 +codecell.menu.DebugLevel.error=Error +codecell.menu.DebugLevel.error.build.code_debug=1 +codecell.menu.DebugLevel.warn=Warn +codecell.menu.DebugLevel.warn.build.code_debug=2 +codecell.menu.DebugLevel.info=Info +codecell.menu.DebugLevel.info.build.code_debug=3 +codecell.menu.DebugLevel.debug=Debug +codecell.menu.DebugLevel.debug.build.code_debug=4 +codecell.menu.DebugLevel.verbose=Verbose +codecell.menu.DebugLevel.verbose.build.code_debug=5 + +codecell.menu.EraseFlash.none=Disabled +codecell.menu.EraseFlash.none.upload.erase_cmd= +codecell.menu.EraseFlash.all=Enabled +codecell.menu.EraseFlash.all.upload.erase_cmd=-e + +codecell.menu.ZigbeeMode.default=Disabled +codecell.menu.ZigbeeMode.default.build.zigbee_mode= +codecell.menu.ZigbeeMode.default.build.zigbee_libs= +codecell.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +codecell.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +codecell.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote +############################################################## + +jczn_2432s028r.name=ESP32-2432S028R CYD + +jczn_2432s028r.bootloader.tool=esptool_py +jczn_2432s028r.bootloader.tool.default=esptool_py + +jczn_2432s028r.upload.tool=esptool_py +jczn_2432s028r.upload.tool.default=esptool_py +jczn_2432s028r.upload.tool.network=esp_ota + +jczn_2432s028r.upload.maximum_size=1310720 +jczn_2432s028r.upload.maximum_data_size=327680 +jczn_2432s028r.upload.flags= +jczn_2432s028r.upload.extra_flags= + +jczn_2432s028r.serial.disableDTR=true +jczn_2432s028r.serial.disableRTS=true + +jczn_2432s028r.build.tarch=xtensa +jczn_2432s028r.build.bootloader_addr=0x1000 +jczn_2432s028r.build.target=esp32 +jczn_2432s028r.build.mcu=esp32 +jczn_2432s028r.build.core=esp32 +jczn_2432s028r.build.variant=jczn_2432s028r +jczn_2432s028r.build.board=ESP32_2432S028R + +jczn_2432s028r.build.f_cpu=240000000L +jczn_2432s028r.build.flash_size=4MB +jczn_2432s028r.build.flash_freq=40m +jczn_2432s028r.build.flash_mode=dio +jczn_2432s028r.build.boot=dio +jczn_2432s028r.build.partitions=default +jczn_2432s028r.build.defines= +jczn_2432s028r.build.loop_core= +jczn_2432s028r.build.event_core= + +## IDE 2.0 Seems to not update the value +jczn_2432s028r.menu.JTAGAdapter.default=Disabled +jczn_2432s028r.menu.JTAGAdapter.default.build.copy_jtag_files=0 +jczn_2432s028r.menu.JTAGAdapter.external=FTDI Adapter +jczn_2432s028r.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg +jczn_2432s028r.menu.JTAGAdapter.external.build.copy_jtag_files=1 +jczn_2432s028r.menu.JTAGAdapter.bridge=ESP USB Bridge +jczn_2432s028r.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg +jczn_2432s028r.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +jczn_2432s028r.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +jczn_2432s028r.menu.PartitionScheme.default.build.partitions=default +jczn_2432s028r.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +jczn_2432s028r.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +jczn_2432s028r.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +jczn_2432s028r.menu.PartitionScheme.no_ota.build.partitions=no_ota +jczn_2432s028r.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +jczn_2432s028r.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +jczn_2432s028r.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +jczn_2432s028r.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +jczn_2432s028r.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +jczn_2432s028r.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +jczn_2432s028r.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +jczn_2432s028r.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +jczn_2432s028r.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +jczn_2432s028r.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +jczn_2432s028r.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +jczn_2432s028r.menu.PartitionScheme.huge_app.build.partitions=huge_app +jczn_2432s028r.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +jczn_2432s028r.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +jczn_2432s028r.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +jczn_2432s028r.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +jczn_2432s028r.menu.PartitionScheme.rainmaker=RainMaker 4MB +jczn_2432s028r.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +jczn_2432s028r.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +jczn_2432s028r.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +jczn_2432s028r.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +jczn_2432s028r.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +jczn_2432s028r.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +jczn_2432s028r.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +jczn_2432s028r.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +jczn_2432s028r.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +jczn_2432s028r.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +jczn_2432s028r.menu.PartitionScheme.all_app.upload.maximum_size=4128768 + +jczn_2432s028r.menu.PartitionScheme.custom=Custom +jczn_2432s028r.menu.PartitionScheme.custom.build.partitions= +jczn_2432s028r.menu.PartitionScheme.custom.upload.maximum_size=4128768 + +jczn_2432s028r.menu.CPUFreq.240=240MHz (WiFi/BT) +jczn_2432s028r.menu.CPUFreq.240.build.f_cpu=240000000L +jczn_2432s028r.menu.CPUFreq.160=160MHz (WiFi/BT) +jczn_2432s028r.menu.CPUFreq.160.build.f_cpu=160000000L +jczn_2432s028r.menu.CPUFreq.80=80MHz (WiFi/BT) +jczn_2432s028r.menu.CPUFreq.80.build.f_cpu=80000000L +jczn_2432s028r.menu.CPUFreq.40=40MHz +jczn_2432s028r.menu.CPUFreq.40.build.f_cpu=40000000L +jczn_2432s028r.menu.CPUFreq.20=20MHz +jczn_2432s028r.menu.CPUFreq.20.build.f_cpu=20000000L +jczn_2432s028r.menu.CPUFreq.10=10MHz +jczn_2432s028r.menu.CPUFreq.10.build.f_cpu=10000000L + +jczn_2432s028r.menu.FlashMode.qio=QIO +jczn_2432s028r.menu.FlashMode.qio.build.flash_mode=dio +jczn_2432s028r.menu.FlashMode.qio.build.boot=qio + +jczn_2432s028r.menu.FlashFreq.80=80MHz +jczn_2432s028r.menu.FlashFreq.80.build.flash_freq=80m +jczn_2432s028r.menu.FlashFreq.40=40MHz +jczn_2432s028r.menu.FlashFreq.40.build.flash_freq=40m + +jczn_2432s028r.menu.FlashSize.4M=4MB +jczn_2432s028r.menu.FlashSize.4M.build.flash_size=4MB + +jczn_2432s028r.menu.UploadSpeed.921600=921600 +jczn_2432s028r.menu.UploadSpeed.921600.upload.speed=921600 +jczn_2432s028r.menu.UploadSpeed.115200=115200 +jczn_2432s028r.menu.UploadSpeed.115200.upload.speed=115200 +jczn_2432s028r.menu.UploadSpeed.256000.windows=256000 +jczn_2432s028r.menu.UploadSpeed.256000.upload.speed=256000 +jczn_2432s028r.menu.UploadSpeed.230400.windows.upload.speed=256000 +jczn_2432s028r.menu.UploadSpeed.230400=230400 +jczn_2432s028r.menu.UploadSpeed.230400.upload.speed=230400 +jczn_2432s028r.menu.UploadSpeed.460800.linux=460800 +jczn_2432s028r.menu.UploadSpeed.460800.macosx=460800 +jczn_2432s028r.menu.UploadSpeed.460800.upload.speed=460800 +jczn_2432s028r.menu.UploadSpeed.512000.windows=512000 +jczn_2432s028r.menu.UploadSpeed.512000.upload.speed=512000 + +jczn_2432s028r.menu.LoopCore.1=Core 1 +jczn_2432s028r.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +jczn_2432s028r.menu.LoopCore.0=Core 0 +jczn_2432s028r.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +jczn_2432s028r.menu.EventsCore.1=Core 1 +jczn_2432s028r.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +jczn_2432s028r.menu.EventsCore.0=Core 0 +jczn_2432s028r.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +jczn_2432s028r.menu.DebugLevel.none=None +jczn_2432s028r.menu.DebugLevel.none.build.code_debug=0 +jczn_2432s028r.menu.DebugLevel.error=Error +jczn_2432s028r.menu.DebugLevel.error.build.code_debug=1 +jczn_2432s028r.menu.DebugLevel.warn=Warn +jczn_2432s028r.menu.DebugLevel.warn.build.code_debug=2 +jczn_2432s028r.menu.DebugLevel.info=Info +jczn_2432s028r.menu.DebugLevel.info.build.code_debug=3 +jczn_2432s028r.menu.DebugLevel.debug=Debug +jczn_2432s028r.menu.DebugLevel.debug.build.code_debug=4 +jczn_2432s028r.menu.DebugLevel.verbose=Verbose +jczn_2432s028r.menu.DebugLevel.verbose.build.code_debug=5 + +jczn_2432s028r.menu.EraseFlash.none=Disabled +jczn_2432s028r.menu.EraseFlash.none.upload.erase_cmd= +jczn_2432s028r.menu.EraseFlash.all=Enabled +jczn_2432s028r.menu.EraseFlash.all.upload.erase_cmd=-e + +jczn_2432s028r.menu.ZigbeeMode.default=Disabled +jczn_2432s028r.menu.ZigbeeMode.default.build.zigbee_mode= +jczn_2432s028r.menu.ZigbeeMode.default.build.zigbee_libs= +jczn_2432s028r.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +jczn_2432s028r.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +jczn_2432s028r.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_touch_amoled_241.name=Waveshare ESP32-S3-Touch-AMOLED-2.41 +waveshare_esp32_s3_touch_amoled_241.vid.0=0x303a +waveshare_esp32_s3_touch_amoled_241.pid.0=0x8242 +waveshare_esp32_s3_touch_amoled_241.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_amoled_241.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_touch_amoled_241.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_241.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_241.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_241.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_241.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_241.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_241.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_241.upload.flags= +waveshare_esp32_s3_touch_amoled_241.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_241.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_241.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_241.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_241.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_241.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_241.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_241.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_241.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_241.build.core=esp32 +waveshare_esp32_s3_touch_amoled_241.build.variant=waveshare_esp32_s3_touch_amoled_241 +waveshare_esp32_s3_touch_amoled_241.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_241 + +waveshare_esp32_s3_touch_amoled_241.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_241.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_241.build.flash_size=16MB + +waveshare_esp32_s3_touch_amoled_241.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_241.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_241.build.boot=qio +waveshare_esp32_s3_touch_amoled_241.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_241.build.partitions=default +waveshare_esp32_s3_touch_amoled_241.build.defines= +waveshare_esp32_s3_touch_amoled_241.build.loop_core= +waveshare_esp32_s3_touch_amoled_241.build.event_core= +waveshare_esp32_s3_touch_amoled_241.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_241.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_241.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_241.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_241.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_241.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_43.name=Waveshare ESP32-S3-Touch-LCD-4.3 +waveshare_esp32_s3_touch_lcd_43.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_43.pid.0=0x822E +waveshare_esp32_s3_touch_lcd_43.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_43.upload_port.0.pid=0x822E + +waveshare_esp32_s3_touch_lcd_43.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_43.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_43.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_43.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_43.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_43.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_43.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_43.upload.flags= +waveshare_esp32_s3_touch_lcd_43.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_43.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_43.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_43.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_43.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_43.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_43.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_43.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_43.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_43.build.core=esp32 +waveshare_esp32_s3_touch_lcd_43.build.variant=waveshare_esp32_s3_touch_lcd_43 +waveshare_esp32_s3_touch_lcd_43.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_43 + +waveshare_esp32_s3_touch_lcd_43.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_43.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_43.build.flash_size=8MB +waveshare_esp32_s3_touch_lcd_43.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_43.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43.build.boot=qio +waveshare_esp32_s3_touch_lcd_43.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_43.build.partitions=default +waveshare_esp32_s3_touch_lcd_43.build.defines= +waveshare_esp32_s3_touch_lcd_43.build.loop_core= +waveshare_esp32_s3_touch_lcd_43.build.event_core= +waveshare_esp32_s3_touch_lcd_43.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_43.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.8M=8MB (64Mb) +waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.8M.build.flash_size=8MB +waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.16M=16MB (128Mb) +waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.16M.build.flash_size=16MB + +waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_43.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_43.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_43.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_43.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_43B.name=Waveshare ESP32-S3-Touch-LCD-4.3B +waveshare_esp32_s3_touch_lcd_43B.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_43B.pid.0=0x8231 +waveshare_esp32_s3_touch_lcd_43B.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_43B.upload_port.0.pid=0x8231 + +waveshare_esp32_s3_touch_lcd_43B.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_43B.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_43B.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_43B.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_43B.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_43B.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_43B.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_43B.upload.flags= +waveshare_esp32_s3_touch_lcd_43B.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_43B.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_43B.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_43B.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_43B.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_43B.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_43B.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_43B.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_43B.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_43B.build.core=esp32 +waveshare_esp32_s3_touch_lcd_43B.build.variant=waveshare_esp32_s3_touch_lcd_43b +waveshare_esp32_s3_touch_lcd_43B.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_43B + +waveshare_esp32_s3_touch_lcd_43B.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_43B.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_43B.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_43B.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_43B.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43B.build.boot=qio +waveshare_esp32_s3_touch_lcd_43B.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_43B.build.partitions=default +waveshare_esp32_s3_touch_lcd_43B.build.defines= +waveshare_esp32_s3_touch_lcd_43B.build.loop_core= +waveshare_esp32_s3_touch_lcd_43B.build.event_core= +waveshare_esp32_s3_touch_lcd_43B.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_43B.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_7.name=Waveshare ESP32-S3-Touch-LCD-7 +waveshare_esp32_s3_touch_lcd_7.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_7.pid.0=0x8234 +waveshare_esp32_s3_touch_lcd_7.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_7.upload_port.0.pid=0x8234 + +waveshare_esp32_s3_touch_lcd_7.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_7.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_7.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_7.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_7.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_7.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_7.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_7.upload.flags= +waveshare_esp32_s3_touch_lcd_7.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_7.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_7.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_7.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_7.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_7.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_7.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_7.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_7.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_7.build.core=esp32 +waveshare_esp32_s3_touch_lcd_7.build.variant=waveshare_esp32_s3_touch_lcd_7 +waveshare_esp32_s3_touch_lcd_7.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_7 + +waveshare_esp32_s3_touch_lcd_7.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_7.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_7.build.flash_size=8MB +waveshare_esp32_s3_touch_lcd_7.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_7.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_7.build.boot=qio +waveshare_esp32_s3_touch_lcd_7.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_7.build.partitions=default +waveshare_esp32_s3_touch_lcd_7.build.defines= +waveshare_esp32_s3_touch_lcd_7.build.loop_core= +waveshare_esp32_s3_touch_lcd_7.build.event_core= +waveshare_esp32_s3_touch_lcd_7.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_7.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.8M=8MB (64Mb) +waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.8M.build.flash_size=8MB +waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.16M=16MB (128Mb) +waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.16M.build.flash_size=16MB + +waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_7.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_7.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_7.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_7.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_5.name=Waveshare ESP32-S3-Touch-LCD-5 +waveshare_esp32_s3_touch_lcd_5.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_5.pid.0=0x8237 +waveshare_esp32_s3_touch_lcd_5.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_5.upload_port.0.pid=0x8237 + +waveshare_esp32_s3_touch_lcd_5.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_5.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_5.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_5.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_5.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_5.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_5.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_5.upload.flags= +waveshare_esp32_s3_touch_lcd_5.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_5.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_5.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_5.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_5.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_5.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_5.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_5.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_5.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_5.build.core=esp32 +waveshare_esp32_s3_touch_lcd_5.build.variant=waveshare_esp32_s3_touch_lcd_5 +waveshare_esp32_s3_touch_lcd_5.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_5 + +waveshare_esp32_s3_touch_lcd_5.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_5.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_5.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_5.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_5.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5.build.boot=qio +waveshare_esp32_s3_touch_lcd_5.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_5.build.partitions=default +waveshare_esp32_s3_touch_lcd_5.build.defines= +waveshare_esp32_s3_touch_lcd_5.build.loop_core= +waveshare_esp32_s3_touch_lcd_5.build.event_core= +waveshare_esp32_s3_touch_lcd_5.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_5.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_5.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_5.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_5.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_5.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_5B.name=Waveshare ESP32-S3-Touch-LCD-5B +waveshare_esp32_s3_touch_lcd_5B.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_5B.pid.0=0x823A +waveshare_esp32_s3_touch_lcd_5B.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_5B.upload_port.0.pid=0x823A + +waveshare_esp32_s3_touch_lcd_5B.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_5B.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_5B.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_5B.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_5B.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_5B.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_5B.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_5B.upload.flags= +waveshare_esp32_s3_touch_lcd_5B.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_5B.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_5B.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_5B.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_5B.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_5B.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_5B.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_5B.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_5B.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_5B.build.core=esp32 +waveshare_esp32_s3_touch_lcd_5B.build.variant=waveshare_esp32_s3_touch_lcd_5b +waveshare_esp32_s3_touch_lcd_5B.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_5B + +waveshare_esp32_s3_touch_lcd_5B.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_5B.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_5B.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_5B.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_5B.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5B.build.boot=qio +waveshare_esp32_s3_touch_lcd_5B.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_5B.build.partitions=default +waveshare_esp32_s3_touch_lcd_5B.build.defines= +waveshare_esp32_s3_touch_lcd_5B.build.loop_core= +waveshare_esp32_s3_touch_lcd_5B.build.event_core= +waveshare_esp32_s3_touch_lcd_5B.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_5B.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_4.name=Waveshare ESP32-S3-Touch-LCD-4 +waveshare_esp32_s3_touch_lcd_4.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_4.pid.0=0x823D +waveshare_esp32_s3_touch_lcd_4.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_4.upload_port.0.pid=0x823D + +waveshare_esp32_s3_touch_lcd_4.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_4.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_4.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_4.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_4.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_4.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_lcd_4.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_4.upload.flags= +waveshare_esp32_s3_touch_lcd_4.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_4.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_4.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_4.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_4.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_4.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_4.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_4.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_4.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_4.build.core=esp32 +waveshare_esp32_s3_touch_lcd_4.build.variant=waveshare_esp32_s3_touch_lcd_4 +waveshare_esp32_s3_touch_lcd_4.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_4 + +waveshare_esp32_s3_touch_lcd_4.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_4.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_4.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_4.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_4.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_4.build.boot=qio +waveshare_esp32_s3_touch_lcd_4.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_4.build.partitions=default +waveshare_esp32_s3_touch_lcd_4.build.defines= +waveshare_esp32_s3_touch_lcd_4.build.loop_core= +waveshare_esp32_s3_touch_lcd_4.build.event_core= +waveshare_esp32_s3_touch_lcd_4.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_4.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_4.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_4.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_4.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_4.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_lcd_185.name=Waveshare ESP32-S3-Touch-LCD-1.85 +waveshare_esp32_s3_touch_lcd_185.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_185.pid.0=0x8290 +waveshare_esp32_s3_touch_lcd_185.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_185.upload_port.0.pid=0x8290 + +waveshare_esp32_s3_touch_lcd_185.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_185.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_185.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_185.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_185.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_185.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_185.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_185.upload.flags= +waveshare_esp32_s3_touch_lcd_185.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_185.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_185.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_185.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_185.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_185.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_185.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_185.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_185.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_185.build.core=esp32 +waveshare_esp32_s3_touch_lcd_185.build.variant=waveshare_esp32_s3_touch_lcd_185 +waveshare_esp32_s3_touch_lcd_185.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_185 + +waveshare_esp32_s3_touch_lcd_185.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_185.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_185.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_185.build.flash_freq=120m +waveshare_esp32_s3_touch_lcd_185.build.flash_mode=qio +waveshare_esp32_s3_touch_lcd_185.build.boot=qio +waveshare_esp32_s3_touch_lcd_185.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185.build.partitions=default +waveshare_esp32_s3_touch_lcd_185.build.defines= +waveshare_esp32_s3_touch_lcd_185.build.loop_core= +waveshare_esp32_s3_touch_lcd_185.build.event_core= +waveshare_esp32_s3_touch_lcd_185.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_185.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_touch_lcd_185.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_185.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_185.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_185.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +cezerio_dev_esp32c6.name=cezerio dev ESP32C6 + +cezerio_dev_esp32c6.bootloader.tool=esptool_py +cezerio_dev_esp32c6.bootloader.tool.default=esptool_py + +cezerio_dev_esp32c6.upload.tool=esptool_py +cezerio_dev_esp32c6.upload.tool.default=esptool_py +cezerio_dev_esp32c6.upload.tool.network=esp_ota + +cezerio_dev_esp32c6.upload.maximum_size=1310720 +cezerio_dev_esp32c6.upload.maximum_data_size=327680 +cezerio_dev_esp32c6.upload.flags= +cezerio_dev_esp32c6.upload.extra_flags= +cezerio_dev_esp32c6.upload.use_1200bps_touch=false +cezerio_dev_esp32c6.upload.wait_for_upload_port=false + +cezerio_dev_esp32c6.serial.disableDTR=false +cezerio_dev_esp32c6.serial.disableRTS=false + +cezerio_dev_esp32c6.build.tarch=riscv32 +cezerio_dev_esp32c6.build.target=esp +cezerio_dev_esp32c6.build.mcu=esp32c6 +cezerio_dev_esp32c6.build.core=esp32 +cezerio_dev_esp32c6.build.variant=cezerio_dev_esp32c6 +cezerio_dev_esp32c6.build.board=CEZERIO_DEV_ESP32C6 +cezerio_dev_esp32c6.build.bootloader_addr=0x0 + +cezerio_dev_esp32c6.build.cdc_on_boot=0 +cezerio_dev_esp32c6.build.f_cpu=160000000L +cezerio_dev_esp32c6.build.flash_size=4MB +cezerio_dev_esp32c6.build.flash_freq=80m +cezerio_dev_esp32c6.build.flash_mode=qio +cezerio_dev_esp32c6.build.boot=qio +cezerio_dev_esp32c6.build.partitions=default +cezerio_dev_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +cezerio_dev_esp32c6.menu.JTAGAdapter.default=Disabled +cezerio_dev_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +cezerio_dev_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +cezerio_dev_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +cezerio_dev_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +cezerio_dev_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +cezerio_dev_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +cezerio_dev_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +cezerio_dev_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +cezerio_dev_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +cezerio_dev_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +cezerio_dev_esp32c6.menu.CDCOnBoot.default=Enabled +cezerio_dev_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=1 +cezerio_dev_esp32c6.menu.CDCOnBoot.cdc=Disabled +cezerio_dev_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +cezerio_dev_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.default.build.partitions=default +cezerio_dev_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +cezerio_dev_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +cezerio_dev_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +cezerio_dev_esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +cezerio_dev_esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs +cezerio_dev_esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +cezerio_dev_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +cezerio_dev_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +cezerio_dev_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +cezerio_dev_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +cezerio_dev_esp32c6.menu.PartitionScheme.custom=Custom +cezerio_dev_esp32c6.menu.PartitionScheme.custom.build.partitions= +cezerio_dev_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +cezerio_dev_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +cezerio_dev_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +cezerio_dev_esp32c6.menu.CPUFreq.120=120MHz (WiFi) +cezerio_dev_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L +cezerio_dev_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +cezerio_dev_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +cezerio_dev_esp32c6.menu.CPUFreq.40=40MHz +cezerio_dev_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +cezerio_dev_esp32c6.menu.CPUFreq.20=20MHz +cezerio_dev_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +cezerio_dev_esp32c6.menu.CPUFreq.10=10MHz +cezerio_dev_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +cezerio_dev_esp32c6.menu.FlashMode.qio=QIO +cezerio_dev_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +cezerio_dev_esp32c6.menu.FlashMode.qio.build.boot=qio +cezerio_dev_esp32c6.menu.FlashMode.dio=DIO +cezerio_dev_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +cezerio_dev_esp32c6.menu.FlashMode.dio.build.boot=dio + +cezerio_dev_esp32c6.menu.FlashFreq.80=80MHz +cezerio_dev_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +cezerio_dev_esp32c6.menu.FlashFreq.40=40MHz +cezerio_dev_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +cezerio_dev_esp32c6.menu.FlashSize.4M=4MB (32Mb) +cezerio_dev_esp32c6.menu.FlashSize.4M.build.flash_size=4MB + +cezerio_dev_esp32c6.menu.UploadSpeed.921600=921600 +cezerio_dev_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +cezerio_dev_esp32c6.menu.UploadSpeed.115200=115200 +cezerio_dev_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +cezerio_dev_esp32c6.menu.UploadSpeed.256000.windows=256000 +cezerio_dev_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +cezerio_dev_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +cezerio_dev_esp32c6.menu.UploadSpeed.230400=230400 +cezerio_dev_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +cezerio_dev_esp32c6.menu.UploadSpeed.460800.linux=460800 +cezerio_dev_esp32c6.menu.UploadSpeed.460800.macosx=460800 +cezerio_dev_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +cezerio_dev_esp32c6.menu.UploadSpeed.512000.windows=512000 +cezerio_dev_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +cezerio_dev_esp32c6.menu.DebugLevel.none=None +cezerio_dev_esp32c6.menu.DebugLevel.none.build.code_debug=0 +cezerio_dev_esp32c6.menu.DebugLevel.error=Error +cezerio_dev_esp32c6.menu.DebugLevel.error.build.code_debug=1 +cezerio_dev_esp32c6.menu.DebugLevel.warn=Warn +cezerio_dev_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +cezerio_dev_esp32c6.menu.DebugLevel.info=Info +cezerio_dev_esp32c6.menu.DebugLevel.info.build.code_debug=3 +cezerio_dev_esp32c6.menu.DebugLevel.debug=Debug +cezerio_dev_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +cezerio_dev_esp32c6.menu.DebugLevel.verbose=Verbose +cezerio_dev_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +cezerio_dev_esp32c6.menu.EraseFlash.none=Disabled +cezerio_dev_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +cezerio_dev_esp32c6.menu.EraseFlash.all=Enabled +cezerio_dev_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +cezerio_dev_esp32c6.menu.ZigbeeMode.default=Disabled +cezerio_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +cezerio_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +cezerio_dev_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +cezerio_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +cezerio_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +cezerio_dev_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator) +cezerio_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +cezerio_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +cezerio_mini_dev_esp32c6.name=cezerio mini dev ESP32C6 + +cezerio_mini_dev_esp32c6.bootloader.tool=esptool_py +cezerio_mini_dev_esp32c6.bootloader.tool.default=esptool_py + +cezerio_mini_dev_esp32c6.upload.tool=esptool_py +cezerio_mini_dev_esp32c6.upload.tool.default=esptool_py +cezerio_mini_dev_esp32c6.upload.tool.network=esp_ota + +cezerio_mini_dev_esp32c6.upload.maximum_size=1310720 +cezerio_mini_dev_esp32c6.upload.maximum_data_size=327680 +cezerio_mini_dev_esp32c6.upload.flags= +cezerio_mini_dev_esp32c6.upload.extra_flags= +cezerio_mini_dev_esp32c6.upload.use_1200bps_touch=false +cezerio_mini_dev_esp32c6.upload.wait_for_upload_port=false + +cezerio_mini_dev_esp32c6.serial.disableDTR=false +cezerio_mini_dev_esp32c6.serial.disableRTS=false + +cezerio_mini_dev_esp32c6.build.tarch=riscv32 +cezerio_mini_dev_esp32c6.build.target=esp +cezerio_mini_dev_esp32c6.build.mcu=esp32c6 +cezerio_mini_dev_esp32c6.build.core=esp32 +cezerio_mini_dev_esp32c6.build.variant=cezerio_mini_dev_esp32c6 +cezerio_mini_dev_esp32c6.build.board=CEZERIO_MINI_DEV_ESP32C6 +cezerio_mini_dev_esp32c6.build.bootloader_addr=0x0 + +cezerio_mini_dev_esp32c6.build.cdc_on_boot=0 +cezerio_mini_dev_esp32c6.build.f_cpu=160000000L +cezerio_mini_dev_esp32c6.build.flash_size=4MB +cezerio_mini_dev_esp32c6.build.flash_freq=80m +cezerio_mini_dev_esp32c6.build.flash_mode=qio +cezerio_mini_dev_esp32c6.build.boot=qio +cezerio_mini_dev_esp32c6.build.partitions=default +cezerio_mini_dev_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.default=Disabled +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +cezerio_mini_dev_esp32c6.menu.CDCOnBoot.default=Enabled +cezerio_mini_dev_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=1 +cezerio_mini_dev_esp32c6.menu.CDCOnBoot.cdc=Disabled +cezerio_mini_dev_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +cezerio_mini_dev_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.default.build.partitions=default +cezerio_mini_dev_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +cezerio_mini_dev_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom=Custom +cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom.build.partitions= +cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +cezerio_mini_dev_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +cezerio_mini_dev_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +cezerio_mini_dev_esp32c6.menu.CPUFreq.120=120MHz (WiFi) +cezerio_mini_dev_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L +cezerio_mini_dev_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +cezerio_mini_dev_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +cezerio_mini_dev_esp32c6.menu.CPUFreq.40=40MHz +cezerio_mini_dev_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +cezerio_mini_dev_esp32c6.menu.CPUFreq.20=20MHz +cezerio_mini_dev_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +cezerio_mini_dev_esp32c6.menu.CPUFreq.10=10MHz +cezerio_mini_dev_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +cezerio_mini_dev_esp32c6.menu.FlashMode.qio=QIO +cezerio_mini_dev_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +cezerio_mini_dev_esp32c6.menu.FlashMode.qio.build.boot=qio +cezerio_mini_dev_esp32c6.menu.FlashMode.dio=DIO +cezerio_mini_dev_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +cezerio_mini_dev_esp32c6.menu.FlashMode.dio.build.boot=dio + +cezerio_mini_dev_esp32c6.menu.FlashFreq.80=80MHz +cezerio_mini_dev_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +cezerio_mini_dev_esp32c6.menu.FlashFreq.40=40MHz +cezerio_mini_dev_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +cezerio_mini_dev_esp32c6.menu.FlashSize.4M=4MB (32Mb) +cezerio_mini_dev_esp32c6.menu.FlashSize.4M.build.flash_size=4MB + +cezerio_mini_dev_esp32c6.menu.UploadSpeed.921600=921600 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.115200=115200 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.256000.windows=256000 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400=230400 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.linux=460800 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.macosx=460800 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.512000.windows=512000 +cezerio_mini_dev_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +cezerio_mini_dev_esp32c6.menu.DebugLevel.none=None +cezerio_mini_dev_esp32c6.menu.DebugLevel.none.build.code_debug=0 +cezerio_mini_dev_esp32c6.menu.DebugLevel.error=Error +cezerio_mini_dev_esp32c6.menu.DebugLevel.error.build.code_debug=1 +cezerio_mini_dev_esp32c6.menu.DebugLevel.warn=Warn +cezerio_mini_dev_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +cezerio_mini_dev_esp32c6.menu.DebugLevel.info=Info +cezerio_mini_dev_esp32c6.menu.DebugLevel.info.build.code_debug=3 +cezerio_mini_dev_esp32c6.menu.DebugLevel.debug=Debug +cezerio_mini_dev_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +cezerio_mini_dev_esp32c6.menu.DebugLevel.verbose=Verbose +cezerio_mini_dev_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +cezerio_mini_dev_esp32c6.menu.EraseFlash.none=Disabled +cezerio_mini_dev_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +cezerio_mini_dev_esp32c6.menu.EraseFlash.all=Enabled +cezerio_mini_dev_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default=Disabled +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator) +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +waveshare_esp32_s3_lcd_185.name=Waveshare ESP32-S3-LCD-1.85 +waveshare_esp32_s3_lcd_185.vid.0=0x303a +waveshare_esp32_s3_lcd_185.pid.0=0x8242 +waveshare_esp32_s3_lcd_185.upload_port.0.vid=0x303a +waveshare_esp32_s3_lcd_185.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_lcd_185.bootloader.tool=esptool_py +waveshare_esp32_s3_lcd_185.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_lcd_185.upload.tool=esptool_py +waveshare_esp32_s3_lcd_185.upload.tool.default=esptool_py +waveshare_esp32_s3_lcd_185.upload.tool.network=esp_ota + +waveshare_esp32_s3_lcd_185.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_185.upload.maximum_data_size=327680 +waveshare_esp32_s3_lcd_185.upload.flags= +waveshare_esp32_s3_lcd_185.upload.extra_flags= +waveshare_esp32_s3_lcd_185.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_185.upload.wait_for_upload_port=false + +waveshare_esp32_s3_lcd_185.serial.disableDTR=false +waveshare_esp32_s3_lcd_185.serial.disableRTS=false + +waveshare_esp32_s3_lcd_185.build.tarch=xtensa +waveshare_esp32_s3_lcd_185.build.bootloader_addr=0x0 +waveshare_esp32_s3_lcd_185.build.target=esp32s3 +waveshare_esp32_s3_lcd_185.build.mcu=esp32s3 +waveshare_esp32_s3_lcd_185.build.core=esp32 +waveshare_esp32_s3_lcd_185.build.variant=waveshare_esp32_s3_lcd_185 +waveshare_esp32_s3_lcd_185.build.board=WAVESHARE_ESP32_S3_LCD_185 + +waveshare_esp32_s3_lcd_185.build.usb_mode=1 +waveshare_esp32_s3_lcd_185.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_185.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_185.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_185.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_185.build.flash_size=16MB +waveshare_esp32_s3_lcd_185.build.flash_freq=120m +waveshare_esp32_s3_lcd_185.build.flash_mode=qio +waveshare_esp32_s3_lcd_185.build.boot=qio +waveshare_esp32_s3_lcd_185.build.boot_freq=80m +waveshare_esp32_s3_lcd_185.build.partitions=default +waveshare_esp32_s3_lcd_185.build.defines= +waveshare_esp32_s3_lcd_185.build.loop_core= +waveshare_esp32_s3_lcd_185.build.event_core= +waveshare_esp32_s3_lcd_185.build.psram_type=opi +waveshare_esp32_s3_lcd_185.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_lcd_185.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_lcd_185.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_185.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_lcd_185.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_185.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_lcd_185.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_lcd_185.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_lcd_185.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_lcd_185.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_lcd_185.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_lcd_185.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_lcd_185.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_lcd_185.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_lcd_185.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_185.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_lcd_185.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_lcd_185.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_185.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_lcd_185.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_lcd_185.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_lcd_185.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_lcd_185.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_lcd_185.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_lcd_185.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_lcd_185.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_lcd_185.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_lcd_185.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_lcd_185.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_lcd_185.menu.DebugLevel.none=None +waveshare_esp32_s3_lcd_185.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_lcd_185.menu.DebugLevel.error=Error +waveshare_esp32_s3_lcd_185.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_lcd_185.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_lcd_185.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_lcd_185.menu.DebugLevel.info=Info +waveshare_esp32_s3_lcd_185.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_lcd_185.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_lcd_185.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_lcd_185.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_lcd_185.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_lcd_185.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_lcd_185.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_lcd_185.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_lcd_185.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +waveshare_esp32_s3_touch_lcd_146.name=Waveshare ESP32-S3-Touch-LCD-1.46 +waveshare_esp32_s3_touch_lcd_146.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_146.pid.0=0x8242 +waveshare_esp32_s3_touch_lcd_146.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_146.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_touch_lcd_146.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_146.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_146.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_146.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_146.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_146.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_146.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_146.upload.flags= +waveshare_esp32_s3_touch_lcd_146.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_146.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_146.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_146.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_146.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_146.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_146.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_146.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_146.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_146.build.core=esp32 +waveshare_esp32_s3_touch_lcd_146.build.variant=waveshare_esp32_s3_touch_lcd_146 +waveshare_esp32_s3_touch_lcd_146.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_146 + +waveshare_esp32_s3_touch_lcd_146.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_146.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_146.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_146.build.flash_freq=120m +waveshare_esp32_s3_touch_lcd_146.build.flash_mode=qio +waveshare_esp32_s3_touch_lcd_146.build.boot=qio +waveshare_esp32_s3_touch_lcd_146.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_146.build.partitions=default +waveshare_esp32_s3_touch_lcd_146.build.defines= +waveshare_esp32_s3_touch_lcd_146.build.loop_core= +waveshare_esp32_s3_touch_lcd_146.build.event_core= +waveshare_esp32_s3_touch_lcd_146.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_146.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_touch_lcd_146.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_146.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_146.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_146.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_lcd_146.name=Waveshare ESP32-S3-LCD-1.46 +waveshare_esp32_s3_lcd_146.vid.0=0x303a +waveshare_esp32_s3_lcd_146.pid.0=0x8242 +waveshare_esp32_s3_lcd_146.upload_port.0.vid=0x303a +waveshare_esp32_s3_lcd_146.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_lcd_146.bootloader.tool=esptool_py +waveshare_esp32_s3_lcd_146.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_lcd_146.upload.tool=esptool_py +waveshare_esp32_s3_lcd_146.upload.tool.default=esptool_py +waveshare_esp32_s3_lcd_146.upload.tool.network=esp_ota + +waveshare_esp32_s3_lcd_146.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_146.upload.maximum_data_size=327680 +waveshare_esp32_s3_lcd_146.upload.flags= +waveshare_esp32_s3_lcd_146.upload.extra_flags= +waveshare_esp32_s3_lcd_146.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_146.upload.wait_for_upload_port=false + +waveshare_esp32_s3_lcd_146.serial.disableDTR=false +waveshare_esp32_s3_lcd_146.serial.disableRTS=false + +waveshare_esp32_s3_lcd_146.build.tarch=xtensa +waveshare_esp32_s3_lcd_146.build.bootloader_addr=0x0 +waveshare_esp32_s3_lcd_146.build.target=esp32s3 +waveshare_esp32_s3_lcd_146.build.mcu=esp32s3 +waveshare_esp32_s3_lcd_146.build.core=esp32 +waveshare_esp32_s3_lcd_146.build.variant=waveshare_esp32_s3_lcd_146 +waveshare_esp32_s3_lcd_146.build.board=WAVESHARE_ESP32_S3_LCD_146 + +waveshare_esp32_s3_lcd_146.build.usb_mode=1 +waveshare_esp32_s3_lcd_146.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_146.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_146.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_146.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_146.build.flash_size=16MB +waveshare_esp32_s3_lcd_146.build.flash_freq=120m +waveshare_esp32_s3_lcd_146.build.flash_mode=qio +waveshare_esp32_s3_lcd_146.build.boot=qio +waveshare_esp32_s3_lcd_146.build.boot_freq=80m +waveshare_esp32_s3_lcd_146.build.partitions=default +waveshare_esp32_s3_lcd_146.build.defines= +waveshare_esp32_s3_lcd_146.build.loop_core= +waveshare_esp32_s3_lcd_146.build.event_core= +waveshare_esp32_s3_lcd_146.build.psram_type=opi +waveshare_esp32_s3_lcd_146.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_lcd_146.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_lcd_146.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_146.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_lcd_146.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_146.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_lcd_146.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_lcd_146.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_lcd_146.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_lcd_146.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_lcd_146.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_lcd_146.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_lcd_146.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_lcd_146.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_lcd_146.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_146.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_lcd_146.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_lcd_146.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_146.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_lcd_146.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_lcd_146.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_lcd_146.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_lcd_146.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_lcd_146.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_lcd_146.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_lcd_146.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_lcd_146.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_lcd_146.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_lcd_146.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_lcd_146.menu.DebugLevel.none=None +waveshare_esp32_s3_lcd_146.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_lcd_146.menu.DebugLevel.error=Error +waveshare_esp32_s3_lcd_146.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_lcd_146.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_lcd_146.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_lcd_146.menu.DebugLevel.info=Info +waveshare_esp32_s3_lcd_146.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_lcd_146.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_lcd_146.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_lcd_146.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_lcd_146.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_lcd_146.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_lcd_146.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_lcd_146.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_lcd_146.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_touch_lcd_185_box.name=Waveshare ESP32-S3-Touch-LCD-1.85-BOX +waveshare_esp32_s3_touch_lcd_185_box.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_185_box.pid.0=0x8242 +waveshare_esp32_s3_touch_lcd_185_box.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_185_box.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_touch_lcd_185_box.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_185_box.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_185_box.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_185_box.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_185_box.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_185_box.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_185_box.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_185_box.upload.flags= +waveshare_esp32_s3_touch_lcd_185_box.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_185_box.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_185_box.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_185_box.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_185_box.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_185_box.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_185_box.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_185_box.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_185_box.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_185_box.build.core=esp32 +waveshare_esp32_s3_touch_lcd_185_box.build.variant=waveshare_esp32_s3_touch_lcd_185_box +waveshare_esp32_s3_touch_lcd_185_box.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_185_BOX + +waveshare_esp32_s3_touch_lcd_185_box.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_185_box.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_185_box.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_185_box.build.flash_freq=120m +waveshare_esp32_s3_touch_lcd_185_box.build.flash_mode=qio +waveshare_esp32_s3_touch_lcd_185_box.build.boot=qio +waveshare_esp32_s3_touch_lcd_185_box.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.build.partitions=default +waveshare_esp32_s3_touch_lcd_185_box.build.defines= +waveshare_esp32_s3_touch_lcd_185_box.build.loop_core= +waveshare_esp32_s3_touch_lcd_185_box.build.event_core= +waveshare_esp32_s3_touch_lcd_185_box.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_185_box.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_lcd_147.name=Waveshare ESP32-S3-LCD-1.47 +waveshare_esp32_s3_lcd_147.vid.0=0x303a +waveshare_esp32_s3_lcd_147.pid.0=0x8242 +waveshare_esp32_s3_lcd_147.upload_port.0.vid=0x303a +waveshare_esp32_s3_lcd_147.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_lcd_147.bootloader.tool=esptool_py +waveshare_esp32_s3_lcd_147.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_lcd_147.upload.tool=esptool_py +waveshare_esp32_s3_lcd_147.upload.tool.default=esptool_py +waveshare_esp32_s3_lcd_147.upload.tool.network=esp_ota + +waveshare_esp32_s3_lcd_147.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_147.upload.maximum_data_size=327680 +waveshare_esp32_s3_lcd_147.upload.flags= +waveshare_esp32_s3_lcd_147.upload.extra_flags= +waveshare_esp32_s3_lcd_147.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_147.upload.wait_for_upload_port=false + +waveshare_esp32_s3_lcd_147.serial.disableDTR=false +waveshare_esp32_s3_lcd_147.serial.disableRTS=false + +waveshare_esp32_s3_lcd_147.build.tarch=xtensa +waveshare_esp32_s3_lcd_147.build.bootloader_addr=0x0 +waveshare_esp32_s3_lcd_147.build.target=esp32s3 +waveshare_esp32_s3_lcd_147.build.mcu=esp32s3 +waveshare_esp32_s3_lcd_147.build.core=esp32 +waveshare_esp32_s3_lcd_147.build.variant=waveshare_esp32_s3_lcd_147 +waveshare_esp32_s3_lcd_147.build.board=WAVESHARE_ESP32_S3_LCD_147 + +waveshare_esp32_s3_lcd_147.build.usb_mode=1 +waveshare_esp32_s3_lcd_147.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_147.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_147.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_147.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_147.build.flash_size=16MB +waveshare_esp32_s3_lcd_147.build.flash_freq=80m +waveshare_esp32_s3_lcd_147.build.flash_mode=qio +waveshare_esp32_s3_lcd_147.build.boot=qio +waveshare_esp32_s3_lcd_147.build.boot_freq=80m +waveshare_esp32_s3_lcd_147.build.partitions=default +waveshare_esp32_s3_lcd_147.build.defines= +waveshare_esp32_s3_lcd_147.build.loop_core= +waveshare_esp32_s3_lcd_147.build.event_core= +waveshare_esp32_s3_lcd_147.build.psram_type=opi +waveshare_esp32_s3_lcd_147.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_lcd_147.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_lcd_147.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_147.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_lcd_147.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_147.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_lcd_147.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_lcd_147.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_lcd_147.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_lcd_147.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_lcd_147.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_lcd_147.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_lcd_147.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_lcd_147.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_lcd_147.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_lcd_147.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_lcd_147.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_lcd_147.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_lcd_147.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_lcd_147.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_lcd_147.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_lcd_147.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_lcd_147.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_lcd_147.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_lcd_147.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_lcd_147.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_lcd_147.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_lcd_147.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_lcd_147.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_lcd_147.menu.DebugLevel.none=None +waveshare_esp32_s3_lcd_147.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_lcd_147.menu.DebugLevel.error=Error +waveshare_esp32_s3_lcd_147.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_lcd_147.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_lcd_147.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_lcd_147.menu.DebugLevel.info=Info +waveshare_esp32_s3_lcd_147.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_lcd_147.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_lcd_147.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_lcd_147.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_lcd_147.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_lcd_147.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_lcd_147.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_lcd_147.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_lcd_147.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_touch_lcd_21.name=Waveshare ESP32-S3-Touch-LCD-2.1 +waveshare_esp32_s3_touch_lcd_21.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_21.pid.0=0x8242 +waveshare_esp32_s3_touch_lcd_21.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_21.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_touch_lcd_21.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_21.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_21.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_21.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_21.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_21.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_21.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_21.upload.flags= +waveshare_esp32_s3_touch_lcd_21.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_21.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_21.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_21.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_21.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_21.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_21.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_21.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_21.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_21.build.core=esp32 +waveshare_esp32_s3_touch_lcd_21.build.variant=waveshare_esp32_s3_touch_lcd_21 +waveshare_esp32_s3_touch_lcd_21.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_21 + +waveshare_esp32_s3_touch_lcd_21.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_21.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_21.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_21.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_21.build.flash_mode=qio +waveshare_esp32_s3_touch_lcd_21.build.boot=qio +waveshare_esp32_s3_touch_lcd_21.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_21.build.partitions=default +waveshare_esp32_s3_touch_lcd_21.build.defines= +waveshare_esp32_s3_touch_lcd_21.build.loop_core= +waveshare_esp32_s3_touch_lcd_21.build.event_core= +waveshare_esp32_s3_touch_lcd_21.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_21.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_21.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_21.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_21.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_21.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_touch_lcd_28.name=Waveshare ESP32-S3-Touch-LCD-2.8 +waveshare_esp32_s3_touch_lcd_28.vid.0=0x303a +waveshare_esp32_s3_touch_lcd_28.pid.0=0x8242 +waveshare_esp32_s3_touch_lcd_28.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_lcd_28.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_touch_lcd_28.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_lcd_28.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_lcd_28.upload.tool=esptool_py +waveshare_esp32_s3_touch_lcd_28.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_lcd_28.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_lcd_28.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_28.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_lcd_28.upload.flags= +waveshare_esp32_s3_touch_lcd_28.upload.extra_flags= +waveshare_esp32_s3_touch_lcd_28.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_28.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_lcd_28.serial.disableDTR=false +waveshare_esp32_s3_touch_lcd_28.serial.disableRTS=false + +waveshare_esp32_s3_touch_lcd_28.build.tarch=xtensa +waveshare_esp32_s3_touch_lcd_28.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_lcd_28.build.target=esp32s3 +waveshare_esp32_s3_touch_lcd_28.build.mcu=esp32s3 +waveshare_esp32_s3_touch_lcd_28.build.core=esp32 +waveshare_esp32_s3_touch_lcd_28.build.variant=waveshare_esp32_s3_touch_lcd_28 +waveshare_esp32_s3_touch_lcd_28.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_28 + +waveshare_esp32_s3_touch_lcd_28.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_28.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_28.build.flash_size=16MB +waveshare_esp32_s3_touch_lcd_28.build.flash_freq=120m +waveshare_esp32_s3_touch_lcd_28.build.flash_mode=qio +waveshare_esp32_s3_touch_lcd_28.build.boot=qio +waveshare_esp32_s3_touch_lcd_28.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_28.build.partitions=default +waveshare_esp32_s3_touch_lcd_28.build.defines= +waveshare_esp32_s3_touch_lcd_28.build.loop_core= +waveshare_esp32_s3_touch_lcd_28.build.event_core= +waveshare_esp32_s3_touch_lcd_28.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_28.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled.build.psram_type=opi +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 +waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +waveshare_esp32_s3_touch_lcd_28.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_lcd_28.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_lcd_28.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_lcd_28.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_relay_6ch.name=Waveshare ESP32-S3-Relay-6CH +waveshare_esp32_s3_relay_6ch.vid.0=0x303a +waveshare_esp32_s3_relay_6ch.pid.0=0x8242 +waveshare_esp32_s3_relay_6ch.upload_port.0.vid=0x303a +waveshare_esp32_s3_relay_6ch.upload_port.0.pid=0x8242 + +waveshare_esp32_s3_relay_6ch.bootloader.tool=esptool_py +waveshare_esp32_s3_relay_6ch.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_relay_6ch.upload.tool=esptool_py +waveshare_esp32_s3_relay_6ch.upload.tool.default=esptool_py +waveshare_esp32_s3_relay_6ch.upload.tool.network=esp_ota + +waveshare_esp32_s3_relay_6ch.upload.maximum_size=1310720 +waveshare_esp32_s3_relay_6ch.upload.maximum_data_size=327680 +waveshare_esp32_s3_relay_6ch.upload.flags= +waveshare_esp32_s3_relay_6ch.upload.extra_flags= +waveshare_esp32_s3_relay_6ch.upload.use_1200bps_touch=false +waveshare_esp32_s3_relay_6ch.upload.wait_for_upload_port=false + +waveshare_esp32_s3_relay_6ch.serial.disableDTR=false +waveshare_esp32_s3_relay_6ch.serial.disableRTS=false + +waveshare_esp32_s3_relay_6ch.build.tarch=xtensa +waveshare_esp32_s3_relay_6ch.build.bootloader_addr=0x0 +waveshare_esp32_s3_relay_6ch.build.target=esp32s3 +waveshare_esp32_s3_relay_6ch.build.mcu=esp32s3 +waveshare_esp32_s3_relay_6ch.build.core=esp32 +waveshare_esp32_s3_relay_6ch.build.variant=waveshare_esp32_s3_relay_6ch +waveshare_esp32_s3_relay_6ch.build.board=WAVESHARE_ESP32_S3_RELAY_6CH + +waveshare_esp32_s3_relay_6ch.build.usb_mode=1 +waveshare_esp32_s3_relay_6ch.build.cdc_on_boot=0 +waveshare_esp32_s3_relay_6ch.build.msc_on_boot=0 +waveshare_esp32_s3_relay_6ch.build.dfu_on_boot=0 +waveshare_esp32_s3_relay_6ch.build.f_cpu=240000000L +waveshare_esp32_s3_relay_6ch.build.flash_size=8MB +waveshare_esp32_s3_relay_6ch.build.flash_freq=80m +waveshare_esp32_s3_relay_6ch.build.flash_mode=qio +waveshare_esp32_s3_relay_6ch.build.boot=qio +waveshare_esp32_s3_relay_6ch.build.boot_freq=80m +waveshare_esp32_s3_relay_6ch.build.partitions=default +waveshare_esp32_s3_relay_6ch.build.defines= +waveshare_esp32_s3_relay_6ch.build.loop_core= +waveshare_esp32_s3_relay_6ch.build.event_core= +waveshare_esp32_s3_relay_6ch.build.psram_type= +waveshare_esp32_s3_relay_6ch.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.default=Disabled +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.default.build.copy_jtag_files=0 +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin=Integrated USB JTAG +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external=FTDI Adapter +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external.build.copy_jtag_files=1 +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge=ESP USB Bridge +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled.build.psram_type=qspi + +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.flash_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio=DIO 80MHz +waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.flash_mode=dio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.boot=dio +waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.boot_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.flash_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi=OPI 80MHz +waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.flash_mode=dout +waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.boot=opi +waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.boot_freq=80m +waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.flash_freq=80m + +waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M=8MB (64Mb) +waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M.build.flash_size=8MB +waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M.build.partitions=default_8MB +waveshare_esp32_s3_relay_6ch.menu.FlashSize.16M=16MB (128Mb) +waveshare_esp32_s3_relay_6ch.menu.FlashSize.16M.build.flash_size=16MB + +waveshare_esp32_s3_relay_6ch.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_relay_6ch.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_relay_6ch.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_relay_6ch.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_relay_6ch.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_relay_6ch.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_relay_6ch.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_relay_6ch.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_relay_6ch.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_relay_6ch.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_relay_6ch.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_relay_6ch.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_relay_6ch.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_relay_6ch.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_relay_6ch.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.minimal.build.partitions=minimal +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs.build.partitions=no_fs +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_relay_6ch.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.none=None +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.error=Error +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.info=Info +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_relay_6ch.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_relay_6ch.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_relay_6ch.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_relay_6ch.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_relay_6ch.menu.EraseFlash.all.upload.erase_cmd=-e + +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default=Disabled +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default.build.zigbee_mode= +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default.build.zigbee_libs= +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +waveshare_esp32_s3_touch_amoled_164.name=Waveshare ESP32-S3-Touch-AMOLED-1.64 +waveshare_esp32_s3_touch_amoled_164.vid.0=0x303a +waveshare_esp32_s3_touch_amoled_164.pid.0=0x8249 +waveshare_esp32_s3_touch_amoled_164.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_amoled_164.upload_port.0.pid=0x8249 + +waveshare_esp32_s3_touch_amoled_164.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_164.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_164.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_164.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_164.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_164.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_164.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_164.upload.flags= +waveshare_esp32_s3_touch_amoled_164.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_164.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_164.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_164.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_164.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_164.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_164.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_164.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_164.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_164.build.core=esp32 +waveshare_esp32_s3_touch_amoled_164.build.variant=waveshare_esp32_s3_touch_amoled_164 +waveshare_esp32_s3_touch_amoled_164.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_164 + +waveshare_esp32_s3_touch_amoled_164.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_164.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_164.build.flash_size=16MB + +waveshare_esp32_s3_touch_amoled_164.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_164.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_164.build.boot=qio +waveshare_esp32_s3_touch_amoled_164.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_164.build.partitions=default +waveshare_esp32_s3_touch_amoled_164.build.defines= +waveshare_esp32_s3_touch_amoled_164.build.loop_core= +waveshare_esp32_s3_touch_amoled_164.build.event_core= +waveshare_esp32_s3_touch_amoled_164.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_164.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_164.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_164.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_164.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_164.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_amoled_143.name=Waveshare ESP32-S3-Touch-AMOLED-1.43 +waveshare_esp32_s3_touch_amoled_143.vid.0=0x303a +waveshare_esp32_s3_touch_amoled_143.pid.0=0x824a +waveshare_esp32_s3_touch_amoled_143.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_amoled_143.upload_port.0.pid=0x824a + +waveshare_esp32_s3_touch_amoled_143.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_143.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_143.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_143.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_143.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_143.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_143.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_143.upload.flags= +waveshare_esp32_s3_touch_amoled_143.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_143.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_143.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_143.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_143.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_143.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_143.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_143.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_143.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_143.build.core=esp32 +waveshare_esp32_s3_touch_amoled_143.build.variant=waveshare_esp32_s3_touch_amoled_143 +waveshare_esp32_s3_touch_amoled_143.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_143 + +waveshare_esp32_s3_touch_amoled_143.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_143.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_143.build.flash_size=16MB + +waveshare_esp32_s3_touch_amoled_143.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_143.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_143.build.boot=qio +waveshare_esp32_s3_touch_amoled_143.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_143.build.partitions=default +waveshare_esp32_s3_touch_amoled_143.build.defines= +waveshare_esp32_s3_touch_amoled_143.build.loop_core= +waveshare_esp32_s3_touch_amoled_143.build.event_core= +waveshare_esp32_s3_touch_amoled_143.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_143.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_143.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_143.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_143.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_143.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +waveshare_esp32_s3_touch_amoled_191.name=Waveshare ESP32-S3-Touch-AMOLED-1.91 +waveshare_esp32_s3_touch_amoled_191.vid.0=0x303a +waveshare_esp32_s3_touch_amoled_191.pid.0=0x824b +waveshare_esp32_s3_touch_amoled_191.upload_port.0.vid=0x303a +waveshare_esp32_s3_touch_amoled_191.upload_port.0.pid=0x824b + +waveshare_esp32_s3_touch_amoled_191.bootloader.tool=esptool_py +waveshare_esp32_s3_touch_amoled_191.bootloader.tool.default=esptool_py + +waveshare_esp32_s3_touch_amoled_191.upload.tool=esptool_py +waveshare_esp32_s3_touch_amoled_191.upload.tool.default=esptool_py +waveshare_esp32_s3_touch_amoled_191.upload.tool.network=esp_ota + +waveshare_esp32_s3_touch_amoled_191.upload.maximum_size=1310720 + +waveshare_esp32_s3_touch_amoled_191.upload.maximum_data_size=327680 +waveshare_esp32_s3_touch_amoled_191.upload.flags= +waveshare_esp32_s3_touch_amoled_191.upload.extra_flags= +waveshare_esp32_s3_touch_amoled_191.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_191.upload.wait_for_upload_port=false + +waveshare_esp32_s3_touch_amoled_191.serial.disableDTR=false +waveshare_esp32_s3_touch_amoled_191.serial.disableRTS=false + +waveshare_esp32_s3_touch_amoled_191.build.tarch=xtensa +waveshare_esp32_s3_touch_amoled_191.build.bootloader_addr=0x0 +waveshare_esp32_s3_touch_amoled_191.build.target=esp32s3 +waveshare_esp32_s3_touch_amoled_191.build.mcu=esp32s3 +waveshare_esp32_s3_touch_amoled_191.build.core=esp32 +waveshare_esp32_s3_touch_amoled_191.build.variant=waveshare_esp32_s3_touch_amoled_191 +waveshare_esp32_s3_touch_amoled_191.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_191 + +waveshare_esp32_s3_touch_amoled_191.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_191.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_191.build.flash_size=16MB + +waveshare_esp32_s3_touch_amoled_191.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_191.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_191.build.boot=qio +waveshare_esp32_s3_touch_amoled_191.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_191.build.partitions=default +waveshare_esp32_s3_touch_amoled_191.build.defines= +waveshare_esp32_s3_touch_amoled_191.build.loop_core= +waveshare_esp32_s3_touch_amoled_191.build.event_core= +waveshare_esp32_s3_touch_amoled_191.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_191.build.memory_type={build.boot}_{build.psram_type} + +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled=Disabled +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled.build.defines= +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled.build.psram_type=qspi +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled=Enabled +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled.build.psram_type=opi + +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio=QIO 80MHz +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.boot=qio +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.boot_freq=80m +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.flash_freq=80m +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120=QIO 120MHz +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.flash_mode=dio +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.boot=qio +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.boot_freq=120m +waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.flash_freq=80m + +waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.1=Core 1 +waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.0=Core 0 +waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +waveshare_esp32_s3_touch_amoled_191.menu.USBMode.hwcdc=Hardware CDC and JTAG +waveshare_esp32_s3_touch_amoled_191.menu.USBMode.hwcdc.build.usb_mode=1 +waveshare_esp32_s3_touch_amoled_191.menu.USBMode.default=USB-OTG (TinyUSB) +waveshare_esp32_s3_touch_amoled_191.menu.USBMode.default.build.usb_mode=0 + +waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.default.build.cdc_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.cdc=Enabled +waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.default.build.msc_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.default=Disabled +waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.default.build.dfu_on_boot=0 +waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default=UART0 / Hardware CDC +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default.upload.use_1200bps_touch=false +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default.upload.wait_for_upload_port=false +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc.upload.use_1200bps_touch=true +waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.default.build.partitions=default +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota.build.partitions=no_ota +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app.build.partitions=huge_app +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker=RainMaker 4MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash.build.partitions=ffat +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs.upload.maximum_size=2031616 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA) +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app.upload.maximum_size=4128768 +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom=Custom +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom.build.partitions= +waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.240=240MHz (WiFi) +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.240.build.f_cpu=240000000L +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.160=160MHz (WiFi) +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.160.build.f_cpu=160000000L +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.80=80MHz (WiFi) +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.80.build.f_cpu=80000000L +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.40=40MHz +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.40.build.f_cpu=40000000L +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.20=20MHz +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.20.build.f_cpu=20000000L +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.10=10MHz +waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.10.build.f_cpu=10000000L + +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.921600=921600 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.921600.upload.speed=921600 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.115200=115200 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.115200.upload.speed=115200 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.256000.windows=256000 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.256000.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400.windows.upload.speed=256000 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400=230400 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400.upload.speed=230400 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.linux=460800 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.macosx=460800 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.upload.speed=460800 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.512000.windows=512000 +waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.512000.upload.speed=512000 + +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.none=None +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.none.build.code_debug=0 +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.error=Error +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.error.build.code_debug=1 +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.warn=Warn +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.warn.build.code_debug=2 +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.info=Info +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.info.build.code_debug=3 +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.debug=Debug +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.debug.build.code_debug=4 +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.verbose=Verbose +waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.verbose.build.code_debug=5 + +waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.none=Disabled +waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.none.upload.erase_cmd= +waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.all=Enabled +waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +Pcbcupid_GLYPH_C3.name=Pcbcupid GLYPH C3 +Pcbcupid_GLYPH_C3.vid.0=0x2886 +Pcbcupid_GLYPH_C3.pid.0=0x0046 + +Pcbcupid_GLYPH_C3.bootloader.tool=esptool_py +Pcbcupid_GLYPH_C3.bootloader.tool.default=esptool_py + +Pcbcupid_GLYPH_C3.upload.tool=esptool_py +Pcbcupid_GLYPH_C3.upload.tool.default=esptool_py +Pcbcupid_GLYPH_C3.upload.tool.network=esp_ota + +Pcbcupid_GLYPH_C3.upload.maximum_size=1310720 +Pcbcupid_GLYPH_C3.upload.maximum_data_size=327680 +Pcbcupid_GLYPH_C3.upload.flags= +Pcbcupid_GLYPH_C3.upload.extra_flags= +Pcbcupid_GLYPH_C3.upload.use_1200bps_touch=false +Pcbcupid_GLYPH_C3.upload.wait_for_upload_port=false + +Pcbcupid_GLYPH_C3.serial.disableDTR=false +Pcbcupid_GLYPH_C3.serial.disableRTS=false + +Pcbcupid_GLYPH_C3.build.tarch=riscv32 +Pcbcupid_GLYPH_C3.build.target=esp +Pcbcupid_GLYPH_C3.build.mcu=esp32c3 +Pcbcupid_GLYPH_C3.build.core=esp32 +Pcbcupid_GLYPH_C3.build.variant=Pcbcupid_GLYPH_C3 +Pcbcupid_GLYPH_C3.build.board=PCBCUPID_GLYPHC3 +Pcbcupid_GLYPH_C3.build.bootloader_addr=0x0 + +Pcbcupid_GLYPH_C3.build.cdc_on_boot=1 +Pcbcupid_GLYPH_C3.build.f_cpu=160000000L +Pcbcupid_GLYPH_C3.build.flash_size=4MB +Pcbcupid_GLYPH_C3.build.flash_freq=80m +Pcbcupid_GLYPH_C3.build.flash_mode=qio +Pcbcupid_GLYPH_C3.build.boot=qio +Pcbcupid_GLYPH_C3.build.partitions=default +Pcbcupid_GLYPH_C3.build.defines= + +Pcbcupid_GLYPH_C3.menu.CDCOnBoot.default=Enabled +Pcbcupid_GLYPH_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Pcbcupid_GLYPH_C3.menu.CDCOnBoot.cdc=Disabled +Pcbcupid_GLYPH_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +Pcbcupid_GLYPH_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.default.build.partitions=default +Pcbcupid_GLYPH_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Pcbcupid_GLYPH_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.minimal.build.partitions=minimal +Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota +Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app +Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 + +Pcbcupid_GLYPH_C3.menu.CPUFreq.160=160MHz (WiFi) +Pcbcupid_GLYPH_C3.menu.CPUFreq.160.build.f_cpu=160000000L +Pcbcupid_GLYPH_C3.menu.CPUFreq.80=80MHz (WiFi) +Pcbcupid_GLYPH_C3.menu.CPUFreq.80.build.f_cpu=80000000L +Pcbcupid_GLYPH_C3.menu.CPUFreq.40=40MHz +Pcbcupid_GLYPH_C3.menu.CPUFreq.40.build.f_cpu=40000000L +Pcbcupid_GLYPH_C3.menu.CPUFreq.20=20MHz +Pcbcupid_GLYPH_C3.menu.CPUFreq.20.build.f_cpu=20000000L +Pcbcupid_GLYPH_C3.menu.CPUFreq.10=10MHz +Pcbcupid_GLYPH_C3.menu.CPUFreq.10.build.f_cpu=10000000L + +Pcbcupid_GLYPH_C3.menu.FlashMode.qio=QIO +Pcbcupid_GLYPH_C3.menu.FlashMode.qio.build.flash_mode=dio +Pcbcupid_GLYPH_C3.menu.FlashMode.qio.build.boot=qio +Pcbcupid_GLYPH_C3.menu.FlashMode.dio=DIO +Pcbcupid_GLYPH_C3.menu.FlashMode.dio.build.flash_mode=dio +Pcbcupid_GLYPH_C3.menu.FlashMode.dio.build.boot=dio + +Pcbcupid_GLYPH_C3.menu.FlashFreq.80=80MHz +Pcbcupid_GLYPH_C3.menu.FlashFreq.80.build.flash_freq=80m +Pcbcupid_GLYPH_C3.menu.FlashFreq.40=40MHz +Pcbcupid_GLYPH_C3.menu.FlashFreq.40.build.flash_freq=40m + +Pcbcupid_GLYPH_C3.menu.FlashSize.4M=4MB (32Mb) +Pcbcupid_GLYPH_C3.menu.FlashSize.4M.build.flash_size=4MB + +Pcbcupid_GLYPH_C3.menu.UploadSpeed.921600=921600 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.921600.upload.speed=921600 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.115200=115200 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.115200.upload.speed=115200 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.256000.windows=256000 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.256000.upload.speed=256000 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400.windows.upload.speed=256000 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400=230400 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400.upload.speed=230400 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.linux=460800 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.macosx=460800 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.upload.speed=460800 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.512000.windows=512000 +Pcbcupid_GLYPH_C3.menu.UploadSpeed.512000.upload.speed=512000 + +Pcbcupid_GLYPH_C3.menu.DebugLevel.none=None +Pcbcupid_GLYPH_C3.menu.DebugLevel.none.build.code_debug=0 +Pcbcupid_GLYPH_C3.menu.DebugLevel.error=Error +Pcbcupid_GLYPH_C3.menu.DebugLevel.error.build.code_debug=1 +Pcbcupid_GLYPH_C3.menu.DebugLevel.warn=Warn +Pcbcupid_GLYPH_C3.menu.DebugLevel.warn.build.code_debug=2 +Pcbcupid_GLYPH_C3.menu.DebugLevel.info=Info +Pcbcupid_GLYPH_C3.menu.DebugLevel.info.build.code_debug=3 +Pcbcupid_GLYPH_C3.menu.DebugLevel.debug=Debug +Pcbcupid_GLYPH_C3.menu.DebugLevel.debug.build.code_debug=4 +Pcbcupid_GLYPH_C3.menu.DebugLevel.verbose=Verbose +Pcbcupid_GLYPH_C3.menu.DebugLevel.verbose.build.code_debug=5 + +Pcbcupid_GLYPH_C3.menu.EraseFlash.none=Disabled +Pcbcupid_GLYPH_C3.menu.EraseFlash.none.upload.erase_cmd= +Pcbcupid_GLYPH_C3.menu.EraseFlash.all=Enabled +Pcbcupid_GLYPH_C3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + + +Pcbcupid_GLYPH_H2.name=Pcbcupid GLYPH H2 + +Pcbcupid_GLYPH_H2.bootloader.tool=esptool_py +Pcbcupid_GLYPH_H2.bootloader.tool.default=esptool_py + +Pcbcupid_GLYPH_H2.upload.tool=esptool_py +Pcbcupid_GLYPH_H2.upload.tool.default=esptool_py +Pcbcupid_GLYPH_H2.upload.tool.network=esp_ota + +Pcbcupid_GLYPH_H2.upload.maximum_size=1310720 +Pcbcupid_GLYPH_H2.upload.maximum_data_size=327680 +Pcbcupid_GLYPH_H2.upload.flags= +Pcbcupid_GLYPH_H2.upload.extra_flags= +Pcbcupid_GLYPH_H2.upload.use_1200bps_touch=false +Pcbcupid_GLYPH_H2.upload.wait_for_upload_port=false + +Pcbcupid_GLYPH_H2.serial.disableDTR=false +Pcbcupid_GLYPH_H2.serial.disableRTS=false + +Pcbcupid_GLYPH_H2.build.tarch=riscv32 +Pcbcupid_GLYPH_H2.build.target=esp +Pcbcupid_GLYPH_H2.build.mcu=esp32h2 +Pcbcupid_GLYPH_H2.build.core=esp32 +Pcbcupid_GLYPH_H2.build.variant=Pcbcupid_GLYPH_H2 +Pcbcupid_GLYPH_H2.build.board=PCBCUPID_GLYPHH2 +Pcbcupid_GLYPH_H2.build.bootloader_addr=0x0 + +Pcbcupid_GLYPH_H2.build.cdc_on_boot=1 +Pcbcupid_GLYPH_H2.build.f_cpu=96000000L +Pcbcupid_GLYPH_H2.build.flash_size=4MB +Pcbcupid_GLYPH_H2.build.flash_freq=64m +Pcbcupid_GLYPH_H2.build.img_freq=48m +Pcbcupid_GLYPH_H2.build.flash_mode=qio +Pcbcupid_GLYPH_H2.build.boot=qio +Pcbcupid_GLYPH_H2.build.partitions=default +Pcbcupid_GLYPH_H2.build.defines= + +## IDE 2.0 Seems to not update the value +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.default=Disabled +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin=Integrated USB JTAG +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external=FTDI Adapter +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge=ESP USB Bridge +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg +Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +Pcbcupid_GLYPH_H2.menu.CDCOnBoot.default=Enabled +Pcbcupid_GLYPH_H2.menu.CDCOnBoot.default.build.cdc_on_boot=1 +Pcbcupid_GLYPH_H2.menu.CDCOnBoot.cdc=Disabled +Pcbcupid_GLYPH_H2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +Pcbcupid_GLYPH_H2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.default.build.partitions=default +Pcbcupid_GLYPH_H2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Pcbcupid_GLYPH_H2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.minimal.build.partitions=minimal +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs.build.partitions=no_fs +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota.build.partitions=no_ota +Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app.build.partitions=huge_app +Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee.build.partitions=zigbee +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom=Custom +Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom.build.partitions= +Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +Pcbcupid_GLYPH_H2.menu.FlashMode.qio=QIO +Pcbcupid_GLYPH_H2.menu.FlashMode.qio.build.flash_mode=dio +Pcbcupid_GLYPH_H2.menu.FlashMode.qio.build.boot=qio +Pcbcupid_GLYPH_H2.menu.FlashMode.dio=DIO +Pcbcupid_GLYPH_H2.menu.FlashMode.dio.build.flash_mode=dio +Pcbcupid_GLYPH_H2.menu.FlashMode.dio.build.boot=dio + +Pcbcupid_GLYPH_H2.menu.FlashFreq.64=64MHz +Pcbcupid_GLYPH_H2.menu.FlashFreq.64.build.flash_freq=64m +Pcbcupid_GLYPH_H2.menu.FlashFreq.64.build.img_freq=48m +#Pcbcupid_GLYPH_H2.menu.FlashFreq.32=32MHz +#Pcbcupid_GLYPH_H2.menu.FlashFreq.32.build.flash_freq=32m +#Pcbcupid_GLYPH_H2.menu.FlashFreq.32.build.img_freq=24m +Pcbcupid_GLYPH_H2.menu.FlashFreq.16=16MHz +Pcbcupid_GLYPH_H2.menu.FlashFreq.16.build.flash_freq=16m +Pcbcupid_GLYPH_H2.menu.FlashFreq.16.build.img_freq=12m + +Pcbcupid_GLYPH_H2.menu.FlashSize.2M=2MB (16Mb) +Pcbcupid_GLYPH_H2.menu.FlashSize.2M.build.flash_size=2MB +Pcbcupid_GLYPH_H2.menu.FlashSize.4M=4MB (32Mb) +Pcbcupid_GLYPH_H2.menu.FlashSize.4M.build.flash_size=4MB + +Pcbcupid_GLYPH_H2.menu.UploadSpeed.921600=921600 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.921600.upload.speed=921600 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.115200=115200 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.115200.upload.speed=115200 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.256000.windows=256000 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.256000.upload.speed=256000 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400.windows.upload.speed=256000 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400=230400 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400.upload.speed=230400 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.linux=460800 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.macosx=460800 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.upload.speed=460800 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.512000.windows=512000 +Pcbcupid_GLYPH_H2.menu.UploadSpeed.512000.upload.speed=512000 + +Pcbcupid_GLYPH_H2.menu.DebugLevel.none=None +Pcbcupid_GLYPH_H2.menu.DebugLevel.none.build.code_debug=0 +Pcbcupid_GLYPH_H2.menu.DebugLevel.error=Error +Pcbcupid_GLYPH_H2.menu.DebugLevel.error.build.code_debug=1 +Pcbcupid_GLYPH_H2.menu.DebugLevel.warn=Warn +Pcbcupid_GLYPH_H2.menu.DebugLevel.warn.build.code_debug=2 +Pcbcupid_GLYPH_H2.menu.DebugLevel.info=Info +Pcbcupid_GLYPH_H2.menu.DebugLevel.info.build.code_debug=3 +Pcbcupid_GLYPH_H2.menu.DebugLevel.debug=Debug +Pcbcupid_GLYPH_H2.menu.DebugLevel.debug.build.code_debug=4 +Pcbcupid_GLYPH_H2.menu.DebugLevel.verbose=Verbose +Pcbcupid_GLYPH_H2.menu.DebugLevel.verbose.build.code_debug=5 + +Pcbcupid_GLYPH_H2.menu.EraseFlash.none=Disabled +Pcbcupid_GLYPH_H2.menu.EraseFlash.none.upload.erase_cmd= +Pcbcupid_GLYPH_H2.menu.EraseFlash.all=Enabled +Pcbcupid_GLYPH_H2.menu.EraseFlash.all.upload.erase_cmd=-e + +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default=Disabled +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default.build.zigbee_mode= +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default.build.zigbee_libs= +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed=Zigbee ED (end device) +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +Pcbcupid_GLYPH_C6.name=Pcbcupid GLYPH C6 + +Pcbcupid_GLYPH_C6.bootloader.tool=esptool_py +Pcbcupid_GLYPH_C6.bootloader.tool.default=esptool_py + +Pcbcupid_GLYPH_C6.upload.tool=esptool_py +Pcbcupid_GLYPH_C6.upload.tool.default=esptool_py +Pcbcupid_GLYPH_C6.upload.tool.network=esp_ota + +Pcbcupid_GLYPH_C6.upload.maximum_size=1310720 +Pcbcupid_GLYPH_C6.upload.maximum_data_size=327680 +Pcbcupid_GLYPH_C6.upload.flags= +Pcbcupid_GLYPH_C6.upload.extra_flags= +Pcbcupid_GLYPH_C6.upload.use_1200bps_touch=false +Pcbcupid_GLYPH_C6.upload.wait_for_upload_port=false + +Pcbcupid_GLYPH_C6.serial.disableDTR=false +Pcbcupid_GLYPH_C6.serial.disableRTS=false + +Pcbcupid_GLYPH_C6.build.tarch=riscv32 +Pcbcupid_GLYPH_C6.build.target=esp +Pcbcupid_GLYPH_C6.build.mcu=esp32c6 +Pcbcupid_GLYPH_C6.build.core=esp32 +Pcbcupid_GLYPH_C6.build.variant=Pcbcupid_GLYPH_C6 +Pcbcupid_GLYPH_C6.build.board=PCBCUPID_GLYPHC6 +Pcbcupid_GLYPH_C6.build.bootloader_addr=0x0 + +Pcbcupid_GLYPH_C6.build.cdc_on_boot=1 +Pcbcupid_GLYPH_C6.build.f_cpu=160000000L +Pcbcupid_GLYPH_C6.build.flash_size=4MB +Pcbcupid_GLYPH_C6.build.flash_freq=80m +Pcbcupid_GLYPH_C6.build.flash_mode=qio +Pcbcupid_GLYPH_C6.build.boot=qio +Pcbcupid_GLYPH_C6.build.partitions=default +Pcbcupid_GLYPH_C6.build.defines= + +## IDE 2.0 Seems to not update the value +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.default=Disabled +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin=Integrated USB JTAG +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external=FTDI Adapter +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge=ESP USB Bridge +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +Pcbcupid_GLYPH_C6.menu.CDCOnBoot.cdc=Enabled +Pcbcupid_GLYPH_C6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +Pcbcupid_GLYPH_C6.menu.CDCOnBoot.default=Disabled +Pcbcupid_GLYPH_C6.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +Pcbcupid_GLYPH_C6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.default.build.partitions=default +Pcbcupid_GLYPH_C6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota.build.partitions=no_ota +Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app.build.partitions=huge_app +Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee.build.partitions=zigbee +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +Pcbcupid_GLYPH_C6.menu.CPUFreq.160=160MHz (WiFi) +Pcbcupid_GLYPH_C6.menu.CPUFreq.160.build.f_cpu=160000000L +Pcbcupid_GLYPH_C6.menu.CPUFreq.80=80MHz (WiFi) +Pcbcupid_GLYPH_C6.menu.CPUFreq.80.build.f_cpu=80000000L +Pcbcupid_GLYPH_C6.menu.CPUFreq.40=40MHz +Pcbcupid_GLYPH_C6.menu.CPUFreq.40.build.f_cpu=40000000L +Pcbcupid_GLYPH_C6.menu.CPUFreq.20=20MHz +Pcbcupid_GLYPH_C6.menu.CPUFreq.20.build.f_cpu=20000000L +Pcbcupid_GLYPH_C6.menu.CPUFreq.10=10MHz +Pcbcupid_GLYPH_C6.menu.CPUFreq.10.build.f_cpu=10000000L + +Pcbcupid_GLYPH_C6.menu.FlashMode.qio=QIO +Pcbcupid_GLYPH_C6.menu.FlashMode.qio.build.flash_mode=dio +Pcbcupid_GLYPH_C6.menu.FlashMode.qio.build.boot=qio +Pcbcupid_GLYPH_C6.menu.FlashMode.dio=DIO +Pcbcupid_GLYPH_C6.menu.FlashMode.dio.build.flash_mode=dio +Pcbcupid_GLYPH_C6.menu.FlashMode.dio.build.boot=dio + +Pcbcupid_GLYPH_C6.menu.FlashFreq.80=80MHz +Pcbcupid_GLYPH_C6.menu.FlashFreq.80.build.flash_freq=80m +Pcbcupid_GLYPH_C6.menu.FlashFreq.40=40MHz +Pcbcupid_GLYPH_C6.menu.FlashFreq.40.build.flash_freq=40m + +Pcbcupid_GLYPH_C6.menu.FlashSize.4M=4MB (32Mb) +Pcbcupid_GLYPH_C6.menu.FlashSize.4M.build.flash_size=4MB + +Pcbcupid_GLYPH_C6.menu.UploadSpeed.921600=921600 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.921600.upload.speed=921600 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.115200=115200 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.115200.upload.speed=115200 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.256000.windows=256000 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.256000.upload.speed=256000 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400.windows.upload.speed=256000 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400=230400 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400.upload.speed=230400 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.linux=460800 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.macosx=460800 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.upload.speed=460800 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.512000.windows=512000 +Pcbcupid_GLYPH_C6.menu.UploadSpeed.512000.upload.speed=512000 + +Pcbcupid_GLYPH_C6.menu.DebugLevel.none=None +Pcbcupid_GLYPH_C6.menu.DebugLevel.none.build.code_debug=0 +Pcbcupid_GLYPH_C6.menu.DebugLevel.error=Error +Pcbcupid_GLYPH_C6.menu.DebugLevel.error.build.code_debug=1 +Pcbcupid_GLYPH_C6.menu.DebugLevel.warn=Warn +Pcbcupid_GLYPH_C6.menu.DebugLevel.warn.build.code_debug=2 +Pcbcupid_GLYPH_C6.menu.DebugLevel.info=Info +Pcbcupid_GLYPH_C6.menu.DebugLevel.info.build.code_debug=3 +Pcbcupid_GLYPH_C6.menu.DebugLevel.debug=Debug +Pcbcupid_GLYPH_C6.menu.DebugLevel.debug.build.code_debug=4 +Pcbcupid_GLYPH_C6.menu.DebugLevel.verbose=Verbose +Pcbcupid_GLYPH_C6.menu.DebugLevel.verbose.build.code_debug=5 + +Pcbcupid_GLYPH_C6.menu.EraseFlash.none=Disabled +Pcbcupid_GLYPH_C6.menu.EraseFlash.none.upload.erase_cmd= +Pcbcupid_GLYPH_C6.menu.EraseFlash.all=Enabled +Pcbcupid_GLYPH_C6.menu.EraseFlash.all.upload.erase_cmd=-e + +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default=Disabled +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default.build.zigbee_mode= +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default.build.zigbee_libs= +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed=Zigbee ED (end device) +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +yb_esp32s3_amp_v2.name=YelloByte YB-ESP32-S3-AMP (Rev.2) + +yb_esp32s3_amp_v2.bootloader.tool=esptool_py +yb_esp32s3_amp_v2.bootloader.tool.default=esptool_py + +yb_esp32s3_amp_v2.upload.tool=esptool_py +yb_esp32s3_amp_v2.upload.tool.default=esptool_py +yb_esp32s3_amp_v2.upload.tool.network=esp_ota + +yb_esp32s3_amp_v2.upload.maximum_size=1310720 +yb_esp32s3_amp_v2.upload.maximum_data_size=327680 +yb_esp32s3_amp_v2.upload.flags= +yb_esp32s3_amp_v2.upload.extra_flags= +yb_esp32s3_amp_v2.upload.use_1200bps_touch=false +yb_esp32s3_amp_v2.upload.wait_for_upload_port=false + +yb_esp32s3_amp_v2.serial.disableDTR=false +yb_esp32s3_amp_v2.serial.disableRTS=false + +yb_esp32s3_amp_v2.build.tarch=xtensa +yb_esp32s3_amp_v2.build.bootloader_addr=0x0 +yb_esp32s3_amp_v2.build.target=esp32s3 +yb_esp32s3_amp_v2.build.mcu=esp32s3 +yb_esp32s3_amp_v2.build.core=esp32 +yb_esp32s3_amp_v2.build.variant=yb_esp32s3_amp_v2 +yb_esp32s3_amp_v2.build.board=YB_ESP32S3_AMP_V2 + +yb_esp32s3_amp_v2.build.usb_mode=1 +yb_esp32s3_amp_v2.build.cdc_on_boot=0 +yb_esp32s3_amp_v2.build.msc_on_boot=0 +yb_esp32s3_amp_v2.build.dfu_on_boot=0 +yb_esp32s3_amp_v2.build.f_cpu=240000000L +yb_esp32s3_amp_v2.build.flash_size=8MB +yb_esp32s3_amp_v2.build.flash_freq=80m +yb_esp32s3_amp_v2.build.flash_mode=dio +yb_esp32s3_amp_v2.build.boot=qio +yb_esp32s3_amp_v2.build.partitions=default +yb_esp32s3_amp_v2.build.defines= +yb_esp32s3_amp_v2.build.loop_core= +yb_esp32s3_amp_v2.build.event_core= +yb_esp32s3_amp_v2.build.flash_type=qio +yb_esp32s3_amp_v2.build.psram_type=qspi +yb_esp32s3_amp_v2.build.memory_type={build.flash_type}_{build.psram_type} + +yb_esp32s3_amp_v2.menu.JTAGAdapter.default=Disabled +yb_esp32s3_amp_v2.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_amp_v2.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_amp_v2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_amp_v2.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_amp_v2.menu.LoopCore.1=Core 1 +yb_esp32s3_amp_v2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_amp_v2.menu.LoopCore.0=Core 0 +yb_esp32s3_amp_v2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_amp_v2.menu.EventsCore.1=Core 1 +yb_esp32s3_amp_v2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_amp_v2.menu.EventsCore.0=Core 0 +yb_esp32s3_amp_v2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_amp_v2.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_amp_v2.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_amp_v2.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_amp_v2.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_amp_v2.menu.CDCOnBoot.default=Disabled +yb_esp32s3_amp_v2.menu.CDCOnBoot.default.build.cdc_on_boot=0 +yb_esp32s3_amp_v2.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_amp_v2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +yb_esp32s3_amp_v2.menu.MSCOnBoot.default=Disabled +yb_esp32s3_amp_v2.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_amp_v2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp_v2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_amp_v2.menu.DFUOnBoot.default=Disabled +yb_esp32s3_amp_v2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_amp_v2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp_v2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_amp_v2.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_amp_v2.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_amp_v2.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_amp_v2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_amp_v2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_amp_v2.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_amp_v2.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_amp_v2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp_v2.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_amp_v2.menu.PSRAM.disabled=Disabled +yb_esp32s3_amp_v2.menu.PSRAM.disabled.build.defines= +yb_esp32s3_amp_v2.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_amp_v2.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_amp_v2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp_v2.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_amp_v2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_amp_v2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_amp_v2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +yb_esp32s3_amp_v2.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_amp_v2.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_amp_v2.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_amp_v2.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_amp_v2.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_amp_v2.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_amp_v2.menu.CPUFreq.40=40MHz +yb_esp32s3_amp_v2.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_amp_v2.menu.CPUFreq.20=20MHz +yb_esp32s3_amp_v2.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_amp_v2.menu.CPUFreq.10=10MHz +yb_esp32s3_amp_v2.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_amp_v2.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_amp_v2.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_amp_v2.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_amp_v2.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_amp_v2.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_amp_v2.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_amp_v2.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_amp_v2.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_amp_v2.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_amp_v2.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_amp_v2.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_amp_v2.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_amp_v2.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_amp_v2.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_amp_v2.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_amp_v2.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_amp_v2.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_amp_v2.menu.UploadSpeed.921600=921600 +yb_esp32s3_amp_v2.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_amp_v2.menu.UploadSpeed.115200=115200 +yb_esp32s3_amp_v2.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_amp_v2.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_amp_v2.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_amp_v2.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_amp_v2.menu.UploadSpeed.230400=230400 +yb_esp32s3_amp_v2.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_amp_v2.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_amp_v2.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_amp_v2.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_amp_v2.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_amp_v2.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_amp_v2.menu.DebugLevel.none=None +yb_esp32s3_amp_v2.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_amp_v2.menu.DebugLevel.error=Error +yb_esp32s3_amp_v2.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_amp_v2.menu.DebugLevel.warn=Warn +yb_esp32s3_amp_v2.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_amp_v2.menu.DebugLevel.info=Info +yb_esp32s3_amp_v2.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_amp_v2.menu.DebugLevel.debug=Debug +yb_esp32s3_amp_v2.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_amp_v2.menu.DebugLevel.verbose=Verbose +yb_esp32s3_amp_v2.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_amp_v2.menu.EraseFlash.none=Disabled +yb_esp32s3_amp_v2.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_amp_v2.menu.EraseFlash.all=Enabled +yb_esp32s3_amp_v2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +yb_esp32s3_amp_v3.name=YelloByte YB-ESP32-S3-AMP (Rev.3) + +yb_esp32s3_amp_v3.bootloader.tool=esptool_py +yb_esp32s3_amp_v3.bootloader.tool.default=esptool_py + +yb_esp32s3_amp_v3.upload.tool=esptool_py +yb_esp32s3_amp_v3.upload.tool.default=esptool_py +yb_esp32s3_amp_v3.upload.tool.network=esp_ota + +yb_esp32s3_amp_v3.upload.maximum_size=1310720 +yb_esp32s3_amp_v3.upload.maximum_data_size=327680 +yb_esp32s3_amp_v3.upload.flags= +yb_esp32s3_amp_v3.upload.extra_flags= +yb_esp32s3_amp_v3.upload.use_1200bps_touch=false +yb_esp32s3_amp_v3.upload.wait_for_upload_port=false + +yb_esp32s3_amp_v3.serial.disableDTR=false +yb_esp32s3_amp_v3.serial.disableRTS=false + +yb_esp32s3_amp_v3.build.tarch=xtensa +yb_esp32s3_amp_v3.build.bootloader_addr=0x0 +yb_esp32s3_amp_v3.build.target=esp32s3 +yb_esp32s3_amp_v3.build.mcu=esp32s3 +yb_esp32s3_amp_v3.build.core=esp32 +yb_esp32s3_amp_v3.build.variant=yb_esp32s3_amp_v3 +yb_esp32s3_amp_v3.build.board=YB_ESP32S3_AMP_V3 + +yb_esp32s3_amp_v3.build.usb_mode=1 +yb_esp32s3_amp_v3.build.cdc_on_boot=1 +yb_esp32s3_amp_v3.build.msc_on_boot=0 +yb_esp32s3_amp_v3.build.dfu_on_boot=0 +yb_esp32s3_amp_v3.build.f_cpu=240000000L +yb_esp32s3_amp_v3.build.flash_size=8MB +yb_esp32s3_amp_v3.build.flash_freq=80m +yb_esp32s3_amp_v3.build.flash_mode=dio +yb_esp32s3_amp_v3.build.boot=qio +yb_esp32s3_amp_v3.build.partitions=default +yb_esp32s3_amp_v3.build.defines= +yb_esp32s3_amp_v3.build.loop_core= +yb_esp32s3_amp_v3.build.event_core= +yb_esp32s3_amp_v3.build.flash_type=qio +yb_esp32s3_amp_v3.build.psram_type=qspi +yb_esp32s3_amp_v3.build.memory_type={build.flash_type}_{build.psram_type} + +yb_esp32s3_amp_v3.menu.JTAGAdapter.default=Disabled +yb_esp32s3_amp_v3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin=Integrated USB JTAG +yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +yb_esp32s3_amp_v3.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_amp_v3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_amp_v3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_amp_v3.menu.LoopCore.1=Core 1 +yb_esp32s3_amp_v3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_amp_v3.menu.LoopCore.0=Core 0 +yb_esp32s3_amp_v3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_amp_v3.menu.EventsCore.1=Core 1 +yb_esp32s3_amp_v3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_amp_v3.menu.EventsCore.0=Core 0 +yb_esp32s3_amp_v3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_amp_v3.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_amp_v3.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_amp_v3.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_amp_v3.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_amp_v3.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_amp_v3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +yb_esp32s3_amp_v3.menu.CDCOnBoot.default=Disabled +yb_esp32s3_amp_v3.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +yb_esp32s3_amp_v3.menu.MSCOnBoot.default=Disabled +yb_esp32s3_amp_v3.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_amp_v3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp_v3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_amp_v3.menu.DFUOnBoot.default=Disabled +yb_esp32s3_amp_v3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_amp_v3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp_v3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_amp_v3.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_amp_v3.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_amp_v3.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_amp_v3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_amp_v3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_amp_v3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_amp_v3.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_amp_v3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp_v3.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_amp_v3.menu.PSRAM.disabled=Disabled +yb_esp32s3_amp_v3.menu.PSRAM.disabled.build.defines= +yb_esp32s3_amp_v3.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_amp_v3.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_amp_v3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp_v3.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_amp_v3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_amp_v3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_amp_v3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +yb_esp32s3_amp_v3.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_amp_v3.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_amp_v3.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_amp_v3.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_amp_v3.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_amp_v3.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_amp_v3.menu.CPUFreq.40=40MHz +yb_esp32s3_amp_v3.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_amp_v3.menu.CPUFreq.20=20MHz +yb_esp32s3_amp_v3.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_amp_v3.menu.CPUFreq.10=10MHz +yb_esp32s3_amp_v3.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_amp_v3.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_amp_v3.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_amp_v3.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_amp_v3.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_amp_v3.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_amp_v3.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_amp_v3.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_amp_v3.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_amp_v3.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_amp_v3.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_amp_v3.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_amp_v3.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_amp_v3.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_amp_v3.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_amp_v3.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_amp_v3.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_amp_v3.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_amp_v3.menu.UploadSpeed.921600=921600 +yb_esp32s3_amp_v3.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_amp_v3.menu.UploadSpeed.115200=115200 +yb_esp32s3_amp_v3.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_amp_v3.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_amp_v3.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_amp_v3.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_amp_v3.menu.UploadSpeed.230400=230400 +yb_esp32s3_amp_v3.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_amp_v3.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_amp_v3.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_amp_v3.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_amp_v3.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_amp_v3.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_amp_v3.menu.DebugLevel.none=None +yb_esp32s3_amp_v3.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_amp_v3.menu.DebugLevel.error=Error +yb_esp32s3_amp_v3.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_amp_v3.menu.DebugLevel.warn=Warn +yb_esp32s3_amp_v3.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_amp_v3.menu.DebugLevel.info=Info +yb_esp32s3_amp_v3.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_amp_v3.menu.DebugLevel.debug=Debug +yb_esp32s3_amp_v3.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_amp_v3.menu.DebugLevel.verbose=Verbose +yb_esp32s3_amp_v3.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_amp_v3.menu.EraseFlash.none=Disabled +yb_esp32s3_amp_v3.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_amp_v3.menu.EraseFlash.all=Enabled +yb_esp32s3_amp_v3.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +yb_esp32s3_eth.name=YelloByte YB-ESP32-S3-ETH + +yb_esp32s3_eth.bootloader.tool=esptool_py +yb_esp32s3_eth.bootloader.tool.default=esptool_py + +yb_esp32s3_eth.upload.tool=esptool_py +yb_esp32s3_eth.upload.tool.default=esptool_py +yb_esp32s3_eth.upload.tool.network=esp_ota + +yb_esp32s3_eth.upload.maximum_size=1310720 +yb_esp32s3_eth.upload.maximum_data_size=327680 +yb_esp32s3_eth.upload.flags= +yb_esp32s3_eth.upload.extra_flags= +yb_esp32s3_eth.upload.use_1200bps_touch=false +yb_esp32s3_eth.upload.wait_for_upload_port=false + +yb_esp32s3_eth.serial.disableDTR=false +yb_esp32s3_eth.serial.disableRTS=false + +yb_esp32s3_eth.build.tarch=xtensa +yb_esp32s3_eth.build.bootloader_addr=0x0 +yb_esp32s3_eth.build.target=esp32s3 +yb_esp32s3_eth.build.mcu=esp32s3 +yb_esp32s3_eth.build.core=esp32 +yb_esp32s3_eth.build.variant=yb_esp32s3_eth +yb_esp32s3_eth.build.board=YB_ESP32S3_ETH + +yb_esp32s3_eth.build.usb_mode=1 +yb_esp32s3_eth.build.cdc_on_boot=0 +yb_esp32s3_eth.build.msc_on_boot=0 +yb_esp32s3_eth.build.dfu_on_boot=0 +yb_esp32s3_eth.build.f_cpu=240000000L +yb_esp32s3_eth.build.flash_size=4MB +yb_esp32s3_eth.build.flash_freq=80m +yb_esp32s3_eth.build.flash_mode=dio +yb_esp32s3_eth.build.boot=qio +yb_esp32s3_eth.build.boot_freq=80m +yb_esp32s3_eth.build.partitions=default +yb_esp32s3_eth.build.defines= +yb_esp32s3_eth.build.loop_core= +yb_esp32s3_eth.build.event_core= +yb_esp32s3_eth.build.psram_type=qspi +yb_esp32s3_eth.build.memory_type={build.boot}_{build.psram_type} + +yb_esp32s3_eth.menu.JTAGAdapter.default=Disabled +yb_esp32s3_eth.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_eth.menu.JTAGAdapter.builtin=Integrated USB JTAG +yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +yb_esp32s3_eth.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_eth.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_eth.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_eth.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_eth.menu.LoopCore.1=Core 1 +yb_esp32s3_eth.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_eth.menu.LoopCore.0=Core 0 +yb_esp32s3_eth.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_eth.menu.EventsCore.1=Core 1 +yb_esp32s3_eth.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_eth.menu.EventsCore.0=Core 0 +yb_esp32s3_eth.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_eth.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_eth.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_eth.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_eth.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_eth.menu.CDCOnBoot.default=Disabled +yb_esp32s3_eth.menu.CDCOnBoot.default.build.cdc_on_boot=0 +yb_esp32s3_eth.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_eth.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +yb_esp32s3_eth.menu.MSCOnBoot.default=Disabled +yb_esp32s3_eth.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_eth.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_eth.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_eth.menu.DFUOnBoot.default=Disabled +yb_esp32s3_eth.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_eth.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_eth.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_eth.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_eth.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_eth.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_eth.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_eth.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_eth.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_eth.menu.PSRAM.disabled=Disabled +yb_esp32s3_eth.menu.PSRAM.disabled.build.defines= +yb_esp32s3_eth.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_eth.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_eth.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_eth.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_eth.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_eth.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_eth.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_eth.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_eth.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_eth.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_eth.menu.PartitionScheme.default_16MB=16M with spiffs (6.25MB APP/3.43MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +yb_esp32s3_eth.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 +yb_esp32s3_eth.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.fatflash.build.partitions=ffat +yb_esp32s3_eth.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_eth.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_eth.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_eth.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_eth.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_eth.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_eth.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_eth.menu.PartitionScheme.custom=Custom +yb_esp32s3_eth.menu.PartitionScheme.custom.build.partitions= +yb_esp32s3_eth.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +yb_esp32s3_eth.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_eth.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_eth.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_eth.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_eth.menu.CPUFreq.40=40MHz +yb_esp32s3_eth.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_eth.menu.CPUFreq.20=20MHz +yb_esp32s3_eth.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_eth.menu.CPUFreq.10=10MHz +yb_esp32s3_eth.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_eth.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_eth.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_eth.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_eth.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_eth.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_eth.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_eth.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_eth.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_eth.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_eth.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_eth.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_eth.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_eth.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_eth.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_eth.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_eth.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_eth.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_eth.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_eth.menu.UploadSpeed.921600=921600 +yb_esp32s3_eth.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_eth.menu.UploadSpeed.115200=115200 +yb_esp32s3_eth.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_eth.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_eth.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_eth.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_eth.menu.UploadSpeed.230400=230400 +yb_esp32s3_eth.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_eth.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_eth.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_eth.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_eth.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_eth.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_eth.menu.DebugLevel.none=None +yb_esp32s3_eth.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_eth.menu.DebugLevel.error=Error +yb_esp32s3_eth.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_eth.menu.DebugLevel.warn=Warn +yb_esp32s3_eth.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_eth.menu.DebugLevel.info=Info +yb_esp32s3_eth.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_eth.menu.DebugLevel.debug=Debug +yb_esp32s3_eth.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_eth.menu.DebugLevel.verbose=Verbose +yb_esp32s3_eth.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_eth.menu.EraseFlash.none=Disabled +yb_esp32s3_eth.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_eth.menu.EraseFlash.all=Enabled +yb_esp32s3_eth.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +yb_esp32s3_drv.name=YelloByte YB-ESP32-S3-DRV + +yb_esp32s3_drv.bootloader.tool=esptool_py +yb_esp32s3_drv.bootloader.tool.default=esptool_py + +yb_esp32s3_drv.upload.tool=esptool_py +yb_esp32s3_drv.upload.tool.default=esptool_py +yb_esp32s3_drv.upload.tool.network=esp_ota + +yb_esp32s3_drv.upload.maximum_size=1310720 +yb_esp32s3_drv.upload.maximum_data_size=327680 +yb_esp32s3_drv.upload.flags= +yb_esp32s3_drv.upload.extra_flags= +yb_esp32s3_drv.upload.use_1200bps_touch=false +yb_esp32s3_drv.upload.wait_for_upload_port=false + +yb_esp32s3_drv.serial.disableDTR=false +yb_esp32s3_drv.serial.disableRTS=false + +yb_esp32s3_drv.build.tarch=xtensa +yb_esp32s3_drv.build.bootloader_addr=0x0 +yb_esp32s3_drv.build.target=esp32s3 +yb_esp32s3_drv.build.mcu=esp32s3 +yb_esp32s3_drv.build.core=esp32 +yb_esp32s3_drv.build.variant=yb_esp32s3_drv +yb_esp32s3_drv.build.board=YB_ESP32S3_DRV + +yb_esp32s3_drv.build.usb_mode=1 +yb_esp32s3_drv.build.cdc_on_boot=1 +yb_esp32s3_drv.build.msc_on_boot=0 +yb_esp32s3_drv.build.dfu_on_boot=0 +yb_esp32s3_drv.build.f_cpu=240000000L +yb_esp32s3_drv.build.flash_size=8MB +yb_esp32s3_drv.build.flash_freq=80m +yb_esp32s3_drv.build.flash_mode=dio +yb_esp32s3_drv.build.boot=qio +yb_esp32s3_drv.build.partitions=default +yb_esp32s3_drv.build.defines= +yb_esp32s3_drv.build.loop_core= +yb_esp32s3_drv.build.event_core= +yb_esp32s3_drv.build.flash_type=qio +yb_esp32s3_drv.build.psram_type=qspi +yb_esp32s3_drv.build.memory_type={build.flash_type}_{build.psram_type} + +yb_esp32s3_drv.menu.JTAGAdapter.default=Disabled +yb_esp32s3_drv.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_drv.menu.JTAGAdapter.builtin=Integrated USB JTAG +yb_esp32s3_drv.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +yb_esp32s3_drv.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +yb_esp32s3_drv.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_drv.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_drv.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_drv.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_drv.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_drv.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_drv.menu.LoopCore.1=Core 1 +yb_esp32s3_drv.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_drv.menu.LoopCore.0=Core 0 +yb_esp32s3_drv.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_drv.menu.EventsCore.1=Core 1 +yb_esp32s3_drv.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_drv.menu.EventsCore.0=Core 0 +yb_esp32s3_drv.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_drv.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_drv.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_drv.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_drv.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_drv.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_drv.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +yb_esp32s3_drv.menu.CDCOnBoot.default=Disabled +yb_esp32s3_drv.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +yb_esp32s3_drv.menu.MSCOnBoot.default=Disabled +yb_esp32s3_drv.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_drv.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_drv.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_drv.menu.DFUOnBoot.default=Disabled +yb_esp32s3_drv.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_drv.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_drv.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_drv.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_drv.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_drv.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_drv.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_drv.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_drv.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_drv.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_drv.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_drv.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_drv.menu.PSRAM.disabled=Disabled +yb_esp32s3_drv.menu.PSRAM.disabled.build.defines= +yb_esp32s3_drv.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_drv.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_drv.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_drv.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_drv.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_drv.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_drv.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_drv.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_drv.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_drv.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_drv.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_drv.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_drv.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_drv.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_drv.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_drv.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_drv.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_drv.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_drv.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_drv.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_drv.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_drv.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_drv.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +yb_esp32s3_drv.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_drv.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_drv.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_drv.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_drv.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +yb_esp32s3_drv.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_drv.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_drv.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_drv.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_drv.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_drv.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_drv.menu.CPUFreq.40=40MHz +yb_esp32s3_drv.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_drv.menu.CPUFreq.20=20MHz +yb_esp32s3_drv.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_drv.menu.CPUFreq.10=10MHz +yb_esp32s3_drv.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_drv.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_drv.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_drv.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_drv.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_drv.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_drv.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_drv.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_drv.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_drv.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_drv.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_drv.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_drv.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_drv.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_drv.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_drv.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_drv.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_drv.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_drv.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_drv.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_drv.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_drv.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_drv.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_drv.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_drv.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_drv.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_drv.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_drv.menu.UploadSpeed.921600=921600 +yb_esp32s3_drv.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_drv.menu.UploadSpeed.115200=115200 +yb_esp32s3_drv.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_drv.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_drv.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_drv.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_drv.menu.UploadSpeed.230400=230400 +yb_esp32s3_drv.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_drv.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_drv.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_drv.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_drv.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_drv.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_drv.menu.DebugLevel.none=None +yb_esp32s3_drv.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_drv.menu.DebugLevel.error=Error +yb_esp32s3_drv.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_drv.menu.DebugLevel.warn=Warn +yb_esp32s3_drv.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_drv.menu.DebugLevel.info=Info +yb_esp32s3_drv.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_drv.menu.DebugLevel.debug=Debug +yb_esp32s3_drv.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_drv.menu.DebugLevel.verbose=Verbose +yb_esp32s3_drv.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_drv.menu.EraseFlash.none=Disabled +yb_esp32s3_drv.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_drv.menu.EraseFlash.all=Enabled +yb_esp32s3_drv.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +yb_esp32s3_amp.name=YelloByte YB-ESP32-S3-AMP + +yb_esp32s3_amp.bootloader.tool=esptool_py +yb_esp32s3_amp.bootloader.tool.default=esptool_py + +yb_esp32s3_amp.upload.tool=esptool_py +yb_esp32s3_amp.upload.tool.default=esptool_py +yb_esp32s3_amp.upload.tool.network=esp_ota + +yb_esp32s3_amp.upload.maximum_size=1310720 +yb_esp32s3_amp.upload.maximum_data_size=327680 +yb_esp32s3_amp.upload.flags= +yb_esp32s3_amp.upload.extra_flags= +yb_esp32s3_amp.upload.use_1200bps_touch=false +yb_esp32s3_amp.upload.wait_for_upload_port=false + +yb_esp32s3_amp.serial.disableDTR=false +yb_esp32s3_amp.serial.disableRTS=false + +yb_esp32s3_amp.build.tarch=xtensa +yb_esp32s3_amp.build.bootloader_addr=0x0 +yb_esp32s3_amp.build.target=esp32s3 +yb_esp32s3_amp.build.mcu=esp32s3 +yb_esp32s3_amp.build.core=esp32 +yb_esp32s3_amp.build.variant=yb_esp32s3_amp +yb_esp32s3_amp.build.board=YB_ESP32S3_AMP + +yb_esp32s3_amp.build.usb_mode=1 +yb_esp32s3_amp.build.cdc_on_boot=0 +yb_esp32s3_amp.build.msc_on_boot=0 +yb_esp32s3_amp.build.dfu_on_boot=0 +yb_esp32s3_amp.build.f_cpu=240000000L +yb_esp32s3_amp.build.flash_size=8MB +yb_esp32s3_amp.build.flash_freq=80m +yb_esp32s3_amp.build.flash_mode=dio +yb_esp32s3_amp.build.boot=qio +yb_esp32s3_amp.build.partitions=default +yb_esp32s3_amp.build.defines= +yb_esp32s3_amp.build.loop_core= +yb_esp32s3_amp.build.event_core= +yb_esp32s3_amp.build.flash_type=qio +yb_esp32s3_amp.build.psram_type=qspi +yb_esp32s3_amp.build.memory_type={build.flash_type}_{build.psram_type} + +yb_esp32s3_amp.menu.JTAGAdapter.default=Disabled +yb_esp32s3_amp.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_amp.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_amp.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_amp.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_amp.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_amp.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_amp.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_amp.menu.LoopCore.1=Core 1 +yb_esp32s3_amp.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_amp.menu.LoopCore.0=Core 0 +yb_esp32s3_amp.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_amp.menu.EventsCore.1=Core 1 +yb_esp32s3_amp.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_amp.menu.EventsCore.0=Core 0 +yb_esp32s3_amp.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_amp.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_amp.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_amp.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_amp.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_amp.menu.CDCOnBoot.default=Disabled +yb_esp32s3_amp.menu.CDCOnBoot.default.build.cdc_on_boot=0 +yb_esp32s3_amp.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_amp.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +yb_esp32s3_amp.menu.MSCOnBoot.default=Disabled +yb_esp32s3_amp.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_amp.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_amp.menu.DFUOnBoot.default=Disabled +yb_esp32s3_amp.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_amp.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_amp.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_amp.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_amp.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_amp.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_amp.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_amp.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_amp.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_amp.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_amp.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_amp.menu.PSRAM.disabled=Disabled +yb_esp32s3_amp.menu.PSRAM.disabled.build.defines= +yb_esp32s3_amp.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_amp.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_amp.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_amp.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_amp.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_amp.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_amp.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_amp.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_amp.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_amp.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_amp.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_amp.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_amp.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_amp.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_amp.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_amp.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_amp.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_amp.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_amp.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_amp.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_amp.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_amp.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_amp.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +yb_esp32s3_amp.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_amp.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_amp.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_amp.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_amp.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +yb_esp32s3_amp.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_amp.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_amp.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_amp.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_amp.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_amp.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_amp.menu.CPUFreq.40=40MHz +yb_esp32s3_amp.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_amp.menu.CPUFreq.20=20MHz +yb_esp32s3_amp.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_amp.menu.CPUFreq.10=10MHz +yb_esp32s3_amp.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_amp.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_amp.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_amp.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_amp.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_amp.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_amp.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_amp.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_amp.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_amp.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_amp.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_amp.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_amp.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_amp.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_amp.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_amp.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_amp.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_amp.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_amp.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_amp.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_amp.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_amp.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_amp.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_amp.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_amp.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_amp.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_amp.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_amp.menu.UploadSpeed.921600=921600 +yb_esp32s3_amp.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_amp.menu.UploadSpeed.115200=115200 +yb_esp32s3_amp.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_amp.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_amp.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_amp.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_amp.menu.UploadSpeed.230400=230400 +yb_esp32s3_amp.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_amp.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_amp.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_amp.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_amp.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_amp.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_amp.menu.DebugLevel.none=None +yb_esp32s3_amp.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_amp.menu.DebugLevel.error=Error +yb_esp32s3_amp.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_amp.menu.DebugLevel.warn=Warn +yb_esp32s3_amp.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_amp.menu.DebugLevel.info=Info +yb_esp32s3_amp.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_amp.menu.DebugLevel.debug=Debug +yb_esp32s3_amp.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_amp.menu.DebugLevel.verbose=Verbose +yb_esp32s3_amp.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_amp.menu.EraseFlash.none=Disabled +yb_esp32s3_amp.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_amp.menu.EraseFlash.all=Enabled +yb_esp32s3_amp.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +yb_esp32s3_dac.name=YelloByte YB-ESP32-S3-DAC + +yb_esp32s3_dac.bootloader.tool=esptool_py +yb_esp32s3_dac.bootloader.tool.default=esptool_py + +yb_esp32s3_dac.upload.tool=esptool_py +yb_esp32s3_dac.upload.tool.default=esptool_py +yb_esp32s3_dac.upload.tool.network=esp_ota + +yb_esp32s3_dac.upload.maximum_size=1310720 +yb_esp32s3_dac.upload.maximum_data_size=327680 +yb_esp32s3_dac.upload.flags= +yb_esp32s3_dac.upload.extra_flags= +yb_esp32s3_dac.upload.use_1200bps_touch=false +yb_esp32s3_dac.upload.wait_for_upload_port=false + +yb_esp32s3_dac.serial.disableDTR=false +yb_esp32s3_dac.serial.disableRTS=false + +yb_esp32s3_dac.build.tarch=xtensa +yb_esp32s3_dac.build.bootloader_addr=0x0 +yb_esp32s3_dac.build.target=esp32s3 +yb_esp32s3_dac.build.mcu=esp32s3 +yb_esp32s3_dac.build.core=esp32 +yb_esp32s3_dac.build.variant=yb_esp32s3_dac +yb_esp32s3_dac.build.board=YB_ESP32S3_DAC + +yb_esp32s3_dac.build.usb_mode=1 +yb_esp32s3_dac.build.cdc_on_boot=0 +yb_esp32s3_dac.build.msc_on_boot=0 +yb_esp32s3_dac.build.dfu_on_boot=0 +yb_esp32s3_dac.build.f_cpu=240000000L +yb_esp32s3_dac.build.flash_size=8MB +yb_esp32s3_dac.build.flash_freq=80m +yb_esp32s3_dac.build.flash_mode=dio +yb_esp32s3_dac.build.boot=qio +yb_esp32s3_dac.build.partitions=default +yb_esp32s3_dac.build.defines= +yb_esp32s3_dac.build.loop_core= +yb_esp32s3_dac.build.event_core= +yb_esp32s3_dac.build.flash_type=qio +yb_esp32s3_dac.build.psram_type=qspi +yb_esp32s3_dac.build.memory_type={build.flash_type}_{build.psram_type} + +yb_esp32s3_dac.menu.JTAGAdapter.default=Disabled +yb_esp32s3_dac.menu.JTAGAdapter.default.build.copy_jtag_files=0 +yb_esp32s3_dac.menu.JTAGAdapter.external=FTDI Adapter +yb_esp32s3_dac.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +yb_esp32s3_dac.menu.JTAGAdapter.external.build.copy_jtag_files=1 +yb_esp32s3_dac.menu.JTAGAdapter.bridge=ESP USB Bridge +yb_esp32s3_dac.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +yb_esp32s3_dac.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +yb_esp32s3_dac.menu.LoopCore.1=Core 1 +yb_esp32s3_dac.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +yb_esp32s3_dac.menu.LoopCore.0=Core 0 +yb_esp32s3_dac.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +yb_esp32s3_dac.menu.EventsCore.1=Core 1 +yb_esp32s3_dac.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +yb_esp32s3_dac.menu.EventsCore.0=Core 0 +yb_esp32s3_dac.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +yb_esp32s3_dac.menu.USBMode.hwcdc=Hardware CDC and JTAG +yb_esp32s3_dac.menu.USBMode.hwcdc.build.usb_mode=1 +yb_esp32s3_dac.menu.USBMode.default=USB-OTG (TinyUSB) +yb_esp32s3_dac.menu.USBMode.default.build.usb_mode=0 + +yb_esp32s3_dac.menu.CDCOnBoot.default=Disabled +yb_esp32s3_dac.menu.CDCOnBoot.default.build.cdc_on_boot=0 +yb_esp32s3_dac.menu.CDCOnBoot.cdc=Enabled +yb_esp32s3_dac.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +yb_esp32s3_dac.menu.MSCOnBoot.default=Disabled +yb_esp32s3_dac.menu.MSCOnBoot.default.build.msc_on_boot=0 +yb_esp32s3_dac.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +yb_esp32s3_dac.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +yb_esp32s3_dac.menu.DFUOnBoot.default=Disabled +yb_esp32s3_dac.menu.DFUOnBoot.default.build.dfu_on_boot=0 +yb_esp32s3_dac.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +yb_esp32s3_dac.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +yb_esp32s3_dac.menu.UploadMode.default=UART0 / Hardware CDC +yb_esp32s3_dac.menu.UploadMode.default.upload.use_1200bps_touch=false +yb_esp32s3_dac.menu.UploadMode.default.upload.wait_for_upload_port=false +yb_esp32s3_dac.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +yb_esp32s3_dac.menu.UploadMode.cdc.upload.use_1200bps_touch=true +yb_esp32s3_dac.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +yb_esp32s3_dac.menu.PSRAM.enabled=QSPI PSRAM +yb_esp32s3_dac.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_dac.menu.PSRAM.enabled.build.psram_type=qspi +yb_esp32s3_dac.menu.PSRAM.disabled=Disabled +yb_esp32s3_dac.menu.PSRAM.disabled.build.defines= +yb_esp32s3_dac.menu.PSRAM.disabled.build.psram_type=qspi +yb_esp32s3_dac.menu.PSRAM.opi=OPI PSRAM +yb_esp32s3_dac.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +yb_esp32s3_dac.menu.PSRAM.opi.build.psram_type=opi + +yb_esp32s3_dac.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +yb_esp32s3_dac.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +yb_esp32s3_dac.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.default.build.partitions=default +yb_esp32s3_dac.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +yb_esp32s3_dac.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +yb_esp32s3_dac.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.minimal.build.partitions=minimal +yb_esp32s3_dac.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.no_ota.build.partitions=no_ota +yb_esp32s3_dac.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +yb_esp32s3_dac.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +yb_esp32s3_dac.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +yb_esp32s3_dac.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +yb_esp32s3_dac.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +yb_esp32s3_dac.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +yb_esp32s3_dac.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +yb_esp32s3_dac.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +yb_esp32s3_dac.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +yb_esp32s3_dac.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.huge_app.build.partitions=huge_app +yb_esp32s3_dac.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +yb_esp32s3_dac.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +yb_esp32s3_dac.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +yb_esp32s3_dac.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +yb_esp32s3_dac.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS) +yb_esp32s3_dac.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB +yb_esp32s3_dac.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536 + +yb_esp32s3_dac.menu.CPUFreq.240=240MHz (WiFi) +yb_esp32s3_dac.menu.CPUFreq.240.build.f_cpu=240000000L +yb_esp32s3_dac.menu.CPUFreq.160=160MHz (WiFi) +yb_esp32s3_dac.menu.CPUFreq.160.build.f_cpu=160000000L +yb_esp32s3_dac.menu.CPUFreq.80=80MHz (WiFi) +yb_esp32s3_dac.menu.CPUFreq.80.build.f_cpu=80000000L +yb_esp32s3_dac.menu.CPUFreq.40=40MHz +yb_esp32s3_dac.menu.CPUFreq.40.build.f_cpu=40000000L +yb_esp32s3_dac.menu.CPUFreq.20=20MHz +yb_esp32s3_dac.menu.CPUFreq.20.build.f_cpu=20000000L +yb_esp32s3_dac.menu.CPUFreq.10=10MHz +yb_esp32s3_dac.menu.CPUFreq.10.build.f_cpu=10000000L + +yb_esp32s3_dac.menu.FlashMode.qio=QIO 80MHz +yb_esp32s3_dac.menu.FlashMode.qio.build.flash_mode=dio +yb_esp32s3_dac.menu.FlashMode.qio.build.boot=qio +yb_esp32s3_dac.menu.FlashMode.qio.build.boot_freq=80m +yb_esp32s3_dac.menu.FlashMode.qio.build.flash_freq=80m +yb_esp32s3_dac.menu.FlashMode.qio120=QIO 120MHz +yb_esp32s3_dac.menu.FlashMode.qio120.build.flash_mode=dio +yb_esp32s3_dac.menu.FlashMode.qio120.build.boot=qio +yb_esp32s3_dac.menu.FlashMode.qio120.build.boot_freq=120m +yb_esp32s3_dac.menu.FlashMode.qio120.build.flash_freq=80m +yb_esp32s3_dac.menu.FlashMode.dio=DIO 80MHz +yb_esp32s3_dac.menu.FlashMode.dio.build.flash_mode=dio +yb_esp32s3_dac.menu.FlashMode.dio.build.boot=dio +yb_esp32s3_dac.menu.FlashMode.dio.build.boot_freq=80m +yb_esp32s3_dac.menu.FlashMode.dio.build.flash_freq=80m +yb_esp32s3_dac.menu.FlashMode.opi=OPI 80MHz +yb_esp32s3_dac.menu.FlashMode.opi.build.flash_mode=dout +yb_esp32s3_dac.menu.FlashMode.opi.build.boot=opi +yb_esp32s3_dac.menu.FlashMode.opi.build.boot_freq=80m +yb_esp32s3_dac.menu.FlashMode.opi.build.flash_freq=80m + +yb_esp32s3_dac.menu.FlashSize.8M=8MB (64Mb) +yb_esp32s3_dac.menu.FlashSize.8M.build.flash_size=8MB +yb_esp32s3_dac.menu.FlashSize.4M=4MB (32Mb) +yb_esp32s3_dac.menu.FlashSize.4M.build.flash_size=4MB +yb_esp32s3_dac.menu.FlashSize.16M=16MB (128Mb) +yb_esp32s3_dac.menu.FlashSize.16M.build.flash_size=16MB + +yb_esp32s3_dac.menu.UploadSpeed.921600=921600 +yb_esp32s3_dac.menu.UploadSpeed.921600.upload.speed=921600 +yb_esp32s3_dac.menu.UploadSpeed.115200=115200 +yb_esp32s3_dac.menu.UploadSpeed.115200.upload.speed=115200 +yb_esp32s3_dac.menu.UploadSpeed.256000.windows=256000 +yb_esp32s3_dac.menu.UploadSpeed.256000.upload.speed=256000 +yb_esp32s3_dac.menu.UploadSpeed.230400.windows.upload.speed=256000 +yb_esp32s3_dac.menu.UploadSpeed.230400=230400 +yb_esp32s3_dac.menu.UploadSpeed.230400.upload.speed=230400 +yb_esp32s3_dac.menu.UploadSpeed.460800.linux=460800 +yb_esp32s3_dac.menu.UploadSpeed.460800.macosx=460800 +yb_esp32s3_dac.menu.UploadSpeed.460800.upload.speed=460800 +yb_esp32s3_dac.menu.UploadSpeed.512000.windows=512000 +yb_esp32s3_dac.menu.UploadSpeed.512000.upload.speed=512000 + +yb_esp32s3_dac.menu.DebugLevel.none=None +yb_esp32s3_dac.menu.DebugLevel.none.build.code_debug=0 +yb_esp32s3_dac.menu.DebugLevel.error=Error +yb_esp32s3_dac.menu.DebugLevel.error.build.code_debug=1 +yb_esp32s3_dac.menu.DebugLevel.warn=Warn +yb_esp32s3_dac.menu.DebugLevel.warn.build.code_debug=2 +yb_esp32s3_dac.menu.DebugLevel.info=Info +yb_esp32s3_dac.menu.DebugLevel.info.build.code_debug=3 +yb_esp32s3_dac.menu.DebugLevel.debug=Debug +yb_esp32s3_dac.menu.DebugLevel.debug.build.code_debug=4 +yb_esp32s3_dac.menu.DebugLevel.verbose=Verbose +yb_esp32s3_dac.menu.DebugLevel.verbose.build.code_debug=5 + +yb_esp32s3_dac.menu.EraseFlash.none=Disabled +yb_esp32s3_dac.menu.EraseFlash.none.upload.erase_cmd= +yb_esp32s3_dac.menu.EraseFlash.all=Enabled +yb_esp32s3_dac.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Huidu HD-WF2 - esp32-s3 HUB75 driver board +# https://www.hdwell.com/Product/index46.html + +huidu_hd_wf2.name=Huidu HD-WF2 + +huidu_hd_wf2.bootloader.tool=esptool_py +huidu_hd_wf2.bootloader.tool.default=esptool_py + +huidu_hd_wf2.upload.tool=esptool_py +huidu_hd_wf2.upload.tool.default=esptool_py +huidu_hd_wf2.upload.tool.network=esp_ota + +huidu_hd_wf2.upload.maximum_size=1310720 +huidu_hd_wf2.upload.maximum_data_size=327680 +huidu_hd_wf2.upload.flags= +huidu_hd_wf2.upload.extra_flags= +huidu_hd_wf2.upload.use_1200bps_touch=true +huidu_hd_wf2.upload.wait_for_upload_port=true + +huidu_hd_wf2.serial.disableDTR=false +huidu_hd_wf2.serial.disableRTS=false + +huidu_hd_wf2.build.tarch=xtensa +huidu_hd_wf2.build.bootloader_addr=0x0 +huidu_hd_wf2.build.target=esp32s3 +huidu_hd_wf2.build.mcu=esp32s3 +huidu_hd_wf2.build.core=esp32 +huidu_hd_wf2.build.variant=huidu_hd_wf2 +huidu_hd_wf2.build.board=HUIDU_HD_WF2 + +huidu_hd_wf2.build.usb_mode=0 +huidu_hd_wf2.build.cdc_on_boot=1 +huidu_hd_wf2.build.msc_on_boot=0 +huidu_hd_wf2.build.dfu_on_boot=0 +huidu_hd_wf2.build.f_cpu=240000000L +huidu_hd_wf2.build.flash_size=8MB +huidu_hd_wf2.build.flash_freq=80m +huidu_hd_wf2.build.flash_mode=qio +huidu_hd_wf2.build.boot=qio +huidu_hd_wf2.build.partitions=default +huidu_hd_wf2.build.defines= +huidu_hd_wf2.build.loop_core= +huidu_hd_wf2.build.event_core= +huidu_hd_wf2.build.flash_type=qio +huidu_hd_wf2.build.psram_type=qspi +huidu_hd_wf2.build.memory_type={build.flash_type}_{build.psram_type} + +huidu_hd_wf2.menu.FlashSize.8M=8MB (64Mb) +huidu_hd_wf2.menu.FlashSize.8M.build.flash_size=8MB + +huidu_hd_wf2.menu.LoopCore.1=Core 1 +huidu_hd_wf2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +huidu_hd_wf2.menu.LoopCore.0=Core 0 +huidu_hd_wf2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +huidu_hd_wf2.menu.EventsCore.1=Core 1 +huidu_hd_wf2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +huidu_hd_wf2.menu.EventsCore.0=Core 0 +huidu_hd_wf2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +huidu_hd_wf2.menu.USBMode.hwcdc=Hardware CDC and JTAG +huidu_hd_wf2.menu.USBMode.hwcdc.build.usb_mode=1 +huidu_hd_wf2.menu.USBMode.default=USB-OTG (TinyUSB) +huidu_hd_wf2.menu.USBMode.default.build.usb_mode=0 + +huidu_hd_wf2.menu.CDCOnBoot.default=Enabled +huidu_hd_wf2.menu.CDCOnBoot.default.build.cdc_on_boot=1 +huidu_hd_wf2.menu.CDCOnBoot.cdc=Disabled +huidu_hd_wf2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +huidu_hd_wf2.menu.MSCOnBoot.default=Disabled +huidu_hd_wf2.menu.MSCOnBoot.default.build.msc_on_boot=0 +huidu_hd_wf2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +huidu_hd_wf2.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +huidu_hd_wf2.menu.DFUOnBoot.default=Disabled +huidu_hd_wf2.menu.DFUOnBoot.default.build.dfu_on_boot=0 +huidu_hd_wf2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +huidu_hd_wf2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +huidu_hd_wf2.menu.UploadMode.default=UART0 / Hardware CDC +huidu_hd_wf2.menu.UploadMode.default.upload.use_1200bps_touch=false +huidu_hd_wf2.menu.UploadMode.default.upload.wait_for_upload_port=false +huidu_hd_wf2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +huidu_hd_wf2.menu.UploadMode.cdc.upload.use_1200bps_touch=true +huidu_hd_wf2.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +huidu_hd_wf2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +huidu_hd_wf2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +huidu_hd_wf2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.3MB APP/5.5MiB SPIFFS) +huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB +huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720 +huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB=8MiB fatfs (3MB APP/1.5MB FATFS) +huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB +huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336 + +huidu_hd_wf2.menu.CPUFreq.240=240MHz (WiFi) +huidu_hd_wf2.menu.CPUFreq.240.build.f_cpu=240000000L +huidu_hd_wf2.menu.CPUFreq.160=160MHz (WiFi) +huidu_hd_wf2.menu.CPUFreq.160.build.f_cpu=160000000L +huidu_hd_wf2.menu.CPUFreq.80=80MHz (WiFi) +huidu_hd_wf2.menu.CPUFreq.80.build.f_cpu=80000000L +huidu_hd_wf2.menu.CPUFreq.40=40MHz +huidu_hd_wf2.menu.CPUFreq.40.build.f_cpu=40000000L + +huidu_hd_wf2.menu.FlashMode.dio=DIO 80MHz +huidu_hd_wf2.menu.FlashMode.dio.build.flash_mode=dio +huidu_hd_wf2.menu.FlashMode.dio.build.boot=dio +huidu_hd_wf2.menu.FlashMode.dio.build.boot_freq=80m +huidu_hd_wf2.menu.FlashMode.dio.build.flash_freq=80m + +huidu_hd_wf2.menu.UploadSpeed.921600=921600 +huidu_hd_wf2.menu.UploadSpeed.921600.upload.speed=921600 +huidu_hd_wf2.menu.UploadSpeed.115200=115200 +huidu_hd_wf2.menu.UploadSpeed.115200.upload.speed=115200 +huidu_hd_wf2.menu.UploadSpeed.460800.linux=460800 +huidu_hd_wf2.menu.UploadSpeed.460800.macosx=460800 +huidu_hd_wf2.menu.UploadSpeed.460800.upload.speed=460800 + +huidu_hd_wf2.menu.DebugLevel.none=None +huidu_hd_wf2.menu.DebugLevel.none.build.code_debug=0 +huidu_hd_wf2.menu.DebugLevel.error=Error +huidu_hd_wf2.menu.DebugLevel.error.build.code_debug=1 +huidu_hd_wf2.menu.DebugLevel.warn=Warn +huidu_hd_wf2.menu.DebugLevel.warn.build.code_debug=2 +huidu_hd_wf2.menu.DebugLevel.info=Info +huidu_hd_wf2.menu.DebugLevel.info.build.code_debug=3 +huidu_hd_wf2.menu.DebugLevel.debug=Debug +huidu_hd_wf2.menu.DebugLevel.debug.build.code_debug=4 +huidu_hd_wf2.menu.DebugLevel.verbose=Verbose +huidu_hd_wf2.menu.DebugLevel.verbose.build.code_debug=5 + +huidu_hd_wf2.menu.EraseFlash.none=Disabled +huidu_hd_wf2.menu.EraseFlash.none.upload.erase_cmd= +huidu_hd_wf2.menu.EraseFlash.all=Enabled +huidu_hd_wf2.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# Huidu HD-WF4 - esp32-s3 HUB75 driver board +# https://www.hdwell.com/Product/index46.html + +huidu_hd_wf4.name=Huidu HD-WF4 + +huidu_hd_wf4.bootloader.tool=esptool_py +huidu_hd_wf4.bootloader.tool.default=esptool_py + +huidu_hd_wf4.upload.tool=esptool_py +huidu_hd_wf4.upload.tool.default=esptool_py +huidu_hd_wf4.upload.tool.network=esp_ota + +huidu_hd_wf4.upload.maximum_size=1310720 +huidu_hd_wf4.upload.maximum_data_size=327680 +huidu_hd_wf4.upload.flags= +huidu_hd_wf4.upload.extra_flags= +huidu_hd_wf4.upload.use_1200bps_touch=true +huidu_hd_wf4.upload.wait_for_upload_port=true + +huidu_hd_wf4.serial.disableDTR=false +huidu_hd_wf4.serial.disableRTS=false + +huidu_hd_wf4.build.tarch=xtensa +huidu_hd_wf4.build.bootloader_addr=0x0 +huidu_hd_wf4.build.target=esp32s3 +huidu_hd_wf4.build.mcu=esp32s3 +huidu_hd_wf4.build.core=esp32 +huidu_hd_wf4.build.variant=huidu_hd_wf4 +huidu_hd_wf4.build.board=HUIDU_HD_WF4 + +huidu_hd_wf4.build.usb_mode=0 +huidu_hd_wf4.build.cdc_on_boot=1 +huidu_hd_wf4.build.msc_on_boot=0 +huidu_hd_wf4.build.dfu_on_boot=0 +huidu_hd_wf4.build.f_cpu=240000000L +huidu_hd_wf4.build.flash_size=8MB +huidu_hd_wf4.build.flash_freq=80m +huidu_hd_wf4.build.flash_mode=qio +huidu_hd_wf4.build.boot=qio +huidu_hd_wf4.build.partitions=default +huidu_hd_wf4.build.defines= +huidu_hd_wf4.build.loop_core= +huidu_hd_wf4.build.event_core= +huidu_hd_wf4.build.flash_type=qio +huidu_hd_wf4.build.psram_type=qspi +huidu_hd_wf4.build.memory_type={build.flash_type}_{build.psram_type} + +huidu_hd_wf4.menu.FlashSize.8M=8MB (64Mb) +huidu_hd_wf4.menu.FlashSize.8M.build.flash_size=8MB + +huidu_hd_wf4.menu.LoopCore.1=Core 1 +huidu_hd_wf4.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +huidu_hd_wf4.menu.LoopCore.0=Core 0 +huidu_hd_wf4.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +huidu_hd_wf4.menu.EventsCore.1=Core 1 +huidu_hd_wf4.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +huidu_hd_wf4.menu.EventsCore.0=Core 0 +huidu_hd_wf4.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +huidu_hd_wf4.menu.USBMode.hwcdc=Hardware CDC and JTAG +huidu_hd_wf4.menu.USBMode.hwcdc.build.usb_mode=1 +huidu_hd_wf4.menu.USBMode.default=USB-OTG (TinyUSB) +huidu_hd_wf4.menu.USBMode.default.build.usb_mode=0 + +huidu_hd_wf4.menu.CDCOnBoot.default=Enabled +huidu_hd_wf4.menu.CDCOnBoot.default.build.cdc_on_boot=1 +huidu_hd_wf4.menu.CDCOnBoot.cdc=Disabled +huidu_hd_wf4.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +huidu_hd_wf4.menu.MSCOnBoot.default=Disabled +huidu_hd_wf4.menu.MSCOnBoot.default.build.msc_on_boot=0 +huidu_hd_wf4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +huidu_hd_wf4.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +huidu_hd_wf4.menu.DFUOnBoot.default=Disabled +huidu_hd_wf4.menu.DFUOnBoot.default.build.dfu_on_boot=0 +huidu_hd_wf4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +huidu_hd_wf4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +huidu_hd_wf4.menu.UploadMode.default=UART0 / Hardware CDC +huidu_hd_wf4.menu.UploadMode.default.upload.use_1200bps_touch=false +huidu_hd_wf4.menu.UploadMode.default.upload.wait_for_upload_port=false +huidu_hd_wf4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +huidu_hd_wf4.menu.UploadMode.cdc.upload.use_1200bps_touch=true +huidu_hd_wf4.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +huidu_hd_wf4.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +huidu_hd_wf4.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +huidu_hd_wf4.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.3MB APP/5.5MiB SPIFFS) +huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB +huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720 +huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB=8MiB fatfs (3MB APP/1.5MB FATFS) +huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB +huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336 + +huidu_hd_wf4.menu.CPUFreq.240=240MHz (WiFi) +huidu_hd_wf4.menu.CPUFreq.240.build.f_cpu=240000000L +huidu_hd_wf4.menu.CPUFreq.160=160MHz (WiFi) +huidu_hd_wf4.menu.CPUFreq.160.build.f_cpu=160000000L +huidu_hd_wf4.menu.CPUFreq.80=80MHz (WiFi) +huidu_hd_wf4.menu.CPUFreq.80.build.f_cpu=80000000L +huidu_hd_wf4.menu.CPUFreq.40=40MHz +huidu_hd_wf4.menu.CPUFreq.40.build.f_cpu=40000000L + +huidu_hd_wf4.menu.FlashMode.dio=DIO 80MHz +huidu_hd_wf4.menu.FlashMode.dio.build.flash_mode=dio +huidu_hd_wf4.menu.FlashMode.dio.build.boot=dio +huidu_hd_wf4.menu.FlashMode.dio.build.boot_freq=80m +huidu_hd_wf4.menu.FlashMode.dio.build.flash_freq=80m + +huidu_hd_wf4.menu.UploadSpeed.921600=921600 +huidu_hd_wf4.menu.UploadSpeed.921600.upload.speed=921600 +huidu_hd_wf4.menu.UploadSpeed.115200=115200 +huidu_hd_wf4.menu.UploadSpeed.115200.upload.speed=115200 +huidu_hd_wf4.menu.UploadSpeed.460800.linux=460800 +huidu_hd_wf4.menu.UploadSpeed.460800.macosx=460800 +huidu_hd_wf4.menu.UploadSpeed.460800.upload.speed=460800 + +huidu_hd_wf4.menu.DebugLevel.none=None +huidu_hd_wf4.menu.DebugLevel.none.build.code_debug=0 +huidu_hd_wf4.menu.DebugLevel.error=Error +huidu_hd_wf4.menu.DebugLevel.error.build.code_debug=1 +huidu_hd_wf4.menu.DebugLevel.warn=Warn +huidu_hd_wf4.menu.DebugLevel.warn.build.code_debug=2 +huidu_hd_wf4.menu.DebugLevel.info=Info +huidu_hd_wf4.menu.DebugLevel.info.build.code_debug=3 +huidu_hd_wf4.menu.DebugLevel.debug=Debug +huidu_hd_wf4.menu.DebugLevel.debug.build.code_debug=4 +huidu_hd_wf4.menu.DebugLevel.verbose=Verbose +huidu_hd_wf4.menu.DebugLevel.verbose.build.code_debug=5 + +huidu_hd_wf4.menu.EraseFlash.none=Disabled +huidu_hd_wf4.menu.EraseFlash.none.upload.erase_cmd= +huidu_hd_wf4.menu.EraseFlash.all=Enabled +huidu_hd_wf4.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + +# CYOBot (CYOBrain V2 ESP32S3) Board +cyobot_v2_esp32s3.name=CYOBOT V2 ESP32S3 + +cyobot_v2_esp32s3.bootloader.tool=esptool_py +cyobot_v2_esp32s3.bootloader.tool.default=esptool_py + +cyobot_v2_esp32s3.upload.tool=esptool_py +cyobot_v2_esp32s3.upload.tool.default=esptool_py +cyobot_v2_esp32s3.upload.tool.network=esp_ota + +cyobot_v2_esp32s3.upload.maximum_size=1310720 +cyobot_v2_esp32s3.upload.maximum_data_size=327680 +cyobot_v2_esp32s3.upload.flags= +cyobot_v2_esp32s3.upload.extra_flags= +cyobot_v2_esp32s3.upload.use_1200bps_touch=false +cyobot_v2_esp32s3.upload.wait_for_upload_port=false + +cyobot_v2_esp32s3.serial.disableDTR=false +cyobot_v2_esp32s3.serial.disableRTS=false + +cyobot_v2_esp32s3.build.tarch=xtensa +cyobot_v2_esp32s3.build.bootloader_addr=0x0 +cyobot_v2_esp32s3.build.target=esp32s3 +cyobot_v2_esp32s3.build.mcu=esp32s3 +cyobot_v2_esp32s3.build.core=esp32 +cyobot_v2_esp32s3.build.variant=cyobot_v2_esp32s3 +cyobot_v2_esp32s3.build.board=CYOBOT_V2_ESP32S3 + +cyobot_v2_esp32s3.build.usb_mode=1 +cyobot_v2_esp32s3.build.cdc_on_boot=0 +cyobot_v2_esp32s3.build.msc_on_boot=0 +cyobot_v2_esp32s3.build.dfu_on_boot=0 +cyobot_v2_esp32s3.build.f_cpu=240000000L +cyobot_v2_esp32s3.build.flash_size=4MB +cyobot_v2_esp32s3.build.flash_freq=80m +cyobot_v2_esp32s3.build.flash_mode=dio +cyobot_v2_esp32s3.build.boot=qio +cyobot_v2_esp32s3.build.boot_freq=80m +cyobot_v2_esp32s3.build.partitions=default +cyobot_v2_esp32s3.build.defines= +cyobot_v2_esp32s3.build.loop_core= +cyobot_v2_esp32s3.build.event_core= +cyobot_v2_esp32s3.build.psram_type=qspi +cyobot_v2_esp32s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +cyobot_v2_esp32s3.menu.JTAGAdapter.default=Disabled +cyobot_v2_esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +cyobot_v2_esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +cyobot_v2_esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=cyobot_v2_esp32s3-builtin.cfg +cyobot_v2_esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +cyobot_v2_esp32s3.menu.JTAGAdapter.external=FTDI Adapter +cyobot_v2_esp32s3.menu.JTAGAdapter.external.build.openocdscript=cyobot_v2_esp32s3-ftdi.cfg +cyobot_v2_esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +cyobot_v2_esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge +cyobot_v2_esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=cyobot_v2_esp32s3-bridge.cfg +cyobot_v2_esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +cyobot_v2_esp32s3.menu.PSRAM.disabled=Disabled +cyobot_v2_esp32s3.menu.PSRAM.disabled.build.defines= +cyobot_v2_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi +cyobot_v2_esp32s3.menu.PSRAM.enabled=QSPI PSRAM +cyobot_v2_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +cyobot_v2_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi +cyobot_v2_esp32s3.menu.PSRAM.opi=OPI PSRAM +cyobot_v2_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +cyobot_v2_esp32s3.menu.PSRAM.opi.build.psram_type=opi + +cyobot_v2_esp32s3.menu.FlashMode.qio=QIO 80MHz +cyobot_v2_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +cyobot_v2_esp32s3.menu.FlashMode.qio.build.boot=qio +cyobot_v2_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.qio120=QIO 120MHz +cyobot_v2_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +cyobot_v2_esp32s3.menu.FlashMode.qio120.build.boot=qio +cyobot_v2_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +cyobot_v2_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.dio=DIO 80MHz +cyobot_v2_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +cyobot_v2_esp32s3.menu.FlashMode.dio.build.boot=dio +cyobot_v2_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.opi=OPI 80MHz +cyobot_v2_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +cyobot_v2_esp32s3.menu.FlashMode.opi.build.boot=opi +cyobot_v2_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +cyobot_v2_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +cyobot_v2_esp32s3.menu.FlashSize.4M=4MB (32Mb) +cyobot_v2_esp32s3.menu.FlashSize.4M.build.flash_size=4MB +cyobot_v2_esp32s3.menu.FlashSize.8M=8MB (64Mb) +cyobot_v2_esp32s3.menu.FlashSize.8M.build.flash_size=8MB +cyobot_v2_esp32s3.menu.FlashSize.16M=16MB (128Mb) +cyobot_v2_esp32s3.menu.FlashSize.16M.build.flash_size=16MB +cyobot_v2_esp32s3.menu.FlashSize.32M=32MB (256Mb) +cyobot_v2_esp32s3.menu.FlashSize.32M.build.flash_size=32MB + +cyobot_v2_esp32s3.menu.LoopCore.1=Core 1 +cyobot_v2_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +cyobot_v2_esp32s3.menu.LoopCore.0=Core 0 +cyobot_v2_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +cyobot_v2_esp32s3.menu.EventsCore.1=Core 1 +cyobot_v2_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +cyobot_v2_esp32s3.menu.EventsCore.0=Core 0 +cyobot_v2_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +cyobot_v2_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +cyobot_v2_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +cyobot_v2_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +cyobot_v2_esp32s3.menu.USBMode.default.build.usb_mode=0 + +cyobot_v2_esp32s3.menu.CDCOnBoot.default=Disabled +cyobot_v2_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +cyobot_v2_esp32s3.menu.CDCOnBoot.cdc=Enabled +cyobot_v2_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +cyobot_v2_esp32s3.menu.MSCOnBoot.default=Disabled +cyobot_v2_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +cyobot_v2_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +cyobot_v2_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +cyobot_v2_esp32s3.menu.DFUOnBoot.default=Disabled +cyobot_v2_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +cyobot_v2_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +cyobot_v2_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +cyobot_v2_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +cyobot_v2_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +cyobot_v2_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +cyobot_v2_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +cyobot_v2_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +cyobot_v2_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +cyobot_v2_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.default.build.partitions=default +cyobot_v2_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +cyobot_v2_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +cyobot_v2_esp32s3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +cyobot_v2_esp32s3.menu.PartitionScheme.no_fs.build.partitions=no_fs +cyobot_v2_esp32s3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +cyobot_v2_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +cyobot_v2_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +cyobot_v2_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +cyobot_v2_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +cyobot_v2_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat +cyobot_v2_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +cyobot_v2_esp32s3.menu.PartitionScheme.custom=Custom +cyobot_v2_esp32s3.menu.PartitionScheme.custom.build.partitions= +cyobot_v2_esp32s3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +cyobot_v2_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +cyobot_v2_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +cyobot_v2_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +cyobot_v2_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +cyobot_v2_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +cyobot_v2_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +cyobot_v2_esp32s3.menu.CPUFreq.40=40MHz +cyobot_v2_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +cyobot_v2_esp32s3.menu.CPUFreq.20=20MHz +cyobot_v2_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +cyobot_v2_esp32s3.menu.CPUFreq.10=10MHz +cyobot_v2_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +cyobot_v2_esp32s3.menu.UploadSpeed.921600=921600 +cyobot_v2_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +cyobot_v2_esp32s3.menu.UploadSpeed.115200=115200 +cyobot_v2_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +cyobot_v2_esp32s3.menu.UploadSpeed.256000.windows=256000 +cyobot_v2_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +cyobot_v2_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +cyobot_v2_esp32s3.menu.UploadSpeed.230400=230400 +cyobot_v2_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +cyobot_v2_esp32s3.menu.UploadSpeed.460800.linux=460800 +cyobot_v2_esp32s3.menu.UploadSpeed.460800.macosx=460800 +cyobot_v2_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +cyobot_v2_esp32s3.menu.UploadSpeed.512000.windows=512000 +cyobot_v2_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +cyobot_v2_esp32s3.menu.DebugLevel.none=None +cyobot_v2_esp32s3.menu.DebugLevel.none.build.code_debug=0 +cyobot_v2_esp32s3.menu.DebugLevel.error=Error +cyobot_v2_esp32s3.menu.DebugLevel.error.build.code_debug=1 +cyobot_v2_esp32s3.menu.DebugLevel.warn=Warn +cyobot_v2_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +cyobot_v2_esp32s3.menu.DebugLevel.info=Info +cyobot_v2_esp32s3.menu.DebugLevel.info.build.code_debug=3 +cyobot_v2_esp32s3.menu.DebugLevel.debug=Debug +cyobot_v2_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +cyobot_v2_esp32s3.menu.DebugLevel.verbose=Verbose +cyobot_v2_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +cyobot_v2_esp32s3.menu.EraseFlash.none=Disabled +cyobot_v2_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +cyobot_v2_esp32s3.menu.EraseFlash.all=Enabled +cyobot_v2_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +cyobot_v2_esp32s3.menu.ZigbeeMode.default=Disabled +cyobot_v2_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +cyobot_v2_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +cyobot_v2_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +rakwireless_rak3112.name=RAKwireless RAK3112 + +rakwireless_rak3112.upload.tool=esptool_py +rakwireless_rak3112.upload.tool.default=esptool_py +rakwireless_rak3112.upload.tool.network=esp_ota +rakwireless_rak3112.upload.maximum_size=1310720 +rakwireless_rak3112.upload.maximum_data_size=327680 +rakwireless_rak3112.upload.wait_for_upload_port=false +rakwireless_rak3112.upload.speed=460800 +rakwireless_rak3112.upload.flags= +rakwireless_rak3112.upload.extra_flags= + +rakwireless_rak3112.bootloader.tool=esptool_py +rakwireless_rak3112.bootloader.tool.default=esptool_py + +rakwireless_rak3112.serial.disableDTR=true +rakwireless_rak3112.serial.disableRTS=true + +rakwireless_rak3112.build.tarch=xtensa +rakwireless_rak3112.build.bootloader_addr=0x0 +rakwireless_rak3112.build.mcu=esp32s3 +rakwireless_rak3112.build.core=esp32 +rakwireless_rak3112.build.target=esp32s3 +rakwireless_rak3112.build.variant=rakwireless_rak3112 +rakwireless_rak3112.build.board=RAKWIRELESS_RAK3112 + +rakwireless_rak3112.build.usb_mode=1 +rakwireless_rak3112.build.cdc_on_boot=1 +rakwireless_rak3112.build.msc_on_boot=0 +rakwireless_rak3112.build.dfu_on_boot=0 + +rakwireless_rak3112.build.f_cpu=240000000L +rakwireless_rak3112.build.flash_size=16MB +rakwireless_rak3112.build.flash_freq=80m +rakwireless_rak3112.build.flash_mode=qio +rakwireless_rak3112.build.boot=qio +rakwireless_rak3112.build.partitions=default +rakwireless_rak3112.build.defines= +rakwireless_rak3112.build.psram_type=opi +rakwireless_rak3112.build.memory_type={build.boot}_{build.psram_type} + +rakwireless_rak3112.menu.PSRAM.enabled=Enabled +rakwireless_rak3112.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +rakwireless_rak3112.menu.PSRAM.enabled.build.psram_type=opi +rakwireless_rak3112.menu.PSRAM.disabled=Disabled +rakwireless_rak3112.menu.PSRAM.disabled.build.defines= + +rakwireless_rak3112.menu.LoopCore.1=Core 1 +rakwireless_rak3112.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +rakwireless_rak3112.menu.LoopCore.0=Core 0 +rakwireless_rak3112.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +rakwireless_rak3112.menu.EventsCore.1=Core 1 +rakwireless_rak3112.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +rakwireless_rak3112.menu.EventsCore.0=Core 0 +rakwireless_rak3112.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +rakwireless_rak3112.menu.USBMode.hwcdc=Hardware CDC and JTAG +rakwireless_rak3112.menu.USBMode.hwcdc.build.usb_mode=1 +rakwireless_rak3112.menu.USBMode.default=USB-OTG (TinyUSB) +rakwireless_rak3112.menu.USBMode.default.build.usb_mode=0 + +rakwireless_rak3112.menu.CDCOnBoot.default=Enabled +rakwireless_rak3112.menu.CDCOnBoot.default.build.cdc_on_boot=1 +rakwireless_rak3112.menu.CDCOnBoot.cdc=Disabled +rakwireless_rak3112.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +rakwireless_rak3112.menu.MSCOnBoot.default=Disabled +rakwireless_rak3112.menu.MSCOnBoot.default.build.msc_on_boot=0 +rakwireless_rak3112.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +rakwireless_rak3112.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +rakwireless_rak3112.menu.DFUOnBoot.default=Disabled +rakwireless_rak3112.menu.DFUOnBoot.default.build.dfu_on_boot=0 +rakwireless_rak3112.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +rakwireless_rak3112.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +rakwireless_rak3112.menu.UploadMode.default=UART0 / Hardware CDC +rakwireless_rak3112.menu.UploadMode.default.upload.use_1200bps_touch=false +rakwireless_rak3112.menu.UploadMode.default.upload.wait_for_upload_port=false +rakwireless_rak3112.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +rakwireless_rak3112.menu.UploadMode.cdc.upload.use_1200bps_touch=true +rakwireless_rak3112.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +rakwireless_rak3112.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +rakwireless_rak3112.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +rakwireless_rak3112.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +rakwireless_rak3112.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS) +rakwireless_rak3112.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +rakwireless_rak3112.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +rakwireless_rak3112.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FATFS) +rakwireless_rak3112.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +rakwireless_rak3112.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-16MB +rakwireless_rak3112.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152 +rakwireless_rak3112.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +rakwireless_rak3112.menu.PartitionScheme.tinyuf2_noota=TinyUF2 16MB No OTA(4MB APP/11.6MB FATFS) +rakwireless_rak3112.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +rakwireless_rak3112.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-16MB-noota +rakwireless_rak3112.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304 +rakwireless_rak3112.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +rakwireless_rak3112.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +rakwireless_rak3112.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +rakwireless_rak3112.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +rakwireless_rak3112.menu.PartitionScheme.custom=Custom +rakwireless_rak3112.menu.PartitionScheme.custom.build.partitions= +rakwireless_rak3112.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +rakwireless_rak3112.menu.CPUFreq.240=240MHz (WiFi/BT) +rakwireless_rak3112.menu.CPUFreq.240.build.f_cpu=240000000L +rakwireless_rak3112.menu.CPUFreq.160=160MHz (WiFi/BT) +rakwireless_rak3112.menu.CPUFreq.160.build.f_cpu=160000000L +rakwireless_rak3112.menu.CPUFreq.80=80MHz (WiFi/BT) +rakwireless_rak3112.menu.CPUFreq.80.build.f_cpu=80000000L + +rakwireless_rak3112.menu.FlashMode.qio=QIO +rakwireless_rak3112.menu.FlashMode.qio.build.flash_mode=dio +rakwireless_rak3112.menu.FlashMode.qio.build.boot=qio +rakwireless_rak3112.menu.FlashMode.dio=DIO +rakwireless_rak3112.menu.FlashMode.dio.build.flash_mode=dio +rakwireless_rak3112.menu.FlashMode.dio.build.boot=dio + +rakwireless_rak3112.menu.FlashFreq.80=80MHz +rakwireless_rak3112.menu.FlashFreq.80.build.flash_freq=80m +rakwireless_rak3112.menu.FlashFreq.40=40MHz +rakwireless_rak3112.menu.FlashFreq.40.build.flash_freq=40m + +rakwireless_rak3112.menu.UploadSpeed.921600=921600 +rakwireless_rak3112.menu.UploadSpeed.921600.upload.speed=921600 +rakwireless_rak3112.menu.UploadSpeed.115200=115200 +rakwireless_rak3112.menu.UploadSpeed.115200.upload.speed=115200 +rakwireless_rak3112.menu.UploadSpeed.256000.windows=256000 +rakwireless_rak3112.menu.UploadSpeed.256000.upload.speed=256000 +rakwireless_rak3112.menu.UploadSpeed.230400.windows.upload.speed=256000 +rakwireless_rak3112.menu.UploadSpeed.230400=230400 +rakwireless_rak3112.menu.UploadSpeed.230400.upload.speed=230400 +rakwireless_rak3112.menu.UploadSpeed.460800.linux=460800 +rakwireless_rak3112.menu.UploadSpeed.460800.macosx=460800 +rakwireless_rak3112.menu.UploadSpeed.460800.upload.speed=460800 +rakwireless_rak3112.menu.UploadSpeed.512000.windows=512000 +rakwireless_rak3112.menu.UploadSpeed.512000.upload.speed=512000 + +rakwireless_rak3112.menu.DebugLevel.none=None +rakwireless_rak3112.menu.DebugLevel.none.build.code_debug=0 +rakwireless_rak3112.menu.DebugLevel.error=Error +rakwireless_rak3112.menu.DebugLevel.error.build.code_debug=1 +rakwireless_rak3112.menu.DebugLevel.warn=Warn +rakwireless_rak3112.menu.DebugLevel.warn.build.code_debug=2 +rakwireless_rak3112.menu.DebugLevel.info=Info +rakwireless_rak3112.menu.DebugLevel.info.build.code_debug=3 +rakwireless_rak3112.menu.DebugLevel.debug=Debug +rakwireless_rak3112.menu.DebugLevel.debug.build.code_debug=4 +rakwireless_rak3112.menu.DebugLevel.verbose=Verbose +rakwireless_rak3112.menu.DebugLevel.verbose.build.code_debug=5 + +rakwireless_rak3112.menu.EraseFlash.none=Disabled +rakwireless_rak3112.menu.EraseFlash.none.upload.erase_cmd= +rakwireless_rak3112.menu.EraseFlash.all=Enabled +rakwireless_rak3112.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +kodedot.name=kode dot + +kodedot.bootloader.tool=esptool_py +kodedot.bootloader.tool.default=esptool_py + +kodedot.upload.tool=esptool_py_app_only +kodedot.upload.tool.default=esptool_py_app_only +kodedot.upload.tool.network=esp_ota + +kodedot.upload.maximum_size=8388608 +kodedot.upload.maximum_data_size=327680 +kodedot.upload.flags= +kodedot.upload.extra_flags= +kodedot.upload.use_1200bps_touch=false +kodedot.upload.wait_for_upload_port=false +kodedot.upload.speed=921600 + +kodedot.upload.erase_cmd= + +kodedot.serial.disableDTR=false +kodedot.serial.disableRTS=false + +kodedot.build.tarch=xtensa +kodedot.build.bootloader_addr=0x0 +kodedot.build.target=esp32s3 +kodedot.build.mcu=esp32s3 +kodedot.build.core=esp32 +kodedot.build.variant=kodedot +kodedot.build.board=KODE_DOT + +kodedot.build.usb_mode=1 +kodedot.build.cdc_on_boot=1 +kodedot.build.msc_on_boot=0 +kodedot.build.dfu_on_boot=0 + +kodedot.build.f_cpu=240000000L + +kodedot.build.flash_offset=0x400000 +kodedot.build.flash_size=32MB +kodedot.build.flash_freq=80m +kodedot.build.flash_mode=dio +kodedot.build.psram_type=opi + +kodedot.build.custom_partitions=kodedot_partitions + +kodedot.build.defines= + +kodedot.build.loop_core=-DARDUINO_RUNNING_CORE=1 +kodedot.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 + +kodedot.recipe.hooks.objcopy.postobjcopy.3.pattern= +kodedot.recipe.hooks.objcopy.postobjcopy.3.pattern_args= + +kodedot.recipe.output.save_file={build.project_name}.ino.bin + +kodedot.menu.DebugLevel.none=None +kodedot.menu.DebugLevel.none.build.code_debug=0 +kodedot.menu.DebugLevel.error=Error +kodedot.menu.DebugLevel.error.build.code_debug=1 +kodedot.menu.DebugLevel.warn=Warn +kodedot.menu.DebugLevel.warn.build.code_debug=2 +kodedot.menu.DebugLevel.info=Info +kodedot.menu.DebugLevel.info.build.code_debug=3 +kodedot.menu.DebugLevel.debug=Debug +kodedot.menu.DebugLevel.debug.build.code_debug=4 +kodedot.menu.DebugLevel.verbose=Verbose +kodedot.menu.DebugLevel.verbose.build.code_debug=5 + +############################################################## + +# FED4 Board +fed4.name=FED4 +fed4.vid.0=0x303A +fed4.pid.0=0x82E5 +fed4.upload_port.0.vid=0x303A +fed4.upload_port.0.pid=0x82E5 +fed4.bootloader.tool=esptool_py +fed4.bootloader.tool.default=esptool_py + +fed4.upload.tool=esptool_py +fed4.upload.tool.default=esptool_py +fed4.upload.tool.network=esp_ota + +fed4.upload.maximum_size=1310720 +fed4.upload.maximum_data_size=327680 +fed4.upload.flags= +fed4.upload.extra_flags= +fed4.upload.use_1200bps_touch=false +fed4.upload.wait_for_upload_port=false + +fed4.serial.disableDTR=false +fed4.serial.disableRTS=false + +fed4.build.tarch=xtensa +fed4.build.bootloader_addr=0x0 +fed4.build.target=esp32s3 +fed4.build.mcu=esp32s3 +fed4.build.core=esp32 +fed4.build.variant=fed4 +fed4.build.board=FED4 + +fed4.build.usb_mode=1 +fed4.build.cdc_on_boot=0 +fed4.build.msc_on_boot=0 +fed4.build.dfu_on_boot=0 +fed4.build.f_cpu=240000000L +fed4.build.flash_size=16MB +fed4.build.flash_freq=80m +fed4.build.flash_mode=dio +fed4.build.boot=qio +fed4.build.boot_freq=80m +fed4.build.partitions=default_16MB +fed4.build.defines= +fed4.build.loop_core= +fed4.build.event_core= +fed4.build.psram_type=qspi +fed4.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +fed4.menu.JTAGAdapter.default=Disabled +fed4.menu.JTAGAdapter.default.build.copy_jtag_files=0 +fed4.menu.JTAGAdapter.builtin=Integrated USB JTAG +fed4.menu.JTAGAdapter.builtin.build.openocdscript=fed4-builtin.cfg +fed4.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +fed4.menu.JTAGAdapter.external=FTDI Adapter +fed4.menu.JTAGAdapter.external.build.openocdscript=fed4-ftdi.cfg +fed4.menu.JTAGAdapter.external.build.copy_jtag_files=1 +fed4.menu.JTAGAdapter.bridge=ESP USB Bridge +fed4.menu.JTAGAdapter.bridge.build.openocdscript=fed4-bridge.cfg +fed4.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +fed4.menu.FlashMode.qio=QIO 80MHz +fed4.menu.FlashMode.qio.build.flash_mode=dio +fed4.menu.FlashMode.qio.build.boot=qio +fed4.menu.FlashMode.qio.build.boot_freq=80m +fed4.menu.FlashMode.qio.build.flash_freq=80m +fed4.menu.FlashMode.qio120=QIO 120MHz +fed4.menu.FlashMode.qio120.build.flash_mode=dio +fed4.menu.FlashMode.qio120.build.boot=qio +fed4.menu.FlashMode.qio120.build.boot_freq=120m +fed4.menu.FlashMode.qio120.build.flash_freq=80m +fed4.menu.FlashMode.dio=DIO 80MHz +fed4.menu.FlashMode.dio.build.flash_mode=dio +fed4.menu.FlashMode.dio.build.boot=dio +fed4.menu.FlashMode.dio.build.boot_freq=80m +fed4.menu.FlashMode.dio.build.flash_freq=80m + +fed4.menu.FlashSize.16M=16MB (128Mb) +fed4.menu.FlashSize.16M.build.flash_size=16MB + +fed4.menu.LoopCore.1=Core 1 +fed4.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +fed4.menu.LoopCore.0=Core 0 +fed4.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +fed4.menu.EventsCore.1=Core 1 +fed4.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +fed4.menu.EventsCore.0=Core 0 +fed4.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +fed4.menu.USBMode.hwcdc=Hardware CDC and JTAG +fed4.menu.USBMode.hwcdc.build.usb_mode=1 +fed4.menu.USBMode.default=USB-OTG (TinyUSB) +fed4.menu.USBMode.default.build.usb_mode=0 + +fed4.menu.CDCOnBoot.default=Disabled +fed4.menu.CDCOnBoot.default.build.cdc_on_boot=0 +fed4.menu.CDCOnBoot.cdc=Enabled +fed4.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +fed4.menu.MSCOnBoot.default=Disabled +fed4.menu.MSCOnBoot.default.build.msc_on_boot=0 +fed4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +fed4.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +fed4.menu.DFUOnBoot.default=Disabled +fed4.menu.DFUOnBoot.default.build.dfu_on_boot=0 +fed4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +fed4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +fed4.menu.UploadMode.default=UART0 / Hardware CDC +fed4.menu.UploadMode.default.upload.use_1200bps_touch=false +fed4.menu.UploadMode.default.upload.wait_for_upload_port=false +fed4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +fed4.menu.UploadMode.cdc.upload.use_1200bps_touch=true +fed4.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +fed4.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS) +fed4.menu.PartitionScheme.default_16MB.build.partitions=default_16MB +fed4.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600 +fed4.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS) +fed4.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB +fed4.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592 +fed4.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS) +fed4.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +fed4.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +fed4.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS) +fed4.menu.PartitionScheme.fatflash.build.partitions=ffat +fed4.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 + +fed4.menu.CPUFreq.240=240MHz (WiFi) +fed4.menu.CPUFreq.240.build.f_cpu=240000000L +fed4.menu.CPUFreq.160=160MHz (WiFi) +fed4.menu.CPUFreq.160.build.f_cpu=160000000L +fed4.menu.CPUFreq.80=80MHz (WiFi) +fed4.menu.CPUFreq.80.build.f_cpu=80000000L +fed4.menu.CPUFreq.40=40MHz +fed4.menu.CPUFreq.40.build.f_cpu=40000000L +fed4.menu.CPUFreq.20=20MHz +fed4.menu.CPUFreq.20.build.f_cpu=20000000L +fed4.menu.CPUFreq.10=10MHz +fed4.menu.CPUFreq.10.build.f_cpu=10000000L + +fed4.menu.UploadSpeed.921600=921600 +fed4.menu.UploadSpeed.921600.upload.speed=921600 +fed4.menu.UploadSpeed.115200=115200 +fed4.menu.UploadSpeed.115200.upload.speed=115200 +fed4.menu.UploadSpeed.256000.windows=256000 +fed4.menu.UploadSpeed.256000.upload.speed=256000 +fed4.menu.UploadSpeed.230400.windows.upload.speed=256000 +fed4.menu.UploadSpeed.230400=230400 +fed4.menu.UploadSpeed.230400.upload.speed=230400 +fed4.menu.UploadSpeed.460800.linux=460800 +fed4.menu.UploadSpeed.460800.macosx=460800 +fed4.menu.UploadSpeed.460800.upload.speed=460800 +fed4.menu.UploadSpeed.512000.windows=512000 +fed4.menu.UploadSpeed.512000.upload.speed=512000 + +fed4.menu.DebugLevel.none=None +fed4.menu.DebugLevel.none.build.code_debug=0 +fed4.menu.DebugLevel.error=Error +fed4.menu.DebugLevel.error.build.code_debug=1 +fed4.menu.DebugLevel.warn=Warn +fed4.menu.DebugLevel.warn.build.code_debug=2 +fed4.menu.DebugLevel.info=Info +fed4.menu.DebugLevel.info.build.code_debug=3 +fed4.menu.DebugLevel.debug=Debug +fed4.menu.DebugLevel.debug.build.code_debug=4 +fed4.menu.DebugLevel.verbose=Verbose +fed4.menu.DebugLevel.verbose.build.code_debug=5 + +fed4.menu.EraseFlash.none=Disabled +fed4.menu.EraseFlash.none.upload.erase_cmd= +fed4.menu.EraseFlash.all=Enabled +fed4.menu.EraseFlash.all.upload.erase_cmd=-e + +fed4.menu.ZigbeeMode.default=Disabled +fed4.menu.ZigbeeMode.default.build.zigbee_mode= +fed4.menu.ZigbeeMode.default.build.zigbee_libs= +fed4.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +fed4.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +fed4.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +# FoBE Quill ESP32S3 Mesh FH4R2 + +fobe_quill_esp32s3_mesh.name=FoBE Quill ESP32S3 Mesh +fobe_quill_esp32s3_mesh.vid.0=0x303a +fobe_quill_esp32s3_mesh.pid.0=0x82f4 +fobe_quill_esp32s3_mesh.vid.1=0x303a +fobe_quill_esp32s3_mesh.pid.1=0x82f5 +fobe_quill_esp32s3_mesh.vid.2=0x303a +fobe_quill_esp32s3_mesh.pid.2=0x82f6 + +fobe_quill_esp32s3_mesh.bootloader.tool=esptool_py +fobe_quill_esp32s3_mesh.bootloader.tool.default=esptool_py + +fobe_quill_esp32s3_mesh.upload.tool=esptool_py +fobe_quill_esp32s3_mesh.upload.tool.default=esptool_py +fobe_quill_esp32s3_mesh.upload.tool.network=esp_ota + +fobe_quill_esp32s3_mesh.upload.maximum_size=1310720 +fobe_quill_esp32s3_mesh.upload.maximum_data_size=327680 +fobe_quill_esp32s3_mesh.upload.flags= +fobe_quill_esp32s3_mesh.upload.extra_flags= +fobe_quill_esp32s3_mesh.upload.use_1200bps_touch=true +fobe_quill_esp32s3_mesh.upload.wait_for_upload_port=true + +fobe_quill_esp32s3_mesh.serial.disableDTR=false +fobe_quill_esp32s3_mesh.serial.disableRTS=false + +fobe_quill_esp32s3_mesh.build.tarch=xtensa +fobe_quill_esp32s3_mesh.build.bootloader_addr=0x0 +fobe_quill_esp32s3_mesh.build.target=esp32s3 +fobe_quill_esp32s3_mesh.build.mcu=esp32s3 +fobe_quill_esp32s3_mesh.build.core=esp32 +fobe_quill_esp32s3_mesh.build.variant=fobe_quill_esp32s3_mesh +fobe_quill_esp32s3_mesh.build.board=FOBE_QUILL_ESP32S3_MESH + +fobe_quill_esp32s3_mesh.build.usb_mode=0 +fobe_quill_esp32s3_mesh.build.cdc_on_boot=1 +fobe_quill_esp32s3_mesh.build.msc_on_boot=0 +fobe_quill_esp32s3_mesh.build.dfu_on_boot=0 +fobe_quill_esp32s3_mesh.build.f_cpu=240000000L +fobe_quill_esp32s3_mesh.build.flash_size=4MB +fobe_quill_esp32s3_mesh.build.flash_freq=80m +fobe_quill_esp32s3_mesh.build.flash_mode=qio +fobe_quill_esp32s3_mesh.build.boot=qio +fobe_quill_esp32s3_mesh.build.boot_freq=80m +fobe_quill_esp32s3_mesh.build.partitions=ffat +fobe_quill_esp32s3_mesh.build.defines= +fobe_quill_esp32s3_mesh.build.loop_core= +fobe_quill_esp32s3_mesh.build.event_core= +fobe_quill_esp32s3_mesh.build.psram_type=qspi +fobe_quill_esp32s3_mesh.build.memory_type={build.boot}_{build.psram_type} + +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.default=Disabled +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.default.build.copy_jtag_files=0 +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.builtin=Integrated USB JTAG +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.external=FTDI Adapter +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.external.build.copy_jtag_files=1 +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.bridge=ESP USB Bridge +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +fobe_quill_esp32s3_mesh.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +fobe_quill_esp32s3_mesh.menu.PSRAM.disabled=Disabled +fobe_quill_esp32s3_mesh.menu.PSRAM.disabled.build.defines= +fobe_quill_esp32s3_mesh.menu.PSRAM.disabled.build.psram_type=qspi +fobe_quill_esp32s3_mesh.menu.PSRAM.enabled=QSPI PSRAM +fobe_quill_esp32s3_mesh.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +fobe_quill_esp32s3_mesh.menu.PSRAM.enabled.build.psram_type=qspi + +fobe_quill_esp32s3_mesh.menu.FlashMode.qio=QIO 80MHz +fobe_quill_esp32s3_mesh.menu.FlashMode.qio.build.flash_mode=dio +fobe_quill_esp32s3_mesh.menu.FlashMode.qio.build.boot=qio +fobe_quill_esp32s3_mesh.menu.FlashMode.qio.build.boot_freq=80m +fobe_quill_esp32s3_mesh.menu.FlashMode.qio.build.flash_freq=80m +fobe_quill_esp32s3_mesh.menu.FlashMode.dio=DIO 80MHz +fobe_quill_esp32s3_mesh.menu.FlashMode.dio.build.flash_mode=dio +fobe_quill_esp32s3_mesh.menu.FlashMode.dio.build.boot=dio +fobe_quill_esp32s3_mesh.menu.FlashMode.dio.build.boot_freq=80m +fobe_quill_esp32s3_mesh.menu.FlashMode.dio.build.flash_freq=80m + +fobe_quill_esp32s3_mesh.menu.FlashSize.4M=4MB (32Mb) +fobe_quill_esp32s3_mesh.menu.FlashSize.4M.build.flash_size=4MB + +fobe_quill_esp32s3_mesh.menu.LoopCore.1=Core 1 +fobe_quill_esp32s3_mesh.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +fobe_quill_esp32s3_mesh.menu.LoopCore.0=Core 0 +fobe_quill_esp32s3_mesh.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +fobe_quill_esp32s3_mesh.menu.EventsCore.1=Core 1 +fobe_quill_esp32s3_mesh.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +fobe_quill_esp32s3_mesh.menu.EventsCore.0=Core 0 +fobe_quill_esp32s3_mesh.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +fobe_quill_esp32s3_mesh.menu.USBMode.hwcdc=Hardware CDC and JTAG +fobe_quill_esp32s3_mesh.menu.USBMode.hwcdc.build.usb_mode=1 +fobe_quill_esp32s3_mesh.menu.USBMode.default=USB-OTG (TinyUSB) +fobe_quill_esp32s3_mesh.menu.USBMode.default.build.usb_mode=0 + +fobe_quill_esp32s3_mesh.menu.CDCOnBoot.default=Enabled +fobe_quill_esp32s3_mesh.menu.CDCOnBoot.default.build.cdc_on_boot=1 +fobe_quill_esp32s3_mesh.menu.CDCOnBoot.cdc=Disabled +fobe_quill_esp32s3_mesh.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +fobe_quill_esp32s3_mesh.menu.MSCOnBoot.default=Disabled +fobe_quill_esp32s3_mesh.menu.MSCOnBoot.default.build.msc_on_boot=0 +fobe_quill_esp32s3_mesh.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +fobe_quill_esp32s3_mesh.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +fobe_quill_esp32s3_mesh.menu.DFUOnBoot.default=Disabled +fobe_quill_esp32s3_mesh.menu.DFUOnBoot.default.build.dfu_on_boot=0 +fobe_quill_esp32s3_mesh.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +fobe_quill_esp32s3_mesh.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +fobe_quill_esp32s3_mesh.menu.UploadMode.default=UART0 / Hardware CDC +fobe_quill_esp32s3_mesh.menu.UploadMode.default.upload.use_1200bps_touch=false +fobe_quill_esp32s3_mesh.menu.UploadMode.default.upload.wait_for_upload_port=false +fobe_quill_esp32s3_mesh.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +fobe_quill_esp32s3_mesh.menu.UploadMode.cdc.upload.use_1200bps_touch=true +fobe_quill_esp32s3_mesh.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin" +fobe_quill_esp32s3_mesh.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.default.build.partitions=default +fobe_quill_esp32s3_mesh.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +fobe_quill_esp32s3_mesh.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.minimal.build.partitions=minimal +fobe_quill_esp32s3_mesh.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.no_ota.build.partitions=no_ota +fobe_quill_esp32s3_mesh.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +fobe_quill_esp32s3_mesh.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.huge_app.build.partitions=huge_app +fobe_quill_esp32s3_mesh.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +fobe_quill_esp32s3_mesh.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +fobe_quill_esp32s3_mesh.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +fobe_quill_esp32s3_mesh.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +fobe_quill_esp32s3_mesh.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +fobe_quill_esp32s3_mesh.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +fobe_quill_esp32s3_mesh.menu.CPUFreq.240=240MHz (WiFi) +fobe_quill_esp32s3_mesh.menu.CPUFreq.240.build.f_cpu=240000000L +fobe_quill_esp32s3_mesh.menu.CPUFreq.160=160MHz (WiFi) +fobe_quill_esp32s3_mesh.menu.CPUFreq.160.build.f_cpu=160000000L +fobe_quill_esp32s3_mesh.menu.CPUFreq.80=80MHz (WiFi) +fobe_quill_esp32s3_mesh.menu.CPUFreq.80.build.f_cpu=80000000L +fobe_quill_esp32s3_mesh.menu.CPUFreq.40=40MHz +fobe_quill_esp32s3_mesh.menu.CPUFreq.40.build.f_cpu=40000000L +fobe_quill_esp32s3_mesh.menu.CPUFreq.20=20MHz +fobe_quill_esp32s3_mesh.menu.CPUFreq.20.build.f_cpu=20000000L +fobe_quill_esp32s3_mesh.menu.CPUFreq.10=10MHz +fobe_quill_esp32s3_mesh.menu.CPUFreq.10.build.f_cpu=10000000L + +fobe_quill_esp32s3_mesh.menu.UploadSpeed.921600=921600 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.921600.upload.speed=921600 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.115200=115200 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.115200.upload.speed=115200 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.256000.windows=256000 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.256000.upload.speed=256000 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.230400.windows.upload.speed=256000 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.230400=230400 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.230400.upload.speed=230400 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.460800.linux=460800 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.460800.macosx=460800 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.460800.upload.speed=460800 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.512000.windows=512000 +fobe_quill_esp32s3_mesh.menu.UploadSpeed.512000.upload.speed=512000 + +fobe_quill_esp32s3_mesh.menu.DebugLevel.none=None +fobe_quill_esp32s3_mesh.menu.DebugLevel.none.build.code_debug=0 +fobe_quill_esp32s3_mesh.menu.DebugLevel.error=Error +fobe_quill_esp32s3_mesh.menu.DebugLevel.error.build.code_debug=1 +fobe_quill_esp32s3_mesh.menu.DebugLevel.warn=Warn +fobe_quill_esp32s3_mesh.menu.DebugLevel.warn.build.code_debug=2 +fobe_quill_esp32s3_mesh.menu.DebugLevel.info=Info +fobe_quill_esp32s3_mesh.menu.DebugLevel.info.build.code_debug=3 +fobe_quill_esp32s3_mesh.menu.DebugLevel.debug=Debug +fobe_quill_esp32s3_mesh.menu.DebugLevel.debug.build.code_debug=4 +fobe_quill_esp32s3_mesh.menu.DebugLevel.verbose=Verbose +fobe_quill_esp32s3_mesh.menu.DebugLevel.verbose.build.code_debug=5 + +fobe_quill_esp32s3_mesh.menu.EraseFlash.none=Disabled +fobe_quill_esp32s3_mesh.menu.EraseFlash.none.upload.erase_cmd= +fobe_quill_esp32s3_mesh.menu.EraseFlash.all=Enabled +fobe_quill_esp32s3_mesh.menu.EraseFlash.all.upload.erase_cmd=-e + +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.default=Disabled +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.default.build.zigbee_mode= +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.default.build.zigbee_libs= +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +fobe_quill_esp32s3_mesh.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +twinaiot.name=Twin AIoT Module + +twinaiot.bootloader.tool=esptool_py +twinaiot.bootloader.tool.default=esptool_py + +twinaiot.upload.tool=esptool_py +twinaiot.upload.tool.default=esptool_py +twinaiot.upload.tool.network=esp_ota + +twinaiot.upload.maximum_size=1310720 +twinaiot.upload.maximum_data_size=327680 +twinaiot.upload.flags= +twinaiot.upload.extra_flags= +twinaiot.upload.use_1200bps_touch=false +twinaiot.upload.wait_for_upload_port=false + +twinaiot.serial.disableDTR=false +twinaiot.serial.disableRTS=false + +twinaiot.build.tarch=xtensa +twinaiot.build.bootloader_addr=0x0 +twinaiot.build.target=esp32s3 +twinaiot.build.mcu=esp32s3 +twinaiot.build.core=esp32 +twinaiot.build.variant=twinaiot +twinaiot.build.board=TWIN_AIOT + +twinaiot.build.usb_mode=1 +twinaiot.build.cdc_on_boot=0 +twinaiot.build.msc_on_boot=0 +twinaiot.build.dfu_on_boot=0 +twinaiot.build.f_cpu=240000000L +twinaiot.build.flash_size=4MB +twinaiot.build.flash_freq=80m +twinaiot.build.flash_mode=dio +twinaiot.build.boot=qio +twinaiot.build.boot_freq=80m +twinaiot.build.partitions=default +twinaiot.build.defines= +twinaiot.build.loop_core= +twinaiot.build.event_core= +twinaiot.build.psram_type=qspi +twinaiot.build.memory_type={build.boot}_{build.psram_type} + +twinaiot.menu.JTAGAdapter.default=Disabled +twinaiot.menu.JTAGAdapter.default.build.copy_jtag_files=0 +twinaiot.menu.JTAGAdapter.builtin=Integrated USB JTAG +twinaiot.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +twinaiot.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +twinaiot.menu.JTAGAdapter.external=FTDI Adapter +twinaiot.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +twinaiot.menu.JTAGAdapter.external.build.copy_jtag_files=1 +twinaiot.menu.JTAGAdapter.bridge=ESP USB Bridge +twinaiot.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +twinaiot.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +twinaiot.menu.PSRAM.disabled=Disabled +twinaiot.menu.PSRAM.disabled.build.defines= +twinaiot.menu.PSRAM.disabled.build.psram_type=qspi +twinaiot.menu.PSRAM.enabled=QSPI PSRAM +twinaiot.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +twinaiot.menu.PSRAM.enabled.build.psram_type=qspi + +twinaiot.menu.FlashMode.qio=QIO 80MHz +twinaiot.menu.FlashMode.qio.build.flash_mode=dio +twinaiot.menu.FlashMode.qio.build.boot=qio +twinaiot.menu.FlashMode.qio.build.boot_freq=80m +twinaiot.menu.FlashMode.qio.build.flash_freq=80m +twinaiot.menu.FlashMode.qio120=QIO 120MHz +twinaiot.menu.FlashMode.qio120.build.flash_mode=dio +twinaiot.menu.FlashMode.qio120.build.boot=qio +twinaiot.menu.FlashMode.qio120.build.boot_freq=120m +twinaiot.menu.FlashMode.qio120.build.flash_freq=80m +twinaiot.menu.FlashMode.dio=DIO 80MHz +twinaiot.menu.FlashMode.dio.build.flash_mode=dio +twinaiot.menu.FlashMode.dio.build.boot=dio +twinaiot.menu.FlashMode.dio.build.boot_freq=80m +twinaiot.menu.FlashMode.dio.build.flash_freq=80m + + +twinaiot.menu.FlashSize.4M=4MB (32Mb) +twinaiot.menu.FlashSize.4M.build.flash_size=4MB + +twinaiot.menu.CPUFreq.240=240MHz (WiFi) +twinaiot.menu.CPUFreq.240.build.f_cpu=240000000L +twinaiot.menu.CPUFreq.160=160MHz (WiFi) +twinaiot.menu.CPUFreq.160.build.f_cpu=160000000L +twinaiot.menu.CPUFreq.80=80MHz (WiFi) +twinaiot.menu.CPUFreq.80.build.f_cpu=80000000L +twinaiot.menu.CPUFreq.40=40MHz +twinaiot.menu.CPUFreq.40.build.f_cpu=40000000L +twinaiot.menu.CPUFreq.20=20MHz +twinaiot.menu.CPUFreq.20.build.f_cpu=20000000L +twinaiot.menu.CPUFreq.10=10MHz +twinaiot.menu.CPUFreq.10.build.f_cpu=10000000L + +twinaiot.menu.UploadSpeed.921600=921600 +twinaiot.menu.UploadSpeed.921600.upload.speed=921600 +twinaiot.menu.UploadSpeed.115200=115200 +twinaiot.menu.UploadSpeed.115200.upload.speed=115200 +twinaiot.menu.UploadSpeed.256000.windows=256000 +twinaiot.menu.UploadSpeed.256000.upload.speed=256000 +twinaiot.menu.UploadSpeed.230400.windows.upload.speed=256000 +twinaiot.menu.UploadSpeed.230400=230400 +twinaiot.menu.UploadSpeed.230400.upload.speed=230400 +twinaiot.menu.UploadSpeed.460800.linux=460800 +twinaiot.menu.UploadSpeed.460800.macosx=460800 +twinaiot.menu.UploadSpeed.460800.upload.speed=460800 +twinaiot.menu.UploadSpeed.512000.windows=512000 +twinaiot.menu.UploadSpeed.512000.upload.speed=512000 + +twinaiot.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +twinaiot.menu.PartitionScheme.default.build.partitions=default +twinaiot.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +twinaiot.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +twinaiot.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +twinaiot.menu.PartitionScheme.minimal.build.partitions=minimal +twinaiot.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +twinaiot.menu.PartitionScheme.no_fs.build.partitions=no_fs +twinaiot.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +twinaiot.menu.PartitionScheme.no_ota.build.partitions=no_ota +twinaiot.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +twinaiot.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +twinaiot.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +twinaiot.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +twinaiot.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +twinaiot.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +twinaiot.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +twinaiot.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +twinaiot.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +twinaiot.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +twinaiot.menu.PartitionScheme.huge_app.build.partitions=huge_app +twinaiot.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +twinaiot.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +twinaiot.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +twinaiot.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +twinaiot.menu.PartitionScheme.rainmaker=RainMaker 4MB +twinaiot.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +twinaiot.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +twinaiot.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +twinaiot.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +twinaiot.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +twinaiot.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +twinaiot.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +twinaiot.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +twinaiot.menu.PartitionScheme.custom=Custom +twinaiot.menu.PartitionScheme.custom.build.partitions= +twinaiot.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +twinaiot.menu.LoopCore.1=Core 1 +twinaiot.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +twinaiot.menu.LoopCore.0=Core 0 +twinaiot.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +twinaiot.menu.EventsCore.1=Core 1 +twinaiot.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +twinaiot.menu.EventsCore.0=Core 0 +twinaiot.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +twinaiot.menu.USBMode.hwcdc=Hardware CDC and JTAG +twinaiot.menu.USBMode.hwcdc.build.usb_mode=1 +twinaiot.menu.USBMode.default=USB-OTG (TinyUSB) +twinaiot.menu.USBMode.default.build.usb_mode=0 + +twinaiot.menu.CDCOnBoot.default=Disabled +twinaiot.menu.CDCOnBoot.default.build.cdc_on_boot=0 +twinaiot.menu.CDCOnBoot.cdc=Enabled +twinaiot.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +twinaiot.menu.MSCOnBoot.default=Disabled +twinaiot.menu.MSCOnBoot.default.build.msc_on_boot=0 +twinaiot.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +twinaiot.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +twinaiot.menu.DFUOnBoot.default=Disabled +twinaiot.menu.DFUOnBoot.default.build.dfu_on_boot=0 +twinaiot.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +twinaiot.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +twinaiot.menu.UploadMode.default=UART0 / Hardware CDC +twinaiot.menu.UploadMode.default.upload.use_1200bps_touch=false +twinaiot.menu.UploadMode.default.upload.wait_for_upload_port=false +twinaiot.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +twinaiot.menu.UploadMode.cdc.upload.use_1200bps_touch=true +twinaiot.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +twinaiot.menu.DebugLevel.none=None +twinaiot.menu.DebugLevel.none.build.code_debug=0 +twinaiot.menu.DebugLevel.error=Error +twinaiot.menu.DebugLevel.error.build.code_debug=1 +twinaiot.menu.DebugLevel.warn=Warn +twinaiot.menu.DebugLevel.warn.build.code_debug=2 +twinaiot.menu.DebugLevel.info=Info +twinaiot.menu.DebugLevel.info.build.code_debug=3 +twinaiot.menu.DebugLevel.debug=Debug +twinaiot.menu.DebugLevel.debug.build.code_debug=4 +twinaiot.menu.DebugLevel.verbose=Verbose +twinaiot.menu.DebugLevel.verbose.build.code_debug=5 + +twinaiot.menu.EraseFlash.none=Disabled +twinaiot.menu.EraseFlash.none.upload.erase_cmd= +twinaiot.menu.EraseFlash.all=Enabled +twinaiot.menu.EraseFlash.all.upload.erase_cmd=-e + +twinaiot.menu.ZigbeeMode.default=Disabled +twinaiot.menu.ZigbeeMode.default.build.zigbee_mode= +twinaiot.menu.ZigbeeMode.default.build.zigbee_libs= +twinaiot.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +twinaiot.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +twinaiot.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +esp32p4_4ds_mipi.name=4D Systems ESP32-P4 MIPI Displays + +esp32p4_4ds_mipi.bootloader.tool=esptool_py +esp32p4_4ds_mipi.bootloader.tool.default=esptool_py + +esp32p4_4ds_mipi.upload.tool=esptool_py +esp32p4_4ds_mipi.upload.tool.default=esptool_py +esp32p4_4ds_mipi.upload.tool.network=esp_ota + +esp32p4_4ds_mipi.upload.maximum_size=1310720 +esp32p4_4ds_mipi.upload.maximum_data_size=327680 +esp32p4_4ds_mipi.upload.flags= +esp32p4_4ds_mipi.upload.extra_flags= +esp32p4_4ds_mipi.upload.use_1200bps_touch=false +esp32p4_4ds_mipi.upload.wait_for_upload_port=false + +esp32p4_4ds_mipi.serial.disableDTR=false +esp32p4_4ds_mipi.serial.disableRTS=false + +esp32p4_4ds_mipi.build.tarch=riscv32 +esp32p4_4ds_mipi.build.target=esp +esp32p4_4ds_mipi.build.mcu=esp32p4 +esp32p4_4ds_mipi.build.core=esp32 +esp32p4_4ds_mipi.build.variant=esp32p4_4ds_mipi +esp32p4_4ds_mipi.build.board=ESP32P4_4DS_MIPI +esp32p4_4ds_mipi.build.bootloader_addr=0x2000 +esp32p4_4ds_mipi.build.chip_variant=esp32p4_es + +esp32p4_4ds_mipi.build.usb_mode=0 +esp32p4_4ds_mipi.build.cdc_on_boot=0 +esp32p4_4ds_mipi.build.msc_on_boot=0 +esp32p4_4ds_mipi.build.dfu_on_boot=0 +esp32p4_4ds_mipi.build.f_cpu=360000000L +esp32p4_4ds_mipi.build.flash_size=32MB +esp32p4_4ds_mipi.build.flash_freq=80m +esp32p4_4ds_mipi.build.img_freq=80m +esp32p4_4ds_mipi.build.flash_mode=qio +esp32p4_4ds_mipi.build.boot=qio +esp32p4_4ds_mipi.build.partitions=app5M_fat24M_32MB + +esp32p4_4ds_mipi.menu.Revision.prev3=Hardware Rev 1.x +esp32p4_4ds_mipi.menu.Revision.prev3.build.chip_variant=esp32p4_es +esp32p4_4ds_mipi.menu.Revision.prev3.build.f_cpu=360000000L +esp32p4_4ds_mipi.menu.Revision.postv3=Hardware Rev 2.x +esp32p4_4ds_mipi.menu.Revision.postv3.build.chip_variant=esp32p4 +esp32p4_4ds_mipi.menu.Revision.postv3.build.f_cpu=400000000L + +## IDE 2.0 Seems to not update the value +esp32p4_4ds_mipi.menu.JTAGAdapter.default=Disabled +esp32p4_4ds_mipi.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32p4_4ds_mipi.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32p4_4ds_mipi.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg +esp32p4_4ds_mipi.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32p4_4ds_mipi.menu.JTAGAdapter.external=FTDI Adapter +esp32p4_4ds_mipi.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg +esp32p4_4ds_mipi.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32p4_4ds_mipi.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32p4_4ds_mipi.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg +esp32p4_4ds_mipi.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32p4_4ds_mipi.menu.USBMode.default=USB-OTG (TinyUSB) +esp32p4_4ds_mipi.menu.USBMode.default.build.usb_mode=0 +esp32p4_4ds_mipi.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32p4_4ds_mipi.menu.USBMode.hwcdc.build.usb_mode=1 + +esp32p4_4ds_mipi.menu.CDCOnBoot.default=Disabled +esp32p4_4ds_mipi.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32p4_4ds_mipi.menu.CDCOnBoot.cdc=Enabled +esp32p4_4ds_mipi.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32p4_4ds_mipi.menu.MSCOnBoot.default=Disabled +esp32p4_4ds_mipi.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32p4_4ds_mipi.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32p4_4ds_mipi.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32p4_4ds_mipi.menu.DFUOnBoot.default=Disabled +esp32p4_4ds_mipi.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32p4_4ds_mipi.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32p4_4ds_mipi.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32p4_4ds_mipi.menu.UploadMode.default=UART0 / Hardware CDC +esp32p4_4ds_mipi.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32p4_4ds_mipi.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32p4_4ds_mipi.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32p4_4ds_mipi.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32p4_4ds_mipi.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32p4_4ds_mipi.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32p4_4ds_mipi.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +esp32p4_4ds_mipi.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +esp32p4_4ds_mipi.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 + +## From https://docs.espressif.com/projects/esp-idf/en/latest/esp32p4/api-reference/kconfig.html#config-esp-default-cpu-freq-mhz + +esp32p4_4ds_mipi.menu.UploadSpeed.921600=921600 +esp32p4_4ds_mipi.menu.UploadSpeed.921600.upload.speed=921600 +esp32p4_4ds_mipi.menu.UploadSpeed.115200=115200 +esp32p4_4ds_mipi.menu.UploadSpeed.115200.upload.speed=115200 +esp32p4_4ds_mipi.menu.UploadSpeed.256000.windows=256000 +esp32p4_4ds_mipi.menu.UploadSpeed.256000.upload.speed=256000 +esp32p4_4ds_mipi.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32p4_4ds_mipi.menu.UploadSpeed.230400=230400 +esp32p4_4ds_mipi.menu.UploadSpeed.230400.upload.speed=230400 +esp32p4_4ds_mipi.menu.UploadSpeed.460800.linux=460800 +esp32p4_4ds_mipi.menu.UploadSpeed.460800.macosx=460800 +esp32p4_4ds_mipi.menu.UploadSpeed.460800.upload.speed=460800 +esp32p4_4ds_mipi.menu.UploadSpeed.512000.windows=512000 +esp32p4_4ds_mipi.menu.UploadSpeed.512000.upload.speed=512000 + +esp32p4_4ds_mipi.menu.DebugLevel.none=None +esp32p4_4ds_mipi.menu.DebugLevel.none.build.code_debug=0 +esp32p4_4ds_mipi.menu.DebugLevel.error=Error +esp32p4_4ds_mipi.menu.DebugLevel.error.build.code_debug=1 +esp32p4_4ds_mipi.menu.DebugLevel.warn=Warn +esp32p4_4ds_mipi.menu.DebugLevel.warn.build.code_debug=2 +esp32p4_4ds_mipi.menu.DebugLevel.info=Info +esp32p4_4ds_mipi.menu.DebugLevel.info.build.code_debug=3 +esp32p4_4ds_mipi.menu.DebugLevel.debug=Debug +esp32p4_4ds_mipi.menu.DebugLevel.debug.build.code_debug=4 +esp32p4_4ds_mipi.menu.DebugLevel.verbose=Verbose +esp32p4_4ds_mipi.menu.DebugLevel.verbose.build.code_debug=5 + +esp32p4_4ds_mipi.menu.EraseFlash.none=Disabled +esp32p4_4ds_mipi.menu.EraseFlash.none.upload.erase_cmd= +esp32p4_4ds_mipi.menu.EraseFlash.all=Enabled +esp32p4_4ds_mipi.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70=ESP32-P4-70 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70.build.DisplayModel=ESP32P4_70 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70ct=ESP32-P4-70CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70ct.build.DisplayModel=ESP32P4_70CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70ct_clb=ESP32-P4-70CT-CLB +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_70ct_clb.build.DisplayModel=ESP32P4_70CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80=ESP32-P4-80 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80.build.DisplayModel=ESP32P4_80 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80ct=ESP32-P4-80CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80ct.build.DisplayModel=ESP32P4_80CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80ct_clb=ESP32-P4-80CT-CLB +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_80ct_clb.build.DisplayModel=ESP32P4_80CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90=ESP32-P4-90 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90.build.DisplayModel=ESP32P4_90 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90ct=ESP32-P4-90CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90ct.build.DisplayModel=ESP32P4_90CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90ct_clb=ESP32-P4-90CT-CLB +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_90ct_clb.build.DisplayModel=ESP32P4_90CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101=ESP32-P4-101 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101.build.DisplayModel=ESP32P4_101 +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101ct=ESP32-P4-101CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101ct.build.DisplayModel=ESP32P4_101CT +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101ct_clb=ESP32-P4-101CT-CLB +esp32p4_4ds_mipi.menu.DisplayModel.esp32p4_101ct_clb.build.DisplayModel=ESP32P4_101CT + +esp32p4_4ds_mipi.build.defines=-DBOARD_HAS_PSRAM -D{build.board} -D{build.DisplayModel} + +############################################################## + +esp32p4_4ds_mipi_round.name=4D Systems ESP32-P4 Round MIPI Displays + +esp32p4_4ds_mipi_round.bootloader.tool=esptool_py +esp32p4_4ds_mipi_round.bootloader.tool.default=esptool_py + +esp32p4_4ds_mipi_round.upload.tool=esptool_py +esp32p4_4ds_mipi_round.upload.tool.default=esptool_py +esp32p4_4ds_mipi_round.upload.tool.network=esp_ota + +esp32p4_4ds_mipi_round.upload.maximum_size=1310720 +esp32p4_4ds_mipi_round.upload.maximum_data_size=327680 +esp32p4_4ds_mipi_round.upload.flags= +esp32p4_4ds_mipi_round.upload.extra_flags= +esp32p4_4ds_mipi_round.upload.use_1200bps_touch=false +esp32p4_4ds_mipi_round.upload.wait_for_upload_port=false + +esp32p4_4ds_mipi_round.serial.disableDTR=false +esp32p4_4ds_mipi_round.serial.disableRTS=false + +esp32p4_4ds_mipi_round.build.tarch=riscv32 +esp32p4_4ds_mipi_round.build.target=esp +esp32p4_4ds_mipi_round.build.mcu=esp32p4 +esp32p4_4ds_mipi_round.build.core=esp32 +esp32p4_4ds_mipi_round.build.variant=esp32p4_4ds_mipi_round +esp32p4_4ds_mipi_round.build.board=ESP32P4_4DS_MIPI_ROUND +esp32p4_4ds_mipi_round.build.bootloader_addr=0x2000 +esp32p4_4ds_mipi_round.build.chip_variant=esp32p4_es + +esp32p4_4ds_mipi_round.build.usb_mode=0 +esp32p4_4ds_mipi_round.build.cdc_on_boot=0 +esp32p4_4ds_mipi_round.build.msc_on_boot=0 +esp32p4_4ds_mipi_round.build.dfu_on_boot=0 +esp32p4_4ds_mipi_round.build.f_cpu=360000000L +esp32p4_4ds_mipi_round.build.flash_size=32MB +esp32p4_4ds_mipi_round.build.flash_freq=80m +esp32p4_4ds_mipi_round.build.img_freq=80m +esp32p4_4ds_mipi_round.build.flash_mode=qio +esp32p4_4ds_mipi_round.build.boot=qio +esp32p4_4ds_mipi_round.build.partitions=app5M_fat24M_32MB + +esp32p4_4ds_mipi_round.menu.Revision.prev3=Hardware Rev 1.x +esp32p4_4ds_mipi_round.menu.Revision.prev3.build.chip_variant=esp32p4_es +esp32p4_4ds_mipi_round.menu.Revision.prev3.build.f_cpu=360000000L +esp32p4_4ds_mipi_round.menu.Revision.postv3=Hardware Rev 2.x +esp32p4_4ds_mipi_round.menu.Revision.postv3.build.chip_variant=esp32p4 +esp32p4_4ds_mipi_round.menu.Revision.postv3.build.f_cpu=400000000L + +esp32p4_4ds_mipi_round.menu.JTAGAdapter.default=Disabled +esp32p4_4ds_mipi_round.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32p4_4ds_mipi_round.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32p4_4ds_mipi_round.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg +esp32p4_4ds_mipi_round.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32p4_4ds_mipi_round.menu.JTAGAdapter.external=FTDI Adapter +esp32p4_4ds_mipi_round.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg +esp32p4_4ds_mipi_round.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32p4_4ds_mipi_round.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32p4_4ds_mipi_round.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg +esp32p4_4ds_mipi_round.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32p4_4ds_mipi_round.menu.USBMode.default=USB-OTG (TinyUSB) +esp32p4_4ds_mipi_round.menu.USBMode.default.build.usb_mode=0 +esp32p4_4ds_mipi_round.menu.USBMode.hwcdc=Hardware CDC and JTAG +esp32p4_4ds_mipi_round.menu.USBMode.hwcdc.build.usb_mode=1 + +esp32p4_4ds_mipi_round.menu.CDCOnBoot.default=Disabled +esp32p4_4ds_mipi_round.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32p4_4ds_mipi_round.menu.CDCOnBoot.cdc=Enabled +esp32p4_4ds_mipi_round.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32p4_4ds_mipi_round.menu.MSCOnBoot.default=Disabled +esp32p4_4ds_mipi_round.menu.MSCOnBoot.default.build.msc_on_boot=0 +esp32p4_4ds_mipi_round.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +esp32p4_4ds_mipi_round.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +esp32p4_4ds_mipi_round.menu.DFUOnBoot.default=Disabled +esp32p4_4ds_mipi_round.menu.DFUOnBoot.default.build.dfu_on_boot=0 +esp32p4_4ds_mipi_round.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +esp32p4_4ds_mipi_round.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +esp32p4_4ds_mipi_round.menu.UploadMode.default=UART0 / Hardware CDC +esp32p4_4ds_mipi_round.menu.UploadMode.default.upload.use_1200bps_touch=false +esp32p4_4ds_mipi_round.menu.UploadMode.default.upload.wait_for_upload_port=false +esp32p4_4ds_mipi_round.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +esp32p4_4ds_mipi_round.menu.UploadMode.cdc.upload.use_1200bps_touch=true +esp32p4_4ds_mipi_round.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +esp32p4_4ds_mipi_round.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +esp32p4_4ds_mipi_round.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +esp32p4_4ds_mipi_round.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +esp32p4_4ds_mipi_round.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 + +esp32p4_4ds_mipi_round.menu.UploadSpeed.921600=921600 +esp32p4_4ds_mipi_round.menu.UploadSpeed.921600.upload.speed=921600 +esp32p4_4ds_mipi_round.menu.UploadSpeed.115200=115200 +esp32p4_4ds_mipi_round.menu.UploadSpeed.115200.upload.speed=115200 +esp32p4_4ds_mipi_round.menu.UploadSpeed.256000.windows=256000 +esp32p4_4ds_mipi_round.menu.UploadSpeed.256000.upload.speed=256000 +esp32p4_4ds_mipi_round.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32p4_4ds_mipi_round.menu.UploadSpeed.230400=230400 +esp32p4_4ds_mipi_round.menu.UploadSpeed.230400.upload.speed=230400 +esp32p4_4ds_mipi_round.menu.UploadSpeed.460800.linux=460800 +esp32p4_4ds_mipi_round.menu.UploadSpeed.460800.macosx=460800 +esp32p4_4ds_mipi_round.menu.UploadSpeed.460800.upload.speed=460800 +esp32p4_4ds_mipi_round.menu.UploadSpeed.512000.windows=512000 +esp32p4_4ds_mipi_round.menu.UploadSpeed.512000.upload.speed=512000 + +esp32p4_4ds_mipi_round.menu.DebugLevel.none=None +esp32p4_4ds_mipi_round.menu.DebugLevel.none.build.code_debug=0 +esp32p4_4ds_mipi_round.menu.DebugLevel.error=Error +esp32p4_4ds_mipi_round.menu.DebugLevel.error.build.code_debug=1 +esp32p4_4ds_mipi_round.menu.DebugLevel.warn=Warn +esp32p4_4ds_mipi_round.menu.DebugLevel.warn.build.code_debug=2 +esp32p4_4ds_mipi_round.menu.DebugLevel.info=Info +esp32p4_4ds_mipi_round.menu.DebugLevel.info.build.code_debug=3 +esp32p4_4ds_mipi_round.menu.DebugLevel.debug=Debug +esp32p4_4ds_mipi_round.menu.DebugLevel.debug.build.code_debug=4 +esp32p4_4ds_mipi_round.menu.DebugLevel.verbose=Verbose +esp32p4_4ds_mipi_round.menu.DebugLevel.verbose.build.code_debug=5 + +esp32p4_4ds_mipi_round.menu.EraseFlash.none=Disabled +esp32p4_4ds_mipi_round.menu.EraseFlash.none.upload.erase_cmd= +esp32p4_4ds_mipi_round.menu.EraseFlash.all=Enabled +esp32p4_4ds_mipi_round.menu.EraseFlash.all.upload.erase_cmd=-e + +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34r=ESP32-P4-34R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34r.build.DisplayModel=ESP32P4_34R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34r_clb=ESP32-P4-34R-CLB +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34r_clb.build.DisplayModel=ESP32P4_34R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34rct=ESP32-P4-34RCT +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34rct.build.DisplayModel=ESP32P4_34RCT +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34rct_clb=ESP32-P4-34RCT-CLB +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_34rct_clb.build.DisplayModel=ESP32P4_34RCT +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40r=ESP32-P4-40R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40r.build.DisplayModel=ESP32P4_40R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40r_clb=ESP32-P4-40R-CLB +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40r_clb.build.DisplayModel=ESP32P4_40R +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40rct=ESP32-P4-40RCT +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40rct.build.DisplayModel=ESP32P4_40RCT +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40rct_clb=ESP32-P4-40RCT-CLB +esp32p4_4ds_mipi_round.menu.DisplayModel.esp32p4_40rct_clb.build.DisplayModel=ESP32P4_40RCT + +esp32p4_4ds_mipi_round.build.defines=-DBOARD_HAS_PSRAM -D{build.board} -D{build.DisplayModel} + +############################################################## + +# Axiometa PIXIE M1 - Based on ESP32-S3-Mini-N4R2 +# 4MB Quad SPI Flash, 2MB Quad SPI PSRAM + +axiometa_pixie_m1.name=Axiometa PIXIE M1 + +axiometa_pixie_m1.bootloader.tool=esptool_py +axiometa_pixie_m1.bootloader.tool.default=esptool_py + +axiometa_pixie_m1.upload.tool=esptool_py +axiometa_pixie_m1.upload.tool.default=esptool_py +axiometa_pixie_m1.upload.tool.network=esp_ota + +axiometa_pixie_m1.upload.maximum_size=1310720 +axiometa_pixie_m1.upload.maximum_data_size=327680 +axiometa_pixie_m1.upload.flags= +axiometa_pixie_m1.upload.extra_flags= +axiometa_pixie_m1.upload.use_1200bps_touch=false +axiometa_pixie_m1.upload.wait_for_upload_port=false + +axiometa_pixie_m1.serial.disableDTR=false +axiometa_pixie_m1.serial.disableRTS=false + +axiometa_pixie_m1.build.tarch=xtensa +axiometa_pixie_m1.build.bootloader_addr=0x0 +axiometa_pixie_m1.build.target=esp32s3 +axiometa_pixie_m1.build.mcu=esp32s3 +axiometa_pixie_m1.build.core=esp32 +axiometa_pixie_m1.build.variant=axiometa_pixie_m1 +axiometa_pixie_m1.build.board=AXIOMETA_PIXIE_M1 + +# Hardware Configuration (ESP32-S3-Mini-N4R2) +axiometa_pixie_m1.build.usb_mode=1 +axiometa_pixie_m1.build.cdc_on_boot=1 +axiometa_pixie_m1.build.msc_on_boot=0 +axiometa_pixie_m1.build.dfu_on_boot=0 +axiometa_pixie_m1.build.f_cpu=240000000L +axiometa_pixie_m1.build.flash_size=4MB +axiometa_pixie_m1.build.flash_freq=80m +axiometa_pixie_m1.build.flash_mode=dio +axiometa_pixie_m1.build.boot=qio +axiometa_pixie_m1.build.boot_freq=80m +axiometa_pixie_m1.build.partitions=default +axiometa_pixie_m1.build.defines=-DBOARD_HAS_PSRAM +axiometa_pixie_m1.build.loop_core= +axiometa_pixie_m1.build.event_core= +axiometa_pixie_m1.build.psram_type=qspi +axiometa_pixie_m1.build.memory_type={build.boot}_{build.psram_type} + +## JTAG Adapter - N4R2 Compatible +axiometa_pixie_m1.menu.JTAGAdapter.default=Disabled +axiometa_pixie_m1.menu.JTAGAdapter.default.build.copy_jtag_files=0 +axiometa_pixie_m1.menu.JTAGAdapter.builtin=Integrated USB JTAG +axiometa_pixie_m1.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +axiometa_pixie_m1.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +axiometa_pixie_m1.menu.JTAGAdapter.external=FTDI Adapter +axiometa_pixie_m1.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +axiometa_pixie_m1.menu.JTAGAdapter.external.build.copy_jtag_files=1 +axiometa_pixie_m1.menu.JTAGAdapter.bridge=ESP USB Bridge +axiometa_pixie_m1.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +axiometa_pixie_m1.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +## PSRAM - N4R2 has 2MB QSPI PSRAM +axiometa_pixie_m1.menu.PSRAM.enabled=QSPI PSRAM (Enabled) +axiometa_pixie_m1.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +axiometa_pixie_m1.menu.PSRAM.enabled.build.psram_type=qspi +axiometa_pixie_m1.menu.PSRAM.disabled=Disabled +axiometa_pixie_m1.menu.PSRAM.disabled.build.defines= +axiometa_pixie_m1.menu.PSRAM.disabled.build.psram_type=qspi + +## Flash Mode - N4R2 Compatible (QSPI Flash) +axiometa_pixie_m1.menu.FlashMode.qio=QIO 80MHz +axiometa_pixie_m1.menu.FlashMode.qio.build.flash_mode=dio +axiometa_pixie_m1.menu.FlashMode.qio.build.boot=qio +axiometa_pixie_m1.menu.FlashMode.qio.build.boot_freq=80m +axiometa_pixie_m1.menu.FlashMode.qio.build.flash_freq=80m +axiometa_pixie_m1.menu.FlashMode.qio120=QIO 120MHz +axiometa_pixie_m1.menu.FlashMode.qio120.build.flash_mode=dio +axiometa_pixie_m1.menu.FlashMode.qio120.build.boot=qio +axiometa_pixie_m1.menu.FlashMode.qio120.build.boot_freq=120m +axiometa_pixie_m1.menu.FlashMode.qio120.build.flash_freq=80m +axiometa_pixie_m1.menu.FlashMode.dio=DIO 80MHz +axiometa_pixie_m1.menu.FlashMode.dio.build.flash_mode=dio +axiometa_pixie_m1.menu.FlashMode.dio.build.boot=dio +axiometa_pixie_m1.menu.FlashMode.dio.build.boot_freq=80m +axiometa_pixie_m1.menu.FlashMode.dio.build.flash_freq=80m + +## CPU Core Assignment +axiometa_pixie_m1.menu.LoopCore.1=Core 1 +axiometa_pixie_m1.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +axiometa_pixie_m1.menu.LoopCore.0=Core 0 +axiometa_pixie_m1.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +axiometa_pixie_m1.menu.EventsCore.1=Core 1 +axiometa_pixie_m1.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +axiometa_pixie_m1.menu.EventsCore.0=Core 0 +axiometa_pixie_m1.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +## USB Mode - Both modes work on N4R2 +axiometa_pixie_m1.menu.USBMode.hwcdc=Hardware CDC and JTAG +axiometa_pixie_m1.menu.USBMode.hwcdc.build.usb_mode=1 +axiometa_pixie_m1.menu.USBMode.default=USB-OTG (TinyUSB) +axiometa_pixie_m1.menu.USBMode.default.build.usb_mode=0 + +## CDC On Boot +axiometa_pixie_m1.menu.CDCOnBoot.cdc=Enabled +axiometa_pixie_m1.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +axiometa_pixie_m1.menu.CDCOnBoot.default=Disabled +axiometa_pixie_m1.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +## MSC On Boot (Only works with USB-OTG mode) +axiometa_pixie_m1.menu.MSCOnBoot.default=Disabled +axiometa_pixie_m1.menu.MSCOnBoot.default.build.msc_on_boot=0 +axiometa_pixie_m1.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +axiometa_pixie_m1.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +## DFU On Boot (Only works with USB-OTG mode) +axiometa_pixie_m1.menu.DFUOnBoot.default=Disabled +axiometa_pixie_m1.menu.DFUOnBoot.default.build.dfu_on_boot=0 +axiometa_pixie_m1.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +axiometa_pixie_m1.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +## Upload Mode +axiometa_pixie_m1.menu.UploadMode.default=UART0 / Hardware CDC +axiometa_pixie_m1.menu.UploadMode.default.upload.use_1200bps_touch=false +axiometa_pixie_m1.menu.UploadMode.default.upload.wait_for_upload_port=false +axiometa_pixie_m1.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +axiometa_pixie_m1.menu.UploadMode.cdc.upload.use_1200bps_touch=true +axiometa_pixie_m1.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +## Partition Schemes - 4MB Flash Compatible Only +axiometa_pixie_m1.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.default.build.partitions=default +axiometa_pixie_m1.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +axiometa_pixie_m1.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +axiometa_pixie_m1.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.minimal.build.partitions=minimal +axiometa_pixie_m1.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +axiometa_pixie_m1.menu.PartitionScheme.no_fs.build.partitions=no_fs +axiometa_pixie_m1.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +axiometa_pixie_m1.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.no_ota.build.partitions=no_ota +axiometa_pixie_m1.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +axiometa_pixie_m1.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +axiometa_pixie_m1.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +axiometa_pixie_m1.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +axiometa_pixie_m1.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +axiometa_pixie_m1.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +axiometa_pixie_m1.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +axiometa_pixie_m1.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +axiometa_pixie_m1.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +axiometa_pixie_m1.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.huge_app.build.partitions=huge_app +axiometa_pixie_m1.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +axiometa_pixie_m1.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +axiometa_pixie_m1.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +axiometa_pixie_m1.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +axiometa_pixie_m1.menu.PartitionScheme.rainmaker=RainMaker 4MB +axiometa_pixie_m1.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +axiometa_pixie_m1.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +axiometa_pixie_m1.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +axiometa_pixie_m1.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +axiometa_pixie_m1.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +axiometa_pixie_m1.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +axiometa_pixie_m1.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +axiometa_pixie_m1.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +axiometa_pixie_m1.menu.PartitionScheme.custom=Custom +axiometa_pixie_m1.menu.PartitionScheme.custom.build.partitions= +axiometa_pixie_m1.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +## CPU Frequency +axiometa_pixie_m1.menu.CPUFreq.240=240MHz (WiFi) +axiometa_pixie_m1.menu.CPUFreq.240.build.f_cpu=240000000L +axiometa_pixie_m1.menu.CPUFreq.160=160MHz (WiFi) +axiometa_pixie_m1.menu.CPUFreq.160.build.f_cpu=160000000L +axiometa_pixie_m1.menu.CPUFreq.80=80MHz (WiFi) +axiometa_pixie_m1.menu.CPUFreq.80.build.f_cpu=80000000L +axiometa_pixie_m1.menu.CPUFreq.40=40MHz +axiometa_pixie_m1.menu.CPUFreq.40.build.f_cpu=40000000L +axiometa_pixie_m1.menu.CPUFreq.20=20MHz +axiometa_pixie_m1.menu.CPUFreq.20.build.f_cpu=20000000L +axiometa_pixie_m1.menu.CPUFreq.10=10MHz +axiometa_pixie_m1.menu.CPUFreq.10.build.f_cpu=10000000L + +## Upload Speed +axiometa_pixie_m1.menu.UploadSpeed.921600=921600 +axiometa_pixie_m1.menu.UploadSpeed.921600.upload.speed=921600 +axiometa_pixie_m1.menu.UploadSpeed.115200=115200 +axiometa_pixie_m1.menu.UploadSpeed.115200.upload.speed=115200 +axiometa_pixie_m1.menu.UploadSpeed.256000.windows=256000 +axiometa_pixie_m1.menu.UploadSpeed.256000.upload.speed=256000 +axiometa_pixie_m1.menu.UploadSpeed.230400.windows.upload.speed=256000 +axiometa_pixie_m1.menu.UploadSpeed.230400=230400 +axiometa_pixie_m1.menu.UploadSpeed.230400.upload.speed=230400 +axiometa_pixie_m1.menu.UploadSpeed.460800.linux=460800 +axiometa_pixie_m1.menu.UploadSpeed.460800.macosx=460800 +axiometa_pixie_m1.menu.UploadSpeed.460800.upload.speed=460800 +axiometa_pixie_m1.menu.UploadSpeed.512000.windows=512000 +axiometa_pixie_m1.menu.UploadSpeed.512000.upload.speed=512000 + +## Debug Level +axiometa_pixie_m1.menu.DebugLevel.none=None +axiometa_pixie_m1.menu.DebugLevel.none.build.code_debug=0 +axiometa_pixie_m1.menu.DebugLevel.error=Error +axiometa_pixie_m1.menu.DebugLevel.error.build.code_debug=1 +axiometa_pixie_m1.menu.DebugLevel.warn=Warn +axiometa_pixie_m1.menu.DebugLevel.warn.build.code_debug=2 +axiometa_pixie_m1.menu.DebugLevel.info=Info +axiometa_pixie_m1.menu.DebugLevel.info.build.code_debug=3 +axiometa_pixie_m1.menu.DebugLevel.debug=Debug +axiometa_pixie_m1.menu.DebugLevel.debug.build.code_debug=4 +axiometa_pixie_m1.menu.DebugLevel.verbose=Verbose +axiometa_pixie_m1.menu.DebugLevel.verbose.build.code_debug=5 + +## Erase Flash +axiometa_pixie_m1.menu.EraseFlash.none=Disabled +axiometa_pixie_m1.menu.EraseFlash.none.upload.erase_cmd= +axiometa_pixie_m1.menu.EraseFlash.all=Enabled +axiometa_pixie_m1.menu.EraseFlash.all.upload.erase_cmd=-e + +## Zigbee Mode +axiometa_pixie_m1.menu.ZigbeeMode.default=Disabled +axiometa_pixie_m1.menu.ZigbeeMode.default.build.zigbee_mode= +axiometa_pixie_m1.menu.ZigbeeMode.default.build.zigbee_libs= +axiometa_pixie_m1.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +axiometa_pixie_m1.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +axiometa_pixie_m1.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +# Axiometa Genesis One - Based on ESP32-S3-WROOM-1-N8R2 +# 8MB Quad SPI Flash, 2MB Quad SPI PSRAM + +axiometa_genesis_one.name=Axiometa Genesis One + +axiometa_genesis_one.bootloader.tool=esptool_py +axiometa_genesis_one.bootloader.tool.default=esptool_py + +axiometa_genesis_one.upload.tool=esptool_py +axiometa_genesis_one.upload.tool.default=esptool_py +axiometa_genesis_one.upload.tool.network=esp_ota + +axiometa_genesis_one.upload.maximum_size=1310720 +axiometa_genesis_one.upload.maximum_data_size=327680 +axiometa_genesis_one.upload.flags= +axiometa_genesis_one.upload.extra_flags= +axiometa_genesis_one.upload.use_1200bps_touch=false +axiometa_genesis_one.upload.wait_for_upload_port=false + +axiometa_genesis_one.serial.disableDTR=false +axiometa_genesis_one.serial.disableRTS=false + +axiometa_genesis_one.build.tarch=xtensa +axiometa_genesis_one.build.bootloader_addr=0x0 +axiometa_genesis_one.build.target=esp32s3 +axiometa_genesis_one.build.mcu=esp32s3 +axiometa_genesis_one.build.core=esp32 +axiometa_genesis_one.build.variant=axiometa_genesis_one +axiometa_genesis_one.build.board=AXIOMETA_GENESIS_ONE + +# Hardware Configuration (ESP32-S3-WROOM-1-N8R2) +axiometa_genesis_one.build.usb_mode=1 +axiometa_genesis_one.build.cdc_on_boot=1 +axiometa_genesis_one.build.msc_on_boot=0 +axiometa_genesis_one.build.dfu_on_boot=0 +axiometa_genesis_one.build.f_cpu=240000000L +axiometa_genesis_one.build.flash_size=8MB +axiometa_genesis_one.build.flash_freq=80m +axiometa_genesis_one.build.flash_mode=dio +axiometa_genesis_one.build.boot=qio +axiometa_genesis_one.build.boot_freq=80m +axiometa_genesis_one.build.partitions=default_8MB +axiometa_genesis_one.build.defines=-DBOARD_HAS_PSRAM +axiometa_genesis_one.build.loop_core= +axiometa_genesis_one.build.event_core= +axiometa_genesis_one.build.psram_type=qspi +axiometa_genesis_one.build.memory_type={build.boot}_{build.psram_type} + +## JTAG Adapter - N8R2 Compatible +axiometa_genesis_one.menu.JTAGAdapter.default=Disabled +axiometa_genesis_one.menu.JTAGAdapter.default.build.copy_jtag_files=0 +axiometa_genesis_one.menu.JTAGAdapter.builtin=Integrated USB JTAG +axiometa_genesis_one.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +axiometa_genesis_one.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +axiometa_genesis_one.menu.JTAGAdapter.external=FTDI Adapter +axiometa_genesis_one.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +axiometa_genesis_one.menu.JTAGAdapter.external.build.copy_jtag_files=1 +axiometa_genesis_one.menu.JTAGAdapter.bridge=ESP USB Bridge +axiometa_genesis_one.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +axiometa_genesis_one.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +## PSRAM - N8R2 has 2MB QSPI PSRAM +axiometa_genesis_one.menu.PSRAM.enabled=QSPI PSRAM (Enabled) +axiometa_genesis_one.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +axiometa_genesis_one.menu.PSRAM.enabled.build.psram_type=qspi +axiometa_genesis_one.menu.PSRAM.disabled=Disabled +axiometa_genesis_one.menu.PSRAM.disabled.build.defines= +axiometa_genesis_one.menu.PSRAM.disabled.build.psram_type=qspi + +## Flash Mode - N8R2 Compatible (QSPI Flash) +axiometa_genesis_one.menu.FlashMode.qio=QIO 80MHz +axiometa_genesis_one.menu.FlashMode.qio.build.flash_mode=dio +axiometa_genesis_one.menu.FlashMode.qio.build.boot=qio +axiometa_genesis_one.menu.FlashMode.qio.build.boot_freq=80m +axiometa_genesis_one.menu.FlashMode.qio.build.flash_freq=80m +axiometa_genesis_one.menu.FlashMode.qio120=QIO 120MHz +axiometa_genesis_one.menu.FlashMode.qio120.build.flash_mode=dio +axiometa_genesis_one.menu.FlashMode.qio120.build.boot=qio +axiometa_genesis_one.menu.FlashMode.qio120.build.boot_freq=120m +axiometa_genesis_one.menu.FlashMode.qio120.build.flash_freq=80m +axiometa_genesis_one.menu.FlashMode.dio=DIO 80MHz +axiometa_genesis_one.menu.FlashMode.dio.build.flash_mode=dio +axiometa_genesis_one.menu.FlashMode.dio.build.boot=dio +axiometa_genesis_one.menu.FlashMode.dio.build.boot_freq=80m +axiometa_genesis_one.menu.FlashMode.dio.build.flash_freq=80m + +## CPU Core Assignment +axiometa_genesis_one.menu.LoopCore.1=Core 1 +axiometa_genesis_one.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +axiometa_genesis_one.menu.LoopCore.0=Core 0 +axiometa_genesis_one.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +axiometa_genesis_one.menu.EventsCore.1=Core 1 +axiometa_genesis_one.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +axiometa_genesis_one.menu.EventsCore.0=Core 0 +axiometa_genesis_one.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +## USB Mode - Both modes work on N8R2 +axiometa_genesis_one.menu.USBMode.hwcdc=Hardware CDC and JTAG +axiometa_genesis_one.menu.USBMode.hwcdc.build.usb_mode=1 +axiometa_genesis_one.menu.USBMode.default=USB-OTG (TinyUSB) +axiometa_genesis_one.menu.USBMode.default.build.usb_mode=0 + +## CDC On Boot +axiometa_genesis_one.menu.CDCOnBoot.cdc=Enabled +axiometa_genesis_one.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +axiometa_genesis_one.menu.CDCOnBoot.default=Disabled +axiometa_genesis_one.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +## MSC On Boot (Only works with USB-OTG mode) +axiometa_genesis_one.menu.MSCOnBoot.default=Disabled +axiometa_genesis_one.menu.MSCOnBoot.default.build.msc_on_boot=0 +axiometa_genesis_one.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +axiometa_genesis_one.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +## DFU On Boot (Only works with USB-OTG mode) +axiometa_genesis_one.menu.DFUOnBoot.default=Disabled +axiometa_genesis_one.menu.DFUOnBoot.default.build.dfu_on_boot=0 +axiometa_genesis_one.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +axiometa_genesis_one.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +## Upload Mode +axiometa_genesis_one.menu.UploadMode.default=UART0 / Hardware CDC +axiometa_genesis_one.menu.UploadMode.default.upload.use_1200bps_touch=false +axiometa_genesis_one.menu.UploadMode.default.upload.wait_for_upload_port=false +axiometa_genesis_one.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +axiometa_genesis_one.menu.UploadMode.cdc.upload.use_1200bps_touch=true +axiometa_genesis_one.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +## Partition Schemes - 8MB Flash Compatible +axiometa_genesis_one.menu.PartitionScheme.default_8MB=Default 8MB with spiffs (3MB APP/1.5MB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +axiometa_genesis_one.menu.PartitionScheme.default_8MB.upload.maximum_size=3145728 +axiometa_genesis_one.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.default.build.partitions=default +axiometa_genesis_one.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +axiometa_genesis_one.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +axiometa_genesis_one.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.minimal.build.partitions=minimal +axiometa_genesis_one.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +axiometa_genesis_one.menu.PartitionScheme.no_fs.build.partitions=no_fs +axiometa_genesis_one.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +axiometa_genesis_one.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.no_ota.build.partitions=no_ota +axiometa_genesis_one.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +axiometa_genesis_one.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +axiometa_genesis_one.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +axiometa_genesis_one.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +axiometa_genesis_one.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +axiometa_genesis_one.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +axiometa_genesis_one.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +axiometa_genesis_one.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +axiometa_genesis_one.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +axiometa_genesis_one.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.huge_app.build.partitions=huge_app +axiometa_genesis_one.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +axiometa_genesis_one.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +axiometa_genesis_one.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +axiometa_genesis_one.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +axiometa_genesis_one.menu.PartitionScheme.rainmaker=RainMaker 4MB +axiometa_genesis_one.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +axiometa_genesis_one.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +axiometa_genesis_one.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +axiometa_genesis_one.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +axiometa_genesis_one.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=3145728 +axiometa_genesis_one.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +axiometa_genesis_one.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +axiometa_genesis_one.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +axiometa_genesis_one.menu.PartitionScheme.custom=Custom +axiometa_genesis_one.menu.PartitionScheme.custom.build.partitions= +axiometa_genesis_one.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +## CPU Frequency +axiometa_genesis_one.menu.CPUFreq.240=240MHz (WiFi) +axiometa_genesis_one.menu.CPUFreq.240.build.f_cpu=240000000L +axiometa_genesis_one.menu.CPUFreq.160=160MHz (WiFi) +axiometa_genesis_one.menu.CPUFreq.160.build.f_cpu=160000000L +axiometa_genesis_one.menu.CPUFreq.80=80MHz (WiFi) +axiometa_genesis_one.menu.CPUFreq.80.build.f_cpu=80000000L +axiometa_genesis_one.menu.CPUFreq.40=40MHz +axiometa_genesis_one.menu.CPUFreq.40.build.f_cpu=40000000L +axiometa_genesis_one.menu.CPUFreq.20=20MHz +axiometa_genesis_one.menu.CPUFreq.20.build.f_cpu=20000000L +axiometa_genesis_one.menu.CPUFreq.10=10MHz +axiometa_genesis_one.menu.CPUFreq.10.build.f_cpu=10000000L + +## Upload Speed +axiometa_genesis_one.menu.UploadSpeed.921600=921600 +axiometa_genesis_one.menu.UploadSpeed.921600.upload.speed=921600 +axiometa_genesis_one.menu.UploadSpeed.115200=115200 +axiometa_genesis_one.menu.UploadSpeed.115200.upload.speed=115200 +axiometa_genesis_one.menu.UploadSpeed.256000.windows=256000 +axiometa_genesis_one.menu.UploadSpeed.256000.upload.speed=256000 +axiometa_genesis_one.menu.UploadSpeed.230400.windows.upload.speed=256000 +axiometa_genesis_one.menu.UploadSpeed.230400=230400 +axiometa_genesis_one.menu.UploadSpeed.230400.upload.speed=230400 +axiometa_genesis_one.menu.UploadSpeed.460800.linux=460800 +axiometa_genesis_one.menu.UploadSpeed.460800.macosx=460800 +axiometa_genesis_one.menu.UploadSpeed.460800.upload.speed=460800 +axiometa_genesis_one.menu.UploadSpeed.512000.windows=512000 +axiometa_genesis_one.menu.UploadSpeed.512000.upload.speed=512000 + +## Debug Level +axiometa_genesis_one.menu.DebugLevel.none=None +axiometa_genesis_one.menu.DebugLevel.none.build.code_debug=0 +axiometa_genesis_one.menu.DebugLevel.error=Error +axiometa_genesis_one.menu.DebugLevel.error.build.code_debug=1 +axiometa_genesis_one.menu.DebugLevel.warn=Warn +axiometa_genesis_one.menu.DebugLevel.warn.build.code_debug=2 +axiometa_genesis_one.menu.DebugLevel.info=Info +axiometa_genesis_one.menu.DebugLevel.info.build.code_debug=3 +axiometa_genesis_one.menu.DebugLevel.debug=Debug +axiometa_genesis_one.menu.DebugLevel.debug.build.code_debug=4 +axiometa_genesis_one.menu.DebugLevel.verbose=Verbose +axiometa_genesis_one.menu.DebugLevel.verbose.build.code_debug=5 + +## Erase Flash +axiometa_genesis_one.menu.EraseFlash.none=Disabled +axiometa_genesis_one.menu.EraseFlash.none.upload.erase_cmd= +axiometa_genesis_one.menu.EraseFlash.all=Enabled +axiometa_genesis_one.menu.EraseFlash.all.upload.erase_cmd=-e + +## Zigbee Mode +axiometa_genesis_one.menu.ZigbeeMode.default=Disabled +axiometa_genesis_one.menu.ZigbeeMode.default.build.zigbee_mode= +axiometa_genesis_one.menu.ZigbeeMode.default.build.zigbee_libs= +axiometa_genesis_one.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +axiometa_genesis_one.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +axiometa_genesis_one.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +soldered_nula_deepsleep_esp32s3.name=Soldered NULA DeepSleep ESP32S3 + +soldered_nula_deepsleep_esp32s3.bootloader.tool=esptool_py +soldered_nula_deepsleep_esp32s3.bootloader.tool.default=esptool_py + +soldered_nula_deepsleep_esp32s3.upload.tool=esptool_py +soldered_nula_deepsleep_esp32s3.upload.tool.default=esptool_py +soldered_nula_deepsleep_esp32s3.upload.tool.network=esp_ota + +soldered_nula_deepsleep_esp32s3.upload.maximum_size=1310720 +soldered_nula_deepsleep_esp32s3.upload.maximum_data_size=327680 +soldered_nula_deepsleep_esp32s3.upload.flags= +soldered_nula_deepsleep_esp32s3.upload.extra_flags= +soldered_nula_deepsleep_esp32s3.upload.use_1200bps_touch=false +soldered_nula_deepsleep_esp32s3.upload.wait_for_upload_port=false + +soldered_nula_deepsleep_esp32s3.serial.disableDTR=false +soldered_nula_deepsleep_esp32s3.serial.disableRTS=false + +soldered_nula_deepsleep_esp32s3.build.tarch=xtensa +soldered_nula_deepsleep_esp32s3.build.bootloader_addr=0x0 +soldered_nula_deepsleep_esp32s3.build.target=esp32s3 +soldered_nula_deepsleep_esp32s3.build.mcu=esp32s3 +soldered_nula_deepsleep_esp32s3.build.core=esp32 +soldered_nula_deepsleep_esp32s3.build.variant=soldered_nula_deepsleep_esp32s3 +soldered_nula_deepsleep_esp32s3.build.board=NULA_DEEPSLEEP + +soldered_nula_deepsleep_esp32s3.build.usb_mode=1 +soldered_nula_deepsleep_esp32s3.build.cdc_on_boot=0 +soldered_nula_deepsleep_esp32s3.build.msc_on_boot=0 +soldered_nula_deepsleep_esp32s3.build.dfu_on_boot=0 +soldered_nula_deepsleep_esp32s3.build.f_cpu=240000000L +soldered_nula_deepsleep_esp32s3.build.flash_size=8MB +soldered_nula_deepsleep_esp32s3.build.flash_freq=80m +soldered_nula_deepsleep_esp32s3.build.flash_mode=dio +soldered_nula_deepsleep_esp32s3.build.boot=qio +soldered_nula_deepsleep_esp32s3.build.boot_freq=80m +soldered_nula_deepsleep_esp32s3.build.partitions=default +soldered_nula_deepsleep_esp32s3.build.defines= +soldered_nula_deepsleep_esp32s3.build.loop_core= +soldered_nula_deepsleep_esp32s3.build.event_core= +soldered_nula_deepsleep_esp32s3.build.psram_type=opi +soldered_nula_deepsleep_esp32s3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.default=Disabled +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.external=FTDI Adapter +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +soldered_nula_deepsleep_esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +soldered_nula_deepsleep_esp32s3.menu.PSRAM.enabled=OPI PSRAM +soldered_nula_deepsleep_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +soldered_nula_deepsleep_esp32s3.menu.PSRAM.enabled.build.psram_type=opi +soldered_nula_deepsleep_esp32s3.menu.PSRAM.disabled=disabled +soldered_nula_deepsleep_esp32s3.menu.PSRAM.disabled.build.defines= + +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio=QIO 80MHz +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio.build.flash_mode=dio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio.build.boot=qio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio.build.boot_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio.build.flash_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio120=QIO 120MHz +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio120.build.boot=qio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.dio=DIO 80MHz +soldered_nula_deepsleep_esp32s3.menu.FlashMode.dio.build.flash_mode=dio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.dio.build.boot=dio +soldered_nula_deepsleep_esp32s3.menu.FlashMode.dio.build.boot_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.dio.build.flash_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.opi=OPI 80MHz +soldered_nula_deepsleep_esp32s3.menu.FlashMode.opi.build.flash_mode=dout +soldered_nula_deepsleep_esp32s3.menu.FlashMode.opi.build.boot=opi +soldered_nula_deepsleep_esp32s3.menu.FlashMode.opi.build.boot_freq=80m +soldered_nula_deepsleep_esp32s3.menu.FlashMode.opi.build.flash_freq=80m + +soldered_nula_deepsleep_esp32s3.menu.FlashSize.8M=8MB (64Mb) +soldered_nula_deepsleep_esp32s3.menu.FlashSize.8M.build.flash_size=8MB + +soldered_nula_deepsleep_esp32s3.menu.LoopCore.1=Core 1 +soldered_nula_deepsleep_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +soldered_nula_deepsleep_esp32s3.menu.LoopCore.0=Core 0 +soldered_nula_deepsleep_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +soldered_nula_deepsleep_esp32s3.menu.EventsCore.1=Core 1 +soldered_nula_deepsleep_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +soldered_nula_deepsleep_esp32s3.menu.EventsCore.0=Core 0 +soldered_nula_deepsleep_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +soldered_nula_deepsleep_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG +soldered_nula_deepsleep_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1 +soldered_nula_deepsleep_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB) +soldered_nula_deepsleep_esp32s3.menu.USBMode.default.build.usb_mode=0 + +soldered_nula_deepsleep_esp32s3.menu.CDCOnBoot.default=Disabled +soldered_nula_deepsleep_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0 +soldered_nula_deepsleep_esp32s3.menu.CDCOnBoot.cdc=Enabled +soldered_nula_deepsleep_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +soldered_nula_deepsleep_esp32s3.menu.MSCOnBoot.default=Disabled +soldered_nula_deepsleep_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0 +soldered_nula_deepsleep_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +soldered_nula_deepsleep_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +soldered_nula_deepsleep_esp32s3.menu.DFUOnBoot.default=Disabled +soldered_nula_deepsleep_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +soldered_nula_deepsleep_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +soldered_nula_deepsleep_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +soldered_nula_deepsleep_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC +soldered_nula_deepsleep_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false +soldered_nula_deepsleep_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false +soldered_nula_deepsleep_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +soldered_nula_deepsleep_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +soldered_nula_deepsleep_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.default.build.partitions=default +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_fs.build.partitions=no_fs +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.custom=Custom +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.custom.build.partitions= +soldered_nula_deepsleep_esp32s3.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.240=240MHz (WiFi) +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.160=160MHz (WiFi) +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.80=80MHz (WiFi) +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.40=40MHz +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.20=20MHz +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.10=10MHz +soldered_nula_deepsleep_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L + +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.921600=921600 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.921600.upload.speed=921600 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.115200=115200 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.115200.upload.speed=115200 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.256000.windows=256000 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.256000.upload.speed=256000 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.230400=230400 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.230400.upload.speed=230400 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.460800.linux=460800 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.460800.macosx=460800 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.460800.upload.speed=460800 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.512000.windows=512000 +soldered_nula_deepsleep_esp32s3.menu.UploadSpeed.512000.upload.speed=512000 + +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.none=None +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.none.build.code_debug=0 +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.error=Error +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.error.build.code_debug=1 +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.warn=Warn +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.warn.build.code_debug=2 +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.info=Info +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.info.build.code_debug=3 +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.debug=Debug +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.debug.build.code_debug=4 +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.verbose=Verbose +soldered_nula_deepsleep_esp32s3.menu.DebugLevel.verbose.build.code_debug=5 + +soldered_nula_deepsleep_esp32s3.menu.EraseFlash.none=Disabled +soldered_nula_deepsleep_esp32s3.menu.EraseFlash.none.upload.erase_cmd= +soldered_nula_deepsleep_esp32s3.menu.EraseFlash.all=Enabled +soldered_nula_deepsleep_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e + +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.default=Disabled +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode= +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs= +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +soldered_nula_deepsleep_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +soldered_nula_mini_esp32c6.name=Soldered NULA Mini ESP32C6 + +soldered_nula_mini_esp32c6.bootloader.tool=esptool_py +soldered_nula_mini_esp32c6.bootloader.tool.default=esptool_py + +soldered_nula_mini_esp32c6.upload.tool=esptool_py +soldered_nula_mini_esp32c6.upload.tool.default=esptool_py +soldered_nula_mini_esp32c6.upload.tool.network=esp_ota + +soldered_nula_mini_esp32c6.upload.maximum_size=1310720 +soldered_nula_mini_esp32c6.upload.maximum_data_size=327680 +soldered_nula_mini_esp32c6.upload.flags= +soldered_nula_mini_esp32c6.upload.extra_flags= +soldered_nula_mini_esp32c6.upload.use_1200bps_touch=false +soldered_nula_mini_esp32c6.upload.wait_for_upload_port=false + +soldered_nula_mini_esp32c6.serial.disableDTR=true +soldered_nula_mini_esp32c6.serial.disableRTS=true + +soldered_nula_mini_esp32c6.build.tarch=riscv32 +soldered_nula_mini_esp32c6.build.target=esp +soldered_nula_mini_esp32c6.build.mcu=esp32c6 +soldered_nula_mini_esp32c6.build.core=esp32 +soldered_nula_mini_esp32c6.build.variant=soldered_nula_mini_esp32c6 +soldered_nula_mini_esp32c6.build.board=SOLDERED_NULA_MINI_ESP32C6 +soldered_nula_mini_esp32c6.build.bootloader_addr=0x0 + +soldered_nula_mini_esp32c6.build.f_cpu=160000000L +soldered_nula_mini_esp32c6.build.flash_size=4MB +soldered_nula_mini_esp32c6.build.flash_freq=80m +soldered_nula_mini_esp32c6.build.flash_mode=qio +soldered_nula_mini_esp32c6.build.boot=qio +soldered_nula_mini_esp32c6.build.partitions=default +soldered_nula_mini_esp32c6.build.defines= + +## IDE 2.0 Seems to not update the value +soldered_nula_mini_esp32c6.menu.JTAGAdapter.default=Disabled +soldered_nula_mini_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +soldered_nula_mini_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG +soldered_nula_mini_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +soldered_nula_mini_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +soldered_nula_mini_esp32c6.menu.JTAGAdapter.external=FTDI Adapter +soldered_nula_mini_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +soldered_nula_mini_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +soldered_nula_mini_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge +soldered_nula_mini_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +soldered_nula_mini_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +soldered_nula_mini_esp32c6.menu.CDCOnBoot.default=Disabled +soldered_nula_mini_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +soldered_nula_mini_esp32c6.menu.CDCOnBoot.cdc=Enabled +soldered_nula_mini_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +soldered_nula_mini_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.default.build.partitions=default +soldered_nula_mini_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +soldered_nula_mini_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal +soldered_nula_mini_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota +soldered_nula_mini_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +soldered_nula_mini_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +soldered_nula_mini_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app +soldered_nula_mini_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +soldered_nula_mini_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +soldered_nula_mini_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +soldered_nula_mini_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +soldered_nula_mini_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +soldered_nula_mini_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +soldered_nula_mini_esp32c6.menu.PartitionScheme.custom=Custom +soldered_nula_mini_esp32c6.menu.PartitionScheme.custom.build.partitions= +soldered_nula_mini_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=4194304 + +soldered_nula_mini_esp32c6.menu.CPUFreq.160=160MHz (WiFi) +soldered_nula_mini_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L +soldered_nula_mini_esp32c6.menu.CPUFreq.80=80MHz (WiFi) +soldered_nula_mini_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L +soldered_nula_mini_esp32c6.menu.CPUFreq.40=40MHz +soldered_nula_mini_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L +soldered_nula_mini_esp32c6.menu.CPUFreq.20=20MHz +soldered_nula_mini_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L +soldered_nula_mini_esp32c6.menu.CPUFreq.10=10MHz +soldered_nula_mini_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L + +soldered_nula_mini_esp32c6.menu.FlashMode.qio=QIO +soldered_nula_mini_esp32c6.menu.FlashMode.qio.build.flash_mode=dio +soldered_nula_mini_esp32c6.menu.FlashMode.qio.build.boot=qio +soldered_nula_mini_esp32c6.menu.FlashMode.dio=DIO +soldered_nula_mini_esp32c6.menu.FlashMode.dio.build.flash_mode=dio +soldered_nula_mini_esp32c6.menu.FlashMode.dio.build.boot=dio + +soldered_nula_mini_esp32c6.menu.FlashFreq.80=80MHz +soldered_nula_mini_esp32c6.menu.FlashFreq.80.build.flash_freq=80m +soldered_nula_mini_esp32c6.menu.FlashFreq.40=40MHz +soldered_nula_mini_esp32c6.menu.FlashFreq.40.build.flash_freq=40m + +soldered_nula_mini_esp32c6.menu.FlashSize.4M=4MB (32Mb) +soldered_nula_mini_esp32c6.menu.FlashSize.4M.build.flash_size=4MB + +soldered_nula_mini_esp32c6.menu.UploadSpeed.921600=921600 +soldered_nula_mini_esp32c6.menu.UploadSpeed.921600.upload.speed=921600 +soldered_nula_mini_esp32c6.menu.UploadSpeed.115200=115200 +soldered_nula_mini_esp32c6.menu.UploadSpeed.115200.upload.speed=115200 +soldered_nula_mini_esp32c6.menu.UploadSpeed.256000.windows=256000 +soldered_nula_mini_esp32c6.menu.UploadSpeed.256000.upload.speed=256000 +soldered_nula_mini_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000 +soldered_nula_mini_esp32c6.menu.UploadSpeed.230400=230400 +soldered_nula_mini_esp32c6.menu.UploadSpeed.230400.upload.speed=230400 +soldered_nula_mini_esp32c6.menu.UploadSpeed.460800.linux=460800 +soldered_nula_mini_esp32c6.menu.UploadSpeed.460800.macosx=460800 +soldered_nula_mini_esp32c6.menu.UploadSpeed.460800.upload.speed=460800 +soldered_nula_mini_esp32c6.menu.UploadSpeed.512000.windows=512000 +soldered_nula_mini_esp32c6.menu.UploadSpeed.512000.upload.speed=512000 + +soldered_nula_mini_esp32c6.menu.DebugLevel.none=None +soldered_nula_mini_esp32c6.menu.DebugLevel.none.build.code_debug=0 +soldered_nula_mini_esp32c6.menu.DebugLevel.error=Error +soldered_nula_mini_esp32c6.menu.DebugLevel.error.build.code_debug=1 +soldered_nula_mini_esp32c6.menu.DebugLevel.warn=Warn +soldered_nula_mini_esp32c6.menu.DebugLevel.warn.build.code_debug=2 +soldered_nula_mini_esp32c6.menu.DebugLevel.info=Info +soldered_nula_mini_esp32c6.menu.DebugLevel.info.build.code_debug=3 +soldered_nula_mini_esp32c6.menu.DebugLevel.debug=Debug +soldered_nula_mini_esp32c6.menu.DebugLevel.debug.build.code_debug=4 +soldered_nula_mini_esp32c6.menu.DebugLevel.verbose=Verbose +soldered_nula_mini_esp32c6.menu.DebugLevel.verbose.build.code_debug=5 + +soldered_nula_mini_esp32c6.menu.EraseFlash.none=Disabled +soldered_nula_mini_esp32c6.menu.EraseFlash.none.upload.erase_cmd= +soldered_nula_mini_esp32c6.menu.EraseFlash.all=Enabled +soldered_nula_mini_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e + +soldered_nula_mini_esp32c6.menu.ZigbeeMode.default=Disabled +soldered_nula_mini_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode= +soldered_nula_mini_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs= +soldered_nula_mini_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device) +soldered_nula_mini_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +soldered_nula_mini_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +soldered_nula_mini_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +soldered_nula_mini_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +soldered_nula_mini_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## + +arduino_nesso_n1.name=Arduino Nesso N1 + +arduino_nesso_n1.bootloader.tool=esptool_py +arduino_nesso_n1.bootloader.tool.default=esptool_py + +arduino_nesso_n1.upload.tool=esptool_py +arduino_nesso_n1.upload.tool.default=esptool_py +arduino_nesso_n1.upload.tool.network=esp_ota + +arduino_nesso_n1.upload.maximum_size=1310720 +arduino_nesso_n1.upload.maximum_data_size=327680 +arduino_nesso_n1.upload.flags= +arduino_nesso_n1.upload.extra_flags= +arduino_nesso_n1.upload.use_1200bps_touch=false +arduino_nesso_n1.upload.wait_for_upload_port=false + +arduino_nesso_n1.serial.disableDTR=false +arduino_nesso_n1.serial.disableRTS=false + +arduino_nesso_n1.build.tarch=riscv32 +arduino_nesso_n1.build.target=esp +arduino_nesso_n1.build.mcu=esp32c6 +arduino_nesso_n1.build.core=esp32 +arduino_nesso_n1.build.variant=arduino_nesso_n1 +arduino_nesso_n1.build.board=ARDUINO_NESSO_N1 +arduino_nesso_n1.build.bootloader_addr=0x0 + +arduino_nesso_n1.build.cdc_on_boot=1 +arduino_nesso_n1.build.f_cpu=160000000L +arduino_nesso_n1.build.flash_size=16MB +arduino_nesso_n1.build.flash_freq=80m +arduino_nesso_n1.build.flash_mode=qio +arduino_nesso_n1.build.boot=qio +arduino_nesso_n1.build.partitions=default +arduino_nesso_n1.build.defines= + +## IDE 2.0 Seems to not update the value +arduino_nesso_n1.menu.JTAGAdapter.default=Disabled +arduino_nesso_n1.menu.JTAGAdapter.default.build.copy_jtag_files=0 +arduino_nesso_n1.menu.JTAGAdapter.builtin=Integrated USB JTAG +arduino_nesso_n1.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +arduino_nesso_n1.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +arduino_nesso_n1.menu.JTAGAdapter.external=FTDI Adapter +arduino_nesso_n1.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +arduino_nesso_n1.menu.JTAGAdapter.external.build.copy_jtag_files=1 +arduino_nesso_n1.menu.JTAGAdapter.bridge=ESP USB Bridge +arduino_nesso_n1.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +arduino_nesso_n1.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +arduino_nesso_n1.menu.CDCOnBoot.default=Enabled +arduino_nesso_n1.menu.CDCOnBoot.default.build.cdc_on_boot=1 +arduino_nesso_n1.menu.CDCOnBoot.cdc=Disabled +arduino_nesso_n1.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +arduino_nesso_n1.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +arduino_nesso_n1.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +arduino_nesso_n1.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +arduino_nesso_n1.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +arduino_nesso_n1.menu.PartitionScheme.default.build.partitions=default +arduino_nesso_n1.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +arduino_nesso_n1.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +arduino_nesso_n1.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +arduino_nesso_n1.menu.PartitionScheme.no_ota.build.partitions=no_ota +arduino_nesso_n1.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +arduino_nesso_n1.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +arduino_nesso_n1.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +arduino_nesso_n1.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +arduino_nesso_n1.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +arduino_nesso_n1.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +arduino_nesso_n1.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +arduino_nesso_n1.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +arduino_nesso_n1.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +arduino_nesso_n1.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +arduino_nesso_n1.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +arduino_nesso_n1.menu.PartitionScheme.huge_app.build.partitions=huge_app +arduino_nesso_n1.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +arduino_nesso_n1.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +arduino_nesso_n1.menu.PartitionScheme.zigbee.build.partitions=zigbee +arduino_nesso_n1.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +arduino_nesso_n1.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +arduino_nesso_n1.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +arduino_nesso_n1.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 + +arduino_nesso_n1.menu.CPUFreq.160=160MHz (WiFi) +arduino_nesso_n1.menu.CPUFreq.160.build.f_cpu=160000000L +arduino_nesso_n1.menu.CPUFreq.80=80MHz (WiFi) +arduino_nesso_n1.menu.CPUFreq.80.build.f_cpu=80000000L +arduino_nesso_n1.menu.CPUFreq.40=40MHz +arduino_nesso_n1.menu.CPUFreq.40.build.f_cpu=40000000L +arduino_nesso_n1.menu.CPUFreq.20=20MHz +arduino_nesso_n1.menu.CPUFreq.20.build.f_cpu=20000000L +arduino_nesso_n1.menu.CPUFreq.10=10MHz +arduino_nesso_n1.menu.CPUFreq.10.build.f_cpu=10000000L + +arduino_nesso_n1.menu.FlashMode.qio=QIO +arduino_nesso_n1.menu.FlashMode.qio.build.flash_mode=dio +arduino_nesso_n1.menu.FlashMode.qio.build.boot=qio +arduino_nesso_n1.menu.FlashMode.dio=DIO +arduino_nesso_n1.menu.FlashMode.dio.build.flash_mode=dio +arduino_nesso_n1.menu.FlashMode.dio.build.boot=dio + +arduino_nesso_n1.menu.UploadSpeed.921600=921600 +arduino_nesso_n1.menu.UploadSpeed.921600.upload.speed=921600 +arduino_nesso_n1.menu.UploadSpeed.115200=115200 +arduino_nesso_n1.menu.UploadSpeed.115200.upload.speed=115200 +arduino_nesso_n1.menu.UploadSpeed.256000.windows=256000 +arduino_nesso_n1.menu.UploadSpeed.256000.upload.speed=256000 +arduino_nesso_n1.menu.UploadSpeed.230400.windows.upload.speed=256000 +arduino_nesso_n1.menu.UploadSpeed.230400=230400 +arduino_nesso_n1.menu.UploadSpeed.230400.upload.speed=230400 +arduino_nesso_n1.menu.UploadSpeed.460800.linux=460800 +arduino_nesso_n1.menu.UploadSpeed.460800.macosx=460800 +arduino_nesso_n1.menu.UploadSpeed.460800.upload.speed=460800 +arduino_nesso_n1.menu.UploadSpeed.512000.windows=512000 +arduino_nesso_n1.menu.UploadSpeed.512000.upload.speed=512000 + +arduino_nesso_n1.menu.DebugLevel.none=None +arduino_nesso_n1.menu.DebugLevel.none.build.code_debug=0 +arduino_nesso_n1.menu.DebugLevel.error=Error +arduino_nesso_n1.menu.DebugLevel.error.build.code_debug=1 +arduino_nesso_n1.menu.DebugLevel.warn=Warn +arduino_nesso_n1.menu.DebugLevel.warn.build.code_debug=2 +arduino_nesso_n1.menu.DebugLevel.info=Info +arduino_nesso_n1.menu.DebugLevel.info.build.code_debug=3 +arduino_nesso_n1.menu.DebugLevel.debug=Debug +arduino_nesso_n1.menu.DebugLevel.debug.build.code_debug=4 +arduino_nesso_n1.menu.DebugLevel.verbose=Verbose +arduino_nesso_n1.menu.DebugLevel.verbose.build.code_debug=5 + +arduino_nesso_n1.menu.EraseFlash.none=Disabled +arduino_nesso_n1.menu.EraseFlash.none.upload.erase_cmd= +arduino_nesso_n1.menu.EraseFlash.all=Enabled +arduino_nesso_n1.menu.EraseFlash.all.upload.erase_cmd=-e + +arduino_nesso_n1.menu.ZigbeeMode.default=Disabled +arduino_nesso_n1.menu.ZigbeeMode.default.build.zigbee_mode= +arduino_nesso_n1.menu.ZigbeeMode.default.build.zigbee_libs= +arduino_nesso_n1.menu.ZigbeeMode.ed=Zigbee ED (end device) +arduino_nesso_n1.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +arduino_nesso_n1.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +arduino_nesso_n1.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +arduino_nesso_n1.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +arduino_nesso_n1.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native + +############################################################## +#PandaByte x32 ESP32 + +pandabyte_x32.name=PandaByte x32 - ESP32 + +pandabyte_x32.bootloader.tool=esptool_py +pandabyte_x32.bootloader.tool.default=esptool_py + +pandabyte_x32.upload.tool=esptool_py +pandabyte_x32.upload.tool.default=esptool_py +pandabyte_x32.upload.tool.network=esp_ota + +pandabyte_x32.upload.maximum_size=1310720 +pandabyte_x32.upload.maximum_data_size=327680 +pandabyte_x32.upload.flags= +pandabyte_x32.upload.extra_flags= + +pandabyte_x32.serial.disableDTR=true +pandabyte_x32.serial.disableRTS=true + +pandabyte_x32.build.tarch=xtensa +pandabyte_x32.build.bootloader_addr=0x1000 +pandabyte_x32.build.target=esp32 +pandabyte_x32.build.mcu=esp32 +pandabyte_x32.build.core=esp32 +pandabyte_x32.build.variant=pandabyte_x32 +pandabyte_x32.build.board=PANDABYTE_X32 + +pandabyte_x32.build.f_cpu=240000000L +pandabyte_x32.build.flash_size=4MB +pandabyte_x32.build.flash_freq=40m +pandabyte_x32.build.flash_mode=dio +pandabyte_x32.build.boot=dio +pandabyte_x32.build.partitions=default +pandabyte_x32.build.defines= +pandabyte_x32.build.loop_core= +pandabyte_x32.build.event_core= + +pandabyte_x32.menu.PSRAM.disabled=Disabled +pandabyte_x32.menu.PSRAM.disabled.build.defines= +pandabyte_x32.menu.PSRAM.disabled.build.extra_libs= +pandabyte_x32.menu.PSRAM.enabled=Enabled +pandabyte_x32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw +pandabyte_x32.menu.PSRAM.enabled.build.extra_libs= + +pandabyte_x32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +pandabyte_x32.menu.PartitionScheme.default.build.partitions=default +pandabyte_x32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +pandabyte_x32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +pandabyte_x32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +pandabyte_x32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +pandabyte_x32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +pandabyte_x32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +pandabyte_x32.menu.PartitionScheme.minimal.build.partitions=minimal +pandabyte_x32.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +pandabyte_x32.menu.PartitionScheme.no_fs.build.partitions=no_fs +pandabyte_x32.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +pandabyte_x32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +pandabyte_x32.menu.PartitionScheme.no_ota.build.partitions=no_ota +pandabyte_x32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pandabyte_x32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +pandabyte_x32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +pandabyte_x32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +pandabyte_x32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +pandabyte_x32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +pandabyte_x32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +pandabyte_x32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +pandabyte_x32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +pandabyte_x32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +pandabyte_x32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +pandabyte_x32.menu.PartitionScheme.huge_app.build.partitions=huge_app +pandabyte_x32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +pandabyte_x32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +pandabyte_x32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pandabyte_x32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +pandabyte_x32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +pandabyte_x32.menu.PartitionScheme.fatflash.build.partitions=ffat +pandabyte_x32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +pandabyte_x32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +pandabyte_x32.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +pandabyte_x32.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +pandabyte_x32.menu.PartitionScheme.rainmaker=RainMaker 4MB +pandabyte_x32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +pandabyte_x32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +pandabyte_x32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +pandabyte_x32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +pandabyte_x32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +pandabyte_x32.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +pandabyte_x32.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +pandabyte_x32.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +pandabyte_x32.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +pandabyte_x32.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +pandabyte_x32.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +pandabyte_x32.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +pandabyte_x32.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +pandabyte_x32.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +pandabyte_x32.menu.PartitionScheme.custom=Custom +pandabyte_x32.menu.PartitionScheme.custom.build.partitions= +pandabyte_x32.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +pandabyte_x32.menu.CPUFreq.240=240MHz (WiFi/BT) +pandabyte_x32.menu.CPUFreq.240.build.f_cpu=240000000L +pandabyte_x32.menu.CPUFreq.160=160MHz (WiFi/BT) +pandabyte_x32.menu.CPUFreq.160.build.f_cpu=160000000L +pandabyte_x32.menu.CPUFreq.80=80MHz (WiFi/BT) +pandabyte_x32.menu.CPUFreq.80.build.f_cpu=80000000L +pandabyte_x32.menu.CPUFreq.40=40MHz (40MHz XTAL) +pandabyte_x32.menu.CPUFreq.40.build.f_cpu=40000000L +pandabyte_x32.menu.CPUFreq.26=26MHz (26MHz XTAL) +pandabyte_x32.menu.CPUFreq.26.build.f_cpu=26000000L +pandabyte_x32.menu.CPUFreq.20=20MHz (40MHz XTAL) +pandabyte_x32.menu.CPUFreq.20.build.f_cpu=20000000L +pandabyte_x32.menu.CPUFreq.13=13MHz (26MHz XTAL) +pandabyte_x32.menu.CPUFreq.13.build.f_cpu=13000000L +pandabyte_x32.menu.CPUFreq.10=10MHz (40MHz XTAL) +pandabyte_x32.menu.CPUFreq.10.build.f_cpu=10000000L + +pandabyte_x32.menu.FlashMode.qio=QIO +pandabyte_x32.menu.FlashMode.qio.build.flash_mode=dio +pandabyte_x32.menu.FlashMode.qio.build.boot=qio +pandabyte_x32.menu.FlashMode.dio=DIO +pandabyte_x32.menu.FlashMode.dio.build.flash_mode=dio +pandabyte_x32.menu.FlashMode.dio.build.boot=dio + +pandabyte_x32.menu.FlashFreq.80=80MHz +pandabyte_x32.menu.FlashFreq.80.build.flash_freq=80m +pandabyte_x32.menu.FlashFreq.40=40MHz +pandabyte_x32.menu.FlashFreq.40.build.flash_freq=40m + +pandabyte_x32.menu.FlashSize.4M=4MB (32Mb) +pandabyte_x32.menu.FlashSize.4M.build.flash_size=4MB +pandabyte_x32.menu.FlashSize.8M=8MB (64Mb) +pandabyte_x32.menu.FlashSize.8M.build.flash_size=8MB +pandabyte_x32.menu.FlashSize.2M=2MB (16Mb) +pandabyte_x32.menu.FlashSize.2M.build.flash_size=2MB +pandabyte_x32.menu.FlashSize.16M=16MB (128Mb) +pandabyte_x32.menu.FlashSize.16M.build.flash_size=16MB + +pandabyte_x32.menu.UploadSpeed.921600=921600 +pandabyte_x32.menu.UploadSpeed.921600.upload.speed=921600 +pandabyte_x32.menu.UploadSpeed.115200=115200 +pandabyte_x32.menu.UploadSpeed.115200.upload.speed=115200 +pandabyte_x32.menu.UploadSpeed.256000.windows=256000 +pandabyte_x32.menu.UploadSpeed.256000.upload.speed=256000 +pandabyte_x32.menu.UploadSpeed.230400.windows.upload.speed=256000 +pandabyte_x32.menu.UploadSpeed.230400=230400 +pandabyte_x32.menu.UploadSpeed.230400.upload.speed=230400 +pandabyte_x32.menu.UploadSpeed.460800.linux=460800 +pandabyte_x32.menu.UploadSpeed.460800.macosx=460800 +pandabyte_x32.menu.UploadSpeed.460800.upload.speed=460800 +pandabyte_x32.menu.UploadSpeed.512000.windows=512000 +pandabyte_x32.menu.UploadSpeed.512000.upload.speed=512000 + +pandabyte_x32.menu.LoopCore.1=Core 1 +pandabyte_x32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +pandabyte_x32.menu.LoopCore.0=Core 0 +pandabyte_x32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +pandabyte_x32.menu.EventsCore.1=Core 1 +pandabyte_x32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +pandabyte_x32.menu.EventsCore.0=Core 0 +pandabyte_x32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +pandabyte_x32.menu.DebugLevel.none=None +pandabyte_x32.menu.DebugLevel.none.build.code_debug=0 +pandabyte_x32.menu.DebugLevel.error=Error +pandabyte_x32.menu.DebugLevel.error.build.code_debug=1 +pandabyte_x32.menu.DebugLevel.warn=Warn +pandabyte_x32.menu.DebugLevel.warn.build.code_debug=2 +pandabyte_x32.menu.DebugLevel.info=Info +pandabyte_x32.menu.DebugLevel.info.build.code_debug=3 +pandabyte_x32.menu.DebugLevel.debug=Debug +pandabyte_x32.menu.DebugLevel.debug.build.code_debug=4 +pandabyte_x32.menu.DebugLevel.verbose=Verbose +pandabyte_x32.menu.DebugLevel.verbose.build.code_debug=5 + +pandabyte_x32.menu.EraseFlash.none=Disabled +pandabyte_x32.menu.EraseFlash.none.upload.erase_cmd= +pandabyte_x32.menu.EraseFlash.all=Enabled +pandabyte_x32.menu.EraseFlash.all.upload.erase_cmd=-e + +pandabyte_x32.menu.ZigbeeMode.default=Disabled +pandabyte_x32.menu.ZigbeeMode.default.build.zigbee_mode= +pandabyte_x32.menu.ZigbeeMode.default.build.zigbee_libs= +pandabyte_x32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +pandabyte_x32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_x32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + + + +############################################################## +# PandaByte xC3m ESP32C3 + +pandabyte_xc3m.name=Pandabyte xC3m - ESP32C3 + +pandabyte_xc3m.bootloader.tool=esptool_py +pandabyte_xc3m.bootloader.tool.default=esptool_py + +pandabyte_xc3m.upload.tool=esptool_py +pandabyte_xc3m.upload.tool.default=esptool_py +pandabyte_xc3m.upload.tool.network=esp_ota + +pandabyte_xc3m.upload.maximum_size=1310720 +pandabyte_xc3m.upload.maximum_data_size=327680 +pandabyte_xc3m.upload.flags= +pandabyte_xc3m.upload.extra_flags= +pandabyte_xc3m.upload.use_1200bps_touch=false +pandabyte_xc3m.upload.wait_for_upload_port=false + +pandabyte_xc3m.serial.disableDTR=false +pandabyte_xc3m.serial.disableRTS=false + +pandabyte_xc3m.build.tarch=riscv32 +pandabyte_xc3m.build.bootloader_addr=0x0 +pandabyte_xc3m.build.target=esp +pandabyte_xc3m.build.mcu=esp32c3 +pandabyte_xc3m.build.core=esp32 +pandabyte_xc3m.build.variant=pandabyte_xc3m +pandabyte_xc3m.build.board=PANDABYTE_XC3M + +pandabyte_xc3m.build.cdc_on_boot=1 +pandabyte_xc3m.build.f_cpu=160000000L +pandabyte_xc3m.build.flash_size=4MB +pandabyte_xc3m.build.flash_freq=80m +pandabyte_xc3m.build.flash_mode=dio +pandabyte_xc3m.build.boot=qio +pandabyte_xc3m.build.partitions=default +pandabyte_xc3m.build.defines= + +pandabyte_xc3m.menu.CDCOnBoot.cdc=Enabled +pandabyte_xc3m.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 +pandabyte_xc3m.menu.CDCOnBoot.default=Enabled +pandabyte_xc3m.menu.CDCOnBoot.default.build.cdc_on_boot=0 + +pandabyte_xc3m.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.default.build.partitions=default +pandabyte_xc3m.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +pandabyte_xc3m.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +pandabyte_xc3m.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.minimal.build.partitions=minimal +pandabyte_xc3m.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.no_ota.build.partitions=no_ota +pandabyte_xc3m.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pandabyte_xc3m.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +pandabyte_xc3m.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +pandabyte_xc3m.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +pandabyte_xc3m.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +pandabyte_xc3m.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +pandabyte_xc3m.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +pandabyte_xc3m.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +pandabyte_xc3m.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +pandabyte_xc3m.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.huge_app.build.partitions=huge_app +pandabyte_xc3m.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +pandabyte_xc3m.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +pandabyte_xc3m.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pandabyte_xc3m.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 + +pandabyte_xc3m.menu.CPUFreq.160=160MHz (WiFi) +pandabyte_xc3m.menu.CPUFreq.160.build.f_cpu=160000000L +pandabyte_xc3m.menu.CPUFreq.80=80MHz (WiFi) +pandabyte_xc3m.menu.CPUFreq.80.build.f_cpu=80000000L +pandabyte_xc3m.menu.CPUFreq.40=40MHz +pandabyte_xc3m.menu.CPUFreq.40.build.f_cpu=40000000L +pandabyte_xc3m.menu.CPUFreq.20=20MHz +pandabyte_xc3m.menu.CPUFreq.20.build.f_cpu=20000000L +pandabyte_xc3m.menu.CPUFreq.10=10MHz +pandabyte_xc3m.menu.CPUFreq.10.build.f_cpu=10000000L + +pandabyte_xc3m.menu.FlashMode.qio=QIO +pandabyte_xc3m.menu.FlashMode.qio.build.flash_mode=dio +pandabyte_xc3m.menu.FlashMode.qio.build.boot=qio +pandabyte_xc3m.menu.FlashMode.dio=DIO +pandabyte_xc3m.menu.FlashMode.dio.build.flash_mode=dio +pandabyte_xc3m.menu.FlashMode.dio.build.boot=dio +pandabyte_xc3m.menu.FlashMode.qout=QOUT +pandabyte_xc3m.menu.FlashMode.qout.build.flash_mode=dout +pandabyte_xc3m.menu.FlashMode.qout.build.boot=qout +pandabyte_xc3m.menu.FlashMode.dout=DOUT +pandabyte_xc3m.menu.FlashMode.dout.build.flash_mode=dout +pandabyte_xc3m.menu.FlashMode.dout.build.boot=dout + +pandabyte_xc3m.menu.FlashFreq.80=80MHz +pandabyte_xc3m.menu.FlashFreq.80.build.flash_freq=80m +pandabyte_xc3m.menu.FlashFreq.40=40MHz +pandabyte_xc3m.menu.FlashFreq.40.build.flash_freq=40m + +pandabyte_xc3m.menu.FlashSize.4M=4MB (32Mb) +pandabyte_xc3m.menu.FlashSize.4M.build.flash_size=4MB + +pandabyte_xc3m.menu.UploadSpeed.921600=921600 +pandabyte_xc3m.menu.UploadSpeed.921600.upload.speed=921600 +pandabyte_xc3m.menu.UploadSpeed.115200=115200 +pandabyte_xc3m.menu.UploadSpeed.115200.upload.speed=115200 +pandabyte_xc3m.menu.UploadSpeed.256000.windows=256000 +pandabyte_xc3m.menu.UploadSpeed.256000.upload.speed=256000 +pandabyte_xc3m.menu.UploadSpeed.230400.windows.upload.speed=256000 +pandabyte_xc3m.menu.UploadSpeed.230400=230400 +pandabyte_xc3m.menu.UploadSpeed.230400.upload.speed=230400 +pandabyte_xc3m.menu.UploadSpeed.460800.linux=460800 +pandabyte_xc3m.menu.UploadSpeed.460800.macosx=460800 +pandabyte_xc3m.menu.UploadSpeed.460800.upload.speed=460800 +pandabyte_xc3m.menu.UploadSpeed.512000.windows=512000 +pandabyte_xc3m.menu.UploadSpeed.512000.upload.speed=512000 + +pandabyte_xc3m.menu.DebugLevel.none=None +pandabyte_xc3m.menu.DebugLevel.none.build.code_debug=0 +pandabyte_xc3m.menu.DebugLevel.error=Error +pandabyte_xc3m.menu.DebugLevel.error.build.code_debug=1 +pandabyte_xc3m.menu.DebugLevel.warn=Warn +pandabyte_xc3m.menu.DebugLevel.warn.build.code_debug=2 +pandabyte_xc3m.menu.DebugLevel.info=Info +pandabyte_xc3m.menu.DebugLevel.info.build.code_debug=3 +pandabyte_xc3m.menu.DebugLevel.debug=Debug +pandabyte_xc3m.menu.DebugLevel.debug.build.code_debug=4 +pandabyte_xc3m.menu.DebugLevel.verbose=Verbose +pandabyte_xc3m.menu.DebugLevel.verbose.build.code_debug=5 + +pandabyte_xc3m.menu.EraseFlash.none=Disabled +pandabyte_xc3m.menu.EraseFlash.none.upload.erase_cmd= +pandabyte_xc3m.menu.EraseFlash.all=Enabled +pandabyte_xc3m.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## +# PandaByte xC5 ESP32C5 +pandabyte_xc5.name=Pandabyte xC5 - ESP32C5 + +pandabyte_xc5.bootloader.tool=esptool_py +pandabyte_xc5.bootloader.tool.default=esptool_py + +pandabyte_xc5.upload.tool=esptool_py +pandabyte_xc5.upload.tool.default=esptool_py +pandabyte_xc5.upload.tool.network=esp_ota + +pandabyte_xc5.upload.maximum_size=1310720 +pandabyte_xc5.upload.maximum_data_size=327680 +pandabyte_xc5.upload.flags= +pandabyte_xc5.upload.extra_flags= +pandabyte_xc5.upload.use_1200bps_touch=false +pandabyte_xc5.upload.wait_for_upload_port=false + +pandabyte_xc5.serial.disableDTR=false +pandabyte_xc5.serial.disableRTS=false + +pandabyte_xc5.build.tarch=riscv32 +pandabyte_xc5.build.target=esp +pandabyte_xc5.build.mcu=esp32c5 +pandabyte_xc5.build.core=esp32 +pandabyte_xc5.build.variant=pandabyte_xc5 +pandabyte_xc5.build.board=PANDABYTE_XC5 +pandabyte_xc5.build.bootloader_addr=0x2000 + +pandabyte_xc5.build.cdc_on_boot=1 +pandabyte_xc5.build.f_cpu=240000000L +pandabyte_xc5.build.flash_size=4MB +pandabyte_xc5.build.flash_freq=80m +pandabyte_xc5.build.flash_mode=qio +pandabyte_xc5.build.boot=qio +pandabyte_xc5.build.partitions=default +pandabyte_xc5.build.defines= + +## IDE 2.0 Seems to not update the value +pandabyte_xc5.menu.JTAGAdapter.default=Disabled +pandabyte_xc5.menu.JTAGAdapter.default.build.copy_jtag_files=0 +pandabyte_xc5.menu.JTAGAdapter.builtin=Integrated USB JTAG +pandabyte_xc5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg +pandabyte_xc5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +pandabyte_xc5.menu.JTAGAdapter.external=FTDI Adapter +pandabyte_xc5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg +pandabyte_xc5.menu.JTAGAdapter.external.build.copy_jtag_files=1 +pandabyte_xc5.menu.JTAGAdapter.bridge=ESP USB Bridge +pandabyte_xc5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg +pandabyte_xc5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +pandabyte_xc5.menu.PSRAM.disabled=Disabled +pandabyte_xc5.menu.PSRAM.disabled.build.defines= +pandabyte_xc5.menu.PSRAM.enabled=Enabled +pandabyte_xc5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +pandabyte_xc5.menu.CDCOnBoot.default=Enabled +pandabyte_xc5.menu.CDCOnBoot.default.build.cdc_on_boot=1 +pandabyte_xc5.menu.CDCOnBoot.cdc=Enabled +pandabyte_xc5.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +pandabyte_xc5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.default.build.partitions=default +pandabyte_xc5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +pandabyte_xc5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +pandabyte_xc5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +pandabyte_xc5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +pandabyte_xc5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.minimal.build.partitions=minimal +pandabyte_xc5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +pandabyte_xc5.menu.PartitionScheme.no_fs.build.partitions=no_fs +pandabyte_xc5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +pandabyte_xc5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.no_ota.build.partitions=no_ota +pandabyte_xc5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pandabyte_xc5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +pandabyte_xc5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +pandabyte_xc5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +pandabyte_xc5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +pandabyte_xc5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +pandabyte_xc5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +pandabyte_xc5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +pandabyte_xc5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +pandabyte_xc5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.huge_app.build.partitions=huge_app +pandabyte_xc5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +pandabyte_xc5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +pandabyte_xc5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pandabyte_xc5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +pandabyte_xc5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +pandabyte_xc5.menu.PartitionScheme.fatflash.build.partitions=ffat +pandabyte_xc5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +pandabyte_xc5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +pandabyte_xc5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +pandabyte_xc5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +pandabyte_xc5.menu.PartitionScheme.rainmaker=RainMaker 4MB +pandabyte_xc5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +pandabyte_xc5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +pandabyte_xc5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +pandabyte_xc5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +pandabyte_xc5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +pandabyte_xc5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +pandabyte_xc5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +pandabyte_xc5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480 +pandabyte_xc5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB +pandabyte_xc5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720 +pandabyte_xc5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee.build.partitions=zigbee +pandabyte_xc5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +pandabyte_xc5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +pandabyte_xc5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720 +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +pandabyte_xc5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +pandabyte_xc5.menu.PartitionScheme.custom=Custom +pandabyte_xc5.menu.PartitionScheme.custom.build.partitions= +pandabyte_xc5.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +pandabyte_xc5.menu.CPUFreq.240=240MHz (WiFi) +pandabyte_xc5.menu.CPUFreq.240.build.f_cpu=240000000L +pandabyte_xc5.menu.CPUFreq.120=120MHz (WiFi) +pandabyte_xc5.menu.CPUFreq.120.build.f_cpu=120000000L +pandabyte_xc5.menu.CPUFreq.80=80MHz (WiFi) +pandabyte_xc5.menu.CPUFreq.80.build.f_cpu=80000000L +pandabyte_xc5.menu.CPUFreq.40=40MHz +pandabyte_xc5.menu.CPUFreq.40.build.f_cpu=40000000L +pandabyte_xc5.menu.CPUFreq.20=20MHz +pandabyte_xc5.menu.CPUFreq.20.build.f_cpu=20000000L +pandabyte_xc5.menu.CPUFreq.10=10MHz +pandabyte_xc5.menu.CPUFreq.10.build.f_cpu=10000000L + +pandabyte_xc5.menu.FlashMode.qio=QIO +pandabyte_xc5.menu.FlashMode.qio.build.flash_mode=dio +pandabyte_xc5.menu.FlashMode.qio.build.boot=qio +pandabyte_xc5.menu.FlashMode.dio=DIO +pandabyte_xc5.menu.FlashMode.dio.build.flash_mode=dio +pandabyte_xc5.menu.FlashMode.dio.build.boot=dio + +pandabyte_xc5.menu.FlashFreq.80=80MHz +pandabyte_xc5.menu.FlashFreq.80.build.flash_freq=80m +pandabyte_xc5.menu.FlashFreq.40=40MHz +pandabyte_xc5.menu.FlashFreq.40.build.flash_freq=40m + +pandabyte_xc5.menu.FlashSize.4M=4MB (32Mb) +pandabyte_xc5.menu.FlashSize.4M.build.flash_size=4MB +pandabyte_xc5.menu.FlashSize.8M=8MB (64Mb) +pandabyte_xc5.menu.FlashSize.8M.build.flash_size=8MB +pandabyte_xc5.menu.FlashSize.2M=2MB (16Mb) +pandabyte_xc5.menu.FlashSize.2M.build.flash_size=2MB +pandabyte_xc5.menu.FlashSize.16M=16MB (128Mb) +pandabyte_xc5.menu.FlashSize.16M.build.flash_size=16MB + +pandabyte_xc5.menu.UploadSpeed.921600=921600 +pandabyte_xc5.menu.UploadSpeed.921600.upload.speed=921600 +pandabyte_xc5.menu.UploadSpeed.115200=115200 +pandabyte_xc5.menu.UploadSpeed.115200.upload.speed=115200 +pandabyte_xc5.menu.UploadSpeed.256000.windows=256000 +pandabyte_xc5.menu.UploadSpeed.256000.upload.speed=256000 +pandabyte_xc5.menu.UploadSpeed.230400.windows.upload.speed=256000 +pandabyte_xc5.menu.UploadSpeed.230400=230400 +pandabyte_xc5.menu.UploadSpeed.230400.upload.speed=230400 +pandabyte_xc5.menu.UploadSpeed.460800.linux=460800 +pandabyte_xc5.menu.UploadSpeed.460800.macosx=460800 +pandabyte_xc5.menu.UploadSpeed.460800.upload.speed=460800 +pandabyte_xc5.menu.UploadSpeed.512000.windows=512000 +pandabyte_xc5.menu.UploadSpeed.512000.upload.speed=512000 + +pandabyte_xc5.menu.DebugLevel.none=None +pandabyte_xc5.menu.DebugLevel.none.build.code_debug=0 +pandabyte_xc5.menu.DebugLevel.error=Error +pandabyte_xc5.menu.DebugLevel.error.build.code_debug=1 +pandabyte_xc5.menu.DebugLevel.warn=Warn +pandabyte_xc5.menu.DebugLevel.warn.build.code_debug=2 +pandabyte_xc5.menu.DebugLevel.info=Info +pandabyte_xc5.menu.DebugLevel.info.build.code_debug=3 +pandabyte_xc5.menu.DebugLevel.debug=Debug +pandabyte_xc5.menu.DebugLevel.debug.build.code_debug=4 +pandabyte_xc5.menu.DebugLevel.verbose=Verbose +pandabyte_xc5.menu.DebugLevel.verbose.build.code_debug=5 + +pandabyte_xc5.menu.EraseFlash.none=Disabled +pandabyte_xc5.menu.EraseFlash.none.upload.erase_cmd= +pandabyte_xc5.menu.EraseFlash.all=Enabled +pandabyte_xc5.menu.EraseFlash.all.upload.erase_cmd=-e + +pandabyte_xc5.menu.ZigbeeMode.default=Disabled +pandabyte_xc5.menu.ZigbeeMode.default.build.zigbee_mode= +pandabyte_xc5.menu.ZigbeeMode.default.build.zigbee_libs= +pandabyte_xc5.menu.ZigbeeMode.ed=Zigbee ED (end device) +pandabyte_xc5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +pandabyte_xc5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +pandabyte_xc5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +pandabyte_xc5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_xc5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +pandabyte_xc5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +pandabyte_xc5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +pandabyte_xc5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +pandabyte_xc5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +pandabyte_xc5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_xc5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## +# PandaByte xC6 ESP32C6 +pandabyte_xc6.name=PandaByte xC6 - ESP32C6 + +pandabyte_xc6.bootloader.tool=esptool_py +pandabyte_xc6.bootloader.tool.default=esptool_py + +pandabyte_xc6.upload.tool=esptool_py +pandabyte_xc6.upload.tool.default=esptool_py +pandabyte_xc6.upload.tool.network=esp_ota + +pandabyte_xc6.upload.maximum_size=1310720 +pandabyte_xc6.upload.maximum_data_size=327680 +pandabyte_xc6.upload.flags= +pandabyte_xc6.upload.extra_flags= +pandabyte_xc6.upload.use_1200bps_touch=false +pandabyte_xc6.upload.wait_for_upload_port=false + +pandabyte_xc6.serial.disableDTR=false +pandabyte_xc6.serial.disableRTS=false + +pandabyte_xc6.build.tarch=riscv32 +pandabyte_xc6.build.target=esp +pandabyte_xc6.build.mcu=esp32c6 +pandabyte_xc6.build.core=esp32 +pandabyte_xc6.build.variant=pandabyte_xc6 +pandabyte_xc6.build.board=PANDABYTE_XC6 +pandabyte_xc6.build.bootloader_addr=0x0 + +pandabyte_xc6.build.cdc_on_boot=0 +pandabyte_xc6.build.f_cpu=160000000L +pandabyte_xc6.build.flash_size=4MB +pandabyte_xc6.build.flash_freq=80m +pandabyte_xc6.build.flash_mode=qio +pandabyte_xc6.build.boot=qio +pandabyte_xc6.build.partitions=default +pandabyte_xc6.build.defines= + +## IDE 2.0 Seems to not update the value +pandabyte_xc6.menu.JTAGAdapter.default=Disabled +pandabyte_xc6.menu.JTAGAdapter.default.build.copy_jtag_files=0 +pandabyte_xc6.menu.JTAGAdapter.builtin=Integrated USB JTAG +pandabyte_xc6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg +pandabyte_xc6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +pandabyte_xc6.menu.JTAGAdapter.external=FTDI Adapter +pandabyte_xc6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg +pandabyte_xc6.menu.JTAGAdapter.external.build.copy_jtag_files=1 +pandabyte_xc6.menu.JTAGAdapter.bridge=ESP USB Bridge +pandabyte_xc6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg +pandabyte_xc6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +pandabyte_xc6.menu.CDCOnBoot.default=Disabled +pandabyte_xc6.menu.CDCOnBoot.default.build.cdc_on_boot=0 +pandabyte_xc6.menu.CDCOnBoot.cdc=Enabled +pandabyte_xc6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +pandabyte_xc6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.default.build.partitions=default +pandabyte_xc6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +pandabyte_xc6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +pandabyte_xc6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +pandabyte_xc6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +pandabyte_xc6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.minimal.build.partitions=minimal +pandabyte_xc6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +pandabyte_xc6.menu.PartitionScheme.no_fs.build.partitions=no_fs +pandabyte_xc6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +pandabyte_xc6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.no_ota.build.partitions=no_ota +pandabyte_xc6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pandabyte_xc6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +pandabyte_xc6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +pandabyte_xc6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +pandabyte_xc6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +pandabyte_xc6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +pandabyte_xc6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +pandabyte_xc6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +pandabyte_xc6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +pandabyte_xc6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.huge_app.build.partitions=huge_app +pandabyte_xc6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +pandabyte_xc6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +pandabyte_xc6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pandabyte_xc6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +pandabyte_xc6.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +pandabyte_xc6.menu.PartitionScheme.fatflash.build.partitions=ffat +pandabyte_xc6.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +pandabyte_xc6.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +pandabyte_xc6.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +pandabyte_xc6.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +pandabyte_xc6.menu.PartitionScheme.rainmaker=RainMaker 4MB +pandabyte_xc6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +pandabyte_xc6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +pandabyte_xc6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +pandabyte_xc6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +pandabyte_xc6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +pandabyte_xc6.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +pandabyte_xc6.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +pandabyte_xc6.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +pandabyte_xc6.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB +pandabyte_xc6.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720 +pandabyte_xc6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee.build.partitions=zigbee +pandabyte_xc6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720 +pandabyte_xc6.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB +pandabyte_xc6.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872 +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720 +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +pandabyte_xc6.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +pandabyte_xc6.menu.PartitionScheme.custom=Custom +pandabyte_xc6.menu.PartitionScheme.custom.build.partitions= +pandabyte_xc6.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +pandabyte_xc6.menu.CPUFreq.160=160MHz (WiFi) +pandabyte_xc6.menu.CPUFreq.160.build.f_cpu=160000000L +pandabyte_xc6.menu.CPUFreq.120=120MHz (WiFi) +pandabyte_xc6.menu.CPUFreq.120.build.f_cpu=120000000L +pandabyte_xc6.menu.CPUFreq.80=80MHz (WiFi) +pandabyte_xc6.menu.CPUFreq.80.build.f_cpu=80000000L +pandabyte_xc6.menu.CPUFreq.40=40MHz +pandabyte_xc6.menu.CPUFreq.40.build.f_cpu=40000000L +pandabyte_xc6.menu.CPUFreq.20=20MHz +pandabyte_xc6.menu.CPUFreq.20.build.f_cpu=20000000L +pandabyte_xc6.menu.CPUFreq.10=10MHz +pandabyte_xc6.menu.CPUFreq.10.build.f_cpu=10000000L + +pandabyte_xc6.menu.FlashMode.qio=QIO +pandabyte_xc6.menu.FlashMode.qio.build.flash_mode=dio +pandabyte_xc6.menu.FlashMode.qio.build.boot=qio +pandabyte_xc6.menu.FlashMode.dio=DIO +pandabyte_xc6.menu.FlashMode.dio.build.flash_mode=dio +pandabyte_xc6.menu.FlashMode.dio.build.boot=dio + +pandabyte_xc6.menu.FlashFreq.80=80MHz +pandabyte_xc6.menu.FlashFreq.80.build.flash_freq=80m +pandabyte_xc6.menu.FlashFreq.40=40MHz +pandabyte_xc6.menu.FlashFreq.40.build.flash_freq=40m + +pandabyte_xc6.menu.FlashSize.4M=4MB (32Mb) +pandabyte_xc6.menu.FlashSize.4M.build.flash_size=4MB +pandabyte_xc6.menu.FlashSize.8M=8MB (64Mb) +pandabyte_xc6.menu.FlashSize.8M.build.flash_size=8MB +pandabyte_xc6.menu.FlashSize.2M=2MB (16Mb) +pandabyte_xc6.menu.FlashSize.2M.build.flash_size=2MB +pandabyte_xc6.menu.FlashSize.16M=16MB (128Mb) +pandabyte_xc6.menu.FlashSize.16M.build.flash_size=16MB + +pandabyte_xc6.menu.UploadSpeed.921600=921600 +pandabyte_xc6.menu.UploadSpeed.921600.upload.speed=921600 +pandabyte_xc6.menu.UploadSpeed.115200=115200 +pandabyte_xc6.menu.UploadSpeed.115200.upload.speed=115200 +pandabyte_xc6.menu.UploadSpeed.256000.windows=256000 +pandabyte_xc6.menu.UploadSpeed.256000.upload.speed=256000 +pandabyte_xc6.menu.UploadSpeed.230400.windows.upload.speed=256000 +pandabyte_xc6.menu.UploadSpeed.230400=230400 +pandabyte_xc6.menu.UploadSpeed.230400.upload.speed=230400 +pandabyte_xc6.menu.UploadSpeed.460800.linux=460800 +pandabyte_xc6.menu.UploadSpeed.460800.macosx=460800 +pandabyte_xc6.menu.UploadSpeed.460800.upload.speed=460800 +pandabyte_xc6.menu.UploadSpeed.512000.windows=512000 +pandabyte_xc6.menu.UploadSpeed.512000.upload.speed=512000 + +pandabyte_xc6.menu.DebugLevel.none=None +pandabyte_xc6.menu.DebugLevel.none.build.code_debug=0 +pandabyte_xc6.menu.DebugLevel.error=Error +pandabyte_xc6.menu.DebugLevel.error.build.code_debug=1 +pandabyte_xc6.menu.DebugLevel.warn=Warn +pandabyte_xc6.menu.DebugLevel.warn.build.code_debug=2 +pandabyte_xc6.menu.DebugLevel.info=Info +pandabyte_xc6.menu.DebugLevel.info.build.code_debug=3 +pandabyte_xc6.menu.DebugLevel.debug=Debug +pandabyte_xc6.menu.DebugLevel.debug.build.code_debug=4 +pandabyte_xc6.menu.DebugLevel.verbose=Verbose +pandabyte_xc6.menu.DebugLevel.verbose.build.code_debug=5 + +pandabyte_xc6.menu.EraseFlash.none=Disabled +pandabyte_xc6.menu.EraseFlash.none.upload.erase_cmd= +pandabyte_xc6.menu.EraseFlash.all=Enabled +pandabyte_xc6.menu.EraseFlash.all.upload.erase_cmd=-e + +pandabyte_xc6.menu.ZigbeeMode.default=Disabled +pandabyte_xc6.menu.ZigbeeMode.default.build.zigbee_mode= +pandabyte_xc6.menu.ZigbeeMode.default.build.zigbee_libs= +pandabyte_xc6.menu.ZigbeeMode.ed=Zigbee ED (end device) +pandabyte_xc6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED +pandabyte_xc6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native +pandabyte_xc6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +pandabyte_xc6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_xc6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native +pandabyte_xc6.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug +pandabyte_xc6.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED +pandabyte_xc6.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug +pandabyte_xc6.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug +pandabyte_xc6.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_xc6.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug + +############################################################## +#PandaByte xS3 ESP32S3 + +pandabyte_xs3.name=PandaByte xS3 - ESP32S3 + +pandabyte_xs3.bootloader.tool=esptool_py +pandabyte_xs3.bootloader.tool.default=esptool_py + +pandabyte_xs3.upload.tool=esptool_py +pandabyte_xs3.upload.tool.default=esptool_py +pandabyte_xs3.upload.tool.network=esp_ota + +pandabyte_xs3.upload.maximum_size=1310720 +pandabyte_xs3.upload.maximum_data_size=327680 +pandabyte_xs3.upload.flags= +pandabyte_xs3.upload.extra_flags= +pandabyte_xs3.upload.use_1200bps_touch=false +pandabyte_xs3.upload.wait_for_upload_port=false + +pandabyte_xs3.serial.disableDTR=false +pandabyte_xs3.serial.disableRTS=false + +pandabyte_xs3.build.tarch=xtensa +pandabyte_xs3.build.bootloader_addr=0x0 +pandabyte_xs3.build.target=esp32s3 +pandabyte_xs3.build.mcu=esp32s3 +pandabyte_xs3.build.core=esp32 +pandabyte_xs3.build.variant=pandabyte_xs3 +pandabyte_xs3.build.board=PANDABYTE_XS3 + +pandabyte_xs3.build.usb_mode=1 +pandabyte_xs3.build.cdc_on_boot=0 +pandabyte_xs3.build.msc_on_boot=0 +pandabyte_xs3.build.dfu_on_boot=0 +pandabyte_xs3.build.f_cpu=240000000L +pandabyte_xs3.build.flash_size=4MB +pandabyte_xs3.build.flash_freq=80m +pandabyte_xs3.build.flash_mode=dio +pandabyte_xs3.build.boot=qio +pandabyte_xs3.build.boot_freq=80m +pandabyte_xs3.build.partitions=default +pandabyte_xs3.build.defines= +pandabyte_xs3.build.loop_core= +pandabyte_xs3.build.event_core= +pandabyte_xs3.build.psram_type=qspi +pandabyte_xs3.build.memory_type={build.boot}_{build.psram_type} + +## IDE 2.0 Seems to not update the value +pandabyte_xs3.menu.JTAGAdapter.default=Disabled +pandabyte_xs3.menu.JTAGAdapter.default.build.copy_jtag_files=0 +pandabyte_xs3.menu.JTAGAdapter.builtin=Integrated USB JTAG +pandabyte_xs3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +pandabyte_xs3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +pandabyte_xs3.menu.JTAGAdapter.external=FTDI Adapter +pandabyte_xs3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +pandabyte_xs3.menu.JTAGAdapter.external.build.copy_jtag_files=1 +pandabyte_xs3.menu.JTAGAdapter.bridge=ESP USB Bridge +pandabyte_xs3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +pandabyte_xs3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +pandabyte_xs3.menu.PSRAM.disabled=Disabled +pandabyte_xs3.menu.PSRAM.disabled.build.defines= +pandabyte_xs3.menu.PSRAM.disabled.build.psram_type=qspi +pandabyte_xs3.menu.PSRAM.enabled=QSPI PSRAM +pandabyte_xs3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +pandabyte_xs3.menu.PSRAM.enabled.build.psram_type=qspi +pandabyte_xs3.menu.PSRAM.opi=OPI PSRAM +pandabyte_xs3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM +pandabyte_xs3.menu.PSRAM.opi.build.psram_type=opi + +pandabyte_xs3.menu.FlashMode.qio=QIO 80MHz +pandabyte_xs3.menu.FlashMode.qio.build.flash_mode=dio +pandabyte_xs3.menu.FlashMode.qio.build.boot=qio +pandabyte_xs3.menu.FlashMode.qio.build.boot_freq=80m +pandabyte_xs3.menu.FlashMode.qio.build.flash_freq=80m +pandabyte_xs3.menu.FlashMode.qio120=QIO 120MHz +pandabyte_xs3.menu.FlashMode.qio120.build.flash_mode=dio +pandabyte_xs3.menu.FlashMode.qio120.build.boot=qio +pandabyte_xs3.menu.FlashMode.qio120.build.boot_freq=120m +pandabyte_xs3.menu.FlashMode.qio120.build.flash_freq=80m +pandabyte_xs3.menu.FlashMode.dio=DIO 80MHz +pandabyte_xs3.menu.FlashMode.dio.build.flash_mode=dio +pandabyte_xs3.menu.FlashMode.dio.build.boot=dio +pandabyte_xs3.menu.FlashMode.dio.build.boot_freq=80m +pandabyte_xs3.menu.FlashMode.dio.build.flash_freq=80m +pandabyte_xs3.menu.FlashMode.opi=OPI 80MHz +pandabyte_xs3.menu.FlashMode.opi.build.flash_mode=dout +pandabyte_xs3.menu.FlashMode.opi.build.boot=opi +pandabyte_xs3.menu.FlashMode.opi.build.boot_freq=80m +pandabyte_xs3.menu.FlashMode.opi.build.flash_freq=80m + +pandabyte_xs3.menu.FlashSize.4M=4MB (32Mb) +pandabyte_xs3.menu.FlashSize.4M.build.flash_size=4MB +pandabyte_xs3.menu.FlashSize.8M=8MB (64Mb) +pandabyte_xs3.menu.FlashSize.8M.build.flash_size=8MB +pandabyte_xs3.menu.FlashSize.16M=16MB (128Mb) +pandabyte_xs3.menu.FlashSize.16M.build.flash_size=16MB +pandabyte_xs3.menu.FlashSize.32M=32MB (256Mb) +pandabyte_xs3.menu.FlashSize.32M.build.flash_size=32MB + +pandabyte_xs3.menu.LoopCore.1=Core 1 +pandabyte_xs3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +pandabyte_xs3.menu.LoopCore.0=Core 0 +pandabyte_xs3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +pandabyte_xs3.menu.EventsCore.1=Core 1 +pandabyte_xs3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +pandabyte_xs3.menu.EventsCore.0=Core 0 +pandabyte_xs3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +pandabyte_xs3.menu.USBMode.hwcdc=Hardware CDC and JTAG +pandabyte_xs3.menu.USBMode.hwcdc.build.usb_mode=1 +pandabyte_xs3.menu.USBMode.default=USB-OTG (TinyUSB) +pandabyte_xs3.menu.USBMode.default.build.usb_mode=0 + +pandabyte_xs3.menu.CDCOnBoot.default=Enabled +pandabyte_xs3.menu.CDCOnBoot.default.build.cdc_on_boot=1 +pandabyte_xs3.menu.CDCOnBoot.cdc=Enabled +pandabyte_xs3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0 + +pandabyte_xs3.menu.MSCOnBoot.default=Disabled +pandabyte_xs3.menu.MSCOnBoot.default.build.msc_on_boot=0 +pandabyte_xs3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +pandabyte_xs3.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +pandabyte_xs3.menu.DFUOnBoot.default=Disabled +pandabyte_xs3.menu.DFUOnBoot.default.build.dfu_on_boot=0 +pandabyte_xs3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +pandabyte_xs3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +pandabyte_xs3.menu.UploadMode.default=UART0 / Hardware CDC +pandabyte_xs3.menu.UploadMode.default.upload.use_1200bps_touch=false +pandabyte_xs3.menu.UploadMode.default.upload.wait_for_upload_port=false +pandabyte_xs3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +pandabyte_xs3.menu.UploadMode.cdc.upload.use_1200bps_touch=true +pandabyte_xs3.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +pandabyte_xs3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.default.build.partitions=default +pandabyte_xs3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +pandabyte_xs3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +pandabyte_xs3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +pandabyte_xs3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +pandabyte_xs3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.minimal.build.partitions=minimal +pandabyte_xs3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +pandabyte_xs3.menu.PartitionScheme.no_fs.build.partitions=no_fs +pandabyte_xs3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +pandabyte_xs3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.no_ota.build.partitions=no_ota +pandabyte_xs3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +pandabyte_xs3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +pandabyte_xs3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +pandabyte_xs3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +pandabyte_xs3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +pandabyte_xs3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +pandabyte_xs3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +pandabyte_xs3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +pandabyte_xs3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +pandabyte_xs3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.huge_app.build.partitions=huge_app +pandabyte_xs3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +pandabyte_xs3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +pandabyte_xs3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +pandabyte_xs3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +pandabyte_xs3.menu.PartitionScheme.fatflash.build.partitions=ffat +pandabyte_xs3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +pandabyte_xs3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +pandabyte_xs3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +pandabyte_xs3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +pandabyte_xs3.menu.PartitionScheme.rainmaker=RainMaker 4MB +pandabyte_xs3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +pandabyte_xs3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +pandabyte_xs3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +pandabyte_xs3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +pandabyte_xs3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +pandabyte_xs3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +pandabyte_xs3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +pandabyte_xs3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +pandabyte_xs3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS) +pandabyte_xs3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB +pandabyte_xs3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592 +pandabyte_xs3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS) +pandabyte_xs3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB +pandabyte_xs3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592 +pandabyte_xs3.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS) +pandabyte_xs3.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB +pandabyte_xs3.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200 +pandabyte_xs3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +pandabyte_xs3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +pandabyte_xs3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +pandabyte_xs3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +pandabyte_xs3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +pandabyte_xs3.menu.PartitionScheme.custom=Custom +pandabyte_xs3.menu.PartitionScheme.custom.build.partitions= +pandabyte_xs3.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +pandabyte_xs3.menu.CPUFreq.240=240MHz (WiFi) +pandabyte_xs3.menu.CPUFreq.240.build.f_cpu=240000000L +pandabyte_xs3.menu.CPUFreq.160=160MHz (WiFi) +pandabyte_xs3.menu.CPUFreq.160.build.f_cpu=160000000L +pandabyte_xs3.menu.CPUFreq.80=80MHz (WiFi) +pandabyte_xs3.menu.CPUFreq.80.build.f_cpu=80000000L +pandabyte_xs3.menu.CPUFreq.40=40MHz +pandabyte_xs3.menu.CPUFreq.40.build.f_cpu=40000000L +pandabyte_xs3.menu.CPUFreq.20=20MHz +pandabyte_xs3.menu.CPUFreq.20.build.f_cpu=20000000L +pandabyte_xs3.menu.CPUFreq.10=10MHz +pandabyte_xs3.menu.CPUFreq.10.build.f_cpu=10000000L + +pandabyte_xs3.menu.UploadSpeed.921600=921600 +pandabyte_xs3.menu.UploadSpeed.921600.upload.speed=921600 +pandabyte_xs3.menu.UploadSpeed.115200=115200 +pandabyte_xs3.menu.UploadSpeed.115200.upload.speed=115200 +pandabyte_xs3.menu.UploadSpeed.256000.windows=256000 +pandabyte_xs3.menu.UploadSpeed.256000.upload.speed=256000 +pandabyte_xs3.menu.UploadSpeed.230400.windows.upload.speed=256000 +pandabyte_xs3.menu.UploadSpeed.230400=230400 +pandabyte_xs3.menu.UploadSpeed.230400.upload.speed=230400 +pandabyte_xs3.menu.UploadSpeed.460800.linux=460800 +pandabyte_xs3.menu.UploadSpeed.460800.macosx=460800 +pandabyte_xs3.menu.UploadSpeed.460800.upload.speed=460800 +pandabyte_xs3.menu.UploadSpeed.512000.windows=512000 +pandabyte_xs3.menu.UploadSpeed.512000.upload.speed=512000 + +pandabyte_xs3.menu.DebugLevel.none=None +pandabyte_xs3.menu.DebugLevel.none.build.code_debug=0 +pandabyte_xs3.menu.DebugLevel.error=Error +pandabyte_xs3.menu.DebugLevel.error.build.code_debug=1 +pandabyte_xs3.menu.DebugLevel.warn=Warn +pandabyte_xs3.menu.DebugLevel.warn.build.code_debug=2 +pandabyte_xs3.menu.DebugLevel.info=Info +pandabyte_xs3.menu.DebugLevel.info.build.code_debug=3 +pandabyte_xs3.menu.DebugLevel.debug=Debug +pandabyte_xs3.menu.DebugLevel.debug.build.code_debug=4 +pandabyte_xs3.menu.DebugLevel.verbose=Verbose +pandabyte_xs3.menu.DebugLevel.verbose.build.code_debug=5 + +pandabyte_xs3.menu.EraseFlash.none=Disabled +pandabyte_xs3.menu.EraseFlash.none.upload.erase_cmd= +pandabyte_xs3.menu.EraseFlash.all=Enabled +pandabyte_xs3.menu.EraseFlash.all.upload.erase_cmd=-e + +pandabyte_xs3.menu.ZigbeeMode.default=Disabled +pandabyte_xs3.menu.ZigbeeMode.default.build.zigbee_mode= +pandabyte_xs3.menu.ZigbeeMode.default.build.zigbee_libs= +pandabyte_xs3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +pandabyte_xs3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +pandabyte_xs3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## + +rootmaker.name=Root Maker + +rootmaker.bootloader.tool=esptool_py +rootmaker.bootloader.tool.default=esptool_py + +rootmaker.upload.tool=esptool_py +rootmaker.upload.tool.default=esptool_py +rootmaker.upload.tool.network=esp_ota + +rootmaker.upload.maximum_size=1310720 +rootmaker.upload.maximum_data_size=327680 +rootmaker.upload.flags= +rootmaker.upload.extra_flags= +rootmaker.upload.use_1200bps_touch=false +rootmaker.upload.wait_for_upload_port=false + +rootmaker.serial.disableDTR=false +rootmaker.serial.disableRTS=false + +rootmaker.build.tarch=xtensa +rootmaker.build.bootloader_addr=0x0 +rootmaker.build.target=esp32s3 +rootmaker.build.mcu=esp32s3 +rootmaker.build.core=esp32 +rootmaker.build.variant=esp32s3 +rootmaker.build.board=ROOT_MAKER + +rootmaker.build.usb_mode=1 +rootmaker.build.cdc_on_boot=0 +rootmaker.build.msc_on_boot=0 +rootmaker.build.dfu_on_boot=0 +rootmaker.build.f_cpu=240000000L +rootmaker.build.flash_size=16MB +rootmaker.build.flash_freq=80m +rootmaker.build.flash_mode=dio +rootmaker.build.boot=qio +rootmaker.build.boot_freq=80m +rootmaker.build.partitions=default +rootmaker.build.defines= +rootmaker.build.loop_core= +rootmaker.build.event_core= +rootmaker.build.psram_type=qspi +rootmaker.build.memory_type={build.boot}_{build.psram_type} + + +## IDE 2.0 Seems to not update the value +rootmaker.menu.JTAGAdapter.default=Disabled +rootmaker.menu.JTAGAdapter.default.build.copy_jtag_files=0 +rootmaker.menu.JTAGAdapter.builtin=Integrated USB JTAG +rootmaker.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg +rootmaker.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +rootmaker.menu.JTAGAdapter.external=FTDI Adapter +rootmaker.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg +rootmaker.menu.JTAGAdapter.external.build.copy_jtag_files=1 +rootmaker.menu.JTAGAdapter.bridge=ESP USB Bridge +rootmaker.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg +rootmaker.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +rootmaker.menu.PSRAM.enabled=QSPI PSRAM +rootmaker.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM +rootmaker.menu.PSRAM.enabled.build.psram_type=qspi + +rootmaker.menu.FlashMode.qio=QIO 80MHz +rootmaker.menu.FlashMode.qio.build.flash_mode=dio +rootmaker.menu.FlashMode.qio.build.boot=qio +rootmaker.menu.FlashMode.qio.build.boot_freq=80m +rootmaker.menu.FlashMode.qio.build.flash_freq=80m +rootmaker.menu.FlashMode.qio120=QIO 120MHz +rootmaker.menu.FlashMode.qio120.build.flash_mode=dio +rootmaker.menu.FlashMode.qio120.build.boot=qio +rootmaker.menu.FlashMode.qio120.build.boot_freq=120m +rootmaker.menu.FlashMode.qio120.build.flash_freq=80m + +rootmaker.menu.FlashSize.16M=16MB (128Mb) +rootmaker.menu.FlashSize.16M.build.flash_size=16MB + +rootmaker.menu.LoopCore.1=Core 1 +rootmaker.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1 +rootmaker.menu.LoopCore.0=Core 0 +rootmaker.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0 + +rootmaker.menu.EventsCore.1=Core 1 +rootmaker.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1 +rootmaker.menu.EventsCore.0=Core 0 +rootmaker.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0 + +rootmaker.menu.USBMode.hwcdc=Hardware CDC and JTAG +rootmaker.menu.USBMode.hwcdc.build.usb_mode=1 +rootmaker.menu.USBMode.default=USB-OTG (TinyUSB) +rootmaker.menu.USBMode.default.build.usb_mode=0 + +rootmaker.menu.CDCOnBoot.default=Disabled +rootmaker.menu.CDCOnBoot.default.build.cdc_on_boot=0 +rootmaker.menu.CDCOnBoot.cdc=Enabled +rootmaker.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +rootmaker.menu.MSCOnBoot.default=Disabled +rootmaker.menu.MSCOnBoot.default.build.msc_on_boot=0 +rootmaker.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode) +rootmaker.menu.MSCOnBoot.msc.build.msc_on_boot=1 + +rootmaker.menu.DFUOnBoot.default=Disabled +rootmaker.menu.DFUOnBoot.default.build.dfu_on_boot=0 +rootmaker.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode) +rootmaker.menu.DFUOnBoot.dfu.build.dfu_on_boot=1 + +rootmaker.menu.UploadMode.default=UART0 / Hardware CDC +rootmaker.menu.UploadMode.default.upload.use_1200bps_touch=false +rootmaker.menu.UploadMode.default.upload.wait_for_upload_port=false +rootmaker.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB) +rootmaker.menu.UploadMode.cdc.upload.use_1200bps_touch=true +rootmaker.menu.UploadMode.cdc.upload.wait_for_upload_port=true + +rootmaker.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +rootmaker.menu.PartitionScheme.default.build.partitions=default +rootmaker.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +rootmaker.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +rootmaker.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +rootmaker.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +rootmaker.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +rootmaker.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +rootmaker.menu.PartitionScheme.minimal.build.partitions=minimal +rootmaker.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +rootmaker.menu.PartitionScheme.no_fs.build.partitions=no_fs +rootmaker.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +rootmaker.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +rootmaker.menu.PartitionScheme.no_ota.build.partitions=no_ota +rootmaker.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +rootmaker.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +rootmaker.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +rootmaker.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +rootmaker.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +rootmaker.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +rootmaker.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +rootmaker.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +rootmaker.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +rootmaker.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +rootmaker.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +rootmaker.menu.PartitionScheme.huge_app.build.partitions=huge_app +rootmaker.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +rootmaker.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/128KB SPIFFS) +rootmaker.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +rootmaker.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +rootmaker.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS) +rootmaker.menu.PartitionScheme.fatflash.build.partitions=ffat +rootmaker.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 +rootmaker.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS) +rootmaker.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB +rootmaker.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728 +rootmaker.menu.PartitionScheme.rainmaker=RainMaker 4MB +rootmaker.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +rootmaker.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +rootmaker.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +rootmaker.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +rootmaker.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +rootmaker.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +rootmaker.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +rootmaker.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +rootmaker.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL) +rootmaker.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728 +rootmaker.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin +rootmaker.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16 +rootmaker.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs +rootmaker.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr +rootmaker.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720 +rootmaker.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs +rootmaker.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB +rootmaker.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872 +rootmaker.menu.PartitionScheme.custom=Custom +rootmaker.menu.PartitionScheme.custom.build.partitions= +rootmaker.menu.PartitionScheme.custom.upload.maximum_size=16777216 + +rootmaker.menu.CPUFreq.240=240MHz (WiFi) +rootmaker.menu.CPUFreq.240.build.f_cpu=240000000L +rootmaker.menu.CPUFreq.160=160MHz (WiFi) +rootmaker.menu.CPUFreq.160.build.f_cpu=160000000L +rootmaker.menu.CPUFreq.80=80MHz (WiFi) +rootmaker.menu.CPUFreq.80.build.f_cpu=80000000L +rootmaker.menu.CPUFreq.40=40MHz +rootmaker.menu.CPUFreq.40.build.f_cpu=40000000L +rootmaker.menu.CPUFreq.20=20MHz +rootmaker.menu.CPUFreq.20.build.f_cpu=20000000L +rootmaker.menu.CPUFreq.10=10MHz +rootmaker.menu.CPUFreq.10.build.f_cpu=10000000L + +rootmaker.menu.UploadSpeed.921600=921600 +rootmaker.menu.UploadSpeed.921600.upload.speed=921600 +rootmaker.menu.UploadSpeed.115200=115200 +rootmaker.menu.UploadSpeed.115200.upload.speed=115200 +rootmaker.menu.UploadSpeed.256000.windows=256000 +rootmaker.menu.UploadSpeed.256000.upload.speed=256000 +rootmaker.menu.UploadSpeed.230400.windows.upload.speed=256000 +rootmaker.menu.UploadSpeed.230400=230400 +rootmaker.menu.UploadSpeed.230400.upload.speed=230400 +rootmaker.menu.UploadSpeed.460800.linux=460800 +rootmaker.menu.UploadSpeed.460800.macosx=460800 +rootmaker.menu.UploadSpeed.460800.upload.speed=460800 +rootmaker.menu.UploadSpeed.512000.windows=512000 +rootmaker.menu.UploadSpeed.512000.upload.speed=512000 + +rootmaker.menu.DebugLevel.none=None +rootmaker.menu.DebugLevel.none.build.code_debug=0 +rootmaker.menu.DebugLevel.error=Error +rootmaker.menu.DebugLevel.error.build.code_debug=1 +rootmaker.menu.DebugLevel.warn=Warn +rootmaker.menu.DebugLevel.warn.build.code_debug=2 +rootmaker.menu.DebugLevel.info=Info +rootmaker.menu.DebugLevel.info.build.code_debug=3 +rootmaker.menu.DebugLevel.debug=Debug +rootmaker.menu.DebugLevel.debug.build.code_debug=4 +rootmaker.menu.DebugLevel.verbose=Verbose +rootmaker.menu.DebugLevel.verbose.build.code_debug=5 + +rootmaker.menu.EraseFlash.none=Disabled +rootmaker.menu.EraseFlash.none.upload.erase_cmd= +rootmaker.menu.EraseFlash.all=Enabled +rootmaker.menu.EraseFlash.all.upload.erase_cmd=-e + +rootmaker.menu.ZigbeeMode.default=Disabled +rootmaker.menu.ZigbeeMode.default.build.zigbee_mode= +rootmaker.menu.ZigbeeMode.default.build.zigbee_libs= +rootmaker.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router) +rootmaker.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR +rootmaker.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote + +############################################################## diff --git a/cores/esp32/Arduino.h b/cores/esp32/Arduino.h new file mode 100644 index 0000000..5a5b0c6 --- /dev/null +++ b/cores/esp32/Arduino.h @@ -0,0 +1,281 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Arduino_h +#define Arduino_h + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "esp_arduino_version.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp8266-compat.h" +#include "soc/gpio_reg.h" + +#include "stdlib_noniso.h" +#include "binary.h" +#include "extra_attr.h" + +#include "pins_arduino.h" +#include "esp32-hal.h" + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 +#define EULER 2.718281828459045235360287471352 + +#define SERIAL 0x0 +#define DISPLAY 0x1 + +#define LSBFIRST 0 +#define MSBFIRST 1 + +//Interrupt Modes +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 +#define ONLOW_WE 0x0C +#define ONHIGH_WE 0x0D + +#define DEFAULT 1 +#define EXTERNAL 0 + +#ifndef __STRINGIFY +#define __STRINGIFY(a) #a +#endif + +// can't define max() / min() because of conflicts with C++ +#define _min(a, b) ((a) < (b) ? (a) : (b)) +#define _max(a, b) ((a) > (b) ? (a) : (b)) +#define _abs(x) ((x) > 0 ? (x) : -(x)) // abs() comes from STL +#define constrain(amt, low, high) ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt))) +#define _round(x) ((x) >= 0 ? (long)((x) + 0.5) : (long)((x) - 0.5)) // round() comes from STL +#define radians(deg) ((deg) * DEG_TO_RAD) +#define degrees(rad) ((rad) * RAD_TO_DEG) +#define sq(x) ((x) * (x)) + +// ESP32xx runs FreeRTOS... disabling interrupts can lead to issues, such as Watchdog Timeout +#define sei() portENABLE_INTERRUPTS() +#define cli() portDISABLE_INTERRUPTS() +#define interrupts() sei() +#define noInterrupts() cli() + +#define clockCyclesPerMicrosecond() ((long int)getCpuFrequencyMhz()) +#define clockCyclesToMicroseconds(a) ((a) / clockCyclesPerMicrosecond()) +#define microsecondsToClockCycles(a) ((a) * clockCyclesPerMicrosecond()) + +#define lowByte(w) ((uint8_t)((w) & 0xff)) +#define highByte(w) ((uint8_t)((w) >> 8)) + +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitToggle(value, bit) ((value) ^= (1UL << (bit))) +#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit)) + +// avr-libc defines _NOP() since 1.6.2 +#ifndef _NOP +#define _NOP() \ + do { \ + __asm__ volatile("nop"); \ + } while (0) +#endif + +#define bit(b) (1UL << (b)) +#define _BV(b) (1UL << (b)) + +#define digitalPinToTimer(pin) (0) +#define analogInPinToBit(P) (P) +#if SOC_GPIO_PIN_COUNT <= 32 +#define digitalPinToPort(pin) (0) +#define digitalPinToBitMask(pin) (1UL << digitalPinToGPIONumber(pin)) +#define portOutputRegister(port) ((volatile uint32_t *)GPIO_OUT_REG) +#define portInputRegister(port) ((volatile uint32_t *)GPIO_IN_REG) +#define portModeRegister(port) ((volatile uint32_t *)GPIO_ENABLE_REG) +#elif SOC_GPIO_PIN_COUNT <= 64 +#define digitalPinToPort(pin) ((digitalPinToGPIONumber(pin) > 31) ? 1 : 0) +#define digitalPinToBitMask(pin) (1UL << (digitalPinToGPIONumber(pin) & 31)) +#define portOutputRegister(port) ((volatile uint32_t *)((port) ? GPIO_OUT1_REG : GPIO_OUT_REG)) +#define portInputRegister(port) ((volatile uint32_t *)((port) ? GPIO_IN1_REG : GPIO_IN_REG)) +#define portModeRegister(port) ((volatile uint32_t *)((port) ? GPIO_ENABLE1_REG : GPIO_ENABLE_REG)) +#else +#error SOC_GPIO_PIN_COUNT > 64 not implemented +#endif + +#define NOT_A_PIN -1 +#define NOT_A_PORT -1 +#define NOT_AN_INTERRUPT -1 +#define NOT_ON_TIMER 0 + +// some defines generic for all SoC moved from variants/board_name/pins_arduino.h +#define NUM_DIGITAL_PINS SOC_GPIO_PIN_COUNT // All GPIOs +#if SOC_ADC_PERIPH_NUM == 1 +#define NUM_ANALOG_INPUTS (SOC_ADC_CHANNEL_NUM(0)) // Depends on the SoC (ESP32C6, ESP32H2, ESP32C2, ESP32P4) +#elif SOC_ADC_PERIPH_NUM == 2 +#define NUM_ANALOG_INPUTS (SOC_ADC_CHANNEL_NUM(0) + SOC_ADC_CHANNEL_NUM(1)) // Depends on the SoC (ESP32, ESP32S2, ESP32S3, ESP32C3) +#endif +#define EXTERNAL_NUM_INTERRUPTS NUM_DIGITAL_PINS // All GPIOs +#define analogInputToDigitalPin(p) (((p) < NUM_ANALOG_INPUTS) ? (analogChannelToDigitalPin(p)) : -1) +#define digitalPinToInterrupt(p) ((((uint8_t)digitalPinToGPIONumber(p)) < NUM_DIGITAL_PINS) ? (p) : NOT_AN_INTERRUPT) +#define digitalPinHasPWM(p) (((uint8_t)digitalPinToGPIONumber(p)) < NUM_DIGITAL_PINS) + +typedef bool boolean; +typedef uint8_t byte; +typedef unsigned int word; + +#ifdef __cplusplus +void setup(void); +void loop(void); + +// The default is using Real Hardware random number generator +// But when randomSeed() is called, it turns to Psedo random +// generator, exactly as done in Arduino mainstream +long random(long); +long random(long, long); +// Calling randomSeed() will make random() +// using pseudo random like in Arduino +void randomSeed(unsigned long); +// Allow the Application to decide if the random generator +// will use Real Hardware random generation (true - default) +// or Pseudo random generation (false) as in Arduino MainStream +void useRealRandomGenerator(bool useRandomHW); +#endif +long map(long, long, long, long, long); + +#ifdef __cplusplus +extern "C" { +#endif + +void init(void); +void initVariant(void); +void initArduino(void); + +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout); +unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout); + +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder); // codespell:ignore shiftin +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val); + +#ifdef __cplusplus +} + +#include +#include + +#include "WCharacter.h" +#include "WString.h" +#include "Stream.h" +#include "Printable.h" +#include "Print.h" +#include "IPAddress.h" +#include "Client.h" +#include "Server.h" +#include "Udp.h" +#include "HardwareSerial.h" +#include "Esp.h" +#include "freertos_stats.h" + +// Use float-compatible stl abs() and round(), we don't use Arduino macros to avoid issues with the C++ libraries +using std::abs; +using std::isinf; +using std::isnan; +using std::max; +using std::min; +using std::round; + +uint16_t makeWord(uint16_t w); +uint16_t makeWord(uint8_t h, uint8_t l); + +#define word(...) makeWord(__VA_ARGS__) + +size_t getArduinoLoopTaskStackSize(void); +#define SET_LOOP_TASK_STACK_SIZE(sz) \ + size_t getArduinoLoopTaskStackSize() { \ + return sz; \ + } + +#define ESP32_USB_MIDI_DEFAULT_NAME "TinyUSB MIDI" +/** +* @brief Set the current device name +* 1. Name set via constructor (if any) +* 2. Name set via SET_USB_MIDI_DEVICE_NAME() macro (if defined) +* 3. Default name "TinyUSB MIDI" +* If device name is set as "", it will be ignored +*/ +#define SET_USB_MIDI_DEVICE_NAME(name) \ + const char *getUSBMIDIDefaultDeviceName() { \ + if (!name || strlen(name) == 0) { \ + return ESP32_USB_MIDI_DEFAULT_NAME; \ + } \ + return name; \ + } + +bool shouldPrintChipDebugReport(void); +#define ENABLE_CHIP_DEBUG_REPORT \ + bool shouldPrintChipDebugReport(void) { \ + return true; \ + } + +// macro SET_TIME_BEFORE_STARTING_SKETCH_MS(time_ms) can set a time in milliseconds +// before the sketch would start its execution. It gives the user time to open the Serial Monitor +uint64_t getArduinoSetupWaitTime_ms(void); +#define SET_TIME_BEFORE_STARTING_SKETCH_MS(time_ms) \ + uint64_t getArduinoSetupWaitTime_ms() { \ + return (time_ms); \ + } + +// allows user to bypass esp_spiram_test() +bool esp_psram_extram_test(void); +#define BYPASS_SPIRAM_TEST(bypass) \ + bool testSPIRAM(void) { \ + if (bypass) \ + return true; \ + else \ + return esp_psram_extram_test(); \ + } + +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L); +unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L); + +extern "C" bool getLocalTime(struct tm *info, uint32_t ms = 5000); +extern "C" void configTime(long gmtOffset_sec, int daylightOffset_sec, const char *server1, const char *server2 = nullptr, const char *server3 = nullptr); +extern "C" void configTzTime(const char *tz, const char *server1, const char *server2 = nullptr, const char *server3 = nullptr); + +void setToneChannel(uint8_t channel = 0); +void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0); +void noTone(uint8_t _pin); + +#endif /* __cplusplus */ + +// must be applied last as it overrides some of the above +#include "io_pin_remap.h" + +#endif /* _ESP32_CORE_ARDUINO_H_ */ diff --git a/cores/esp32/Client.h b/cores/esp32/Client.h new file mode 100644 index 0000000..ab01361 --- /dev/null +++ b/cores/esp32/Client.h @@ -0,0 +1,47 @@ +/* + Client.h - Base class that provides Client + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef client_h +#define client_h +#include "Print.h" +#include "Stream.h" +#include "IPAddress.h" + +class Client : public Stream { +public: + virtual int connect(IPAddress ip, uint16_t port) = 0; + virtual int connect(const char *host, uint16_t port) = 0; + virtual size_t write(uint8_t) = 0; + virtual size_t write(const uint8_t *buf, size_t size) = 0; + virtual int available() = 0; + virtual int read() = 0; + virtual int read(uint8_t *buf, size_t size) = 0; + virtual int peek() = 0; + virtual void flush() = 0; + virtual void stop() = 0; + virtual uint8_t connected() = 0; + virtual operator bool() = 0; + +protected: + uint8_t *rawIPAddress(IPAddress &addr) { + return addr.raw_address(); + } +}; + +#endif diff --git a/cores/esp32/ColorFormat.c b/cores/esp32/ColorFormat.c new file mode 100644 index 0000000..052249f --- /dev/null +++ b/cores/esp32/ColorFormat.c @@ -0,0 +1,281 @@ +/* + * + * Copyright (c) 2021 Project CHIP Authors + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ColorFormat.h" + +#include + +// define a clamp macro to substitute the std::clamp macro which is available from C++17 onwards +#define clamp(a, min, max) ((a) < (min) ? (min) : ((a) > (max) ? (max) : (a))) + +const espHsvColor_t HSV_BLACK = {0, 0, 0}; +const espHsvColor_t HSV_WHITE = {0, 0, 254}; +const espHsvColor_t HSV_RED = {0, 254, 254}; +const espHsvColor_t HSV_YELLOW = {42, 254, 254}; +const espHsvColor_t HSV_GREEN = {84, 254, 254}; +const espHsvColor_t HSV_CYAN = {127, 254, 254}; +const espHsvColor_t HSV_BLUE = {169, 254, 254}; +const espHsvColor_t HSV_MAGENTA = {211, 254, 254}; + +const espRgbColor_t RGB_BLACK = {0, 0, 0}; +const espRgbColor_t RGB_WHITE = {255, 255, 255}; +const espRgbColor_t RGB_RED = {255, 0, 0}; +const espRgbColor_t RGB_YELLOW = {255, 255, 0}; +const espRgbColor_t RGB_GREEN = {0, 255, 0}; +const espRgbColor_t RGB_CYAN = {0, 255, 255}; +const espRgbColor_t RGB_BLUE = {0, 0, 255}; +const espRgbColor_t RGB_MAGENTA = {255, 0, 255}; + +// main color temperature values +const espCtColor_t COOL_WHITE_COLOR_TEMPERATURE = {142}; +const espCtColor_t DAYLIGHT_WHITE_COLOR_TEMPERATURE = {181}; +const espCtColor_t WHITE_COLOR_TEMPERATURE = {250}; +const espCtColor_t SOFT_WHITE_COLOR_TEMPERATURE = {370}; +const espCtColor_t WARM_WHITE_COLOR_TEMPERATURE = {454}; + +espRgbColor_t espHsvToRgbColor(uint16_t h, uint8_t s, uint8_t v) { + espHsvColor_t hsv = {h, s, v}; + return espHsvColorToRgbColor(hsv); +} + +espRgbColor_t espHsvColorToRgbColor(espHsvColor_t hsv) { + espRgbColor_t rgb; + + uint8_t region, p, q, t; + uint32_t h, s, v, remainder; + + if (hsv.s == 0) { + rgb.r = rgb.g = rgb.b = hsv.v; + } else { + h = hsv.h; + s = hsv.s; + v = hsv.v; + + region = h / 43; + remainder = (h - (region * 43)) * 6; + p = (v * (255 - s)) >> 8; + q = (v * (255 - ((s * remainder) >> 8))) >> 8; + t = (v * (255 - ((s * (255 - remainder)) >> 8))) >> 8; + switch (region) { + case 0: rgb.r = v, rgb.g = t, rgb.b = p; break; + case 1: rgb.r = q, rgb.g = v, rgb.b = p; break; + case 2: rgb.r = p, rgb.g = v, rgb.b = t; break; + case 3: rgb.r = p, rgb.g = q, rgb.b = v; break; + case 4: rgb.r = t, rgb.g = p, rgb.b = v; break; + case 5: + default: rgb.r = v, rgb.g = p, rgb.b = q; break; + } + } + return rgb; +} + +espHsvColor_t espRgbToHsvColor(uint8_t r, uint8_t g, uint8_t b) { + espRgbColor_t rgb = {r, g, b}; + return espRgbColorToHsvColor(rgb); +} + +espHsvColor_t espRgbColorToHsvColor(espRgbColor_t rgb) { + espHsvColor_t hsv; + uint8_t rgbMin, rgbMax; + + rgbMin = rgb.r < rgb.g ? (rgb.r < rgb.b ? rgb.r : rgb.b) : (rgb.g < rgb.b ? rgb.g : rgb.b); + rgbMax = rgb.r > rgb.g ? (rgb.r > rgb.b ? rgb.r : rgb.b) : (rgb.g > rgb.b ? rgb.g : rgb.b); + + hsv.v = rgbMax; + if (hsv.v == 0) { + hsv.h = 0; + hsv.s = 0; + return hsv; + } + + hsv.s = 255 * (rgbMax - rgbMin) / hsv.v; + if (hsv.s == 0) { + hsv.h = 0; + return hsv; + } + if (rgbMax == rgb.r) { + hsv.h = 0 + 43 * (rgb.g - rgb.b) / (rgbMax - rgbMin); + } else if (rgbMax == rgb.g) { + hsv.h = 85 + 43 * (rgb.b - rgb.r) / (rgbMax - rgbMin); + } else { + hsv.h = 171 + 43 * (rgb.r - rgb.g) / (rgbMax - rgbMin); + } + return hsv; +} + +espRgbColor_t espXYColorToRgbColor(uint8_t Level, espXyColor_t xy) { + return espXYToRgbColor(Level, xy.x, xy.y, true); +} + +espRgbColor_t espXYToRgbColor(uint8_t Level, uint16_t current_X, uint16_t current_Y, bool addXYZScaling) { + // convert xyY color space to RGB + + // https://www.easyrgb.com/en/math.php + // https://en.wikipedia.org/wiki/SRGB + // refer https://en.wikipedia.org/wiki/CIE_1931_color_space#CIE_xy_chromaticity_diagram_and_the_CIE_xyY_color_space + + // The current_X/current_Y attribute contains the current value of the normalized chromaticity value of x/y. + // The value of x/y shall be related to the current_X/current_Y attribute by the relationship + // x = current_X/65536 + // y = current_Y/65536 + // z = 1-x-y + + espRgbColor_t rgb; + + float x, y, z; + float X, Y, Z; + float r, g, b; + + x = ((float)current_X) / 65535.0f; + y = ((float)current_Y) / 65535.0f; + + z = 1.0f - x - y; + + // Calculate XYZ values + + // Y - given brightness in 0 - 1 range + Y = ((float)Level) / 254.0f; + X = (Y / y) * x; + Z = (Y / y) * z; + + // X, Y and Z input refer to a D65/2° standard illuminant. + // sR, sG and sB (standard RGB) output range = 0 ÷ 255 + // convert XYZ to RGB - CIE XYZ to sRGB + if (addXYZScaling) { + X = X / 100.0f; + Y = Y / 100.0f; + Z = Z / 100.0f; + } + + r = (X * 3.2406f) - (Y * 1.5372f) - (Z * 0.4986f); + g = -(X * 0.9689f) + (Y * 1.8758f) + (Z * 0.0415f); + b = (X * 0.0557f) - (Y * 0.2040f) + (Z * 1.0570f); + + // apply gamma 2.2 correction + r = (r <= 0.0031308f ? 12.92f * r : (1.055f) * pow(r, (1.0f / 2.4f)) - 0.055f); + g = (g <= 0.0031308f ? 12.92f * g : (1.055f) * pow(g, (1.0f / 2.4f)) - 0.055f); + b = (b <= 0.0031308f ? 12.92f * b : (1.055f) * pow(b, (1.0f / 2.4f)) - 0.055f); + + // Round off + r = clamp(r, 0, 1); + g = clamp(g, 0, 1); + b = clamp(b, 0, 1); + + // these rgb values are in the range of 0 to 1, convert to limit of HW specific LED + rgb.r = (uint8_t)(r * 255); + rgb.g = (uint8_t)(g * 255); + rgb.b = (uint8_t)(b * 255); + + return rgb; +} + +espXyColor_t espRgbToXYColor(uint8_t r, uint8_t g, uint8_t b) { + espRgbColor_t rgb = {r, g, b}; + return espRgbColorToXYColor(rgb); +} + +espXyColor_t espRgbColorToXYColor(espRgbColor_t rgb) { + // convert RGB to xy color space + + // https://www.easyrgb.com/en/math.php + // https://en.wikipedia.org/wiki/SRGB + // refer https://en.wikipedia.org/wiki/CIE_1931_color_space#CIE_xy_chromaticity_diagram_and_the_CIE_xyY_color_space + + espXyColor_t xy; + + float r, g, b; + float X, Y, Z; + float x, y; + + r = ((float)rgb.r) / 255.0f; + g = ((float)rgb.g) / 255.0f; + b = ((float)rgb.b) / 255.0f; + + // convert RGB to XYZ - sRGB to CIE XYZ + r = (r <= 0.04045f ? r / 12.92f : pow((r + 0.055f) / 1.055f, 2.4f)); + g = (g <= 0.04045f ? g / 12.92f : pow((g + 0.055f) / 1.055f, 2.4f)); + b = (b <= 0.04045f ? b / 12.92f : pow((b + 0.055f) / 1.055f, 2.4f)); + + // https://gist.github.com/popcorn245/30afa0f98eea1c2fd34d + X = r * 0.649926f + g * 0.103455f + b * 0.197109f; + Y = r * 0.234327f + g * 0.743075f + b * 0.022598f; + Z = r * 0.0000000f + g * 0.053077f + b * 1.035763f; + + // sR, sG and sB (standard RGB) input range = 0 ÷ 255 + // X, Y and Z output refer to a D65/2° standard illuminant. + X = r * 0.4124564f + g * 0.3575761f + b * 0.1804375f; + Y = r * 0.2126729f + g * 0.7151522f + b * 0.0721750f; + Z = r * 0.0193339f + g * 0.1191920f + b * 0.9503041f; + + // Calculate xy values + x = X / (X + Y + Z); + y = Y / (X + Y + Z); + + // convert to 0-65535 range + xy.x = (uint16_t)(x * 65535); + xy.y = (uint16_t)(y * 65535); + return xy; +} + +espRgbColor_t espCTToRgbColor(uint16_t ct) { + espCtColor_t ctColor = {ct}; + return espCTColorToRgbColor(ctColor); +} + +espRgbColor_t espCTColorToRgbColor(espCtColor_t ct) { + espRgbColor_t rgb = {0, 0, 0}; + float r, g, b; + + if (ct.ctMireds == 0) { + return rgb; + } + // Algorithm credits to Tanner Helland: https://tannerhelland.com/2012/09/18/convert-temperature-rgb-algorithm-code.html + + // Convert Mireds to centiKelvins. k = 1,000,000/mired + float ctCentiKelvin = 10000 / ct.ctMireds; + + // Red + if (ctCentiKelvin <= 66) { + r = 255; + } else { + r = 329.698727446f * pow(ctCentiKelvin - 60, -0.1332047592f); + } + + // Green + if (ctCentiKelvin <= 66) { + g = 99.4708025861f * log(ctCentiKelvin) - 161.1195681661f; + } else { + g = 288.1221695283f * pow(ctCentiKelvin - 60, -0.0755148492f); + } + + // Blue + if (ctCentiKelvin >= 66) { + b = 255; + } else { + if (ctCentiKelvin <= 19) { + b = 0; + } else { + b = 138.5177312231 * log(ctCentiKelvin - 10) - 305.0447927307; + } + } + rgb.r = (uint8_t)clamp(r, 0, 255); + rgb.g = (uint8_t)clamp(g, 0, 255); + rgb.b = (uint8_t)clamp(b, 0, 255); + + return rgb; +} diff --git a/cores/esp32/ColorFormat.h b/cores/esp32/ColorFormat.h new file mode 100644 index 0000000..288b79b --- /dev/null +++ b/cores/esp32/ColorFormat.h @@ -0,0 +1,71 @@ +/* + * + * Copyright (c) 2021 Project CHIP Authors + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#pragma once + +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +struct RgbColor_t { + uint8_t r; + uint8_t g; + uint8_t b; +}; + +struct HsvColor_t { + uint16_t h; + uint8_t s; + uint8_t v; +}; + +struct XyColor_t { + uint16_t x; + uint16_t y; +}; + +struct CtColor_t { + uint16_t ctMireds; +}; + +typedef struct RgbColor_t espRgbColor_t; +typedef struct HsvColor_t espHsvColor_t; +typedef struct XyColor_t espXyColor_t; +typedef struct CtColor_t espCtColor_t; + +espRgbColor_t espXYToRgbColor(uint8_t Level, uint16_t current_X, uint16_t current_Y, bool addXYZScaling); +espRgbColor_t espXYColorToRgb(uint8_t Level, espXyColor_t xy); +espXyColor_t espRgbColorToXYColor(espRgbColor_t rgb); +espXyColor_t espRgbToXYColor(uint8_t r, uint8_t g, uint8_t b); +espRgbColor_t espHsvColorToRgbColor(espHsvColor_t hsv); +espRgbColor_t espHsvToRgbColor(uint16_t h, uint8_t s, uint8_t v); +espRgbColor_t espCTColorToRgbColor(espCtColor_t ct); +espRgbColor_t espCTToRgbColor(uint16_t ct); +espHsvColor_t espRgbColorToHsvColor(espRgbColor_t rgb); +espHsvColor_t espRgbToHsvColor(uint8_t r, uint8_t g, uint8_t b); + +extern const espHsvColor_t HSV_BLACK, HSV_WHITE, HSV_RED, HSV_YELLOW, HSV_GREEN, HSV_CYAN, HSV_BLUE, HSV_MAGENTA; +extern const espCtColor_t COOL_WHITE_COLOR_TEMPERATURE, DAYLIGHT_WHITE_COLOR_TEMPERATURE, WHITE_COLOR_TEMPERATURE, SOFT_WHITE_COLOR_TEMPERATURE, + WARM_WHITE_COLOR_TEMPERATURE; +extern const espRgbColor_t RGB_BLACK, RGB_WHITE, RGB_RED, RGB_YELLOW, RGB_GREEN, RGB_CYAN, RGB_BLUE, RGB_MAGENTA; + +#ifdef __cplusplus +} +#endif diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp new file mode 100644 index 0000000..023afd8 --- /dev/null +++ b/cores/esp32/Esp.cpp @@ -0,0 +1,607 @@ +/* + Esp.cpp - ESP31B-specific APIs + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Arduino.h" +#include "Esp.h" +#include "esp_sleep.h" +#include "spi_flash_mmap.h" +#include "esp_idf_version.h" +#include +#include +#include +extern "C" { +#include "esp_ota_ops.h" +#include "esp_image_format.h" +} +#include + +#include "soc/spi_reg.h" +#include "esp_system.h" +#include "esp_chip_info.h" +#include "esp_mac.h" +#include "esp_flash.h" + +// Include HAL layer for flash clock access +#include "hal/spi_flash_ll.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "soc/spi_struct.h" +#else +// All modern chips (S2, S3, C2, C3, C5, C6, H2, P4) use spimem +#include "hal/spimem_flash_ll.h" +// Try to include the newer c_struct header first, fall back to regular struct +#if __has_include("soc/spi_mem_c_struct.h") +#include "soc/spi_mem_c_struct.h" +#else +#include "soc/spi_mem_struct.h" +#endif +#endif + +#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "esp32/rom/spi_flash.h" +#include "soc/efuse_reg.h" +#define ESP_FLASH_IMAGE_BASE 0x1000 // Flash offset containing flash size and spi mode +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/spi_flash.h" +#include "soc/efuse_reg.h" +#define ESP_FLASH_IMAGE_BASE 0x1000 +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" +#include "soc/efuse_reg.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32s3 is located at 0x0000 +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c2 is located at 0x0000 +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000 +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c6 is located at 0x0000 +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32h2 is located at 0x0000 +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000 +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32c5 is located at 0x2000 +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c61 is located at 0x0000 +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif +#else // ESP32 Before IDF 4.0 +#include "rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x1000 +#endif + +// REG_SPI_BASE is not defined for S3/C3 ?? + +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#ifdef REG_SPI_BASE +#undef REG_SPI_BASE +#endif // REG_SPI_BASE +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) +#endif // TARGET + +/** + * User-defined Literals + * usage: + * + * uint32_t = test = 10_MHz; // --> 10000000 + */ + +unsigned long long operator""_kHz(unsigned long long x) { + return x * 1000; +} + +unsigned long long operator""_MHz(unsigned long long x) { + return x * 1000 * 1000; +} + +unsigned long long operator""_GHz(unsigned long long x) { + return x * 1000 * 1000 * 1000; +} + +unsigned long long operator""_kBit(unsigned long long x) { + return x * 1024; +} + +unsigned long long operator""_MBit(unsigned long long x) { + return x * 1024 * 1024; +} + +unsigned long long operator""_GBit(unsigned long long x) { + return x * 1024 * 1024 * 1024; +} + +unsigned long long operator""_kB(unsigned long long x) { + return x * 1024; +} + +unsigned long long operator""_MB(unsigned long long x) { + return x * 1024 * 1024; +} + +unsigned long long operator""_GB(unsigned long long x) { + return x * 1024 * 1024 * 1024; +} + +EspClass ESP; + +void EspClass::deepSleep(uint64_t time_us) { + esp_deep_sleep(time_us); +} + +void EspClass::restart(void) { + esp_restart(); +} + +uint32_t EspClass::getHeapSize(void) { + return heap_caps_get_total_size(MALLOC_CAP_INTERNAL); +} + +uint32_t EspClass::getFreeHeap(void) { + return heap_caps_get_free_size(MALLOC_CAP_INTERNAL); +} + +uint32_t EspClass::getMinFreeHeap(void) { + return heap_caps_get_minimum_free_size(MALLOC_CAP_INTERNAL); +} + +uint32_t EspClass::getMaxAllocHeap(void) { + return heap_caps_get_largest_free_block(MALLOC_CAP_INTERNAL); +} + +uint32_t EspClass::getPsramSize(void) { + if (psramFound()) { + return heap_caps_get_total_size(MALLOC_CAP_SPIRAM); + } + return 0; +} + +uint32_t EspClass::getFreePsram(void) { + if (psramFound()) { + return heap_caps_get_free_size(MALLOC_CAP_SPIRAM); + } + return 0; +} + +uint32_t EspClass::getMinFreePsram(void) { + if (psramFound()) { + return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM); + } + return 0; +} + +uint32_t EspClass::getMaxAllocPsram(void) { + if (psramFound()) { + return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM); + } + return 0; +} + +static uint32_t sketchSize(sketchSize_t response) { + esp_image_metadata_t data; + const esp_partition_t *running = esp_ota_get_running_partition(); + if (!running) { + return 0; + } + const esp_partition_pos_t running_pos = { + .offset = running->address, + .size = running->size, + }; + data.start_addr = running_pos.offset; + esp_image_verify(ESP_IMAGE_VERIFY, &running_pos, &data); + if (response) { + return running_pos.size - data.image_len; + } else { + return data.image_len; + } +} + +uint32_t EspClass::getSketchSize() { + return sketchSize(SKETCH_SIZE_TOTAL); +} + +String EspClass::getSketchMD5() { + static String result; + if (result.length()) { + return result; + } + uint32_t lengthLeft = getSketchSize(); + + const esp_partition_t *running = esp_ota_get_running_partition(); + if (!running) { + log_e("Partition could not be found"); + return String(); + } + + const size_t bufSize = SPI_FLASH_SEC_SIZE; + uint8_t *pb = (uint8_t *)malloc(bufSize); + if (!pb) { + log_e("Not enough memory to allocate buffer"); + return String(); + } + uint32_t offset = 0; + + MD5Builder md5; + md5.begin(); + while (lengthLeft > 0) { + size_t readBytes = (lengthLeft < bufSize) ? lengthLeft : bufSize; + if (!ESP.flashRead(running->address + offset, (uint32_t *)pb, (readBytes + 3) & ~3)) { + free(pb); + log_e("Could not read buffer from flash"); + return String(); + } + md5.add(pb, readBytes); + lengthLeft -= readBytes; + offset += readBytes; + +#if CONFIG_FREERTOS_UNICORE + delay(1); // Fix solo WDT +#endif + } + free(pb); + md5.calculate(); + result = md5.toString(); + return result; +} + +uint32_t EspClass::getFreeSketchSpace() { + const esp_partition_t *_partition = esp_ota_get_next_update_partition(NULL); + if (!_partition) { + return 0; + } + + return _partition->size; +} + +uint16_t EspClass::getChipRevision(void) { + esp_chip_info_t chip_info; + esp_chip_info(&chip_info); + return chip_info.revision; +} + +const char *EspClass::getChipModel(void) { +#if CONFIG_IDF_TARGET_ESP32 + uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE); + uint32_t pkg_ver = chip_ver & 0x7; + switch (pkg_ver) { + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6: + if ((getChipRevision() / 100) == 3) { + return "ESP32-D0WDQ6-V3"; + } else { + return "ESP32-D0WDQ6"; + } + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5: + if ((getChipRevision() / 100) == 3) { + return "ESP32-D0WD-V3"; + } else { + return "ESP32-D0WD"; + } + case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5: return "ESP32-D2WD"; + case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH: return "ESP32-U4WDH"; + case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4: return "ESP32-PICO-D4"; + case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: return "ESP32-PICO-V3-02"; + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3: return "ESP32-D0WDR2-V3"; + default: return "Unknown"; + } +#elif CONFIG_IDF_TARGET_ESP32S2 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); + switch (pkg_ver) { + case 0: return "ESP32-S2"; + case 1: return "ESP32-S2FH16"; + case 2: return "ESP32-S2FH32"; + default: return "ESP32-S2 (Unknown)"; + } +#else + esp_chip_info_t chip_info; + esp_chip_info(&chip_info); + switch (chip_info.model) { + case CHIP_ESP32S3: return "ESP32-S3"; + case CHIP_ESP32C3: return "ESP32-C3"; + case CHIP_ESP32C2: return "ESP32-C2"; + case CHIP_ESP32C6: return "ESP32-C6"; + case CHIP_ESP32H2: return "ESP32-H2"; + case CHIP_ESP32P4: return "ESP32-P4"; +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) + case CHIP_ESP32C5: return "ESP32-C5"; + case CHIP_ESP32C61: return "ESP32-C61"; + case CHIP_ESP32H21: return "ESP32-H21"; +#endif + default: return "UNKNOWN"; + } +#endif +} + +uint8_t EspClass::getChipCores(void) { + esp_chip_info_t chip_info; + esp_chip_info(&chip_info); + return chip_info.cores; +} + +const char *EspClass::getSdkVersion(void) { + return esp_get_idf_version(); +} + +const char *EspClass::getCoreVersion(void) { + return ESP_ARDUINO_VERSION_STR; +} + +uint32_t ESP_getFlashChipId(void) { + uint32_t id = g_rom_flashchip.device_id; + id = ((id & 0xff) << 16) | ((id >> 16) & 0xff) | (id & 0xff00); + return id; +} + +uint32_t EspClass::getFlashChipSize(void) { + uint32_t id = (ESP_getFlashChipId() >> 16) & 0xFF; + return 2 << (id - 1); +} + +uint32_t EspClass::getFlashChipSpeed(void) { + esp_image_header_t fhdr; + if (esp_flash_read(esp_flash_default_chip, (void *)&fhdr, ESP_FLASH_IMAGE_BASE, sizeof(esp_image_header_t)) && fhdr.magic != ESP_IMAGE_HEADER_MAGIC) { + return 0; + } + return magicFlashChipSpeed(fhdr.spi_speed); +} + +FlashMode_t EspClass::getFlashChipMode(void) { +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 + uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL); +#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 + uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8); +#else + uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0)); +#endif + /* Not all of the following constants are already defined in older versions of spi_reg.h, so do it manually for now*/ + if (spi_ctrl & BIT(24)) { //SPI_FREAD_QIO + return (FM_QIO); + } else if (spi_ctrl & BIT(20)) { //SPI_FREAD_QUAD + return (FM_QOUT); + } else if (spi_ctrl & BIT(23)) { //SPI_FREAD_DIO + return (FM_DIO); + } else if (spi_ctrl & BIT(14)) { // SPI_FREAD_DUAL + return (FM_DOUT); + } else if (spi_ctrl & BIT(13)) { //SPI_FASTRD_MODE + return (FM_FAST_READ); + } else { + return (FM_SLOW_READ); + } +} + +uint32_t EspClass::magicFlashChipSize(uint8_t flashByte) { + /* + FLASH_SIZES = { + "1MB": 0x00, + "2MB": 0x10, + "4MB": 0x20, + "8MB": 0x30, + "16MB": 0x40, + "32MB": 0x50, + "64MB": 0x60, + "128MB": 0x70, + } +*/ + switch (flashByte & 0x0F) { + case 0x0: return (1_MB); // 8 MBit (1MB) + case 0x1: return (2_MB); // 16 MBit (2MB) + case 0x2: return (4_MB); // 32 MBit (4MB) + case 0x3: return (8_MB); // 64 MBit (8MB) + case 0x4: return (16_MB); // 128 MBit (16MB) + case 0x5: return (32_MB); // 256 MBit (32MB) + case 0x6: return (64_MB); // 512 MBit (64MB) + case 0x7: return (128_MB); // 1 GBit (128MB) + default: // fail? + return 0; + } +} + +uint32_t EspClass::magicFlashChipSpeed(uint8_t flashByte) { +#if CONFIG_IDF_TARGET_ESP32C2 + /* + FLASH_FREQUENCY = { + "60m": 0xF, + "30m": 0x0, + "20m": 0x1, + "15m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0xF: return (60_MHz); + case 0x0: return (30_MHz); + case 0x1: return (20_MHz); + case 0x2: return (15_MHz); + default: // fail? + return 0; + } + +#elif CONFIG_IDF_TARGET_ESP32C6 + /* + FLASH_FREQUENCY = { + "80m": 0x0, # workaround for wrong mspi HS div value in ROM + "40m": 0x0, + "20m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0x0: return (80_MHz); + case 0x2: return (20_MHz); + default: // fail? + return 0; + } + +#elif CONFIG_IDF_TARGET_ESP32C61 + /* + FLASH_FREQUENCY = { + "80m": 0xF, + "40m": 0x0, + "20m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0xF: return (80_MHz); + case 0x0: return (40_MHz); + case 0x2: return (20_MHz); + default: // fail? + return 0; + } + +#elif CONFIG_IDF_TARGET_ESP32H2 + + /* + FLASH_FREQUENCY = { + "48m": 0xF, + "24m": 0x0, + "16m": 0x1, + "12m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0xF: return (48_MHz); + case 0x0: return (24_MHz); + case 0x1: return (16_MHz); + case 0x2: return (12_MHz); + default: // fail? + return 0; + } + +#else + /* + FLASH_FREQUENCY = { + "80m": 0xF, + "40m": 0x0, + "26m": 0x1, + "20m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0xF: return (80_MHz); + case 0x0: return (40_MHz); + case 0x1: return (26_MHz); + case 0x2: return (20_MHz); + default: // fail? + return 0; + } +#endif +} + +FlashMode_t EspClass::magicFlashChipMode(uint8_t flashByte) { + FlashMode_t mode = (FlashMode_t)flashByte; + if (mode > FM_SLOW_READ) { + mode = FM_UNKNOWN; + } + return mode; +} + +bool EspClass::flashEraseSector(uint32_t sector) { + return esp_flash_erase_region(esp_flash_default_chip, sector * SPI_FLASH_SEC_SIZE, SPI_FLASH_SEC_SIZE) == ESP_OK; +} + +// Warning: These functions do not work with encrypted flash +bool EspClass::flashWrite(uint32_t offset, uint32_t *data, size_t size) { + return esp_flash_write(esp_flash_default_chip, (const void *)data, offset, size) == ESP_OK; +} + +bool EspClass::flashRead(uint32_t offset, uint32_t *data, size_t size) { + return esp_flash_read(esp_flash_default_chip, (void *)data, offset, size) == ESP_OK; +} + +bool EspClass::partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size) { + return esp_partition_erase_range(partition, offset, size) == ESP_OK; +} + +bool EspClass::partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) { + return esp_partition_write(partition, offset, data, size) == ESP_OK; +} + +bool EspClass::partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) { + return esp_partition_read(partition, offset, data, size) == ESP_OK; +} + +uint64_t EspClass::getEfuseMac(void) { + uint64_t _chipmacid = 0LL; + esp_efuse_mac_get_default((uint8_t *)(&_chipmacid)); + return _chipmacid; +} + +// ============================================================================ +// Flash Frequency Runtime Detection +// ============================================================================ + +/** + * @brief Read the source clock frequency using ESP-IDF HAL functions + * @return Source clock frequency in MHz (80, 120, 160, or 240) + */ +uint8_t EspClass::getFlashSourceFrequencyMHz(void) { +#if CONFIG_IDF_TARGET_ESP32 + // ESP32: Use HAL function + return spi_flash_ll_get_source_clock_freq_mhz(0); // host_id = 0 for SPI0 +#else + // All modern MCUs: Use spimem HAL function + return spimem_flash_ll_get_source_freq_mhz(); +#endif +} + +/** + * @brief Read the clock divider from hardware using HAL structures + * Based on ESP-IDF HAL implementation: + * - ESP32: Uses SPI1.clock (typedef in spi_flash_ll.h) + * - All newer MCUs: Use SPIMEM1.clock (typedef in spimem_flash_ll.h) + * @return Clock divider value (1 = no division, 2 = divide by 2, etc.) + */ +uint8_t EspClass::getFlashClockDivider(void) { +#if CONFIG_IDF_TARGET_ESP32 + // ESP32: Flash uses SPI1 + // See: line 52: esp-idf/components/hal/esp32/include/hal/spi_flash_ll.h + if (SPI1.clock.clk_equ_sysclk) { + return 1; // 1:1 clock + } + return SPI1.clock.clkcnt_n + 1; +#else + // All newer MCUs: Flash uses SPIMEM1 + // See: esp-idf/components/hal/esp32*/include/hal/spimem_flash_ll.h + // Example S3: line 38: typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t; + // Example C5: lines 97-99: esp-idf/components/soc/esp32c5/mp/include/soc/spi_mem_struct.h + if (SPIMEM1.clock.clk_equ_sysclk) { + return 1; // 1:1 clock + } + return SPIMEM1.clock.clkcnt_n + 1; +#endif +} + +/** + * @brief Get the actual flash frequency in MHz + * @return Flash frequency in MHz (80, 120, 160, or 240) + */ +uint32_t EspClass::getFlashFrequencyMHz(void) { + uint8_t source = getFlashSourceFrequencyMHz(); + uint8_t divider = getFlashClockDivider(); + + if (divider == 0) { + divider = 1; // Safety check + } + + return source / divider; +} diff --git a/cores/esp32/Esp.h b/cores/esp32/Esp.h new file mode 100644 index 0000000..7d5266f --- /dev/null +++ b/cores/esp32/Esp.h @@ -0,0 +1,125 @@ +/* + Esp.h - ESP31B-specific APIs + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ESP_H +#define ESP_H + +#include +#include +#include +#include "esp_cpu.h" + +/** + * AVR macros for WDT management + */ +typedef enum { + WDTO_0MS = 0, //!< WDTO_0MS + WDTO_15MS = 15, //!< WDTO_15MS + WDTO_30MS = 30, //!< WDTO_30MS + WDTO_60MS = 60, //!< WDTO_60MS + WDTO_120MS = 120, //!< WDTO_120MS + WDTO_250MS = 250, //!< WDTO_250MS + WDTO_500MS = 500, //!< WDTO_500MS + WDTO_1S = 1000, //!< WDTO_1S + WDTO_2S = 2000, //!< WDTO_2S + WDTO_4S = 4000, //!< WDTO_4S + WDTO_8S = 8000 //!< WDTO_8S +} WDTO_t; + +typedef enum { + FM_QIO = 0x00, + FM_QOUT = 0x01, + FM_DIO = 0x02, + FM_DOUT = 0x03, + FM_FAST_READ = 0x04, + FM_SLOW_READ = 0x05, + FM_UNKNOWN = 0xff +} FlashMode_t; + +typedef enum { + SKETCH_SIZE_TOTAL = 0, + SKETCH_SIZE_FREE = 1 +} sketchSize_t; + +class EspClass { +public: + EspClass() {} + ~EspClass() {} + void restart(); + + //Internal RAM + uint32_t getHeapSize(); //total heap size + uint32_t getFreeHeap(); //available heap + uint32_t getMinFreeHeap(); //lowest level of free heap since boot + uint32_t getMaxAllocHeap(); //largest block of heap that can be allocated at once + + //SPI RAM + uint32_t getPsramSize(); + uint32_t getFreePsram(); + uint32_t getMinFreePsram(); + uint32_t getMaxAllocPsram(); + + uint16_t getChipRevision(); + const char *getChipModel(); + uint8_t getChipCores(); + uint32_t getCpuFreqMHz() { + return getCpuFrequencyMhz(); + } + inline uint32_t getCycleCount() __attribute__((always_inline)); + + const char *getSdkVersion(); //version of ESP-IDF + const char *getCoreVersion(); //version of this core + + void deepSleep(uint64_t time_us); + + uint32_t getFlashChipSize(); + uint32_t getFlashChipSpeed(); + FlashMode_t getFlashChipMode(); + + // Flash frequency runtime detection + uint32_t getFlashFrequencyMHz(); + uint8_t getFlashSourceFrequencyMHz(); + uint8_t getFlashClockDivider(); + + uint32_t magicFlashChipSize(uint8_t flashByte); + uint32_t magicFlashChipSpeed(uint8_t flashByte); + FlashMode_t magicFlashChipMode(uint8_t flashByte); + + uint32_t getSketchSize(); + String getSketchMD5(); + uint32_t getFreeSketchSpace(); + + bool flashEraseSector(uint32_t sector); + bool flashWrite(uint32_t offset, uint32_t *data, size_t size); + bool flashRead(uint32_t offset, uint32_t *data, size_t size); + + bool partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size); + bool partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size); + bool partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size); + + uint64_t getEfuseMac(); +}; + +uint32_t ARDUINO_ISR_ATTR EspClass::getCycleCount() { + return (uint32_t)esp_cpu_get_cycle_count(); +} + +extern EspClass ESP; + +#endif //ESP_H diff --git a/cores/esp32/FirmwareMSC.cpp b/cores/esp32/FirmwareMSC.cpp new file mode 100644 index 0000000..2e944ad --- /dev/null +++ b/cores/esp32/FirmwareMSC.cpp @@ -0,0 +1,427 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "FirmwareMSC.h" + +#if CONFIG_TINYUSB_MSC_ENABLED + +#include +#include "esp_partition.h" +#include "esp_ota_ops.h" +#include "esp_image_format.h" +#include "pins_arduino.h" +#include "esp32-hal.h" +#include "firmware_msc_fat.h" +#include "spi_flash_mmap.h" + +#ifndef USB_FW_MSC_VENDOR_ID +#define USB_FW_MSC_VENDOR_ID "ESP32" //max 8 chars +#endif +#ifndef USB_FW_MSC_PRODUCT_ID +#define USB_FW_MSC_PRODUCT_ID "Firmware MSC" //max 16 chars +#endif +#ifndef USB_FW_MSC_PRODUCT_REVISION +#define USB_FW_MSC_PRODUCT_REVISION "1.0" //max 4 chars +#endif +#ifndef USB_FW_MSC_VOLUME_NAME +#define USB_FW_MSC_VOLUME_NAME "ESP32-FWMSC" //max 11 chars +#endif +#ifndef USB_FW_MSC_SERIAL_NUMBER +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 +#endif + +ESP_EVENT_DEFINE_BASE(ARDUINO_FIRMWARE_MSC_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +//General Variables +static uint8_t *msc_ram_disk = NULL; +static fat_boot_sector_t *msc_boot = NULL; +static uint8_t *msc_table = NULL; +static uint16_t msc_table_sectors = 0; +static uint16_t msc_total_sectors = 0; +static bool mcs_is_fat16 = false; + +//Firmware Read +static const esp_partition_t *msc_run_partition = NULL; +static uint16_t fw_start_sector = 0; +static uint16_t fw_end_sector = 0; +static size_t fw_size = 0; +static fat_dir_entry_t *fw_entry = NULL; + +//Firmware Write +typedef enum { + MSC_UPDATE_IDLE, + MSC_UPDATE_STARTING, + MSC_UPDATE_RUNNING, + MSC_UPDATE_END +} msc_update_state_t; + +static const esp_partition_t *msc_ota_partition = NULL; +static msc_update_state_t msc_update_state = MSC_UPDATE_IDLE; +static uint16_t msc_update_start_sector = 0; +static uint32_t msc_update_bytes_written = 0; +static fat_dir_entry_t *msc_update_entry = NULL; + +static uint32_t get_firmware_size(const esp_partition_t *partition) { + esp_image_metadata_t data; + const esp_partition_pos_t running_pos = { + .offset = partition->address, + .size = partition->size, + }; + data.start_addr = running_pos.offset; + esp_image_verify(ESP_IMAGE_VERIFY, &running_pos, &data); + return data.image_len; +} + +//Get number of sectors required based on the size of the firmware and OTA partition +static size_t msc_update_get_required_disk_sectors() { + size_t data_sectors = 16; + size_t total_sectors = 0; + msc_run_partition = esp_ota_get_running_partition(); + msc_ota_partition = esp_ota_get_next_update_partition(NULL); + if (msc_run_partition) { + fw_size = get_firmware_size(msc_run_partition); + data_sectors += FAT_SIZE_TO_SECTORS(fw_size); + log_d("APP size: %u (%u sectors)", fw_size, FAT_SIZE_TO_SECTORS(fw_size)); + } else { + log_w("APP partition not found. Reading disabled"); + } + if (msc_ota_partition) { + data_sectors += FAT_SIZE_TO_SECTORS(msc_ota_partition->size); + log_d("OTA size: %u (%u sectors)", msc_ota_partition->size, FAT_SIZE_TO_SECTORS(msc_ota_partition->size)); + } else { + log_w("OTA partition not found. Writing disabled"); + } + msc_table_sectors = fat_sectors_per_alloc_table(data_sectors, false); + total_sectors = data_sectors + msc_table_sectors + 2; + if (total_sectors > 0xFF4) { + log_d("USING FAT16"); + mcs_is_fat16 = true; + total_sectors -= msc_table_sectors; + msc_table_sectors = fat_sectors_per_alloc_table(data_sectors, true); + total_sectors += msc_table_sectors; + } else { + log_d("USING FAT12"); + mcs_is_fat16 = false; + } + log_d("FAT sector size: %u", DISK_SECTOR_SIZE); + log_d("FAT data sectors: %u", data_sectors); + log_d("FAT table sectors: %u", msc_table_sectors); + log_d("FAT total sectors: %u (%uKB)", total_sectors, (total_sectors * DISK_SECTOR_SIZE) / 1024); + return total_sectors; +} + +//setup the ramdisk and add the firmware download file +static bool msc_update_setup_disk(const char *volume_label, uint32_t serial_number) { + msc_total_sectors = msc_update_get_required_disk_sectors(); + uint8_t ram_sectors = msc_table_sectors + 2; + msc_ram_disk = (uint8_t *)calloc(ram_sectors, DISK_SECTOR_SIZE); + if (!msc_ram_disk) { + log_e("Failed to allocate RAM Disk: %u bytes", ram_sectors * DISK_SECTOR_SIZE); + return false; + } + fw_start_sector = ram_sectors; + fw_end_sector = fw_start_sector; + msc_boot = fat_add_boot_sector(msc_ram_disk, msc_total_sectors, msc_table_sectors, fat_file_system_type(mcs_is_fat16), volume_label, serial_number); + msc_table = fat_add_table(msc_ram_disk, msc_boot, mcs_is_fat16); + //fat_dir_entry_t * label = fat_add_label(msc_ram_disk, volume_label); + if (msc_run_partition) { + fw_entry = fat_add_root_file(msc_ram_disk, 0, "FIRMWARE", "BIN", fw_size, 2, mcs_is_fat16); + fw_end_sector = FAT_SIZE_TO_SECTORS(fw_size) + fw_start_sector; + } + return true; +} + +static void msc_update_delete_disk() { + fw_entry = NULL; + fw_size = 0; + fw_end_sector = 0; + fw_start_sector = 0; + msc_table = NULL; + msc_boot = NULL; + msc_table_sectors = 0; + msc_total_sectors = 0; + msc_run_partition = NULL; + msc_ota_partition = NULL; + msc_update_state = MSC_UPDATE_IDLE; + msc_update_start_sector = 0; + msc_update_bytes_written = 0; + msc_update_entry = NULL; + free(msc_ram_disk); + msc_ram_disk = NULL; +} + +//filter out entries to only include BINs in the root folder +static fat_dir_entry_t *msc_update_get_root_bin_entry(uint8_t index) { + fat_dir_entry_t *entry = (fat_dir_entry_t *)(msc_ram_disk + ((msc_boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE) + (index * sizeof(fat_dir_entry_t))); + fat_lfn_entry_t *lfn = (fat_lfn_entry_t *)entry; + + //empty entry + if (entry->file_magic == 0) { + return NULL; + } + //long file name + if (lfn->attr == 0x0F && lfn->type == 0x00 && lfn->first_cluster == 0x0000) { + return NULL; + } + //only files marked as archives + if (entry->file_attr != FAT_FILE_ATTR_ARCHIVE) { + return NULL; + } + //deleted + if (entry->file_magic == 0xE5 || entry->file_magic == 0x05) { + return NULL; + } + //not bins + if (memcmp("BIN", entry->file_extension, 3)) { + return NULL; + } + return entry; +} + +//get an empty bin (the host will add an entry for file about to be written with size of zero) +static fat_dir_entry_t *msc_update_find_new_bin() { + for (uint8_t i = 16; i;) { + i--; + fat_dir_entry_t *entry = msc_update_get_root_bin_entry(i); + if (entry && entry->file_size == 0) { + return entry; + } + } + return NULL; +} + +//get a bin starting from particular sector +static fat_dir_entry_t *msc_update_find_bin(uint16_t sector) { + for (uint8_t i = 16; i;) { + i--; + fat_dir_entry_t *entry = msc_update_get_root_bin_entry(i); + if (entry && entry->data_start_sector == (sector - msc_boot->sectors_per_alloc_table)) { + return entry; + } + } + return NULL; +} + +//write the new data and erase the flash blocks when necessary +static esp_err_t msc_update_write(const esp_partition_t *partition, uint32_t offset, void *data, size_t size) { + esp_err_t err = ESP_OK; + if ((offset & (SPI_FLASH_SEC_SIZE - 1)) == 0) { + err = esp_partition_erase_range(partition, offset, SPI_FLASH_SEC_SIZE); + log_v("ERASE[0x%08X]: %s", offset, (err != ESP_OK) ? "FAIL" : "OK"); + if (err != ESP_OK) { + return err; + } + } + return esp_partition_write(partition, offset, data, size); +} + +//called when error was encountered while updating +static void msc_update_error() { + log_e("UPDATE_ERROR: %u", msc_update_bytes_written); + arduino_firmware_msc_event_data_t p; + p.error.size = msc_update_bytes_written; + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_ERROR_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); + msc_update_state = MSC_UPDATE_IDLE; + msc_update_entry = NULL; + msc_update_bytes_written = 0; + msc_update_start_sector = 0; +} + +//called when all firmware bytes have been received +static void msc_update_end() { + log_d("UPDATE_END: %u", msc_update_entry->file_size); + msc_update_state = MSC_UPDATE_END; + size_t ota_size = get_firmware_size(msc_ota_partition); + if (ota_size != msc_update_entry->file_size) { + log_e("OTA SIZE MISMATCH %u != %u", ota_size, msc_update_entry->file_size); + msc_update_error(); + return; + } + if (!ota_size || esp_ota_set_boot_partition(msc_ota_partition) != ESP_OK) { + log_e("ENABLING OTA PARTITION FAILED"); + msc_update_error(); + return; + } + arduino_firmware_msc_event_data_t p; + p.end.size = msc_update_entry->file_size; + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_END_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); +} + +static int32_t msc_write(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) { + //log_d("lba: %u, offset: %u, bufsize: %u", lba, offset, bufsize); + if (lba < fw_start_sector) { + //write to sectors that are in RAM + memcpy(msc_ram_disk + (lba * DISK_SECTOR_SIZE) + offset, buffer, bufsize); + if (msc_ota_partition && lba == (fw_start_sector - 1)) { + //monitor the root folder table + if (msc_update_state <= MSC_UPDATE_RUNNING) { + fat_dir_entry_t *update_entry = msc_update_find_new_bin(); + if (update_entry) { + if (msc_update_entry) { + log_v("REPLACING ENTRY"); + } else { + log_v("ASSIGNING ENTRY"); + } + if (msc_update_state <= MSC_UPDATE_STARTING) { + msc_update_state = MSC_UPDATE_STARTING; + msc_update_bytes_written = 0; + msc_update_start_sector = 0; + } + msc_update_entry = update_entry; + } else if (msc_update_state == MSC_UPDATE_RUNNING) { + if (!msc_update_entry && msc_update_start_sector) { + msc_update_entry = msc_update_find_bin(msc_update_start_sector); + } + if (msc_update_entry && msc_update_bytes_written >= msc_update_entry->file_size) { + msc_update_end(); + } + } + } + } + } else if (msc_ota_partition && lba >= msc_update_start_sector) { + //handle writes to the region where the new firmware will be uploaded + arduino_firmware_msc_event_data_t p; + if (msc_update_state <= MSC_UPDATE_STARTING && buffer[0] == 0xE9) { + msc_update_state = MSC_UPDATE_RUNNING; + msc_update_start_sector = lba; + msc_update_bytes_written = 0; + log_d("UPDATE_START: %u (0x%02X)", lba, lba - msc_boot->sectors_per_alloc_table); + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_START_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); + if (msc_update_write(msc_ota_partition, ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) == ESP_OK) { + log_v("UPDATE_WRITE: %u %u", ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, bufsize); + msc_update_bytes_written = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset + bufsize; + p.write.offset = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset; + p.write.size = bufsize; + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_WRITE_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); + } else { + msc_update_error(); + return 0; + } + } else if (msc_update_state == MSC_UPDATE_RUNNING) { + if (msc_update_entry && msc_update_entry->file_size && msc_update_bytes_written < msc_update_entry->file_size + && (msc_update_bytes_written + bufsize) >= msc_update_entry->file_size) { + bufsize = msc_update_entry->file_size - msc_update_bytes_written; + } + if (msc_update_write(msc_ota_partition, ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) == ESP_OK) { + log_v("UPDATE_WRITE: %u %u", ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, bufsize); + msc_update_bytes_written = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset + bufsize; + p.write.offset = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset; + p.write.size = bufsize; + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_WRITE_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); + if (msc_update_entry && msc_update_entry->file_size && msc_update_bytes_written >= msc_update_entry->file_size) { + msc_update_end(); + } + } else { + msc_update_error(); + return 0; + } + } + } + return bufsize; +} + +static int32_t msc_read(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) { + //log_d("lba: %u, offset: %u, bufsize: %u", lba, offset, bufsize); + if (lba < fw_start_sector) { + memcpy(buffer, msc_ram_disk + (lba * DISK_SECTOR_SIZE) + offset, bufsize); + } else if (msc_run_partition && lba < fw_end_sector) { + //read the currently running firmware + if (esp_partition_read(msc_run_partition, ((lba - fw_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) != ESP_OK) { + return 0; + } + } else { + memset(buffer, 0, bufsize); + } + return bufsize; +} + +static bool msc_start_stop(uint8_t power_condition, bool start, bool load_eject) { + //log_d("power: %u, start: %u, eject: %u", power_condition, start, load_eject); + arduino_firmware_msc_event_data_t p; + p.power.power_condition = power_condition; + p.power.start = start; + p.power.load_eject = load_eject; + arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_POWER_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY); + return true; +} + +static volatile TaskHandle_t msc_task_handle = NULL; +static void msc_task(void *pvParameters) { + for (;;) { + if (msc_update_state == MSC_UPDATE_END) { + delay(100); + esp_restart(); + } + delay(100); + } + msc_task_handle = NULL; + vTaskDelete(NULL); +} + +FirmwareMSC::FirmwareMSC() : msc() {} + +FirmwareMSC::~FirmwareMSC() { + end(); +} + +bool FirmwareMSC::begin() { + if (msc_ram_disk) { + return true; + } + + if (!msc_update_setup_disk(USB_FW_MSC_VOLUME_NAME, USB_FW_MSC_SERIAL_NUMBER)) { + return false; + } + + if (!msc_task_handle) { + xTaskCreateUniversal(msc_task, "msc_disk", 1024, NULL, 2, (TaskHandle_t *)&msc_task_handle, 0); + if (!msc_task_handle) { + msc_update_delete_disk(); + return false; + } + } + + msc.vendorID(USB_FW_MSC_VENDOR_ID); + msc.productID(USB_FW_MSC_PRODUCT_ID); + msc.productRevision(USB_FW_MSC_PRODUCT_REVISION); + msc.onStartStop(msc_start_stop); + msc.onRead(msc_read); + msc.onWrite(msc_write); + msc.mediaPresent(true); + msc.begin(msc_boot->fat12_sector_num, DISK_SECTOR_SIZE); + return true; +} + +void FirmwareMSC::end() { + msc.end(); + if (msc_task_handle) { + vTaskDelete(msc_task_handle); + msc_task_handle = NULL; + } + msc_update_delete_disk(); +} + +void FirmwareMSC::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_FIRMWARE_MSC_ANY_EVENT, callback); +} +void FirmwareMSC::onEvent(arduino_firmware_msc_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_FIRMWARE_MSC_EVENTS, event, callback, this); +} + +#if ARDUINO_USB_MSC_ON_BOOT +FirmwareMSC MSC_Update; +#endif + +#endif /* CONFIG_USB_MSC_ENABLED */ diff --git a/cores/esp32/FirmwareMSC.h b/cores/esp32/FirmwareMSC.h new file mode 100644 index 0000000..3eaa184 --- /dev/null +++ b/cores/esp32/FirmwareMSC.h @@ -0,0 +1,70 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include "USBMSC.h" + +#if CONFIG_TINYUSB_MSC_ENABLED + +#include "esp_event.h" + +ESP_EVENT_DECLARE_BASE(ARDUINO_FIRMWARE_MSC_EVENTS); + +typedef enum { + ARDUINO_FIRMWARE_MSC_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_FIRMWARE_MSC_START_EVENT = 0, + ARDUINO_FIRMWARE_MSC_WRITE_EVENT, + ARDUINO_FIRMWARE_MSC_END_EVENT, + ARDUINO_FIRMWARE_MSC_ERROR_EVENT, + ARDUINO_FIRMWARE_MSC_POWER_EVENT, + ARDUINO_FIRMWARE_MSC_MAX_EVENT, +} arduino_firmware_msc_event_t; + +typedef union { + struct { + size_t offset; + size_t size; + } write; + struct { + uint8_t power_condition; + bool start; + bool load_eject; + } power; + struct { + size_t size; + } end; + struct { + size_t size; + } error; +} arduino_firmware_msc_event_data_t; + +class FirmwareMSC { +private: + USBMSC msc; + +public: + FirmwareMSC(); + ~FirmwareMSC(); + bool begin(); + void end(); + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_firmware_msc_event_t event, esp_event_handler_t callback); +}; + +#if ARDUINO_USB_MSC_ON_BOOT +extern FirmwareMSC MSC_Update; +#endif + +#endif /* CONFIG_TINYUSB_MSC_ENABLED */ diff --git a/cores/esp32/FunctionalInterrupt.cpp b/cores/esp32/FunctionalInterrupt.cpp new file mode 100644 index 0000000..bc3fdf1 --- /dev/null +++ b/cores/esp32/FunctionalInterrupt.cpp @@ -0,0 +1,34 @@ +/* + * FunctionalInterrupt.cpp + * + * Created on: 8 jul. 2018 + * Author: Herman + */ + +#include "FunctionalInterrupt.h" +#include "Arduino.h" + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void *); + +extern "C" { +extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type, bool functional); +} + +void ARDUINO_ISR_ATTR interruptFunctional(void *arg) { + InterruptArgStructure *localArg = (InterruptArgStructure *)arg; + if (localArg->interruptFunction) { + localArg->interruptFunction(); + } +} + +void attachInterrupt(uint8_t pin, std::function intRoutine, int mode) { + // use the local interrupt routine which takes the ArgStructure as argument + __attachInterruptFunctionalArg(pin, (voidFuncPtrArg)interruptFunctional, new InterruptArgStructure{intRoutine}, mode, true); +} + +extern "C" { +void cleanupFunctional(void *arg) { + delete (InterruptArgStructure *)arg; +} +} diff --git a/cores/esp32/FunctionalInterrupt.h b/cores/esp32/FunctionalInterrupt.h new file mode 100644 index 0000000..4b31d32 --- /dev/null +++ b/cores/esp32/FunctionalInterrupt.h @@ -0,0 +1,22 @@ +/* + * FunctionalInterrupt.h + * + * Created on: 8 jul. 2018 + * Author: Herman + */ + +#ifndef CORE_CORE_FUNCTIONALINTERRUPT_H_ +#define CORE_CORE_FUNCTIONALINTERRUPT_H_ + +#include +#include + +struct InterruptArgStructure { + std::function interruptFunction; +}; + +// The extra set of parentheses here prevents macros defined +// in io_pin_remap.h from applying to this declaration. +void(attachInterrupt)(uint8_t pin, std::function intRoutine, int mode); + +#endif /* CORE_CORE_FUNCTIONALINTERRUPT_H_ */ diff --git a/cores/esp32/HEXBuilder.cpp b/cores/esp32/HEXBuilder.cpp new file mode 100644 index 0000000..52c53fe --- /dev/null +++ b/cores/esp32/HEXBuilder.cpp @@ -0,0 +1,89 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp32 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "HEXBuilder.h" +#include + +static uint8_t hex_char_to_byte(uint8_t c) { + return (c >= 'a' && c <= 'f') ? (c - ((uint8_t)'a' - 0xa)) + : (c >= 'A' && c <= 'F') ? (c - ((uint8_t)'A' - 0xA)) + : (c >= '0' && c <= '9') ? (c - (uint8_t)'0') + : 0x10; // unknown char is 16 +} + +bool HEXBuilder::isHexString(const char *str, size_t len) { + for (size_t i = 0; i < len; i++) { + if (isxdigit(str[i]) == 0) { + return false; + } + } + return true; +} + +bool HEXBuilder::isHexString(String str) { + return isHexString(str.c_str(), str.length()); +} + +size_t HEXBuilder::hex2bytes(unsigned char *out, size_t maxlen, String &in) { + return hex2bytes(out, maxlen, in.c_str()); +} + +size_t HEXBuilder::hex2bytes(unsigned char *out, size_t maxlen, const char *in) { + size_t len = 0; + for (; *in; in++) { + uint8_t c = hex_char_to_byte(*in); + // Silently skip anything unknown. + if (c > 15) { + continue; + } + + if (len & 1) { + if (len / 2 < maxlen) { + out[len / 2] |= c; + } + } else { + if (len / 2 < maxlen) { + out[len / 2] = c << 4; + } + } + len++; + } + return (len + 1) / 2; +} + +size_t HEXBuilder::bytes2hex(char *out, size_t maxlen, const unsigned char *in, size_t len) { + for (size_t i = 0; i < len; i++) { + if (i * 2 + 1 < maxlen) { + sprintf(out + (i * 2), "%02x", in[i]); + } + } + return len * 2 + 1; +} + +String HEXBuilder::bytes2hex(const unsigned char *in, size_t len) { + size_t maxlen = len * 2 + 1; + char *out = (char *)malloc(maxlen); + if (!out) { + return String(); + } + bytes2hex(out, maxlen, in, len); + String ret = String(out); + free(out); + return ret; +} diff --git a/cores/esp32/HEXBuilder.h b/cores/esp32/HEXBuilder.h new file mode 100644 index 0000000..dc977c9 --- /dev/null +++ b/cores/esp32/HEXBuilder.h @@ -0,0 +1,39 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp32 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef HEXBuilder_h +#define HEXBuilder_h + +#include +#include + +// Basic hex/byte conversion class to be used by hash builders + +class HEXBuilder { +public: + static size_t hex2bytes(unsigned char *out, size_t maxlen, String &in); + static size_t hex2bytes(unsigned char *out, size_t maxlen, const char *in); + + static String bytes2hex(const unsigned char *in, size_t len); + static size_t bytes2hex(char *out, size_t maxlen, const unsigned char *in, size_t len); + + static bool isHexString(const char *str, size_t len); + static bool isHexString(String str); +}; +#endif diff --git a/cores/esp32/HWCDC.cpp b/cores/esp32/HWCDC.cpp new file mode 100644 index 0000000..87df44b --- /dev/null +++ b/cores/esp32/HWCDC.cpp @@ -0,0 +1,622 @@ +// Copyright 2015-2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USB.h" +#if SOC_USB_SERIAL_JTAG_SUPPORTED + +#include "Arduino.h" // defines ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE and ARDUINO_SERIAL_EVENT_TASK_PRIORITY +#include "esp32-hal.h" +#include "esp32-hal-periman.h" +#include "HWCDC.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/queue.h" +#include "freertos/ringbuf.h" +#include "esp_intr_alloc.h" +#include "soc/periph_defs.h" +#include "soc/io_mux_reg.h" +#include "soc/usb_serial_jtag_struct.h" +#pragma GCC diagnostic ignored "-Wvolatile" +#include "hal/usb_serial_jtag_ll.h" +#pragma GCC diagnostic warning "-Wvolatile" +#include "rom/ets_sys.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_HW_CDC_EVENTS); + +static RingbufHandle_t tx_ring_buf = NULL; +static QueueHandle_t rx_queue = NULL; +static uint8_t rx_data_buf[64] = {0}; +static intr_handle_t intr_handle = NULL; +static SemaphoreHandle_t tx_lock = NULL; +static volatile bool connected = false; + +// SOF in ISR causes problems for uploading firmware +//static volatile unsigned long lastSOF_ms; +//static volatile uint8_t SOF_TIMEOUT; + +// timeout has no effect when USB CDC is unplugged +static uint32_t tx_timeout_ms = 100; + +static esp_event_loop_handle_t arduino_hw_cdc_event_loop_handle = NULL; + +static esp_err_t + arduino_hw_cdc_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, BaseType_t *task_unblocked) { + if (arduino_hw_cdc_event_loop_handle == NULL) { + return ESP_FAIL; + } + return esp_event_isr_post_to(arduino_hw_cdc_event_loop_handle, event_base, event_id, event_data, event_data_size, task_unblocked); +} + +static esp_err_t + arduino_hw_cdc_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg) { + if (!arduino_hw_cdc_event_loop_handle) { + esp_event_loop_args_t event_task_args = { + .queue_size = 5, + .task_name = "arduino_hw_cdc_events", + .task_priority = ARDUINO_SERIAL_EVENT_TASK_PRIORITY, + .task_stack_size = ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE, + .task_core_id = tskNO_AFFINITY + }; + if (esp_event_loop_create(&event_task_args, &arduino_hw_cdc_event_loop_handle) != ESP_OK) { + log_e("esp_event_loop_create failed"); + } + } + if (arduino_hw_cdc_event_loop_handle == NULL) { + return ESP_FAIL; + } + return esp_event_handler_register_with(arduino_hw_cdc_event_loop_handle, event_base, event_id, event_handler, event_handler_arg); +} + +static void hw_cdc_isr_handler(void *arg) { + portBASE_TYPE xTaskWoken = 0; + uint32_t usbjtag_intr_status = 0; + arduino_hw_cdc_event_data_t event = {0}; + usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask(); + + if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY) { + // Interrupt tells us the host picked up the data we sent. + if (!HWCDC::isPlugged()) { + connected = false; + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + // USB is unplugged, nothing to be done here + return; + } else { + connected = true; + } + if (tx_ring_buf != NULL && usb_serial_jtag_ll_txfifo_writable() == 1) { + // We disable the interrupt here so that the interrupt won't be triggered if there is no data to send. + usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + size_t queued_size = 0; + uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpToFromISR(tx_ring_buf, &queued_size, 64); + // If the hardware fifo is available, write in it. Otherwise, do nothing. + if (queued_buff != NULL) { //Although tx_queued_bytes may be larger than 0. We may have interrupt before xRingbufferSend() was called. + //Copy the queued buffer into the TX FIFO + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + usb_serial_jtag_ll_write_txfifo(queued_buff, queued_size); + usb_serial_jtag_ll_txfifo_flush(); + vRingbufferReturnItemFromISR(tx_ring_buf, queued_buff, &xTaskWoken); + if (connected) { + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + //send event? + //ets_printf("TX:%u\n", queued_size); + event.tx.len = queued_size; + arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_TX_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken); + } + } else { + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + } + + if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT) { + // read rx buffer(max length is 64), and send available data to ringbuffer. + // Ensure the rx buffer size is larger than RX_MAX_SIZE. + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT); + uint32_t rx_fifo_len = usb_serial_jtag_ll_read_rxfifo(rx_data_buf, 64); + uint32_t i = 0; + for (i = 0; i < rx_fifo_len; i++) { + if (rx_queue == NULL || !xQueueSendFromISR(rx_queue, rx_data_buf + i, &xTaskWoken)) { + break; + } + } + event.rx.len = i; + arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_RX_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken); + connected = true; + } + + if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_BUS_RESET) { + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_BUS_RESET); + arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_BUS_RESET_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken); + connected = false; + } + + // SOF ISR is causing esptool to be unable to upload firmware to the board + // if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SOF) { + // usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SOF); + // lastSOF_ms = millis(); + // } + + if (xTaskWoken == pdTRUE) { + portYIELD_FROM_ISR(); + } +} + +// Moved to header file as inline function. Kept just as future reference. +//inline bool HWCDC::isPlugged(void) { +// SOF ISR is causing esptool to be unable to upload firmware to the board +// Timer test for SOF seems to work when uploading firmware +// return usb_serial_jtag_is_connected();//(lastSOF_ms + SOF_TIMEOUT) >= millis(); +//} + +bool HWCDC::isCDC_Connected() { + static bool running = false; + + // USB may be unplugged + if (!isPlugged()) { + connected = false; + running = false; + // SOF in ISR causes problems for uploading firmware + //SOF_TIMEOUT = 5; // SOF timeout when unplugged + return false; + } + //else { + // SOF_TIMEOUT = 50; // SOF timeout when plugged + //} + + if (connected) { + running = false; + return true; + } + + if (running == false && !connected) { // enables it only once! + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + + // this will feed CDC TX FIFO to trigger IN_EMPTY + usb_serial_jtag_ll_txfifo_flush(); + running = true; + return false; +} + +static void flushTXBuffer(const uint8_t *buffer, size_t size) { + if (!tx_ring_buf) { + return; + } + UBaseType_t uxItemsWaiting = 0; + vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting); + size_t freeSpace = xRingbufferGetCurFreeSize(tx_ring_buf); + size_t ringbufferLength = freeSpace + uxItemsWaiting; + + if (buffer == NULL) { + // just flush the whole ring buffer and exit - used by HWCDC::flush() + size_t queued_size = 0; + uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpTo(tx_ring_buf, &queued_size, 0, ringbufferLength); + if (queued_size && queued_buff != NULL) { + vRingbufferReturnItem(tx_ring_buf, (void *)queued_buff); + } + return; + } + if (size == 0) { + return; // nothing to do + } + if (freeSpace >= size) { + // there is enough space, just add the data to the ring buffer + if (xRingbufferSend(tx_ring_buf, (void *)buffer, size, 0) != pdTRUE) { + return; + } + } else { + // how many byte should be flushed to make space for the new data + size_t to_flush = size - freeSpace; + if (to_flush > ringbufferLength) { + to_flush = ringbufferLength; + } + size_t queued_size = 0; + uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpTo(tx_ring_buf, &queued_size, 0, to_flush); + if (queued_size && queued_buff != NULL) { + vRingbufferReturnItem(tx_ring_buf, (void *)queued_buff); + } + // now add the new data that fits into the ring buffer + uint8_t *bptr = (uint8_t *)buffer; + if (size >= ringbufferLength) { + size = ringbufferLength; + bptr = (uint8_t *)buffer + (size - ringbufferLength); + } + if (xRingbufferSend(tx_ring_buf, (void *)bptr, size, 0) != pdTRUE) { + return; + } + } + // flushes CDC FIFO + usb_serial_jtag_ll_txfifo_flush(); +} + +static void ARDUINO_ISR_ATTR cdc0_write_char(char c) { + if (tx_ring_buf == NULL) { + return; + } + if (!HWCDC::isConnected()) { + // just pop/push RingBuffer and apply FIFO policy + flushTXBuffer((const uint8_t *)&c, 1); + return; + } + if (xPortInIsrContext()) { + xRingbufferSendFromISR(tx_ring_buf, (void *)(&c), 1, NULL); + } else { + xRingbufferSend(tx_ring_buf, (void *)(&c), 1, tx_timeout_ms / portTICK_PERIOD_MS); + } + usb_serial_jtag_ll_txfifo_flush(); + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); +} + +HWCDC::HWCDC() { + // SOF in ISR causes problems for uploading firmware + // lastSOF_ms = 0; + // SOF_TIMEOUT = 5; +} + +HWCDC::~HWCDC() { + end(); +} + +// It should return just when USB is plugged and CDC is connected. +HWCDC::operator bool() const { + return HWCDC::isCDC_Connected(); +} + +void HWCDC::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_HW_CDC_ANY_EVENT, callback); +} + +void HWCDC::onEvent(arduino_hw_cdc_event_t event, esp_event_handler_t callback) { + arduino_hw_cdc_event_handler_register_with(ARDUINO_HW_CDC_EVENTS, event, callback, this); +} + +bool HWCDC::deinit(void *busptr) { + // avoid any recursion issue with Peripheral Manager perimanSetPinBus() call + static bool running = false; + if (running) { + return true; + } + running = true; + // Setting USB D+ D- pins + bool retCode = true; + retCode &= perimanClearPinBus(USB_INT_PHY0_DM_GPIO_NUM); + retCode &= perimanClearPinBus(USB_INT_PHY0_DP_GPIO_NUM); + if (retCode) { + // Force the host to re-enumerate (BUS_RESET) + pinMode(USB_INT_PHY0_DM_GPIO_NUM, OUTPUT_OPEN_DRAIN); + pinMode(USB_INT_PHY0_DP_GPIO_NUM, OUTPUT_OPEN_DRAIN); + digitalWrite(USB_INT_PHY0_DM_GPIO_NUM, LOW); + digitalWrite(USB_INT_PHY0_DP_GPIO_NUM, LOW); + } + // release the flag + running = false; + return retCode; +} + +void HWCDC::begin(unsigned long baud) { + if (tx_lock == NULL) { + tx_lock = xSemaphoreCreateMutex(); + } + //RX Buffer default has 256 bytes if not preset + if (rx_queue == NULL) { + if (!setRxBufferSize(256)) { + log_e("HW CDC RX Buffer error"); + } + } + //TX Buffer default has 256 bytes if not preset + if (tx_ring_buf == NULL) { + if (!setTxBufferSize(256)) { + log_e("HW CDC TX Buffer error"); + } + } + + // the HW Serial pins needs to be first deinited in order to allow `if(Serial)` to work :-( + // But this is also causing terminal to hang, so they are disabled + // deinit(NULL); + // delay(10); // USB Host has to enumerate it again + + // Peripheral Manager setting for USB D+ D- pins + uint8_t pin = USB_INT_PHY0_DM_GPIO_NUM; + if (perimanGetBusDeinit(ESP32_BUS_TYPE_USB_DM) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DM, HWCDC::deinit); + } + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_USB_DM, (void *)this, -1, -1)) { + goto err; + } + pin = USB_INT_PHY0_DP_GPIO_NUM; + if (perimanGetBusDeinit(ESP32_BUS_TYPE_USB_DP) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DP, HWCDC::deinit); + } + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_USB_DP, (void *)this, -1, -1)) { + goto err; + } + // Configure PHY + // USB_Serial_JTAG use internal PHY + USB_SERIAL_JTAG.conf0.phy_sel = 0; + // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) + USB_SERIAL_JTAG.conf0.pad_pull_override = 0; + // Enable USB D+ pullup + USB_SERIAL_JTAG.conf0.dp_pullup = 1; + // Enable USB pad function + USB_SERIAL_JTAG.conf0.usb_pad_enable = 1; + usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT | USB_SERIAL_JTAG_INTR_BUS_RESET); + // SOF ISR is causing esptool to be unable to upload firmware to the board + // usb_serial_jtag_ll_ena_intr_mask( + // USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT | USB_SERIAL_JTAG_INTR_BUS_RESET | USB_SERIAL_JTAG_INTR_SOF + // ); + if (!intr_handle && esp_intr_alloc(ETS_USB_SERIAL_JTAG_INTR_SOURCE, 0, hw_cdc_isr_handler, NULL, &intr_handle) != ESP_OK) { + isr_log_e("HW USB CDC failed to init interrupts"); + end(); + return; + } + return; + +err: + log_e("Serial JTAG Pin %u can't be set into Peripheral Manager.", pin); + end(); +} + +void HWCDC::end() { + //Disable/clear/free tx/rx interrupt. + usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + esp_intr_free(intr_handle); + intr_handle = NULL; + if (tx_lock != NULL) { + vSemaphoreDelete(tx_lock); + tx_lock = NULL; + } + setRxBufferSize(0); + setTxBufferSize(0); + if (arduino_hw_cdc_event_loop_handle) { + esp_event_loop_delete(arduino_hw_cdc_event_loop_handle); + arduino_hw_cdc_event_loop_handle = NULL; + } + HWCDC::deinit(this); + setDebugOutput(false); + connected = false; +} + +void HWCDC::setTxTimeoutMs(uint32_t timeout) { + tx_timeout_ms = timeout; +} + +/* + * WRITING +*/ + +size_t HWCDC::setTxBufferSize(size_t tx_queue_len) { + if (tx_ring_buf) { + vRingbufferDelete(tx_ring_buf); + tx_ring_buf = NULL; + } + if (!tx_queue_len) { + return 0; + } + tx_ring_buf = xRingbufferCreate(tx_queue_len, RINGBUF_TYPE_BYTEBUF); + if (!tx_ring_buf) { + return 0; + } + return tx_queue_len; +} + +int HWCDC::availableForWrite(void) { + if (tx_ring_buf == NULL || tx_lock == NULL) { + return 0; + } + if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return 0; + } + size_t a = xRingbufferGetCurFreeSize(tx_ring_buf); + xSemaphoreGive(tx_lock); + return a; +} + +size_t HWCDC::write(const uint8_t *buffer, size_t size) { + if (buffer == NULL || size == 0 || tx_ring_buf == NULL || tx_lock == NULL) { + return 0; + } + if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return 0; + } + if (!isCDC_Connected()) { + // just pop/push RingBuffer and apply FIFO policy + flushTXBuffer(buffer, size); + } else { + size_t space = xRingbufferGetCurFreeSize(tx_ring_buf); + size_t to_send = size, so_far = 0; + + if (space > size) { + space = size; + } + // Non-Blocking method, Sending data to ringbuffer, and handle the data in ISR. + if (space > 0 && xRingbufferSend(tx_ring_buf, (void *)(buffer), space, 0) != pdTRUE) { + size = 0; + } else { + to_send -= space; + so_far += space; + // Now trigger the ISR to read data from the ring buffer. + usb_serial_jtag_ll_txfifo_flush(); + if (connected) { + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + // tracks CDC transmission progress to avoid hanging if CDC is unplugged while still sending data + size_t last_toSend = to_send; + uint32_t tries = tx_timeout_ms; // waits 1ms per sending data attempt, in case CDC is unplugged + while (connected && to_send) { + space = xRingbufferGetCurFreeSize(tx_ring_buf); + if (space > to_send) { + space = to_send; + } + // Blocking method, Sending data to ringbuffer, and handle the data in ISR. + if (xRingbufferSend(tx_ring_buf, (void *)(buffer + so_far), space, tx_timeout_ms / portTICK_PERIOD_MS) != pdTRUE) { + size = so_far; + log_w("write failed due to ring buffer full - timeout"); + break; + } + so_far += space; + to_send -= space; + // Now trigger the ISR to read data from the ring buffer. + usb_serial_jtag_ll_txfifo_flush(); + if (connected) { + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + if (last_toSend == to_send) { + // no progress in sending data... USB CDC is probably unplugged + tries--; + delay(1); + } else { + last_toSend = to_send; + tries = tx_timeout_ms; // reset the timeout + } + if (tries == 0) { // CDC isn't connected anymore... + size = so_far; + log_w("write failed due to waiting USB Host - timeout"); + connected = false; + } + } + } + // CDC was disconnected while sending data ==> flush the TX buffer keeping the last data + if (to_send && !usb_serial_jtag_ll_txfifo_writable()) { + connected = false; + flushTXBuffer(buffer + so_far, to_send); + } + } + xSemaphoreGive(tx_lock); + return size; +} + +size_t HWCDC::write(uint8_t c) { + return write(&c, 1); +} + +void HWCDC::flush(void) { + if (tx_ring_buf == NULL || tx_lock == NULL) { + return; + } + if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return; + } + if (!isCDC_Connected()) { + flushTXBuffer(NULL, 0); + } else { + UBaseType_t uxItemsWaiting = 0; + vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting); + if (uxItemsWaiting) { + // Now trigger the ISR to read data from the ring buffer. + usb_serial_jtag_ll_txfifo_flush(); + if (connected) { + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + } + uint32_t tries = tx_timeout_ms; // waits 1ms per ISR sending data attempt, in case CDC is unplugged + while (connected && tries && uxItemsWaiting) { + delay(1); + UBaseType_t lastUxItemsWaiting = uxItemsWaiting; + vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting); + if (lastUxItemsWaiting == uxItemsWaiting) { + tries--; + } + if (connected) { + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY); + } + } + if (tries == 0) { // CDC isn't connected anymore... + connected = false; + flushTXBuffer(NULL, 0); // flushes all TX Buffer + } + } + xSemaphoreGive(tx_lock); +} + +/* + * READING +*/ + +size_t HWCDC::setRxBufferSize(size_t rx_queue_len) { + if (rx_queue) { + vQueueDelete(rx_queue); + rx_queue = NULL; + } + if (!rx_queue_len) { + return 0; + } + rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t)); + if (!rx_queue) { + return 0; + } + return rx_queue_len; +} + +int HWCDC::available(void) { + if (rx_queue == NULL) { + return -1; + } + return uxQueueMessagesWaiting(rx_queue); +} + +int HWCDC::peek(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c; + if (xQueuePeek(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +int HWCDC::read(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + if (xQueueReceive(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +size_t HWCDC::read(uint8_t *buffer, size_t size) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + size_t count = 0; + while (count < size && xQueueReceive(rx_queue, &c, 0)) { + buffer[count++] = c; + } + return count; +} + +/* + * DEBUG +*/ + +void HWCDC::setDebugOutput(bool en) { + if (en) { + uartSetDebug(NULL); + ets_install_putc2((void (*)(char)) & cdc0_write_char); + } else { + ets_install_putc2(NULL); + } + ets_install_putc1(NULL); // closes UART log output +} + +#if ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT // Hardware JTAG CDC selected +// USBSerial is always available to be used +HWCDC HWCDCSerial; +#endif + +#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */ diff --git a/cores/esp32/HWCDC.h b/cores/esp32/HWCDC.h new file mode 100644 index 0000000..29caae3 --- /dev/null +++ b/cores/esp32/HWCDC.h @@ -0,0 +1,118 @@ +// Copyright 2015-2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_USB_SERIAL_JTAG_SUPPORTED + +#include +#include "esp_event.h" +#include "Stream.h" +#include "driver/usb_serial_jtag.h" + +ESP_EVENT_DECLARE_BASE(ARDUINO_HW_CDC_EVENTS); + +typedef enum { + ARDUINO_HW_CDC_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_HW_CDC_CONNECTED_EVENT = 0, + ARDUINO_HW_CDC_BUS_RESET_EVENT, + ARDUINO_HW_CDC_RX_EVENT, + ARDUINO_HW_CDC_TX_EVENT, + ARDUINO_HW_CDC_MAX_EVENT, +} arduino_hw_cdc_event_t; + +typedef union { + struct { + size_t len; + } rx; + struct { + size_t len; + } tx; +} arduino_hw_cdc_event_data_t; + +class HWCDC : public Stream { +private: + static bool deinit(void *busptr); + static bool isCDC_Connected(); + +public: + HWCDC(); + ~HWCDC(); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_hw_cdc_event_t event, esp_event_handler_t callback); + + size_t setRxBufferSize(size_t); + size_t setTxBufferSize(size_t); + void setTxTimeoutMs(uint32_t timeout); + void begin(unsigned long baud = 0); + void end(); + + int available(void); + int availableForWrite(void); + int peek(void); + int read(void); + size_t read(uint8_t *buffer, size_t size); + size_t write(uint8_t); + size_t write(const uint8_t *buffer, size_t size); + void flush(void); + + inline static bool isPlugged(void) { + // SOF ISR is causing esptool to be unable to upload firmware to the board + // Using IDF 5.1 helper function because it is based on Timer check instead of ISR + return usb_serial_jtag_is_connected(); + } + + inline static bool isConnected(void) { + return isCDC_Connected(); + } + + inline size_t read(char *buffer, size_t size) { + return read((uint8_t *)buffer, size); + } + inline size_t write(const char *buffer, size_t size) { + return write((uint8_t *)buffer, size); + } + inline size_t write(const char *s) { + return write((uint8_t *)s, strlen(s)); + } + inline size_t write(unsigned long n) { + return write((uint8_t)n); + } + inline size_t write(long n) { + return write((uint8_t)n); + } + inline size_t write(unsigned int n) { + return write((uint8_t)n); + } + inline size_t write(int n) { + return write((uint8_t)n); + } + operator bool() const; + void setDebugOutput(bool); + uint32_t baudRate() { + return 115200; + } +}; +#if ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT // Hardware JTAG CDC selected +#ifndef HWCDC_SERIAL_IS_DEFINED +#define HWCDC_SERIAL_IS_DEFINED 1 +#endif +// HWCDCSerial is always available to be used +extern HWCDC HWCDCSerial; +#endif + +#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */ diff --git a/cores/esp32/HardwareI2C.h b/cores/esp32/HardwareI2C.h new file mode 100644 index 0000000..c44f34e --- /dev/null +++ b/cores/esp32/HardwareI2C.h @@ -0,0 +1,43 @@ +/* + Copyright (c) 2016 Arduino LLC. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#include +#include "Stream.h" +#include + +class HardwareI2C : public Stream { +public: + virtual bool begin() = 0; + virtual bool begin(uint8_t address) = 0; + virtual bool end() = 0; + + virtual bool setClock(uint32_t freq) = 0; + + virtual void beginTransmission(uint8_t address) = 0; + virtual uint8_t endTransmission(bool stopBit) = 0; + virtual uint8_t endTransmission(void) = 0; + + virtual size_t requestFrom(uint8_t address, size_t len, bool stopBit) = 0; + virtual size_t requestFrom(uint8_t address, size_t len) = 0; + + // Update base class to use std::function + virtual void onReceive(const std::function &) = 0; + virtual void onRequest(const std::function &) = 0; +}; diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp new file mode 100644 index 0000000..7d4e488 --- /dev/null +++ b/cores/esp32/HardwareSerial.cpp @@ -0,0 +1,696 @@ +#include +#include +#include +#include +#include + +#include "pins_arduino.h" +#include "io_pin_remap.h" +#include "HardwareSerial.h" +#include "soc/soc_caps.h" +#include "driver/uart.h" +#include "freertos/queue.h" + +#if (SOC_UART_LP_NUM >= 1) +#define UART_HW_FIFO_LEN(uart_num) ((uart_num < SOC_UART_HP_NUM) ? SOC_UART_FIFO_LEN : SOC_LP_UART_FIFO_LEN) +#else +#define UART_HW_FIFO_LEN(uart_num) SOC_UART_FIFO_LEN +#endif + +void serialEvent(void) __attribute__((weak)); + +#if SOC_UART_NUM > 1 +void serialEvent1(void) __attribute__((weak)); +#endif /* SOC_UART_NUM > 1 */ + +#if SOC_UART_NUM > 2 +void serialEvent2(void) __attribute__((weak)); +#endif /* SOC_UART_NUM > 2 */ + +#if SOC_UART_NUM > 3 +void serialEvent3(void) __attribute__((weak)); +#endif /* SOC_UART_NUM > 3 */ + +#if SOC_UART_NUM > 4 +void serialEvent4(void) __attribute__((weak)); +#endif /* SOC_UART_NUM > 4 */ + +#if SOC_UART_NUM > 5 +void serialEvent5(void) __attribute__((weak)); +#endif /* SOC_UART_NUM > 5 */ + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) +// There is always Seria0 for UART0 +HardwareSerial Serial0(0); +#if SOC_UART_NUM > 1 +HardwareSerial Serial1(1); +#endif +#if SOC_UART_NUM > 2 +HardwareSerial Serial2(2); +#endif +#if SOC_UART_NUM > 3 +HardwareSerial Serial3(3); +#endif +#if SOC_UART_NUM > 4 +HardwareSerial Serial4(4); +#endif +#if (SOC_UART_NUM > 5) +HardwareSerial Serial5(5); +#endif +#if HWCDC_SERIAL_IS_DEFINED == 1 // Hardware JTAG CDC Event +extern void HWCDCSerialEvent(void) __attribute__((weak)); +#endif + +// C-callable helper used by HAL when pins are detached and the high-level +// HardwareSerial instance must be finalized. +extern "C" void hal_uart_notify_pins_detached(int uart_num) { + log_d("hal_uart_notify_pins_detached: Notifying HardwareSerial for UART%d", uart_num); + switch (uart_num) { + case 0: Serial0.end(); break; +#if SOC_UART_NUM > 1 + case 1: Serial1.end(); break; +#endif +#if SOC_UART_NUM > 2 + case 2: Serial2.end(); break; +#endif +#if SOC_UART_NUM > 3 + case 3: Serial3.end(); break; +#endif +#if SOC_UART_NUM > 4 + case 4: Serial4.end(); break; +#endif +#if SOC_UART_NUM > 5 + case 5: Serial5.end(); break; +#endif + default: log_e("hal_uart_notify_pins_detached: UART%d not handled!", uart_num); break; + } +} + +#if USB_SERIAL_IS_DEFINED == 1 // Native USB CDC Event +// Used by Hardware Serial for USB CDC events +extern void USBSerialEvent(void) __attribute__((weak)); +#endif + +void serialEventRun(void) { +#if HWCDC_SERIAL_IS_DEFINED == 1 // Hardware JTAG CDC Event + if (HWCDCSerialEvent && HWCDCSerial.available()) { + HWCDCSerialEvent(); + } +#endif +#if USB_SERIAL_IS_DEFINED == 1 // Native USB CDC Event + if (USBSerialEvent && USBSerial.available()) { + USBSerialEvent(); + } +#endif + // UART0 is default serialEvent() + if (serialEvent && Serial0.available()) { + serialEvent(); + } +#if SOC_UART_NUM > 1 + if (serialEvent1 && Serial1.available()) { + serialEvent1(); + } +#endif +#if SOC_UART_NUM > 2 + if (serialEvent2 && Serial2.available()) { + serialEvent2(); + } +#endif +#if SOC_UART_NUM > 3 + if (serialEvent3 && Serial3.available()) { + serialEvent3(); + } +#endif +#if SOC_UART_NUM > 4 + if (serialEvent4 && Serial4.available()) { + serialEvent4(); + } +#endif +#if SOC_UART_NUM > 5 + if (serialEvent5 && Serial5.available()) { + serialEvent5(); + } +#endif +} +#endif + +#if !CONFIG_DISABLE_HAL_LOCKS +#define HSERIAL_MUTEX_LOCK() \ + do { \ + } while (xSemaphoreTake(_lock, portMAX_DELAY) != pdPASS) +#define HSERIAL_MUTEX_UNLOCK() xSemaphoreGive(_lock) +#else +#define HSERIAL_MUTEX_LOCK() +#define HSERIAL_MUTEX_UNLOCK() +#endif + +HardwareSerial::HardwareSerial(uint8_t uart_nr) + : _uart_nr(uart_nr), _uart(NULL), _rxBufferSize(256), _txBufferSize(0), _onReceiveCB(NULL), _onReceiveErrorCB(NULL), _onReceiveTimeout(false), _rxTimeout(1), + _rxFIFOFull(0), _eventTask(NULL) +#if !CONFIG_DISABLE_HAL_LOCKS + , + _lock(NULL) +#endif +{ +#if !CONFIG_DISABLE_HAL_LOCKS + if (_lock == NULL) { + _lock = xSemaphoreCreateMutex(); + if (_lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return; + } + } +#endif +} + +HardwareSerial::~HardwareSerial() { + end(); // explicit Full UART termination +#if !CONFIG_DISABLE_HAL_LOCKS + if (_lock != NULL) { + vSemaphoreDelete(_lock); + } +#endif +} + +void HardwareSerial::_createEventTask(void *args) { + // Creating UART event Task + xTaskCreateUniversal( + _uartEventTask, "uart_event_task", ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE, this, ARDUINO_SERIAL_EVENT_TASK_PRIORITY, &_eventTask, + ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE + ); + if (_eventTask == NULL) { + log_e(" -- UART%d Event Task not Created!", _uart_nr); + } +} + +void HardwareSerial::_destroyEventTask(void) { + if (_eventTask != NULL) { + vTaskDelete(_eventTask); + _eventTask = NULL; + } +} + +void HardwareSerial::onReceiveError(OnReceiveErrorCb function) { + HSERIAL_MUTEX_LOCK(); + // function may be NULL to cancel onReceive() from its respective task + _onReceiveErrorCB = function; + // this can be called after Serial.begin(), therefore it shall create the event task + if (function != NULL && _uart != NULL && _eventTask == NULL) { + _createEventTask(this); + } + HSERIAL_MUTEX_UNLOCK(); +} + +void HardwareSerial::onReceive(OnReceiveCb function, bool onlyOnTimeout) { + HSERIAL_MUTEX_LOCK(); + // function may be NULL to cancel onReceive() from its respective task + _onReceiveCB = function; + + // setting the callback to NULL will just disable it + if (_onReceiveCB != NULL) { + // When Rx timeout is Zero (disabled), there is only one possible option that is callback when FIFO reaches 120 bytes + _onReceiveTimeout = _rxTimeout > 0 ? onlyOnTimeout : false; + + // in case that onReceive() shall work only with RX Timeout, FIFO shall be high + // this is a work around for an IDF issue with events and low FIFO Full value (< 3) + // Not valid for the LP UART + if (_onReceiveTimeout && _uart_nr < SOC_UART_HP_NUM) { + uartSetRxFIFOFull(_uart, 120); + log_w("OnReceive is set to Timeout only, thus FIFO Full is now 120 bytes."); + } + + // this method can be called after Serial.begin(), therefore it shall create the event task + if (_uart != NULL && _eventTask == NULL) { + _createEventTask(this); // Create event task + } + } + HSERIAL_MUTEX_UNLOCK(); +} + +// This function allow the user to define how many bytes will trigger an Interrupt that will copy RX FIFO to the internal RX Ringbuffer +// ISR will also move data from FIFO to RX Ringbuffer after a RX Timeout defined in HardwareSerial::setRxTimeout(uint8_t symbols_timeout) +// A low value of FIFO Full bytes will consume more CPU time within the ISR +// A high value of FIFO Full bytes will make the application wait longer to have byte available for the Stkech in a streaming scenario +// Both RX FIFO Full and RX Timeout may affect when onReceive() will be called +bool HardwareSerial::setRxFIFOFull(uint8_t fifoBytes) { + HSERIAL_MUTEX_LOCK(); + // in case that onReceive() shall work only with RX Timeout, FIFO shall be high + // this is a work around for an IDF issue with events and low FIFO Full value (< 3) + // Not valid for the LP UART + if (_onReceiveCB != NULL && _onReceiveTimeout && _uart_nr < SOC_UART_HP_NUM) { + fifoBytes = 120; + log_w("OnReceive is set to Timeout only, thus FIFO Full is now 120 bytes."); + } + bool retCode = uartSetRxFIFOFull(_uart, fifoBytes); // Set new timeout + if (fifoBytes > 0 && fifoBytes < UART_HW_FIFO_LEN(_uart_nr) - 1) { + _rxFIFOFull = fifoBytes; + } + HSERIAL_MUTEX_UNLOCK(); + return retCode; +} + +// timeout is calculates in time to receive UART symbols at the UART baudrate. +// the estimation is about 11 bits per symbol (SERIAL_8N1) +bool HardwareSerial::setRxTimeout(uint8_t symbols_timeout) { + HSERIAL_MUTEX_LOCK(); + + // Zero disables timeout, thus, onReceive callback will only be called when RX FIFO reaches 120 bytes + // Any non-zero value will activate onReceive callback based on UART baudrate with about 11 bits per symbol + _rxTimeout = symbols_timeout; + if (!symbols_timeout) { + _onReceiveTimeout = false; // only when RX timeout is disabled, we also must disable this flag + } + + bool retCode = uartSetRxTimeout(_uart, _rxTimeout); // Set new timeout + + HSERIAL_MUTEX_UNLOCK(); + return retCode; +} + +void HardwareSerial::eventQueueReset() { + QueueHandle_t uartEventQueue = NULL; + if (_uart == NULL) { + return; + } + uartGetEventQueue(_uart, &uartEventQueue); + if (uartEventQueue != NULL) { + xQueueReset(uartEventQueue); + } +} + +void HardwareSerial::_uartEventTask(void *args) { + HardwareSerial *uart = (HardwareSerial *)args; + uart_event_t event; + QueueHandle_t uartEventQueue = NULL; + uartGetEventQueue(uart->_uart, &uartEventQueue); + if (uartEventQueue != NULL) { + for (;;) { + //Waiting for UART event. + if (xQueueReceive(uartEventQueue, (void *)&event, (TickType_t)portMAX_DELAY)) { + hardwareSerial_error_t currentErr = UART_NO_ERROR; + switch (event.type) { + case UART_DATA: + if (uart->_onReceiveCB && uart->available() > 0 && ((uart->_onReceiveTimeout && event.timeout_flag) || !uart->_onReceiveTimeout)) { + uart->_onReceiveCB(); + } + break; + case UART_FIFO_OVF: + log_w("UART%d FIFO Overflow. Consider adding Hardware Flow Control to your Application.", uart->_uart_nr); + currentErr = UART_FIFO_OVF_ERROR; + break; + case UART_BUFFER_FULL: + log_w("UART%d Buffer Full. Consider increasing your buffer size of your Application.", uart->_uart_nr); + currentErr = UART_BUFFER_FULL_ERROR; + break; + case UART_BREAK: + log_v("UART%d RX break.", uart->_uart_nr); + currentErr = UART_BREAK_ERROR; + break; + case UART_PARITY_ERR: + log_v("UART%d parity error.", uart->_uart_nr); + currentErr = UART_PARITY_ERROR; + break; + case UART_FRAME_ERR: + log_v("UART%d frame error.", uart->_uart_nr); + currentErr = UART_FRAME_ERROR; + break; + default: log_v("UART%d unknown event type %d.", uart->_uart_nr, event.type); break; + } + if (currentErr != UART_NO_ERROR) { + if (uart->_onReceiveErrorCB) { + uart->_onReceiveErrorCB(currentErr); + } + } + } + } + } + vTaskDelete(NULL); +} + +void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms, uint8_t rxfifo_full_thrhd) { + if (_uart_nr >= SOC_UART_NUM) { + log_e("Serial number is invalid, please use a number from 0 to %u", SOC_UART_NUM - 1); + return; + } + +#if !CONFIG_DISABLE_HAL_LOCKS + if (_lock == NULL) { + log_e("MUTEX Lock failed. Can't begin."); + return; + } +#endif + + // map logical pins to GPIO numbers + rxPin = digitalPinToGPIONumber(rxPin); + txPin = digitalPinToGPIONumber(txPin); + int8_t _rxPin = uart_get_RxPin(_uart_nr); + int8_t _txPin = uart_get_TxPin(_uart_nr); + + rxPin = rxPin < 0 ? _rxPin : rxPin; + txPin = txPin < 0 ? _txPin : txPin; + + HSERIAL_MUTEX_LOCK(); + // First Time or after end() --> set default Pins + if (!uartIsDriverInstalled(_uart)) { + // get previously used RX/TX pins, if any. + int8_t _rxPin = uart_get_RxPin(_uart_nr); + int8_t _txPin = uart_get_TxPin(_uart_nr); + switch (_uart_nr) { + case UART_NUM_0: + if (rxPin < 0 && txPin < 0) { + // do not change RX0/TX0 if it has already been set before + rxPin = _rxPin < 0 ? (int8_t)SOC_RX0 : _rxPin; + txPin = _txPin < 0 ? (int8_t)SOC_TX0 : _txPin; + } + break; +#if SOC_UART_HP_NUM > 1 + case UART_NUM_1: + if (rxPin < 0 && txPin < 0) { + // do not change RX1/TX1 if it has already been set before + rxPin = _rxPin < 0 ? (int8_t)RX1 : _rxPin; + txPin = _txPin < 0 ? (int8_t)TX1 : _txPin; + } + break; +#endif // UART_NUM_1 +#if SOC_UART_HP_NUM > 2 + case UART_NUM_2: + if (rxPin < 0 && txPin < 0) { + // do not change RX2/TX2 if it has already been set before +#ifdef RX2 + rxPin = _rxPin < 0 ? (int8_t)RX2 : _rxPin; +#endif +#ifdef TX2 + txPin = _txPin < 0 ? (int8_t)TX2 : _txPin; +#endif + } + break; +#endif // UART_NUM_2 +#if SOC_UART_HP_NUM > 3 + case UART_NUM_3: + if (rxPin < 0 && txPin < 0) { + // do not change RX3/TX3 if it has already been set before +#ifdef RX3 + rxPin = _rxPin < 0 ? (int8_t)RX3 : _rxPin; +#endif +#ifdef TX3 + txPin = _txPin < 0 ? (int8_t)TX3 : _txPin; +#endif + } + break; +#endif // UART_NUM_3 +#if SOC_UART_HP_NUM > 4 + case UART_NUM_4: + if (rxPin < 0 && txPin < 0) { + // do not change RX4/TX4 if it has already been set before +#ifdef RX4 + rxPin = _rxPin < 0 ? (int8_t)RX4 : _rxPin; +#endif +#ifdef TX4 + txPin = _txPin < 0 ? (int8_t)TX4 : _txPin; +#endif + } + break; +#endif // UART_NUM_4 +#if (SOC_UART_LP_NUM >= 1) + case LP_UART_NUM_0: + if (rxPin < 0 && txPin < 0) { + // do not change RX0_LP/TX0_LP if it has already been set before +#ifdef LP_RX0 + rxPin = _rxPin < 0 ? (int8_t)LP_RX0 : _rxPin; +#endif +#ifdef LP_TX0 + txPin = _txPin < 0 ? (int8_t)LP_TX0 : _txPin; +#endif + } + break; +#endif // LP_UART_NUM_0 + } + } + + // if no RX/TX pins are defined, it will not start the UART driver + if (rxPin < 0 && txPin < 0) { + log_e("No RX/TX pins defined. Please set RX/TX pins."); + HSERIAL_MUTEX_UNLOCK(); + return; + } + + // IDF UART driver keeps Pin setting on restarting. Negative Pin number will keep it unmodified. + // it will detach previous UART attached pins + + // indicates that uartbegin() has to initialize a new IDF driver + if (_testUartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd)) { + _destroyEventTask(); // when IDF uart driver must be restarted, _eventTask must finish too + } + + // IDF UART driver keeps Pin setting on restarting. Negative Pin number will keep it unmodified. + // it will detach previous UART attached pins + _uart = uartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd); + if (_uart == NULL) { + log_e("UART driver failed to start. Please check the logs."); + HSERIAL_MUTEX_UNLOCK(); + return; + } + if (!baud) { + // using baud rate as zero, forces it to try to detect the current baud rate in place + uartStartDetectBaudrate(_uart); + time_t startMillis = millis(); + unsigned long detectedBaudRate = 0; + while (millis() - startMillis < timeout_ms && !(detectedBaudRate = uartDetectBaudrate(_uart))) { + yield(); + } + + if (detectedBaudRate) { + delay(100); // Give some time... + _uart = uartBegin(_uart_nr, detectedBaudRate, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd); + if (_uart == NULL) { + log_e("UART driver failed to start. Please check the logs."); + HSERIAL_MUTEX_UNLOCK(); + return; + } + } else { + log_e("Could not detect baudrate. Serial data at the port must be present within the timeout for detection to be possible"); + _uart = NULL; + } + } + // create a task to deal with Serial Events when, for example, calling begin() twice to change the baudrate, + // or when setting the callback before calling begin() + if (_uart != NULL && (_onReceiveCB != NULL || _onReceiveErrorCB != NULL) && _eventTask == NULL) { + _createEventTask(this); + } + + // Set UART RX timeout + uartSetRxTimeout(_uart, _rxTimeout); + + // Set UART FIFO Full depending on the baud rate. + // Lower baud rates will force to emulate byte-by-byte reading + // Higher baud rates will keep IDF default of 120 bytes for FIFO FULL Interrupt + // It can also be changed by the application at any time + if (!_rxFIFOFull) { // it has not being changed before calling begin() + // set a default FIFO Full value for the IDF driver + uint8_t fifoFull = 1; + // if baud rate is higher than 57600 or onReceive() is set, it will set FIFO Full to 120 bytes, except for LP UART + if (_uart_nr < SOC_UART_HP_NUM && (baud > 57600 || (_onReceiveCB != NULL && _onReceiveTimeout))) { + fifoFull = 120; + } + uartSetRxFIFOFull(_uart, fifoFull); + _rxFIFOFull = fifoFull; + } + + HSERIAL_MUTEX_UNLOCK(); +} + +void HardwareSerial::updateBaudRate(unsigned long baud) { + uartSetBaudRate(_uart, baud); +} + +void HardwareSerial::end() { + // default Serial.end() will completely disable HardwareSerial, + // including any tasks or debug message channel (log_x()) - but not for IDF log messages! + _onReceiveCB = NULL; + _onReceiveErrorCB = NULL; + _rxFIFOFull = 0; + uartEnd(_uart_nr); // fully detach all pins and delete the UART driver + _destroyEventTask(); // when IDF uart driver is deleted, _eventTask must finish too + _uart = NULL; +} + +void HardwareSerial::setDebugOutput(bool en) { + if (_uart == 0) { + return; + } +#if (SOC_UART_LP_NUM >= 1) + if (_uart_nr >= SOC_UART_HP_NUM) { + log_e("LP UART does not support Debug Output."); + return; + } +#endif + if (en) { + uartSetDebug(_uart); + } else { + if (uartGetDebug() == _uart_nr) { + uartSetDebug(NULL); + } + } +} + +int HardwareSerial::available(void) { + return uartAvailable(_uart); +} +int HardwareSerial::availableForWrite(void) { + return uartAvailableForWrite(_uart); +} + +int HardwareSerial::peek(void) { + if (available()) { + return uartPeek(_uart); + } + return -1; +} + +int HardwareSerial::read(void) { + uint8_t c = 0; + if (uartReadBytes(_uart, &c, 1, 0) == 1) { + return c; + } else { + return -1; + } +} + +// read characters into buffer +// terminates if size characters have been read, or no further are pending +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +size_t HardwareSerial::read(uint8_t *buffer, size_t size) { + return uartReadBytes(_uart, buffer, size, 0); +} + +// Overrides Stream::readBytes() to be faster using IDF +size_t HardwareSerial::readBytes(uint8_t *buffer, size_t length) { + return uartReadBytes(_uart, buffer, length, (uint32_t)getTimeout()); +} + +void HardwareSerial::flush(void) { + uartFlush(_uart); +} + +void HardwareSerial::flush(bool txOnly) { + uartFlushTxOnly(_uart, txOnly); +} + +size_t HardwareSerial::write(uint8_t c) { + uartWrite(_uart, c); + return 1; +} + +size_t HardwareSerial::write(const uint8_t *buffer, size_t size) { + uartWriteBuf(_uart, buffer, size); + return size; +} + +uint32_t HardwareSerial::baudRate() { + return uartGetBaudRate(_uart); +} +HardwareSerial::operator bool() const { + return uartIsDriverInstalled(_uart); +} + +bool HardwareSerial::setRxInvert(bool invert) { + return uartSetRxInvert(_uart, invert); +} + +bool HardwareSerial::setTxInvert(bool invert) { + return uartSetTxInvert(_uart, invert); +} + +bool HardwareSerial::setCtsInvert(bool invert) { + return uartSetCtsInvert(_uart, invert); +} + +bool HardwareSerial::setRtsInvert(bool invert) { + return uartSetRtsInvert(_uart, invert); +} + +// negative Pin value will keep it unmodified +// can be called after or before begin() +bool HardwareSerial::setPins(int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) { + // map logical pins to GPIO numbers + rxPin = digitalPinToGPIONumber(rxPin); + txPin = digitalPinToGPIONumber(txPin); + ctsPin = digitalPinToGPIONumber(ctsPin); + rtsPin = digitalPinToGPIONumber(rtsPin); + + // uartSetPins() checks if pins are valid and, if necessary, detaches the previous ones + return uartSetPins(_uart_nr, rxPin, txPin, ctsPin, rtsPin); +} + +// Enables or disables Hardware Flow Control using RTS and/or CTS pins +// must use setAllPins() in order to set RTS/CTS pins +// SerialHwFlowCtrl = UART_HW_FLOWCTRL_DISABLE, UART_HW_FLOWCTRL_RTS, +// UART_HW_FLOWCTRL_CTS, UART_HW_FLOWCTRL_CTS_RTS +bool HardwareSerial::setHwFlowCtrlMode(SerialHwFlowCtrl mode, uint8_t threshold) { + return uartSetHwFlowCtrlMode(_uart, mode, threshold); +} + +// Sets the uart mode in the esp32 uart for use with RS485 modes +// HwFlowCtrl must be disabled and RTS pin set +// SerialMode = UART_MODE_UART, UART_MODE_RS485_HALF_DUPLEX, UART_MODE_IRDA, +// or testing mode: UART_MODE_RS485_COLLISION_DETECT, UART_MODE_RS485_APP_CTRL +bool HardwareSerial::setMode(SerialMode mode) { + return uartSetMode(_uart, mode); +} + +// Sets the UART Clock Source based on the compatible SoC options +// This method must be called before starting UART using begin(), otherwise it won't have any effect. +// Clock Source Options are: +// UART_CLK_SRC_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source +// UART_CLK_SRC_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3 +// UART_CLK_SRC_PLL :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4 +// UART_CLK_SRC_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 +// UART_CLK_SRC_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 +// UART_CLK_SRC_REF_TICK :: ESP32 and ESP32-S2 +// Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz +// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source +bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) { + if (_uart) { + log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr); + return false; + } + return uartSetClockSource(_uart_nr, (uart_sclk_t)clkSrc); +} +// minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition. +// LP UART has FIFO of 16 bytes +size_t HardwareSerial::setRxBufferSize(size_t new_size) { + + if (_uart) { + log_e("RX Buffer can't be resized when Serial is already running. Set it before calling begin()."); + return 0; + } + uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr); + // Valid value is higher than the FIFO length + if (new_size <= FIFOLen) { + new_size = FIFOLen + 1; + log_w("RX Buffer set to minimum value: %d.", new_size); + } + + _rxBufferSize = new_size; + return _rxBufferSize; +} + +// minimum total TX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. +// LP UART has FIFO of 16 bytes +size_t HardwareSerial::setTxBufferSize(size_t new_size) { + + if (_uart) { + log_e("TX Buffer can't be resized when Serial is already running. Set it before calling begin()."); + return 0; + } + uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr); + // Valid values are zero or higher than the FIFO length + if (new_size > 0 && new_size <= FIFOLen) { + new_size = FIFOLen + 1; + log_w("TX Buffer set to minimum value: %d.", new_size); + } + // if new_size is higher than SOC_UART_FIFO_LEN, TX Ringbuffer will be active and it will be used to report back "availableToWrite()" + _txBufferSize = new_size; + return new_size; +} diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h new file mode 100644 index 0000000..7f843fe --- /dev/null +++ b/cores/esp32/HardwareSerial.h @@ -0,0 +1,460 @@ +/* + HardwareSerial.h - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 28 September 2010 by Mark Sproul + Modified 14 August 2012 by Alarus + Modified 3 December 2013 by Matthijs Kooijman + Modified 18 December 2014 by Ivan Grokhotkov (esp8266 platform support) + Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266) + Modified 25 April 2015 by Thomas Flayols (add configuration different from 8N1 in ESP8266) + Modified 13 October 2018 by Jeroen Döll (add baudrate detection) + Baudrate detection example usage (detection on Serial1): + void setup() { + Serial.begin(115200); + delay(100); + Serial.println(); + + Serial1.begin(0, SERIAL_8N1, -1, -1, true, 11000UL); // Passing 0 for baudrate to detect it, the last parameter is a timeout in ms + + unsigned long detectedBaudRate = Serial1.baudRate(); + if(detectedBaudRate) { + Serial.printf("Detected baudrate is %lu\n", detectedBaudRate); + } else { + Serial.println("No baudrate detected, Serial1 will not work!"); + } + } + + Pay attention: the baudrate returned by baudRate() may be rounded, eg 115200 returns 115201 + */ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include +#include +#include "Stream.h" +#include "esp32-hal.h" +#include "soc/soc_caps.h" +#include "HWCDC.h" +#include "USBCDC.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" + +enum SerialConfig { + SERIAL_5N1 = 0x8000010, + SERIAL_6N1 = 0x8000014, + SERIAL_7N1 = 0x8000018, + SERIAL_8N1 = 0x800001c, + SERIAL_5N2 = 0x8000030, + SERIAL_6N2 = 0x8000034, + SERIAL_7N2 = 0x8000038, + SERIAL_8N2 = 0x800003c, + SERIAL_5E1 = 0x8000012, + SERIAL_6E1 = 0x8000016, + SERIAL_7E1 = 0x800001a, + SERIAL_8E1 = 0x800001e, + SERIAL_5E2 = 0x8000032, + SERIAL_6E2 = 0x8000036, + SERIAL_7E2 = 0x800003a, + SERIAL_8E2 = 0x800003e, + SERIAL_5O1 = 0x8000013, + SERIAL_6O1 = 0x8000017, + SERIAL_7O1 = 0x800001b, + SERIAL_8O1 = 0x800001f, + SERIAL_5O2 = 0x8000033, + SERIAL_6O2 = 0x8000037, + SERIAL_7O2 = 0x800003b, + SERIAL_8O2 = 0x800003f +}; + +typedef uart_mode_t SerialMode; +typedef uart_hw_flowcontrol_t SerialHwFlowCtrl; + +typedef enum { + UART_NO_ERROR, + UART_BREAK_ERROR, + UART_BUFFER_FULL_ERROR, + UART_FIFO_OVF_ERROR, + UART_FRAME_ERROR, + UART_PARITY_ERROR +} hardwareSerial_error_t; + +typedef enum { + UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT, +#if SOC_UART_SUPPORT_APB_CLK + UART_CLK_SRC_APB = UART_SCLK_APB, +#endif +#if SOC_UART_SUPPORT_PLL_F40M_CLK + UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M, +#elif SOC_UART_SUPPORT_PLL_F80M_CLK + UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M, +#elif CONFIG_IDF_TARGET_ESP32H2 + UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M, +#endif +#if SOC_UART_SUPPORT_XTAL_CLK + UART_CLK_SRC_XTAL = UART_SCLK_XTAL, +#endif +#if SOC_UART_SUPPORT_RTC_CLK + UART_CLK_SRC_RTC = UART_SCLK_RTC, +#endif +#if SOC_UART_SUPPORT_REF_TICK + UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK, +#endif +} SerialClkSrc; + +#ifndef ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE +#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE +#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE 2048 +#else +#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE +#endif +#endif + +#ifndef ARDUINO_SERIAL_EVENT_TASK_PRIORITY +#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_PRIORITY +#define ARDUINO_SERIAL_EVENT_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#else +#define ARDUINO_SERIAL_EVENT_TASK_PRIORITY CONFIG_ARDUINO_SERIAL_EVENT_TASK_PRIORITY +#endif +#endif + +#ifndef ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE +#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE +#define ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE -1 +#else +#define ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE CONFIG_ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE +#endif +#endif + +// UART0 pins are defined by default by the bootloader. +// The definitions for SOC_* should not be changed unless the bootloader pins +// have changed and you know what you are doing. + +#ifndef SOC_RX0 +#if CONFIG_IDF_TARGET_ESP32 +#define SOC_RX0 (gpio_num_t)3 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#define SOC_RX0 (gpio_num_t)44 +#elif CONFIG_IDF_TARGET_ESP32C2 +#define SOC_RX0 (gpio_num_t)19 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define SOC_RX0 (gpio_num_t)20 +#elif CONFIG_IDF_TARGET_ESP32C6 +#define SOC_RX0 (gpio_num_t)17 +#elif CONFIG_IDF_TARGET_ESP32H2 +#define SOC_RX0 (gpio_num_t)23 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define SOC_RX0 (gpio_num_t)38 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define SOC_RX0 (gpio_num_t)12 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define SOC_RX0 (gpio_num_t)10 +#endif +#endif + +#ifndef SOC_TX0 +#if CONFIG_IDF_TARGET_ESP32 +#define SOC_TX0 (gpio_num_t)1 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#define SOC_TX0 (gpio_num_t)43 +#elif CONFIG_IDF_TARGET_ESP32C2 +#define SOC_TX0 (gpio_num_t)20 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define SOC_TX0 (gpio_num_t)21 +#elif CONFIG_IDF_TARGET_ESP32C6 +#define SOC_TX0 (gpio_num_t)16 +#elif CONFIG_IDF_TARGET_ESP32H2 +#define SOC_TX0 (gpio_num_t)24 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define SOC_TX0 (gpio_num_t)37 +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 +#define SOC_TX0 (gpio_num_t)11 +#endif +#endif + +// Default pins for UART1 are arbitrary, and defined here for convenience. + +#if SOC_UART_HP_NUM > 1 +#ifndef RX1 +#if CONFIG_IDF_TARGET_ESP32 +#define RX1 (gpio_num_t)26 +#elif CONFIG_IDF_TARGET_ESP32S2 +#define RX1 (gpio_num_t)4 +#elif CONFIG_IDF_TARGET_ESP32C2 +#define RX1 (gpio_num_t)10 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define RX1 (gpio_num_t)18 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define RX1 (gpio_num_t)15 +#elif CONFIG_IDF_TARGET_ESP32C6 +#define RX1 (gpio_num_t)4 +#elif CONFIG_IDF_TARGET_ESP32H2 +#define RX1 (gpio_num_t)0 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define RX1 (gpio_num_t)11 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define RX1 (gpio_num_t)4 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define RX1 (gpio_num_t)8 +#endif +#endif + +#ifndef TX1 +#if CONFIG_IDF_TARGET_ESP32 +#define TX1 (gpio_num_t)27 +#elif CONFIG_IDF_TARGET_ESP32S2 +#define TX1 (gpio_num_t)5 +#elif CONFIG_IDF_TARGET_ESP32C2 +#define TX1 (gpio_num_t)18 +#elif CONFIG_IDF_TARGET_ESP32C3 +#define TX1 (gpio_num_t)19 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define TX1 (gpio_num_t)16 +#elif CONFIG_IDF_TARGET_ESP32C6 +#define TX1 (gpio_num_t)5 +#elif CONFIG_IDF_TARGET_ESP32H2 +#define TX1 (gpio_num_t)1 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define TX1 (gpio_num_t)10 +#elif CONFIG_IDF_TARGET_ESP32C5 +#define TX1 (gpio_num_t)5 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define TX1 (gpio_num_t)29 +#endif +#endif +#endif /* SOC_UART_HP_NUM > 1 */ + +// Default pins for UART2 are arbitrary, and defined here for convenience. + +#if SOC_UART_HP_NUM > 2 +#ifndef RX2 +#if CONFIG_IDF_TARGET_ESP32 +#define RX2 (gpio_num_t)4 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define RX2 (gpio_num_t)19 +#endif +#endif + +#ifndef TX2 +#if CONFIG_IDF_TARGET_ESP32 +#define TX2 (gpio_num_t)25 +#elif CONFIG_IDF_TARGET_ESP32S3 +#define TX2 (gpio_num_t)20 +#endif +#endif +#endif /* SOC_UART_HP_NUM > 2 */ + +#if SOC_UART_LP_NUM >= 1 +#ifndef LP_RX0 +#define LP_RX0 (gpio_num_t) LP_U0RXD_GPIO_NUM +#endif + +#ifndef LP_TX0 +#define LP_TX0 (gpio_num_t) LP_U0TXD_GPIO_NUM +#endif +#endif /* SOC_UART_LP_NUM >= 1 */ + +typedef std::function OnReceiveCb; +typedef std::function OnReceiveErrorCb; + +class HardwareSerial : public Stream { +public: + HardwareSerial(uint8_t uart_nr); + ~HardwareSerial(); + + // setRxTimeout sets the timeout after which onReceive callback will be called (after receiving data, it waits for this time of UART rx inactivity to call the callback fnc) + // param symbols_timeout defines a timeout threshold in uart symbol periods. Setting 0 symbol timeout disables the callback call by timeout. + // Maximum timeout setting is calculacted automatically by IDF. If set above the maximum, it is ignored and an error is printed on Serial0 (check console). + // Examples: Maximum for 11 bits symbol is 92 (SERIAL_8N2, SERIAL_8E1, SERIAL_8O1, etc), Maximum for 10 bits symbol is 101 (SERIAL_8N1). + // For example symbols_timeout=1 defines a timeout equal to transmission time of one symbol (~11 bit) on current baudrate. + // For a baudrate of 9600, SERIAL_8N1 (10 bit symbol) and symbols_timeout = 3, the timeout would be 3 / (9600 / 10) = 3.125 ms + bool setRxTimeout(uint8_t symbols_timeout); + + // setRxFIFOFull(uint8_t fifoBytes) will set the number of bytes that will trigger UART_INTR_RXFIFO_FULL interrupt and fill up RxRingBuffer + // This affects some functions such as Serial::available() and Serial.read() because, in a UART flow of receiving data, Serial internal + // RxRingBuffer will be filled only after these number of bytes arrive or a RX Timeout happens. + // This parameter can be set to 1 in order to receive byte by byte, but it will also consume more CPU time as the ISR will be activates often. + bool setRxFIFOFull(uint8_t fifoBytes); + + // onReceive will setup a callback that will be called whenever an UART interruption occurs (UART_INTR_RXFIFO_FULL or UART_INTR_RXFIFO_TOUT) + // UART_INTR_RXFIFO_FULL interrupt triggers at UART_FULL_THRESH_DEFAULT bytes received (defined as 120 bytes by default in IDF) + // UART_INTR_RXFIFO_TOUT interrupt triggers at UART_TOUT_THRESH_DEFAULT symbols passed without any reception (defined as 10 symbols by default in IDF) + // onlyOnTimeout parameter will define how onReceive will behave: + // Default: true -- The callback will only be called when RX Timeout happens. + // Whole stream of bytes will be ready for being read on the callback function at once. + // This option may lead to Rx Overflow depending on the Rx Buffer Size and number of bytes received in the streaming + // false -- The callback will be called when FIFO reaches 120 bytes and also on RX Timeout. + // The stream of incommig bytes will be "split" into blocks of 120 bytes on each callback. + // This option avoid any sort of Rx Overflow, but leaves the UART packet reassembling work to the Application. + void onReceive(OnReceiveCb function, bool onlyOnTimeout = false); + + // onReceive will be called on error events (see hardwareSerial_error_t) + void onReceiveError(OnReceiveErrorCb function); + + // eventQueueReset clears all events in the queue (the events that trigger onReceive and onReceiveError) - maybe useful in some use cases + void eventQueueReset(); + + // When pins are changed, it will detach the previous ones + // if pin is negative, it won't be set/changed and will be kept as is + // timeout_ms is used in baudrate detection (ESP32, ESP32S2 only) + // invert will invert RX/TX polarity + // rxfifo_full_thrhd if the UART Flow Control Threshold in the UART FIFO (max 127) + void begin( + unsigned long baud, uint32_t config = SERIAL_8N1, int8_t rxPin = -1, int8_t txPin = -1, bool invert = false, unsigned long timeout_ms = 20000UL, + uint8_t rxfifo_full_thrhd = 120 + ); + void end(void); + void updateBaudRate(unsigned long baud); + int available(void); + int availableForWrite(void); + int peek(void); + int read(void); + size_t read(uint8_t *buffer, size_t size); + inline size_t read(char *buffer, size_t size) { + return read((uint8_t *)buffer, size); + } + // Overrides Stream::readBytes() to be faster using IDF + size_t readBytes(uint8_t *buffer, size_t length); + size_t readBytes(char *buffer, size_t length) { + return readBytes((uint8_t *)buffer, length); + } + void flush(void); + void flush(bool txOnly); + size_t write(uint8_t); + size_t write(const uint8_t *buffer, size_t size); + inline size_t write(const char *buffer, size_t size) { + return write((uint8_t *)buffer, size); + } + inline size_t write(const char *s) { + return write((uint8_t *)s, strlen(s)); + } + inline size_t write(unsigned long n) { + return write((uint8_t)n); + } + inline size_t write(long n) { + return write((uint8_t)n); + } + inline size_t write(unsigned int n) { + return write((uint8_t)n); + } + inline size_t write(int n) { + return write((uint8_t)n); + } + uint32_t baudRate(); + operator bool() const; + + void setDebugOutput(bool); + + // functions used to enable or disable UART pins signal inversion + // returns the requested operation success status + bool setRxInvert(bool); + bool setTxInvert(bool); + bool setCtsInvert(bool); + bool setRtsInvert(bool); + + // Negative Pin Number will keep it unmodified, thus this function can set individual pins + // setPins() can be called after or before begin() + // When pins are changed, it will detach the previous ones + bool setPins(int8_t rxPin, int8_t txPin, int8_t ctsPin = -1, int8_t rtsPin = -1); + // Enables or disables Hardware Flow Control using RTS and/or CTS pins (must use setAllPins() before) + // UART_HW_FLOWCTRL_DISABLE = 0x0 disable hardware flow control + // UART_HW_FLOWCTRL_RTS = 0x1 enable RX hardware flow control (rts) + // UART_HW_FLOWCTRL_CTS = 0x2 enable TX hardware flow control (cts) + // UART_HW_FLOWCTRL_CTS_RTS = 0x3 enable hardware flow control + bool setHwFlowCtrlMode(SerialHwFlowCtrl mode = UART_HW_FLOWCTRL_CTS_RTS, uint8_t threshold = 64); // 64 is half FIFO Length + // Used to set RS485 modes such as UART_MODE_RS485_HALF_DUPLEX for Auto RTS function on ESP32 + // UART_MODE_UART = 0x00 mode: regular UART mode + // UART_MODE_RS485_HALF_DUPLEX = 0x01 mode: half duplex RS485 UART mode control by RTS pin + // UART_MODE_IRDA = 0x02 mode: IRDA UART mode + // UART_MODE_RS485_COLLISION_DETECT = 0x03 mode: RS485 collision detection UART mode (used for test purposes) + // UART_MODE_RS485_APP_CTRL = 0x04 mode: application control RS485 UART mode (used for test purposes) + bool setMode(SerialMode mode); + // Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect. + // Not all clock source are available to every SoC. The compatible option are listed here: + // UART_CLK_SRC_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source + // UART_CLK_SRC_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3 + // UART_CLK_SRC_PLL :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4 + // UART_CLK_SRC_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 + // UART_CLK_SRC_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 + // UART_CLK_SRC_REF_TICK :: ESP32 and ESP32-S2 + // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz + // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source + bool setClockSource(SerialClkSrc clkSrc); + size_t setRxBufferSize(size_t new_size); + size_t setTxBufferSize(size_t new_size); + +protected: + uint8_t _uart_nr; + uart_t *_uart; + size_t _rxBufferSize; + size_t _txBufferSize; + OnReceiveCb _onReceiveCB; + OnReceiveErrorCb _onReceiveErrorCB; + // _onReceive and _rxTimeout have be consistent when timeout is disabled + bool _onReceiveTimeout; + uint8_t _rxTimeout, _rxFIFOFull; + TaskHandle_t _eventTask; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t _lock; +#endif + + void _createEventTask(void *args); + void _destroyEventTask(void); + static void _uartEventTask(void *args); +}; + +extern void serialEventRun(void) __attribute__((weak)); + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) +#ifndef ARDUINO_USB_CDC_ON_BOOT +#define ARDUINO_USB_CDC_ON_BOOT 0 +#endif +#if ARDUINO_USB_CDC_ON_BOOT //Serial used from Native_USB_CDC | HW_CDC_JTAG +#if ARDUINO_USB_MODE // Hardware CDC mode +// Arduino Serial is the HW JTAG CDC device +#define Serial HWCDCSerial +#else // !ARDUINO_USB_MODE -- Native USB Mode +// Arduino Serial is the Native USB CDC device +#define Serial USBSerial +#endif // ARDUINO_USB_MODE +#else // !ARDUINO_USB_CDC_ON_BOOT -- Serial is used from UART0 +// if not using CDC on Boot, Arduino Serial is the UART0 device +#define Serial Serial0 +#endif // ARDUINO_USB_CDC_ON_BOOT +// There is always Seria0 for UART0 +extern HardwareSerial Serial0; +#if SOC_UART_NUM > 1 +extern HardwareSerial Serial1; +#endif +#if SOC_UART_NUM > 2 +extern HardwareSerial Serial2; +#endif +#if SOC_UART_NUM > 3 +extern HardwareSerial Serial3; +#endif +#if SOC_UART_NUM > 4 +extern HardwareSerial Serial4; +#endif +#if SOC_UART_NUM > 5 +extern HardwareSerial Serial5; +#endif +#endif //!defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) + +#endif // HardwareSerial_h diff --git a/cores/esp32/HashBuilder.cpp b/cores/esp32/HashBuilder.cpp new file mode 100644 index 0000000..be3f67e --- /dev/null +++ b/cores/esp32/HashBuilder.cpp @@ -0,0 +1,38 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "HashBuilder.h" + +void HashBuilder::add(const char *data) { + add((const uint8_t *)data, strlen(data)); +} + +void HashBuilder::add(String data) { + add(data.c_str()); +} + +void HashBuilder::addHexString(const char *data) { + size_t len = strlen(data); + uint8_t *tmp = (uint8_t *)malloc(len / 2); + if (tmp == NULL) { + return; + } + hex2bytes(tmp, len / 2, data); + add(tmp, len / 2); + free(tmp); +} + +void HashBuilder::addHexString(String data) { + addHexString(data.c_str()); +} diff --git a/cores/esp32/HashBuilder.h b/cores/esp32/HashBuilder.h new file mode 100644 index 0000000..dc62404 --- /dev/null +++ b/cores/esp32/HashBuilder.h @@ -0,0 +1,63 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef HashBuilder_h +#define HashBuilder_h + +#include +#include + +#include "HEXBuilder.h" + +/* Try to prevent most compilers from optimizing out clearing of memory that + * becomes unaccessible after this function is called. This is mostly the case + * for clearing local stack variables at the end of a function. This is not + * exactly perfect, i.e., someone could come up with a compiler that figures out + * the pointer is pointing to memset and then end up optimizing the call out, so + * try go a bit further by storing the first octet (now zero) to make this even + * a bit more difficult to optimize out. Once memset_s() is available, that + * could be used here instead. */ +static void *(*const volatile memset_func)(void *, int, size_t) = memset; +static uint8_t forced_memzero_val; + +static inline void forced_memzero(void *ptr, size_t len) { + memset_func(ptr, 0, len); + if (len) { + forced_memzero_val = ((uint8_t *)ptr)[0]; + } +} + +// Base class for hash builders + +class HashBuilder : public HEXBuilder { +public: + virtual ~HashBuilder() {} + virtual void begin() = 0; + + virtual void add(const uint8_t *data, size_t len) = 0; + void add(const char *data); + void add(String data); + + void addHexString(const char *data); + void addHexString(String data); + + virtual bool addStream(Stream &stream, const size_t maxLen) = 0; + virtual void calculate() = 0; + virtual void getBytes(uint8_t *output) = 0; + virtual void getChars(char *output) = 0; + virtual String toString() = 0; + virtual size_t getHashSize() const = 0; +}; + +#endif diff --git a/cores/esp32/IPAddress.cpp b/cores/esp32/IPAddress.cpp new file mode 100644 index 0000000..299a625 --- /dev/null +++ b/cores/esp32/IPAddress.cpp @@ -0,0 +1,453 @@ +/* + IPAddress.cpp - Base class that provides IPAddress + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "IPAddress.h" +#include "Print.h" +#include "lwip/netif.h" +#include "StreamString.h" + +#ifndef CONFIG_LWIP_IPV6 +#define IP6_NO_ZONE 0 +#endif + +IPAddress::IPAddress() : IPAddress(IPv4) {} + +IPAddress::IPAddress(IPType ip_type) { + _type = ip_type; + _zone = IP6_NO_ZONE; + memset(_address.bytes, 0, sizeof(_address.bytes)); +} + +IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet) { + _type = IPv4; + _zone = IP6_NO_ZONE; + memset(_address.bytes, 0, sizeof(_address.bytes)); + _address.bytes[IPADDRESS_V4_BYTES_INDEX] = first_octet; + _address.bytes[IPADDRESS_V4_BYTES_INDEX + 1] = second_octet; + _address.bytes[IPADDRESS_V4_BYTES_INDEX + 2] = third_octet; + _address.bytes[IPADDRESS_V4_BYTES_INDEX + 3] = fourth_octet; +} + +IPAddress::IPAddress( + uint8_t o1, uint8_t o2, uint8_t o3, uint8_t o4, uint8_t o5, uint8_t o6, uint8_t o7, uint8_t o8, uint8_t o9, uint8_t o10, uint8_t o11, uint8_t o12, + uint8_t o13, uint8_t o14, uint8_t o15, uint8_t o16, uint8_t z +) { + _type = IPv6; + _address.bytes[0] = o1; + _address.bytes[1] = o2; + _address.bytes[2] = o3; + _address.bytes[3] = o4; + _address.bytes[4] = o5; + _address.bytes[5] = o6; + _address.bytes[6] = o7; + _address.bytes[7] = o8; + _address.bytes[8] = o9; + _address.bytes[9] = o10; + _address.bytes[10] = o11; + _address.bytes[11] = o12; + _address.bytes[12] = o13; + _address.bytes[13] = o14; + _address.bytes[14] = o15; + _address.bytes[15] = o16; + _zone = z; +} + +IPAddress::IPAddress(uint32_t address) { + // IPv4 only + _type = IPv4; + _zone = IP6_NO_ZONE; + memset(_address.bytes, 0, sizeof(_address.bytes)); + _address.dword[IPADDRESS_V4_DWORD_INDEX] = address; + + // NOTE on conversion/comparison and uint32_t: + // These conversions are host platform dependent. + // There is a defined integer representation of IPv4 addresses, + // based on network byte order (will be the value on big endian systems), + // e.g. http://2398766798 is the same as http://142.250.70.206, + // However on little endian systems the octets 0x83, 0xFA, 0x46, 0xCE, + // in that order, will form the integer (uint32_t) 3460758158 . +} + +IPAddress::IPAddress(const uint8_t *address) : IPAddress(IPv4, address) {} + +IPAddress::IPAddress(IPType ip_type, const uint8_t *address, uint8_t z) { + _type = ip_type; + if (ip_type == IPv4) { + memset(_address.bytes, 0, sizeof(_address.bytes)); + memcpy(&_address.bytes[IPADDRESS_V4_BYTES_INDEX], address, sizeof(uint32_t)); + _zone = 0; + } else { + memcpy(_address.bytes, address, sizeof(_address.bytes)); + _zone = z; + } +} + +IPAddress::IPAddress(const char *address) { + fromString(address); +} + +IPAddress::IPAddress(const IPAddress &address) { + *this = address; +} + +String IPAddress::toString(bool includeZone) const { + StreamString s; + printTo(s, includeZone); + return String(s); +} + +bool IPAddress::fromString(const char *address) { + if (!fromString4(address)) { + return fromString6(address); + } + return true; +} + +bool IPAddress::fromString4(const char *address) { + // TODO: add support for "a", "a.b", "a.b.c" formats + + int16_t acc = -1; // Accumulator + uint8_t dots = 0; + + memset(_address.bytes, 0, sizeof(_address.bytes)); + while (*address) { + char c = *address++; + if (c >= '0' && c <= '9') { + acc = (acc < 0) ? (c - '0') : acc * 10 + (c - '0'); + if (acc > 255) { + // Value out of [0..255] range + return false; + } + } else if (c == '.') { + if (dots == 3) { + // Too many dots (there must be 3 dots) + return false; + } + if (acc < 0) { + /* No value between dots, e.g. '1..' */ + return false; + } + _address.bytes[IPADDRESS_V4_BYTES_INDEX + dots++] = acc; + acc = -1; + } else { + // Invalid char + return false; + } + } + + if (dots != 3) { + // Too few dots (there must be 3 dots) + return false; + } + if (acc < 0) { + /* No value between dots, e.g. '1..' */ + return false; + } + _address.bytes[IPADDRESS_V4_BYTES_INDEX + 3] = acc; + _type = IPv4; + return true; +} + +bool IPAddress::fromString6(const char *address) { + uint32_t acc = 0; // Accumulator + int colons = 0, double_colons = -1; + + while (*address) { + char c = tolower(*address++); + if (isalnum(c) && c <= 'f') { + if (c >= 'a') { + c -= 'a' - '0' - 10; + } + acc = acc * 16 + (c - '0'); + if (acc > 0xffff) { + // Value out of range + return false; + } + } else if (c == ':') { + if (*address == ':') { + if (double_colons >= 0) { + // :: allowed once + return false; + } + if (*address != '\0' && *(address + 1) == ':') { + // ::: not allowed + return false; + } + // remember location + double_colons = colons + !!acc; + address++; + } else if (*address == '\0') { + // can't end with a single colon + return false; + } + if (colons == 7) { + // too many separators + return false; + } + _address.bytes[colons * 2] = acc >> 8; + _address.bytes[colons * 2 + 1] = acc & 0xff; + colons++; + acc = 0; + } else if (c == '%') { + // netif_index_to_name crashes on latest esp-idf + // _zone = netif_name_to_index(address); + // in the interim, we parse the suffix as a zone number + while ((*address != '\0') && (!isdigit(*address))) { // skip all non-digit after '%' + address++; + } + _zone = atol(address) + 1; // increase by one by convention, so we can have zone '0' + while (*address != '\0') { + address++; + } + } else { + // Invalid char + return false; + } + } + + if (double_colons == -1 && colons != 7) { + // Too few separators + return false; + } + if (double_colons > -1 && colons > 6) { + // Too many segments (double colon must be at least one zero field) + return false; + } + _address.bytes[colons * 2] = acc >> 8; + _address.bytes[colons * 2 + 1] = acc & 0xff; + colons++; + + if (double_colons != -1) { + for (int i = colons * 2 - double_colons * 2 - 1; i >= 0; i--) { + _address.bytes[16 - colons * 2 + double_colons * 2 + i] = _address.bytes[double_colons * 2 + i]; + } + for (int i = double_colons * 2; i < 16 - colons * 2 + double_colons * 2; i++) { + _address.bytes[i] = 0; + } + } + + _type = IPv6; + return true; +} + +IPAddress &IPAddress::operator=(const uint8_t *address) { + // IPv4 only conversion from byte pointer + _type = IPv4; + memset(_address.bytes, 0, sizeof(_address.bytes)); + memcpy(&_address.bytes[IPADDRESS_V4_BYTES_INDEX], address, sizeof(uint32_t)); + return *this; +} + +IPAddress &IPAddress::operator=(const char *address) { + fromString(address); + return *this; +} + +IPAddress &IPAddress::operator=(uint32_t address) { + // IPv4 conversion + // See note on conversion/comparison and uint32_t + _type = IPv4; + memset(_address.bytes, 0, sizeof(_address.bytes)); + _address.dword[IPADDRESS_V4_DWORD_INDEX] = address; + return *this; +} + +IPAddress &IPAddress::operator=(const IPAddress &address) { + _type = address.type(); + _zone = address.zone(); + memcpy(_address.bytes, address._address.bytes, sizeof(_address.bytes)); + return *this; +} + +bool IPAddress::operator==(const IPAddress &addr) const { + return (addr._type == _type) && (_type == IPType::IPv4 ? addr._address.dword[IPADDRESS_V4_DWORD_INDEX] == _address.dword[IPADDRESS_V4_DWORD_INDEX] : memcmp(addr._address.bytes, _address.bytes, sizeof(_address.bytes)) == 0); +} + +bool IPAddress::operator==(const uint8_t *addr) const { + // IPv4 only comparison to byte pointer + // Can't support IPv6 as we know our type, but not the length of the pointer + return _type == IPv4 && memcmp(addr, &_address.bytes[IPADDRESS_V4_BYTES_INDEX], sizeof(uint32_t)) == 0; +} + +uint8_t IPAddress::operator[](int index) const { + if (_type == IPv4) { + return _address.bytes[IPADDRESS_V4_BYTES_INDEX + index]; + } + return _address.bytes[index]; +} + +uint8_t &IPAddress::operator[](int index) { + if (_type == IPv4) { + return _address.bytes[IPADDRESS_V4_BYTES_INDEX + index]; + } + return _address.bytes[index]; +} + +size_t IPAddress::printTo(Print &p) const { + return printTo(p, false); +} + +size_t IPAddress::printTo(Print &p, bool includeZone) const { + size_t n = 0; + + if (_type == IPv6) { + // IPv6 IETF canonical format: compress left-most longest run of two or more zero fields, lower case + int8_t longest_start = -1; + int8_t longest_length = 1; + int8_t current_start = -1; + int8_t current_length = 0; + for (int8_t f = 0; f < 8; f++) { + if (_address.bytes[f * 2] == 0 && _address.bytes[f * 2 + 1] == 0) { + if (current_start == -1) { + current_start = f; + current_length = 1; + } else { + current_length++; + } + if (current_length > longest_length) { + longest_start = current_start; + longest_length = current_length; + } + } else { + current_start = -1; + } + } + for (int f = 0; f < 8; f++) { + if (f < longest_start || f >= longest_start + longest_length) { + uint8_t c1 = _address.bytes[f * 2] >> 4; + uint8_t c2 = _address.bytes[f * 2] & 0xf; + uint8_t c3 = _address.bytes[f * 2 + 1] >> 4; + uint8_t c4 = _address.bytes[f * 2 + 1] & 0xf; + if (c1 > 0) { + n += p.print((char)(c1 < 10 ? '0' + c1 : 'a' + c1 - 10)); + } + if (c1 > 0 || c2 > 0) { + n += p.print((char)(c2 < 10 ? '0' + c2 : 'a' + c2 - 10)); + } + if (c1 > 0 || c2 > 0 || c3 > 0) { + n += p.print((char)(c3 < 10 ? '0' + c3 : 'a' + c3 - 10)); + } + n += p.print((char)(c4 < 10 ? '0' + c4 : 'a' + c4 - 10)); + if (f < 7) { + n += p.print(':'); + } + } else if (f == longest_start) { + if (longest_start == 0) { + n += p.print(':'); + } + n += p.print(':'); + } + } + // add a zone if zone-id is non-zero (causes exception on recent IDF builds) + // if (_zone > 0 && includeZone) { + // n += p.print('%'); + // char if_name[NETIF_NAMESIZE]; + // netif_index_to_name(_zone, if_name); + // n += p.print(if_name); + // } + // In the interim, we just output the index number + if (_zone > 0 && includeZone) { + n += p.print('%'); + // look for the interface name + for (netif *intf = netif_list; intf != nullptr; intf = intf->next) { + if (_zone - 1 == intf->num) { + n += p.print(intf->name[0]); + n += p.print(intf->name[1]); + break; + } + } + n += p.print(_zone - 1); + } + return n; + } + + // IPv4 + for (int i = 0; i < 3; i++) { + n += p.print(_address.bytes[IPADDRESS_V4_BYTES_INDEX + i], DEC); + n += p.print('.'); + } + n += p.print(_address.bytes[IPADDRESS_V4_BYTES_INDEX + 3], DEC); + return n; +} + +IPAddress::IPAddress(const ip_addr_t *addr) { + from_ip_addr_t(addr); +} + +void IPAddress::to_ip_addr_t(ip_addr_t *addr) const { +#if CONFIG_LWIP_IPV6 + if (_type == IPv6) { + addr->type = IPADDR_TYPE_V6; + addr->u_addr.ip6.addr[0] = _address.dword[0]; + addr->u_addr.ip6.addr[1] = _address.dword[1]; + addr->u_addr.ip6.addr[2] = _address.dword[2]; + addr->u_addr.ip6.addr[3] = _address.dword[3]; +#if LWIP_IPV6_SCOPES + addr->u_addr.ip6.zone = _zone; +#endif /* LWIP_IPV6_SCOPES */ + } else { + addr->type = IPADDR_TYPE_V4; + addr->u_addr.ip4.addr = _address.dword[IPADDRESS_V4_DWORD_INDEX]; + } +#else + addr->addr = _address.dword[IPADDRESS_V4_DWORD_INDEX]; +#endif +} + +IPAddress &IPAddress::from_ip_addr_t(const ip_addr_t *addr) { +#if CONFIG_LWIP_IPV6 + if (addr->type == IPADDR_TYPE_V6) { + _type = IPv6; + _address.dword[0] = addr->u_addr.ip6.addr[0]; + _address.dword[1] = addr->u_addr.ip6.addr[1]; + _address.dword[2] = addr->u_addr.ip6.addr[2]; + _address.dword[3] = addr->u_addr.ip6.addr[3]; +#if LWIP_IPV6_SCOPES + _zone = addr->u_addr.ip6.zone; +#endif /* LWIP_IPV6_SCOPES */ + } else { +#endif + _type = IPv4; + memset(_address.bytes, 0, sizeof(_address.bytes)); +#if CONFIG_LWIP_IPV6 + _address.dword[IPADDRESS_V4_DWORD_INDEX] = addr->u_addr.ip4.addr; +#else + _address.dword[IPADDRESS_V4_DWORD_INDEX] = addr->addr; +#endif +#if CONFIG_LWIP_IPV6 + } +#endif + return *this; +} + +#if CONFIG_LWIP_IPV6 +esp_ip6_addr_type_t IPAddress::addr_type() const { + if (_type != IPv6) { + return ESP_IP6_ADDR_IS_UNKNOWN; + } + ip_addr_t addr; + to_ip_addr_t(&addr); + return esp_netif_ip6_get_addr_type((esp_ip6_addr_t *)(&(addr.u_addr.ip6))); +} +#endif + +#if CONFIG_LWIP_IPV6 +const IPAddress IN6ADDR_ANY(IPv6); +#endif +const IPAddress INADDR_NONE(0, 0, 0, 0); diff --git a/cores/esp32/IPAddress.h b/cores/esp32/IPAddress.h new file mode 100644 index 0000000..923f4dd --- /dev/null +++ b/cores/esp32/IPAddress.h @@ -0,0 +1,140 @@ +/* + IPAddress.h - Base class that provides IPAddress + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#include +#include "Printable.h" +#include "WString.h" +#include "lwip/ip_addr.h" +#include "esp_netif_ip_addr.h" +#include "sdkconfig.h" + +#define IPADDRESS_V4_BYTES_INDEX 12 +#define IPADDRESS_V4_DWORD_INDEX 3 + +// A class to make it easier to handle and pass around IP addresses + +enum IPType { + IPv4, + IPv6 +}; + +class IPAddress : public Printable { +private: + union { + uint8_t bytes[16]; + uint32_t dword[4]; + } _address; + IPType _type; + uint8_t _zone; + + // Access the raw byte array containing the address. Because this returns a pointer + // to the internal structure rather than a copy of the address this function should only + // be used when you know that the usage of the returned uint8_t* will be transient and not + // stored. + uint8_t *raw_address() { + return _type == IPv4 ? &_address.bytes[IPADDRESS_V4_BYTES_INDEX] : _address.bytes; + } + +public: + // Constructors + + // Default IPv4 + IPAddress(); + IPAddress(IPType ip_type); + IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet); + IPAddress( + uint8_t o1, uint8_t o2, uint8_t o3, uint8_t o4, uint8_t o5, uint8_t o6, uint8_t o7, uint8_t o8, uint8_t o9, uint8_t o10, uint8_t o11, uint8_t o12, + uint8_t o13, uint8_t o14, uint8_t o15, uint8_t o16, uint8_t z = 0 + ); + // IPv4; see implementation note + IPAddress(uint32_t address); + // Default IPv4 + IPAddress(const uint8_t *address); + IPAddress(IPType ip_type, const uint8_t *address, uint8_t z = 0); + // If IPv4 fails tries IPv6 see fromString function + IPAddress(const char *address); + IPAddress(const IPAddress &address); + + bool fromString(const char *address); + bool fromString(const String &address) { + return fromString(address.c_str()); + } + + // Overloaded cast operator to allow IPAddress objects to be used where a uint32_t is expected + // NOTE: IPv4 only; see implementation note + operator uint32_t() const { + return _type == IPv4 ? _address.dword[IPADDRESS_V4_DWORD_INDEX] : 0; + }; + + bool operator==(const IPAddress &addr) const; + bool operator!=(const IPAddress &addr) const { + return !(*this == addr); + }; + + // NOTE: IPv4 only; we don't know the length of the pointer + bool operator==(const uint8_t *addr) const; + + // Overloaded index operator to allow getting and setting individual octets of the address + uint8_t operator[](int index) const; + uint8_t &operator[](int index); + + // Overloaded copy operators to allow initialization of IPAddress objects from other types + // NOTE: IPv4 only + IPAddress &operator=(const uint8_t *address); + // NOTE: IPv4 only; see implementation note + IPAddress &operator=(uint32_t address); + // If IPv4 fails tries IPv6 see fromString function + IPAddress &operator=(const char *address); + IPAddress &operator=(const IPAddress &address); + + virtual size_t printTo(Print &p) const; + String toString(bool includeZone = false) const; + + IPType type() const { + return _type; + } + + // Espresif LwIP conversions + IPAddress(const ip_addr_t *addr); + void to_ip_addr_t(ip_addr_t *addr) const; + IPAddress &from_ip_addr_t(const ip_addr_t *addr); +#if CONFIG_LWIP_IPV6 + esp_ip6_addr_type_t addr_type() const; +#endif + uint8_t zone() const { + return (type() == IPv6) ? _zone : 0; + } + size_t printTo(Print &p, bool includeZone) const; + + friend class UDP; + friend class Client; + friend class Server; + friend class EthernetClass; + friend class DhcpClass; + friend class DNSClient; + +protected: + bool fromString4(const char *address); + bool fromString6(const char *address); +}; + +extern const IPAddress IN6ADDR_ANY; +extern const IPAddress INADDR_NONE; diff --git a/cores/esp32/MD5Builder.cpp b/cores/esp32/MD5Builder.cpp new file mode 100644 index 0000000..3c57849 --- /dev/null +++ b/cores/esp32/MD5Builder.cpp @@ -0,0 +1,87 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "HEXBuilder.h" +#include "MD5Builder.h" + +void MD5Builder::begin(void) { + memset(_buf, 0x00, ESP_ROM_MD5_DIGEST_LEN); + esp_rom_md5_init(&_ctx); +} + +void MD5Builder::add(const uint8_t *data, size_t len) { + esp_rom_md5_update(&_ctx, data, len); +} + +bool MD5Builder::addStream(Stream &stream, const size_t maxLen) { + const int buf_size = 512; + int maxLengthLeft = maxLen; + uint8_t *buf = (uint8_t *)malloc(buf_size); + + if (!buf) { + return false; + } + + int bytesAvailable = stream.available(); + while ((bytesAvailable > 0) && (maxLengthLeft > 0)) { + + // determine number of bytes to read + int readBytes = bytesAvailable; + if (readBytes > maxLengthLeft) { + readBytes = maxLengthLeft; // read only until max_len + } + if (readBytes > buf_size) { + readBytes = buf_size; // not read more the buffer can handle + } + + // read data and check if we got something + int numBytesRead = stream.readBytes(buf, readBytes); + if (numBytesRead < 1) { + free(buf); + return false; + } + + // Update MD5 with buffer payload + esp_rom_md5_update(&_ctx, buf, numBytesRead); + + // update available number of bytes + maxLengthLeft -= numBytesRead; + bytesAvailable = stream.available(); + } + free(buf); + return true; +} + +void MD5Builder::calculate(void) { + esp_rom_md5_final(_buf, &_ctx); +} + +void MD5Builder::getBytes(uint8_t *output) { + memcpy(output, _buf, ESP_ROM_MD5_DIGEST_LEN); +} + +void MD5Builder::getChars(char *output) { + bytes2hex(output, ESP_ROM_MD5_DIGEST_LEN * 2 + 1, _buf, ESP_ROM_MD5_DIGEST_LEN); +} + +String MD5Builder::toString(void) { + char out[(ESP_ROM_MD5_DIGEST_LEN * 2) + 1]; + getChars(out); + return String(out); +} diff --git a/cores/esp32/MD5Builder.h b/cores/esp32/MD5Builder.h new file mode 100644 index 0000000..cbddf8f --- /dev/null +++ b/cores/esp32/MD5Builder.h @@ -0,0 +1,52 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp32 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 10 Jan 2024 by Lucas Saavedra Vaz (Use abstract class HashBuilder) +*/ +#ifndef MD5Builder_h +#define MD5Builder_h + +#include +#include + +#include "esp_system.h" +#include "esp_rom_md5.h" + +#include "HashBuilder.h" + +class MD5Builder : public HashBuilder { +private: + md5_context_t _ctx; + uint8_t _buf[ESP_ROM_MD5_DIGEST_LEN]; + +public: + using HashBuilder::add; + + void begin(void) override; + void add(const uint8_t *data, size_t len) override; + bool addStream(Stream &stream, const size_t maxLen) override; + void calculate(void) override; + void getBytes(uint8_t *output) override; + void getChars(char *output) override; + String toString(void) override; + size_t getHashSize() const override { + return ESP_ROM_MD5_DIGEST_LEN; + } +}; + +#endif diff --git a/cores/esp32/MacAddress.cpp b/cores/esp32/MacAddress.cpp new file mode 100644 index 0000000..279b251 --- /dev/null +++ b/cores/esp32/MacAddress.cpp @@ -0,0 +1,246 @@ +#include +#include +#include + +//Default constructor, blank mac address. +MacAddress::MacAddress() : MacAddress(MAC6) {} + +MacAddress::MacAddress(MACType mac_type) { + _type = mac_type; + memset(_mac.bytes, 0, sizeof(_mac.bytes)); +} +MacAddress::MacAddress(MACType mac_type, uint64_t mac) { + _type = mac_type; + _mac.val = mac; +} + +MacAddress::MacAddress(MACType mac_type, const uint8_t *macbytearray) { + _type = mac_type; + memset(_mac.bytes, 0, sizeof(_mac.bytes)); + if (_type == MAC6) { + memcpy(_mac.bytes, macbytearray, 6); + } else { + memcpy(_mac.bytes, macbytearray, 8); + } +} + +MacAddress::MacAddress(const char *macstr) { + fromString(macstr); +} + +MacAddress::MacAddress(const String &macstr) { + fromString(macstr.c_str()); +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +MacAddress::MacAddress(std::initializer_list list) { + size_t size = list.size(); + memset(_mac.bytes, 0, sizeof(_mac.bytes)); + if (size == 6) { + _type = MAC6; + } else if (size == 8) { + _type = MAC8; + } else { + // Default to MAC6 and keep the rest of the bytes as 0 + _type = MAC6; + return; + } + + memcpy(_mac.bytes, list.begin(), size); +} +#endif + +MacAddress::MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6) { + _type = MAC6; + memset(_mac.bytes, 0, sizeof(_mac.bytes)); + _mac.bytes[0] = b1; + _mac.bytes[1] = b2; + _mac.bytes[2] = b3; + _mac.bytes[3] = b4; + _mac.bytes[4] = b5; + _mac.bytes[5] = b6; +} + +MacAddress::MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6, uint8_t b7, uint8_t b8) { + _type = MAC8; + _mac.bytes[0] = b1; + _mac.bytes[1] = b2; + _mac.bytes[2] = b3; + _mac.bytes[3] = b4; + _mac.bytes[4] = b5; + _mac.bytes[5] = b6; + _mac.bytes[6] = b7; + _mac.bytes[7] = b8; +} + +//Parse user entered string into MAC address +bool MacAddress::fromString(const char *buf) { + if (strlen(buf) == 17) { + return fromString6(buf); + } else if (strlen(buf) == 23) { + return fromString8(buf); + } + return false; +} + +//Parse user entered string into MAC address +bool MacAddress::fromString6(const char *buf) { + char cs[18]; // 17 + 1 for null terminator + char *token; + char *next; //Unused but required + int i; + + strncpy(cs, buf, sizeof(cs) - 1); //strtok modifies the buffer: copy to working buffer. + + for (i = 0; i < 6; i++) { + token = strtok((i == 0) ? cs : NULL, ":"); //Find first or next token + if (!token) { //No more tokens found + return false; + } + _mac.bytes[i] = strtol(token, &next, 16); + } + _type = MAC6; + return true; +} + +bool MacAddress::fromString8(const char *buf) { + char cs[24]; // 23 + 1 for null terminator + char *token; + char *next; //Unused but required + int i; + + strncpy(cs, buf, sizeof(cs) - 1); //strtok modifies the buffer: copy to working buffer. + + for (i = 0; i < 8; i++) { + token = strtok((i == 0) ? cs : NULL, ":"); //Find first or next token + if (!token) { //No more tokens found + return false; + } + _mac.bytes[i] = strtol(token, &next, 16); + } + _type = MAC8; + return true; +} + +//Copy MAC into byte array +void MacAddress::toBytes(uint8_t *buf) { + if (_type == MAC6) { + memcpy(buf, _mac.bytes, 6); + } else { + memcpy(buf, _mac.bytes, sizeof(_mac.bytes)); + } +} + +//Print MAC address into a C string. +//MAC: Buffer must be at least 18 chars +int MacAddress::toString(char *buf) { + if (_type == MAC6) { + return sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5]); + } else { + return sprintf( + buf, "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5], _mac.bytes[6], + _mac.bytes[7] + ); + } +} + +String MacAddress::toString() const { + uint8_t bytes = (_type == MAC6) ? 18 : 24; + char buf[bytes]; + if (_type == MAC6) { + snprintf(buf, sizeof(buf), "%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5]); + } else { + snprintf( + buf, sizeof(buf), "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5], + _mac.bytes[6], _mac.bytes[7] + ); + } + return String(buf); +} + +uint64_t MacAddress::Value() { + return _mac.val; +} + +//Allow getting individual octets of the address. e.g. uint8_t b0 = ma[0]; +uint8_t MacAddress::operator[](int index) const { + index = EnforceIndexBounds(index); + return _mac.bytes[index]; +} + +//Allow setting individual octets of the address. e.g. ma[2] = 255; +uint8_t &MacAddress::operator[](int index) { + index = EnforceIndexBounds(index); + return _mac.bytes[index]; +} + +//Overloaded copy operator: init MacAddress object from byte array +MacAddress &MacAddress::operator=(const uint8_t *macbytearray) { + // 6-bytes MacAddress only + _type = MAC6; + memset(_mac.bytes, 0, sizeof(_mac.bytes)); + memcpy(_mac.bytes, macbytearray, 6); + return *this; +} + +//Overloaded copy operator: init MacAddress object from uint64_t +MacAddress &MacAddress::operator=(uint64_t macval) { + // 6-bytes MacAddress only + _type = MAC6; + _mac.val = macval; + return *this; +} + +//Compare class to byte array +bool MacAddress::operator==(const uint8_t *macbytearray) const { + return !memcmp(_mac.bytes, macbytearray, 6); +} + +//Allow comparing value of two classes +bool MacAddress::operator==(const MacAddress &mac2) const { + return _mac.val == mac2._mac.val; +} + +//Type converter object to uint64_t [same as .Value()] +MacAddress::operator uint64_t() const { + return _mac.val; +} + +//Type converter object to read only pointer to mac bytes. e.g. const uint8_t *ip_8 = ma; +MacAddress::operator const uint8_t *() const { + return _mac.bytes; +} + +//Type converter object to read only pointer to mac value. e.g. const uint32_t *ip_64 = ma; +MacAddress::operator const uint64_t *() const { + return &_mac.val; +} + +size_t MacAddress::printTo(Print &p) const { + uint8_t bytes = (_type == MAC6) ? 6 : 8; + size_t n = 0; + for (int i = 0; i < bytes; i++) { + if (i) { + n += p.print(':'); + } + n += p.printf("%02X", _mac.bytes[i]); + } + return n; +} + +//Bounds checking +int MacAddress::EnforceIndexBounds(int i) const { + if (i < 0) { + return 0; + } + if (_type == MAC6) { + if (i >= 6) { + return 5; + } + } else { + if (i >= 8) { + return 7; + } + } + return i; +} diff --git a/cores/esp32/MacAddress.h b/cores/esp32/MacAddress.h new file mode 100644 index 0000000..1fb7029 --- /dev/null +++ b/cores/esp32/MacAddress.h @@ -0,0 +1,113 @@ +//----------------------------------------------------------------------------- +// MacAddress.h - class to make it easier to handle BSSID and MAC addresses. +// +// Copyright 2022 David McCurley +// Modified by Espressif Systems 2024 +// +// Licensed under the Apache License, Version 2.0 (the "License"). +// You may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//----------------------------------------------------------------------------- + +#ifndef MacAddress_h +#define MacAddress_h + +#include +#include +#include +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +#include +#endif + +enum MACType { + MAC6, + MAC8 +}; + +// A class to make it easier to handle and pass around MAC addresses, supporting both 6-byte and 8-byte MAC addresses. +class MacAddress : public Printable { +private: + union { + uint8_t bytes[8]; + uint64_t val; + } _mac; + MACType _type; + +public: + //Default MAC6 + MacAddress(); + + MacAddress(MACType mac_type); + MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6); + MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6, uint8_t b7, uint8_t b8); + + MacAddress(MACType mac_type, uint64_t mac); + MacAddress(MACType mac_type, const uint8_t *macbytearray); + + //Default MAC6 + MacAddress(uint64_t mac) : MacAddress(MAC6, mac) {} + MacAddress(const uint8_t *macbytearray) : MacAddress(MAC6, macbytearray) {} + + MacAddress(const char *macstr); + MacAddress(const String &macstr); + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + // Initializer list constructor for {0xAA, 0xBB, ...} syntax + // This has higher priority than String conversion, preventing ambiguity + MacAddress(std::initializer_list list); +#endif + + virtual ~MacAddress() {} + + bool fromString(const char *buf); + bool fromString(const String &macstr) { + return fromString(macstr.c_str()); + } + + void toBytes(uint8_t *buf); + int toString(char *buf); + String toString() const; + uint64_t Value(); + + uint8_t operator[](int index) const; + uint8_t &operator[](int index); + + //MAC6 only + MacAddress &operator=(const uint8_t *macbytearray); + MacAddress &operator=(uint64_t macval); + + bool operator==(const uint8_t *macbytearray) const; + bool operator==(const MacAddress &mac2) const; + operator uint64_t() const; + operator const uint8_t *() const; + operator const uint64_t *() const; + + virtual size_t printTo(Print &p) const; + + // future use in Arduino Networking + /* + friend class EthernetClass; + friend class UDP; + friend class Client; + friend class Server; + friend class DhcpClass; + friend class DNSClient; + */ + +protected: + bool fromString6(const char *buf); + bool fromString8(const char *buf); + +private: + int EnforceIndexBounds(int i) const; +}; + +#endif diff --git a/cores/esp32/Print.cpp b/cores/esp32/Print.cpp new file mode 100644 index 0000000..53780d5 --- /dev/null +++ b/cores/esp32/Print.cpp @@ -0,0 +1,345 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified December 2014 by Ivan Grokhotkov + Modified May 2015 by Michael C. Miller - ESP31B progmem support + */ + +#include +#include +#include +#include +#include "Arduino.h" + +#include "Print.h" +extern "C" { +#include "time.h" +} + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +size_t Print::write(const uint8_t *buffer, size_t size) { + size_t n = 0; + while (size--) { + n += write(*buffer++); + } + return n; +} + +size_t Print::vprintf(const char *format, va_list arg) { + char loc_buf[64]; + char *temp = loc_buf; + va_list copy; + va_copy(copy, arg); + int len = vsnprintf(temp, sizeof(loc_buf), format, copy); + va_end(copy); + if (len < 0) { + va_end(arg); + return 0; + } + if (len >= (int)sizeof(loc_buf)) { // comparison of same sign type for the compiler + temp = (char *)malloc(len + 1); + if (temp == NULL) { + va_end(arg); + return 0; + } + len = vsnprintf(temp, len + 1, format, arg); + } + va_end(arg); + len = write((uint8_t *)temp, len); + if (temp != loc_buf) { + free(temp); + } + return len; +} + +size_t Print::printf(const __FlashStringHelper *ifsh, ...) { + va_list arg; + va_start(arg, ifsh); + const char *format = (reinterpret_cast(ifsh)); + size_t ret = vprintf(format, arg); + va_end(arg); + return ret; +} + +size_t Print::printf(const char *format, ...) { + va_list arg; + va_start(arg, format); + size_t ret = vprintf(format, arg); + va_end(arg); + return ret; +} + +size_t Print::print(const String &s) { + return write(s.c_str(), s.length()); +} + +size_t Print::print(const char str[]) { + return write(str); +} + +size_t Print::print(char c) { + return write(c); +} + +size_t Print::print(unsigned char b, int base) { + return print((unsigned long)b, base); +} + +size_t Print::print(int n, int base) { + return print((long)n, base); +} + +size_t Print::print(unsigned int n, int base) { + return print((unsigned long)n, base); +} + +size_t Print::print(long n, int base) { + int t = 0; + if (base == 10 && n < 0) { + t = print('-'); + n = -n; + } + return printNumber(static_cast(n), base) + t; +} + +size_t Print::print(unsigned long n, int base) { + if (base == 0) { + return write(n); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(long long n, int base) { + int t = 0; + if (base == 10 && n < 0) { + t = print('-'); + n = -n; + } + return printNumber(static_cast(n), base) + t; +} + +size_t Print::print(unsigned long long n, int base) { + if (base == 0) { + return write(n); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(double n, int digits) { + return printFloat(n, digits); +} + +size_t Print::print(const Printable &x) { + return x.printTo(*this); +} + +size_t Print::print(struct tm *timeinfo, const char *format) { + const char *f = format; + if (!f) { + f = "%c"; + } + char buf[64]; + size_t written = strftime(buf, 64, f, timeinfo); + if (written == 0) { + return written; + } + return print(buf); +} + +size_t Print::println(void) { + return print("\r\n"); +} + +size_t Print::println(const String &s) { + size_t n = print(s); + n += println(); + return n; +} + +size_t Print::println(const char c[]) { + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(char c) { + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(unsigned char b, int base) { + size_t n = print(b, base); + n += println(); + return n; +} + +size_t Print::println(int num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned int num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long long num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long long num, int base) { + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(double num, int digits) { + size_t n = print(num, digits); + n += println(); + return n; +} + +size_t Print::println(const Printable &x) { + size_t n = print(x); + n += println(); + return n; +} + +size_t Print::println(struct tm *timeinfo, const char *format) { + size_t n = print(timeinfo, format); + n += println(); + return n; +} + +// Private Methods ///////////////////////////////////////////////////////////// + +size_t Print::printNumber(unsigned long n, uint8_t base) { + char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if (base < 2) { + base = 10; + } + + do { + char c = n % base; + n /= base; + + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while (n); + + return write(str); +} + +size_t Print::printNumber(unsigned long long n, uint8_t base) { + char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if (base < 2) { + base = 10; + } + + do { + auto m = n; + n /= base; + char c = m - base * n; + + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while (n); + + return write(str); +} + +size_t Print::printFloat(double number, uint8_t digits) { + size_t n = 0; + + if (isnan(number)) { + return print("nan"); + } + if (isinf(number)) { + return print("inf"); + } + if (number > 4294967040.0) { + return print("ovf"); // constant determined empirically + } + if (number < -4294967040.0) { + return print("ovf"); // constant determined empirically + } + + // Handle negative numbers + if (number < 0.0) { + n += print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i = 0; i < digits; ++i) { + rounding /= 10.0; + } + + number += rounding; + + // Extract the integer part of the number and print it + unsigned long int_part = (unsigned long)number; + double remainder = number - (double)int_part; + n += print(int_part); + + // Print the decimal point, but only if there are digits beyond + if (digits > 0) { + n += print("."); + } + + // Extract digits from the remainder one at a time + while (digits-- > 0) { + remainder *= 10.0; + int toPrint = int(remainder); + n += print(toPrint); + remainder -= toPrint; + } + + return n; +} diff --git a/cores/esp32/Print.h b/cores/esp32/Print.h new file mode 100644 index 0000000..d02a823 --- /dev/null +++ b/cores/esp32/Print.h @@ -0,0 +1,118 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Print_h +#define Print_h + +#include +#include +#include + +#include "WString.h" +#include "Printable.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 + +class Print { +private: + int write_error; + size_t printNumber(unsigned long, uint8_t); + size_t printNumber(unsigned long long, uint8_t); + size_t printFloat(double, uint8_t); + +protected: + void setWriteError(int err = 1) { + write_error = err; + } + +public: + Print() : write_error(0) {} + virtual ~Print() {} + int getWriteError() { + return write_error; + } + void clearWriteError() { + setWriteError(0); + } + + virtual size_t write(uint8_t) = 0; + size_t write(const char *str) { + if (str == NULL) { + return 0; + } + return write((const uint8_t *)str, strlen(str)); + } + virtual size_t write(const uint8_t *buffer, size_t size); + size_t write(const char *buffer, size_t size) { + return write((const uint8_t *)buffer, size); + } + + size_t vprintf(const char *format, va_list arg); + + size_t printf(const char *format, ...) __attribute__((format(printf, 2, 3))); + size_t printf(const __FlashStringHelper *ifsh, ...); + + // add availableForWrite to make compatible with Arduino Print.h + // default to zero, meaning "a single write may block" + // should be overridden by subclasses with buffering + virtual int availableForWrite() { + return 0; + } + size_t print(const __FlashStringHelper *ifsh) { + return print(reinterpret_cast(ifsh)); + } + size_t print(const String &); + size_t print(const char[]); + size_t print(char); + size_t print(unsigned char, int = DEC); + size_t print(int, int = DEC); + size_t print(unsigned int, int = DEC); + size_t print(long, int = DEC); + size_t print(unsigned long, int = DEC); + size_t print(long long, int = DEC); + size_t print(unsigned long long, int = DEC); + size_t print(double, int = 2); + size_t print(const Printable &); + size_t print(struct tm *timeinfo, const char *format = NULL); + + size_t println(const __FlashStringHelper *ifsh) { + return println(reinterpret_cast(ifsh)); + } + size_t println(const String &s); + size_t println(const char[]); + size_t println(char); + size_t println(unsigned char, int = DEC); + size_t println(int, int = DEC); + size_t println(unsigned int, int = DEC); + size_t println(long, int = DEC); + size_t println(unsigned long, int = DEC); + size_t println(long long, int = DEC); + size_t println(unsigned long long, int = DEC); + size_t println(double, int = 2); + size_t println(const Printable &); + size_t println(struct tm *timeinfo, const char *format = NULL); + size_t println(void); + + virtual void flush() { /* Empty implementation for backward compatibility */ } +}; + +#endif diff --git a/cores/esp32/Printable.h b/cores/esp32/Printable.h new file mode 100644 index 0000000..3a8fe00 --- /dev/null +++ b/cores/esp32/Printable.h @@ -0,0 +1,39 @@ +/* + Printable.h - Interface class that allows printing of complex types + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Printable_h +#define Printable_h + +#include + +class Print; + +/** The Printable class provides a way for new classes to allow themselves to be printed. + By deriving from Printable and implementing the printTo method, it will then be possible + for users to print out instances of this class by passing them into the usual + Print::print and Print::println methods. + */ + +class Printable { +public: + virtual ~Printable() {} + virtual size_t printTo(Print &p) const = 0; +}; + +#endif diff --git a/cores/esp32/Server.h b/cores/esp32/Server.h new file mode 100644 index 0000000..f4825d3 --- /dev/null +++ b/cores/esp32/Server.h @@ -0,0 +1,30 @@ +/* + Server.h - Base class that provides Server + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef server_h +#define server_h + +#include "Print.h" + +class Server : public Print { +public: + virtual void begin() = 0; +}; + +#endif diff --git a/cores/esp32/Stream.cpp b/cores/esp32/Stream.cpp new file mode 100644 index 0000000..5c2060e --- /dev/null +++ b/cores/esp32/Stream.cpp @@ -0,0 +1,318 @@ +/* + Stream.cpp - adds parsing methods to Stream class + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Created July 2011 + parsing functions based on TextFinder library by Michael Margolis + + findMulti/findUntil routines written by Jim Leonard/Xuth + */ + +#include "Arduino.h" +#include "Stream.h" + +#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait + +// private method to read stream with timeout +int Stream::timedRead() { + int c; + _startMillis = millis(); + do { + c = read(); + if (c >= 0) { + return c; + } + } while (millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// private method to peek stream with timeout +int Stream::timedPeek() { + int c; + _startMillis = millis(); + do { + c = peek(); + if (c >= 0) { + return c; + } + } while (millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// returns peek of the next digit in the stream or -1 if timeout +// discards non-numeric characters +int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal) { + int c; + while (1) { + c = timedPeek(); + + if (c < 0 || c == '-' || (c >= '0' && c <= '9') || (detectDecimal && c == '.')) { + return c; + } + + switch (lookahead) { + case SKIP_NONE: return -1; // Fail code. + case SKIP_WHITESPACE: + switch (c) { + case ' ': + case '\t': + case '\r': + case '\n': break; + default: return -1; // Fail code. + } + case SKIP_ALL: break; + } + read(); // discard non-numeric + } +} + +// Public Methods +////////////////////////////////////////////////////////////// + +void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait +{ + _timeout = timeout; +} + +// find returns true if the target string is found +bool Stream::find(const char *target) { + return findUntil(target, strlen(target), NULL, 0); +} + +// reads data from the stream until the target string of given length is found +// returns true if target string is found, false if timed out +bool Stream::find(const char *target, size_t length) { + return findUntil(target, length, NULL, 0); +} + +// as find but search ends if the terminator string is found +bool Stream::findUntil(const char *target, const char *terminator) { + return findUntil(target, strlen(target), terminator, strlen(terminator)); +} + +// reads data from the stream until the target string of the given length is found +// search terminated if the terminator string is found +// returns true if target string is found, false if terminated or timed out +bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen) { + if (terminator == NULL) { + MultiTarget t[1] = {{target, targetLen, 0}}; + return findMulti(t, 1) == 0; + } else { + MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}}; + return findMulti(t, 2) == 0; + } +} + +// returns the first valid (long) integer value from the current position. +// lookahead determines how parseInt looks ahead in the stream. +// See LookaheadMode enumeration at the top of the file. +// Lookahead is terminated by the first character that is not a valid part of an integer. +// Once parsing commences, 'ignore' will be skipped in the stream. +long Stream::parseInt(LookaheadMode lookahead, char ignore) { + bool isNegative = false; + long value = 0; + int c; + + c = peekNextDigit(lookahead, false); + // ignore non numeric leading characters + if (c < 0) { + return 0; // zero returned if timeout + } + + do { + if ((char)c == ignore) + ; // ignore this character + else if (c == '-') { + isNegative = true; + } else if (c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + } + read(); // consume the character we got with peek + c = timedPeek(); + } while ((c >= '0' && c <= '9') || (char)c == ignore); + + if (isNegative) { + value = -value; + } + return value; +} + +// as parseInt but returns a floating point value +float Stream::parseFloat(LookaheadMode lookahead, char ignore) { + bool isNegative = false; + bool isFraction = false; + double value = 0.0; + int c; + double fraction = 1.0; + + c = peekNextDigit(lookahead, true); + // ignore non numeric leading characters + if (c < 0) { + return 0; // zero returned if timeout + } + + do { + if ((char)c == ignore) + ; // ignore + else if (c == '-') { + isNegative = true; + } else if (c == '.') { + isFraction = true; + } else if (c >= '0' && c <= '9') { // is c a digit? + if (isFraction) { + fraction *= 0.1; + value = value + fraction * (c - '0'); + } else { + value = value * 10 + c - '0'; + } + } + read(); // consume the character we got with peek + c = timedPeek(); + } while ((c >= '0' && c <= '9') || (c == '.' && !isFraction) || (char)c == ignore); + + if (isNegative) { + value = -value; + } + + return value; +} + +// read characters from stream into buffer +// terminates if length characters have been read, or timeout (see setTimeout) +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +// +size_t Stream::readBytes(char *buffer, size_t length) { + size_t count = 0; + while (count < length) { + int c = timedRead(); + if (c < 0) { + break; + } + *buffer++ = (char)c; + count++; + } + return count; +} + +// as readBytes with terminator character +// terminates if length characters have been read, timeout, or if the terminator character detected +// returns the number of characters placed in the buffer (0 means no valid data found) + +size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) { + size_t index = 0; + while (index < length) { + int c = timedRead(); + if (c < 0 || (char)c == terminator) { + break; + } + *buffer++ = (char)c; + index++; + } + return index; // return number of characters, not including null terminator +} + +String Stream::readString() { + String ret; + int c = timedRead(); + while (c >= 0) { + ret += (char)c; + c = timedRead(); + } + return ret; +} + +String Stream::readStringUntil(char terminator) { + String ret; + int c = timedRead(); + while (c >= 0 && (char)c != terminator) { + ret += (char)c; + c = timedRead(); + } + return ret; +} + +int Stream::findMulti(struct Stream::MultiTarget *targets, int tCount) { + // any zero length target string automatically matches and would make + // a mess of the rest of the algorithm. + for (struct MultiTarget *t = targets; t < targets + tCount; ++t) { + if (t->len <= 0) { + return t - targets; + } + } + + while (1) { + int c = timedRead(); + if (c < 0) { + return -1; + } + + for (struct MultiTarget *t = targets; t < targets + tCount; ++t) { + // the simple case is if we match, deal with that first. + if ((char)c == t->str[t->index]) { + if (++t->index == t->len) { + return t - targets; + } else { + continue; + } + } + + // if not we need to walk back and see if we could have matched further + // down the stream (ie '1112' doesn't match the first position in '11112' + // but it will match the second position so we can't just reset the current + // index to 0 when we find a mismatch. + if (t->index == 0) { + continue; + } + + int origIndex = t->index; + do { + --t->index; + // first check if current char works against the new current index + if ((char)c != t->str[t->index]) { + continue; + } + + // if it's the only char then we're good, nothing more to check + if (t->index == 0) { + t->index++; + break; + } + + // otherwise we need to check the rest of the found string + int diff = origIndex - t->index; + size_t i; + for (i = 0; i < t->index; ++i) { + if (t->str[i] != t->str[i + diff]) { + break; + } + } + + // if we successfully got through the previous loop then our current + // index is good. + if (i == t->index) { + t->index++; + break; + } + + // otherwise we just try the next index + } while (t->index); + } + } + // unreachable + return -1; +} diff --git a/cores/esp32/Stream.h b/cores/esp32/Stream.h new file mode 100644 index 0000000..37346cd --- /dev/null +++ b/cores/esp32/Stream.h @@ -0,0 +1,148 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + parsing functions based on TextFinder library by Michael Margolis +*/ + +#pragma once + +#include +#include "Print.h" + +// compatibility macros for testing +/* +#define getInt() parseInt() +#define getInt(ignore) parseInt(ignore) +#define getFloat() parseFloat() +#define getFloat(ignore) parseFloat(ignore) +#define getString( pre_string, post_string, buffer, length) +readBytesBetween( pre_string, terminator, buffer, length) +*/ + +// This enumeration provides the lookahead options for parseInt(), parseFloat() +// The rules set out here are used until either the first valid character is found +// or a time out occurs due to lack of input. +enum LookaheadMode { + SKIP_ALL, // All invalid characters are ignored. + SKIP_NONE, // Nothing is skipped, and the stream is not touched unless the first waiting character is valid. + SKIP_WHITESPACE // Only tabs, spaces, line feeds & carriage returns are skipped. +}; + +#define NO_IGNORE_CHAR '\x01' // a char not found in a valid ASCII numeric field + +class Stream : public Print { +protected: + unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read + unsigned long _startMillis; // used for timeout measurement + int timedRead(); // private method to read stream with timeout + int timedPeek(); // private method to peek stream with timeout + int peekNextDigit(LookaheadMode lookahead, bool detectDecimal); // returns the next numeric digit in the stream or -1 if timeout + +public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + + Stream() { + _timeout = 1000; + } + + // parsing methods + + void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + unsigned long getTimeout(void) { + return _timeout; + } + + bool find(const char *target); // reads data from the stream until the target string is found + bool find(const uint8_t *target) { + return find((const char *)target); + } + // returns true if target string is found, false if timed out (see setTimeout) + + bool find(const char *target, size_t length); // reads data from the stream until the target string of given length is found + bool find(const uint8_t *target, size_t length) { + return find((const char *)target, length); + } + // returns true if target string is found, false if timed out + + bool find(char target) { + return find(&target, 1); + } + + bool findUntil(const char *target, const char *terminator); // as find but search ends if the terminator string is found + bool findUntil(const uint8_t *target, const char *terminator) { + return findUntil((const char *)target, terminator); + } + + bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen); // as above but search ends if the terminate string is found + bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen) { + return findUntil((const char *)target, targetLen, terminate, termLen); + } + + long parseInt(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR); + // returns the first valid (long) integer value from the current position. + // lookahead determines how parseInt looks ahead in the stream. + // See LookaheadMode enumeration at the top of the file. + // Lookahead is terminated by the first character that is not a valid part of an integer. + // Once parsing commences, 'ignore' will be skipped in the stream. + + float parseFloat(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR); + // float version of parseInt + + virtual size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer + virtual size_t readBytes(uint8_t *buffer, size_t length) { + return readBytes((char *)buffer, length); + } + // terminates if length characters have been read or timeout (see setTimeout) + // returns the number of characters placed in the buffer (0 means no valid data found) + + size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character + size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) { + return readBytesUntil(terminator, (char *)buffer, length); + } + // terminates if length characters have been read, timeout, or if the terminator character detected + // returns the number of characters placed in the buffer (0 means no valid data found) + + // Arduino String functions to be added here + virtual String readString(); + String readStringUntil(char terminator); + +protected: + long parseInt(char ignore) { + return parseInt(SKIP_ALL, ignore); + } + float parseFloat(char ignore) { + return parseFloat(SKIP_ALL, ignore); + } + // These overload exists for compatibility with any class that has derived + // Stream and used parseFloat/Int with a custom ignore character. To keep + // the public API simple, these overload remains protected. + + struct MultiTarget { + const char *str; // string you're searching for + size_t len; // length of string you're searching for + size_t index; // index used by the search routine. + }; + + // This allows you to search for an arbitrary number of strings. + // Returns index of the target that is found first or -1 if timeout occurs. + int findMulti(struct MultiTarget *targets, int tCount); +}; + +#undef NO_IGNORE_CHAR diff --git a/cores/esp32/StreamString.cpp b/cores/esp32/StreamString.cpp new file mode 100644 index 0000000..d0117c3 --- /dev/null +++ b/cores/esp32/StreamString.cpp @@ -0,0 +1,64 @@ +/** + StreamString.cpp + + Copyright (c) 2015 Markus Sattler. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + */ + +#include +#include "StreamString.h" + +size_t StreamString::write(const uint8_t *data, size_t size) { + if (size && data) { + const unsigned int newlen = length() + size; + if (reserve(newlen + 1)) { + memcpy((void *)(wbuffer() + len()), (const void *)data, size); + setLen(newlen); + *(wbuffer() + newlen) = 0x00; // add null for string end + return size; + } + } + return 0; +} + +size_t StreamString::write(uint8_t data) { + return concat((char)data); +} + +int StreamString::available() { + return length(); +} + +int StreamString::read() { + if (length()) { + char c = charAt(0); + remove(0, 1); + return c; + } + return -1; +} + +int StreamString::peek() { + if (length()) { + char c = charAt(0); + return c; + } + return -1; +} + +void StreamString::flush() {} diff --git a/cores/esp32/StreamString.h b/cores/esp32/StreamString.h new file mode 100644 index 0000000..b4f2014 --- /dev/null +++ b/cores/esp32/StreamString.h @@ -0,0 +1,38 @@ +/** + StreamString.h + + Copyright (c) 2015 Markus Sattler. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#ifndef STREAMSTRING_H_ +#define STREAMSTRING_H_ +#include "Stream.h" +#include "WString.h" + +class StreamString : public Stream, public String { +public: + size_t write(const uint8_t *buffer, size_t size) override; + size_t write(uint8_t data) override; + + int available() override; + int read() override; + int peek() override; + void flush() override; +}; + +#endif /* STREAMSTRING_H_ */ diff --git a/cores/esp32/Tone.cpp b/cores/esp32/Tone.cpp new file mode 100644 index 0000000..ec8587d --- /dev/null +++ b/cores/esp32/Tone.cpp @@ -0,0 +1,152 @@ +#include +#include "esp32-hal-ledc.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" + +#if SOC_LEDC_SUPPORTED +static TaskHandle_t _tone_task = NULL; +static QueueHandle_t _tone_queue = NULL; +static int8_t _pin = -1; +static uint8_t _channel = 255; + +typedef enum { + TONE_START, + TONE_END +} tone_cmd_t; + +typedef struct { + tone_cmd_t tone_cmd; + uint8_t pin; + unsigned int frequency; + unsigned long duration; +} tone_msg_t; + +#ifdef SOC_LEDC_SUPPORT_HS_MODE +#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM << 1) +#else +#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM) +#endif + +static void tone_task(void *) { + tone_msg_t tone_msg; + while (1) { + xQueueReceive(_tone_queue, &tone_msg, portMAX_DELAY); + switch (tone_msg.tone_cmd) { + case TONE_START: + log_d("Task received from queue TONE_START: pin=%d, frequency=%u Hz, duration=%lu ms", tone_msg.pin, tone_msg.frequency, tone_msg.duration); + + if (_pin == -1) { + bool ret = true; + if (_channel == 255) { + ret = ledcAttach(tone_msg.pin, tone_msg.frequency, 10); + } else { + ret = ledcAttachChannel(tone_msg.pin, tone_msg.frequency, 10, _channel); + } + if (!ret) { + log_e("Tone start failed"); + break; + } + _pin = tone_msg.pin; + } + ledcWriteTone(tone_msg.pin, tone_msg.frequency); + + if (tone_msg.duration) { + delay(tone_msg.duration); + ledcWriteTone(tone_msg.pin, 0); + } + break; + + case TONE_END: + log_d("Task received from queue TONE_END: pin=%d", tone_msg.pin); + ledcWriteTone(tone_msg.pin, 0); + ledcDetach(tone_msg.pin); + _pin = -1; + break; + + default:; // do nothing + } // switch + } // infinite loop +} + +static int tone_init() { + if (_tone_queue == NULL) { + log_v("Creating tone queue"); + _tone_queue = xQueueCreate(128, sizeof(tone_msg_t)); + if (_tone_queue == NULL) { + log_e("Could not create tone queue"); + return 0; // ERR + } + log_v("Tone queue created"); + } + + if (_tone_task == NULL) { + log_v("Creating tone task"); + xTaskCreate( + tone_task, // Function to implement the task + "toneTask", // Name of the task + 3500, // Stack size in words + NULL, // Task input parameter + 10, // Priority of the task must be higher than Arduino task + &_tone_task // Task handle. + ); + if (_tone_task == NULL) { + log_e("Could not create tone task"); + return 0; // ERR + } + log_v("Tone task created"); + } + return 1; // OK +} + +void noTone(uint8_t pin) { + log_d("noTone was called"); + if (_pin == pin) { + if (tone_init()) { + tone_msg_t tone_msg = { + .tone_cmd = TONE_END, + .pin = pin, + .frequency = 0, // Ignored + .duration = 0, // Ignored + }; + xQueueReset(_tone_queue); // clear queue + xQueueSend(_tone_queue, &tone_msg, portMAX_DELAY); + } + } else { + log_e("Tone is not running on given pin %d", pin); + } +} + +// parameters: +// pin - pin number which will output the signal +// frequency - PWM frequency in Hz +// duration - time in ms - how long will the signal be outputted. +// If not provided, or 0 you must manually call noTone to end output +void tone(uint8_t pin, unsigned int frequency, unsigned long duration) { + log_d("pin=%d, frequency=%u Hz, duration=%lu ms", pin, frequency, duration); + if (_pin == -1 || _pin == pin) { + if (tone_init()) { + tone_msg_t tone_msg = { + .tone_cmd = TONE_START, + .pin = pin, + .frequency = frequency, + .duration = duration, + }; + xQueueSend(_tone_queue, &tone_msg, portMAX_DELAY); + return; + } + } else { + log_e("Tone is still running on pin %d, call noTone(%d) first!", _pin, _pin); + return; + } +} + +void setToneChannel(uint8_t channel) { + if (channel >= LEDC_CHANNELS) { + log_e("Channel %u is not available (maximum %u)!", channel, LEDC_CHANNELS); + return; + } + _channel = channel; +} + +#endif /* SOC_LEDC_SUPPORTED */ diff --git a/cores/esp32/USB.cpp b/cores/esp32/USB.cpp new file mode 100644 index 0000000..269e9a7 --- /dev/null +++ b/cores/esp32/USB.cpp @@ -0,0 +1,358 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "USB.h" + +#if SOC_USB_OTG_SUPPORTED +#if CONFIG_TINYUSB_ENABLED + +#include "pins_arduino.h" +#include "esp32-hal.h" +#include "esp32-hal-tinyusb.h" +#include "common/tusb_common.h" +#include "StreamString.h" +#include "rom/ets_sys.h" +#include "esp_mac.h" + +#ifndef USB_VID +#define USB_VID USB_ESPRESSIF_VID +#endif +#ifndef USB_PID +#define USB_PID 0x0002 +#endif +#ifndef USB_MANUFACTURER +#define USB_MANUFACTURER "Espressif Systems" +#endif +#ifndef USB_PRODUCT +#define USB_PRODUCT ARDUINO_BOARD +#endif +#ifndef USB_SERIAL +#if CONFIG_IDF_TARGET_ESP32S3 +#define USB_SERIAL "__MAC__" +#else +#define USB_SERIAL "0" +#endif +#endif +#ifndef USB_WEBUSB_ENABLED +#define USB_WEBUSB_ENABLED false +#endif +#ifndef USB_WEBUSB_URL +#define USB_WEBUSB_URL "https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html" +#endif + +#if CFG_TUD_DFU +__attribute__((weak)) uint16_t load_dfu_ota_descriptor(uint8_t *dst, uint8_t *itf) { + return 0; +} +#elif CFG_TUD_DFU_RUNTIME +static uint16_t load_dfu_descriptor(uint8_t *dst, uint8_t *itf) { +#define DFU_ATTRS (DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_CAN_UPLOAD | DFU_ATTR_MANIFESTATION_TOLERANT) + + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB DFU_RT"); + uint8_t descriptor[TUD_DFU_RT_DESC_LEN] = {// Interface number, string index, attributes, detach timeout, transfer size */ + TUD_DFU_RT_DESCRIPTOR(*itf, str_index, DFU_ATTRS, 700, 64) + }; + *itf += 1; + memcpy(dst, descriptor, TUD_DFU_RT_DESC_LEN); + return TUD_DFU_RT_DESC_LEN; +} +#endif /* CFG_TUD_DFU_RUNTIME */ + +#if CFG_TUD_DFU_RUNTIME +// Invoked on DFU_DETACH request to reboot to the bootloader +void tud_dfu_runtime_reboot_to_dfu_cb(void) { + usb_persist_restart(RESTART_BOOTLOADER_DFU); +} +#endif /* CFG_TUD_DFU_RUNTIME */ + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_EVENTS); + +static esp_event_loop_handle_t arduino_usb_event_loop_handle = NULL; + +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait) { + if (arduino_usb_event_loop_handle == NULL) { + return ESP_FAIL; + } + return esp_event_post_to(arduino_usb_event_loop_handle, event_base, event_id, event_data, event_data_size, ticks_to_wait); +} +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg) { + if (arduino_usb_event_loop_handle == NULL) { + return ESP_FAIL; + } + return esp_event_handler_register_with(arduino_usb_event_loop_handle, event_base, event_id, event_handler, event_handler_arg); +} + +static bool tinyusb_device_mounted = false; +static bool tinyusb_device_suspended = false; + +// Invoked when device is mounted (configured) +void tud_mount_cb(void) { + tinyusb_device_mounted = true; + arduino_usb_event_data_t p; + p.suspend.remote_wakeup_en = 0; + arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_STARTED_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY); +} + +// Invoked when device is unmounted +void tud_umount_cb(void) { + tinyusb_device_mounted = false; + arduino_usb_event_data_t p; + p.suspend.remote_wakeup_en = 0; + arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_STOPPED_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY); +} + +// Invoked when usb bus is suspended +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +void tud_suspend_cb(bool remote_wakeup_en) { + tinyusb_device_suspended = true; + arduino_usb_event_data_t p; + p.suspend.remote_wakeup_en = remote_wakeup_en; + arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_SUSPEND_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY); +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) { + tinyusb_device_suspended = false; + arduino_usb_event_data_t p; + p.suspend.remote_wakeup_en = 0; + arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_RESUME_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY); +} + +ESPUSB::ESPUSB(size_t task_stack_size, uint8_t event_task_priority) + : vid(USB_VID), pid(USB_PID), product_name(USB_PRODUCT), manufacturer_name(USB_MANUFACTURER), serial_number(USB_SERIAL), fw_version(0x0100), + usb_version(0x0200) // at least 2.1 or 3.x for BOS & webUSB + , + usb_class(TUSB_CLASS_MISC), usb_subclass(MISC_SUBCLASS_COMMON), usb_protocol(MISC_PROTOCOL_IAD), usb_attributes(TUSB_DESC_CONFIG_ATT_SELF_POWERED), + usb_power_ma(500), webusb_enabled(USB_WEBUSB_ENABLED), webusb_url(USB_WEBUSB_URL), _started(false), _task_stack_size(task_stack_size), + _event_task_priority(event_task_priority) { + if (!arduino_usb_event_loop_handle) { + esp_event_loop_args_t event_task_args = { + .queue_size = 5, + .task_name = "arduino_usb_events", + .task_priority = _event_task_priority, + .task_stack_size = _task_stack_size, + .task_core_id = tskNO_AFFINITY + }; + if (esp_event_loop_create(&event_task_args, &arduino_usb_event_loop_handle) != ESP_OK) { + log_e("esp_event_loop_create failed"); + } + } +} + +ESPUSB::~ESPUSB() { + if (arduino_usb_event_loop_handle) { + esp_event_loop_delete(arduino_usb_event_loop_handle); + arduino_usb_event_loop_handle = NULL; + } +} + +bool ESPUSB::begin() { + if (!_started) { +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + if (serial_number == "__MAC__") { + StreamString s; + uint8_t m[6]; + esp_efuse_mac_get_default(m); + s.printf("%02X%02X%02X%02X%02X%02X", m[0], m[1], m[2], m[3], m[4], m[5]); + serial_number = s; + } +#endif + tinyusb_device_config_t tinyusb_device_config = { + .vid = vid, + .pid = pid, + .product_name = product_name.c_str(), + .manufacturer_name = manufacturer_name.c_str(), + .serial_number = serial_number.c_str(), + .fw_version = fw_version, + .usb_version = usb_version, + .usb_class = usb_class, + .usb_subclass = usb_subclass, + .usb_protocol = usb_protocol, + .usb_attributes = usb_attributes, + .usb_power_ma = usb_power_ma, + .webusb_enabled = webusb_enabled, + .webusb_url = webusb_url.c_str() + }; + _started = tinyusb_init(&tinyusb_device_config) == ESP_OK; + } + return _started; +} + +void ESPUSB::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_ANY_EVENT, callback); +} +void ESPUSB::onEvent(arduino_usb_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_EVENTS, event, callback, this); +} + +ESPUSB::operator bool() const { + return _started && tinyusb_device_mounted; +} + +bool ESPUSB::enableDFU() { +#if CFG_TUD_DFU + return tinyusb_enable_interface(USB_INTERFACE_DFU, TUD_DFU_DESC_LEN(1), load_dfu_ota_descriptor) == ESP_OK; +#elif CFG_TUD_DFU_RUNTIME + return tinyusb_enable_interface(USB_INTERFACE_DFU, TUD_DFU_RT_DESC_LEN, load_dfu_descriptor) == ESP_OK; +#endif /* CFG_TUD_DFU_RUNTIME */ + return false; +} + +bool ESPUSB::VID(uint16_t v) { + if (!_started) { + vid = v; + } + return !_started; +} +uint16_t ESPUSB::VID(void) { + return vid; +} + +bool ESPUSB::PID(uint16_t p) { + if (!_started) { + pid = p; + } + return !_started; +} +uint16_t ESPUSB::PID(void) { + return pid; +} + +bool ESPUSB::firmwareVersion(uint16_t version) { + if (!_started) { + fw_version = version; + } + return !_started; +} +uint16_t ESPUSB::firmwareVersion(void) { + return fw_version; +} + +bool ESPUSB::usbVersion(uint16_t version) { + if (!_started) { + usb_version = version; + } + return !_started; +} +uint16_t ESPUSB::usbVersion(void) { + return usb_version; +} + +bool ESPUSB::usbPower(uint16_t mA) { + if (!_started) { + usb_power_ma = mA; + } + return !_started; +} +uint16_t ESPUSB::usbPower(void) { + return usb_power_ma; +} + +bool ESPUSB::usbClass(uint8_t _class) { + if (!_started) { + usb_class = _class; + } + return !_started; +} +uint8_t ESPUSB::usbClass(void) { + return usb_class; +} + +bool ESPUSB::usbSubClass(uint8_t subClass) { + if (!_started) { + usb_subclass = subClass; + } + return !_started; +} +uint8_t ESPUSB::usbSubClass(void) { + return usb_subclass; +} + +bool ESPUSB::usbProtocol(uint8_t protocol) { + if (!_started) { + usb_protocol = protocol; + } + return !_started; +} +uint8_t ESPUSB::usbProtocol(void) { + return usb_protocol; +} + +bool ESPUSB::usbAttributes(uint8_t attr) { + if (!_started) { + usb_attributes = attr; + } + return !_started; +} +uint8_t ESPUSB::usbAttributes(void) { + return usb_attributes; +} + +bool ESPUSB::webUSB(bool enabled) { + if (!_started) { + webusb_enabled = enabled; + if (enabled && usb_version < 0x0210) { + usb_version = 0x0210; + } + } + return !_started; +} +bool ESPUSB::webUSB(void) { + return webusb_enabled; +} + +bool ESPUSB::productName(const char *name) { + if (!_started) { + product_name = name; + } + return !_started; +} +const char *ESPUSB::productName(void) { + return product_name.c_str(); +} + +bool ESPUSB::manufacturerName(const char *name) { + if (!_started) { + manufacturer_name = name; + } + return !_started; +} +const char *ESPUSB::manufacturerName(void) { + return manufacturer_name.c_str(); +} + +bool ESPUSB::serialNumber(const char *name) { + if (!_started) { + serial_number = name; + } + return !_started; +} +const char *ESPUSB::serialNumber(void) { + return serial_number.c_str(); +} + +bool ESPUSB::webUSBURL(const char *name) { + if (!_started) { + webusb_url = name; + } + return !_started; +} +const char *ESPUSB::webUSBURL(void) { + return webusb_url.c_str(); +} + +ESPUSB USB; + +#endif /* CONFIG_TINYUSB_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/USB.h b/cores/esp32/USB.h new file mode 100644 index 0000000..782121e --- /dev/null +++ b/cores/esp32/USB.h @@ -0,0 +1,123 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "sdkconfig.h" +#if CONFIG_TINYUSB_ENABLED + +#include "esp_event.h" +#include "USBCDC.h" +#include "Arduino.h" // defines ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE and ARDUINO_SERIAL_EVENT_TASK_PRIORITY + +#define ARDUINO_USB_ON_BOOT (ARDUINO_USB_CDC_ON_BOOT | ARDUINO_USB_MSC_ON_BOOT | ARDUINO_USB_DFU_ON_BOOT) + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_EVENTS); + +typedef enum { + ARDUINO_USB_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_STARTED_EVENT = 0, + ARDUINO_USB_STOPPED_EVENT, + ARDUINO_USB_SUSPEND_EVENT, + ARDUINO_USB_RESUME_EVENT, + ARDUINO_USB_MAX_EVENT, +} arduino_usb_event_t; + +typedef union { + struct { + bool remote_wakeup_en; + } suspend; +} arduino_usb_event_data_t; + +class ESPUSB { +public: + ESPUSB(size_t event_task_stack_size = ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE, uint8_t event_task_priority = ARDUINO_SERIAL_EVENT_TASK_PRIORITY); + ~ESPUSB(); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_event_t event, esp_event_handler_t callback); + + bool VID(uint16_t v); + uint16_t VID(void); + + bool PID(uint16_t p); + uint16_t PID(void); + + bool firmwareVersion(uint16_t version); + uint16_t firmwareVersion(void); + + bool usbVersion(uint16_t version); + uint16_t usbVersion(void); + + bool usbPower(uint16_t mA); + uint16_t usbPower(void); + + bool usbClass(uint8_t _class); + uint8_t usbClass(void); + + bool usbSubClass(uint8_t subClass); + uint8_t usbSubClass(void); + + bool usbProtocol(uint8_t protocol); + uint8_t usbProtocol(void); + + bool usbAttributes(uint8_t attr); + uint8_t usbAttributes(void); + + bool webUSB(bool enabled); + bool webUSB(void); + + bool productName(const char *name); + const char *productName(void); + + bool manufacturerName(const char *name); + const char *manufacturerName(void); + + bool serialNumber(const char *name); + const char *serialNumber(void); + + bool webUSBURL(const char *name); + const char *webUSBURL(void); + + bool enableDFU(); + bool begin(); + operator bool() const; + +private: + uint16_t vid; + uint16_t pid; + String product_name; + String manufacturer_name; + String serial_number; + uint16_t fw_version; + uint16_t usb_version; + uint8_t usb_class; + uint8_t usb_subclass; + uint8_t usb_protocol; + uint8_t usb_attributes; + uint16_t usb_power_ma; + bool webusb_enabled; + String webusb_url; + + bool _started; + size_t _task_stack_size; + uint8_t _event_task_priority; +}; + +extern ESPUSB USB; + +#endif /* CONFIG_TINYUSB_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/USBCDC.cpp b/cores/esp32/USBCDC.cpp new file mode 100644 index 0000000..4eea884 --- /dev/null +++ b/cores/esp32/USBCDC.cpp @@ -0,0 +1,477 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "USBCDC.h" + +#if SOC_USB_OTG_SUPPORTED +#include "USB.h" +#if CONFIG_TINYUSB_CDC_ENABLED + +#include "esp32-hal-tinyusb.h" +#include "rom/ets_sys.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_CDC_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +USBCDC *devices[CFG_TUD_CDC]; + +static uint16_t load_cdc_descriptor(uint8_t *dst, uint8_t *itf) { + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB CDC"); + uint8_t descriptor[TUD_CDC_DESC_LEN] = {// Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(*itf, str_index, 0x85, CFG_TUD_ENDOINT_SIZE, 0x03, 0x84, CFG_TUD_ENDOINT_SIZE) + }; + *itf += 2; + memcpy(dst, descriptor, TUD_CDC_DESC_LEN); + return TUD_CDC_DESC_LEN; +} + +static uint16_t load_cdc_descriptor2(uint8_t *dst, uint8_t *itf) { + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB CDC2"); + uint8_t ep_ntfy = tinyusb_get_free_in_endpoint(); + TU_VERIFY(ep_ntfy != 0); + uint8_t ep_in = tinyusb_get_free_in_endpoint(); + TU_VERIFY(ep_in != 0); + uint8_t ep_out = tinyusb_get_free_out_endpoint(); + TU_VERIFY(ep_out != 0); + uint8_t descriptor[TUD_CDC_DESC_LEN] = { + // Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(*itf, str_index, (uint8_t)(0x80 | ep_ntfy), CFG_TUD_ENDOINT_SIZE, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE) + }; + *itf += 2; + memcpy(dst, descriptor, TUD_CDC_DESC_LEN); + return TUD_CDC_DESC_LEN; +} + +// Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE +void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { + //log_v("ITF: %u, DTR: %u, RTS: %u", itf, dtr, rts); + if (itf < CFG_TUD_CDC && devices[itf] != NULL) { + devices[itf]->_onLineState(dtr, rts); + } +} + +// Invoked when line coding is change via SET_LINE_CODING +void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const *p_line_coding) { + //log_v("ITF: %u, BITRATE: %lu, STOP_BITS: %u, PARITY: %u, DATA_BITS: %u", itf, p_line_coding->bit_rate, p_line_coding->stop_bits, p_line_coding->parity, p_line_coding->data_bits); + if (itf < CFG_TUD_CDC && devices[itf] != NULL) { + devices[itf]->_onLineCoding(p_line_coding->bit_rate, p_line_coding->stop_bits, p_line_coding->parity, p_line_coding->data_bits); + } +} + +// Invoked when received new data +void tud_cdc_rx_cb(uint8_t itf) { + //log_v("ITF: %u", itf); + if (itf < CFG_TUD_CDC && devices[itf] != NULL) { + devices[itf]->_onRX(); + } +} + +// Invoked when received send break +void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms) { + //log_v("itf: %u, duration_ms: %u", itf, duration_ms); +} + +// Invoked when space becomes available in TX buffer +void tud_cdc_tx_complete_cb(uint8_t itf) { + if (itf < CFG_TUD_CDC && devices[itf] != NULL) { + devices[itf]->_onTX(); + } +} + +static void ARDUINO_ISR_ATTR cdc0_write_char(char c) { + if (CFG_TUD_CDC && devices[0] != NULL) { + tud_cdc_n_write_char(0, c); + } +} + +static void usb_unplugged_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) { + ((USBCDC *)arg)->_onUnplugged(); +} + +USBCDC::USBCDC(uint8_t itfn) + : itf(itfn), bit_rate(0), stop_bits(0), parity(0), data_bits(0), dtr(false), rts(false), connected(false), reboot_enable(true), rx_queue(NULL), tx_lock(NULL), + tx_timeout_ms(250) { + if (itf < CFG_TUD_CDC) { + if (itf == 0) { + tinyusb_enable_interface(USB_INTERFACE_CDC, TUD_CDC_DESC_LEN, load_cdc_descriptor); + } else { + tinyusb_enable_interface(USB_INTERFACE_CDC2, TUD_CDC_DESC_LEN, load_cdc_descriptor2); + } + arduino_usb_event_handler_register_with(ARDUINO_USB_EVENTS, ARDUINO_USB_STOPPED_EVENT, usb_unplugged_cb, this); + } else { + log_e("Maximum of %u CDC devices are supported", CFG_TUD_CDC); + } +} + +USBCDC::~USBCDC() { + end(); +} + +void USBCDC::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_CDC_ANY_EVENT, callback); +} +void USBCDC::onEvent(arduino_usb_cdc_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_CDC_EVENTS, event, callback, this); +} + +size_t USBCDC::setRxBufferSize(size_t rx_queue_len) { + size_t currentQueueSize = rx_queue ? uxQueueSpacesAvailable(rx_queue) + uxQueueMessagesWaiting(rx_queue) : 0; + + if (rx_queue_len != currentQueueSize) { + QueueHandle_t new_rx_queue = NULL; + if (rx_queue_len) { + new_rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t)); + if (!new_rx_queue) { + log_e("CDC Queue creation failed."); + return 0; + } + if (rx_queue) { + size_t copySize = uxQueueMessagesWaiting(rx_queue); + if (copySize > 0) { + for (size_t i = 0; i < copySize; i++) { + uint8_t ch = 0; + xQueueReceive(rx_queue, &ch, 0); + if (!xQueueSend(new_rx_queue, &ch, 0)) { + arduino_usb_cdc_event_data_t p; + p.rx_overflow.dropped_bytes = copySize - i; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_OVERFLOW_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + log_e("CDC RX Overflow."); + break; + } + } + } + vQueueDelete(rx_queue); + } + rx_queue = new_rx_queue; + return rx_queue_len; + } else { + if (rx_queue) { + vQueueDelete(rx_queue); + rx_queue = NULL; + } + } + } + return rx_queue_len; +} + +void USBCDC::begin(unsigned long baud) { + if (itf >= CFG_TUD_CDC) { + return; + } + if (tx_lock == NULL) { + tx_lock = xSemaphoreCreateMutex(); + } + // if rx_queue was set before begin(), keep it + if (!rx_queue) { + setRxBufferSize(256); //default if not preset + } + devices[itf] = this; +} + +void USBCDC::end() { + if (itf >= CFG_TUD_CDC) { + return; + } + connected = false; + devices[itf] = NULL; + setRxBufferSize(0); + if (tx_lock != NULL) { + vSemaphoreDelete(tx_lock); + tx_lock = NULL; + } +} + +void USBCDC::setTxTimeoutMs(uint32_t timeout) { + tx_timeout_ms = timeout; +} + +void USBCDC::_onUnplugged(void) { + if (connected) { + connected = false; + dtr = false; + rts = false; + arduino_usb_cdc_event_data_t p; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } +} + +enum { + CDC_LINE_IDLE, + CDC_LINE_1, + CDC_LINE_2, + CDC_LINE_3 +}; +void USBCDC::_onLineState(bool _dtr, bool _rts) { + static uint8_t lineState = CDC_LINE_IDLE; + + if (dtr == _dtr && rts == _rts) { + return; // Skip duplicate events + } + + dtr = _dtr; + rts = _rts; + + if (reboot_enable) { + if (!dtr && rts) { + if (lineState == CDC_LINE_IDLE) { + lineState++; + if (connected) { + connected = false; + arduino_usb_cdc_event_data_t p; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } + // } else if(lineState == CDC_LINE_2){//esptool.js + // lineState++; + } else { + lineState = CDC_LINE_IDLE; + } + } else if (dtr && rts) { + if (lineState == CDC_LINE_1) { + lineState++; + } else { + lineState = CDC_LINE_IDLE; + } + } else if (dtr && !rts) { + if (lineState == CDC_LINE_2) { + lineState++; + // } else if(lineState == CDC_LINE_IDLE){//esptool.js + // lineState++; + } else { + lineState = CDC_LINE_IDLE; + } + } else if (!dtr && !rts) { + if (lineState == CDC_LINE_3) { + usb_persist_restart(RESTART_BOOTLOADER); + } else { + lineState = CDC_LINE_IDLE; + } + } + } + + if (lineState == CDC_LINE_IDLE) { + if (dtr && rts && !connected) { + connected = true; + arduino_usb_cdc_event_data_t p; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_CONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } else if (!dtr && connected) { + connected = false; + arduino_usb_cdc_event_data_t p; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } + arduino_usb_cdc_event_data_t l; + l.line_state.dtr = dtr; + l.line_state.rts = rts; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_LINE_STATE_EVENT, &l, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } +} + +void USBCDC::_onLineCoding(uint32_t _bit_rate, uint8_t _stop_bits, uint8_t _parity, uint8_t _data_bits) { + if (bit_rate != _bit_rate || data_bits != _data_bits || stop_bits != _stop_bits || parity != _parity) { + // ArduinoIDE sends LineCoding with 1200bps baud to reset the device + if (reboot_enable && _bit_rate == 1200) { + usb_persist_restart(RESTART_BOOTLOADER); + } else { + bit_rate = _bit_rate; + data_bits = _data_bits; + stop_bits = _stop_bits; + parity = _parity; + arduino_usb_cdc_event_data_t p; + p.line_coding.bit_rate = bit_rate; + p.line_coding.data_bits = data_bits; + p.line_coding.stop_bits = stop_bits; + p.line_coding.parity = parity; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_LINE_CODING_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } + } +} + +void USBCDC::_onRX() { + arduino_usb_cdc_event_data_t p; + uint8_t buf[CONFIG_TINYUSB_CDC_RX_BUFSIZE + 1]; + uint32_t count = tud_cdc_n_read(itf, buf, CONFIG_TINYUSB_CDC_RX_BUFSIZE); + for (uint32_t i = 0; i < count; i++) { + if (rx_queue == NULL || !xQueueSend(rx_queue, buf + i, 10)) { + p.rx_overflow.dropped_bytes = count - i; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_OVERFLOW_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + log_e("CDC RX Overflow."); + count = i; + break; + } + } + if (count) { + p.rx.len = count; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); + } +} + +void USBCDC::_onTX() { + arduino_usb_cdc_event_data_t p; + arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_TX_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY); +} + +void USBCDC::enableReboot(bool enable) { + reboot_enable = enable; +} +bool USBCDC::rebootEnabled(void) { + return reboot_enable; +} + +int USBCDC::available(void) { + if (itf >= CFG_TUD_CDC || rx_queue == NULL) { + return -1; + } + return uxQueueMessagesWaiting(rx_queue); +} + +int USBCDC::peek(void) { + if (itf >= CFG_TUD_CDC || rx_queue == NULL) { + return -1; + } + uint8_t c; + if (xQueuePeek(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +int USBCDC::read(void) { + if (itf >= CFG_TUD_CDC || rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + if (xQueueReceive(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +size_t USBCDC::read(uint8_t *buffer, size_t size) { + if (itf >= CFG_TUD_CDC || rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + size_t count = 0; + while (count < size && xQueueReceive(rx_queue, &c, 0)) { + buffer[count++] = c; + } + return count; +} + +void USBCDC::flush(void) { + if (itf >= CFG_TUD_CDC || tx_lock == NULL || !tud_cdc_n_connected(itf)) { + return; + } + if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return; + } + tud_cdc_n_write_flush(itf); + xSemaphoreGive(tx_lock); +} + +int USBCDC::availableForWrite(void) { + if (itf >= CFG_TUD_CDC || tx_lock == NULL || !tud_cdc_n_connected(itf)) { + return 0; + } + if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return 0; + } + size_t a = tud_cdc_n_write_available(itf); + xSemaphoreGive(tx_lock); + return a; +} + +size_t USBCDC::write(const uint8_t *buffer, size_t size) { + if (itf >= CFG_TUD_CDC || tx_lock == NULL || buffer == NULL || size == 0 || !tud_cdc_n_connected(itf)) { + return 0; + } + if (xPortInIsrContext()) { + BaseType_t taskWoken = false; + if (xSemaphoreTakeFromISR(tx_lock, &taskWoken) != pdPASS) { + return 0; + } + } else if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) { + return 0; + } + size_t to_send = size, so_far = 0; + // writeTimeout will prevent that TinyUSB failure locks the while(to_send) loop + uint32_t writeTimeout = millis() + tx_timeout_ms; + while (to_send) { + if (!tud_cdc_n_connected(itf) || (int32_t)(millis() - writeTimeout) >= 0) { + log_e("USB is disconnected or CDC writing has timed out."); + size = so_far; + break; + } + size_t space = tud_cdc_n_write_available(itf); + if (!space) { + tud_cdc_n_write_flush(itf); + continue; + } + if (space > to_send) { + space = to_send; + } + size_t sent = tud_cdc_n_write(itf, buffer + so_far, space); + if (sent) { + so_far += sent; + to_send -= sent; + tud_cdc_n_write_flush(itf); + } else { + size = so_far; + break; + } + } + if (xPortInIsrContext()) { + BaseType_t taskWoken = false; + xSemaphoreGiveFromISR(tx_lock, &taskWoken); + } else { + xSemaphoreGive(tx_lock); + } + return size; +} + +size_t USBCDC::write(uint8_t c) { + return write(&c, 1); +} + +uint32_t USBCDC::baudRate() { + return bit_rate; +} + +void USBCDC::setDebugOutput(bool en) { + if (itf) { + return; + } + if (en) { + uartSetDebug(NULL); + ets_install_putc2((void (*)(char)) & cdc0_write_char); + } else { + ets_install_putc2(NULL); + } + ets_install_putc1(NULL); // closes UART log output +} + +USBCDC::operator bool() const { + if (itf >= CFG_TUD_CDC) { + return false; + } + return connected; +} + +#if !ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT // Native USB CDC selected +// USBSerial is always available to be used +USBCDC USBSerial(0); +#endif + +#endif /* CONFIG_TINYUSB_CDC_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/USBCDC.h b/cores/esp32/USBCDC.h new file mode 100644 index 0000000..4221c37 --- /dev/null +++ b/cores/esp32/USBCDC.h @@ -0,0 +1,144 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "sdkconfig.h" +#if CONFIG_TINYUSB_CDC_ENABLED + +#include +#include "esp_event.h" +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" +#include "Stream.h" + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_CDC_EVENTS); + +typedef enum { + ARDUINO_USB_CDC_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_CDC_CONNECTED_EVENT = 0, + ARDUINO_USB_CDC_DISCONNECTED_EVENT, + ARDUINO_USB_CDC_LINE_STATE_EVENT, + ARDUINO_USB_CDC_LINE_CODING_EVENT, + ARDUINO_USB_CDC_RX_EVENT, + ARDUINO_USB_CDC_TX_EVENT, + ARDUINO_USB_CDC_RX_OVERFLOW_EVENT, + ARDUINO_USB_CDC_MAX_EVENT, +} arduino_usb_cdc_event_t; + +typedef union { + struct { + bool dtr; + bool rts; + } line_state; + struct { + uint32_t bit_rate; + uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits + uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space + uint8_t data_bits; ///< can be 5, 6, 7, 8 or 16 + } line_coding; + struct { + size_t len; + } rx; + struct { + size_t dropped_bytes; + } rx_overflow; +} arduino_usb_cdc_event_data_t; + +class USBCDC : public Stream { +public: + USBCDC(uint8_t itf = 0); + ~USBCDC(); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_cdc_event_t event, esp_event_handler_t callback); + + size_t setRxBufferSize(size_t size); + void setTxTimeoutMs(uint32_t timeout); + void begin(unsigned long baud = 0); + void end(); + + int available(void); + int availableForWrite(void); + int peek(void); + int read(void); + size_t read(uint8_t *buffer, size_t size); + size_t write(uint8_t); + size_t write(const uint8_t *buffer, size_t size); + void flush(void); + + inline size_t read(char *buffer, size_t size) { + return read((uint8_t *)buffer, size); + } + inline size_t write(const char *buffer, size_t size) { + return write((uint8_t *)buffer, size); + } + inline size_t write(const char *s) { + return write((uint8_t *)s, strlen(s)); + } + inline size_t write(unsigned long n) { + return write((uint8_t)n); + } + inline size_t write(long n) { + return write((uint8_t)n); + } + inline size_t write(unsigned int n) { + return write((uint8_t)n); + } + inline size_t write(int n) { + return write((uint8_t)n); + } + uint32_t baudRate(); + void setDebugOutput(bool); + operator bool() const; + + void enableReboot(bool enable); + bool rebootEnabled(void); + + //internal methods + void _onDFU(void); + void _onLineState(bool _dtr, bool _rts); + void _onLineCoding(uint32_t _bit_rate, uint8_t _stop_bits, uint8_t _parity, uint8_t _data_bits); + void _onRX(void); + void _onTX(void); + void _onUnplugged(void); + +protected: + uint8_t itf; + uint32_t bit_rate; + uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits + uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space + uint8_t data_bits; ///< can be 5, 6, 7, 8 or 16 + bool dtr; + bool rts; + bool connected; + bool reboot_enable; + QueueHandle_t rx_queue; + SemaphoreHandle_t tx_lock; + uint32_t tx_timeout_ms; +}; + +#if !ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT // Native USB CDC selected +#ifndef USB_SERIAL_IS_DEFINED +#define USB_SERIAL_IS_DEFINED 1 +#endif +// USBSerial is always available to be used +extern USBCDC USBSerial; +#endif + +#endif /* CONFIG_TINYUSB_CDC_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/USBMSC.cpp b/cores/esp32/USBMSC.cpp new file mode 100644 index 0000000..aeb7988 --- /dev/null +++ b/cores/esp32/USBMSC.cpp @@ -0,0 +1,267 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "USBMSC.h" + +#if SOC_USB_OTG_SUPPORTED +#if CONFIG_TINYUSB_MSC_ENABLED + +#include "esp32-hal-tinyusb.h" + +extern "C" uint16_t tusb_msc_load_descriptor(uint8_t *dst, uint8_t *itf) { + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB MSC"); + uint8_t ep_num = tinyusb_get_free_duplex_endpoint(); + TU_VERIFY(ep_num != 0); + uint8_t descriptor[TUD_MSC_DESC_LEN] = {// Interface number, string index, EP Out & EP In address, EP size + TUD_MSC_DESCRIPTOR(*itf, str_index, ep_num, (uint8_t)(0x80 | ep_num), CFG_TUD_ENDOINT_SIZE) + }; + *itf += 1; + memcpy(dst, descriptor, TUD_MSC_DESC_LEN); + return TUD_MSC_DESC_LEN; +} + +typedef struct { + bool media_present; + bool is_writable; + uint8_t vendor_id[8]; + uint8_t product_id[16]; + uint8_t product_rev[4]; + uint16_t block_size; + uint32_t block_count; + bool (*start_stop)(uint8_t power_condition, bool start, bool load_eject); + int32_t (*read)(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize); + int32_t (*write)(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize); +} msc_lun_t; + +static const uint8_t MSC_MAX_LUN = 3; +static uint8_t MSC_ACTIVE_LUN = 0; +static msc_lun_t msc_luns[MSC_MAX_LUN]; + +static void cplstr(void *dst, const void *src, size_t max_len) { + if (!src || !dst || !max_len) { + return; + } + size_t l = strlen((const char *)src); + if (l > max_len) { + l = max_len; + } + memcpy(dst, src, l); +} + +// Invoked when received GET_MAX_LUN request, required for multiple LUNs implementation +uint8_t tud_msc_get_maxlun_cb(void) { + log_v("%u", MSC_ACTIVE_LUN); + return MSC_ACTIVE_LUN; +} + +// Invoked when received SCSI_CMD_INQUIRY +// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively +void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { + log_v("[%u]", lun); + cplstr(vendor_id, msc_luns[lun].vendor_id, 8); + cplstr(product_id, msc_luns[lun].product_id, 16); + cplstr(product_rev, msc_luns[lun].product_rev, 4); +} + +// Invoked when received Test Unit Ready command. +// return true allowing host to read/write this LUN e.g SD card inserted +bool tud_msc_test_unit_ready_cb(uint8_t lun) { + log_v("[%u]: %u", lun, msc_luns[lun].media_present); + return msc_luns[lun].media_present; // RAM disk is always ready +} + +// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size +// Application update block count and block size +void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) { + log_v("[%u]", lun); + if (!msc_luns[lun].media_present) { + *block_count = 0; + *block_size = 0; + return; + } + + *block_count = msc_luns[lun].block_count; + *block_size = msc_luns[lun].block_size; +} + +// Invoked when received Start Stop Unit command +// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage +// - Start = 1 : active mode, if load_eject = 1 : load disk storage +bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) { + log_v("[%u] power: %u, start: %u, eject: %u", lun, power_condition, start, load_eject); + if (msc_luns[lun].start_stop) { + return msc_luns[lun].start_stop(power_condition, start, load_eject); + } + return true; +} + +// Callback invoked when received READ10 command. +// Copy disk's data to buffer (up to bufsize) and return number of copied bytes. +int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) { + log_v("[%u], lba: %u, offset: %u, bufsize: %u", lun, lba, offset, bufsize); + if (!msc_luns[lun].media_present) { + return 0; + } + if (msc_luns[lun].read) { + return msc_luns[lun].read(lba, offset, buffer, bufsize); + } + return 0; +} + +// Callback invoked when received WRITE10 command. +// Process data in buffer to disk's storage and return number of written bytes +int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) { + log_v("[%u], lba: %u, offset: %u, bufsize: %u", lun, lba, offset, bufsize); + if (!msc_luns[lun].media_present) { + return 0; + } + if (msc_luns[lun].write) { + return msc_luns[lun].write(lba, offset, buffer, bufsize); + } + return 0; +} + +// Callback invoked when received an SCSI command not in built-in list below +// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE +// - READ10 and WRITE10 has their own callbacks +int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) { + // read10 & write10 has their own callback and MUST not be handled here + log_v("[%u] cmd: %u, bufsize: %u", lun, scsi_cmd[0], bufsize); + + void const *response = NULL; + uint16_t resplen = 0; + + // most scsi handled is input + bool in_xfer = true; + + if (!msc_luns[lun].media_present) { + return -1; + } + + switch (scsi_cmd[0]) { + case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: + // Host is about to read/write etc ... better not to disconnect disk + resplen = 0; + break; + + default: + // Set Sense = Invalid Command Operation + tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + + // negative means error -> tinyusb could stall and/or response with failed status + resplen = -1; + break; + } + + // return resplen must not larger than bufsize + if (resplen > bufsize) { + resplen = bufsize; + } + + if (response && (resplen > 0)) { + if (in_xfer) { + memcpy(buffer, response, resplen); + } else { + // SCSI output + } + } + + return resplen; +} + +bool tud_msc_is_writable_cb(uint8_t lun) { + log_v("[%u]: %u", lun, msc_luns[lun].is_writable); + return msc_luns[lun].is_writable; // RAM disk is always ready +} + +USBMSC::USBMSC() { + if (MSC_ACTIVE_LUN < MSC_MAX_LUN) { + _lun = MSC_ACTIVE_LUN; + MSC_ACTIVE_LUN++; + msc_luns[_lun].media_present = false; + msc_luns[_lun].is_writable = true; + msc_luns[_lun].vendor_id[0] = 0; + msc_luns[_lun].product_id[0] = 0; + msc_luns[_lun].product_rev[0] = 0; + msc_luns[_lun].block_size = 0; + msc_luns[_lun].block_count = 0; + msc_luns[_lun].start_stop = NULL; + msc_luns[_lun].read = NULL; + msc_luns[_lun].write = NULL; + } + if (_lun == 0) { + tinyusb_enable_interface(USB_INTERFACE_MSC, TUD_MSC_DESC_LEN, tusb_msc_load_descriptor); + } +} + +USBMSC::~USBMSC() { + end(); +} + +bool USBMSC::begin(uint32_t block_count, uint16_t block_size) { + msc_luns[_lun].block_size = block_size; + msc_luns[_lun].block_count = block_count; + if (!msc_luns[_lun].block_size || !msc_luns[_lun].block_count || !msc_luns[_lun].read || !msc_luns[_lun].write) { + return false; + } + return true; +} + +void USBMSC::end() { + msc_luns[_lun].media_present = false; + msc_luns[_lun].is_writable = false; + msc_luns[_lun].vendor_id[0] = 0; + msc_luns[_lun].product_id[0] = 0; + msc_luns[_lun].product_rev[0] = 0; + msc_luns[_lun].block_size = 0; + msc_luns[_lun].block_count = 0; + msc_luns[_lun].start_stop = NULL; + msc_luns[_lun].read = NULL; + msc_luns[_lun].write = NULL; +} + +void USBMSC::vendorID(const char *vid) { + cplstr(msc_luns[_lun].vendor_id, vid, 8); +} + +void USBMSC::productID(const char *pid) { + cplstr(msc_luns[_lun].product_id, pid, 16); +} + +void USBMSC::productRevision(const char *rev) { + cplstr(msc_luns[_lun].product_rev, rev, 4); +} + +void USBMSC::onStartStop(msc_start_stop_cb cb) { + msc_luns[_lun].start_stop = cb; +} + +void USBMSC::onRead(msc_read_cb cb) { + msc_luns[_lun].read = cb; +} + +void USBMSC::onWrite(msc_write_cb cb) { + msc_luns[_lun].write = cb; +} + +void USBMSC::isWritable(bool is_writable) { + msc_luns[_lun].is_writable = is_writable; +} + +void USBMSC::mediaPresent(bool media_present) { + msc_luns[_lun].media_present = media_present; +} + +#endif /* CONFIG_TINYUSB_MSC_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/USBMSC.h b/cores/esp32/USBMSC.h new file mode 100644 index 0000000..454aca3 --- /dev/null +++ b/cores/esp32/USBMSC.h @@ -0,0 +1,57 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include +#include +#include "sdkconfig.h" + +#if CONFIG_TINYUSB_MSC_ENABLED + +// Invoked when received Start Stop Unit command +// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage +// - Start = 1 : active mode, if load_eject = 1 : load disk storage +typedef bool (*msc_start_stop_cb)(uint8_t power_condition, bool start, bool load_eject); + +// Copy disk's data to buffer (up to bufsize) and return number of copied bytes. +typedef int32_t (*msc_read_cb)(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize); + +// Process data in buffer to disk's storage and return number of written bytes +typedef int32_t (*msc_write_cb)(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize); + +class USBMSC { +public: + USBMSC(); + ~USBMSC(); + bool begin(uint32_t block_count, uint16_t block_size); + void end(); + void vendorID(const char *vid); //max 8 chars + void productID(const char *pid); //max 16 chars + void productRevision(const char *ver); //max 4 chars + void mediaPresent(bool media_present); + void isWritable(bool is_writable); + void onStartStop(msc_start_stop_cb cb); + void onRead(msc_read_cb cb); + void onWrite(msc_write_cb cb); + +private: + uint8_t _lun; +}; + +#endif /* CONFIG_TINYUSB_MSC_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/Udp.h b/cores/esp32/Udp.h new file mode 100644 index 0000000..3d3daef --- /dev/null +++ b/cores/esp32/Udp.h @@ -0,0 +1,94 @@ +/* + * Udp.cpp: Library to send/receive UDP packets. + * + * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these) + * 1) UDP does not guarantee the order in which assembled UDP packets are received. This + * might not happen often in practice, but in larger network topologies, a UDP + * packet can be received out of sequence. + * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being + * aware of it. Again, this may not be a concern in practice on small local networks. + * For more information, see http://www.cafeaulait.org/course/week12/35.html + * + * MIT License: + * Copyright (c) 2008 Bjoern Hartmann + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * bjoern@cs.stanford.edu 12/30/2008 + */ + +#ifndef udp_h +#define udp_h + +#include +#include + +class UDP : public Stream { + +public: + virtual uint8_t begin(uint16_t) = 0; // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use + virtual uint8_t beginMulticast(IPAddress, uint16_t) { + return 0; + } // initialize, start listening on specified multicast IP address and port. Returns 1 if successful, 0 on failure + virtual void stop() = 0; // Finish with the UDP socket + + // Sending UDP packets + + // Start building up a packet to send to the remote host specific in ip and port + // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port + virtual int beginPacket(IPAddress ip, uint16_t port) = 0; + // Start building up a packet to send to the remote host specific in host and port + // Returns 1 if successful, 0 if there was a problem resolving the hostname or port + virtual int beginPacket(const char *host, uint16_t port) = 0; + // Finish off this packet and send it + // Returns 1 if the packet was sent successfully, 0 if there was an error + virtual int endPacket() = 0; + // Write a single byte into the packet + virtual size_t write(uint8_t) = 0; + // Write size bytes from buffer into the packet + virtual size_t write(const uint8_t *buffer, size_t size) = 0; + + // Start processing the next available incoming packet + // Returns the size of the packet in bytes, or 0 if no packets are available + virtual int parsePacket() = 0; + // Number of bytes remaining in the current packet + virtual int available() = 0; + // Read a single byte from the current packet + virtual int read() = 0; + // Read up to len bytes from the current packet and place them into buffer + // Returns the number of bytes read, or 0 if none are available + virtual int read(unsigned char *buffer, size_t len) = 0; + // Read up to len characters from the current packet and place them into buffer + // Returns the number of characters read, or 0 if none are available + virtual int read(char *buffer, size_t len) = 0; + // Return the next byte from the current packet without moving on to the next byte + virtual int peek() = 0; + virtual void flush() = 0; // Finish reading the current packet + + // Return the IP address of the host who sent the current incoming packet + virtual IPAddress remoteIP() = 0; + // Return the port of the host who sent the current incoming packet + virtual uint16_t remotePort() = 0; + +protected: + uint8_t *rawIPAddress(IPAddress &addr) { + return addr.raw_address(); + } +}; + +#endif diff --git a/cores/esp32/WCharacter.h b/cores/esp32/WCharacter.h new file mode 100644 index 0000000..611d943 --- /dev/null +++ b/cores/esp32/WCharacter.h @@ -0,0 +1,138 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include +#define isascii(__c) ((unsigned)(__c) <= 0177) +#define toascii(__c) ((__c) & 0177) + +// WCharacter.h prototypes +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c) __attribute__((always_inline)); + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) { + return (isalnum(c) == 0 ? false : true); +} + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) { + return (isalpha(c) == 0 ? false : true); +} + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) { + return (isascii(c) == 0 ? false : true); +} + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) { + return (isblank(c) == 0 ? false : true); +} + +// Checks for a control character. +inline boolean isControl(int c) { + return (iscntrl(c) == 0 ? false : true); +} + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) { + return (isdigit(c) == 0 ? false : true); +} + +// Checks for any printable character except space. +inline boolean isGraph(int c) { + return (isgraph(c) == 0 ? false : true); +} + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) { + return (islower(c) == 0 ? false : true); +} + +// Checks for any printable character including space. +inline boolean isPrintable(int c) { + return (isprint(c) == 0 ? false : true); +} + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) { + return (ispunct(c) == 0 ? false : true); +} + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) { + return (isspace(c) == 0 ? false : true); +} + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) { + return (isupper(c) == 0 ? false : true); +} + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) { + return (isxdigit(c) == 0 ? false : true); +} + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) { + return toascii(c); +} + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) { + return tolower(c); +} + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) { + return toupper(c); +} + +#endif diff --git a/cores/esp32/WMath.cpp b/cores/esp32/WMath.cpp new file mode 100644 index 0000000..13b736a --- /dev/null +++ b/cores/esp32/WMath.cpp @@ -0,0 +1,89 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.org.co + Copyright (c) 2004-06 Hernando Barragan + Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/ + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id$ + */ + +extern "C" { +#include +#include "esp_system.h" +} +#include "esp32-hal-log.h" +#include "esp_random.h" + +// Allows the user to choose between Real Hardware +// or Software Pseudo random generators for the +// Arduino random() functions +static bool s_useRandomHW = true; +void useRealRandomGenerator(bool useRandomHW) { + s_useRandomHW = useRandomHW; +} + +// Calling randomSeed() will force the +// Pseudo Random generator like in +// Arduino mainstream API +void randomSeed(unsigned long seed) { + if (seed != 0) { + srand(seed); + s_useRandomHW = false; + } +} + +long random(long howsmall, long howbig); +long random(long howbig) { + if (howbig == 0) { + return 0; + } + if (howbig < 0) { + return (random(0, -howbig)); + } + // if randomSeed was called, fall back to software PRNG + uint32_t val = (s_useRandomHW) ? esp_random() : rand(); + return val % howbig; +} + +long random(long howsmall, long howbig) { + if (howsmall >= howbig) { + return howsmall; + } + long diff = howbig - howsmall; + return random(diff) + howsmall; +} + +long map(long x, long in_min, long in_max, long out_min, long out_max) { + const long run = in_max - in_min; + if (run == 0) { + log_e("map(): Invalid input range, min == max"); + return -1; // AVR returns -1, SAM returns 0 + } + const long rise = out_max - out_min; + const long delta = x - in_min; + return (delta * rise) / run + out_min; +} + +uint16_t makeWord(uint16_t w) { + return w; +} + +uint16_t makeWord(uint8_t h, uint8_t l) { + return (h << 8) | l; +} diff --git a/cores/esp32/WString.cpp b/cores/esp32/WString.cpp new file mode 100644 index 0000000..ead5721 --- /dev/null +++ b/cores/esp32/WString.cpp @@ -0,0 +1,934 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + Modified by Ivan Grokhotkov, 2014 - esp8266 support + Modified by Michael C. Miller, 2015 - esp8266 progmem support + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Arduino.h" +#include "WString.h" +#include "stdlib_noniso.h" +#include "esp32-hal-log.h" + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) { + init(); + if (cstr) { + copy(cstr, strlen(cstr)); + } +} + +String::String(const char *cstr, unsigned int length) { + init(); + if (cstr) { + copy(cstr, length); + } +} + +String::String(const String &value) { + init(); + *this = value; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) { + init(); + move(rval); +} + +String::String(StringSumHelper &&rval) { + init(); + move(rval); +} + +String::String(std::initializer_list list) { + init(); + if (list.size() > 0) { + copy(list.begin(), list.size()); + } +} +#endif + +String::String(char c) { + init(); + char buf[] = {c, '\0'}; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) { + init(); + char buf[1 + 8 * sizeof(unsigned char)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) { + init(); + char buf[2 + 8 * sizeof(int)]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) { + init(); + char buf[1 + 8 * sizeof(unsigned int)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) { + init(); + char buf[2 + 8 * sizeof(long)]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) { + init(); + char buf[1 + 8 * sizeof(unsigned long)]; + ultoa(value, buf, base); + *this = buf; +} + +String::String(float value, unsigned int decimalPlaces) { + init(); + char *buf = (char *)malloc(decimalPlaces + 42); + if (buf) { + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); + free(buf); + } else { + *this = "nan"; + log_e("No enough memory for the operation."); + } +} + +String::String(double value, unsigned int decimalPlaces) { + init(); + char *buf = (char *)malloc(decimalPlaces + 312); + if (buf) { + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); + free(buf); + } else { + *this = "nan"; + log_e("No enough memory for the operation."); + } +} + +String::String(long long value, unsigned char base) { + init(); + char buf[2 + 8 * sizeof(long long)]; + lltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long long value, unsigned char base) { + init(); + char buf[1 + 8 * sizeof(unsigned long long)]; + ulltoa(value, buf, base); + *this = buf; +} + +String::~String() { + invalidate(); +} + +/*********************************************/ +/* Memory Management */ +/*********************************************/ + +inline void String::init(void) { + setSSO(false); + setBuffer(nullptr); + setCapacity(0); + setLen(0); +} + +void String::invalidate(void) { + if (!isSSO() && wbuffer()) { + free(wbuffer()); + } + init(); +} + +bool String::reserve(unsigned int size) { + if (buffer() && capacity() >= size) { + return true; + } + if (changeBuffer(size)) { + if (len() == 0) { + wbuffer()[0] = 0; + } + return true; + } + return false; +} + +bool String::changeBuffer(unsigned int maxStrLen) { + // Can we use SSO here to avoid allocation? + if (maxStrLen < sizeof(sso.buff) - 1) { + if (isSSO() || !buffer()) { + // Already using SSO, nothing to do + size_t oldLen = len(); + setSSO(true); + setLen(oldLen); + } else { // if bufptr && !isSSO() + // Using bufptr, need to shrink into sso.buff + char temp[sizeof(sso.buff)]; + memcpy(temp, buffer(), maxStrLen); + free(wbuffer()); + size_t oldLen = len(); + setSSO(true); + memcpy(wbuffer(), temp, maxStrLen); + setLen(oldLen); + } + return true; + } + // Fallthrough to normal allocator + size_t newSize = (maxStrLen + 16) & (~0xf); + // Make sure we can fit newsize in the buffer + if (newSize > CAPACITY_MAX) { + return false; + } + size_t oldLen = len(); + char *newbuffer = (char *)realloc(isSSO() ? nullptr : wbuffer(), newSize); + if (newbuffer) { + size_t oldSize = capacity() + 1; // include NULL. + if (isSSO()) { + // Copy the SSO buffer into allocated space + memmove(newbuffer, sso.buff, sizeof(sso.buff)); + } + if (newSize > oldSize) { + memset(newbuffer + oldSize, 0, newSize - oldSize); + } + setSSO(false); + setCapacity(newSize - 1); + setBuffer(newbuffer); + setLen(oldLen); // Needed in case of SSO where len() never existed + return true; + } + return false; +} + +/*********************************************/ +/* Copy and Move */ +/*********************************************/ + +String &String::copy(const char *cstr, unsigned int length) { + if (cstr == nullptr || !reserve(length)) { + invalidate(); + return *this; + } + memmove(wbuffer(), cstr, length); + setLen(length); + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) { + if (buffer()) { + if (capacity() >= rhs.len()) { + // Use case: When 'reserve()' was called and the first + // assignment/append is the return value of a function. + if (rhs.len() && rhs.buffer()) { + memmove(wbuffer(), rhs.buffer(), rhs.length()); + } + setLen(rhs.len()); + rhs.invalidate(); + return; + } + if (!isSSO()) { + free(wbuffer()); + setBuffer(nullptr); + } + } + if (rhs.isSSO()) { + setSSO(true); + memmove(sso.buff, rhs.sso.buff, sizeof(sso.buff)); + } else { + setSSO(false); + setBuffer(rhs.wbuffer()); + } + setCapacity(rhs.capacity()); + setLen(rhs.len()); + rhs.init(); +} +#endif + +String &String::operator=(const String &rhs) { + if (this == &rhs) { + return *this; + } + return copy(rhs.buffer(), rhs.len()); +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String &String::operator=(String &&rval) { + if (this != &rval) { + move(rval); + } + return *this; +} + +String &String::operator=(StringSumHelper &&rval) { + if (this != &rval) { + move(rval); + } + return *this; +} +#endif + +String &String::operator=(const char *cstr) { + const uint32_t length = cstr ? strlen(cstr) : 0u; + return copy(cstr, length); +} + +/*********************************************/ +/* concat */ +/*********************************************/ + +bool String::concat(const String &s) { + // Special case if we're concatting ourself (s += s;) since we may end up + // realloc'ing the buffer and moving s.buffer in the method called + if (&s == this) { + if (s.len() == 0) { + return true; + } + if (!s.buffer()) { + return false; + } + unsigned int newlen = 2 * len(); + if (!reserve(newlen)) { + return false; + } + memmove(wbuffer() + len(), buffer(), len()); + setLen(newlen); + return true; + } + return concat(s.buffer(), s.len()); +} + +bool String::concat(const char *cstr, unsigned int length) { + unsigned int newlen = len() + length; + if (!cstr) { + return false; + } + if (length == 0) { + return true; + } + if (!reserve(newlen)) { + return false; + } + if (cstr >= wbuffer() && cstr < wbuffer() + len()) { + // compatible with SSO in ram #6155 (case "x += x.c_str()") + memmove(wbuffer() + len(), cstr, length); + } else { + // compatible with source in flash #6367 + memcpy_P(wbuffer() + len(), cstr, length); + } + setLen(newlen); + return true; +} + +bool String::concat(const char *cstr) { + if (!cstr) { + return false; + } + return concat(cstr, strlen(cstr)); +} + +bool String::concat(char c) { + char buf[] = {c, '\0'}; + return concat(buf, 1); +} + +bool String::concat(unsigned char num) { + char buf[1 + 3 * sizeof(unsigned char)]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(int num) { + char buf[2 + 3 * sizeof(int)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(unsigned int num) { + char buf[1 + 3 * sizeof(unsigned int)]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(long num) { + char buf[2 + 3 * sizeof(long)]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(unsigned long num) { + char buf[1 + 3 * sizeof(unsigned long)]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(long long num) { + char buf[2 + 3 * sizeof(long long)]; + lltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(unsigned long long num) { + char buf[1 + 3 * sizeof(unsigned long long)]; + ulltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +bool String::concat(float num) { + char buf[20]; + char *string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +bool String::concat(double num) { + char buf[20]; + char *string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs.buffer(), rhs.len())) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr) { + StringSumHelper &a = const_cast(lhs); + if (!cstr || !a.concat(cstr, strlen(cstr))) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, char c) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(c)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, int num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, long num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, float num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, double num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, long long num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long long num) { + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) { + a.invalidate(); + } + return a; +} + +/*********************************************/ +/* Comparison */ +/*********************************************/ + +int String::compareTo(const String &s) const { + if (!buffer() || !s.buffer()) { + if (s.buffer() && s.len() > 0) { + return 0 - *(unsigned char *)s.buffer(); + } + if (buffer() && len() > 0) { + return *(unsigned char *)buffer(); + } + return 0; + } + return strcmp(buffer(), s.buffer()); +} + +bool String::equals(const String &s2) const { + return (len() == s2.len() && compareTo(s2) == 0); +} + +bool String::equals(const char *cstr) const { + if (len() == 0) { + return (cstr == NULL || *cstr == 0); + } + if (cstr == NULL) { + return buffer()[0] == 0; + } + return strcmp(buffer(), cstr) == 0; +} + +bool String::operator<(const String &rhs) const { + return compareTo(rhs) < 0; +} + +bool String::operator>(const String &rhs) const { + return compareTo(rhs) > 0; +} + +bool String::operator<=(const String &rhs) const { + return compareTo(rhs) <= 0; +} + +bool String::operator>=(const String &rhs) const { + return compareTo(rhs) >= 0; +} + +bool String::equalsIgnoreCase(const String &s2) const { + if (this == &s2) { + return true; + } + if (len() != s2.len()) { + return false; + } + if (len() == 0) { + return true; + } + const char *p1 = buffer(); + const char *p2 = s2.buffer(); + while (*p1) { + if (tolower(*p1++) != tolower(*p2++)) { + return false; + } + } + return true; +} + +unsigned char String::equalsConstantTime(const String &s2) const { + // To avoid possible time-based attacks present function + // compares given strings in a constant time. + if (len() != s2.len()) { + return 0; + } + //at this point lengths are the same + if (len() == 0) { + return 1; + } + //at this point lengths are the same and non-zero + const char *p1 = buffer(); + const char *p2 = s2.buffer(); + unsigned int equalchars = 0; + unsigned int diffchars = 0; + while (*p1) { + if (*p1 == *p2) { + ++equalchars; + } else { + ++diffchars; + } + ++p1; + ++p2; + } + //the following should force a constant time eval of the condition without a compiler "logical shortcut" + unsigned char equalcond = (equalchars == len()); + unsigned char diffcond = (diffchars == 0); + return (equalcond & diffcond); //bitwise AND +} + +bool String::startsWith(const String &s2) const { + if (len() < s2.len()) { + return false; + } + return startsWith(s2, 0); +} + +bool String::startsWith(const String &s2, unsigned int offset) const { + if (offset > (unsigned)(len() - s2.len()) || !buffer() || !s2.buffer()) { + return false; + } + return strncmp(&buffer()[offset], s2.buffer(), s2.len()) == 0; +} + +bool String::endsWith(const String &s2) const { + if (len() < s2.len() || !buffer() || !s2.buffer()) { + return false; + } + return strcmp(&buffer()[len() - s2.len()], s2.buffer()) == 0; +} + +/*********************************************/ +/* Character Access */ +/*********************************************/ + +char String::charAt(unsigned int loc) const { + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) { + if (loc < len()) { + wbuffer()[loc] = c; + } +} + +char &String::operator[](unsigned int index) { + static char dummy_writable_char; + if (index >= len() || !buffer()) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return wbuffer()[index]; +} + +char String::operator[](unsigned int index) const { + if (index >= len() || !buffer()) { + return 0; + } + return buffer()[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const { + if (!bufsize || !buf) { + return; + } + if (index >= len()) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if (n > len() - index) { + n = len() - index; + } + strncpy((char *)buf, buffer() + index, n); + buf[n] = 0; +} + +/*********************************************/ +/* Search */ +/*********************************************/ + +int String::indexOf(char c) const { + return indexOf(c, 0); +} + +int String::indexOf(char ch, unsigned int fromIndex) const { + if (fromIndex >= len()) { + return -1; + } + const char *temp = strchr(buffer() + fromIndex, ch); + if (temp == NULL) { + return -1; + } + return temp - buffer(); +} + +int String::indexOf(const String &s2) const { + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const { + if (fromIndex >= len()) { + return -1; + } + const char *found = strstr(buffer() + fromIndex, s2.buffer()); + if (found == NULL) { + return -1; + } + return found - buffer(); +} + +int String::lastIndexOf(char theChar) const { + return lastIndexOf(theChar, len() - 1); +} + +int String::lastIndexOf(char ch, unsigned int fromIndex) const { + if (fromIndex >= len()) { + return -1; + } + char tempchar = buffer()[fromIndex + 1]; + wbuffer()[fromIndex + 1] = '\0'; + char *temp = strrchr(wbuffer(), ch); + wbuffer()[fromIndex + 1] = tempchar; + if (temp == NULL) { + return -1; + } + const int rv = temp - buffer(); + if (rv >= len()) { + return -1; + } + return rv; +} + +int String::lastIndexOf(const String &s2) const { + return lastIndexOf(s2, len() - s2.len()); +} + +int String::lastIndexOf(const String &s2, unsigned int fromIndex) const { + if (s2.len() == 0 || len() == 0 || s2.len() > len()) { + return -1; + } + if (fromIndex >= len()) { + fromIndex = len() - 1; + } + int found = -1; + for (char *p = wbuffer(); p <= wbuffer() + fromIndex; p++) { + p = strstr(p, s2.buffer()); + if (!p) { + break; + } + if ((unsigned int)(p - wbuffer()) <= fromIndex) { + found = p - buffer(); + } + } + return found; +} + +String String::substring(unsigned int left, unsigned int right) const { + if (left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if (left >= len()) { + return out; + } + if (right > len()) { + right = len(); + } + out.copy(buffer() + left, right - left); + return out; +} + +/*********************************************/ +/* Modification */ +/*********************************************/ + +void String::replace(char find, char replace) { + if (!buffer()) { + return; + } + for (char *p = wbuffer(); *p; p++) { + if (*p == find) { + *p = replace; + } + } +} + +void String::replace(const String &find, const String &replace) { + if (len() == 0 || find.len() == 0) { + return; + } + int diff = replace.len() - find.len(); + char *readFrom = wbuffer(); + char *foundAt; + if (diff == 0) { + while ((foundAt = strstr(readFrom, find.buffer())) != NULL) { + memmove(foundAt, replace.buffer(), replace.len()); + readFrom = foundAt + replace.len(); + } + } else if (diff < 0) { + char *writeTo = wbuffer(); + unsigned int l = len(); + while ((foundAt = strstr(readFrom, find.buffer())) != NULL) { + unsigned int n = foundAt - readFrom; + memmove(writeTo, readFrom, n); + writeTo += n; + memmove(writeTo, replace.buffer(), replace.len()); + writeTo += replace.len(); + readFrom = foundAt + find.len(); + l += diff; + } + memmove(writeTo, readFrom, strlen(readFrom) + 1); + setLen(l); + } else { + unsigned int size = len(); // compute size needed for result + while ((foundAt = strstr(readFrom, find.buffer())) != NULL) { + readFrom = foundAt + find.len(); + size += diff; + } + if (size == len()) { + return; + } + if (size > capacity() && !changeBuffer(size)) { + log_w("String.Replace() Insufficient space to replace string"); + return; + } + int index = len() - 1; + while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) { + readFrom = wbuffer() + index + find.len(); + memmove(readFrom + diff, readFrom, len() - (readFrom - buffer())); + int newLen = len() + diff; + memmove(wbuffer() + index, replace.buffer(), replace.len()); + setLen(newLen); + wbuffer()[newLen] = 0; + index--; + } + } +} + +void String::remove(unsigned int index) { + // Pass the biggest integer as the count. The remove method + // below will take care of truncating it at the end of the + // string. + remove(index, (unsigned int)-1); +} + +void String::remove(unsigned int index, unsigned int count) { + if (index >= len()) { + return; + } + if (count <= 0) { + return; + } + if (count > len() - index) { + count = len() - index; + } + char *writeTo = wbuffer() + index; + unsigned int newlen = len() - count; + memmove(writeTo, wbuffer() + index + count, newlen - index); + setLen(newlen); + wbuffer()[newlen] = 0; +} + +void String::toLowerCase(void) { + if (!buffer()) { + return; + } + for (char *p = wbuffer(); *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) { + if (!buffer()) { + return; + } + for (char *p = wbuffer(); *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) { + if (!buffer() || len() == 0) { + return; + } + char *begin = wbuffer(); + while (isspace(*begin)) { + begin++; + } + char *end = wbuffer() + len() - 1; + while (isspace(*end) && end >= begin) { + end--; + } + unsigned int newlen = end + 1 - begin; + if (begin > buffer()) { + memmove(wbuffer(), begin, newlen); + } + setLen(newlen); + wbuffer()[newlen] = 0; +} + +/*********************************************/ +/* Parsing / Conversion */ +/*********************************************/ + +long String::toInt(void) const { + if (buffer()) { + return atol(buffer()); + } + return 0; +} + +float String::toFloat(void) const { + if (buffer()) { + return static_cast(atof(buffer())); + } + return 0; +} + +double String::toDouble(void) const { + if (buffer()) { + return atof(buffer()); + } + return 0.0; +} + +// global empty string to allow returning const String& with nothing + +const String emptyString; diff --git a/cores/esp32/WString.h b/cores/esp32/WString.h new file mode 100644 index 0000000..d9cc785 --- /dev/null +++ b/cores/esp32/WString.h @@ -0,0 +1,426 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include + +#include +#include +#include +#include +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +#include +#endif + +// A pure abstract class forward used as a means to proide a unique pointer type +// but really is never defined. +class __FlashStringHelper; +#define FPSTR(str_pointer) (reinterpret_cast(str_pointer)) +#define F(string_literal) (FPSTR(PSTR(string_literal))) + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// The string class +class String { + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const {} + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const char *cstr, unsigned int length); +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(const uint8_t *cstr, unsigned int length) : String(reinterpret_cast(cstr), length) {} + String(std::initializer_list list); +#endif + String(const String &str); + String(const __FlashStringHelper *str) : String(reinterpret_cast(str)) {} +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); +#endif + explicit String(char c); + explicit String(unsigned char, unsigned char base = 10); + explicit String(int, unsigned char base = 10); + explicit String(unsigned int, unsigned char base = 10); + explicit String(long, unsigned char base = 10); + explicit String(unsigned long, unsigned char base = 10); + explicit String(float, unsigned int decimalPlaces = 2); + explicit String(double, unsigned int decimalPlaces = 2); + explicit String(long long, unsigned char base = 10); + explicit String(unsigned long long, unsigned char base = 10); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + bool reserve(unsigned int size); + inline unsigned int length(void) const { + if (buffer()) { + return len(); + } else { + return 0; + } + } + inline void clear(void) { + setLen(0); + } + inline bool isEmpty(void) const { + return length() == 0; + } + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String &operator=(const String &rhs); + String &operator=(const char *cstr); + String &operator=(const __FlashStringHelper *str) { + return *this = reinterpret_cast(str); + } +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + String &operator=(String &&rval); + String &operator=(StringSumHelper &&rval); +#endif + + // concatenate (works w/ built-in types, same as assignment) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsuccessful. + bool concat(const String &str); + bool concat(const char *cstr); + bool concat(const char *cstr, unsigned int length); + bool concat(const uint8_t *cstr, unsigned int length) { + return concat(reinterpret_cast(cstr), length); + } + bool concat(char c); + bool concat(unsigned char c); + bool concat(int num); + bool concat(unsigned int num); + bool concat(long num); + bool concat(unsigned long num); + bool concat(float num); + bool concat(double num); + bool concat(long long num); + bool concat(unsigned long long num); + bool concat(const __FlashStringHelper *str) { + return concat(reinterpret_cast(str)); + } + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signaled in any way) + String &operator+=(const String &rhs) { + concat(rhs); + return (*this); + } + String &operator+=(const char *cstr) { + concat(cstr); + return (*this); + } + String &operator+=(char c) { + concat(c); + return (*this); + } + String &operator+=(unsigned char num) { + concat(num); + return (*this); + } + String &operator+=(int num) { + concat(num); + return (*this); + } + String &operator+=(unsigned int num) { + concat(num); + return (*this); + } + String &operator+=(long num) { + concat(num); + return (*this); + } + String &operator+=(unsigned long num) { + concat(num); + return (*this); + } + String &operator+=(float num) { + concat(num); + return (*this); + } + String &operator+=(double num) { + concat(num); + return (*this); + } + String &operator+=(long long num) { + concat(num); + return (*this); + } + String &operator+=(unsigned long long num) { + concat(num); + return (*this); + } + String &operator+=(const __FlashStringHelper *str) { + return *this += reinterpret_cast(str); + } + + friend StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper &operator+(const StringSumHelper &lhs, char c); + friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, int num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, long num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, float num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, double num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, long long num); + friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long long num); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const { + return buffer() ? &String::StringIfHelper : 0; + } + int compareTo(const String &s) const; + bool equals(const String &s) const; + bool equals(const char *cstr) const; + bool operator==(const String &rhs) const { + return equals(rhs); + } + bool operator==(const char *cstr) const { + return equals(cstr); + } + bool operator!=(const String &rhs) const { + return !equals(rhs); + } + bool operator!=(const char *cstr) const { + return !equals(cstr); + } + bool operator<(const String &rhs) const; + bool operator>(const String &rhs) const; + bool operator<=(const String &rhs) const; + bool operator>=(const String &rhs) const; + bool equalsIgnoreCase(const String &s) const; + unsigned char equalsConstantTime(const String &s) const; + bool startsWith(const String &prefix) const; + bool startsWith(const char *prefix) const { + return this->startsWith(String(prefix)); + } + bool startsWith(const __FlashStringHelper *prefix) const { + return this->startsWith(reinterpret_cast(prefix)); + } + bool startsWith(const String &prefix, unsigned int offset) const; + bool endsWith(const String &suffix) const; + bool endsWith(const char *suffix) const { + return this->endsWith(String(suffix)); + } + bool endsWith(const __FlashStringHelper *suffix) const { + return this->endsWith(reinterpret_cast(suffix)); + } + + // character access + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator[](unsigned int index) const; + char &operator[](unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const { + getBytes((unsigned char *)buf, bufsize, index); + } + const char *c_str() const { + return buffer(); + } + char *begin() { + return wbuffer(); + } + char *end() { + return wbuffer() + length(); + } + const char *begin() const { + return c_str(); + } + const char *end() const { + return c_str() + length(); + } + + // search + int indexOf(char ch) const; + int indexOf(char ch, unsigned int fromIndex) const; + int indexOf(const String &str) const; + int indexOf(const String &str, unsigned int fromIndex) const; + int lastIndexOf(char ch) const; + int lastIndexOf(char ch, unsigned int fromIndex) const; + int lastIndexOf(const String &str) const; + int lastIndexOf(const String &str, unsigned int fromIndex) const; + String substring(unsigned int beginIndex) const { + return substring(beginIndex, len()); + } + String substring(unsigned int beginIndex, unsigned int endIndex) const; + + // modification + void replace(char find, char replace); + void replace(const String &find, const String &replace); + void replace(const char *find, const String &replace) { + this->replace(String(find), replace); + } + void replace(const __FlashStringHelper *find, const String &replace) { + this->replace(reinterpret_cast(find), replace); + } + void replace(const char *find, const char *replace) { + this->replace(String(find), String(replace)); + } + void replace(const __FlashStringHelper *find, const char *replace) { + this->replace(reinterpret_cast(find), String(replace)); + } + void replace(const __FlashStringHelper *find, const __FlashStringHelper *replace) { + this->replace(reinterpret_cast(find), reinterpret_cast(replace)); + } + void remove(unsigned int index); + void remove(unsigned int index, unsigned int count); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + float toFloat(void) const; + double toDouble(void) const; + +protected: + // Contains the string info when we're not in SSO mode + struct _ptr { + char *buff; + uint32_t cap; + uint32_t len; + }; + // This allows strings up up to 11 (10 + \0 termination) without any extra space. + enum { + SSOSIZE = sizeof(struct _ptr) + 4 - 1 + }; // Characters to allocate space for SSO, must be 12 or more + struct _sso { + char buff[SSOSIZE]; + unsigned char len : 7; // Ensure only one byte is allocated by GCC for the bitfields + unsigned char isSSO : 1; + } __attribute__((packed)); // Ensure that GCC doesn't expand the flag byte to a 32-bit word for alignment issues +#ifdef BOARD_HAS_PSRAM + enum { + CAPACITY_MAX = 3145728 + }; +#else + enum { + CAPACITY_MAX = 65535 + }; +#endif + union { + struct _ptr ptr; + struct _sso sso; + }; + // Accessor functions + inline bool isSSO() const { + return sso.isSSO; + } + inline unsigned int len() const { + return isSSO() ? sso.len : ptr.len; + } + inline unsigned int capacity() const { + return isSSO() ? (unsigned int)SSOSIZE - 1 : ptr.cap; + } // Size of max string not including terminal NUL + inline void setSSO(bool set) { + sso.isSSO = set; + } + inline void setLen(int len) { + if (isSSO()) { + sso.len = len; + sso.buff[len] = 0; + } else { + ptr.len = len; + if (ptr.buff) { + ptr.buff[len] = 0; + } + } + } + inline void setCapacity(int cap) { + if (!isSSO()) { + ptr.cap = cap; + } + } + inline void setBuffer(char *buff) { + if (!isSSO()) { + ptr.buff = buff; + } + } + // Buffer accessor functions + inline const char *buffer() const { + return reinterpret_cast(isSSO() ? sso.buff : ptr.buff); + } + inline char *wbuffer() const { + return isSSO() ? const_cast(sso.buff) : ptr.buff; + } // Writable version of buffer + +protected: + void init(void); + void invalidate(void); + bool changeBuffer(unsigned int maxStrLen); + + // copy and move + String ©(const char *cstr, unsigned int length); + String ©(const __FlashStringHelper *pstr, unsigned int length) { + return copy(reinterpret_cast(pstr), length); + } +#ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); +#endif +}; + +class StringSumHelper : public String { +public: + StringSumHelper(const String &s) : String(s) {} + StringSumHelper(const char *p) : String(p) {} + StringSumHelper(char c) : String(c) {} + StringSumHelper(unsigned char num) : String(num) {} + StringSumHelper(int num) : String(num) {} + StringSumHelper(unsigned int num) : String(num) {} + StringSumHelper(long num) : String(num) {} + StringSumHelper(unsigned long num) : String(num) {} + StringSumHelper(float num) : String(num) {} + StringSumHelper(double num) : String(num) {} + StringSumHelper(long long num) : String(num) {} + StringSumHelper(unsigned long long num) : String(num) {} +}; + +inline StringSumHelper &operator+(const StringSumHelper &lhs, const __FlashStringHelper *rhs) { + return lhs + reinterpret_cast(rhs); +} + +extern const String emptyString; + +#endif // __cplusplus +#endif // String_class_h diff --git a/cores/esp32/apps/sntp/sntp.h b/cores/esp32/apps/sntp/sntp.h new file mode 100644 index 0000000..8a940f8 --- /dev/null +++ b/cores/esp32/apps/sntp/sntp.h @@ -0,0 +1 @@ +#include "lwip/apps/sntp.h" diff --git a/cores/esp32/base64.cpp b/cores/esp32/base64.cpp new file mode 100644 index 0000000..8fa9617 --- /dev/null +++ b/cores/esp32/base64.cpp @@ -0,0 +1,61 @@ +/** + * base64.cpp + * + * Created on: 09.12.2015 + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the ESP31B core for Arduino. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "Arduino.h" +extern "C" { +#include "libb64/cdecode.h" +#include "libb64/cencode.h" +} +#include "base64.h" + +/** + * convert input data to base64 + * @param data const uint8_t * + * @param length size_t + * @return String + */ +String base64::encode(const uint8_t *data, size_t length) { + size_t size = base64_encode_expected_len(length) + 1; + char *buffer = (char *)malloc(size); + if (buffer) { + base64_encodestate _state; + base64_init_encodestate(&_state); + int len = base64_encode_block((const char *)&data[0], length, &buffer[0], &_state); + len = base64_encode_blockend((buffer + len), &_state); + + String base64 = String(buffer); + free(buffer); + return base64; + } + return String("-FAIL-"); +} + +/** + * convert input data to base64 + * @param text const String& + * @return String + */ +String base64::encode(const String &text) { + return base64::encode((uint8_t *)text.c_str(), text.length()); +} diff --git a/cores/esp32/base64.h b/cores/esp32/base64.h new file mode 100644 index 0000000..63a0e21 --- /dev/null +++ b/cores/esp32/base64.h @@ -0,0 +1,12 @@ +#ifndef CORE_BASE64_H_ +#define CORE_BASE64_H_ + +class base64 { +public: + static String encode(const uint8_t *data, size_t length); + static String encode(const String &text); + +private: +}; + +#endif /* CORE_BASE64_H_ */ diff --git a/cores/esp32/binary.h b/cores/esp32/binary.h new file mode 100644 index 0000000..4a8e4e7 --- /dev/null +++ b/cores/esp32/binary.h @@ -0,0 +1,552 @@ +/* + binary.h - Definitions for binary constants + Deprecated -- use 0b binary literals instead + Copyright (c) 2006 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Binary_h +#define Binary_h + +/* If supported, 0b binary literals are preferable to these constants. + * In that case, warn the user about these being deprecated (if possible). */ +#if __cplusplus >= 201402L +/* C++14 introduces binary literals; C++11 introduces [[deprecated()]] */ +#define DEPRECATED(x) [[deprecated("use " #x " instead")]] +#elif __GNUC__ >= 6 +/* GCC 4.3 supports binary literals; GCC 6 supports __deprecated__ on enums*/ +#define DEPRECATED(x) __attribute__((__deprecated__("use " #x " instead"))) +#else +/* binary literals not supported, or "deprecated" warning not displayable */ +#define DEPRECATED(x) +#endif + +enum { + B0 DEPRECATED(0b0) = 0, + B00 DEPRECATED(0b00) = 0, + B000 DEPRECATED(0b000) = 0, + B0000 DEPRECATED(0b0000) = 0, + B00000 DEPRECATED(0b00000) = 0, + B000000 DEPRECATED(0b000000) = 0, + B0000000 DEPRECATED(0b0000000) = 0, + B00000000 DEPRECATED(0b00000000) = 0, + B1 DEPRECATED(0b1) = 1, + B01 DEPRECATED(0b01) = 1, + B001 DEPRECATED(0b001) = 1, + B0001 DEPRECATED(0b0001) = 1, + B00001 DEPRECATED(0b00001) = 1, + B000001 DEPRECATED(0b000001) = 1, + B0000001 DEPRECATED(0b0000001) = 1, + B00000001 DEPRECATED(0b00000001) = 1, + B10 DEPRECATED(0b10) = 2, + B010 DEPRECATED(0b010) = 2, + B0010 DEPRECATED(0b0010) = 2, + B00010 DEPRECATED(0b00010) = 2, + B000010 DEPRECATED(0b000010) = 2, + B0000010 DEPRECATED(0b0000010) = 2, + B00000010 DEPRECATED(0b00000010) = 2, + B11 DEPRECATED(0b11) = 3, + B011 DEPRECATED(0b011) = 3, + B0011 DEPRECATED(0b0011) = 3, + B00011 DEPRECATED(0b00011) = 3, + B000011 DEPRECATED(0b000011) = 3, + B0000011 DEPRECATED(0b0000011) = 3, + B00000011 DEPRECATED(0b00000011) = 3, + B100 DEPRECATED(0b100) = 4, + B0100 DEPRECATED(0b0100) = 4, + B00100 DEPRECATED(0b00100) = 4, + B000100 DEPRECATED(0b000100) = 4, + B0000100 DEPRECATED(0b0000100) = 4, + B00000100 DEPRECATED(0b00000100) = 4, + B101 DEPRECATED(0b101) = 5, + B0101 DEPRECATED(0b0101) = 5, + B00101 DEPRECATED(0b00101) = 5, + B000101 DEPRECATED(0b000101) = 5, + B0000101 DEPRECATED(0b0000101) = 5, + B00000101 DEPRECATED(0b00000101) = 5, + B110 DEPRECATED(0b110) = 6, + B0110 DEPRECATED(0b0110) = 6, + B00110 DEPRECATED(0b00110) = 6, + B000110 DEPRECATED(0b000110) = 6, + B0000110 DEPRECATED(0b0000110) = 6, + B00000110 DEPRECATED(0b00000110) = 6, + B111 DEPRECATED(0b111) = 7, + B0111 DEPRECATED(0b0111) = 7, + B00111 DEPRECATED(0b00111) = 7, + B000111 DEPRECATED(0b000111) = 7, + B0000111 DEPRECATED(0b0000111) = 7, + B00000111 DEPRECATED(0b00000111) = 7, + B1000 DEPRECATED(0b1000) = 8, + B01000 DEPRECATED(0b01000) = 8, + B001000 DEPRECATED(0b001000) = 8, + B0001000 DEPRECATED(0b0001000) = 8, + B00001000 DEPRECATED(0b00001000) = 8, + B1001 DEPRECATED(0b1001) = 9, + B01001 DEPRECATED(0b01001) = 9, + B001001 DEPRECATED(0b001001) = 9, + B0001001 DEPRECATED(0b0001001) = 9, + B00001001 DEPRECATED(0b00001001) = 9, + B1010 DEPRECATED(0b1010) = 10, + B01010 DEPRECATED(0b01010) = 10, + B001010 DEPRECATED(0b001010) = 10, + B0001010 DEPRECATED(0b0001010) = 10, + B00001010 DEPRECATED(0b00001010) = 10, + B1011 DEPRECATED(0b1011) = 11, + B01011 DEPRECATED(0b01011) = 11, + B001011 DEPRECATED(0b001011) = 11, + B0001011 DEPRECATED(0b0001011) = 11, + B00001011 DEPRECATED(0b00001011) = 11, + B1100 DEPRECATED(0b1100) = 12, + B01100 DEPRECATED(0b01100) = 12, + B001100 DEPRECATED(0b001100) = 12, + B0001100 DEPRECATED(0b0001100) = 12, + B00001100 DEPRECATED(0b00001100) = 12, + B1101 DEPRECATED(0b1101) = 13, + B01101 DEPRECATED(0b01101) = 13, + B001101 DEPRECATED(0b001101) = 13, + B0001101 DEPRECATED(0b0001101) = 13, + B00001101 DEPRECATED(0b00001101) = 13, + B1110 DEPRECATED(0b1110) = 14, + B01110 DEPRECATED(0b01110) = 14, + B001110 DEPRECATED(0b001110) = 14, + B0001110 DEPRECATED(0b0001110) = 14, + B00001110 DEPRECATED(0b00001110) = 14, + B1111 DEPRECATED(0b1111) = 15, + B01111 DEPRECATED(0b01111) = 15, + B001111 DEPRECATED(0b001111) = 15, + B0001111 DEPRECATED(0b0001111) = 15, + B00001111 DEPRECATED(0b00001111) = 15, + B10000 DEPRECATED(0b10000) = 16, + B010000 DEPRECATED(0b010000) = 16, + B0010000 DEPRECATED(0b0010000) = 16, + B00010000 DEPRECATED(0b00010000) = 16, + B10001 DEPRECATED(0b10001) = 17, + B010001 DEPRECATED(0b010001) = 17, + B0010001 DEPRECATED(0b0010001) = 17, + B00010001 DEPRECATED(0b00010001) = 17, + B10010 DEPRECATED(0b10010) = 18, + B010010 DEPRECATED(0b010010) = 18, + B0010010 DEPRECATED(0b0010010) = 18, + B00010010 DEPRECATED(0b00010010) = 18, + B10011 DEPRECATED(0b10011) = 19, + B010011 DEPRECATED(0b010011) = 19, + B0010011 DEPRECATED(0b0010011) = 19, + B00010011 DEPRECATED(0b00010011) = 19, + B10100 DEPRECATED(0b10100) = 20, + B010100 DEPRECATED(0b010100) = 20, + B0010100 DEPRECATED(0b0010100) = 20, + B00010100 DEPRECATED(0b00010100) = 20, + B10101 DEPRECATED(0b10101) = 21, + B010101 DEPRECATED(0b010101) = 21, + B0010101 DEPRECATED(0b0010101) = 21, + B00010101 DEPRECATED(0b00010101) = 21, + B10110 DEPRECATED(0b10110) = 22, + B010110 DEPRECATED(0b010110) = 22, + B0010110 DEPRECATED(0b0010110) = 22, + B00010110 DEPRECATED(0b00010110) = 22, + B10111 DEPRECATED(0b10111) = 23, + B010111 DEPRECATED(0b010111) = 23, + B0010111 DEPRECATED(0b0010111) = 23, + B00010111 DEPRECATED(0b00010111) = 23, + B11000 DEPRECATED(0b11000) = 24, + B011000 DEPRECATED(0b011000) = 24, + B0011000 DEPRECATED(0b0011000) = 24, + B00011000 DEPRECATED(0b00011000) = 24, + B11001 DEPRECATED(0b11001) = 25, + B011001 DEPRECATED(0b011001) = 25, + B0011001 DEPRECATED(0b0011001) = 25, + B00011001 DEPRECATED(0b00011001) = 25, + B11010 DEPRECATED(0b11010) = 26, + B011010 DEPRECATED(0b011010) = 26, + B0011010 DEPRECATED(0b0011010) = 26, + B00011010 DEPRECATED(0b00011010) = 26, + B11011 DEPRECATED(0b11011) = 27, + B011011 DEPRECATED(0b011011) = 27, + B0011011 DEPRECATED(0b0011011) = 27, + B00011011 DEPRECATED(0b00011011) = 27, + B11100 DEPRECATED(0b11100) = 28, + B011100 DEPRECATED(0b011100) = 28, + B0011100 DEPRECATED(0b0011100) = 28, + B00011100 DEPRECATED(0b00011100) = 28, + B11101 DEPRECATED(0b11101) = 29, + B011101 DEPRECATED(0b011101) = 29, + B0011101 DEPRECATED(0b0011101) = 29, + B00011101 DEPRECATED(0b00011101) = 29, + B11110 DEPRECATED(0b11110) = 30, + B011110 DEPRECATED(0b011110) = 30, + B0011110 DEPRECATED(0b0011110) = 30, + B00011110 DEPRECATED(0b00011110) = 30, + B11111 DEPRECATED(0b11111) = 31, + B011111 DEPRECATED(0b011111) = 31, + B0011111 DEPRECATED(0b0011111) = 31, + B00011111 DEPRECATED(0b00011111) = 31, + B100000 DEPRECATED(0b100000) = 32, + B0100000 DEPRECATED(0b0100000) = 32, + B00100000 DEPRECATED(0b00100000) = 32, + B100001 DEPRECATED(0b100001) = 33, + B0100001 DEPRECATED(0b0100001) = 33, + B00100001 DEPRECATED(0b00100001) = 33, + B100010 DEPRECATED(0b100010) = 34, + B0100010 DEPRECATED(0b0100010) = 34, + B00100010 DEPRECATED(0b00100010) = 34, + B100011 DEPRECATED(0b100011) = 35, + B0100011 DEPRECATED(0b0100011) = 35, + B00100011 DEPRECATED(0b00100011) = 35, + B100100 DEPRECATED(0b100100) = 36, + B0100100 DEPRECATED(0b0100100) = 36, + B00100100 DEPRECATED(0b00100100) = 36, + B100101 DEPRECATED(0b100101) = 37, + B0100101 DEPRECATED(0b0100101) = 37, + B00100101 DEPRECATED(0b00100101) = 37, + B100110 DEPRECATED(0b100110) = 38, + B0100110 DEPRECATED(0b0100110) = 38, + B00100110 DEPRECATED(0b00100110) = 38, + B100111 DEPRECATED(0b100111) = 39, + B0100111 DEPRECATED(0b0100111) = 39, + B00100111 DEPRECATED(0b00100111) = 39, + B101000 DEPRECATED(0b101000) = 40, + B0101000 DEPRECATED(0b0101000) = 40, + B00101000 DEPRECATED(0b00101000) = 40, + B101001 DEPRECATED(0b101001) = 41, + B0101001 DEPRECATED(0b0101001) = 41, + B00101001 DEPRECATED(0b00101001) = 41, + B101010 DEPRECATED(0b101010) = 42, + B0101010 DEPRECATED(0b0101010) = 42, + B00101010 DEPRECATED(0b00101010) = 42, + B101011 DEPRECATED(0b101011) = 43, + B0101011 DEPRECATED(0b0101011) = 43, + B00101011 DEPRECATED(0b00101011) = 43, + B101100 DEPRECATED(0b101100) = 44, + B0101100 DEPRECATED(0b0101100) = 44, + B00101100 DEPRECATED(0b00101100) = 44, + B101101 DEPRECATED(0b101101) = 45, + B0101101 DEPRECATED(0b0101101) = 45, + B00101101 DEPRECATED(0b00101101) = 45, + B101110 DEPRECATED(0b101110) = 46, + B0101110 DEPRECATED(0b0101110) = 46, + B00101110 DEPRECATED(0b00101110) = 46, + B101111 DEPRECATED(0b101111) = 47, + B0101111 DEPRECATED(0b0101111) = 47, + B00101111 DEPRECATED(0b00101111) = 47, + B110000 DEPRECATED(0b110000) = 48, + B0110000 DEPRECATED(0b0110000) = 48, + B00110000 DEPRECATED(0b00110000) = 48, + B110001 DEPRECATED(0b110001) = 49, + B0110001 DEPRECATED(0b0110001) = 49, + B00110001 DEPRECATED(0b00110001) = 49, + B110010 DEPRECATED(0b110010) = 50, + B0110010 DEPRECATED(0b0110010) = 50, + B00110010 DEPRECATED(0b00110010) = 50, + B110011 DEPRECATED(0b110011) = 51, + B0110011 DEPRECATED(0b0110011) = 51, + B00110011 DEPRECATED(0b00110011) = 51, + B110100 DEPRECATED(0b110100) = 52, + B0110100 DEPRECATED(0b0110100) = 52, + B00110100 DEPRECATED(0b00110100) = 52, + B110101 DEPRECATED(0b110101) = 53, + B0110101 DEPRECATED(0b0110101) = 53, + B00110101 DEPRECATED(0b00110101) = 53, + B110110 DEPRECATED(0b110110) = 54, + B0110110 DEPRECATED(0b0110110) = 54, + B00110110 DEPRECATED(0b00110110) = 54, + B110111 DEPRECATED(0b110111) = 55, + B0110111 DEPRECATED(0b0110111) = 55, + B00110111 DEPRECATED(0b00110111) = 55, + B111000 DEPRECATED(0b111000) = 56, + B0111000 DEPRECATED(0b0111000) = 56, + B00111000 DEPRECATED(0b00111000) = 56, + B111001 DEPRECATED(0b111001) = 57, + B0111001 DEPRECATED(0b0111001) = 57, + B00111001 DEPRECATED(0b00111001) = 57, + B111010 DEPRECATED(0b111010) = 58, + B0111010 DEPRECATED(0b0111010) = 58, + B00111010 DEPRECATED(0b00111010) = 58, + B111011 DEPRECATED(0b111011) = 59, + B0111011 DEPRECATED(0b0111011) = 59, + B00111011 DEPRECATED(0b00111011) = 59, + B111100 DEPRECATED(0b111100) = 60, + B0111100 DEPRECATED(0b0111100) = 60, + B00111100 DEPRECATED(0b00111100) = 60, + B111101 DEPRECATED(0b111101) = 61, + B0111101 DEPRECATED(0b0111101) = 61, + B00111101 DEPRECATED(0b00111101) = 61, + B111110 DEPRECATED(0b111110) = 62, + B0111110 DEPRECATED(0b0111110) = 62, + B00111110 DEPRECATED(0b00111110) = 62, + B111111 DEPRECATED(0b111111) = 63, + B0111111 DEPRECATED(0b0111111) = 63, + B00111111 DEPRECATED(0b00111111) = 63, + B1000000 DEPRECATED(0b1000000) = 64, + B01000000 DEPRECATED(0b01000000) = 64, + B1000001 DEPRECATED(0b1000001) = 65, + B01000001 DEPRECATED(0b01000001) = 65, + B1000010 DEPRECATED(0b1000010) = 66, + B01000010 DEPRECATED(0b01000010) = 66, + B1000011 DEPRECATED(0b1000011) = 67, + B01000011 DEPRECATED(0b01000011) = 67, + B1000100 DEPRECATED(0b1000100) = 68, + B01000100 DEPRECATED(0b01000100) = 68, + B1000101 DEPRECATED(0b1000101) = 69, + B01000101 DEPRECATED(0b01000101) = 69, + B1000110 DEPRECATED(0b1000110) = 70, + B01000110 DEPRECATED(0b01000110) = 70, + B1000111 DEPRECATED(0b1000111) = 71, + B01000111 DEPRECATED(0b01000111) = 71, + B1001000 DEPRECATED(0b1001000) = 72, + B01001000 DEPRECATED(0b01001000) = 72, + B1001001 DEPRECATED(0b1001001) = 73, + B01001001 DEPRECATED(0b01001001) = 73, + B1001010 DEPRECATED(0b1001010) = 74, + B01001010 DEPRECATED(0b01001010) = 74, + B1001011 DEPRECATED(0b1001011) = 75, + B01001011 DEPRECATED(0b01001011) = 75, + B1001100 DEPRECATED(0b1001100) = 76, + B01001100 DEPRECATED(0b01001100) = 76, + B1001101 DEPRECATED(0b1001101) = 77, + B01001101 DEPRECATED(0b01001101) = 77, + B1001110 DEPRECATED(0b1001110) = 78, + B01001110 DEPRECATED(0b01001110) = 78, + B1001111 DEPRECATED(0b1001111) = 79, + B01001111 DEPRECATED(0b01001111) = 79, + B1010000 DEPRECATED(0b1010000) = 80, + B01010000 DEPRECATED(0b01010000) = 80, + B1010001 DEPRECATED(0b1010001) = 81, + B01010001 DEPRECATED(0b01010001) = 81, + B1010010 DEPRECATED(0b1010010) = 82, + B01010010 DEPRECATED(0b01010010) = 82, + B1010011 DEPRECATED(0b1010011) = 83, + B01010011 DEPRECATED(0b01010011) = 83, + B1010100 DEPRECATED(0b1010100) = 84, + B01010100 DEPRECATED(0b01010100) = 84, + B1010101 DEPRECATED(0b1010101) = 85, + B01010101 DEPRECATED(0b01010101) = 85, + B1010110 DEPRECATED(0b1010110) = 86, + B01010110 DEPRECATED(0b01010110) = 86, + B1010111 DEPRECATED(0b1010111) = 87, + B01010111 DEPRECATED(0b01010111) = 87, + B1011000 DEPRECATED(0b1011000) = 88, + B01011000 DEPRECATED(0b01011000) = 88, + B1011001 DEPRECATED(0b1011001) = 89, + B01011001 DEPRECATED(0b01011001) = 89, + B1011010 DEPRECATED(0b1011010) = 90, + B01011010 DEPRECATED(0b01011010) = 90, + B1011011 DEPRECATED(0b1011011) = 91, + B01011011 DEPRECATED(0b01011011) = 91, + B1011100 DEPRECATED(0b1011100) = 92, + B01011100 DEPRECATED(0b01011100) = 92, + B1011101 DEPRECATED(0b1011101) = 93, + B01011101 DEPRECATED(0b01011101) = 93, + B1011110 DEPRECATED(0b1011110) = 94, + B01011110 DEPRECATED(0b01011110) = 94, + B1011111 DEPRECATED(0b1011111) = 95, + B01011111 DEPRECATED(0b01011111) = 95, + B1100000 DEPRECATED(0b1100000) = 96, + B01100000 DEPRECATED(0b01100000) = 96, + B1100001 DEPRECATED(0b1100001) = 97, + B01100001 DEPRECATED(0b01100001) = 97, + B1100010 DEPRECATED(0b1100010) = 98, + B01100010 DEPRECATED(0b01100010) = 98, + B1100011 DEPRECATED(0b1100011) = 99, + B01100011 DEPRECATED(0b01100011) = 99, + B1100100 DEPRECATED(0b1100100) = 100, + B01100100 DEPRECATED(0b01100100) = 100, + B1100101 DEPRECATED(0b1100101) = 101, + B01100101 DEPRECATED(0b01100101) = 101, + B1100110 DEPRECATED(0b1100110) = 102, + B01100110 DEPRECATED(0b01100110) = 102, + B1100111 DEPRECATED(0b1100111) = 103, + B01100111 DEPRECATED(0b01100111) = 103, + B1101000 DEPRECATED(0b1101000) = 104, + B01101000 DEPRECATED(0b01101000) = 104, + B1101001 DEPRECATED(0b1101001) = 105, + B01101001 DEPRECATED(0b01101001) = 105, + B1101010 DEPRECATED(0b1101010) = 106, + B01101010 DEPRECATED(0b01101010) = 106, + B1101011 DEPRECATED(0b1101011) = 107, + B01101011 DEPRECATED(0b01101011) = 107, + B1101100 DEPRECATED(0b1101100) = 108, + B01101100 DEPRECATED(0b01101100) = 108, + B1101101 DEPRECATED(0b1101101) = 109, + B01101101 DEPRECATED(0b01101101) = 109, + B1101110 DEPRECATED(0b1101110) = 110, + B01101110 DEPRECATED(0b01101110) = 110, + B1101111 DEPRECATED(0b1101111) = 111, + B01101111 DEPRECATED(0b01101111) = 111, + B1110000 DEPRECATED(0b1110000) = 112, + B01110000 DEPRECATED(0b01110000) = 112, + B1110001 DEPRECATED(0b1110001) = 113, + B01110001 DEPRECATED(0b01110001) = 113, + B1110010 DEPRECATED(0b1110010) = 114, + B01110010 DEPRECATED(0b01110010) = 114, + B1110011 DEPRECATED(0b1110011) = 115, + B01110011 DEPRECATED(0b01110011) = 115, + B1110100 DEPRECATED(0b1110100) = 116, + B01110100 DEPRECATED(0b01110100) = 116, + B1110101 DEPRECATED(0b1110101) = 117, + B01110101 DEPRECATED(0b01110101) = 117, + B1110110 DEPRECATED(0b1110110) = 118, + B01110110 DEPRECATED(0b01110110) = 118, + B1110111 DEPRECATED(0b1110111) = 119, + B01110111 DEPRECATED(0b01110111) = 119, + B1111000 DEPRECATED(0b1111000) = 120, + B01111000 DEPRECATED(0b01111000) = 120, + B1111001 DEPRECATED(0b1111001) = 121, + B01111001 DEPRECATED(0b01111001) = 121, + B1111010 DEPRECATED(0b1111010) = 122, + B01111010 DEPRECATED(0b01111010) = 122, + B1111011 DEPRECATED(0b1111011) = 123, + B01111011 DEPRECATED(0b01111011) = 123, + B1111100 DEPRECATED(0b1111100) = 124, + B01111100 DEPRECATED(0b01111100) = 124, + B1111101 DEPRECATED(0b1111101) = 125, + B01111101 DEPRECATED(0b01111101) = 125, + B1111110 DEPRECATED(0b1111110) = 126, + B01111110 DEPRECATED(0b01111110) = 126, + B1111111 DEPRECATED(0b1111111) = 127, + B01111111 DEPRECATED(0b01111111) = 127, + B10000000 DEPRECATED(0b10000000) = 128, + B10000001 DEPRECATED(0b10000001) = 129, + B10000010 DEPRECATED(0b10000010) = 130, + B10000011 DEPRECATED(0b10000011) = 131, + B10000100 DEPRECATED(0b10000100) = 132, + B10000101 DEPRECATED(0b10000101) = 133, + B10000110 DEPRECATED(0b10000110) = 134, + B10000111 DEPRECATED(0b10000111) = 135, + B10001000 DEPRECATED(0b10001000) = 136, + B10001001 DEPRECATED(0b10001001) = 137, + B10001010 DEPRECATED(0b10001010) = 138, + B10001011 DEPRECATED(0b10001011) = 139, + B10001100 DEPRECATED(0b10001100) = 140, + B10001101 DEPRECATED(0b10001101) = 141, + B10001110 DEPRECATED(0b10001110) = 142, + B10001111 DEPRECATED(0b10001111) = 143, + B10010000 DEPRECATED(0b10010000) = 144, + B10010001 DEPRECATED(0b10010001) = 145, + B10010010 DEPRECATED(0b10010010) = 146, + B10010011 DEPRECATED(0b10010011) = 147, + B10010100 DEPRECATED(0b10010100) = 148, + B10010101 DEPRECATED(0b10010101) = 149, + B10010110 DEPRECATED(0b10010110) = 150, + B10010111 DEPRECATED(0b10010111) = 151, + B10011000 DEPRECATED(0b10011000) = 152, + B10011001 DEPRECATED(0b10011001) = 153, + B10011010 DEPRECATED(0b10011010) = 154, + B10011011 DEPRECATED(0b10011011) = 155, + B10011100 DEPRECATED(0b10011100) = 156, + B10011101 DEPRECATED(0b10011101) = 157, + B10011110 DEPRECATED(0b10011110) = 158, + B10011111 DEPRECATED(0b10011111) = 159, + B10100000 DEPRECATED(0b10100000) = 160, + B10100001 DEPRECATED(0b10100001) = 161, + B10100010 DEPRECATED(0b10100010) = 162, + B10100011 DEPRECATED(0b10100011) = 163, + B10100100 DEPRECATED(0b10100100) = 164, + B10100101 DEPRECATED(0b10100101) = 165, + B10100110 DEPRECATED(0b10100110) = 166, + B10100111 DEPRECATED(0b10100111) = 167, + B10101000 DEPRECATED(0b10101000) = 168, + B10101001 DEPRECATED(0b10101001) = 169, + B10101010 DEPRECATED(0b10101010) = 170, + B10101011 DEPRECATED(0b10101011) = 171, + B10101100 DEPRECATED(0b10101100) = 172, + B10101101 DEPRECATED(0b10101101) = 173, + B10101110 DEPRECATED(0b10101110) = 174, + B10101111 DEPRECATED(0b10101111) = 175, + B10110000 DEPRECATED(0b10110000) = 176, + B10110001 DEPRECATED(0b10110001) = 177, + B10110010 DEPRECATED(0b10110010) = 178, + B10110011 DEPRECATED(0b10110011) = 179, + B10110100 DEPRECATED(0b10110100) = 180, + B10110101 DEPRECATED(0b10110101) = 181, + B10110110 DEPRECATED(0b10110110) = 182, + B10110111 DEPRECATED(0b10110111) = 183, + B10111000 DEPRECATED(0b10111000) = 184, + B10111001 DEPRECATED(0b10111001) = 185, + B10111010 DEPRECATED(0b10111010) = 186, + B10111011 DEPRECATED(0b10111011) = 187, + B10111100 DEPRECATED(0b10111100) = 188, + B10111101 DEPRECATED(0b10111101) = 189, + B10111110 DEPRECATED(0b10111110) = 190, + B10111111 DEPRECATED(0b10111111) = 191, + B11000000 DEPRECATED(0b11000000) = 192, + B11000001 DEPRECATED(0b11000001) = 193, + B11000010 DEPRECATED(0b11000010) = 194, + B11000011 DEPRECATED(0b11000011) = 195, + B11000100 DEPRECATED(0b11000100) = 196, + B11000101 DEPRECATED(0b11000101) = 197, + B11000110 DEPRECATED(0b11000110) = 198, + B11000111 DEPRECATED(0b11000111) = 199, + B11001000 DEPRECATED(0b11001000) = 200, + B11001001 DEPRECATED(0b11001001) = 201, + B11001010 DEPRECATED(0b11001010) = 202, + B11001011 DEPRECATED(0b11001011) = 203, + B11001100 DEPRECATED(0b11001100) = 204, + B11001101 DEPRECATED(0b11001101) = 205, + B11001110 DEPRECATED(0b11001110) = 206, + B11001111 DEPRECATED(0b11001111) = 207, + B11010000 DEPRECATED(0b11010000) = 208, + B11010001 DEPRECATED(0b11010001) = 209, + B11010010 DEPRECATED(0b11010010) = 210, + B11010011 DEPRECATED(0b11010011) = 211, + B11010100 DEPRECATED(0b11010100) = 212, + B11010101 DEPRECATED(0b11010101) = 213, + B11010110 DEPRECATED(0b11010110) = 214, + B11010111 DEPRECATED(0b11010111) = 215, + B11011000 DEPRECATED(0b11011000) = 216, + B11011001 DEPRECATED(0b11011001) = 217, + B11011010 DEPRECATED(0b11011010) = 218, + B11011011 DEPRECATED(0b11011011) = 219, + B11011100 DEPRECATED(0b11011100) = 220, + B11011101 DEPRECATED(0b11011101) = 221, + B11011110 DEPRECATED(0b11011110) = 222, + B11011111 DEPRECATED(0b11011111) = 223, + B11100000 DEPRECATED(0b11100000) = 224, + B11100001 DEPRECATED(0b11100001) = 225, + B11100010 DEPRECATED(0b11100010) = 226, + B11100011 DEPRECATED(0b11100011) = 227, + B11100100 DEPRECATED(0b11100100) = 228, + B11100101 DEPRECATED(0b11100101) = 229, + B11100110 DEPRECATED(0b11100110) = 230, + B11100111 DEPRECATED(0b11100111) = 231, + B11101000 DEPRECATED(0b11101000) = 232, + B11101001 DEPRECATED(0b11101001) = 233, + B11101010 DEPRECATED(0b11101010) = 234, + B11101011 DEPRECATED(0b11101011) = 235, + B11101100 DEPRECATED(0b11101100) = 236, + B11101101 DEPRECATED(0b11101101) = 237, + B11101110 DEPRECATED(0b11101110) = 238, + B11101111 DEPRECATED(0b11101111) = 239, + B11110000 DEPRECATED(0b11110000) = 240, + B11110001 DEPRECATED(0b11110001) = 241, + B11110010 DEPRECATED(0b11110010) = 242, + B11110011 DEPRECATED(0b11110011) = 243, + B11110100 DEPRECATED(0b11110100) = 244, + B11110101 DEPRECATED(0b11110101) = 245, + B11110110 DEPRECATED(0b11110110) = 246, + B11110111 DEPRECATED(0b11110111) = 247, + B11111000 DEPRECATED(0b11111000) = 248, + B11111001 DEPRECATED(0b11111001) = 249, + B11111010 DEPRECATED(0b11111010) = 250, + B11111011 DEPRECATED(0b11111011) = 251, + B11111100 DEPRECATED(0b11111100) = 252, + B11111101 DEPRECATED(0b11111101) = 253, + B11111110 DEPRECATED(0b11111110) = 254, + B11111111 DEPRECATED(0b11111111) = 255 +}; + +#undef DEPRECATED + +#endif diff --git a/cores/esp32/cbuf.cpp b/cores/esp32/cbuf.cpp new file mode 100644 index 0000000..2f942d5 --- /dev/null +++ b/cores/esp32/cbuf.cpp @@ -0,0 +1,289 @@ +/* + cbuf.cpp - Circular buffer implementation + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "cbuf.h" +#include "esp32-hal-log.h" + +#if CONFIG_DISABLE_HAL_LOCKS +#define CBUF_MUTEX_CREATE() +#define CBUF_MUTEX_LOCK() +#define CBUF_MUTEX_UNLOCK() +#define CBUF_MUTEX_DELETE() +#else +#define CBUF_MUTEX_CREATE() \ + if (_lock == NULL) { \ + _lock = xSemaphoreCreateMutex(); \ + if (_lock == NULL) { \ + log_e("failed to create mutex"); \ + } \ + } +#define CBUF_MUTEX_LOCK() \ + if (_lock != NULL) { \ + xSemaphoreTakeRecursive(_lock, portMAX_DELAY); \ + } +#define CBUF_MUTEX_UNLOCK() \ + if (_lock != NULL) { \ + xSemaphoreGiveRecursive(_lock); \ + } +#define CBUF_MUTEX_DELETE() \ + if (_lock != NULL) { \ + SemaphoreHandle_t l = _lock; \ + _lock = NULL; \ + vSemaphoreDelete(l); \ + } +#endif + +cbuf::cbuf(size_t size) : next(NULL), has_peek(false), peek_byte(0), _buf(xRingbufferCreate(size, RINGBUF_TYPE_BYTEBUF)) { + if (_buf == NULL) { + log_e("failed to allocate ring buffer"); + } + CBUF_MUTEX_CREATE(); +} + +cbuf::~cbuf() { + CBUF_MUTEX_LOCK(); + if (_buf != NULL) { + RingbufHandle_t b = _buf; + _buf = NULL; + vRingbufferDelete(b); + } + CBUF_MUTEX_UNLOCK(); + CBUF_MUTEX_DELETE(); +} + +size_t cbuf::resizeAdd(size_t addSize) { + return resize(size() + addSize); +} + +size_t cbuf::resize(size_t newSize) { + CBUF_MUTEX_LOCK(); + size_t _size = size(); + if (newSize == _size) { + return _size; + } + + // not lose any data + // if data can be lost use remove or flush before resize + size_t bytes_available = available(); + if (newSize < bytes_available) { + CBUF_MUTEX_UNLOCK(); + log_e("new size is less than the currently available data size"); + return _size; + } + + RingbufHandle_t newbuf = xRingbufferCreate(newSize, RINGBUF_TYPE_BYTEBUF); + if (newbuf == NULL) { + CBUF_MUTEX_UNLOCK(); + log_e("failed to allocate new ring buffer"); + return _size; + } + + if (_buf != NULL) { + if (bytes_available) { + char *old_data = (char *)malloc(bytes_available); + if (old_data == NULL) { + vRingbufferDelete(newbuf); + CBUF_MUTEX_UNLOCK(); + log_e("failed to allocate temporary buffer"); + return _size; + } + bytes_available = read(old_data, bytes_available); + if (!bytes_available) { + free(old_data); + vRingbufferDelete(newbuf); + CBUF_MUTEX_UNLOCK(); + log_e("failed to read previous data"); + return _size; + } + if (xRingbufferSend(newbuf, (void *)old_data, bytes_available, 0) != pdTRUE) { + write(old_data, bytes_available); + free(old_data); + vRingbufferDelete(newbuf); + CBUF_MUTEX_UNLOCK(); + log_e("failed to restore previous data"); + return _size; + } + free(old_data); + } + + RingbufHandle_t b = _buf; + _buf = newbuf; + vRingbufferDelete(b); + } else { + _buf = newbuf; + } + CBUF_MUTEX_UNLOCK(); + return newSize; +} + +size_t cbuf::available() const { + size_t available = 0; + if (_buf != NULL) { + vRingbufferGetInfo(_buf, NULL, NULL, NULL, NULL, (UBaseType_t *)&available); + } + if (has_peek) { + available++; + } + return available; +} + +size_t cbuf::size() { + size_t _size = 0; + if (_buf != NULL) { + _size = xRingbufferGetMaxItemSize(_buf); + } + return _size; +} + +size_t cbuf::room() const { + size_t _room = 0; + if (_buf != NULL) { + _room = xRingbufferGetCurFreeSize(_buf); + } + return _room; +} + +bool cbuf::empty() const { + return available() == 0; +} + +bool cbuf::full() const { + return room() == 0; +} + +int cbuf::peek() { + if (!available()) { + return -1; + } + + int c; + + CBUF_MUTEX_LOCK(); + if (has_peek) { + c = peek_byte; + } else { + c = read(); + if (c >= 0) { + has_peek = true; + peek_byte = c; + } + } + CBUF_MUTEX_UNLOCK(); + return c; +} + +int cbuf::read() { + char result = 0; + if (!read(&result, 1)) { + return -1; + } + return static_cast(result); +} + +size_t cbuf::read(char *dst, size_t size) { + CBUF_MUTEX_LOCK(); + size_t bytes_available = available(); + if (!bytes_available || !size) { + CBUF_MUTEX_UNLOCK(); + return 0; + } + + if (has_peek) { + if (dst != NULL) { + *dst++ = peek_byte; + } + size--; + } + + size_t size_read = 0; + if (size) { + size_t received_size = 0; + size_t size_to_read = (size < bytes_available) ? size : bytes_available; + uint8_t *received_buff = (uint8_t *)xRingbufferReceiveUpTo(_buf, &received_size, 0, size_to_read); + if (received_buff != NULL) { + if (dst != NULL) { + memcpy(dst, received_buff, received_size); + } + vRingbufferReturnItem(_buf, received_buff); + size_read = received_size; + size_to_read -= received_size; + // wrap around data + if (size_to_read) { + received_size = 0; + received_buff = (uint8_t *)xRingbufferReceiveUpTo(_buf, &received_size, 0, size_to_read); + if (received_buff != NULL) { + if (dst != NULL) { + memcpy(dst + size_read, received_buff, received_size); + } + vRingbufferReturnItem(_buf, received_buff); + size_read += received_size; + } else { + log_e("failed to read wrap around data from ring buffer"); + } + } + } else { + log_e("failed to read from ring buffer"); + } + } + + if (has_peek) { + has_peek = false; + size_read++; + } + + CBUF_MUTEX_UNLOCK(); + return size_read; +} + +size_t cbuf::write(char c) { + return write(&c, 1); +} + +size_t cbuf::write(const char *src, size_t size) { + CBUF_MUTEX_LOCK(); + size_t bytes_available = room(); + if (!bytes_available || !size) { + CBUF_MUTEX_UNLOCK(); + return 0; + } + size_t size_to_write = (size < bytes_available) ? size : bytes_available; + if (xRingbufferSend(_buf, (void *)src, size_to_write, 0) != pdTRUE) { + CBUF_MUTEX_UNLOCK(); + log_e("failed to write to ring buffer"); + return 0; + } + CBUF_MUTEX_UNLOCK(); + return size_to_write; +} + +void cbuf::flush() { + read(NULL, available()); +} + +size_t cbuf::remove(size_t size) { + CBUF_MUTEX_LOCK(); + size_t bytes_available = available(); + if (bytes_available && size) { + size_t size_to_remove = (size < bytes_available) ? size : bytes_available; + bytes_available -= read(NULL, size_to_remove); + } + CBUF_MUTEX_UNLOCK(); + return bytes_available; +} diff --git a/cores/esp32/cbuf.h b/cores/esp32/cbuf.h new file mode 100644 index 0000000..3d2a173 --- /dev/null +++ b/cores/esp32/cbuf.h @@ -0,0 +1,65 @@ +/* + cbuf.h - Circular buffer implementation + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include +#include +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/ringbuf.h" +#include "freertos/semphr.h" + +class cbuf { +public: + cbuf(size_t size); + ~cbuf(); + + size_t resizeAdd(size_t addSize); + size_t resize(size_t newSize); + + size_t available() const; + size_t size(); + size_t room() const; + bool empty() const; + bool full() const; + + int peek(); + + int read(); + size_t read(char *dst, size_t size); + + size_t write(char c); + size_t write(const char *src, size_t size); + + void flush(); + size_t remove(size_t size); + + cbuf *next; + bool has_peek; + uint8_t peek_byte; + +protected: + RingbufHandle_t _buf = NULL; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t _lock = NULL; +#endif +}; diff --git a/cores/esp32/chip-debug-report.cpp b/cores/esp32/chip-debug-report.cpp new file mode 100644 index 0000000..414dd10 --- /dev/null +++ b/cores/esp32/chip-debug-report.cpp @@ -0,0 +1,338 @@ +#include "esp_heap_caps.h" +#include "esp_chip_info.h" +#include "esp_idf_version.h" +#include "esp_arduino_version.h" +#include "esp_rom_spiflash.h" +#include "esp_flash.h" +#include "esp_partition.h" +#include "esp_app_format.h" +#include "soc/efuse_reg.h" +#include "soc/rtc.h" +#include "soc/spi_reg.h" +#include "soc/soc.h" +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/spi_flash.h" +#endif +#include "esp_bit_defs.h" + +#include "Arduino.h" +#include "esp32-hal-periman.h" +#include "chip-debug-report.h" + +#define chip_report_printf log_printf + +#define printMemCapsInfo(caps) _printMemCapsInfo(MALLOC_CAP_##caps, #caps) +#define b2kb(b) ((float)b / 1024.0) +#define b2mb(b) ((float)b / (1024.0 * 1024.0)) +static void _printMemCapsInfo(uint32_t caps, const char *caps_str) { + multi_heap_info_t info; + size_t total = heap_caps_get_total_size(caps); + heap_caps_get_info(&info, caps); + chip_report_printf("%s Memory Info:\n", caps_str); + chip_report_printf("------------------------------------------\n"); + chip_report_printf(" Total Size : %8u B (%6.1f KB)\n", total, b2kb(total)); + chip_report_printf(" Free Bytes : %8u B (%6.1f KB)\n", info.total_free_bytes, b2kb(info.total_free_bytes)); + chip_report_printf(" Allocated Bytes : %8u B (%6.1f KB)\n", info.total_allocated_bytes, b2kb(info.total_allocated_bytes)); + chip_report_printf(" Minimum Free Bytes: %8u B (%6.1f KB)\n", info.minimum_free_bytes, b2kb(info.minimum_free_bytes)); + chip_report_printf(" Largest Free Block: %8u B (%6.1f KB)\n", info.largest_free_block, b2kb(info.largest_free_block)); +} + +static void printPkgVersion(void) { + chip_report_printf(" Package : "); +#if CONFIG_IDF_TARGET_ESP32 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE); + switch (pkg_ver) { + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3: chip_report_printf("D0WD-R2-V3"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6: chip_report_printf("D0WD-Q6"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5: chip_report_printf("D0WD-Q5"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5: chip_report_printf("D2WD-Q5"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH: chip_report_printf("U4WD-H"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4: chip_report_printf("PICO-D4"); break; + case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: chip_report_printf("PICO-V3-02"); break; + } +#elif CONFIG_IDF_TARGET_ESP32S2 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); + switch (pkg_ver) { + case 1: chip_report_printf("FH16"); break; + case 2: chip_report_printf("FH32"); break; + default: chip_report_printf("%lu", pkg_ver); break; + } +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); + chip_report_printf("%lu", pkg_ver); +#elif CONFIG_IDF_TARGET_ESP32C2 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION); + chip_report_printf("%lu", pkg_ver); +#elif CONFIG_IDF_TARGET_ESP32H2 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_4_REG, EFUSE_PKG_VERSION); + chip_report_printf("%lu", pkg_ver); +#elif CONFIG_IDF_TARGET_ESP32P4 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION); + chip_report_printf("%lu", pkg_ver); +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION); + chip_report_printf("%lu", pkg_ver); +#else + chip_report_printf("Unknown"); +#endif + chip_report_printf("\n"); +} + +static void printChipInfo(void) { + esp_chip_info_t info; + esp_chip_info(&info); + chip_report_printf("Chip Info:\n"); + chip_report_printf("------------------------------------------\n"); + chip_report_printf(" Model : "); + switch (info.model) { + case CHIP_ESP32: chip_report_printf("ESP32\n"); break; + case CHIP_ESP32S2: chip_report_printf("ESP32-S2\n"); break; + case CHIP_ESP32S3: chip_report_printf("ESP32-S3\n"); break; + case CHIP_ESP32C2: chip_report_printf("ESP32-C2\n"); break; + case CHIP_ESP32C3: chip_report_printf("ESP32-C3\n"); break; + case CHIP_ESP32C6: chip_report_printf("ESP32-C6\n"); break; + case CHIP_ESP32H2: chip_report_printf("ESP32-H2\n"); break; + case CHIP_ESP32P4: chip_report_printf("ESP32-P4\n"); break; +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) + case CHIP_ESP32C5: chip_report_printf("ESP32-C5\n"); break; + case CHIP_ESP32C61: chip_report_printf("ESP32-C61\n"); break; + case CHIP_ESP32H21: chip_report_printf("ESP32-H21\n"); break; +#endif + default: chip_report_printf("Unknown %d\n", info.model); break; + } + printPkgVersion(); + chip_report_printf(" Revision : %.2f\n", (float)(info.revision) / 100.0); + chip_report_printf(" Cores : %d\n", info.cores); + rtc_cpu_freq_config_t conf; + rtc_clk_cpu_freq_get_config(&conf); + chip_report_printf(" CPU Frequency : %lu MHz\n", conf.freq_mhz); + chip_report_printf(" XTAL Frequency : %d MHz\n", rtc_clk_xtal_freq_get()); + chip_report_printf(" Features Bitfield : %#010x\n", info.features); + chip_report_printf(" Embedded Flash : %s\n", (info.features & CHIP_FEATURE_EMB_FLASH) ? "Yes" : "No"); + chip_report_printf(" Embedded PSRAM : %s\n", (info.features & CHIP_FEATURE_EMB_PSRAM) ? "Yes" : "No"); + chip_report_printf(" 2.4GHz WiFi : %s\n", (info.features & CHIP_FEATURE_WIFI_BGN) ? "Yes" : "No"); + chip_report_printf(" Classic BT : %s\n", (info.features & CHIP_FEATURE_BT) ? "Yes" : "No"); + chip_report_printf(" BT Low Energy : %s\n", (info.features & CHIP_FEATURE_BLE) ? "Yes" : "No"); + chip_report_printf(" IEEE 802.15.4 : %s\n", (info.features & CHIP_FEATURE_IEEE802154) ? "Yes" : "No"); +} + +static void printFlashInfo(void) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 +#define ESP_FLASH_IMAGE_BASE 0x1000 +#elif CONFIG_IDF_TARGET_ESP32P4 +#define ESP_FLASH_IMAGE_BASE 0x2000 +#else +#define ESP_FLASH_IMAGE_BASE 0x0000 +#endif +// REG_SPI_BASE is not defined for S3/C3 ?? +#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#ifdef REG_SPI_BASE +#undef REG_SPI_BASE +#endif // REG_SPI_BASE +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000))) +#endif // TARGET + + chip_report_printf("Flash Info:\n"); + chip_report_printf("------------------------------------------\n"); + uint32_t hw_size = 1 << (g_rom_flashchip.device_id & 0xFF); + chip_report_printf(" Chip Size : %8lu B (%.0f MB)\n", hw_size, b2mb(hw_size)); + chip_report_printf(" Block Size : %8lu B (%6.1f KB)\n", g_rom_flashchip.block_size, b2kb(g_rom_flashchip.block_size)); + chip_report_printf(" Sector Size : %8lu B (%6.1f KB)\n", g_rom_flashchip.sector_size, b2kb(g_rom_flashchip.sector_size)); + chip_report_printf(" Page Size : %8lu B (%6.1f KB)\n", g_rom_flashchip.page_size, b2kb(g_rom_flashchip.page_size)); + + // Runtime flash frequency detection from hardware registers + uint32_t actual_freq = ESP.getFlashFrequencyMHz(); + uint8_t source_freq = ESP.getFlashSourceFrequencyMHz(); + uint8_t divider = ESP.getFlashClockDivider(); + + chip_report_printf(" Bus Speed : %lu MHz\n", actual_freq); + chip_report_printf(" Flash Frequency : %lu MHz (source: %u MHz, divider: %u)\n", actual_freq, source_freq, divider); + + chip_report_printf(" Bus Mode : "); +#if CONFIG_ESPTOOLPY_OCT_FLASH + chip_report_printf("OPI\n"); +#elif CONFIG_ESPTOOLPY_FLASHMODE_QIO + chip_report_printf("QIO\n"); +#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT + chip_report_printf("QOUT\n"); +#elif CONFIG_ESPTOOLPY_FLASHMODE_DIO + chip_report_printf("DIO\n"); +#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT + chip_report_printf("DOUT\n"); +#endif +} + +static void printPartitionsInfo(void) { + chip_report_printf("Partitions Info:\n"); + chip_report_printf("------------------------------------------\n"); + esp_partition_iterator_t iterator = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL); + if (iterator != NULL) { + esp_partition_iterator_t it = iterator; + while (it != NULL) { + const esp_partition_t *partition = esp_partition_get(it); + if (partition) { + chip_report_printf(" %17s : addr: 0x%08X, size: %7.1f KB", partition->label, partition->address, b2kb(partition->size)); + if (partition->type == ESP_PARTITION_TYPE_APP) { + chip_report_printf(", type: APP"); + if (partition->subtype == 0) { + chip_report_printf(", subtype: FACTORY"); + } else if (partition->subtype >= 0x10 && partition->subtype < 0x20) { + chip_report_printf(", subtype: OTA_%lu", partition->subtype - 0x10); + } else if (partition->subtype == 0x20) { + chip_report_printf(", subtype: TEST"); + } else { + chip_report_printf(", subtype: 0x%02X", partition->subtype); + } + } else { + chip_report_printf(", type: DATA"); + chip_report_printf(", subtype: "); + switch (partition->subtype) { + case ESP_PARTITION_SUBTYPE_DATA_OTA: chip_report_printf("OTA"); break; + case ESP_PARTITION_SUBTYPE_DATA_PHY: chip_report_printf("PHY"); break; + case ESP_PARTITION_SUBTYPE_DATA_NVS: chip_report_printf("NVS"); break; + case ESP_PARTITION_SUBTYPE_DATA_COREDUMP: chip_report_printf("COREDUMP"); break; + case ESP_PARTITION_SUBTYPE_DATA_NVS_KEYS: chip_report_printf("NVS_KEYS"); break; + case ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM: chip_report_printf("EFUSE_EM"); break; + case ESP_PARTITION_SUBTYPE_DATA_UNDEFINED: chip_report_printf("UNDEFINED"); break; + case ESP_PARTITION_SUBTYPE_DATA_ESPHTTPD: chip_report_printf("ESPHTTPD"); break; + case ESP_PARTITION_SUBTYPE_DATA_FAT: chip_report_printf("FAT"); break; + case ESP_PARTITION_SUBTYPE_DATA_SPIFFS: chip_report_printf("SPIFFS"); break; + case ESP_PARTITION_SUBTYPE_DATA_LITTLEFS: chip_report_printf("LITTLEFS"); break; + default: chip_report_printf("0x%02X", partition->subtype); break; + } + } + chip_report_printf("\n"); + } + it = esp_partition_next(it); + } + //esp_partition_iterator_release(iterator); + } +} + +static void printSoftwareInfo(void) { + chip_report_printf("Software Info:\n"); + chip_report_printf("------------------------------------------\n"); + chip_report_printf(" Compile Date/Time : %s %s\n", __DATE__, __TIME__); +#ifdef ARDUINO_HOST_OS + chip_report_printf(" Compile Host OS : %s\n", ARDUINO_HOST_OS); +#endif + chip_report_printf(" ESP-IDF Version : %s\n", esp_get_idf_version()); + chip_report_printf(" Arduino Version : %s\n", ESP_ARDUINO_VERSION_STR); +} + +static void printBoardInfo(void) { + chip_report_printf("Board Info:\n"); + chip_report_printf("------------------------------------------\n"); + chip_report_printf(" Arduino Board : %s\n", ARDUINO_BOARD); + chip_report_printf(" Arduino Variant : %s\n", ARDUINO_VARIANT); +#ifdef ARDUINO_FQBN + chip_report_printf(" Arduino FQBN : %s\n", ARDUINO_FQBN); +#else +#ifdef CORE_DEBUG_LEVEL + chip_report_printf(" Core Debug Level : %d\n", CORE_DEBUG_LEVEL); +#endif +#ifdef ARDUINO_RUNNING_CORE + chip_report_printf(" Arduino Runs Core : %d\n", ARDUINO_RUNNING_CORE); + chip_report_printf(" Arduino Events on : %d\n", ARDUINO_EVENT_RUNNING_CORE); +#endif +#ifdef ARDUINO_USB_MODE + chip_report_printf(" Arduino USB Mode : %d\n", ARDUINO_USB_MODE); +#endif +#ifdef ARDUINO_USB_CDC_ON_BOOT + chip_report_printf(" CDC On Boot : %d\n", ARDUINO_USB_CDC_ON_BOOT); +#endif +#endif /* ARDUINO_FQBN */ +} + +static void printPerimanInfo(void) { + chip_report_printf("GPIO Info:\n"); + chip_report_printf("------------------------------------------\n"); +#if defined(BOARD_HAS_PIN_REMAP) + chip_report_printf(" DPIN|GPIO : BUS_TYPE[bus/unit][chan]\n"); +#else + chip_report_printf(" GPIO : BUS_TYPE[bus/unit][chan]\n"); +#endif + chip_report_printf(" -------------------------------------- \n"); + for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) { + if (!perimanPinIsValid(i)) { + continue; //invalid pin + } + peripheral_bus_type_t type = perimanGetPinBusType(i); + if (type == ESP32_BUS_TYPE_INIT) { + continue; //unused pin + } +#if defined(BOARD_HAS_PIN_REMAP) + int dpin = gpioNumberToDigitalPin(i); + if (dpin < 0) { + continue; //pin is not exported + } else { + chip_report_printf(" D%-3d|%4u : ", dpin, i); + } +#else + chip_report_printf(" %4u : ", i); +#endif + const char *extra_type = perimanGetPinBusExtraType(i); + if (extra_type) { + chip_report_printf("%s", extra_type); + } else { + chip_report_printf("%s", perimanGetTypeName(type)); + } + int8_t bus_number = perimanGetPinBusNum(i); + if (bus_number != -1) { + chip_report_printf("[%u]", bus_number); + } + int8_t bus_channel = perimanGetPinBusChannel(i); + if (bus_channel != -1) { + chip_report_printf("[%u]", bus_channel); + } + chip_report_printf("\n"); + } +} + +void printBeforeSetupInfo(void) { +#if ARDUINO_USB_CDC_ON_BOOT + Serial.begin(); + Serial.setDebugOutput(true); + uint8_t t = 0; + while (!Serial && (t++ < 200)) { + delay(10); //wait up to 2 seconds for the IDE to connect + } +#endif + chip_report_printf("=========== Before Setup Start ===========\n"); + printChipInfo(); + chip_report_printf("------------------------------------------\n"); + printMemCapsInfo(INTERNAL); + chip_report_printf("------------------------------------------\n"); + if (psramFound()) { + printMemCapsInfo(SPIRAM); + chip_report_printf(" Bus Mode : "); +#if CONFIG_SPIRAM_MODE_OCT + chip_report_printf("OPI\n"); +#else + chip_report_printf("QSPI\n"); +#endif + chip_report_printf("------------------------------------------\n"); + } + printFlashInfo(); + chip_report_printf("------------------------------------------\n"); + printPartitionsInfo(); + chip_report_printf("------------------------------------------\n"); + printSoftwareInfo(); + chip_report_printf("------------------------------------------\n"); + printBoardInfo(); + chip_report_printf("============ Before Setup End ============\n"); + delay(100); //allow the print to finish +} + +void printAfterSetupInfo(void) { + chip_report_printf("=========== After Setup Start ============\n"); + printMemCapsInfo(INTERNAL); + chip_report_printf("------------------------------------------\n"); + if (psramFound()) { + printMemCapsInfo(SPIRAM); + chip_report_printf("------------------------------------------\n"); + } + printPerimanInfo(); + chip_report_printf("============ After Setup End =============\n"); + delay(20); //allow the print to finish +} diff --git a/cores/esp32/chip-debug-report.h b/cores/esp32/chip-debug-report.h new file mode 100644 index 0000000..5c2c849 --- /dev/null +++ b/cores/esp32/chip-debug-report.h @@ -0,0 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +void printBeforeSetupInfo(void); +void printAfterSetupInfo(void); diff --git a/cores/esp32/core_version.h b/cores/esp32/core_version.h new file mode 100644 index 0000000..bfdf55f --- /dev/null +++ b/cores/esp32/core_version.h @@ -0,0 +1,4 @@ +#define ARDUINO_ESP32_GIT_VER 0xc3e5d72f +#define ARDUINO_ESP32_GIT_DESC 3.3.7-1-gc3e5d72fb +#define ARDUINO_ESP32_RELEASE_3_3_7 +#define ARDUINO_ESP32_RELEASE "3_3_7" diff --git a/cores/esp32/esp32-hal-adc.c b/cores/esp32/esp32-hal-adc.c new file mode 100644 index 0000000..4fb62ad --- /dev/null +++ b/cores/esp32/esp32-hal-adc.c @@ -0,0 +1,772 @@ +// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-adc.h" + +#if SOC_ADC_SUPPORTED +#include "esp32-hal.h" +#include "esp32-hal-periman.h" +#include "esp_adc/adc_oneshot.h" +#include "esp_adc/adc_continuous.h" +#include "esp_adc/adc_cali_scheme.h" +#include "esp_heap_caps.h" + +#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL >= 300 +// NOTE: These weak definitions allow successful linkage if the real efuse calibration functions are missing. +// This is a workaround for the ESP32P4 rev 3.0+, which is missing efuse calibration functions in the IDF. +__attribute__((weak)) uint32_t esp_efuse_rtc_calib_get_ver(void) { + return 0; +} + +__attribute__((weak)) uint32_t esp_efuse_rtc_calib_get_init_code(uint32_t atten, uint32_t *code) { + if (code) { + *code = 0; + } + return 0; // 0 means success in ESP-IDF conventions +} + +__attribute__((weak)) uint32_t esp_efuse_rtc_calib_get_chan_compens(uint32_t atten, uint32_t *comp) { + if (comp) { + *comp = 0; + } + return 0; +} + +__attribute__((weak)) uint32_t esp_efuse_rtc_calib_get_cal_voltage(uint32_t atten, uint32_t *voltage) { + if (voltage) { + *voltage = 0; + } + return 0; +} +#endif + +// ESP32-C2 does not define those two for some reason +#ifndef SOC_ADC_DIGI_RESULT_BYTES +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#endif +#ifndef SOC_ADC_DIGI_DATA_BYTES_PER_CONV +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +#endif + +static uint8_t __analogAttenuation = ADC_11db; +static uint8_t __analogWidth = SOC_ADC_RTC_MAX_BITWIDTH; +static uint8_t __analogReturnedWidth = SOC_ADC_RTC_MAX_BITWIDTH; + +typedef struct { + voidFuncPtr fn; + void *arg; +} interrupt_config_t; + +typedef struct { + adc_oneshot_unit_handle_t adc_oneshot_handle; + adc_continuous_handle_t adc_continuous_handle; + interrupt_config_t adc_interrupt_handle; + adc_cali_handle_t adc_cali_handle; + uint32_t buffer_size; + uint32_t conversion_frame_size; +} adc_handle_t; + +adc_handle_t adc_handle[SOC_ADC_PERIPH_NUM]; + +static bool adcDetachBus(void *pin) { + adc_channel_t adc_channel; + adc_unit_t adc_unit; + uint8_t used_channels = 0; + + adc_oneshot_io_to_channel((int)(pin - 1), &adc_unit, &adc_channel); + for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(adc_unit); channel++) { + int io_pin; + adc_oneshot_channel_to_io(adc_unit, channel, &io_pin); + if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_ONESHOT) { + used_channels++; + } + } + + if (used_channels == 1) { //only 1 channel is used + esp_err_t err = adc_oneshot_del_unit(adc_handle[adc_unit].adc_oneshot_handle); + if (err != ESP_OK) { + return false; + } + adc_handle[adc_unit].adc_oneshot_handle = NULL; + if (adc_handle[adc_unit].adc_cali_handle != NULL) { +#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED + err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + return false; + } +#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED + err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + return false; + } +#else + log_e("ADC Calibration scheme is not supported!"); + return false; +#endif + } + adc_handle[adc_unit].adc_cali_handle = NULL; + } + return true; +} + +esp_err_t __analogChannelConfig(adc_bitwidth_t width, adc_attenuation_t atten, int8_t pin) { + esp_err_t err = ESP_OK; + adc_oneshot_chan_cfg_t config = { + .bitwidth = width, + .atten = (atten & 3), + }; + if (pin == -1) { //Reconfigure all used analog pins/channels + for (int adc_unit = 0; adc_unit < SOC_ADC_PERIPH_NUM; adc_unit++) { + if (adc_handle[adc_unit].adc_oneshot_handle != NULL) { + for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(adc_unit); channel++) { + int io_pin; + adc_oneshot_channel_to_io(adc_unit, channel, &io_pin); + if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_ONESHOT) { + err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config); + if (err != ESP_OK) { + log_e("adc_oneshot_config_channel failed with error: %d", err); + return err; + } + } + } + //ADC calibration reconfig only if all channels are updated + if (adc_handle[adc_unit].adc_cali_handle != NULL) { +#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED + log_d("Deleting ADC_UNIT_%d cali handle", adc_unit); + err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + log_e("adc_cali_delete_scheme_curve_fitting failed with error: %d", err); + return err; + } + adc_cali_curve_fitting_config_t cali_config = { + .unit_id = adc_unit, + .atten = atten, + .bitwidth = width, + }; + log_d("Creating ADC_UNIT_%d curve cali handle", adc_unit); + err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + log_e("adc_cali_create_scheme_curve_fitting failed with error: %d", err); + return err; + } +#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED + log_d("Deleting ADC_UNIT_%d line cali handle", adc_unit); + err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + log_e("adc_cali_delete_scheme_line_fitting failed with error: %d", err); + return err; + } + adc_cali_line_fitting_config_t cali_config = { + .unit_id = adc_unit, + .atten = atten, + .bitwidth = width, + }; + log_d("Creating ADC_UNIT_%d line cali handle", adc_unit); + err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + log_e("adc_cali_create_scheme_line_fitting failed with error: %d", err); + return err; + } +#else + log_e("ADC Calibration scheme is not supported!"); + return ESP_ERR_NOT_SUPPORTED; +#endif + } + } + } + + //make it default for next channels + __analogWidth = width; + __analogAttenuation = atten; + } else { //Reconfigure single channel + if (perimanGetPinBusType(pin) == ESP32_BUS_TYPE_ADC_ONESHOT) { + adc_channel_t channel; + adc_unit_t adc_unit; + + adc_oneshot_io_to_channel(pin, &adc_unit, &channel); + if (err != ESP_OK) { + log_e("Pin %u is not ADC pin!", pin); + return err; + } + err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config); + if (err != ESP_OK) { + log_e("adc_oneshot_config_channel failed with error: %d", err); + return err; + } + } else { + log_e("Pin is not configured as analog channel"); + } + } + return ESP_OK; +} + +static inline uint16_t mapResolution(uint16_t value) { + uint8_t from = __analogWidth; + if (from == __analogReturnedWidth) { + return value; + } + if (from > __analogReturnedWidth) { + return value >> (from - __analogReturnedWidth); + } + return value << (__analogReturnedWidth - from); +} + +void __analogSetAttenuation(adc_attenuation_t attenuation) { + if (__analogChannelConfig(__analogWidth, attenuation, -1) != ESP_OK) { + log_e("__analogChannelConfig failed!"); + } +} + +#if CONFIG_IDF_TARGET_ESP32 +void __analogSetWidth(uint8_t bits) { + if (bits < SOC_ADC_RTC_MIN_BITWIDTH) { + bits = SOC_ADC_RTC_MIN_BITWIDTH; + } else if (bits > SOC_ADC_RTC_MAX_BITWIDTH) { + bits = SOC_ADC_RTC_MAX_BITWIDTH; + } + if (__analogChannelConfig(bits, __analogAttenuation, -1) != ESP_OK) { + log_e("__analogChannelConfig failed!"); + } +} +#endif + +esp_err_t __analogInit(uint8_t pin, adc_channel_t channel, adc_unit_t adc_unit) { + esp_err_t err = ESP_OK; + if (adc_handle[adc_unit].adc_oneshot_handle == NULL) { + adc_oneshot_unit_init_cfg_t init_config1 = { + .unit_id = adc_unit, + .ulp_mode = ADC_ULP_MODE_DISABLE, + }; + err = adc_oneshot_new_unit(&init_config1, &adc_handle[adc_unit].adc_oneshot_handle); + + if (err != ESP_OK) { + log_e("adc_oneshot_new_unit failed with error: %d", err); + return err; + } + } + perimanSetBusDeinit(ESP32_BUS_TYPE_ADC_ONESHOT, adcDetachBus); + + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT, (void *)(pin + 1), adc_unit, channel)) { + adcDetachBus((void *)(pin + 1)); + return err; + } + + adc_oneshot_chan_cfg_t config = { + .bitwidth = __analogWidth, + .atten = __analogAttenuation, + }; + + err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config); + if (err != ESP_OK) { + log_e("adc_oneshot_config_channel failed with error: %d", err); + return err; + } + return ESP_OK; +} + +void __analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation) { + if (__analogChannelConfig(__analogWidth, attenuation, pin) != ESP_OK) { + log_e("__analogChannelConfig failed!"); + } +} + +void __analogReadResolution(uint8_t bits) { + if (!bits || bits > 16) { + return; + } + __analogReturnedWidth = bits; + +#if CONFIG_IDF_TARGET_ESP32 + __analogSetWidth(bits); // hardware analog resolution from 9 to 12 +#endif +} + +uint16_t __analogRead(uint8_t pin) { + int value = 0; + adc_channel_t channel; + adc_unit_t adc_unit; + + esp_err_t err = ESP_OK; + err = adc_oneshot_io_to_channel(pin, &adc_unit, &channel); + if (err != ESP_OK) { + log_e("Pin %u is not ADC pin!", pin); + return value; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT) == NULL) { + log_d("Calling __analogInit! pin = %d", pin); + err = __analogInit(pin, channel, adc_unit); + if (err != ESP_OK) { + log_e("Analog initialization failed!"); + return value; + } + } + + adc_oneshot_read(adc_handle[adc_unit].adc_oneshot_handle, channel, &value); + return mapResolution(value); +} + +uint32_t __analogReadMilliVolts(uint8_t pin) { + int value = 0; + adc_channel_t channel; + adc_unit_t adc_unit; + esp_err_t err = ESP_OK; + + adc_oneshot_io_to_channel(pin, &adc_unit, &channel); + if (err != ESP_OK) { + log_e("Pin %u is not ADC pin!", pin); + return value; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT) == NULL) { + err = __analogInit(pin, channel, adc_unit); + if (err != ESP_OK) { + log_e("Analog initialization failed!"); + return value; + } + } + + if (adc_handle[adc_unit].adc_cali_handle == NULL) { + log_d("Creating cali handle for ADC_%d", adc_unit); +#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED + adc_cali_curve_fitting_config_t cali_config = { + .unit_id = adc_unit, + .atten = __analogAttenuation, + .bitwidth = __analogWidth, + }; + err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); +#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED + adc_cali_line_fitting_config_t cali_config = { + .unit_id = adc_unit, + .bitwidth = __analogWidth, + .atten = __analogAttenuation, + }; + err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); +#else + log_e("ADC Calibration scheme is not supported!"); + return value; +#endif + if (err != ESP_OK) { + log_e("adc_cali_create_scheme_x failed!"); + return value; + } + } + + err = adc_oneshot_get_calibrated_result(adc_handle[adc_unit].adc_oneshot_handle, adc_handle[adc_unit].adc_cali_handle, channel, &value); + if (err != ESP_OK) { + log_e("adc_oneshot_get_calibrated_result failed!"); + return 0; + } + return value; +} + +extern uint16_t analogRead(uint8_t pin) __attribute__((weak, alias("__analogRead"))); +extern uint32_t analogReadMilliVolts(uint8_t pin) __attribute__((weak, alias("__analogReadMilliVolts"))); +extern void analogReadResolution(uint8_t bits) __attribute__((weak, alias("__analogReadResolution"))); +extern void analogSetAttenuation(adc_attenuation_t attenuation) __attribute__((weak, alias("__analogSetAttenuation"))); +extern void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation) __attribute__((weak, alias("__analogSetPinAttenuation"))); + +#if CONFIG_IDF_TARGET_ESP32 +extern void analogSetWidth(uint8_t bits) __attribute__((weak, alias("__analogSetWidth"))); +#endif + +/* + * ADC Continuous mode + */ + +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 +#define ADC_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE1 +#define ADC_GET_CHANNEL(p_data) ((p_data)->type1.channel) +#define ADC_GET_DATA(p_data) ((p_data)->type1.data) +#else +#define ADC_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE2 +#define ADC_GET_CHANNEL(p_data) ((p_data)->type2.channel) +#define ADC_GET_DATA(p_data) ((p_data)->type2.data) +#endif + +static uint8_t __adcContinuousAtten = ADC_11db; +static uint8_t __adcContinuousWidth = SOC_ADC_DIGI_MAX_BITWIDTH; + +static uint8_t used_adc_channels = 0; +adc_continuous_result_t *adc_result = NULL; + +static bool adcContinuousDetachBus(void *adc_unit_number) { + adc_unit_t adc_unit = (adc_unit_t)adc_unit_number - 1; + + // Guard against double-cleanup: check if already cleaned up + if (adc_handle[adc_unit].adc_continuous_handle == NULL) { + return true; + } + + // Clean up ADC driver + esp_err_t err = adc_continuous_deinit(adc_handle[adc_unit].adc_continuous_handle); + if (err != ESP_OK) { + return false; + } + adc_handle[adc_unit].adc_continuous_handle = NULL; + + // Clean up calibration handle if exists + if (adc_handle[adc_unit].adc_cali_handle != NULL) { +#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED + err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + return false; + } +#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED + err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle); + if (err != ESP_OK) { + return false; + } +#else + log_e("ADC Calibration scheme is not supported!"); + return false; +#endif + adc_handle[adc_unit].adc_cali_handle = NULL; + } + + // Don't call perimanClearPinBus() here - the peripheral manager already handles it. + // This callback is only responsible for cleaning up the IDF's ADC driver and calibration handles. + // It does NOT free the adc_result buffer. The caller is responsible for freeing adc_result. + return true; +} + +bool IRAM_ATTR adcFnWrapper(adc_continuous_handle_t handle, const adc_continuous_evt_data_t *edata, void *args) { + interrupt_config_t *isr = (interrupt_config_t *)args; + //Check if edata->size matches conversion_frame_size, else just return from ISR + if (edata->size == adc_handle[0].conversion_frame_size) { + if (isr->fn) { + if (isr->arg) { + ((voidFuncPtrArg)isr->fn)(isr->arg); + } else { + isr->fn(); + } + } + } + return false; +} + +esp_err_t __analogContinuousInit(adc_channel_t *channel, uint8_t channel_num, adc_unit_t adc_unit, uint32_t sampling_freq_hz) { + //Create new ADC continuous handle + adc_continuous_handle_cfg_t adc_config = { + .max_store_buf_size = adc_handle[adc_unit].buffer_size, + .conv_frame_size = adc_handle[adc_unit].conversion_frame_size, + }; + + esp_err_t err = adc_continuous_new_handle(&adc_config, &adc_handle[adc_unit].adc_continuous_handle); + if (err != ESP_OK) { + log_e("adc_continuous_new_handle failed with error: %d", err); + return ESP_FAIL; + } + + //Configure adc pins + adc_continuous_config_t dig_cfg = { + .sample_freq_hz = sampling_freq_hz, + .conv_mode = ADC_CONV_SINGLE_UNIT_1, + .format = ADC_OUTPUT_TYPE, + }; + adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0}; + dig_cfg.pattern_num = channel_num; + for (int i = 0; i < channel_num; i++) { + adc_pattern[i].atten = __adcContinuousAtten; + adc_pattern[i].channel = channel[i]; + adc_pattern[i].unit = ADC_UNIT_1; + adc_pattern[i].bit_width = __adcContinuousWidth; + } + dig_cfg.adc_pattern = adc_pattern; + err = adc_continuous_config(adc_handle[adc_unit].adc_continuous_handle, &dig_cfg); + + if (err != ESP_OK) { + log_e("adc_continuous_config failed with error: %d", err); + return ESP_FAIL; + } + + used_adc_channels = channel_num; + return ESP_OK; +} + +bool analogContinuous(const uint8_t pins[], size_t pins_count, uint32_t conversions_per_pin, uint32_t sampling_freq_hz, void (*userFunc)(void)) { + adc_channel_t channel[pins_count]; + adc_unit_t adc_unit = ADC_UNIT_1; + esp_err_t err = ESP_OK; + + //Convert pins to channels and check if all are ADC1s unit + for (int i = 0; i < pins_count; i++) { + err = adc_continuous_io_to_channel(pins[i], &adc_unit, &channel[i]); + if (err != ESP_OK) { + log_e("Pin %u is not ADC pin!", pins[i]); + return false; + } + if (adc_unit != 0) { + log_e("Only ADC1 pins are supported in continuous mode!"); + return false; + } + } + + //Check if Oneshot and Continuous handle exists + if (adc_handle[adc_unit].adc_oneshot_handle != NULL) { + log_e("ADC%d is running in oneshot mode. Aborting.", adc_unit + 1); + return false; + } + if (adc_handle[adc_unit].adc_continuous_handle != NULL) { + log_e("ADC%d continuous is already initialized. To reconfigure call analogContinuousDeinit() first.", adc_unit + 1); + return false; + } + + //Check sampling frequency + if ((sampling_freq_hz < SOC_ADC_SAMPLE_FREQ_THRES_LOW) || (sampling_freq_hz > SOC_ADC_SAMPLE_FREQ_THRES_HIGH)) { + log_e("Sampling frequency is out of range. Supported sampling frequencies are %d - %d", SOC_ADC_SAMPLE_FREQ_THRES_LOW, SOC_ADC_SAMPLE_FREQ_THRES_HIGH); + return false; + } + + //Set periman deinit function and reset all pins to init state. + perimanSetBusDeinit(ESP32_BUS_TYPE_ADC_CONT, adcContinuousDetachBus); + for (int j = 0; j < pins_count; j++) { + if (!perimanClearPinBus(pins[j])) { + return false; + } + } + + //Set conversion frame and buffer size (conversion frame must be in multiples of SOC_ADC_DIGI_DATA_BYTES_PER_CONV) + adc_handle[adc_unit].conversion_frame_size = conversions_per_pin * pins_count * SOC_ADC_DIGI_RESULT_BYTES; + +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + uint8_t calc_multiple = adc_handle[adc_unit].conversion_frame_size % SOC_ADC_DIGI_DATA_BYTES_PER_CONV; + if (calc_multiple != 0) { + adc_handle[adc_unit].conversion_frame_size = (adc_handle[adc_unit].conversion_frame_size + calc_multiple); + } +#endif + +#if CONFIG_IDF_TARGET_ESP32P4 + // Align conversion frame size to cache line size (required for DMA on targets with cache) + uint32_t alignment_remainder = adc_handle[adc_unit].conversion_frame_size % CONFIG_CACHE_L1_CACHE_LINE_SIZE; + if (alignment_remainder != 0) { + adc_handle[adc_unit].conversion_frame_size += (CONFIG_CACHE_L1_CACHE_LINE_SIZE - alignment_remainder); + } +#endif + + adc_handle[adc_unit].buffer_size = adc_handle[adc_unit].conversion_frame_size * 2; + + //Conversion frame size buffer cant be bigger than 4092 bytes + if (adc_handle[adc_unit].conversion_frame_size > 4092) { + log_e("Buffers are too big. Please set lower conversions per pin."); + return false; + } + + //Initialize continuous handle and pins + err = __analogContinuousInit(channel, sizeof(channel) / sizeof(adc_channel_t), adc_unit, sampling_freq_hz); + if (err != ESP_OK) { + log_e("Analog initialization failed!"); + return false; + } + + //Setup callbacks for complete event + adc_continuous_evt_cbs_t cbs = { + .on_conv_done = adcFnWrapper, + //.on_pool_ovf can be used in future + }; + adc_handle[adc_unit].adc_interrupt_handle.fn = (voidFuncPtr)userFunc; + err = adc_continuous_register_event_callbacks(adc_handle[adc_unit].adc_continuous_handle, &cbs, &adc_handle[adc_unit].adc_interrupt_handle); + if (err != ESP_OK) { + log_e("adc_continuous_register_event_callbacks failed!"); + return false; + } + + //Allocate and prepare result structure for adc readings + adc_result = malloc(pins_count * sizeof(adc_continuous_result_t)); + for (int k = 0; k < pins_count; k++) { + adc_result[k].pin = pins[k]; + adc_result[k].channel = channel[k]; + } + + //Initialize ADC calibration handle + if (adc_handle[adc_unit].adc_cali_handle == NULL) { + log_d("Creating cali handle for ADC_%d", adc_unit); +#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED + adc_cali_curve_fitting_config_t cali_config = { + .unit_id = adc_unit, + .atten = __adcContinuousAtten, + .bitwidth = __adcContinuousWidth, + }; + err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); +#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED + adc_cali_line_fitting_config_t cali_config = { + .unit_id = adc_unit, + .bitwidth = __adcContinuousWidth, + .atten = __adcContinuousAtten, + }; + err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle); +#else + log_e("ADC Calibration scheme is not supported!"); + return false; +#endif + if (err != ESP_OK) { + log_e("adc_cali_create_scheme_x failed!"); + return false; + } + } + + for (int k = 0; k < pins_count; k++) { + if (!perimanSetPinBus(pins[k], ESP32_BUS_TYPE_ADC_CONT, (void *)(adc_unit + 1), adc_unit, channel[k])) { + log_e("perimanSetPinBus to ADC Continuous failed!"); + adcContinuousDetachBus((void *)(adc_unit + 1)); + return false; + } + } + + return true; +} + +bool analogContinuousRead(adc_continuous_result_t **buffer, uint32_t timeout_ms) { + if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) { + uint32_t bytes_read = 0; + uint32_t read_raw[used_adc_channels]; + uint32_t read_count[used_adc_channels]; + + // Allocate DMA buffer with cache line alignment (required for ESP32-P4 and other targets with cache) + size_t buffer_size = adc_handle[ADC_UNIT_1].conversion_frame_size; +#if CONFIG_IDF_TARGET_ESP32P4 + uint8_t *adc_read = (uint8_t *)heap_caps_aligned_alloc(CONFIG_CACHE_L1_CACHE_LINE_SIZE, buffer_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); +#else + uint8_t *adc_read = (uint8_t *)heap_caps_malloc(buffer_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); +#endif + if (adc_read == NULL) { + log_e("Failed to allocate DMA buffer"); + *buffer = NULL; + return false; + } + + memset(adc_read, 0xcc, buffer_size); + memset(read_raw, 0, sizeof(read_raw)); + memset(read_count, 0, sizeof(read_count)); + + esp_err_t err = adc_continuous_read(adc_handle[ADC_UNIT_1].adc_continuous_handle, adc_read, adc_handle[0].conversion_frame_size, &bytes_read, timeout_ms); + if (err != ESP_OK) { + if (err == ESP_ERR_TIMEOUT) { + log_e("Reading data failed: No data, increase timeout"); + } else { + log_e("Reading data failed with error: %X", err); + } + free(adc_read); + adc_read = NULL; + *buffer = NULL; + return false; + } + + for (int i = 0; i < bytes_read; i += SOC_ADC_DIGI_RESULT_BYTES) { + adc_digi_output_data_t *p = (adc_digi_output_data_t *)&adc_read[i]; + uint32_t chan_num = ADC_GET_CHANNEL(p); + uint32_t data = ADC_GET_DATA(p); + + /* Check the channel number validation, the data is invalid if the channel num exceed the maximum channel */ + if (chan_num >= SOC_ADC_CHANNEL_NUM(0)) { + log_e("Invalid data [%d_%d]", chan_num, data); + *buffer = NULL; + return false; + } + if (data >= (1 << SOC_ADC_DIGI_MAX_BITWIDTH)) { + data = 0; + log_e("Invalid data"); + } + + for (int j = 0; j < used_adc_channels; j++) { + if (adc_result[j].channel == chan_num) { + read_raw[j] += data; + read_count[j] += 1; + break; + } + } + } + + for (int j = 0; j < used_adc_channels; j++) { + if (read_count[j] != 0) { + adc_result[j].avg_read_raw = read_raw[j] / read_count[j]; + adc_cali_raw_to_voltage(adc_handle[ADC_UNIT_1].adc_cali_handle, adc_result[j].avg_read_raw, &adc_result[j].avg_read_mvolts); + } else { + log_w("No data read for pin %d", adc_result[j].pin); + } + } + + free(adc_read); + adc_read = NULL; + *buffer = adc_result; + return true; + + } else { + log_e("ADC Continuous is not initialized!"); + return false; + } +} + +bool analogContinuousStart() { + if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) { + if (adc_continuous_start(adc_handle[ADC_UNIT_1].adc_continuous_handle) == ESP_OK) { + return true; + } + } else { + log_e("ADC Continuous is not initialized!"); + } + return false; +} + +bool analogContinuousStop() { + if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) { + if (adc_continuous_stop(adc_handle[ADC_UNIT_1].adc_continuous_handle) == ESP_OK) { + return true; + } + } else { + log_e("ADC Continuous is not initialized!"); + } + return false; +} + +bool analogContinuousDeinit() { + if (adc_handle[ADC_UNIT_1].adc_continuous_handle == NULL) { + log_i("ADC Continuous was not initialized"); + return true; + } + + // Clear all used pins from peripheral manager + // This will trigger adcContinuousDetachBus() callback which cleans up the ADC driver + for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1); channel++) { + int io_pin; + adc_oneshot_channel_to_io(ADC_UNIT_1, channel, &io_pin); + if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_CONT) { + if (!perimanClearPinBus(io_pin)) { + return false; + } + } + } + + // Free the result buffer (callback doesn't do this) + if (adc_result != NULL) { + free(adc_result); + adc_result = NULL; + } + + return true; +} + +void analogContinuousSetAtten(adc_attenuation_t attenuation) { + __adcContinuousAtten = attenuation; +} + +void analogContinuousSetWidth(uint8_t bits) { + if ((bits < SOC_ADC_DIGI_MIN_BITWIDTH) || (bits > SOC_ADC_DIGI_MAX_BITWIDTH)) { + log_e("Selected width cannot be set. Range is from %d to %d", SOC_ADC_DIGI_MIN_BITWIDTH, SOC_ADC_DIGI_MAX_BITWIDTH); + return; + } + __adcContinuousWidth = bits; +} + +#endif diff --git a/cores/esp32/esp32-hal-adc.h b/cores/esp32/esp32-hal-adc.h new file mode 100644 index 0000000..d22ac65 --- /dev/null +++ b/cores/esp32/esp32-hal-adc.h @@ -0,0 +1,133 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_ADC_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" + +typedef enum { + ADC_0db, + ADC_2_5db, + ADC_6db, + ADC_11db, + ADC_ATTENDB_MAX +} adc_attenuation_t; + +/* + * Get ADC value for pin + * */ +uint16_t analogRead(uint8_t pin); + +/* + * Get MilliVolts value for pin + * */ +uint32_t analogReadMilliVolts(uint8_t pin); + +/* + * Set the resolution of analogRead return values. Default is 12 bits (range from 0 to 4096). + * If between 9 and 12, it will equal the set hardware resolution, else value will be shifted. + * Range is 1 - 16 + * + * Note: compatibility with Arduino SAM + */ +void analogReadResolution(uint8_t bits); + +/* + * Set the attenuation for all channels + * Default is 11db + * */ +void analogSetAttenuation(adc_attenuation_t attenuation); + +/* + * Set the attenuation for particular pin + * Default is 11db + * */ +void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation); + +#if CONFIG_IDF_TARGET_ESP32 +/* + * Sets the sample bits and read resolution + * Default is 12bit (0 - 4095) + * Range is 9 - 12 + * */ +void analogSetWidth(uint8_t bits); + +#endif + +/* + * Analog Continuous mode + * */ + +typedef struct { + uint8_t pin; /*! + +#ifdef __cplusplus +extern "C" { +#endif + +// Flag defined in esp32-hal-bt.c, set by constructors when BT libraries are linked +extern bool _btLibraryInUse; + +// Constructor runs before app_main(), setting the flag if any BT library is used. +// Multiple libraries including this header just set the same flag to true. +__attribute__((constructor)) static void _setBtLibraryInUse(void) { + _btLibraryInUse = true; +} + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_BT_SUPPORTED */ + +#endif /* ESP32_HAL_BT_MEM_H */ diff --git a/cores/esp32/esp32-hal-bt.c b/cores/esp32/esp32-hal-bt.c new file mode 100644 index 0000000..00edc04 --- /dev/null +++ b/cores/esp32/esp32-hal-bt.c @@ -0,0 +1,133 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-bt.h" + +#if SOC_BT_SUPPORTED +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + +// Flag set by constructors in esp32-hal-bt-mem.h when BT libraries are linked +bool _btLibraryInUse = false; + +// Default behavior: release BTDM memory (~36KB) unless a BT library is used or user overrides. +// BT libraries include esp32-hal-bt-mem.h which sets _btLibraryInUse = true via constructor. +// Users can also provide their own strong btInUse() implementation. +__attribute__((weak)) bool btInUse(void) { + return _btLibraryInUse; +} + +#include "esp_bt.h" + +#ifdef CONFIG_BTDM_CONTROLLER_MODE_BTDM +#define BT_MODE ESP_BT_MODE_BTDM +#elif defined(CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY) +#define BT_MODE ESP_BT_MODE_CLASSIC_BT +#else +#define BT_MODE ESP_BT_MODE_BLE +#endif + +bool btStarted() { + return (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED); +} + +bool btStart() { + return btStartMode(BT_MODE); +} + +bool btStartMode(bt_mode mode) { + esp_bt_mode_t esp_bt_mode; + esp_bt_controller_config_t cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); +#if CONFIG_IDF_TARGET_ESP32 + switch (mode) { + case BT_MODE_BLE: esp_bt_mode = ESP_BT_MODE_BLE; break; + case BT_MODE_CLASSIC_BT: esp_bt_mode = ESP_BT_MODE_CLASSIC_BT; break; + case BT_MODE_BTDM: esp_bt_mode = ESP_BT_MODE_BTDM; break; + default: esp_bt_mode = BT_MODE; break; + } + // esp_bt_controller_enable(MODE) This mode must be equal as the mode in “cfg” of esp_bt_controller_init(). + cfg.mode = esp_bt_mode; + if (cfg.mode == ESP_BT_MODE_CLASSIC_BT) { + esp_bt_controller_mem_release(ESP_BT_MODE_BLE); + } +#else + // other esp variants dont support BT-classic / DM. + esp_bt_mode = BT_MODE; +#endif + + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) { + return true; + } + esp_err_t ret; + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) { + if ((ret = esp_bt_controller_init(&cfg)) != ESP_OK) { + log_e("initialize controller failed: %s", esp_err_to_name(ret)); + return false; + } + while (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) {} + } + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED) { + if ((ret = esp_bt_controller_enable(esp_bt_mode)) != ESP_OK) { + log_e("BT Enable mode=%d failed %s", BT_MODE, esp_err_to_name(ret)); + return false; + } + } + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) { + return true; + } + log_e("BT Start failed"); + return false; +} + +bool btStop() { + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) { + return true; + } + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) { + if (esp_bt_controller_disable()) { + log_e("BT Disable failed"); + return false; + } + while (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED); + } + if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED) { + if (esp_bt_controller_deinit()) { + log_e("BT deint failed"); + return false; + } + vTaskDelay(1); + if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_IDLE) { + return false; + } + return true; + } + log_e("BT Stop failed"); + return false; +} + +#else // !__has_include("esp_bt.h") || !(defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) +bool btStarted() { + return false; +} + +bool btStart() { + return false; +} + +bool btStop() { + return false; +} + +#endif /* !__has_include("esp_bt.h") || !(defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) */ + +#endif /* SOC_BT_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-bt.h b/cores/esp32/esp32-hal-bt.h new file mode 100644 index 0000000..98b21b2 --- /dev/null +++ b/cores/esp32/esp32-hal-bt.h @@ -0,0 +1,51 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_ESP32_HAL_BT_H_ +#define _ESP32_ESP32_HAL_BT_H_ + +#include "soc/soc_caps.h" +#if SOC_BT_SUPPORTED + +#include "esp32-hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + BT_MODE_DEFAULT, + BT_MODE_BLE, + BT_MODE_CLASSIC_BT, + BT_MODE_BTDM +} bt_mode; + +// Returns true if BT memory should be kept, false to release it (~36KB). +// Default (weak): returns false unless a BT library is linked. +// BT libraries include esp32-hal-bt-mem.h which automatically sets a flag. +// Users may also provide their own strong btInUse() to override. +bool btInUse(void); + +bool btStarted(); +bool btStart(); +bool btStartMode(bt_mode mode); +bool btStop(); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_BT_SUPPORTED */ + +#endif /* _ESP32_ESP32_HAL_BT_H_ */ diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c new file mode 100644 index 0000000..0df0093 --- /dev/null +++ b/cores/esp32/esp32-hal-cpu.c @@ -0,0 +1,335 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/task.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "soc/rtc.h" +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3) +#include "soc/rtc_cntl_reg.h" +#include "soc/syscon_reg.h" +#endif +#include "soc/efuse_reg.h" +#include "esp32-hal.h" +#include "esp32-hal-cpu.h" +#include "hal/timer_ll.h" +#include "esp_private/systimer.h" + +#include "esp_system.h" +#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "xtensa_timer.h" +#include "esp32/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "APLL"}; +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "xtensa_timer.h" +#include "esp32s2/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "APLL"}; +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "xtensa_timer.h" +#include "esp32s3/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"}; +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"}; +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"}; +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "17.5M"}; +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "PLL", "8.5M", "FLASH_PLL"}; +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "CPLL", "17.5M"}; +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "17.5M", "PLL_F160M", "PLL_F240M"}; +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/rtc.h" +static const char *clock_source_names[] = {"XTAL", "17.5M", "PLL_F160M"}; +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif +#else // ESP32 Before IDF 4.0 +#include "rom/rtc.h" +#endif + +typedef struct apb_change_cb_s { + struct apb_change_cb_s *prev; + struct apb_change_cb_s *next; + void *arg; + apb_change_cb_t cb; +} apb_change_t; + +static apb_change_t *apb_change_callbacks = NULL; +static SemaphoreHandle_t apb_change_lock = NULL; + +static void initApbChangeCallback() { + static volatile bool initialized = false; + if (!initialized) { + initialized = true; + apb_change_lock = xSemaphoreCreateMutex(); + if (!apb_change_lock) { + initialized = false; + } + } +} + +static void triggerApbChangeCallback(apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb) { + initApbChangeCallback(); + xSemaphoreTake(apb_change_lock, portMAX_DELAY); + apb_change_t *r = apb_change_callbacks; + if (r != NULL) { + if (ev_type == APB_BEFORE_CHANGE) { + while (r != NULL) { + r->cb(r->arg, ev_type, old_apb, new_apb); + r = r->next; + } + } else { // run backwards through chain + while (r->next != NULL) { + r = r->next; // find first added + } + while (r != NULL) { + r->cb(r->arg, ev_type, old_apb, new_apb); + r = r->prev; + } + } + } + xSemaphoreGive(apb_change_lock); +} + +bool addApbChangeCallback(void *arg, apb_change_cb_t cb) { + initApbChangeCallback(); + apb_change_t *c = (apb_change_t *)malloc(sizeof(apb_change_t)); + if (!c) { + log_e("Callback Object Malloc Failed"); + return false; + } + c->next = NULL; + c->prev = NULL; + c->arg = arg; + c->cb = cb; + xSemaphoreTake(apb_change_lock, portMAX_DELAY); + if (apb_change_callbacks == NULL) { + apb_change_callbacks = c; + } else { + apb_change_t *r = apb_change_callbacks; + // look for duplicate callbacks + while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) { + r = r->next; + } + if (r) { + log_e("duplicate func=%8p arg=%8p", c->cb, c->arg); + free(c); + xSemaphoreGive(apb_change_lock); + return false; + } else { + c->next = apb_change_callbacks; + apb_change_callbacks->prev = c; + apb_change_callbacks = c; + } + } + xSemaphoreGive(apb_change_lock); + return true; +} + +bool removeApbChangeCallback(void *arg, apb_change_cb_t cb) { + initApbChangeCallback(); + xSemaphoreTake(apb_change_lock, portMAX_DELAY); + apb_change_t *r = apb_change_callbacks; + // look for matching callback + while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) { + r = r->next; + } + if (r == NULL) { + log_e("not found func=%8p arg=%8p", cb, arg); + xSemaphoreGive(apb_change_lock); + return false; + } else { + // patch links + if (r->prev) { + r->prev->next = r->next; + } else { // this is first link + apb_change_callbacks = r->next; + } + if (r->next) { + r->next->prev = r->prev; + } + free(r); + } + xSemaphoreGive(apb_change_lock); + return true; +} + +static uint32_t calculateApb(rtc_cpu_freq_config_t *conf) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + if (conf->freq_mhz >= 80) { + return 80 * MHZ; + } + return (conf->source_freq_mhz * MHZ) / conf->div; +#else + return APB_CLK_FREQ; +#endif +} + +#if defined(CONFIG_IDF_TARGET_ESP32) && !defined(LACT_MODULE) && !defined(LACT_TICKS_PER_US) +void esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us); //private in IDF +#endif + +const char *getClockSourceName(uint8_t source) { + if (source < SOC_CPU_CLK_SRC_INVALID) { + return clock_source_names[source]; + } + + return "Invalid"; +} + +const char *getSupportedCpuFrequencyMhz(uint8_t xtal) { + char *supported_frequencies = (char *)calloc(256, sizeof(char)); + int pos = 0; + +#if TARGET_CPU_FREQ_MAX_400 +#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300 + pos += snprintf(supported_frequencies + pos, 256 - pos, "360"); +#else + pos += snprintf(supported_frequencies + pos, 256 - pos, "400"); +#endif +#elif TARGET_CPU_FREQ_MAX_240 +#if CONFIG_IDF_TARGET_ESP32 + if (!REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) || !REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { + pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 80"); + } else +#endif + { + pos += snprintf(supported_frequencies + pos, 256 - pos, "240, 160, 80"); + } +#elif TARGET_CPU_FREQ_MAX_160 + pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 120, 80"); +#elif TARGET_CPU_FREQ_MAX_120 + pos += snprintf(supported_frequencies + pos, 256 - pos, "120, 80"); +#elif TARGET_CPU_FREQ_MAX_96 + pos += snprintf(supported_frequencies + pos, 256 - pos, "96, 64, 48"); +#else + free(supported_frequencies); + return "Unknown"; +#endif + + // Append xtal and its dividers only if xtal is nonzero + if (xtal != 0) { + // We'll show as: , , [, ] MHz + pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u, %u", xtal, xtal / 2); + +#if CONFIG_IDF_TARGET_ESP32 + // Only append xtal/4 if it's > 0 and meaningful for higher-frequency chips (e.g., ESP32 40MHz/4=10) + if (xtal >= RTC_XTAL_FREQ_40M) { + pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u", xtal / 4); + } +#endif + } + + pos += snprintf(supported_frequencies + pos, 256 - pos, " MHz"); + return supported_frequencies; +} + +bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) { + rtc_cpu_freq_config_t conf, cconf; + uint32_t capb, apb; + [[maybe_unused]] + uint8_t xtal = 0; + + // ===== Get XTAL Frequency and validate input ===== +#if TARGET_HAS_XTAL_FREQ + xtal = (uint8_t)rtc_clk_xtal_freq_get(); +#endif + + // ===== Get current configuration and check if change is needed ===== + rtc_clk_cpu_freq_get_config(&cconf); + if (cconf.freq_mhz == cpu_freq_mhz) { + return true; // Frequency already set + } + + // ===== Get configuration for new frequency ===== + if (!rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &conf)) { + log_e("CPU clock could not be set to %u MHz. Supported frequencies: %s", cpu_freq_mhz, getSupportedCpuFrequencyMhz(xtal)); + return false; + } + + // ===== Calculate APB frequencies ===== + capb = calculateApb(&cconf); + apb = calculateApb(&conf); + + // ===== Apply frequency change ===== + if (apb_change_callbacks) { + triggerApbChangeCallback(APB_BEFORE_CHANGE, capb, apb); + } + + rtc_clk_cpu_freq_set_config_fast(&conf); + + // Update APB frequency for targets with dynamic APB +#if TARGET_HAS_DYNAMIC_APB + if (capb != apb) { + // Update REF_TICK (uncomment if REF_TICK is different than 1MHz) + // if (conf.freq_mhz < 80) { + // ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1; + // } + rtc_clk_apb_freq_update(apb); + + // ESP32-specific: Update esp_timer divisor +#if CONFIG_IDF_TARGET_ESP32 +#if defined(LACT_MODULE) && defined(LACT_TICKS_PER_US) + timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), apb / MHZ / LACT_TICKS_PER_US); +#else + esp_timer_impl_update_apb_freq(apb / MHZ); +#endif +#endif + } +#endif + + // Update FreeRTOS Tick Divisor for Xtensa targets +#if TARGET_HAS_XTENSA_TICK + uint32_t fcpu = (conf.freq_mhz >= 80) ? (conf.freq_mhz * MHZ) : (apb); + _xt_tick_divisor = fcpu / XT_TICK_PER_SEC; +#endif + + if (apb_change_callbacks) { + triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb); + } + + // ===== Debug logging ===== + log_d("%s: %u / %u = %u Mhz, APB: %u Hz", getClockSourceName(conf.source), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb); + + return true; +} + +uint32_t getCpuFrequencyMhz() { + rtc_cpu_freq_config_t conf; + rtc_clk_cpu_freq_get_config(&conf); + return conf.freq_mhz; +} + +uint32_t getXtalFrequencyMhz() { + return rtc_clk_xtal_freq_get(); +} + +uint32_t getApbFrequency() { + rtc_cpu_freq_config_t conf; + rtc_clk_cpu_freq_get_config(&conf); + return calculateApb(&conf); +} diff --git a/cores/esp32/esp32-hal-cpu.h b/cores/esp32/esp32-hal-cpu.h new file mode 100644 index 0000000..dfae106 --- /dev/null +++ b/cores/esp32/esp32-hal-cpu.h @@ -0,0 +1,119 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_CPU_H_ +#define _ESP32_HAL_CPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +// When adding a new target, update the appropriate group(s) below + +// Targets that support XTAL frequency queries via rtc_clk_xtal_freq_get() +#if (!defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_HAS_XTAL_FREQ 1 +#else +#define TARGET_HAS_XTAL_FREQ 0 +#endif + +// Targets that need dynamic APB frequency updates via rtc_clk_apb_freq_update() +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3)) +#define TARGET_HAS_DYNAMIC_APB 1 +#else +#define TARGET_HAS_DYNAMIC_APB 0 +#endif + +// Xtensa architecture targets that need FreeRTOS tick divisor updates +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2)) +#define TARGET_HAS_XTENSA_TICK 1 +#else +#define TARGET_HAS_XTENSA_TICK 0 +#endif + +// Targets with APLL support (uses IDF SOC capability macro) +// Note: ESP32-P4 APLL support is not yet fully implemented in IDF +#if (defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_HAS_APLL 1 +#else +#define TARGET_HAS_APLL 0 +#endif + +// Targets grouped by maximum CPU frequency support + +#if (defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_CPU_FREQ_MAX_400 1 +#else +#define TARGET_CPU_FREQ_MAX_400 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32C5) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)) +#define TARGET_CPU_FREQ_MAX_240 1 +#else +#define TARGET_CPU_FREQ_MAX_240 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61)) +#define TARGET_CPU_FREQ_MAX_160 1 +#else +#define TARGET_CPU_FREQ_MAX_160 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32C2)) +#define TARGET_CPU_FREQ_MAX_120 1 +#else +#define TARGET_CPU_FREQ_MAX_120 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32H2)) +#define TARGET_CPU_FREQ_MAX_96 1 +#else +#define TARGET_CPU_FREQ_MAX_96 0 +#endif + +typedef enum { + APB_BEFORE_CHANGE, + APB_AFTER_CHANGE +} apb_change_ev_t; + +typedef void (*apb_change_cb_t)(void *arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb); + +bool addApbChangeCallback(void *arg, apb_change_cb_t cb); +bool removeApbChangeCallback(void *arg, apb_change_cb_t cb); + +//function takes the following frequencies as valid values: +// 240, 160, 80 <<< For all XTAL types +// 40, 20, 10 <<< For 40MHz XTAL +// 26, 13 <<< For 26MHz XTAL +// 24, 12 <<< For 24MHz XTAL +bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz); + +const char *getSupportedCpuFrequencyMhz(uint8_t xtal); +const char *getClockSourceName(uint8_t source); +uint32_t getCpuFrequencyMhz(); // In MHz +uint32_t getXtalFrequencyMhz(); // In MHz +uint32_t getApbFrequency(); // In Hz + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_CPU_H_ */ diff --git a/cores/esp32/esp32-hal-dac.c b/cores/esp32/esp32-hal-dac.c new file mode 100644 index 0000000..267f9cd --- /dev/null +++ b/cores/esp32/esp32-hal-dac.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32-hal-dac.h" + +#if SOC_DAC_SUPPORTED +#include "esp32-hal.h" +#include "esp32-hal-periman.h" +#include "soc/dac_channel.h" +#include "driver/dac_oneshot.h" + +static bool dacDetachBus(void *bus) { + esp_err_t err = dac_oneshot_del_channel((dac_oneshot_handle_t)bus); + if (err != ESP_OK) { + log_e("dac_oneshot_del_channel failed with error: %d", err); + return false; + } + return true; +} + +bool __dacWrite(uint8_t pin, uint8_t value) { + esp_err_t err = ESP_OK; + if (pin != DAC_CHAN0_GPIO_NUM && pin != DAC_CHAN1_GPIO_NUM) { + log_e("pin %u is not a DAC pin", pin); + return false; //not dac pin + } + + dac_oneshot_handle_t bus = (dac_oneshot_handle_t)perimanGetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT); + if (bus == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_DAC_ONESHOT, dacDetachBus); + if (!perimanClearPinBus(pin)) { + return false; + } + dac_channel_t channel = (pin == DAC_CHAN0_GPIO_NUM) ? DAC_CHAN_0 : DAC_CHAN_1; + dac_oneshot_config_t config = {.chan_id = channel}; + err = dac_oneshot_new_channel(&config, &bus); + if (err != ESP_OK) { + log_e("dac_oneshot_new_channel failed with error: %d", err); + return false; + } + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT, (void *)bus, -1, channel)) { + dacDetachBus((void *)bus); + return false; + } + } + + err = dac_oneshot_output_voltage(bus, value); + if (err != ESP_OK) { + log_e("dac_oneshot_output_voltage failed with error: %d", err); + return false; + } + return true; +} + +bool __dacDisable(uint8_t pin) { + if (pin != DAC_CHAN0_GPIO_NUM && pin != DAC_CHAN1_GPIO_NUM) { + log_e("pin %u is not a DAC pin", pin); + return false; //not dac pin + } + void *bus = perimanGetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT); + if (bus != NULL) { + // will call dacDetachBus + return perimanClearPinBus(pin); + } else { + log_e("pin %u is not attached to DAC", pin); + } + return false; +} + +extern bool dacWrite(uint8_t pin, uint8_t value) __attribute__((weak, alias("__dacWrite"))); +extern bool dacDisable(uint8_t pin) __attribute__((weak, alias("__dacDisable"))); + +#endif diff --git a/cores/esp32/esp32-hal-dac.h b/cores/esp32/esp32-hal-dac.h new file mode 100644 index 0000000..113354b --- /dev/null +++ b/cores/esp32/esp32-hal-dac.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_DAC_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +bool dacWrite(uint8_t pin, uint8_t value); +bool dacDisable(uint8_t pin); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_DAC_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-gpio.c b/cores/esp32/esp32-hal-gpio.c new file mode 100644 index 0000000..4a7fe6d --- /dev/null +++ b/cores/esp32/esp32-hal-gpio.c @@ -0,0 +1,284 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-gpio.h" +#include "esp32-hal-periman.h" +#include "hal/gpio_hal.h" +#include "soc/soc_caps.h" + +// RGB_BUILTIN is defined in pins_arduino.h +// If RGB_BUILTIN is defined, it will be used as a pin number for the RGB LED +// If RGB_BUILTIN has a side effect that prevents using RMT Legacy driver in IDF 5.1 +// Define ESP32_ARDUINO_NO_RGB_BUILTIN in build_opt.h or through CLI to disable RGB_BUILTIN +#ifdef ESP32_ARDUINO_NO_RGB_BUILTIN +#ifdef RGB_BUILTIN +#undef RGB_BUILTIN +#endif +#endif + +// It fixes lack of pin definition for S3 and for any future SoC +// this function works for ESP32, ESP32-S2 and ESP32-S3 - including the C3, it will return -1 for any pin +#if SOC_TOUCH_SENSOR_NUM > 0 +#include "soc/touch_sensor_periph.h" + +int8_t digitalPinToTouchChannel(uint8_t pin) { + if (pin < SOC_GPIO_PIN_COUNT) { + for (uint8_t i = 0; i < SOC_TOUCH_SENSOR_NUM; i++) { + if (touch_sensor_channel_io_map[i] == pin) { + return i; + } + } + } + + log_e("No touch pad on selected pin(%u)!", pin); + return -1; +} +#else +// No Touch Sensor available +int8_t digitalPinToTouchChannel(uint8_t pin) { + log_e("Touch sensor not available on this chip"); + return -1; +} +#endif + +#ifdef SOC_ADC_SUPPORTED +#include "soc/adc_periph.h" + +int8_t digitalPinToAnalogChannel(uint8_t pin) { + uint8_t channel = 0; + if (pin < SOC_GPIO_PIN_COUNT) { + for (uint8_t i = 0; i < SOC_ADC_PERIPH_NUM; i++) { + for (uint8_t j = 0; j < SOC_ADC_MAX_CHANNEL_NUM; j++) { + if (adc_channel_io_map[i][j] == pin) { + return channel; + } + channel++; + } + } + } + return -1; +} + +int8_t analogChannelToDigitalPin(uint8_t channel) { + if (channel >= (SOC_ADC_PERIPH_NUM * SOC_ADC_MAX_CHANNEL_NUM)) { + return -1; + } + uint8_t adc_unit = (channel / SOC_ADC_MAX_CHANNEL_NUM); + uint8_t adc_chan = (channel % SOC_ADC_MAX_CHANNEL_NUM); + return adc_channel_io_map[adc_unit][adc_chan]; +} +#else +// No Analog channels available +int8_t analogChannelToDigitalPin(uint8_t channel) { + return -1; +} +#endif + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void *); +typedef struct { + voidFuncPtr fn; + void *arg; + bool functional; +} InterruptHandle_t; +static InterruptHandle_t __pinInterruptHandlers[SOC_GPIO_PIN_COUNT] = { + 0, +}; + +#include "driver/rtc_io.h" + +static bool gpioDetachBus(void *bus) { + return true; +} + +extern void ARDUINO_ISR_ATTR __pinMode(uint8_t pin, uint8_t mode) { +#ifdef RGB_BUILTIN + if (pin == RGB_BUILTIN) { + __pinMode(RGB_BUILTIN - SOC_GPIO_PIN_COUNT, mode); + return; + } +#endif + + if (pin >= SOC_GPIO_PIN_COUNT) { + log_e("Invalid IO %i selected", pin); + return; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_GPIO, gpioDetachBus); + if (!perimanClearPinBus(pin)) { + log_e("Deinit of previous bus from IO %i failed", pin); + return; + } + } + + gpio_hal_context_t gpiohal; + gpiohal.dev = GPIO_LL_GET_HW(GPIO_PORT_0); + + gpio_config_t conf = { + .pin_bit_mask = (1ULL << pin), /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */ + .mode = GPIO_MODE_DISABLE, /*!< GPIO mode: set input/output mode */ + .pull_up_en = GPIO_PULLUP_DISABLE, /*!< GPIO pull-up */ + .pull_down_en = GPIO_PULLDOWN_DISABLE, /*!< GPIO pull-down */ +#ifndef CONFIG_IDF_TARGET_ESP32C61 + .intr_type = gpiohal.dev->pin[pin].int_type /*!< GPIO interrupt type - previously set */ +#else + .intr_type = gpiohal.dev->pinn[pin].pinn_int_type /*!< GPIO interrupt type - previously set */ +#endif + }; + if (mode < 0x20) { //io + conf.mode = mode & (INPUT | OUTPUT); + if (mode & OPEN_DRAIN) { + conf.mode |= GPIO_MODE_DEF_OD; + } + if (mode & PULLUP) { + conf.pull_up_en = GPIO_PULLUP_ENABLE; + } + if (mode & PULLDOWN) { + conf.pull_down_en = GPIO_PULLDOWN_ENABLE; + } + } + if (gpio_config(&conf) != ESP_OK) { + log_e("IO %i config failed", pin); + return; + } + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) { + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_GPIO, (void *)(pin + 1), -1, -1)) { + //gpioDetachBus((void *)(pin+1)); + return; + } + } +} + +#ifdef RGB_BUILTIN +uint8_t RGB_BUILTIN_storage = 0; +#endif + +extern void ARDUINO_ISR_ATTR __digitalWrite(uint8_t pin, uint8_t val) { +#ifdef RGB_BUILTIN + if (pin == RGB_BUILTIN) { + //use RMT to set all channels on/off + RGB_BUILTIN_storage = val; + const uint8_t comm_val = val != 0 ? RGB_BRIGHTNESS : 0; + rgbLedWrite(RGB_BUILTIN, comm_val, comm_val, comm_val); + return; + } +#endif // RGB_BUILTIN + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) != NULL) { + gpio_set_level((gpio_num_t)pin, val); + } else { + log_e("IO %i is not set as GPIO. Execute digitalMode(%i, OUTPUT) first.", pin, pin); + } +} + +extern int ARDUINO_ISR_ATTR __digitalRead(uint8_t pin) { +#ifdef RGB_BUILTIN + if (pin == RGB_BUILTIN) { + return RGB_BUILTIN_storage; + } +#endif // RGB_BUILTIN + // This work when the pin is set as GPIO and in INPUT mode. For all other pin functions, it may return inconsistent response + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) { + log_w("IO %i is not set as GPIO. digitalRead() may return an inconsistent value.", pin); + } + return gpio_get_level((gpio_num_t)pin); +} + +static void ARDUINO_ISR_ATTR __onPinInterrupt(void *arg) { + InterruptHandle_t *isr = (InterruptHandle_t *)arg; + if (isr->fn) { + if (isr->arg) { + ((voidFuncPtrArg)isr->fn)(isr->arg); + } else { + isr->fn(); + } + } +} + +extern void cleanupFunctional(void *arg); + +extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type, bool functional) { + static bool interrupt_initialized = false; + + // makes sure that pin -1 (255) will never work -- this follows Arduino standard + if (pin >= SOC_GPIO_PIN_COUNT) { + return; + } + + if (!interrupt_initialized) { + esp_err_t err = gpio_install_isr_service((int)ARDUINO_ISR_FLAG); + interrupt_initialized = (err == ESP_OK) || (err == ESP_ERR_INVALID_STATE); + } + if (!interrupt_initialized) { + log_e("IO %i ISR Service Failed To Start", pin); + return; + } + + // if new attach without detach remove old info + if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg) { + cleanupFunctional(__pinInterruptHandlers[pin].arg); + } + __pinInterruptHandlers[pin].fn = (voidFuncPtr)userFunc; + __pinInterruptHandlers[pin].arg = arg; + __pinInterruptHandlers[pin].functional = functional; + + gpio_set_intr_type((gpio_num_t)pin, (gpio_int_type_t)(intr_type & 0x7)); + if (intr_type & 0x8) { + gpio_wakeup_enable((gpio_num_t)pin, (gpio_int_type_t)(intr_type & 0x7)); + } + gpio_isr_handler_add((gpio_num_t)pin, __onPinInterrupt, &__pinInterruptHandlers[pin]); + + //FIX interrupts on peripherals outputs (eg. LEDC,...) + //Enable input in GPIO register + gpio_hal_context_t gpiohal; + gpiohal.dev = GPIO_LL_GET_HW(GPIO_PORT_0); + gpio_hal_input_enable(&gpiohal, pin); +} + +extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type) { + __attachInterruptFunctionalArg(pin, userFunc, arg, intr_type, false); +} + +extern void __attachInterrupt(uint8_t pin, voidFuncPtr userFunc, int intr_type) { + __attachInterruptFunctionalArg(pin, (voidFuncPtrArg)userFunc, NULL, intr_type, false); +} + +extern void __detachInterrupt(uint8_t pin) { + gpio_isr_handler_remove((gpio_num_t)pin); //remove handle and disable isr for pin + gpio_wakeup_disable((gpio_num_t)pin); + + if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg) { + cleanupFunctional(__pinInterruptHandlers[pin].arg); + } + __pinInterruptHandlers[pin].fn = NULL; + __pinInterruptHandlers[pin].arg = NULL; + __pinInterruptHandlers[pin].functional = false; + + gpio_set_intr_type((gpio_num_t)pin, GPIO_INTR_DISABLE); +} + +extern void enableInterrupt(uint8_t pin) { + gpio_intr_enable((gpio_num_t)pin); +} + +extern void disableInterrupt(uint8_t pin) { + gpio_intr_disable((gpio_num_t)pin); +} + +extern void pinMode(uint8_t pin, uint8_t mode) __attribute__((weak, alias("__pinMode"))); +extern void digitalWrite(uint8_t pin, uint8_t val) __attribute__((weak, alias("__digitalWrite"))); +extern int digitalRead(uint8_t pin) __attribute__((weak, alias("__digitalRead"))); +extern void attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode) __attribute__((weak, alias("__attachInterrupt"))); +extern void attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void *arg, int mode) __attribute__((weak, alias("__attachInterruptArg"))); +extern void detachInterrupt(uint8_t pin) __attribute__((weak, alias("__detachInterrupt"))); diff --git a/cores/esp32/esp32-hal-gpio.h b/cores/esp32/esp32-hal-gpio.h new file mode 100644 index 0000000..9fce436 --- /dev/null +++ b/cores/esp32/esp32-hal-gpio.h @@ -0,0 +1,92 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_GPIO_H_ +#define MAIN_ESP32_HAL_GPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pins_arduino.h" +#include "esp32-hal.h" +#include "soc/soc_caps.h" +#include "driver/gpio.h" + +#if (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3) +#define NUM_OUPUT_PINS 46 +#define PIN_DAC1 17 +#define PIN_DAC2 18 +#else +#define NUM_OUPUT_PINS 34 +#define PIN_DAC1 25 +#define PIN_DAC2 26 +#endif + +#define LOW 0x0 +#define HIGH 0x1 + +//GPIO FUNCTIONS +#define INPUT 0x01 +// Changed OUTPUT from 0x02 to behave the same as Arduino pinMode(pin,OUTPUT) +// where you can read the state of pin even when it is set as OUTPUT +#define OUTPUT 0x03 +#define PULLUP 0x04 +#define INPUT_PULLUP 0x05 +#define PULLDOWN 0x08 +#define INPUT_PULLDOWN 0x09 +#define OPEN_DRAIN 0x10 +#define OUTPUT_OPEN_DRAIN 0x13 +#define ANALOG 0xC0 + +//Interrupt Modes +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 +#define ONLOW_WE 0x0C +#define ONHIGH_WE 0x0D + +#define digitalPinIsValid(pin) GPIO_IS_VALID_GPIO(pin) +#define digitalPinCanOutput(pin) GPIO_IS_VALID_OUTPUT_GPIO(pin) + +#define digitalPinToRtcPin(pin) ((RTC_GPIO_IS_VALID_GPIO(pin)) ? rtc_io_number_get(pin) : -1) +#define digitalPinToDacChannel(pin) (((pin) == DAC_CHANNEL_1_GPIO_NUM) ? 0 : ((pin) == DAC_CHANNEL_2_GPIO_NUM) ? 1 : -1) + +void pinMode(uint8_t pin, uint8_t mode); +void digitalWrite(uint8_t pin, uint8_t val); +int digitalRead(uint8_t pin); + +void attachInterrupt(uint8_t pin, void (*)(void), int mode); +void attachInterruptArg(uint8_t pin, void (*)(void *), void *arg, int mode); +void detachInterrupt(uint8_t pin); +void enableInterrupt(uint8_t pin); +void disableInterrupt(uint8_t pin); + +int8_t digitalPinToTouchChannel(uint8_t pin); +int8_t digitalPinToAnalogChannel(uint8_t pin); +int8_t analogChannelToDigitalPin(uint8_t channel); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_GPIO_H_ */ diff --git a/cores/esp32/esp32-hal-hosted.c b/cores/esp32/esp32-hal-hosted.c new file mode 100644 index 0000000..8a18969 --- /dev/null +++ b/cores/esp32/esp32-hal-hosted.c @@ -0,0 +1,365 @@ +// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "sdkconfig.h" +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) || defined(CONFIG_ESP_WIFI_REMOTE_ENABLED) + +#include "esp32-hal-hosted.h" +#include "esp32-hal-log.h" +#include "esp32-hal.h" +#include "pins_arduino.h" + +#include "esp_hosted.h" +#include "esp_hosted_transport_config.h" +// extern esp_err_t esp_hosted_init(); +// extern esp_err_t esp_hosted_deinit(); + +static bool hosted_initialized = false; +static bool hosted_ble_active = false; +static bool hosted_wifi_active = false; + +static sdio_pin_config_t sdio_pin_config = { +#ifdef BOARD_HAS_SDIO_ESP_HOSTED + .pin_clk = BOARD_SDIO_ESP_HOSTED_CLK, + .pin_cmd = BOARD_SDIO_ESP_HOSTED_CMD, + .pin_d0 = BOARD_SDIO_ESP_HOSTED_D0, + .pin_d1 = BOARD_SDIO_ESP_HOSTED_D1, + .pin_d2 = BOARD_SDIO_ESP_HOSTED_D2, + .pin_d3 = BOARD_SDIO_ESP_HOSTED_D3, + .pin_reset = BOARD_SDIO_ESP_HOSTED_RESET +#else + .pin_clk = CONFIG_ESP_SDIO_PIN_CLK, + .pin_cmd = CONFIG_ESP_SDIO_PIN_CMD, + .pin_d0 = CONFIG_ESP_SDIO_PIN_D0, + .pin_d1 = CONFIG_ESP_SDIO_PIN_D1, + .pin_d2 = CONFIG_ESP_SDIO_PIN_D2, + .pin_d3 = CONFIG_ESP_SDIO_PIN_D3, + .pin_reset = CONFIG_ESP_SDIO_GPIO_RESET_SLAVE +#endif +}; + +static esp_hosted_coprocessor_fwver_t slave_version_struct = {.major1 = 0, .minor1 = 0, .patch1 = 0}; +static esp_hosted_coprocessor_fwver_t host_version_struct = { + .major1 = ESP_HOSTED_VERSION_MAJOR_1, .minor1 = ESP_HOSTED_VERSION_MINOR_1, .patch1 = ESP_HOSTED_VERSION_PATCH_1 +}; + +static bool hostedInit(); +static bool hostedDeinit(); + +void hostedGetHostVersion(uint32_t *major, uint32_t *minor, uint32_t *patch) { + *major = host_version_struct.major1; + *minor = host_version_struct.minor1; + *patch = host_version_struct.patch1; +} + +void hostedGetSlaveVersion(uint32_t *major, uint32_t *minor, uint32_t *patch) { + *major = slave_version_struct.major1; + *minor = slave_version_struct.minor1; + *patch = slave_version_struct.patch1; +} + +bool hostedHasUpdate() { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + uint32_t host_version = ESP_HOSTED_VERSION_VAL(host_version_struct.major1, host_version_struct.minor1, host_version_struct.patch1); + uint32_t slave_version = 0; + + esp_err_t ret = esp_hosted_get_coprocessor_fwversion(&slave_version_struct); + if (ret != ESP_OK) { + log_e("Could not get slave firmware version: %s", esp_err_to_name(ret)); + } else { + slave_version = ESP_HOSTED_VERSION_VAL(slave_version_struct.major1, slave_version_struct.minor1, slave_version_struct.patch1); + } + + log_i("Host firmware version: %" PRIu32 ".%" PRIu32 ".%" PRIu32, host_version_struct.major1, host_version_struct.minor1, host_version_struct.patch1); + log_i("Slave firmware version: %" PRIu32 ".%" PRIu32 ".%" PRIu32, slave_version_struct.major1, slave_version_struct.minor1, slave_version_struct.patch1); + + // compare major.minor only + // slave_version &= 0xFFFFFF00; + // host_version &= 0xFFFFFF00; + + if (host_version == slave_version) { + log_i("Versions Match!"); + } else if (host_version > slave_version) { + log_w("Version on Host is NEWER than version on co-processor"); + log_w("Update URL: %s", hostedGetUpdateURL()); + return true; + } else { + log_w("Version on Host is OLDER than version on co-processor"); + } + return false; +} + +char *hostedGetUpdateURL() { + // https://espressif.github.io/arduino-esp32/hosted/esp32c6-v1.2.3.bin + static char url[92] = {0}; + snprintf( + url, 92, "https://espressif.github.io/arduino-esp32/hosted/%s-v%" PRIu32 ".%" PRIu32 ".%" PRIu32 ".bin", CONFIG_ESP_HOSTED_IDF_SLAVE_TARGET, + host_version_struct.major1, host_version_struct.minor1, host_version_struct.patch1 + ); + return url; +} + +bool hostedBeginUpdate() { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + esp_err_t err = esp_hosted_slave_ota_begin(); + if (err != ESP_OK) { + log_e("Failed to begin Update: %s", esp_err_to_name(err)); + } + return err == ESP_OK; +} + +bool hostedWriteUpdate(uint8_t *buf, uint32_t len) { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + esp_err_t err = esp_hosted_slave_ota_write(buf, len); + if (err != ESP_OK) { + log_e("Failed to write Update: %s", esp_err_to_name(err)); + } + return err == ESP_OK; +} + +bool hostedEndUpdate() { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + esp_err_t err = esp_hosted_slave_ota_end(); + if (err != ESP_OK) { + log_e("Failed to end Update: %s", esp_err_to_name(err)); + } + return err == ESP_OK; +} + +bool hostedActivateUpdate() { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + // Activate can fail on older firmwares and that is not critical + uint32_t slave_version = ESP_HOSTED_VERSION_VAL(slave_version_struct.major1, slave_version_struct.minor1, slave_version_struct.patch1); + uint32_t min_version = ESP_HOSTED_VERSION_VAL(2, 6, 0); + + if (slave_version < min_version) { + // Silence messages caused by earlier versions + esp_log_level_set("rpc_core", ESP_LOG_NONE); + } + + esp_err_t err = esp_hosted_slave_ota_activate(); + + // Any further communication will result in logged errors + esp_log_level_set("sdmmc_io", ESP_LOG_NONE); + esp_log_level_set("H_SDIO_DRV", ESP_LOG_NONE); + + if (err != ESP_OK && slave_version >= min_version) { + log_e("Failed to activate Update: %s", esp_err_to_name(err)); + return false; + } + return true; +} + +static bool hostedInit() { + if (!hosted_initialized) { + log_i("Initializing ESP-Hosted"); + log_d( + "SDIO pins: clk=%d, cmd=%d, d0=%d, d1=%d, d2=%d, d3=%d, rst=%d", sdio_pin_config.pin_clk, sdio_pin_config.pin_cmd, sdio_pin_config.pin_d0, + sdio_pin_config.pin_d1, sdio_pin_config.pin_d2, sdio_pin_config.pin_d3, sdio_pin_config.pin_reset + ); + hosted_initialized = true; + struct esp_hosted_sdio_config conf = INIT_DEFAULT_HOST_SDIO_CONFIG(); + conf.pin_clk.pin = sdio_pin_config.pin_clk; + conf.pin_cmd.pin = sdio_pin_config.pin_cmd; + conf.pin_d0.pin = sdio_pin_config.pin_d0; + conf.pin_d1.pin = sdio_pin_config.pin_d1; + conf.pin_d2.pin = sdio_pin_config.pin_d2; + conf.pin_d3.pin = sdio_pin_config.pin_d3; + conf.pin_reset.pin = sdio_pin_config.pin_reset; + esp_err_t err = esp_hosted_sdio_set_config(&conf); + if (err != ESP_OK) { //&& err != ESP_ERR_NOT_ALLOWED) { // uncomment when second init is fixed + log_e("esp_hosted_sdio_set_config failed: %s", esp_err_to_name(err)); + return false; + } + err = esp_hosted_init(); + if (err != ESP_OK) { + log_e("esp_hosted_init failed: %s", esp_err_to_name(err)); + hosted_initialized = false; + return false; + } + log_i("ESP-Hosted initialized!"); + err = esp_hosted_connect_to_slave(); + if (err != ESP_OK) { + log_e("esp_hosted_connect_to_slave failed: %s", esp_err_to_name(err)); + hosted_initialized = false; + return false; + } + hostedHasUpdate(); + return true; + } + + // Attach pins to PeriMan here + // Slave chip model is CONFIG_IDF_SLAVE_TARGET + // sdio_pin_config.pin_clk + // sdio_pin_config.pin_cmd + // sdio_pin_config.pin_d0 + // sdio_pin_config.pin_d1 + // sdio_pin_config.pin_d2 + // sdio_pin_config.pin_d3 + // sdio_pin_config.pin_reset + + return true; +} + +static bool hostedDeinit() { + if (!hosted_initialized) { + log_e("ESP-Hosted is not initialized"); + return false; + } + + if (esp_hosted_deinit() != ESP_OK) { + log_e("esp_hosted_deinit failed!"); + return false; + } + + hosted_initialized = false; + return true; +} + +bool hostedInitBLE() { + log_i("Initializing ESP-Hosted for BLE"); + if (!hostedInit()) { + return false; + } + + uint32_t slave_version = ESP_HOSTED_VERSION_VAL(slave_version_struct.major1, slave_version_struct.minor1, slave_version_struct.patch1); + uint32_t min_version = ESP_HOSTED_VERSION_VAL(2, 6, 0); + if (slave_version >= min_version) { + esp_err_t err = esp_hosted_bt_controller_init(); + if (err != ESP_OK) { + log_e("esp_hosted_bt_controller_init failed: %s", esp_err_to_name(err)); + return false; + } + err = esp_hosted_bt_controller_enable(); + if (err != ESP_OK) { + log_e("esp_hosted_bt_controller_enable failed: %s", esp_err_to_name(err)); + return false; + } + } + hosted_ble_active = true; + return true; +} + +bool hostedInitWiFi() { + log_i("Initializing ESP-Hosted for WiFi"); + hosted_wifi_active = true; + return hostedInit(); +} + +bool hostedDeinitBLE() { + log_i("Deinitializing ESP-Hosted for BLE"); + uint32_t slave_version = ESP_HOSTED_VERSION_VAL(slave_version_struct.major1, slave_version_struct.minor1, slave_version_struct.patch1); + uint32_t min_version = ESP_HOSTED_VERSION_VAL(2, 6, 0); + if (slave_version >= min_version) { + esp_err_t err = esp_hosted_bt_controller_disable(); + if (err != ESP_OK) { + log_e("esp_hosted_bt_controller_disable failed: %s", esp_err_to_name(err)); + return false; + } + err = esp_hosted_bt_controller_deinit(false); + if (err != ESP_OK) { + log_e("esp_hosted_bt_controller_deinit failed: %s", esp_err_to_name(err)); + return false; + } + } + hosted_ble_active = false; + if (!hosted_wifi_active) { + return hostedDeinit(); + } else { + log_i("ESP-Hosted is still being used by Wi-Fi. Skipping deinit."); + return true; + } +} + +bool hostedDeinitWiFi() { + log_i("Deinitializing ESP-Hosted for WiFi"); + hosted_wifi_active = false; + if (!hosted_ble_active) { + return hostedDeinit(); + } else { + log_i("ESP-Hosted is still being used by BLE. Skipping deinit."); + return true; + } +} + +bool hostedSetPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst) { + if (clk < 0 || cmd < 0 || d0 < 0 || d1 < 0 || d2 < 0 || d3 < 0 || rst < 0) { + log_e("All SDIO pins must be defined"); + return false; + } + + if (hosted_initialized) { + int8_t current_clk, current_cmd, current_d0, current_d1, current_d2, current_d3, current_rst; + hostedGetPins(¤t_clk, ¤t_cmd, ¤t_d0, ¤t_d1, ¤t_d2, ¤t_d3, ¤t_rst); + log_e("SDIO pins must be set before ESP-Hosted is initialized"); + log_e( + "Current pins used: clk=%d, cmd=%d, d0=%d, d1=%d, d2=%d, d3=%d, rst=%d", current_clk, current_cmd, current_d0, current_d1, current_d2, current_d3, + current_rst + ); + return false; + } + + sdio_pin_config.pin_clk = clk; + sdio_pin_config.pin_cmd = cmd; + sdio_pin_config.pin_d0 = d0; + sdio_pin_config.pin_d1 = d1; + sdio_pin_config.pin_d2 = d2; + sdio_pin_config.pin_d3 = d3; + sdio_pin_config.pin_reset = rst; + return true; +} + +void hostedGetPins(int8_t *clk, int8_t *cmd, int8_t *d0, int8_t *d1, int8_t *d2, int8_t *d3, int8_t *rst) { + *clk = sdio_pin_config.pin_clk; + *cmd = sdio_pin_config.pin_cmd; + *d0 = sdio_pin_config.pin_d0; + *d1 = sdio_pin_config.pin_d1; + *d2 = sdio_pin_config.pin_d2; + *d3 = sdio_pin_config.pin_d3; + *rst = sdio_pin_config.pin_reset; +} + +bool hostedIsBLEActive() { + return hosted_ble_active; +} + +bool hostedIsWiFiActive() { + return hosted_wifi_active; +} + +bool hostedIsInitialized() { + return hosted_initialized; +} + +#endif /* defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) || defined(CONFIG_ESP_WIFI_REMOTE_ENABLED) */ diff --git a/cores/esp32/esp32-hal-hosted.h b/cores/esp32/esp32-hal-hosted.h new file mode 100644 index 0000000..1b329fc --- /dev/null +++ b/cores/esp32/esp32-hal-hosted.h @@ -0,0 +1,61 @@ +// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_HOSTED_H_ +#define MAIN_ESP32_HAL_HOSTED_H_ + +#include "sdkconfig.h" +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) || defined(CONFIG_ESP_WIFI_REMOTE_ENABLED) + +#include "stdint.h" +#include "stdbool.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint8_t pin_clk; + uint8_t pin_cmd; + uint8_t pin_d0; + uint8_t pin_d1; + uint8_t pin_d2; + uint8_t pin_d3; + uint8_t pin_reset; +} sdio_pin_config_t; + +bool hostedInitBLE(); +bool hostedInitWiFi(); +bool hostedDeinitBLE(); +bool hostedDeinitWiFi(); +bool hostedIsInitialized(); +bool hostedIsBLEActive(); +bool hostedIsWiFiActive(); +bool hostedSetPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst); +void hostedGetPins(int8_t *clk, int8_t *cmd, int8_t *d0, int8_t *d1, int8_t *d2, int8_t *d3, int8_t *rst); +void hostedGetHostVersion(uint32_t *major, uint32_t *minor, uint32_t *patch); +void hostedGetSlaveVersion(uint32_t *major, uint32_t *minor, uint32_t *patch); +bool hostedHasUpdate(); +char *hostedGetUpdateURL(); +bool hostedBeginUpdate(); +bool hostedWriteUpdate(uint8_t *buf, uint32_t len); +bool hostedEndUpdate(); +bool hostedActivateUpdate(); + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) || defined(CONFIG_ESP_WIFI_REMOTE_ENABLED) */ +#endif /* MAIN_ESP32_HAL_HOSTED_H_ */ diff --git a/cores/esp32/esp32-hal-i2c-ng.c b/cores/esp32/esp32-hal-i2c-ng.c new file mode 100644 index 0000000..8a55b36 --- /dev/null +++ b/cores/esp32/esp32-hal-i2c-ng.c @@ -0,0 +1,455 @@ +// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-i2c.h" + +#if SOC_I2C_SUPPORTED +#include "esp_idf_version.h" +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) +#include "esp32-hal.h" +#if !CONFIG_DISABLE_HAL_LOCKS +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#endif +#include "esp_attr.h" +#include "esp_system.h" +#include "soc/soc_caps.h" +#include "driver/i2c_master.h" +#include "esp32-hal-periman.h" + +typedef volatile struct { + bool initialized; + uint32_t frequency; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t lock; +#endif + int8_t scl; + int8_t sda; + i2c_master_bus_handle_t bus_handle; + i2c_master_dev_handle_t dev_handles[128]; +} i2c_bus_t; + +static i2c_bus_t bus[SOC_I2C_NUM]; + +static bool i2cDetachBus(void *bus_i2c_num) { + uint8_t i2c_num = (int)bus_i2c_num - 1; + if (!bus[i2c_num].initialized) { + return true; + } + esp_err_t err = i2cDeinit(i2c_num); + if (err != ESP_OK) { + log_e("i2cDeinit failed with error: %d", err); + return false; + } + return true; +} + +void *i2cBusHandle(uint8_t i2c_num) { + if (i2c_num >= SOC_I2C_NUM) { + return NULL; + } + return bus[i2c_num].bus_handle; +} + +bool i2cIsInit(uint8_t i2c_num) { + if (i2c_num >= SOC_I2C_NUM) { + return false; + } + return bus[i2c_num].initialized; +} + +esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) { + esp_err_t ret = ESP_OK; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + if (bus[i2c_num].lock == NULL) { + bus[i2c_num].lock = xSemaphoreCreateMutex(); + if (bus[i2c_num].lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return ESP_ERR_NO_MEM; + } + } + //acquire lock + if (xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ESP_FAIL; + } +#endif + if (bus[i2c_num].initialized) { + log_e("bus is already initialized"); + ret = ESP_FAIL; + goto init_fail; + } + + if (!frequency) { + frequency = 100000UL; + } else if (frequency > 1000000UL) { + frequency = 1000000UL; + } + + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SDA, i2cDetachBus); + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SCL, i2cDetachBus); + + if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) { + ret = ESP_FAIL; + goto init_fail; + } + + log_i("Initializing I2C Master: num=%u sda=%d scl=%d freq=%lu", i2c_num, sda, scl, frequency); + + i2c_master_bus_handle_t bus_handle = NULL; + i2c_master_bus_config_t bus_config; + memset(&bus_config, 0, sizeof(i2c_master_bus_config_t)); + bus_config.i2c_port = (i2c_port_num_t)i2c_num; + bus_config.sda_io_num = (gpio_num_t)sda; + bus_config.scl_io_num = (gpio_num_t)scl; +#if SOC_LP_I2C_SUPPORTED + if (i2c_num >= SOC_HP_I2C_NUM) { + bus_config.lp_source_clk = LP_I2C_SCLK_DEFAULT; + } else +#endif + { + bus_config.clk_source = I2C_CLK_SRC_DEFAULT; + } + bus_config.glitch_ignore_cnt = 7; + bus_config.intr_priority = 0; // auto + bus_config.trans_queue_depth = 0; // only valid in asynchronous transaction, which Arduino does not use + bus_config.flags.enable_internal_pullup = 1; +#if SOC_I2C_SUPPORT_SLEEP_RETENTION + bus_config.flags.allow_pd = 1; // backup/restore the I2C registers before/after entering/exist sleep mode +#endif + + ret = i2c_new_master_bus(&bus_config, &bus_handle); + if (ret != ESP_OK) { + log_e("i2c_new_master_bus failed: [%d] %s", ret, esp_err_to_name(ret)); + } else { + bus[i2c_num].initialized = true; + bus[i2c_num].frequency = frequency; + bus[i2c_num].scl = scl; + bus[i2c_num].sda = sda; + bus[i2c_num].bus_handle = bus_handle; + for (uint8_t i = 0; i < 128; i++) { + bus[i2c_num].dev_handles[i] = NULL; + } + if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_MASTER_SDA, (void *)(i2c_num + 1), i2c_num, -1) + || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_MASTER_SCL, (void *)(i2c_num + 1), i2c_num, -1)) { +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock so that i2cDetachBus can execute i2cDeinit + xSemaphoreGive(bus[i2c_num].lock); +#endif + i2cDetachBus((void *)(i2c_num + 1)); + return ESP_FAIL; + } + } + + // Silence messages coming from the IDF driver + esp_log_level_set("i2c.master", ESP_LOG_NONE); + +init_fail: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cDeinit(uint8_t i2c_num) { + esp_err_t err = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return err; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + } else { + // remove devices from the bus + for (uint8_t i = 0; i < 128; i++) { + if (bus[i2c_num].dev_handles[i] != NULL) { + err = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]); + bus[i2c_num].dev_handles[i] = NULL; + if (err != ESP_OK) { + log_e("i2c_master_bus_rm_device failed: [%d] %s", err, esp_err_to_name(err)); + } + } + } + err = i2c_del_master_bus(bus[i2c_num].bus_handle); + if (err != ESP_OK) { + log_e("i2c_del_master_bus failed: [%d] %s", err, esp_err_to_name(err)); + } else { + bus[i2c_num].initialized = false; + perimanClearPinBus(bus[i2c_num].scl); + perimanClearPinBus(bus[i2c_num].sda); + bus[i2c_num].scl = -1; + bus[i2c_num].sda = -1; + bus[i2c_num].bus_handle = NULL; + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return err; +} + +static esp_err_t i2cAddDeviceIfNeeded(uint8_t i2c_num, uint16_t address) { + esp_err_t ret = ESP_OK; + if (bus[i2c_num].dev_handles[address] == NULL) { + i2c_master_dev_handle_t dev_handle = NULL; + i2c_device_config_t dev_config; + memset(&dev_config, 0, sizeof(i2c_device_config_t)); + dev_config.dev_addr_length = I2C_ADDR_BIT_LEN_7; // Arduino supports only 7bit addresses + dev_config.device_address = address; + dev_config.scl_speed_hz = bus[i2c_num].frequency; + dev_config.scl_wait_us = 0; + dev_config.flags.disable_ack_check = 0; + + ret = i2c_master_bus_add_device(bus[i2c_num].bus_handle, &dev_config, &dev_handle); + if (ret != ESP_OK) { + log_e("i2c_master_bus_add_device failed: [%d] %s", ret, esp_err_to_name(ret)); + } else { + bus[i2c_num].dev_handles[address] = dev_handle; + log_v("added device: bus=%u addr=0x%x handle=0x%08x", i2c_num, address, dev_handle); + } + } + return ret; +} + +esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis) { + esp_err_t ret = ESP_FAIL; + // i2c_cmd_handle_t cmd = NULL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } + if (address >= 128) { + log_e("Only 7bit I2C addresses are supported"); + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + + if (size == 0) { + // Probe device + ret = i2c_master_probe(bus[i2c_num].bus_handle, address, timeOutMillis); + if (ret != ESP_OK) { + log_v("i2c_master_probe failed: [%d] %s", ret, esp_err_to_name(ret)); + } + } else { + // writing data to device + ret = i2cAddDeviceIfNeeded(i2c_num, address); + if (ret != ESP_OK) { + goto end; + } + + log_v("i2c_master_transmit: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size); + ret = i2c_master_transmit(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis); + if (ret != ESP_OK) { + log_e("i2c_master_transmit failed: [%d] %s", ret, esp_err_to_name(ret)); + goto end; + } + + // wait for transactions to finish (is it needed with sync transactions?) + // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis); + // if (ret != ESP_OK) { + // log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret)); + // goto end; + // } + } + +end: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount) { + esp_err_t ret = ESP_FAIL; + *readCount = 0; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + + ret = i2cAddDeviceIfNeeded(i2c_num, address); + if (ret != ESP_OK) { + goto end; + } + + log_v("i2c_master_receive: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size); + ret = i2c_master_receive(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis); + if (ret != ESP_OK) { + log_e("i2c_master_receive failed: [%d] %s", ret, esp_err_to_name(ret)); + goto end; + } + + // wait for transactions to finish (is it needed with sync transactions?) + // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis); + // if (ret != ESP_OK) { + // log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret)); + // goto end; + // } + *readCount = size; + +end: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cWriteReadNonStop( + uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount +) { + esp_err_t ret = ESP_FAIL; + *readCount = 0; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + + ret = i2cAddDeviceIfNeeded(i2c_num, address); + if (ret != ESP_OK) { + goto end; + } + + log_v("i2c_master_transmit_receive: bus=%u addr=0x%x handle=0x%08x write=%u read=%u", i2c_num, address, bus[i2c_num].dev_handles[address], wsize, rsize); + ret = i2c_master_transmit_receive(bus[i2c_num].dev_handles[address], wbuff, wsize, rbuff, rsize, timeOutMillis); + if (ret != ESP_OK) { + log_e("i2c_master_transmit_receive failed: [%d] %s", ret, esp_err_to_name(ret)); + goto end; + } + + // wait for transactions to finish (is it needed with sync transactions?) + // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis); + // if (ret != ESP_OK) { + // log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret)); + // goto end; + // } + *readCount = rsize; + +end: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency) { + esp_err_t ret = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + if (bus[i2c_num].frequency == frequency) { + ret = ESP_OK; + goto end; + } + if (!frequency) { + frequency = 100000UL; + } else if (frequency > 1000000UL) { + frequency = 1000000UL; + } + + bus[i2c_num].frequency = frequency; + + // loop through devices, remove them and then re-add them with the new frequency + for (uint8_t i = 0; i < 128; i++) { + if (bus[i2c_num].dev_handles[i] != NULL) { + ret = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]); + if (ret != ESP_OK) { + log_e("i2c_master_bus_rm_device failed: [%d] %s", ret, esp_err_to_name(ret)); + goto end; + } else { + bus[i2c_num].dev_handles[i] = NULL; + ret = i2cAddDeviceIfNeeded(i2c_num, i); + if (ret != ESP_OK) { + goto end; + } + } + } + } + +end: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) { + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + return ESP_FAIL; + } + *frequency = bus[i2c_num].frequency; + return ESP_OK; +} + +#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) */ +#endif /* SOC_I2C_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-i2c-slave.c b/cores/esp32/esp32-hal-i2c-slave.c new file mode 100644 index 0000000..5c0991c --- /dev/null +++ b/cores/esp32/esp32-hal-i2c-slave.c @@ -0,0 +1,925 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc_caps.h" + +#if SOC_I2C_SUPPORT_SLAVE +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdkconfig.h" +#include "esp_attr.h" +#include "rom/gpio.h" +#include "soc/gpio_sig_map.h" +#include "hal/gpio_types.h" +#include "driver/gpio.h" +#include "esp_err.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" +#include "freertos/ringbuf.h" + +#include "esp_intr_alloc.h" +#include "soc/i2c_reg.h" +#include "soc/i2c_struct.h" +#include "soc/periph_defs.h" +#include "hal/i2c_ll.h" +#include "hal/i2c_types.h" +#if !defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32C61) +#include "hal/clk_gate_ll.h" +#endif +#include "esp32-hal-log.h" +#include "esp32-hal-i2c-slave.h" +#include "esp32-hal-periman.h" +#include "esp_private/periph_ctrl.h" + +#if SOC_PERIPH_CLK_CTRL_SHARED +#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define I2C_CLOCK_SRC_ATOMIC() +#endif + +#if !SOC_RCC_IS_INDEPENDENT +#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define I2C_RCC_ATOMIC() +#endif + +#define I2C_SLAVE_USE_RX_QUEUE 0 // 1: Queue, 0: RingBuffer + +#ifdef CONFIG_IDF_TARGET_ESP32P4 +#define I2C_SCL_IDX(p) ((p == 0) ? I2C0_SCL_PAD_OUT_IDX : ((p == 1) ? I2C1_SCL_PAD_OUT_IDX : 0)) +#define I2C_SDA_IDX(p) ((p == 0) ? I2C0_SDA_PAD_OUT_IDX : ((p == 1) ? I2C1_SDA_PAD_OUT_IDX : 0)) +#else +#if SOC_HP_I2C_NUM > 1 +#define I2C_SCL_IDX(p) ((p == 0) ? I2CEXT0_SCL_OUT_IDX : ((p == 1) ? I2CEXT1_SCL_OUT_IDX : 0)) +#define I2C_SDA_IDX(p) ((p == 0) ? I2CEXT0_SDA_OUT_IDX : ((p == 1) ? I2CEXT1_SDA_OUT_IDX : 0)) +#else +#define I2C_SCL_IDX(p) I2CEXT0_SCL_OUT_IDX +#define I2C_SDA_IDX(p) I2CEXT0_SDA_OUT_IDX +#endif +#endif // ifdef CONFIG_IDF_TARGET_ESP32P4 + +#if CONFIG_IDF_TARGET_ESP32 +#define I2C_TXFIFO_WM_INT_ENA I2C_TXFIFO_EMPTY_INT_ENA +#define I2C_RXFIFO_WM_INT_ENA I2C_RXFIFO_FULL_INT_ENA +#endif + +enum { + I2C_SLAVE_EVT_RX, + I2C_SLAVE_EVT_TX +}; + +typedef struct i2c_slave_struct_t { + i2c_dev_t *dev; + uint8_t num; + int8_t sda; + int8_t scl; + i2c_slave_request_cb_t request_callback; + i2c_slave_receive_cb_t receive_callback; + void *arg; + intr_handle_t intr_handle; + TaskHandle_t task_handle; + QueueHandle_t event_queue; +#if I2C_SLAVE_USE_RX_QUEUE + QueueHandle_t rx_queue; +#else + RingbufHandle_t rx_ring_buf; +#endif + QueueHandle_t tx_queue; + uint32_t rx_data_count; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t lock; +#endif +} i2c_slave_struct_t; + +typedef union { + struct { + uint32_t event : 2; + uint32_t stop : 1; + uint32_t param : 29; + }; + uint32_t val; +} i2c_slave_queue_event_t; + +static i2c_slave_struct_t _i2c_bus_array[SOC_HP_I2C_NUM] = { + {&I2C0, 0, -1, -1, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0 +#if !CONFIG_DISABLE_HAL_LOCKS + , + NULL +#endif + }, +#if SOC_HP_I2C_NUM > 1 + {&I2C1, 1, -1, -1, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0 +#if !CONFIG_DISABLE_HAL_LOCKS + , + NULL +#endif + } +#endif +}; + +#if CONFIG_DISABLE_HAL_LOCKS +#define I2C_SLAVE_MUTEX_LOCK() +#define I2C_SLAVE_MUTEX_UNLOCK() +#else +#define I2C_SLAVE_MUTEX_LOCK() \ + if (i2c->lock) { \ + xSemaphoreTake(i2c->lock, portMAX_DELAY); \ + } +#define I2C_SLAVE_MUTEX_UNLOCK() \ + if (i2c->lock) { \ + xSemaphoreGive(i2c->lock); \ + } +#endif + +//-------------------------------------- HAL_LL (Missing Functions) ------------------------------------------------ +typedef enum { + I2C_STRETCH_CAUSE_MASTER_READ, + I2C_STRETCH_CAUSE_TX_FIFO_EMPTY, + I2C_STRETCH_CAUSE_RX_FIFO_FULL, + I2C_STRETCH_CAUSE_MAX +} i2c_stretch_cause_t; + +static inline i2c_stretch_cause_t i2c_ll_stretch_cause(i2c_dev_t *hw) { +#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 + return hw->sr.stretch_cause; +#elif CONFIG_IDF_TARGET_ESP32S2 + return hw->status_reg.stretch_cause; +#else + return I2C_STRETCH_CAUSE_MAX; +#endif +} + +static inline void i2c_ll_set_stretch(i2c_dev_t *hw, uint16_t time) { +#ifndef CONFIG_IDF_TARGET_ESP32 + typeof(hw->scl_stretch_conf) scl_stretch_conf; + scl_stretch_conf.val = 0; + scl_stretch_conf.slave_scl_stretch_en = (time > 0); + scl_stretch_conf.stretch_protect_num = time; + scl_stretch_conf.slave_scl_stretch_clr = 1; + hw->scl_stretch_conf.val = scl_stretch_conf.val; + if (time > 0) { + //enable interrupt + hw->int_ena.val |= I2C_SLAVE_STRETCH_INT_ENA; + } else { + //disable interrupt + hw->int_ena.val &= (~I2C_SLAVE_STRETCH_INT_ENA); + } +#endif +} + +static inline void i2c_ll_stretch_clr(i2c_dev_t *hw) { +#ifndef CONFIG_IDF_TARGET_ESP32 + hw->scl_stretch_conf.slave_scl_stretch_clr = 1; +#endif +} + +static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + return hw->status_reg.slave_addressed; +#else + return hw->sr.slave_addressed; +#endif +} + +static inline bool i2c_ll_slave_rw(i2c_dev_t *hw) //not exposed by hal_ll +{ +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + return hw->status_reg.slave_rw; +#else + return hw->sr.slave_rw; +#endif +} + +//-------------------------------------- PRIVATE (Function Prototypes) ------------------------------------------------ +static void i2c_slave_free_resources(i2c_slave_struct_t *i2c); +static void i2c_slave_delay_us(uint64_t us); +static void i2c_slave_gpio_mode(int8_t pin, gpio_mode_t mode); +static bool i2c_slave_check_line_state(int8_t sda, int8_t scl); +static bool i2c_slave_attach_gpio(i2c_slave_struct_t *i2c, int8_t sda, int8_t scl); +static bool i2c_slave_detach_gpio(i2c_slave_struct_t *i2c); +static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed); +static bool i2c_slave_send_event(i2c_slave_struct_t *i2c, i2c_slave_queue_event_t *event); +static bool i2c_slave_handle_tx_fifo_empty(i2c_slave_struct_t *i2c); +static bool i2c_slave_handle_rx_fifo_full(i2c_slave_struct_t *i2c, uint32_t len); +static size_t i2c_slave_read_rx(i2c_slave_struct_t *i2c, uint8_t *data, size_t len); +static void i2c_slave_isr_handler(void *arg); +static void i2c_slave_task(void *pv_args); +static bool i2cSlaveDetachBus(void *bus_i2c_num); + +//===================================================================================================================== +//-------------------------------------- Public Functions ------------------------------------------------------------- +//===================================================================================================================== + +esp_err_t i2cSlaveAttachCallbacks(uint8_t num, i2c_slave_request_cb_t request_callback, i2c_slave_receive_cb_t receive_callback, void *arg) { + if (num >= SOC_HP_I2C_NUM) { + log_e("Invalid port num: %u", num); + return ESP_ERR_INVALID_ARG; + } + i2c_slave_struct_t *i2c = &_i2c_bus_array[num]; + I2C_SLAVE_MUTEX_LOCK(); + i2c->request_callback = request_callback; + i2c->receive_callback = receive_callback; + i2c->arg = arg; + I2C_SLAVE_MUTEX_UNLOCK(); + return ESP_OK; +} + +esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t frequency, size_t rx_len, size_t tx_len) { + if (num >= SOC_HP_I2C_NUM) { + log_e("Invalid port num: %u", num); + return ESP_ERR_INVALID_ARG; + } + + if (sda < 0 || scl < 0) { + log_e("invalid pins sda=%d, scl=%d", sda, scl); + return ESP_ERR_INVALID_ARG; + } + + if (!frequency) { + frequency = 100000; + } else if (frequency > 1000000) { + frequency = 1000000; + } + + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_SLAVE_SDA, i2cSlaveDetachBus); + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_SLAVE_SCL, i2cSlaveDetachBus); + + if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) { + return false; + } + + log_i("Initializing I2C Slave: sda=%d scl=%d freq=%d, addr=0x%x", sda, scl, frequency, slaveID); + + i2c_slave_struct_t *i2c = &_i2c_bus_array[num]; + esp_err_t ret = ESP_OK; + +#if !CONFIG_DISABLE_HAL_LOCKS + if (!i2c->lock) { + i2c->lock = xSemaphoreCreateMutex(); + if (i2c->lock == NULL) { + log_e("RX queue create failed"); + return ESP_ERR_NO_MEM; + } + } +#endif + + I2C_SLAVE_MUTEX_LOCK(); + i2c_slave_free_resources(i2c); + +#if I2C_SLAVE_USE_RX_QUEUE + i2c->rx_queue = xQueueCreate(rx_len, sizeof(uint8_t)); + if (i2c->rx_queue == NULL) { + log_e("RX queue create failed"); + ret = ESP_ERR_NO_MEM; + goto fail; + } +#else + i2c->rx_ring_buf = xRingbufferCreate(rx_len, RINGBUF_TYPE_BYTEBUF); + if (i2c->rx_ring_buf == NULL) { + log_e("RX RingBuf create failed"); + ret = ESP_ERR_NO_MEM; + goto fail; + } +#endif + + i2c->tx_queue = xQueueCreate(tx_len, sizeof(uint8_t)); + if (i2c->tx_queue == NULL) { + log_e("TX queue create failed"); + ret = ESP_ERR_NO_MEM; + goto fail; + } + + i2c->event_queue = xQueueCreate(16, sizeof(i2c_slave_queue_event_t)); + if (i2c->event_queue == NULL) { + log_e("Event queue create failed"); + ret = ESP_ERR_NO_MEM; + goto fail; + } + + xTaskCreate(i2c_slave_task, "i2c_slave_task", 4096, i2c, 20, &i2c->task_handle); + if (i2c->task_handle == NULL) { + log_e("Event thread create failed"); + ret = ESP_ERR_NO_MEM; + goto fail; + } + + if (frequency == 0) { + frequency = 100000L; + } + frequency = (frequency * 5) / 4; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 \ + || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + if (i2c->num == 0) { + periph_ll_enable_clk_clear_rst(PERIPH_I2C0_MODULE); +#if SOC_HP_I2C_NUM > 1 + } else { + periph_ll_enable_clk_clear_rst(PERIPH_I2C1_MODULE); +#endif + } +#endif // !defined(CONFIG_IDF_TARGET_ESP32P4) + +#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)) || (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) && ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0)) \ + || (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 3) && ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0)) + i2c_ll_set_mode(i2c->dev, I2C_BUS_MODE_SLAVE); + i2c_ll_enable_pins_open_drain(i2c->dev, true); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) + i2c_ll_enable_fifo_mode(i2c->dev, true); +#else + i2c_ll_slave_set_fifo_mode(i2c->dev, true); +#endif +#else + i2c_ll_slave_init(i2c->dev); + i2c_ll_slave_set_fifo_mode(i2c->dev, true); +#endif + i2c_ll_set_slave_addr(i2c->dev, slaveID, false); + i2c_ll_set_tout(i2c->dev, I2C_LL_MAX_TIMEOUT); + i2c_slave_set_frequency(i2c, frequency); + + if (!i2c_slave_check_line_state(sda, scl)) { + log_e("bad pin state"); + ret = ESP_FAIL; + goto fail; + } + + i2c_slave_attach_gpio(i2c, sda, scl); + + if (i2c_ll_is_bus_busy(i2c->dev)) { + log_w("Bus busy, reinit"); + ret = ESP_FAIL; + goto fail; + } + + i2c_ll_disable_intr_mask(i2c->dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c->dev, I2C_LL_INTR_MASK); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) + i2c_ll_enable_fifo_mode(i2c->dev, true); +#else + i2c_ll_slave_set_fifo_mode(i2c->dev, true); +#endif + + if (!i2c->intr_handle) { + uint32_t flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED; + if (i2c->num == 0) { +#if !defined(CONFIG_IDF_TARGET_ESP32P4) + ret = esp_intr_alloc(ETS_I2C_EXT0_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle); +#else + ret = esp_intr_alloc(ETS_I2C0_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle); +#endif +#if SOC_HP_I2C_NUM > 1 + } else { +#if !defined(CONFIG_IDF_TARGET_ESP32P4) + ret = esp_intr_alloc(ETS_I2C_EXT1_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle); +#else + ret = esp_intr_alloc(ETS_I2C1_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle); +#endif +#endif + } + + if (ret != ESP_OK) { + log_e("install interrupt handler Failed=%d", ret); + goto fail; + } + } + + i2c_ll_txfifo_rst(i2c->dev); + i2c_ll_rxfifo_rst(i2c->dev); + i2c_ll_slave_enable_rx_it(i2c->dev); + i2c_ll_set_stretch(i2c->dev, 0x3FF); + i2c_ll_update(i2c->dev); + if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_SLAVE_SDA, (void *)(i2c->num + 1), i2c->num, -1) + || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_SLAVE_SCL, (void *)(i2c->num + 1), i2c->num, -1)) { + i2cSlaveDetachBus((void *)(i2c->num + 1)); + ret = ESP_FAIL; + } + I2C_SLAVE_MUTEX_UNLOCK(); + return ret; + +fail: + i2c_slave_free_resources(i2c); + I2C_SLAVE_MUTEX_UNLOCK(); + return ret; +} + +esp_err_t i2cSlaveDeinit(uint8_t num) { + if (num >= SOC_HP_I2C_NUM) { + log_e("Invalid port num: %u", num); + return ESP_ERR_INVALID_ARG; + } + + i2c_slave_struct_t *i2c = &_i2c_bus_array[num]; +#if !CONFIG_DISABLE_HAL_LOCKS + if (!i2c->lock) { + log_e("Lock is not initialized! Did you call i2c_slave_init()?"); + return ESP_ERR_NO_MEM; + } +#endif + I2C_SLAVE_MUTEX_LOCK(); + int scl = i2c->scl; + int sda = i2c->sda; + i2c_slave_free_resources(i2c); + perimanClearPinBus(scl); + perimanClearPinBus(sda); + I2C_SLAVE_MUTEX_UNLOCK(); + return ESP_OK; +} + +size_t i2cSlaveWrite(uint8_t num, const uint8_t *buf, uint32_t len, uint32_t timeout_ms) { + if (num >= SOC_HP_I2C_NUM) { + log_e("Invalid port num: %u", num); + return 0; + } + uint32_t to_queue = 0, to_fifo = 0; + i2c_slave_struct_t *i2c = &_i2c_bus_array[num]; +#if !CONFIG_DISABLE_HAL_LOCKS + if (!i2c->lock) { + log_e("Lock is not initialized! Did you call i2c_slave_init()?"); + return ESP_ERR_NO_MEM; + } +#endif + if (!i2c->tx_queue) { + return 0; + } + I2C_SLAVE_MUTEX_LOCK(); +#if CONFIG_IDF_TARGET_ESP32 + i2c_ll_slave_disable_tx_it(i2c->dev); + uint32_t txfifo_len = 0; + i2c_ll_get_txfifo_len(i2c->dev, &txfifo_len); + if (txfifo_len < SOC_I2C_FIFO_LEN) { + i2c_ll_txfifo_rst(i2c->dev); + } +#endif + i2c_ll_get_txfifo_len(i2c->dev, &to_fifo); + if (to_fifo) { + if (len < to_fifo) { + to_fifo = len; + } + i2c_ll_write_txfifo(i2c->dev, (uint8_t *)buf, to_fifo); + buf += to_fifo; + len -= to_fifo; + //reset tx_queue + xQueueReset(i2c->tx_queue); + //write the rest of the bytes to the queue + if (len) { + to_queue = uxQueueSpacesAvailable(i2c->tx_queue); + if (len < to_queue) { + to_queue = len; + } + for (size_t i = 0; i < to_queue; i++) { + if (xQueueSend(i2c->tx_queue, &buf[i], timeout_ms / portTICK_PERIOD_MS) != pdTRUE) { + xQueueReset(i2c->tx_queue); + to_queue = 0; + break; + } + } + //no need to enable TX_EMPTY if tx_queue is empty + if (to_queue) { + i2c_ll_slave_enable_tx_it(i2c->dev); + } + } + } + I2C_SLAVE_MUTEX_UNLOCK(); + return to_queue + to_fifo; +} + +//===================================================================================================================== +//-------------------------------------- Private Functions ------------------------------------------------------------ +//===================================================================================================================== + +static void i2c_slave_free_resources(i2c_slave_struct_t *i2c) { + i2c_slave_detach_gpio(i2c); + i2c_ll_set_slave_addr(i2c->dev, 0, false); + i2c_ll_disable_intr_mask(i2c->dev, I2C_LL_INTR_MASK); + i2c_ll_clear_intr_mask(i2c->dev, I2C_LL_INTR_MASK); + + if (i2c->intr_handle) { + esp_intr_free(i2c->intr_handle); + i2c->intr_handle = NULL; + } + + if (i2c->task_handle) { + vTaskDelete(i2c->task_handle); + i2c->task_handle = NULL; + } + +#if I2C_SLAVE_USE_RX_QUEUE + if (i2c->rx_queue) { + vQueueDelete(i2c->rx_queue); + i2c->rx_queue = NULL; + } +#else + if (i2c->rx_ring_buf) { + vRingbufferDelete(i2c->rx_ring_buf); + i2c->rx_ring_buf = NULL; + } +#endif + + if (i2c->tx_queue) { + vQueueDelete(i2c->tx_queue); + i2c->tx_queue = NULL; + } + + if (i2c->event_queue) { + vQueueDelete(i2c->event_queue); + i2c->event_queue = NULL; + } + + i2c->rx_data_count = 0; +} + +static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed) { + if (i2c == NULL) { + log_e("no control buffer"); + return false; + } + if (clk_speed > 1100000UL) { + clk_speed = 1100000UL; + } + + // Adjust Fifo thresholds based on frequency + uint32_t a = (clk_speed / 50000L) + 2; + log_d("Fifo thresholds: rx_fifo_full = %d, tx_fifo_empty = %d", SOC_I2C_FIFO_LEN - a, a); + + i2c_hal_clk_config_t clk_cal; +#if SOC_I2C_SUPPORT_APB + i2c_ll_master_cal_bus_clk(APB_CLK_FREQ, clk_speed, &clk_cal); + I2C_CLOCK_SRC_ATOMIC() { + i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_APB); /*!< I2C source clock from APB, 80M*/ + } +#elif SOC_I2C_SUPPORT_XTAL +#ifndef XTAL_CLK_FREQ +#define XTAL_CLK_FREQ APB_CLK_FREQ +#endif + i2c_ll_master_cal_bus_clk(XTAL_CLK_FREQ, clk_speed, &clk_cal); + I2C_CLOCK_SRC_ATOMIC() { + i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_XTAL); /*!< I2C source clock from XTAL, 40M */ + } +#endif + i2c_ll_set_txfifo_empty_thr(i2c->dev, a); + i2c_ll_set_rxfifo_full_thr(i2c->dev, SOC_I2C_FIFO_LEN - a); + i2c_ll_master_set_bus_timing(i2c->dev, &clk_cal); + i2c_ll_master_set_filter(i2c->dev, 3); + return true; +} + +static void i2c_slave_delay_us(uint64_t us) { + uint64_t m = esp_timer_get_time(); + if (us) { + uint64_t e = (m + us); + if (m > e) { //overflow + while ((uint64_t)esp_timer_get_time() > e); + } + while ((uint64_t)esp_timer_get_time() < e); + } +} + +static void i2c_slave_gpio_mode(int8_t pin, gpio_mode_t mode) { + gpio_config_t conf = { + .pin_bit_mask = 1LL << pin, .mode = mode, .pull_up_en = GPIO_PULLUP_ENABLE, .pull_down_en = GPIO_PULLDOWN_DISABLE, .intr_type = GPIO_INTR_DISABLE + }; + gpio_config(&conf); +} + +static bool i2c_slave_check_line_state(int8_t sda, int8_t scl) { + if (sda < 0 || scl < 0) { + return false; //return false since there is nothing to do + } + // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles + gpio_set_level(sda, 1); + gpio_set_level(scl, 1); + i2c_slave_gpio_mode(sda, GPIO_MODE_INPUT | GPIO_MODE_DEF_OD); + i2c_slave_gpio_mode(scl, GPIO_MODE_INPUT | GPIO_MODE_DEF_OD); + gpio_set_level(scl, 1); + + if (!gpio_get_level(sda) || !gpio_get_level(scl)) { // bus in busy state + log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, gpio_get_level(sda), scl, gpio_get_level(scl)); + for (uint8_t a = 0; a < 9; a++) { + i2c_slave_delay_us(5); + if (gpio_get_level(sda) && gpio_get_level(scl)) { // bus recovered + log_w("Recovered after %d Cycles", a); + gpio_set_level(sda, 0); // start + i2c_slave_delay_us(5); + for (uint8_t b = 0; b < 9; b++) { + gpio_set_level(scl, 1); + i2c_slave_delay_us(5); + gpio_set_level(scl, 0); + i2c_slave_delay_us(5); + } + gpio_set_level(scl, 1); + i2c_slave_delay_us(5); + gpio_set_level(sda, 1); // stop + break; + } + gpio_set_level(scl, 0); + i2c_slave_delay_us(5); + gpio_set_level(scl, 1); + } + } + + if (!gpio_get_level(sda) || !gpio_get_level(scl)) { // bus in busy state + log_e("Bus Invalid State, Can't init sda=%d, scl=%d", gpio_get_level(sda), gpio_get_level(scl)); + return false; // bus is busy + } + return true; +} + +static bool i2c_slave_attach_gpio(i2c_slave_struct_t *i2c, int8_t sda, int8_t scl) { + if (i2c == NULL) { + log_e("no control block"); + return false; + } + + if ((sda < 0) || (scl < 0)) { + log_e("bad pins sda=%d, scl=%d", sda, scl); + return false; + } + + i2c->scl = scl; + gpio_set_level(scl, 1); + i2c_slave_gpio_mode(scl, GPIO_MODE_INPUT_OUTPUT_OD); + gpio_matrix_out(scl, I2C_SCL_IDX(i2c->num), false, false); + gpio_matrix_in(scl, I2C_SCL_IDX(i2c->num), false); + + i2c->sda = sda; + gpio_set_level(sda, 1); + i2c_slave_gpio_mode(sda, GPIO_MODE_INPUT_OUTPUT_OD); + gpio_matrix_out(sda, I2C_SDA_IDX(i2c->num), false, false); + gpio_matrix_in(sda, I2C_SDA_IDX(i2c->num), false); + + return true; +} + +static bool i2c_slave_detach_gpio(i2c_slave_struct_t *i2c) { + if (i2c == NULL) { + log_e("no control Block"); + return false; + } + if (i2c->scl >= 0) { + gpio_matrix_out(i2c->scl, 0x100, false, false); + gpio_matrix_in(0x30, I2C_SCL_IDX(i2c->num), false); + i2c_slave_gpio_mode(i2c->scl, GPIO_MODE_INPUT); + i2c->scl = -1; // un attached + } + if (i2c->sda >= 0) { + gpio_matrix_out(i2c->sda, 0x100, false, false); + gpio_matrix_in(0x30, I2C_SDA_IDX(i2c->num), false); + i2c_slave_gpio_mode(i2c->sda, GPIO_MODE_INPUT); + i2c->sda = -1; // un attached + } + return true; +} + +static bool i2c_slave_send_event(i2c_slave_struct_t *i2c, i2c_slave_queue_event_t *event) { + bool pxHigherPriorityTaskWoken = false; + if (i2c->event_queue) { + if (xQueueSendFromISR(i2c->event_queue, event, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) { + //log_e("event_queue_full"); + } + } + return pxHigherPriorityTaskWoken; +} + +static bool i2c_slave_handle_tx_fifo_empty(i2c_slave_struct_t *i2c) { + bool pxHigherPriorityTaskWoken = false; + uint32_t d = 0, moveCnt = 0; + i2c_ll_get_txfifo_len(i2c->dev, &moveCnt); + while (moveCnt > 0) { // read tx queue until Fifo is full or queue is empty + if (xQueueReceiveFromISR(i2c->tx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) == pdTRUE) { + i2c_ll_write_txfifo(i2c->dev, (uint8_t *)&d, 1); + moveCnt--; + } else { + i2c_ll_slave_disable_tx_it(i2c->dev); + break; + } + } + return pxHigherPriorityTaskWoken; +} + +static bool i2c_slave_handle_rx_fifo_full(i2c_slave_struct_t *i2c, uint32_t len) { +#if I2C_SLAVE_USE_RX_QUEUE + uint32_t d = 0; +#else + uint8_t data[SOC_I2C_FIFO_LEN]; +#endif + bool pxHigherPriorityTaskWoken = false; +#if I2C_SLAVE_USE_RX_QUEUE + while (len > 0) { + i2c_ll_read_rxfifo(i2c->dev, (uint8_t *)&d, 1); + if (xQueueSendFromISR(i2c->rx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) { + log_e("rx_queue_full"); + } else { + i2c->rx_data_count++; + } + if (--len == 0) { + len = i2c_ll_get_rxfifo_cnt(i2c->dev); + } +#else + if (len) { + i2c_ll_read_rxfifo(i2c->dev, data, len); + if (xRingbufferSendFromISR(i2c->rx_ring_buf, (void *)data, len, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) { + log_e("rx_ring_buf_full"); + } else { + i2c->rx_data_count += len; + } +#endif + } + return pxHigherPriorityTaskWoken; +} + +static void i2c_slave_isr_handler(void *arg) { + bool pxHigherPriorityTaskWoken = false; + i2c_slave_struct_t *i2c = (i2c_slave_struct_t *)arg; // recover data + + uint32_t activeInt = 0; + i2c_ll_get_intr_mask(i2c->dev, &activeInt); + i2c_ll_clear_intr_mask(i2c->dev, activeInt); + uint32_t rx_fifo_len = 0; + i2c_ll_get_rxfifo_cnt(i2c->dev, &rx_fifo_len); + bool slave_rw = i2c_ll_slave_rw(i2c->dev); + + if (activeInt & I2C_RXFIFO_WM_INT_ENA) { // RX FiFo Full + pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len); + i2c_ll_slave_enable_rx_it(i2c->dev); //is this necessary? + } + + if (activeInt & I2C_TRANS_COMPLETE_INT_ENA) { // STOP + if (rx_fifo_len) { //READ RX FIFO + pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len); + } + if (i2c->rx_data_count) { //WRITE or RepeatedStart + //SEND RX Event + i2c_slave_queue_event_t event; + event.event = I2C_SLAVE_EVT_RX; + event.stop = !slave_rw; + event.param = i2c->rx_data_count; + pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event); + //Zero RX count + i2c->rx_data_count = 0; + } + if (slave_rw) { // READ +#if CONFIG_IDF_TARGET_ESP32 + if (i2c->dev->status_reg.scl_main_state_last == 6) { + //SEND TX Event + i2c_slave_queue_event_t event; + event.event = I2C_SLAVE_EVT_TX; + pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event); + } +#else + //reset TX data + i2c_ll_txfifo_rst(i2c->dev); + uint8_t d; + while (xQueueReceiveFromISR(i2c->tx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) == pdTRUE); //flush partial write +#endif + } + } + +#ifndef CONFIG_IDF_TARGET_ESP32 + if (activeInt & I2C_SLAVE_STRETCH_INT_ENA) { // STRETCH + i2c_stretch_cause_t cause = i2c_ll_stretch_cause(i2c->dev); + if (cause == I2C_STRETCH_CAUSE_MASTER_READ) { + //on C3 RX data disappears with repeated start, so we need to get it here + if (rx_fifo_len) { + pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len); + } + //SEND TX Event + i2c_slave_queue_event_t event; + event.event = I2C_SLAVE_EVT_TX; + pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event); + //will clear after execution + } else if (cause == I2C_STRETCH_CAUSE_TX_FIFO_EMPTY) { + pxHigherPriorityTaskWoken |= i2c_slave_handle_tx_fifo_empty(i2c); + i2c_ll_stretch_clr(i2c->dev); + } else if (cause == I2C_STRETCH_CAUSE_RX_FIFO_FULL) { + pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len); + i2c_ll_stretch_clr(i2c->dev); + } + } +#endif + + if (activeInt & I2C_TXFIFO_WM_INT_ENA) { // TX FiFo Empty + pxHigherPriorityTaskWoken |= i2c_slave_handle_tx_fifo_empty(i2c); + } + + if (pxHigherPriorityTaskWoken) { + portYIELD_FROM_ISR(); + } +} + +static size_t i2c_slave_read_rx(i2c_slave_struct_t *i2c, uint8_t *data, size_t len) { + if (!len) { + return 0; + } +#if I2C_SLAVE_USE_RX_QUEUE + uint8_t d = 0; + BaseType_t res = pdTRUE; + for (size_t i = 0; i < len; i++) { + if (data) { + res = xQueueReceive(i2c->rx_queue, &data[i], 0); + } else { + res = xQueueReceive(i2c->rx_queue, &d, 0); + } + if (res != pdTRUE) { + log_e("Read Queue(%u) Failed", i); + len = i; + break; + } + } + return (data) ? len : 0; +#else + size_t dlen = 0, to_read = len, so_far = 0, available = 0; + uint8_t *rx_data = NULL; + + vRingbufferGetInfo(i2c->rx_ring_buf, NULL, NULL, NULL, NULL, &available); + if (available < to_read) { + log_e("Less available than requested. %u < %u", available, len); + to_read = available; + } + + while (to_read) { + dlen = 0; + rx_data = (uint8_t *)xRingbufferReceiveUpTo(i2c->rx_ring_buf, &dlen, 0, to_read); + if (!rx_data) { + log_e("Receive %u Failed", to_read); + return so_far; + } + if (data) { + memcpy(data + so_far, rx_data, dlen); + } + vRingbufferReturnItem(i2c->rx_ring_buf, rx_data); + so_far += dlen; + to_read -= dlen; + } + return (data) ? so_far : 0; +#endif +} + +static void i2c_slave_task(void *pv_args) { + i2c_slave_struct_t *i2c = (i2c_slave_struct_t *)pv_args; + i2c_slave_queue_event_t event; + size_t len = 0; + bool stop = false; + uint8_t *data = NULL; + for (;;) { + if (xQueueReceive(i2c->event_queue, &event, portMAX_DELAY) == pdTRUE) { + // Write + if (event.event == I2C_SLAVE_EVT_RX) { + len = event.param; + stop = event.stop; + data = (len > 0) ? (uint8_t *)malloc(len) : NULL; + + if (len && data == NULL) { + log_e("Malloc (%u) Failed", len); + } + len = i2c_slave_read_rx(i2c, data, len); + if (i2c->receive_callback) { + i2c->receive_callback(i2c->num, data, len, stop, i2c->arg); + } + free(data); + + // Read + } else if (event.event == I2C_SLAVE_EVT_TX) { + if (i2c->request_callback) { + i2c->request_callback(i2c->num, i2c->arg); + } + i2c_ll_stretch_clr(i2c->dev); + } + } + } + vTaskDelete(NULL); +} + +static bool i2cSlaveDetachBus(void *bus_i2c_num) { + uint8_t num = (int)bus_i2c_num - 1; + i2c_slave_struct_t *i2c = &_i2c_bus_array[num]; + if (i2c->scl == -1 && i2c->sda == -1) { + return true; + } + esp_err_t err = i2cSlaveDeinit(num); + if (err != ESP_OK) { + log_e("i2cSlaveDeinit failed with error: %d", err); + return false; + } + return true; +} + +#endif /* SOC_I2C_SUPPORT_SLAVE */ diff --git a/cores/esp32/esp32-hal-i2c-slave.h b/cores/esp32/esp32-hal-i2c-slave.h new file mode 100644 index 0000000..7876565 --- /dev/null +++ b/cores/esp32/esp32-hal-i2c-slave.h @@ -0,0 +1,40 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_I2C_SUPPORT_SLAVE + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" +#include "stddef.h" +#include "esp_err.h" + +typedef void (*i2c_slave_request_cb_t)(uint8_t num, void *arg); +typedef void (*i2c_slave_receive_cb_t)(uint8_t num, uint8_t *data, size_t len, bool stop, void *arg); +esp_err_t i2cSlaveAttachCallbacks(uint8_t num, i2c_slave_request_cb_t request_callback, i2c_slave_receive_cb_t receive_callback, void *arg); + +esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t frequency, size_t rx_len, size_t tx_len); +esp_err_t i2cSlaveDeinit(uint8_t num); +size_t i2cSlaveWrite(uint8_t num, const uint8_t *buf, uint32_t len, uint32_t timeout_ms); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_I2C_SUPPORT_SLAVE */ diff --git a/cores/esp32/esp32-hal-i2c.c b/cores/esp32/esp32-hal-i2c.c new file mode 100644 index 0000000..71c8ae1 --- /dev/null +++ b/cores/esp32/esp32-hal-i2c.c @@ -0,0 +1,435 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-i2c.h" + +#if SOC_I2C_SUPPORTED +#include "esp_idf_version.h" +#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0) +#include "esp32-hal.h" +#if !CONFIG_DISABLE_HAL_LOCKS +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#endif +#include "esp_attr.h" +#include "esp_system.h" +#include "soc/soc_caps.h" +#include "soc/i2c_periph.h" +#include "hal/i2c_hal.h" +#include "hal/i2c_ll.h" +#include "driver/i2c.h" +#include "esp32-hal-periman.h" +#include "esp_private/periph_ctrl.h" + +#if SOC_PERIPH_CLK_CTRL_SHARED +#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define I2C_CLOCK_SRC_ATOMIC() +#endif + +#if !SOC_RCC_IS_INDEPENDENT +#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define I2C_RCC_ATOMIC() +#endif + +#if SOC_I2C_SUPPORT_APB || SOC_I2C_SUPPORT_XTAL +#include "esp_private/esp_clk.h" +#endif +#if SOC_I2C_SUPPORT_RTC +#include "clk_ctrl_os.h" +#endif + +typedef volatile struct { + bool initialized; + uint32_t frequency; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t lock; +#endif + int8_t scl; + int8_t sda; + +} i2c_bus_t; + +static i2c_bus_t bus[SOC_I2C_NUM]; + +static bool i2cDetachBus(void *bus_i2c_num) { + uint8_t i2c_num = (int)bus_i2c_num - 1; + if (!bus[i2c_num].initialized) { + return true; + } + esp_err_t err = i2cDeinit(i2c_num); + if (err != ESP_OK) { + log_e("i2cDeinit failed with error: %d", err); + return false; + } + return true; +} + +bool i2cIsInit(uint8_t i2c_num) { + if (i2c_num >= SOC_I2C_NUM) { + return false; + } + return bus[i2c_num].initialized; +} + +esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) { + esp_err_t ret = ESP_OK; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + if (bus[i2c_num].lock == NULL) { + bus[i2c_num].lock = xSemaphoreCreateMutex(); + if (bus[i2c_num].lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return ESP_ERR_NO_MEM; + } + } + //acquire lock + if (xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ESP_FAIL; + } +#endif + if (bus[i2c_num].initialized) { + log_e("bus is already initialized"); + ret = ESP_FAIL; + goto init_fail; + } + + if (!frequency) { + frequency = 100000UL; + } else if (frequency > 1000000UL) { + frequency = 1000000UL; + } + + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SDA, i2cDetachBus); + perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SCL, i2cDetachBus); + + if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) { + ret = ESP_FAIL; + goto init_fail; + } + + log_i("Initializing I2C Master: sda=%d scl=%d freq=%d", sda, scl, frequency); + + i2c_config_t conf = {}; + conf.mode = I2C_MODE_MASTER; + conf.scl_io_num = (gpio_num_t)scl; + conf.sda_io_num = (gpio_num_t)sda; + conf.scl_pullup_en = GPIO_PULLUP_ENABLE; + conf.sda_pullup_en = GPIO_PULLUP_ENABLE; + conf.master.clk_speed = frequency; + conf.clk_flags = I2C_SCLK_SRC_FLAG_FOR_NOMAL; //Any one clock source that is available for the specified frequency may be chosen + + ret = i2c_param_config((i2c_port_t)i2c_num, &conf); + if (ret != ESP_OK) { + log_e("i2c_param_config failed"); + } else { + ret = i2c_driver_install((i2c_port_t)i2c_num, conf.mode, 0, 0, 0); + if (ret != ESP_OK) { + log_e("i2c_driver_install failed"); + } else { + bus[i2c_num].initialized = true; + bus[i2c_num].frequency = frequency; + bus[i2c_num].scl = scl; + bus[i2c_num].sda = sda; + //Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2 + i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT); + if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_MASTER_SDA, (void *)(i2c_num + 1), i2c_num, -1) + || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_MASTER_SCL, (void *)(i2c_num + 1), i2c_num, -1)) { +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock so that i2cDetachBus can execute i2cDeinit + xSemaphoreGive(bus[i2c_num].lock); +#endif + i2cDetachBus((void *)(i2c_num + 1)); + return ESP_FAIL; + } + } + } +init_fail: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cDeinit(uint8_t i2c_num) { + esp_err_t err = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return err; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + } else { + err = i2c_driver_delete((i2c_port_t)i2c_num); + if (err == ESP_OK) { + bus[i2c_num].initialized = false; + perimanClearPinBus(bus[i2c_num].scl); + perimanClearPinBus(bus[i2c_num].sda); + bus[i2c_num].scl = -1; + bus[i2c_num].sda = -1; + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return err; +} + +esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis) { + esp_err_t ret = ESP_FAIL; + i2c_cmd_handle_t cmd = NULL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + + //short implementation does not support zero size writes (example when scanning) PR in IDF? + //ret = i2c_master_write_to_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_PERIOD_MS); + + ret = ESP_OK; + uint8_t cmd_buff[I2C_LINK_RECOMMENDED_SIZE(1)] = {0}; + cmd = i2c_cmd_link_create_static(cmd_buff, I2C_LINK_RECOMMENDED_SIZE(1)); + ret = i2c_master_start(cmd); + if (ret != ESP_OK) { + goto end; + } + ret = i2c_master_write_byte(cmd, (address << 1) | I2C_MASTER_WRITE, true); + if (ret != ESP_OK) { + goto end; + } + if (size) { + ret = i2c_master_write(cmd, buff, size, true); + if (ret != ESP_OK) { + goto end; + } + } + ret = i2c_master_stop(cmd); + if (ret != ESP_OK) { + goto end; + } + ret = i2c_master_cmd_begin((i2c_port_t)i2c_num, cmd, timeOutMillis / portTICK_PERIOD_MS); + +end: + if (cmd != NULL) { + i2c_cmd_link_delete_static(cmd); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount) { + esp_err_t ret = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + } else { + ret = i2c_master_read_from_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_PERIOD_MS); + if (ret == ESP_OK) { + *readCount = size; + } else { + *readCount = 0; + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cWriteReadNonStop( + uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount +) { + esp_err_t ret = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + } else { + ret = i2c_master_write_read_device((i2c_port_t)i2c_num, address, wbuff, wsize, rbuff, rsize, timeOutMillis / portTICK_PERIOD_MS); + if (ret == ESP_OK) { + *readCount = rsize; + } else { + *readCount = 0; + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency) { + esp_err_t ret = ESP_FAIL; + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return ret; + } +#endif + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + goto end; + } + if (bus[i2c_num].frequency == frequency) { + ret = ESP_OK; + goto end; + } + if (!frequency) { + frequency = 100000UL; + } else if (frequency > 1000000UL) { + frequency = 1000000UL; + } + + typedef struct { + soc_module_clk_t clk; /*!< I2C source clock */ + uint32_t clk_freq; /*!< I2C source clock frequency */ + } i2c_clk_alloc_t; + + typedef enum { + I2C_SCLK_DEFAULT = 0, /*!< I2C source clock not selected*/ +#if SOC_I2C_SUPPORT_APB + I2C_SCLK_APB, /*!< I2C source clock from APB, 80M*/ +#endif +#if SOC_I2C_SUPPORT_XTAL + I2C_SCLK_XTAL, /*!< I2C source clock from XTAL, 40M */ +#endif +#if SOC_I2C_SUPPORT_RTC + I2C_SCLK_RTC, /*!< I2C source clock from 8M RTC, 8M */ +#endif +#if SOC_I2C_SUPPORT_REF_TICK + I2C_SCLK_REF_TICK, /*!< I2C source clock from REF_TICK, 1M */ +#endif + I2C_SCLK_MAX, + } i2c_sclk_t; + + // i2c clock characteristic, The order is the same as i2c_sclk_t. + i2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = { + {0, 0}, +#if SOC_I2C_SUPPORT_APB + {SOC_MOD_CLK_APB, esp_clk_apb_freq()}, /*!< I2C APB clock characteristic*/ +#endif +#if SOC_I2C_SUPPORT_XTAL + {SOC_MOD_CLK_XTAL, esp_clk_xtal_freq()}, /*!< I2C XTAL characteristic*/ +#endif +#if SOC_I2C_SUPPORT_RTC + {SOC_MOD_CLK_RC_FAST, periph_rtc_dig_clk8m_get_freq()}, /*!< I2C 20M RTC characteristic*/ +#endif +#if SOC_I2C_SUPPORT_REF_TICK + {SOC_MOD_CLK_REF_TICK, REF_CLK_FREQ}, /*!< I2C REF_TICK characteristic*/ +#endif + }; + + i2c_sclk_t src_clk = I2C_SCLK_DEFAULT; + ret = ESP_OK; + for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) { +#if CONFIG_IDF_TARGET_ESP32S3 + if (clk == I2C_SCLK_RTC) { // RTC clock for s3 is inaccessible now. + continue; + } +#endif + if (frequency <= i2c_clk_alloc[clk].clk_freq) { + src_clk = clk; + break; + } + } + if (src_clk == I2C_SCLK_DEFAULT || src_clk == I2C_SCLK_MAX) { + log_e("clock source could not be selected"); + ret = ESP_FAIL; + } else { + i2c_hal_context_t hal; + hal.dev = I2C_LL_GET_HW(i2c_num); +#if SOC_I2C_SUPPORT_RTC + if (src_clk == I2C_SCLK_RTC) { + periph_rtc_dig_clk8m_enable(); + } +#endif + I2C_CLOCK_SRC_ATOMIC() { + i2c_hal_set_bus_timing(&(hal), frequency, i2c_clk_alloc[src_clk].clk, i2c_clk_alloc[src_clk].clk_freq); + } + bus[i2c_num].frequency = frequency; + //Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2 + i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT); + } + +end: +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(bus[i2c_num].lock); +#endif + return ret; +} + +esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) { + if (i2c_num >= SOC_I2C_NUM) { + return ESP_ERR_INVALID_ARG; + } + if (!bus[i2c_num].initialized) { + log_e("bus is not initialized"); + return ESP_FAIL; + } + *frequency = bus[i2c_num].frequency; + return ESP_OK; +} + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0) */ +#endif /* SOC_I2C_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-i2c.h b/cores/esp32/esp32-hal-i2c.h new file mode 100644 index 0000000..0e4f484 --- /dev/null +++ b/cores/esp32/esp32-hal-i2c.h @@ -0,0 +1,52 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// modified Nov 2017 by Chuck Todd to support Interrupt Driven I/O +// modified Nov 2021 by Hristo Gochkov to support ESP-IDF API + +#ifndef _ESP32_HAL_I2C_H_ +#define _ESP32_HAL_I2C_H_ + +#include "soc/soc_caps.h" +#if SOC_I2C_SUPPORTED +#include "esp_idf_version.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed); +esp_err_t i2cDeinit(uint8_t i2c_num); +esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency); +esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency); +esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis); +esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount); +esp_err_t i2cWriteReadNonStop( + uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount +); +bool i2cIsInit(uint8_t i2c_num); + +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) +void *i2cBusHandle(uint8_t i2c_num); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_I2C_SUPPORTED */ +#endif /* _ESP32_HAL_I2C_H_ */ diff --git a/cores/esp32/esp32-hal-ledc.c b/cores/esp32/esp32-hal-ledc.c new file mode 100644 index 0000000..1847f6a --- /dev/null +++ b/cores/esp32/esp32-hal-ledc.c @@ -0,0 +1,808 @@ +// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc_caps.h" + +#if SOC_LEDC_SUPPORTED +#include "esp32-hal.h" +#include "esp32-hal-ledc.h" +#include "driver/ledc.h" +#include "esp32-hal-periman.h" +#include "soc/gpio_sig_map.h" +#include "esp_rom_gpio.h" +#include "hal/ledc_ll.h" +#if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED +#include +#endif + +#ifdef SOC_LEDC_SUPPORT_HS_MODE +#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM << 1) +#else +#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM) +#endif + +//Use XTAL clock if possible to avoid timer frequency error when setting APB clock < 80 Mhz +//Need to be fixed in ESP-IDF +#ifdef SOC_LEDC_SUPPORT_XTAL_CLOCK +#define LEDC_DEFAULT_CLK LEDC_USE_XTAL_CLK +#else +#define LEDC_DEFAULT_CLK LEDC_AUTO_CLK +#endif + +#define LEDC_MAX_BIT_WIDTH SOC_LEDC_TIMER_BIT_WIDTH + +typedef struct { + int used_channels : LEDC_CHANNELS; // Used channels as a bits +} ledc_periph_t; + +ledc_periph_t ledc_handle = {0}; + +// Helper function to find a timer with matching frequency and resolution +static bool find_matching_timer(uint8_t speed_mode, uint32_t freq, uint8_t resolution, uint8_t *timer_num) { + log_d("Searching for timer with freq=%u, resolution=%u", freq, resolution); + // Check all channels to find one with matching frequency and resolution + for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) { + if (!perimanPinIsValid(i)) { + continue; + } + peripheral_bus_type_t type = perimanGetPinBusType(i); + if (type == ESP32_BUS_TYPE_LEDC) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(i, ESP32_BUS_TYPE_LEDC); + if (bus != NULL && (bus->channel / SOC_LEDC_CHANNEL_NUM) == speed_mode && bus->freq_hz == freq && bus->channel_resolution == resolution) { + log_d("Found matching timer %u for freq=%u, resolution=%u", bus->timer_num, freq, resolution); + *timer_num = bus->timer_num; + return true; + } + } + } + log_d("No matching timer found for freq=%u, resolution=%u", freq, resolution); + return false; +} + +// Helper function to find an unused timer +static bool find_free_timer(uint8_t speed_mode, uint8_t *timer_num) { + // Check which timers are in use + uint8_t used_timers = 0; + for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) { + if (!perimanPinIsValid(i)) { + continue; + } + peripheral_bus_type_t type = perimanGetPinBusType(i); + if (type == ESP32_BUS_TYPE_LEDC) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(i, ESP32_BUS_TYPE_LEDC); + if (bus != NULL && (bus->channel / SOC_LEDC_CHANNEL_NUM) == speed_mode) { + log_d("Timer %u is in use by channel %u", bus->timer_num, bus->channel); + used_timers |= (1 << bus->timer_num); + } + } + } + +#ifndef SOC_LEDC_TIMER_NUM +#define SOC_LEDC_TIMER_NUM 4 +#endif + // Find first unused timer + for (uint8_t i = 0; i < SOC_LEDC_TIMER_NUM; i++) { + if (!(used_timers & (1 << i))) { + log_d("Found free timer %u", i); + *timer_num = i; + return true; + } + } + log_e("No free timers available"); + return false; +} + +// Helper function to remove a channel from a timer and clear timer if no channels are using it +static void remove_channel_from_timer(uint8_t speed_mode, uint8_t timer_num, uint8_t channel) { + log_d("Removing channel %u from timer %u in speed_mode %u", channel, timer_num, speed_mode); + + // Check if any other channels are using this timer + bool timer_in_use = false; + for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) { + if (!perimanPinIsValid(i)) { + continue; + } + peripheral_bus_type_t type = perimanGetPinBusType(i); + if (type == ESP32_BUS_TYPE_LEDC) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(i, ESP32_BUS_TYPE_LEDC); + if (bus != NULL && (bus->channel / SOC_LEDC_CHANNEL_NUM) == speed_mode && bus->timer_num == timer_num && bus->channel != channel) { + log_d("Timer %u is still in use by channel %u", timer_num, bus->channel); + timer_in_use = true; + break; + } + } + } + + if (!timer_in_use) { + log_d("No other channels using timer %u, deconfiguring timer", timer_num); + // Stop the timer + ledc_timer_pause(speed_mode, timer_num); + // Deconfigure the timer + ledc_timer_config_t ledc_timer; + memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t)); + ledc_timer.speed_mode = speed_mode; + ledc_timer.timer_num = timer_num; + ledc_timer.deconfigure = true; + ledc_timer_config(&ledc_timer); + } +} + +static bool fade_initialized = false; + +static ledc_clk_cfg_t clock_source = LEDC_DEFAULT_CLK; + +ledc_clk_cfg_t ledcGetClockSource(void) { + return clock_source; +} + +bool ledcSetClockSource(ledc_clk_cfg_t source) { + if (ledc_handle.used_channels) { + log_e("Cannot change LEDC clock source! LEDC channels in use."); + return false; + } + clock_source = source; + return true; +} + +static bool ledcDetachBus(void *bus) { + ledc_channel_handle_t *handle = (ledc_channel_handle_t *)bus; + bool channel_found = false; + // Check if more pins are attached to the same ledc channel + for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) { + if (!perimanPinIsValid(i) || i == handle->pin) { + continue; //invalid pin or same pin + } + peripheral_bus_type_t type = perimanGetPinBusType(i); + if (type == ESP32_BUS_TYPE_LEDC) { + ledc_channel_handle_t *bus_check = (ledc_channel_handle_t *)perimanGetPinBus(i, ESP32_BUS_TYPE_LEDC); + if (bus_check->channel == handle->channel) { + channel_found = true; + break; + } + } + } + pinMatrixOutDetach(handle->pin, false, false); + if (!channel_found) { + uint8_t group = (handle->channel / SOC_LEDC_CHANNEL_NUM); + remove_channel_from_timer(group, handle->timer_num, handle->channel % SOC_LEDC_CHANNEL_NUM); + ledc_handle.used_channels &= ~(1UL << handle->channel); + } + free(handle); + if (ledc_handle.used_channels == 0) { + ledc_fade_func_uninstall(); + fade_initialized = false; + } + return true; +} + +bool ledcAttachChannel(uint8_t pin, uint32_t freq, uint8_t resolution, uint8_t channel) { + if (channel >= LEDC_CHANNELS) { + log_e("Channel %u is not available (maximum %u)!", channel, LEDC_CHANNELS); + return false; + } + if (freq == 0) { + log_e("LEDC pin %u - frequency can't be zero.", pin); + return false; + } + if (resolution == 0 || resolution > LEDC_MAX_BIT_WIDTH) { + log_e("LEDC pin %u - resolution is zero or it is too big (maximum %u)", pin, LEDC_MAX_BIT_WIDTH); + return false; + } + + perimanSetBusDeinit(ESP32_BUS_TYPE_LEDC, ledcDetachBus); + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + log_e("Pin %u is already attached to LEDC (channel %u, resolution %u)", pin, bus->channel, bus->channel_resolution); + return false; + } + + if (!perimanClearPinBus(pin)) { + log_e("Pin %u is already attached to another bus and failed to detach", pin); + return false; + } + + uint8_t group = (channel / SOC_LEDC_CHANNEL_NUM); + uint8_t timer = 0; + bool channel_used = ledc_handle.used_channels & (1UL << channel); + + if (channel_used) { + log_i("Channel %u is already set up, given frequency and resolution will be ignored", channel); + if (ledc_set_pin(pin, group, channel % SOC_LEDC_CHANNEL_NUM) != ESP_OK) { + log_e("Attaching pin to already used channel failed!"); + return false; + } + } else { + // Find a timer with matching frequency and resolution, or a free timer + if (!find_matching_timer(group, freq, resolution, &timer)) { + if (!find_free_timer(group, &timer)) { + log_w("No free timers available for speed mode %u", group); + return false; + } + + // Configure the timer if we're using a new one + ledc_timer_config_t ledc_timer; + memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t)); + ledc_timer.speed_mode = group; + ledc_timer.timer_num = timer; + ledc_timer.duty_resolution = resolution; + ledc_timer.freq_hz = freq; + ledc_timer.clk_cfg = clock_source; + + if (ledc_timer_config(&ledc_timer) != ESP_OK) { + log_e("ledc setup failed!"); + return false; + } + } + + uint32_t duty = ledc_get_duty(group, (channel % SOC_LEDC_CHANNEL_NUM)); + + ledc_channel_config_t ledc_channel; + memset((void *)&ledc_channel, 0, sizeof(ledc_channel_config_t)); + ledc_channel.speed_mode = group; + ledc_channel.channel = (channel % SOC_LEDC_CHANNEL_NUM); + ledc_channel.timer_sel = timer; + ledc_channel.intr_type = LEDC_INTR_DISABLE; + ledc_channel.gpio_num = pin; + ledc_channel.duty = duty; + ledc_channel.hpoint = 0; + + ledc_channel_config(&ledc_channel); + } + + ledc_channel_handle_t *handle = (ledc_channel_handle_t *)malloc(sizeof(ledc_channel_handle_t)); + handle->pin = pin; + handle->channel = channel; + handle->timer_num = timer; + handle->freq_hz = freq; +#ifndef SOC_LEDC_SUPPORT_FADE_STOP + handle->lock = NULL; +#endif + + //get resolution of selected channel when used + if (channel_used) { + uint32_t channel_resolution = 0; + ledc_ll_get_duty_resolution(LEDC_LL_GET_HW(), group, timer, &channel_resolution); + log_i("Channel %u frequency: %u, resolution: %u", channel, ledc_get_freq(group, timer), channel_resolution); + handle->channel_resolution = (uint8_t)channel_resolution; + } else { + handle->channel_resolution = resolution; + ledc_handle.used_channels |= 1UL << channel; + } + + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_LEDC, (void *)handle, channel, timer)) { + ledcDetachBus((void *)handle); + return false; + } + + log_i("LEDC attached to pin %u (channel %u, resolution %u)", pin, channel, resolution); + return true; +} + +bool ledcAttach(uint8_t pin, uint32_t freq, uint8_t resolution) { + int free_channel = ~ledc_handle.used_channels & (ledc_handle.used_channels + 1); + if (free_channel == 0) { + log_e("No more LEDC channels available! (maximum is %u channels)", LEDC_CHANNELS); + return false; + } + uint8_t channel = __builtin_ctz(free_channel); // Convert the free_channel bit to channel number + + // Try the first available channel + if (ledcAttachChannel(pin, freq, resolution, channel)) { + return true; + } + +#ifdef SOC_LEDC_SUPPORT_HS_MODE + // If first attempt failed and HS mode is supported, try to find a free channel in group 1 + if ((channel / SOC_LEDC_CHANNEL_NUM) == 0) { // First attempt was in group 0 + log_d("LEDC: Group 0 channel %u failed, trying to find a free channel in group 1", channel); + // Find free channels specifically in group 1 + uint32_t group1_mask = ((1UL << SOC_LEDC_CHANNEL_NUM) - 1) << SOC_LEDC_CHANNEL_NUM; + int group1_free_channel = (~ledc_handle.used_channels) & group1_mask; + if (group1_free_channel != 0) { + uint8_t group1_channel = __builtin_ctz(group1_free_channel); + if (ledcAttachChannel(pin, freq, resolution, group1_channel)) { + return true; + } + } + } +#endif + + log_e( + "No free timers available for freq=%u, resolution=%u. To attach a new channel, use the same frequency and resolution as an already attached channel to " + "share its timer.", + freq, resolution + ); + return false; +} + +bool ledcWrite(uint8_t pin, uint32_t duty) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM), channel = (bus->channel % SOC_LEDC_CHANNEL_NUM); + + //Fixing if all bits in resolution is set = LEDC FULL ON + uint32_t max_duty = (1 << bus->channel_resolution) - 1; + + if ((duty == max_duty) && (max_duty != 1)) { + duty = max_duty + 1; + } + + if (ledc_set_duty(group, channel, duty) != ESP_OK) { + log_e("ledc_set_duty failed"); + return false; + } + if (ledc_update_duty(group, channel) != ESP_OK) { + log_e("ledc_update_duty failed"); + return false; + } + + return true; + } + return false; +} + +bool ledcWriteChannel(uint8_t channel, uint32_t duty) { + //check if channel is valid and used + if (channel >= LEDC_CHANNELS || !(ledc_handle.used_channels & (1UL << channel))) { + log_e("Channel %u is not available (maximum %u) or not used!", channel, LEDC_CHANNELS); + return false; + } + uint8_t group = (channel / SOC_LEDC_CHANNEL_NUM); + ledc_timer_t timer; + + // Get the actual timer being used by this channel + ledc_ll_get_channel_timer(LEDC_LL_GET_HW(), group, (channel % SOC_LEDC_CHANNEL_NUM), &timer); + + //Fixing if all bits in resolution is set = LEDC FULL ON + uint32_t resolution = 0; + ledc_ll_get_duty_resolution(LEDC_LL_GET_HW(), group, timer, &resolution); + + uint32_t max_duty = (1 << resolution) - 1; + + if ((duty == max_duty) && (max_duty != 1)) { + duty = max_duty + 1; + } + + if (ledc_set_duty(group, channel, duty) != ESP_OK) { + log_e("ledc_set_duty failed"); + return false; + } + if (ledc_update_duty(group, channel) != ESP_OK) { + log_e("ledc_update_duty failed"); + return false; + } + + return true; +} + +uint32_t ledcRead(uint8_t pin) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM), channel = (bus->channel % SOC_LEDC_CHANNEL_NUM); + return ledc_get_duty(group, channel); + } + return 0; +} + +uint32_t ledcReadFreq(uint8_t pin) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + if (!ledcRead(pin)) { + return 0; + } + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM); + return ledc_get_freq(group, bus->timer_num); + } + return 0; +} + +uint32_t ledcWriteTone(uint8_t pin, uint32_t freq) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + + if (!freq) { + ledcWrite(pin, 0); + return 0; + } + + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM); + + ledc_timer_config_t ledc_timer; + memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t)); + ledc_timer.speed_mode = group; + ledc_timer.timer_num = bus->timer_num; + ledc_timer.duty_resolution = 10; + ledc_timer.freq_hz = freq; + ledc_timer.clk_cfg = clock_source; + + if (ledc_timer_config(&ledc_timer) != ESP_OK) { + log_e("ledcWriteTone configuration failed!"); + return 0; + } + bus->channel_resolution = 10; + + uint32_t res_freq = ledc_get_freq(group, bus->timer_num); + ledcWrite(pin, 0x1FF); + return res_freq; + } + return 0; +} + +uint32_t ledcWriteNote(uint8_t pin, note_t note, uint8_t octave) { + const uint16_t noteFrequencyBase[12] = {// C C# D Eb E F F# G G# A Bb B + 4186, 4435, 4699, 4978, 5274, 5588, 5920, 6272, 6645, 7040, 7459, 7902 + }; + + if (octave > 8 || note >= NOTE_MAX) { + return 0; + } + uint32_t noteFreq = (uint32_t)noteFrequencyBase[note] / (uint32_t)(1 << (8 - octave)); + return ledcWriteTone(pin, noteFreq); +} + +bool ledcDetach(uint8_t pin) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + // will call ledcDetachBus + return perimanClearPinBus(pin); + } else { + log_e("pin %u is not attached to LEDC", pin); + } + return false; +} + +uint32_t ledcChangeFrequency(uint8_t pin, uint32_t freq, uint8_t resolution) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + if (freq == 0) { + log_e("LEDC pin %u - frequency can't be zero.", pin); + return 0; + } + if (resolution == 0 || resolution > LEDC_MAX_BIT_WIDTH) { + log_e("LEDC pin %u - resolution is zero or it is too big (maximum %u)", pin, LEDC_MAX_BIT_WIDTH); + return 0; + } + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM); + + ledc_timer_config_t ledc_timer; + memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t)); + ledc_timer.speed_mode = group; + ledc_timer.timer_num = bus->timer_num; + ledc_timer.duty_resolution = resolution; + ledc_timer.freq_hz = freq; + ledc_timer.clk_cfg = clock_source; + + if (ledc_timer_config(&ledc_timer) != ESP_OK) { + log_e("ledcChangeFrequency failed!"); + return 0; + } + bus->channel_resolution = resolution; + return ledc_get_freq(group, bus->timer_num); + } + return 0; +} + +bool ledcOutputInvert(uint8_t pin, bool out_invert) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + gpio_set_level(pin, out_invert); + +#ifdef CONFIG_IDF_TARGET_ESP32P4 + esp_rom_gpio_connect_out_signal(pin, LEDC_LS_SIG_OUT_PAD_OUT0_IDX + ((bus->channel) % SOC_LEDC_CHANNEL_NUM), out_invert, 0); +#else +#ifdef SOC_LEDC_SUPPORT_HS_MODE + esp_rom_gpio_connect_out_signal( + pin, ((bus->channel / SOC_LEDC_CHANNEL_NUM == 0) ? LEDC_HS_SIG_OUT0_IDX : LEDC_LS_SIG_OUT0_IDX) + ((bus->channel) % SOC_LEDC_CHANNEL_NUM), out_invert, 0 + ); +#else + esp_rom_gpio_connect_out_signal(pin, LEDC_LS_SIG_OUT0_IDX + ((bus->channel) % SOC_LEDC_CHANNEL_NUM), out_invert, 0); +#endif +#endif // ifdef CONFIG_IDF_TARGET_ESP32P4 + return true; + } + return false; +} + +static IRAM_ATTR bool ledcFnWrapper(const ledc_cb_param_t *param, void *user_arg) { + if (param->event == LEDC_FADE_END_EVT) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)user_arg; +#ifndef SOC_LEDC_SUPPORT_FADE_STOP + portBASE_TYPE xTaskWoken = 0; + xSemaphoreGiveFromISR(bus->lock, &xTaskWoken); +#endif + if (bus->fn) { + if (bus->arg) { + ((voidFuncPtrArg)bus->fn)(bus->arg); + } else { + bus->fn(); + } + } + } + return true; +} + +static bool ledcFadeConfig(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + +#ifndef SOC_LEDC_SUPPORT_FADE_STOP +#if !CONFIG_DISABLE_HAL_LOCKS + if (bus->lock == NULL) { + bus->lock = xSemaphoreCreateBinary(); + if (bus->lock == NULL) { + log_e("xSemaphoreCreateBinary failed"); + return false; + } + xSemaphoreGive(bus->lock); + } + //acquire lock + if (xSemaphoreTake(bus->lock, 0) != pdTRUE) { + log_e("LEDC Fade is still running on pin %u! SoC does not support stopping fade.", pin); + return false; + } +#endif +#endif + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM), channel = (bus->channel % SOC_LEDC_CHANNEL_NUM); + + // Initialize fade service. + if (!fade_initialized) { + ledc_fade_func_install(0); + fade_initialized = true; + } + + bus->fn = (voidFuncPtr)userFunc; + bus->arg = arg; + + ledc_cbs_t callbacks = {.fade_cb = ledcFnWrapper}; + ledc_cb_register(group, channel, &callbacks, (void *)bus); + + //Fixing if all bits in resolution is set = LEDC FULL ON + uint32_t max_duty = (1 << bus->channel_resolution) - 1; + + if ((target_duty == max_duty) && (max_duty != 1)) { + target_duty = max_duty + 1; + } else if ((start_duty == max_duty) && (max_duty != 1)) { + start_duty = max_duty + 1; + } + +#if SOC_LEDC_SUPPORT_FADE_STOP + ledc_fade_stop(group, channel); +#endif + + if (ledc_set_duty_and_update(group, channel, start_duty, 0) != ESP_OK) { + log_e("ledc_set_duty_and_update failed"); + return false; + } + // Wait for LEDCs next PWM cycle to update duty (~ 1-2 ms) + while (ledc_get_duty(group, channel) != start_duty); + + if (ledc_set_fade_time_and_start(group, channel, target_duty, max_fade_time_ms, LEDC_FADE_NO_WAIT) != ESP_OK) { + log_e("ledc_set_fade_time_and_start failed"); + return false; + } + } else { + log_e("Pin %u is not attached to LEDC. Call ledcAttach first!", pin); + return false; + } + return true; +} + +bool ledcFade(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms) { + return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, NULL, NULL); +} + +bool ledcFadeWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, voidFuncPtr userFunc) { + return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, (voidFuncPtrArg)userFunc, NULL); +} + +bool ledcFadeWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) { + return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, userFunc, arg); +} + +#ifdef SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED +// Default gamma factor for gamma correction (common value for LEDs) +static float ledcGammaFactor = 2.8; +// Gamma correction LUT support +static const float *ledcGammaLUT = NULL; +static uint16_t ledcGammaLUTSize = 0; +// Global variable to store current resolution for gamma callback +static uint8_t ledcGammaResolution = 13; + +bool ledcSetGammaTable(const float *gamma_table, uint16_t size) { + if (gamma_table == NULL || size == 0) { + log_e("Invalid gamma table or size"); + return false; + } + ledcGammaLUT = gamma_table; + ledcGammaLUTSize = size; + log_i("Custom gamma LUT set with %u entries", size); + return true; +} + +void ledcClearGammaTable(void) { + ledcGammaLUT = NULL; + ledcGammaLUTSize = 0; + log_i("Gamma LUT cleared, using mathematical calculation"); +} + +void ledcSetGammaFactor(float factor) { + ledcGammaFactor = factor; +} + +// Gamma correction calculator function +static uint32_t ledcGammaCorrection(uint32_t duty) { + if (duty == 0) { + return 0; + } + + uint32_t max_duty = (1U << ledcGammaResolution) - 1; + if (duty >= (1U << ledcGammaResolution)) { + return max_duty; + } + + // Use LUT if provided, otherwise use mathematical calculation + if (ledcGammaLUT != NULL && ledcGammaLUTSize > 0) { + // LUT-based gamma correction + uint32_t lut_index = (duty * (ledcGammaLUTSize - 1)) / max_duty; + if (lut_index >= ledcGammaLUTSize) { + lut_index = ledcGammaLUTSize - 1; + } + + float corrected_normalized = ledcGammaLUT[lut_index]; + return (uint32_t)(corrected_normalized * max_duty); + } else { + // Mathematical gamma correction + double normalized = (double)duty / (1U << ledcGammaResolution); + double corrected = pow(normalized, ledcGammaFactor); + return (uint32_t)(corrected * (1U << ledcGammaResolution)); + } +} + +static bool ledcFadeGammaConfig(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { + +#ifndef SOC_LEDC_SUPPORT_FADE_STOP +#if !CONFIG_DISABLE_HAL_LOCKS + if (bus->lock == NULL) { + bus->lock = xSemaphoreCreateBinary(); + if (bus->lock == NULL) { + log_e("xSemaphoreCreateBinary failed"); + return false; + } + xSemaphoreGive(bus->lock); + } + //acquire lock + if (xSemaphoreTake(bus->lock, 0) != pdTRUE) { + log_e("LEDC Fade is still running on pin %u! SoC does not support stopping fade.", pin); + return false; + } +#endif +#endif + uint8_t group = (bus->channel / SOC_LEDC_CHANNEL_NUM), channel = (bus->channel % SOC_LEDC_CHANNEL_NUM); + + // Initialize fade service. + if (!fade_initialized) { + ledc_fade_func_install(0); + fade_initialized = true; + } + + bus->fn = (voidFuncPtr)userFunc; + bus->arg = arg; + + ledc_cbs_t callbacks = {.fade_cb = ledcFnWrapper}; + ledc_cb_register(group, channel, &callbacks, (void *)bus); + + // Prepare gamma curve fade parameters + ledc_fade_param_config_t fade_params[SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX]; + uint32_t actual_fade_ranges = 0; + + // Use a moderate number of linear segments for smooth gamma curve + const uint32_t linear_fade_segments = 12; + + // Set the global resolution for gamma correction + ledcGammaResolution = bus->channel_resolution; + + // Fill multi-fade parameter list using ESP-IDF API + esp_err_t err = ledc_fill_multi_fade_param_list( + group, channel, start_duty, target_duty, linear_fade_segments, max_fade_time_ms, ledcGammaCorrection, SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, fade_params, + &actual_fade_ranges + ); + + if (err != ESP_OK) { + log_e("ledc_fill_multi_fade_param_list failed: %s", esp_err_to_name(err)); + return false; + } + + // Apply the gamma-corrected start duty + uint32_t gamma_start_duty = ledcGammaCorrection(start_duty); + + // Set multi-fade parameters + err = ledc_set_multi_fade(group, channel, gamma_start_duty, fade_params, actual_fade_ranges); + if (err != ESP_OK) { + log_e("ledc_set_multi_fade failed: %s", esp_err_to_name(err)); + return false; + } + + // Start the gamma curve fade + err = ledc_fade_start(group, channel, LEDC_FADE_NO_WAIT); + if (err != ESP_OK) { + log_e("ledc_fade_start failed: %s", esp_err_to_name(err)); + return false; + } + + log_d("Gamma curve fade started on pin %u: %u -> %u over %dms", pin, start_duty, target_duty, max_fade_time_ms); + + } else { + log_e("Pin %u is not attached to LEDC. Call ledcAttach first!", pin); + return false; + } + return true; +} + +bool ledcFadeGamma(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms) { + return ledcFadeGammaConfig(pin, start_duty, target_duty, max_fade_time_ms, NULL, NULL); +} + +bool ledcFadeGammaWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, voidFuncPtr userFunc) { + return ledcFadeGammaConfig(pin, start_duty, target_duty, max_fade_time_ms, (voidFuncPtrArg)userFunc, NULL); +} + +bool ledcFadeGammaWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) { + return ledcFadeGammaConfig(pin, start_duty, target_duty, max_fade_time_ms, userFunc, arg); +} + +#endif /* SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED */ + +static uint8_t analog_resolution = 8; +static int analog_frequency = 1000; +void analogWrite(uint8_t pin, int value) { + // Use ledc hardware for internal pins + if (pin < SOC_GPIO_PIN_COUNT) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus == NULL && perimanClearPinBus(pin)) { + if (ledcAttach(pin, analog_frequency, analog_resolution) == 0) { + log_e("analogWrite setup failed (freq = %u, resolution = %u). Try setting different resolution or frequency"); + return; + } + } + ledcWrite(pin, value); + } +} + +void analogWriteFrequency(uint8_t pin, uint32_t freq) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { // if pin is attached to LEDC change frequency, otherwise update the global frequency + if (ledcChangeFrequency(pin, freq, analog_resolution) == 0) { + log_e("analogWrite frequency cant be set due to selected resolution! Try to adjust resolution first"); + return; + } + } + analog_frequency = freq; +} + +void analogWriteResolution(uint8_t pin, uint8_t resolution) { + ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC); + if (bus != NULL) { // if pin is attached to LEDC change resolution, otherwise update the global resolution + if (ledcChangeFrequency(pin, analog_frequency, resolution) == 0) { + log_e("analogWrite resolution cant be set due to selected frequency! Try to adjust frequency first"); + return; + } + } + analog_resolution = resolution; +} + +#endif /* SOC_LEDC_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-ledc.h b/cores/esp32/esp32-hal-ledc.h new file mode 100644 index 0000000..1663b88 --- /dev/null +++ b/cores/esp32/esp32-hal-ledc.h @@ -0,0 +1,319 @@ +// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_LEDC_H_ +#define _ESP32_HAL_LEDC_H_ + +#include "soc/soc_caps.h" +#if SOC_LEDC_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "hal/ledc_types.h" + +typedef enum { + NOTE_C, + NOTE_Cs, + NOTE_D, + NOTE_Eb, + NOTE_E, + NOTE_F, + NOTE_Fs, + NOTE_G, + NOTE_Gs, + NOTE_A, + NOTE_Bb, + NOTE_B, + NOTE_MAX +} note_t; + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void *); + +typedef struct { + uint8_t pin; // Pin assigned to channel + uint8_t channel; // Channel number + uint8_t channel_resolution; // Resolution of channel + uint8_t timer_num; // Timer number used by this channel + uint32_t freq_hz; // Frequency configured for this channel + voidFuncPtr fn; + void *arg; +#ifndef SOC_LEDC_SUPPORT_FADE_STOP + SemaphoreHandle_t lock; //xSemaphoreCreateBinary +#endif +} ledc_channel_handle_t; + +/** + * @brief Get the LEDC clock source. + * + * @return LEDC clock source. + */ +ledc_clk_cfg_t ledcGetClockSource(void); + +/** + * @brief Set the LEDC clock source. + * + * @param source LEDC clock source to set. + * + * @return true if LEDC clock source was successfully set, false otherwise. + */ +bool ledcSetClockSource(ledc_clk_cfg_t source); + +/** + * @brief Attach a pin to the LEDC driver, with a given frequency and resolution. + * Channel is automatically assigned. + * + * @param pin GPIO pin + * @param freq frequency of PWM signal + * @param resolution resolution for LEDC pin + * + * @return true if configuration is successful and pin was successfully attached, false otherwise. + */ +bool ledcAttach(uint8_t pin, uint32_t freq, uint8_t resolution); + +/** + * @brief Attach a pin to the LEDC driver, with a given frequency, resolution and channel. + * + * @param pin GPIO pin + * @param freq frequency of PWM signal + * @param resolution resolution for LEDC pin + * @param channel LEDC channel to attach to + * + * @return true if configuration is successful and pin was successfully attached, false otherwise. + */ +bool ledcAttachChannel(uint8_t pin, uint32_t freq, uint8_t resolution, uint8_t channel); + +/** + * @brief Set the duty cycle of a given pin. + * + * @param pin GPIO pin + * @param duty duty cycle to set + * + * @return true if duty cycle was successfully set, false otherwise. + */ +bool ledcWrite(uint8_t pin, uint32_t duty); + +/** + * @brief Set the duty cycle of a given channel. + * + * @param channel LEDC channel + * @param duty duty cycle to set + * + * @return true if duty cycle was successfully set, false otherwise. + */ +bool ledcWriteChannel(uint8_t channel, uint32_t duty); + +/** + * @brief Sets the duty to 50 % PWM tone on selected frequency. + * + * @param pin GPIO pin + * @param freq select frequency of pwm signal. If frequency is 0, duty will be set to 0. + * + * @return frequency if tone was successfully set. + * If ``0`` is returned, error occurs and LEDC pin was not configured. + */ +uint32_t ledcWriteTone(uint8_t pin, uint32_t freq); + +/** + * @brief Sets the LEDC pin to specific note. + * + * @param pin GPIO pin + * @param note select note to be set (NOTE_C, NOTE_Cs, NOTE_D, NOTE_Eb, NOTE_E, NOTE_F, NOTE_Fs, NOTE_G, NOTE_Gs, NOTE_A, NOTE_Bb, NOTE_B). + * @param octave select octave for note. + * + * @return frequency if note was successfully set. + * If ``0`` is returned, error occurs and LEDC pin was not configured. + */ +uint32_t ledcWriteNote(uint8_t pin, note_t note, uint8_t octave); + +/** + * @brief Read the duty cycle of a given LEDC pin. + * + * @param pin GPIO pin + * + * @return duty cycle of selected LEDC pin. + */ +uint32_t ledcRead(uint8_t pin); + +/** + * @brief Read the frequency of a given LEDC pin. + * + * @param pin GPIO pin + * + * @return frequency of selected LEDC pin. + */ +uint32_t ledcReadFreq(uint8_t pin); + +/** + * @brief Detach a pin from the LEDC driver. + * + * @param pin GPIO pin + * + * @return true if pin was successfully detached, false otherwise. + */ +bool ledcDetach(uint8_t pin); + +/** + * @brief Change the frequency and resolution of a given LEDC pin. + * + * @param pin GPIO pin + * @param freq frequency of PWM signal + * @param resolution resolution for LEDC pin + * + * @return frequency configured for the LEDC channel. + * If ``0`` is returned, error occurs and LEDC pin was not configured. + */ +uint32_t ledcChangeFrequency(uint8_t pin, uint32_t freq, uint8_t resolution); + +/** + * @brief Sets inverting of the output signal for a given LEDC pin. + * + * @param pin GPIO pin + * @param out_invert select, if output should be inverted (true = inverting output). + * + * @return true if output inverting was successfully set, false otherwise. + */ +bool ledcOutputInvert(uint8_t pin, bool out_invert); + +//Fade functions +/** + * @brief Setup and start a fade on a given LEDC pin. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * + * @return true if fade was successfully set and started, false otherwise. + */ +bool ledcFade(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms); + +/** + * @brief Setup and start a fade on a given LEDC pin with a callback function. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * @param userFunc callback function to be called after fade is finished + * + * @return true if fade was successfully set and started, false otherwise. + */ +bool ledcFadeWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void)); + +/** + * @brief Setup and start a fade on a given LEDC pin with a callback function and argument. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * @param userFunc callback function to be called after fade is finished + * @param arg argument to be passed to the callback function + * + * @return true if fade was successfully set and started, false otherwise. + */ +bool ledcFadeWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg); + +//Gamma Curve Fade functions - only available on supported chips +#ifdef SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED + +/** + * @brief Set a custom gamma correction lookup table for gamma curve fading. + * The LUT should contain normalized values (0.0 to 1.0) representing + * the gamma-corrected brightness curve. + * + * @param gamma_table Pointer to array of float values (0.0 to 1.0) + * @param size Number of entries in the lookup table + * + * @return true if gamma table was successfully set, false otherwise. + * + * @note The LUT array must remain valid for as long as gamma fading is used. + * Larger tables provide smoother transitions but use more memory. + */ +bool ledcSetGammaTable(const float *gamma_table, uint16_t size); + +/** + * @brief Clear the current gamma correction lookup table. + * After calling this, gamma correction will use mathematical + * calculation with the default gamma factor (2.8). + */ +void ledcClearGammaTable(void); + +/** + * @brief Set the gamma factor for gamma correction. + * + * @param factor Gamma factor to use for gamma correction. + */ +void ledcSetGammaFactor(float factor); + +/** + * @brief Setup and start a gamma curve fade on a given LEDC pin. + * Gamma correction makes LED brightness changes appear more gradual to human eyes. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * + * @return true if gamma fade was successfully set and started, false otherwise. + * + * @note This function is only available on ESP32 variants that support gamma curve fading. + */ +bool ledcFadeGamma(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms); + +/** + * @brief Setup and start a gamma curve fade on a given LEDC pin with a callback function. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * @param userFunc callback function to be called after fade is finished + * + * @return true if gamma fade was successfully set and started, false otherwise. + * + * @note This function is only available on ESP32 variants that support gamma curve fading. + */ +bool ledcFadeGammaWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void)); + +/** + * @brief Setup and start a gamma curve fade on a given LEDC pin with a callback function and argument. + * + * @param pin GPIO pin + * @param start_duty initial duty cycle of the fade + * @param target_duty target duty cycle of the fade + * @param max_fade_time_ms maximum fade time in milliseconds + * @param userFunc callback function to be called after fade is finished + * @param arg argument to be passed to the callback function + * + * @return true if gamma fade was successfully set and started, false otherwise. + * + * @note This function is only available on ESP32 variants that support gamma curve fading. + */ +bool ledcFadeGammaWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg); +#endif // SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_LEDC_SUPPORTED */ +#endif /* _ESP32_HAL_LEDC_H_ */ diff --git a/cores/esp32/esp32-hal-log-wrapper.c b/cores/esp32/esp32-hal-log-wrapper.c new file mode 100644 index 0000000..785c0a5 --- /dev/null +++ b/cores/esp32/esp32-hal-log-wrapper.c @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" + +/* + * This file provides wrapper implementations for esp_log_write and esp_log_writev + * when CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP is not enabled. + * + * When CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP is enabled, the esp_diagnostics component + * provides these wrappers. However, when it's disabled, WiFi libraries still expect + * these wrapper functions to exist, causing linker errors. + * + * This implementation provides simple pass-through wrappers that call the real + * ESP-IDF logging functions, ensuring compatibility without requiring esp_diagnostics. + */ + +#ifndef CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP + +#include +#include "esp_log.h" + +// Declare the real functions that will be wrapped by the linker +void __real_esp_log_write(esp_log_level_t level, const char *tag, const char *format, ...); +void __real_esp_log_writev(esp_log_level_t level, const char *tag, const char *format, va_list args); + +// Wrapper implementations that simply call through to the real functions +void __wrap_esp_log_write(esp_log_level_t level, const char *tag, const char *format, ...) { + va_list args; + va_start(args, format); + __real_esp_log_writev(level, tag, format, args); + va_end(args); +} + +void __wrap_esp_log_writev(esp_log_level_t level, const char *tag, const char *format, va_list args) { + __real_esp_log_writev(level, tag, format, args); +} + +#endif // !CONFIG_DIAG_USE_EXTERNAL_LOG_WRAP diff --git a/cores/esp32/esp32-hal-log.h b/cores/esp32/esp32-hal-log.h new file mode 100644 index 0000000..da63c6d --- /dev/null +++ b/cores/esp32/esp32-hal-log.h @@ -0,0 +1,349 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __ARDUHAL_LOG_H__ +#define __ARDUHAL_LOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdkconfig.h" +#include "esp_timer.h" +#include "rom/ets_sys.h" + +#define ARDUHAL_LOG_LEVEL_NONE (0) +#define ARDUHAL_LOG_LEVEL_ERROR (1) +#define ARDUHAL_LOG_LEVEL_WARN (2) +#define ARDUHAL_LOG_LEVEL_INFO (3) +#define ARDUHAL_LOG_LEVEL_DEBUG (4) +#define ARDUHAL_LOG_LEVEL_VERBOSE (5) + +#ifndef CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL +#define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL ARDUHAL_LOG_LEVEL_NONE +#endif + +#ifndef CORE_DEBUG_LEVEL +#define ARDUHAL_LOG_LEVEL CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL +#else +#define ARDUHAL_LOG_LEVEL CORE_DEBUG_LEVEL +#ifdef USE_ESP_IDF_LOG +#ifndef LOG_LOCAL_LEVEL +#define LOG_LOCAL_LEVEL CORE_DEBUG_LEVEL +#endif +#endif +#endif + +#ifndef CONFIG_ARDUHAL_LOG_COLORS +#define CONFIG_ARDUHAL_LOG_COLORS 0 +#endif + +#if CONFIG_ARDUHAL_LOG_COLORS +#define ARDUHAL_LOG_COLOR_BLACK "30" +#define ARDUHAL_LOG_COLOR_RED "31" //ERROR +#define ARDUHAL_LOG_COLOR_GREEN "32" //INFO +#define ARDUHAL_LOG_COLOR_YELLOW "33" //WARNING +#define ARDUHAL_LOG_COLOR_BLUE "34" +#define ARDUHAL_LOG_COLOR_MAGENTA "35" +#define ARDUHAL_LOG_COLOR_CYAN "36" //DEBUG +#define ARDUHAL_LOG_COLOR_GRAY "37" //VERBOSE +#define ARDUHAL_LOG_COLOR_WHITE "38" + +#define ARDUHAL_LOG_COLOR(COLOR) "\033[0;" COLOR "m" +#define ARDUHAL_LOG_BOLD(COLOR) "\033[1;" COLOR "m" +#define ARDUHAL_LOG_RESET_COLOR "\033[0m" + +#define ARDUHAL_LOG_COLOR_E ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_RED) +#define ARDUHAL_LOG_COLOR_W ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_YELLOW) +#define ARDUHAL_LOG_COLOR_I ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GREEN) +#define ARDUHAL_LOG_COLOR_D ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_CYAN) +#define ARDUHAL_LOG_COLOR_V ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GRAY) +#define ARDUHAL_LOG_COLOR_PRINT(letter) log_printf(ARDUHAL_LOG_COLOR_##letter) +#define ARDUHAL_LOG_COLOR_PRINT_END log_printf(ARDUHAL_LOG_RESET_COLOR) +#else +#define ARDUHAL_LOG_COLOR_E +#define ARDUHAL_LOG_COLOR_W +#define ARDUHAL_LOG_COLOR_I +#define ARDUHAL_LOG_COLOR_D +#define ARDUHAL_LOG_COLOR_V +#define ARDUHAL_LOG_RESET_COLOR +#define ARDUHAL_LOG_COLOR_PRINT(letter) +#define ARDUHAL_LOG_COLOR_PRINT_END +#endif + +#ifdef USE_ESP_IDF_LOG +#ifndef ARDUHAL_ESP_LOG_TAG +#define ARDUHAL_ESP_LOG_TAG "ARDUINO" +#endif +#endif + +const char *pathToFileName(const char *path); +int log_printf(const char *fmt, ...); +void log_print_buf(const uint8_t *b, size_t len); + +#define ARDUHAL_SHORT_LOG_FORMAT(letter, format) ARDUHAL_LOG_COLOR_##letter format ARDUHAL_LOG_RESET_COLOR "\r\n" +#define ARDUHAL_LOG_FORMAT(letter, format) \ + ARDUHAL_LOG_COLOR_##letter "[%6u][" #letter "][%s:%u] %s(): " format ARDUHAL_LOG_RESET_COLOR "\r\n", (unsigned long)(esp_timer_get_time() / 1000ULL), \ + pathToFileName(__FILE__), __LINE__, __FUNCTION__ + +//esp_rom_printf(DRAM_STR("ST:%d\n"), frame_pos); + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE +#ifndef USE_ESP_IDF_LOG +#define log_v(format, ...) log_printf(ARDUHAL_LOG_FORMAT(V, format), ##__VA_ARGS__) +#define isr_log_v(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(V, format), ##__VA_ARGS__) +#define log_buf_v(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(V); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_v(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_VERBOSE, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_v(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_v(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_VERBOSE); \ + } while (0) +#endif +#else +#define log_v(format, ...) \ + do { \ + } while (0) +#define isr_log_v(format, ...) \ + do { \ + } while (0) +#define log_buf_v(b, l) \ + do { \ + } while (0) +#endif + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG +#ifndef USE_ESP_IDF_LOG +#define log_d(format, ...) log_printf(ARDUHAL_LOG_FORMAT(D, format), ##__VA_ARGS__) +#define isr_log_d(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(D, format), ##__VA_ARGS__) +#define log_buf_d(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(D); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_d(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_DEBUG, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_d(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_d(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_DEBUG); \ + } while (0) +#endif +#else +#define log_d(format, ...) \ + do { \ + } while (0) +#define isr_log_d(format, ...) \ + do { \ + } while (0) +#define log_buf_d(b, l) \ + do { \ + } while (0) +#endif + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO +#ifndef USE_ESP_IDF_LOG +#define log_i(format, ...) log_printf(ARDUHAL_LOG_FORMAT(I, format), ##__VA_ARGS__) +#define isr_log_i(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(I, format), ##__VA_ARGS__) +#define log_buf_i(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(I); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_i(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_INFO, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_i(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_i(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_INFO); \ + } while (0) +#endif +#else +#define log_i(format, ...) \ + do { \ + } while (0) +#define isr_log_i(format, ...) \ + do { \ + } while (0) +#define log_buf_i(b, l) \ + do { \ + } while (0) +#endif + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_WARN +#ifndef USE_ESP_IDF_LOG +#define log_w(format, ...) log_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__) +#define isr_log_w(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__) +#define log_buf_w(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(W); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_w(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_WARN, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_w(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_w(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_WARN); \ + } while (0) +#endif +#else +#define log_w(format, ...) \ + do { \ + } while (0) +#define isr_log_w(format, ...) \ + do { \ + } while (0) +#define log_buf_w(b, l) \ + do { \ + } while (0) +#endif + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR +#ifndef USE_ESP_IDF_LOG +#define log_e(format, ...) log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__) +#define isr_log_e(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__) +#define log_buf_e(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(E); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_e(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_e(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_e(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_ERROR); \ + } while (0) +#endif +#else +#define log_e(format, ...) \ + do { \ + } while (0) +#define isr_log_e(format, ...) \ + do { \ + } while (0) +#define log_buf_e(b, l) \ + do { \ + } while (0) +#endif + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_NONE +#ifndef USE_ESP_IDF_LOG +#define log_n(format, ...) log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__) +#define isr_log_n(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__) +#define log_buf_n(b, l) \ + do { \ + ARDUHAL_LOG_COLOR_PRINT(E); \ + log_print_buf(b, l); \ + ARDUHAL_LOG_COLOR_PRINT_END; \ + } while (0) +#else +#define log_n(format, ...) \ + do { \ + ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \ + } while (0) +#define isr_log_n(format, ...) \ + do { \ + ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \ + } while (0) +#define log_buf_n(b, l) \ + do { \ + ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_ERROR); \ + } while (0) +#endif +#else +#define log_n(format, ...) \ + do { \ + } while (0) +#define isr_log_n(format, ...) \ + do { \ + } while (0) +#define log_buf_n(b, l) \ + do { \ + } while (0) +#endif + +#include "esp_log.h" + +#ifndef USE_ESP_IDF_LOG +#ifdef CONFIG_ARDUHAL_ESP_LOG +#undef ESP_LOGE +#undef ESP_LOGW +#undef ESP_LOGI +#undef ESP_LOGD +#undef ESP_LOGV +#undef ESP_EARLY_LOGE +#undef ESP_EARLY_LOGW +#undef ESP_EARLY_LOGI +#undef ESP_EARLY_LOGD +#undef ESP_EARLY_LOGV + +#define ESP_LOGE(tag, format, ...) log_e("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_LOGW(tag, format, ...) log_w("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_LOGI(tag, format, ...) log_i("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_LOGD(tag, format, ...) log_d("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_LOGV(tag, format, ...) log_v("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGE(tag, format, ...) isr_log_e("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGW(tag, format, ...) isr_log_w("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGI(tag, format, ...) isr_log_i("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGD(tag, format, ...) isr_log_d("[%s] " format, tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGV(tag, format, ...) isr_log_v("[%s] " format, tag, ##__VA_ARGS__) +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_LOGGING_H__ */ diff --git a/cores/esp32/esp32-hal-matrix.c b/cores/esp32/esp32-hal-matrix.c new file mode 100644 index 0000000..f609d9e --- /dev/null +++ b/cores/esp32/esp32-hal-matrix.c @@ -0,0 +1,69 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-matrix.h" +#include "esp_attr.h" + +#include "esp_system.h" +#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ +#include "soc/gpio_pins.h" +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "esp32/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/gpio.h" +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif +#else // ESP32 Before IDF 4.0 +#include "rom/gpio.h" +#define GPIO_MATRIX_CONST_ZERO_INPUT GPIO_FUNC_IN_LOW +#define GPIO_MATRIX_CONST_ONE_INPUT GPIO_FUNC_IN_HIGH +#endif + +void ARDUINO_ISR_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) { + gpio_matrix_out(pin, function, invertOut, invertEnable); +} + +void ARDUINO_ISR_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) { + gpio_matrix_out(pin, SIG_GPIO_OUT_IDX, invertOut, invertEnable); +} + +void ARDUINO_ISR_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) { + gpio_matrix_in(pin, signal, inverted); +} + +void ARDUINO_ISR_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) { + gpio_matrix_in(high ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT, signal, inverted); +} +/* +void ARDUINO_ISR_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){ + intr_matrix_set(PRO_CPU_NUM, source, inum); +} +*/ diff --git a/cores/esp32/esp32-hal-matrix.h b/cores/esp32/esp32-hal-matrix.h new file mode 100644 index 0000000..f7c99ae --- /dev/null +++ b/cores/esp32/esp32-hal-matrix.h @@ -0,0 +1,34 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_MATRIX_H_ +#define _ESP32_HAL_MATRIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "soc/gpio_sig_map.h" + +void pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable); +void pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable); +void pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted); +void pinMatrixInDetach(uint8_t signal, bool high, bool inverted); + +#ifdef __cplusplus +} +#endif + +#endif /* COMPONENTS_ARDUHAL_INCLUDE_ESP32_HAL_MATRIX_H_ */ diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c new file mode 100644 index 0000000..a0f8493 --- /dev/null +++ b/cores/esp32/esp32-hal-misc.c @@ -0,0 +1,457 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_attr.h" +#include "nvs_flash.h" +#include "nvs.h" +#include "esp_partition.h" +#include "esp_log.h" +#include "esp_timer.h" +#ifdef CONFIG_APP_ROLLBACK_ENABLE +#include "esp_ota_ops.h" +#endif //CONFIG_APP_ROLLBACK_ENABLE +#include "esp_private/startup_internal.h" +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && SOC_BT_SUPPORTED && __has_include("esp_bt.h") +#include "esp_bt.h" +#endif +#include +#include "soc/rtc.h" +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) +#include "soc/rtc_cntl_reg.h" +#include "soc/syscon_reg.h" +#endif +#include "esp_task_wdt.h" +#include "esp32-hal.h" + +#include "esp_system.h" +#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ + +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "esp32/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/rtc.h" +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif + +#if SOC_TEMP_SENSOR_SUPPORTED +#include "driver/temperature_sensor.h" +#endif + +#else // ESP32 Before IDF 4.0 +#include "rom/rtc.h" +#endif + +//Undocumented!!! Get chip temperature in Fahrenheit +//Source: https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_int_temp_sensor/ESP32_int_temp_sensor.ino +#ifdef CONFIG_IDF_TARGET_ESP32 +uint8_t temprature_sens_read(); + +float temperatureRead() { + return (temprature_sens_read() - 32) / 1.8; +} +#elif SOC_TEMP_SENSOR_SUPPORTED +static temperature_sensor_handle_t temp_sensor = NULL; + +static bool temperatureReadInit() { + static volatile bool initialized = false; + if (!initialized) { + initialized = true; + //Install temperature sensor, expected temp ranger range: 10~50 ℃ + temperature_sensor_config_t temp_sensor_config = TEMPERATURE_SENSOR_CONFIG_DEFAULT(10, 50); + if (temperature_sensor_install(&temp_sensor_config, &temp_sensor) != ESP_OK) { + initialized = false; + temp_sensor = NULL; + log_e("temperature_sensor_install failed"); + } else if (temperature_sensor_enable(temp_sensor) != ESP_OK) { + temperature_sensor_uninstall(temp_sensor); + initialized = false; + temp_sensor = NULL; + log_e("temperature_sensor_enable failed"); + } + } + return initialized; +} + +float temperatureRead() { + float result = NAN; + if (temperatureReadInit()) { + if (temperature_sensor_get_celsius(temp_sensor, &result) != ESP_OK) { + log_e("temperature_sensor_get_celsius failed"); + } + } + return result; +} +#endif + +void __yield() { + vPortYield(); +} + +void yield() __attribute__((weak, alias("__yield"))); + +#if CONFIG_AUTOSTART_ARDUINO + +extern TaskHandle_t loopTaskHandle; +extern bool loopTaskWDTEnabled; + +void enableLoopWDT() { + if (loopTaskHandle != NULL) { + if (esp_task_wdt_add(loopTaskHandle) != ESP_OK) { + log_e("Failed to add loop task to WDT"); + } else { + loopTaskWDTEnabled = true; + } + } +} + +void disableLoopWDT() { + if (loopTaskHandle != NULL && loopTaskWDTEnabled) { + loopTaskWDTEnabled = false; + if (esp_task_wdt_delete(loopTaskHandle) != ESP_OK) { + log_e("Failed to remove loop task from WDT"); + } + } +} + +void feedLoopWDT() { + esp_err_t err = esp_task_wdt_reset(); + if (err != ESP_OK) { + log_e("Failed to feed WDT! Error: %d", err); + } +} +#endif + +void enableCore0WDT() { + TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCore(0); + if (idle_0 == NULL || esp_task_wdt_add(idle_0) != ESP_OK) { + log_e("Failed to add Core 0 IDLE task to WDT"); + } +} + +bool disableCore0WDT() { + TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCore(0); + if (idle_0 == NULL || esp_task_wdt_status(idle_0) || esp_task_wdt_delete(idle_0) != ESP_OK) { + log_e("Failed to remove Core 0 IDLE task from WDT"); + return false; + } + return true; +} + +#ifndef CONFIG_FREERTOS_UNICORE +void enableCore1WDT() { + TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCore(1); + if (idle_1 == NULL || esp_task_wdt_add(idle_1) != ESP_OK) { + log_e("Failed to add Core 1 IDLE task to WDT"); + } +} + +bool disableCore1WDT() { + TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCore(1); + if (idle_1 == NULL || esp_task_wdt_status(idle_1) || esp_task_wdt_delete(idle_1) != ESP_OK) { + log_e("Failed to remove Core 1 IDLE task from WDT"); + return false; + } + return true; +} +#endif + +BaseType_t xTaskCreateUniversal( + TaskFunction_t pxTaskCode, const char *const pcName, const uint32_t usStackDepth, void *const pvParameters, UBaseType_t uxPriority, + TaskHandle_t *const pxCreatedTask, const BaseType_t xCoreID +) { +#ifndef CONFIG_FREERTOS_UNICORE + if (xCoreID >= 0 && xCoreID < 2) { + return xTaskCreatePinnedToCore(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, xCoreID); + } else { +#endif + return xTaskCreate(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask); +#ifndef CONFIG_FREERTOS_UNICORE + } +#endif +} + +unsigned long ARDUINO_ISR_ATTR micros() { + return (unsigned long)(esp_timer_get_time()); +} + +unsigned long ARDUINO_ISR_ATTR millis() { + return (unsigned long)(esp_timer_get_time() / 1000ULL); +} + +void delay(uint32_t ms) { + vTaskDelay(ms / portTICK_PERIOD_MS); +} + +void ARDUINO_ISR_ATTR delayMicroseconds(uint32_t us) { + uint64_t m = (uint64_t)esp_timer_get_time(); + if (us) { + uint64_t e = (m + us); + if (m > e) { //overflow + while ((uint64_t)esp_timer_get_time() > e) { + NOP(); + } + } + while ((uint64_t)esp_timer_get_time() < e) { + NOP(); + } + } +} + +void initVariant() __attribute__((weak)); +void initVariant() {} + +void init() __attribute__((weak)); +void init() {} + +#ifdef CONFIG_APP_ROLLBACK_ENABLE +/** + * @brief Verify the OTA image after boot + * + * This weak hook is invoked when a newly-updated application image is in + * the `ESP_OTA_IMG_PENDING_VERIFY` state. The default implementation + * returns `true`, indicating the image is considered valid. Applications + * may override this function (provide a non-weak implementation) to + * perform custom checks such as running a self-test, validating + * application-specific state, or performing connectivity / sensor checks + * before confirming the update. + * + * Usage: + * - Return `true` to mark the OTA image as valid; the system will call + * `esp_ota_mark_app_valid_cancel_rollback()` to cancel rollback. + * - Return `false` to indicate verification failure; the system will + * call `esp_ota_mark_app_invalid_rollback_and_reboot()` to rollback. + * + * @note Keep this function short and non-blocking if possible; blocking + * for long periods may delay boot. + * + * @return true if verification succeeds and the image should be kept + * @return false if verification fails and the image should be rolled back + */ +bool verifyOta() __attribute__((weak)); +bool verifyOta() { + return true; +} + +/** + * @brief Optionally defer OTA verification to later + * + * This weak hook allows an application to postpone the default OTA + * verification performed at startup. If this function returns `true`, the + * initialization code will skip immediate verification and the application + * can choose to verify the update at a later time (for example, after a + * lengthy hardware initialization or user interaction). The default weak + * implementation returns `false`, meaning verification will run during + * `initArduino()` when an image is pending verification. + * + * Usage: + * - Return `true` to delay verification and handle it manually later. + * - Return `false` to allow the built-in verification flow to run at + * startup. + * + * @return true to defer verification to a later time + * @return false to perform verification immediately during init + */ +bool verifyRollbackLater() __attribute__((weak)); +bool verifyRollbackLater() { + return false; +} +#endif + +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && SOC_BT_SUPPORTED && __has_include("esp_bt.h") +// declared here, defined in esp32-hal-bt.c (weak so users can override) +extern bool btInUse(void); +#endif + +#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM +ESP_SYSTEM_INIT_FN(init_psram_new, CORE, BIT(0), 99) { + psramInit(); + return ESP_OK; +} +#endif + +void initArduino() { + //init proper ref tick value for PLL (uncomment if REF_TICK is different than 1MHz) + //ESP_REG(APB_CTRL_PLL_TICK_CONF_REG) = APB_CLK_FREQ / REF_CLK_FREQ - 1; +#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM +#ifndef CONFIG_SPIRAM_BOOT_INIT + psramAddToHeap(); +#endif +#endif +#ifdef CONFIG_APP_ROLLBACK_ENABLE + if (!verifyRollbackLater()) { + const esp_partition_t *running = esp_ota_get_running_partition(); + esp_ota_img_states_t ota_state; + if (esp_ota_get_state_partition(running, &ota_state) == ESP_OK) { + if (ota_state == ESP_OTA_IMG_PENDING_VERIFY) { + if (verifyOta()) { + esp_ota_mark_app_valid_cancel_rollback(); + } else { + log_e("OTA verification failed! Start rollback to the previous version ..."); + esp_ota_mark_app_invalid_rollback_and_reboot(); + } + } + } + } +#endif + esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL); + esp_err_t err = nvs_flash_init(); + if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) { + const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, NULL); + if (partition != NULL) { + err = esp_partition_erase_range(partition, 0, partition->size); + if (!err) { + err = nvs_flash_init(); + } else { + log_e("Failed to format the broken NVS partition!"); + } + } else { + log_e("Could not find NVS partition"); + } + } + if (err) { + log_e("Failed to initialize NVS! Error: %u", err); + } +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && SOC_BT_SUPPORTED && __has_include("esp_bt.h") + if (!btInUse()) { + esp_bt_controller_mem_release(ESP_BT_MODE_BTDM); + } +#endif + init(); + initVariant(); +} + +//used by hal log +const char *ARDUINO_ISR_ATTR pathToFileName(const char *path) { + size_t i = 0; + size_t pos = 0; + char *p = (char *)path; + while (*p) { + i++; + if (*p == '/' || *p == '\\') { + pos = i; + } + p++; + } + return path + pos; +} + +#include "esp_rom_sys.h" +#include "esp_debug_helpers.h" +#if CONFIG_IDF_TARGET_ARCH_XTENSA +#include "esp_cpu_utils.h" +#else +#include "riscv/rvruntime-frames.h" +#endif +#include "esp_memory_utils.h" +#include "esp_private/panic_internal.h" + +static arduino_panic_handler_t _panic_handler = NULL; +static void *_panic_handler_arg = NULL; + +void set_arduino_panic_handler(arduino_panic_handler_t handler, void *arg) { + _panic_handler = handler; + _panic_handler_arg = arg; +} + +arduino_panic_handler_t get_arduino_panic_handler(void) { + return _panic_handler; +} + +void *get_arduino_panic_handler_arg(void) { + return _panic_handler_arg; +} + +static void handle_custom_backtrace(panic_info_t *info) { + arduino_panic_info_t p_info; + p_info.reason = info->reason; + p_info.core = info->core; + p_info.pc = info->addr; + p_info.backtrace_len = 0; + p_info.backtrace_corrupt = false; + p_info.backtrace_continues = false; + +#if CONFIG_IDF_TARGET_ARCH_XTENSA + XtExcFrame *xt_frame = (XtExcFrame *)info->frame; + esp_backtrace_frame_t stk_frame = {.pc = xt_frame->pc, .sp = xt_frame->a1, .next_pc = xt_frame->a0, .exc_frame = xt_frame}; + uint32_t i = 100, pc_ptr = esp_cpu_process_stack_pc(stk_frame.pc); + p_info.backtrace[p_info.backtrace_len++] = pc_ptr; + + bool corrupted = !(esp_stack_ptr_is_sane(stk_frame.sp) && (esp_ptr_executable((void *)esp_cpu_process_stack_pc(stk_frame.pc)) || + /* Ignore the first corrupted PC in case of InstrFetchProhibited */ + (stk_frame.exc_frame && ((XtExcFrame *)stk_frame.exc_frame)->exccause == EXCCAUSE_INSTR_PROHIBITED))); + + while (i-- > 0 && stk_frame.next_pc != 0 && !corrupted) { + if (!esp_backtrace_get_next_frame(&stk_frame)) { + corrupted = true; + } + pc_ptr = esp_cpu_process_stack_pc(stk_frame.pc); + if (esp_ptr_executable((void *)pc_ptr)) { + p_info.backtrace[p_info.backtrace_len++] = pc_ptr; + if (p_info.backtrace_len == 60) { + break; + } + } + } + + if (corrupted) { + p_info.backtrace_corrupt = true; + } else if (stk_frame.next_pc != 0) { + p_info.backtrace_continues = true; + } +#elif CONFIG_IDF_TARGET_ARCH_RISCV + uint32_t sp = (uint32_t)((RvExcFrame *)info->frame)->sp; + p_info.backtrace[p_info.backtrace_len++] = sp; + uint32_t *spptr = (uint32_t *)(sp); + for (int i = 0; i < 256; i++) { + if (esp_ptr_executable((void *)spptr[i])) { + p_info.backtrace[p_info.backtrace_len++] = spptr[i]; + if (p_info.backtrace_len == 60) { + if (i < 255) { + p_info.backtrace_continues = true; + } + break; + } + } + } +#endif + _panic_handler(&p_info, _panic_handler_arg); +} + +void __real_esp_panic_handler(panic_info_t *); +void __wrap_esp_panic_handler(panic_info_t *info) { + if (_panic_handler != NULL) { + handle_custom_backtrace(info); + } + __real_esp_panic_handler(info); +} diff --git a/cores/esp32/esp32-hal-periman.c b/cores/esp32/esp32-hal-periman.c new file mode 100644 index 0000000..bec88b0 --- /dev/null +++ b/cores/esp32/esp32-hal-periman.c @@ -0,0 +1,268 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32-hal-log.h" +#include "esp32-hal-periman.h" +#include "esp_bit_defs.h" + +typedef struct ATTR_PACKED { + peripheral_bus_type_t type; + const char *extra_type; + void *bus; + int8_t bus_num; + int8_t bus_channel; +} peripheral_pin_item_t; + +static peripheral_bus_deinit_cb_t deinit_functions[ESP32_BUS_TYPE_MAX] = {NULL}; +static peripheral_pin_item_t pins[SOC_GPIO_PIN_COUNT]; + +#define GPIO_NOT_VALID(p) ((p >= SOC_GPIO_PIN_COUNT) || ((SOC_GPIO_VALID_GPIO_MASK & (1ULL << p)) == 0)) + +const char *perimanGetTypeName(peripheral_bus_type_t type) { + switch (type) { + case ESP32_BUS_TYPE_INIT: return "INIT"; + case ESP32_BUS_TYPE_GPIO: return "GPIO"; + case ESP32_BUS_TYPE_UART_RX: return "UART_RX"; + case ESP32_BUS_TYPE_UART_TX: return "UART_TX"; + case ESP32_BUS_TYPE_UART_CTS: return "UART_CTS"; + case ESP32_BUS_TYPE_UART_RTS: return "UART_RTS"; +#if SOC_SDM_SUPPORTED + case ESP32_BUS_TYPE_SIGMADELTA: return "SIGMADELTA"; +#endif +#if SOC_ADC_SUPPORTED + case ESP32_BUS_TYPE_ADC_ONESHOT: return "ADC_ONESHOT"; + case ESP32_BUS_TYPE_ADC_CONT: return "ADC_CONT"; +#endif +#if SOC_DAC_SUPPORTED + case ESP32_BUS_TYPE_DAC_ONESHOT: return "DAC_ONESHOT"; + case ESP32_BUS_TYPE_DAC_CONT: return "DAC_CONT"; + case ESP32_BUS_TYPE_DAC_COSINE: return "DAC_COSINE"; +#endif +#if SOC_LEDC_SUPPORTED + case ESP32_BUS_TYPE_LEDC: return "LEDC"; +#endif +#if SOC_RMT_SUPPORTED + case ESP32_BUS_TYPE_RMT_TX: return "RMT_TX"; + case ESP32_BUS_TYPE_RMT_RX: return "RMT_RX"; +#endif +#if SOC_I2S_SUPPORTED + case ESP32_BUS_TYPE_I2S_STD_MCLK: return "I2S_STD_MCLK"; + case ESP32_BUS_TYPE_I2S_STD_BCLK: return "I2S_STD_BCLK"; + case ESP32_BUS_TYPE_I2S_STD_WS: return "I2S_STD_WS"; + case ESP32_BUS_TYPE_I2S_STD_DOUT: return "I2S_STD_DOUT"; + case ESP32_BUS_TYPE_I2S_STD_DIN: return "I2S_STD_DIN"; + case ESP32_BUS_TYPE_I2S_TDM_MCLK: return "I2S_TDM_MCLK"; + case ESP32_BUS_TYPE_I2S_TDM_BCLK: return "I2S_TDM_BCLK"; + case ESP32_BUS_TYPE_I2S_TDM_WS: return "I2S_TDM_WS"; + case ESP32_BUS_TYPE_I2S_TDM_DOUT: return "I2S_TDM_DOUT"; + case ESP32_BUS_TYPE_I2S_TDM_DIN: return "I2S_TDM_DIN"; + case ESP32_BUS_TYPE_I2S_PDM_TX_CLK: return "I2S_PDM_TX_CLK"; + case ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0: return "I2S_PDM_TX_DOUT0"; + case ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1: return "I2S_PDM_TX_DOUT1"; + case ESP32_BUS_TYPE_I2S_PDM_RX_CLK: return "I2S_PDM_RX_CLK"; + case ESP32_BUS_TYPE_I2S_PDM_RX_DIN0: return "I2S_PDM_RX_DIN0"; + case ESP32_BUS_TYPE_I2S_PDM_RX_DIN1: return "I2S_PDM_RX_DIN1"; + case ESP32_BUS_TYPE_I2S_PDM_RX_DIN2: return "I2S_PDM_RX_DIN2"; + case ESP32_BUS_TYPE_I2S_PDM_RX_DIN3: return "I2S_PDM_RX_DIN3"; +#endif +#if SOC_I2C_SUPPORTED + case ESP32_BUS_TYPE_I2C_MASTER_SDA: return "I2C_MASTER_SDA"; + case ESP32_BUS_TYPE_I2C_MASTER_SCL: return "I2C_MASTER_SCL"; + case ESP32_BUS_TYPE_I2C_SLAVE_SDA: return "I2C_SLAVE_SDA"; + case ESP32_BUS_TYPE_I2C_SLAVE_SCL: return "I2C_SLAVE_SCL"; +#endif +#if SOC_GPSPI_SUPPORTED + case ESP32_BUS_TYPE_SPI_MASTER_SCK: return "SPI_MASTER_SCK"; + case ESP32_BUS_TYPE_SPI_MASTER_MISO: return "SPI_MASTER_MISO"; + case ESP32_BUS_TYPE_SPI_MASTER_MOSI: return "SPI_MASTER_MOSI"; + case ESP32_BUS_TYPE_SPI_MASTER_SS: return "SPI_MASTER_SS"; +#endif +#if SOC_SDMMC_HOST_SUPPORTED + case ESP32_BUS_TYPE_SDMMC_CLK: return "SDMMC_CLK"; + case ESP32_BUS_TYPE_SDMMC_CMD: return "SDMMC_CMD"; + case ESP32_BUS_TYPE_SDMMC_D0: return "SDMMC_D0"; + case ESP32_BUS_TYPE_SDMMC_D1: return "SDMMC_D1"; + case ESP32_BUS_TYPE_SDMMC_D2: return "SDMMC_D2"; + case ESP32_BUS_TYPE_SDMMC_D3: return "SDMMC_D3"; +#endif +#if SOC_TOUCH_SENSOR_SUPPORTED + case ESP32_BUS_TYPE_TOUCH: return "TOUCH"; +#endif +#if SOC_USB_SERIAL_JTAG_SUPPORTED || SOC_USB_OTG_SUPPORTED + case ESP32_BUS_TYPE_USB_DM: return "USB_DM"; + case ESP32_BUS_TYPE_USB_DP: return "USB_DP"; +#endif +#if SOC_GPSPI_SUPPORTED + case ESP32_BUS_TYPE_ETHERNET_SPI: return "ETHERNET_SPI"; +#endif +#if CONFIG_ETH_USE_ESP32_EMAC + case ESP32_BUS_TYPE_ETHERNET_RMII: return "ETHERNET_RMII"; + case ESP32_BUS_TYPE_ETHERNET_CLK: return "ETHERNET_CLK"; + case ESP32_BUS_TYPE_ETHERNET_MCD: return "ETHERNET_MCD"; + case ESP32_BUS_TYPE_ETHERNET_MDIO: return "ETHERNET_MDIO"; + case ESP32_BUS_TYPE_ETHERNET_PWR: return "ETHERNET_PWR"; +#endif +#if CONFIG_LWIP_PPP_SUPPORT + case ESP32_BUS_TYPE_PPP_TX: return "PPP_MODEM_TX"; + case ESP32_BUS_TYPE_PPP_RX: return "PPP_MODEM_RX"; + case ESP32_BUS_TYPE_PPP_RTS: return "PPP_MODEM_RTS"; + case ESP32_BUS_TYPE_PPP_CTS: return "PPP_MODEM_CTS"; +#endif + default: return "UNKNOWN"; + } +} + +bool perimanSetPinBus(uint8_t pin, peripheral_bus_type_t type, void *bus, int8_t bus_num, int8_t bus_channel) { + peripheral_bus_type_t otype = ESP32_BUS_TYPE_INIT; + void *obus = NULL; + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return false; + } + if (type >= ESP32_BUS_TYPE_MAX) { + log_e("Invalid type: %s (%u) when setting pin %u", perimanGetTypeName(type), (unsigned int)type, pin); + return false; + } + if (type > ESP32_BUS_TYPE_GPIO && bus == NULL) { + log_e("Bus is NULL for pin %u with type %s (%u)", pin, perimanGetTypeName(type), (unsigned int)type); + return false; + } + if (type == ESP32_BUS_TYPE_INIT && bus != NULL) { + log_e("Can't set a Bus to INIT Type (pin %u)", pin); + return false; + } + otype = pins[pin].type; + obus = pins[pin].bus; + if (type == otype && bus == obus) { + if (type != ESP32_BUS_TYPE_INIT) { + log_i("Pin %u already has type %s (%u) with bus %p", pin, perimanGetTypeName(type), (unsigned int)type, bus); + } + return true; + } + if (obus != NULL) { + if (deinit_functions[otype] == NULL) { + log_e("No deinit function for type %s (%u) (pin %u)", perimanGetTypeName(otype), (unsigned int)otype, pin); + return false; + } + if (!deinit_functions[otype](obus)) { + log_e("Deinit function for previous bus type %s (%u) failed (pin %u)", perimanGetTypeName(otype), (unsigned int)otype, pin); + return false; + } + } + pins[pin].type = type; + pins[pin].bus = bus; + pins[pin].bus_num = bus_num; + pins[pin].bus_channel = bus_channel; + pins[pin].extra_type = NULL; + log_v("Pin %u successfully set to type %s (%u) with bus %p", pin, perimanGetTypeName(type), (unsigned int)type, bus); + return true; +} + +bool perimanSetPinBusExtraType(uint8_t pin, const char *extra_type) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return false; + } + if (pins[pin].type == ESP32_BUS_TYPE_INIT) { + log_e("Can't set extra type for Bus INIT Type (pin %u)", pin); + return false; + } + pins[pin].extra_type = extra_type; + log_v("Successfully set extra_type %s for pin %u", extra_type, pin); + return true; +} + +void *perimanGetPinBus(uint8_t pin, peripheral_bus_type_t type) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return NULL; + } + if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) { + log_e("Invalid type %s (%u) for pin %u", perimanGetTypeName(type), (unsigned int)type, pin); + return NULL; + } + if (pins[pin].type == type) { + return pins[pin].bus; + } + return NULL; +} + +peripheral_bus_type_t perimanGetPinBusType(uint8_t pin) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return ESP32_BUS_TYPE_MAX; + } + return pins[pin].type; +} + +const char *perimanGetPinBusExtraType(uint8_t pin) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return NULL; + } + return pins[pin].extra_type; +} + +int8_t perimanGetPinBusNum(uint8_t pin) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return -1; + } + return pins[pin].bus_num; +} + +int8_t perimanGetPinBusChannel(uint8_t pin) { + if (GPIO_NOT_VALID(pin)) { + log_e("Invalid pin: %u", pin); + return -1; + } + return pins[pin].bus_channel; +} + +bool perimanSetBusDeinit(peripheral_bus_type_t type, peripheral_bus_deinit_cb_t cb) { + if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) { + log_e("Invalid type: %s (%u)", perimanGetTypeName(type), (unsigned int)type); + return false; + } + if (cb == NULL) { + log_e("Callback is NULL when setting deinit function for type %s (%u)", perimanGetTypeName(type), (unsigned int)type); + return false; + } + deinit_functions[type] = cb; + log_v("Deinit function for type %s (%u) successfully set to %p", perimanGetTypeName(type), (unsigned int)type, cb); + return true; +} + +// This no-op callback is used by perimanClearBusDeinit() to effectively disable bus deinit functionality +// without setting the callback to NULL, which would cause errors in perimanSetPinBus() at line 146. +static bool empty_bus_deinit_cb(void *bus) { + return true; +} + +bool perimanClearBusDeinit(peripheral_bus_type_t type) { + if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) { + log_e("Invalid type: %s (%u)", perimanGetTypeName(type), (unsigned int)type); + return false; + } + deinit_functions[type] = empty_bus_deinit_cb; + log_v("Deinit function for type %s (%u) cleared", perimanGetTypeName(type), (unsigned int)type); + return true; +} + +peripheral_bus_deinit_cb_t perimanGetBusDeinit(peripheral_bus_type_t type) { + if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) { + log_e("Invalid type: %s (%u)", perimanGetTypeName(type), (unsigned int)type); + return NULL; + } + if (deinit_functions[type] == empty_bus_deinit_cb) { + return NULL; + } + return deinit_functions[type]; +} + +bool perimanPinIsValid(uint8_t pin) { + return !(GPIO_NOT_VALID(pin)); +} diff --git a/cores/esp32/esp32-hal-periman.h b/cores/esp32/esp32-hal-periman.h new file mode 100644 index 0000000..1256371 --- /dev/null +++ b/cores/esp32/esp32-hal-periman.h @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#include +#include +#include + +#define perimanClearPinBus(p) perimanSetPinBus(p, ESP32_BUS_TYPE_INIT, NULL, -1, -1) + +typedef enum { + ESP32_BUS_TYPE_INIT, // IO has not been attached to a bus yet + ESP32_BUS_TYPE_GPIO, // IO is used as GPIO + ESP32_BUS_TYPE_UART_RX, // IO is used as UART RX pin + ESP32_BUS_TYPE_UART_TX, // IO is used as UART TX pin + ESP32_BUS_TYPE_UART_CTS, // IO is used as UART CTS pin + ESP32_BUS_TYPE_UART_RTS, // IO is used as UART RTS pin +#if SOC_SDM_SUPPORTED + ESP32_BUS_TYPE_SIGMADELTA, // IO is used as SigmeDelta output +#endif +#if SOC_ADC_SUPPORTED + ESP32_BUS_TYPE_ADC_ONESHOT, // IO is used as ADC OneShot input + ESP32_BUS_TYPE_ADC_CONT, // IO is used as ADC continuous input +#endif +#if SOC_DAC_SUPPORTED + ESP32_BUS_TYPE_DAC_ONESHOT, // IO is used as DAC OneShot output + ESP32_BUS_TYPE_DAC_CONT, // IO is used as DAC continuous output + ESP32_BUS_TYPE_DAC_COSINE, // IO is used as DAC cosine output +#endif +#if SOC_LEDC_SUPPORTED + ESP32_BUS_TYPE_LEDC, // IO is used as LEDC output +#endif +#if SOC_RMT_SUPPORTED + ESP32_BUS_TYPE_RMT_TX, // IO is used as RMT output + ESP32_BUS_TYPE_RMT_RX, // IO is used as RMT input +#endif +#if SOC_I2S_SUPPORTED + ESP32_BUS_TYPE_I2S_STD_MCLK, // IO is used as I2S STD MCLK pin + ESP32_BUS_TYPE_I2S_STD_BCLK, // IO is used as I2S STD BCLK pin + ESP32_BUS_TYPE_I2S_STD_WS, // IO is used as I2S STD WS pin + ESP32_BUS_TYPE_I2S_STD_DOUT, // IO is used as I2S STD DOUT pin + ESP32_BUS_TYPE_I2S_STD_DIN, // IO is used as I2S STD DIN pin + + ESP32_BUS_TYPE_I2S_TDM_MCLK, // IO is used as I2S TDM MCLK pin + ESP32_BUS_TYPE_I2S_TDM_BCLK, // IO is used as I2S TDM BCLK pin + ESP32_BUS_TYPE_I2S_TDM_WS, // IO is used as I2S TDM WS pin + ESP32_BUS_TYPE_I2S_TDM_DOUT, // IO is used as I2S TDM DOUT pin + ESP32_BUS_TYPE_I2S_TDM_DIN, // IO is used as I2S TDM DIN pin + + ESP32_BUS_TYPE_I2S_PDM_TX_CLK, // IO is used as I2S PDM CLK pin + ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0, // IO is used as I2S PDM DOUT0 pin + ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1, // IO is used as I2S PDM DOUT1 pin + + ESP32_BUS_TYPE_I2S_PDM_RX_CLK, // IO is used as I2S PDM CLK pin + ESP32_BUS_TYPE_I2S_PDM_RX_DIN0, // IO is used as I2S PDM DIN0 pin + ESP32_BUS_TYPE_I2S_PDM_RX_DIN1, // IO is used as I2S PDM DIN1 pin + ESP32_BUS_TYPE_I2S_PDM_RX_DIN2, // IO is used as I2S PDM DIN2 pin + ESP32_BUS_TYPE_I2S_PDM_RX_DIN3, // IO is used as I2S PDM DIN3 pin +#endif +#if SOC_I2C_SUPPORTED + ESP32_BUS_TYPE_I2C_MASTER_SDA, // IO is used as I2C master SDA pin + ESP32_BUS_TYPE_I2C_MASTER_SCL, // IO is used as I2C master SCL pin + ESP32_BUS_TYPE_I2C_SLAVE_SDA, // IO is used as I2C slave SDA pin + ESP32_BUS_TYPE_I2C_SLAVE_SCL, // IO is used as I2C slave SCL pin +#endif +#if SOC_GPSPI_SUPPORTED + ESP32_BUS_TYPE_SPI_MASTER_SCK, // IO is used as SPI master SCK pin + ESP32_BUS_TYPE_SPI_MASTER_MISO, // IO is used as SPI master MISO pin + ESP32_BUS_TYPE_SPI_MASTER_MOSI, // IO is used as SPI master MOSI pin + ESP32_BUS_TYPE_SPI_MASTER_SS, // IO is used as SPI master SS pin +#endif +#if SOC_SDMMC_HOST_SUPPORTED + ESP32_BUS_TYPE_SDMMC_CLK, // IO is used as SDMMC CLK pin + ESP32_BUS_TYPE_SDMMC_CMD, // IO is used as SDMMC CMD pin + ESP32_BUS_TYPE_SDMMC_D0, // IO is used as SDMMC D0 pin + ESP32_BUS_TYPE_SDMMC_D1, // IO is used as SDMMC D1 pin + ESP32_BUS_TYPE_SDMMC_D2, // IO is used as SDMMC D2 pin + ESP32_BUS_TYPE_SDMMC_D3, // IO is used as SDMMC D3 pin +#endif +#if SOC_TOUCH_SENSOR_SUPPORTED + ESP32_BUS_TYPE_TOUCH, // IO is used as TOUCH pin +#endif +#if SOC_USB_SERIAL_JTAG_SUPPORTED || SOC_USB_OTG_SUPPORTED + ESP32_BUS_TYPE_USB_DM, // IO is used as USB DM (+) pin + ESP32_BUS_TYPE_USB_DP, // IO is used as USB DP (-) pin +#endif +#if SOC_GPSPI_SUPPORTED + ESP32_BUS_TYPE_ETHERNET_SPI, // IO is used as ETHERNET SPI pin +#endif +#if CONFIG_ETH_USE_ESP32_EMAC + ESP32_BUS_TYPE_ETHERNET_RMII, // IO is used as ETHERNET RMII pin + ESP32_BUS_TYPE_ETHERNET_CLK, // IO is used as ETHERNET CLK pin + ESP32_BUS_TYPE_ETHERNET_MCD, // IO is used as ETHERNET MCD pin + ESP32_BUS_TYPE_ETHERNET_MDIO, // IO is used as ETHERNET MDIO pin + ESP32_BUS_TYPE_ETHERNET_PWR, // IO is used as ETHERNET PWR pin +#endif +#if CONFIG_LWIP_PPP_SUPPORT + ESP32_BUS_TYPE_PPP_TX, // IO is used as PPP Modem TX pin + ESP32_BUS_TYPE_PPP_RX, // IO is used as PPP Modem RX pin + ESP32_BUS_TYPE_PPP_RTS, // IO is used as PPP Modem RTS pin + ESP32_BUS_TYPE_PPP_CTS, // IO is used as PPP Modem CTS pin +#endif + ESP32_BUS_TYPE_MAX +} peripheral_bus_type_t; + +typedef bool (*peripheral_bus_deinit_cb_t)(void *bus); + +const char *perimanGetTypeName(peripheral_bus_type_t type); + +// Sets the bus type, bus handle, bus number and bus channel for given pin. +bool perimanSetPinBus(uint8_t pin, peripheral_bus_type_t type, void *bus, int8_t bus_num, int8_t bus_channel); + +// Returns handle of the bus for the given pin if type of bus matches. NULL otherwise +void *perimanGetPinBus(uint8_t pin, peripheral_bus_type_t type); + +// Returns the type of the bus for the given pin if attached. ESP32_BUS_TYPE_MAX otherwise +peripheral_bus_type_t perimanGetPinBusType(uint8_t pin); + +// Returns the bus number or unit of the bus for the given pin if set. -1 otherwise +int8_t perimanGetPinBusNum(uint8_t pin); + +// Returns the bus channel of the bus for the given pin if set. -1 otherwise +int8_t perimanGetPinBusChannel(uint8_t pin); + +// Sets the peripheral destructor callback. Used to destroy bus when pin is assigned another function +bool perimanSetBusDeinit(peripheral_bus_type_t type, peripheral_bus_deinit_cb_t cb); + +// Clears the peripheral destructor callback +bool perimanClearBusDeinit(peripheral_bus_type_t type); + +// Get the peripheral destructor callback. It allows changing/restoring the peripheral pin function detaching, if necessary +// returns NULL if none is set +peripheral_bus_deinit_cb_t perimanGetBusDeinit(peripheral_bus_type_t type); + +// Check if given pin is a valid GPIO number +bool perimanPinIsValid(uint8_t pin); + +// Sets the extra type for non Init bus. Used to customize pin bus name which can be printed by printPerimanInfo(). +bool perimanSetPinBusExtraType(uint8_t pin, const char *extra_type); + +// Returns the extra type of the bus for given pin if set. NULL otherwise +const char *perimanGetPinBusExtraType(uint8_t pin); + +#ifdef __cplusplus +} +#endif diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c new file mode 100644 index 0000000..9b985e8 --- /dev/null +++ b/cores/esp32/esp32-hal-psram.c @@ -0,0 +1,157 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal.h" + +#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM +#include "soc/efuse_reg.h" +#include "esp_heap_caps.h" + +#include "esp_system.h" +#include "esp_psram.h" +#include "esp_private/esp_psram_extram.h" +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "esp32/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/cache.h" +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif + +#define TAG "arduino-psram" + +static volatile bool spiramDetected = false; +static volatile bool spiramFailed = false; + +//allows user to bypass SPI RAM test routine +__attribute__((weak)) bool testSPIRAM(void) { + return esp_psram_extram_test(); +} + +bool psramInit() { + if (spiramDetected) { + return true; + } +#ifndef CONFIG_SPIRAM_BOOT_INIT + if (spiramFailed) { + return false; + } +#if CONFIG_IDF_TARGET_ESP32 + uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE); + uint32_t pkg_ver = chip_ver & 0x7; + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { + spiramFailed = true; + ESP_EARLY_LOGW(TAG, "PSRAM not supported!"); + return false; + } +#elif CONFIG_IDF_TARGET_ESP32S2 + extern void esp_config_data_cache_mode(void); + esp_config_data_cache_mode(); + Cache_Enable_DCache(0); +#endif + if (esp_psram_init() != ESP_OK) { + spiramFailed = true; + ESP_EARLY_LOGW(TAG, "PSRAM init failed!"); +#if CONFIG_IDF_TARGET_ESP32 + if (pkg_ver != EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { + pinMatrixOutDetach(16, false, false); + pinMatrixOutDetach(17, false, false); + } +#endif + return false; + } + //testSPIRAM() allows user to bypass SPI RAM test routine + if (!testSPIRAM()) { + spiramFailed = true; + ESP_EARLY_LOGE(TAG, "PSRAM test failed!"); + return false; + } + //ESP_EARLY_LOGI(TAG, "PSRAM enabled"); +#endif /* CONFIG_SPIRAM_BOOT_INIT */ + spiramDetected = true; + return true; +} + +bool psramAddToHeap() { + if (!spiramDetected) { + log_e("PSRAM not initialized!"); + return false; + } + if (esp_psram_extram_add_to_heap_allocator() != ESP_OK) { + log_e("PSRAM could not be added to the heap!"); + return false; + } +#if CONFIG_SPIRAM_USE_MALLOC && !CONFIG_ARDUINO_ISR_IRAM + heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL); +#endif + log_i("PSRAM added to the heap."); + return true; +} + +bool ARDUINO_ISR_ATTR psramFound() { + return spiramDetected; +} + +void ARDUINO_ISR_ATTR *ps_malloc(size_t size) { + if (!spiramDetected) { + return NULL; + } + return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); +} + +void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) { + if (!spiramDetected) { + return NULL; + } + return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); +} + +void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) { + if (!spiramDetected) { + return NULL; + } + return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); +} + +#else + +bool psramInit() { + return false; +} + +bool ARDUINO_ISR_ATTR psramFound() { + return false; +} + +void ARDUINO_ISR_ATTR *ps_malloc(size_t size) { + return NULL; +} + +void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) { + return NULL; +} + +void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) { + return NULL; +} + +#endif diff --git a/cores/esp32/esp32-hal-psram.h b/cores/esp32/esp32-hal-psram.h new file mode 100644 index 0000000..69c1c62 --- /dev/null +++ b/cores/esp32/esp32-hal-psram.h @@ -0,0 +1,46 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP32_HAL_PSRAM_H_ +#define _ESP32_HAL_PSRAM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdkconfig.h" + +// Clear flags in Arduino IDE when PSRAM is disabled +#if defined(ESP32_ARDUINO_LIB_BUILDER) && !defined(BOARD_HAS_PSRAM) +#ifdef CONFIG_SPIRAM_SUPPORT +#undef CONFIG_SPIRAM_SUPPORT +#endif +#ifdef CONFIG_SPIRAM +#undef CONFIG_SPIRAM +#endif +#endif + +bool psramInit(); +bool psramAddToHeap(); +bool psramFound(); + +void *ps_malloc(size_t size); +void *ps_calloc(size_t n, size_t size); +void *ps_realloc(void *ptr, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* _ESP32_HAL_PSRAM_H_ */ diff --git a/cores/esp32/esp32-hal-rgb-led.c b/cores/esp32/esp32-hal-rgb-led.c new file mode 100644 index 0000000..d47dde5 --- /dev/null +++ b/cores/esp32/esp32-hal-rgb-led.c @@ -0,0 +1,98 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc_caps.h" + +#include "esp32-hal-rgb-led.h" + +// Backward compatibility - Deprecated. It will be removed in future releases. +void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val) { + log_w("neopixelWrite() is deprecated. Use rgbLedWrite()."); + rgbLedWrite(pin, red_val, green_val, blue_val); +} + +void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val) { + rgbLedWriteOrdered(pin, RGB_BUILTIN_LED_COLOR_ORDER, red_val, green_val, blue_val); +} + +void rgbLedWriteOrdered(uint8_t pin, rgb_led_color_order_t order, uint8_t red_val, uint8_t green_val, uint8_t blue_val) { +#if SOC_RMT_SUPPORTED + rmt_data_t led_data[24]; + + // Verify if the pin used is RGB_BUILTIN and fix GPIO number +#ifdef RGB_BUILTIN + pin = pin == RGB_BUILTIN ? pin - SOC_GPIO_PIN_COUNT : pin; +#endif + if (!rmtInit(pin, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000)) { + log_e("RGB LED driver initialization failed for GPIO%d!", pin); + return; + } + + // default WS2812B color order is G, R, B + int color[3] = {green_val, red_val, blue_val}; + + switch (order) { + case LED_COLOR_ORDER_RGB: + color[0] = red_val; + color[1] = green_val; + color[2] = blue_val; + break; + case LED_COLOR_ORDER_BGR: + color[0] = blue_val; + color[1] = green_val; + color[2] = red_val; + break; + case LED_COLOR_ORDER_BRG: + color[0] = blue_val; + color[1] = red_val; + color[2] = green_val; + break; + case LED_COLOR_ORDER_RBG: + color[0] = red_val; + color[1] = blue_val; + color[2] = green_val; + break; + case LED_COLOR_ORDER_GBR: + color[0] = green_val; + color[1] = blue_val; + color[2] = red_val; + break; + default: // GRB + break; + } + + int i = 0; + for (int col = 0; col < 3; col++) { + for (int bit = 0; bit < 8; bit++) { + if ((color[col] & (1 << (7 - bit)))) { + // HIGH bit + led_data[i].level0 = 1; // T1H + led_data[i].duration0 = 8; // 0.8us + led_data[i].level1 = 0; // T1L + led_data[i].duration1 = 4; // 0.4us + } else { + // LOW bit + led_data[i].level0 = 1; // T0H + led_data[i].duration0 = 4; // 0.4us + led_data[i].level1 = 0; // T0L + led_data[i].duration1 = 8; // 0.8us + } + i++; + } + } + rmtWrite(pin, led_data, RMT_SYMBOLS_OF(led_data), RMT_WAIT_FOR_EVER); +#else + log_e("RMT is not supported on " CONFIG_IDF_TARGET); +#endif /* SOC_RMT_SUPPORTED */ +} diff --git a/cores/esp32/esp32-hal-rgb-led.h b/cores/esp32/esp32-hal-rgb-led.h new file mode 100644 index 0000000..b151732 --- /dev/null +++ b/cores/esp32/esp32-hal-rgb-led.h @@ -0,0 +1,40 @@ +#ifndef MAIN_ESP32_HAL_RGB_LED_H_ +#define MAIN_ESP32_HAL_RGB_LED_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" + +#ifndef RGB_BRIGHTNESS +#define RGB_BRIGHTNESS 64 +#endif + +#ifndef RGB_BUILTIN_LED_COLOR_ORDER +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_GRB // default WS2812B color order +#endif + +typedef enum { + LED_COLOR_ORDER_RGB, + LED_COLOR_ORDER_BGR, + LED_COLOR_ORDER_BRG, + LED_COLOR_ORDER_RBG, + LED_COLOR_ORDER_GBR, + LED_COLOR_ORDER_GRB +} rgb_led_color_order_t; + +void rgbLedWriteOrdered(uint8_t pin, rgb_led_color_order_t order, uint8_t red_val, uint8_t green_val, uint8_t blue_val); + +// Will use RGB_BUILTIN_LED_COLOR_ORDER +void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val); + +// Backward compatibility - Deprecated. It will be removed in future releases. +[[deprecated("Use rgbLedWrite() instead.")]] +void neopixelWrite(uint8_t p, uint8_t r, uint8_t g, uint8_t b); + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_ESP32_HAL_RGB_LED_H_ */ diff --git a/cores/esp32/esp32-hal-rmt.c b/cores/esp32/esp32-hal-rmt.c new file mode 100644 index 0000000..9a16c06 --- /dev/null +++ b/cores/esp32/esp32-hal-rmt.c @@ -0,0 +1,675 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/soc_caps.h" + +#if SOC_RMT_SUPPORTED +#include "esp32-hal.h" +#include "driver/gpio.h" +#include "driver/rmt_tx.h" +#include "driver/rmt_rx.h" +#include "hal/rmt_ll.h" + +#include "esp32-hal-rmt.h" +#include "esp32-hal-periman.h" +#include "esp_idf_version.h" + +// Arduino Task Handle indicates if the Arduino Task has been started already +extern TaskHandle_t loopTaskHandle; + +// RMT Events +#define RMT_FLAG_RX_DONE (1) +#define RMT_FLAG_TX_DONE (2) + +/** + Internal macros +*/ + +#if CONFIG_DISABLE_HAL_LOCKS +#define RMT_MUTEX_LOCK(busptr) +#define RMT_MUTEX_UNLOCK(busptr) +#else +#define RMT_MUTEX_LOCK(busptr) \ + do { \ + } while (xSemaphoreTake(busptr->g_rmt_objlocks, portMAX_DELAY) != pdPASS) +#define RMT_MUTEX_UNLOCK(busptr) xSemaphoreGive(busptr->g_rmt_objlocks) +#endif /* CONFIG_DISABLE_HAL_LOCKS */ + +/** + Typedefs for internal structures, enums +*/ + +struct rmt_obj_s { + // general RMT information + rmt_channel_handle_t rmt_channel_h; // IDF RMT channel handler + rmt_encoder_handle_t rmt_copy_encoder_h; // RMT simple copy encoder handle + + uint32_t signal_range_min_ns; // RX Filter data - Low Pass pulse width + uint32_t signal_range_max_ns; // RX idle time that defines end of reading + + EventGroupHandle_t rmt_events; // read/write done event RMT callback handle + bool rmt_ch_is_looping; // Is this RMT TX Channel in LOOPING MODE? + size_t *num_symbols_read; // Pointer to the number of RMT symbol read by IDF RMT RX Done + rmt_reserve_memsize_t mem_size; // RMT Memory size + uint32_t frequency_Hz; // RMT Frequency + uint8_t rmt_EOT_Level; // RMT End of Transmission Level - default is LOW + +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t g_rmt_objlocks; // Channel Semaphore Lock +#endif /* CONFIG_DISABLE_HAL_LOCKS */ +}; + +typedef struct rmt_obj_s *rmt_bus_handle_t; + +/** + Internal variables used in RMT API +*/ +static SemaphoreHandle_t g_rmt_block_lock = NULL; + +/** + Internal method (private) declarations +*/ + +// This is called from an IDF ISR code, therefore this code is part of an ISR +static bool _rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *data, void *args) { + BaseType_t high_task_wakeup = pdFALSE; + rmt_bus_handle_t bus = (rmt_bus_handle_t)args; + // sets the returning number of RMT symbols (32 bits) effectively read + *bus->num_symbols_read = data->num_symbols; + // set RX event group and signal the received RMT symbols of that channel + xEventGroupSetBitsFromISR(bus->rmt_events, RMT_FLAG_RX_DONE, &high_task_wakeup); + // A "need to yield" is returned in order to execute portYIELD_FROM_ISR() in the main IDF RX ISR + return high_task_wakeup == pdTRUE; +} + +// This is called from an IDF ISR code, therefore this code is part of an ISR +static bool _rmt_tx_done_callback(rmt_channel_handle_t channel, const rmt_tx_done_event_data_t *data, void *args) { + BaseType_t high_task_wakeup = pdFALSE; + rmt_bus_handle_t bus = (rmt_bus_handle_t)args; + // set RX event group and signal the received RMT symbols of that channel + xEventGroupSetBitsFromISR(bus->rmt_events, RMT_FLAG_TX_DONE, &high_task_wakeup); + // A "need to yield" is returned in order to execute portYIELD_FROM_ISR() in the main IDF RX ISR + return high_task_wakeup == pdTRUE; +} + +// This function must be called only after checking the pin and its bus with _rmtGetBus() +static bool _rmtCheckDirection(uint8_t gpio_num, rmt_ch_dir_t rmt_dir, const char *labelFunc) { + // gets bus RMT direction from the Peripheral Manager information + rmt_ch_dir_t bus_rmt_dir = perimanGetPinBusType(gpio_num) == ESP32_BUS_TYPE_RMT_TX ? RMT_TX_MODE : RMT_RX_MODE; + + if (bus_rmt_dir == rmt_dir) { // matches expected RX/TX channel + return true; + } + + // print error message + if (rmt_dir == RMT_RX_MODE) { + log_w("==>%s():Channel set as TX instead of RX.", labelFunc); + } else { + log_w("==>%s():Channel set as RX instead of TX.", labelFunc); + } + return false; // mismatched +} + +static rmt_bus_handle_t _rmtGetBus(int pin, const char *labelFunc) { + // Is pin RX or TX? Let's find it out + peripheral_bus_type_t rmt_bus_type = perimanGetPinBusType(pin); + if (rmt_bus_type != ESP32_BUS_TYPE_RMT_TX && rmt_bus_type != ESP32_BUS_TYPE_RMT_RX) { + log_e("==>%s():GPIO %u is not attached to an RMT channel.", labelFunc, pin); + return NULL; + } + + return (rmt_bus_handle_t)perimanGetPinBus(pin, rmt_bus_type); +} + +// Peripheral Manager detach callback +static bool _rmtDetachBus(void *busptr) { + // sanity check - it should never happen + assert(busptr && "_rmtDetachBus bus NULL pointer."); + + bool retCode = true; + rmt_bus_handle_t bus = (rmt_bus_handle_t)busptr; + log_v("Detaching RMT GPIO Bus"); + + // lock it + while (xSemaphoreTake(g_rmt_block_lock, portMAX_DELAY) != pdPASS) {} + + // free Event Group + if (bus->rmt_events != NULL) { + vEventGroupDelete(bus->rmt_events); + bus->rmt_events = NULL; + } + // deallocate the channel encoder + if (bus->rmt_copy_encoder_h != NULL) { + if (ESP_OK != rmt_del_encoder(bus->rmt_copy_encoder_h)) { + log_w("RMT Encoder Deletion has failed."); + retCode = false; + } + } + // disable and deallocate RMT channel + if (bus->rmt_channel_h != NULL) { + // force stopping rmt TX/RX processing and unlock Power Management (APB Freq) + rmt_disable(bus->rmt_channel_h); + if (ESP_OK != rmt_del_channel(bus->rmt_channel_h)) { + log_w("RMT Channel Deletion has failed."); + retCode = false; + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + // deallocate channel semaphore + if (bus->g_rmt_objlocks != NULL) { + vSemaphoreDelete(bus->g_rmt_objlocks); + } +#endif + // free the allocated bus data structure + free(bus); + + // release the mutex + xSemaphoreGive(g_rmt_block_lock); + return retCode; +} + +/** + Public method definitions +*/ + +bool rmtSetEOT(int pin, uint8_t EOT_Level) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) { + return false; + } + + bus->rmt_EOT_Level = EOT_Level > 0 ? 1 : 0; + return true; +} + +bool rmtSetCarrier(int pin, bool carrier_en, bool carrier_level, uint32_t frequency_Hz, float duty_percent) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + + if (duty_percent > 1) { + log_w("GPIO %d - RMT Carrier must be a float percentage from 0 to 1. Setting to 50%.", pin); + duty_percent = 0.5; + } + rmt_carrier_config_t carrier_cfg; + memset((void *)&carrier_cfg, 0, sizeof(rmt_carrier_config_t)); + carrier_cfg.duty_cycle = duty_percent; // duty cycle + carrier_cfg.frequency_hz = carrier_en ? frequency_Hz : 0; // carrier frequency in Hz + carrier_cfg.flags.polarity_active_low = carrier_level; // carrier modulation polarity level + + bool retCode = true; + RMT_MUTEX_LOCK(bus); + // modulate carrier to TX channel + if (ESP_OK != rmt_apply_carrier(bus->rmt_channel_h, &carrier_cfg)) { + log_w("GPIO %d - Error applying RMT carrier.", pin); + retCode = false; + } + RMT_MUTEX_UNLOCK(bus); + + return retCode; +} + +bool rmtSetRxMinThreshold(int pin, uint8_t filter_pulse_ticks) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + + if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) { + return false; + } + + uint32_t filter_pulse_ns = (1000000000 / bus->frequency_Hz) * filter_pulse_ticks; + // RMT_LL_MAX_FILTER_VALUE is 255 for ESP32, S2, S3, C3, C6 and H2; + // filter_pulse_ticks is 8 bits, thus it will not exceed 255 +#if 0 // for the future, in case some other SoC has different limit + if (filter_pulse_ticks > RMT_LL_MAX_FILTER_VALUE) { + log_e("filter_pulse_ticks is too big. Max = %d", RMT_LL_MAX_FILTER_VALUE); + return false; + } +#endif + + RMT_MUTEX_LOCK(bus); + bus->signal_range_min_ns = filter_pulse_ns; // set zero to disable it + RMT_MUTEX_UNLOCK(bus); + return true; +} + +bool rmtSetRxMaxThreshold(int pin, uint16_t idle_thres_ticks) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + + if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) { + return false; + } + + uint32_t idle_thres_ns = (1000000000 / bus->frequency_Hz) * idle_thres_ticks; + // RMT_LL_MAX_IDLE_VALUE is 65535 for ESP32,S2 and 32767 for S3, C3, C6 and H2 +#if RMT_LL_MAX_IDLE_VALUE < 65535 // idle_thres_ticks is 16 bits anyway - save some bytes + if (idle_thres_ticks > RMT_LL_MAX_IDLE_VALUE) { + log_e("idle_thres_ticks is too big. Max = %ld", RMT_LL_MAX_IDLE_VALUE); + return false; + } +#endif + + RMT_MUTEX_LOCK(bus); + bus->signal_range_max_ns = idle_thres_ns; + RMT_MUTEX_UNLOCK(bus); + return true; +} + +bool rmtDeinit(int pin) { + log_v("Deiniting RMT GPIO %d", pin); + if (_rmtGetBus(pin, __FUNCTION__) != NULL) { + // release all allocated data + return perimanClearPinBus(pin); + } + log_e("GPIO %d - No RMT channel associated.", pin); + return false; +} + +static bool _rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, bool blocking, uint32_t loop, uint32_t timeout_ms) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) { + return false; + } + bool loopCancel = false; // user wants to cancel the writing loop mode + if (data == NULL || num_rmt_symbols == 0) { + if (!loop) { + log_w("GPIO %d - RMT Write Data NULL pointer or size is zero.", pin); + return false; + } else { + loopCancel = true; + } + } + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + log_v("GPIO: %d - Request: %d RMT Symbols - %s - Timeout: %d", pin, num_rmt_symbols, blocking ? "Blocking" : "Non-Blocking", timeout_ms); + // loop parameter semantics: + // loop == 0: no looping (single transmission) + // loop == 1: infinite looping + // loop > 1: transmit the data 'loop' times + { + char buf[17]; // placeholder for up to maximum uint32_t value (4294967295) = 10 digits + " times" (6 chars) + null terminator (17 bytes) + snprintf(buf, sizeof(buf), "%lu times", loop); + log_v( + "GPIO: %d - Currently in Loop Mode: [%s] | Loop Request: [%s], LoopCancel: [%s]", pin, bus->rmt_ch_is_looping ? "YES" : "NO", + loop == 0 ? "NO" : (loop == 1 ? "FOREVER" : buf), loopCancel ? "YES" : "NO" + ); + } +#endif + + if ((xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_TX_DONE) == 0) { + log_v("GPIO %d - RMT Write still pending to be completed.", pin); + return false; + } + + rmt_transmit_config_t transmit_cfg; // loop mode disabled + memset((void *)&transmit_cfg, 0, sizeof(rmt_transmit_config_t)); + bool retCode = true; + + RMT_MUTEX_LOCK(bus); + // wants to start in writing or looping over a previous looping --> resets the channel + if (bus->rmt_ch_is_looping == true) { + // must force stopping a previous loop transmission first + rmt_disable(bus->rmt_channel_h); + // enable it again for looping or writing + rmt_enable(bus->rmt_channel_h); + bus->rmt_ch_is_looping = false; // not looping anymore + } + // sets the End of Transmission level to HIGH if the user has requested so + if (bus->rmt_EOT_Level) { + transmit_cfg.flags.eot_level = 1; // EOT is HIGH + } + if (loopCancel) { + // just resets and releases the channel, maybe, already done above, then exits + bus->rmt_ch_is_looping = false; + } else { // new writing | looping request + // looping | Writing over a previous looping state is valid + if (loop > 0) { + transmit_cfg.loop_count = (loop == 1) ? -1 : loop; + // keeps RMT_FLAG_TX_DONE set - it never changes + } else { + // looping mode never sets this flag (IDF 5.1) in the callback + xEventGroupClearBits(bus->rmt_events, RMT_FLAG_TX_DONE); + } + // transmits just once or looping data + if (ESP_OK != rmt_transmit(bus->rmt_channel_h, bus->rmt_copy_encoder_h, (const void *)data, num_rmt_symbols * sizeof(rmt_data_t), &transmit_cfg)) { + retCode = false; + log_w("GPIO %d - RMT Transmission failed.", pin); + } else { // transmit OK + if (loop > 0) { + // rmt_ch_is_looping is used as a flag to indicate that RMT is in looping execution in order to + // be canceled whenever a new _rmtWrite() is executed while it is looping + bus->rmt_ch_is_looping = true; + } else { + if (blocking) { + // wait for transmission confirmation | timeout + retCode = (xEventGroupWaitBits(bus->rmt_events, RMT_FLAG_TX_DONE, pdFALSE /* do not clear on exit */, pdFALSE /* wait for all bits */, timeout_ms) + & RMT_FLAG_TX_DONE) + != 0; + } + } + } + } + RMT_MUTEX_UNLOCK(bus); + return retCode; +} + +static bool _rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, bool waitForData, uint32_t timeout_ms) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) { + return false; + } + if (data == NULL || num_rmt_symbols == NULL) { + log_w("GPIO %d - RMT Read Data and/or Size NULL pointer.", pin); + return false; + } + log_v("GPIO: %d - Request: %d RMT Symbols - %s - Timeout: %d", pin, *num_rmt_symbols, waitForData ? "Blocking" : "Non-Blocking", timeout_ms); + bool retCode = true; + RMT_MUTEX_LOCK(bus); + + // request reading RMT Channel Data + rmt_receive_config_t receive_config; + memset((void *)&receive_config, 0, sizeof(rmt_receive_config_t)); + receive_config.signal_range_min_ns = bus->signal_range_min_ns; + receive_config.signal_range_max_ns = bus->signal_range_max_ns; + + xEventGroupClearBits(bus->rmt_events, RMT_FLAG_RX_DONE); + bus->num_symbols_read = num_rmt_symbols; + + if (waitForData) { + // resets the reading channel to start fresh + rmt_disable(bus->rmt_channel_h); + rmt_enable(bus->rmt_channel_h); + } + + rmt_receive(bus->rmt_channel_h, data, *num_rmt_symbols * sizeof(rmt_data_t), &receive_config); + // wait for data if requested + if (waitForData) { + retCode = (xEventGroupWaitBits(bus->rmt_events, RMT_FLAG_RX_DONE, pdFALSE /* do not clear on exit */, pdFALSE /* wait for all bits */, timeout_ms) + & RMT_FLAG_RX_DONE) + != 0; + } + + RMT_MUTEX_UNLOCK(bus); + return retCode; +} + +bool rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t timeout_ms) { + return _rmtWrite(pin, data, num_rmt_symbols, true /*blocks*/, 0 /*looping*/, timeout_ms); +} + +bool rmtWriteAsync(int pin, rmt_data_t *data, size_t num_rmt_symbols) { + return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, 0 /*looping*/, 0 /*N/A*/); +} + +bool rmtWriteLooping(int pin, rmt_data_t *data, size_t num_rmt_symbols) { + return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, 1 /*looping*/, 0 /*N/A*/); +} + +// Same as rmtWriteLooping(...) but it transmits the data a fixed number of times ("loop_count"). +// loop_count == 0 is invalid (no transmission); loop_count == 1 transmits once (no looping); loop_count > 1 transmits the data repeatedly (looping). +bool rmtWriteRepeated(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t loop_count) { + if (loop_count == 0) { + log_e("RMT TX GPIO %d : Invalid loop_count (%u). Must be at least 1.", pin, loop_count); + return false; + } + if (loop_count == 1) { + // send the RMT symbols once using non-blocking write (single non-looping transmission) + return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, 0 /*looping*/, 0 /*N/A*/); + } else { + // write the RMT symbols for loop_count times +#if SOC_RMT_SUPPORT_TX_LOOP_COUNT + return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, loop_count /*looping*/, 0 /*N/A*/); +#else + log_e("RMT TX GPIO %d : Loop Count is not supported. Writing failed.", pin); + return false; +#endif + } +} + +bool rmtTransmitCompleted(int pin) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) { + return false; + } + + bool retCode = true; + RMT_MUTEX_LOCK(bus); + retCode = (xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_TX_DONE) != 0; + RMT_MUTEX_UNLOCK(bus); + return retCode; +} + +bool rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, uint32_t timeout_ms) { + return _rmtRead(pin, data, num_rmt_symbols, true /* blocking */, timeout_ms); +} + +bool rmtReadAsync(int pin, rmt_data_t *data, size_t *num_rmt_symbols) { + return _rmtRead(pin, data, num_rmt_symbols, false /* non-blocking */, 0 /* N/A */); +} + +bool rmtReceiveCompleted(int pin) { + rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__); + if (bus == NULL) { + return false; + } + if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) { + return false; + } + + bool retCode = true; + RMT_MUTEX_LOCK(bus); + retCode = (xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_RX_DONE) != 0; + RMT_MUTEX_UNLOCK(bus); + return retCode; +} + +bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t mem_size, uint32_t frequency_Hz) { + log_v( + "GPIO %d - %s - MemSize[%d] - Freq=%dHz", pin, channel_direction == RMT_RX_MODE ? "RX MODE" : "TX MODE", mem_size * RMT_SYMBOLS_PER_CHANNEL_BLOCK, + frequency_Hz + ); + + // create common block mutex for protecting allocs from multiple threads allocating RMT channels + if (!g_rmt_block_lock) { + g_rmt_block_lock = xSemaphoreCreateMutex(); + if (g_rmt_block_lock == NULL) { + log_e("GPIO %d - Failed creating RMT Mutex.", pin); + return false; + } + } + + // check if the RMT peripheral is already initialized with the same parameters + rmt_bus_handle_t bus = NULL; + peripheral_bus_type_t rmt_bus_type = perimanGetPinBusType(pin); + if (rmt_bus_type == ESP32_BUS_TYPE_RMT_TX || rmt_bus_type == ESP32_BUS_TYPE_RMT_RX) { + rmt_ch_dir_t bus_rmt_dir = rmt_bus_type == ESP32_BUS_TYPE_RMT_TX ? RMT_TX_MODE : RMT_RX_MODE; + bus = (rmt_bus_handle_t)perimanGetPinBus(pin, rmt_bus_type); + if (bus->frequency_Hz == frequency_Hz && bus_rmt_dir == channel_direction && bus->mem_size == mem_size) { + return true; // already initialized with the same parameters + } + } + + // set Peripheral Manager deInit Callback + perimanSetBusDeinit(ESP32_BUS_TYPE_RMT_TX, _rmtDetachBus); + perimanSetBusDeinit(ESP32_BUS_TYPE_RMT_RX, _rmtDetachBus); + + // check is pin is valid and in the right direction + if ((channel_direction == RMT_TX_MODE && !GPIO_IS_VALID_OUTPUT_GPIO(pin)) || (!GPIO_IS_VALID_GPIO(pin))) { + log_e("GPIO %d is not valid or can't be used for output in TX mode.", pin); + return false; + } + + // validate the RMT ticks by the requested frequency + // Based on 80Mhz using a divider of 8 bits (calculated as 1..256) + if (frequency_Hz > 80000000 || frequency_Hz < 312500) { + log_e("GPIO %d - Bad RMT frequency resolution. Must be between 312.5KHz to 80MHz.", pin); + return false; + } + + // Try to detach any (Tx|Rx|Whatever) previous bus or just keep it as not attached + if (!perimanClearPinBus(pin)) { + log_w("GPIO %d - Can't detach previous peripheral.", pin); + return false; + } + + // lock it + while (xSemaphoreTake(g_rmt_block_lock, portMAX_DELAY) != pdPASS) {} + + // allocate the rmt bus object and sets all fields to NULL + bus = (rmt_bus_handle_t)heap_caps_calloc(1, sizeof(struct rmt_obj_s), MALLOC_CAP_DEFAULT); + if (bus == NULL) { + log_e("GPIO %d - Bus Memory allocation fault.", pin); + goto Err; + } + + // store the RMT Freq and mem_size to check Initialization, Filter and Idle valid values in the RMT API + bus->frequency_Hz = frequency_Hz; + bus->mem_size = mem_size; + // pulses with width smaller than min_ns will be ignored (as a glitch) + //bus->signal_range_min_ns = 0; // disabled --> not necessary CALLOC set all to ZERO. + // RMT stops reading if the input stays idle for longer than max_ns + bus->signal_range_max_ns = (1000000000 / frequency_Hz) * RMT_LL_MAX_IDLE_VALUE; // maximum possible + // creates the event group to control read_done and write_done + bus->rmt_events = xEventGroupCreate(); + if (bus->rmt_events == NULL) { + log_e("GPIO %d - RMT Group Event allocation fault.", pin); + goto Err; + } + + // Starting with Receive|Transmit DONE bits set, for allowing a new request from user + xEventGroupSetBits(bus->rmt_events, RMT_FLAG_RX_DONE | RMT_FLAG_TX_DONE); + + // channel particular configuration + if (channel_direction == RMT_TX_MODE) { + // TX Channel + rmt_tx_channel_config_t tx_cfg; + memset((void *)&tx_cfg, 0, sizeof(rmt_tx_channel_config_t)); + tx_cfg.gpio_num = pin; + // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2 + tx_cfg.clk_src = RMT_CLK_SRC_DEFAULT; + tx_cfg.resolution_hz = frequency_Hz; + tx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size; + tx_cfg.trans_queue_depth = 10; // maximum allowed + tx_cfg.flags.invert_out = 0; + tx_cfg.flags.with_dma = 0; + tx_cfg.flags.io_loop_back = 0; + tx_cfg.flags.io_od_mode = 0; +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 2) + tx_cfg.intr_priority = 0; +#endif + + if (rmt_new_tx_channel(&tx_cfg, &bus->rmt_channel_h) != ESP_OK) { + log_e("GPIO %d - RMT TX Initialization error.", pin); + goto Err; + } + + // set TX Callback + rmt_tx_event_callbacks_t cbs = {.on_trans_done = _rmt_tx_done_callback}; + if (ESP_OK != rmt_tx_register_event_callbacks(bus->rmt_channel_h, &cbs, bus)) { + log_e("GPIO %d RMT - Error registering TX Callback.", pin); + goto Err; + } + + } else { + // RX Channel + rmt_rx_channel_config_t rx_cfg; + memset((void *)&rx_cfg, 0, sizeof(rmt_rx_channel_config_t)); + rx_cfg.gpio_num = pin; + // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2 + rx_cfg.clk_src = RMT_CLK_SRC_DEFAULT; + rx_cfg.resolution_hz = frequency_Hz; + rx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size; + rx_cfg.flags.invert_in = 0; + rx_cfg.flags.with_dma = 0; + rx_cfg.flags.io_loop_back = 0; +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 2) + rx_cfg.intr_priority = 0; +#endif + // try to allocate the RMT Channel + if (ESP_OK != rmt_new_rx_channel(&rx_cfg, &bus->rmt_channel_h)) { + log_e("GPIO %d RMT - RX Initialization error.", pin); + goto Err; + } + + // set RX Callback + rmt_rx_event_callbacks_t cbs = {.on_recv_done = _rmt_rx_done_callback}; + if (ESP_OK != rmt_rx_register_event_callbacks(bus->rmt_channel_h, &cbs, bus)) { + log_e("GPIO %d RMT - Error registering RX Callback.", pin); + goto Err; + } + } + + // allocate memory for the RMT Copy encoder + rmt_copy_encoder_config_t copy_encoder_config; + memset((void *)©_encoder_config, 0, sizeof(rmt_copy_encoder_config_t)); + if (rmt_new_copy_encoder(©_encoder_config, &bus->rmt_copy_encoder_h) != ESP_OK) { + log_e("GPIO %d - RMT Encoder Memory Allocation error.", pin); + goto Err; + } + + // create each channel Mutex for multi thread operations +#if !CONFIG_DISABLE_HAL_LOCKS + bus->g_rmt_objlocks = xSemaphoreCreateMutex(); + if (bus->g_rmt_objlocks == NULL) { + log_e("GPIO %d - Failed creating RMT Channel Mutex.", pin); + goto Err; + } +#endif + + rmt_enable(bus->rmt_channel_h); // starts/enables the channel + + // Finally, allocate Peripheral Manager RMT bus and associate it to its GPIO + peripheral_bus_type_t pinBusType = channel_direction == RMT_TX_MODE ? ESP32_BUS_TYPE_RMT_TX : ESP32_BUS_TYPE_RMT_RX; + if (!perimanSetPinBus(pin, pinBusType, (void *)bus, -1, -1)) { + log_e("Can't allocate the GPIO %d in the Peripheral Manager.", pin); + goto Err; + } + + // this delay is necessary when CPU frequency changes, but internal RMT setup is "old/wrong" + // The use case is related to the RMT_CPUFreq_Test example. The very first RMT Write + // goes in the wrong pace (frequency). The delay allows other IDF tasks to run to fix it. + if (loopTaskHandle != NULL) { + // it can only run when Arduino task has been already started. + delay(1); + } // prevent panic when rmtInit() is executed within an C++ object constructor + // release the mutex + xSemaphoreGive(g_rmt_block_lock); + return true; + +Err: + // release LOCK and the RMT object + xSemaphoreGive(g_rmt_block_lock); + _rmtDetachBus((void *)bus); + return false; +} + +#endif /* SOC_RMT_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-rmt.h b/cores/esp32/esp32-hal-rmt.h new file mode 100644 index 0000000..2698f9d --- /dev/null +++ b/cores/esp32/esp32-hal-rmt.h @@ -0,0 +1,240 @@ +// Copyright 2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_RMT_H_ +#define MAIN_ESP32_HAL_RMT_H_ + +#include "soc/soc_caps.h" +#if SOC_RMT_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + RMT_RX_MODE = 0, // false + RMT_TX_MODE = 1, // true +} rmt_ch_dir_t; + +typedef enum { + RMT_MEM_NUM_BLOCKS_1 = 1, + RMT_MEM_NUM_BLOCKS_2 = 2, +#if SOC_RMT_TX_CANDIDATES_PER_GROUP > 2 + RMT_MEM_NUM_BLOCKS_3 = 3, + RMT_MEM_NUM_BLOCKS_4 = 4, +#if SOC_RMT_TX_CANDIDATES_PER_GROUP > 4 + RMT_MEM_NUM_BLOCKS_5 = 5, + RMT_MEM_NUM_BLOCKS_6 = 6, + RMT_MEM_NUM_BLOCKS_7 = 7, + RMT_MEM_NUM_BLOCKS_8 = 8, +#endif +#endif +} rmt_reserve_memsize_t; + +// Each RMT Symbols has 4 bytes +// Total number of bytes per RMT_MEM_BLOCK is RMT_SYMBOLS_PER_CHANNEL_BLOCK * 4 bytes +typedef union { + struct { + uint32_t duration0 : 15; + uint32_t level0 : 1; + uint32_t duration1 : 15; + uint32_t level1 : 1; + }; + uint32_t val; +} rmt_data_t; + +// Reading and Writing shall use as rmt_symbols_size this unit +// ESP32 has 8 MEM BLOCKS in total shared with Reading and/or Writing +// ESP32-S2 has 4 MEM BLOCKS in total shared with Reading and/or Writing +// ESP32-S3 has 4 MEM BLOCKS for Reading and another 4 MEM BLOCKS for Writing +// ESP32-C3 has 2 MEM BLOCKS for Reading and another 2 MEM BLOCKS for Writing +#define RMT_SYMBOLS_PER_CHANNEL_BLOCK SOC_RMT_MEM_WORDS_PER_CHANNEL + +// Used to tell rmtRead() to wait for ever until reading data from the RMT channel +#define RMT_WAIT_FOR_EVER ((uint32_t)portMAX_DELAY) + +// Helper macro to calculate the number of RTM symbols in a array or type +#define RMT_SYMBOLS_OF(x) (sizeof(x) / sizeof(rmt_data_t)) + +/** + Initialize the object + + New Parameters in Arduino Core 3: RMT tick is set in the rmtInit() function by the + frequency of the RMT channel. Example: 100ns tick => 10MHz, thus frequency will be 10,000,000 Hz + Returns on execution success, otherwise +*/ +bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t memsize, uint32_t frequency_Hz); + +/** + Sets the End of Transmission level to be set for the when the RMT transmission ends. + This function affects how rmtWrite(), rmtWriteAsync() or rmtWriteLooping() will set the pin after writing the data. + The default EOT level is LOW, in case this function isn't used before RMT Writing. + This level can be set for each RMT pin and can be changed between writings to the same pin. + + shall be Zero (LOW) or non-zero (HIGH) value. + It only affects the transmission process, therefore, it doesn't affect any IDLE LEVEL before starting the RMT transmission. + The pre-transmission idle level can be set manually calling, for instance, digitalWrite(pin, Level). + + Returns when EOT has been correctly set for , otherwise. +*/ +bool rmtSetEOT(int pin, uint8_t EOT_Level); + +/** + Sending data in Blocking Mode. + is a 32 bits structure as defined by rmt_data_t type. + It is possible to use the macro RMT_SYMBOLS_OF(data), if data is an array of . + + Blocking mode - only returns after sending all data or by timeout. + If the writing operation takes longer than in milliseconds, it will end its + execution returning . + Timeout can be set as undefined time by passing as parameter. + When the operation is timed out, rmtTransmitCompleted() will return until the transmission + is finished, when rmtTransmitCompleted() will return . + + Returns when there is no error in the write operation, otherwise, including when it + exits by timeout. +*/ +bool rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t timeout_ms); + +/** + Sending data in Async Mode. + is a 32 bits structure as defined by rmt_data_t type. + It is possible to use the macro RMT_SYMBOLS_OF(data), if is an array of + + If more than one rmtWriteAsync() is executed in sequence, it will wait for the first transmission + to finish, resulting in a return that indicates that the rmtWriteAsync() call has failed. + In such case, this channel will have to finish the previous transmission before starting a new one. + + Non-Blocking mode - returns right after execution. + Returns on execution success, otherwise. + + will return when all data is sent. +*/ +bool rmtWriteAsync(int pin, rmt_data_t *data, size_t num_rmt_symbols); + +/** + Writing data up to the reserved memsize, looping continuously (rmtWriteLooping()) or fixed + number of times (rmtWriteRepeated()) + + is a 32 bits structure as defined by rmt_data_t type. + It is possible to use the macro RMT_SYMBOLS_OF(data), if data is an array of rmt_data_t + + If *data or size_byte are NULL | Zero, it will disable the writing loop and stop transmission + + Non-Blocking mode - returns right after execution + Returns on execution success, otherwise + + will return always while it is looping mode. + looping mode is active for rmtWriteLooping() and for rmtWriteRepeated() when loop_count > 1. +*/ +bool rmtWriteLooping(int pin, rmt_data_t *data, size_t num_rmt_symbols); +bool rmtWriteRepeated(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t loop_count); + +/** + Checks if transmission is completed and the rmtChannel ready for transmitting new data. + To be ready for a new transmission, means that the previous transmission is completed. + Returns when all data has been sent, otherwise. + The data transmission information is reset when a new rmtWrite/Async function is called. + If rmtWrite() times out or rmtWriteAsync() is called, this function will return until + all data is sent out. + rmtTranmitCompleted() will always return when rmtWriteLooping() is called, + because it has no effect in such case. +*/ +bool rmtTransmitCompleted(int pin); + +/** + Initiates blocking receive. Read data will be stored in a user provided buffer <*data> + It will read up to RMT Symbols and the value of this variable will + change to the effective number of symbols read. + is a 32 bits structure as defined by rmt_data_t type. + + If the reading operation takes longer than in milliseconds, it will end its + execution and the function will return . In a time out scenario, won't + change and rmtReceiveCompleted() can be used latter to check if there is data available. + Timeout can be set as undefined time by passing RMT_WAIT_FOR_EVER as parameter + + Returns when there is no error in the read operation, otherwise, including when it + exits by timeout. + Returns, by value, the number of RMT Symbols read in and the user buffer + when the read operation has success within the defined . If the function times out, it + will read RMT data latter asynchronously, affecting <*data> and <*num_rmt_symbols>. After timeout, + the application can check if data is already available using +*/ +bool rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, uint32_t timeout_ms); + +/** + Initiates async (non-blocking) receive. It will return immediately after execution. + Read data will be stored in a user provided buffer <*data>. + It will read up to RMT Symbols and the value of this variable will + change to the effective number of symbols read, whenever the read is completed. + is a 32 bits structure as defined by type. + + Returns when there is no error in the read operation, otherwise. + Returns asynchronously, by value, the number of RMT Symbols read, and also, it will copy + the RMT received data to the user buffer when the read operation happens. + The application can check if data is already available using +*/ +bool rmtReadAsync(int pin, rmt_data_t *data, size_t *num_rmt_symbols); + +/** + Checks if a data reception is completed and the rmtChannel has new data for processing. + Returns when data has been received, otherwise. + The data reception information is reset when a new rmtRead/Async function is called. +*/ +bool rmtReceiveCompleted(int pin); + +/** + Function used to set a threshold (in ticks) used to consider that a data reception has ended. + In receive mode, when no edge is detected on the input signal for longer than idle_thres_ticks + time, the receiving process is finished and the Data is made available by + the rmtRead/Async functions. Note that this time (in RMT channel frequency cycles) will also + define how many low/high bits are read at the end of the received data. + The function returns if it is correctly executed, otherwise. +*/ +bool rmtSetRxMaxThreshold(int pin, uint16_t idle_thres_ticks); + +/** + Parameters changed in Arduino Core 3: low and high (ticks) are now expressed in Carrier Freq in Hz and + duty cycle in percentage float 0.0 to 1.0 - example: 38.5KHz 33% High => 38500, 0.33 + + Function to set a RX demodulation carrier or TX modulation carrier + is used to enable/disable the use of demodulation/modulation for RX/TX + true means that the polarity level for the (de)modulation is positive + is the carrier frequency used + is a float deom 0 to 1 (0.5 means a square wave) of the carrier frequency + The function returns if it is correctly executed, otherwise. +*/ +bool rmtSetCarrier(int pin, bool carrier_en, bool carrier_level, uint32_t frequency_Hz, float duty_percent); + +/** + Function used to filter input noise in the RX channel. + In receiving mode, channel will ignore any input pulse which width (high or low) + is smaller than + If is Zero, it will to disable the filter. + The function returns if it is correctly executed, otherwise. +*/ +bool rmtSetRxMinThreshold(int pin, uint8_t filter_pulse_ticks); + +/** + Deinitializes the driver and releases all allocated memory + It also disables RMT for this gpio +*/ +bool rmtDeinit(int pin); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_RMT_SUPPORTED */ +#endif /* MAIN_ESP32_HAL_RMT_H_ */ diff --git a/cores/esp32/esp32-hal-sigmadelta.c b/cores/esp32/esp32-hal-sigmadelta.c new file mode 100644 index 0000000..988f441 --- /dev/null +++ b/cores/esp32/esp32-hal-sigmadelta.c @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32-hal-sigmadelta.h" + +#if SOC_SDM_SUPPORTED +#include "esp32-hal.h" +#include "esp32-hal-periman.h" +#include "driver/sdm.h" + +static bool sigmaDeltaDetachBus(void *bus) { + esp_err_t err = sdm_channel_disable((sdm_channel_handle_t)bus); + if (err != ESP_OK) { + log_w("sdm_channel_disable failed with error: %d", err); + } + err = sdm_del_channel((sdm_channel_handle_t)bus); + if (err != ESP_OK) { + log_e("sdm_del_channel failed with error: %d", err); + return false; + } + return true; +} + +bool sigmaDeltaAttach(uint8_t pin, uint32_t freq) //freq 1220-312500 +{ + perimanSetBusDeinit(ESP32_BUS_TYPE_SIGMADELTA, sigmaDeltaDetachBus); + sdm_channel_handle_t bus = NULL; + // pin may be previously attached to other peripheral -> detach it. + // if attached to sigmaDelta, detach it and set the new frequency + if (perimanGetPinBusType(pin) != ESP32_BUS_TYPE_INIT && !perimanClearPinBus(pin)) { + log_e("Pin %u could not be detached.", pin); + return false; + } + sdm_config_t config = {.gpio_num = (int)pin, .clk_src = SDM_CLK_SRC_DEFAULT, .sample_rate_hz = freq, .flags = {.invert_out = 0, .io_loop_back = 0}}; + esp_err_t err = sdm_new_channel(&config, &bus); + if (err != ESP_OK) { + log_e("sdm_new_channel failed with error: %d", err); + return false; + } + err = sdm_channel_enable(bus); + if (err != ESP_OK) { + sigmaDeltaDetachBus((void *)bus); + log_e("sdm_channel_enable failed with error: %d", err); + return false; + } + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA, (void *)bus, -1, -1)) { + sigmaDeltaDetachBus((void *)bus); + return false; + } + return true; +} + +bool sigmaDeltaWrite(uint8_t pin, uint8_t duty) //chan 0-x according to SOC duty 8 bit +{ + sdm_channel_handle_t bus = (sdm_channel_handle_t)perimanGetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA); + if (bus != NULL) { + int8_t d = duty - 128; + esp_err_t err = sdm_channel_set_duty(bus, d); + if (err != ESP_OK) { + log_e("sdm_channel_set_duty failed with error: %d", err); + return false; + } + return true; + } else { + log_e("pin %u is not attached to SigmaDelta", pin); + } + return false; +} + +bool sigmaDeltaDetach(uint8_t pin) { + void *bus = perimanGetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA); + if (bus != NULL) { + // will call sigmaDeltaDetachBus + return perimanClearPinBus(pin); + } else { + log_e("pin %u is not attached to SigmaDelta", pin); + } + return false; +} +#endif diff --git a/cores/esp32/esp32-hal-sigmadelta.h b/cores/esp32/esp32-hal-sigmadelta.h new file mode 100644 index 0000000..3ae5dd7 --- /dev/null +++ b/cores/esp32/esp32-hal-sigmadelta.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_SDM_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +//freq 1220-312500 duty 0-255 +bool sigmaDeltaAttach(uint8_t pin, uint32_t freq); +bool sigmaDeltaWrite(uint8_t pin, uint8_t duty); +bool sigmaDeltaDetach(uint8_t pin); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_SDM_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-spi.c b/cores/esp32/esp32-hal-spi.c new file mode 100644 index 0000000..a147ad3 --- /dev/null +++ b/cores/esp32/esp32-hal-spi.c @@ -0,0 +1,1865 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-spi.h" + +#if SOC_GPSPI_SUPPORTED +#include "esp32-hal.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp_attr.h" +#include "soc/spi_reg.h" +#include "soc/spi_struct.h" +#include "soc/periph_defs.h" +#include "soc/io_mux_reg.h" +#include "soc/gpio_sig_map.h" +#include "soc/rtc.h" +#if !defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32C61) +#include "hal/clk_gate_ll.h" +#endif +#include "esp32-hal-periman.h" +#include "esp_private/periph_ctrl.h" + +#include "esp_system.h" +#include "esp_intr_alloc.h" + +#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 +#include "soc/dport_reg.h" +#include "esp32/rom/ets_sys.h" +#include "esp32/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "soc/dport_reg.h" +#include "esp32s2/rom/ets_sys.h" +#include "esp32s2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "soc/dport_reg.h" +#include "esp32s3/rom/ets_sys.h" +#include "esp32s3/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C2 +#include "esp32c2/rom/ets_sys.h" +#include "esp32c2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/ets_sys.h" +#include "esp32c3/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C6 +#include "esp32c6/rom/ets_sys.h" +#include "esp32c6/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32H2 +#include "esp32h2/rom/ets_sys.h" +#include "esp32h2/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#include "esp32p4/rom/ets_sys.h" +#include "esp32p4/rom/gpio.h" +#include "hal/spi_ll.h" +#include "hal/clk_tree_ll.h" + +// ESP32P4 SPI clock source frequencies +#define SPI_P4_SPLL_FREQ_HZ (CLK_LL_PLL_480M_FREQ_MHZ * MHZ) // System PLL base frequency (480 MHz) +#define SPI_P4_MAX_FREQ_HZ 80000000 // SPI peripheral maximum frequency (80 MHz) +#elif CONFIG_IDF_TARGET_ESP32C5 +#include "esp32c5/rom/ets_sys.h" +#include "esp32c5/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/ets_sys.h" +#include "esp32c61/rom/gpio.h" +#else +#error Target CONFIG_IDF_TARGET is not supported +#endif + +struct spi_struct_t { + volatile spi_dev_t *dev; +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t lock; +#endif + uint8_t num; + int8_t sck; + int8_t miso; + int8_t mosi; + int8_t ss; + bool ss_invert; +#if defined(CONFIG_IDF_TARGET_ESP32P4) + uint8_t clk_src; // Clock source: 0=XTAL, 1=SPLL + uint32_t last_clock_div; // Last clock divider calculated + uint8_t last_clk_src; // Last clock source selected (0=XTAL, 1=SPLL) +#endif +}; + +#if CONFIG_IDF_TARGET_ESP32S2 +// ESP32S2 +#define SPI_COUNT (2) + +#define SPI_CLK_IDX(p) ((p == 0) ? FSPICLK_OUT_MUX_IDX : ((p == 1) ? SPI3_CLK_OUT_MUX_IDX : 0)) +#define SPI_MISO_IDX(p) ((p == 0) ? FSPIQ_OUT_IDX : ((p == 1) ? SPI3_Q_OUT_IDX : 0)) +#define SPI_MOSI_IDX(p) ((p == 0) ? FSPID_IN_IDX : ((p == 1) ? SPI3_D_IN_IDX : 0)) + +#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS0_OUT_IDX : ((n == 1) ? SPI3_CS1_OUT_IDX : ((n == 2) ? SPI3_CS2_OUT_IDX : 0))) +#define SPI_FSPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : 0))) +#define SPI_SS_IDX(p, n) ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0)) + +#elif CONFIG_IDF_TARGET_ESP32S3 +// ESP32S3 +#define SPI_COUNT (2) + +#define SPI_CLK_IDX(p) ((p == 0) ? FSPICLK_OUT_IDX : ((p == 1) ? SPI3_CLK_OUT_IDX : 0)) +#define SPI_MISO_IDX(p) ((p == 0) ? FSPIQ_OUT_IDX : ((p == 1) ? SPI3_Q_OUT_IDX : 0)) +#define SPI_MOSI_IDX(p) ((p == 0) ? FSPID_IN_IDX : ((p == 1) ? SPI3_D_IN_IDX : 0)) + +#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS0_OUT_IDX : ((n == 1) ? SPI3_CS1_OUT_IDX : ((n == 2) ? SPI3_CS2_OUT_IDX : 0))) +#define SPI_FSPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : 0))) +#define SPI_SS_IDX(p, n) ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0)) + +#elif CONFIG_IDF_TARGET_ESP32P4 +// ESP32P4 +#define SPI_COUNT (2) // SPI2 and SPI3. SPI0 and SPI1 are reserved for flash and PSRAM + +#define SPI_CLK_IDX(p) ((p == 0) ? SPI2_CK_PAD_OUT_IDX : ((p == 1) ? SPI3_CK_PAD_OUT_IDX : 0)) +#define SPI_MISO_IDX(p) ((p == 0) ? SPI2_Q_PAD_OUT_IDX : ((p == 1) ? SPI3_QO_PAD_OUT_IDX : 0)) +#define SPI_MOSI_IDX(p) ((p == 0) ? SPI2_D_PAD_IN_IDX : ((p == 1) ? SPI3_D_PAD_IN_IDX : 0)) + +#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS_PAD_OUT_IDX : ((n == 1) ? SPI3_CS1_PAD_OUT_IDX : ((n == 2) ? SPI3_CS2_PAD_OUT_IDX : 0))) + +#define SPI_FSPI_SS_IDX(n) \ + ((n == 0) ? SPI2_CS_PAD_OUT_IDX \ + : ((n == 1) ? SPI2_CS1_PAD_OUT_IDX \ + : ((n == 2) ? SPI2_CS2_PAD_OUT_IDX \ + : ((n == 3) ? SPI2_CS3_PAD_OUT_IDX : ((n == 4) ? SPI2_CS4_PAD_OUT_IDX : ((n == 5) ? SPI2_CS5_PAD_OUT_IDX : 0)))))) + +#define SPI_SS_IDX(p, n) ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0)) + +#elif CONFIG_IDF_TARGET_ESP32 +// ESP32 +#define SPI_COUNT (4) + +#define SPI_CLK_IDX(p) ((p == 0) ? SPICLK_OUT_IDX : ((p == 1) ? SPICLK_OUT_IDX : ((p == 2) ? HSPICLK_OUT_IDX : ((p == 3) ? VSPICLK_OUT_IDX : 0)))) +#define SPI_MISO_IDX(p) ((p == 0) ? SPIQ_OUT_IDX : ((p == 1) ? SPIQ_OUT_IDX : ((p == 2) ? HSPIQ_OUT_IDX : ((p == 3) ? VSPIQ_OUT_IDX : 0)))) +#define SPI_MOSI_IDX(p) ((p == 0) ? SPID_IN_IDX : ((p == 1) ? SPID_IN_IDX : ((p == 2) ? HSPID_IN_IDX : ((p == 3) ? VSPID_IN_IDX : 0)))) + +#define SPI_SPI_SS_IDX(n) ((n == 0) ? SPICS0_OUT_IDX : ((n == 1) ? SPICS1_OUT_IDX : ((n == 2) ? SPICS2_OUT_IDX : SPICS0_OUT_IDX))) +#define SPI_HSPI_SS_IDX(n) ((n == 0) ? HSPICS0_OUT_IDX : ((n == 1) ? HSPICS1_OUT_IDX : ((n == 2) ? HSPICS2_OUT_IDX : HSPICS0_OUT_IDX))) +#define SPI_VSPI_SS_IDX(n) ((n == 0) ? VSPICS0_OUT_IDX : ((n == 1) ? VSPICS1_OUT_IDX : ((n == 2) ? VSPICS2_OUT_IDX : VSPICS0_OUT_IDX))) +#define SPI_SS_IDX(p, n) ((p == 0) ? SPI_SPI_SS_IDX(n) : ((p == 1) ? SPI_SPI_SS_IDX(n) : ((p == 2) ? SPI_HSPI_SS_IDX(n) : ((p == 3) ? SPI_VSPI_SS_IDX(n) : 0)))) + +#else +// ESP32C2, C3, C5, C6, C61, H2 +#define SPI_COUNT (1) + +#define SPI_CLK_IDX(p) FSPICLK_OUT_IDX +#define SPI_MISO_IDX(p) FSPIQ_OUT_IDX +#define SPI_MOSI_IDX(p) FSPID_IN_IDX + +#define SPI_SPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : FSPICS0_OUT_IDX))) +#define SPI_SS_IDX(p, n) SPI_SPI_SS_IDX(n) + +#endif + +#if CONFIG_DISABLE_HAL_LOCKS +#define SPI_MUTEX_LOCK() +#define SPI_MUTEX_UNLOCK() +// clang-format off +static spi_t _spi_bus_array[] = { +#if CONFIG_IDF_TARGET_ESP32S2 ||CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 1, -1, -1, -1, -1, false} +#elif CONFIG_IDF_TARGET_ESP32 + {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 2, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 3, -1, -1, -1, -1, false} +#else // ESP32C2, C3, C5, C6, C61, H2 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false} +#endif +}; +// clang-format on +#else +#define SPI_MUTEX_LOCK() \ + do { \ + } while (xSemaphoreTake(spi->lock, portMAX_DELAY) != pdPASS) +#define SPI_MUTEX_UNLOCK() xSemaphoreGive(spi->lock) + +// clang-format off +static spi_t _spi_bus_array[] = { +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 1, -1, -1, -1, -1, false} +#elif CONFIG_IDF_TARGET_ESP32 + {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), NULL, 0, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 1, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 2, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 3, -1, -1, -1, -1, false} +#else // ESP32C2, C3, C5, C6, C61, H2 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false} +#endif +}; +// clang-format on +#endif + +static bool spiDetachBus(void *bus) { + uint8_t spi_num = (int)bus - 1; + spi_t *spi = &_spi_bus_array[spi_num]; + + if (spi->dev->clock.val == 0) { + log_d("SPI bus already stopped"); + return true; + } else if (spi->sck == -1 || (spi->miso == -1 && spi->mosi == -1)) { + log_d("Stopping SPI bus"); + spiStopBus(spi); + + spiDetachSCK(spi); + spiDetachMISO(spi); + spiDetachMOSI(spi); + spiDetachSS(spi); + spi = NULL; + return true; + } + return true; +} + +static bool spiDetachBus_SCK(void *bus) { + uint8_t spi_num = (int)bus - 1; + spi_t *spi = &_spi_bus_array[spi_num]; + if (spi->sck != -1) { + spiDetachSCK(spi); + spiDetachBus(bus); + } + return true; +} + +static bool spiDetachBus_MISO(void *bus) { + uint8_t spi_num = (int)bus - 1; + spi_t *spi = &_spi_bus_array[spi_num]; + if (spi->miso != -1) { + spiDetachMISO(spi); + spiDetachBus(bus); + } + return true; +} + +static bool spiDetachBus_MOSI(void *bus) { + uint8_t spi_num = (int)bus - 1; + spi_t *spi = &_spi_bus_array[spi_num]; + if (spi->mosi != -1) { + spiDetachMOSI(spi); + spiDetachBus(bus); + } + return true; +} + +static bool spiDetachBus_SS(void *bus) { + uint8_t spi_num = (int)bus - 1; + spi_t *spi = &_spi_bus_array[spi_num]; + if (spi->ss != -1) { + spiDetachSS(spi); + spiDetachBus(bus); + } + return true; +} + +bool spiAttachSCK(spi_t *spi, int8_t sck) { + if (!spi || sck < 0) { + return false; + } + void *bus = perimanGetPinBus(sck, ESP32_BUS_TYPE_SPI_MASTER_SCK); + if (bus != NULL && !perimanClearPinBus(sck)) { + return false; + } + pinMode(sck, OUTPUT); + pinMatrixOutAttach(sck, SPI_CLK_IDX(spi->num), false, false); + spi->sck = sck; + if (!perimanSetPinBus(sck, ESP32_BUS_TYPE_SPI_MASTER_SCK, (void *)(spi->num + 1), spi->num, -1)) { + spiDetachBus_SCK((void *)(spi->num + 1)); + log_e("Failed to set pin bus to SPI for pin %d", sck); + return false; + } + return true; +} + +bool spiAttachMISO(spi_t *spi, int8_t miso) { + if (!spi || miso < 0) { + return false; + } + void *bus = perimanGetPinBus(miso, ESP32_BUS_TYPE_SPI_MASTER_MISO); + if (bus != NULL && !perimanClearPinBus(miso)) { + return false; + } + pinMode(miso, INPUT); + pinMatrixInAttach(miso, SPI_MISO_IDX(spi->num), false); + spi->miso = miso; + if (!perimanSetPinBus(miso, ESP32_BUS_TYPE_SPI_MASTER_MISO, (void *)(spi->num + 1), spi->num, -1)) { + spiDetachBus_MISO((void *)(spi->num + 1)); + log_e("Failed to set pin bus to SPI for pin %d", miso); + return false; + } + return true; +} + +bool spiAttachMOSI(spi_t *spi, int8_t mosi) { + if (!spi || mosi < 0) { + return false; + } + void *bus = perimanGetPinBus(mosi, ESP32_BUS_TYPE_SPI_MASTER_MOSI); + if (bus != NULL && !perimanClearPinBus(mosi)) { + return false; + } + pinMode(mosi, OUTPUT); + pinMatrixOutAttach(mosi, SPI_MOSI_IDX(spi->num), false, false); + spi->mosi = mosi; + if (!perimanSetPinBus(mosi, ESP32_BUS_TYPE_SPI_MASTER_MOSI, (void *)(spi->num + 1), spi->num, -1)) { + spiDetachBus_MOSI((void *)(spi->num + 1)); + log_e("Failed to set pin bus to SPI for pin %d", mosi); + return false; + } + return true; +} + +bool spiDetachSCK(spi_t *spi) { + if (!spi) { + return false; + } + int8_t sck = spi->sck; + if (sck != -1) { + pinMatrixOutDetach(sck, false, false); + spi->sck = -1; + perimanClearPinBus(sck); + } + return true; +} + +bool spiDetachMISO(spi_t *spi) { + if (!spi) { + return false; + } + int8_t miso = spi->miso; + if (miso != -1) { + pinMatrixInDetach(SPI_MISO_IDX(spi->num), false, false); + spi->miso = -1; + perimanClearPinBus(miso); + } + return true; +} + +bool spiDetachMOSI(spi_t *spi) { + if (!spi) { + return false; + } + int8_t mosi = spi->mosi; + if (mosi != -1) { + pinMatrixOutDetach(mosi, false, false); + spi->mosi = -1; + perimanClearPinBus(mosi); + } + return true; +} + +bool spiAttachSS(spi_t *spi, uint8_t ss_num, int8_t ss) { + if (!spi || ss < 0 || ss_num > 2) { + return false; + } + void *bus = perimanGetPinBus(ss, ESP32_BUS_TYPE_SPI_MASTER_SS); + if (bus != NULL && !perimanClearPinBus(ss)) { + return false; + } + pinMode(ss, OUTPUT); + pinMatrixOutAttach(ss, SPI_SS_IDX(spi->num, ss_num), spi->ss_invert, false); + spiEnableSSPins(spi, (1 << ss_num)); + spi->ss = ss; + if (!perimanSetPinBus(ss, ESP32_BUS_TYPE_SPI_MASTER_SS, (void *)(spi->num + 1), spi->num, -1)) { + spiDetachBus_SS((void *)(spi->num + 1)); + log_e("Failed to set pin bus to SPI for pin %d", ss); + return false; + } + return true; +} + +bool spiDetachSS(spi_t *spi) { + if (!spi) { + return false; + } + int8_t ss = spi->ss; + if (ss != -1) { + pinMatrixOutDetach(ss, false, false); + spi->ss = -1; + perimanClearPinBus(ss); + } + return true; +} + +void spiEnableSSPins(spi_t *spi, uint8_t ss_mask) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.val &= ~(ss_mask & SPI_SS_MASK_ALL); +#else + spi->dev->misc.val &= ~(ss_mask & SPI_SS_MASK_ALL); +#endif + SPI_MUTEX_UNLOCK(); +} + +void spiDisableSSPins(spi_t *spi, uint8_t ss_mask) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.val |= (ss_mask & SPI_SS_MASK_ALL); +#else + spi->dev->misc.val |= (ss_mask & SPI_SS_MASK_ALL); +#endif + SPI_MUTEX_UNLOCK(); +} + +void spiSSEnable(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + spi->dev->user.cs_setup = 1; + spi->dev->user.cs_hold = 1; + SPI_MUTEX_UNLOCK(); +} + +void spiSSDisable(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + spi->dev->user.cs_setup = 0; + spi->dev->user.cs_hold = 0; + SPI_MUTEX_UNLOCK(); +} + +void spiSSInvert(spi_t *spi, bool invert) { + if (spi) { + spi->ss_invert = invert; + } +} + +void spiSSSet(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.cs_keep_active = 1; +#else + spi->dev->misc.cs_keep_active = 1; +#endif + SPI_MUTEX_UNLOCK(); +} + +void spiSSClear(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.cs_keep_active = 0; +#else + spi->dev->misc.cs_keep_active = 0; +#endif + SPI_MUTEX_UNLOCK(); +} + +uint32_t spiGetClockDiv(spi_t *spi) { + if (!spi) { + return 0; + } + return spi->dev->clock.val; +} + +#if defined(CONFIG_IDF_TARGET_ESP32P4) +/** + * @brief Calculate SPI frequency from divider value and source frequency + * + * @param divider The clock divider value (must be > 0) + * @param source_freq The source clock frequency in Hz (e.g., 40MHz for XTAL, 480MHz for SPLL) + * @return uint32_t The calculated SPI clock frequency in Hz, or 0 if divider is 0 + * + * @note ESP32P4-specific helper function. Calculates: frequency = source_freq / divider + */ +static inline uint32_t _dividerToFreq(uint32_t divider, uint32_t source_freq) { + if (divider == 0) { + return 0; // Safety check + } + return source_freq / divider; +} + +/** + * @brief Extract the divider value from a clockDiv register value + * + * @param clockDiv The SPI clock divider register value + * @return uint32_t The calculated divider: (clkdiv_pre + 1) * (clkcnt_n + 1) + * + * @note ESP32P4-specific helper function. Extracts clkcnt_n (bits 12-17) and + * clkdiv_pre (bits 18-21) from the register value using bit shifts. + * For SPI_CLK_EQU_SYSCLK (0x80000000), this naturally returns 1 (no division). + */ +static inline uint32_t _clockDivToDivider(uint32_t clockDiv) { + uint32_t clkcnt_n = (clockDiv >> 12) & 0x3F; + uint32_t clkdiv_pre = (clockDiv >> 18) & 0xF; + return ((clkdiv_pre + 1) * (clkcnt_n + 1)); +} +#endif + +/** + * @brief Internal function to set SPI clock divider and handle ESP32P4 clock source switching + * + * @param spi Pointer to SPI bus structure + * @param clockDiv The clock divider register value to set + * + * @note This function does NOT acquire the SPI mutex - it must be called from within + * a context that already holds the mutex. + * + * @note Callers (all properly acquire mutex before calling): + * - spiSetClockDiv() - acquires mutex via SPI_MUTEX_LOCK() before calling + * - spiTransaction() - acquires mutex via SPI_MUTEX_LOCK() before calling + * - _on_apb_change() - acquires mutex via SPI_MUTEX_LOCK() before calling (APB_AFTER_CHANGE case) + * + * @note ESP32P4-specific behavior: + * - Determines the appropriate clock source (XTAL or SPLL) based on the divider value + * - Uses stored per-instance clock source information if available (from last calculation) + * - Otherwise infers clock source by checking which gives a valid frequency: + * * XTAL is capped at 40MHz, so if calculated frequency > 40MHz, must use SPLL + * * For <= 40MHz frequencies, prefers XTAL if valid + * - Switches clock source if needed (with proper clock gating and delay) + * - Updates per-instance tracking variables (last_clock_div, last_clk_src) + */ +static void _spiSetClockDivInternal(spi_t *spi, uint32_t clockDiv) { + if (!spi) { + return; + } +#if defined(CONFIG_IDF_TARGET_ESP32P4) + // ESP32P4: Determine clock source from divider + // The divider was calculated by spiFrequencyToClockDiv() which picks the best match + // We store which source was selected per SPI instance, so use that if available. + // Otherwise, infer from the divider by checking which gives a "more reasonable" frequency. + uint32_t xtal_freq = getXtalFrequencyMhz() * 1000000; // Actual XTAL frequency (typically 40 MHz) + uint32_t spll_freq = SPI_P4_SPLL_FREQ_HZ; + + uint8_t new_clk_src; + if (clockDiv == spi->last_clock_div && spi->last_clock_div != 0) { + new_clk_src = spi->last_clk_src; + } else { + uint32_t divider = _clockDivToDivider(clockDiv); + uint32_t freq_with_xtal = _dividerToFreq(divider, xtal_freq); + uint32_t freq_with_spll = _dividerToFreq(divider, spll_freq); + + // Infer: Prefer XTAL whenever it yields a valid <= 40MHz SPI clock, + // and fall back to SPLL only when XTAL cannot produce a valid frequency. + if (freq_with_xtal > 0 && freq_with_xtal <= xtal_freq) { + new_clk_src = 0; // XTAL + } else if (freq_with_spll > 0) { + new_clk_src = 1; // SPLL + } else { + // Both inferred frequencies are invalid; keep current source to avoid unnecessary switching. + new_clk_src = spi->clk_src; + } + } + + // Store the divider and source for this SPI instance + spi->last_clock_div = clockDiv; + spi->last_clk_src = new_clk_src; + + if (spi->clk_src != new_clk_src) { + // Determine SPI host ID once to avoid duplicate conditionals + int host = (spi->num == FSPI) ? SPI2_HOST : SPI3_HOST; + + PERIPH_RCC_ATOMIC() { + spi_ll_enable_clock(host, false); + spi_ll_set_clk_source(spi->dev, new_clk_src ? SPI_CLK_SRC_SPLL : SPI_CLK_SRC_XTAL); + spi_ll_enable_clock(host, true); + } + spi->clk_src = new_clk_src; + ets_delay_us(10); + } +#endif + spi->dev->clock.val = clockDiv; +} + +void spiSetClockDiv(spi_t *spi, uint32_t clockDiv) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + _spiSetClockDivInternal(spi, clockDiv); + SPI_MUTEX_UNLOCK(); +} + +uint8_t spiGetDataMode(spi_t *spi) { + if (!spi) { + return 0; + } +#if CONFIG_IDF_TARGET_ESP32 + bool idleEdge = spi->dev->pin.ck_idle_edge; +#else + bool idleEdge = spi->dev->misc.ck_idle_edge; +#endif + bool outEdge = spi->dev->user.ck_out_edge; + if (idleEdge) { + if (outEdge) { + return SPI_MODE2; + } + return SPI_MODE3; + } + if (outEdge) { + return SPI_MODE1; + } + return SPI_MODE0; +} + +void spiSetDataMode(spi_t *spi, uint8_t dataMode) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + switch (dataMode) { + case SPI_MODE1: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 0; +#else + spi->dev->misc.ck_idle_edge = 0; +#endif + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE2: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 1; +#else + spi->dev->misc.ck_idle_edge = 1; +#endif + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE3: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 1; +#else + spi->dev->misc.ck_idle_edge = 1; +#endif + spi->dev->user.ck_out_edge = 0; + break; + case SPI_MODE0: + default: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 0; +#else + spi->dev->misc.ck_idle_edge = 0; +#endif + spi->dev->user.ck_out_edge = 0; + break; + } + SPI_MUTEX_UNLOCK(); +} + +uint8_t spiGetBitOrder(spi_t *spi) { + if (!spi) { + return 0; + } + return (spi->dev->ctrl.wr_bit_order | spi->dev->ctrl.rd_bit_order) == 0; +} + +void spiSetBitOrder(spi_t *spi, uint8_t bitOrder) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + if (SPI_MSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 0; + spi->dev->ctrl.rd_bit_order = 0; + } else if (SPI_LSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 1; + spi->dev->ctrl.rd_bit_order = 1; + } + SPI_MUTEX_UNLOCK(); +} + +static void _on_apb_change(void *arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb) { + spi_t *spi = (spi_t *)arg; + if (ev_type == APB_BEFORE_CHANGE) { + SPI_MUTEX_LOCK(); + while (spi->dev->cmd.usr); + } else { +#if defined(CONFIG_IDF_TARGET_ESP32P4) + // ESP32P4: Use the stored clock source to determine base frequency + uint32_t base_freq = (spi->clk_src == 1) ? SPI_P4_SPLL_FREQ_HZ : (getXtalFrequencyMhz() * 1000000); + uint32_t current_freq = base_freq / ((spi->dev->clock.clkdiv_pre + 1) * (spi->dev->clock.clkcnt_n + 1)); + uint32_t new_clockDiv = spiFrequencyToClockDiv(spi, current_freq); + // Use _spiSetClockDivInternal to ensure clock source is updated if needed + _spiSetClockDivInternal(spi, new_clockDiv); +#else + spi->dev->clock.val = spiFrequencyToClockDiv(spi, old_apb / ((spi->dev->clock.clkdiv_pre + 1) * (spi->dev->clock.clkcnt_n + 1))); +#endif + SPI_MUTEX_UNLOCK(); + } +} + +static void spiInitBus(spi_t *spi) { +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->slave.trans_done = 0; +#endif + spi->dev->slave.val = 0; +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.val = 0; +#else + spi->dev->misc.val = 0; +#endif + spi->dev->user.val = 0; + spi->dev->user1.val = 0; + spi->dev->ctrl.val = 0; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->ctrl1.val = 0; + spi->dev->ctrl2.val = 0; +#else + spi->dev->clk_gate.val = 0; + spi->dev->dma_conf.val = 0; + spi->dev->dma_conf.rx_afifo_rst = 1; + spi->dev->dma_conf.buf_afifo_rst = 1; +#endif + spi->dev->clock.val = 0; +} + +void spiStopBus(spi_t *spi) { + if (!spi) { + return; + } + + removeApbChangeCallback(spi, _on_apb_change); + + SPI_MUTEX_LOCK(); + spiInitBus(spi); + SPI_MUTEX_UNLOCK(); +} + +spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder) { + if (spi_num >= SPI_COUNT) { + log_e("SPI bus index %d is out of range", spi_num); + return NULL; + } + + perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_SCK, spiDetachBus_SCK); + perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_MISO, spiDetachBus_MISO); + perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_MOSI, spiDetachBus_MOSI); + perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_SS, spiDetachBus_SS); + + spi_t *spi = &_spi_bus_array[spi_num]; + +#if !CONFIG_DISABLE_HAL_LOCKS + if (spi->lock == NULL) { + spi->lock = xSemaphoreCreateMutex(); + if (spi->lock == NULL) { + return NULL; + } + } +#endif + +#if CONFIG_IDF_TARGET_ESP32S2 + if (spi_num == FSPI) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST); + } else if (spi_num == HSPI) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST); + } +#elif CONFIG_IDF_TARGET_ESP32S3 + if (spi_num == FSPI) { + periph_ll_reset(PERIPH_SPI2_MODULE); + periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE); + } else if (spi_num == HSPI) { + periph_ll_reset(PERIPH_SPI3_MODULE); + periph_ll_enable_clk_clear_rst(PERIPH_SPI3_MODULE); + } +#elif CONFIG_IDF_TARGET_ESP32 + if (spi_num == HSPI) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST); + } else if (spi_num == VSPI) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST); + } else { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST); + } +#elif CONFIG_IDF_TARGET_ESP32P4 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" + if (spi_num == FSPI) { + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_GPSPI2_MODULE, ref_count) { + if (ref_count == 0) { + PERIPH_RCC_ATOMIC() { + spi_ll_enable_bus_clock(SPI2_HOST, true); + spi_ll_reset_register(SPI2_HOST); + spi_ll_enable_clock(SPI2_HOST, true); + } + } + } + } else if (spi_num == HSPI) { + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_GPSPI3_MODULE, ref_count) { + if (ref_count == 0) { + PERIPH_RCC_ATOMIC() { + spi_ll_enable_bus_clock(SPI3_HOST, true); + spi_ll_reset_register(SPI3_HOST); + spi_ll_enable_clock(SPI3_HOST, true); + } + } + } + } +#pragma GCC diagnostic pop +#elif defined(__PERIPH_CTRL_ALLOW_LEGACY_API) + periph_ll_reset(PERIPH_SPI2_MODULE); + periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE); +#endif + + SPI_MUTEX_LOCK(); + spiInitBus(spi); +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->clk_gate.clk_en = 1; + spi->dev->clk_gate.mst_clk_sel = 1; + spi->dev->clk_gate.mst_clk_active = 1; +#if defined(CONFIG_IDF_TARGET_ESP32P4) + // Initialize clock source to XTAL (will be changed to SPLL if needed) + spi->clk_src = 0; // 0 = XTAL, 1 = SPLL + spi->last_clock_div = 0; // Initialize per-instance storage + spi->last_clk_src = 0; // Initialize per-instance storage +#endif +#if defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) + spi->dev->dma_conf.tx_seg_trans_clr_en = 1; + spi->dev->dma_conf.rx_seg_trans_clr_en = 1; + spi->dev->dma_conf.dma_seg_trans_en = 0; +#endif +#endif + spi->dev->user.usr_mosi = 1; + spi->dev->user.usr_miso = 1; + spi->dev->user.doutdin = 1; + int i; + for (i = 0; i < 16; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = 0x00000000; +#else + spi->dev->data_buf[i].val = 0x00000000; +#endif + } + SPI_MUTEX_UNLOCK(); + + spiSetDataMode(spi, dataMode); + spiSetBitOrder(spi, bitOrder); + spiSetClockDiv(spi, clockDiv); + + addApbChangeCallback(spi, _on_apb_change); + + return spi; +} + +void spiWaitReady(spi_t *spi) { + if (!spi) { + return; + } + while (spi->dev->cmd.usr); +} + +#if CONFIG_IDF_TARGET_ESP32S2 +#define usr_mosi_dbitlen usr_mosi_bit_len +#define usr_miso_dbitlen usr_miso_bit_len +#elif !defined(CONFIG_IDF_TARGET_ESP32) +#define usr_mosi_dbitlen ms_data_bitlen +#define usr_miso_dbitlen ms_data_bitlen +#define mosi_dlen ms_dlen +#define miso_dlen ms_dlen +#endif + +void spiWrite(spi_t *spi, const uint32_t *data, uint8_t len) { + if (!spi) { + return; + } + int i; + if (len > 16) { + len = 16; + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif + for (i = 0; i < len; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; +#endif + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + SPI_MUTEX_UNLOCK(); +} + +void spiTransfer(spi_t *spi, uint32_t *data, uint8_t len) { + if (!spi) { + return; + } + int i; + if (len > 16) { + len = 16; + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1; + spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1; + for (i = 0; i < len; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; +#endif + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + for (i = 0; i < len; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data[i] = spi->dev->data_buf[i]; +#else + data[i] = spi->dev->data_buf[i].val; +#endif + } + SPI_MUTEX_UNLOCK(); +} + +void spiWriteByte(spi_t *spi, uint8_t data) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif + +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + SPI_MUTEX_UNLOCK(); +} + +uint8_t spiTransferByte(spi_t *spi, uint8_t data) { + if (!spi) { + return 0; + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; + spi->dev->miso_dlen.usr_miso_dbitlen = 7; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0] & 0xFF; +#else + data = spi->dev->data_buf[0].val & 0xFF; +#endif + SPI_MUTEX_UNLOCK(); + return data; +} + +static uint32_t __spiTranslate32(uint32_t data) { + union { + uint32_t l; + uint8_t b[4]; + } out; + out.l = data; + return out.b[3] | (out.b[2] << 8) | (out.b[1] << 16) | (out.b[0] << 24); +} + +void spiWriteWord(spi_t *spi, uint16_t data) { + if (!spi) { + return; + } + if (!spi->dev->ctrl.wr_bit_order) { + data = (data >> 8) | (data << 8); + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + SPI_MUTEX_UNLOCK(); +} + +uint16_t spiTransferWord(spi_t *spi, uint16_t data) { + if (!spi) { + return 0; + } + if (!spi->dev->ctrl.wr_bit_order) { + data = (data >> 8) | (data << 8); + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; + spi->dev->miso_dlen.usr_miso_dbitlen = 15; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; +#endif + SPI_MUTEX_UNLOCK(); + if (!spi->dev->ctrl.rd_bit_order) { + data = (data >> 8) | (data << 8); + } + return data; +} + +void spiWriteLong(spi_t *spi, uint32_t data) { + if (!spi) { + return; + } + if (!spi->dev->ctrl.wr_bit_order) { + data = __spiTranslate32(data); + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + SPI_MUTEX_UNLOCK(); +} + +uint32_t spiTransferLong(spi_t *spi, uint32_t data) { + if (!spi) { + return 0; + } + if (!spi->dev->ctrl.wr_bit_order) { + data = __spiTranslate32(data); + } + SPI_MUTEX_LOCK(); + spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; + spi->dev->miso_dlen.usr_miso_dbitlen = 31; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; +#endif + SPI_MUTEX_UNLOCK(); + if (!spi->dev->ctrl.rd_bit_order) { + data = __spiTranslate32(data); + } + return data; +} + +static void __spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t bytes) { + if (!spi) { + return; + } + uint32_t i; + + if (bytes > 64) { + bytes = 64; + } + + uint32_t words = (bytes + 3) / 4; //16 max + + uint32_t wordsBuf[16] = { + 0, + }; + uint8_t *bytesBuf = (uint8_t *)wordsBuf; + + if (data) { + memcpy(bytesBuf, data, bytes); //copy data to buffer + } else { + memset(bytesBuf, 0xFF, bytes); + } + + spi->dev->mosi_dlen.usr_mosi_dbitlen = ((bytes * 8) - 1); + spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1); + + for (i = 0; i < words; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = wordsBuf[i]; //copy buffer to spi fifo +#else + spi->dev->data_buf[i].val = wordsBuf[i]; //copy buffer to spi fifo +#endif + } + +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + + while (spi->dev->cmd.usr); + + if (out) { + for (i = 0; i < words; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + wordsBuf[i] = spi->dev->data_buf[i]; //copy spi fifo to buffer +#else + wordsBuf[i] = spi->dev->data_buf[i].val; //copy spi fifo to buffer +#endif + } + memcpy(out, bytesBuf, bytes); //copy buffer to output + } +} + +void spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t size) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + while (size) { + if (size > 64) { + __spiTransferBytes(spi, data, out, 64); + size -= 64; + if (data) { + data += 64; + } + if (out) { + out += 64; + } + } else { + __spiTransferBytes(spi, data, out, size); + size = 0; + } + } + SPI_MUTEX_UNLOCK(); +} + +void spiTransferBits(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + spiTransferBitsNL(spi, data, out, bits); + SPI_MUTEX_UNLOCK(); +} + +/* + * Manual Lock Management + * */ + +#define MSB_32_SET(var, val) \ + { \ + uint8_t *d = (uint8_t *)&(val); \ + (var) = d[3] | (d[2] << 8) | (d[1] << 16) | (d[0] << 24); \ + } +#define MSB_24_SET(var, val) \ + { \ + uint8_t *d = (uint8_t *)&(val); \ + (var) = d[2] | (d[1] << 8) | (d[0] << 16); \ + } +#define MSB_16_SET(var, val) \ + { (var) = (((val) & 0xFF00) >> 8) | (((val) & 0xFF) << 8); } +#define MSB_PIX_SET(var, val) \ + { \ + uint8_t *d = (uint8_t *)&(val); \ + (var) = d[1] | (d[0] << 8) | (d[3] << 16) | (d[2] << 24); \ + } + +void spiTransaction(spi_t *spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); + // Set clock divider (handles ESP32P4 clock source selection if needed) + _spiSetClockDivInternal(spi, clockDiv); + switch (dataMode) { + case SPI_MODE1: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 0; +#else + spi->dev->misc.ck_idle_edge = 0; +#endif + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE2: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 1; +#else + spi->dev->misc.ck_idle_edge = 1; +#endif + spi->dev->user.ck_out_edge = 1; + break; + case SPI_MODE3: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 1; +#else + spi->dev->misc.ck_idle_edge = 1; +#endif + spi->dev->user.ck_out_edge = 0; + break; + case SPI_MODE0: + default: +#if CONFIG_IDF_TARGET_ESP32 + spi->dev->pin.ck_idle_edge = 0; +#else + spi->dev->misc.ck_idle_edge = 0; +#endif + spi->dev->user.ck_out_edge = 0; + break; + } + if (SPI_MSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 0; + spi->dev->ctrl.rd_bit_order = 0; + } else if (SPI_LSBFIRST == bitOrder) { + spi->dev->ctrl.wr_bit_order = 1; + spi->dev->ctrl.rd_bit_order = 1; + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + // Sync new config with hardware, fixes https://github.com/espressif/arduino-esp32/issues/9221 + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif +} + +void spiSimpleTransaction(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_LOCK(); +} + +void spiEndTransaction(spi_t *spi) { + if (!spi) { + return; + } + SPI_MUTEX_UNLOCK(); +} + +void ARDUINO_ISR_ATTR spiWriteByteNL(spi_t *spi, uint8_t data) { + if (!spi) { + return; + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +} + +uint8_t spiTransferByteNL(spi_t *spi, uint8_t data) { + if (!spi) { + return 0; + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; + spi->dev->miso_dlen.usr_miso_dbitlen = 7; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0] & 0xFF; +#else + data = spi->dev->data_buf[0].val & 0xFF; +#endif + return data; +} + +void ARDUINO_ISR_ATTR spiWriteShortNL(spi_t *spi, uint16_t data) { + if (!spi) { + return; + } + if (!spi->dev->ctrl.wr_bit_order) { + MSB_16_SET(data, data); + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +} + +uint16_t spiTransferShortNL(spi_t *spi, uint16_t data) { + if (!spi) { + return 0; + } + if (!spi->dev->ctrl.wr_bit_order) { + MSB_16_SET(data, data); + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; + spi->dev->miso_dlen.usr_miso_dbitlen = 15; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0] & 0xFFFF; +#else + data = spi->dev->data_buf[0].val & 0xFFFF; +#endif + if (!spi->dev->ctrl.rd_bit_order) { + MSB_16_SET(data, data); + } + return data; +} + +void ARDUINO_ISR_ATTR spiWriteLongNL(spi_t *spi, uint32_t data) { + if (!spi) { + return; + } + if (!spi->dev->ctrl.wr_bit_order) { + MSB_32_SET(data, data); + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +} + +uint32_t spiTransferLongNL(spi_t *spi, uint32_t data) { + if (!spi) { + return 0; + } + if (!spi->dev->ctrl.wr_bit_order) { + MSB_32_SET(data, data); + } + spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; + spi->dev->miso_dlen.usr_miso_dbitlen = 31; +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; +#endif + if (!spi->dev->ctrl.rd_bit_order) { + MSB_32_SET(data, data); + } + return data; +} + +void spiWriteNL(spi_t *spi, const void *data_in, uint32_t len) { + if (!spi) { + return; + } + size_t longs = len >> 2; + if (len & 3) { + longs++; + } + uint32_t *data = (uint32_t *)data_in; + size_t c_len = 0, c_longs = 0; + + while (len) { + c_len = (len > 64) ? 64 : len; + c_longs = (longs > 16) ? 16 : longs; + + spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif + for (size_t i = 0; i < c_longs; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; +#endif + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + + data += c_longs; + longs -= c_longs; + len -= c_len; + } +} + +void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint32_t len) { + if (!spi) { + return; + } + size_t longs = len >> 2; + if (len & 3) { + longs++; + } + uint32_t *data = (uint32_t *)data_in; + uint32_t *result = (uint32_t *)data_out; + size_t c_len = 0, c_longs = 0; + + while (len) { + c_len = (len > 64) ? 64 : len; + c_longs = (longs > 16) ? 16 : longs; + + spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1; + spi->dev->miso_dlen.usr_miso_dbitlen = (c_len * 8) - 1; + if (data) { + for (size_t i = 0; i < c_longs; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; +#endif + } + } else { + for (size_t i = 0; i < c_longs; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = 0xFFFFFFFF; +#else + spi->dev->data_buf[i].val = 0xFFFFFFFF; +#endif + } + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + if (result) { + if (c_len & 3) { + for (size_t i = 0; i < (c_longs - 1); i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + result[i] = spi->dev->data_buf[i]; +#else + result[i] = spi->dev->data_buf[i].val; +#endif + } +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + uint32_t last_data = spi->dev->data_buf[c_longs - 1]; +#else + uint32_t last_data = spi->dev->data_buf[c_longs - 1].val; +#endif + uint8_t *last_out8 = (uint8_t *)&result[c_longs - 1]; + uint8_t *last_data8 = (uint8_t *)&last_data; + for (size_t i = 0; i < (c_len & 3); i++) { + last_out8[i] = last_data8[i]; + } + } else { + for (size_t i = 0; i < c_longs; i++) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + result[i] = spi->dev->data_buf[i]; +#else + result[i] = spi->dev->data_buf[i].val; +#endif + } + } + } + if (data) { + data += c_longs; + } + if (result) { + result += c_longs; + } + longs -= c_longs; + len -= c_len; + } +} + +void spiTransferBitsNL(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) { + if (!spi) { + return; + } + + if (bits > 32) { + bits = 32; + } + uint32_t bytes = (bits + 7) / 8; //64 max + uint32_t mask = (((uint64_t)1 << bits) - 1) & 0xFFFFFFFF; + data = data & mask; + if (!spi->dev->ctrl.wr_bit_order) { + if (bytes == 2) { + MSB_16_SET(data, data); + } else if (bytes == 3) { + MSB_24_SET(data, data); + } else { + MSB_32_SET(data, data); + } + } + + spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1); + spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; +#endif +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; +#endif + if (out) { + *out = data; + if (!spi->dev->ctrl.rd_bit_order) { + if (bytes == 2) { + MSB_16_SET(*out, data); + } else if (bytes == 3) { + MSB_24_SET(*out, data); + } else { + MSB_32_SET(*out, data); + } + } + } +} + +void ARDUINO_ISR_ATTR spiWritePixelsNL(spi_t *spi, const void *data_in, uint32_t len) { + size_t longs = len >> 2; + if (len & 3) { + longs++; + } + bool msb = !spi->dev->ctrl.wr_bit_order; + uint32_t *data = (uint32_t *)data_in; + size_t c_len = 0, c_longs = 0, l_bytes = 0; + + while (len) { + c_len = (len > 64) ? 64 : len; + c_longs = (longs > 16) ? 16 : longs; + l_bytes = (c_len & 3); + + spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 + spi->dev->miso_dlen.usr_miso_dbitlen = 0; +#endif + for (size_t i = 0; i < c_longs; i++) { + if (msb) { + if (l_bytes && i == (c_longs - 1)) { + if (l_bytes == 2) { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + MSB_16_SET(spi->dev->data_buf[i], data[i]); +#else + MSB_16_SET(spi->dev->data_buf[i].val, data[i]); +#endif + } else { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i] & 0xFF; +#else + spi->dev->data_buf[i].val = data[i] & 0xFF; +#endif + } + } else { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + MSB_PIX_SET(spi->dev->data_buf[i], data[i]); +#else + MSB_PIX_SET(spi->dev->data_buf[i].val, data[i]); +#endif + } + } else { +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; +#endif + } + } +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + spi->dev->cmd.update = 1; + while (spi->dev->cmd.update); +#endif + spi->dev->cmd.usr = 1; + while (spi->dev->cmd.usr); + + data += c_longs; + longs -= c_longs; + len -= c_len; + } +} + +/* + * Clock Calculators + * + * */ + +typedef union { + uint32_t value; + struct { + uint32_t clkcnt_l : 6; /*it must be equal to spi_clkcnt_N.*/ + uint32_t clkcnt_h : 6; /*it must be floor((spi_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n : 6; /*it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + uint32_t clkdiv_pre : 4; /*it is pre-divider of spi_clk.*/ + uint32_t reserved : 9; /*reserved*/ +#else + uint32_t clkdiv_pre : 13; /*it is pre-divider of spi_clk.*/ +#endif + uint32_t clk_equ_sysclk : 1; /*1: spi_clk is equal to system 0: spi_clk is divided from system clock.*/ + }; +} spiClk_t; + +#define ClkRegToFreq(reg) (apb_freq / (((reg)->clkdiv_pre + 1) * ((reg)->clkcnt_n + 1))) + +uint32_t spiClockDivToFrequency(spi_t *spi, uint32_t clockDiv) { + uint32_t apb_freq = getApbFrequency(); +#if defined(CONFIG_IDF_TARGET_ESP32P4) + // ESP32P4: Use the actual clock source being used by this SPI instance + if (spi && spi->clk_src == 1) { + // SPLL is being used + apb_freq = SPI_P4_SPLL_FREQ_HZ; + } else { + // XTAL is being used (default or if spi is NULL) + apb_freq = getXtalFrequencyMhz() * 1000000; + } +#else + // For non-ESP32P4 targets, ignore spi parameter; always use system APB frequency. + (void)spi; +#endif + spiClk_t reg = {clockDiv}; + return ClkRegToFreq(®); +} + +/** + * @brief Calculate SPI clock divider register value for a given frequency and clock source + * + * @param freq Desired SPI clock frequency in Hz + * @param source_freq Source clock frequency in Hz (e.g., 40MHz for XTAL, 480MHz for SPLL) + * @return uint32_t Clock divider register value, or SPI_CLK_EQU_SYSCLK if freq >= source_freq + * + * @note This function calculates the optimal divider values (clkdiv_pre and clkcnt_n) to achieve + * the desired frequency from the given source. It searches for the best match that produces + * a frequency <= the desired frequency (never exceeding it). + * + * @note If the desired frequency is >= source_freq, returns SPI_CLK_EQU_SYSCLK (0x80000000) + * which indicates the clock should equal the source without division. + * + * @note If the desired frequency is below the minimum achievable, returns the minimum divider + * register value (0x7FFFF000). + * + * @note Used by spiFrequencyToClockDiv() to calculate dividers for both XTAL and SPLL sources + * on ESP32P4, allowing selection of the source that gives the closest match. + */ +static uint32_t _spiFrequencyToClockDivWithSource(uint32_t freq, uint32_t source_freq) { + if (freq >= source_freq) { + return SPI_CLK_EQU_SYSCLK; + } + + const spiClk_t minFreqReg = {0x7FFFF000}; + // Calculate minFreq using the provided source frequency + uint32_t minFreq = source_freq / (((minFreqReg.clkdiv_pre + 1) * (minFreqReg.clkcnt_n + 1))); + if (freq < minFreq) { + return minFreqReg.value; + } + + uint8_t calN = 1; + spiClk_t bestReg = {0}; + uint32_t bestFreq = 0; + + while (calN <= 0x3F) { + spiClk_t reg = {0}; + uint32_t calFreq; + int32_t calPre; + int8_t calPreVari = -2; + + reg.clkcnt_n = calN; + + while (calPreVari++ <= 1) { + calPre = (((source_freq / (reg.clkcnt_n + 1)) / freq) - 1) + calPreVari; +#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) + if (calPre > 0xF) { + reg.clkdiv_pre = 0xF; +#else + if (calPre > 0x1FFF) { + reg.clkdiv_pre = 0x1FFF; +#endif + } else if (calPre <= 0) { + reg.clkdiv_pre = 0; + } else { + reg.clkdiv_pre = calPre; + } + reg.clkcnt_l = ((reg.clkcnt_n + 1) / 2); + // Calculate frequency directly using source_freq instead of ClkRegToFreq macro + calFreq = source_freq / (((reg.clkdiv_pre + 1) * (reg.clkcnt_n + 1))); + if (calFreq == freq) { + memcpy(&bestReg, ®, sizeof(bestReg)); + break; + } else if (calFreq < freq) { + if (bestFreq == 0 || (freq - calFreq) < (freq - bestFreq)) { + bestFreq = calFreq; + memcpy(&bestReg, ®, sizeof(bestReg)); + } + } + } + if (calFreq == (int32_t)freq) { + break; + } + calN++; + } + return bestReg.value; +} + +uint32_t spiFrequencyToClockDiv(spi_t *spi, uint32_t freq) { +#if defined(CONFIG_IDF_TARGET_ESP32P4) + // ESP32P4: Limit frequency to SPI peripheral maximum + if (freq > SPI_P4_MAX_FREQ_HZ) { + freq = SPI_P4_MAX_FREQ_HZ; + } + + // Try both clock sources and pick the one that gives frequency closest to desired + uint32_t xtal_freq = getXtalFrequencyMhz() * 1000000; // Actual XTAL frequency (typically 40 MHz) + uint32_t spll_freq = SPI_P4_SPLL_FREQ_HZ; + + // Calculate dividers for both sources + uint32_t div_xtal = _spiFrequencyToClockDivWithSource(freq, xtal_freq); + uint32_t div_spll = _spiFrequencyToClockDivWithSource(freq, spll_freq); + + // Calculate actual frequencies each divider would produce + uint32_t divider_xtal = _clockDivToDivider(div_xtal); + uint32_t divider_spll = _clockDivToDivider(div_spll); + uint32_t freq_xtal = _dividerToFreq(divider_xtal, xtal_freq); + uint32_t freq_spll = _dividerToFreq(divider_spll, spll_freq); + + // Pick the one closest to desired frequency + uint32_t diff_xtal = (freq > freq_xtal) ? (freq - freq_xtal) : (freq_xtal - freq); + uint32_t diff_spll = (freq > freq_spll) ? (freq - freq_spll) : (freq_spll - freq); + + // Pick the one with closest difference to desired frequency + // If both are valid (XTAL capped at its actual frequency) and differences are equal, prefer XTAL + uint8_t best_is_spll; + if (diff_spll < diff_xtal) { + best_is_spll = 1; // SPLL is closer + } else if (diff_xtal < diff_spll) { + best_is_spll = 0; // XTAL is closer + } else { + // Equal differences: prefer XTAL if it's valid (freq_xtal <= xtal_freq), otherwise use SPLL + best_is_spll = (freq_xtal <= xtal_freq) ? 0 : 1; + } + uint32_t best_div = best_is_spll ? div_spll : div_xtal; + + // Store the divider and source for this SPI instance (if spi is provided) + if (spi) { + spi->last_clock_div = best_div; + spi->last_clk_src = best_is_spll; + } + + // Return divider for the clock source that gives closest match + return best_div; +#else + // Non-ESP32P4: Only use APB clock, spi parameter unused. + (void)spi; // Suppress unused parameter warning + return _spiFrequencyToClockDivWithSource(freq, getApbFrequency()); +#endif +} + +#endif /* SOC_GPSPI_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-spi.h b/cores/esp32/esp32-hal-spi.h new file mode 100644 index 0000000..f692221 --- /dev/null +++ b/cores/esp32/esp32-hal-spi.h @@ -0,0 +1,151 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_SPI_H_ +#define MAIN_ESP32_HAL_SPI_H_ + +#include "soc/soc_caps.h" +#if SOC_GPSPI_SUPPORTED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdkconfig.h" +#include +#include + +#define SPI_HAS_TRANSACTION +#ifdef CONFIG_IDF_TARGET_ESP32 +#define FSPI 1 //SPI 1 bus attached to the flash (can use the same data lines but different SS) +#define HSPI 2 //SPI 2 bus normally mapped to pins 12 - 15, but can be matrixed to any pins +#define VSPI 3 //SPI 3 bus normally attached to pins 5, 18, 19 and 23, but can be matrixed to any pins +#else +#define FSPI 0 // ESP32C2, C3, C5, C6, C61, H2, S2, S3, P4 - SPI 2 bus +#define HSPI 1 // ESP32S2, S3, P4 - SPI 3 bus +#endif + +// This defines are not representing the real Divider of the ESP32 +// the Defines match to an AVR Arduino on 16MHz for better compatibility +#define SPI_CLOCK_DIV2 0x00101001 //8 MHz +#define SPI_CLOCK_DIV4 0x00241001 //4 MHz +#define SPI_CLOCK_DIV8 0x004c1001 //2 MHz +#define SPI_CLOCK_DIV16 0x009c1001 //1 MHz +#define SPI_CLOCK_DIV32 0x013c1001 //500 KHz +#define SPI_CLOCK_DIV64 0x027c1001 //250 KHz +#define SPI_CLOCK_DIV128 0x04fc1001 //125 KHz + +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 + +#define SPI_SS0 0 +#define SPI_SS1 1 +#define SPI_SS2 2 +#define SPI_SS_MASK_ALL 0x7 + +#define SPI_LSBFIRST 0 +#define SPI_MSBFIRST 1 + +struct spi_struct_t; +typedef struct spi_struct_t spi_t; + +spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder); +void spiStopBus(spi_t *spi); + +//Attach/Detach Signal Pins +bool spiAttachSCK(spi_t *spi, int8_t sck); +bool spiAttachMISO(spi_t *spi, int8_t miso); +bool spiAttachMOSI(spi_t *spi, int8_t mosi); +bool spiDetachSCK(spi_t *spi); +bool spiDetachMISO(spi_t *spi); +bool spiDetachMOSI(spi_t *spi); + +//Attach/Detach SS pin to SPI_SSx signal +bool spiAttachSS(spi_t *spi, uint8_t ss_num, int8_t ss); +bool spiDetachSS(spi_t *spi); + +//Enable/Disable SPI_SSx pins +void spiEnableSSPins(spi_t *spi, uint8_t ss_mask); +void spiDisableSSPins(spi_t *spi, uint8_t ss_mask); + +//Enable/Disable hardware control of SPI_SSx pins +void spiSSEnable(spi_t *spi); +void spiSSDisable(spi_t *spi); + +//Activate enabled SPI_SSx pins +void spiSSSet(spi_t *spi); +//Deactivate enabled SPI_SSx pins +void spiSSClear(spi_t *spi); + +void spiWaitReady(spi_t *spi); +//invert hardware SS +void spiSSInvert(spi_t *spi, bool invert); + +uint32_t spiGetClockDiv(spi_t *spi); +uint8_t spiGetDataMode(spi_t *spi); +uint8_t spiGetBitOrder(spi_t *spi); + +/* + * Non transaction based lock methods (each locks and unlocks when called) + * */ +void spiSetClockDiv(spi_t *spi, uint32_t clockDiv); +void spiSetDataMode(spi_t *spi, uint8_t dataMode); +void spiSetBitOrder(spi_t *spi, uint8_t bitOrder); + +void spiWrite(spi_t *spi, const uint32_t *data, uint8_t len); +void spiWriteByte(spi_t *spi, uint8_t data); +void spiWriteWord(spi_t *spi, uint16_t data); +void spiWriteLong(spi_t *spi, uint32_t data); + +void spiTransfer(spi_t *spi, uint32_t *out, uint8_t len); +uint8_t spiTransferByte(spi_t *spi, uint8_t data); +uint16_t spiTransferWord(spi_t *spi, uint16_t data); +uint32_t spiTransferLong(spi_t *spi, uint32_t data); +void spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t size); +void spiTransferBits(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits); + +/* + * New (EXPERIMENTAL) Transaction lock based API (lock once until endTransaction) + * */ +void spiTransaction(spi_t *spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder); +void spiSimpleTransaction(spi_t *spi); +void spiEndTransaction(spi_t *spi); + +void spiWriteNL(spi_t *spi, const void *data_in, uint32_t len); +void spiWriteByteNL(spi_t *spi, uint8_t data); +void spiWriteShortNL(spi_t *spi, uint16_t data); +void spiWriteLongNL(spi_t *spi, uint32_t data); +void spiWritePixelsNL(spi_t *spi, const void *data_in, uint32_t len); + +#define spiTransferNL(spi, data, len) spiTransferBytesNL(spi, data, data, len) +uint8_t spiTransferByteNL(spi_t *spi, uint8_t data); +uint16_t spiTransferShortNL(spi_t *spi, uint16_t data); +uint32_t spiTransferLongNL(spi_t *spi, uint32_t data); +void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint32_t len); +void spiTransferBitsNL(spi_t *spi, uint32_t data_in, uint32_t *data_out, uint8_t bits); + +/* + * Helper functions to translate frequency to clock divider and back + * */ +uint32_t spiFrequencyToClockDiv(spi_t *spi, uint32_t freq); +uint32_t spiClockDivToFrequency(spi_t *spi, uint32_t clockDiv); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_GPSPI_SUPPORTED */ +#endif /* MAIN_ESP32_HAL_SPI_H_ */ diff --git a/cores/esp32/esp32-hal-time.c b/cores/esp32/esp32-hal-time.c new file mode 100644 index 0000000..e66a68f --- /dev/null +++ b/cores/esp32/esp32-hal-time.c @@ -0,0 +1,126 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal.h" +#include "lwip/apps/sntp.h" +//#include "tcpip_adapter.h" +#include "esp_netif.h" + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING +#include "lwip/priv/tcpip_priv.h" +#endif + +static void setTimeZone(long offset, int daylight) { + char cst[21] = {0}; + char cdt[21] = "DST"; + char tz[41] = {0}; + + if (offset % 3600) { + snprintf(cst, sizeof(cst), "UTC%ld:%02u:%02u", offset / 3600, abs((offset % 3600) / 60), abs(offset % 60)); + } else { + snprintf(cst, sizeof(cst), "UTC%ld", offset / 3600); + } + if (daylight != 3600) { + long tz_dst = offset - daylight; + if (tz_dst % 3600) { + snprintf(cdt, sizeof(cdt), "DST%ld:%02u:%02u", tz_dst / 3600, abs((tz_dst % 3600) / 60), abs(tz_dst % 60)); + } else { + snprintf(cdt, sizeof(cdt), "DST%ld", tz_dst / 3600); + } + } + snprintf(tz, sizeof(tz), "%s%s", cst, cdt); + setenv("TZ", tz, 1); + tzset(); +} + +/* + * configTime + * Source: https://github.com/esp8266/Arduino/blob/master/cores/esp8266/time.c + * */ +void configTime(long gmtOffset_sec, int daylightOffset_sec, const char *server1, const char *server2, const char *server3) { + //tcpip_adapter_init(); // Should not hurt anything if already inited + esp_netif_init(); + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING + if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { + LOCK_TCPIP_CORE(); + } +#endif + + if (sntp_enabled()) { + sntp_stop(); + } + + sntp_setoperatingmode(SNTP_OPMODE_POLL); + sntp_setservername(0, (char *)server1); + sntp_setservername(1, (char *)server2); + sntp_setservername(2, (char *)server3); + sntp_init(); + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING + if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { + UNLOCK_TCPIP_CORE(); + } +#endif + + setTimeZone(-gmtOffset_sec, daylightOffset_sec); +} + +/* + * configTzTime + * sntp setup using TZ environment variable + * */ +void configTzTime(const char *tz, const char *server1, const char *server2, const char *server3) { + //tcpip_adapter_init(); // Should not hurt anything if already inited + esp_netif_init(); + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING + if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { + LOCK_TCPIP_CORE(); + } +#endif + + if (sntp_enabled()) { + sntp_stop(); + } + + sntp_setoperatingmode(SNTP_OPMODE_POLL); + sntp_setservername(0, (char *)server1); + sntp_setservername(1, (char *)server2); + sntp_setservername(2, (char *)server3); + sntp_init(); + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING + if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { + UNLOCK_TCPIP_CORE(); + } +#endif + + setenv("TZ", tz, 1); + tzset(); +} + +bool getLocalTime(struct tm *info, uint32_t ms) { + uint32_t start = millis(); + time_t now; + while ((millis() - start) <= ms) { + time(&now); + localtime_r(&now, info); + if (info->tm_year > (2016 - 1900)) { + return true; + } + delay(10); + } + return false; +} diff --git a/cores/esp32/esp32-hal-timer.c b/cores/esp32/esp32-hal-timer.c new file mode 100644 index 0000000..85e0071 --- /dev/null +++ b/cores/esp32/esp32-hal-timer.c @@ -0,0 +1,285 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-timer.h" + +#if SOC_GPTIMER_SUPPORTED +#include "driver/gptimer.h" +#if defined __has_include && __has_include("clk_tree.h") +#include "clk_tree.h" +#else +#include "esp_clk_tree.h" +#endif + +#if CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM +#define TIMER_IRAM IRAM_ATTR +#else +#define TIMER_IRAM +#endif + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void *); + +typedef struct { + voidFuncPtr fn; + void *arg; +} interrupt_config_t; + +struct timer_struct_t { + gptimer_handle_t timer_handle; + interrupt_config_t interrupt_handle; + bool timer_started; +}; + +inline TIMER_IRAM uint64_t timerRead(hw_timer_t *timer) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return 0; + } + uint64_t value; + gptimer_get_raw_count(timer->timer_handle, &value); + return value; +} + +void TIMER_IRAM timerWrite(hw_timer_t *timer, uint64_t val) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return; + } + gptimer_set_raw_count(timer->timer_handle, val); +} + +void TIMER_IRAM timerAlarm(hw_timer_t *timer, uint64_t alarm_value, bool autoreload, uint64_t reload_count) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return; + } + esp_err_t err = ESP_OK; + gptimer_alarm_config_t alarm_cfg = { + .alarm_count = alarm_value, + .reload_count = reload_count, + .flags.auto_reload_on_alarm = autoreload, + }; + err = gptimer_set_alarm_action(timer->timer_handle, &alarm_cfg); + if (err != ESP_OK) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer Alarm Write failed, error num=%d", err); +#endif + } +} + +uint32_t timerGetFrequency(hw_timer_t *timer) { + if (timer == NULL) { + return 0; + } + uint32_t frequency; + gptimer_get_resolution(timer->timer_handle, &frequency); + return frequency; +} + +void TIMER_IRAM timerStart(hw_timer_t *timer) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return; + } + gptimer_start(timer->timer_handle); + timer->timer_started = true; +} + +void TIMER_IRAM timerStop(hw_timer_t *timer) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return; + } + gptimer_stop(timer->timer_handle); + timer->timer_started = false; +} + +void TIMER_IRAM timerRestart(hw_timer_t *timer) { + if (timer == NULL) { +#ifndef CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM + log_e("Timer handle is NULL"); +#endif + return; + } + gptimer_set_raw_count(timer->timer_handle, 0); +} + +hw_timer_t *timerBegin(uint32_t frequency) { + esp_err_t err = ESP_OK; + uint32_t counter_src_hz = 0; + uint32_t divider = 0; + soc_periph_gptimer_clk_src_t clk; + + soc_periph_gptimer_clk_src_t gptimer_clks[] = SOC_GPTIMER_CLKS; + for (size_t i = 0; i < sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + clk = gptimer_clks[i]; +#if defined __has_include && __has_include("clk_tree.h") + clk_tree_src_get_freq_hz(clk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz); +#else + esp_clk_tree_src_get_freq_hz(clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz); +#endif + divider = counter_src_hz / frequency; + if ((divider >= 2) && (divider <= 65536)) { + break; + } else { + divider = 0; + } + } + + if (divider == 0) { + log_e("Resolution cannot be reached with any clock source, aborting!"); + return NULL; + } + + gptimer_config_t config = { + .clk_src = clk, + .direction = GPTIMER_COUNT_UP, + .resolution_hz = frequency, + .flags.intr_shared = true, + }; + + hw_timer_t *timer = malloc(sizeof(hw_timer_t)); + + err = gptimer_new_timer(&config, &timer->timer_handle); + if (err != ESP_OK) { + log_e("Failed to create a new GPTimer, error num=%d", err); + free(timer); + return NULL; + } + gptimer_enable(timer->timer_handle); + gptimer_start(timer->timer_handle); + timer->timer_started = true; + return timer; +} + +void timerEnd(hw_timer_t *timer) { + if (timer != NULL) { + esp_err_t err = ESP_OK; + if (timer->timer_started == true) { + gptimer_stop(timer->timer_handle); + } + gptimer_disable(timer->timer_handle); + err = gptimer_del_timer(timer->timer_handle); + if (err != ESP_OK) { + log_e("Failed to destroy GPTimer, error num=%d", err); + return; + } + free(timer); + } +} + +bool IRAM_ATTR timerFnWrapper(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *args) { + interrupt_config_t *isr = (interrupt_config_t *)args; + if (isr->fn) { + if (isr->arg) { + ((voidFuncPtrArg)isr->fn)(isr->arg); + } else { + isr->fn(); + } + } + // some additional logic or handling may be required here to appropriately yield or not + return false; +} + +void timerAttachInterruptFunctionalArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg) { + if (timer == NULL) { + log_e("Timer handle is NULL"); + return; + } + esp_err_t err = ESP_OK; + gptimer_event_callbacks_t cbs = { + .on_alarm = timerFnWrapper, + }; + + timer->interrupt_handle.fn = (voidFuncPtr)userFunc; + timer->interrupt_handle.arg = arg; + + if (timer->timer_started == true) { + gptimer_stop(timer->timer_handle); + } + gptimer_disable(timer->timer_handle); + err = gptimer_register_event_callbacks(timer->timer_handle, &cbs, &timer->interrupt_handle); + if (err != ESP_OK) { + log_e("Timer Attach Interrupt failed, error num=%d", err); + } + gptimer_enable(timer->timer_handle); + if (timer->timer_started == true) { + gptimer_start(timer->timer_handle); + } +} + +void timerAttachInterruptArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg) { + timerAttachInterruptFunctionalArg(timer, userFunc, arg); +} + +void timerAttachInterrupt(hw_timer_t *timer, voidFuncPtr userFunc) { + timerAttachInterruptFunctionalArg(timer, (voidFuncPtrArg)userFunc, NULL); +} + +void timerDetachInterrupt(hw_timer_t *timer) { + if (timer == NULL) { + log_e("Timer handle is NULL"); + return; + } + esp_err_t err = ESP_OK; + err = gptimer_set_alarm_action(timer->timer_handle, NULL); + timer->interrupt_handle.fn = NULL; + timer->interrupt_handle.arg = NULL; + if (err != ESP_OK) { + log_e("Timer Detach Interrupt failed, error num=%d", err); + } +} + +uint64_t timerReadMicros(hw_timer_t *timer) { + if (timer == NULL) { + log_e("Timer handle is NULL"); + return 0; + } + uint64_t timer_val = timerRead(timer); + uint32_t frequency = timerGetFrequency(timer); + return timer_val * 1000000 / frequency; +} + +uint64_t timerReadMillis(hw_timer_t *timer) { + if (timer == NULL) { + log_e("Timer handle is NULL"); + return 0; + } + uint64_t timer_val = timerRead(timer); + uint32_t frequency = timerGetFrequency(timer); + return timer_val * 1000 / frequency; +} + +double timerReadSeconds(hw_timer_t *timer) { + if (timer == NULL) { + log_e("Timer handle is NULL"); + return 0; + } + uint64_t timer_val = timerRead(timer); + uint32_t frequency = timerGetFrequency(timer); + return (double)timer_val / frequency; +} + +#endif /* SOC_GPTIMER_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-timer.h b/cores/esp32/esp32-hal-timer.h new file mode 100644 index 0000000..59b88c9 --- /dev/null +++ b/cores/esp32/esp32-hal-timer.h @@ -0,0 +1,60 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_GPTIMER_SUPPORTED + +#include "esp32-hal.h" +#include "driver/gptimer_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct timer_struct_t; +typedef struct timer_struct_t hw_timer_t; + +hw_timer_t *timerBegin(uint32_t frequency); +void timerEnd(hw_timer_t *timer); + +void timerStart(hw_timer_t *timer); +void timerStop(hw_timer_t *timer); +void timerRestart(hw_timer_t *timer); +void timerWrite(hw_timer_t *timer, uint64_t val); + +uint64_t timerRead(hw_timer_t *timer); +uint64_t timerReadMicros(hw_timer_t *timer); +uint64_t timerReadMillis(hw_timer_t *timer); +double timerReadSeconds(hw_timer_t *timer); + +uint32_t timerGetFrequency(hw_timer_t *timer); + +void timerAttachInterrupt(hw_timer_t *timer, void (*userFunc)(void)); +void timerAttachInterruptArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg); +void timerDetachInterrupt(hw_timer_t *timer); + +void timerAlarm(hw_timer_t *timer, uint64_t alarm_value, bool autoreload, uint64_t reload_count); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_GPTIMER_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-tinyusb.c b/cores/esp32/esp32-hal-tinyusb.c new file mode 100644 index 0000000..ed1ff2a --- /dev/null +++ b/cores/esp32/esp32-hal-tinyusb.c @@ -0,0 +1,931 @@ +#include "soc/soc_caps.h" + +#if SOC_USB_OTG_SUPPORTED +#include "sdkconfig.h" +#if CONFIG_TINYUSB_ENABLED +#include +#include + +#include "esp_log.h" + +#include "soc/soc.h" +#include "soc/efuse_reg.h" +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#include "soc/rtc_cntl_reg.h" +#include "soc/usb_struct.h" +#include "soc/usb_reg.h" +#include "soc/usb_wrap_reg.h" +#include "soc/usb_wrap_struct.h" +#include "soc/usb_periph.h" +#endif + +#include "soc/periph_defs.h" +#include "soc/timer_group_struct.h" +#include "soc/system_reg.h" + +#include "rom/gpio.h" + +#include "hal/gpio_ll.h" +#include "hal/clk_gate_ll.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "driver/gpio.h" + +#include "esp_rom_gpio.h" + +#include "esp32-hal.h" +#include "esp32-hal-periman.h" +#include "esp32-hal-tinyusb.h" + +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/usb/usb_persist.h" +#include "esp32s2/rom/usb/usb_dc.h" +#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#if defined __has_include && __has_include("hal/usb_phy_ll.h") +#include "hal/usb_phy_ll.h" +#elif defined __has_include && __has_include("hal/usb_fsls_phy_ll.h") +#include "hal/usb_fsls_phy_ll.h" +#endif +#include "hal/usb_serial_jtag_ll.h" +#include "esp32s3/rom/usb/usb_persist.h" +#include "esp32s3/rom/usb/usb_dc.h" +#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h" +#elif CONFIG_IDF_TARGET_ESP32P4 +#endif + +typedef enum { + TINYUSB_USBDEV_0, +} tinyusb_usbdev_t; + +typedef char *tusb_desc_strarray_device_t[USB_STRING_DESCRIPTOR_ARRAY_SIZE]; + +typedef struct { + bool external_phy; +} tinyusb_config_t; + +#if __has_include("hal/usb_hal.h") + +#include "hal/usb_hal.h" + +static bool usb_otg_deinit(void *busptr) { + // Once USB OTG is initialized, its GPIOs are assigned and it shall never be deinited + // except when S3 swithicng usb from cdc to jtag while resetting to bootrom +#if CONFIG_IDF_TARGET_ESP32S3 + return true; +#else + return false; +#endif +} + +static void configure_pins(usb_hal_context_t *usb) { + for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { + if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { + esp_rom_gpio_pad_select_gpio(iopin->pin); + if (iopin->is_output) { + esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false); + } else { + esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false); + if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) { + gpio_ll_input_enable(&GPIO, iopin->pin); + } + } + esp_rom_gpio_pad_unhold(iopin->pin); + } + } + if (!usb->use_external_phy) { + gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + if (perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DM, usb_otg_deinit) && perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DP, usb_otg_deinit)) { + // Bus Pointer is not used anyway - once the USB GPIOs are assigned, they can't be detached + perimanSetPinBus(USBPHY_DM_NUM, ESP32_BUS_TYPE_USB_DM, (void *)usb, -1, -1); + perimanSetPinBus(USBPHY_DP_NUM, ESP32_BUS_TYPE_USB_DP, (void *)usb, -1, -1); + } else { + log_e("USB OTG Pins can't be set into Peripheral Manager."); + } + } +} + +esp_err_t init_usb_hal(bool external_phy) { + usb_hal_context_t hal = {.use_external_phy = external_phy}; + usb_hal_init(&hal); + configure_pins(&hal); + return ESP_OK; +} + +esp_err_t deinit_usb_hal() { + return ESP_OK; +} + +#elif __has_include("esp_private/usb_phy.h") + +#include "esp_private/usb_phy.h" + +static usb_phy_handle_t phy_handle = NULL; + +esp_err_t init_usb_hal(bool external_phy) { + esp_err_t ret = ESP_OK; + usb_phy_config_t phy_config = { + .controller = USB_PHY_CTRL_OTG, + .target = USB_PHY_TARGET_INT, + .otg_mode = USB_OTG_MODE_DEVICE, +#if CONFIG_IDF_TARGET_ESP32P4 + .otg_speed = USB_PHY_SPEED_HIGH, +#else + .otg_speed = USB_PHY_SPEED_FULL, +#endif + .ext_io_conf = NULL, + .otg_io_conf = NULL, + }; + + ret = usb_new_phy(&phy_config, &phy_handle); + if (ret != ESP_OK) { + log_e("Failed to init USB PHY"); + } + return ret; +} + +esp_err_t deinit_usb_hal() { + esp_err_t ret = ESP_OK; + if (phy_handle) { + ret = usb_del_phy(phy_handle); + if (ret != ESP_OK) { + log_e("Failed to deinit USB PHY"); + } + } + return ret; +} + +#else + +#error No way to initialize USP PHY + +void init_usb_hal(bool external_phy) { + return ESP_OK; +} + +void deinit_usb_hal() { + return ESP_OK; +} +#endif + +esp_err_t tinyusb_driver_install(const tinyusb_config_t *config) { + init_usb_hal(config->external_phy); + tusb_rhport_init_t tinit; + memset(&tinit, 0, sizeof(tusb_rhport_init_t)); + tinit.role = TUSB_ROLE_DEVICE; +#if CONFIG_IDF_TARGET_ESP32P4 + tinit.speed = TUSB_SPEED_HIGH; + if (!tusb_init(1, &tinit)) { +#else + tinit.speed = TUSB_SPEED_FULL; + if (!tusb_init(0, &tinit)) { +#endif + log_e("Can't initialize the TinyUSB stack."); + return ESP_FAIL; + } + return ESP_OK; +} + +typedef char tusb_str_t[127]; + +static bool WEBUSB_ENABLED = false; + +static tusb_str_t WEBUSB_URL = ""; +static tusb_str_t USB_DEVICE_PRODUCT = ""; +static tusb_str_t USB_DEVICE_MANUFACTURER = ""; +static tusb_str_t USB_DEVICE_SERIAL = ""; +static tusb_str_t USB_DEVICE_LANGUAGE = "\x09\x04"; //English (0x0409) + +static uint8_t USB_DEVICE_ATTRIBUTES = 0; +static uint16_t USB_DEVICE_POWER = 0; + +/* + * Device Descriptor + * */ +static tusb_desc_device_t tinyusb_device_descriptor = { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0, + .bDeviceClass = 0, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE, + + .idVendor = 0, + .idProduct = 0, + .bcdDevice = 0, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +/* + * String Descriptors + * */ +#define MAX_STRING_DESCRIPTORS 20 +static uint32_t tinyusb_string_descriptor_len = 4; +static char *tinyusb_string_descriptor[MAX_STRING_DESCRIPTORS] = { + // array of pointer to string descriptors + USB_DEVICE_LANGUAGE, // 0: is supported language + USB_DEVICE_MANUFACTURER, // 1: Manufacturer + USB_DEVICE_PRODUCT, // 2: Product + USB_DEVICE_SERIAL, // 3: Serials, should use chip ID +}; + +/* Microsoft OS 2.0 registry property descriptor +Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx +device should create DeviceInterfaceGUIDs. It can be done by driver and +in case of real PnP solution device should expose MS "Microsoft OS 2.0 +registry property descriptor". Such descriptor can insert any record +into Windows registry per device/configuration/interface. In our case it +will insert "DeviceInterfaceGUIDs" multistring property. + +GUID is freshly generated and should be OK to use. + +https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ +(Section Microsoft OS compatibility descriptors) + */ + +#define MS_OS_20_DESC_LEN 0xB2 + +static uint8_t const tinyusb_ms_os_20_descriptor[] = { + // Set header: length, type, windows version, total length + U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN), + + // Configuration subset header: length, type, configuration index, reserved, configuration total length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_CONFIGURATION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A), + + // Function Subset header: length, type, first interface, reserved, subset length + U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_FUNCTION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08), + + // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID + U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, // sub-compatible + + // MS OS 2.0 Registry property descriptor: length, type + U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08 - 0x08 - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), U16_TO_U8S_LE(0x0007), + U16_TO_U8S_LE(0x002A), // wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16 + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', + 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00, + U16_TO_U8S_LE(0x0050), // wPropertyDataLength + //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. + '{', 0x00, '9', 0x00, '7', 0x00, '5', 0x00, 'F', 0x00, '4', 0x00, '4', 0x00, 'D', 0x00, '9', 0x00, '-', 0x00, '0', 0x00, 'D', 0x00, '0', 0x00, '8', 0x00, '-', + 0x00, '4', 0x00, '3', 0x00, 'F', 0x00, 'D', 0x00, '-', 0x00, '8', 0x00, 'B', 0x00, '3', 0x00, 'E', 0x00, '-', 0x00, '1', 0x00, '2', 0x00, '7', 0x00, 'C', + 0x00, 'A', 0x00, '8', 0x00, 'A', 0x00, 'F', 0x00, 'F', 0x00, 'F', 0x00, '9', 0x00, 'D', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +TU_VERIFY_STATIC(sizeof(tinyusb_ms_os_20_descriptor) == MS_OS_20_DESC_LEN, "Incorrect size"); + +/* + * BOS Descriptor (required for webUSB) + * */ +#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_WEBUSB_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) + +enum { + VENDOR_REQUEST_WEBUSB = 1, + VENDOR_REQUEST_MICROSOFT = 2 +}; + +static uint8_t const tinyusb_bos_descriptor[] = {// total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 2), + + // Vendor Code, iLandingPage + TUD_BOS_WEBUSB_DESCRIPTOR(VENDOR_REQUEST_WEBUSB, 1), + + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, VENDOR_REQUEST_MICROSOFT) +}; + +/* + * URL Descriptor (required for webUSB) + * */ +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char url[127]; +} tinyusb_desc_webusb_url_t; + +static tinyusb_desc_webusb_url_t tinyusb_url_descriptor = { + .bLength = 3, + .bDescriptorType = 3, // WEBUSB URL type + .bScheme = 255, // URL Scheme Prefix: 0: "http://", 1: "https://", 255: "" + .url = "" +}; + +/* + * Configuration Descriptor + * */ + +static tinyusb_descriptor_cb_t tinyusb_loaded_interfaces_callbacks[USB_INTERFACE_MAX]; +static uint32_t tinyusb_loaded_interfaces_mask = 0; +static uint8_t tinyusb_loaded_interfaces_num = 0; +static uint16_t tinyusb_config_descriptor_len = 0; +static uint8_t *tinyusb_config_descriptor = NULL; + +/* + * Endpoint Usage Tracking + * */ +typedef union { + struct { + uint32_t in : 16; + uint32_t out : 16; + }; + uint32_t val; +} tinyusb_endpoints_usage_t; + +static tinyusb_endpoints_usage_t tinyusb_endpoints; + +/* + * TinyUSB Callbacks + * */ + +/** + * @brief Invoked when received GET CONFIGURATION DESCRIPTOR. + */ +__attribute__((weak)) uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + //log_d("%u", index); + return tinyusb_config_descriptor; +} + +/** + * @brief Invoked when received GET DEVICE DESCRIPTOR. + */ +__attribute__((weak)) uint8_t const *tud_descriptor_device_cb(void) { + //log_d(""); + return (uint8_t const *)&tinyusb_device_descriptor; +} + +/** + * @brief Invoked when received GET STRING DESCRIPTOR request. + */ +__attribute__((weak)) uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + //log_d("%u (0x%x)", index, langid); + static uint16_t _desc_str[127]; + uint8_t chr_count; + + if (index == 0) { + memcpy(&_desc_str[1], tinyusb_string_descriptor[0], 2); + chr_count = 1; + } else { + // Convert ASCII string into UTF-16 + if (index >= tinyusb_string_descriptor_len) { + return NULL; + } + const char *str = tinyusb_string_descriptor[index]; + // Cap at max char + chr_count = strlen(str); + if (chr_count > 126) { + chr_count = 126; + } + for (uint8_t i = 0; i < chr_count; i++) { + _desc_str[1 + i] = str[i]; + } + } + + // first byte is len, second byte is string type + _desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * chr_count + 2); + + return _desc_str; +} + +/** + * @brief Invoked when received GET BOS DESCRIPTOR request. + */ +uint8_t const *tud_descriptor_bos_cb(void) { + //log_v(""); + return tinyusb_bos_descriptor; +} + +__attribute__((weak)) bool tinyusb_vendor_control_request_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + return false; +} + +/** + * @brief Handle WebUSB and Vendor requests. + */ +bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + if (WEBUSB_ENABLED && (request->bRequest == VENDOR_REQUEST_WEBUSB || (request->bRequest == VENDOR_REQUEST_MICROSOFT && request->wIndex == 7))) { + // we only care for SETUP stage + if (stage == CONTROL_STAGE_SETUP) { + if (request->bRequest == VENDOR_REQUEST_WEBUSB) { + // match vendor request in BOS descriptor + // Get landing page url + tinyusb_url_descriptor.bLength = 3 + strlen(WEBUSB_URL); + snprintf(tinyusb_url_descriptor.url, 127, "%s", WEBUSB_URL); + return tud_control_xfer(rhport, request, (void *)&tinyusb_url_descriptor, tinyusb_url_descriptor.bLength); + } + // Get Microsoft OS 2.0 compatible descriptor + uint16_t total_len; + memcpy(&total_len, tinyusb_ms_os_20_descriptor + 8, 2); + return tud_control_xfer(rhport, request, (void *)tinyusb_ms_os_20_descriptor, total_len); + } + return true; + } + log_v("rhport: %u, stage: %u, type: 0x%x, request: 0x%x", rhport, stage, request->bmRequestType_bit.type, request->bRequest); + return tinyusb_vendor_control_request_cb(rhport, stage, request); +} + +/* + * Required Callbacks + * */ +#if CFG_TUD_DFU +__attribute__((weak)) uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) { + return 0; +} +__attribute__((weak)) void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const *data, uint16_t length) {} +__attribute__((weak)) void tud_dfu_manifest_cb(uint8_t alt) {} +#endif +#if CFG_TUD_HID +__attribute__((weak)) const uint8_t *tud_hid_descriptor_report_cb(uint8_t itf) { + return NULL; +} +__attribute__((weak)) uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) { + return 0; +} +__attribute__((weak)) void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, const uint8_t *buffer, uint16_t bufsize) {} +#endif +#if CFG_TUD_MSC +__attribute__((weak)) bool tud_msc_test_unit_ready_cb(uint8_t lun) { + return false; +} +__attribute__((weak)) void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) {} +__attribute__((weak)) void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) {} +__attribute__((weak)) int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) { + return -1; +} +__attribute__((weak)) int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) { + return -1; +} +__attribute__((weak)) int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) { + return -1; +} +#endif +#if CFG_TUD_NCM +__attribute__((weak)) bool tud_network_recv_cb(const uint8_t *src, uint16_t size) { + return false; +} +__attribute__((weak)) uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) { + return 0; +} +__attribute__((weak)) void tud_network_init_cb(void) {} +#endif + +#if CFG_TUH_HID +__attribute__((weak)) void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t idx, uint8_t const *report_desc, uint16_t desc_len) {} +__attribute__((weak)) void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t idx) {} +__attribute__((weak)) void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t idx, uint8_t const *report, uint16_t len) {} +__attribute__((weak)) void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t idx, uint8_t const *report, uint16_t len) {} +__attribute__((weak)) void tuh_hid_get_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len) {} +__attribute__((weak)) void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len) {} +__attribute__((weak)) void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t protocol) {} +#endif +#if CFG_TUH_CDC +__attribute__((weak)) void tuh_cdc_mount_cb(uint8_t idx) {} +__attribute__((weak)) void tuh_cdc_umount_cb(uint8_t idx) {} +__attribute__((weak)) void tuh_cdc_rx_cb(uint8_t idx) {} +__attribute__((weak)) void tuh_cdc_tx_complete_cb(uint8_t idx) {} +#endif +#if CFG_TUH_MSC +__attribute__((weak)) void tuh_msc_mount_cb(uint8_t dev_addr) {} +__attribute__((weak)) void tuh_msc_umount_cb(uint8_t dev_addr) {} +#endif +/* + * Private API + * */ +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +static bool usb_persist_enabled = false; +static restart_type_t usb_persist_mode = RESTART_NO_PERSIST; +#endif + +#if CONFIG_IDF_TARGET_ESP32S3 + +static void hw_cdc_reset_handler(void *arg) { + portBASE_TYPE xTaskWoken = 0; + uint32_t usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask(); + usb_serial_jtag_ll_clr_intsts_mask(usbjtag_intr_status); + + if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_BUS_RESET) { + xSemaphoreGiveFromISR((SemaphoreHandle_t)arg, &xTaskWoken); + } + + if (xTaskWoken == pdTRUE) { + portYIELD_FROM_ISR(); + } +} + +static void usb_switch_to_cdc_jtag() { + // Disable USB-OTG + deinit_usb_hal(); + periph_ll_reset(PERIPH_USB_MODULE); + //periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE); + periph_ll_disable_clk_set_rst(PERIPH_USB_MODULE); + + // Switch to hardware CDC+JTAG + CLEAR_PERI_REG_MASK(RTC_CNTL_USB_CONF_REG, (RTC_CNTL_SW_HW_USB_PHY_SEL | RTC_CNTL_SW_USB_PHY_SEL | RTC_CNTL_USB_PAD_ENABLE)); + + // Do not use external PHY + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PHY_SEL); + + // Release GPIO pins from CDC+JTAG + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + + // Force the host to re-enumerate (BUS_RESET) + pinMode(USBPHY_DM_NUM, OUTPUT_OPEN_DRAIN); + pinMode(USBPHY_DP_NUM, OUTPUT_OPEN_DRAIN); + digitalWrite(USBPHY_DM_NUM, LOW); + digitalWrite(USBPHY_DP_NUM, LOW); + +// Initialize CDC+JTAG ISR to listen for BUS_RESET +#if defined __has_include && __has_include("hal/usb_phy_ll.h") + usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG); +#elif defined __has_include && __has_include("hal/usb_fsls_phy_ll.h") + usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG); +#else + // usb_serial_jtag_ll_phy_set_defaults(); + const usb_serial_jtag_pull_override_vals_t pull_conf = {.dp_pu = 1, .dm_pu = 0, .dp_pd = 0, .dm_pd = 0}; + usb_serial_jtag_ll_phy_enable_pull_override(&pull_conf); + usb_serial_jtag_ll_phy_disable_pull_override(); +#endif + usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_BUS_RESET); + intr_handle_t intr_handle = NULL; + SemaphoreHandle_t reset_sem = xSemaphoreCreateBinary(); + if (reset_sem) { + if (esp_intr_alloc(ETS_USB_SERIAL_JTAG_INTR_SOURCE, 0, hw_cdc_reset_handler, reset_sem, &intr_handle) != ESP_OK) { + vSemaphoreDelete(reset_sem); + reset_sem = NULL; + log_e("HW USB CDC failed to init interrupts"); + } + } else { + log_e("reset_sem init failed"); + } + + // Connect GPIOs to integrated CDC+JTAG + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + + // Wait for BUS_RESET to give us back the semaphore + if (reset_sem) { + if (xSemaphoreTake(reset_sem, 1000 / portTICK_PERIOD_MS) != pdPASS) { + log_e("reset_sem timeout"); + } + usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK); + esp_intr_free(intr_handle); + vSemaphoreDelete(reset_sem); + } +} +#endif + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +static void IRAM_ATTR usb_persist_shutdown_handler(void) { + if (usb_persist_mode != RESTART_NO_PERSIST) { + if (usb_persist_enabled) { + usb_dc_prepare_persist(); + } + if (usb_persist_mode == RESTART_BOOTLOADER) { + //USB CDC Download + if (usb_persist_enabled) { + chip_usb_set_persist_flags(USBDC_PERSIST_ENA); +#if CONFIG_IDF_TARGET_ESP32S2 + } else { + periph_ll_reset(PERIPH_USB_MODULE); + periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE); +#endif + } + REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT); + } else if (usb_persist_mode == RESTART_BOOTLOADER_DFU) { + //DFU Download +#if CONFIG_IDF_TARGET_ESP32S2 + // Reset USB Core + USB0.grstctl |= USB_CSFTRST; + while ((USB0.grstctl & USB_CSFTRST) == USB_CSFTRST) {} +#endif + chip_usb_set_persist_flags(USBDC_BOOT_DFU); + REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT); + } else if (usb_persist_enabled) { + //USB Persist reboot + chip_usb_set_persist_flags(USBDC_PERSIST_ENA); + } + } +} +#endif + +void usb_persist_restart(restart_type_t mode) { +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + if (mode < RESTART_TYPE_MAX && esp_register_shutdown_handler(usb_persist_shutdown_handler) == ESP_OK) { + usb_persist_mode = mode; +#if CONFIG_IDF_TARGET_ESP32S3 + if (mode == RESTART_BOOTLOADER) { + usb_switch_to_cdc_jtag(); + } +#endif + esp_restart(); + } +#endif +} + +static bool tinyusb_reserve_in_endpoint(uint8_t endpoint) { + if (endpoint > CFG_TUD_NUM_EPS || (tinyusb_endpoints.in & BIT(endpoint)) != 0) { + return false; + } + tinyusb_endpoints.in |= BIT(endpoint); + return true; +} + +static bool tinyusb_reserve_out_endpoint(uint8_t endpoint) { + if (endpoint > CFG_TUD_NUM_EPS || (tinyusb_endpoints.out & BIT(endpoint)) != 0) { + return false; + } + tinyusb_endpoints.out |= BIT(endpoint); + return true; +} + +static bool tinyusb_has_available_fifos(void) { + uint8_t max_endpoints = CFG_TUD_NUM_IN_EPS - 1, active_endpoints = 0; +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + if (tinyusb_loaded_interfaces_mask & BIT(USB_INTERFACE_CDC)) { + max_endpoints = CFG_TUD_NUM_IN_EPS; //CDC endpoint 0x85 is actually not linked to FIFO and not used + } +#endif + for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) { + if ((tinyusb_endpoints.in & BIT(i)) != 0) { + active_endpoints++; + } + } + + return active_endpoints < max_endpoints; +} + +static uint16_t tinyusb_load_descriptor(tinyusb_interface_t interface, uint8_t *dst, uint8_t *itf) { + if (tinyusb_loaded_interfaces_callbacks[interface]) { + return tinyusb_loaded_interfaces_callbacks[interface](dst, itf); + } + return 0; +} + +static bool tinyusb_load_enabled_interfaces() { + tinyusb_config_descriptor_len += TUD_CONFIG_DESC_LEN; + tinyusb_config_descriptor = (uint8_t *)malloc(tinyusb_config_descriptor_len); + if (tinyusb_config_descriptor == NULL) { + log_e("Descriptor Malloc Failed"); + return false; + } + uint8_t *dst = tinyusb_config_descriptor + TUD_CONFIG_DESC_LEN; + + for (int i = 0; i < USB_INTERFACE_MAX; i++) { + if (tinyusb_loaded_interfaces_mask & (1U << i)) { + uint16_t len = tinyusb_load_descriptor((tinyusb_interface_t)i, dst, &tinyusb_loaded_interfaces_num); + if (!len) { + log_e("Descriptor Load Failed"); + return false; + } else { + dst += len; + } + } + } + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB Device"); + uint8_t descriptor[TUD_CONFIG_DESC_LEN] = { + //num configs, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, tinyusb_loaded_interfaces_num, str_index, tinyusb_config_descriptor_len, USB_DEVICE_ATTRIBUTES, USB_DEVICE_POWER) + }; + memcpy(tinyusb_config_descriptor, descriptor, TUD_CONFIG_DESC_LEN); + if ((tinyusb_loaded_interfaces_mask == (BIT(USB_INTERFACE_CDC) | BIT(USB_INTERFACE_DFU))) || (tinyusb_loaded_interfaces_mask == BIT(USB_INTERFACE_CDC))) { + //usb_persist_enabled = true; + //log_d("USB Persist enabled"); + } + log_d("Load Done: if_num: %u, descr_len: %u, if_mask: 0x%x", tinyusb_loaded_interfaces_num, tinyusb_config_descriptor_len, tinyusb_loaded_interfaces_mask); + return true; +} + +static inline char nibble_to_hex_char(uint8_t b) { + if (b < 0xa) { + return '0' + b; + } else { + return 'a' + b - 0xa; + } +} + +static void set_usb_serial_num(void) { + /* Get the MAC address */ +#if CONFIG_IDF_TARGET_ESP32P4 + const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SYS_0_REG, EFUSE_MAC_0); + const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SYS_0_REG, EFUSE_MAC_1); +#else + const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_MAC_0); + const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_1_REG, EFUSE_MAC_1); +#endif + uint8_t mac_bytes[6]; + memcpy(mac_bytes, &mac0, 4); + memcpy(mac_bytes + 4, &mac1, 2); + + /* Convert to UTF16 string */ + uint8_t *srl = (uint8_t *)USB_DEVICE_SERIAL; + for (int i = 0; i < 6; ++i) { + uint8_t b = mac_bytes[5 - i]; /* printing from the MSB */ + if (i) { + *srl++ = ':'; + } + *srl++ = nibble_to_hex_char(b >> 4); + *srl++ = nibble_to_hex_char(b & 0xf); + } + *srl++ = '\0'; +} + +static void tinyusb_apply_device_config(tinyusb_device_config_t *config) { + if (config->product_name) { + snprintf(USB_DEVICE_PRODUCT, 126, "%s", config->product_name); + } + + if (config->manufacturer_name) { + snprintf(USB_DEVICE_MANUFACTURER, 126, "%s", config->manufacturer_name); + } + + if (config->serial_number && config->serial_number[0]) { + snprintf(USB_DEVICE_SERIAL, 126, "%s", config->serial_number); + } else { + set_usb_serial_num(); + } + + if (config->webusb_url) { + snprintf(WEBUSB_URL, 126, "%s", config->webusb_url); + } + + // Windows 10 will not recognize the CDC device if WebUSB is enabled and USB Class is not 2 (CDC) + if ((tinyusb_loaded_interfaces_mask & BIT(USB_INTERFACE_CDC)) && config->webusb_enabled && (config->usb_class != TUSB_CLASS_CDC)) { + config->usb_class = TUSB_CLASS_CDC; + config->usb_protocol = 0x00; + } + + WEBUSB_ENABLED = config->webusb_enabled; + USB_DEVICE_ATTRIBUTES = config->usb_attributes; + USB_DEVICE_POWER = config->usb_power_ma; + + tinyusb_device_descriptor.bcdUSB = config->usb_version; + tinyusb_device_descriptor.idVendor = config->vid; + tinyusb_device_descriptor.idProduct = config->pid; + tinyusb_device_descriptor.bcdDevice = config->fw_version; + tinyusb_device_descriptor.bDeviceClass = config->usb_class; + tinyusb_device_descriptor.bDeviceSubClass = config->usb_subclass; + tinyusb_device_descriptor.bDeviceProtocol = config->usb_protocol; +} + +// USB Device Driver task +// This top level thread processes all usb events and invokes callbacks +static void usb_device_task(void *param) { + (void)param; + while (1) { + tud_task(); // RTOS forever loop + } +} + +/* + * PUBLIC API + * */ +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR +const char *tinyusb_interface_names[USB_INTERFACE_MAX] = {"MSC", "DFU", "HID", "VENDOR", "CDC", "CDC2", "MIDI", "CUSTOM"}; +#endif +static bool tinyusb_is_initialized = false; + +esp_err_t tinyusb_enable_interface(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb) { + return tinyusb_enable_interface2(interface, descriptor_len, cb, false); +} + +esp_err_t tinyusb_enable_interface2(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb, bool reserve_endpoints) { + if (tinyusb_is_initialized) { + log_e("TinyUSB has already started! Interface %s not enabled", (interface >= USB_INTERFACE_MAX) ? "" : tinyusb_interface_names[interface]); + return ESP_FAIL; + } + if ((interface >= USB_INTERFACE_MAX) || (tinyusb_loaded_interfaces_mask & (1U << interface))) { + log_e("Interface %s invalid or already enabled", (interface >= USB_INTERFACE_MAX) ? "" : tinyusb_interface_names[interface]); + return ESP_FAIL; + } + if (interface == USB_INTERFACE_HID && reserve_endpoints) { + // Some simple PC BIOS requires specific endpoint addresses for keyboard at boot + if (!tinyusb_reserve_out_endpoint(1) || !tinyusb_reserve_in_endpoint(1)) { + log_e("HID Reserve Endpoints Failed"); + return ESP_FAIL; + } + } + if (interface == USB_INTERFACE_CDC) { + if (!tinyusb_reserve_out_endpoint(3) || !tinyusb_reserve_in_endpoint(4) || !tinyusb_reserve_in_endpoint(5)) { + log_e("CDC Reserve Endpoints Failed"); + return ESP_FAIL; + } + } + tinyusb_loaded_interfaces_mask |= (1U << interface); + tinyusb_config_descriptor_len += descriptor_len; + tinyusb_loaded_interfaces_callbacks[interface] = cb; + log_d("Interface %s enabled", tinyusb_interface_names[interface]); + return ESP_OK; +} + +esp_err_t tinyusb_init(tinyusb_device_config_t *config) { + if (tinyusb_is_initialized) { + return ESP_OK; + } + tinyusb_is_initialized = true; + + //tinyusb_endpoints.val = 0; + tinyusb_apply_device_config(config); + if (!tinyusb_load_enabled_interfaces()) { + tinyusb_is_initialized = false; + return ESP_FAIL; + } + +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + bool usb_did_persist = (USB_WRAP.date.val == USBDC_PERSIST_ENA); + + //if(usb_did_persist && usb_persist_enabled){ + // Enable USB/IO_MUX peripheral reset, if coming from persistent reboot + REG_CLR_BIT(RTC_CNTL_USB_CONF_REG, RTC_CNTL_IO_MUX_RESET_DISABLE); + REG_CLR_BIT(RTC_CNTL_USB_CONF_REG, RTC_CNTL_USB_RESET_DISABLE); + //} else + if (!usb_did_persist || !usb_persist_enabled) { + // Reset USB module + periph_ll_reset(PERIPH_USB_MODULE); + periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE); + } +#endif + + tinyusb_config_t tusb_cfg = { + .external_phy = false // In the most cases you need to use a `false` value + }; + esp_err_t err = tinyusb_driver_install(&tusb_cfg); + if (err != ESP_OK) { + tinyusb_is_initialized = false; + return err; + } + xTaskCreate(usb_device_task, "usbd", 4096, NULL, configMAX_PRIORITIES - 1, NULL); + return err; +} + +uint8_t tinyusb_add_string_descriptor(const char *str) { + if (str == NULL || tinyusb_string_descriptor_len >= MAX_STRING_DESCRIPTORS) { + return 0; + } + uint8_t index = tinyusb_string_descriptor_len; + tinyusb_string_descriptor[tinyusb_string_descriptor_len++] = (char *)str; + return index; +} + +uint8_t tinyusb_get_free_duplex_endpoint(void) { + if (!tinyusb_has_available_fifos()) { + log_e("No available IN endpoints"); + return 0; + } + for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) { + if ((tinyusb_endpoints.in & BIT(i)) == 0 && (tinyusb_endpoints.out & BIT(i)) == 0) { + tinyusb_endpoints.in |= BIT(i); + tinyusb_endpoints.out |= BIT(i); + return i; + } + } + log_e("No available duplex endpoints"); + return 0; +} + +uint8_t tinyusb_get_free_in_endpoint(void) { + if (!tinyusb_has_available_fifos()) { + log_e("No available IN endpoints"); + return 0; + } + for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) { + if ((tinyusb_endpoints.in & BIT(i)) == 0 && (tinyusb_endpoints.out & BIT(i)) != 0) { + tinyusb_endpoints.in |= BIT(i); + return i; + } + } + for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) { + if ((tinyusb_endpoints.in & BIT(i)) == 0) { + tinyusb_endpoints.in |= BIT(i); + return i; + } + } + return 0; +} + +uint8_t tinyusb_get_free_out_endpoint(void) { + for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) { + if ((tinyusb_endpoints.out & BIT(i)) == 0 && (tinyusb_endpoints.in & BIT(i)) != 0) { + tinyusb_endpoints.out |= BIT(i); + return i; + } + } + for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) { + if ((tinyusb_endpoints.out & BIT(i)) == 0) { + tinyusb_endpoints.out |= BIT(i); + return i; + } + } + return 0; +} + +#endif /* CONFIG_TINYUSB_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-tinyusb.h b/cores/esp32/esp32-hal-tinyusb.h new file mode 100644 index 0000000..73210c4 --- /dev/null +++ b/cores/esp32/esp32-hal-tinyusb.h @@ -0,0 +1,118 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "esp32-hal.h" + +#if CONFIG_TINYUSB_ENABLED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tusb.h" +#include "tusb_option.h" +#include "tusb_config.h" + +#define USB_ESPRESSIF_VID 0x303A +#define USB_STRING_DESCRIPTOR_ARRAY_SIZE 10 + +#ifndef CFG_TUD_ENDOINT_SIZE +#if CONFIG_IDF_TARGET_ESP32P4 +#define CFG_TUD_ENDOINT_SIZE 512 +#else +#define CFG_TUD_ENDOINT_SIZE 64 +#endif +#endif +#if CONFIG_IDF_TARGET_ESP32P4 +#define CFG_TUD_NUM_EPS 15 +#define CFG_TUD_NUM_IN_EPS 8 +#else +#define CFG_TUD_NUM_EPS 6 +#define CFG_TUD_NUM_IN_EPS 5 +#endif + +typedef struct { + uint16_t vid; + uint16_t pid; + const char *product_name; + const char *manufacturer_name; + const char *serial_number; + uint16_t fw_version; + + uint16_t usb_version; + uint8_t usb_class; + uint8_t usb_subclass; + uint8_t usb_protocol; + uint8_t usb_attributes; + uint16_t usb_power_ma; + + bool webusb_enabled; + const char *webusb_url; +} tinyusb_device_config_t; + +#define TINYUSB_CONFIG_DEFAULT() \ + { \ + .vid = USB_ESPRESSIF_VID, .pid = 0x0002, .product_name = CONFIG_TINYUSB_DESC_PRODUCT_STRING, .manufacturer_name = CONFIG_TINYUSB_DESC_MANUFACTURER_STRING, \ + .serial_number = CONFIG_TINYUSB_DESC_SERIAL_STRING, .fw_version = CONFIG_TINYUSB_DESC_BCDDEVICE, .usb_version = 0x0200, .usb_class = TUSB_CLASS_MISC, \ + .usb_subclass = MISC_SUBCLASS_COMMON, .usb_protocol = MISC_PROTOCOL_IAD, .usb_attributes = TUSB_DESC_CONFIG_ATT_SELF_POWERED, .usb_power_ma = 500, \ + .webusb_enabled = false, .webusb_url = "espressif.github.io/arduino-esp32/webusb.html" \ + } + +esp_err_t tinyusb_init(tinyusb_device_config_t *config); + +/* + * USB Persistence API + * */ +typedef enum { + RESTART_NO_PERSIST, + RESTART_PERSIST, + RESTART_BOOTLOADER, + RESTART_BOOTLOADER_DFU, + RESTART_TYPE_MAX +} restart_type_t; + +void usb_persist_restart(restart_type_t mode); + +// The following definitions and functions are to be used only by the drivers +typedef enum { + USB_INTERFACE_MSC, + USB_INTERFACE_DFU, + USB_INTERFACE_HID, + USB_INTERFACE_VENDOR, + USB_INTERFACE_CDC, + USB_INTERFACE_CDC2, + USB_INTERFACE_MIDI, + USB_INTERFACE_CUSTOM, + USB_INTERFACE_MAX +} tinyusb_interface_t; + +typedef uint16_t (*tinyusb_descriptor_cb_t)(uint8_t *dst, uint8_t *itf); + +esp_err_t tinyusb_enable_interface(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb); +esp_err_t tinyusb_enable_interface2(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb, bool reserve_endpoints); +uint8_t tinyusb_add_string_descriptor(const char *str); +uint8_t tinyusb_get_free_duplex_endpoint(void); +uint8_t tinyusb_get_free_in_endpoint(void); +uint8_t tinyusb_get_free_out_endpoint(void); + +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_TINYUSB_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-touch-ng.c b/cores/esp32/esp32-hal-touch-ng.c new file mode 100644 index 0000000..a28ee49 --- /dev/null +++ b/cores/esp32/esp32-hal-touch-ng.c @@ -0,0 +1,560 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "soc/soc_caps.h" +#include "esp_idf_version.h" + +#if SOC_TOUCH_SENSOR_SUPPORTED +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) || SOC_TOUCH_SENSOR_VERSION == 3 + +#include "esp32-hal-touch-ng.h" +#include "esp32-hal-periman.h" + +/* + Internal Private Touch Data Structure and Functions +*/ + +typedef void (*voidFuncPtr)(void); +typedef void (*voidArgFuncPtr)(void *); + +typedef struct { + voidFuncPtr fn; + bool callWithArgs; + void *arg; + bool lastStatusIsPressed; +} TouchInterruptHandle_t; + +static TouchInterruptHandle_t __touchInterruptHandlers[SOC_TOUCH_SENSOR_NUM] = { + 0, +}; +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +static uint8_t _sample_num = 1; // only one sample configuration supported +static float _duration_ms = 5.0f; +static touch_volt_lim_l_t _volt_low = TOUCH_VOLT_LIM_L_0V5; +static touch_volt_lim_h_t _volt_high = TOUCH_VOLT_LIM_H_1V7; +static touch_intr_trig_mode_t _intr_trig_mode = TOUCH_INTR_TRIG_ON_BELOW_THRESH; +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 +static uint8_t _sample_num = 1; // only one sample configuration supported +static uint32_t _chg_times = 500; +static touch_volt_lim_l_t _volt_low = TOUCH_VOLT_LIM_L_0V5; +static touch_volt_lim_h_t _volt_high = TOUCH_VOLT_LIM_H_2V2; +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32P4 +static uint8_t _sample_num = 1; // TODO: can be extended to multiple samples +static uint32_t _div_num = 1; +static uint8_t _coarse_freq_tune = 1; +static uint8_t _fine_freq_tune = 1; +#endif + +static uint8_t used_pads = 0; + +static uint32_t __touchSleepTime = 256; +static float __touchMeasureTime = 32.0f; + +static touch_sensor_config_t sensor_config; + +static bool initialized = false; +static bool enabled = false; +static bool running = false; +static bool channels_initialized[SOC_TOUCH_SENSOR_NUM] = {false}; + +static touch_sensor_handle_t touch_sensor_handle = NULL; +static touch_channel_handle_t touch_channel_handle[SOC_TOUCH_SENSOR_NUM] = {}; + +// Active threshold to benchmark ratio. (i.e., touch will be activated when data >= benchmark * (1 + ratio)) +static float s_thresh2bm_ratio = 0.015f; // 1.5% for all channels + +static bool ARDUINO_ISR_ATTR __touchOnActiveISR(touch_sensor_handle_t sens_handle, const touch_active_event_data_t *event, void *user_ctx) { + uint8_t pad_num = (uint8_t)event->chan_id; + __touchInterruptHandlers[pad_num].lastStatusIsPressed = true; + if (__touchInterruptHandlers[pad_num].fn) { + // keeping backward compatibility with "void cb(void)" and with new "void cb(void *)" + if (__touchInterruptHandlers[pad_num].callWithArgs) { + ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg); + } else { + __touchInterruptHandlers[pad_num].fn(); + } + } + return false; +} + +static bool ARDUINO_ISR_ATTR __touchOnInactiveISR(touch_sensor_handle_t sens_handle, const touch_inactive_event_data_t *event, void *user_ctx) { + uint8_t pad_num = (uint8_t)event->chan_id; + __touchInterruptHandlers[pad_num].lastStatusIsPressed = false; + if (__touchInterruptHandlers[pad_num].fn) { + // keeping backward compatibility with "void cb(void)" and with new "void cb(void *)" + if (__touchInterruptHandlers[pad_num].callWithArgs) { + ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg); + } else { + __touchInterruptHandlers[pad_num].fn(); + } + } + return false; +} + +bool touchStop() { + if (!running) { // Already stopped + return true; + } + if (touch_sensor_stop_continuous_scanning(touch_sensor_handle) != ESP_OK) { + log_e("Touch sensor stop scanning failed!"); + return false; + } + running = false; + return true; +} + +bool touchDisable() { + if (!enabled) { // Already disabled + return true; + } + if (running) { + log_e("Touch sensor still running!"); + return false; + } + if (touch_sensor_disable(touch_sensor_handle) != ESP_OK) { + log_e("Touch sensor disable failed!"); + return false; + } + enabled = false; + return true; +} + +bool touchStart() { + if (running) { // Already running + return true; + } + if (!enabled) { + log_e("Touch sensor not enabled!"); + return false; + } + if (touch_sensor_start_continuous_scanning(touch_sensor_handle) != ESP_OK) { + log_e("Touch sensor failed to start continuous scanning!"); + return false; + } + running = true; + return true; +} + +bool touchEnable() { + if (enabled) { // Already enabled + return true; + } + if (touch_sensor_enable(touch_sensor_handle) != ESP_OK) { + log_e("Touch sensor enable failed!"); + return false; + } + enabled = true; + return true; +} + +bool touchBenchmarkThreshold(uint8_t pad) { + if (!touchEnable()) { + return false; + } + + /* Scan the enabled touch channels for several times, to make sure the initial channel data is stable */ + for (int i = 0; i < 3; i++) { + if (touch_sensor_trigger_oneshot_scanning(touch_sensor_handle, 2000) != ESP_OK) { + log_e("Touch sensor trigger oneshot scanning failed!"); + return false; + } + } + + /* Disable the touch channel to rollback the state */ + if (!touchDisable()) { + return false; + } + + // Reconfigure passed pad with new threshold + uint32_t benchmark[_sample_num] = {}; +#if SOC_TOUCH_SUPPORT_BENCHMARK // ESP32S2, ESP32S3,ESP32P4 + if (touch_channel_read_data(touch_channel_handle[pad], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark) != ESP_OK) { + log_e("Touch channel read data failed!"); + return false; + } +#else + if (touch_channel_read_data(touch_channel_handle[pad], TOUCH_CHAN_DATA_TYPE_SMOOTH, benchmark) != ESP_OK) { + log_e("Touch channel read data failed!"); + return false; + } +#endif + + /* Calculate the proper active thresholds regarding the initial benchmark */ + touch_channel_config_t chan_cfg = TOUCH_CHANNEL_DEFAULT_CONFIG(); + for (int i = 0; i < _sample_num; i++) { +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + chan_cfg.abs_active_thresh[i] = (uint32_t)(benchmark[i] * (1 - s_thresh2bm_ratio)); + log_v("Configured [CH %d] sample %d: benchmark = %" PRIu32 ", threshold = %" PRIu32 "\t", pad, i, benchmark[i], chan_cfg.abs_active_thresh[i]); +#else + chan_cfg.active_thresh[i] = (uint32_t)(benchmark[i] * s_thresh2bm_ratio); + log_v("Configured [CH %d] sample %d: benchmark = %" PRIu32 ", threshold = %" PRIu32 "\t", pad, i, benchmark[i], chan_cfg.active_thresh[i]); +#endif + } + /* Update the channel configuration */ + if (touch_sensor_reconfig_channel(touch_channel_handle[pad], &chan_cfg) != ESP_OK) { + log_e("Touch sensor threshold reconfig channel failed!"); + return false; + } + return true; +} + +static bool touchDetachBus(void *pin) { + int8_t pad = digitalPinToTouchChannel((int)(pin - 1)); + channels_initialized[pad] = false; + //disable touch pad and delete the channel + if (!touchStop()) { + log_e("touchStop() failed!"); + return false; + } + if (!touchDisable()) { + log_e("touchDisable() failed!"); + return false; + } + touch_sensor_del_channel(touch_channel_handle[pad]); + used_pads--; + if (used_pads == 0) { + if (touch_sensor_del_controller(touch_sensor_handle) != ESP_OK) //deinit touch module, as no pads are used + { + log_e("Touch module deinit failed!"); + return false; + } + initialized = false; + } else { + touchEnable(); + touchStart(); + } + return true; +} + +static void __touchInit() { + if (initialized) { + return; + } + // Support only one sample configuration for now +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + touch_sensor_sample_config_t single_sample_cfg = TOUCH_SENSOR_V1_DEFAULT_SAMPLE_CONFIG(_duration_ms, _volt_low, _volt_high); +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + touch_sensor_sample_config_t single_sample_cfg = TOUCH_SENSOR_V2_DEFAULT_SAMPLE_CONFIG(_chg_times, _volt_low, _volt_high); +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32P4 + touch_sensor_sample_config_t single_sample_cfg = TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(_div_num, _coarse_freq_tune, _fine_freq_tune); +#endif + touch_sensor_sample_config_t sample_cfg[_sample_num] = {}; + sample_cfg[0] = single_sample_cfg; + + touch_sensor_config_t sens_cfg = { +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + .power_on_wait_us = __touchSleepTime, + .meas_interval_us = __touchMeasureTime, + .intr_trig_mode = _intr_trig_mode, + .intr_trig_group = TOUCH_INTR_TRIG_GROUP_BOTH, + .sample_cfg_num = _sample_num, + .sample_cfg = sample_cfg, +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + .power_on_wait_us = __touchSleepTime, + .meas_interval_us = __touchMeasureTime, + .max_meas_time_us = 0, + .sample_cfg_num = _sample_num, + .sample_cfg = sample_cfg, +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32P4 + .power_on_wait_us = __touchSleepTime, + .meas_interval_us = __touchMeasureTime, + .max_meas_time_us = 0, + .output_mode = TOUCH_PAD_OUT_AS_CLOCK, + .sample_cfg_num = _sample_num, + .sample_cfg = sample_cfg, +#endif + }; + + if (touch_sensor_new_controller(&sens_cfg, &touch_sensor_handle) != ESP_OK) { + goto err; + } + + sensor_config = sens_cfg; + /* Configure the touch sensor filter */ + touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG(); + if (touch_sensor_config_filter(touch_sensor_handle, &filter_cfg) != ESP_OK) { + goto err; + } + + /* Register the touch sensor on_active and on_inactive callbacks */ + touch_event_callbacks_t callbacks = {0}; + callbacks.on_active = __touchOnActiveISR; + callbacks.on_inactive = __touchOnInactiveISR; + + if (touch_sensor_register_callbacks(touch_sensor_handle, &callbacks, NULL) != ESP_OK) { + goto err; + } + + initialized = true; + return; +err: + log_e(" Touch sensor initialization error."); + initialized = false; + return; +} + +static void __touchChannelInit(int pad) { + if (channels_initialized[pad]) { + return; + } + + // Initial setup with default Threshold + __touchInterruptHandlers[pad].fn = NULL; + + touch_channel_config_t chan_cfg = TOUCH_CHANNEL_DEFAULT_CONFIG(); + + if (!touchStop() || !touchDisable()) { + log_e("Touch sensor stop and disable failed!"); + return; + } + + if (touch_sensor_new_channel(touch_sensor_handle, pad, &chan_cfg, &touch_channel_handle[pad]) != ESP_OK) { + log_e("Touch sensor new channel failed!"); + return; + } + + // Benchmark active threshold and reconfigure pad + if (!touchBenchmarkThreshold(pad)) { + log_e("Touch sensor benchmark threshold failed!"); + return; + } + + channels_initialized[pad] = true; + used_pads++; + + if (!touchEnable() || !touchStart()) { + log_e("Touch sensor enable and start failed!"); + } +} + +static touch_value_t __touchRead(uint8_t pin) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return 0; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus); + if (!perimanClearPinBus(pin)) { + return 0; + } + __touchInit(); + __touchChannelInit(pad); + + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) { + touchDetachBus((void *)(pin + 1)); + return 0; + } + } + + uint32_t touch_read[_sample_num] = {}; + touch_channel_read_data(touch_channel_handle[pad], TOUCH_CHAN_DATA_TYPE_SMOOTH, touch_read); + touch_value_t touch_value = touch_read[0]; // only one sample configuration for now + + return touch_value; +} + +static void __touchConfigInterrupt(uint8_t pin, void (*userFunc)(void), void *Args, bool callWithArgs, touch_value_t threshold) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return; + } + + if (userFunc == NULL) { + // detach ISR User Call + __touchInterruptHandlers[pad].fn = NULL; + __touchInterruptHandlers[pad].callWithArgs = false; + __touchInterruptHandlers[pad].arg = NULL; + } else { + // attach ISR User Call + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus); + if (!perimanClearPinBus(pin)) { + log_e("Failed to clear pin bus"); + return; + } + __touchInit(); + __touchChannelInit(pad); + + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) { + touchDetachBus((void *)(pin + 1)); + log_e("Failed to set bus to Peripheral manager"); + return; + } + } + __touchInterruptHandlers[pad].fn = userFunc; + __touchInterruptHandlers[pad].callWithArgs = callWithArgs; + __touchInterruptHandlers[pad].arg = Args; + } + + if (threshold != 0) { + if (!touchStop() || !touchDisable()) { + log_e("Touch sensor stop and disable failed!"); + return; + } + + touch_channel_config_t chan_cfg = TOUCH_CHANNEL_DEFAULT_CONFIG(); + for (int i = 0; i < _sample_num; i++) { +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + chan_cfg.abs_active_thresh[i] = threshold; +#else + chan_cfg.active_thresh[i] = threshold; +#endif + } + + if (touch_sensor_reconfig_channel(touch_channel_handle[pad], &chan_cfg) != ESP_OK) { + log_e("Touch sensor threshold reconfig channel failed!"); + } + + if (!touchEnable() || !touchStart()) { + log_e("Touch sensor enable and start failed!"); + } + } +} + +// it keeps backwards compatibility +static void __touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold) { + __touchConfigInterrupt(pin, userFunc, NULL, false, threshold); +} + +// new additional version of the API with User Args +static void __touchAttachArgsInterrupt(uint8_t pin, void (*userFunc)(void), void *args, touch_value_t threshold) { + __touchConfigInterrupt(pin, userFunc, args, true, threshold); +} + +// new additional API to detach touch ISR +static void __touchDettachInterrupt(uint8_t pin) { + __touchConfigInterrupt(pin, NULL, NULL, false, 0); // userFunc as NULL acts as detaching +} + +// /* +// External Public Touch API Functions +// */ + +bool touchInterruptGetLastStatus(uint8_t pin) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return false; + } + return __touchInterruptHandlers[pad].lastStatusIsPressed; +} + +void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus); + __touchInit(); + __touchChannelInit(pad); + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) { + log_e("Failed to set bus to Peripheral manager"); + touchDetachBus((void *)(pin + 1)); + return; + } + } + + log_v("Touch sensor deep sleep wake-up configuration for pad %d with threshold %d", pad, threshold); + if (!touchStop() || !touchDisable()) { + log_e("Touch sensor stop and disable failed!"); + return; + } + + touch_sleep_config_t deep_slp_cfg = { + .slp_wakeup_lvl = TOUCH_DEEP_SLEEP_WAKEUP, +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + .deep_slp_sens_cfg = NULL, // Use the original touch sensor configuration +#else // SOC_TOUCH_SENSOR_VERSION 2 and 3// ESP32S2, ESP32S3, ESP32P4 + .deep_slp_chan = touch_channel_handle[pad], + .deep_slp_thresh = {threshold}, + .deep_slp_sens_cfg = NULL, // Use the original touch sensor configuration +#endif + }; + + // Register the deep sleep wake-up + if (touch_sensor_config_sleep_wakeup(touch_sensor_handle, &deep_slp_cfg) != ESP_OK) { + log_e("Touch sensor deep sleep wake-up failed!"); + return; + } + + if (!touchEnable() || !touchStart()) { + log_e("Touch sensor enable and start failed!"); + } +} + +void touchSetDefaultThreshold(float percentage) { + s_thresh2bm_ratio = (float)percentage / 100.0f; +} + +void touchSetTiming(float measure, uint32_t sleep) { + if (initialized) { + log_e("Touch sensor already initialized. Cannot set cycles."); + return; + } + __touchSleepTime = sleep; + __touchMeasureTime = measure; +} + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +void touchSetConfig(float duration_ms, touch_volt_lim_l_t volt_low, touch_volt_lim_h_t volt_high) { + if (initialized) { + log_e("Touch sensor already initialized. Cannot set configuration."); + return; + } + _duration_ms = duration_ms; + _volt_low = volt_low; + _volt_high = volt_high; +} + +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 +void touchSetConfig(uint32_t chg_times, touch_volt_lim_l_t volt_low, touch_volt_lim_h_t volt_high) { + if (initialized) { + log_e("Touch sensor already initialized. Cannot set configuration."); + return; + } + _chg_times = chg_times; + _volt_low = volt_low; + _volt_high = volt_high; +} + +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32P4 +void touchSetConfig(uint32_t div_num, uint8_t coarse_freq_tune, uint8_t fine_freq_tune) { + if (initialized) { + log_e("Touch sensor already initialized. Cannot set configuration."); + return; + } + _div_num = div_num; + _coarse_freq_tune = coarse_freq_tune; + _fine_freq_tune = fine_freq_tune; +} +#endif + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +void touchInterruptSetThresholdDirection(bool mustbeLower) { + if (mustbeLower) { + _intr_trig_mode = TOUCH_INTR_TRIG_ON_BELOW_THRESH; + } else { + _intr_trig_mode = TOUCH_INTR_TRIG_ON_ABOVE_THRESH; + } +} +#endif + +extern touch_value_t touchRead(uint8_t) __attribute__((weak, alias("__touchRead"))); +extern void touchAttachInterrupt(uint8_t, voidFuncPtr, touch_value_t) __attribute__((weak, alias("__touchAttachInterrupt"))); +extern void touchAttachInterruptArg(uint8_t, voidArgFuncPtr, void *, touch_value_t) __attribute__((weak, alias("__touchAttachArgsInterrupt"))); +extern void touchDetachInterrupt(uint8_t) __attribute__((weak, alias("__touchDettachInterrupt"))); + +#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) || SOC_TOUCH_SENSOR_VERSION == 3 */ +#endif /* SOC_TOUCH_SENSOR_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-touch-ng.h b/cores/esp32/esp32-hal-touch-ng.h new file mode 100644 index 0000000..ebe4946 --- /dev/null +++ b/cores/esp32/esp32-hal-touch-ng.h @@ -0,0 +1,136 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_TOUCH_NEW_H_ +#define MAIN_ESP32_HAL_TOUCH_NEW_H_ + +#include "soc/soc_caps.h" +#include "esp_idf_version.h" + +#if SOC_TOUCH_SENSOR_SUPPORTED +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) || SOC_TOUCH_SENSOR_VERSION == 3 + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" +#include "driver/touch_sens.h" + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +#define TOUCH_CHANNEL_DEFAULT_CONFIG() \ + { \ + .abs_active_thresh = {1000}, .charge_speed = TOUCH_CHARGE_SPEED_7, .init_charge_volt = TOUCH_INIT_CHARGE_VOLT_DEFAULT, \ + .group = TOUCH_CHAN_TRIG_GROUP_BOTH, \ + } +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32-S2 & ESP32-S3 +#define TOUCH_CHANNEL_DEFAULT_CONFIG() \ + { .active_thresh = {2000}, .charge_speed = TOUCH_CHARGE_SPEED_7, .init_charge_volt = TOUCH_INIT_CHARGE_VOLT_DEFAULT, } +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32-P4 +#define TOUCH_CHANNEL_DEFAULT_CONFIG() \ + { .active_thresh = {1000}, } +#endif + +typedef uint32_t touch_value_t; + +/* + * Set time in us that measurement operation takes + * The result from touchRead, threshold and detection + * accuracy depend on these values. + * Note: must be called before setting up touch pads + **/ +void touchSetTiming(float measure, uint32_t sleep); + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +/* + * @param[in] duration_ms The measurement duration of the touch channel + * @param[in] volt_low The low voltage limit of the touch channel + * @param[in] volt_high The high voltage limit of the touch channel + */ +void touchSetConfig(float duration_ms, touch_volt_lim_l_t volt_low, touch_volt_lim_h_t volt_high); + +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 +/* + * @param[in] chg_times The charge times of the touch channel + * @param[in] volt_low The low voltage limit of the touch channel + * @param[in] volt_high The high voltage limit of the touch channel + */ +void touchSetConfig(uint32_t chg_times, touch_volt_lim_l_t volt_low, touch_volt_lim_h_t volt_high); + +#elif SOC_TOUCH_SENSOR_VERSION == 3 // ESP32P4 +/* + * Tune the touch pad frequency. + * Note: Must be called before setting up touch pads +*/ +void touchSetConfig(uint32_t _div_num, uint8_t coarse_freq_tune, uint8_t fine_freq_tune); +#endif + +#if SOC_TOUCH_SENSOR_VERSION == 1 +/* + * Specific functions to ESP32 + * Tells the driver if it shall activate the ISR if the sensor is Lower or Higher than the Threshold + * Default if Lower. + * Note: Must be called before setting up touch pads + **/ +void touchInterruptSetThresholdDirection(bool mustbeLower); +#endif + +/* + * Read touch pad value. + * You can use this method to chose a good threshold value + * to use as value for touchAttachInterrupt. + * */ +touch_value_t touchRead(uint8_t pin); + +/* + * Set function to be called if touch pad value rises by given increment (threshold). + * Use touchRead to determine a proper threshold between touched and untouched state. + * */ +void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold); +void touchAttachInterruptArg(uint8_t pin, void (*userFunc)(void *), void *arg, touch_value_t threshold); +void touchDetachInterrupt(uint8_t pin); + +/* + * Returns true when the latest ISR status for the Touchpad is that it is touched (Active) + * and false when the Touchpad is untoouched (Inactive). + * This function can be used in conjunction with ISR User callback in order to take action + * as soon as the touchpad is touched and/or released. + **/ +bool touchInterruptGetLastStatus(uint8_t pin); + +/* + * Set the default threshold for touch pads. + * The threshold is a percentage of the benchmark value. + * The default value is 1.5%. + **/ +void touchSetDefaultThreshold(float percentage); + +/* + * Setup touch pad wake up from deep sleep /light sleep with given threshold. + * When light sleep is used, all used touch pads will be able to wake up the chip. + **/ +void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold); + +#ifdef __cplusplus +} +#endif + +#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0) || SOC_TOUCH_SENSOR_VERSION == 3 */ +#endif /* SOC_TOUCH_SENSOR_SUPPORTED */ +#endif /* MAIN_ESP32_HAL_TOUCH_H_ */ diff --git a/cores/esp32/esp32-hal-touch.c b/cores/esp32/esp32-hal-touch.c new file mode 100644 index 0000000..e27064d --- /dev/null +++ b/cores/esp32/esp32-hal-touch.c @@ -0,0 +1,327 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "soc/soc_caps.h" +#include "esp_idf_version.h" + +#if SOC_TOUCH_SENSOR_SUPPORTED +#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) && SOC_TOUCH_SENSOR_VERSION <= 2 // ESP32, ESP32S2, ESP32S3 + +#include "driver/touch_sensor.h" +#include "esp32-hal-touch.h" +#include "esp32-hal-periman.h" + +/* + Internal Private Touch Data Structure and Functions +*/ + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +static uint16_t __touchSleepCycles = 0x1000; +static uint16_t __touchMeasureCycles = 0x1000; +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 +static uint16_t __touchSleepCycles = TOUCH_PAD_SLEEP_CYCLE_DEFAULT; +static uint16_t __touchMeasureCycles = TOUCH_PAD_MEASURE_CYCLE_DEFAULT; +#endif + +typedef void (*voidFuncPtr)(void); +typedef void (*voidArgFuncPtr)(void *); + +typedef struct { + voidFuncPtr fn; + bool callWithArgs; + void *arg; +#if SOC_TOUCH_SENSOR_VERSION == 2 // Only for ESP32S2 and ESP32S3 + bool lastStatusIsPressed; +#endif +} TouchInterruptHandle_t; + +static TouchInterruptHandle_t __touchInterruptHandlers[SOC_TOUCH_SENSOR_NUM] = { + 0, +}; + +static uint8_t used_pads = 0; +static bool initialized = false; +static bool channels_initialized[SOC_TOUCH_SENSOR_NUM] = {false}; + +static void ARDUINO_ISR_ATTR __touchISR(void *arg) { +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + uint32_t pad_intr = touch_pad_get_status(); + //clear interrupt + touch_pad_clear_status(); + // call Pad ISR User callback + for (int i = 0; i < SOC_TOUCH_SENSOR_NUM; i++) { + if ((pad_intr >> i) & 0x01) { + if (__touchInterruptHandlers[i].fn) { + // keeping backward compatibility with "void cb(void)" and with new "void cb(vooid *)" + if (__touchInterruptHandlers[i].callWithArgs) { + ((voidArgFuncPtr)__touchInterruptHandlers[i].fn)(__touchInterruptHandlers[i].arg); + } else { + __touchInterruptHandlers[i].fn(); + } + } + } + } +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + touch_pad_intr_mask_t evt = touch_pad_read_intr_status_mask(); + uint8_t pad_num = touch_pad_get_current_meas_channel(); + if (evt & TOUCH_PAD_INTR_MASK_ACTIVE) { + // touch has been pressed / touched + __touchInterruptHandlers[pad_num].lastStatusIsPressed = true; + } + if (evt & TOUCH_PAD_INTR_MASK_INACTIVE) { + // touch has been released / untouched + __touchInterruptHandlers[pad_num].lastStatusIsPressed = false; + } + if (__touchInterruptHandlers[pad_num].fn) { + // keeping backward compatibility with "void cb(void)" and with new "void cb(vooid *)" + if (__touchInterruptHandlers[pad_num].callWithArgs) { + ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg); + } else { + __touchInterruptHandlers[pad_num].fn(); + } + } +#endif +} + +static void __touchSetCycles(uint16_t measure, uint16_t sleep) { + __touchSleepCycles = sleep; + __touchMeasureCycles = measure; +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + touch_pad_set_measurement_clock_cycles(measure); +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + touch_pad_set_charge_discharge_times(measure); +#endif + touch_pad_set_measurement_interval(sleep); +} + +static bool touchDetachBus(void *pin) { + int8_t pad = digitalPinToTouchChannel((int)(pin - 1)); + channels_initialized[pad] = false; + used_pads--; + if (used_pads == 0) { + if (touch_pad_deinit() != ESP_OK) //deinit touch module, as no pads are used + { + log_e("Touch module deinit failed!"); + return false; + } + initialized = false; + } + return true; +} + +static void __touchInit() { + if (initialized) { + return; + } + + esp_err_t err = ESP_OK; + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + err = touch_pad_init(); + if (err != ESP_OK) { + goto err; + } + // the next two lines will drive the touch reading values -- both will return ESP_OK + touch_pad_set_voltage(TOUCH_HVOLT_2V7, TOUCH_LVOLT_0V5, TOUCH_HVOLT_ATTEN_0V); + touch_pad_set_measurement_clock_cycles(__touchMeasureCycles); + touch_pad_set_measurement_interval(__touchSleepCycles); + // Touch Sensor Timer initiated + touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER); // returns ESP_OK + err = touch_pad_filter_start(10); + if (err != ESP_OK) { + goto err; + } + // keep ISR activated - it can run all together (ISR + touchRead()) + err = touch_pad_isr_register(__touchISR, NULL); + if (err != ESP_OK) { + goto err; + } + touch_pad_intr_enable(); // returns ESP_OK +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + err = touch_pad_init(); + if (err != ESP_OK) { + goto err; + } + // the next lines will drive the touch reading values -- all os them return ESP_OK + touch_pad_set_charge_discharge_times(__touchMeasureCycles); + touch_pad_set_measurement_interval(__touchSleepCycles); + touch_pad_set_voltage(TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD, TOUCH_PAD_LOW_VOLTAGE_THRESHOLD, TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD); + touch_pad_set_idle_channel_connect(TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT); + touch_pad_denoise_t denoise = { + .grade = TOUCH_PAD_DENOISE_BIT4, + .cap_level = TOUCH_PAD_DENOISE_CAP_L4, + }; + touch_pad_denoise_set_config(&denoise); + touch_pad_denoise_enable(); + // Touch Sensor Timer initiated + touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER); // returns ESP_OK + touch_pad_fsm_start(); // returns ESP_OK + //ISR setup moved to __touchChannelInit +#endif + initialized = true; + return; +err: + log_e(" Touch sensor initialization error."); + initialized = false; + return; +} + +static void __touchChannelInit(int pad) { + if (channels_initialized[pad]) { + return; + } + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 + // Initial no Threshold and setup + __touchInterruptHandlers[pad].fn = NULL; + touch_pad_config(pad, TOUCH_PAD_THRESHOLD_MAX); // returns ESP_OK +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2, ESP32S3 + // Initial no Threshold and setup + __touchInterruptHandlers[pad].fn = NULL; + touch_pad_config(pad); // returns ESP_OK + // keep ISR activated - it can run all together (ISR + touchRead()) + esp_err_t err = touch_pad_isr_register(__touchISR, NULL, TOUCH_PAD_INTR_MASK_ACTIVE | TOUCH_PAD_INTR_MASK_INACTIVE); + if (err != ESP_OK) { + log_e(" Touch sensor initialization error."); + return; + } + touch_pad_intr_enable(TOUCH_PAD_INTR_MASK_ACTIVE | TOUCH_PAD_INTR_MASK_INACTIVE); // returns ESP_OK +#endif + + channels_initialized[pad] = true; + used_pads++; + delay(20); //delay needed before reading from touch channel after config +} + +static touch_value_t __touchRead(uint8_t pin) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return 0; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus); + if (!perimanClearPinBus(pin)) { + return 0; + } + __touchInit(); + __touchChannelInit(pad); + + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) { + touchDetachBus((void *)(pin + 1)); + return 0; + } + } + + touch_value_t touch_value; + touch_pad_read_raw_data(pad, &touch_value); + + return touch_value; +} + +static void __touchConfigInterrupt(uint8_t pin, void (*userFunc)(void), void *Args, touch_value_t threshold, bool callWithArgs) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return; + } + + if (userFunc == NULL) { + // detach ISR User Call + __touchInterruptHandlers[pad].fn = NULL; + threshold = TOUCH_PAD_THRESHOLD_MAX; // deactivate the ISR with SOC_TOUCH_PAD_THRESHOLD_MAX + } else { + // attach ISR User Call + __touchInit(); + __touchChannelInit(pad); + __touchInterruptHandlers[pad].fn = userFunc; + __touchInterruptHandlers[pad].callWithArgs = callWithArgs; + __touchInterruptHandlers[pad].arg = Args; + } + + touch_pad_set_thresh(pad, threshold); +} + +// it keeps backwards compatibility +static void __touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold) { + __touchConfigInterrupt(pin, userFunc, NULL, threshold, false); +} + +// new additional version of the API with User Args +static void __touchAttachArgsInterrupt(uint8_t pin, void (*userFunc)(void), void *args, touch_value_t threshold) { + __touchConfigInterrupt(pin, userFunc, args, threshold, true); +} + +// new additional API to detach touch ISR +static void __touchDettachInterrupt(uint8_t pin) { + __touchConfigInterrupt(pin, NULL, NULL, 0, false); // userFunc as NULL acts as detaching +} + +/* + External Public Touch API Functions +*/ + +#if SOC_TOUCH_SENSOR_VERSION == 1 // Only for ESP32 SoC +void touchInterruptSetThresholdDirection(bool mustbeLower) { + if (mustbeLower) { + touch_pad_set_trigger_mode(TOUCH_TRIGGER_BELOW); + } else { + touch_pad_set_trigger_mode(TOUCH_TRIGGER_ABOVE); + } +} +#elif SOC_TOUCH_SENSOR_VERSION == 2 // Only for ESP32S2 and ESP32S3 +// returns true if touch pad has been and continues pressed and false otherwise +bool touchInterruptGetLastStatus(uint8_t pin) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return false; + } + + return __touchInterruptHandlers[pad].lastStatusIsPressed; +} +#endif + +void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold) { + int8_t pad = digitalPinToTouchChannel(pin); + if (pad < 0) { + return; + } + + if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus); + __touchInit(); + __touchChannelInit(pad); + if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) { + log_e("Failed to set bus to Peripheral manager"); + touchDetachBus((void *)(pin + 1)); + return; + } + } +#if SOC_TOUCH_SENSOR_VERSION == 1 // Only for ESP32 SoC + touch_pad_set_thresh(pad, threshold); + +#elif SOC_TOUCH_SENSOR_VERSION == 2 + touch_pad_sleep_channel_enable(pad, true); + touch_pad_sleep_set_threshold(pad, threshold); + +#endif + esp_sleep_enable_touchpad_wakeup(); +} + +extern touch_value_t touchRead(uint8_t) __attribute__((weak, alias("__touchRead"))); +extern void touchAttachInterrupt(uint8_t, voidFuncPtr, touch_value_t) __attribute__((weak, alias("__touchAttachInterrupt"))); +extern void touchAttachInterruptArg(uint8_t, voidArgFuncPtr, void *, touch_value_t) __attribute__((weak, alias("__touchAttachArgsInterrupt"))); +extern void touchDetachInterrupt(uint8_t) __attribute__((weak, alias("__touchDettachInterrupt"))); +extern void touchSetCycles(uint16_t, uint16_t) __attribute__((weak, alias("__touchSetCycles"))); + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) && SOC_TOUCH_SENSOR_VERSION <= 2 */ +#endif /* SOC_TOUCH_SENSOR_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-touch.h b/cores/esp32/esp32-hal-touch.h new file mode 100644 index 0000000..44c99dc --- /dev/null +++ b/cores/esp32/esp32-hal-touch.h @@ -0,0 +1,105 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_ESP32_HAL_TOUCH_H_ +#define MAIN_ESP32_HAL_TOUCH_H_ + +#include "soc/soc_caps.h" +#include "esp_idf_version.h" + +#if SOC_TOUCH_SENSOR_SUPPORTED +#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) && SOC_TOUCH_SENSOR_VERSION <= 2 // ESP32, ESP32S2, ESP32S3 + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp32-hal.h" + +#if !SOC_TOUCH_SENSOR_SUPPORTED +#error Touch IDF driver Not supported! +#endif + +#if SOC_TOUCH_SENSOR_VERSION == 1 // ESP32 +typedef uint16_t touch_value_t; +#elif SOC_TOUCH_SENSOR_VERSION == 2 // ESP32S2 ESP32S3 +typedef uint32_t touch_value_t; +#endif + +/* + * Set cycles that measurement operation takes + * The result from touchRead, threshold and detection + * accuracy depend on these values. Defaults are + * 0x1000 for measure and 0x1000 for sleep. + * With default values touchRead takes 0.5ms + * */ +void touchSetCycles(uint16_t measure, uint16_t sleep); + +/* + * Read touch pad (for ESP32 values close to 0 mean touch detected / + * for ESP32-S2/S3 higher values mean touch detected) + * You can use this method to chose a good threshold value + * to use as value for touchAttachInterrupt + * */ +touch_value_t touchRead(uint8_t pin); + +/* + * Set function to be called if touch pad value falls (ESP32) + * below the given threshold / rises (ESP32-S2/S3) by given increment (threshold). + * Use touchRead to determine a proper threshold between touched and untouched state + * */ +void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold); +void touchAttachInterruptArg(uint8_t pin, void (*userFunc)(void *), void *arg, touch_value_t threshold); +void touchDetachInterrupt(uint8_t pin); + +/* + * Specific functions to ESP32 + * Tells the driver if it shall activate the ISR if the sensor is Lower or Higher than the Threshold + * Default if Lower. + **/ + +#if SOC_TOUCH_SENSOR_VERSION == 1 // Only for ESP32 SoC +void touchInterruptSetThresholdDirection(bool mustbeLower); +#endif + +/* + * Specific functions to ESP32-S2 and ESP32-S3 + * Returns true when the latest ISR status for the Touchpad is that it is touched (Active) + * and false when the Touchpad is untoouched (Inactive) + * This function can be used in conjunction with ISR User callback in order to take action + * as soon as the touchpad is touched and/or released + **/ + +#if SOC_TOUCH_SENSOR_VERSION == 2 // Only for ESP32S2 and ESP32S3 +// returns true if touch pad has been and continues pressed and false otherwise +bool touchInterruptGetLastStatus(uint8_t pin); +#endif + +/* + * Setup touch pad wake up from deep sleep with given threshold. + **/ +void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold); + +#ifdef __cplusplus +} +#endif + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 5, 0) && SOC_TOUCH_SENSOR_VERSION <= 2 */ +#endif /* SOC_TOUCH_SENSOR_SUPPORTED */ +#endif /* MAIN_ESP32_HAL_TOUCH_H_ */ diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c new file mode 100644 index 0000000..d678b9a --- /dev/null +++ b/cores/esp32/esp32-hal-uart.c @@ -0,0 +1,1591 @@ +// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp32-hal-uart.h" + +#if SOC_UART_SUPPORTED +#include "esp32-hal.h" +#include "esp32-hal-periman.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +#include "driver/uart.h" +#include "hal/uart_ll.h" +#include "soc/soc_caps.h" +#include "soc/uart_struct.h" +#include "soc/uart_periph.h" +#include "rom/ets_sys.h" +#include "rom/gpio.h" + +#include "driver/gpio.h" +#include "hal/gpio_hal.h" +#include "esp_rom_gpio.h" +#include "esp_private/gpio.h" + +#include "driver/rtc_io.h" +#include "driver/lp_io.h" +#include "soc/uart_pins.h" +#include "esp_private/uart_share_hw_ctrl.h" + +static int s_uart_debug_nr = 0; // UART number for debug output +#define REF_TICK_BAUDRATE_LIMIT 250000 // this is maximum UART badrate using REF_TICK as clock + +/* C prototype for the notifier implemented in HardwareSerial.cpp */ +extern void hal_uart_notify_pins_detached(int uart_num); + +struct uart_struct_t { + +#if !CONFIG_DISABLE_HAL_LOCKS + SemaphoreHandle_t lock; // UART lock +#endif + + uint8_t num; // UART number for IDF driver API + bool has_peek; // flag to indicate that there is a peek byte pending to be read + uint8_t peek_byte; // peek byte that has been read but not consumed + QueueHandle_t uart_event_queue; // export it by some uartGetEventQueue() function + // configuration data:: Arduino API typical data + int8_t _rxPin, _txPin, _ctsPin, _rtsPin; // UART GPIOs + uint32_t _baudrate, _config; // UART baudrate and config + // UART ESP32 specific data + uint16_t _rx_buffer_size, _tx_buffer_size; // UART RX and TX buffer sizes + bool _inverted; // UART inverted signal + uint8_t _rxfifo_full_thrhd; // UART RX FIFO full threshold + int8_t _uart_clock_source; // UART Clock Source that should be used if user defines an specific one with setClockSource() + uint32_t inv_mask; // UART inverse mask used to maintain related pin state +}; + +#if CONFIG_DISABLE_HAL_LOCKS + +#define UART_MUTEX_LOCK() +#define UART_MUTEX_UNLOCK() + +static uart_t _uart_bus_array[] = { + {0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#if SOC_UART_NUM > 1 + {1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 2 + {2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 3 + {3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 4 + {4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 5 + {5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +}; + +#else + +#define UART_MUTEX_LOCK() \ + if (uart->lock != NULL) \ + do { \ + } while (xSemaphoreTake(uart->lock, portMAX_DELAY) != pdPASS) +#define UART_MUTEX_UNLOCK() \ + if (uart->lock != NULL) \ + xSemaphoreGive(uart->lock) + +static uart_t _uart_bus_array[] = { + {NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#if SOC_UART_NUM > 1 + {NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 2 + {NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 3 + {NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 4 + {NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +#if SOC_UART_NUM > 5 + {NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1, 0}, +#endif +}; + +#endif + +#if SOC_UART_LP_NUM >= 1 +// LP UART enable pins routine +static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t direction, uint32_t idx) { + /* Skip configuration if the LP_IO is -1 */ + if (pin < 0) { + return true; + } + + // Initialize LP_IO + if (rtc_gpio_init(pin) != ESP_OK) { + log_e("Failed to initialize LP_IO %d", pin); + return false; + } + + // Set LP_IO direction + if (rtc_gpio_set_direction(pin, direction) != ESP_OK) { + log_e("Failed to set LP_IO %d direction", pin); + return false; + } + + // Connect pins + const uart_periph_sig_t *upin = &uart_periph_signal[uart_num].pins[idx]; +#if !SOC_LP_GPIO_MATRIX_SUPPORTED // ESP32-C6/C61/C5 + // When LP_IO Matrix is not support, LP_IO Mux must be connected to the pins + if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) { + log_e("Failed to set LP_IO pin %d into Mux function", pin); + return false; + } +#else // So far, only ESP32-P4 + // If the configured pin is the default LP_IO Mux pin for LP UART, then set the LP_IO MUX function + if (upin->default_gpio == pin) { + if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) { + log_e("Failed to set LP_IO pin %d into Mux function", pin); + return false; + } + } else { + // Otherwise, set the LP_IO Matrix and select FUNC1 + if (rtc_gpio_iomux_func_sel(pin, 1) != ESP_OK) { + log_e("Failed to set LP_IO pin %d into Mux function GPIO", pin); + return false; + } + // Connect the LP_IO to the LP UART peripheral signal + esp_err_t ret; + if (direction == RTC_GPIO_MODE_OUTPUT_ONLY) { + ret = lp_gpio_connect_out_signal(pin, UART_PERIPH_SIGNAL(uart_num, idx), 0, 0); + } else { + ret = lp_gpio_connect_in_signal(pin, UART_PERIPH_SIGNAL(uart_num, idx), 0); + } + if (ret != ESP_OK) { + log_e("Failed to connect LP_IO pin %d to UART%d signal", pin, uart_num); + return false; + } + } +#endif // SOC_LP_GPIO_MATRIX_SUPPORTED + + return true; +} + +// When LP UART needs the RTC IO MUX to set the pin, it will always have fixed pins for RX, TX, CTS and RTS +static bool lpuartCheckPins(int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin, uint8_t uart_nr) { +// check if LP UART is being used and if the pins are valid +#if !SOC_LP_GPIO_MATRIX_SUPPORTED // ESP32-C6/C61/C5 + uint16_t lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RX_PIN_IDX].default_gpio; + if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM + if (rxPin > 0 && rxPin != lp_uart_fixed_pin) { + log_e("UART%d LP UART requires RX pin to be set to %d.", uart_nr, lp_uart_fixed_pin); + return false; + } + lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_TX_PIN_IDX].default_gpio; + if (txPin > 0 && txPin != lp_uart_fixed_pin) { + log_e("UART%d LP UART requires TX pin to be set to %d.", uart_nr, lp_uart_fixed_pin); + return false; + } + lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_CTS_PIN_IDX].default_gpio; + if (ctsPin > 0 && ctsPin != lp_uart_fixed_pin) { + log_e("UART%d LP UART requires CTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin); + return false; + } + lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RTS_PIN_IDX].default_gpio; + if (rtsPin > 0 && rtsPin != lp_uart_fixed_pin) { + log_e("UART%d LP UART requires RTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin); + return false; + } + } + return true; +#else // ESP32-P4 can set any pin for LP UART + return true; +#endif // SOC_LP_GPIO_MATRIX_SUPPORTED +} +#endif // SOC_UART_LP_NUM >= 1 + +#ifndef GPIO_FUNC_IN_LOW +#define GPIO_FUNC_IN_LOW GPIO_MATRIX_CONST_ZERO_INPUT +#endif + +#ifndef GPIO_FUNC_IN_HIGH +#define GPIO_FUNC_IN_HIGH GPIO_MATRIX_CONST_ONE_INPUT +#endif + +// Negative Pin Number will keep it unmodified, thus this function can detach individual pins +// This function will also unset the pins in the Peripheral Manager and set the pin to -1 after detaching +static bool _uartDetachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) { + if (uart_num >= SOC_UART_NUM) { + log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1); + return false; + } + // get UART information + uart_t *uart = &_uart_bus_array[uart_num]; + bool retCode = true; + //log_v("detaching UART%d pins: prev,pin RX(%d,%d) TX(%d,%d) CTS(%d,%d) RTS(%d,%d)", uart_num, + // uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10); + + // detaches HP and LP pins and sets Peripheral Manager and UART information + if (rxPin >= 0 && uart->_rxPin == rxPin && perimanGetPinBusType(rxPin) == ESP32_BUS_TYPE_UART_RX) { + //gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rxPin], PIN_FUNC_GPIO); + esp_rom_gpio_pad_select_gpio(rxPin); + // avoids causing BREAK in the UART line + if (uart->_inverted) { + esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_LOW, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); + } else { + esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_HIGH, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false); + } + uart->_rxPin = -1; // -1 means unassigned/detached + if (!perimanClearPinBus(rxPin)) { + retCode = false; + log_e("UART%d failed to detach RX pin %d", uart_num, rxPin); + } + } + if (txPin >= 0 && uart->_txPin == txPin && perimanGetPinBusType(txPin) == ESP32_BUS_TYPE_UART_TX) { + //gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[txPin], PIN_FUNC_GPIO); + esp_rom_gpio_pad_select_gpio(txPin); + esp_rom_gpio_connect_out_signal(txPin, SIG_GPIO_OUT_IDX, false, false); + uart->_txPin = -1; // -1 means unassigned/detached + if (!perimanClearPinBus(txPin)) { + retCode = false; + log_e("UART%d failed to detach TX pin %d", uart_num, txPin); + } + } + if (ctsPin >= 0 && uart->_ctsPin == ctsPin && perimanGetPinBusType(ctsPin) == ESP32_BUS_TYPE_UART_CTS) { + //gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[ctsPin], PIN_FUNC_GPIO); + esp_rom_gpio_pad_select_gpio(ctsPin); + esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_LOW, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false); + uart->_ctsPin = -1; // -1 means unassigned/detached + if (!perimanClearPinBus(ctsPin)) { + retCode = false; + log_e("UART%d failed to detach CTS pin %d", uart_num, ctsPin); + } + } + if (rtsPin >= 0 && uart->_rtsPin == rtsPin && perimanGetPinBusType(rtsPin) == ESP32_BUS_TYPE_UART_RTS) { + //gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rtsPin], PIN_FUNC_GPIO); + esp_rom_gpio_pad_select_gpio(rtsPin); + esp_rom_gpio_connect_out_signal(rtsPin, SIG_GPIO_OUT_IDX, false, false); + uart->_rtsPin = -1; // -1 means unassigned/detached + if (!perimanClearPinBus(rtsPin)) { + retCode = false; + log_e("UART%d failed to detach RTS pin %d", uart_num, rtsPin); + } + } + return retCode; +} + +// Peripheral Manager detach callback for each specific UART PIN +static bool _uartDetachBus_RX(void *busptr) { + // sanity check - it should never happen + if (busptr == NULL) { + log_e("_uartDetachBus_RX: busptr is NULL"); + return false; + } + uart_t *bus = (uart_t *)busptr; + if (bus->_rxPin < 0) { + log_d("_uartDetachBus_RX: RX pin already detached for UART%d", bus->num); + return true; + } + if (bus->_txPin < 0) { // both rx and tx pins are detached, terminate the uart driver + log_d("_uartDetachBus_RX: both RX and TX pins detached for UART%d, terminating driver", bus->num); + hal_uart_notify_pins_detached(bus->num); + return true; + } + return _uartDetachPins(bus->num, bus->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); +} + +static bool _uartDetachBus_TX(void *busptr) { + // sanity check - it should never happen + if (busptr == NULL) { + log_e("_uartDetachBus_TX: busptr is NULL"); + return false; + } + uart_t *bus = (uart_t *)busptr; + if (bus->_txPin < 0) { + log_d("_uartDetachBus_TX: TX pin already detached for UART%d", bus->num); + return true; + } + if (bus->_rxPin < 0) { // both rx and tx pins are detached, terminate the uart driver + log_d("_uartDetachBus_TX: both RX and TX pins detached for UART%d, terminating driver", bus->num); + hal_uart_notify_pins_detached(bus->num); + return true; + } + return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, bus->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); +} + +static bool _uartDetachBus_CTS(void *busptr) { + // sanity check - it should never happen + if (busptr == NULL) { + log_e("_uartDetachBus_CTS: busptr is NULL"); + return false; + } + uart_t *bus = (uart_t *)busptr; + if (bus->_ctsPin < 0) { + log_d("_uartDetachBus_CTS: CTS pin already detached for UART%d", bus->num); + return true; + } + return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, bus->_ctsPin, UART_PIN_NO_CHANGE); +} + +static bool _uartDetachBus_RTS(void *busptr) { + // sanity check - it should never happen + if (busptr == NULL) { + log_e("_uartDetachBus_RTS: busptr is NULL"); + return false; + } + uart_t *bus = (uart_t *)busptr; + if (bus->_rtsPin < 0) { + log_d("_uartDetachBus_RTS: RTS pin already detached for UART%d", bus->num); + return true; + } + return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, bus->_rtsPin); +} + +// Attach function for UART +// connects the IO Pad, set Paripheral Manager and internal UART structure data +static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) { + if (uart_num >= SOC_UART_NUM) { + log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1); + return false; + } + // get UART information + uart_t *uart = &_uart_bus_array[uart_num]; + //log_v("attaching UART%d pins: prev,new RX(%d,%d) TX(%d,%d) CTS(%d,%d) RTS(%d,%d)", uart_num, + // uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10); + + // IDF uart_set_pin() checks if the pin is used within LP UART and if it is a valid RTC IO pin + // No need for Arduino Layer to check it again + bool retCode = true; + if (rxPin >= 0) { + // forces a clean detaching from a previous peripheral + if (perimanGetPinBusType(rxPin) != ESP32_BUS_TYPE_INIT) { + perimanClearPinBus(rxPin); + } + // connect RX Pad + bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); +#if SOC_UART_LP_NUM >= 1 + if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM + ret &= lp_uart_config_io(uart->num, rxPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_RX_PIN_IDX); + } +#endif + if (ret) { + ret &= perimanSetPinBus(rxPin, ESP32_BUS_TYPE_UART_RX, (void *)uart, uart_num, -1); + if (ret) { + uart->_rxPin = rxPin; + // set Peripheral Manager deInit Callback for this UART pin + if (perimanGetBusDeinit(ESP32_BUS_TYPE_UART_RX) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RX, _uartDetachBus_RX); + } + } + } + if (!ret) { + log_e("UART%d failed to attach RX pin %d", uart_num, rxPin); + } + retCode &= ret; + } + if (txPin >= 0) { + // forces a clean detaching from a previous peripheral + if (perimanGetPinBusType(txPin) != ESP32_BUS_TYPE_INIT) { + perimanClearPinBus(txPin); + } + // connect TX Pad + bool ret = ESP_OK == uart_set_pin(uart->num, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); +#if SOC_UART_LP_NUM >= 1 + if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM + ret &= lp_uart_config_io(uart->num, txPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_TX_PIN_IDX); + } +#endif + if (ret) { + ret &= perimanSetPinBus(txPin, ESP32_BUS_TYPE_UART_TX, (void *)uart, uart_num, -1); + if (ret) { + uart->_txPin = txPin; + // set Peripheral Manager deInit Callback for this UART pin + if (perimanGetBusDeinit(ESP32_BUS_TYPE_UART_TX) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_TX, _uartDetachBus_TX); + } + } + } + if (!ret) { + log_e("UART%d failed to attach TX pin %d", uart_num, txPin); + } + retCode &= ret; + } + if (ctsPin >= 0) { + // forces a clean detaching from a previous peripheral + if (perimanGetPinBusType(ctsPin) != ESP32_BUS_TYPE_INIT) { + perimanClearPinBus(ctsPin); + } + // connect CTS Pad + bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ctsPin); +#if SOC_UART_LP_NUM >= 1 + if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM + ret &= lp_uart_config_io(uart->num, ctsPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX); + } +#endif + if (ret) { + ret &= perimanSetPinBus(ctsPin, ESP32_BUS_TYPE_UART_CTS, (void *)uart, uart_num, -1); + if (ret) { + uart->_ctsPin = ctsPin; + // set Peripheral Manager deInit Callback for this UART pin + if (perimanGetBusDeinit(ESP32_BUS_TYPE_UART_CTS) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_CTS, _uartDetachBus_CTS); + } + } + } + if (!ret) { + log_e("UART%d failed to attach CTS pin %d", uart_num, ctsPin); + } + retCode &= ret; + } + if (rtsPin >= 0) { + // forces a clean detaching from a previous peripheral + if (perimanGetPinBusType(rtsPin) != ESP32_BUS_TYPE_INIT) { + perimanClearPinBus(rtsPin); + } + // connect RTS Pad + bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, rtsPin, UART_PIN_NO_CHANGE); +#if SOC_UART_LP_NUM >= 1 + if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM + ret &= lp_uart_config_io(uart->num, rtsPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX); + } +#endif + if (ret) { + ret &= perimanSetPinBus(rtsPin, ESP32_BUS_TYPE_UART_RTS, (void *)uart, uart_num, -1); + if (ret) { + uart->_rtsPin = rtsPin; + // set Peripheral Manager deInit Callback for this UART pin + if (perimanGetBusDeinit(ESP32_BUS_TYPE_UART_RTS) == NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RTS, _uartDetachBus_RTS); + } + } + } + if (!ret) { + log_e("UART%d failed to attach RTS pin %d", uart_num, rtsPin); + } + retCode &= ret; + } + return retCode; +} + +// just helper functions +int8_t uart_get_RxPin(uint8_t uart_num) { + return _uart_bus_array[uart_num]._rxPin; +} + +int8_t uart_get_TxPin(uint8_t uart_num) { + return _uart_bus_array[uart_num]._txPin; +} + +// Routines that take care of UART events will be in the HardwareSerial Class code +void uartGetEventQueue(uart_t *uart, QueueHandle_t *q) { + // passing back NULL for the Queue pointer when UART is not initialized yet + *q = NULL; + if (uart == NULL) { + return; + } + *q = uart->uart_event_queue; + return; +} + +bool uartIsDriverInstalled(uart_t *uart) { + if (uart == NULL) { + return false; + } + + if (uart_is_driver_installed(uart->num)) { + return true; + } + return false; +} + +// Negative Pin Number will keep it unmodified, thus this function can set individual pins +// When pins are changed, it will detach the previous one +bool uartSetPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) { + if (uart_num >= SOC_UART_NUM) { + log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1); + return false; + } + // get UART information + uart_t *uart = &_uart_bus_array[uart_num]; + +#if SOC_UART_LP_NUM >= 1 + // check if LP UART is being used and if the pins are valid + if (!lpuartCheckPins(rxPin, txPin, ctsPin, rtsPin, uart_num)) { + return false; // failed to set pins + } +#endif + + bool retCode = true; + UART_MUTEX_LOCK(); + + //log_v("setting UART%d pins: prev->new RX(%d->%d) TX(%d->%d) CTS(%d->%d) RTS(%d->%d)", uart_num, + // uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10); + + // mute bus detaching callbacks to avoid terminating the UART driver when both RX and TX pins are detached + peripheral_bus_deinit_cb_t rxDeinit = perimanGetBusDeinit(ESP32_BUS_TYPE_UART_RX); + peripheral_bus_deinit_cb_t txDeinit = perimanGetBusDeinit(ESP32_BUS_TYPE_UART_TX); + peripheral_bus_deinit_cb_t ctsDeinit = perimanGetBusDeinit(ESP32_BUS_TYPE_UART_CTS); + peripheral_bus_deinit_cb_t rtsDeinit = perimanGetBusDeinit(ESP32_BUS_TYPE_UART_RTS); + perimanClearBusDeinit(ESP32_BUS_TYPE_UART_RX); + perimanClearBusDeinit(ESP32_BUS_TYPE_UART_TX); + perimanClearBusDeinit(ESP32_BUS_TYPE_UART_CTS); + perimanClearBusDeinit(ESP32_BUS_TYPE_UART_RTS); + + // First step: detaches all previous UART pins + bool rxPinChanged = rxPin >= 0 && rxPin != uart->_rxPin; + if (rxPinChanged) { + retCode &= _uartDetachPins(uart_num, uart->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + } + bool txPinChanged = txPin >= 0 && txPin != uart->_txPin; + if (txPinChanged) { + retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, uart->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + } + bool ctsPinChanged = ctsPin >= 0 && ctsPin != uart->_ctsPin; + if (ctsPinChanged) { + retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart->_ctsPin, UART_PIN_NO_CHANGE); + } + bool rtsPinChanged = rtsPin >= 0 && rtsPin != uart->_rtsPin; + if (rtsPinChanged) { + retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart->_rtsPin); + } + + // Second step: attach all UART new pins + if (rxPinChanged) { + retCode &= _uartAttachPins(uart_num, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + } + if (txPinChanged) { + retCode &= _uartAttachPins(uart_num, UART_PIN_NO_CHANGE, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + } + if (ctsPinChanged) { + retCode &= _uartAttachPins(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ctsPin, UART_PIN_NO_CHANGE); + } + if (rtsPinChanged) { + retCode &= _uartAttachPins(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, rtsPin); + } + + // restore bus detaching callbacks + if (rxDeinit != NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RX, rxDeinit); + } + if (txDeinit != NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_TX, txDeinit); + } + if (ctsDeinit != NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_CTS, ctsDeinit); + } + if (rtsDeinit != NULL) { + perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RTS, rtsDeinit); + } + + UART_MUTEX_UNLOCK(); + + if (!retCode) { + log_e("UART%d set pins failed.", uart_num); + } + return retCode; +} + +// +bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t threshold) { + if (uart == NULL) { + return false; + } + // IDF will issue corresponding error message when mode or threshold are wrong and prevent crashing + // IDF will check (mode > HW_FLOWCTRL_CTS_RTS || threshold >= SOC_UART_FIFO_LEN) + UART_MUTEX_LOCK(); + bool retCode = (ESP_OK == uart_set_hw_flow_ctrl(uart->num, mode, threshold)); + UART_MUTEX_UNLOCK(); + return retCode; +} + +// This helper function will return true if a new IDF UART driver needs to be restarted and false if the current one can continue its execution +bool _testUartBegin( + uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted, + uint8_t rxfifo_full_thrhd +) { + if (uart_nr >= SOC_UART_NUM) { + return false; // no new driver has to be installed + } + uart_t *uart = &_uart_bus_array[uart_nr]; + // verify if is necessary to restart the UART driver + if (uart_is_driver_installed(uart_nr)) { + // some parameters can't be changed unless we end the UART driver + if (uart->_rx_buffer_size != rx_buffer_size || uart->_tx_buffer_size != tx_buffer_size || uart->_inverted != inverted + || uart->_rxfifo_full_thrhd != rxfifo_full_thrhd) { + return true; // the current IDF UART driver must be terminated and a new driver shall be installed + } else { + return false; // The current IDF UART driver can continue its execution + } + } else { + return true; // no IDF UART driver is running and a new driver shall be installed + } +} + +uart_t *uartBegin( + uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted, + uint8_t rxfifo_full_thrhd +) { + if (uart_nr >= SOC_UART_NUM) { + log_e("UART number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1); + return NULL; // no new driver was installed + } + uart_t *uart = &_uart_bus_array[uart_nr]; + log_v("UART%d baud(%ld) Mode(%x) rxPin(%d) txPin(%d)", uart_nr, baudrate, config, rxPin, txPin); + +#if SOC_UART_LP_NUM >= 1 + // check if LP UART is being used and if the pins are valid + if (!lpuartCheckPins(rxPin, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart_nr)) { + if (uart_is_driver_installed(uart_nr)) { + return uart; // keep the same installed driver + } else { + return NULL; // no new driver was installed + } + } +#endif + +#if !CONFIG_DISABLE_HAL_LOCKS + if (uart->lock == NULL) { + uart->lock = xSemaphoreCreateMutex(); + if (uart->lock == NULL) { + log_e("HAL LOCK error."); + return NULL; // no new driver was installed + } + } +#endif + + if (uart_is_driver_installed(uart_nr)) { + log_v("UART%d Driver already installed.", uart_nr); + // some parameters can't be changed unless we end the UART driver + if (uart->_rx_buffer_size != rx_buffer_size || uart->_tx_buffer_size != tx_buffer_size || uart->_inverted != inverted + || uart->_rxfifo_full_thrhd != rxfifo_full_thrhd) { + log_v("UART%d changing buffer sizes or inverted signal or rxfifo_full_thrhd. IDF driver will be restarted", uart_nr); + log_v("RX buffer size: %d -> %d", uart->_rx_buffer_size, rx_buffer_size); + log_v("TX buffer size: %d -> %d", uart->_tx_buffer_size, tx_buffer_size); + log_v("Inverted signal: %s -> %s", uart->_inverted ? "true" : "false", inverted ? "true" : "false"); + log_v("RX FIFO full threshold: %d -> %d", uart->_rxfifo_full_thrhd, rxfifo_full_thrhd); + uartEnd(uart_nr); + } else { + bool retCode = true; + //User may just want to change some parameters, such as baudrate, data length, parity, stop bits or pins + if (uart->_baudrate != baudrate) { + retCode = uartSetBaudRate(uart, baudrate); + } + UART_MUTEX_LOCK(); + uart_word_length_t data_bits = (config & 0xc) >> 2; + uart_parity_t parity = config & 0x3; + uart_stop_bits_t stop_bits = (config & 0x30) >> 4; + if (retCode && (uart->_config & 0xc) >> 2 != data_bits) { + if (ESP_OK != uart_set_word_length(uart_nr, data_bits)) { + log_e("UART%d changing data length failed.", uart_nr); + retCode = false; + } else { + log_v("UART%d changed data length to %d", uart_nr, data_bits + 5); + } + } + if (retCode && (uart->_config & 0x3) != parity) { + if (ESP_OK != uart_set_parity(uart_nr, parity)) { + log_e("UART%d changing parity failed.", uart_nr); + retCode = false; + } else { + log_v("UART%d changed parity to %s", uart_nr, parity == 0 ? "NONE" : parity == 2 ? "EVEN" : "ODD"); + } + } + if (retCode && (uart->_config & 0xc30) >> 4 != stop_bits) { + if (ESP_OK != uart_set_stop_bits(uart_nr, stop_bits)) { + log_e("UART%d changing stop bits failed.", uart_nr); + retCode = false; + } else { + log_v("UART%d changed stop bits to %d", uart_nr, stop_bits == 3 ? 2 : 1); + } + } + if (retCode) { + uart->_config = config; + } + if (retCode && rxPin > 0 && uart->_rxPin != rxPin) { + retCode &= _uartDetachPins(uart_nr, uart->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + retCode &= _uartAttachPins(uart_nr, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + if (!retCode) { + log_e("UART%d changing RX pin failed.", uart_nr); + } else { + log_v("UART%d changed RX pin to %d", uart_nr, rxPin); + } + } + if (retCode && txPin > 0 && uart->_txPin != txPin) { + retCode &= _uartDetachPins(uart_nr, UART_PIN_NO_CHANGE, uart->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + retCode &= _uartAttachPins(uart_nr, UART_PIN_NO_CHANGE, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + if (!retCode) { + log_e("UART%d changing TX pin failed.", uart_nr); + } else { + log_v("UART%d changed TX pin to %d", uart_nr, txPin); + } + } + UART_MUTEX_UNLOCK(); + if (retCode) { + // UART driver was already working, just return the uart_t structure, saying that no new driver was installed + return uart; + } + // if we reach this point, it means that we need to restart the UART driver + uartEnd(uart_nr); + } + } else { + log_v("UART%d not installed. Starting installation", uart_nr); + } + uart_config_t uart_config; + memset(&uart_config, 0, sizeof(uart_config_t)); + uart_config.flags.backup_before_sleep = false; // new flag from IDF v5.3 + uart_config.data_bits = (config & 0xc) >> 2; + uart_config.parity = (config & 0x3); + uart_config.stop_bits = (config & 0x30) >> 4; + uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd >= UART_HW_FIFO_LEN(uart_nr) ? UART_HW_FIFO_LEN(uart_nr) - 6 : rxfifo_full_thrhd; + log_v( + "UART%d RX FIFO full threshold set to %d (value requested: %d || FIFO Max = %d)", uart_nr, uart_config.rx_flow_ctrl_thresh, rxfifo_full_thrhd, + UART_HW_FIFO_LEN(uart_nr) + ); + rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh; // makes sure that it will be set correctly in the struct + uart_config.baud_rate = baudrate; +#if SOC_UART_LP_NUM >= 1 + if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM + if (uart->_uart_clock_source >= 0) { + uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source; // use user defined LP UART clock + log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source); + } else { + uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT; // use default LP clock + log_v("Setting UART%d to Default LP clock source", uart_nr); + } + } else +#endif // SOC_UART_LP_NUM >= 1 + { + if (uart->_uart_clock_source >= 0) { + uart_config.source_clk = (soc_module_clk_t)uart->_uart_clock_source; // use user defined HP UART clock + log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source); + } else { + // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored + // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. +#if SOC_UART_SUPPORT_XTAL_CLK + uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 + log_v("Setting UART%d to use XTAL clock", uart_nr); +#elif SOC_UART_SUPPORT_REF_TICK + if (baudrate <= REF_TICK_BAUDRATE_LIMIT) { + uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps + log_v("Setting UART%d to use REF_TICK clock", uart_nr); + } else { + uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency! + log_v("Setting UART%d to use APB clock", uart_nr); + } +#else + // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4 + uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency! + log_v("Setting UART%d to use DEFAULT clock", uart_nr); +#endif // SOC_UART_SUPPORT_XTAL_CLK + } + } + + UART_MUTEX_LOCK(); + bool retCode = ESP_OK == uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0); + + if (retCode) { + retCode &= ESP_OK == uart_param_config(uart_nr, &uart_config); + } + + if (retCode) { + if (inverted) { + // invert signal for both Rx and Tx + uint32_t _inv_mask = uart->inv_mask; + _inv_mask |= UART_SIGNAL_TXD_INV | UART_SIGNAL_RXD_INV; + retCode &= ESP_OK == uart_set_line_inverse(uart_nr, _inv_mask); + if (retCode) { + uart->inv_mask = _inv_mask; + log_v("UART%d: RX and TX signals are set to be inverted.", uart_nr); + } + } else { + // disable invert signal for both Rx and Tx + retCode &= ESP_OK == uart_set_line_inverse(uart_nr, UART_SIGNAL_INV_DISABLE); + if (retCode) { + uart->inv_mask = UART_SIGNAL_INV_DISABLE; + log_v("UART%d: RX and TX signals are set not inverted.", uart_nr); + } + } + } + // if all fine, set internal parameters + if (retCode) { + uart->_baudrate = baudrate; + uart->_config = config; + uart->_inverted = inverted; + uart->_rxfifo_full_thrhd = rxfifo_full_thrhd; + uart->_rx_buffer_size = rx_buffer_size; + uart->_tx_buffer_size = tx_buffer_size; + uart->has_peek = false; + uart->peek_byte = 0; + // uart->_uart_clock_source can only change by explicit user API request/call + } + UART_MUTEX_UNLOCK(); + + // uartSetPins detaches previous pins if new ones are used over a previous begin() + if (retCode) { + retCode &= uartSetPins(uart_nr, rxPin, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + } + if (!retCode) { + log_e("UART%d initialization error.", uart->num); + uartEnd(uart_nr); + uart = NULL; + } else { + uartFlush(uart); + log_v("UART%d initialization done.", uart->num); + } + return uart; // a new driver was installed +} + +// This function code is under testing - for now just keep it here +void uartSetFastReading(uart_t *uart) { + if (uart == NULL) { + return; + } + + UART_MUTEX_LOCK(); + // override default RX IDF Driver Interrupt - no BREAK, PARITY or OVERFLOW + uart_intr_config_t uart_intr = { + .intr_enable_mask = UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT, // only these IRQs - no BREAK, PARITY or OVERFLOW + .rx_timeout_thresh = 1, + .txfifo_empty_intr_thresh = 10, + .rxfifo_full_thresh = 2, + }; + + ESP_ERROR_CHECK(uart_intr_config(uart->num, &uart_intr)); + UART_MUTEX_UNLOCK(); +} + +bool uartSetRxTimeout(uart_t *uart, uint8_t numSymbTimeout) { + if (uart == NULL) { + return false; + } + uint16_t maxRXTimeout = uart_get_max_rx_timeout(uart->num); + if (numSymbTimeout > maxRXTimeout) { + log_e("Invalid RX Timeout value, its limit is %d", maxRXTimeout); + return false; + } + UART_MUTEX_LOCK(); + bool retCode = (ESP_OK == uart_set_rx_timeout(uart->num, numSymbTimeout)); + UART_MUTEX_UNLOCK(); + return retCode; +} + +bool uartSetRxFIFOFull(uart_t *uart, uint8_t numBytesFIFOFull) { + if (uart == NULL) { + return false; + } + uint8_t rxfifo_full_thrhd = numBytesFIFOFull >= UART_HW_FIFO_LEN(uart->num) ? UART_HW_FIFO_LEN(uart->num) - 6 : numBytesFIFOFull; + UART_MUTEX_LOCK(); + bool retCode = (ESP_OK == uart_set_rx_full_threshold(uart->num, rxfifo_full_thrhd)); + if (retCode) { + uart->_rxfifo_full_thrhd = rxfifo_full_thrhd; + if (rxfifo_full_thrhd != numBytesFIFOFull) { + log_w("The RX FIFO Full value for UART%d was set to %d instead of %d", uart->num, rxfifo_full_thrhd, numBytesFIFOFull); + } + log_v("UART%d RX FIFO Full value set to %d from a requested value of %d", uart->num, rxfifo_full_thrhd, numBytesFIFOFull); + } else { + log_e("UART%d failed to set RX FIFO Full value to %d", uart->num, numBytesFIFOFull); + } + UART_MUTEX_UNLOCK(); + return retCode; +} + +void uartEnd(uint8_t uart_num) { + if (uart_num >= SOC_UART_NUM) { + log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1); + return; + } + // get UART information + uart_t *uart = &_uart_bus_array[uart_num]; + + UART_MUTEX_LOCK(); + _uartDetachPins(uart_num, uart->_rxPin, uart->_txPin, uart->_ctsPin, uart->_rtsPin); + if (uart_is_driver_installed(uart_num)) { + uart_driver_delete(uart_num); + } + if (uartGetDebug() == uart_num) { + uartSetDebug(0); + } + UART_MUTEX_UNLOCK(); +} + +// Helper generic function that takes a uart_signal_inv_t mask to be properly applied to the designated uart pin +// invMask can be UART_SIGNAL_RXD_INV, UART_SIGNAL_TXD_INV, UART_SIGNAL_RTS_INV, UART_SIGNAL_CTS_INV +// returns the operation success status +bool uartPinSignalInversion(uart_t *uart, uint32_t invMask, bool inverted) { + if (uart == NULL) { + return false; + } + UART_MUTEX_LOCK(); + uint32_t _inv_mask = uart->inv_mask; + if (inverted) { + _inv_mask |= invMask; + } else { + _inv_mask &= ~invMask; + } + bool retCode = ESP_OK == uart_set_line_inverse(uart->num, _inv_mask); + if (retCode) { + uart->inv_mask = _inv_mask; + } + UART_MUTEX_UNLOCK(); + return retCode; +} + +bool uartSetRxInvert(uart_t *uart, bool invert) { + if (uartPinSignalInversion(uart, UART_SIGNAL_RXD_INV, invert)) { + log_v("UART%d: RX signal inversion %s", uart->num, invert ? "enabled" : "disabled"); + return true; + } + return false; +} + +bool uartSetTxInvert(uart_t *uart, bool invert) { + if (uartPinSignalInversion(uart, UART_SIGNAL_TXD_INV, invert)) { + log_v("UART%d: TX signal inversion %s", uart->num, invert ? "enabled" : "disabled"); + return true; + } + return false; +} + +bool uartSetCtsInvert(uart_t *uart, bool invert) { + if (uartPinSignalInversion(uart, UART_SIGNAL_CTS_INV, invert)) { + log_v("UART%d: CTS signal inversion %s", uart->num, invert ? "enabled" : "disabled"); + return true; + } + return false; +} + +bool uartSetRtsInvert(uart_t *uart, bool invert) { + if (uartPinSignalInversion(uart, UART_SIGNAL_RTS_INV, invert)) { + log_v("UART%d: RTS signal inversion %s", uart->num, invert ? "enabled" : "disabled"); + return true; + } + return false; +} + +uint32_t uartAvailable(uart_t *uart) { + + if (uart == NULL) { + return 0; + } + + UART_MUTEX_LOCK(); + size_t available; + uart_get_buffered_data_len(uart->num, &available); + if (uart->has_peek) { + available++; + } + UART_MUTEX_UNLOCK(); + return available; +} + +uint32_t uartAvailableForWrite(uart_t *uart) { + if (uart == NULL) { + return 0; + } + UART_MUTEX_LOCK(); + uint32_t available = uart_ll_get_txfifo_len(UART_LL_GET_HW(uart->num)); + size_t txRingBufferAvailable = 0; + if (ESP_OK == uart_get_tx_buffer_free_size(uart->num, &txRingBufferAvailable)) { + available = txRingBufferAvailable == 0 ? available : txRingBufferAvailable; + } + UART_MUTEX_UNLOCK(); + return available; +} + +size_t uartReadBytes(uart_t *uart, uint8_t *buffer, size_t size, uint32_t timeout_ms) { + if (uart == NULL || size == 0 || buffer == NULL) { + return 0; + } + + size_t bytes_read = 0; + + UART_MUTEX_LOCK(); + + if (uart->has_peek) { + uart->has_peek = false; + *buffer++ = uart->peek_byte; + size--; + bytes_read = 1; + } + + if (size > 0) { + int len = uart_read_bytes(uart->num, buffer, size, pdMS_TO_TICKS(timeout_ms)); + if (len < 0) { + len = 0; // error reading UART + } + bytes_read += len; + } + + UART_MUTEX_UNLOCK(); + return bytes_read; +} + +// DEPRECATED but the original code will be kept here as future reference when a final solution +// to the UART driver is defined in the use case of reading byte by byte from UART. +uint8_t uartRead(uart_t *uart) { + if (uart == NULL) { + return 0; + } + uint8_t c = 0; + + UART_MUTEX_LOCK(); + + if (uart->has_peek) { + uart->has_peek = false; + c = uart->peek_byte; + } else { + + int len = uart_read_bytes(uart->num, &c, 1, 20 / portTICK_PERIOD_MS); + if (len <= 0) { // includes negative return from IDF in case of error + c = 0; + } + } + UART_MUTEX_UNLOCK(); + return c; +} + +uint8_t uartPeek(uart_t *uart) { + if (uart == NULL) { + return 0; + } + uint8_t c = 0; + + UART_MUTEX_LOCK(); + + if (uart->has_peek) { + c = uart->peek_byte; + } else { + int len = uart_read_bytes(uart->num, &c, 1, 20 / portTICK_PERIOD_MS); + if (len <= 0) { // includes negative return from IDF in case of error + c = 0; + } else { + uart->has_peek = true; + uart->peek_byte = c; + } + } + UART_MUTEX_UNLOCK(); + return c; +} + +void uartWrite(uart_t *uart, uint8_t c) { + if (uart == NULL) { + return; + } + UART_MUTEX_LOCK(); + uart_write_bytes(uart->num, &c, 1); + UART_MUTEX_UNLOCK(); +} + +void uartWriteBuf(uart_t *uart, const uint8_t *data, size_t len) { + if (uart == NULL || data == NULL || !len) { + return; + } + + UART_MUTEX_LOCK(); + uart_write_bytes(uart->num, data, len); + UART_MUTEX_UNLOCK(); +} + +void uartFlush(uart_t *uart) { + uartFlushTxOnly(uart, true); +} + +void uartFlushTxOnly(uart_t *uart, bool txOnly) { + if (uart == NULL) { + return; + } + + UART_MUTEX_LOCK(); + while (!uart_ll_is_tx_idle(UART_LL_GET_HW(uart->num))); + + if (!txOnly) { + ESP_ERROR_CHECK(uart_flush_input(uart->num)); + } + UART_MUTEX_UNLOCK(); +} + +bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) { + if (uart == NULL) { + return false; + } + bool retCode = true; + soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT; +#if SOC_UART_LP_NUM >= 1 + if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM + if (uart->_uart_clock_source >= 0) { + newClkSrc = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source; // use user defined LP UART clock + log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc); + } else { + newClkSrc = LP_UART_SCLK_DEFAULT; // use default LP clock + log_v("Setting UART%d to Default LP clock source", uart->num); + } + } else +#endif // SOC_UART_LP_NUM >= 1 + { + if (uart->_uart_clock_source >= 0) { + newClkSrc = (soc_module_clk_t)uart->_uart_clock_source; // use user defined HP UART clock + log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc); + } else { + // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored + // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue. +#if SOC_UART_SUPPORT_XTAL_CLK + newClkSrc = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4 + log_v("Setting UART%d to use XTAL clock", uart->num); +#elif SOC_UART_SUPPORT_REF_TICK + if (baud_rate <= REF_TICK_BAUDRATE_LIMIT) { + newClkSrc = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps + log_v("Setting UART%d to use REF_TICK clock", uart->num); + } else { + newClkSrc = UART_SCLK_APB; // baudrate may change with the APB Frequency! + log_v("Setting UART%d to use APB clock", uart->num); + } +#else + // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4 + // using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration + log_v("Setting UART%d to use DEFAULT clock", uart->num); +#endif // SOC_UART_SUPPORT_XTAL_CLK + } + } + UART_MUTEX_LOCK(); + HP_UART_SRC_CLK_ATOMIC() { + uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc); + } + // uart->_uart_clock_source can only change by explicit user API request/call + if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) { + log_v("Setting UART%d baud rate to %ld.", uart->num, baud_rate); + uart->_baudrate = baud_rate; + } else { + retCode = false; + log_e("Setting UART%d baud rate to %ld has failed.", uart->num, baud_rate); + } + UART_MUTEX_UNLOCK(); + return retCode; +} + +uint32_t uartGetBaudRate(uart_t *uart) { + uint32_t baud_rate = 0; + + if (uart == NULL) { + return 0; + } + + UART_MUTEX_LOCK(); + if (uart_get_baudrate(uart->num, &baud_rate) != ESP_OK) { + log_e("Getting UART%d baud rate has failed.", uart->num); + baud_rate = (uint32_t)-1; // return value when failed + } + UART_MUTEX_UNLOCK(); + return baud_rate; +} + +static void ARDUINO_ISR_ATTR uart0_write_char(char c) { + while (uart_ll_get_txfifo_len(&UART0) == 0); + uart_ll_write_txfifo(&UART0, (const uint8_t *)&c, 1); +} + +#if SOC_UART_HP_NUM > 1 +static void ARDUINO_ISR_ATTR uart1_write_char(char c) { + while (uart_ll_get_txfifo_len(&UART1) == 0); + uart_ll_write_txfifo(&UART1, (const uint8_t *)&c, 1); +} +#endif + +#if SOC_UART_HP_NUM > 2 +static void ARDUINO_ISR_ATTR uart2_write_char(char c) { + while (uart_ll_get_txfifo_len(&UART2) == 0); + uart_ll_write_txfifo(&UART2, (const uint8_t *)&c, 1); +} +#endif + +#if SOC_UART_HP_NUM > 3 +static void ARDUINO_ISR_ATTR uart3_write_char(char c) { + while (uart_ll_get_txfifo_len(&UART3) == 0); + uart_ll_write_txfifo(&UART3, (const uint8_t *)&c, 1); +} +#endif + +#if SOC_UART_HP_NUM > 4 +static void ARDUINO_ISR_ATTR uart4_write_char(char c) { + while (uart_ll_get_txfifo_len(&UART4) == 0); + uart_ll_write_txfifo(&UART4, (const uint8_t *)&c, 1); +} +#endif + +void uart_install_putc() { + switch (s_uart_debug_nr) { + case 0: ets_install_putc1((void (*)(char)) & uart0_write_char); break; +#if SOC_UART_HP_NUM > 1 + case 1: ets_install_putc1((void (*)(char)) & uart1_write_char); break; +#endif +#if SOC_UART_HP_NUM > 2 + case 2: ets_install_putc1((void (*)(char)) & uart2_write_char); break; +#endif +#if SOC_UART_HP_NUM > 3 + case 3: ets_install_putc1((void (*)(char)) & uart3_write_char); break; +#endif +#if SOC_UART_HP_NUM > 4 + case 4: ets_install_putc1((void (*)(char)) & uart4_write_char); break; +#endif + default: ets_install_putc1(NULL); break; + } + ets_install_putc2(NULL); +} + +// Routines that take care of UART mode in the HardwareSerial Class code +// used to set UART_MODE_RS485_HALF_DUPLEX auto RTS for TXD for ESP32 chips +bool uartSetMode(uart_t *uart, uart_mode_t mode) { + if (uart == NULL || uart->num >= SOC_UART_NUM) { + return false; + } + + UART_MUTEX_LOCK(); + bool retCode = (ESP_OK == uart_set_mode(uart->num, mode)); + UART_MUTEX_UNLOCK(); + return retCode; +} + +// this function will set the uart clock source +// it must be called before uartBegin(), otherwise it won't change any thing. +bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) { + if (uartNum >= SOC_UART_NUM) { + log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1); + return false; + } + uart_t *uart = &_uart_bus_array[uartNum]; +#if SOC_UART_LP_NUM >= 1 + if (uart->num >= SOC_UART_HP_NUM) { + switch (clkSrc) { + case UART_SCLK_XTAL: uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2; break; +#if CONFIG_IDF_TARGET_ESP32C5 + case UART_SCLK_RTC: uart->_uart_clock_source = LP_UART_SCLK_RC_FAST; break; +#elif CONFIG_IDF_TARGET_ESP32P4 + case UART_SCLK_RTC: uart->_uart_clock_source = LP_UART_SCLK_DEFAULT; break; // default is RTC_FAST for P4 +#else + case UART_SCLK_RTC: uart->_uart_clock_source = LP_UART_SCLK_LP_FAST; break; +#endif + case UART_SCLK_DEFAULT: + default: uart->_uart_clock_source = LP_UART_SCLK_DEFAULT; + } + } else +#endif + { + uart->_uart_clock_source = clkSrc; + } + log_v("UART%d set clock source to %d", uart->num, uart->_uart_clock_source); + return true; +} + +void uartSetDebug(uart_t *uart) { + // LP UART is not supported for debug + if (uart == NULL || uart->num >= SOC_UART_HP_NUM) { + s_uart_debug_nr = -1; + } else { + s_uart_debug_nr = uart->num; + } + uart_install_putc(); +} + +int uartGetDebug() { + return s_uart_debug_nr; +} + +int log_printfv(const char *format, va_list arg) { + static char loc_buf[64]; + char *temp = loc_buf; + uint32_t len; + va_list copy; + va_copy(copy, arg); + len = vsnprintf(NULL, 0, format, copy); + va_end(copy); + if (len >= sizeof(loc_buf)) { + temp = (char *)malloc(len + 1); + if (temp == NULL) { + return 0; + } + } + /* +// This causes dead locks with logging in specific cases and also with C++ constructors that may send logs +#if !CONFIG_DISABLE_HAL_LOCKS + if(s_uart_debug_nr != -1 && _uart_bus_array[s_uart_debug_nr].lock){ + xSemaphoreTake(_uart_bus_array[s_uart_debug_nr].lock, portMAX_DELAY); + } +#endif +*/ + vsnprintf(temp, len + 1, format, arg); + ets_printf("%s", temp); + /* +// This causes dead locks with logging and also with constructors that may send logs +#if !CONFIG_DISABLE_HAL_LOCKS + if(s_uart_debug_nr != -1 && _uart_bus_array[s_uart_debug_nr].lock){ + xSemaphoreGive(_uart_bus_array[s_uart_debug_nr].lock); + } +#endif +*/ + if (len >= sizeof(loc_buf)) { + free(temp); + } + // flushes TX - make sure that the log message is completely sent. + if (s_uart_debug_nr != -1) { + while (!uart_ll_is_tx_idle(UART_LL_GET_HW(s_uart_debug_nr))); + } + return len; +} + +int log_printf(const char *format, ...) { + int len; + va_list arg; + va_start(arg, format); + len = log_printfv(format, arg); + va_end(arg); + return len; +} + +static void log_print_buf_line(const uint8_t *b, size_t len, size_t total_len) { + for (size_t i = 0; i < len; i++) { + log_printf("%s0x%02x,", i ? " " : "", b[i]); + } + if (total_len > 16) { + for (size_t i = len; i < 16; i++) { + log_printf(" "); + } + log_printf(" // "); + } else { + log_printf(" // "); + } + for (size_t i = 0; i < len; i++) { + log_printf("%c", ((b[i] >= 0x20) && (b[i] < 0x80)) ? b[i] : '.'); + } + log_printf("\n"); +} + +void log_print_buf(const uint8_t *b, size_t len) { + if (!len || !b) { + return; + } + for (size_t i = 0; i < len; i += 16) { + if (len > 16) { + log_printf("/* 0x%04X */ ", i); + } + log_print_buf_line(b + i, ((len - i) < 16) ? (len - i) : 16, len); + } +} + +/* + * if enough pulses are detected return the minimum high pulse duration + minimum low pulse duration divided by two. + * This equals one bit period. If flag is true the function return immediately, otherwise it waits for enough pulses. + */ +unsigned long uartBaudrateDetect(uart_t *uart, bool flg) { +// Baud rate detection only works for ESP32 and ESP32S2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + if (uart == NULL) { + return 0; + } + + uart_dev_t *hw = UART_LL_GET_HW(uart->num); + + while (hw->rxd_cnt.edge_cnt < 30) { // UART_PULSE_NUM(uart_num) + if (flg) { + return 0; + } + ets_delay_us(1000); + } + + UART_MUTEX_LOCK(); + //log_i("lowpulse_min_cnt = %d hightpulse_min_cnt = %d", hw->lowpulse.min_cnt, hw->highpulse.min_cnt); + unsigned long ret = ((hw->lowpulse.min_cnt + hw->highpulse.min_cnt) >> 1); + UART_MUTEX_UNLOCK(); + + return ret; +#else + return 0; +#endif +} + +/* + * To start detection of baud rate with the uart the auto_baud.en bit needs to be cleared and set. The bit period is + * detected calling uartBadrateDetect(). The raw baudrate is computed using the UART_CLK_FREQ. The raw baudrate is + * rounded to the closed real baudrate. + * + * ESP32-C3 reports wrong baud rate detection as shown below: + * + * This will help in a future recall for the C3. + * Baud Sent: Baud Read: + * 300 --> 19536 + * 2400 --> 19536 + * 4800 --> 19536 + * 9600 --> 28818 + * 19200 --> 57678 + * 38400 --> 115440 + * 57600 --> 173535 + * 115200 --> 347826 + * 230400 --> 701754 + * + * +*/ +void uartStartDetectBaudrate(uart_t *uart) { + if (uart == NULL) { + return; + } + +// Baud rate detection only works for ESP32 and ESP32S2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + uart_dev_t *hw = UART_LL_GET_HW(uart->num); + hw->auto_baud.glitch_filt = 0x08; + hw->auto_baud.en = 0; + hw->auto_baud.en = 1; +#else + + // ESP32-C3 requires further testing + // Baud rate detection returns wrong values + + log_e("baud rate detection for this SoC is not supported."); + return; + + // Code below for C3 kept for future recall + //hw->rx_filt.glitch_filt = 0x08; + //hw->rx_filt.glitch_filt_en = 1; + //hw->conf0.autobaud_en = 0; + //hw->conf0.autobaud_en = 1; +#endif +} + +unsigned long uartDetectBaudrate(uart_t *uart) { + if (uart == NULL) { + return 0; + } + +// Baud rate detection only works for ESP32 and ESP32S2 +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + + static bool uartStateDetectingBaudrate = false; + + if (!uartStateDetectingBaudrate) { + uartStartDetectBaudrate(uart); + uartStateDetectingBaudrate = true; + } + + unsigned long divisor = uartBaudrateDetect(uart, true); + if (!divisor) { + return 0; + } + + uart_dev_t *hw = UART_LL_GET_HW(uart->num); + hw->auto_baud.en = 0; + + uartStateDetectingBaudrate = false; // Initialize for the next round + + unsigned long baudrate = getApbFrequency() / divisor; + + //log_i("APB_FREQ = %d\nraw baudrate detected = %d", getApbFrequency(), baudrate); + + static const unsigned long default_rates[] = {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, + 74880, 115200, 230400, 256000, 460800, 921600, 1843200, 3686400}; + + size_t i; + for (i = 1; i < sizeof(default_rates) / sizeof(default_rates[0]) - 1; i++) // find the nearest real baudrate + { + if (baudrate <= default_rates[i]) { + if (baudrate - default_rates[i - 1] < default_rates[i] - baudrate) { + i--; + } + break; + } + } + + return default_rates[i]; +#else + log_e("baud rate detection this SoC is not supported."); + return 0; +#endif +} + +/* + * These functions are for testing purposes only and can be used in Arduino Sketches. + * They are utilized in the UART examples and CI. + */ + +/* + This function internally binds defined UARTs TX signal with defined RX pin of any UART (same or different). + This creates a loop that lets us receive anything we send on the UART without external wires. +*/ +void uart_internal_loopback(uint8_t uartNum, int8_t rxPin) { + // LP UART is not supported for loopback + if (uartNum >= SOC_UART_HP_NUM || !GPIO_IS_VALID_GPIO(rxPin)) { + log_e("UART%d is not supported for loopback or RX pin %d is invalid.", uartNum, rxPin); + return; + } +#if 0 // leave this code here for future reference and need + // forces rxPin to use GPIO Matrix and setup the pin to receive UART TX Signal - IDF 5.4.1 Change with uart_release_pin() + gpio_func_sel((gpio_num_t)rxPin, PIN_FUNC_GPIO); + gpio_pullup_en((gpio_num_t)rxPin); + gpio_input_enable((gpio_num_t)rxPin); + esp_rom_gpio_connect_in_signal(rxPin, uart_periph_signal[uartNum].pins[SOC_UART_RX_PIN_IDX].signal, false); +#endif + esp_rom_gpio_connect_out_signal(rxPin, uart_periph_signal[uartNum].pins[SOC_UART_TX_PIN_IDX].signal, false, false); +} + +/* + This function internally binds defined UARTs CTS signal with defined RTS pin of any UART (same or different). + This creates a internal connection of CTS to RTS used when testing Hardware Flow Control without external wires. +*/ +void uart_internal_hw_flow_ctrl_loopback(uint8_t uartNum, int8_t ctsPin) { + // LP UART is not supported for hw flow ctrl loopback + if (uartNum >= SOC_UART_HP_NUM || !GPIO_IS_VALID_GPIO(ctsPin)) { + log_e("UART%d is not supported for hw flow ctrl loopback or CTS pin %d is invalid.", uartNum, ctsPin); + return; + } + esp_rom_gpio_connect_out_signal(ctsPin, uart_periph_signal[uartNum].pins[SOC_UART_RTS_PIN_IDX].signal, false, false); +} + +/* + This is intended to generate BREAK in an UART line +*/ + +// Forces a BREAK in the line based on SERIAL_8N1 configuration at any baud rate +void uart_send_break(uint8_t uartNum) { + uint32_t currentBaudrate = 0; + uart_get_baudrate(uartNum, ¤tBaudrate); + // calculates 10 bits of breaks in microseconds for baudrates up to 500mbps + // This is very sensitive timing... it works fine for SERIAL_8N1 + uint32_t breakTime = (uint32_t)(10.0 * (1000000.0 / currentBaudrate)); + uart_set_line_inverse(uartNum, UART_SIGNAL_TXD_INV); + esp_rom_delay_us(breakTime); + uart_set_line_inverse(uartNum, UART_SIGNAL_INV_DISABLE); +} + +// Sends a buffer and at the end of the stream, it generates BREAK in the line +int uart_send_msg_with_break(uint8_t uartNum, uint8_t *msg, size_t msgSize) { + // 12 bits long BREAK for 8N1 + return uart_write_bytes_with_break(uartNum, (const void *)msg, msgSize, 12); +} + +// returns the maximum valid uart RX Timeout based on the UART Source Clock and Baudrate +uint16_t uart_get_max_rx_timeout(uint8_t uartNum) { + if (uartNum >= SOC_UART_NUM) { + log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1); + return (uint16_t)-1; + } + uint16_t tout_max_thresh = uart_ll_max_tout_thrd(UART_LL_GET_HW(uartNum)); + uint8_t symbol_len = 1; // number of bits per symbol including start + uart_parity_t parity_mode; + uart_stop_bits_t stop_bit; + uart_word_length_t data_bit; + uart_ll_get_data_bit_num(UART_LL_GET_HW(uartNum), &data_bit); + uart_ll_get_stop_bits(UART_LL_GET_HW(uartNum), &stop_bit); + uart_ll_get_parity(UART_LL_GET_HW(uartNum), &parity_mode); + symbol_len += (data_bit < UART_DATA_BITS_MAX) ? (uint8_t)data_bit + 5 : 8; + symbol_len += (stop_bit > UART_STOP_BITS_1) ? 2 : 1; + symbol_len += (parity_mode > UART_PARITY_DISABLE) ? 1 : 0; + return (uint16_t)(tout_max_thresh / symbol_len); +} + +#endif /* SOC_UART_SUPPORTED */ diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h new file mode 100644 index 0000000..343e8cf --- /dev/null +++ b/cores/esp32/esp32-hal-uart.h @@ -0,0 +1,152 @@ +// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef MAIN_ESP32_HAL_UART_H_ +#define MAIN_ESP32_HAL_UART_H_ + +#include "soc/soc_caps.h" +#if SOC_UART_SUPPORTED +#include "soc/uart_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/queue.h" +#include "hal/uart_types.h" + +struct uart_struct_t; +typedef struct uart_struct_t uart_t; + +bool _testUartBegin( + uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted, + uint8_t rxfifo_full_thrhd +); +uart_t *uartBegin( + uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted, + uint8_t rxfifo_full_thrhd +); +void uartEnd(uint8_t uart_num); + +// This is used to retrieve the Event Queue pointer from a UART IDF Driver in order to allow user to deal with its events +void uartGetEventQueue(uart_t *uart, QueueHandle_t *q); + +uint32_t uartAvailable(uart_t *uart); +uint32_t uartAvailableForWrite(uart_t *uart); +size_t uartReadBytes(uart_t *uart, uint8_t *buffer, size_t size, uint32_t timeout_ms); +uint8_t uartRead(uart_t *uart); +uint8_t uartPeek(uart_t *uart); + +void uartWrite(uart_t *uart, uint8_t c); +void uartWriteBuf(uart_t *uart, const uint8_t *data, size_t len); + +void uartFlush(uart_t *uart); +void uartFlushTxOnly(uart_t *uart, bool txOnly); + +bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate); +uint32_t uartGetBaudRate(uart_t *uart); + +// Helper generic function that takes a uart_signal_inv_t mask to be properly applied to the designated uart pin +// invMask can be UART_SIGNAL_RXD_INV, UART_SIGNAL_TXD_INV, UART_SIGNAL_RTS_INV, UART_SIGNAL_CTS_INV +// returns the operation success status +bool uartPinSignalInversion(uart_t *uart, uint32_t invMask, bool inverted); +// functions used to individually enable or disable UART pins inversion +bool uartSetRxInvert(uart_t *uart, bool invert); +bool uartSetTxInvert(uart_t *uart, bool invert); +bool uartSetCtsInvert(uart_t *uart, bool invert); +bool uartSetRtsInvert(uart_t *uart, bool invert); +bool uartSetRxTimeout(uart_t *uart, uint8_t numSymbTimeout); +bool uartSetRxFIFOFull(uart_t *uart, uint8_t numBytesFIFOFull); +void uartSetFastReading(uart_t *uart); + +void uartSetDebug(uart_t *uart); +int uartGetDebug(); + +bool uartIsDriverInstalled(uart_t *uart); + +// Negative Pin Number will keep it unmodified, thus this function can set individual pins +// When pins are changed, it will detach the previous ones +// Can be called before or after begin() +bool uartSetPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin); + +// helper functions +int8_t uart_get_RxPin(uint8_t uart_num); +int8_t uart_get_TxPin(uint8_t uart_num); + +// Enables or disables HW Flow Control function -- needs also to set CTS and/or RTS pins +// UART_HW_FLOWCTRL_DISABLE = 0x0 disable hardware flow control +// UART_HW_FLOWCTRL_RTS = 0x1 enable RX hardware flow control (rts) +// UART_HW_FLOWCTRL_CTS = 0x2 enable TX hardware flow control (cts) +// UART_HW_FLOWCTRL_CTS_RTS = 0x3 enable hardware flow control +bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t threshold); + +// Used to set RS485 function -- needs to disable HW Flow Control and set RTS pin to use +// RTS pin becomes RS485 half duplex RE/DE +// UART_MODE_UART = 0x00 mode: regular UART mode +// UART_MODE_RS485_HALF_DUPLEX = 0x01 mode: half duplex RS485 UART mode control by RTS pin +// UART_MODE_IRDA = 0x02 mode: IRDA UART mode +// UART_MODE_RS485_COLLISION_DETECT = 0x03 mode: RS485 collision detection UART mode (used for test purposes) +// UART_MODE_RS485_APP_CTRL = 0x04 mode: application control RS485 UART mode (used for test purposes) +bool uartSetMode(uart_t *uart, uart_mode_t mode); + +// Used to set the UART clock source mode. It must be set before calling uartBegin(), otherwise it won't have any effect. +// Not all clock source are available to every SoC. The compatible option are listed here: +// UART_SCLK_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source +// UART_SCLK_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3 +// UART_SCLK_PLL_F80M :: ESP32-C5, ESP32-C6, ESP32-C61 and ESP32-P4 +// UART_SCLK_PLL_F40M :: ESP32-C2 +// UART_SCLK_PLL_F48M :: ESP32-H2 +// UART_SCLK_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 +// UART_SCLK_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4 +// UART_SCLK_REF_TICK :: ESP32 and ESP32-S2 +// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only LP_UART_SCLK_LP_FAST (RTC_FAST) or LP_UART_SCLK_XTAL_D2 (XTAL/2) as Clock Source +bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc); + +void uartStartDetectBaudrate(uart_t *uart); +unsigned long uartDetectBaudrate(uart_t *uart); + +/* + These functions are for testing purposes only and can be used in Arduino Sketches + Those are used in the UART examples +*/ + +// Make sure UART's RX signal is connected to TX pin +// This creates a loop that lets us receive anything we send on the UART +void uart_internal_loopback(uint8_t uartNum, int8_t rxPin); + +// Make sure UART's RTS signal is connected to CTS pin +// This creates an RTS-CTS connection for testing hardware flow control on the selected UART +void uart_internal_hw_flow_ctrl_loopback(uint8_t uartNum, int8_t ctsPin); + +// Routines that generate BREAK in the UART for testing purpose + +// Forces a BREAK in the line based on SERIAL_8N1 configuration at any baud rate +void uart_send_break(uint8_t uartNum); +// Sends a buffer and at the end of the stream, it generates BREAK in the line +int uart_send_msg_with_break(uint8_t uartNum, uint8_t *msg, size_t msgSize); + +// UART RX Timeout (in UART Symbols) depends on the UART Clock Source and the SoC that is used +// This is a helper function that calculates what is the maximum RX Timeout that a running UART IDF driver allows. +uint16_t uart_get_max_rx_timeout(uint8_t uartNum); + +#ifdef __cplusplus +} +#endif + +#endif /* SOC_UART_SUPPORTED */ +#endif /* MAIN_ESP32_HAL_UART_H_ */ diff --git a/cores/esp32/esp32-hal.h b/cores/esp32/esp32-hal.h new file mode 100644 index 0000000..e3a1f6e --- /dev/null +++ b/cores/esp32/esp32-hal.h @@ -0,0 +1,173 @@ +/* + Arduino.h - Main include file for the Arduino SDK + Copyright (c) 2005-2013 Arduino Team. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef HAL_ESP32_HAL_H_ +#define HAL_ESP32_HAL_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_system.h" +#include "esp_sleep.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" +#include "freertos/event_groups.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef F_CPU +#define F_CPU (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000U) +#endif + +#if CONFIG_ARDUINO_ISR_IRAM +#define ARDUINO_ISR_ATTR IRAM_ATTR +#define ARDUINO_ISR_FLAG ESP_INTR_FLAG_IRAM +#else +#define ARDUINO_ISR_ATTR +#define ARDUINO_ISR_FLAG (0) +#endif + +#ifndef ARDUINO_RUNNING_CORE +#define ARDUINO_RUNNING_CORE CONFIG_ARDUINO_RUNNING_CORE +#endif + +#ifndef ARDUINO_EVENT_RUNNING_CORE +#define ARDUINO_EVENT_RUNNING_CORE CONFIG_ARDUINO_EVENT_RUNNING_CORE +#endif + +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +static const uint8_t BOOT_PIN = 0; +#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H2 \ + || CONFIG_IDF_TARGET_ESP32C61 +static const uint8_t BOOT_PIN = 9; +#elif CONFIG_IDF_TARGET_ESP32P4 +static const uint8_t BOOT_PIN = 35; +#elif CONFIG_IDF_TARGET_ESP32C5 +static const uint8_t BOOT_PIN = 28; +#else +#error BOOT_PIN not defined for this chip! +#endif +#define BOOT_PIN BOOT_PIN + +//forward declaration from freertos/portmacro.h +void vPortYield(void); +void yield(void); +#define optimistic_yield(u) + +#define ESP_REG(addr) *((volatile uint32_t *)(addr)) +#define NOP() asm volatile("nop") + +#include "esp32-hal-log.h" +#include "esp32-hal-matrix.h" +#include "esp32-hal-uart.h" +#include "esp32-hal-gpio.h" +#include "esp32-hal-touch.h" +#include "esp32-hal-touch-ng.h" +#include "esp32-hal-dac.h" +#include "esp32-hal-adc.h" +#include "esp32-hal-spi.h" +#include "esp32-hal-i2c.h" +#include "esp32-hal-ledc.h" +#include "esp32-hal-rmt.h" +#include "esp32-hal-sigmadelta.h" +#include "esp32-hal-timer.h" +#include "esp32-hal-bt.h" +#include "esp32-hal-psram.h" +#include "esp32-hal-rgb-led.h" +#include "esp32-hal-cpu.h" +#include "esp32-hal-hosted.h" + +void analogWrite(uint8_t pin, int value); +void analogWriteFrequency(uint8_t pin, uint32_t freq); +void analogWriteResolution(uint8_t pin, uint8_t bits); + +//returns chip temperature in Celsius +float temperatureRead(); + +//allows user to bypass SPI RAM test routine +bool testSPIRAM(void); + +#if CONFIG_AUTOSTART_ARDUINO +//enable/disable WDT for Arduino's setup and loop functions +void enableLoopWDT(); +void disableLoopWDT(); +//feed WDT for the loop task +void feedLoopWDT(); +#endif + +//enable/disable WDT for the IDLE task on Core 0 (SYSTEM) +void enableCore0WDT(); +bool disableCore0WDT(); +#ifndef CONFIG_FREERTOS_UNICORE +//enable/disable WDT for the IDLE task on Core 1 (Arduino) +void enableCore1WDT(); +bool disableCore1WDT(); +#endif + +//if xCoreID < 0 or CPU is unicore, it will use xTaskCreate, else xTaskCreatePinnedToCore +//allows to easily handle all possible situations without repetitive code +BaseType_t xTaskCreateUniversal( + TaskFunction_t pxTaskCode, const char *const pcName, const uint32_t usStackDepth, void *const pvParameters, UBaseType_t uxPriority, + TaskHandle_t *const pxCreatedTask, const BaseType_t xCoreID +); + +unsigned long micros(); +unsigned long millis(); +void delay(uint32_t); +void delayMicroseconds(uint32_t us); + +#if !CONFIG_ESP32_PHY_AUTO_INIT +void arduino_phy_init(); +#endif + +#if !CONFIG_AUTOSTART_ARDUINO +void initArduino(); +#endif + +typedef struct { + int core; // core which triggered panic + const char *reason; // exception string + const void *pc; // instruction address that triggered the exception + bool backtrace_corrupt; // if backtrace is corrupt + bool backtrace_continues; // if backtrace continues, but did not fit + unsigned int backtrace_len; // number of backtrace addresses + unsigned int backtrace[60]; // backtrace addresses array +} arduino_panic_info_t; + +typedef void (*arduino_panic_handler_t)(arduino_panic_info_t *info, void *arg); + +void set_arduino_panic_handler(arduino_panic_handler_t handler, void *arg); +arduino_panic_handler_t get_arduino_panic_handler(void); +void *get_arduino_panic_handler_arg(void); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_ESP32_HAL_H_ */ diff --git a/cores/esp32/esp8266-compat.h b/cores/esp32/esp8266-compat.h new file mode 100644 index 0000000..8123cd0 --- /dev/null +++ b/cores/esp32/esp8266-compat.h @@ -0,0 +1,23 @@ +// esp8266-compat.h - Compatibility functions to help ESP8266 libraries and user code run on ESP32 + +// Copyright (c) 2017 Evandro Luis Copercini. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP8266_COMPAT_H_ +#define _ESP8266_COMPAT_H_ + +#define ICACHE_FLASH_ATTR +#define ICACHE_RAM_ATTR ARDUINO_ISR_ATTR + +#endif /* _ESP8266_COMPAT_H_ */ diff --git a/cores/esp32/esp_arduino_version.h b/cores/esp32/esp_arduino_version.h new file mode 100644 index 0000000..dd10360 --- /dev/null +++ b/cores/esp32/esp_arduino_version.h @@ -0,0 +1,51 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** Major version number (X.x.x) */ +#define ESP_ARDUINO_VERSION_MAJOR 3 +/** Minor version number (x.X.x) */ +#define ESP_ARDUINO_VERSION_MINOR 3 +/** Patch version number (x.x.X) */ +#define ESP_ARDUINO_VERSION_PATCH 7 + +/** + * Macro to convert ARDUINO version number into an integer + * + * To be used in comparisons, such as ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2, 0, 0) + */ +#define ESP_ARDUINO_VERSION_VAL(major, minor, patch) ((major << 16) | (minor << 8) | (patch)) + +/** + * Current ARDUINO version, as an integer + * + * To be used in comparisons, such as ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2, 0, 0) + */ +#define ESP_ARDUINO_VERSION ESP_ARDUINO_VERSION_VAL(ESP_ARDUINO_VERSION_MAJOR, ESP_ARDUINO_VERSION_MINOR, ESP_ARDUINO_VERSION_PATCH) + +/** + * Current ARDUINO version, as string + */ +#define df2xstr(s) #s +#define df2str(s) df2xstr(s) +#define ESP_ARDUINO_VERSION_STR df2str(ESP_ARDUINO_VERSION_MAJOR) "." df2str(ESP_ARDUINO_VERSION_MINOR) "." df2str(ESP_ARDUINO_VERSION_PATCH) + +#ifdef __cplusplus +} +#endif diff --git a/cores/esp32/extra_attr.h b/cores/esp32/extra_attr.h new file mode 100644 index 0000000..d5342a5 --- /dev/null +++ b/cores/esp32/extra_attr.h @@ -0,0 +1,3 @@ +#define ATTR_PACKED __attribute__((__packed__)) +#define ATTR_ALIGNED(x) __attribute__((__aligned__(x))) +#define ATTR_SECTION(x) __attribute__((__section__(x))) diff --git a/cores/esp32/firmware_msc_fat.c b/cores/esp32/firmware_msc_fat.c new file mode 100644 index 0000000..e66cc26 --- /dev/null +++ b/cores/esp32/firmware_msc_fat.c @@ -0,0 +1,210 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "firmware_msc_fat.h" +//copy up to max_len chars from src to dst and do not terminate +static size_t cplstr(void *dst, const void *src, size_t max_len) { + if (!src || !dst || !max_len) { + return 0; + } + size_t l = strlen((const char *)src); + if (l > max_len) { + l = max_len; + } + memcpy(dst, src, l); + return l; +} + +//copy up to max_len chars from src to dst, adding spaces up to max_len. do not terminate +static void cplstrsp(void *dst, const void *src, size_t max_len) { + size_t l = cplstr(dst, src, max_len); + for (; l < max_len; l++) { + ((uint8_t *)dst)[l] = 0x20; + } +} + +// FAT12 +static const char *FAT12_FILE_SYSTEM_TYPE = "FAT12"; + +static uint16_t fat12_sectors_per_alloc_table(uint32_t sector_num) { + uint32_t required_bytes = (((sector_num * 3) + 1) / 2); + return (required_bytes / DISK_SECTOR_SIZE) + ((required_bytes & (DISK_SECTOR_SIZE - 1)) ? 1 : 0); +} + +static uint8_t *fat12_add_table(uint8_t *dst, fat_boot_sector_t *boot) { + memset(dst + DISK_SECTOR_SIZE, 0, boot->sectors_per_alloc_table * DISK_SECTOR_SIZE); + uint8_t *d = dst + DISK_SECTOR_SIZE; + d[0] = 0xF8; + d[1] = 0xFF; + d[2] = 0xFF; + return d; +} + +static void fat12_set_table_index(uint8_t *table, uint16_t index, uint16_t value) { + uint16_t offset = (index >> 1) * 3; + uint8_t *data = table + offset; + if (index & 1) { + data[2] = (value >> 4) & 0xFF; + data[1] = (data[1] & 0xF) | ((value & 0xF) << 4); + } else { + data[0] = value & 0xFF; + data[1] = (data[1] & 0xF0) | ((value >> 8) & 0xF); + } +} + +//FAT16 +static const char *FAT16_FILE_SYSTEM_TYPE = "FAT16"; + +static uint16_t fat16_sectors_per_alloc_table(uint32_t sector_num) { + uint32_t required_bytes = sector_num * 2; + return (required_bytes / DISK_SECTOR_SIZE) + ((required_bytes & (DISK_SECTOR_SIZE - 1)) ? 1 : 0); +} + +static uint8_t *fat16_add_table(uint8_t *dst, fat_boot_sector_t *boot) { + memset(dst + DISK_SECTOR_SIZE, 0, boot->sectors_per_alloc_table * DISK_SECTOR_SIZE); + uint16_t *d = (uint16_t *)(dst + DISK_SECTOR_SIZE); + d[0] = 0xFFF8; + d[1] = 0xFFFF; + return (uint8_t *)d; +} + +static void fat16_set_table_index(uint8_t *table, uint16_t index, uint16_t value) { + uint16_t offset = index * 2; + *(uint16_t *)(table + offset) = value; +} + +//Interface +const char *fat_file_system_type(bool fat16) { + return ((fat16) ? FAT16_FILE_SYSTEM_TYPE : FAT12_FILE_SYSTEM_TYPE); +} + +uint16_t fat_sectors_per_alloc_table(uint32_t sector_num, bool fat16) { + if (fat16) { + return fat16_sectors_per_alloc_table(sector_num); + } + return fat12_sectors_per_alloc_table(sector_num); +} + +uint8_t *fat_add_table(uint8_t *dst, fat_boot_sector_t *boot, bool fat16) { + if (fat16) { + return fat16_add_table(dst, boot); + } + return fat12_add_table(dst, boot); +} + +void fat_set_table_index(uint8_t *table, uint16_t index, uint16_t value, bool fat16) { + if (fat16) { + fat16_set_table_index(table, index, value); + } else { + fat12_set_table_index(table, index, value); + } +} + +fat_boot_sector_t *fat_add_boot_sector( + uint8_t *dst, uint16_t sector_num, uint16_t table_sectors, const char *file_system_type, const char *volume_label, uint32_t serial_number +) { + fat_boot_sector_t *boot = (fat_boot_sector_t *)dst; + boot->jump_instruction[0] = 0xEB; + boot->jump_instruction[1] = 0x3C; + boot->jump_instruction[2] = 0x90; + cplstr(boot->oem_name, "MSDOS5.0", 8); + boot->bytes_per_sector = DISK_SECTOR_SIZE; + boot->sectors_per_cluster = 1; + boot->reserved_sectors_count = 1; + boot->file_alloc_tables_num = 1; + boot->max_root_dir_entries = 16; + boot->fat12_sector_num = sector_num; + boot->media_descriptor = 0xF8; + boot->sectors_per_alloc_table = table_sectors; + boot->sectors_per_track = 1; + boot->num_heads = 1; + boot->hidden_sectors_count = 0; + boot->total_sectors_32 = 0; + boot->physical_drive_number = 0x80; + boot->reserved0 = 0x00; + boot->extended_boot_signature = 0x29; + boot->serial_number = serial_number; + cplstrsp(boot->volume_label, volume_label, 11); + memset(boot->reserved, 0, 448); + cplstrsp(boot->file_system_type, file_system_type, 8); + boot->signature = 0xAA55; + return boot; +} + +fat_dir_entry_t *fat_add_label(uint8_t *dst, const char *volume_label) { + fat_boot_sector_t *boot = (fat_boot_sector_t *)dst; + fat_dir_entry_t *entry = (fat_dir_entry_t *)(dst + ((boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE)); + memset(entry, 0, sizeof(fat_dir_entry_t)); + cplstrsp(entry->volume_label, volume_label, 11); + entry->file_attr = FAT_FILE_ATTR_VOLUME_LABEL; + return entry; +} + +fat_dir_entry_t *fat_add_root_file( + uint8_t *dst, uint8_t index, const char *file_name, const char *file_extension, size_t file_size, uint16_t data_start_sector, bool is_fat16 +) { + fat_boot_sector_t *boot = (fat_boot_sector_t *)dst; + uint8_t *table = dst + DISK_SECTOR_SIZE; + fat_dir_entry_t *entry = (fat_dir_entry_t *)(dst + ((boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE) + (index * sizeof(fat_dir_entry_t))); + memset(entry, 0, sizeof(fat_dir_entry_t)); + cplstrsp(entry->file_name, file_name, 8); + cplstrsp(entry->file_extension, file_extension, 3); + entry->file_attr = FAT_FILE_ATTR_ARCHIVE; + entry->file_size = file_size; + entry->data_start_sector = data_start_sector; + entry->extended_attr = 0; + + uint16_t file_sectors = file_size / DISK_SECTOR_SIZE; + if (file_size % DISK_SECTOR_SIZE) { + file_sectors++; + } + + uint16_t data_end_sector = data_start_sector + file_sectors; + for (uint16_t i = data_start_sector; i < (data_end_sector - 1); i++) { + fat_set_table_index(table, i, i + 1, is_fat16); + } + fat_set_table_index(table, data_end_sector - 1, 0xFFFF, is_fat16); + + //Set Firmware Date based on the build time + static const char *month_names_short[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"}; + char mstr[8] = { + '\0', + }; + const char *str = __DATE__ " " __TIME__; + int ms = 0, seconds = 0, minutes = 0, hours = 0, year = 0, date = 0, month = 0; + int r = sscanf(str, "%s %d %d %d:%d:%d", mstr, &date, &year, &hours, &minutes, &seconds); + if (r >= 0) { + for (int i = 0; i < 12; i++) { + if (!strcmp(mstr, month_names_short[i])) { + month = i; + break; + } + } + entry->creation_time_ms = FAT_MS2V(seconds, ms); + entry->creation_time_hms = FAT_HMS2V(hours, minutes, seconds); + entry->creation_time_ymd = FAT_YMD2V(year, month, date); + entry->last_access_ymd = entry->creation_time_ymd; + entry->last_modified_hms = entry->creation_time_hms; + entry->last_modified_ymd = entry->creation_time_ymd; + } + return entry; +} + +uint8_t fat_lfn_checksum(const uint8_t *short_filename) { + uint8_t sum = 0; + for (uint8_t i = 11; i; i--) { + sum = ((sum & 1) << 7) + (sum >> 1) + *short_filename++; + } + return sum; +} diff --git a/cores/esp32/firmware_msc_fat.h b/cores/esp32/firmware_msc_fat.h new file mode 100644 index 0000000..a88e051 --- /dev/null +++ b/cores/esp32/firmware_msc_fat.h @@ -0,0 +1,145 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define FAT_U8(v) ((v) & 0xFF) +#define FAT_U16(v) FAT_U8(v), FAT_U8((v) >> 8) +#define FAT_U32(v) FAT_U8(v), FAT_U8((v) >> 8), FAT_U8((v) >> 16), FAT_U8((v) >> 24) + +#define FAT12_TBL2B(l, h) FAT_U8(l), FAT_U8(((l >> 8) & 0xF) | ((h << 4) & 0xF0)), FAT_U8(h >> 4) + +#define FAT_MS2B(s, ms) FAT_U8(((((s) & 0x1) * 1000) + (ms)) / 10) +#define FAT_HMS2B(h, m, s) FAT_U8(((s) >> 1) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x7) | ((h) << 3)) +#define FAT_YMD2B(y, m, d) FAT_U8(((d) & 0x1F) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x1) | ((((y) - 1980) & 0x7F) << 1)) + +#define FAT_MS2V(s, ms) FAT_U8(((((s) & 0x1) * 1000) + (ms)) / 10) +#define FAT_HMS2V(h, m, s) (FAT_U8(((s) >> 1) | (((m) & 0x7) << 5)) | (FAT_U8((((m) >> 3) & 0x7) | ((h) << 3)) << 8)) +#define FAT_YMD2V(y, m, d) (FAT_U8(((d) & 0x1F) | (((m) & 0x7) << 5)) | (FAT_U8((((m) >> 3) & 0x1) | ((((y) - 1980) & 0x7F) << 1)) << 8)) + +#define FAT_B2HMS(hms) ((hms >> 11) & 0x1F), ((hms >> 5) & 0x3F), ((hms & 0x1F) << 1) +#define FAT_B2YMD(ymd) (((ymd >> 9) & 0x7F) + 1980), ((ymd >> 5) & 0x0F), (ymd & 0x1F) + +#define FAT_FILE_ATTR_READ_ONLY 0x01 +#define FAT_FILE_ATTR_HIDDEN 0x02 +#define FAT_FILE_ATTR_SYSTEM 0x04 +#define FAT_FILE_ATTR_VOLUME_LABEL 0x08 +#define FAT_FILE_ATTR_SUBDIRECTORY 0x10 +#define FAT_FILE_ATTR_ARCHIVE 0x20 +#define FAT_FILE_ATTR_DEVICE 0x40 + +static const uint16_t DISK_SECTOR_SIZE = 512; + +#define FAT_SIZE_TO_SECTORS(bytes) ((bytes) / DISK_SECTOR_SIZE) + (((bytes) % DISK_SECTOR_SIZE) ? 1 : 0) + +typedef struct __attribute__((packed)) { + uint8_t jump_instruction[3]; + char oem_name[8]; //padded with spaces (0x20) + uint16_t bytes_per_sector; //DISK_SECTOR_SIZE usually 512 + uint8_t sectors_per_cluster; //Allowed values are 1, 2, 4, 8, 16, 32, 64, and 128 + uint16_t reserved_sectors_count; //At least 1 for this sector, usually 32 for FAT32 + uint8_t file_alloc_tables_num; //Almost always 2; RAM disks might use 1 + uint16_t max_root_dir_entries; //FAT12 and FAT16 + uint16_t fat12_sector_num; //DISK_SECTOR_NUM FAT12 and FAT16 + uint8_t media_descriptor; + uint16_t sectors_per_alloc_table; //FAT12 and FAT16 + uint16_t sectors_per_track; //A value of 0 may indicate LBA-only access + uint16_t num_heads; + uint32_t hidden_sectors_count; + uint32_t total_sectors_32; + uint8_t physical_drive_number; //0x00 for (first) removable media, 0x80 for (first) fixed disk + uint8_t reserved0; + uint8_t extended_boot_signature; //should be 0x29 + uint32_t serial_number; //0x1234 => 1234 + char volume_label[11]; //padded with spaces (0x20) + char file_system_type[8]; //padded with spaces (0x20) + uint8_t reserved[448]; + uint16_t signature; //should be 0xAA55 +} fat_boot_sector_t; + +typedef struct __attribute__((packed)) { + union { + struct { + char file_name[8]; //padded with spaces (0x20) + char file_extension[3]; //padded with spaces (0x20) + }; + struct { + uint8_t file_magic; // 0xE5:deleted, 0x05:will_be_deleted, 0x00:end_marker, 0x2E:dot_marker(. or ..) + char file_magic_data[10]; + }; + char volume_label[11]; //padded with spaces (0x20) + }; + uint8_t file_attr; //mask of FAT_FILE_ATTR_* + uint8_t reserved; //always 0 + uint8_t creation_time_ms; //ms * 10; max 1990 (1s 990ms) + uint16_t creation_time_hms; // [5:6:5] => h:m:(s/2) + uint16_t creation_time_ymd; // [7:4:5] => (y+1980):m:d + uint16_t last_access_ymd; + uint16_t extended_attr; + uint16_t last_modified_hms; + uint16_t last_modified_ymd; + uint16_t data_start_sector; + uint32_t file_size; +} fat_dir_entry_t; + +typedef struct __attribute__((packed)) { + union { + struct { + uint8_t number : 5; + uint8_t reserved0 : 1; + uint8_t llfp : 1; + uint8_t reserved1 : 1; + } seq; + uint8_t seq_num; //0xE5: Deleted Entry + }; + uint16_t name0[5]; + uint8_t attr; //ALWAYS 0x0F + uint8_t type; //ALWAYS 0x00 + uint8_t dos_checksum; + uint16_t name1[6]; + uint16_t first_cluster; //ALWAYS 0x0000 + uint16_t name2[2]; +} fat_lfn_entry_t; + +typedef union { + fat_dir_entry_t dir; + fat_lfn_entry_t lfn; +} fat_entry_t; + +const char *fat_file_system_type(bool fat16); +uint16_t fat_sectors_per_alloc_table(uint32_t sector_num, bool fat16); +uint8_t *fat_add_table(uint8_t *dst, fat_boot_sector_t *boot, bool fat16); +void fat_set_table_index(uint8_t *table, uint16_t index, uint16_t value, bool fat16); +fat_boot_sector_t *fat_add_boot_sector( + uint8_t *dst, uint16_t sector_num, uint16_t table_sectors, const char *file_system_type, const char *volume_label, uint32_t serial_number +); +fat_dir_entry_t *fat_add_label(uint8_t *dst, const char *volume_label); +fat_dir_entry_t *fat_add_root_file( + uint8_t *dst, uint8_t index, const char *file_name, const char *file_extension, size_t file_size, uint16_t data_start_sector, bool is_fat16 +); +uint8_t fat_lfn_checksum(const uint8_t *short_filename); + +#ifdef __cplusplus +} +#endif diff --git a/cores/esp32/freertos_stats.cpp b/cores/esp32/freertos_stats.cpp new file mode 100644 index 0000000..b37a520 --- /dev/null +++ b/cores/esp32/freertos_stats.cpp @@ -0,0 +1,112 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "freertos_stats.h" +#include "sdkconfig.h" + +#if CONFIG_FREERTOS_USE_TRACE_FACILITY +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/portable.h" +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ + +void printRunningTasks(Print &printer) { +#if CONFIG_FREERTOS_USE_TRACE_FACILITY +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS +#define FREERTOS_TASK_NUMBER_MAX_NUM 256 // RunTime stats for how many Tasks to be stored + static configRUN_TIME_COUNTER_TYPE ulRunTimeCounters[FREERTOS_TASK_NUMBER_MAX_NUM]; + static configRUN_TIME_COUNTER_TYPE ulLastRunTime = 0; + configRUN_TIME_COUNTER_TYPE ulCurrentRunTime = 0, ulTaskRunTime = 0; +#endif + configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0; + TaskStatus_t *pxTaskStatusArray = NULL; + volatile UBaseType_t uxArraySize = 0; + uint32_t x = 0; + const char *taskStates[] = {"Running", "Ready", "Blocked", "Suspended", "Deleted", "Invalid"}; + + // Take a snapshot of the number of tasks in case it changes while this function is executing. + uxArraySize = uxTaskGetNumberOfTasks(); + + // Allocate a TaskStatus_t structure for each task. + pxTaskStatusArray = (TaskStatus_t *)pvPortMalloc(uxArraySize * sizeof(TaskStatus_t)); + + if (pxTaskStatusArray != NULL) { + // Generate raw status information about each task. + uxArraySize = uxTaskGetSystemState(pxTaskStatusArray, uxArraySize, &ulTotalRunTime); + +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + ulCurrentRunTime = ulTotalRunTime - ulLastRunTime; + ulLastRunTime = ulTotalRunTime; +#endif + printer.printf( + "Tasks: %u" +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + ", Runtime: %lus, Period: %luus" +#endif + "\n", + uxArraySize +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + , + ulTotalRunTime / 1000000, ulCurrentRunTime +#endif + ); + printer.printf("Num\t Name" +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + "\tLoad" +#endif + "\tPrio\t Free" +#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + "\tCore" +#endif + "\tState\r\n"); + for (x = 0; x < uxArraySize; x++) { +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + if (pxTaskStatusArray[x].xTaskNumber < FREERTOS_TASK_NUMBER_MAX_NUM) { + ulTaskRunTime = (pxTaskStatusArray[x].ulRunTimeCounter - ulRunTimeCounters[pxTaskStatusArray[x].xTaskNumber]); + ulRunTimeCounters[pxTaskStatusArray[x].xTaskNumber] = pxTaskStatusArray[x].ulRunTimeCounter; + ulTaskRunTime = (ulTaskRunTime * 100) / ulCurrentRunTime; // in percentage + } else { + ulTaskRunTime = 0; + } +#endif + printer.printf( + "%3u\t%16s" +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + "\t%3lu%%" +#endif + "\t%4u\t%5lu" +#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + "\t%4c" +#endif + "\t%s\r\n", + pxTaskStatusArray[x].xTaskNumber, pxTaskStatusArray[x].pcTaskName, +#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS + ulTaskRunTime, +#endif + pxTaskStatusArray[x].uxCurrentPriority, pxTaskStatusArray[x].usStackHighWaterMark, +#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID + (pxTaskStatusArray[x].xCoreID == tskNO_AFFINITY) ? '*' : ('0' + pxTaskStatusArray[x].xCoreID), +#endif + taskStates[pxTaskStatusArray[x].eCurrentState] + ); + } + + // The array is no longer needed, free the memory it consumes. + vPortFree(pxTaskStatusArray); + printer.println(); + } +#else + printer.println("FreeRTOS trace facility is not enabled."); +#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */ +} diff --git a/cores/esp32/freertos_stats.h b/cores/esp32/freertos_stats.h new file mode 100644 index 0000000..ea9e1a5 --- /dev/null +++ b/cores/esp32/freertos_stats.h @@ -0,0 +1,28 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus + +#include "Print.h" + +/* + * Executing this function will cause interrupts and + * the scheduler to be blocked for some time. + * Please use only for debugging purposes. + */ +void printRunningTasks(Print &printer); + +#endif diff --git a/cores/esp32/idf_openthread_mpool_wrapper.c b/cores/esp32/idf_openthread_mpool_wrapper.c new file mode 100644 index 0000000..0b547c8 --- /dev/null +++ b/cores/esp32/idf_openthread_mpool_wrapper.c @@ -0,0 +1,147 @@ +// Copyright 2024-2026 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* + * OpenThread message pool platform wrapper (core). + * + * Provides __wrap_otPlatMessagePool* so that any build that links libopenthread + * (OpenThread library, Matter/esp_matter, etc.) gets correct allocation + * via -Wl,--wrap=... in platform.txt. + * + * Pool size matches IDF OpenThread Kconfig: + * - CONFIG_OPENTHREAD_NUM_MESSAGE_BUFFERS default 1024 when platform pool from PSRAM + * - CONFIG_OPENTHREAD_NUM_MESSAGE_BUFFERS default 65 when not (internal RAM) + * So: BOARD_HAS_PSRAM -> use requested size (1024 buffers); otherwise -> 65 buffers. + * Buffer size (aBufferSize) is unchanged; only the number of buffers is reduced + * when PSRAM is disabled. + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" + +#if SOC_IEEE802154_SUPPORTED +#if CONFIG_OPENTHREAD_ENABLED +/* + * BOARD_HAS_PSRAM is defined by the Arduino build system (boards.txt) when the + * user selects "PSRAM: Enabled" in the board menu (-DBOARD_HAS_PSRAM). + */ + +#include +#include +#include + +#include "esp_heap_caps.h" +#include "esp_log.h" +#include "openthread/instance.h" +#include "openthread/platform/messagepool.h" + +#define OT_MPOOL_TAG "OPENTHREAD" + +/* Match IDF Kconfig: 65 buffers when not using PSRAM for message pool */ +/* from IDF 5.5.2 openthread component kconfig: + config OPENTHREAD_NUM_MESSAGE_BUFFERS + int "The number of openthread message buffers" + default 65 if !OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT + default 1024 if OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT +*/ +#define OT_MPOOL_NUM_BUFFERS_NO_PSRAM 65 + +static int s_buffer_pool_head = -1; +static otMessageBuffer **s_buffer_pool_pointer = NULL; +static otMessageBuffer *s_buffer_pool = NULL; + +void __wrap_otPlatMessagePoolInit(otInstance *aInstance, uint16_t aMinNumFreeBuffers, size_t aBufferSize) { + (void)aInstance; + + uint16_t num_buffers; + +#ifdef BOARD_HAS_PSRAM + const uint32_t mem_caps = MALLOC_CAP_SPIRAM; + const char *mem_type = "PSRAM"; + num_buffers = aMinNumFreeBuffers; + ESP_LOGD(OT_MPOOL_TAG, "OpenThread Message buffer pool: %u buffers, %u bytes (PSRAM)", num_buffers, (unsigned)(num_buffers * aBufferSize)); +#else + const uint32_t mem_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT; + const char *mem_type = "internal RAM"; + num_buffers = (aMinNumFreeBuffers > OT_MPOOL_NUM_BUFFERS_NO_PSRAM) ? OT_MPOOL_NUM_BUFFERS_NO_PSRAM : aMinNumFreeBuffers; + ESP_LOGD(OT_MPOOL_TAG, "OpenThread Message buffer pool: %u buffers, %u bytes (internal RAM)", num_buffers, (unsigned)(num_buffers * aBufferSize)); +#endif + + otMessageBuffer *buffer_pool = (otMessageBuffer *)heap_caps_calloc(num_buffers, aBufferSize, mem_caps); + s_buffer_pool_pointer = (otMessageBuffer **)heap_caps_calloc(num_buffers, sizeof(otMessageBuffer *), mem_caps); + + if (buffer_pool == NULL || s_buffer_pool_pointer == NULL) { + ESP_LOGE( + OT_MPOOL_TAG, "Failed to allocate message buffer pool from %s (%u buffers x %u bytes = %u bytes)", mem_type, num_buffers, (unsigned)aBufferSize, + (unsigned)(num_buffers * aBufferSize) + ); + if (buffer_pool) { + heap_caps_free(buffer_pool); + } + if (s_buffer_pool_pointer) { + heap_caps_free(s_buffer_pool_pointer); + s_buffer_pool_pointer = NULL; + } + assert(false); + return; + } + + for (uint16_t i = 0; i < num_buffers; i++) { + s_buffer_pool_pointer[i] = (otMessageBuffer *)((uint8_t *)buffer_pool + i * aBufferSize); + } + s_buffer_pool_head = (int)num_buffers - 1; + s_buffer_pool = buffer_pool; + ESP_LOGI(OT_MPOOL_TAG, "Message buffer pool: %u buffers, %u bytes (%s)", num_buffers, (unsigned)(num_buffers * aBufferSize), mem_type); +} + +otMessageBuffer *__wrap_otPlatMessagePoolNew(otInstance *aInstance) { + (void)aInstance; + + otMessageBuffer *ret = NULL; + if (s_buffer_pool_head >= 0) { + ret = s_buffer_pool_pointer[s_buffer_pool_head]; + s_buffer_pool_head--; + } + return ret; +} + +void __wrap_otPlatMessagePoolFree(otInstance *aInstance, otMessageBuffer *aBuffer) { + (void)aInstance; + + s_buffer_pool_head++; + s_buffer_pool_pointer[s_buffer_pool_head] = aBuffer; +} + +uint16_t __wrap_otPlatMessagePoolNumFreeBuffers(otInstance *aInstance) { + (void)aInstance; + + return s_buffer_pool_head + 1; +} + +void __wrap_otPlatMessagePoolDeinit(otInstance *aInstance) { + (void)aInstance; + + if (s_buffer_pool_pointer != NULL) { + heap_caps_free(s_buffer_pool_pointer); + s_buffer_pool_pointer = NULL; + } + if (s_buffer_pool != NULL) { + heap_caps_free(s_buffer_pool); + s_buffer_pool = NULL; + } + s_buffer_pool_head = -1; +} + +#endif /* CONFIG_OPENTHREAD_ENABLED */ +#endif /* SOC_IEEE802154_SUPPORTED */ diff --git a/cores/esp32/io_pin_remap.h b/cores/esp32/io_pin_remap.h new file mode 100644 index 0000000..10f11a5 --- /dev/null +++ b/cores/esp32/io_pin_remap.h @@ -0,0 +1,137 @@ +#ifndef __IO_PIN_REMAP_H__ +#define __IO_PIN_REMAP_H__ + +#include "Arduino.h" + +#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS) + +// Pin remapping functions +int8_t digitalPinToGPIONumber(int8_t digitalPin); +int8_t gpioNumberToDigitalPin(int8_t gpioNumber); + +// Apply pin remapping to API only when building libraries and user sketch +#ifndef ARDUINO_CORE_BUILD + +// Override APIs requiring pin remapping + +// cores/esp32/Arduino.h +#define pulseInLong(pin, args...) pulseInLong(digitalPinToGPIONumber(pin), args) +#define pulseIn(pin, args...) pulseIn(digitalPinToGPIONumber(pin), args) +#define noTone(_pin) noTone(digitalPinToGPIONumber(_pin)) +#define tone(_pin, args...) tone(digitalPinToGPIONumber(_pin), args) + +// cores/esp32/esp32-hal.h +#define analogGetChannel(pin) analogGetChannel(digitalPinToGPIONumber(pin)) +#define analogWrite(pin, value) analogWrite(digitalPinToGPIONumber(pin), value) +#define analogWriteFrequency(pin, freq) analogWriteFrequency(digitalPinToGPIONumber(pin), freq) +#define analogWriteResolution(pin, bits) analogWriteResolution(digitalPinToGPIONumber(pin), bits) + +// cores/esp32/esp32-hal-adc.h +#define analogRead(pin) analogRead(digitalPinToGPIONumber(pin)) +#define analogReadMilliVolts(pin) analogReadMilliVolts(digitalPinToGPIONumber(pin)) +#define analogSetPinAttenuation(pin, attenuation) analogSetPinAttenuation(digitalPinToGPIONumber(pin), attenuation) + +// cores/esp32/esp32-hal-dac.h +#define dacDisable(pin) dacDisable(digitalPinToGPIONumber(pin)) +#define dacWrite(pin, value) dacWrite(digitalPinToGPIONumber(pin), value) + +// cores/esp32/esp32-hal-gpio.h +#define analogChannelToDigitalPin(channel) gpioNumberToDigitalPin(analogChannelToDigitalPin(channel)) +#define digitalPinToAnalogChannel(pin) digitalPinToAnalogChannel(digitalPinToGPIONumber(pin)) +#define digitalPinToTouchChannel(pin) digitalPinToTouchChannel(digitalPinToGPIONumber(pin)) +#define digitalRead(pin) digitalRead(digitalPinToGPIONumber(pin)) +#define attachInterruptArg(pin, fcn, arg, mode) attachInterruptArg(digitalPinToGPIONumber(pin), fcn, arg, mode) +#define attachInterrupt(pin, fcn, mode) attachInterrupt(digitalPinToGPIONumber(pin), fcn, mode) +#define detachInterrupt(pin) detachInterrupt(digitalPinToGPIONumber(pin)) +#define digitalWrite(pin, val) digitalWrite(digitalPinToGPIONumber(pin), val) +#define pinMode(pin, mode) pinMode(digitalPinToGPIONumber(pin), mode) + +// cores/esp32/esp32-hal-i2c.h +#define i2cInit(i2c_num, sda, scl, clk_speed) i2cInit(i2c_num, digitalPinToGPIONumber(sda), digitalPinToGPIONumber(scl), clk_speed) + +// cores/esp32/esp32-hal-i2c-slave.h +#define i2cSlaveInit(num, sda, scl, slaveID, frequency, rx_len, tx_len) \ + i2cSlaveInit(num, digitalPinToGPIONumber(sda), digitalPinToGPIONumber(scl), slaveID, frequency, rx_len, tx_len) + +// cores/esp32/esp32-hal-ledc.h +#define ledcAttach(pin, freq, resolution) ledcAttach(digitalPinToGPIONumber(pin), freq, resolution) +#define ledcAttachChannel(pin, freq, resolution, channel) ledcAttachChannel(digitalPinToGPIONumber(pin), freq, resolution, channel) +#define ledcWrite(pin, duty) ledcWrite(digitalPinToGPIONumber(pin), duty) +#define ledcWriteTone(pin, freq) ledcWriteTone(digitalPinToGPIONumber(pin), freq) +#define ledcWriteNote(pin, note, octave) ledcWriteNote(digitalPinToGPIONumber(pin), note, octave) +#define ledcRead(pin) ledcRead(digitalPinToGPIONumber(pin)) +#define ledcReadFreq(pin) ledcReadFreq(digitalPinToGPIONumber(pin)) +#define ledcDetach(pin) ledcDetach(digitalPinToGPIONumber(pin)) +#define ledcChangeFrequency(pin, freq, resolution) ledcChangeFrequency(digitalPinToGPIONumber(pin), freq, resolution) +#define ledcOutputInvert(pin, out_invert) ledcOutputInvert(digitalPinToGPIONumber(pin), out_invert) + +#define ledcFade(pin, start_duty, target_duty, max_fade_time_ms) ledcFade(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms) +#define ledcFadeWithInterrupt(pin, start_duty, target_duty, max_fade_time_ms, userFunc) \ + ledcFadeWithInterrupt(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms, userFunc) +#define ledcFadeWithInterruptArg(pin, start_duty, target_duty, max_fade_time_ms, userFunc, arg) \ + ledcFadeWithInterruptArg(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms, userFunc, arg) + +// cores/esp32/esp32-hal-matrix.h +#define pinMatrixInAttach(pin, signal, inverted) pinMatrixInAttach(digitalPinToGPIONumber(pin), signal, inverted) +#define pinMatrixOutAttach(pin, function, invertOut, invertEnable) pinMatrixOutAttach(digitalPinToGPIONumber(pin), function, invertOut, invertEnable) +#define pinMatrixOutDetach(pin, invertOut, invertEnable) pinMatrixOutDetach(digitalPinToGPIONumber(pin), invertOut, invertEnable) + +// cores/esp32/esp32-hal-rgb-led.h +#define rgbLedWrite(pin, red_val, green_val, blue_val) rgbLedWrite(digitalPinToGPIONumber(pin), red_val, green_val, blue_val) + +// cores/esp32/esp32-hal-rmt.h +#define rmtInit(pin, channel_direction, memsize, frequency_Hz) rmtInit(digitalPinToGPIONumber(pin), channel_direction, memsize, frequency_Hz) +#define rmtSetEOT(pin, EOT_Level) rmtSetEOT(digitalPinToGPIONumber(pin), EOT_Level) +#define rmtWrite(pin, data, num_rmt_symbols, timeout_ms) rmtWrite(digitalPinToGPIONumber(pin), data, num_rmt_symbols, timeout_ms) +#define rmtWriteAsync(pin, data, num_rmt_symbols) rmtWriteAsync(digitalPinToGPIONumber(pin), data, num_rmt_symbols) +#define rmtWriteLooping(pin, data, num_rmt_symbols) rmtWriteLooping(digitalPinToGPIONumber(pin), data, num_rmt_symbols) +#define rmtTransmitCompleted(pin) rmtTransmitCompleted(digitalPinToGPIONumber(pin)) +#define rmtRead(pin, data, num_rmt_symbols, timeout_ms) rmtRead(digitalPinToGPIONumber(pin), data, num_rmt_symbols, timeout_ms) +#define rmtReadAsync(pin, data, num_rmt_symbols) rmtReadAsync(digitalPinToGPIONumber(pin), data, num_rmt_symbols) +#define rmtReceiveCompleted(pin) rmtReceiveCompleted(digitalPinToGPIONumber(pin)) +#define rmtSetRxMaxThreshold(pin, idle_thres_ticks) rmtSetRxMaxThreshold(digitalPinToGPIONumber(pin), idle_thres_ticks) +#define rmtSetCarrier(pin, carrier_en, carrier_level, frequency_Hz, duty_percent) \ + rmtSetCarrier(digitalPinToGPIONumber(pin), carrier_en, carrier_level, frequency_Hz, duty_percent) +#define rmtSetRxMinThreshold(pin, filter_pulse_ticks) rmtSetRxMinThreshold(digitalPinToGPIONumber(pin), filter_pulse_ticks) +#define rmtDeinit(pin) rmtDeinit(digitalPinToGPIONumber(pin)) + +// cores/esp32/esp32-hal-sigmadelta.h +#define sigmaDeltaAttach(pin, freq) sigmaDeltaAttach(digitalPinToGPIONumber(pin), freq) +#define sigmaDeltaWrite(pin, duty) sigmaDeltaWrite(digitalPinToGPIONumber(pin), duty) +#define sigmaDeltaDetach(pin) sigmaDeltaDetach(digitalPinToGPIONumber(pin)) + +// cores/esp32/esp32-hal-spi.h +#define spiAttachSCK(spi, sck) spiAttachSCK(spi, digitalPinToGPIONumber(sck)) +#define spiAttachMISO(spi, miso) spiAttachMISO(spi, digitalPinToGPIONumber(miso)) +#define spiAttachMOSI(spi, mosi) spiAttachMOSI(spi, digitalPinToGPIONumber(mosi)) +#define spiAttachSS(spi, cs_num, ss) spiAttachSS(spi, cs_num, digitalPinToGPIONumber(ss)) + +// cores/esp32/esp32-hal-touch.h && cores/esp32/esp32-hal-touch-ng.h +#define touchInterruptGetLastStatus(pin) touchInterruptGetLastStatus(digitalPinToGPIONumber(pin)) +#define touchRead(pin) touchRead(digitalPinToGPIONumber(pin)) +#define touchAttachInterruptArg(pin, userFunc, arg, threshold) touchAttachInterruptArg(digitalPinToGPIONumber(pin), userFunc, arg, threshold) +#define touchAttachInterrupt(pin, userFunc, threshold) touchAttachInterrupt(digitalPinToGPIONumber(pin), userFunc, threshold) +#define touchDetachInterrupt(pin) touchDetachInterrupt(digitalPinToGPIONumber(pin)) +#define touchSleepWakeUpEnable(pin, threshold) touchSleepWakeUpEnable(digitalPinToGPIONumber(pin), threshold) + +// cores/esp32/esp32-hal-uart.h +#define uartBegin(uart_nr, baudrate, config, rxPin, txPin, rx_buffer_size, tx_buffer_size, inverted, rxfifo_full_thrhd) \ + uartBegin( \ + uart_nr, baudrate, config, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), rx_buffer_size, tx_buffer_size, inverted, rxfifo_full_thrhd \ + ) +#define uartSetPins(uart, rxPin, txPin, ctsPin, rtsPin) \ + uartSetPins(uart, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), digitalPinToGPIONumber(ctsPin), digitalPinToGPIONumber(rtsPin)) +#define uartDetachPins(uart, rxPin, txPin, ctsPin, rtsPin) \ + uartDetachPins(uart, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), digitalPinToGPIONumber(ctsPin), digitalPinToGPIONumber(rtsPin)) + +#endif // ARDUINO_CORE_BUILD + +#else + +// pin remapping disabled: use stubs +#define digitalPinToGPIONumber(digitalPin) (digitalPin) +#define gpioNumberToDigitalPin(gpioNumber) (gpioNumber) + +#endif + +#endif /* __GPIO_PIN_REMAP_H__ */ diff --git a/cores/esp32/libb64/AUTHORS b/cores/esp32/libb64/AUTHORS new file mode 100644 index 0000000..af68737 --- /dev/null +++ b/cores/esp32/libb64/AUTHORS @@ -0,0 +1,7 @@ +libb64: Base64 Encoding/Decoding Routines +====================================== + +Authors: +------- + +Chris Venter chris.venter@gmail.com http://rocketpod.blogspot.com diff --git a/cores/esp32/libb64/LICENSE b/cores/esp32/libb64/LICENSE new file mode 100644 index 0000000..ae8a7b9 --- /dev/null +++ b/cores/esp32/libb64/LICENSE @@ -0,0 +1,29 @@ +Copyright-Only Dedication (based on United States law) +or Public Domain Certification + +The person or persons who have associated work with this document (the +"Dedicator" or "Certifier") hereby either (a) certifies that, to the best of +his knowledge, the work of authorship identified is in the public domain of the +country from which the work is published, or (b) hereby dedicates whatever +copyright the dedicators holds in the work of authorship identified below (the +"Work") to the public domain. A certifier, moreover, dedicates any copyright +interest he may have in the associated work, and for these purposes, is +described as a "dedicator" below. + +A certifier has taken reasonable steps to verify the copyright status of this +work. Certifier recognizes that his good faith efforts may not shield him from +liability if in fact the work certified is not in the public domain. + +Dedicator makes this dedication for the benefit of the public at large and to +the detriment of the Dedicator's heirs and successors. Dedicator intends this +dedication to be an overt act of relinquishment in perpetuity of all present +and future rights under copyright law, whether vested or contingent, in the +Work. Dedicator understands that such relinquishment of all rights includes +the relinquishment of all rights to enforce (by lawsuit or otherwise) those +copyrights in the Work. + +Dedicator recognizes that, once placed in the public domain, the Work may be +freely reproduced, distributed, transmitted, used, modified, built upon, or +otherwise exploited by anyone for any purpose, commercial or non-commercial, +and in any way, including by methods that have not yet been invented or +conceived. diff --git a/cores/esp32/libb64/cdecode.c b/cores/esp32/libb64/cdecode.c new file mode 100644 index 0000000..2485397 --- /dev/null +++ b/cores/esp32/libb64/cdecode.c @@ -0,0 +1,108 @@ +/* +cdecoder.c - c source to a base64 decoding algorithm implementation + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#include "cdecode.h" +#include + +static int base64_decode_value_signed(int8_t value_in) { + static const int8_t decoding[] = {62, -1, -1, -1, 63, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, -1, -1, -1, -2, -1, -1, -1, 0, 1, 2, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, -1, -1, -1, -1, -1, -1, + 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51}; + static const int8_t decoding_size = sizeof(decoding); + value_in -= 43; + if (value_in < 0 || value_in >= decoding_size) { + return -1; + } + return decoding[(int)value_in]; +} + +void base64_init_decodestate(base64_decodestate *state_in) { + state_in->step = step_a; + state_in->plainchar = 0; +} + +static int base64_decode_block_signed(const int8_t *code_in, const int length_in, int8_t *plaintext_out, base64_decodestate *state_in) { + const int8_t *codechar = code_in; + int8_t *plainchar = plaintext_out; + int8_t fragment; + + *plainchar = state_in->plainchar; + + switch (state_in->step) { + while (1) { + case step_a: + do { + if (codechar == code_in + length_in) { + state_in->step = step_a; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (int8_t)base64_decode_value_signed(*codechar++); + } while (fragment < 0); + *plainchar = (fragment & 0x03f) << 2; + // fall through + case step_b: + do { + if (codechar == code_in + length_in) { + state_in->step = step_b; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (int8_t)base64_decode_value_signed(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x030) >> 4; + *plainchar = (fragment & 0x00f) << 4; + // fall through + case step_c: + do { + if (codechar == code_in + length_in) { + state_in->step = step_c; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (int8_t)base64_decode_value_signed(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x03c) >> 2; + *plainchar = (fragment & 0x003) << 6; + // fall through + case step_d: + do { + if (codechar == code_in + length_in) { + state_in->step = step_d; + state_in->plainchar = *plainchar; + return plainchar - plaintext_out; + } + fragment = (int8_t)base64_decode_value_signed(*codechar++); + } while (fragment < 0); + *plainchar++ |= (fragment & 0x03f); + } + } + /* control should not reach here */ + return plainchar - plaintext_out; +} + +static int base64_decode_chars_signed(const int8_t *code_in, const int length_in, int8_t *plaintext_out) { + base64_decodestate _state; + base64_init_decodestate(&_state); + int len = base64_decode_block_signed(code_in, length_in, plaintext_out, &_state); + if (len > 0) { + plaintext_out[len] = 0; + } + return len; +} + +int base64_decode_value(char value_in) { + return base64_decode_value_signed(*((int8_t *)&value_in)); +} + +int base64_decode_block(const char *code_in, const int length_in, char *plaintext_out, base64_decodestate *state_in) { + return base64_decode_block_signed((int8_t *)code_in, length_in, (int8_t *)plaintext_out, state_in); +} + +int base64_decode_chars(const char *code_in, const int length_in, char *plaintext_out) { + return base64_decode_chars_signed((int8_t *)code_in, length_in, (int8_t *)plaintext_out); +} diff --git a/cores/esp32/libb64/cdecode.h b/cores/esp32/libb64/cdecode.h new file mode 100644 index 0000000..f2ec3d6 --- /dev/null +++ b/cores/esp32/libb64/cdecode.h @@ -0,0 +1,41 @@ +/* +cdecode.h - c header for a base64 decoding algorithm + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#ifndef BASE64_CDECODE_H +#define BASE64_CDECODE_H + +#define base64_decode_expected_len(n) ((n * 3) / 4) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + step_a, + step_b, + step_c, + step_d +} base64_decodestep; + +typedef struct { + base64_decodestep step; + char plainchar; +} base64_decodestate; + +void base64_init_decodestate(base64_decodestate *state_in); + +int base64_decode_value(char value_in); + +int base64_decode_block(const char *code_in, const int length_in, char *plaintext_out, base64_decodestate *state_in); + +int base64_decode_chars(const char *code_in, const int length_in, char *plaintext_out); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* BASE64_CDECODE_H */ diff --git a/cores/esp32/libb64/cencode.c b/cores/esp32/libb64/cencode.c new file mode 100644 index 0000000..75b0f31 --- /dev/null +++ b/cores/esp32/libb64/cencode.c @@ -0,0 +1,98 @@ +/* +cencoder.c - c source to a base64 encoding algorithm implementation + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#include "cencode.h" + +void base64_init_encodestate(base64_encodestate *state_in) { + state_in->step = step_A; + state_in->result = 0; +} + +char base64_encode_value(char value_in) { + static const char *encoding = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + if (value_in > 63) { + return '='; + } + return encoding[(int)value_in]; +} + +int base64_encode_block(const char *plaintext_in, int length_in, char *code_out, base64_encodestate *state_in) { + const char *plainchar = plaintext_in; + const char *const plaintextend = plaintext_in + length_in; + char *codechar = code_out; + char result; + char fragment; + + result = state_in->result; + + switch (state_in->step) { + while (1) { + case step_A: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_A; + return codechar - code_out; + } + fragment = *plainchar++; + result = (fragment & 0x0fc) >> 2; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x003) << 4; + // fall through + case step_B: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_B; + return codechar - code_out; + } + fragment = *plainchar++; + result |= (fragment & 0x0f0) >> 4; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x00f) << 2; + // fall through + case step_C: + if (plainchar == plaintextend) { + state_in->result = result; + state_in->step = step_C; + return codechar - code_out; + } + fragment = *plainchar++; + result |= (fragment & 0x0c0) >> 6; + *codechar++ = base64_encode_value(result); + result = (fragment & 0x03f) >> 0; + *codechar++ = base64_encode_value(result); + } + } + /* control should not reach here */ + return codechar - code_out; +} + +int base64_encode_blockend(char *code_out, base64_encodestate *state_in) { + char *codechar = code_out; + + switch (state_in->step) { + case step_B: + *codechar++ = base64_encode_value(state_in->result); + *codechar++ = '='; + *codechar++ = '='; + break; + case step_C: + *codechar++ = base64_encode_value(state_in->result); + *codechar++ = '='; + break; + case step_A: break; + } + *codechar = 0x00; + + return codechar - code_out; +} + +int base64_encode_chars(const char *plaintext_in, int length_in, char *code_out) { + base64_encodestate _state; + base64_init_encodestate(&_state); + int len = base64_encode_block(plaintext_in, length_in, code_out, &_state); + return len + base64_encode_blockend((code_out + len), &_state); +} diff --git a/cores/esp32/libb64/cencode.h b/cores/esp32/libb64/cencode.h new file mode 100644 index 0000000..165220e --- /dev/null +++ b/cores/esp32/libb64/cencode.h @@ -0,0 +1,43 @@ +/* +cencode.h - c header for a base64 encoding algorithm + +This is part of the libb64 project, and has been placed in the public domain. +For details, see http://sourceforge.net/projects/libb64 +*/ + +#ifndef BASE64_CENCODE_H +#define BASE64_CENCODE_H + +#define base64_encode_expected_len(n) ((((4 * n) / 3) + 3) & ~3) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + step_A, + step_B, + step_C +} base64_encodestep; + +typedef struct { + base64_encodestep step; + char result; + int stepcount; +} base64_encodestate; + +void base64_init_encodestate(base64_encodestate *state_in); + +char base64_encode_value(char value_in); + +int base64_encode_block(const char *plaintext_in, int length_in, char *code_out, base64_encodestate *state_in); + +int base64_encode_blockend(char *code_out, base64_encodestate *state_in); + +int base64_encode_chars(const char *plaintext_in, int length_in, char *code_out); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* BASE64_CENCODE_H */ diff --git a/cores/esp32/main.cpp b/cores/esp32/main.cpp new file mode 100644 index 0000000..4d1ec77 --- /dev/null +++ b/cores/esp32/main.cpp @@ -0,0 +1,116 @@ +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_task_wdt.h" +#include "soc/rtc.h" +#include "Arduino.h" +#if (ARDUINO_USB_CDC_ON_BOOT | ARDUINO_USB_MSC_ON_BOOT | ARDUINO_USB_DFU_ON_BOOT) && !ARDUINO_USB_MODE +#include "USB.h" +#if ARDUINO_USB_MSC_ON_BOOT +#include "FirmwareMSC.h" +#endif +#endif + +#include "chip-debug-report.h" + +#ifndef ARDUINO_LOOP_STACK_SIZE +#ifndef CONFIG_ARDUINO_LOOP_STACK_SIZE +#define ARDUINO_LOOP_STACK_SIZE 8192 +#else +#define ARDUINO_LOOP_STACK_SIZE CONFIG_ARDUINO_LOOP_STACK_SIZE +#endif +#endif + +TaskHandle_t loopTaskHandle = NULL; + +#if CONFIG_AUTOSTART_ARDUINO +#if CONFIG_FREERTOS_UNICORE +void yieldIfNecessary(void) { + static uint64_t lastYield = 0; + uint64_t now = millis(); + if ((now - lastYield) > 2000) { + lastYield = now; + vTaskDelay(5); //delay 1 RTOS tick + } +} +#endif + +bool loopTaskWDTEnabled; + +__attribute__((weak)) size_t getArduinoLoopTaskStackSize(void) { + return ARDUINO_LOOP_STACK_SIZE; +} + +__attribute__((weak)) bool shouldPrintChipDebugReport(void) { + return false; +} + +// this function can be changed by the sketch using the macro SET_TIME_BEFORE_STARTING_SKETCH_MS(time_ms) +__attribute__((weak)) uint64_t getArduinoSetupWaitTime_ms(void) { + return 0; +} + +void loopTask(void *pvParameters) { + delay(getArduinoSetupWaitTime_ms()); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + printBeforeSetupInfo(); +#else + if (shouldPrintChipDebugReport()) { + printBeforeSetupInfo(); + } +#endif +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL) + // sets UART0 (default console) RX/TX pins as already configured in boot or as defined in variants/pins_arduino.h + Serial0.setPins(gpioNumberToDigitalPin(SOC_RX0), gpioNumberToDigitalPin(SOC_TX0)); + // time in ms that the sketch may wait before starting its execution - default is zero + // usually done for opening the Serial Monitor and seeing all debug messages +#endif + setup(); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + printAfterSetupInfo(); +#else + if (shouldPrintChipDebugReport()) { + printAfterSetupInfo(); + } +#endif + for (;;) { +#if CONFIG_FREERTOS_UNICORE + yieldIfNecessary(); +#endif + if (loopTaskWDTEnabled) { + esp_task_wdt_reset(); + } + loop(); + if (serialEventRun) { + serialEventRun(); + } + } +} + +extern "C" void app_main() { +#ifdef F_XTAL_MHZ +#if !CONFIG_IDF_TARGET_ESP32S2 // ESP32-S2 does not support rtc_clk_xtal_freq_update + rtc_clk_xtal_freq_update((rtc_xtal_freq_t)F_XTAL_MHZ); + rtc_clk_cpu_freq_set_xtal(); +#endif +#endif +#ifdef F_CPU + setCpuFrequencyMhz(F_CPU / 1000000); +#endif +#if ARDUINO_USB_CDC_ON_BOOT && !ARDUINO_USB_MODE + Serial.begin(); +#endif +#if ARDUINO_USB_MSC_ON_BOOT && !ARDUINO_USB_MODE + MSC_Update.begin(); +#endif +#if ARDUINO_USB_DFU_ON_BOOT && !ARDUINO_USB_MODE + USB.enableDFU(); +#endif +#if ARDUINO_USB_ON_BOOT && !ARDUINO_USB_MODE + USB.begin(); +#endif + loopTaskWDTEnabled = false; + initArduino(); + xTaskCreateUniversal(loopTask, "loopTask", getArduinoLoopTaskStackSize(), NULL, 1, &loopTaskHandle, ARDUINO_RUNNING_CORE); +} + +#endif diff --git a/cores/esp32/pgmspace.h b/cores/esp32/pgmspace.h new file mode 100644 index 0000000..4a53b1d --- /dev/null +++ b/cores/esp32/pgmspace.h @@ -0,0 +1,93 @@ +/* + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the RaspberryPi core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#ifndef PGMSPACE_INCLUDE +#define PGMSPACE_INCLUDE + +typedef void prog_void; +typedef char prog_char; +typedef unsigned char prog_uchar; +typedef char prog_int8_t; +typedef unsigned char prog_uint8_t; +typedef short prog_int16_t; +typedef unsigned short prog_uint16_t; +typedef long prog_int32_t; +typedef unsigned long prog_uint32_t; + +#define PROGMEM +#define PGM_P const char * +#define PGM_VOID_P const void * +#define PSTR(s) (s) +#define _SFR_BYTE(n) (n) + +#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) +#define pgm_read_word(addr) \ + ({ \ + typeof(addr) _addr = (addr); \ + *(const unsigned short *)(_addr); \ + }) +#define pgm_read_dword(addr) \ + ({ \ + typeof(addr) _addr = (addr); \ + *(const unsigned long *)(_addr); \ + }) +#define pgm_read_float(addr) \ + ({ \ + typeof(addr) _addr = (addr); \ + *(const float *)(_addr); \ + }) +#define pgm_read_ptr(addr) \ + ({ \ + typeof(addr) _addr = (addr); \ + *(void *const *)(_addr); \ + }) + +#define pgm_get_far_address(x) ((uint32_t)(&(x))) + +#define pgm_read_byte_near(addr) pgm_read_byte(addr) +#define pgm_read_word_near(addr) pgm_read_word(addr) +#define pgm_read_dword_near(addr) pgm_read_dword(addr) +#define pgm_read_float_near(addr) pgm_read_float(addr) +#define pgm_read_ptr_near(addr) pgm_read_ptr(addr) +#define pgm_read_byte_far(addr) pgm_read_byte(addr) +#define pgm_read_word_far(addr) pgm_read_word(addr) +#define pgm_read_dword_far(addr) pgm_read_dword(addr) +#define pgm_read_float_far(addr) pgm_read_float(addr) +#define pgm_read_ptr_far(addr) pgm_read_ptr(addr) + +#define memcmp_P memcmp +#define memccpy_P memccpy +#define memmem_P memmem +#define memcpy_P memcpy +#define strcpy_P strcpy +#define strncpy_P strncpy +#define strcat_P strcat +#define strncat_P strncat +#define strcmp_P strcmp +#define strncmp_P strncmp +#define strcasecmp_P strcasecmp +#define strncasecmp_P strncasecmp +#define strlen_P strlen +#define strnlen_P strnlen +#define strstr_P strstr +#define printf_P printf +#define sprintf_P sprintf +#define snprintf_P snprintf +#define vsnprintf_P vsnprintf + +#endif diff --git a/cores/esp32/stdlib_noniso.c b/cores/esp32/stdlib_noniso.c new file mode 100644 index 0000000..352eed4 --- /dev/null +++ b/cores/esp32/stdlib_noniso.c @@ -0,0 +1,215 @@ +/* + core_esp8266_noniso.c - nonstandard (but useful) conversion functions + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 03 April 2015 by Markus Sattler + + */ + +#include +#include +#include +#include +#include +#include "stdlib_noniso.h" +#include "esp_system.h" + +static void reverse(char *begin, char *end) { + char *is = begin; + char *ie = end - 1; + while (is < ie) { + char tmp = *ie; + *ie = *is; + *is = tmp; + ++is; + --ie; + } +} + +char *ltoa(long value, char *result, int base) { + if (base < 2 || base > 16) { + *result = 0; + return result; + } + + char *out = result; + long quotient = labs(value); + + do { + const long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while (quotient); + + // Apply negative sign + if (value < 0) { + *out++ = '-'; + } + + reverse(result, out); + *out = 0; + return result; +} + +char *lltoa(long long val, char *result, int base) { + if (base < 2 || base > 16) { + *result = 0; + return result; + } + + char *out = result; + long long quotient = val > 0 ? val : -val; + + do { + const long long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while (quotient); + + // Apply negative sign + if (val < 0) { + *out++ = '-'; + } + + reverse(result, out); + *out = 0; + return result; +} + +char *ultoa(unsigned long value, char *result, int base) { + if (base < 2 || base > 16) { + *result = 0; + return result; + } + + char *out = result; + unsigned long quotient = value; + + do { + const unsigned long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while (quotient); + + reverse(result, out); + *out = 0; + return result; +} + +char *ulltoa(unsigned long long val, char *result, int base) { + if (base < 2 || base > 16) { + *result = 0; + return result; + } + + char *out = result; + unsigned long long quotient = val; + + do { + const unsigned long long tmp = quotient / base; + *out = "0123456789abcdef"[quotient - (tmp * base)]; + ++out; + quotient = tmp; + } while (quotient); + + reverse(result, out); + *out = 0; + return result; +} + +char *dtostrf(double number, signed int width, unsigned int prec, char *s) { + bool negative = false; + + if (isnan(number)) { + strcpy(s, "nan"); + return s; + } + if (isinf(number)) { + strcpy(s, "inf"); + return s; + } + + char *out = s; + + int fillme = width; // how many cells to fill for the integer part + if (prec > 0) { + fillme -= (prec + 1); + } + + // Handle negative numbers + if (number < 0.0) { + negative = true; + fillme--; + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + // I optimized out most of the divisions + double rounding = 2.0; + for (unsigned int i = 0; i < prec; ++i) { + rounding *= 10.0; + } + rounding = 1.0 / rounding; + + number += rounding; + + // Figure out how big our number really is + double tenpow = 1.0; + unsigned int digitcount = 1; + while (number >= 10.0 * tenpow) { + tenpow *= 10.0; + digitcount++; + } + + number /= tenpow; + fillme -= digitcount; + + // Pad unused cells with spaces + while (fillme-- > 0) { + *out++ = ' '; + } + + // Handle negative sign + if (negative) { + *out++ = '-'; + } + + // Print the digits, and if necessary, the decimal point + digitcount += prec; + int8_t digit = 0; + while (digitcount-- > 0) { + digit = (int8_t)number; + if (digit > 9) { + digit = 9; // insurance + } + *out++ = (char)('0' | digit); + if ((digitcount == prec) && (prec > 0)) { + *out++ = '.'; + } + number -= digit; + number *= 10.0; + } + + // make sure the string is terminated + *out = 0; + return s; +} diff --git a/cores/esp32/stdlib_noniso.h b/cores/esp32/stdlib_noniso.h new file mode 100644 index 0000000..8c162e6 --- /dev/null +++ b/cores/esp32/stdlib_noniso.h @@ -0,0 +1,52 @@ +/* + stdlib_noniso.h - nonstandard (but useful) conversion functions + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef STDLIB_NONISO_H +#define STDLIB_NONISO_H + +#ifdef __cplusplus +extern "C" { +#endif + +int atoi(const char *s); + +long atol(const char *s); + +double atof(const char *s); + +char *itoa(int val, char *s, int radix); + +char *ltoa(long val, char *s, int radix); + +char *lltoa(long long val, char *s, int radix); + +char *utoa(unsigned int val, char *s, int radix); + +char *ultoa(unsigned long val, char *s, int radix); + +char *ulltoa(unsigned long long val, char *s, int radix); + +char *dtostrf(double val, signed int width, unsigned int prec, char *s); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/cores/esp32/wiring_private.h b/cores/esp32/wiring_private.h new file mode 100644 index 0000000..753fe40 --- /dev/null +++ b/cores/esp32/wiring_private.h @@ -0,0 +1,45 @@ +/* + wiring_private.h - Internal header file. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 239 2007-01-12 17:58:39Z mellis $ + */ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*voidFuncPtr)(void); + +void initPins(); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/cores/esp32/wiring_pulse.c b/cores/esp32/wiring_pulse.c new file mode 100644 index 0000000..1f9d175 --- /dev/null +++ b/cores/esp32/wiring_pulse.c @@ -0,0 +1,46 @@ +/* + pulse.c - wiring pulseIn implementation for esp8266 + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +//#include +#include "wiring_private.h" +#include "pins_arduino.h" +#include "esp_cpu.h" + +#define WAIT_FOR_PIN_STATE(state) \ + while (digitalRead(pin) != (state)) { \ + if (esp_cpu_get_cycle_count() - start_cycle_count > timeout_cycles) { \ + return 0; \ + } \ + } + +// max timeout is 27 seconds at 160MHz clock and 54 seconds at 80MHz clock +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) { + const uint32_t max_timeout_us = clockCyclesToMicroseconds(UINT_MAX); + if (timeout > max_timeout_us) { + timeout = max_timeout_us; + } + const uint32_t timeout_cycles = microsecondsToClockCycles(timeout); + const uint32_t start_cycle_count = esp_cpu_get_cycle_count(); + WAIT_FOR_PIN_STATE(!state); + WAIT_FOR_PIN_STATE(state); + const uint32_t pulse_start_cycle_count = esp_cpu_get_cycle_count(); + WAIT_FOR_PIN_STATE(!state); + return clockCyclesToMicroseconds(esp_cpu_get_cycle_count() - pulse_start_cycle_count); +} + +unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout) { + return pulseIn(pin, state, timeout); +} diff --git a/cores/esp32/wiring_shift.c b/cores/esp32/wiring_shift.c new file mode 100644 index 0000000..2198b2e --- /dev/null +++ b/cores/esp32/wiring_shift.c @@ -0,0 +1,53 @@ +/* + wiring_shift.c - shiftOut() function + Part of Arduino - http://www.arduino.cc/ + Copyright (c) 2005-2006 David A. Mellis + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ + */ + +#include "esp32-hal.h" +#include "wiring_private.h" + +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) { // codespell:ignore shiftin + uint8_t value = 0; + uint8_t i; + + for (i = 0; i < 8; ++i) { + //digitalWrite(clockPin, HIGH); + if (bitOrder == LSBFIRST) { + value |= digitalRead(dataPin) << i; + } else { + value |= digitalRead(dataPin) << (7 - i); + } + digitalWrite(clockPin, HIGH); + digitalWrite(clockPin, LOW); + } + return value; +} + +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val) { + uint8_t i; + + for (i = 0; i < 8; i++) { + if (bitOrder == LSBFIRST) { + digitalWrite(dataPin, !!(val & (1 << i))); + } else { + digitalWrite(dataPin, !!(val & (1 << (7 - i)))); + } + + digitalWrite(clockPin, HIGH); + digitalWrite(clockPin, LOW); + } +} diff --git a/idf_component.yml b/idf_component.yml new file mode 100644 index 0000000..913539d --- /dev/null +++ b/idf_component.yml @@ -0,0 +1,137 @@ +description: "Arduino core for ESP32, ESP32-C, ESP32-H, ESP32-P, ESP32-S series of SoCs" +url: "https://github.com/espressif/arduino-esp32" +license: "LGPL-2.1" +targets: + - esp32 + - esp32c2 + - esp32c3 + - esp32c5 + - esp32c6 + - esp32c61 + - esp32h2 + - esp32p4 + - esp32s2 + - esp32s3 +tags: + - arduino +files: + include: + - "variants/esp32/**/*" + - "variants/esp32c2/**/*" + - "variants/esp32c3/**/*" + - "variants/esp32c5/**/*" + - "variants/esp32c6/**/*" + - "variants/esp32c61/**/*" + - "variants/esp32h2/**/*" + - "variants/esp32p4/**/*" + - "variants/esp32s2/**/*" + - "variants/esp32s3/**/*" + exclude: + - ".*" # All files in the root directory that start with a dot. + - ".gitlab/" + - ".gitlab/**/*" + - "docs/" + - "docs/**/*" + - "idf_component_examples/" + - "idf_component_examples/**/*" + - "package/" + - "package/**/*" + - "tests/" + - "tests/**/*" + - "tools/" + - "tools/**/*" + - "variants/**/*" + - "boards.txt" + - "CODE_OF_CONDUCT.md" + - "LICENSE.md" + - "package.json" + - "platform.txt" + - "programmers.txt" +dependencies: + idf: ">=5.3,<5.6" + # mdns 1.2.1 is necessary to build H2 with no WiFi + espressif/mdns: + version: "^1.2.3" + require: public + espressif/esp_modem: + version: "^2.0.0" + espressif/esp-zboss-lib: + version: "==1.6.4" # compatible with esp-zigbee-lib 1.6.8 + require: public + rules: + - if: "target not in [esp32c2, esp32c61, esp32p4]" + espressif/esp-zigbee-lib: + version: "==1.6.8" + require: public + rules: + - if: "target not in [esp32c2, esp32c61, esp32p4]" + espressif/esp-dsp: + version: "^1.3.4" + rules: + - if: "target not in [esp32c2, esp32c61]" + # RainMaker Start (Fixed versions, because Matter supports only Insights 1.0.1) + espressif/network_provisioning: + version: "1.0.2" + rules: + - if: "target != esp32c2" + espressif/esp_rainmaker: + version: "1.5.2" + rules: + - if: "target not in [esp32c2, esp32p4]" + espressif/rmaker_common: + version: "1.4.6" + rules: + - if: "target not in [esp32c2, esp32p4]" + espressif/esp_insights: + version: "1.2.2" + rules: + - if: "target not in [esp32c2, esp32p4]" + # New version breaks esp_insights 1.0.1 + espressif/esp_diag_data_store: + version: "1.0.2" + rules: + - if: "target not in [esp32c2, esp32p4]" + espressif/esp_diagnostics: + version: "1.2.1" + rules: + - if: "target not in [esp32c2, esp32p4]" + espressif/cbor: + version: "0.6.1~4" + rules: + - if: "target not in [esp32c2, esp32p4]" + espressif/qrcode: + version: "0.1.0~2" + rules: + - if: "target not in [esp32c2, esp32p4]" + # RainMaker End + espressif/esp-sr: + version: "^2.1.5" + rules: + - if: "target in [esp32s3, esp32p4]" + espressif/esp_hosted: + version: "^2.9.2" + rules: + - if: "target == esp32p4" + espressif/esp_wifi_remote: + version: "^1.2.2" + rules: + - if: "target == esp32p4" + espressif/libsodium: + version: "^1.0.20~1" + require: public + espressif/esp-modbus: + version: "^1.0.15" + require: public + joltwallet/littlefs: + version: "^1.10.2" + chmorgan/esp-libhelix-mp3: + version: "1.0.3" + require: public + espressif/lan867x: + version: "^2.0.0" + rules: + - if: "target in [esp32, esp32p4]" +examples: + - path: ./idf_component_examples/Arduino_ESP_Matter_over_OpenThread + - path: ./idf_component_examples/hello_world + - path: ./idf_component_examples/hw_cdc_hello_world diff --git a/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino b/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino new file mode 100644 index 0000000..4dba935 --- /dev/null +++ b/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino @@ -0,0 +1,94 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include + +const char *ssid = ".........."; +const char *password = ".........."; +uint32_t last_ota_time = 0; + +void setup() { + Serial.begin(115200); + Serial.println("Booting"); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + while (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("Connection Failed! Rebooting..."); + delay(5000); + ESP.restart(); + } + + // Port defaults to 3232 + // ArduinoOTA.setPort(3232); + + // Hostname defaults to esp3232-[MAC] + // ArduinoOTA.setHostname("myesp32"); + + // Password can be set with plain text (will be hashed internally) + // The authentication uses PBKDF2-HMAC-SHA256 with 10,000 iterations + // ArduinoOTA.setPassword("admin"); + + // Or set password with pre-hashed value (SHA256 hash of "admin") + // SHA256(admin) = 8c6976e5b5410415bde908bd4dee15dfb167a9c873fc4bb8a81f6f2ab448a918 + // ArduinoOTA.setPasswordHash("8c6976e5b5410415bde908bd4dee15dfb167a9c873fc4bb8a81f6f2ab448a918"); + + ArduinoOTA + .onStart([]() { + String type; + if (ArduinoOTA.getCommand() == U_FLASH) { + type = "sketch"; + } else { // U_SPIFFS + type = "filesystem"; + } + + // NOTE: if updating SPIFFS this would be the place to unmount SPIFFS using SPIFFS.end() + Serial.println("Start updating " + type); + }) + .onEnd([]() { + Serial.println("\nEnd"); + }) + .onProgress([](unsigned int progress, unsigned int total) { + if (millis() - last_ota_time > 500) { + Serial.printf("Progress: %u%%\n", (progress / (total / 100))); + last_ota_time = millis(); + } + }) + .onError([](ota_error_t error) { + Serial.printf("Error[%u]: ", error); + if (error == OTA_AUTH_ERROR) { + Serial.println("Auth Failed"); + } else if (error == OTA_BEGIN_ERROR) { + Serial.println("Begin Failed"); + } else if (error == OTA_CONNECT_ERROR) { + Serial.println("Connect Failed"); + } else if (error == OTA_RECEIVE_ERROR) { + Serial.println("Receive Failed"); + } else if (error == OTA_END_ERROR) { + Serial.println("End Failed"); + } + }); + + ArduinoOTA.begin(); + + Serial.println("Ready"); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); +} + +void loop() { + ArduinoOTA.handle(); +} diff --git a/libraries/ArduinoOTA/examples/BasicOTA/ci.yml b/libraries/ArduinoOTA/examples/BasicOTA/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/ArduinoOTA/examples/BasicOTA/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/ArduinoOTA/examples/SignedOTA/README.md b/libraries/ArduinoOTA/examples/SignedOTA/README.md new file mode 100644 index 0000000..bf5f12b --- /dev/null +++ b/libraries/ArduinoOTA/examples/SignedOTA/README.md @@ -0,0 +1,323 @@ +# SignedOTA - Secure OTA Updates with Signature Verification + +This example demonstrates how to perform secure OTA updates with cryptographic signature verification using the ArduinoOTA library. + +## Overview + +**SignedOTA** adds an extra layer of security to Arduino OTA updates by requiring all firmware to be cryptographically signed with your private key. This protects against: + +- ✅ Unauthorized firmware updates +- ✅ Man-in-the-middle attacks +- ✅ Compromised networks +- ✅ Firmware tampering +- ✅ Supply chain attacks + +Even if an attacker gains access to your network, they **cannot** install unsigned firmware on your devices. + +## Features + +- **RSA & ECDSA Support**: RSA-2048/3072/4096 and ECDSA-P256/P384 +- **Multiple Hash Algorithms**: SHA-256, SHA-384, SHA-512 +- **Arduino IDE Compatible**: Works with standard Arduino OTA workflow +- **Optional Password Protection**: Add password authentication in addition to signature verification +- **Easy Integration**: Just a few lines of code + +## Requirements + +- **ESP32 Arduino Core 3.3.0+** +- **Python 3.6+** with `cryptography` library + +- **OTA-capable partition scheme** (e.g., "Minimal SPIFFS (1.9MB APP with OTA)") + + +## Quick Start Guide + +### 1. Generate Cryptographic Keys + +```bash +# Navigate to Arduino ESP32 tools directory +cd /tools + +# Install Python dependencies +pip install cryptography + +# Generate RSA-2048 key pair (recommended) +python bin_signing.py --generate-key rsa-2048 --out private_key.pem + +# Extract public key +python bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +``` + +**⚠️ IMPORTANT: Keep `private_key.pem` secure! Anyone with this key can sign firmware for your devices.** + +### 2. Setup the Example + +1. Copy `public_key.h` (generated in step 1) to this sketch directory +2. Open `SignedOTA.ino` in Arduino IDE + +3. Configure WiFi credentials: + ```cpp + const char *ssid = "YourWiFiSSID"; + const char *password = "YourWiFiPassword"; + ``` + + +4. Select appropriate partition scheme: + - **Tools → Partition Scheme → "Minimal SPIFFS (1.9MB APP with OTA)"** + + +### 3. Upload Initial Firmware + +1. Connect your ESP32 via USB +2. Upload the sketch normally +3. Open Serial Monitor (115200 baud) +4. Note the device IP address + +### 4. Build & Sign Firmware for OTA Update Example + +**Option A: Using Arduino IDE** + +```bash +# Export compiled binary +# In Arduino IDE: Sketch → Export Compiled Binary + +# Sign the firmware +cd /tools +python bin_signing.py \ + --bin /path/to/SignedOTA.ino.bin \ + --key private_key.pem \ + --out firmware_signed.bin +``` + +**Option B: Using arduino-cli** + +```bash +# Compile and export +arduino-cli compile --fqbn esp32:esp32:esp32 --export-binaries SignedOTA + +# Sign the firmware +cd /tools +python bin_signing.py \ + --bin build/esp32.esp32.esp32/SignedOTA.ino.bin \ + --key private_key.pem \ + --out firmware_signed.bin +``` + +### 5. Upload Signed Firmware via OTA + +Upload the signed firmware using `espota.py`: + +```bash +python /tools/espota.py -i -f firmware_signed.bin +``` + +The device will automatically: +1. Receive the signed firmware (firmware + signature) +2. Hash only the firmware portion +3. Verify the signature +4. Install if valid, reject if invalid + +**Note**: You can also use the Update library's `Signed_OTA_Update` example for HTTP-based OTA updates. + +## Configuration Options + +### Hash Algorithms + +Choose one in `SignedOTA.ino`: + +```cpp +#define USE_SHA256 // Default, fastest +// #define USE_SHA384 +// #define USE_SHA512 +``` + +**Must match** the `--hash` parameter when signing: + +```bash +python bin_signing.py --bin firmware.bin --key private.pem --out signed.bin --hash sha256 +``` + +### Signature Algorithms + +Choose one in `SignedOTA.ino`: + +```cpp +#define USE_RSA // For RSA keys +// #define USE_ECDSA // For ECDSA keys +``` + +### Optional Password Protection + +Add password authentication **in addition to** signature verification: + +```cpp +const char *ota_password = "yourpassword"; // Set password +// const char *ota_password = nullptr; // Disable password +``` + +## How It Works + +``` +┌─────────────────┐ +│ Build Firmware │ +└────────┬────────┘ + │ + ▼ +┌─────────────────┐ +│ Sign Firmware │ ← Uses your private key +│ (bin_signing) │ +└────────┬────────┘ + │ + ▼ +┌─────────────────────────┐ +│ firmware_signed.bin │ +│ [firmware][signature] │ +└────────┬────────────────┘ + │ + ▼ OTA Upload +┌─────────────────────────┐ +│ ESP32 Device │ +│ ┌──────────────────┐ │ +│ │ Verify Signature │ │ ← Uses your public key +│ │ ✓ or ✗ │ │ +│ └──────────────────┘ │ +│ │ │ +│ ✓ Valid? │ +│ ├─ Yes: Install │ +│ └─ No: Reject │ +└─────────────────────────┘ +``` + +## Troubleshooting + +### "Begin Failed" Error + +**Cause**: Signature verification setup failed, or partition scheme issue + +**Solutions**: + +1. Check partition scheme (use "Minimal SPIFFS (1.9MB APP with OTA)") +2. Verify `public_key.h` is in the sketch directory +3. Check hash and signature algorithm match your key type + + +### "End Failed" Error + +**Cause**: Signature verification failed + +**Solutions**: +1. Ensure firmware was signed with the **correct private key** +2. Verify hash algorithm matches (SHA-256, SHA-384, SHA-512) +3. Check firmware wasn't corrupted during signing/transfer +4. Confirm you signed the **correct** `.bin` file + +### "Receive Failed" Error + +**Cause**: Network timeout or connection issue + +**Solutions**: +1. Check Wi-Fi signal strength +2. Ensure device is reachable on the network +3. Try increasing timeout: `ArduinoOTA.setTimeout(5000)` + +### Upload Fails + +**Issue**: OTA upload fails or times out + +**Solutions**: +1. Verify device is on the same network +2. Check firewall settings aren't blocking port 3232 +3. Ensure Wi-Fi signal strength is adequate +4. If using password protection, ensure the password is correct +5. Try: `python /tools/espota.py -i -f firmware_signed.bin -d` + +## Security Considerations + +### Best Practices + +✅ **Keep private key secure**: Never commit to git, store encrypted +✅ **Use strong keys**: RSA-2048+ or ECDSA-P256+ +✅ **Use HTTPS when possible**: For additional transport security +✅ **Add password authentication**: Extra layer of protection +✅ **Rotate keys periodically**: Generate new keys every 1-2 years + +### What This Protects Against + +- ✅ Unsigned firmware installation +- ✅ Firmware signed with wrong key +- ✅ Tampered/corrupted firmware +- ✅ Network-based attacks (when combined with password) + +### What This Does NOT Protect Against + + +- ❌ Physical access (USB flashing still works) +- ❌ Downgrade attacks (no version checking by default) +- ❌ Replay attacks (no timestamp/nonce by default) +- ❌ Key compromise (if private key is stolen) + + +### Additional Security + +For production deployments, consider: + +1. **Add version checking** to prevent downgrades +2. **Add timestamp validation** to prevent replay attacks +3. **Use secure boot** for additional protection +4. **Store keys in HSM** or secure key management system +5. **Implement key rotation** mechanism + +## Advanced Usage + +### Using ECDSA Instead of RSA + +ECDSA keys are smaller and faster: + +```bash +# Generate ECDSA-P256 key +python bin_signing.py --generate-key ecdsa-p256 --out private_key.pem +python bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +``` + +In `SignedOTA.ino`: + +```cpp +#define USE_SHA256 +#define USE_ECDSA // Instead of USE_RSA +``` + +### Using SHA-384 or SHA-512 + +For higher security: + +```bash +# Sign with SHA-384 +python bin_signing.py --bin firmware.bin --key private.pem --out signed.bin --hash sha384 +``` + +In `SignedOTA.ino`: + +```cpp +#define USE_SHA384 // Instead of USE_SHA256 +#define USE_RSA +``` + +### Custom Partition Label + +To update a specific partition: + +```cpp +ArduinoOTA.setPartitionLabel("my_partition"); +``` + +## Support + +For issues and questions: + +- Update Library README: `libraries/Update/README.md` +- ESP32 Arduino Core: https://github.com/espressif/arduino-esp32 +- Forum: https://github.com/espressif/arduino-esp32/discussions + +## License + +This library is part of the Arduino-ESP32 project and is licensed under the Apache License 2.0. diff --git a/libraries/ArduinoOTA/examples/SignedOTA/SignedOTA.ino b/libraries/ArduinoOTA/examples/SignedOTA/SignedOTA.ino new file mode 100644 index 0000000..ec23489 --- /dev/null +++ b/libraries/ArduinoOTA/examples/SignedOTA/SignedOTA.ino @@ -0,0 +1,204 @@ +/* + * SignedOTA Example - Secure OTA Updates with Signature Verification + * + * This example demonstrates how to perform OTA updates with cryptographic + * signature verification using ArduinoOTA library. + * + * IMPORTANT: This example requires firmware to be signed with bin_signing.py + * + * NOTE: Signature verification support is enabled via the build_opt.h file + * in this directory. + * + * Setup: + * 1. Generate keys: + * python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem + * python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem + * + * 2. Copy public_key.h to this sketch directory + * + * 3. Configure WiFi credentials below + * + * 4. Upload this sketch to your device + * + * 5. Build your firmware and sign it: + * arduino-cli compile --fqbn esp32:esp32:esp32 --export-binaries SignedOTA + * python /tools/bin_signing.py --bin build/.bin --key private_key.pem --out firmware_signed.bin + * + * 6. Upload signed firmware using espota.py or Arduino IDE (after modifying espota.py to handle signed binaries) + * python /tools/espota.py -i -f firmware_signed.bin + * + * For more information, see the Update library's Signed_OTA_Update example + * and README.md in the Update library folder. + * + * Created by lucasssvaz + */ + +#include +#include +#include +#include + +// Include your public key (generated with bin_signing.py) +#include "public_key.h" + +// ==================== CONFIGURATION ==================== + +// WiFi credentials +const char *ssid = ".........."; +const char *password = ".........."; + +// Optional: Set a password for OTA authentication +// This is in ADDITION to signature verification +// ArduinoOTA password protects the OTA connection +// Signature verification ensures firmware authenticity +const char *ota_password = nullptr; // Set to nullptr to disable, or "yourpassword" to enable + +// Choose hash algorithm (must match what you use with bin_signing.py --hash) +// Uncomment ONE of these: +#define USE_SHA256 // Default, recommended +// #define USE_SHA384 +// #define USE_SHA512 + +// Choose signature algorithm (must match your key type) +// Uncomment ONE of these: +#define USE_RSA // Recommended (works with rsa-2048, rsa-3072, rsa-4096) +// #define USE_ECDSA // Works with ecdsa-p256, ecdsa-p384 + +// ======================================================= + +uint32_t last_ota_time = 0; + +void setup() { + Serial.begin(115200); + Serial.println("\n\n================================="); + Serial.println("SignedOTA - Secure OTA Updates"); + Serial.println("=================================\n"); + Serial.println("Booting..."); + + // Connect to WiFi + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + while (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("Connection Failed! Rebooting..."); + delay(5000); + ESP.restart(); + } + + Serial.println("WiFi Connected!"); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + // ==================== SIGNATURE VERIFICATION SETUP ==================== + + // Select hash algorithm +#ifdef USE_SHA256 + int hashType = HASH_SHA256; + Serial.println("Using SHA-256 hash"); +#elif defined(USE_SHA384) + int hashType = HASH_SHA384; + Serial.println("Using SHA-384 hash"); +#elif defined(USE_SHA512) + int hashType = HASH_SHA512; + Serial.println("Using SHA-512 hash"); +#else +#error "Please define a hash algorithm (USE_SHA256, USE_SHA384, or USE_SHA512)" +#endif + + // Create verifier object +#ifdef USE_RSA + static UpdaterRSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, hashType); + Serial.println("Using RSA signature verification"); +#elif defined(USE_ECDSA) + static UpdaterECDSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, hashType); + Serial.println("Using ECDSA signature verification"); +#else +#error "Please define a signature type (USE_RSA or USE_ECDSA)" +#endif + + // Install signature verification BEFORE ArduinoOTA.begin() + ArduinoOTA.setSignature(&sign); + Serial.println("✓ Signature verification enabled"); + + // ======================================================================= + + // Optional: Set hostname + // ArduinoOTA.setHostname("myesp32"); + + // Optional: Set OTA password (in addition to signature verification) + if (ota_password != nullptr) { + ArduinoOTA.setPassword(ota_password); + Serial.println("✓ OTA password protection enabled"); + } + + // Configure OTA callbacks + ArduinoOTA + .onStart([]() { + String type; + if (ArduinoOTA.getCommand() == U_FLASH) { + type = "sketch"; + } else { // U_SPIFFS + type = "filesystem"; + } + Serial.println("\n================================="); + Serial.println("OTA Update Starting: " + type); + Serial.println("================================="); + Serial.println("⚠️ Signature will be verified!"); + }) + .onEnd([]() { + Serial.println("\n================================="); + Serial.println("✅ OTA Update Complete!"); + Serial.println("✅ Signature Verified!"); + Serial.println("================================="); + Serial.println("Rebooting..."); + }) + .onProgress([](unsigned int progress, unsigned int total) { + if (millis() - last_ota_time > 500) { + Serial.printf("Progress: %u%%\r", (progress / (total / 100))); + last_ota_time = millis(); + } + }) + .onError([](ota_error_t error) { + Serial.println("\n================================="); + Serial.println("❌ OTA Update Failed!"); + Serial.println("================================="); + Serial.printf("Error[%u]: ", error); + if (error == OTA_AUTH_ERROR) { + Serial.println("Authentication Failed"); + Serial.println("Check your OTA password"); + } else if (error == OTA_BEGIN_ERROR) { + Serial.println("Begin Failed"); + Serial.println("This could be:"); + Serial.println("- Signature verification setup failed"); + Serial.println("- Not enough space for update"); + Serial.println("- Invalid partition"); + } else if (error == OTA_CONNECT_ERROR) { + Serial.println("Connect Failed"); + } else if (error == OTA_RECEIVE_ERROR) { + Serial.println("Receive Failed"); + } else if (error == OTA_END_ERROR) { + Serial.println("End Failed"); + Serial.println("This could be:"); + Serial.println("- ❌ SIGNATURE VERIFICATION FAILED!"); + Serial.println("- Firmware not signed with correct key"); + Serial.println("- Firmware corrupted during transfer"); + Serial.println("- MD5 checksum mismatch"); + } + Serial.println("================================="); + }); + + // Start ArduinoOTA service + ArduinoOTA.begin(); + + Serial.println("\n================================="); + Serial.println("✓ OTA Server Ready"); + Serial.println("================================="); + Serial.printf("Hostname: %s.local\n", ArduinoOTA.getHostname().c_str()); + Serial.printf("IP: %s\n", WiFi.localIP().toString().c_str()); + Serial.println("Port: 3232"); + Serial.println("\n⚠️ Only signed firmware will be accepted!"); + Serial.println("=================================\n"); +} + +void loop() { + ArduinoOTA.handle(); +} diff --git a/libraries/ArduinoOTA/examples/SignedOTA/build_opt.h b/libraries/ArduinoOTA/examples/SignedOTA/build_opt.h new file mode 100644 index 0000000..1b328fa --- /dev/null +++ b/libraries/ArduinoOTA/examples/SignedOTA/build_opt.h @@ -0,0 +1 @@ +-DUPDATE_SIGN diff --git a/libraries/ArduinoOTA/examples/SignedOTA/ci.yml b/libraries/ArduinoOTA/examples/SignedOTA/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/ArduinoOTA/examples/SignedOTA/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/ArduinoOTA/examples/SignedOTA/public_key.h b/libraries/ArduinoOTA/examples/SignedOTA/public_key.h new file mode 100644 index 0000000..fd82028 --- /dev/null +++ b/libraries/ArduinoOTA/examples/SignedOTA/public_key.h @@ -0,0 +1,30 @@ +// Public key for OTA signature verification +// Include this in your Arduino sketch + +// ⚠️ THIS IS A TEST KEY - DO NOT USE IN PRODUCTION! +// Generate your own keys using: +// python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem +// python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +// +// Then replace this file with the generated public_key.h + +// Test RSA-2048 Public Key (PEM format) +const uint8_t PUBLIC_KEY[] PROGMEM = { + 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x42, 0x45, 0x47, 0x49, 0x4e, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, 0x43, 0x20, 0x4b, 0x45, 0x59, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, + 0x0a, 0x4d, 0x49, 0x49, 0x42, 0x49, 0x6a, 0x41, 0x4e, 0x42, 0x67, 0x6b, 0x71, 0x68, 0x6b, 0x69, 0x47, 0x39, 0x77, 0x30, 0x42, 0x41, 0x51, 0x45, 0x46, 0x41, + 0x41, 0x4f, 0x43, 0x41, 0x51, 0x38, 0x41, 0x4d, 0x49, 0x49, 0x42, 0x43, 0x67, 0x4b, 0x43, 0x41, 0x51, 0x45, 0x41, 0x73, 0x35, 0x35, 0x66, 0x4f, 0x74, 0x51, + 0x64, 0x69, 0x70, 0x39, 0x58, 0x6f, 0x49, 0x61, 0x6c, 0x52, 0x5a, 0x4b, 0x6c, 0x4a, 0x0a, 0x52, 0x62, 0x55, 0x73, 0x49, 0x30, 0x4c, 0x48, 0x5a, 0x74, 0x2b, + 0x50, 0x58, 0x35, 0x4b, 0x58, 0x43, 0x79, 0x54, 0x64, 0x63, 0x78, 0x71, 0x6c, 0x6f, 0x44, 0x45, 0x2b, 0x63, 0x38, 0x43, 0x6f, 0x32, 0x50, 0x77, 0x37, 0x6f, + 0x66, 0x63, 0x66, 0x30, 0x47, 0x41, 0x38, 0x4a, 0x55, 0x65, 0x6e, 0x6d, 0x45, 0x46, 0x6b, 0x57, 0x6a, 0x50, 0x53, 0x48, 0x4c, 0x55, 0x55, 0x79, 0x44, 0x0a, + 0x63, 0x65, 0x4b, 0x63, 0x2b, 0x71, 0x45, 0x47, 0x54, 0x58, 0x72, 0x59, 0x39, 0x56, 0x6f, 0x4d, 0x38, 0x6f, 0x42, 0x58, 0x39, 0x67, 0x48, 0x41, 0x64, 0x4b, + 0x4f, 0x51, 0x48, 0x33, 0x50, 0x4d, 0x70, 0x4a, 0x69, 0x56, 0x51, 0x71, 0x4e, 0x43, 0x36, 0x37, 0x31, 0x44, 0x37, 0x54, 0x45, 0x76, 0x4e, 0x52, 0x43, 0x67, + 0x6e, 0x4f, 0x41, 0x37, 0x77, 0x62, 0x77, 0x6f, 0x78, 0x4e, 0x0a, 0x63, 0x75, 0x59, 0x30, 0x49, 0x6e, 0x51, 0x4e, 0x30, 0x64, 0x6b, 0x42, 0x43, 0x4f, 0x63, + 0x34, 0x4e, 0x66, 0x31, 0x56, 0x42, 0x76, 0x35, 0x64, 0x71, 0x55, 0x57, 0x41, 0x62, 0x66, 0x43, 0x57, 0x68, 0x5a, 0x37, 0x31, 0x72, 0x4a, 0x56, 0x32, 0x53, + 0x68, 0x79, 0x35, 0x48, 0x42, 0x48, 0x48, 0x52, 0x4e, 0x43, 0x78, 0x4f, 0x67, 0x58, 0x68, 0x4f, 0x6c, 0x66, 0x6c, 0x66, 0x0a, 0x72, 0x49, 0x57, 0x56, 0x71, + 0x66, 0x51, 0x4b, 0x2b, 0x75, 0x54, 0x4d, 0x62, 0x39, 0x4a, 0x4c, 0x51, 0x67, 0x76, 0x4a, 0x66, 0x70, 0x4c, 0x61, 0x65, 0x35, 0x35, 0x61, 0x61, 0x4e, 0x77, + 0x63, 0x72, 0x62, 0x59, 0x38, 0x58, 0x67, 0x53, 0x79, 0x31, 0x64, 0x6c, 0x58, 0x76, 0x4e, 0x37, 0x4d, 0x33, 0x75, 0x4c, 0x52, 0x72, 0x4b, 0x79, 0x61, 0x75, + 0x34, 0x59, 0x0a, 0x39, 0x51, 0x53, 0x71, 0x76, 0x4a, 0x71, 0x67, 0x52, 0x61, 0x36, 0x66, 0x47, 0x51, 0x2f, 0x4d, 0x41, 0x63, 0x6c, 0x48, 0x59, 0x33, 0x6d, + 0x4b, 0x64, 0x6e, 0x64, 0x68, 0x51, 0x49, 0x44, 0x41, 0x51, 0x41, 0x42, 0x0a, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x45, 0x4e, 0x44, 0x20, 0x50, 0x55, 0x42, 0x4c, + 0x49, 0x43, 0x20, 0x4b, 0x45, 0x59, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x0a, 0x00, +}; +const size_t PUBLIC_KEY_LEN = 451; diff --git a/libraries/ArduinoOTA/keywords.txt b/libraries/ArduinoOTA/keywords.txt new file mode 100644 index 0000000..9c8a81d --- /dev/null +++ b/libraries/ArduinoOTA/keywords.txt @@ -0,0 +1,47 @@ +####################################### +# Syntax Coloring Map For Ultrasound +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +ArduinoOTA KEYWORD1 +ArduinoOTAClass KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +handle KEYWORD2 +onStart KEYWORD2 +onEnd KEYWORD2 +onError KEYWORD2 +onProgress KEYWORD2 +setPort KEYWORD2 +setHostname KEYWORD2 +getHostname KEYWORD2 +setPassword KEYWORD2 +setPasswordHash KEYWORD2 +setPartitionLabel KEYWORD2 +getPartitionLabel KEYWORD2 +setRebootOnSuccess KEYWORD2 +setMdnsEnabled KEYWORD2 +setSignature KEYWORD2 +getCommand KEYWORD2 +setTimeout KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +OTA_IDLE LITERAL1 +OTA_WAITAUTH LITERAL1 +OTA_RUNUPDATE LITERAL1 +OTA_AUTH_ERROR LITERAL1 +OTA_BEGIN_ERROR LITERAL1 +OTA_CONNECT_ERROR LITERAL1 +OTA_RECEIVE_ERROR LITERAL1 +OTA_END_ERROR LITERAL1 diff --git a/libraries/ArduinoOTA/library.properties b/libraries/ArduinoOTA/library.properties new file mode 100644 index 0000000..f6f9fba --- /dev/null +++ b/libraries/ArduinoOTA/library.properties @@ -0,0 +1,9 @@ +name=ArduinoOTA +version=3.3.7 +author=Ivan Grokhotkov and Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Enables Over The Air upgrades, via wifi and espota.py UDP request/TCP download. +paragraph=With this library you can enable your sketch to be upgraded over network. Includes mdns announces to get discovered by the arduino IDE. +category=Communication +url= +architectures=esp32 diff --git a/libraries/ArduinoOTA/src/ArduinoOTA.cpp b/libraries/ArduinoOTA/src/ArduinoOTA.cpp new file mode 100644 index 0000000..d20cfb0 --- /dev/null +++ b/libraries/ArduinoOTA/src/ArduinoOTA.cpp @@ -0,0 +1,499 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef LWIP_OPEN_SRC +#define LWIP_OPEN_SRC +#endif +#include +#include "ArduinoOTA.h" +#include "NetworkClient.h" +#include "ESPmDNS.h" +#include "HEXBuilder.h" +#include "SHA2Builder.h" +#include "PBKDF2_HMACBuilder.h" +#include "Update.h" + +// #define OTA_DEBUG Serial + +ArduinoOTAClass::ArduinoOTAClass(UpdateClass *updater) + : _updater(updater), _port(0), _initialized(false), _rebootOnSuccess(true), _mdnsEnabled(true), _state(OTA_IDLE), _size(0), _cmd(0), _ota_port(0), + _ota_timeout(1000), _start_callback(NULL), _end_callback(NULL), _error_callback(NULL), _progress_callback(NULL) +#ifdef UPDATE_SIGN + , + _sign(NULL) +#endif /* UPDATE_SIGN */ +{ +} + +ArduinoOTAClass::~ArduinoOTAClass() { + end(); +} + +ArduinoOTAClass &ArduinoOTAClass::onStart(THandlerFunction fn) { + _start_callback = fn; + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::onEnd(THandlerFunction fn) { + _end_callback = fn; + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::onProgress(THandlerFunction_Progress fn) { + _progress_callback = fn; + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::onError(THandlerFunction_Error fn) { + _error_callback = fn; + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::setPort(uint16_t port) { + if (!_initialized && !_port && port) { + _port = port; + } + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::setHostname(const char *hostname) { + if (!_initialized && !_hostname.length() && hostname) { + _hostname = hostname; + } + return *this; +} + +String ArduinoOTAClass::getHostname() { + return _hostname; +} + +ArduinoOTAClass &ArduinoOTAClass::setPassword(const char *password) { + if (_state == OTA_IDLE && password) { + // Hash the password with SHA256 for storage (not plain text) + SHA256Builder pass_hash; + pass_hash.begin(); + pass_hash.add(password); + pass_hash.calculate(); + _password.clear(); + _password = pass_hash.toString(); + } + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::setPasswordHash(const char *password) { + if (_state == OTA_IDLE && password) { + size_t len = strlen(password); + bool is_hex = HEXBuilder::isHexString(password, len); + + if (!is_hex) { + log_e("Invalid password hash. Expected hex string (0-9, a-f, A-F)."); + return *this; + } + + if (len == 32) { + // Warn if MD5 hash is detected (32 hex characters) + log_w("MD5 password hash detected. MD5 is deprecated and insecure."); + log_w("Please use setPassword() with plain text or setPasswordHash() with SHA256 hash (64 chars)."); + log_w("To generate SHA256: echo -n 'yourpassword' | sha256sum"); + } else if (len == 64) { + log_i("Using SHA256 password hash."); + } else { + log_e("Invalid password hash length. Expected 32 (deprecated MD5) or 64 (SHA256) characters."); + return *this; + } + + // Store the pre-hashed password directly + _password.clear(); + _password = password; + } + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::setPartitionLabel(const char *partition_label) { + if (_state == OTA_IDLE && partition_label) { + _partition_label.clear(); + _partition_label = partition_label; + } + return *this; +} + +String ArduinoOTAClass::getPartitionLabel() { + return _partition_label; +} + +ArduinoOTAClass &ArduinoOTAClass::setRebootOnSuccess(bool reboot) { + _rebootOnSuccess = reboot; + return *this; +} + +ArduinoOTAClass &ArduinoOTAClass::setMdnsEnabled(bool enabled) { + _mdnsEnabled = enabled; + return *this; +} + +#ifdef UPDATE_SIGN +ArduinoOTAClass &ArduinoOTAClass::setSignature(UpdaterVerifyClass *sign) { + if (_state == OTA_IDLE && sign) { + _sign = sign; + int hashType = sign->getHashType(); + [[maybe_unused]] + const char *hashName = (hashType == HASH_SHA256) ? "SHA-256" + : (hashType == HASH_SHA384) ? "SHA-384" + : "SHA-512"; + log_i("Signature verification enabled for ArduinoOTA (hash: %s)", hashName); + } + return *this; +} +#endif /* UPDATE_SIGN */ + +void ArduinoOTAClass::begin() { + if (_initialized) { + log_w("already initialized"); + return; + } + + if (!_port) { + _port = 3232; + } + + if (!_udp_ota.begin(_port)) { + log_e("udp bind failed"); + return; + } + + if (!_hostname.length()) { + char tmp[20]; + uint8_t mac[6]; + Network.macAddress(mac); + sprintf(tmp, "esp32-%02x%02x%02x%02x%02x%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + _hostname = tmp; + } +#ifdef CONFIG_MDNS_MAX_INTERFACES + if (_mdnsEnabled) { + MDNS.begin(_hostname.c_str()); + MDNS.enableArduino(_port, (_password.length() > 0)); + } +#endif + _initialized = true; + _state = OTA_IDLE; + log_i("OTA server at: %s.local:%u", _hostname.c_str(), _port); +} + +int ArduinoOTAClass::parseInt() { + char data[INT_BUFFER_SIZE]; + uint8_t index = 0; + char value; + while (_udp_ota.peek() == ' ') { + _udp_ota.read(); + } + while (index < INT_BUFFER_SIZE - 1) { + value = _udp_ota.peek(); + if (value < '0' || value > '9') { + data[index++] = '\0'; + return atoi(data); + } + data[index++] = _udp_ota.read(); + } + return 0; +} + +String ArduinoOTAClass::readStringUntil(char end) { + String res = ""; + int value; + while (true) { + value = _udp_ota.read(); + if (value <= 0 || value == end) { + return res; + } + res += (char)value; + } + return res; +} + +void ArduinoOTAClass::_onRx() { + if (_state == OTA_IDLE) { + int cmd = parseInt(); + if (cmd != U_FLASH && cmd != U_FLASHFS) { + return; + } + _cmd = cmd; + _ota_port = parseInt(); + _size = parseInt(); + _udp_ota.read(); + _md5 = readStringUntil('\n'); + _md5.trim(); + if (_md5.length() != 32) { // MD5 produces 32 character hex string for firmware integrity + log_e("bad md5 length"); + return; + } + + if (_password.length()) { + // Generate a random challenge (nonce) + SHA256Builder nonce_sha256; + nonce_sha256.begin(); + nonce_sha256.add(String(micros()) + String(random(1000000))); + nonce_sha256.calculate(); + _nonce = nonce_sha256.toString(); + + _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort()); + _udp_ota.printf("AUTH %s", _nonce.c_str()); + _udp_ota.endPacket(); + _state = OTA_WAITAUTH; + return; + } else { + _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort()); + _udp_ota.print("OK"); + _udp_ota.endPacket(); + _ota_ip = _udp_ota.remoteIP(); + _state = OTA_RUNUPDATE; + } + } else if (_state == OTA_WAITAUTH) { + int cmd = parseInt(); + if (cmd != U_AUTH) { + log_e("%d was expected. got %d instead", U_AUTH, cmd); + _state = OTA_IDLE; + return; + } + _udp_ota.read(); + String cnonce = readStringUntil(' '); + String response = readStringUntil('\n'); + if (cnonce.length() != 64 || response.length() != 64) { // SHA256 produces 64 character hex string + log_e("auth param fail"); + _state = OTA_IDLE; + return; + } + + // Verify the challenge/response using PBKDF2-HMAC-SHA256 + // The client should derive a key using PBKDF2-HMAC-SHA256 with: + // - password: the OTA password (or its hash if using setPasswordHash) + // - salt: nonce + cnonce + // - iterations: 10000 (or configurable) + // Then hash the challenge with the derived key + + String salt = _nonce + ":" + cnonce; + SHA256Builder sha256; + // Use the stored password hash for PBKDF2 derivation + PBKDF2_HMACBuilder pbkdf2(&sha256, _password, salt, 10000); + + pbkdf2.begin(); + pbkdf2.calculate(); + String derived_key = pbkdf2.toString(); + + // Create challenge: derived_key + nonce + cnonce + String challenge = derived_key + ":" + _nonce + ":" + cnonce; + SHA256Builder challenge_sha256; + challenge_sha256.begin(); + challenge_sha256.add(challenge); + challenge_sha256.calculate(); + String expected_response = challenge_sha256.toString(); + + if (expected_response.equals(response)) { + _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort()); + _udp_ota.print("OK"); + _udp_ota.endPacket(); + _ota_ip = _udp_ota.remoteIP(); + _state = OTA_RUNUPDATE; + } else { + _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort()); + _udp_ota.print("Authentication Failed"); + log_w("Authentication Failed"); + _udp_ota.endPacket(); + if (_error_callback) { + _error_callback(OTA_AUTH_ERROR); + } + _state = OTA_IDLE; + } + } +} + +void ArduinoOTAClass::_runUpdate() { + if (!_updater) { + log_e("UpdateClass is NULL!"); + return; + } + +#ifdef UPDATE_SIGN + // Install signature verification if enabled + if (_sign) { + if (!_updater->installSignature(_sign)) { + log_e("Failed to install signature verification"); + if (_error_callback) { + _error_callback(OTA_BEGIN_ERROR); + } + _state = OTA_IDLE; + return; + } + log_i("Signature verification installed for OTA update"); + } +#endif /* UPDATE_SIGN */ + + const char *partition_label = _partition_label.length() ? _partition_label.c_str() : NULL; + if (!_updater->begin(_size, _cmd, -1, LOW, partition_label)) { + + log_e("Begin ERROR: %s", _updater->errorString()); + + if (_error_callback) { + _error_callback(OTA_BEGIN_ERROR); + } + _state = OTA_IDLE; + return; + } + + _updater->setMD5(_md5.c_str()); // Note: Update library still uses MD5 for firmware integrity, this is separate from authentication + + if (_start_callback) { + _start_callback(); + } + if (_progress_callback) { + _progress_callback(0, _size); + } + + NetworkClient client; + if (!client.connect(_ota_ip, _ota_port)) { + if (_error_callback) { + _error_callback(OTA_CONNECT_ERROR); + } + _state = OTA_IDLE; + } + + uint32_t written = 0, total = 0, tried = 0; + + while (!_updater->isFinished() && client.connected()) { + size_t waited = _ota_timeout; + size_t available = client.available(); + while (!available && waited) { + delay(1); + waited -= 1; + available = client.available(); + } + if (!waited) { + if (written && tried++ < 3) { + log_i("Try[%u]: %u", tried, written); + if (!client.printf("%lu", written)) { + log_e("failed to respond"); + _state = OTA_IDLE; + break; + } + continue; + } + log_e("Receive Failed"); + if (_error_callback) { + _error_callback(OTA_RECEIVE_ERROR); + } + _state = OTA_IDLE; + _updater->abort(); + return; + } + if (!available) { + log_e("No Data: %u", waited); + _state = OTA_IDLE; + break; + } + tried = 0; + static uint8_t buf[1460]; + if (available > 1460) { + available = 1460; + } + size_t r = client.read(buf, available); + if (r != available) { + log_w("didn't read enough! %u != %u", r, available); + if ((int32_t)r < 0) { + delay(1); + continue; //let's not try to write 4 gigabytes when client.read returns -1 + } + } + + written = _updater->write(buf, r); + if (written > 0) { + if (written != r) { + log_w("didn't write enough! %u != %u", written, r); + } + if (!client.printf("%lu", written)) { + log_w("failed to respond"); + } + total += written; + if (_progress_callback) { + _progress_callback(total, _size); + } + } else { + log_e("Write ERROR: %s", _updater->errorString()); + } + } + + if (_updater->end()) { + client.print("OK"); + client.stop(); + delay(10); + if (_end_callback) { + _end_callback(); + } + if (_rebootOnSuccess) { + //let serial/network finish tasks that might be given in _end_callback + delay(100); + ESP.restart(); + } + } else { + if (_error_callback) { + _error_callback(OTA_END_ERROR); + } + _updater->printError(client); + client.stop(); + delay(10); + log_e("Update ERROR: %s", _updater->errorString()); + _state = OTA_IDLE; + } +} + +void ArduinoOTAClass::end() { + _initialized = false; + _udp_ota.stop(); +#ifdef CONFIG_MDNS_MAX_INTERFACES + if (_mdnsEnabled) { + MDNS.end(); + } +#endif + _state = OTA_IDLE; + log_i("OTA server stopped."); +} + +void ArduinoOTAClass::handle() { + if (!_initialized) { + return; + } + if (_state == OTA_RUNUPDATE) { + _runUpdate(); + _state = OTA_IDLE; + } + if (_udp_ota.parsePacket()) { + _onRx(); + } + _udp_ota.clear(); // always clear, even zero length packets must be cleared. +} + +int ArduinoOTAClass::getCommand() { + return _cmd; +} + +void ArduinoOTAClass::setTimeout(int timeoutInMillis) { + _ota_timeout = timeoutInMillis; +} + +ArduinoOTAClass &ArduinoOTAClass::setUpdaterInstance(UpdateClass *updater) { + _updater = updater; + return *this; +} + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_ARDUINOOTA) +ArduinoOTAClass ArduinoOTA; +#endif diff --git a/libraries/ArduinoOTA/src/ArduinoOTA.h b/libraries/ArduinoOTA/src/ArduinoOTA.h new file mode 100644 index 0000000..e291f1b --- /dev/null +++ b/libraries/ArduinoOTA/src/ArduinoOTA.h @@ -0,0 +1,149 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ARDUINO_OTA_H +#define __ARDUINO_OTA_H + +#include "Network.h" +#include "Update.h" +#include + +#define INT_BUFFER_SIZE 16 + +typedef enum { + OTA_IDLE, + OTA_WAITAUTH, + OTA_RUNUPDATE +} ota_state_t; + +typedef enum { + OTA_AUTH_ERROR, + OTA_BEGIN_ERROR, + OTA_CONNECT_ERROR, + OTA_RECEIVE_ERROR, + OTA_END_ERROR +} ota_error_t; + +class ArduinoOTAClass { +public: + typedef std::function THandlerFunction; + typedef std::function THandlerFunction_Error; + typedef std::function THandlerFunction_Progress; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_UPDATE) + ArduinoOTAClass(UpdateClass *updater = &Update); +#else + ArduinoOTAClass(UpdateClass *updater = nullptr); +#endif + ~ArduinoOTAClass(); + + //Sets the service port. Default 3232 + ArduinoOTAClass &setPort(uint16_t port); + + //Sets the device hostname. Default esp32-xxxxxx + ArduinoOTAClass &setHostname(const char *hostname); + String getHostname(); + + //Sets the password that will be required for OTA. Default NULL + ArduinoOTAClass &setPassword(const char *password); + + //Sets the password as above but in the form SHA256(password). Default NULL + ArduinoOTAClass &setPasswordHash(const char *password); + + //Sets the partition label to write to when updating SPIFFS. Default NULL + ArduinoOTAClass &setPartitionLabel(const char *partition_label); + String getPartitionLabel(); + + //Sets instance of UpdateClass to perform updating operations + ArduinoOTAClass &setUpdaterInstance(UpdateClass *updater); + + //Sets if the device should be rebooted after successful update. Default true + ArduinoOTAClass &setRebootOnSuccess(bool reboot); + + //Sets if the device should advertise itself to Arduino IDE. Default true + ArduinoOTAClass &setMdnsEnabled(bool enabled); + +#ifdef UPDATE_SIGN + //Install signature verification for OTA updates + //Must be called before begin() + //sign: Signature verifier to use (e.g., UpdaterRSAVerifier or UpdaterECDSAVerifier) + // The hash type is determined from the verifier's configuration + ArduinoOTAClass &setSignature(UpdaterVerifyClass *sign); +#endif /* UPDATE_SIGN */ + + //This callback will be called when OTA connection has begun + ArduinoOTAClass &onStart(THandlerFunction fn); + + //This callback will be called when OTA has finished + ArduinoOTAClass &onEnd(THandlerFunction fn); + + //This callback will be called when OTA encountered Error + ArduinoOTAClass &onError(THandlerFunction_Error fn); + + //This callback will be called when OTA is receiving data + ArduinoOTAClass &onProgress(THandlerFunction_Progress fn); + + //Starts the ArduinoOTA service + void begin(); + + //Ends the ArduinoOTA service + void end(); + + //Call this in loop() to run the service + void handle(); + + //Gets update command type after OTA has started. Either U_FLASH or U_SPIFFS + int getCommand(); + + void setTimeout(int timeoutInMillis); + +private: + UpdateClass *_updater; + int _port; + String _password; + String _hostname; + String _partition_label; + String _nonce; + NetworkUDP _udp_ota; + bool _initialized; + bool _rebootOnSuccess; + bool _mdnsEnabled; + ota_state_t _state; + int _size; + int _cmd; + int _ota_port; + int _ota_timeout; + IPAddress _ota_ip; + String _md5; + + THandlerFunction _start_callback; + THandlerFunction _end_callback; + THandlerFunction_Error _error_callback; + THandlerFunction_Progress _progress_callback; + +#ifdef UPDATE_SIGN + UpdaterVerifyClass *_sign; +#endif /* UPDATE_SIGN */ + + void _runUpdate(void); + void _onRx(void); + int parseInt(void); + String readStringUntil(char end); +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_ARDUINOOTA) +extern ArduinoOTAClass ArduinoOTA; +#endif + +#endif /* __ARDUINO_OTA_H */ diff --git a/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino b/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino new file mode 100644 index 0000000..75be68a --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino @@ -0,0 +1,49 @@ +#include "WiFi.h" +#include "AsyncUDP.h" + +const char *ssid = "***********"; +const char *password = "***********"; + +AsyncUDP udp; + +void setup() { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Failed"); + while (1) { + delay(1000); + } + } + if (udp.connect(IPAddress(192, 168, 1, 100), 1234)) { + Serial.println("UDP connected"); + udp.onPacket([](AsyncUDPPacket packet) { + Serial.print("UDP Packet Type: "); + Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast"); + Serial.print(", From: "); + Serial.print(packet.remoteIP()); + Serial.print(":"); + Serial.print(packet.remotePort()); + Serial.print(", To: "); + Serial.print(packet.localIP()); + Serial.print(":"); + Serial.print(packet.localPort()); + Serial.print(", Length: "); + Serial.print(packet.length()); + Serial.print(", Data: "); + Serial.write(packet.data(), packet.length()); + Serial.println(); + //reply to the client + packet.printf("Got %zu bytes of data", packet.length()); + }); + //Send unicast + udp.print("Hello Server!"); + } +} + +void loop() { + delay(1000); + //Send broadcast on port 1234 + udp.broadcastTo("Anyone here?", 1234); +} diff --git a/libraries/AsyncUDP/examples/AsyncUDPClient/ci.yml b/libraries/AsyncUDP/examples/AsyncUDPClient/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPClient/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino new file mode 100644 index 0000000..c5a59f8 --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino @@ -0,0 +1,50 @@ +#include "WiFi.h" +#include "AsyncUDP.h" + +const char *ssid = "***********"; +const char *password = "***********"; + +AsyncUDP udp; + +void setup() { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Failed"); + while (1) { + delay(1000); + } + } + if (udp.listenMulticast(IPAddress(239, 1, 2, 3), 1234)) { + Serial.print("UDP Listening on IP: "); + Serial.println(WiFi.localIP()); + udp.onPacket([](AsyncUDPPacket packet) { + Serial.print("UDP Packet Type: "); + Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast"); + Serial.print(", From: "); + Serial.print(packet.remoteIP()); + Serial.print(":"); + Serial.print(packet.remotePort()); + Serial.print(", To: "); + Serial.print(packet.localIP()); + Serial.print(":"); + Serial.print(packet.localPort()); + Serial.print(", Length: "); + Serial.print(packet.length()); + Serial.print(", Data: "); + Serial.write(packet.data(), packet.length()); + Serial.println(); + //reply to the client + packet.printf("Got %zu bytes of data", packet.length()); + }); + //Send multicast + udp.print("Hello!"); + } +} + +void loop() { + delay(1000); + //Send multicast + udp.print("Anyone here?"); +} diff --git a/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.yml b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino b/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino new file mode 100644 index 0000000..be93a9d --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino @@ -0,0 +1,48 @@ +#include "WiFi.h" +#include "AsyncUDP.h" + +const char *ssid = "***********"; +const char *password = "***********"; + +AsyncUDP udp; + +void setup() { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Failed"); + while (1) { + delay(1000); + } + } + if (udp.listen(1234)) { + Serial.print("UDP Listening on IP: "); + Serial.println(WiFi.localIP()); + udp.onPacket([](AsyncUDPPacket packet) { + Serial.print("UDP Packet Type: "); + Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast"); + Serial.print(", From: "); + Serial.print(packet.remoteIP()); + Serial.print(":"); + Serial.print(packet.remotePort()); + Serial.print(", To: "); + Serial.print(packet.localIP()); + Serial.print(":"); + Serial.print(packet.localPort()); + Serial.print(", Length: "); + Serial.print(packet.length()); + Serial.print(", Data: "); + Serial.write(packet.data(), packet.length()); + Serial.println(); + //reply to the client + packet.printf("Got %zu bytes of data", packet.length()); + }); + } +} + +void loop() { + delay(1000); + //Send broadcast + udp.broadcast("Anyone here?"); +} diff --git a/libraries/AsyncUDP/examples/AsyncUDPServer/ci.yml b/libraries/AsyncUDP/examples/AsyncUDPServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/AsyncUDP/examples/AsyncUDPServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/AsyncUDP/keywords.txt b/libraries/AsyncUDP/keywords.txt new file mode 100644 index 0000000..1401ea6 --- /dev/null +++ b/libraries/AsyncUDP/keywords.txt @@ -0,0 +1,59 @@ +####################################### +# Syntax Coloring Map For Ultrasound +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +AsyncUDP KEYWORD1 +AsyncUDPPacket KEYWORD1 +AsyncUDPMessage KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +connect KEYWORD2 +connected KEYWORD2 +listen KEYWORD2 +listenMulticast KEYWORD2 +close KEYWORD2 +write KEYWORD2 +space KEYWORD2 +flush KEYWORD2 +isBroadcast KEYWORD2 +isMulticast KEYWORD2 +isIPv6 KEYWORD2 +interface KEYWORD2 +localIPv6 KEYWORD2 +remoteIPv6 KEYWORD2 +remoteMac KEYWORD2 +send KEYWORD2 +peek KEYWORD2 +available KEYWORD2 +writeTo KEYWORD2 +broadcastTo KEYWORD2 +sendTo KEYWORD2 +broadcast KEYWORD2 +onPacket KEYWORD2 +data KEYWORD2 +length KEYWORD2 +localIP KEYWORD2 +localPort KEYWORD2 +remoteIP KEYWORD2 +remotePort KEYWORD2 +listenIP KEYWORD2 +listenIPv6 KEYWORD2 +lastErr KEYWORD2 +_s_recv KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +TCPIP_ADAPTER_IF_STA LITERAL1 +TCPIP_ADAPTER_IF_STA LITERAL1 +TCPIP_ADAPTER_IF_AP LITERAL1 +TCPIP_ADAPTER_IF_ETH LITERAL1 +TCPIP_ADAPTER_IF_PPP LITERAL1 diff --git a/libraries/AsyncUDP/library.properties b/libraries/AsyncUDP/library.properties new file mode 100644 index 0000000..3236577 --- /dev/null +++ b/libraries/AsyncUDP/library.properties @@ -0,0 +1,9 @@ +name=ESP32 Async UDP +version=3.3.7 +author=Me-No-Dev +maintainer=Me-No-Dev +sentence=Async UDP Library for ESP32 +paragraph=Async UDP Library for ESP32 +category=Other +url=https://github.com/me-no-dev/ESPAsyncUDP +architectures=* diff --git a/libraries/AsyncUDP/src/AsyncUDP.cpp b/libraries/AsyncUDP/src/AsyncUDP.cpp new file mode 100644 index 0000000..b9832fc --- /dev/null +++ b/libraries/AsyncUDP/src/AsyncUDP.cpp @@ -0,0 +1,942 @@ +#include "Arduino.h" +#include "AsyncUDP.h" + +extern "C" { +#include "lwip/opt.h" +#include "lwip/inet.h" +#include "lwip/udp.h" +#include "lwip/igmp.h" +#include "lwip/ip_addr.h" +#include "lwip/mld6.h" +#include "lwip/prot/ethernet.h" +#include +#include +} + +#include "lwip/priv/tcpip_priv.h" + +#define CONFIG_UDP_MSS 1460 + +#ifndef CONFIG_ARDUINO_UDP_TASK_STACK_SIZE +#define CONFIG_ARDUINO_UDP_TASK_STACK_SIZE 4096 +#endif +#ifndef ARDUINO_UDP_TASK_STACK_SIZE +#define ARDUINO_UDP_TASK_STACK_SIZE CONFIG_ARDUINO_UDP_TASK_STACK_SIZE +#endif + +#ifndef CONFIG_ARDUINO_UDP_TASK_PRIORITY +#define CONFIG_ARDUINO_UDP_TASK_PRIORITY 3 +#endif +#ifndef ARDUINO_UDP_TASK_PRIORITY +#define ARDUINO_UDP_TASK_PRIORITY CONFIG_ARDUINO_UDP_TASK_PRIORITY +#endif + +#ifndef CONFIG_ARDUINO_UDP_RUNNING_CORE +#define CONFIG_ARDUINO_UDP_RUNNING_CORE -1 +#endif +#ifndef ARDUINO_UDP_RUNNING_CORE +#define ARDUINO_UDP_RUNNING_CORE CONFIG_ARDUINO_UDP_RUNNING_CORE +#endif + +#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING +#define UDP_MUTEX_LOCK() \ + if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { \ + LOCK_TCPIP_CORE(); \ + } + +#define UDP_MUTEX_UNLOCK() \ + if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { \ + UNLOCK_TCPIP_CORE(); \ + } +#else // CONFIG_LWIP_TCPIP_CORE_LOCKING +#define UDP_MUTEX_LOCK() +#define UDP_MUTEX_UNLOCK() +#endif // CONFIG_LWIP_TCPIP_CORE_LOCKING + +static const char *netif_ifkeys[TCPIP_ADAPTER_IF_MAX] = {"WIFI_STA_DEF", "WIFI_AP_DEF", "ETH_DEF", "PPP_DEF"}; + +static esp_err_t tcpip_adapter_get_netif(tcpip_adapter_if_t tcpip_if, void **netif) { + *netif = NULL; + if (tcpip_if < TCPIP_ADAPTER_IF_MAX) { + esp_netif_t *esp_netif = esp_netif_get_handle_from_ifkey(netif_ifkeys[tcpip_if]); + if (esp_netif == NULL) { + return ESP_FAIL; + } + int netif_index = esp_netif_get_netif_impl_index(esp_netif); + if (netif_index < 0) { + return ESP_FAIL; + } + UDP_MUTEX_LOCK(); + *netif = (void *)netif_get_by_index(netif_index); + UDP_MUTEX_UNLOCK(); + } else { + *netif = netif_default; + } + return (*netif != NULL) ? ESP_OK : ESP_FAIL; +} + +typedef struct { + struct tcpip_api_call_data call; + udp_pcb *pcb; + const ip_addr_t *addr; + uint16_t port; + struct pbuf *pb; + struct netif *netif; + err_t err; +} udp_api_call_t; + +static err_t _udp_connect_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = udp_connect(msg->pcb, msg->addr, msg->port); + return msg->err; +} + +static err_t _udp_connect(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port) { + udp_api_call_t msg; + msg.pcb = pcb; + msg.addr = addr; + msg.port = port; + tcpip_api_call(_udp_connect_api, (struct tcpip_api_call_data *)&msg); + return msg.err; +} + +static err_t _udp_disconnect_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = 0; + udp_disconnect(msg->pcb); + return msg->err; +} + +static void _udp_disconnect(struct udp_pcb *pcb) { + udp_api_call_t msg; + msg.pcb = pcb; + tcpip_api_call(_udp_disconnect_api, (struct tcpip_api_call_data *)&msg); +} + +static err_t _udp_remove_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = 0; + udp_remove(msg->pcb); + return msg->err; +} + +static void _udp_remove(struct udp_pcb *pcb) { + udp_api_call_t msg; + msg.pcb = pcb; + tcpip_api_call(_udp_remove_api, (struct tcpip_api_call_data *)&msg); +} + +static err_t _udp_bind_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = udp_bind(msg->pcb, msg->addr, msg->port); + return msg->err; +} + +static err_t _udp_bind(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port) { + udp_api_call_t msg; + msg.pcb = pcb; + msg.addr = addr; + msg.port = port; + tcpip_api_call(_udp_bind_api, (struct tcpip_api_call_data *)&msg); + return msg.err; +} + +static err_t _udp_sendto_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = udp_sendto(msg->pcb, msg->pb, msg->addr, msg->port); + return msg->err; +} + +static err_t _udp_sendto(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port) { + udp_api_call_t msg; + msg.pcb = pcb; + msg.addr = addr; + msg.port = port; + msg.pb = pb; + tcpip_api_call(_udp_sendto_api, (struct tcpip_api_call_data *)&msg); + return msg.err; +} + +static err_t _udp_sendto_if_api(struct tcpip_api_call_data *api_call_msg) { + udp_api_call_t *msg = (udp_api_call_t *)api_call_msg; + msg->err = udp_sendto_if(msg->pcb, msg->pb, msg->addr, msg->port, msg->netif); + return msg->err; +} + +static err_t _udp_sendto_if(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port, struct netif *netif) { + udp_api_call_t msg; + msg.pcb = pcb; + msg.addr = addr; + msg.port = port; + msg.pb = pb; + msg.netif = netif; + tcpip_api_call(_udp_sendto_if_api, (struct tcpip_api_call_data *)&msg); + return msg.err; +} + +typedef struct { + void *arg; + udp_pcb *pcb; + pbuf *pb; + const ip_addr_t *addr; + uint16_t port; + struct netif *netif; +} lwip_event_packet_t; + +static QueueHandle_t _udp_queue; +static volatile TaskHandle_t _udp_task_handle = NULL; + +static void _udp_task(void *pvParameters) { + (void)pvParameters; + lwip_event_packet_t *e = NULL; + for (;;) { + if (xQueueReceive(_udp_queue, &e, portMAX_DELAY) == pdTRUE) { + if (!e->pb) { + free((void *)(e)); + continue; + } + AsyncUDP::_s_recv(e->arg, e->pcb, e->pb, e->addr, e->port, e->netif); + free((void *)(e)); + } + } + _udp_task_handle = NULL; + vTaskDelete(NULL); +} + +static bool _udp_task_start() { + if (!_udp_queue) { + _udp_queue = xQueueCreate(32, sizeof(lwip_event_packet_t *)); + if (!_udp_queue) { + return false; + } + } + if (!_udp_task_handle) { + xTaskCreateUniversal( + _udp_task, "async_udp", ARDUINO_UDP_TASK_STACK_SIZE, NULL, ARDUINO_UDP_TASK_PRIORITY, (TaskHandle_t *)&_udp_task_handle, ARDUINO_UDP_RUNNING_CORE + ); + if (!_udp_task_handle) { + return false; + } + } + return true; +} + +static bool _udp_task_post(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif) { + if (!_udp_task_handle || !_udp_queue) { + return false; + } + lwip_event_packet_t *e = (lwip_event_packet_t *)malloc(sizeof(lwip_event_packet_t)); + if (!e) { + return false; + } + e->arg = arg; + e->pcb = pcb; + e->pb = pb; + e->addr = addr; + e->port = port; + e->netif = netif; + if (xQueueSend(_udp_queue, &e, portMAX_DELAY) != pdPASS) { + free((void *)(e)); + return false; + } + return true; +} + +static void _udp_recv(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port) { + while (pb != NULL) { + pbuf *this_pb = pb; + pb = pb->next; + this_pb->next = NULL; + if (!_udp_task_post(arg, pcb, this_pb, addr, port, ip_current_input_netif())) { + pbuf_free(this_pb); + } + } +} +/* +static bool _udp_task_stop(){ + if(!_udp_task_post(NULL, NULL, NULL, NULL, 0, NULL)){ + return false; + } + while(_udp_task_handle){ + vTaskDelay(10); + } + + lwip_event_packet_t * e; + while (xQueueReceive(_udp_queue, &e, 0) == pdTRUE) { + if(e->pb){ + pbuf_free(e->pb); + } + free((void*)(e)); + } + vQueueDelete(_udp_queue); + _udp_queue = NULL; +} +*/ + +AsyncUDPMessage::AsyncUDPMessage(size_t size) { + _index = 0; + if (size > CONFIG_UDP_MSS) { + size = CONFIG_UDP_MSS; + } + _size = size; + _buffer = (uint8_t *)malloc(size); +} + +AsyncUDPMessage::~AsyncUDPMessage() { + if (_buffer) { + free(_buffer); + } +} + +size_t AsyncUDPMessage::write(const uint8_t *data, size_t len) { + if (_buffer == NULL) { + return 0; + } + size_t s = space(); + if (len > s) { + len = s; + } + memcpy(_buffer + _index, data, len); + _index += len; + return len; +} + +size_t AsyncUDPMessage::write(uint8_t data) { + return write(&data, 1); +} + +size_t AsyncUDPMessage::space() { + if (_buffer == NULL) { + return 0; + } + return _size - _index; +} + +uint8_t *AsyncUDPMessage::data() { + return _buffer; +} + +size_t AsyncUDPMessage::length() { + return _index; +} + +void AsyncUDPMessage::flush() { + _index = 0; +} + +AsyncUDPPacket::AsyncUDPPacket(AsyncUDPPacket &packet) { + _udp = packet._udp; + _pb = packet._pb; + _if = packet._if; + _data = packet._data; + _len = packet._len; + _index = 0; + + memcpy(&_remoteIp, &packet._remoteIp, sizeof(ip_addr_t)); + memcpy(&_localIp, &packet._localIp, sizeof(ip_addr_t)); + _localPort = packet._localPort; + _remotePort = packet._remotePort; + memcpy(_remoteMac, packet._remoteMac, 6); + + pbuf_ref(_pb); +} + +AsyncUDPPacket &AsyncUDPPacket::operator=(const AsyncUDPPacket &packet) { + if (this != &packet) { + if (_pb) { + // Free existing pbuf reference + pbuf_free(_pb); + } + + // Copy all members + _udp = packet._udp; + _pb = packet._pb; + _if = packet._if; + _data = packet._data; + _len = packet._len; + _index = 0; + + memcpy(&_remoteIp, &packet._remoteIp, sizeof(ip_addr_t)); + memcpy(&_localIp, &packet._localIp, sizeof(ip_addr_t)); + _localPort = packet._localPort; + _remotePort = packet._remotePort; + memcpy(_remoteMac, packet._remoteMac, 6); + + // Increment reference count for the new pbuf + pbuf_ref(_pb); + } + return *this; +} + +AsyncUDPPacket::AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *raddr, uint16_t rport, struct netif *ntif) { + _udp = udp; + _pb = pb; + _if = TCPIP_ADAPTER_IF_MAX; + _data = (uint8_t *)(pb->payload); + _len = pb->len; + _index = 0; + + pbuf_ref(_pb); + + //memcpy(&_remoteIp, raddr, sizeof(ip_addr_t)); +#if CONFIG_LWIP_IPV6 + _remoteIp.type = raddr->type; + _localIp.type = _remoteIp.type; +#endif + + eth_hdr *eth = NULL; + udp_hdr *udphdr = (udp_hdr *)(_data - UDP_HLEN); + _localPort = ntohs(udphdr->dest); + _remotePort = ntohs(udphdr->src); + +#if CONFIG_LWIP_IPV6 + if (_remoteIp.type == IPADDR_TYPE_V4) { +#endif + eth = (eth_hdr *)(_data - UDP_HLEN - IP_HLEN - SIZEOF_ETH_HDR); + struct ip_hdr *iphdr = (struct ip_hdr *)(_data - UDP_HLEN - IP_HLEN); +#if CONFIG_LWIP_IPV6 + _localIp.u_addr.ip4.addr = iphdr->dest.addr; + _remoteIp.u_addr.ip4.addr = iphdr->src.addr; +#else + _localIp.addr = iphdr->dest.addr; + _remoteIp.addr = iphdr->src.addr; +#endif +#if CONFIG_LWIP_IPV6 + } else { + eth = (eth_hdr *)(_data - UDP_HLEN - IP6_HLEN - SIZEOF_ETH_HDR); + struct ip6_hdr *ip6hdr = (struct ip6_hdr *)(_data - UDP_HLEN - IP6_HLEN); + memcpy(&_localIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->dest.addr, 16); + memcpy(&_remoteIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->src.addr, 16); + } +#endif + memcpy(_remoteMac, eth->src.addr, 6); + + struct netif *netif = NULL; + void *nif = NULL; + int i; + for (i = 0; i < TCPIP_ADAPTER_IF_MAX; i++) { + tcpip_adapter_get_netif((tcpip_adapter_if_t)i, &nif); + netif = (struct netif *)nif; + if (netif && netif == ntif) { + _if = (tcpip_adapter_if_t)i; + break; + } + } +} + +AsyncUDPPacket::~AsyncUDPPacket() { + pbuf_free(_pb); +} + +uint8_t *AsyncUDPPacket::data() { + return _data; +} + +size_t AsyncUDPPacket::length() { + return _len; +} + +int AsyncUDPPacket::available() { + return _len - _index; +} + +size_t AsyncUDPPacket::read(uint8_t *data, size_t len) { + size_t i; + size_t a = _len - _index; + if (len > a) { + len = a; + } + for (i = 0; i < len; i++) { + data[i] = read(); + } + return len; +} + +int AsyncUDPPacket::read() { + if (_index < _len) { + return _data[_index++]; + } + return -1; +} + +int AsyncUDPPacket::peek() { + if (_index < _len) { + return _data[_index]; + } + return -1; +} + +void AsyncUDPPacket::flush() { + _index = _len; +} + +tcpip_adapter_if_t AsyncUDPPacket::interface() { + return _if; +} + +IPAddress AsyncUDPPacket::localIP() { +#if CONFIG_LWIP_IPV6 + if (_localIp.type != IPADDR_TYPE_V4) { + return IPAddress(); + } + return IPAddress(_localIp.u_addr.ip4.addr); +#else + return IPAddress(_localIp.addr); +#endif +} + +#if CONFIG_LWIP_IPV6 +IPAddress AsyncUDPPacket::localIPv6() { + if (_localIp.type != IPADDR_TYPE_V6) { + return IPAddress(IPv6); + } + return IPAddress(IPv6, (const uint8_t *)_localIp.u_addr.ip6.addr, _localIp.u_addr.ip6.zone); +} +#endif + +uint16_t AsyncUDPPacket::localPort() { + return _localPort; +} + +IPAddress AsyncUDPPacket::remoteIP() { +#if CONFIG_LWIP_IPV6 + if (_remoteIp.type != IPADDR_TYPE_V4) { + return IPAddress(); + } + return IPAddress(_remoteIp.u_addr.ip4.addr); +#else + return IPAddress(_remoteIp.addr); +#endif +} + +#if CONFIG_LWIP_IPV6 +IPAddress AsyncUDPPacket::remoteIPv6() { + if (_remoteIp.type != IPADDR_TYPE_V6) { + return IPAddress(IPv6); + } + return IPAddress(IPv6, (const uint8_t *)_remoteIp.u_addr.ip6.addr, _remoteIp.u_addr.ip6.zone); +} +#endif + +uint16_t AsyncUDPPacket::remotePort() { + return _remotePort; +} + +void AsyncUDPPacket::remoteMac(uint8_t *mac) { + memcpy(mac, _remoteMac, 6); +} + +bool AsyncUDPPacket::isIPv6() { +#if CONFIG_LWIP_IPV6 + return _localIp.type == IPADDR_TYPE_V6; +#else + return false; +#endif +} + +bool AsyncUDPPacket::isBroadcast() { +#if CONFIG_LWIP_IPV6 + if (_localIp.type == IPADDR_TYPE_V6) { + return false; + } + uint32_t ip = _localIp.u_addr.ip4.addr; +#else + uint32_t ip = _localIp.addr; +#endif + return ip == 0xFFFFFFFF || ip == 0 || (ip & 0xFF000000) == 0xFF000000; +} + +bool AsyncUDPPacket::isMulticast() { + return ip_addr_ismulticast(&(_localIp)); +} + +size_t AsyncUDPPacket::write(const uint8_t *data, size_t len) { + if (!data) { + return 0; + } + return _udp->writeTo(data, len, &_remoteIp, _remotePort, _if); +} + +size_t AsyncUDPPacket::write(uint8_t data) { + return write(&data, 1); +} + +size_t AsyncUDPPacket::send(AsyncUDPMessage &message) { + return write(message.data(), message.length()); +} + +bool AsyncUDP::_init() { + if (_pcb) { + return true; + } + UDP_MUTEX_LOCK(); + _pcb = udp_new(); + if (!_pcb) { + UDP_MUTEX_UNLOCK(); + return false; + } + udp_recv(_pcb, &_udp_recv, (void *)this); + UDP_MUTEX_UNLOCK(); + return true; +} + +AsyncUDP::AsyncUDP() { + _pcb = NULL; + _connected = false; + _lastErr = ERR_OK; + _handler = NULL; +} + +AsyncUDP::~AsyncUDP() { + close(); + UDP_MUTEX_LOCK(); + udp_recv(_pcb, NULL, NULL); + UDP_MUTEX_UNLOCK(); + _udp_remove(_pcb); + _pcb = NULL; +} + +void AsyncUDP::close() { + if (_pcb != NULL) { + if (_connected) { + _udp_disconnect(_pcb); + } + _connected = false; + //todo: unjoin multicast group + } +} + +bool AsyncUDP::connect(const ip_addr_t *addr, uint16_t port) { + if (!_udp_task_start()) { + log_e("failed to start task"); + return false; + } + if (!_init()) { + return false; + } + close(); + _lastErr = _udp_connect(_pcb, addr, port); + if (_lastErr != ERR_OK) { + return false; + } + _connected = true; + return true; +} + +bool AsyncUDP::listen(const ip_addr_t *addr, uint16_t port) { + if (!_udp_task_start()) { + log_e("failed to start task"); + return false; + } + if (!_init()) { + return false; + } + close(); + if (addr) { + IP_SET_TYPE_VAL(_pcb->local_ip, IP_GET_TYPE(addr)); + IP_SET_TYPE_VAL(_pcb->remote_ip, IP_GET_TYPE(addr)); + } + if (_udp_bind(_pcb, addr, port) != ERR_OK) { + return false; + } + _connected = true; + return true; +} + +static esp_err_t joinMulticastGroup(const ip_addr_t *addr, bool join, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX) { + struct netif *netif = NULL; + if (tcpip_if < TCPIP_ADAPTER_IF_MAX) { + void *nif = NULL; + esp_err_t err = tcpip_adapter_get_netif(tcpip_if, &nif); + if (err) { + return ESP_ERR_INVALID_ARG; + } + netif = (struct netif *)nif; + UDP_MUTEX_LOCK(); + +#if CONFIG_LWIP_IPV6 + if (addr->type == IPADDR_TYPE_V4) { + if (join) { + if (igmp_joingroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) { + goto igmp_fail; + } + } else { + if (igmp_leavegroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) { + goto igmp_fail; + } + } + } else { + if (join) { + if (mld6_joingroup_netif(netif, &(addr->u_addr.ip6))) { + goto igmp_fail; + } + } else { + if (mld6_leavegroup_netif(netif, &(addr->u_addr.ip6))) { + goto igmp_fail; + } + } + } +#else + if (join) { + if (igmp_joingroup_netif(netif, (const ip4_addr *)(addr))) { + goto igmp_fail; + } + } else { + if (igmp_leavegroup_netif(netif, (const ip4_addr *)(addr))) { + goto igmp_fail; + } + } +#endif + UDP_MUTEX_UNLOCK(); + } else { + UDP_MUTEX_LOCK(); +#if CONFIG_LWIP_IPV6 + if (addr->type == IPADDR_TYPE_V4) { + if (join) { + if (igmp_joingroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) { + goto igmp_fail; + } + } else { + if (igmp_leavegroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) { + goto igmp_fail; + } + } + } else { + if (join) { + if (mld6_joingroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) { + goto igmp_fail; + } + } else { + if (mld6_leavegroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) { + goto igmp_fail; + } + } + } +#else + if (join) { + if (igmp_joingroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)(addr))) { + goto igmp_fail; + } + } else { + if (igmp_leavegroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)(addr))) { + goto igmp_fail; + } + } +#endif + UDP_MUTEX_UNLOCK(); + } + return ESP_OK; + +igmp_fail: + UDP_MUTEX_UNLOCK(); + return ESP_ERR_INVALID_STATE; +} + +bool AsyncUDP::listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if) { + ip_addr_t bind_addr; + + if (!ip_addr_ismulticast(addr)) { + return false; + } + + if (joinMulticastGroup(addr, true, tcpip_if) != ERR_OK) { + return false; + } + + IP_SET_TYPE(&bind_addr, IP_GET_TYPE(addr)); + ip_addr_set_any(IP_IS_V6(addr), &bind_addr); + if (!listen(&bind_addr, port)) { + return false; + } + + _pcb->mcast_ttl = ttl; + _pcb->remote_port = port; + ip_addr_copy(_pcb->remote_ip, *addr); + //ip_addr_copy(_pcb->remote_ip, ip_addr_any_type); + + return true; +} + +size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if) { + if (!_pcb) { + UDP_MUTEX_LOCK(); + _pcb = udp_new(); + UDP_MUTEX_UNLOCK(); + if (_pcb == NULL) { + return 0; + } + } + if (len > CONFIG_UDP_MSS) { + len = CONFIG_UDP_MSS; + } + _lastErr = ERR_OK; + pbuf *pbt = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pbt != NULL) { + uint8_t *dst = reinterpret_cast(pbt->payload); + memcpy(dst, data, len); + if (tcpip_if < TCPIP_ADAPTER_IF_MAX) { + void *nif = NULL; + tcpip_adapter_get_netif((tcpip_adapter_if_t)tcpip_if, &nif); + if (!nif) { + _lastErr = _udp_sendto(_pcb, pbt, addr, port); + } else { + _lastErr = _udp_sendto_if(_pcb, pbt, addr, port, (struct netif *)nif); + } + } else { + _lastErr = _udp_sendto(_pcb, pbt, addr, port); + } + pbuf_free(pbt); + if (_lastErr < ERR_OK) { + return 0; + } + return len; + } + return 0; +} + +void AsyncUDP::_recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif) { + while (pb != NULL) { + pbuf *this_pb = pb; + pb = pb->next; + this_pb->next = NULL; + if (_handler) { + AsyncUDPPacket packet(this, this_pb, addr, port, netif); + _handler(packet); + } + pbuf_free(this_pb); + } +} + +void AsyncUDP::_s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif *netif) { + reinterpret_cast(arg)->_recv(upcb, p, addr, port, netif); +} + +bool AsyncUDP::listen(uint16_t port) { + return listen(IP_ANY_TYPE, port); +} + +bool AsyncUDP::listen(const IPAddress addr, uint16_t port) { + ip_addr_t laddr; + addr.to_ip_addr_t(&laddr); + return listen(&laddr, port); +} + +bool AsyncUDP::listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if) { + ip_addr_t laddr; + addr.to_ip_addr_t(&laddr); + return listenMulticast(&laddr, port, ttl, tcpip_if); +} + +bool AsyncUDP::connect(const IPAddress addr, uint16_t port) { + ip_addr_t daddr; + addr.to_ip_addr_t(&daddr); + return connect(&daddr, port); +} + +size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if) { + ip_addr_t daddr; + addr.to_ip_addr_t(&daddr); + return writeTo(data, len, &daddr, port, tcpip_if); +} + +IPAddress AsyncUDP::listenIP() { +#if CONFIG_LWIP_IPV6 + if (!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V4) { + return IPAddress(); + } + return IPAddress(_pcb->remote_ip.u_addr.ip4.addr); +#else + return IPAddress(_pcb->remote_ip.addr); +#endif +} + +#if CONFIG_LWIP_IPV6 +IPAddress AsyncUDP::listenIPv6() { + if (!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V6) { + return IPAddress(IPv6); + } + return IPAddress(IPv6, (const uint8_t *)_pcb->remote_ip.u_addr.ip6.addr, _pcb->remote_ip.u_addr.ip6.zone); +} +#endif + +size_t AsyncUDP::write(const uint8_t *data, size_t len) { + return writeTo(data, len, &(_pcb->remote_ip), _pcb->remote_port); +} + +size_t AsyncUDP::write(uint8_t data) { + return write(&data, 1); +} + +size_t AsyncUDP::broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if) { + return writeTo(data, len, IP_ADDR_BROADCAST, port, tcpip_if); +} + +size_t AsyncUDP::broadcastTo(const char *data, uint16_t port, tcpip_adapter_if_t tcpip_if) { + return broadcastTo((uint8_t *)data, strlen(data), port, tcpip_if); +} + +size_t AsyncUDP::broadcast(uint8_t *data, size_t len) { + if (_pcb->local_port != 0) { + return broadcastTo(data, len, _pcb->local_port); + } + return 0; +} + +size_t AsyncUDP::broadcast(const char *data) { + return broadcast((uint8_t *)data, strlen(data)); +} + +size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if) { + if (!message) { + return 0; + } + return writeTo(message.data(), message.length(), addr, port, tcpip_if); +} + +size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if) { + if (!message) { + return 0; + } + return writeTo(message.data(), message.length(), addr, port, tcpip_if); +} + +size_t AsyncUDP::send(AsyncUDPMessage &message) { + if (!message) { + return 0; + } + return writeTo(message.data(), message.length(), &(_pcb->remote_ip), _pcb->remote_port); +} + +size_t AsyncUDP::broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if) { + if (!message) { + return 0; + } + return broadcastTo(message.data(), message.length(), port, tcpip_if); +} + +size_t AsyncUDP::broadcast(AsyncUDPMessage &message) { + if (!message) { + return 0; + } + return broadcast(message.data(), message.length()); +} + +AsyncUDP::operator bool() { + return _connected; +} + +bool AsyncUDP::connected() { + return _connected; +} + +esp_err_t AsyncUDP::lastErr() { + return _lastErr; +} + +void AsyncUDP::onPacket(AuPacketHandlerFunctionWithArg cb, void *arg) { + onPacket(std::bind(cb, arg, std::placeholders::_1)); +} + +void AsyncUDP::onPacket(AuPacketHandlerFunction cb) { + _handler = cb; +} diff --git a/libraries/AsyncUDP/src/AsyncUDP.h b/libraries/AsyncUDP/src/AsyncUDP.h new file mode 100644 index 0000000..9f47788 --- /dev/null +++ b/libraries/AsyncUDP/src/AsyncUDP.h @@ -0,0 +1,166 @@ +#ifndef ESPASYNCUDP_H +#define ESPASYNCUDP_H + +#include "IPAddress.h" +#include "Print.h" +#include "Stream.h" +#include +extern "C" { +#include "esp_netif.h" +#include "lwip/ip_addr.h" +#include "freertos/queue.h" +#include "freertos/semphr.h" +} + +// This enum and it's uses are copied and adapted for compatibility from ESP-IDF 4- +typedef enum { + TCPIP_ADAPTER_IF_STA = 0, /**< Wi-Fi STA (station) interface */ + TCPIP_ADAPTER_IF_AP, /**< Wi-Fi soft-AP interface */ + TCPIP_ADAPTER_IF_ETH, /**< Ethernet interface */ + TCPIP_ADAPTER_IF_PPP, /**< PPP interface */ + TCPIP_ADAPTER_IF_MAX +} tcpip_adapter_if_t; + +class AsyncUDP; +class AsyncUDPPacket; +class AsyncUDPMessage; +struct udp_pcb; +struct pbuf; +struct netif; + +typedef std::function AuPacketHandlerFunction; +typedef std::function AuPacketHandlerFunctionWithArg; + +class AsyncUDPMessage : public Print { +protected: + uint8_t *_buffer; + size_t _index; + size_t _size; + +public: + AsyncUDPMessage(size_t size = CONFIG_TCP_MSS); + virtual ~AsyncUDPMessage(); + size_t write(const uint8_t *data, size_t len); + size_t write(uint8_t data); + size_t space(); + uint8_t *data(); + size_t length(); + void flush(); + operator bool() { + return _buffer != NULL; + } +}; + +class AsyncUDPPacket : public Stream { +protected: + AsyncUDP *_udp; + pbuf *_pb; + tcpip_adapter_if_t _if; + ip_addr_t _localIp; + uint16_t _localPort; + ip_addr_t _remoteIp; + uint16_t _remotePort; + uint8_t _remoteMac[6]; + uint8_t *_data; + size_t _len; + size_t _index; + +public: + AsyncUDPPacket(AsyncUDPPacket &packet); + AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif); + virtual ~AsyncUDPPacket(); + + uint8_t *data(); + size_t length(); + bool isBroadcast(); + bool isMulticast(); + bool isIPv6(); + + tcpip_adapter_if_t interface(); + + IPAddress localIP(); +#if CONFIG_LWIP_IPV6 + IPAddress localIPv6(); +#endif + uint16_t localPort(); + IPAddress remoteIP(); +#if CONFIG_LWIP_IPV6 + IPAddress remoteIPv6(); +#endif + uint16_t remotePort(); + void remoteMac(uint8_t *mac); + + size_t send(AsyncUDPMessage &message); + + int available(); + size_t read(uint8_t *data, size_t len); + int read(); + int peek(); + void flush(); + + size_t write(const uint8_t *data, size_t len); + size_t write(uint8_t data); + + // Copy assignment operator + AsyncUDPPacket &operator=(const AsyncUDPPacket &packet); +}; + +class AsyncUDP : public Print { +protected: + udp_pcb *_pcb; + //SemaphoreHandle_t _lock; + bool _connected; + esp_err_t _lastErr; + AuPacketHandlerFunction _handler; + + bool _init(); + void _recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif); + +public: + AsyncUDP(); + virtual ~AsyncUDP(); + + void onPacket(AuPacketHandlerFunctionWithArg cb, void *arg = NULL); + void onPacket(AuPacketHandlerFunction cb); + + bool listen(const ip_addr_t *addr, uint16_t port); + bool listen(const IPAddress addr, uint16_t port); + bool listen(uint16_t port); + + bool listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl = 1, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + bool listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl = 1, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + + bool connect(const ip_addr_t *addr, uint16_t port); + bool connect(const IPAddress addr, uint16_t port); + + void close(); + + size_t writeTo(const uint8_t *data, size_t len, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t write(const uint8_t *data, size_t len); + size_t write(uint8_t data); + + size_t broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t broadcastTo(const char *data, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t broadcast(uint8_t *data, size_t len); + size_t broadcast(const char *data); + + size_t sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t send(AsyncUDPMessage &message); + + size_t broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX); + size_t broadcast(AsyncUDPMessage &message); + + IPAddress listenIP(); +#if CONFIG_LWIP_IPV6 + IPAddress listenIPv6(); +#endif + bool connected(); + esp_err_t lastErr(); + operator bool(); + + static void _s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif *netif); +}; + +#endif diff --git a/libraries/BLE/LICENSE b/libraries/BLE/LICENSE new file mode 100644 index 0000000..4558f79 --- /dev/null +++ b/libraries/BLE/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2017 Neil Kolban + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/libraries/BLE/README.md b/libraries/BLE/README.md new file mode 100644 index 0000000..b89d556 --- /dev/null +++ b/libraries/BLE/README.md @@ -0,0 +1,467 @@ +# BLE for ESP32 Arduino Core + +A comprehensive reference for ESP32 Bluetooth Low Energy (BLE) pairing and security implementation using the ESP32 Arduino BLE library. + +## Overview + +This guide provides ESP32 developers with comprehensive information about BLE security implementation using the ESP32 Arduino BLE library. It covers both Bluedroid (ESP32) and NimBLE (other SoCs) implementations with realistic scenarios and troubleshooting guidance. + +Issues and questions should be raised here: https://github.com/espressif/arduino-esp32/issues
(please don't use https://github.com/nkolban/esp32-snippets/issues or https://github.com/h2zero/NimBLE-Arduino/issues) + +## Security + +### Quick Start + +1. **Choose your ESP32's IO capabilities** using `ESP_IO_CAP_*` constants +2. **Configure authentication requirements** with properties or permissions +3. **Set up security** using `BLESecurity` class methods +4. **Handle stack differences** between Bluedroid (ESP32) and NimBLE (other SoCs) +5. **Test with NVS clearing** during development + +### Understanding BLE Pairing + +#### Pairing vs Bonding +- **Pairing**: The process of establishing encryption keys between devices +- **Bonding**: Storing those keys for future reconnections (persistent pairing) + +#### Pairing Types +- **Legacy Pairing**: Original BLE pairing (Bluetooth 4.0/4.1) +- **Secure Connections**: Enhanced security (Bluetooth 4.2+) using FIPS-approved algorithms + +#### Security Levels +- **Just Works**: Encryption without user verification (vulnerable to passive eavesdropping) +- **MITM Protected**: User verification prevents man-in-the-middle attacks + +### IO Capabilities Explained + +The ESP32 BLE library defines the following IO capabilities: + +| Capability | Library Constant | Can Display | Can Input | Can Confirm | Example Devices | +|------------|-----------------|-------------|-----------|-------------|-----------------| +| **No Input No Output** | `ESP_IO_CAP_NONE` | ❌ | ❌ | ❌ | Sensor nodes, beacons, simple actuators | +| **Display Only** | `ESP_IO_CAP_OUT` | ✅ | ❌ | ❌ | E-ink displays, LED matrix displays | +| **Keyboard Only** | `ESP_IO_CAP_IN` | ❌ | ✅ | ❌ | Button-only devices, rotary encoders | +| **Display Yes/No** | `ESP_IO_CAP_IO` | ✅ | ❌ | ✅ | Devices with display + confirmation button | +| **Keyboard Display** | `ESP_IO_CAP_KBDISP` | ✅ | ✅ | ✅ | Full-featured ESP32 devices with UI | + +### Pairing Methods Explained + +#### 🔓 Just Works +- **Security**: Encryption only (no MITM protection) +- **User Experience**: Automatic, no user interaction +- **Use Case**: Convenience over security (fitness trackers, mice) +- **Vulnerability**: Susceptible to passive eavesdropping during pairing + +#### 🔐 Passkey Entry +- **Security**: Full MITM protection +- **User Experience**: One device shows 6-digit code, other inputs it +- **Use Case**: Keyboards pairing to computers +- **Process**: + 1. Display device shows random 6-digit number (000000-999999) + 2. Input device user types the number + 3. Pairing succeeds if numbers match + +#### 🔐 Numeric Comparison (Secure Connections Only) +- **Security**: Full MITM protection +- **User Experience**: Both devices show same number, user confirms match +- **Use Case**: Two smartphones/tablets pairing +- **Process**: + 1. Both devices display identical 6-digit number + 2. User verifies numbers match on both screens + 3. User confirms "Yes" on both devices + +#### 🔐 Out-of-Band (OOB) (Not supported by this library) +- **Security**: Highest security level +- **User Experience**: Uses external channel (NFC, QR code) +- **Use Case**: High-security applications +- **Priority**: Always used when OOB data is available + +### Pairing Methods Compatibility Matrix + +Here is the compatibility matrix for the pairing methods depending on the IO capabilities of the devices. +Note that the initiator is the device that starts the pairing process (usually the client) and the responder is +the device that accepts the pairing request (usually the server). + +![Pairing Methods Compatibility Matrix](https://www.bluetooth.com/wp-content/uploads/2016/06/screen-shot-06-08-16-at-0124-pm.png) + +### Bluedroid vs NimBLE + +Bluedroid and NimBLE are two different Bluetooth stack implementations. + +#### Bluedroid + +Bluedroid is the default Bluetooth stack in ESP-IDF. It supports both Bluetooth Classic and Bluetooth LE. It is used by the ESP32 in the Arduino Core. + +Bluedroid requires more flash and RAM than NimBLE and access permissions for characteristics and descriptors are set using a specific API through the `setAccessPermissions()` function. + +The original source of the Bluedroid project, **which is not maintained anymore**, can be found here: https://github.com/nkolban/esp32-snippets + +**Bluedroid will be replaced by NimBLE in version 4.0.0 of the Arduino Core. Bluetooth Classic and Bluedroid will no longer be supported but can be used by using Arduino as an ESP-IDF component.** + +#### NimBLE + +NimBLE is a lightweight Bluetooth stack for Bluetooth LE only. It is used by all SoCs that are not the ESP32. + +NimBLE requires less flash and RAM than Bluedroid. Access permissions for characteristics are set using exclusive properties in the characteristic creation. Access permissions for descriptors are set using the `setAccessPermissions()` function just like in Bluedroid. + +Some parts of the NimBLE implementation are based on the work of h2zero, which can be found here: https://github.com/h2zero/NimBLE-Arduino. For a more customizable and feature-rich implementation of the NimBLE stack, you can use the [NimBLE-Arduino](https://github.com/h2zero/NimBLE-Arduino) library. + +### Common Scenarios + +Here are some common scenarios for the pairing methods depending on the IO capabilities of the devices. Check also the secure BLE examples in the ESP32 Arduino Core for more detailed usage examples. + +#### Scenario 1: Mobile App ↔ ESP32 Sensor Node +- **Devices**: Mobile (`ESP_IO_CAP_IO`) ↔ ESP32 Sensor (`ESP_IO_CAP_NONE`) +- **MITM**: Not achievable with this IO combination (falls back to Just Works) +- **Characteristic Authentication**: Bonding only +- **Result**: Just Works with bonding for reconnection +- **Use Case**: Weather stations, environmental monitors + +#### Scenario 2: ESP32 Smart Lock ↔ Mobile App +- **Devices**: ESP32 Lock (`ESP_IO_CAP_OUT`) ↔ Mobile (`ESP_IO_CAP_KBDISP`) +- **MITM**: Required for security +- **Characteristic Authentication**: Bonding + Secure Connection + MITM +- **Result**: Passkey Entry (ESP32 displays, mobile enters) +- **Implementation**: Static passkey or dynamic display + +#### Scenario 3: ESP32 Configuration Device ↔ Admin Tool +- **Devices**: ESP32 (`ESP_IO_CAP_KBDISP`) ↔ Admin Tool (`ESP_IO_CAP_KBDISP`) +- **MITM**: Required for configuration security +- **Characteristic Authentication**: Bonding + Secure Connection + MITM +- **Result**: + - Legacy: Passkey Entry + - Secure Connections: Numeric Comparison +- **Use Case**: Industrial IoT configuration, network setup + +#### Scenario 4: ESP32 Beacon ↔ Scanner App +- **Devices**: ESP32 Beacon (`ESP_IO_CAP_NONE`) ↔ Scanner (`ESP_IO_CAP_IO`) +- **MITM**: Not required (broadcast only) +- **Characteristic Authentication**: None +- **Result**: No pairing required +- **Use Case**: Asset tracking, proximity detection + +#### Scenario 5: ESP32 Smart Home Hub ↔ Multiple Devices +- **Devices**: ESP32 Hub (`ESP_IO_CAP_IO`) ↔ Various sensors (`ESP_IO_CAP_NONE`) +- **MITM**: Not possible when any of the peers are `ESP_IO_CAP_NONE` +- **Characteristic Authentication**: Bonding only (no MITM possible with `ESP_IO_CAP_NONE`) +- **Result**: Just Works only +- **Use Case**: Centralized home automation controller + +### Implementation Guidelines + +#### For ESP32 Device Developers + +##### Choosing IO Capabilities +```cpp +#include + +// Conservative approach - limits pairing methods but ensures compatibility +pSecurity->setCapability(ESP_IO_CAP_NONE); // Just Works only + +// Balanced approach - good UX with optional security +pSecurity->setCapability(ESP_IO_CAP_IO); // Just Works or Numeric Comparison + +// Maximum security - supports all methods +pSecurity->setCapability(ESP_IO_CAP_KBDISP); // All pairing methods available +``` + +##### Authentication Configuration +```cpp +BLESecurity *pSecurity = new BLESecurity(); + +// Low security applications (sensors, environmental monitoring) +pSecurity->setAuthenticationMode(ESP_LE_AUTH_NO_BOND); + +// Standard security with bonding (smart home devices) +pSecurity->setAuthenticationMode(ESP_LE_AUTH_BOND); + +// MITM protection required (access control, payments) +pSecurity->setAuthenticationMode(ESP_LE_AUTH_REQ_MITM | ESP_LE_AUTH_BOND); + +// Maximum security with Secure Connections (critical systems) +pSecurity->setAuthenticationMode(ESP_LE_AUTH_REQ_SC_MITM_BOND); + +// Alternative syntax (more readable for complex requirements) +pSecurity->setAuthenticationMode(true, true, true); // Bonding, MITM, Secure Connections +``` + +##### Static Passkey Example (from secure examples) +```cpp +// Set a static passkey for consistent pairing experience +#define DEVICE_PASSKEY 123456 +pSecurity->setPassKey(true, DEVICE_PASSKEY); // static=true, passkey=123456 +pSecurity->setCapability(ESP_IO_CAP_KBDISP); // Required for MITM even with static passkey +``` + +### Security Considerations + +#### When to Require MITM +- **Always**: Payment systems, medical devices, access control +- **Usually**: File transfers, personal data sync, keyboards +- **Optional**: Fitness trackers, environmental sensors, mice +- **Never**: Beacons, broadcast-only devices + +#### Legacy vs Secure Connections +- **Legacy**: Compatible with all BLE devices (2010+) +- **Secure Connections**: Better security but requires Bluetooth 4.2+ (2014+) +- **Recommendation**: Support both, prefer Secure Connections when available + +#### Implementation Differences +```cpp +// Basic characteristic properties (both stacks) +uint32_t properties = BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE; + +// NimBLE: Add authentication properties (ignored by Bluedroid) +properties |= BLECharacteristic::PROPERTY_READ_AUTHEN | BLECharacteristic::PROPERTY_WRITE_AUTHEN; + +BLECharacteristic *pCharacteristic = pService->createCharacteristic(CHAR_UUID, properties); + +// Bluedroid: Set access permissions (ignored by NimBLE) +pCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM | ESP_GATT_PERM_WRITE_ENC_MITM); + +// Check which stack is running +String stackType = BLEDevice::getBLEStackString(); +Serial.println("Using BLE stack: " + stackType); +``` + +#### Known Vulnerabilities +1. **Just Works**: Vulnerable to passive eavesdropping during initial pairing +2. **Legacy Pairing**: Uses weaker cryptographic algorithms +3. **Passkey Brute Force**: 6-digit passkeys have only 1M combinations +4. **Physical Security**: Displayed passkeys can be shoulder-surfed + +### Troubleshooting + +#### Common Issues + +##### Pairing Always Uses Just Works +```cpp +// ❌ Problem: Missing MITM flag +pSecurity->setAuthenticationMode(ESP_LE_AUTH_REQ_SC_BOND); + +// ✅ Solution: Add MITM protection +pSecurity->setAuthenticationMode(ESP_LE_AUTH_REQ_SC_MITM_BOND); +``` + +##### Static passkey not being requested / Nothing happens when trying to read secure characteristic +```cpp +// ❌ Problem: Wrong IO capability for MITM +pSecurity->setCapability(ESP_IO_CAP_NONE); // Can't support MITM + +// ✅ Solution: Set proper capability even for static passkey +pSecurity->setCapability(ESP_IO_CAP_KBDISP); // Required for MITM +pSecurity->setPassKey(true, 123456); +``` + +##### Secure Characteristic Access Fails +```cpp +// ❌ Problem: Wrong security method for stack +// Bluedroid approach (won't work on NimBLE) +uint32_t properties = BLECharacteristic::PROPERTY_READ; +pCharacteristic = pService->createCharacteristic(uuid, properties); +pCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM); // Ignored by NimBLE! + +// ✅ Solution: Use both methods for cross-compatibility +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_READ_AUTHEN; // For NimBLE +pCharacteristic = pService->createCharacteristic(uuid, properties); +pCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM); // For Bluedroid +``` + +##### Pairing Works Once, Then Fails (NVS Cache Issue) +```cpp +// ✅ Solution: Clear NVS for testing/development +Serial.println("Clearing NVS pairing data for testing..."); +nvs_flash_erase(); +nvs_flash_init(); +``` + +##### Default Passkey Warning +``` +*WARNING* Using default passkey: 123456 +*WARNING* Please use a random passkey or set a different static passkey +``` +```cpp +// ✅ Solution: Change from default +#define CUSTOM_PASSKEY 567890 // Your unique passkey +pSecurity->setPassKey(true, CUSTOM_PASSKEY); +``` + +##### Connection drops during pairing +```cpp +// ✅ Solution: Implement security callbacks for better error handling +class MySecurityCallbacks : public BLESecurityCallbacks { + void onAuthenticationComplete(esp_ble_auth_cmpl_t param) override { + if (param.success) { + Serial.println("Pairing successful!"); + } else { + Serial.printf("Pairing failed, reason: %d\n", param.fail_reason); + } + } +}; + +BLEDevice::setSecurityCallbacks(new MySecurityCallbacks()); +``` + +#### Cross-Platform Best Practice +```cpp +// Always use both methods for maximum compatibility +uint32_t secure_properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE | + BLECharacteristic::PROPERTY_READ_AUTHEN | // NimBLE + BLECharacteristic::PROPERTY_WRITE_AUTHEN; // NimBLE + +BLECharacteristic *pChar = pService->createCharacteristic(uuid, secure_properties); + +// Bluedroid permissions (ignored by NimBLE, but doesn't hurt) +pChar->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM | ESP_GATT_PERM_WRITE_ENC_MITM); +``` + +### Complete Properties and Permissions Reference + +#### Bluedroid + +Bluedroid uses properties to define the capabilities of a characteristic and permissions to define the access permissions. NimBLE will ignore the access permissions. + +##### Supported Properties +```cpp +BLECharacteristic::PROPERTY_READ // Read operation +BLECharacteristic::PROPERTY_WRITE // Write operation +BLECharacteristic::PROPERTY_WRITE_NR // Write without response +BLECharacteristic::PROPERTY_NOTIFY // Notifications +BLECharacteristic::PROPERTY_INDICATE // Indications +BLECharacteristic::PROPERTY_BROADCAST // Broadcast +``` + +##### Characteristic and Descriptor Access Permissions +```cpp +// Basic permissions +ESP_GATT_PERM_READ // Read allowed +ESP_GATT_PERM_WRITE // Write allowed + +// Encryption required +ESP_GATT_PERM_READ_ENCRYPTED // Read requires encryption +ESP_GATT_PERM_WRITE_ENCRYPTED // Write requires encryption + +// Authentication required (MITM protection) +ESP_GATT_PERM_READ_ENC_MITM // Read requires encryption + MITM +ESP_GATT_PERM_WRITE_ENC_MITM // Write requires encryption + MITM + +// Authorization required +ESP_GATT_PERM_READ_AUTHORIZATION // Read requires authorization callback +ESP_GATT_PERM_WRITE_AUTHORIZATION // Write requires authorization callback +``` + +#### NimBLE + +NimBLE uses properties to define both the capabilities of a characteristic and the access permissions. Bluedroid will ignore the NimBLE exclusive properties. + +##### Supported Properties +```cpp +// Basic properties +BLECharacteristic::PROPERTY_READ // Read operation +BLECharacteristic::PROPERTY_WRITE // Write operation +BLECharacteristic::PROPERTY_WRITE_NR // Write without response +BLECharacteristic::PROPERTY_NOTIFY // Notifications +BLECharacteristic::PROPERTY_INDICATE // Indications +BLECharacteristic::PROPERTY_BROADCAST // Broadcast + +// NimBLE specific properties + +// Encryption required +BLECharacteristic::PROPERTY_READ_ENC // Read requires encryption +BLECharacteristic::PROPERTY_WRITE_ENC // Write requires encryption + +// Authentication required (MITM protection) +BLECharacteristic::PROPERTY_READ_AUTHEN // Read requires encryption + MITM protection +BLECharacteristic::PROPERTY_WRITE_AUTHEN // Write requires encryption + MITM protection + +// Authorization required +BLECharacteristic::PROPERTY_READ_AUTHOR // Read requires authorization callback +BLECharacteristic::PROPERTY_WRITE_AUTHOR // Write requires authorization callback +``` + +##### Descriptor Access Permissions +```cpp +// Basic permissions +ESP_GATT_PERM_READ // Read allowed +ESP_GATT_PERM_WRITE // Write allowed + +// Encryption required +ESP_GATT_PERM_READ_ENCRYPTED // Read requires encryption +ESP_GATT_PERM_WRITE_ENCRYPTED // Write requires encryption + +// Authentication required (MITM protection) +ESP_GATT_PERM_READ_ENC_MITM // Read requires encryption + MITM +ESP_GATT_PERM_WRITE_ENC_MITM // Write requires encryption + MITM + +// Authorization required +ESP_GATT_PERM_READ_AUTHORIZATION // Read requires authorization callback +ESP_GATT_PERM_WRITE_AUTHORIZATION // Write requires authorization callback +``` + +#### Usage Examples by Security Level + +##### No Security (Both Stacks) +```cpp +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE; +``` + +##### Encryption Only +```cpp +// NimBLE +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE | + BLECharacteristic::PROPERTY_READ_ENC | + BLECharacteristic::PROPERTY_WRITE_ENC; + +// Bluedroid +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE; +pChar->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED); +``` + +##### MITM Protection (Authentication) +```cpp +// NimBLE +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE | + BLECharacteristic::PROPERTY_READ_AUTHEN | + BLECharacteristic::PROPERTY_WRITE_AUTHEN; + +// Bluedroid +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE; +pChar->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM | ESP_GATT_PERM_WRITE_ENC_MITM); +``` + +##### Authorization Required +```cpp +// NimBLE +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE | + BLECharacteristic::PROPERTY_READ_AUTHOR | + BLECharacteristic::PROPERTY_WRITE_AUTHOR; + +// Bluedroid +uint32_t properties = BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE; +pChar->setAccessPermissions(ESP_GATT_PERM_READ_AUTHORIZATION | ESP_GATT_PERM_WRITE_AUTHORIZATION); +``` + +#### Debug Tips +1. **Log pairing features** exchanged between devices +2. **Monitor pairing method** selected by the stack +3. **Check timeout values** for user input methods +4. **Verify key distribution** flags match on both sides + +### Standards References + +- **Bluetooth Core Specification v5.4**: Volume 3, Part H (Security Manager) +- **Bluetooth Assigned Numbers**: IO Capability values +- **FIPS-140-2**: Cryptographic standards for Secure Connections + +--- + +*This guide is based on the ESP32 Arduino BLE library implementation and the official Bluetooth Core Specification. For the latest API documentation, refer to the ESP32 Arduino BLE library source code and examples.* diff --git a/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino b/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino new file mode 100644 index 0000000..e50d733 --- /dev/null +++ b/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino @@ -0,0 +1,52 @@ +/* + BLE5 extended scan example for esp32 C3 and S3 + with this code it is simple to scan legacy (BLE4) compatible advertising, + and BLE5 extended advertising. New coded added in BLEScan is not changing old behavior, + which can be used with old esp32, but is adding functionality to use on C3/S3. + With this new API advertised device wont be stored in API, it is now user responsibility + + author: chegewara +*/ +#ifndef CONFIG_BLUEDROID_ENABLED +#error "NimBLE does not support extended scan yet. Try using Bluedroid." +#elif !defined(SOC_BLE_50_SUPPORTED) +#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3" +#else + +#include +#include +#include +#include + +uint32_t scanTime = 100; //In 10ms (1000ms) +BLEScan *pBLEScan; + +class MyBLEExtAdvertisingCallbacks : public BLEExtAdvertisingCallbacks { + void onResult(esp_ble_gap_ext_adv_report_t report) { + if (report.event_type & ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY) { + // here we can receive regular advertising data from BLE4.x devices + Serial.println("BLE4.2"); + } else { + // here we will get extended advertising data that are advertised over data channel by BLE5 devices + Serial.printf("Ext advertise: data_le: %d, data_status: %d \n", report.adv_data_len, report.data_status); + } + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Scanning..."); + + BLEDevice::init(""); + pBLEScan = BLEDevice::getScan(); //create new scan + pBLEScan->setExtendedScanCallback(new MyBLEExtAdvertisingCallbacks()); + pBLEScan->setExtScanParams(); // use with pre-defined/default values, overloaded function allows to pass parameters + delay(1000); // it is just for simplicity this example, to let ble stack to set extended scan params + pBLEScan->startExtScan(scanTime, 3); // scan duration in n * 10ms, period - repeat after n seconds (period >= duration) +} + +void loop() { + // put your main code here, to run repeatedly: + delay(2000); +} +#endif // SOC_BLE_50_SUPPORTED diff --git a/libraries/BLE/examples/BLE5_extended_scan/ci.yml b/libraries/BLE/examples/BLE5_extended_scan/ci.yml new file mode 100644 index 0000000..304e725 --- /dev/null +++ b/libraries/BLE/examples/BLE5_extended_scan/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_BLE_50_SUPPORTED=y + - CONFIG_BLUEDROID_ENABLED=y diff --git a/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino b/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino new file mode 100644 index 0000000..ee25f8e --- /dev/null +++ b/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino @@ -0,0 +1,143 @@ +/* + Simple BLE5 multi advertising example on esp32 C3/S3 + only ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND is backward compatible + and can be scanned with BLE4.2 devices + + author: chegewara +*/ + +#ifndef CONFIG_BLUEDROID_ENABLED +#error "NimBLE does not support multi advertising yet. Try using Bluedroid." +#elif !defined(CONFIG_BT_BLE_50_FEATURES_SUPPORTED) +#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3" +#else + +#include +#include + +esp_ble_gap_ext_adv_params_t ext_adv_params_1M = { + .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE, + .interval_min = 0x30, + .interval_max = 0x30, + .channel_map = ADV_CHNL_ALL, + .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr = {0, 0, 0, 0, 0, 0}, + .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, + .primary_phy = ESP_BLE_GAP_PHY_CODED, + .max_skip = 0, + .secondary_phy = ESP_BLE_GAP_PHY_1M, + .sid = 0, + .scan_req_notif = false, +}; + +esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { + .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE, + .interval_min = 0x40, + .interval_max = 0x40, + .channel_map = ADV_CHNL_ALL, + .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr = {0, 0, 0, 0, 0, 0}, + .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, + .primary_phy = ESP_BLE_GAP_PHY_1M, + .max_skip = 0, + .secondary_phy = ESP_BLE_GAP_PHY_2M, + .sid = 1, + .scan_req_notif = false, +}; + +esp_ble_gap_ext_adv_params_t legacy_adv_params = { + .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND, + .interval_min = 0x45, + .interval_max = 0x45, + .channel_map = ADV_CHNL_ALL, + .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr = {0, 0, 0, 0, 0, 0}, + .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, + .primary_phy = ESP_BLE_GAP_PHY_1M, + .max_skip = 0, + .secondary_phy = ESP_BLE_GAP_PHY_1M, + .sid = 2, + .scan_req_notif = false, +}; + +esp_ble_gap_ext_adv_params_t ext_adv_params_coded = { + .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE, + .interval_min = 0x50, + .interval_max = 0x50, + .channel_map = ADV_CHNL_ALL, + .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr = {0, 0, 0, 0, 0, 0}, + .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, + .primary_phy = ESP_BLE_GAP_PHY_1M, + .max_skip = 0, + .secondary_phy = ESP_BLE_GAP_PHY_CODED, + .sid = 3, + .scan_req_notif = false, +}; + +static uint8_t raw_adv_data_1m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M', + 'U', 'L', 'T', 'I', '_', 'A', 'D', 'V', '_', '1', 'M', 0X0}; + +static uint8_t raw_scan_rsp_data_2m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M', + 'U', 'L', 'T', 'I', '_', 'A', 'D', 'V', '_', '2', 'M', 0X0}; + +static uint8_t legacy_adv_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x15, 0x09, 'E', 'S', 'P', '_', 'M', 'U', + 'L', 'T', 'I', '_', 'A', 'D', 'V', '_', 'C', 'O', 'D', 'E', 'D', 0X0}; + +static uint8_t legacy_scan_rsp_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x16, 0x09, 'E', 'S', 'P', '_', 'M', 'U', 'L', + 'T', 'I', '_', 'A', 'D', 'V', '_', 'L', 'E', 'G', 'A', 'C', 'Y', 0X0}; + +static uint8_t raw_scan_rsp_data_coded[] = {0x37, 0x09, 'V', 'E', 'R', 'Y', '_', 'L', 'O', 'N', 'G', '_', 'D', 'E', 'V', 'I', 'C', 'E', '_', + 'N', 'A', 'M', 'E', '_', 'S', 'E', 'N', 'T', '_', 'U', 'S', 'I', 'N', 'G', '_', 'E', 'X', 'T', + 'E', 'N', 'D', 'E', 'D', '_', 'A', 'D', 'V', 'E', 'R', 'T', 'I', 'S', 'I', 'N', 'G', 0X0}; + +uint8_t addr_1m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x01}; +uint8_t addr_2m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x02}; +uint8_t addr_legacy[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x03}; +uint8_t addr_coded[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x04}; + +BLEMultiAdvertising advert(4); // max number of advertisement data + +void setup() { + Serial.begin(115200); + Serial.println("Multi-Advertising..."); + + BLEDevice::init(""); + + advert.setAdvertisingParams(0, &ext_adv_params_1M); + advert.setAdvertisingData(0, sizeof(raw_adv_data_1m), &raw_adv_data_1m[0]); + advert.setInstanceAddress(0, addr_1m); + advert.setDuration(0); + + advert.setAdvertisingParams(1, &ext_adv_params_2M); + advert.setScanRspData(1, sizeof(raw_scan_rsp_data_2m), &raw_scan_rsp_data_2m[0]); + advert.setInstanceAddress(1, addr_2m); + advert.setDuration(1); + + advert.setAdvertisingParams(2, &legacy_adv_params); + advert.setAdvertisingData(2, sizeof(legacy_adv_data), &legacy_adv_data[0]); + advert.setScanRspData(2, sizeof(legacy_scan_rsp_data), &legacy_scan_rsp_data[0]); + advert.setInstanceAddress(2, addr_legacy); + advert.setDuration(2); + + advert.setAdvertisingParams(3, &ext_adv_params_coded); + advert.setDuration(3); + advert.setScanRspData(3, sizeof(raw_scan_rsp_data_coded), &raw_scan_rsp_data_coded[0]); + advert.setInstanceAddress(3, addr_coded); + + delay(1000); + advert.start(4, 0); +} + +void loop() { + delay(2000); +} +#endif diff --git a/libraries/BLE/examples/BLE5_multi_advertising/ci.yml b/libraries/BLE/examples/BLE5_multi_advertising/ci.yml new file mode 100644 index 0000000..304e725 --- /dev/null +++ b/libraries/BLE/examples/BLE5_multi_advertising/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_BLE_50_SUPPORTED=y + - CONFIG_BLUEDROID_ENABLED=y diff --git a/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino b/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino new file mode 100644 index 0000000..effb7ef --- /dev/null +++ b/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino @@ -0,0 +1,70 @@ +/* + Simple BLE5 periodic advertising example on esp32 C3/S3 + only ESP_BLE_GAP_SET_EXT_ADV_PROP_NONCONN_NONSCANNABLE_UNDIRECTED can be used for periodic advertising + + author: chegewara +*/ + +#ifndef CONFIG_BLUEDROID_ENABLED +#error "NimBLE does not support periodic advertising yet. Try using Bluedroid." +#elif !defined(CONFIG_BT_BLE_50_FEATURES_SUPPORTED) +#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3" +#else +#include +#include + +esp_ble_gap_ext_adv_params_t ext_adv_params_2M = { + .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_NONCONN_NONSCANNABLE_UNDIRECTED, + .interval_min = 0x40, + .interval_max = 0x40, + .channel_map = ADV_CHNL_ALL, + .own_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr_type = BLE_ADDR_TYPE_RANDOM, + .peer_addr = {0, 0, 0, 0, 0, 0}, + .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, + .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE, + .primary_phy = ESP_BLE_GAP_PHY_1M, + .max_skip = 0, + .secondary_phy = ESP_BLE_GAP_PHY_2M, + .sid = 1, + .scan_req_notif = false, +}; + +static uint8_t raw_scan_rsp_data_2m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M', + 'U', 'L', 'T', 'I', '_', 'A', 'D', 'V', '_', '2', 'M', 0X0}; + +static esp_ble_gap_periodic_adv_params_t periodic_adv_params = { + .interval_min = 0x320, // 1000 ms interval + .interval_max = 0x640, + .properties = 0, // Do not include TX power +}; + +static uint8_t periodic_adv_raw_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x03, 0x03, 0xab, 0xcd, 0x11, 0x09, 'E', 'S', + 'P', '_', 'P', 'E', 'R', 'I', 'O', 'D', 'I', 'C', '_', 'A', 'D', 'V'}; + +uint8_t addr_2m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x02}; + +BLEMultiAdvertising advert(1); // max number of advertisement data + +void setup() { + Serial.begin(115200); + Serial.println("Multi-Advertising..."); + + BLEDevice::init(""); + + advert.setAdvertisingParams(0, &ext_adv_params_2M); + advert.setAdvertisingData(0, sizeof(raw_scan_rsp_data_2m), &raw_scan_rsp_data_2m[0]); + advert.setInstanceAddress(0, addr_2m); + advert.setDuration(0, 0, 0); + + delay(100); + advert.start(); + advert.setPeriodicAdvertisingParams(0, &periodic_adv_params); + advert.setPeriodicAdvertisingData(0, sizeof(periodic_adv_raw_data), &periodic_adv_raw_data[0]); + advert.startPeriodicAdvertising(0); +} + +void loop() { + delay(2000); +} +#endif diff --git a/libraries/BLE/examples/BLE5_periodic_advertising/ci.yml b/libraries/BLE/examples/BLE5_periodic_advertising/ci.yml new file mode 100644 index 0000000..304e725 --- /dev/null +++ b/libraries/BLE/examples/BLE5_periodic_advertising/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_BLE_50_SUPPORTED=y + - CONFIG_BLUEDROID_ENABLED=y diff --git a/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino b/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino new file mode 100644 index 0000000..a93ebce --- /dev/null +++ b/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino @@ -0,0 +1,93 @@ +/* + BLE5 extended scan example for esp32 C3 and S3 + with this code it is simple to scan legacy (BLE4) compatible advertising, + and BLE5 extended advertising. New coded added in BLEScan is not changing old behavior, + which can be used with old esp32, but is adding functionality to use on C3/S3. + With this new API advertised device wont be stored in API, it is now user responsibility + + author: chegewara +*/ +#ifndef CONFIG_BLUEDROID_ENABLED +#error "NimBLE does not support periodic sync yet. Try using Bluedroid." +#elif !defined(SOC_BLE_50_SUPPORTED) +#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3" +#else +#include +#include +#include + +BLEScan *pBLEScan; +static bool periodic_sync = false; + +static esp_ble_gap_periodic_adv_sync_params_t periodic_adv_sync_params = { + .filter_policy = 0, + .sid = 0, + .addr_type = BLE_ADDR_TYPE_RANDOM, + .addr = {0, 0, 0, 0, 0, 0}, + .skip = 10, + .sync_timeout = 1000, // timeout: 1000 * 10ms +}; + +class MyBLEExtAdvertisingCallbacks : public BLEExtAdvertisingCallbacks { + void onResult(esp_ble_gap_ext_adv_report_t params) { + uint8_t *adv_name = NULL; + uint8_t adv_name_len = 0; + adv_name = esp_ble_resolve_adv_data(params.adv_data, ESP_BLE_AD_TYPE_NAME_CMPL, &adv_name_len); + if ((adv_name != NULL) && (memcmp(adv_name, "ESP_MULTI_ADV_2M", adv_name_len) == 0) && !periodic_sync) { + periodic_sync = true; + char adv_temp_name[60] = {'0'}; + memcpy(adv_temp_name, adv_name, adv_name_len); + log_i("Start create sync with the peer device %s", adv_temp_name); + periodic_adv_sync_params.sid = params.sid; + // periodic_adv_sync_params.addr_type = params.addr_type; + memcpy(periodic_adv_sync_params.addr, params.addr, sizeof(esp_bd_addr_t)); + esp_ble_gap_periodic_adv_create_sync(&periodic_adv_sync_params); + } + } +}; + +class MyPeriodicScan : public BLEPeriodicScanCallbacks { + // void onCreateSync(esp_bt_status_t status){} + // void onCancelSync(esp_bt_status_t status){} + // void onTerminateSync(esp_bt_status_t status){} + + void onStop(esp_bt_status_t status) { + log_i("ESP_GAP_BLE_EXT_SCAN_STOP_COMPLETE_EVT"); + periodic_sync = false; + pBLEScan->startExtScan(0, 0); // scan duration in n * 10ms, period - repeat after n seconds (period >= duration) + } + + void onLostSync(uint16_t sync_handle) { + log_i("ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT"); + esp_ble_gap_stop_ext_scan(); + } + + void onSync(esp_ble_periodic_adv_sync_estab_param_t params) { + log_i("ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT, status %d", params.status); + // esp_log_buffer_hex("sync addr", param->periodic_adv_sync_estab.adv_addr, 6); + log_i("sync handle %d sid %d perioic adv interval %d adv phy %d", params.sync_handle, params.sid, params.period_adv_interval, params.adv_phy); + } + + void onReport(esp_ble_gap_periodic_adv_report_t params) { + log_i("periodic adv report, sync handle %d data status %d data len %d rssi %d", params.sync_handle, params.data_status, params.data_length, params.rssi); + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Periodic scan..."); + + BLEDevice::init(""); + pBLEScan = BLEDevice::getScan(); //create new scan + pBLEScan->setExtendedScanCallback(new MyBLEExtAdvertisingCallbacks()); + pBLEScan->setExtScanParams(); // use with pre-defined/default values, overloaded function allows to pass parameters + pBLEScan->setPeriodicScanCallback(new MyPeriodicScan()); + delay(100); // it is just for simplicity this example, to let ble stack to set extended scan params + pBLEScan->startExtScan(0, 0); +} + +void loop() { + delay(2000); +} + +#endif // SOC_BLE_50_SUPPORTED diff --git a/libraries/BLE/examples/BLE5_periodic_sync/ci.yml b/libraries/BLE/examples/BLE5_periodic_sync/ci.yml new file mode 100644 index 0000000..304e725 --- /dev/null +++ b/libraries/BLE/examples/BLE5_periodic_sync/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_BLE_50_SUPPORTED=y + - CONFIG_BLUEDROID_ENABLED=y diff --git a/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino new file mode 100644 index 0000000..bdbf759 --- /dev/null +++ b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino @@ -0,0 +1,118 @@ +/* + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp + Ported to Arduino ESP32 by Evandro Copercini + Changed to a beacon scanner to report iBeacon, EddystoneURL and EddystoneTLM beacons by beegee-tokyo + Upgraded Eddystone part by Tomas Pilny on Feb 20, 2023 +*/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +int scanTime = 5; //In seconds +BLEScan *pBLEScan; + +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + void onResult(BLEAdvertisedDevice advertisedDevice) { + if (advertisedDevice.haveName()) { + Serial.print("Device name: "); + Serial.println(advertisedDevice.getName().c_str()); + Serial.println(""); + } + + if (advertisedDevice.haveServiceUUID()) { + BLEUUID devUUID = advertisedDevice.getServiceUUID(); + Serial.print("Found ServiceUUID: "); + Serial.println(devUUID.toString().c_str()); + Serial.println(""); + } + + if (advertisedDevice.haveManufacturerData() == true) { + String strManufacturerData = advertisedDevice.getManufacturerData(); + + // Buffer to store manufacturer data (BLE max is 255 bytes) + uint8_t cManufacturerData[255]; + size_t dataLength = strManufacturerData.length(); + + // Bounds checking to prevent buffer overflow + if (dataLength <= sizeof(cManufacturerData)) { + memcpy(cManufacturerData, strManufacturerData.c_str(), dataLength); + + if (dataLength == 25 && cManufacturerData[0] == 0x4C && cManufacturerData[1] == 0x00) { + Serial.println("Found an iBeacon!"); + BLEBeacon oBeacon = BLEBeacon(); + oBeacon.setData(strManufacturerData); + Serial.printf("iBeacon Frame\n"); + Serial.printf( + "ID: %04X Major: %d Minor: %d UUID: %s Power: %d\n", oBeacon.getManufacturerId(), ENDIAN_CHANGE_U16(oBeacon.getMajor()), + ENDIAN_CHANGE_U16(oBeacon.getMinor()), oBeacon.getProximityUUID().toString().c_str(), oBeacon.getSignalPower() + ); + } else { + Serial.println("Found another manufacturers beacon!"); + Serial.printf("strManufacturerData: %zu ", dataLength); + for (int i = 0; i < dataLength; i++) { + Serial.printf("[%X]", cManufacturerData[i]); + } + Serial.printf("\n"); + } + } else { + Serial.printf("Manufacturer data too large (%zu bytes), skipping\n", dataLength); + } + } + + if (advertisedDevice.getFrameType() == BLE_EDDYSTONE_URL_FRAME) { + Serial.println("Found an EddystoneURL beacon!"); + BLEEddystoneURL EddystoneURL = BLEEddystoneURL(&advertisedDevice); + Serial.printf("URL bytes: 0x"); + String url = EddystoneURL.getURL(); + for (auto byte : url) { + Serial.printf("%02X", byte); + } + Serial.printf("\n"); + Serial.printf("Decoded URL: %s\n", EddystoneURL.getDecodedURL().c_str()); + Serial.printf("EddystoneURL.getDecodedURL(): %s\n", EddystoneURL.getDecodedURL().c_str()); + Serial.printf("TX power %d (Raw 0x%02X)\n", EddystoneURL.getPower(), EddystoneURL.getPower()); + Serial.println("\n"); + } + + if (advertisedDevice.getFrameType() == BLE_EDDYSTONE_TLM_FRAME) { + Serial.println("Found an EddystoneTLM beacon!"); + BLEEddystoneTLM EddystoneTLM(&advertisedDevice); + Serial.printf("Reported battery voltage: %dmV\n", EddystoneTLM.getVolt()); + Serial.printf("Reported temperature: %.2f°C (raw data=0x%04X)\n", EddystoneTLM.getTemp(), EddystoneTLM.getRawTemp()); + Serial.printf("Reported advertise count: %lu\n", EddystoneTLM.getCount()); + Serial.printf("Reported time since last reboot: %lus\n", EddystoneTLM.getTime()); + Serial.println("\n"); + Serial.print(EddystoneTLM.toString().c_str()); + Serial.println("\n"); + } + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Scanning..."); + + BLEDevice::init(""); + pBLEScan = BLEDevice::getScan(); //create new scan + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setActiveScan(true); //active scan uses more power, but get results faster + pBLEScan->setInterval(100); + pBLEScan->setWindow(99); // less or equal setInterval value +} + +void loop() { + // put your main code here, to run repeatedly: + BLEScanResults *foundDevices = pBLEScan->start(scanTime, false); + Serial.print("Devices found: "); + Serial.println(foundDevices->getCount()); + Serial.println("Scan done!"); + pBLEScan->clearResults(); // delete results fromBLEScan buffer to release memory + delay(2000); +} diff --git a/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md new file mode 100644 index 0000000..34101fe --- /dev/null +++ b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md @@ -0,0 +1,9 @@ +## BLE Beacon Scanner + +Initiates a BLE device scan. +Checks if the discovered devices are +- an iBeacon +- an Eddystone TLM beacon +- an Eddystone URL beacon + +and sends the decoded beacon information over Serial log diff --git a/libraries/BLE/examples/Beacon_Scanner/ci.yml b/libraries/BLE/examples/Beacon_Scanner/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Beacon_Scanner/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Client/Client.ino b/libraries/BLE/examples/Client/Client.ino new file mode 100644 index 0000000..713bfda --- /dev/null +++ b/libraries/BLE/examples/Client/Client.ino @@ -0,0 +1,158 @@ +/** + * A BLE client example that is rich in capabilities. + * There is a lot new capabilities implemented. + * author unknown + * updated by chegewara + */ + +#include "BLEDevice.h" +//#include "BLEScan.h" + +// The remote service we wish to connect to. +static BLEUUID serviceUUID("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); +// The characteristic of the remote service we are interested in. +static BLEUUID charUUID("beb5483e-36e1-4688-b7f5-ea07361b26a8"); + +static boolean doConnect = false; +static boolean connected = false; +static boolean doScan = false; +static BLERemoteCharacteristic *pRemoteCharacteristic; +static BLEAdvertisedDevice *myDevice; + +// Callback function to handle notifications +static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) { + Serial.print("Notify callback for characteristic "); + Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str()); + Serial.print(" of data length "); + Serial.println(length); + Serial.print("data: "); + Serial.write(pData, length); + Serial.println(); +} + +class MyClientCallback : public BLEClientCallbacks { + void onConnect(BLEClient *pclient) {} + + void onDisconnect(BLEClient *pclient) { + connected = false; + Serial.println("onDisconnect"); + } +}; + +bool connectToServer() { + Serial.print("Forming a connection to "); + Serial.println(myDevice->getAddress().toString().c_str()); + + BLEClient *pClient = BLEDevice::createClient(); + Serial.println(" - Created client"); + + pClient->setClientCallbacks(new MyClientCallback()); + + // Connect to the remove BLE Server. + pClient->connect(myDevice); // if you pass BLEAdvertisedDevice instead of address, it will be recognized type of peer device address (public or private) + Serial.println(" - Connected to server"); + pClient->setMTU(517); //set client to request maximum MTU from server (default is 23 otherwise) + + // Obtain a reference to the service we are after in the remote BLE server. + BLERemoteService *pRemoteService = pClient->getService(serviceUUID); + if (pRemoteService == nullptr) { + Serial.print("Failed to find our service UUID: "); + Serial.println(serviceUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println(" - Found our service"); + + // Obtain a reference to the characteristic in the service of the remote BLE server. + pRemoteCharacteristic = pRemoteService->getCharacteristic(charUUID); + if (pRemoteCharacteristic == nullptr) { + Serial.print("Failed to find our characteristic UUID: "); + Serial.println(charUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println(" - Found our characteristic"); + + // Read the value of the characteristic. + if (pRemoteCharacteristic->canRead()) { + String value = pRemoteCharacteristic->readValue(); + Serial.print("The characteristic value was: "); + Serial.println(value.c_str()); + } + + if (pRemoteCharacteristic->canNotify()) { + // Register/Subscribe for notifications + pRemoteCharacteristic->registerForNotify(notifyCallback); + } + + connected = true; + return true; +} +/** + * Scan for BLE servers and find the first one that advertises the service we are looking for. + */ +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + /** + * Called for each advertising BLE server. + */ + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.print("BLE Advertised Device found: "); + Serial.println(advertisedDevice.toString().c_str()); + + // We have found a device, let us now see if it contains the service we are looking for. + if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(serviceUUID)) { + + BLEDevice::getScan()->stop(); + myDevice = new BLEAdvertisedDevice(advertisedDevice); + doConnect = true; + doScan = true; + + } // Found our server + } // onResult +}; // MyAdvertisedDeviceCallbacks + +void setup() { + Serial.begin(115200); + Serial.println("Starting Arduino BLE Client application..."); + BLEDevice::init(""); + + // Retrieve a Scanner and set the callback we want to use to be informed when we + // have detected a new device. Specify that we want active scanning and start the + // scan to run for 5 seconds. + BLEScan *pBLEScan = BLEDevice::getScan(); + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setInterval(1349); + pBLEScan->setWindow(449); + pBLEScan->setActiveScan(true); + pBLEScan->start(5, false); +} // End of setup. + +// This is the Arduino main loop function. +void loop() { + + // If the flag "doConnect" is true then we have scanned for and found the desired + // BLE Server with which we wish to connect. Now we connect to it. Once we are + // connected we set the connected flag to be true. + if (doConnect == true) { + if (connectToServer()) { + Serial.println("We are now connected to the BLE Server."); + } else { + Serial.println("We have failed to connect to the server; there is nothing more we will do."); + } + doConnect = false; + } + + // If we are connected to a peer BLE Server, update the characteristic each time we are reached + // with the current time since boot. + if (connected) { + String newValue = "Time since boot: " + String(millis() / 1000); + Serial.println("Setting new characteristic value to \"" + newValue + "\""); + + // Set the characteristic's value to be the array of bytes that is actually a string. + pRemoteCharacteristic->writeValue(newValue.c_str(), newValue.length()); + } else if (doScan) { + BLEDevice::getScan()->start(0); // this is just example to start scan after disconnect, most likely there is better way to do it in arduino + } + + delay(1000); // Delay a second between loops. +} // End of loop diff --git a/libraries/BLE/examples/Client/ci.yml b/libraries/BLE/examples/Client/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Client/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Client_Gamepad/Client_Gamepad.ino b/libraries/BLE/examples/Client_Gamepad/Client_Gamepad.ino new file mode 100644 index 0000000..e2ace41 --- /dev/null +++ b/libraries/BLE/examples/Client_Gamepad/Client_Gamepad.ino @@ -0,0 +1,253 @@ +/* + * BLE HID Gamepad Client Example + * + * This example demonstrates how to connect to a BLE HID Gamepad and read its input. + * The ESP32 acts as a BLE Central (client) that connects to a BLE gamepad peripheral. + * + * Features: + * - Scans for BLE HID gamepad devices + * - Connects to the first gamepad found + * - Secure pairing with bonding + * - Subscribes to input report notifications + * - Parses and displays gamepad input (buttons and axes) + * - Automatic reconnection on disconnect + * + * Usage: + * 1. Upload this sketch to your ESP32 + * 2. Turn on your BLE gamepad (or run the Server_Gamepad example on another ESP32) + * 3. The ESP32 will scan, connect, and display gamepad input in the serial monitor + * + * Note: This example uses "Just Works" pairing for automatic connection without + * PIN entry or confirmation. The bond is saved for future connections. + * + * Compatible with gamepads using the standard HID Report Descriptor format + * + * Created by lucasssvaz + */ + +#include +#include + +// HID Service UUID (standard UUID for HID over GATT) +static BLEUUID hidServiceUUID((uint16_t)0x1812); +// HID Report characteristic UUID (used for input/output reports) +static BLEUUID reportCharUUID((uint16_t)0x2A4D); +// HID Report Map characteristic UUID +static BLEUUID reportMapUUID((uint16_t)0x2A4B); + +static boolean doConnect = false; +static boolean connected = false; +static boolean doScan = false; +static BLERemoteCharacteristic *pInputReportCharacteristic = nullptr; +static BLEAdvertisedDevice *myDevice = nullptr; +static BLEClient *pClient = nullptr; + +// Gamepad report structure (adjust based on your gamepad's report descriptor) +// This matches the Server_Gamepad example format +struct GamepadReport { + uint8_t reportId; // Report ID + int8_t x; // X axis (-127 to 127) + int8_t y; // Y axis (-127 to 127) + uint8_t buttons; // 8 buttons (bit 0-7) +} __attribute__((packed)); + +// Callback function to handle gamepad input notifications +static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) { + Serial.printf("Received %d bytes: ", length); + + // Check if data length matches our expected gamepad report + if (length == sizeof(GamepadReport)) { + GamepadReport *report = (GamepadReport *)pData; + + Serial.printf("ID=%d, X=%4d, Y=%4d, Buttons=0x%02X [", report->reportId, report->x, report->y, report->buttons); + + // Display which buttons are pressed + for (int i = 0; i < 8; i++) { + if (report->buttons & (1 << i)) { + Serial.printf("%d ", i + 1); + } + } + Serial.println("]"); + } else { + // Unknown format, just display hex dump + Serial.print("Raw data: "); + for (size_t i = 0; i < length; i++) { + Serial.printf("%02X ", pData[i]); + } + Serial.println(); + } +} + +// Client callbacks to handle connection events +class MyClientCallback : public BLEClientCallbacks { + void onConnect(BLEClient *pclient) { + Serial.println("Connected to gamepad"); + } + + void onDisconnect(BLEClient *pclient) { + connected = false; + Serial.println("Disconnected from gamepad"); + } +}; + +// Function to connect to the gamepad +bool connectToServer() { + Serial.print("Connecting to gamepad at "); + Serial.println(myDevice->getAddress().toString().c_str()); + + pClient = BLEDevice::createClient(); + Serial.println(" - Created client"); + + pClient->setClientCallbacks(new MyClientCallback()); + + // Connect to the gamepad + pClient->connect(myDevice); + Serial.println(" - Connected to server"); + pClient->setMTU(185); // Set MTU for larger data transfers + + // Obtain a reference to the HID service + BLERemoteService *pRemoteService = pClient->getService(hidServiceUUID); + if (pRemoteService == nullptr) { + Serial.println("Failed to find HID service"); + pClient->disconnect(); + return false; + } + Serial.println(" - Found HID service"); + + // Get all characteristics to find input reports + std::map *pCharMap = pRemoteService->getCharacteristics(); + + // Look for input report characteristics (UUID 0x2A4D) + for (auto const &entry : *pCharMap) { + BLERemoteCharacteristic *pChar = entry.second; + + if (pChar->getUUID().equals(reportCharUUID)) { + // Check if this characteristic has notify property (input report) + if (pChar->canNotify()) { + Serial.printf(" - Found input report characteristic (handle: 0x%04X)\n", pChar->getHandle()); + + // Try to read Report Reference Descriptor to identify report type and ID + BLERemoteDescriptor *pReportRefDesc = pChar->getDescriptor(BLEUUID((uint16_t)0x2908)); + if (pReportRefDesc != nullptr) { + String refValue = pReportRefDesc->readValue(); + if (refValue.length() >= 2) { + uint8_t reportId = refValue[0]; + uint8_t reportType = refValue[1]; + Serial.printf(" Report ID: %d, Type: %d (1=Input, 2=Output, 3=Feature)\n", reportId, reportType); + + // We want input reports (type = 1) + if (reportType == 1) { + pInputReportCharacteristic = pChar; + } + } + } else { + // No report reference descriptor, assume it's an input report + pInputReportCharacteristic = pChar; + } + } + } + } + + if (pInputReportCharacteristic == nullptr) { + Serial.println("Failed to find input report characteristic"); + pClient->disconnect(); + return false; + } + + // Subscribe to input report notifications + Serial.println(" - Subscribing to input report notifications"); + pInputReportCharacteristic->registerForNotify(notifyCallback); + + connected = true; + Serial.println("Successfully connected and subscribed to gamepad!"); + + // Note: Security/encryption will be automatically handled by the BLE stack + // when the HID device requires it (using "Just Works" pairing). + + return true; +} + +// Scan callback to detect gamepad devices +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.print("BLE Device found: "); + Serial.print(advertisedDevice.toString().c_str()); + + // Check if device advertises HID service + if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(hidServiceUUID)) { + Serial.print(" - HID Device!"); + + // Check if it's a gamepad by appearance (0x03C4 = HID Gamepad) + if (advertisedDevice.haveAppearance()) { + uint16_t appearance = advertisedDevice.getAppearance(); + Serial.printf(" (Appearance: 0x%04X)", appearance); + if (appearance == 0x03C4) { + Serial.print(" - GAMEPAD!"); + } + } + Serial.println(); + + // Stop scanning and connect + BLEDevice::getScan()->stop(); + myDevice = new BLEAdvertisedDevice(advertisedDevice); + doConnect = true; + doScan = true; + } else { + Serial.println(); + } + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("\n=== BLE HID Gamepad Client ==="); + Serial.println("Scanning for BLE HID gamepads...\n"); + + BLEDevice::init("ESP32-Gamepad-Client"); + + // Configure BLE Security for pairing with HID devices + BLESecurity *pSecurity = new BLESecurity(); + + // Set security capabilities and authentication mode + // HID devices typically use "Just Works" pairing (no MITM) with bonding + + // Set IO capability to NONE for "Just Works" pairing + pSecurity->setCapability(ESP_IO_CAP_NONE); + + // Bonding, no MITM, secure connections (for "Just Works" pairing) + pSecurity->setAuthenticationMode(true, false, true); + + // Set security callbacks (using default implementation) + BLEDevice::setSecurityCallbacks(new BLESecurityCallbacks()); + + Serial.println("Security configured: Bonding + Secure Connections\n"); + + // Create scanner and set callbacks + BLEScan *pBLEScan = BLEDevice::getScan(); + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setInterval(1349); + pBLEScan->setWindow(449); + pBLEScan->setActiveScan(true); + pBLEScan->start(5, false); +} + +void loop() { + // Connect to gamepad if found + if (doConnect == true) { + if (connectToServer()) { + Serial.println("\n*** Ready to receive gamepad input ***\n"); + } else { + Serial.println("Failed to connect to gamepad"); + } + doConnect = false; + } + + // Restart scanning if disconnected + if (!connected && doScan) { + Serial.println("\nScanning for gamepads..."); + BLEDevice::getScan()->start(5, false); + delay(1000); + } + + delay(100); +} diff --git a/libraries/BLE/examples/Client_Gamepad/ci.yml b/libraries/BLE/examples/Client_Gamepad/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Client_Gamepad/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Client_Server/Client_Server.ino b/libraries/BLE/examples/Client_Server/Client_Server.ino new file mode 100644 index 0000000..af8db87 --- /dev/null +++ b/libraries/BLE/examples/Client_Server/Client_Server.ino @@ -0,0 +1,280 @@ +/* + * BLE Client and Server Coexistence Example + * + * This example demonstrates how to run both BLE client and server + * functionality on the same ESP32 device simultaneously. + * + * The device will: + * - Act as a BLE server, advertising a service with a characteristic + * - Act as a BLE client, scanning for other BLE servers + * - Connect to found servers and interact with their services + * - Handle both incoming and outgoing connections + * + * You can test this example by uploading it to two ESP32 boards. + * + * Author: lucasssvaz + * Based on Arduino BLE examples + */ + +#include +#include +#include +#include +#include + +// Server-side definitions +#define SERVER_SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define SERVER_CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +// Client-side definitions (looking for the same service) +static BLEUUID clientServiceUUID(SERVER_SERVICE_UUID); +static BLEUUID clientCharUUID(SERVER_CHARACTERISTIC_UUID); + +// Server objects +BLEServer *pServer = nullptr; +BLECharacteristic *pServerCharacteristic = nullptr; + +// Client objects +static boolean doConnect = false; +static boolean clientConnected = false; +static BLERemoteCharacteristic *pRemoteCharacteristic; +static BLEAdvertisedDevice *targetDevice; +static BLEClient *pClient = nullptr; +BLEScan *pBLEScan = nullptr; + +// Server callbacks +class ServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + Serial.println("Server: Client connected"); + } + + void onDisconnect(BLEServer *pServer) { + Serial.println("Server: Client disconnected"); + // Restart advertising + BLEDevice::startAdvertising(); + } +}; + +// Characteristic callbacks for server +class CharacteristicCallbacks : public BLECharacteristicCallbacks { + void onWrite(BLECharacteristic *pCharacteristic) { + String value = pCharacteristic->getValue(); + Serial.print("Server: Characteristic written, value: "); + Serial.println(value.c_str()); + } + + void onRead(BLECharacteristic *pCharacteristic) { + Serial.println("Server: Characteristic read"); + } +}; + +// Client callbacks +class ClientCallbacks : public BLEClientCallbacks { + void onConnect(BLEClient *pClient) { + Serial.println("Client: Connected to server"); + clientConnected = true; + } + + void onDisconnect(BLEClient *pClient) { + Serial.println("Client: Disconnected from server"); + clientConnected = false; + } +}; + +// Client notification callback +static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) { + Serial.print("Client: Notify callback for characteristic "); + Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str()); + Serial.print(" of data length "); + Serial.println(length); + Serial.print("Client: Data: "); + Serial.write(pData, length); + Serial.println(); +} + +// Scan callbacks +class AdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.print("Client: Found device: "); + Serial.println(advertisedDevice.toString().c_str()); + + // Check if this device has our target service + if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(clientServiceUUID) && !clientConnected) { + + Serial.println("Client: Found target service, attempting connection..."); + BLEDevice::getScan()->stop(); + targetDevice = new BLEAdvertisedDevice(advertisedDevice); + doConnect = true; + } + } +}; + +bool connectToServer() { + Serial.print("Client: Forming connection to "); + Serial.println(targetDevice->getAddress().toString().c_str()); + + // Create client if it doesn't exist, otherwise reuse existing one + if (pClient == nullptr) { + pClient = BLEDevice::createClient(); + pClient->setClientCallbacks(new ClientCallbacks()); + Serial.println("Client: Created new client"); + } else { + Serial.println("Client: Reusing existing client"); + } + + if (!pClient->connect(targetDevice)) { + Serial.println("Client: Failed to connect"); + return false; + } + + Serial.println("Client: Connected to server"); + pClient->setMTU(517); // Request maximum MTU + + // Get the service + BLERemoteService *pRemoteService = pClient->getService(clientServiceUUID); + if (pRemoteService == nullptr) { + Serial.print("Client: Failed to find service UUID: "); + Serial.println(clientServiceUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println("Client: Found service"); + + // Get the characteristic + pRemoteCharacteristic = pRemoteService->getCharacteristic(clientCharUUID); + if (pRemoteCharacteristic == nullptr) { + Serial.print("Client: Failed to find characteristic UUID: "); + Serial.println(clientCharUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println("Client: Found characteristic"); + + // Read the initial value + if (pRemoteCharacteristic->canRead()) { + String value = pRemoteCharacteristic->readValue(); + Serial.print("Client: Initial characteristic value: "); + Serial.println(value.c_str()); + } + + // Register for notifications if available + if (pRemoteCharacteristic->canNotify()) { + pRemoteCharacteristic->registerForNotify(notifyCallback); + Serial.println("Client: Registered for notifications"); + } + + return true; +} + +void setupServer() { + Serial.println("Setting up BLE Server..."); + + // Create server + pServer = BLEDevice::createServer(); + pServer->setCallbacks(new ServerCallbacks()); + + // Create service + BLEService *pService = pServer->createService(SERVER_SERVICE_UUID); + + // Create characteristic + pServerCharacteristic = pService->createCharacteristic( + SERVER_CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY + ); + + pServerCharacteristic->setCallbacks(new CharacteristicCallbacks()); + pServerCharacteristic->setValue("Hello from Coexistence Server"); + + // Start service + pService->start(); + + // Start advertising + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVER_SERVICE_UUID); + pAdvertising->setScanResponse(true); + pAdvertising->setMinPreferred(0x06); + pAdvertising->setMinPreferred(0x12); + + BLEDevice::startAdvertising(); + + Serial.println("Server: Advertising started"); +} + +void setupClient() { + Serial.println("Setting up BLE Client..."); + + // Create scanner + pBLEScan = BLEDevice::getScan(); + pBLEScan->setAdvertisedDeviceCallbacks(new AdvertisedDeviceCallbacks()); + pBLEScan->setActiveScan(true); + pBLEScan->setInterval(100); + pBLEScan->setWindow(99); + + Serial.println("Client: Scanner configured"); +} + +void setup() { + Serial.begin(115200); + Serial.println("Starting BLE Client-Server Coexistence Example..."); + + // Initialize BLE device with a name + BLEDevice::init("ESP32-Coexistence"); + + // Setup both server and client + setupServer(); + setupClient(); + + // Start initial scan + pBLEScan->start(10, false); // Scan for 10 seconds, don't repeat + + Serial.println("Setup complete. Device is advertising as server and scanning as client."); +} + +void loop() { + static unsigned long lastServerUpdate = 0; + static unsigned long lastClientWrite = 0; + static unsigned long lastScanStart = 0; + unsigned long currentTime = millis(); + + // Handle client connection attempts + if (doConnect && !clientConnected) { + if (connectToServer()) { + Serial.println("Client: Successfully connected to remote server"); + } else { + Serial.println("Client: Failed to connect, will retry scanning"); + // Restart scanning after failed connection + pBLEScan->start(10, false); + } + doConnect = false; + } + + // Update server characteristic periodically + if (currentTime - lastServerUpdate > 5000) { // Every 5 seconds + String value = "Server time: " + String(millis() / 1000); + pServerCharacteristic->setValue(value.c_str()); + pServerCharacteristic->notify(); // Notify connected clients + Serial.print("Server: Updated characteristic to: "); + Serial.println(value); + + lastServerUpdate = currentTime; + } + + // Write to remote characteristic if connected as client + if (clientConnected && pRemoteCharacteristic && currentTime - lastClientWrite > 3000) { + if (pRemoteCharacteristic->canWrite()) { + String clientValue = "Client msg: " + String(millis() / 1000); + pRemoteCharacteristic->writeValue(clientValue.c_str(), clientValue.length()); + Serial.print("Client: Wrote to remote characteristic: "); + Serial.println(clientValue); + lastClientWrite = currentTime; + } + } + + // Restart scanning periodically if not connected + if (!clientConnected && currentTime - lastScanStart > 15000) { // Every 15 seconds + Serial.println("Client: Restarting scan..."); + pBLEScan->start(10, false); + lastScanStart = currentTime; + } + + delay(100); +} diff --git a/libraries/BLE/examples/Client_Server/ci.yml b/libraries/BLE/examples/Client_Server/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Client_Server/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Client_multiconnect/Client_multiconnect.ino b/libraries/BLE/examples/Client_multiconnect/Client_multiconnect.ino new file mode 100644 index 0000000..712e5bb --- /dev/null +++ b/libraries/BLE/examples/Client_multiconnect/Client_multiconnect.ino @@ -0,0 +1,276 @@ +/** + * A BLE client example that connects to multiple BLE servers simultaneously. + * + * This example demonstrates how to: + * - Scan for multiple BLE servers + * - Connect to multiple servers at the same time + * - Interact with characteristics on different servers + * - Handle disconnections and reconnections + * + * The example looks for servers advertising the service UUID: 4fafc201-1fb5-459e-8fcc-c5c9c331914b + * and connects to up to MAX_SERVERS servers. + * + * Created by lucasssvaz + * Based on the original Client example by Neil Kolban and chegewara + */ + +#include "BLEDevice.h" + +// The remote service we wish to connect to. +static BLEUUID serviceUUID("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); +// The characteristic of the remote service we are interested in. +static BLEUUID charUUID("beb5483e-36e1-4688-b7f5-ea07361b26a8"); + +// Maximum number of servers to connect to +#define MAX_SERVERS 3 + +// Structure to hold information about each connected server +struct ServerConnection { + BLEClient *pClient; + BLEAdvertisedDevice *pDevice; + BLERemoteCharacteristic *pRemoteCharacteristic; + bool connected; + bool doConnect; + String name; +}; + +// Array to manage multiple server connections +ServerConnection servers[MAX_SERVERS]; +int connectedServers = 0; +static bool doScan = true; + +// Callback function to handle notifications from any server +static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) { + // Find which server this notification came from + for (int i = 0; i < MAX_SERVERS; i++) { + if (servers[i].connected && servers[i].pRemoteCharacteristic == pBLERemoteCharacteristic) { + Serial.print("Notify from server "); + Serial.print(servers[i].name); + Serial.print(" - Characteristic: "); + Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str()); + Serial.print(" | Length: "); + Serial.print(length); + Serial.print(" | Data: "); + Serial.write(pData, length); + Serial.println(); + break; + } + } +} + +// Client callback class to handle connect/disconnect events +class MyClientCallback : public BLEClientCallbacks { + int serverIndex; + +public: + MyClientCallback(int index) : serverIndex(index) {} + + void onConnect(BLEClient *pclient) { + Serial.print("Connected to server "); + Serial.println(servers[serverIndex].name); + } + + void onDisconnect(BLEClient *pclient) { + servers[serverIndex].connected = false; + connectedServers--; + Serial.print("Disconnected from server "); + Serial.print(servers[serverIndex].name); + Serial.print(" | Total connected: "); + Serial.println(connectedServers); + doScan = true; // Resume scanning to find replacement servers + } +}; + +// Function to connect to a specific server +bool connectToServer(int serverIndex) { + Serial.print("Connecting to server "); + Serial.print(serverIndex); + Serial.print(" at address: "); + Serial.println(servers[serverIndex].pDevice->getAddress().toString().c_str()); + + servers[serverIndex].pClient = BLEDevice::createClient(); + Serial.println(" - Created client"); + + // Set the callback for this specific server connection + servers[serverIndex].pClient->setClientCallbacks(new MyClientCallback(serverIndex)); + + // Connect to the remote BLE Server + servers[serverIndex].pClient->connect(servers[serverIndex].pDevice); + Serial.println(" - Connected to server"); + servers[serverIndex].pClient->setMTU(517); // Request maximum MTU from server + + // Obtain a reference to the service we are after in the remote BLE server + BLERemoteService *pRemoteService = servers[serverIndex].pClient->getService(serviceUUID); + if (pRemoteService == nullptr) { + Serial.print("Failed to find service UUID: "); + Serial.println(serviceUUID.toString().c_str()); + servers[serverIndex].pClient->disconnect(); + return false; + } + Serial.println(" - Found service"); + + // Obtain a reference to the characteristic in the service + servers[serverIndex].pRemoteCharacteristic = pRemoteService->getCharacteristic(charUUID); + if (servers[serverIndex].pRemoteCharacteristic == nullptr) { + Serial.print("Failed to find characteristic UUID: "); + Serial.println(charUUID.toString().c_str()); + servers[serverIndex].pClient->disconnect(); + return false; + } + Serial.println(" - Found characteristic"); + + // Read the value of the characteristic + if (servers[serverIndex].pRemoteCharacteristic->canRead()) { + String value = servers[serverIndex].pRemoteCharacteristic->readValue(); + Serial.print("Initial characteristic value: "); + Serial.println(value.c_str()); + } + + // Register for notifications if available + if (servers[serverIndex].pRemoteCharacteristic->canNotify()) { + servers[serverIndex].pRemoteCharacteristic->registerForNotify(notifyCallback); + Serial.println(" - Registered for notifications"); + } + + servers[serverIndex].connected = true; + connectedServers++; + Serial.print("Successfully connected! Total servers connected: "); + Serial.println(connectedServers); + return true; +} + +// Scan callback class to find BLE servers +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.print("BLE Device found: "); + Serial.println(advertisedDevice.toString().c_str()); + + // Check if this device has the service we're looking for + if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(serviceUUID)) { + Serial.println(" -> This device has our service!"); + + // Check if we already know about this device + String deviceAddress = advertisedDevice.getAddress().toString().c_str(); + bool alreadyKnown = false; + + for (int i = 0; i < MAX_SERVERS; i++) { + if (servers[i].pDevice != nullptr) { + if (servers[i].pDevice->getAddress().toString() == deviceAddress) { + alreadyKnown = true; + break; + } + } + } + + if (alreadyKnown) { + Serial.println(" -> Already connected or connecting to this device"); + return; + } + + // Find an empty slot for this server + for (int i = 0; i < MAX_SERVERS; i++) { + if (servers[i].pDevice == nullptr || (!servers[i].connected && !servers[i].doConnect)) { + servers[i].pDevice = new BLEAdvertisedDevice(advertisedDevice); + servers[i].doConnect = true; + servers[i].name = "Server_" + String(i); + Serial.print(" -> Assigned to slot "); + Serial.println(i); + + // If we've found enough servers, stop scanning + int pendingConnections = 0; + for (int j = 0; j < MAX_SERVERS; j++) { + if (servers[j].connected || servers[j].doConnect) { + pendingConnections++; + } + } + if (pendingConnections >= MAX_SERVERS) { + Serial.println("Found enough servers, stopping scan"); + BLEDevice::getScan()->stop(); + doScan = false; + } + break; + } + } + } + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("================================="); + Serial.println("BLE Multi-Client Example"); + Serial.println("================================="); + Serial.print("Max servers to connect: "); + Serial.println(MAX_SERVERS); + Serial.println(); + + // Initialize all server connections + for (int i = 0; i < MAX_SERVERS; i++) { + servers[i].pClient = nullptr; + servers[i].pDevice = nullptr; + servers[i].pRemoteCharacteristic = nullptr; + servers[i].connected = false; + servers[i].doConnect = false; + servers[i].name = ""; + } + + // Initialize BLE + BLEDevice::init("ESP32_MultiClient"); + + // Set up BLE scanner + BLEScan *pBLEScan = BLEDevice::getScan(); + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setInterval(1349); + pBLEScan->setWindow(449); + pBLEScan->setActiveScan(true); + pBLEScan->start(5, false); + + Serial.println("Scanning for BLE servers..."); +} + +void loop() { + // Process any pending connections + for (int i = 0; i < MAX_SERVERS; i++) { + if (servers[i].doConnect) { + if (connectToServer(i)) { + Serial.println("Connection successful"); + } else { + Serial.println("Connection failed"); + // Clear this slot so we can try another server + delete servers[i].pDevice; + servers[i].pDevice = nullptr; + } + servers[i].doConnect = false; + } + } + + // If we're connected to servers, send data to each one + if (connectedServers > 0) { + for (int i = 0; i < MAX_SERVERS; i++) { + if (servers[i].connected && servers[i].pRemoteCharacteristic != nullptr) { + // Create a unique message for each server + String newValue = servers[i].name + " | Time: " + String(millis() / 1000); + + Serial.print("Sending to "); + Serial.print(servers[i].name); + Serial.print(": "); + Serial.println(newValue); + + // Write the value to the characteristic + servers[i].pRemoteCharacteristic->writeValue(newValue.c_str(), newValue.length()); + } + } + } else { + Serial.println("No servers connected"); + } + + // Resume scanning if we have room for more connections + if (doScan && connectedServers < MAX_SERVERS) { + Serial.println("Resuming scan for more servers..."); + BLEDevice::getScan()->start(5, false); + doScan = false; + delay(5000); // Wait for scan to complete + } + + delay(2000); // Delay between loop iterations +} diff --git a/libraries/BLE/examples/Client_multiconnect/ci.yml b/libraries/BLE/examples/Client_multiconnect/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Client_multiconnect/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Client_secure_static_passkey/Client_secure_static_passkey.ino b/libraries/BLE/examples/Client_secure_static_passkey/Client_secure_static_passkey.ino new file mode 100644 index 0000000..a3204fc --- /dev/null +++ b/libraries/BLE/examples/Client_secure_static_passkey/Client_secure_static_passkey.ino @@ -0,0 +1,327 @@ +/* + Secure client with static passkey and IRK retrieval + + This example demonstrates how to create a secure BLE client that connects to + a secure BLE server using a static passkey without prompting the user. + The client will automatically use the same passkey (123456) as the server. + + After successful bonding, the example demonstrates how to retrieve the + server's Identity Resolving Key (IRK) in multiple formats: + - Comma-separated hex format: 0x1A,0x1B,0x1C,... + - Base64 encoded (for Home Assistant Private BLE Device service) + - Reverse hex order (for Home Assistant ESPresense) + + This client is designed to work with the Server_secure_static_passkey example. + + Note that ESP32 uses Bluedroid by default and the other SoCs use NimBLE. + Bluedroid initiates security on-connect, while NimBLE initiates security on-demand. + This means that in NimBLE you can read the insecure characteristic without entering + the passkey. This is not possible in Bluedroid. + + IMPORTANT: + - MITM (Man-In-The-Middle protection) must be enabled for password prompts to work. + - Bonding must be enabled to store and retrieve the IRK. + - The server must distribute its Identity Key during pairing. + + Based on examples from Neil Kolban and h2zero. + Created by lucasssvaz. +*/ + +#include "BLEDevice.h" +#include "BLESecurity.h" +#include "nvs_flash.h" + +// The remote service we wish to connect to. +static BLEUUID serviceUUID("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); +// The characteristics of the remote service we are interested in. +static BLEUUID insecureCharUUID("beb5483e-36e1-4688-b7f5-ea07361b26a8"); +static BLEUUID secureCharUUID("ff1d2614-e2d6-4c87-9154-6625d39ca7f8"); + +// This must match the server's passkey +#define CLIENT_PIN 123456 + +static boolean doConnect = false; +static boolean connected = false; +static boolean doScan = false; +static BLEClient *pClient = nullptr; +static BLERemoteCharacteristic *pRemoteInsecureCharacteristic; +static BLERemoteCharacteristic *pRemoteSecureCharacteristic; +static BLEAdvertisedDevice *myDevice; + +// Print an IRK buffer as hex with leading zeros and ':' separator +static void printIrkBinary(uint8_t *irk) { + for (int i = 0; i < 16; i++) { + if (irk[i] < 0x10) { + Serial.print("0"); + } + Serial.print(irk[i], HEX); + if (i < 15) { + Serial.print(":"); + } + } +} + +static void get_peer_irk(BLEAddress peerAddr) { + Serial.println("\n=== Retrieving peer IRK (Server) ===\n"); + + uint8_t irk[16]; + + // Get IRK in binary format + if (BLEDevice::getPeerIRK(peerAddr, irk)) { + Serial.println("Successfully retrieved peer IRK in binary format:"); + printIrkBinary(irk); + Serial.println("\n"); + } + + // Get IRK in different string formats + String irkString = BLEDevice::getPeerIRKString(peerAddr); + String irkBase64 = BLEDevice::getPeerIRKBase64(peerAddr); + String irkReverse = BLEDevice::getPeerIRKReverse(peerAddr); + + if (irkString.length() > 0) { + Serial.println("Successfully retrieved peer IRK in multiple formats:\n"); + Serial.print("IRK (comma-separated hex): "); + Serial.println(irkString); + Serial.print("IRK (Base64 for Home Assistant Private BLE Device): "); + Serial.println(irkBase64); + Serial.print("IRK (reverse hex for Home Assistant ESPresense): "); + Serial.println(irkReverse); + Serial.println(); + } else { + Serial.println("!!! Failed to retrieve peer IRK !!!"); + Serial.println("This is expected if bonding is disabled or the peer doesn't distribute its Identity Key."); + Serial.println("To enable bonding, change setAuthenticationMode to: pSecurity->setAuthenticationMode(true, true, true);\n"); + } + + Serial.println("=======================================\n"); +} + +// Callback function to handle notifications +static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) { + Serial.print("Notify callback for characteristic "); + Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str()); + Serial.print(" of data length "); + Serial.println(length); + Serial.print("data: "); + Serial.write(pData, length); + Serial.println(); +} + +class MyClientCallback : public BLEClientCallbacks { + void onConnect(BLEClient *pclient) { + Serial.println("Connected to secure server"); + } + + void onDisconnect(BLEClient *pclient) { + connected = false; + Serial.println("Disconnected from server"); + } +}; + +// Security callbacks to print IRKs once authentication completes +class MySecurityCallbacks : public BLESecurityCallbacks { +#if defined(CONFIG_BLUEDROID_ENABLED) + void onAuthenticationComplete(esp_ble_auth_cmpl_t desc) override { + // Print the IRK received by the peer + BLEAddress peerAddr(desc.bd_addr); + get_peer_irk(peerAddr); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + void onAuthenticationComplete(ble_gap_conn_desc *desc) override { + // Print the IRK received by the peer + BLEAddress peerAddr(desc->peer_id_addr.val, desc->peer_id_addr.type); + get_peer_irk(peerAddr); + } +#endif +}; + +bool connectToServer() { + Serial.print("Forming a secure connection to "); + Serial.println(myDevice->getAddress().toString().c_str()); + + pClient = BLEDevice::createClient(); + Serial.println(" - Created client"); + + pClient->setClientCallbacks(new MyClientCallback()); + + // Connect to the remote BLE Server. + pClient->connect(myDevice); + Serial.println(" - Connected to server"); + + // Set MTU to maximum for better performance + pClient->setMTU(517); + + // Obtain a reference to the service we are after in the remote BLE server. + BLERemoteService *pRemoteService = pClient->getService(serviceUUID); + if (pRemoteService == nullptr) { + Serial.print("Failed to find our service UUID: "); + Serial.println(serviceUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println(" - Found our service"); + + // Obtain a reference to the insecure characteristic + pRemoteInsecureCharacteristic = pRemoteService->getCharacteristic(insecureCharUUID); + if (pRemoteInsecureCharacteristic == nullptr) { + Serial.print("Failed to find insecure characteristic UUID: "); + Serial.println(insecureCharUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println(" - Found insecure characteristic"); + + // Obtain a reference to the secure characteristic + pRemoteSecureCharacteristic = pRemoteService->getCharacteristic(secureCharUUID); + if (pRemoteSecureCharacteristic == nullptr) { + Serial.print("Failed to find secure characteristic UUID: "); + Serial.println(secureCharUUID.toString().c_str()); + pClient->disconnect(); + return false; + } + Serial.println(" - Found secure characteristic"); + + // Read the value of the insecure characteristic (should work without authentication) + if (pRemoteInsecureCharacteristic->canRead()) { + String value = pRemoteInsecureCharacteristic->readValue(); + Serial.print("Insecure characteristic value: "); + Serial.println(value.c_str()); + } + + // For Bluedroid, we need to set the authentication request type for the secure characteristic + // This is not needed for NimBLE and will be ignored. + pRemoteSecureCharacteristic->setAuth(ESP_GATT_AUTH_REQ_MITM); + + // Try to read the secure characteristic (this will trigger security negotiation in NimBLE) + if (pRemoteSecureCharacteristic->canRead()) { + Serial.println("Attempting to read secure characteristic..."); + String value = pRemoteSecureCharacteristic->readValue(); + Serial.print("Secure characteristic value: "); + Serial.println(value.c_str()); + } + + // Register for notifications on both characteristics if they support it + if (pRemoteInsecureCharacteristic->canNotify()) { + pRemoteInsecureCharacteristic->registerForNotify(notifyCallback); + Serial.println(" - Registered for insecure characteristic notifications"); + } + + if (pRemoteSecureCharacteristic->canNotify()) { + pRemoteSecureCharacteristic->registerForNotify(notifyCallback); + Serial.println(" - Registered for secure characteristic notifications"); + } + + connected = true; + return true; +} + +/** + * Scan for BLE servers and find the first one that advertises the service we are looking for. + */ +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + /** + * Called for each advertising BLE server. + */ + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.print("BLE Advertised Device found: "); + Serial.println(advertisedDevice.toString().c_str()); + + // We have found a device, let us now see if it contains the service we are looking for. + if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(serviceUUID)) { + Serial.println("Found our secure server!"); + BLEDevice::getScan()->stop(); + myDevice = new BLEAdvertisedDevice(advertisedDevice); + doConnect = true; + doScan = true; + } + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Starting Secure BLE Client application..."); + + // Clear NVS to remove any cached pairing information + // This ensures fresh authentication for testing + Serial.println("Clearing NVS pairing data..."); + nvs_flash_erase(); + nvs_flash_init(); + + BLEDevice::init("Secure BLE Client"); + + // Set up security with the same passkey as the server + BLESecurity *pSecurity = new BLESecurity(); + + // Set security parameters + // Default parameters: + // - IO capability is set to NONE + // - Initiator and responder key distribution flags are set to both encryption and identity keys. + // - Passkey is set to BLE_SM_DEFAULT_PASSKEY (123456). It will warn if you don't change it. + // - Key size is set to 16 bytes + + // Set the same static passkey as the server + // The first argument defines if the passkey is static or random. + // The second argument is the passkey (ignored when using a random passkey). + pSecurity->setPassKey(true, CLIENT_PIN); + + // Set authentication mode to match server requirements + // Enable bonding, MITM (for password prompts), and secure connection for this example + // Bonding is required to store and retrieve the IRK + pSecurity->setAuthenticationMode(true, true, true); + + // Set IO capability to KeyboardOnly + // We need the proper IO capability for MITM authentication even + // if the passkey is static and won't be entered by the user + // See https://www.bluetooth.com/blog/bluetooth-pairing-part-2-key-generation-methods/ + pSecurity->setCapability(ESP_IO_CAP_IN); + + // Set callbacks to handle authentication completion and print IRKs + BLEDevice::setSecurityCallbacks(new MySecurityCallbacks()); + + // Retrieve a Scanner and set the callback we want to use to be informed when we + // have detected a new device. Specify that we want active scanning and start the + // scan to run for 5 seconds. + BLEScan *pBLEScan = BLEDevice::getScan(); + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setInterval(1349); + pBLEScan->setWindow(449); + pBLEScan->setActiveScan(true); + pBLEScan->start(5, false); +} + +void loop() { + // If the flag "doConnect" is true then we have scanned for and found the desired + // BLE Server with which we wish to connect. Now we connect to it. + if (doConnect == true) { + if (connectToServer()) { + Serial.println("We are now connected to the secure BLE Server."); + } else { + Serial.println("We have failed to connect to the server; there is nothing more we will do."); + } + doConnect = false; + } + + // If we are connected to a peer BLE Server, demonstrate secure communication + if (connected) { + // Write to the insecure characteristic + String insecureValue = "Client time: " + String(millis() / 1000); + if (pRemoteInsecureCharacteristic->canWrite()) { + pRemoteInsecureCharacteristic->writeValue(insecureValue.c_str(), insecureValue.length()); + Serial.println("Wrote to insecure characteristic: " + insecureValue); + } + + // Write to the secure characteristic + String secureValue = "Secure client time: " + String(millis() / 1000); + if (pRemoteSecureCharacteristic->canWrite()) { + pRemoteSecureCharacteristic->writeValue(secureValue.c_str(), secureValue.length()); + Serial.println("Wrote to secure characteristic: " + secureValue); + } + } else if (doScan) { + // Restart scanning if we're disconnected + BLEDevice::getScan()->start(0); + } + + delay(2000); // Delay 2 seconds between loops +} diff --git a/libraries/BLE/examples/Client_secure_static_passkey/ci.yml b/libraries/BLE/examples/Client_secure_static_passkey/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Client_secure_static_passkey/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino new file mode 100644 index 0000000..d66ceb5 --- /dev/null +++ b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino @@ -0,0 +1,92 @@ +/* + EddystoneTLM beacon by BeeGee based on https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_Eddystone_TLM_deepsleep/ESP32_Eddystone_TLM_deepsleep.ino + EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md +*/ + +/* + Create a BLE server that will send periodic Eddystone URL frames. + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create advertising data + 3. Start advertising. + 4. wait + 5. Stop advertising. + 6. deep sleep + + To read data advertised by this beacon use second ESP with example sketch BLE_Beacon_Scanner +*/ +#include "sys/time.h" + +#include + +#include "BLEDevice.h" +#include "BLEUtils.h" +#include "BLEBeacon.h" +#include "BLEAdvertising.h" +#include "BLEEddystoneTLM.h" + +#include "esp_sleep.h" + +#define GPIO_DEEP_SLEEP_DURATION 10 // sleep x seconds and then wake up +#define BEACON_POWER ESP_PWR_LVL_N12 +RTC_DATA_ATTR static time_t last; // remember last boot in RTC Memory +RTC_DATA_ATTR static uint32_t bootcount; // remember number of boots in RTC Memory + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ +BLEAdvertising *pAdvertising; +struct timeval nowTimeStruct; + +time_t lastTenth; + +#define BEACON_UUID "8ec76ea3-6668-48da-9866-75be8bc86f4d" // UUID 1 128-Bit (may use linux tool uuidgen or random numbers via https://www.uuidgenerator.net/) + +// Check +// https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md +// and http://www.hugi.scene.org/online/coding/hugi%2015%20-%20cmtadfix.htm +// for the temperature value. It is a 8.8 fixed-point notation +void setBeacon() { + BLEEddystoneTLM EddystoneTLM; + EddystoneTLM.setVolt((uint16_t)random(2800, 3700)); // 3300mV = 3.3V + EddystoneTLM.setTemp(random(-3000, 3000) / 100.0f); // 3000 = 30.00 ˚C + Serial.printf("Random Battery voltage is %d mV = 0x%04X\n", EddystoneTLM.getVolt(), EddystoneTLM.getVolt()); + Serial.printf("Random temperature is %.2f°C\n", EddystoneTLM.getTemp()); + Serial.printf("Converted to 8.8 format: 0x%04X\n", EddystoneTLM.getRawTemp()); + + BLEAdvertisementData oAdvertisementData = BLEAdvertisementData(); + BLEAdvertisementData oScanResponseData = BLEAdvertisementData(); + oScanResponseData.setServiceData(BLEUUID((uint16_t)0xFEAA), String(EddystoneTLM.getData().c_str(), EddystoneTLM.getData().length())); + + oAdvertisementData.setName("ESP32 TLM Beacon"); + pAdvertising->setAdvertisementData(oAdvertisementData); + pAdvertising->setScanResponseData(oScanResponseData); +} + +void setup() { + Serial.begin(115200); + gettimeofday(&nowTimeStruct, NULL); + + Serial.printf("Starting ESP32. Bootcount = %lu\n", bootcount++); + Serial.printf("Deep sleep (%llds since last reset, %llds since last boot)\n", nowTimeStruct.tv_sec, nowTimeStruct.tv_sec - last); + + last = nowTimeStruct.tv_sec; + lastTenth = nowTimeStruct.tv_sec * 10; // Time since last reset as 0.1 second resolution counter + + // Create the BLE Device + BLEDevice::init("TLMBeacon"); + + BLEDevice::setPower(BEACON_POWER); + + pAdvertising = BLEDevice::getAdvertising(); + + setBeacon(); + // Start advertising + pAdvertising->start(); + Serial.println("Advertising started for 10s ..."); + delay(10000); + pAdvertising->stop(); + Serial.printf("Enter deep sleep for 10s\n"); + esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION); +} + +void loop() {} diff --git a/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.md b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.md new file mode 100644 index 0000000..2e34029 --- /dev/null +++ b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.md @@ -0,0 +1,14 @@ +## Eddystone TLM beacon +EddystoneTLM beacon by BeeGee based on +[pcbreflux ESP32 Eddystone TLM deepsleep](https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_Eddystone_TLM_deepsleep/ESP32_Eddystone_TLM_deepsleep.ino) + +[EddystoneTLM frame specification](https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md) + + Create a BLE server that will send periodic Eddystone TLM frames. + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create advertising data + 3. Start advertising. + 4. wait + 5. Stop advertising. + 6. deep sleep diff --git a/libraries/BLE/examples/EddystoneTLM_Beacon/ci.yml b/libraries/BLE/examples/EddystoneTLM_Beacon/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/EddystoneTLM_Beacon/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino new file mode 100644 index 0000000..d520c84 --- /dev/null +++ b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino @@ -0,0 +1,105 @@ +/* + EddystoneURL beacon by BeeGee + EddystoneURL frame specification https://github.com/google/eddystone/blob/master/eddystone-url/README.md + + Upgraded on: Feb 20, 2023 + By: Tomas Pilny +*/ + +/* + Create a BLE server that will send periodic Eddystone URL frames. + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create advertising data + 3. Start advertising. + 4. wait + 5. Stop advertising. + 6. deep sleep + +*/ +#include "sys/time.h" + +#include + +#include "BLEDevice.h" +#include "BLEUtils.h" +#include "BLEBeacon.h" +#include "BLEAdvertising.h" +#include "BLEEddystoneURL.h" +#include "esp_sleep.h" + +char unprintable[] = {0x01, 0xFF, 0xDE, 0xAD}; +String URL[] = { + "http://www.espressif.com/", // prefix 0x00, suffix 0x00 + "https://www.texas.gov", // prefix 0x01, suffix 0x0D + "http://en.mapy.cz", // prefix 0x02, no valid suffix + "https://arduino.cc", // prefix 0x03, no valid suffix + "google.com", // URL without specified prefix - the function will assume default prefix "http://www." = 0x00 + "diginfo.tv", // URL without specified prefix - the function will assume default prefix "http://www." = 0x00 + // "http://www.URLsAbove17BytesAreNotAllowed.com", // Too long URL - setSmartURL() will return 0 = ERR + // "", // Empty string - setSmartURL() will return 0 = ERR + // String(unprintable), // Unprintable characters / corrupted String - setSmartURL() will return 0 = ERR +}; + +#define GPIO_DEEP_SLEEP_DURATION 10 // sleep x seconds and then wake up +#define BEACON_POWER ESP_PWR_LVL_N12 +RTC_DATA_ATTR static time_t last; // remember last boot in RTC Memory +RTC_DATA_ATTR static uint32_t bootcount; // remember number of boots in RTC Memory + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ +BLEAdvertising *pAdvertising; +struct timeval now; + +int setBeacon() { + BLEAdvertisementData oAdvertisementData = BLEAdvertisementData(); + BLEAdvertisementData oScanResponseData = BLEAdvertisementData(); + + BLEEddystoneURL EddystoneURL; + EddystoneURL.setPower(BEACON_POWER); // This is only information about the power. The actual power is set by `BLEDevice::setPower(BEACON_POWER)` + if (EddystoneURL.setSmartURL(URL[bootcount % (sizeof(URL) / sizeof(URL[0]))])) { + String frame = EddystoneURL.getFrame(); + String data(EddystoneURL.getFrame().c_str(), frame.length()); + oAdvertisementData.addData(data); + oScanResponseData.setName("ESP32 URLBeacon"); + pAdvertising->setAdvertisementData(oAdvertisementData); + pAdvertising->setScanResponseData(oScanResponseData); + Serial.printf("Advertise URL \"%s\"\n", URL[bootcount % (sizeof(URL) / sizeof(URL[0]))].c_str()); + return 1; // OK + } else { + Serial.println("Smart URL set ERR"); + return 0; // ERR + } +} + +void setup() { + Serial.begin(115200); + gettimeofday(&now, NULL); + + Serial.printf("Start ESP32 %lu\n", bootcount++); + Serial.printf("Deep sleep (%llds since last reset, %llds since last boot)\n", now.tv_sec, now.tv_sec - last); + + last = now.tv_sec; + + // Create the BLE Device + BLEDevice::init("URLBeacon"); + BLEDevice::setPower(BEACON_POWER); + + // Create the BLE Server + // BLEServer *pServer = BLEDevice::createServer(); // <-- no longer required to instantiate BLEServer, less flash and ram usage + + pAdvertising = BLEDevice::getAdvertising(); + + if (setBeacon()) { + // Start advertising + pAdvertising->start(); + Serial.println("Advertising started..."); + delay(10000); + pAdvertising->stop(); + } + Serial.println("Enter deep sleep"); + bootcount++; + esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION); +} + +void loop() {} diff --git a/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.md b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.md new file mode 100644 index 0000000..2baf1cc --- /dev/null +++ b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.md @@ -0,0 +1,14 @@ +## Eddystone URL beacon +EddystoneURL beacon by BeeGee based on +[pcbreflux ESP32 Eddystone URL deepsleep](https://github.com/pcbreflux/espressif/tree/master/esp32/arduino/sketchbook/ESP32_Eddystone_URL_deepsleep) + +[EddystoneURL frame specification](https://github.com/google/eddystone/blob/master/eddystone-url/README.md) + + Create a BLE server that will send periodic Eddystone URL frames. + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create advertising data + 3. Start advertising. + 4. wait + 5. Stop advertising. + 6. deep sleep diff --git a/libraries/BLE/examples/EddystoneURL_Beacon/ci.yml b/libraries/BLE/examples/EddystoneURL_Beacon/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/EddystoneURL_Beacon/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Notify/Notify.ino b/libraries/BLE/examples/Notify/Notify.ino new file mode 100644 index 0000000..5f26768 --- /dev/null +++ b/libraries/BLE/examples/Notify/Notify.ino @@ -0,0 +1,112 @@ +/* + Video: https://www.youtube.com/watch?v=oCMOYS71NIU + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp + Ported to Arduino ESP32 by Evandro Copercini + updated by chegewara + + Create a BLE server that, once we receive a connection, will send periodic notifications. + The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b + And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8 + + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create a BLE Service + 3. Create a BLE Characteristic on the Service + 4. Create a BLE Descriptor on the characteristic + 5. Start the service. + 6. Start advertising. + + A connect handler associated with the server starts a background task that performs notification + every couple of seconds. +*/ +#include +#include +#include +#include +#include + +BLEServer *pServer = NULL; +BLECharacteristic *pCharacteristic = NULL; +BLE2901 *descriptor_2901 = NULL; + +bool deviceConnected = false; +bool oldDeviceConnected = false; +uint32_t value = 0; + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +class MyServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + deviceConnected = true; + }; + + void onDisconnect(BLEServer *pServer) { + deviceConnected = false; + } +}; + +void setup() { + Serial.begin(115200); + + // Create the BLE Device + BLEDevice::init("ESP32"); + + // Create the BLE Server + pServer = BLEDevice::createServer(); + pServer->setCallbacks(new MyServerCallbacks()); + + // Create the BLE Service + BLEService *pService = pServer->createService(SERVICE_UUID); + + // Create a BLE Characteristic + pCharacteristic = pService->createCharacteristic( + CHARACTERISTIC_UUID, + BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY | BLECharacteristic::PROPERTY_INDICATE + ); + + // Creates BLE Descriptor 0x2902: Client Characteristic Configuration Descriptor (CCCD) + // Descriptor 2902 is not required when using NimBLE as it is automatically added based on the characteristic properties + pCharacteristic->addDescriptor(new BLE2902()); + // Adds also the Characteristic User Description - 0x2901 descriptor + descriptor_2901 = new BLE2901(); + descriptor_2901->setDescription("My own description for this characteristic."); + descriptor_2901->setAccessPermissions(ESP_GATT_PERM_READ); // enforce read only - default is Read|Write + pCharacteristic->addDescriptor(descriptor_2901); + + // Start the service + pService->start(); + + // Start advertising + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVICE_UUID); + pAdvertising->setScanResponse(false); + pAdvertising->setMinPreferred(0x0); // set value to 0x00 to not advertise this parameter + BLEDevice::startAdvertising(); + Serial.println("Waiting a client connection to notify..."); +} + +void loop() { + // notify changed value + if (deviceConnected) { + pCharacteristic->setValue((uint8_t *)&value, 4); + pCharacteristic->notify(); + value++; + delay(500); + } + // disconnecting + if (!deviceConnected && oldDeviceConnected) { + delay(500); // give the bluetooth stack the chance to get things ready + pServer->startAdvertising(); // restart advertising + Serial.println("start advertising"); + oldDeviceConnected = deviceConnected; + } + // connecting + if (deviceConnected && !oldDeviceConnected) { + // do stuff here on connecting + oldDeviceConnected = deviceConnected; + } +} diff --git a/libraries/BLE/examples/Notify/ci.yml b/libraries/BLE/examples/Notify/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Notify/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Scan/Scan.ino b/libraries/BLE/examples/Scan/Scan.ino new file mode 100644 index 0000000..6b8a1fa --- /dev/null +++ b/libraries/BLE/examples/Scan/Scan.ino @@ -0,0 +1,40 @@ +/* + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp + Ported to Arduino ESP32 by Evandro Copercini +*/ + +#include +#include +#include +#include + +int scanTime = 5; //In seconds +BLEScan *pBLEScan; + +class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks { + void onResult(BLEAdvertisedDevice advertisedDevice) { + Serial.printf("Advertised Device: %s \n", advertisedDevice.toString().c_str()); + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Scanning..."); + + BLEDevice::init(""); + pBLEScan = BLEDevice::getScan(); //create new scan + pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks()); + pBLEScan->setActiveScan(true); //active scan uses more power, but get results faster + pBLEScan->setInterval(100); + pBLEScan->setWindow(99); // less or equal setInterval value +} + +void loop() { + // put your main code here, to run repeatedly: + BLEScanResults *foundDevices = pBLEScan->start(scanTime, false); + Serial.print("Devices found: "); + Serial.println(foundDevices->getCount()); + Serial.println("Scan done!"); + pBLEScan->clearResults(); // delete results fromBLEScan buffer to release memory + delay(2000); +} diff --git a/libraries/BLE/examples/Scan/ci.yml b/libraries/BLE/examples/Scan/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Scan/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Server/Server.ino b/libraries/BLE/examples/Server/Server.ino new file mode 100644 index 0000000..da7f6bc --- /dev/null +++ b/libraries/BLE/examples/Server/Server.ino @@ -0,0 +1,46 @@ +/* + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleServer.cpp + Ported to Arduino ESP32 by Evandro Copercini + updates by chegewara +*/ + +#include +#include +#include + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +void setup() { + Serial.begin(115200); + Serial.println("Starting BLE work!"); + + if (!BLEDevice::init("BLE Server Example")) { + Serial.println("BLE initialization failed!"); + return; + } + + BLEServer *pServer = BLEDevice::createServer(); + BLEService *pService = pServer->createService(SERVICE_UUID); + BLECharacteristic *pCharacteristic = + pService->createCharacteristic(CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE); + + pCharacteristic->setValue("Hello World says Neil"); + pService->start(); + // BLEAdvertising *pAdvertising = pServer->getAdvertising(); // this still is working for backward compatibility + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVICE_UUID); + pAdvertising->setScanResponse(true); + pAdvertising->setMinPreferred(0x06); // functions that help with iPhone connections issue + pAdvertising->setMaxPreferred(0x12); + BLEDevice::startAdvertising(); + Serial.println("Characteristic defined! Now you can read it in your phone!"); +} + +void loop() { + // put your main code here, to run repeatedly: + delay(2000); +} diff --git a/libraries/BLE/examples/Server/ci.yml b/libraries/BLE/examples/Server/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Server/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Server_Gamepad/Server_Gamepad.ino b/libraries/BLE/examples/Server_Gamepad/Server_Gamepad.ino new file mode 100644 index 0000000..301bcac --- /dev/null +++ b/libraries/BLE/examples/Server_Gamepad/Server_Gamepad.ino @@ -0,0 +1,214 @@ +/* + * BLE HID Gamepad Example + * + * This example demonstrates how to create a BLE HID Gamepad device using ESP32. + * The gamepad will appear as a standard HID game controller on Windows, macOS, Linux, Android, and iOS. + * + * Features: + * - 8 buttons (mapped to buttons 1-8) + * - 2 axes (X, Y for joystick movement) + * - Secure pairing with bonding + * - Battery level reporting + * - Automatic reconnection after power cycle + * + * Usage: + * 1. Upload this sketch to your ESP32 + * 2. Pair with your device (Windows: Settings > Bluetooth & devices) + * 3. The gamepad will send test input (circular motion and button toggle) + * 4. Test in any game or with gamepad testing tools like https://hardwaretester.com/gamepad + * + * Note: This example uses "Just Works" pairing for automatic connection without + * PIN entry or confirmation, just like real gamepads. The bond is saved for future connections. + * + * Created by lucasssvaz + */ + +#include +#include +#include +#include +#include + +// HID Report Descriptor for a gamepad with 8 buttons and 2 axes (X, Y) +// This descriptor defines the gamepad as having: +// - 8 buttons (usage buttons 1-8) +// - 2 8-bit axes (X, Y) with range -127 to 127 +const uint8_t hidReportDescriptor[] = { + 0x05, 0x01, // Usage Page (Generic Desktop) + 0x09, 0x05, // Usage (Gamepad) + 0xA1, 0x01, // Collection (Application) + 0x85, 0x01, // Report ID (1) + 0x09, 0x01, // Usage (Pointer) + 0xA1, 0x00, // Collection (Physical) + 0x09, 0x30, // Usage (X) + 0x09, 0x31, // Usage (Y) + 0x15, 0x81, // Logical Minimum (-127) + 0x25, 0x7F, // Logical Maximum (127) + 0x75, 0x08, // Report Size (8) + 0x95, 0x02, // Report Count (2) + 0x81, 0x02, // Input (Data, Variable, Absolute) + 0xC0, // End Collection + 0x05, 0x09, // Usage Page (Button) + 0x19, 0x01, // Usage Minimum (Button 1) + 0x29, 0x08, // Usage Maximum (Button 8) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x75, 0x01, // Report Size (1) + 0x95, 0x08, // Report Count (8) + 0x81, 0x02, // Input (Data, Variable, Absolute) + 0xC0 // End Collection +}; + +// Gamepad report structure (matches the HID descriptor) +struct GamepadReport { + uint8_t reportId; // Report ID (must be 1) + int8_t x; // X axis (-127 to 127) + int8_t y; // Y axis (-127 to 127) + uint8_t buttons; // 8 buttons (bit 0-7) +} __attribute__((packed)); + +BLEHIDDevice *hid; +BLECharacteristic *inputGamepad; +BLEServer *server; +bool deviceConnected = false; + +// Server callbacks to track connection status +class ServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + deviceConnected = true; + Serial.println("Client connected"); + } + + void onDisconnect(BLEServer *pServer) { + deviceConnected = false; + Serial.println("Client disconnected"); + // Restart advertising so we can reconnect + BLEDevice::startAdvertising(); + Serial.println("Advertising restarted"); + } +}; + +// Security callbacks for "Just Works" pairing +class SecurityCallbacks : public BLESecurityCallbacks { + bool onSecurityRequest() { + return true; // Accept all pairing requests + } + +#if defined(CONFIG_BLUEDROID_ENABLED) + void onAuthenticationComplete(esp_ble_auth_cmpl_t auth_cmpl) { + if (auth_cmpl.success) { + Serial.println("Pairing successful!"); + } else { + Serial.printf("Pairing failed, status: %d\n", auth_cmpl.fail_reason); + } + } +#elif defined(CONFIG_NIMBLE_ENABLED) + void onAuthenticationComplete(ble_gap_conn_desc *desc) { + if (desc->sec_state.encrypted) { + Serial.println("Pairing successful!"); + } else { + Serial.println("Pairing failed"); + } + } +#endif + + // These are not used with "Just Works" pairing (ESP_IO_CAP_NONE) + uint32_t onPassKeyRequest() { + return 0; + } + void onPassKeyNotify(uint32_t pass_key) {} + bool onConfirmPIN(uint32_t pass_key) { + return true; + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Starting BLE HID Gamepad"); + + // Initialize BLE + BLEDevice::init("ESP32-Gamepad"); + + // Configure BLE Security for pairing and bonding + // Use "Just Works" pairing - no user interaction required (like a real gamepad) + BLESecurity *pSecurity = new BLESecurity(); + + // Set IO capability to NONE (no display, no keyboard - like a real gamepad) + pSecurity->setCapability(ESP_IO_CAP_NONE); + + // Set authentication mode: bonding=true, MITM=false, secure connection=true + // This enables "Just Works" pairing with bonding + pSecurity->setAuthenticationMode(true, false, true); + + // Set security callbacks + BLEDevice::setSecurityCallbacks(new SecurityCallbacks()); + + // Create BLE Server + server = BLEDevice::createServer(); + server->setCallbacks(new ServerCallbacks()); + + // Create HID Device + hid = new BLEHIDDevice(server); + + // Set HID device information + hid->manufacturer()->setValue("Espressif"); + hid->pnp(0x02, 0x05ac, 0x820a, 0x0110); // Vendor ID, Product ID, Product Version + hid->hidInfo(0x00, 0x01); // HID version, country code + + // Set Report Map (HID descriptor) + hid->reportMap((uint8_t *)hidReportDescriptor, sizeof(hidReportDescriptor)); + + // Create input report characteristic for gamepad + inputGamepad = hid->inputReport(1); // Report ID 1 + + // Set battery level to 100% + hid->setBatteryLevel(100); + + // Start HID services + hid->startServices(); + + // Setup advertising + BLEAdvertising *advertising = BLEDevice::getAdvertising(); + advertising->setAppearance(0x03C4); // HID Gamepad appearance + advertising->addServiceUUID(hid->hidService()->getUUID()); + advertising->setScanResponse(true); + advertising->setMinPreferred(0x06); // Help with connection issues + advertising->setMaxPreferred(0x12); + + BLEDevice::startAdvertising(); + + Serial.println("BLE HID Gamepad ready!"); + Serial.println("Waiting for connection..."); +} + +void loop() { + if (deviceConnected) { + static uint32_t lastReportTime = 0; + static uint32_t counter = 0; + + // Send a report every 50ms (20Hz) + if (millis() - lastReportTime >= 50) { + lastReportTime = millis(); + counter++; + + GamepadReport report; + report.reportId = 1; + + // Simulate some movement (sine wave pattern) + report.x = (int8_t)(127 * sin(counter * 0.1)); // X axis: -127 to 127 + report.y = (int8_t)(127 * cos(counter * 0.1)); // Y axis: -127 to 127 + report.buttons = (counter % 40 < 20) ? 0x01 : 0x00; // Toggle first button every second + + // Send the report + inputGamepad->setValue((uint8_t *)&report, sizeof(report)); + inputGamepad->notify(); + + // Print status every 2 seconds + if (counter % 40 == 0) { + Serial.printf("Report #%lu: X=%d, Y=%d, Buttons=0x%02X\n", counter, report.x, report.y, report.buttons); + } + } + } + + delay(10); +} diff --git a/libraries/BLE/examples/Server_Gamepad/ci.yml b/libraries/BLE/examples/Server_Gamepad/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Server_Gamepad/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino b/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino new file mode 100644 index 0000000..ff8712d --- /dev/null +++ b/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino @@ -0,0 +1,123 @@ +/* + Video: https://www.youtube.com/watch?v=oCMOYS71NIU + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp + Ported to Arduino ESP32 by Evandro Copercini + updated by chegewara + + Create a BLE server that, once we receive a connection, will send periodic notifications. + The server will continue advertising for more connections after the first one and will notify + the value of a counter to all connected clients. + + The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b + And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8 + + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create a BLE Service + 3. Create a BLE Characteristic on the Service + 4. Create a BLE Descriptor on the characteristic + 5. Start the service. + 6. Start advertising. + + A connect handler associated with the server starts a background task that performs notification + every couple of seconds. +*/ +#include +#include +#include +#include + +BLEServer *pServer = NULL; +BLECharacteristic *pCharacteristic = NULL; +int connectedClients = 0; +bool deviceConnected = false; +uint32_t value = 0; + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +class MyServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + connectedClients++; + Serial.print("Client connected. Total clients: "); + Serial.println(connectedClients); + // Continue advertising for more connections + BLEDevice::startAdvertising(); + }; + + void onDisconnect(BLEServer *pServer) { + connectedClients--; + Serial.print("Client disconnected. Total clients: "); + Serial.println(connectedClients); + } +}; + +void setup() { + Serial.begin(115200); + + // Create the BLE Device + BLEDevice::init("ESP32"); + + // Create the BLE Server + pServer = BLEDevice::createServer(); + pServer->setCallbacks(new MyServerCallbacks()); + + // Create the BLE Service + BLEService *pService = pServer->createService(SERVICE_UUID); + + // Create a BLE Characteristic + pCharacteristic = pService->createCharacteristic( + CHARACTERISTIC_UUID, + BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY | BLECharacteristic::PROPERTY_INDICATE + ); + + // Descriptor 2902 is not required when using NimBLE as it is automatically added based on the characteristic properties + pCharacteristic->addDescriptor(new BLE2902()); + + // Start the service + pService->start(); + + // Start advertising + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVICE_UUID); + pAdvertising->setScanResponse(false); + pAdvertising->setMinPreferred(0x0); // set value to 0x00 to not advertise this parameter + BLEDevice::startAdvertising(); + Serial.println("Waiting for client connections to notify..."); +} + +void loop() { + // Notify changed value to all connected clients + if (connectedClients > 0) { + Serial.print("Notifying value: "); + Serial.print(value); + Serial.print(" to "); + Serial.print(connectedClients); + Serial.println(" client(s)"); + pCharacteristic->setValue((uint8_t *)&value, 4); + pCharacteristic->notify(); + value++; + // Bluetooth stack will go into congestion, if too many packets are sent. + // In 6 hours of testing, I was able to go as low as 3ms. + // When using core debug level "debug" or "verbose", the delay can be increased in + // order to reduce the number of debug messages in the serial monitor. + delay(100); + } + + // Disconnecting - restart advertising when no clients are connected + if (connectedClients == 0 && deviceConnected) { + delay(500); // give the bluetooth stack the chance to get things ready + pServer->startAdvertising(); // restart advertising + Serial.println("No clients connected, restarting advertising"); + deviceConnected = false; + } + + // Connecting - update state when first client connects + if (connectedClients > 0 && !deviceConnected) { + // do stuff here on first connecting + deviceConnected = true; + } +} diff --git a/libraries/BLE/examples/Server_multiconnect/ci.yml b/libraries/BLE/examples/Server_multiconnect/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Server_multiconnect/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Server_secure_authorization/Server_secure_authorization.ino b/libraries/BLE/examples/Server_secure_authorization/Server_secure_authorization.ino new file mode 100644 index 0000000..2056e79 --- /dev/null +++ b/libraries/BLE/examples/Server_secure_authorization/Server_secure_authorization.ino @@ -0,0 +1,160 @@ +/* + Simple BLE Server Authorization Example + + This example demonstrates how to create a BLE server with authorization + requirements. It shows the essential setup for: + - Authorization with static passkey + - Secure connection + - MITM (Man-In-The-Middle) protection + + The server creates a single characteristic that requires authorization + to access. Clients must provide the correct passkey (123456) to read + or write to the characteristic. + + Note that ESP32 uses Bluedroid by default and the other SoCs use NimBLE. + Bluedroid initiates security on-connect, while NimBLE initiates security on-demand. + + Due to a bug in ESP-IDF's Bluedroid, this example will currently not work with ESP32. + + IMPORTANT: MITM (Man-In-The-Middle protection) must be enabled for password prompts + to work. Without MITM, the BLE stack assumes no user interaction is needed and will use + "Just Works" pairing method (with encryption if secure connection is enabled). + + Created by lucasssvaz. +*/ + +#include +#include +#include +#include +#include + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +// Example passkey - change this for production use +#define AUTH_PASSKEY 123456 + +static int s_readCount = 0; +static BLECharacteristic *s_pCharacteristic; + +class MySecurityCallbacks : public BLESecurityCallbacks { + bool onAuthorizationRequest(uint16_t connHandle, uint16_t attrHandle, bool isRead) { + Serial.println("Authorization request received"); + if (isRead) { + s_readCount++; + // Keep value length <= (MTU - 1) to avoid a follow-up read request + uint16_t maxLen = BLEDevice::getServer()->getPeerMTU(connHandle) - 1; + String msg = "Authorized #" + String(s_readCount); + if (msg.length() > maxLen) { + msg = msg.substring(0, maxLen); + } + s_pCharacteristic->setValue(msg); + // Grant authorization to the first 3 reads + if (s_readCount <= 3) { + Serial.println("Authorization granted"); + return true; + } else { + Serial.println("Authorization denied, read count exceeded"); + Serial.println("Please reset the read counter to continue"); + return false; + } + } + // Fallback to deny + Serial.println("Authorization denied"); + return false; + } +}; + +void setup() { + Serial.begin(115200); + Serial.println("Starting BLE Authorization Example!"); + + // Initialize the BOOT pin for resetting the read count + pinMode(BOOT_PIN, INPUT_PULLUP); + + // Clear NVS to remove any cached pairing information + // This ensures fresh authentication for testing + Serial.println("Clearing NVS pairing data..."); + nvs_flash_erase(); + nvs_flash_init(); + + Serial.print("Using BLE stack: "); + Serial.println(BLEDevice::getBLEStackString()); + + BLEDevice::init("BLE Auth Server"); + + // Set MTU to 517 to avoid a follow-up read request + BLEDevice::setMTU(517); + + // Configure BLE Security + BLESecurity *pSecurity = new BLESecurity(); + + // Set static passkey for authentication + pSecurity->setPassKey(true, AUTH_PASSKEY); + + // Set IO capability to DisplayOnly for MITM authentication + pSecurity->setCapability(ESP_IO_CAP_OUT); + + // Enable authorization requirements: + // - bonding: true (for persistent storage of the keys) + // - MITM: true (enables Man-In-The-Middle protection for password prompts) + // - secure connection: true (enables secure connection for encryption) + pSecurity->setAuthenticationMode(true, true, true); + + // Set the security callbacks + BLEDevice::setSecurityCallbacks(new MySecurityCallbacks()); + + // Create BLE Server + BLEServer *pServer = BLEDevice::createServer(); + pServer->advertiseOnDisconnect(true); + + // Create BLE Service + BLEService *pService = pServer->createService(SERVICE_UUID); + + // Create characteristic with read and write properties + uint32_t properties = BLECharacteristic::PROPERTY_READ; + + // For NimBLE: Add authentication properties + // These properties ensure the characteristic requires authorization + // (ignored by Bluedroid but harmless) + properties |= BLECharacteristic::PROPERTY_READ_AUTHEN | BLECharacteristic::PROPERTY_READ_AUTHOR; + + s_pCharacteristic = pService->createCharacteristic(CHARACTERISTIC_UUID, properties); + + // For Bluedroid: Set access permissions that require encryption and MITM + // This ensures authorization is required (ignored by NimBLE) + s_pCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM | ESP_GATT_PERM_READ_AUTHORIZATION); + + // Set initial value + s_pCharacteristic->setValue("Hello! You needed authorization to read this!"); + + // Start the service + pService->start(); + + // Configure and start advertising + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVICE_UUID); + pAdvertising->setScanResponse(true); + pAdvertising->setMinPreferred(0x06); // helps with iPhone connections + pAdvertising->setMaxPreferred(0x12); + + BLEDevice::startAdvertising(); + + Serial.println("BLE Server is running!"); + Serial.println("Authorization is required to access the characteristic."); + Serial.printf("Use passkey: %d when prompted\n", AUTH_PASSKEY); +} + +void loop() { + // Reset the read count if the BOOT pin is pressed + if (digitalRead(BOOT_PIN) == LOW) { + s_readCount = 0; + Serial.println("Read count reset"); + } + + delay(100); +} diff --git a/libraries/BLE/examples/Server_secure_authorization/ci.yml b/libraries/BLE/examples/Server_secure_authorization/ci.yml new file mode 100644 index 0000000..274bd2b --- /dev/null +++ b/libraries/BLE/examples/Server_secure_authorization/ci.yml @@ -0,0 +1,7 @@ +targets: + esp32: false + +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_BLE_SUPPORTED=y diff --git a/libraries/BLE/examples/Server_secure_static_passkey/Server_secure_static_passkey.ino b/libraries/BLE/examples/Server_secure_static_passkey/Server_secure_static_passkey.ino new file mode 100644 index 0000000..3ccba21 --- /dev/null +++ b/libraries/BLE/examples/Server_secure_static_passkey/Server_secure_static_passkey.ino @@ -0,0 +1,195 @@ +/* + Secure server with static passkey + + This example demonstrates how to create a secure BLE server with no + IO capability using a static passkey. + The server will accept connections from devices that have the same passkey set. + The example passkey is set to 123456. + The server will create a service and a secure and an insecure characteristic + to be used as example. + + This server is designed to be used with the Client_secure_static_passkey example. + + Note that ESP32 uses Bluedroid by default and the other SoCs use NimBLE. + Bluedroid initiates security on-connect, while NimBLE initiates security on-demand. + This means that in NimBLE you can read the insecure characteristic without entering + the passkey. This is not possible in Bluedroid. + + IMPORTANT: MITM (Man-In-The-Middle protection) must be enabled for password prompts + to work. Without MITM, the BLE stack assumes no user interaction is needed and will use + "Just Works" pairing method (with encryption if secure connection is enabled). + + Based on examples from Neil Kolban and h2zero. + Created by lucasssvaz. +*/ + +#include +#include +#include +#include +#include +#include + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define INSECURE_CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" +#define SECURE_CHARACTERISTIC_UUID "ff1d2614-e2d6-4c87-9154-6625d39ca7f8" + +// This is an example passkey. You should use a different or random passkey. +#define SERVER_PIN 123456 + +// Print an IRK buffer as hex with leading zeros and ':' separator +static void printIrkBinary(uint8_t *irk) { + for (int i = 0; i < 16; i++) { + if (irk[i] < 0x10) { + Serial.print("0"); + } + Serial.print(irk[i], HEX); + if (i < 15) { + Serial.print(":"); + } + } +} + +static void get_peer_irk(BLEAddress peerAddr) { + Serial.println("\n=== Retrieving peer IRK (Client) ===\n"); + + uint8_t irk[16]; + + // Get IRK in binary format + if (BLEDevice::getPeerIRK(peerAddr, irk)) { + Serial.println("Successfully retrieved peer IRK in binary format:"); + printIrkBinary(irk); + Serial.println("\n"); + } + + // Get IRK in different string formats + String irkString = BLEDevice::getPeerIRKString(peerAddr); + String irkBase64 = BLEDevice::getPeerIRKBase64(peerAddr); + String irkReverse = BLEDevice::getPeerIRKReverse(peerAddr); + + if (irkString.length() > 0) { + Serial.println("Successfully retrieved peer IRK in multiple formats:\n"); + Serial.print("IRK (comma-separated hex): "); + Serial.println(irkString); + Serial.print("IRK (Base64 for Home Assistant Private BLE Device): "); + Serial.println(irkBase64); + Serial.print("IRK (reverse hex for Home Assistant ESPresense): "); + Serial.println(irkReverse); + Serial.println(); + } else { + Serial.println("!!! Failed to retrieve peer IRK !!!"); + Serial.println("This is expected if bonding is disabled or the peer doesn't distribute its Identity Key."); + Serial.println("To enable bonding, change setAuthenticationMode to: pSecurity->setAuthenticationMode(true, true, true);\n"); + } + + Serial.println("=======================================\n"); +} + +// Security callbacks to print IRKs once authentication completes +class MySecurityCallbacks : public BLESecurityCallbacks { +#if defined(CONFIG_BLUEDROID_ENABLED) + void onAuthenticationComplete(esp_ble_auth_cmpl_t desc) override { + // Print the IRK received by the peer + BLEAddress peerAddr(desc.bd_addr); + get_peer_irk(peerAddr); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + void onAuthenticationComplete(ble_gap_conn_desc *desc) override { + // Print the IRK received by the peer + BLEAddress peerAddr(desc->peer_id_addr.val, desc->peer_id_addr.type); + get_peer_irk(peerAddr); + } +#endif +}; + +void setup() { + Serial.begin(115200); + Serial.println("Starting BLE work!"); + + // Clear NVS to remove any cached pairing information + // This ensures fresh authentication for testing + Serial.println("Clearing NVS pairing data..."); + nvs_flash_erase(); + nvs_flash_init(); + + Serial.print("Using BLE stack: "); + Serial.println(BLEDevice::getBLEStackString()); + + BLEDevice::init("Secure BLE Server"); + + BLESecurity *pSecurity = new BLESecurity(); + + // Set security parameters + // Default parameters: + // - IO capability is set to NONE + // - Initiator and responder key distribution flags are set to both encryption and identity keys. + // - Passkey is set to BLE_SM_DEFAULT_PASSKEY (123456). It will warn if you don't change it. + // - Key size is set to 16 bytes + + // Set static passkey + // The first argument defines if the passkey is static or random. + // The second argument is the passkey (ignored when using a random passkey). + pSecurity->setPassKey(true, SERVER_PIN); + + // Set IO capability to DisplayOnly + // We need the proper IO capability for MITM authentication even + // if the passkey is static and won't be shown to the user + // See https://www.bluetooth.com/blog/bluetooth-pairing-part-2-key-generation-methods/ + pSecurity->setCapability(ESP_IO_CAP_OUT); + + // Set authentication mode + // Enable bonding, MITM (for password prompts), and secure connection for this example + pSecurity->setAuthenticationMode(true, true, true); + + // Set callbacks to handle authentication completion and print IRKs + BLEDevice::setSecurityCallbacks(new MySecurityCallbacks()); + + BLEServer *pServer = BLEDevice::createServer(); + pServer->advertiseOnDisconnect(true); + + BLEService *pService = pServer->createService(SERVICE_UUID); + + uint32_t insecure_properties = BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE; + uint32_t secure_properties = insecure_properties; + + // NimBLE uses properties to secure characteristics. + // These special permission properties are not supported by Bluedroid and will be ignored. + // This can be removed if only using Bluedroid (ESP32). + // Check the BLECharacteristic.h file for more information. + secure_properties |= BLECharacteristic::PROPERTY_READ_AUTHEN | BLECharacteristic::PROPERTY_WRITE_AUTHEN; + + BLECharacteristic *pSecureCharacteristic = pService->createCharacteristic(SECURE_CHARACTERISTIC_UUID, secure_properties); + BLECharacteristic *pInsecureCharacteristic = pService->createCharacteristic(INSECURE_CHARACTERISTIC_UUID, insecure_properties); + + // Bluedroid uses permissions to secure characteristics. + // This is the same as using the properties above. + // NimBLE does not use permissions and will ignore these calls. + // This can be removed if only using NimBLE (any SoC except ESP32). + pSecureCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENC_MITM | ESP_GATT_PERM_WRITE_ENC_MITM); + pInsecureCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + + // Set value for secure characteristic + pSecureCharacteristic->setValue("Secure Hello World!"); + + // Set value for insecure characteristic + // When using NimBLE you will be able to read this characteristic without entering the passkey. + pInsecureCharacteristic->setValue("Insecure Hello World!"); + + pService->start(); + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(SERVICE_UUID); + pAdvertising->setScanResponse(true); + pAdvertising->setMinPreferred(0x06); // functions that help with iPhone connections issue + pAdvertising->setMaxPreferred(0x12); + BLEDevice::startAdvertising(); + Serial.println("Characteristic defined! Now you can read it in your phone!"); +} + +void loop() { + delay(2000); +} diff --git a/libraries/BLE/examples/Server_secure_static_passkey/ci.yml b/libraries/BLE/examples/Server_secure_static_passkey/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Server_secure_static_passkey/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/UART/UART.ino b/libraries/BLE/examples/UART/UART.ino new file mode 100644 index 0000000..d17ab49 --- /dev/null +++ b/libraries/BLE/examples/UART/UART.ino @@ -0,0 +1,123 @@ +/* + Video: https://www.youtube.com/watch?v=oCMOYS71NIU + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp + Ported to Arduino ESP32 by Evandro Copercini + + Create a BLE server that, once we receive a connection, will send periodic notifications. + The service advertises itself as: 6E400001-B5A3-F393-E0A9-E50E24DCCA9E + Has a characteristic of: 6E400002-B5A3-F393-E0A9-E50E24DCCA9E - used for receiving data with "WRITE" + Has a characteristic of: 6E400003-B5A3-F393-E0A9-E50E24DCCA9E - used to send data with "NOTIFY" + + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create a BLE Service + 3. Create a BLE Characteristic on the Service + 4. Create a BLE Descriptor on the characteristic + 5. Start the service. + 6. Start advertising. + + In this example rxValue is the data received (only accessible inside that function). + And txValue is the data to be sent, in this example just a byte incremented every second. +*/ +#include +#include +#include +#include + +BLEServer *pServer = NULL; +BLECharacteristic *pTxCharacteristic; +bool deviceConnected = false; +bool oldDeviceConnected = false; +uint8_t txValue = 0; + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "6E400001-B5A3-F393-E0A9-E50E24DCCA9E" // UART service UUID +#define CHARACTERISTIC_UUID_RX "6E400002-B5A3-F393-E0A9-E50E24DCCA9E" +#define CHARACTERISTIC_UUID_TX "6E400003-B5A3-F393-E0A9-E50E24DCCA9E" + +class MyServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + deviceConnected = true; + Serial.println("Device connected"); + }; + + void onDisconnect(BLEServer *pServer) { + deviceConnected = false; + Serial.println("Device disconnected"); + } +}; + +class MyCallbacks : public BLECharacteristicCallbacks { + void onWrite(BLECharacteristic *pCharacteristic) { + String rxValue = pCharacteristic->getValue(); + + if (rxValue.length() > 0) { + Serial.println("*********"); + Serial.print("Received Value: "); + for (int i = 0; i < rxValue.length(); i++) { + Serial.print(rxValue[i]); + } + + Serial.println(); + Serial.println("*********"); + } + } +}; + +void setup() { + Serial.begin(115200); + + // Create the BLE Device + BLEDevice::init("UART Service"); + + // Create the BLE Server + pServer = BLEDevice::createServer(); + pServer->setCallbacks(new MyServerCallbacks()); + + // Create the BLE Service + BLEService *pService = pServer->createService(SERVICE_UUID); + + // Create a BLE Characteristic + pTxCharacteristic = pService->createCharacteristic(CHARACTERISTIC_UUID_TX, BLECharacteristic::PROPERTY_NOTIFY); + + // Descriptor 2902 is not required when using NimBLE as it is automatically added based on the characteristic properties + pTxCharacteristic->addDescriptor(new BLE2902()); + + BLECharacteristic *pRxCharacteristic = pService->createCharacteristic(CHARACTERISTIC_UUID_RX, BLECharacteristic::PROPERTY_WRITE); + + pRxCharacteristic->setCallbacks(new MyCallbacks()); + + // Start the service + pService->start(); + + // Start advertising + pServer->getAdvertising()->start(); + Serial.println("Waiting a client connection to notify..."); +} + +void loop() { + + if (deviceConnected) { + Serial.print("Notifying Value: "); + Serial.println(txValue); + pTxCharacteristic->setValue(&txValue, 1); + pTxCharacteristic->notify(); + txValue++; + delay(1000); // Notifying every 1 second + } + + // disconnecting + if (!deviceConnected && oldDeviceConnected) { + delay(500); // give the bluetooth stack the chance to get things ready + pServer->startAdvertising(); // restart advertising + Serial.println("Started advertising again..."); + oldDeviceConnected = false; + } + // connecting + if (deviceConnected && !oldDeviceConnected) { + // do stuff here on connecting + oldDeviceConnected = true; + } +} diff --git a/libraries/BLE/examples/UART/ci.yml b/libraries/BLE/examples/UART/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/UART/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/Write/Write.ino b/libraries/BLE/examples/Write/Write.ino new file mode 100644 index 0000000..3cc6936 --- /dev/null +++ b/libraries/BLE/examples/Write/Write.ino @@ -0,0 +1,62 @@ +/* + Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleWrite.cpp + Ported to Arduino ESP32 by Evandro Copercini +*/ + +#include +#include +#include + +// See the following for generating UUIDs: +// https://www.uuidgenerator.net/ + +#define SERVICE_UUID "4fafc201-1fb5-459e-8fcc-c5c9c331914b" +#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8" + +class MyCallbacks : public BLECharacteristicCallbacks { + void onWrite(BLECharacteristic *pCharacteristic) { + String value = pCharacteristic->getValue(); + + if (value.length() > 0) { + Serial.println("*********"); + Serial.print("New value: "); + for (int i = 0; i < value.length(); i++) { + Serial.print(value[i]); + } + + Serial.println(); + Serial.println("*********"); + } + } +}; + +void setup() { + Serial.begin(115200); + + Serial.println("1- Download and install an BLE scanner app in your phone"); + Serial.println("2- Scan for BLE devices in the app"); + Serial.println("3- Connect to MyESP32"); + Serial.println("4- Go to CUSTOM CHARACTERISTIC in CUSTOM SERVICE and write something"); + Serial.println("5- See the magic =)"); + + BLEDevice::init("MyESP32"); + BLEServer *pServer = BLEDevice::createServer(); + + BLEService *pService = pServer->createService(SERVICE_UUID); + + BLECharacteristic *pCharacteristic = + pService->createCharacteristic(CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE); + + pCharacteristic->setCallbacks(new MyCallbacks()); + + pCharacteristic->setValue("Hello World"); + pService->start(); + + BLEAdvertising *pAdvertising = pServer->getAdvertising(); + pAdvertising->start(); +} + +void loop() { + // put your main code here, to run repeatedly: + delay(2000); +} diff --git a/libraries/BLE/examples/Write/ci.yml b/libraries/BLE/examples/Write/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/Write/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/iBeacon/ci.yml b/libraries/BLE/examples/iBeacon/ci.yml new file mode 100644 index 0000000..cfee8c8 --- /dev/null +++ b/libraries/BLE/examples/iBeacon/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_BLE_SUPPORTED=y + - CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE=y diff --git a/libraries/BLE/examples/iBeacon/iBeacon.ino b/libraries/BLE/examples/iBeacon/iBeacon.ino new file mode 100644 index 0000000..d5db613 --- /dev/null +++ b/libraries/BLE/examples/iBeacon/iBeacon.ino @@ -0,0 +1,133 @@ +/* + Based on 31337Ghost's reference code from https://github.com/nkolban/esp32-snippets/issues/385#issuecomment-362535434 + which is based on pcbreflux's Arduino ESP32 port of Neil Kolban's example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp +*/ + +/* + Create a BLE server that will send periodic iBeacon frames. + The design of creating the BLE server is: + 1. Create a BLE Server + 2. Create advertising data + 3. Start advertising. + 4. wait + 5. Stop advertising. +*/ +#include +#include +#include +#include +#include + +#define DEVICE_NAME "ESP32" +#define SERVICE_UUID "7A0247E7-8E88-409B-A959-AB5092DDB03E" +#define BEACON_UUID "2D7A9F0C-E0E8-4CC9-A71B-A21DB2D034A1" +#define BEACON_UUID_REV "A134D0B2-1DA2-1BA7-C94C-E8E00C9F7A2D" +#define CHARACTERISTIC_UUID "82258BAA-DF72-47E8-99BC-B73D7ECD08A5" + +BLEServer *pServer; +BLECharacteristic *pCharacteristic; +bool deviceConnected = false; +uint8_t value = 0; + +class MyServerCallbacks : public BLEServerCallbacks { + void onConnect(BLEServer *pServer) { + deviceConnected = true; + Serial.println("deviceConnected = true"); + }; + + void onDisconnect(BLEServer *pServer) { + deviceConnected = false; + Serial.println("deviceConnected = false"); + + // Restart advertising to be visible and connectable again + BLEAdvertising *pAdvertising; + pAdvertising = pServer->getAdvertising(); + pAdvertising->start(); + Serial.println("iBeacon advertising restarted"); + } +}; + +class MyCallbacks : public BLECharacteristicCallbacks { + void onWrite(BLECharacteristic *pCharacteristic) { + String rxValue = pCharacteristic->getValue(); + + if (rxValue.length() > 0) { + Serial.println("*********"); + Serial.print("Received Value: "); + for (int i = 0; i < rxValue.length(); i++) { + Serial.print(rxValue[i]); + } + Serial.println(); + Serial.println("*********"); + } + } +}; + +void init_service() { + BLEAdvertising *pAdvertising; + pAdvertising = pServer->getAdvertising(); + pAdvertising->stop(); + + // Create the BLE Service + BLEService *pService = pServer->createService(BLEUUID(SERVICE_UUID)); + + // Create a BLE Characteristic + pCharacteristic = pService->createCharacteristic( + CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY + ); + pCharacteristic->setCallbacks(new MyCallbacks()); + pCharacteristic->addDescriptor(new BLE2902()); + + pAdvertising->addServiceUUID(BLEUUID(SERVICE_UUID)); + + // Start the service + pService->start(); + + pAdvertising->start(); +} + +void init_beacon() { + BLEAdvertising *pAdvertising; + pAdvertising = pServer->getAdvertising(); + pAdvertising->stop(); + // iBeacon + BLEBeacon myBeacon; + myBeacon.setManufacturerId(0x4c00); + myBeacon.setMajor(5); + myBeacon.setMinor(88); + myBeacon.setSignalPower(0xc5); + myBeacon.setProximityUUID(BLEUUID(BEACON_UUID_REV)); + + BLEAdvertisementData advertisementData; + advertisementData.setFlags(0x1A); + advertisementData.setManufacturerData(myBeacon.getData()); + pAdvertising->setAdvertisementData(advertisementData); + + pAdvertising->start(); +} + +void setup() { + Serial.begin(115200); + Serial.println(); + Serial.println("Initializing..."); + Serial.flush(); + + BLEDevice::init(DEVICE_NAME); + pServer = BLEDevice::createServer(); + pServer->setCallbacks(new MyServerCallbacks()); + + init_service(); + init_beacon(); + + Serial.println("iBeacon + service defined and advertising!"); +} + +void loop() { + if (deviceConnected) { + Serial.printf("*** NOTIFY: %d ***\n", value); + pCharacteristic->setValue(&value, 1); + pCharacteristic->notify(); + value++; + } + delay(2000); +} diff --git a/libraries/BLE/library.properties b/libraries/BLE/library.properties new file mode 100644 index 0000000..a68a055 --- /dev/null +++ b/libraries/BLE/library.properties @@ -0,0 +1,10 @@ +name=BLE +version=3.3.7 +author=Neil Kolban +maintainer=lucasssvaz +sentence=BLE functions for ESP32 +paragraph=This library provides an implementation Bluetooth Low Energy support for the ESP32 using the Arduino platform. +category=Communication +url=https://github.com/espressif/arduino-esp32/tree/master/libraries/BLE +architectures=esp32 +includes=BLEDevice.h, BLEUtils.h, BLEScan.h, BLEAdvertisedDevice.h diff --git a/libraries/BLE/src/BLE2901.cpp b/libraries/BLE/src/BLE2901.cpp new file mode 100644 index 0000000..20535dd --- /dev/null +++ b/libraries/BLE/src/BLE2901.cpp @@ -0,0 +1,58 @@ +/* + BLE2901.h + + GATT Descriptor 0x2901 Characteristic User Description + + The value of this description is a user-readable string + describing the characteristic. + + The Characteristic User Description descriptor + provides a textual user description for a characteristic + value. + If the Writable Auxiliary bit of the Characteristics + Properties is set then this descriptor is written. Only one + User Description descriptor exists in a characteristic + definition. +*/ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes and definitions * + ***************************************************************************/ + +#include "BLE2901.h" + +#define BLE2901_UUID 0x2901 + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#define ESP_GATT_MAX_ATTR_LEN BLE_ATT_ATTR_MAX_LEN +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLE2901::BLE2901() : BLEDescriptor(BLEUUID((uint16_t)BLE2901_UUID)) {} + +/** + * @brief Set the Characteristic User Description + */ +void BLE2901::setDescription(const String &userDesc) { + if (userDesc.length() > ESP_GATT_MAX_ATTR_LEN) { + log_e("Size %d too large, must be no bigger than %d", userDesc.length(), ESP_GATT_MAX_ATTR_LEN); + return; + } + setValue(userDesc); +} + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLE2901.h b/libraries/BLE/src/BLE2901.h new file mode 100644 index 0000000..949cad0 --- /dev/null +++ b/libraries/BLE/src/BLE2901.h @@ -0,0 +1,48 @@ +/* + BLE2901.h + + GATT Descriptor 0x2901 Characteristic User Description + + The value of this description is a user-readable string + describing the characteristic. + + The Characteristic User Description descriptor + provides a textual user description for a characteristic + value. + If the Writable Auxiliary bit of the Characteristics + Properties is set then this descriptor is written. Only one + User Description descriptor exists in a characteristic + definition. +*/ + +#ifndef COMPONENTS_CPP_UTILS_BLE2901_H_ +#define COMPONENTS_CPP_UTILS_BLE2901_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEDescriptor.h" + +/** + * @brief GATT Descriptor 0x2901 Characteristic User Description + */ +class BLE2901 : public BLEDescriptor { +public: + /*************************************************************************** + * Common public functions * + ***************************************************************************/ + + BLE2901(); + void setDescription(const String &desc); +}; // BLE2901 + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLE2901_H_ */ diff --git a/libraries/BLE/src/BLE2902.cpp b/libraries/BLE/src/BLE2902.cpp new file mode 100644 index 0000000..eb9b6b5 --- /dev/null +++ b/libraries/BLE/src/BLE2902.cpp @@ -0,0 +1,252 @@ +/* + * BLE2902.cpp + * + * Created on: Jun 25, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +/* + * See also: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes and definitions * + ***************************************************************************/ + +#include "BLE2902.h" +#include "esp32-hal-log.h" + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +#define BLE2902_UUID 0x2902 +#define BLE_CCCD_NVS_NS "ble_cccd" +#define BLE_CCCD_KEY_PREFIX "c" + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLE2902::BLE2902() : BLEDescriptor(BLEUUID((uint16_t)BLE2902_UUID)) { +#if defined(CONFIG_BLUEDROID_ENABLED) + uint8_t data[2] = {0, 0}; + setValue(data, 2); +#endif +} + +/** + * @brief Get the notifications value. + * @return The notifications value. True if notifications are enabled and false if not. + */ +bool BLE2902::getNotifications() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return (getValue()[0] & (1 << 0)) != 0; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_pCharacteristic != nullptr) { + return (m_pCharacteristic->getProperties() & BLECharacteristic::PROPERTY_NOTIFY) != 0; + } else { + log_w("BLE2902::getNotifications() called on an uninitialized descriptor"); + return false; + } +#endif +} + +/** + * @brief Get the indications value. + * @return The indications value. True if indications are enabled and false if not. + */ +bool BLE2902::getIndications() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return (getValue()[0] & (1 << 1)) != 0; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_pCharacteristic != nullptr) { + return (m_pCharacteristic->getProperties() & BLECharacteristic::PROPERTY_INDICATE) != 0; + } else { + log_w("BLE2902::getIndications() called on an uninitialized descriptor"); + return false; + } +#endif +} + +/** + * @brief Set the indications flag. + * @param [in] flag The indications flag. + */ +void BLE2902::setIndications(bool flag) { +#if defined(CONFIG_BLUEDROID_ENABLED) + uint8_t *pValue = getValue(); + if (flag) { + pValue[0] |= 1 << 1; + } else { + pValue[0] &= ~(1 << 1); + } + setValue(pValue, 2); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_pCharacteristic != nullptr) { + m_pCharacteristic->setIndicateProperty(flag); + } else { + log_w("BLE2902::setIndications() called on an uninitialized descriptor"); + } +#endif +} + +/** + * @brief Set the notifications flag. + * @param [in] flag The notifications flag. + */ +void BLE2902::setNotifications(bool flag) { +#if defined(CONFIG_BLUEDROID_ENABLED) + uint8_t *pValue = getValue(); + if (flag) { + pValue[0] |= 1 << 0; + } else { + pValue[0] &= ~(1 << 0); + } + setValue(pValue, 2); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_pCharacteristic != nullptr) { + m_pCharacteristic->setNotifyProperty(flag); + } else { + log_w("BLE2902::setNotifications() called on an uninitialized descriptor"); + } +#endif +} + +/*************************************************************************** + * Bluedroid CCCD persistence * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Generate NVS key for CCCD persistence. + * Format: "c" + last 4 chars of MAC (no colons) + "_" + handle in hex + * Example: "c5AC2_002a" for address ending in :5A:C2 and handle 0x002a + * Max length: 1 (prefix) + 4 (addr) + 1 (_) + 4 (handle) + 1 (null) = 11 chars + */ +String BLE2902::getNvsKey(const BLEAddress &peerAddress, uint16_t charHandle) { + String addrStr = peerAddress.toString(); + // Get last 4 characters of address (without colons) - e.g., "5AC2" from "XX:XX:XX:XX:5A:C2" + String shortAddr = addrStr.substring(addrStr.length() - 5); + shortAddr.replace(":", ""); + + char key[24]; // Sized generously to avoid truncation warnings + snprintf(key, sizeof(key), "%s%s_%04x", BLE_CCCD_KEY_PREFIX, shortAddr.c_str(), charHandle); + return String(key); +} + +/** + * @brief Persist CCCD value to NVS for a bonded device. + */ +bool BLE2902::persistValue(const BLEAddress &peerAddress, uint16_t charHandle) { + Preferences prefs; + if (!prefs.begin(BLE_CCCD_NVS_NS, false)) { + log_e("Failed to open NVS namespace for CCCD persistence"); + return false; + } + + String key = getNvsKey(peerAddress, charHandle); + uint8_t *pValue = getValue(); + uint16_t cccdValue = pValue[0] | (pValue[1] << 8); + + size_t written = prefs.putUShort(key.c_str(), cccdValue); + prefs.end(); + + if (written == 0) { + log_e("Failed to persist CCCD value to NVS"); + return false; + } + + log_i("Persisted CCCD value 0x%04x for peer %s, handle 0x%04x (key: %s)", cccdValue, peerAddress.toString().c_str(), charHandle, key.c_str()); + return true; +} + +/** + * @brief Restore CCCD value from NVS for a bonded device. + */ +bool BLE2902::restoreValue(const BLEAddress &peerAddress, uint16_t charHandle) { + Preferences prefs; + if (!prefs.begin(BLE_CCCD_NVS_NS, true)) { // Read-only + log_d("No CCCD persistence namespace found (first boot?)"); + return false; + } + + String key = getNvsKey(peerAddress, charHandle); + + if (!prefs.isKey(key.c_str())) { + prefs.end(); + log_d("No persisted CCCD value for peer %s, handle 0x%04x", peerAddress.toString().c_str(), charHandle); + return false; + } + + uint16_t cccdValue = prefs.getUShort(key.c_str(), 0); + prefs.end(); + + // Set the value in the descriptor + uint8_t data[2] = {(uint8_t)(cccdValue & 0xFF), (uint8_t)((cccdValue >> 8) & 0xFF)}; + setValue(data, 2); + + log_i("Restored CCCD value 0x%04x for peer %s, handle 0x%04x (key: %s)", cccdValue, peerAddress.toString().c_str(), charHandle, key.c_str()); + return true; +} + +/** + * @brief Delete persisted CCCD value from NVS for a device. + */ +bool BLE2902::deletePersistedValue(const BLEAddress &peerAddress, uint16_t charHandle) { + Preferences prefs; + if (!prefs.begin(BLE_CCCD_NVS_NS, false)) { + return false; + } + + String key = getNvsKey(peerAddress, charHandle); + bool result = prefs.remove(key.c_str()); + prefs.end(); + + if (result) { + log_i("Deleted persisted CCCD value for peer %s, handle 0x%04x", peerAddress.toString().c_str(), charHandle); + } + return result; +} + +/** + * @brief Delete all persisted CCCD values from NVS. + */ +bool BLE2902::deleteAllPersistedValues() { + Preferences prefs; + if (!prefs.begin(BLE_CCCD_NVS_NS, false)) { + return false; + } + + bool result = prefs.clear(); + prefs.end(); + + if (result) { + log_i("Deleted all persisted CCCD values"); + } + return result; +} + +#endif /* CONFIG_BLUEDROID_ENABLED */ + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLE2902.h b/libraries/BLE/src/BLE2902.h new file mode 100644 index 0000000..b76dca2 --- /dev/null +++ b/libraries/BLE/src/BLE2902.h @@ -0,0 +1,106 @@ +/* + * BLE2902.h + * + * Created on: Jun 25, 2017 + * Author: kolban + * + * Modified on: Feb 28, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLE2902_H_ +#define COMPONENTS_CPP_UTILS_BLE2902_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEDescriptor.h" + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include "BLEAddress.h" +#endif + +/** + * @brief Descriptor for Client Characteristic Configuration. + * + * This is a convenience descriptor for the Client Characteristic Configuration which has a UUID of 0x2902. + * + * See also: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml + */ + +// Class declaration for Bluedroid +#if defined(CONFIG_BLUEDROID_ENABLED) +class BLE2902 : public BLEDescriptor { +#endif + +// Class declaration for NimBLE (deprecated) +#if defined(CONFIG_NIMBLE_ENABLED) + class [[deprecated("NimBLE does not support manually adding 2902 descriptors as they \ +are automatically added when the characteristic has notifications or indications enabled. \ +Get/Set the notifications/indications properties of the characteristic instead. \ +This class will be removed in a future version.")]] BLE2902 : public BLEDescriptor { +#endif + + public: + /*************************************************************************** + * Common public functions * + ***************************************************************************/ + + BLE2902(); + bool getNotifications(); + bool getIndications(); + void setNotifications(bool flag); + void setIndications(bool flag); + +#if defined(CONFIG_BLUEDROID_ENABLED) + /*************************************************************************** + * Bluedroid CCCD persistence * + ***************************************************************************/ + + /** + * @brief Persist CCCD value to NVS for a bonded device. + * @param [in] peerAddress The address of the bonded peer device. + * @param [in] charHandle The handle of the characteristic this CCCD belongs to. + * @return true if the value was successfully persisted, false otherwise. + */ + bool persistValue(const BLEAddress &peerAddress, uint16_t charHandle); + + /** + * @brief Restore CCCD value from NVS for a bonded device. + * @param [in] peerAddress The address of the bonded peer device. + * @param [in] charHandle The handle of the characteristic this CCCD belongs to. + * @return true if the value was successfully restored, false otherwise. + */ + bool restoreValue(const BLEAddress &peerAddress, uint16_t charHandle); + + /** + * @brief Delete persisted CCCD value from NVS for a device. + * @param [in] peerAddress The address of the peer device. + * @param [in] charHandle The handle of the characteristic this CCCD belongs to. + * @return true if the value was successfully deleted, false otherwise. + */ + static bool deletePersistedValue(const BLEAddress &peerAddress, uint16_t charHandle); + + /** + * @brief Delete all persisted CCCD values from NVS. + * @return true if all values were successfully deleted, false otherwise. + */ + static bool deleteAllPersistedValues(); + + private: + static String getNvsKey(const BLEAddress &peerAddress, uint16_t charHandle); +#endif + }; // BLE2902 + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLE2902_H_ */ diff --git a/libraries/BLE/src/BLE2904.cpp b/libraries/BLE/src/BLE2904.cpp new file mode 100644 index 0000000..2d3565a --- /dev/null +++ b/libraries/BLE/src/BLE2904.cpp @@ -0,0 +1,88 @@ +/* + * BLE2904.cpp + * + * Created on: Dec 23, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +/* + * See also: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes and definitions * + ***************************************************************************/ + +#include "BLE2904.h" + +#define BLE2904_UUID 0x2904 +#define BLE2904_DEFAULT_NAMESPACE 1 // 1 = Bluetooth SIG Assigned Numbers +#define BLE2904_DEFAULT_UNIT 0x2700 // 0x2700 = Unitless + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLE2904::BLE2904() : BLEDescriptor(BLEUUID((uint16_t)BLE2904_UUID)) { + m_data.m_format = 0; + m_data.m_exponent = 0; + m_data.m_namespace = BLE2904_DEFAULT_NAMESPACE; + m_data.m_unit = BLE2904_DEFAULT_UNIT; + m_data.m_description = 0; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +/** + * @brief Set the description. + */ +void BLE2904::setDescription(uint16_t description) { + m_data.m_description = description; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +/** + * @brief Set the exponent. + */ +void BLE2904::setExponent(int8_t exponent) { + m_data.m_exponent = exponent; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +/** + * @brief Set the format. + */ +void BLE2904::setFormat(uint8_t format) { + m_data.m_format = format; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +/** + * @brief Set the namespace. + */ +void BLE2904::setNamespace(uint8_t namespace_value) { + m_data.m_namespace = namespace_value; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +/** + * @brief Set the units for this value. It should be one of the encoded values defined here: + * https://www.bluetooth.com/specifications/assigned-numbers/units + * @param [in] unit The type of units of this characteristic as defined by assigned numbers. + */ +void BLE2904::setUnit(uint16_t unit) { + m_data.m_unit = unit; + setValue((uint8_t *)&m_data, sizeof(m_data)); +} + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLE2904.h b/libraries/BLE/src/BLE2904.h new file mode 100644 index 0000000..f0f2676 --- /dev/null +++ b/libraries/BLE/src/BLE2904.h @@ -0,0 +1,107 @@ +/* + * BLE2904.h + * + * Created on: Dec 23, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLE2904_H_ +#define COMPONENTS_CPP_UTILS_BLE2904_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEDescriptor.h" + +/*************************************************************************** + * Common types * + ***************************************************************************/ + +struct BLE2904_Data { + uint8_t m_format; + int8_t m_exponent; + uint16_t m_unit; // See https://www.bluetooth.com/specifications/assigned-numbers/units + uint8_t m_namespace; + uint16_t m_description; +} __attribute__((packed)); + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Descriptor for Characteristic Presentation Format. + * + * This is a convenience descriptor for the Characteristic Presentation Format which has a UUID of 0x2904. + * + * See also: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + */ +class BLE2904 : public BLEDescriptor { +public: + /*************************************************************************** + * Common public constants * + ***************************************************************************/ + + static const uint8_t FORMAT_BOOLEAN = 1; + static const uint8_t FORMAT_UINT2 = 2; + static const uint8_t FORMAT_UINT4 = 3; + static const uint8_t FORMAT_UINT8 = 4; + static const uint8_t FORMAT_UINT12 = 5; + static const uint8_t FORMAT_UINT16 = 6; + static const uint8_t FORMAT_UINT24 = 7; + static const uint8_t FORMAT_UINT32 = 8; + static const uint8_t FORMAT_UINT48 = 9; + static const uint8_t FORMAT_UINT64 = 10; + static const uint8_t FORMAT_UINT128 = 11; + static const uint8_t FORMAT_SINT8 = 12; + static const uint8_t FORMAT_SINT12 = 13; + static const uint8_t FORMAT_SINT16 = 14; + static const uint8_t FORMAT_SINT24 = 15; + static const uint8_t FORMAT_SINT32 = 16; + static const uint8_t FORMAT_SINT48 = 17; + static const uint8_t FORMAT_SINT64 = 18; + static const uint8_t FORMAT_SINT128 = 19; + static const uint8_t FORMAT_FLOAT32 = 20; + static const uint8_t FORMAT_FLOAT64 = 21; + static const uint8_t FORMAT_SFLOAT16 = 22; + static const uint8_t FORMAT_SFLOAT32 = 23; + static const uint8_t FORMAT_IEEE20601 = 24; + static const uint8_t FORMAT_UTF8 = 25; + static const uint8_t FORMAT_UTF16 = 26; + static const uint8_t FORMAT_OPAQUE = 27; + static const uint8_t FORMAT_MEDASN1 = 28; + + /*************************************************************************** + * Common public functions * + ***************************************************************************/ + + BLE2904(); + void setDescription(uint16_t); + void setExponent(int8_t exponent); + void setFormat(uint8_t format); + void setNamespace(uint8_t namespace_value); + void setUnit(uint16_t unit); + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLE2904_Data m_data; +}; // BLE2904 + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLE2904_H_ */ diff --git a/libraries/BLE/src/BLEAddress.cpp b/libraries/BLE/src/BLEAddress.cpp new file mode 100644 index 0000000..994d12b --- /dev/null +++ b/libraries/BLE/src/BLEAddress.cpp @@ -0,0 +1,235 @@ +/* + * BLEAddress.cpp + * + * Created on: Jul 2, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEAddress.h" +#include +#include +#include +#include +#include +#include + +#ifdef ARDUINO_ARCH_ESP32 +#include "esp32-hal-log.h" +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +/************************************************* + * NOTE: NimBLE address bytes are in INVERSE ORDER! + * We will accommodate that fact in these methods. +*************************************************/ +#include +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLEAddress::BLEAddress() { + memset(m_address, 0, ESP_BD_ADDR_LEN); + m_addrType = 0; +} + +/** + * @brief Determine if this address equals another. + * @param [in] otherAddress The other address to compare against. + * @return True if the addresses are equal. + */ +bool BLEAddress::equals(const BLEAddress &otherAddress) const { + return *this == otherAddress; +} + +bool BLEAddress::operator==(const BLEAddress &otherAddress) const { + if (m_addrType != otherAddress.m_addrType) { + return false; + } + return memcmp(otherAddress.m_address, m_address, ESP_BD_ADDR_LEN) == 0; +} + +bool BLEAddress::operator!=(const BLEAddress &otherAddress) const { + return !(*this == otherAddress); +} + +bool BLEAddress::operator<(const BLEAddress &otherAddress) const { + return memcmp(m_address, otherAddress.m_address, ESP_BD_ADDR_LEN) < 0; +} + +bool BLEAddress::operator<=(const BLEAddress &otherAddress) const { + return !(*this > otherAddress); +} + +bool BLEAddress::operator>=(const BLEAddress &otherAddress) const { + return !(*this < otherAddress); +} + +bool BLEAddress::operator>(const BLEAddress &otherAddress) const { + return memcmp(m_address, otherAddress.m_address, ESP_BD_ADDR_LEN) > 0; +} + +/** + * @brief Return the native representation of the address. + * @return The native representation of the address. + */ +uint8_t *BLEAddress::getNative() { + return m_address; +} + +/** + * @brief Return the address type. + * @return The address type. + */ +uint8_t BLEAddress::getType() const { + return m_addrType; +} + +/** + * @brief Set the address type. + * @param [in] type The address type. + */ +void BLEAddress::setType(uint8_t type) { + m_addrType = type; +} + +/** + * @brief Convert a BLE address to a string. + * + * A string representation of an address is in the format: + * + * ``` + * xx:xx:xx:xx:xx:xx + * ``` + * + * @return The string representation of the address. + */ +String BLEAddress::toString() const { + constexpr size_t size = 18; + char res[size]; + +#if defined(CONFIG_BLUEDROID_ENABLED) + snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[5], m_address[4], m_address[3], m_address[2], m_address[1], m_address[0]); +#endif + + String ret(res); + return ret; +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Create an address from the native ESP32 representation. + * @param [in] address The native representation. + * @param [in] type The address type. + */ +BLEAddress::BLEAddress(esp_bd_addr_t address, uint8_t type) { + memcpy(m_address, address, ESP_BD_ADDR_LEN); + m_addrType = type; +} + +/** + * @brief Create an address from a hex string + * + * A hex string is of the format: + * ``` + * 00:00:00:00:00:00 + * ``` + * which is 17 characters in length. + * + * @param [in] stringAddress The hex representation of the address. + * @param [in] type The address type. + */ +BLEAddress::BLEAddress(const String &stringAddress, uint8_t type) { + if (stringAddress.length() != 17) { + return; + } + + int data[6]; + m_addrType = type; + sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[0], &data[1], &data[2], &data[3], &data[4], &data[5]); + + for (size_t index = 0; index < sizeof(m_address); index++) { + m_address[index] = (uint8_t)data[index]; + } +} + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +/************************************************* + * NOTE: NimBLE address bytes are in INVERSE ORDER! + * We will accommodate that fact in these methods. +*************************************************/ + +BLEAddress::BLEAddress(uint8_t address[ESP_BD_ADDR_LEN], uint8_t type) { + std::reverse_copy(address, address + sizeof(m_address), m_address); + m_addrType = type; +} + +BLEAddress::BLEAddress(ble_addr_t address) { + memcpy(m_address, address.val, ESP_BD_ADDR_LEN); + m_addrType = address.type; +} + +/** + * @brief Create an address from a hex string + * + * A hex string is of the format: + * ``` + * 00:00:00:00:00:00 + * ``` + * which is 17 characters in length. + * + * @param [in] stringAddress The hex representation of the address. + * @param [in] type The address type. + */ +BLEAddress::BLEAddress(const String &stringAddress, uint8_t type) { + if (stringAddress.length() != 17) { + return; + } + + int data[6]; + m_addrType = type; + // NimBLE addresses are in INVERSE ORDER! + sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[5], &data[4], &data[3], &data[2], &data[1], &data[0]); + + for (size_t index = 0; index < sizeof(m_address); index++) { + m_address[index] = (uint8_t)data[index]; + } +} + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEAddress.h b/libraries/BLE/src/BLEAddress.h new file mode 100644 index 0000000..0b65e34 --- /dev/null +++ b/libraries/BLE/src/BLEAddress.h @@ -0,0 +1,110 @@ +/* + * BLEAddress.h + * + * Created on: Jul 2, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEADDRESS_H_ +#define COMPONENTS_CPP_UTILS_BLEADDRESS_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "WString.h" +#if SOC_BLE_SUPPORTED +#include +#endif +#include + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#define ESP_BD_ADDR_LEN BLE_DEV_ADDR_LEN +#endif + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN]; +#endif + +/** + * @brief A %BLE device address. + * + * Every %BLE device has a unique address which can be used to identify it and form connections. + */ +class BLEAddress { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEAddress(); + bool equals(const BLEAddress &otherAddress) const; + bool operator==(const BLEAddress &otherAddress) const; + bool operator!=(const BLEAddress &otherAddress) const; + bool operator<(const BLEAddress &otherAddress) const; + bool operator<=(const BLEAddress &otherAddress) const; + bool operator>(const BLEAddress &otherAddress) const; + bool operator>=(const BLEAddress &otherAddress) const; + uint8_t *getNative(); + uint8_t getType() const; + void setType(uint8_t type); + String toString() const; + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + BLEAddress(esp_bd_addr_t address, uint8_t type = 0); + BLEAddress(const String &stringAddress, uint8_t type = 0); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + BLEAddress(ble_addr_t address); + BLEAddress(const String &stringAddress, uint8_t type = BLE_ADDR_PUBLIC); + BLEAddress(uint8_t address[ESP_BD_ADDR_LEN], uint8_t type = BLE_ADDR_PUBLIC); +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + uint8_t m_address[ESP_BD_ADDR_LEN]; + uint8_t m_addrType; +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEADDRESS_H_ */ diff --git a/libraries/BLE/src/BLEAdvertisedDevice.cpp b/libraries/BLE/src/BLEAdvertisedDevice.cpp new file mode 100644 index 0000000..c09bb7d --- /dev/null +++ b/libraries/BLE/src/BLEAdvertisedDevice.cpp @@ -0,0 +1,805 @@ +/* + * BLEAdvertisedDevice.cpp + * + * During the scanning procedure, we will be finding advertised BLE devices. This class + * models a found device. + * + * See also: + * https://www.bluetooth.com/specifications/assigned-numbers/generic-access-profile + * + * Created on: Jul 3, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLEAdvertisedDevice.h" +#include "BLEUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLEAdvertisedDevice::BLEAdvertisedDevice() { + m_adFlag = 0; + m_appearance = 0; + m_deviceType = 0; + m_manufacturerData = ""; + m_name = ""; + m_rssi = -9999; + m_serviceUUIDs = {}; + m_serviceData = {}; + m_serviceDataUUIDs = {}; + m_txPower = 0; + m_pScan = nullptr; + m_advType = 0; + m_payload = nullptr; + m_payloadLength = 0; + +#if defined(CONFIG_NIMBLE_ENABLED) + m_callbackSent = false; +#endif + + m_haveAppearance = false; + m_haveManufacturerData = false; + m_haveName = false; + m_haveRSSI = false; + m_haveTXPower = false; + m_isLegacyAdv = true; +} // BLEAdvertisedDevice + +BLEAdvertisedDevice::~BLEAdvertisedDevice() { + if (m_payload != nullptr) { + free(m_payload); + m_payload = nullptr; + m_payloadLength = 0; + } +} // ~BLEAdvertisedDevice + +BLEAdvertisedDevice::BLEAdvertisedDevice(const BLEAdvertisedDevice &other) { + m_adFlag = other.m_adFlag; + m_appearance = other.m_appearance; + m_deviceType = other.m_deviceType; + m_manufacturerData = other.m_manufacturerData; + m_name = other.m_name; + m_rssi = other.m_rssi; + m_serviceUUIDs = other.m_serviceUUIDs; + m_serviceData = other.m_serviceData; + m_serviceDataUUIDs = other.m_serviceDataUUIDs; + m_txPower = other.m_txPower; + m_pScan = other.m_pScan; + m_advType = other.m_advType; + m_address = other.m_address; + +#if defined(CONFIG_NIMBLE_ENABLED) + m_callbackSent = other.m_callbackSent; +#endif + + m_haveAppearance = other.m_haveAppearance; + m_haveManufacturerData = other.m_haveManufacturerData; + m_haveName = other.m_haveName; + m_haveRSSI = other.m_haveRSSI; + m_haveTXPower = other.m_haveTXPower; + m_isLegacyAdv = other.m_isLegacyAdv; + + // Deep copy the payload + m_payloadLength = other.m_payloadLength; + if (other.m_payload != nullptr && other.m_payloadLength > 0) { + m_payload = (uint8_t *)malloc(m_payloadLength); + if (m_payload != nullptr) { + memcpy(m_payload, other.m_payload, m_payloadLength); + } else { + log_e("Failed to allocate %zu bytes for payload in copy constructor", m_payloadLength); + m_payloadLength = 0; + } + } else { + m_payload = nullptr; + m_payloadLength = 0; + } +} // BLEAdvertisedDevice copy constructor + +BLEAdvertisedDevice &BLEAdvertisedDevice::operator=(const BLEAdvertisedDevice &other) { + if (this == &other) { + return *this; + } + + m_adFlag = other.m_adFlag; + m_appearance = other.m_appearance; + m_deviceType = other.m_deviceType; + m_manufacturerData = other.m_manufacturerData; + m_name = other.m_name; + m_rssi = other.m_rssi; + m_serviceUUIDs = other.m_serviceUUIDs; + m_serviceData = other.m_serviceData; + m_serviceDataUUIDs = other.m_serviceDataUUIDs; + m_txPower = other.m_txPower; + m_pScan = other.m_pScan; + m_advType = other.m_advType; + m_address = other.m_address; + +#if defined(CONFIG_NIMBLE_ENABLED) + m_callbackSent = other.m_callbackSent; +#endif + + m_haveAppearance = other.m_haveAppearance; + m_haveManufacturerData = other.m_haveManufacturerData; + m_haveName = other.m_haveName; + m_haveRSSI = other.m_haveRSSI; + m_haveTXPower = other.m_haveTXPower; + m_isLegacyAdv = other.m_isLegacyAdv; + + // Free existing payload and deep copy the new one + if (m_payload != nullptr) { + free(m_payload); + } + + m_payloadLength = other.m_payloadLength; + if (other.m_payload != nullptr && other.m_payloadLength > 0) { + m_payload = (uint8_t *)malloc(m_payloadLength); + if (m_payload != nullptr) { + memcpy(m_payload, other.m_payload, m_payloadLength); + } else { + log_e("Failed to allocate %zu bytes for payload in assignment operator", m_payloadLength); + m_payloadLength = 0; + } + } else { + m_payload = nullptr; + m_payloadLength = 0; + } + + return *this; +} // BLEAdvertisedDevice assignment operator + +bool BLEAdvertisedDevice::isLegacyAdvertisement() { + return m_isLegacyAdv; +} + +bool BLEAdvertisedDevice::isScannable() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return isLegacyAdvertisement() && (m_advType == ESP_BLE_EVT_CONN_ADV || m_advType == ESP_BLE_EVT_DISC_ADV); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + return isLegacyAdvertisement() && (m_advType == BLE_HCI_ADV_TYPE_ADV_IND || m_advType == BLE_HCI_ADV_TYPE_ADV_SCAN_IND); +#endif +} + +bool BLEAdvertisedDevice::isConnectable() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return m_advType == ESP_BLE_EVT_CONN_ADV || m_advType == ESP_BLE_EVT_CONN_DIR_ADV; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_isLegacyAdv) { + return m_advType == BLE_HCI_ADV_RPT_EVTYPE_ADV_IND || m_advType == BLE_HCI_ADV_RPT_EVTYPE_DIR_IND; + } + return (m_advType & BLE_HCI_ADV_CONN_MASK) || (m_advType & BLE_HCI_ADV_DIRECT_MASK); +#endif +} + +/** + * @brief Get the address. + * + * Every %BLE device exposes an address that is used to identify it and subsequently connect to it. + * Call this function to obtain the address of the advertised device. + * + * @return The address of the advertised device. + */ +BLEAddress BLEAdvertisedDevice::getAddress() { + return m_address; +} // getAddress + +/** + * @brief Get the appearance. + * + * A %BLE device can declare its own appearance. The appearance is how it would like to be shown to an end user + * typically in the form of an icon. + * + * @return The appearance of the advertised device. + */ +uint16_t BLEAdvertisedDevice::getAppearance() { + return m_appearance; +} // getAppearance + +/** + * @brief Get the manufacturer data. + * @return The manufacturer data of the advertised device. + */ +String BLEAdvertisedDevice::getManufacturerData() { + return m_manufacturerData; +} // getManufacturerData + +/** + * @brief Get the name. + * @return The name of the advertised device. + */ +String BLEAdvertisedDevice::getName() { + return m_name; +} // getName + +/** + * @brief Get the RSSI. + * @return The RSSI of the advertised device. + */ +int BLEAdvertisedDevice::getRSSI() { + return m_rssi; +} // getRSSI + +/** + * @brief Get the scan object that created this advertisement. + * @return The scan object. + */ +BLEScan *BLEAdvertisedDevice::getScan() { + return m_pScan; +} // getScan + +/** + * @brief Get the number of service data. + * @return Number of service data discovered. + */ +int BLEAdvertisedDevice::getServiceDataCount() { + return m_serviceData.size(); +} //getServiceDataCount + +/** + * @brief Get the service data. + * @return The ServiceData of the advertised device. + */ +String BLEAdvertisedDevice::getServiceData() { + return m_serviceData.empty() ? String() : m_serviceData.front(); +} //getServiceData + +/** + * @brief Get the service data. + * @return The ServiceData of the advertised device. + */ +String BLEAdvertisedDevice::getServiceData(int i) { + return m_serviceData[i]; +} //getServiceData + +/** + * @brief Get the number of service data UUIDs. + * @return Number of service data UUIDs discovered. + */ +int BLEAdvertisedDevice::getServiceDataUUIDCount() { + return m_serviceDataUUIDs.size(); +} //getServiceDataUUIDCount + +/** + * @brief Get the service data UUID. + * @return The service data UUID. + */ +BLEUUID BLEAdvertisedDevice::getServiceDataUUID() { + return m_serviceDataUUIDs.empty() ? BLEUUID() : m_serviceDataUUIDs.front(); +} // getServiceDataUUID + +/** + * @brief Get the service data UUID. + * @return The service data UUID. + */ +BLEUUID BLEAdvertisedDevice::getServiceDataUUID(int i) { + return m_serviceDataUUIDs[i]; +} // getServiceDataUUID + +/** + * @brief Get the number of service UUIDs. + * @return Number of service UUIDs discovered. + */ +int BLEAdvertisedDevice::getServiceUUIDCount() { + return m_serviceUUIDs.size(); +} //getServiceUUIDCount + +/** + * @brief Get the Service UUID. + * @return The Service UUID of the advertised device. + */ +BLEUUID BLEAdvertisedDevice::getServiceUUID() { + return m_serviceUUIDs.empty() ? BLEUUID() : m_serviceUUIDs.front(); +} // getServiceUUID + +/** + * @brief Get the Service UUID. + * @return The Service UUID of the advertised device. + */ +BLEUUID BLEAdvertisedDevice::getServiceUUID(int i) { + return m_serviceUUIDs[i]; +} // getServiceUUID + +/** + * @brief Check advertised serviced for existence required UUID + * @return Return true if service is advertised + */ +bool BLEAdvertisedDevice::isAdvertisingService(BLEUUID uuid) { + for (int i = 0; i < getServiceUUIDCount(); i++) { + if (m_serviceUUIDs[i].equals(uuid)) { + return true; + } + } + return false; +} + +/** + * @brief Get the TX Power. + * @return The TX Power of the advertised device. + */ +int8_t BLEAdvertisedDevice::getTXPower() { + return m_txPower; +} // getTXPower + +/** + * @brief Does this advertisement have an appearance value? + * @return True if there is an appearance value present. + */ +bool BLEAdvertisedDevice::haveAppearance() { + return m_haveAppearance; +} // haveAppearance + +/** + * @brief Does this advertisement have manufacturer data? + * @return True if there is manufacturer data present. + */ +bool BLEAdvertisedDevice::haveManufacturerData() { + return m_haveManufacturerData; +} // haveManufacturerData + +/** + * @brief Does this advertisement have a name value? + * @return True if there is a name value present. + */ +bool BLEAdvertisedDevice::haveName() { + return m_haveName; +} // haveName + +/** + * @brief Does this advertisement have a signal strength value? + * @return True if there is a signal strength value present. + */ +bool BLEAdvertisedDevice::haveRSSI() { + return m_haveRSSI; +} // haveRSSI + +/** + * @brief Does this advertisement have a service data value? + * @return True if there is a service data value present. + */ +bool BLEAdvertisedDevice::haveServiceData() { + return !m_serviceData.empty(); +} // haveServiceData + +/** + * @brief Does this advertisement have a service UUID value? + * @return True if there is a service UUID value present. + */ +bool BLEAdvertisedDevice::haveServiceUUID() { + return !m_serviceUUIDs.empty(); +} // haveServiceUUID + +/** + * @brief Does this advertisement have a transmission power value? + * @return True if there is a transmission power value present. + */ +bool BLEAdvertisedDevice::haveTXPower() { + return m_haveTXPower; +} // haveTXPower + +/** + * @brief Parse the advertising pay load. + * + * The pay load is a buffer of bytes that is either 31 bytes long or terminated by + * a 0 length value. Each entry in the buffer has the format: + * [length][type][data...] + * + * The length does not include itself but does include everything after it until the next record. A record + * with a length value of 0 indicates a terminator. + * + * https://www.bluetooth.com/specifications/assigned-numbers/generic-access-profile + */ +void BLEAdvertisedDevice::parseAdvertisement(uint8_t *payload, size_t total_len) { + uint8_t length; + uint8_t ad_type; + uint8_t sizeConsumed = 0; + bool finished = false; + + // Store/append raw payload data for later retrieval + // This handles both ADV and Scan Response packets by merging them + if (m_payload != nullptr && m_payloadLength > 0) { + // Append new payload data (scan response) to existing (advertisement) + uint8_t *new_payload = (uint8_t *)realloc(m_payload, m_payloadLength + total_len); + if (new_payload != nullptr) { + memcpy(new_payload + m_payloadLength, payload, total_len); + m_payload = new_payload; + m_payloadLength += total_len; + } else { + log_e("Failed to reallocate %zu bytes for payload (append)", m_payloadLength + total_len); + } + } else { + // First payload - make a copy since the original buffer may be reused + m_payload = (uint8_t *)malloc(total_len); + if (m_payload != nullptr) { + memcpy(m_payload, payload, total_len); + m_payloadLength = total_len; + } else { + log_e("Failed to allocate %zu bytes for payload", total_len); + m_payloadLength = 0; + } + } + + while (!finished) { + length = *payload; // Retrieve the length of the record. + payload++; // Skip to type + sizeConsumed += 1 + length; // increase the size consumed. + + if (length != 0) { // A length of 0 indicates that we have reached the end. + ad_type = *payload; + payload++; + length--; + + char *pHex = BLEUtils::buildHexData(nullptr, payload, length); + log_d("Type: 0x%.2x (%s), length: %d, data: %s", ad_type, BLEUtils::advDataTypeToString(ad_type), length, pHex); + free(pHex); + + switch (ad_type) { + case ESP_BLE_AD_TYPE_NAME_CMPL: // 0x09 + { // Adv Data Type: ESP_BLE_AD_TYPE_NAME_CMPL + setName(String(reinterpret_cast(payload), length)); + break; + } // 0x09 + + case ESP_BLE_AD_TYPE_TX_PWR: // 0x0A + { // Adv Data Type: ESP_BLE_AD_TYPE_TX_PWR + setTXPower(*payload); + break; + } // 0x0A + + case ESP_BLE_AD_TYPE_APPEARANCE: // 0x19 + { // Adv Data Type: ESP_BLE_AD_TYPE_APPEARANCE + setAppearance(*reinterpret_cast(payload)); + break; + } // 0x19 + + case ESP_BLE_AD_TYPE_FLAG: // 0x01 + { // Adv Data Type: ESP_BLE_AD_TYPE_FLAG + setAdFlag(*payload); + break; + } // 0x01 + + case ESP_BLE_AD_TYPE_16SRV_PART: // 0x02 + case ESP_BLE_AD_TYPE_16SRV_CMPL: // 0x03 + { // Adv Data Type: ESP_BLE_AD_TYPE_16SRV_PART/CMPL + for (int var = 0; var < length / 2; ++var) { + setServiceUUID(BLEUUID(*reinterpret_cast(payload + var * 2))); + } + break; + } // 0x02, 0x03 + + case ESP_BLE_AD_TYPE_32SRV_PART: // 0x04 + case ESP_BLE_AD_TYPE_32SRV_CMPL: // 0x05 + { // Adv Data Type: ESP_BLE_AD_TYPE_32SRV_PART/CMPL + for (int var = 0; var < length / 4; ++var) { + setServiceUUID(BLEUUID(*reinterpret_cast(payload + var * 4))); + } + break; + } // 0x04, 0x05 + + case ESP_BLE_AD_TYPE_128SRV_CMPL: // 0x07 + { // Adv Data Type: ESP_BLE_AD_TYPE_128SRV_CMPL + setServiceUUID(BLEUUID(payload, 16, false)); + break; + } // 0x07 + + case ESP_BLE_AD_TYPE_128SRV_PART: // 0x06 + { // Adv Data Type: ESP_BLE_AD_TYPE_128SRV_PART + setServiceUUID(BLEUUID(payload, 16, false)); + break; + } // 0x06 + + // See CSS Part A 1.4 Manufacturer Specific Data + case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE: // 0xFF + { + setManufacturerData(String(reinterpret_cast(payload), length)); + break; + } // 0xFF + + case ESP_BLE_AD_TYPE_SERVICE_DATA: // 0x16 + { // Adv Data Type: ESP_BLE_AD_TYPE_SERVICE_DATA - 2 byte UUID + if (length < 2) { + log_e("Length too small for SERVICE_DATA"); + break; + } + uint16_t uuid = *(uint16_t *)payload; + setServiceDataUUID(BLEUUID(uuid)); + if (length > 2) { + setServiceData(String(reinterpret_cast(payload + 2), length - 2)); + } + break; + } // 0x16 + + case ESP_BLE_AD_TYPE_32SERVICE_DATA: // 0x20 + { // Adv Data Type: ESP_BLE_AD_TYPE_32SERVICE_DATA - 4 byte UUID + if (length < 4) { + log_e("Length too small for 32SERVICE_DATA"); + break; + } + uint32_t uuid = *(uint32_t *)payload; + setServiceDataUUID(BLEUUID(uuid)); + if (length > 4) { + setServiceData(String(reinterpret_cast(payload + 4), length - 4)); + } + break; + } // 0x20 + + case ESP_BLE_AD_TYPE_128SERVICE_DATA: // 0x21 + { // Adv Data Type: ESP_BLE_AD_TYPE_128SERVICE_DATA - 16 byte UUID + if (length < 16) { + log_e("Length too small for 128SERVICE_DATA"); + break; + } + + setServiceDataUUID(BLEUUID(payload, (size_t)16, false)); + if (length > 16) { + setServiceData(String(reinterpret_cast(payload + 16), length - 16)); + } + break; + } // 0x21 + + default: + { + log_d("Unhandled type: adType: %d - 0x%.2x", ad_type, ad_type); + break; + } // default + } // switch + payload += length; + } // Length <> 0 + + if (sizeConsumed >= total_len) { + finished = true; + } + + } // !finished +} // parseAdvertisement + +/** + * @brief Set the advertising payload. + * @param [in] payload The payload of the advertised device. + * @param [in] total_len The length of payload + * @param [in] append If true, append to existing payload (for scan response merging) + */ +void BLEAdvertisedDevice::setPayload(uint8_t *payload, size_t total_len, bool append) { + if (total_len == 0 || payload == nullptr) { + return; + } + + if (append && m_payload != nullptr && m_payloadLength > 0) { + // Append scan response data to existing advertisement data + uint8_t *new_payload = (uint8_t *)realloc(m_payload, m_payloadLength + total_len); + if (new_payload == nullptr) { + log_e("Failed to reallocate %zu bytes for payload buffer", m_payloadLength + total_len); + return; + } + memcpy(new_payload + m_payloadLength, payload, total_len); + m_payload = new_payload; + m_payloadLength += total_len; + } else { + // First payload or replacing existing - make a copy + if (m_payload != nullptr && m_payloadLength > 0) { + free(m_payload); + } + m_payload = (uint8_t *)malloc(total_len); + if (m_payload == nullptr) { + log_e("Failed to allocate %zu bytes for payload buffer", total_len); + m_payloadLength = 0; + return; + } + memcpy(m_payload, payload, total_len); + m_payloadLength = total_len; + } +} // setPayload + +/** + * @brief Set the address of the advertised device. + * @param [in] address The address of the advertised device. + */ +void BLEAdvertisedDevice::setAddress(BLEAddress address) { + m_address = address; +} // setAddress + +/** + * @brief Set the adFlag for this device. + * @param [in] The discovered adFlag. + */ +void BLEAdvertisedDevice::setAdFlag(uint8_t adFlag) { + m_adFlag = adFlag; +} // setAdFlag + +/** + * @brief Set the appearance for this device. + * @param [in] The discovered appearance. + */ +void BLEAdvertisedDevice::setAppearance(uint16_t appearance) { + m_appearance = appearance; + m_haveAppearance = true; + log_d("- appearance: %d", m_appearance); +} // setAppearance + +/** + * @brief Set the manufacturer data for this device. + * @param [in] The discovered manufacturer data. + */ +void BLEAdvertisedDevice::setManufacturerData(String manufacturerData) { + m_manufacturerData = manufacturerData; + m_haveManufacturerData = true; + char *pHex = BLEUtils::buildHexData(nullptr, (uint8_t *)m_manufacturerData.c_str(), (uint8_t)m_manufacturerData.length()); + log_d("- manufacturer data: %s", pHex); + free(pHex); +} // setManufacturerData + +/** + * @brief Set the name for this device. + * @param [in] name The discovered name. + */ +void BLEAdvertisedDevice::setName(String name) { + m_name = name; + m_haveName = true; + log_d("- setName(): name: %s", m_name.c_str()); +} // setName + +/** + * @brief Set the RSSI for this device. + * @param [in] rssi The discovered RSSI. + */ +void BLEAdvertisedDevice::setRSSI(int rssi) { + m_rssi = rssi; + m_haveRSSI = true; + log_d("- setRSSI(): rssi: %d", m_rssi); +} // setRSSI + +/** + * @brief Set the Scan that created this advertised device. + * @param pScan The Scan that created this advertised device. + */ +void BLEAdvertisedDevice::setScan(BLEScan *pScan) { + m_pScan = pScan; +} // setScan + +/** + * @brief Set the Service UUID for this device. + * @param [in] serviceUUID The discovered serviceUUID + */ +void BLEAdvertisedDevice::setServiceUUID(const char *serviceUUID) { + return setServiceUUID(BLEUUID(serviceUUID)); +} // setServiceUUID + +/** + * @brief Set the Service UUID for this device. + * @param [in] serviceUUID The discovered serviceUUID + */ +void BLEAdvertisedDevice::setServiceUUID(BLEUUID serviceUUID) { + m_serviceUUIDs.push_back(serviceUUID); + log_d("- addServiceUUID(): serviceUUID: %s", serviceUUID.toString().c_str()); +} // setServiceUUID + +/** + * @brief Set the ServiceData value. + * @param [in] data ServiceData value. + */ +void BLEAdvertisedDevice::setServiceData(String serviceData) { + m_serviceData.push_back(serviceData); // Save the service data that we received. +} //setServiceData + +/** + * @brief Set the ServiceDataUUID value. + * @param [in] data ServiceDataUUID value. + */ +void BLEAdvertisedDevice::setServiceDataUUID(BLEUUID uuid) { + m_serviceDataUUIDs.push_back(uuid); + log_d("- addServiceDataUUID(): serviceDataUUID: %s", uuid.toString().c_str()); +} // setServiceDataUUID + +/** + * @brief Set the power level for this device. + * @param [in] txPower The discovered power level. + */ +void BLEAdvertisedDevice::setTXPower(int8_t txPower) { + m_txPower = txPower; + m_haveTXPower = true; + log_d("- txPower: %d", m_txPower); +} // setTXPower + +/** + * @brief Create a string representation of this device. + * @return A string representation of this device. + */ +String BLEAdvertisedDevice::toString() { + String res = "Name: " + getName() + ", Address: " + getAddress().toString(); + if (haveAppearance()) { + char val[6]; + snprintf(val, sizeof(val), "%d", getAppearance()); + res += ", appearance: "; + res += val; + } + if (haveManufacturerData()) { + char *pHex = BLEUtils::buildHexData(nullptr, (uint8_t *)getManufacturerData().c_str(), getManufacturerData().length()); + res += ", manufacturer data: "; + res += pHex; + free(pHex); + } + if (haveServiceUUID()) { + for (int i = 0; i < getServiceUUIDCount(); i++) { + res += ", serviceUUID: " + getServiceUUID(i).toString(); + } + } + if (haveTXPower()) { + char val[6]; + snprintf(val, sizeof(val), "%d", getTXPower()); + res += ", txPower: "; + res += val; + } + if (haveRSSI()) { + char val[5]; + snprintf(val, sizeof(val), "%i", getRSSI()); + res += ", rssi: "; + res += val; + } + if (haveServiceData()) { + for (int i = 0; i < getServiceDataCount(); i++) { + res += ", serviceData: " + getServiceData(i); + } + } + return res; +} // toString + +uint8_t *BLEAdvertisedDevice::getPayload() { + return m_payload; +} + +uint8_t BLEAdvertisedDevice::getAddressType() { + return m_address.getType(); +} + +ble_frame_type_t BLEAdvertisedDevice::getFrameType() { + for (int i = 0; i < m_payloadLength; ++i) { + log_d("check [%d]=0x%02X", i, m_payload[i]); + if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x00) { + return BLE_EDDYSTONE_UUID_FRAME; + } + if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x10) { + return BLE_EDDYSTONE_URL_FRAME; + } + if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x20) { + return BLE_EDDYSTONE_TLM_FRAME; + } + } + return BLE_UNKNOWN_FRAME; +} + +void BLEAdvertisedDevice::setAddressType(uint8_t type) { + m_address.setType(type); +} + +size_t BLEAdvertisedDevice::getPayloadLength() { + return m_payloadLength; +} + +void BLEAdvertisedDevice::setAdvType(uint8_t type) { + m_advType = type; +} + +uint8_t BLEAdvertisedDevice::getAdvType() { + return m_advType; +} + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEAdvertisedDevice.h b/libraries/BLE/src/BLEAdvertisedDevice.h new file mode 100644 index 0000000..60f224f --- /dev/null +++ b/libraries/BLE/src/BLEAdvertisedDevice.h @@ -0,0 +1,237 @@ +/* + * BLEAdvertisedDevice.h + * + * Created on: Jul 3, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_ +#define COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLEAddress.h" +#include "BLEScan.h" +#include "BLEUUID.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#endif + +/*************************************************************************** + * Common types * + ***************************************************************************/ + +typedef enum { + BLE_UNKNOWN_FRAME, + BLE_EDDYSTONE_UUID_FRAME, + BLE_EDDYSTONE_URL_FRAME, + BLE_EDDYSTONE_TLM_FRAME, + BLE_FRAME_MAX +} ble_frame_type_t; + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEScan; + +/** + * @brief A representation of a %BLE advertised device found by a scan. + * + * When we perform a %BLE scan, the result will be a set of devices that are advertising. This + * class provides a model of a detected device. + */ +class BLEAdvertisedDevice { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEAdvertisedDevice(); + ~BLEAdvertisedDevice(); + BLEAdvertisedDevice(const BLEAdvertisedDevice &other); + BLEAdvertisedDevice &operator=(const BLEAdvertisedDevice &other); + BLEAddress getAddress(); + uint16_t getAppearance(); + String getManufacturerData(); + String getName(); + int getRSSI(); + BLEScan *getScan(); + String getServiceData(); + String getServiceData(int i); + BLEUUID getServiceDataUUID(); + BLEUUID getServiceDataUUID(int i); + BLEUUID getServiceUUID(); + BLEUUID getServiceUUID(int i); + int getServiceDataCount(); + int getServiceDataUUIDCount(); + int getServiceUUIDCount(); + int8_t getTXPower(); + uint8_t *getPayload(); + size_t getPayloadLength(); + uint8_t getAddressType(); + ble_frame_type_t getFrameType(); + void setAddressType(uint8_t type); + void setAdvType(uint8_t type); + uint8_t getAdvType(); + + bool isLegacyAdvertisement(); + bool isScannable(); + bool isConnectable(); + bool isAdvertisingService(BLEUUID uuid); + bool haveAppearance(); + bool haveManufacturerData(); + bool haveName(); + bool haveRSSI(); + bool haveServiceData(); + bool haveServiceUUID(); + bool haveTXPower(); + + String toString(); + +private: + friend class BLEScan; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + bool m_haveAppearance; + bool m_haveManufacturerData; + bool m_haveName; + bool m_haveRSSI; + bool m_haveTXPower; + BLEAddress m_address = BLEAddress((uint8_t *)"\0\0\0\0\0\0"); + uint8_t m_adFlag; + uint16_t m_appearance; + int m_deviceType; + String m_manufacturerData; + String m_name; + BLEScan *m_pScan; + int m_rssi; + std::vector m_serviceUUIDs; + int8_t m_txPower; + std::vector m_serviceData; + std::vector m_serviceDataUUIDs; + uint8_t *m_payload; + size_t m_payloadLength = 0; + uint8_t m_advType; + bool m_isLegacyAdv; + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + bool m_callbackSent; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void parseAdvertisement(uint8_t *payload, size_t total_len = 62); + void setPayload(uint8_t *payload, size_t total_len = 62, bool append = false); + void setAddress(BLEAddress address); + void setAdFlag(uint8_t adFlag); + void setAdvertizementResult(uint8_t *payload); + void setAppearance(uint16_t appearance); + void setManufacturerData(String manufacturerData); + void setName(String name); + void setRSSI(int rssi); + void setScan(BLEScan *pScan); + void setServiceData(String data); + void setServiceDataUUID(BLEUUID uuid); + void setServiceUUID(const char *serviceUUID); + void setServiceUUID(BLEUUID serviceUUID); + void setTXPower(int8_t txPower); +}; + +/** + * @brief A callback handler for callbacks associated device scanning. + * + * When we are performing a scan as a %BLE client, we may wish to know when a new device that is advertising + * has been found. This class can be sub-classed and registered such that when a scan is performed and + * a new advertised device has been found, we will be called back to be notified. + */ +class BLEAdvertisedDeviceCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEAdvertisedDeviceCallbacks() {} + /** + * @brief Called when a new scan result is detected. + * + * As we are scanning, we will find new devices. When found, this call back is invoked with a reference to the + * device that was found. During any individual scan, a device will only be detected one time. + */ + virtual void onResult(BLEAdvertisedDevice advertisedDevice) = 0; +}; + +#if defined(SOC_BLE_50_SUPPORTED) && defined(CONFIG_BLUEDROID_ENABLED) +class BLEExtAdvertisingCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEExtAdvertisingCallbacks() {} + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + + /** + * @brief Called when a new scan result is detected. + * + * As we are scanning, we will find new devices. When found, this call back is invoked with a reference to the + * device that was found. During any individual scan, a device will only be detected one time. + */ + +#if defined(CONFIG_BLUEDROID_ENABLED) + virtual void onResult(esp_ble_gap_ext_adv_report_t report) = 0; +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + + // Extended advertising for NimBLE is not supported yet. +#if defined(CONFIG_NIMBLE_ENABLED) + virtual void onResult(struct ble_gap_ext_disc_desc report) = 0; +#endif +}; +#endif // SOC_BLE_50_SUPPORTED && CONFIG_BLUEDROID_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_ */ diff --git a/libraries/BLE/src/BLEAdvertising.cpp b/libraries/BLE/src/BLEAdvertising.cpp new file mode 100644 index 0000000..5bce7c6 --- /dev/null +++ b/libraries/BLE/src/BLEAdvertising.cpp @@ -0,0 +1,1453 @@ +/* + * BLEAdvertising.cpp + * + * This class encapsulates advertising a BLE Server. + * Created on: Jun 21, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + * + * The ESP-IDF provides a framework for BLE advertising. It has determined that there are a common set + * of properties that are advertised and has built a data structure that can be populated by the programmer. + * This means that the programmer doesn't have to "mess with" the low level construction of a low level + * BLE advertising frame. Many of the fields are determined for us while others we can set before starting + * to advertise. + * + * Should we wish to construct our own payload, we can use the BLEAdvertisementData class and call the setters + * upon it. Once it is populated, we can then associate it with the advertising and what ever the programmer + * set in the data will be advertised. + * + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEAdvertising.h" +#include +#include "BLEUtils.h" +#include "BLEDevice.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Construct a default advertising object. + */ +BLEAdvertising::BLEAdvertising() { + reset(); +} // BLEAdvertising + +/** + * @brief Add a service uuid to exposed list of services. + * @param [in] serviceUUID The UUID of the service to expose. + */ +void BLEAdvertising::addServiceUUID(BLEUUID serviceUUID) { + m_serviceUUIDs.push_back(serviceUUID); +#ifdef CONFIG_NIMBLE_ENABLED + m_advDataSet = false; +#endif +} // addServiceUUID + +/** + * @brief Add a service uuid to exposed list of services. + * @param [in] serviceUUID The string representation of the service to expose. + */ +void BLEAdvertising::addServiceUUID(const char *serviceUUID) { + addServiceUUID(BLEUUID(serviceUUID)); +#ifdef CONFIG_NIMBLE_ENABLED + m_advDataSet = false; +#endif +} // addServiceUUID + +/** + * @brief Remove a service uuid to exposed list of services. + * @param [in] index The index of the service to stop exposing. + */ +bool BLEAdvertising::removeServiceUUID(int index) { + + // If index is larger than the size of the + // advertised services, return false + if (index > m_serviceUUIDs.size()) { + return false; + } + + m_serviceUUIDs.erase(m_serviceUUIDs.begin() + index); +#ifdef CONFIG_NIMBLE_ENABLED + m_advDataSet = false; +#endif + return true; +} + +/** + * @brief Remove a service uuid to exposed list of services. + * @param [in] serviceUUID The BLEUUID of the service to stop exposing. + */ +bool BLEAdvertising::removeServiceUUID(BLEUUID serviceUUID) { + for (int i = 0; i < m_serviceUUIDs.size(); i++) { + if (m_serviceUUIDs.at(i).equals(serviceUUID)) { + return removeServiceUUID(i); + } + } + return false; +} + +/** + * @brief Remove a service uuid to exposed list of services. + * @param [in] serviceUUID The string of the service to stop exposing. + */ +bool BLEAdvertising::removeServiceUUID(const char *serviceUUID) { + return removeServiceUUID(BLEUUID(serviceUUID)); +} + +/** + * @brief Set the device appearance in the advertising data. + * The appearance attribute is of type 0x19. The codes for distinct appearances can be found here: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.characteristic.gap.appearance.xml. + * @param [in] appearance The appearance of the device in the advertising data. + * @return N/A. + */ +void BLEAdvertising::setAppearance(uint16_t appearance) { + m_advData.appearance = appearance; +#ifdef CONFIG_NIMBLE_ENABLED + m_advData.appearance_is_present = 1; + m_advDataSet = false; +#endif +} // setAppearance + +void BLEAdvertising::setAdvertisementType(uint8_t adv_type) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_type = (esp_ble_adv_type_t)adv_type; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.conn_mode = adv_type; +#endif +} // setAdvertisementType + +void BLEAdvertising::setMinInterval(uint16_t mininterval) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_int_min = mininterval; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.itvl_min = mininterval; +#endif +} // setMinInterval + +void BLEAdvertising::setMaxInterval(uint16_t maxinterval) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_int_max = maxinterval; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.itvl_max = maxinterval; +#endif +} // setMaxInterval + +void BLEAdvertising::setMinPreferred(uint16_t mininterval) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_advData.min_interval = mininterval; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + // invalid parameters, set the slave interval to null + if (mininterval < 0x0006 || mininterval > 0x0C80) { + m_advData.slave_itvl_range = nullptr; + return; + } + + if (m_advData.slave_itvl_range == nullptr) { + m_advData.slave_itvl_range = m_slaveItvl; + } + + m_slaveItvl[0] = mininterval; + m_slaveItvl[1] = mininterval >> 8; + + uint16_t maxinterval = *(uint16_t *)(m_advData.slave_itvl_range + 2); + + // If mininterval is higher than the maxinterval make them the same + if (mininterval > maxinterval) { + m_slaveItvl[2] = m_slaveItvl[0]; + m_slaveItvl[3] = m_slaveItvl[1]; + } + + m_advDataSet = false; +#endif +} // + +void BLEAdvertising::setMaxPreferred(uint16_t maxinterval) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_advData.max_interval = maxinterval; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + // invalid parameters, set the slave interval to null + if (maxinterval < 0x0006 || maxinterval > 0x0C80) { + m_advData.slave_itvl_range = nullptr; + return; + } + if (m_advData.slave_itvl_range == nullptr) { + m_advData.slave_itvl_range = m_slaveItvl; + } + m_slaveItvl[2] = maxinterval; + m_slaveItvl[3] = maxinterval >> 8; + + uint16_t mininterval = *(uint16_t *)(m_advData.slave_itvl_range); + + // If mininterval is higher than the maxinterval make them the same + if (mininterval > maxinterval) { + m_slaveItvl[0] = m_slaveItvl[2]; + m_slaveItvl[1] = m_slaveItvl[3]; + } + + m_advDataSet = false; +#endif +} // + +void BLEAdvertising::setScanResponse(bool set) { + m_scanResp = set; +#ifdef CONFIG_NIMBLE_ENABLED + m_advDataSet = false; +#endif +} + +/** + * @brief Set the filtering for the scan filter. + * @param [in] scanRequestWhitelistOnly If true, only allow scan requests from those on the white list. + * @param [in] connectWhitelistOnly If true, only allow connections from those on the white list. + */ +void BLEAdvertising::setScanFilter(bool scanRequestWhitelistOnly, bool connectWhitelistOnly) { + log_v(">> setScanFilter: scanRequestWhitelistOnly: %d, connectWhitelistOnly: %d", scanRequestWhitelistOnly, connectWhitelistOnly); + if (!scanRequestWhitelistOnly && !connectWhitelistOnly) { + +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.filter_policy = BLE_HCI_ADV_FILT_NONE; +#endif + + log_v("<< setScanFilter"); + return; + } + if (scanRequestWhitelistOnly && !connectWhitelistOnly) { + +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_ANY; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.filter_policy = BLE_HCI_ADV_FILT_SCAN; +#endif + + log_v("<< setScanFilter"); + return; + } + if (!scanRequestWhitelistOnly && connectWhitelistOnly) { + +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_WLST; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.filter_policy = BLE_HCI_ADV_FILT_CONN; +#endif + + log_v("<< setScanFilter"); + return; + } + if (scanRequestWhitelistOnly && connectWhitelistOnly) { + +#ifdef CONFIG_BLUEDROID_ENABLED + m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_WLST; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_advParams.filter_policy = BLE_HCI_ADV_FILT_BOTH; +#endif + + log_v("<< setScanFilter"); + return; + } +} // setScanFilter + +/** + * @brief Set the advertisement data that is to be published in a regular advertisement. + * @param [in] advertisementData The data to be advertised. + */ +bool BLEAdvertising::setAdvertisementData(BLEAdvertisementData &advertisementData) { + log_v(">> setAdvertisementData"); + +#ifdef CONFIG_BLUEDROID_ENABLED + esp_err_t errRc = ::esp_ble_gap_config_adv_data_raw((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length()); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_config_adv_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc)); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + esp_err_t errRc = ble_gap_adv_set_data((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length()); + if (errRc != ESP_OK) { + log_e("ble_gap_adv_set_data: %d %s", errRc, BLEUtils::returnCodeToString(errRc)); + } +#endif + + m_customAdvData = true; // Set the flag that indicates we are using custom advertising data. + log_v("<< setAdvertisementData"); + return ESP_OK == errRc; +} // setAdvertisementData + +/** + * @brief Set the advertisement data that is to be published in a scan response. + * @param [in] advertisementData The data to be advertised. + */ +bool BLEAdvertising::setScanResponseData(BLEAdvertisementData &advertisementData) { + log_v(">> setScanResponseData"); + +#ifdef CONFIG_BLUEDROID_ENABLED + esp_err_t errRc = ::esp_ble_gap_config_scan_rsp_data_raw((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length()); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_config_scan_rsp_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc)); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + esp_err_t errRc = ble_gap_adv_rsp_set_data((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length()); + if (errRc != ESP_OK) { + log_e("ble_gap_adv_rsp_set_data: %d %s", errRc, BLEUtils::returnCodeToString(errRc)); + } +#endif + + m_customScanResponseData = true; // Set the flag that indicates we are using custom scan response data. + log_v("<< setScanResponseData"); + return ESP_OK == errRc; +} // setScanResponseData + +/** + * @brief Add data to the payload to be advertised. + * @param [in] data The data to be added to the payload. + */ +void BLEAdvertisementData::addData(String data) { + if ((m_payload.length() + data.length()) > ESP_BLE_ADV_DATA_LEN_MAX) { + return; + } + m_payload.concat(data); +} // addData + +void BLEAdvertisementData::addData(char *data, size_t length) { + if ((m_payload.length() + length) > ESP_BLE_ADV_DATA_LEN_MAX) { + return; + } + m_payload.concat(String(data, length)); +} // addData + +/** + * @brief Set the appearance. + * @param [in] appearance The appearance code value. + * + * See also: + * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.characteristic.gap.appearance.xml + */ +void BLEAdvertisementData::setAppearance(uint16_t appearance) { + char cdata[2]; + cdata[0] = 3; + cdata[1] = ESP_BLE_AD_TYPE_APPEARANCE; // 0x19 + addData(String(cdata, 2) + String((char *)&appearance, 2)); +} // setAppearance + +/** + * @brief Set the complete services. + * @param [in] uuid The single service to advertise. + */ +void BLEAdvertisementData::setCompleteServices(BLEUUID uuid) { + char cdata[2]; + switch (uuid.bitSize()) { + case 16: + { + // [Len] [0x03] [LL] [HH] + cdata[0] = 3; + cdata[1] = ESP_BLE_AD_TYPE_16SRV_CMPL; // 0x03 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u16.value, 2)); +#endif + break; + } + + case 32: + { + // [Len] [0x05] [LL] [LL] [HH] [HH] + cdata[0] = 5; + cdata[1] = ESP_BLE_AD_TYPE_32SRV_CMPL; // 0x05 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u32.value, 4)); +#endif + break; + } + + case 128: + { + // [Len] [0x07] [0] [1] ... [15] + cdata[0] = 17; + cdata[1] = ESP_BLE_AD_TYPE_128SRV_CMPL; // 0x07 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)uuid.getNative()->uuid.uuid128, 16)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)uuid.getNative()->u128.value, 16)); +#endif + break; + } + + default: return; + } +} // setCompleteServices + +/** + * @brief Set the advertisement flags. + * @param [in] The flags to be set in the advertisement. + * + * * ESP_BLE_ADV_FLAG_LIMIT_DISC + * * ESP_BLE_ADV_FLAG_GEN_DISC + * * ESP_BLE_ADV_FLAG_BREDR_NOT_SPT + * * ESP_BLE_ADV_FLAG_DMT_CONTROLLER_SPT + * * ESP_BLE_ADV_FLAG_DMT_HOST_SPT + * * ESP_BLE_ADV_FLAG_NON_LIMIT_DISC + */ +void BLEAdvertisementData::setFlags(uint8_t flag) { + char cdata[3]; + cdata[0] = 2; + cdata[1] = ESP_BLE_AD_TYPE_FLAG; // 0x01 + cdata[2] = flag; + addData(String(cdata, 3)); +} // setFlag + +/** + * @brief Set manufacturer specific data. + * @param [in] data Manufacturer data. + */ +void BLEAdvertisementData::setManufacturerData(String data) { + log_d("BLEAdvertisementData", ">> setManufacturerData"); + char cdata[2]; + cdata[0] = data.length() + 1; + cdata[1] = ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE; // 0xff + addData(String(cdata, 2) + data); + log_d("BLEAdvertisementData", "<< setManufacturerData"); +} // setManufacturerData + +/** + * @brief Set the name. + * @param [in] The complete name of the device. + */ +void BLEAdvertisementData::setName(String name) { + log_d("BLEAdvertisementData", ">> setName: %s", name.c_str()); + char cdata[2]; + cdata[0] = name.length() + 1; + cdata[1] = ESP_BLE_AD_TYPE_NAME_CMPL; // 0x09 + addData(String(cdata, 2) + name); + log_d("BLEAdvertisementData", "<< setName"); +} // setName + +/** + * @brief Set the partial services. + * @param [in] uuid The single service to advertise. + */ +void BLEAdvertisementData::setPartialServices(BLEUUID uuid) { + char cdata[2]; + switch (uuid.bitSize()) { + case 16: + { + // [Len] [0x02] [LL] [HH] + cdata[0] = 3; + cdata[1] = ESP_BLE_AD_TYPE_16SRV_PART; // 0x02 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u16.value, 2)); +#endif + break; + } + + case 32: + { + // [Len] [0x04] [LL] [LL] [HH] [HH] + cdata[0] = 5; + cdata[1] = ESP_BLE_AD_TYPE_32SRV_PART; // 0x04 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u32.value, 4)); +#endif + break; + } + + case 128: + { + // [Len] [0x06] [0] [1] ... [15] + cdata[0] = 17; + cdata[1] = ESP_BLE_AD_TYPE_128SRV_PART; // 0x06 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid128, 16)); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u128.value, 16)); +#endif + break; + } + + default: return; + } +} // setPartialServices + +/** + * @brief Set the service data (UUID + data) + * @param [in] uuid The UUID to set with the service data. Size of UUID will be used. + * @param [in] data The data to be associated with the service data advert. + */ +void BLEAdvertisementData::setServiceData(BLEUUID uuid, String data) { + char cdata[2]; + switch (uuid.bitSize()) { + case 16: + { + // [Len] [0x16] [UUID16] data + cdata[0] = data.length() + 3; + cdata[1] = ESP_BLE_AD_TYPE_SERVICE_DATA; // 0x16 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2) + data); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u16.value, 2) + data); +#endif + break; + } + + case 32: + { + // [Len] [0x20] [UUID32] data + cdata[0] = data.length() + 5; + cdata[1] = ESP_BLE_AD_TYPE_32SERVICE_DATA; // 0x20 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4) + data); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u32.value, 4) + data); +#endif + break; + } + + case 128: + { + // [Len] [0x21] [UUID128] data + cdata[0] = data.length() + 17; + cdata[1] = ESP_BLE_AD_TYPE_128SERVICE_DATA; // 0x21 +#if defined(CONFIG_BLUEDROID_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid128, 16) + data); +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + addData(String(cdata, 2) + String((char *)&uuid.getNative()->u128.value, 16) + data); +#endif + break; + } + + default: return; + } +} // setServiceData + +/** + * @brief Set the short name. + * @param [in] The short name of the device. + */ +void BLEAdvertisementData::setShortName(String name) { + log_d("BLEAdvertisementData", ">> setShortName: %s", name.c_str()); + char cdata[2]; + cdata[0] = name.length() + 1; + cdata[1] = ESP_BLE_AD_TYPE_NAME_SHORT; // 0x08 + addData(String(cdata, 2) + name); + log_d("BLEAdvertisementData", "<< setShortName"); +} // setShortName + +/** + * @brief Adds Tx power level to the advertisement data. + */ +void BLEAdvertisementData::addTxPower() { + char cdata[3]; + cdata[0] = 2; // length + cdata[1] = ESP_BLE_AD_TYPE_TX_PWR; + cdata[2] = BLEDevice::getPower(); + addData(cdata, 3); +} // addTxPower + +/** + * @brief Set the preferred connection interval parameters. + * @param [in] min The minimum interval desired. + * @param [in] max The maximum interval desired. + */ +void BLEAdvertisementData::setPreferredParams(uint16_t min, uint16_t max) { + char cdata[6]; + cdata[0] = 5; // length + cdata[1] = ESP_BLE_AD_TYPE_INT_RANGE; + cdata[2] = min; + cdata[3] = min >> 8; + cdata[4] = max; + cdata[5] = max >> 8; + addData(cdata, 6); +} // setPreferredParams + +/** + * @brief Retrieve the payload that is to be advertised. + * @return The payload that is to be advertised. + */ +String BLEAdvertisementData::getPayload() { + return m_payload; +} // getPayload + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +void BLEAdvertising::reset() { + if (BLEDevice::getInitialized()) { + stop(); + } + + memset(&m_scanRespData, 0, sizeof(esp_ble_adv_data_t)); + memset(&m_advData, 0, sizeof(esp_ble_adv_data_t)); + memset(&m_advParams, 0, sizeof(esp_ble_adv_params_t)); + + m_advData.set_scan_rsp = false; + m_advData.include_name = true; + m_advData.include_txpower = true; + m_advData.min_interval = 0x20; + m_advData.max_interval = 0x40; + m_advData.appearance = 0x00; + m_advData.manufacturer_len = 0; + m_advData.p_manufacturer_data = nullptr; + m_advData.service_data_len = 0; + m_advData.p_service_data = nullptr; + m_advData.service_uuid_len = 0; + m_advData.p_service_uuid = nullptr; + m_advData.flag = (ESP_BLE_ADV_FLAG_GEN_DISC | ESP_BLE_ADV_FLAG_BREDR_NOT_SPT); + + m_advParams.adv_int_min = 0x20; + m_advParams.adv_int_max = 0x40; + m_advParams.adv_type = ADV_TYPE_IND; + m_advParams.own_addr_type = BLE_ADDR_TYPE_PUBLIC; + m_advParams.channel_map = ADV_CHNL_ALL; + m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY; + m_advParams.peer_addr_type = BLE_ADDR_TYPE_PUBLIC; + + m_customAdvData = false; // No custom advertising data + m_customScanResponseData = false; // No custom scan response data +} // BLEAdvertising + +void BLEAdvertising::setAdvertisementChannelMap(esp_ble_adv_channel_t channel_map) { + m_advParams.channel_map = channel_map; +} // setAdvertisementChannelMap + +/** + * @brief Start advertising. + * Start advertising. + * @return N/A. + */ +bool BLEAdvertising::start() { + log_v(">> start: customAdvData: %d, customScanResponseData: %d", m_customAdvData, m_customScanResponseData); + + // We have a vector of service UUIDs that we wish to advertise. In order to use the + // ESP-IDF framework, these must be supplied in a contiguous array of their 128bit (16 byte) + // representations. If we have 1 or more services to advertise then we allocate enough + // storage to host them and then copy them in one at a time into the contiguous storage. + int numServices = m_serviceUUIDs.size(); + if (numServices > 0) { + m_advData.service_uuid_len = 16 * numServices; + m_advData.p_service_uuid = (uint8_t *)malloc(m_advData.service_uuid_len); + if (!m_advData.p_service_uuid) { + log_e(">> start failed: out of memory"); + return false; + } + + uint8_t *p = m_advData.p_service_uuid; + for (int i = 0; i < numServices; i++) { + log_d("- advertising service: %s", m_serviceUUIDs[i].toString().c_str()); + BLEUUID serviceUUID128 = m_serviceUUIDs[i].to128(); + memcpy(p, serviceUUID128.getNative()->uuid.uuid128, 16); + p += 16; + } + } else { + m_advData.service_uuid_len = 0; + log_d("- no services advertised"); + } + + esp_err_t errRc; + + if (!m_customAdvData) { + // Set the configuration for advertising. + // This is an async operation - we must wait for ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT + m_advData.set_scan_rsp = false; + m_advData.include_name = !m_scanResp; + m_advData.include_txpower = !m_scanResp; + m_semaphoreSetAdv.take("config_adv_data"); + errRc = ::esp_ble_gap_config_adv_data(&m_advData); + if (errRc != ESP_OK) { + log_e("<< esp_ble_gap_config_adv_data: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreSetAdv.give(); + return false; + } + m_semaphoreSetAdv.wait("config_adv_data"); + log_d("Advertising data configured"); + } + + if (!m_customScanResponseData && m_scanResp) { + // Set the configuration for scan response. + // This is an async operation - we must wait for ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT + memcpy(&m_scanRespData, &m_advData, sizeof(esp_ble_adv_data_t)); // Copy the content of m_advData. + m_scanRespData.set_scan_rsp = true; // Define this struct as scan response data + m_scanRespData.include_name = true; // Caution: This may lead to a crash if the device name has more than 29 characters + m_scanRespData.include_txpower = true; + m_scanRespData.appearance = 0; // If defined the 'Appearance' attribute is already included in the advertising data + m_scanRespData.flag = 0; // 'Flags' attribute should no be included in the scan response + + m_semaphoreSetAdv.take("config_scan_rsp"); + errRc = ::esp_ble_gap_config_adv_data(&m_scanRespData); + if (errRc != ESP_OK) { + log_e("<< esp_ble_gap_config_adv_data (Scan response): rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreSetAdv.give(); + return false; + } + m_semaphoreSetAdv.wait("config_scan_rsp"); + log_d("Scan response data configured"); + } + + // If we had services to advertise then we previously allocated some storage for them. + // Here we release that storage. + free(m_advData.p_service_uuid); //TODO change this variable to local scope? + m_advData.p_service_uuid = nullptr; + + // Start advertising. + errRc = ::esp_ble_gap_start_advertising(&m_advParams); + if (errRc != ESP_OK) { + log_e("<< esp_ble_gap_start_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } else { + log_v("<< start"); + } + return ESP_OK == errRc; +} // start + +/** + * @brief Stop advertising. + * Stop advertising. + * @return N/A. + */ +bool BLEAdvertising::stop() { + log_v(">> stop"); + esp_err_t errRc = ::esp_ble_gap_stop_advertising(); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_stop_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } else { + log_v("<< stop"); + } + return ESP_OK == errRc; +} // stop + +void BLEAdvertising::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + log_d("handleGAPEvent [event no: %d]", (int)event); + + switch (event) { + case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: + { + log_d("Advertising data set complete, status=%d", param->adv_data_cmpl.status); + m_semaphoreSetAdv.give(); + break; + } + case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: + { + log_d("Scan response data set complete, status=%d", param->scan_rsp_data_cmpl.status); + m_semaphoreSetAdv.give(); + break; + } + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + { + log_d("Advertising start complete, status=%d", param->adv_start_cmpl.status); + break; + } + case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: + { + log_i("STOP advertising"); + //start(); + break; + } + default: break; + } +} + +/** + * @brief Set BLE address. + * @param [in] Bluetooth address. + * @param [in] Bluetooth address type. + * Set BLE address. + */ +bool BLEAdvertising::setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type) { + log_v(">> setPrivateAddress"); + + m_advParams.own_addr_type = type; + esp_err_t errRc = esp_ble_gap_set_rand_addr((uint8_t *)addr); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_set_rand_addr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } else { + log_v("<< setPrivateAddress"); + } + return ESP_OK == errRc; +} // setPrivateAddress + +#if defined(SOC_BLE_50_SUPPORTED) + +/** +* @brief Creator +* +* @param[in] instance : number of multi advertising instances +* +* +*/ +BLEMultiAdvertising::BLEMultiAdvertising(uint8_t num) { + params_arrays = (esp_ble_gap_ext_adv_params_t *)calloc(num, sizeof(esp_ble_gap_ext_adv_params_t)); + ext_adv = (esp_ble_gap_ext_adv_t *)calloc(num, sizeof(esp_ble_gap_ext_adv_t)); + count = num; +} + +/** +* @brief This function is used by the Host to set the advertising parameters. +* +* @param[in] instance : identifies the advertising set whose parameters are being configured. +* @param[in] params : advertising parameters +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::setAdvertisingParams(uint8_t instance, const esp_ble_gap_ext_adv_params_t *params) { + if (params->type == ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND && params->primary_phy == ESP_BLE_GAP_PHY_2M) { + return false; + } + esp_err_t rc; + rc = esp_ble_gap_ext_adv_set_params(instance, params); + + return ESP_OK == rc; +} + +/** +* @brief This function is used to set the data used in advertising PDUs that have a data field +* +* @param[in] instance : identifies the advertising set whose data are being configured +* @param[in] length : data length +* @param[in] data : data information +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::setAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data) { + esp_err_t rc; + rc = esp_ble_gap_config_ext_adv_data_raw(instance, length, data); + if (rc) { + log_e("set advertising data err: %d", rc); + } + + return ESP_OK == rc; +} + +bool BLEMultiAdvertising::setScanRspData(uint8_t instance, uint16_t length, const uint8_t *data) { + esp_err_t rc; + rc = esp_ble_gap_config_ext_scan_rsp_data_raw(instance, length, data); + if (rc) { + log_e("set scan resp data err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to request the Controller to enable one or more +* advertising sets using the advertising sets identified by the instance parameter. +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::start() { + return start(count, 0); +} + +/** +* @brief This function is used to request the Controller to enable one or more +* advertising sets using the advertising sets identified by the instance parameter. +* +* @param[in] num : Number of advertising sets to enable or disable +* @param[in] from : first sxt adv set to use +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::start(uint8_t num, uint8_t from) { + if (num > count || from >= count) { + return false; + } + + esp_err_t rc; + rc = esp_ble_gap_ext_adv_start(num, &ext_adv[from]); + if (rc) { + log_e("start extended advertising err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to request the Controller to disable one or more +* advertising sets using the advertising sets identified by the instance parameter. +* +* @param[in] num_adv : Number of advertising sets to enable or disable +* @param[in] ext_adv_inst : ext adv instance +* +* @return - ESP_OK : success +* - other : failed +* +*/ +bool BLEMultiAdvertising::stop(uint8_t num_adv, const uint8_t *ext_adv_inst) { + esp_err_t rc; + rc = esp_ble_gap_ext_adv_stop(num_adv, ext_adv_inst); + if (rc) { + log_e("stop extended advertising err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to remove an advertising set from the Controller. +* +* @param[in] instance : Used to identify an advertising set +* +* @return - ESP_OK : success +* - other : failed +* +*/ +bool BLEMultiAdvertising::remove(uint8_t instance) { + esp_err_t rc; + rc = esp_ble_gap_ext_adv_set_remove(instance); + if (rc) { + log_e("remove extended advertising err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to remove all existing advertising sets from the Controller. +* +* +* @return - ESP_OK : success +* - other : failed +* +*/ +bool BLEMultiAdvertising::clear() { + esp_err_t rc; + rc = esp_ble_gap_ext_adv_set_clear(); + if (rc) { + log_e("clear extended advertising err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used by the Host to set the random device address specified by the Random_Address parameter. +* +* @param[in] instance : Used to identify an advertising set +* @param[in] addr_legacy : Random Device Address +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::setInstanceAddress(uint8_t instance, uint8_t *addr_legacy) { + esp_err_t rc; + rc = esp_ble_gap_ext_adv_set_rand_addr(instance, addr_legacy); + if (rc) { + log_e("set random address err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used by the Host to set the parameters for periodic advertising. +* +* @param[in] instance : identifies the advertising set whose periodic advertising parameters are being configured. +* @param[in] params : periodic adv parameters +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::setPeriodicAdvertisingParams(uint8_t instance, const esp_ble_gap_periodic_adv_params_t *params) { + esp_err_t rc; + rc = esp_ble_gap_periodic_adv_set_params(instance, params); + if (rc) { + log_e("set periodic advertising params err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to set the data used in periodic advertising PDUs. +* +* @param[in] instance : identifies the advertising set whose periodic advertising parameters are being configured. +* @param[in] length : the length of periodic data +* @param[in] data : periodic data information +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::setPeriodicAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data) { + esp_err_t rc; + rc = esp_ble_gap_config_periodic_adv_data_raw(instance, length, data); + if (rc) { + log_e("set periodic advertising raw data err: %d", rc); + } + + return ESP_OK == rc; +} + +/** +* @brief This function is used to request the Controller to enable the periodic advertising for the advertising set specified +* +* @param[in] instance : Used to identify an advertising set +* +* @return - true : success +* - false : failed +* +*/ +bool BLEMultiAdvertising::startPeriodicAdvertising(uint8_t instance) { + esp_err_t rc; + rc = esp_ble_gap_periodic_adv_start(instance); + if (rc) { + log_e("start periodic advertising err: %d", rc); + } + + return ESP_OK == rc; +} + +void BLEMultiAdvertising::setDuration(uint8_t instance, int duration, int max_events) { + ext_adv[instance] = {instance, duration, max_events}; +} + +#endif /* SOC_BLE_50_SUPPORTED */ + +#endif /* CONFIG_BLUEDROID_ENABLED */ + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +void BLEAdvertising::reset() { + if (BLEDevice::getInitialized() && isAdvertising()) { + stop(); + } + memset(&m_advData, 0, sizeof m_advData); + memset(&m_scanData, 0, sizeof m_scanData); + memset(&m_advParams, 0, sizeof m_advParams); + memset(&m_slaveItvl, 0, sizeof m_slaveItvl); + const char *name = ble_svc_gap_device_name(); + + m_advData.name = (uint8_t *)name; + m_advData.name_len = strlen(name); + m_advData.name_is_complete = 1; + m_advData.tx_pwr_lvl = BLEDevice::getPower(); + m_advData.flags = (BLE_HS_ADV_F_DISC_GEN | BLE_HS_ADV_F_BREDR_UNSUP); + m_advParams.conn_mode = BLE_GAP_CONN_MODE_UND; + m_advParams.disc_mode = BLE_GAP_DISC_MODE_GEN; + m_customAdvData = false; + m_customScanResponseData = false; + m_scanResp = true; + m_advDataSet = false; + // Set this to non-zero to prevent auto start if host reset before started by app. + m_duration = BLE_HS_FOREVER; + m_advCompCB = nullptr; +} // BLEAdvertising + +void BLEAdvertising::setName(String name) { + m_name = name; + m_advData.name = (uint8_t *)m_name.c_str(); + m_advData.name_len = m_name.length(); + m_advDataSet = false; +} + +/** + * @brief Add the transmission power level to the advertisement packet. + */ +void BLEAdvertising::addTxPower() { + m_advData.tx_pwr_lvl_is_present = 1; + m_advDataSet = false; +} // addTxPower + +/** + * @brief Handles the callback when advertising stops. + */ +void BLEAdvertising::advCompleteCB() { + if (m_advCompCB != nullptr) { + m_advCompCB(this); + } +} // advCompleteCB + +/** + * @brief Check if currently advertising. + * @return true if advertising is active. + */ +bool BLEAdvertising::isAdvertising() { + return ble_gap_adv_active(); +} // isAdvertising + +/* + * Host reset seems to clear advertising data, + * we need clear the flag so it reloads it. + */ +void BLEAdvertising::onHostSync() { + log_v("Host re-synced"); + + m_advDataSet = false; + // If we were advertising forever, restart it now + if (m_duration == 0) { + start(m_duration, m_advCompCB); + } else { + // Otherwise we should tell the app that advertising stopped. + advCompleteCB(); + } +} // onHostSync + +/** + * @brief Handler for gap events when not using peripheral role. + * @param [in] event the event data. + * @param [in] arg pointer to the advertising instance. + */ +int BLEAdvertising::handleGAPEvent(struct ble_gap_event *event, void *arg) { + BLEAdvertising *pAdv = (BLEAdvertising *)arg; + + if (event->type == BLE_GAP_EVENT_ADV_COMPLETE) { + switch (event->adv_complete.reason) { + // Don't call the callback if host reset, we want to + // preserve the active flag until re-sync to restart advertising. + case BLE_HS_ETIMEOUT_HCI: + case BLE_HS_EOS: + case BLE_HS_ECONTROLLER: + case BLE_HS_ENOTSYNCED: + log_e("host reset, rc=%d", event->adv_complete.reason); + BLEDevice::onReset(event->adv_complete.reason); + return 0; + default: break; + } + pAdv->advCompleteCB(); + } + return 0; +} + +/** + * @brief Start advertising. + * @param [in] duration The duration, in seconds, to advertise, 0 == advertise forever. + * @param [in] advCompleteCB A pointer to a callback to be invoked when advertising ends. + * @return True if advertising started successfully. + */ +bool BLEAdvertising::start(uint32_t duration, void (*advCompleteCB)(BLEAdvertising *pAdv)) { + log_v(">> Advertising start: customAdvData: %d, customScanResponseData: %d", m_customAdvData, m_customScanResponseData); + + // If Host is not synced we cannot start advertising. + if (!BLEDevice::m_synced) { + log_e("Host reset, wait for sync."); + return false; + } + + // If already advertising just return + if (ble_gap_adv_active()) { + log_w("Advertising already active"); + return true; + } + + BLEServer *pServer = BLEDevice::getServer(); + if (pServer != nullptr) { + if (!pServer->m_gattsStarted) { + pServer->start(); + } else if (pServer->getConnectedCount() >= CONFIG_BT_NIMBLE_MAX_CONNECTIONS) { + log_e("Max connections reached - not advertising"); + return false; + } + } + + // Save the duration in case of host reset so we can restart with the same parameters + m_duration = duration; + + if (duration == 0) { + duration = BLE_HS_FOREVER; + } else { + duration = duration * 1000; // convert duration to milliseconds + } + + m_advCompCB = advCompleteCB; + + m_advParams.disc_mode = BLE_GAP_DISC_MODE_GEN; + m_advData.flags = (BLE_HS_ADV_F_DISC_GEN | BLE_HS_ADV_F_BREDR_UNSUP); + if (m_advParams.conn_mode == BLE_GAP_CONN_MODE_NON) { + if (!m_scanResp) { + m_advParams.disc_mode = BLE_GAP_DISC_MODE_NON; + m_advData.flags = BLE_HS_ADV_F_BREDR_UNSUP; + } + } + + int rc = 0; + + // Use the device name from BLEDevice for advertising + // Note: ble_svc_gap_device_name() doesn't reliably return the name set via + // ble_svc_gap_device_name_set(), so we store and use the name directly (like SimpleBLE does) + // If setName() was called on advertising, m_name will already be set and we use that + if (!m_customAdvData && m_name.isEmpty()) { + m_name = BLEDevice::getDeviceName(); + if (m_name.length() > 0) { + m_advData.name = (uint8_t *)m_name.c_str(); + m_advData.name_len = m_name.length(); + m_advData.name_is_complete = 1; + m_advDataSet = false; // Force rebuild of advertising data + } + } + + if (!m_customAdvData && !m_advDataSet) { + //start with 3 bytes for the flags data + uint8_t payloadLen = (2 + 1); + if (m_advData.mfg_data_len > 0) { + payloadLen += (2 + m_advData.mfg_data_len); + } + + if (m_advData.svc_data_uuid16_len > 0) { + payloadLen += (2 + m_advData.svc_data_uuid16_len); + } + + if (m_advData.svc_data_uuid32_len > 0) { + payloadLen += (2 + m_advData.svc_data_uuid32_len); + } + + if (m_advData.svc_data_uuid128_len > 0) { + payloadLen += (2 + m_advData.svc_data_uuid128_len); + } + + if (m_advData.uri_len > 0) { + payloadLen += (2 + m_advData.uri_len); + } + + if (m_advData.appearance_is_present) { + payloadLen += (2 + BLE_HS_ADV_APPEARANCE_LEN); + } + + if (m_advData.tx_pwr_lvl_is_present) { + payloadLen += (2 + BLE_HS_ADV_TX_PWR_LVL_LEN); + } + + if (m_advData.slave_itvl_range != nullptr) { + payloadLen += (2 + BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN); + } + + for (auto &it : m_serviceUUIDs) { + if (it.getNative()->u.type == BLE_UUID_TYPE_16) { + int add = (m_advData.num_uuids16 > 0) ? 2 : 4; + if ((payloadLen + add) > BLE_HS_ADV_MAX_SZ) { + m_advData.uuids16_is_complete = 0; + continue; + } + payloadLen += add; + + if (nullptr == (m_advData.uuids16 = (ble_uuid16_t *)realloc((void *)m_advData.uuids16, (m_advData.num_uuids16 + 1) * sizeof(ble_uuid16_t)))) { + log_e("Error, no mem"); + abort(); + } + memcpy((void *)&m_advData.uuids16[m_advData.num_uuids16], &it.getNative()->u16, sizeof(ble_uuid16_t)); + m_advData.uuids16_is_complete = 1; + m_advData.num_uuids16++; + } + if (it.getNative()->u.type == BLE_UUID_TYPE_32) { + int add = (m_advData.num_uuids32 > 0) ? 4 : 6; + if ((payloadLen + add) > BLE_HS_ADV_MAX_SZ) { + m_advData.uuids32_is_complete = 0; + continue; + } + payloadLen += add; + + if (nullptr == (m_advData.uuids32 = (ble_uuid32_t *)realloc((void *)m_advData.uuids32, (m_advData.num_uuids32 + 1) * sizeof(ble_uuid32_t)))) { + log_e("Error, no mem"); + abort(); + } + memcpy((void *)&m_advData.uuids32[m_advData.num_uuids32], &it.getNative()->u32, sizeof(ble_uuid32_t)); + m_advData.uuids32_is_complete = 1; + m_advData.num_uuids32++; + } + if (it.getNative()->u.type == BLE_UUID_TYPE_128) { + int add = (m_advData.num_uuids128 > 0) ? 16 : 18; + if ((payloadLen + add) > BLE_HS_ADV_MAX_SZ) { + m_advData.uuids128_is_complete = 0; + continue; + } + payloadLen += add; + + if (nullptr == (m_advData.uuids128 = (ble_uuid128_t *)realloc((void *)m_advData.uuids128, (m_advData.num_uuids128 + 1) * sizeof(ble_uuid128_t)))) { + log_e("Error, no mem"); + abort(); + } + memcpy((void *)&m_advData.uuids128[m_advData.num_uuids128], &it.getNative()->u128, sizeof(ble_uuid128_t)); + m_advData.uuids128_is_complete = 1; + m_advData.num_uuids128++; + } + } + + // check if there is room for the name, if not put it in scan data + if ((payloadLen + (2 + m_advData.name_len)) > BLE_HS_ADV_MAX_SZ) { + if (m_scanResp && !m_customScanResponseData) { + m_scanData.name = m_advData.name; + m_scanData.name_len = m_advData.name_len; + if (m_scanData.name_len > BLE_HS_ADV_MAX_SZ - 2) { + m_scanData.name_len = BLE_HS_ADV_MAX_SZ - 2; + m_scanData.name_is_complete = 0; + } else { + m_scanData.name_is_complete = 1; + } + m_advData.name = nullptr; + m_advData.name_len = 0; + m_advData.name_is_complete = 0; + } else { + if (m_advData.tx_pwr_lvl_is_present) { + m_advData.tx_pwr_lvl_is_present = 0; + payloadLen -= (2 + 1); + } + // if not using scan response just cut the name down + // leaving 2 bytes for the data specifier. + if (m_advData.name_len > (BLE_HS_ADV_MAX_SZ - payloadLen - 2)) { + m_advData.name_len = (BLE_HS_ADV_MAX_SZ - payloadLen - 2); + m_advData.name_is_complete = 0; + } + } + } + + if (m_scanResp && !m_customScanResponseData) { + rc = ble_gap_adv_rsp_set_fields(&m_scanData); + switch (rc) { + case 0: break; + + case BLE_HS_EBUSY: log_e("Already advertising"); break; + + case BLE_HS_EMSGSIZE: log_e("Scan data too long"); break; + + default: log_e("Error setting scan response data; rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); break; + } + } + + if (rc == 0) { + rc = ble_gap_adv_set_fields(&m_advData); + switch (rc) { + case 0: break; + + case BLE_HS_EBUSY: log_e("Already advertising"); break; + + case BLE_HS_EMSGSIZE: log_e("Advertisement data too long"); break; + + default: log_e("Error setting advertisement data; rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); break; + } + } + + if (m_advData.num_uuids128 > 0) { + free((void *)m_advData.uuids128); + m_advData.uuids128 = nullptr; + m_advData.num_uuids128 = 0; + } + + if (m_advData.num_uuids32 > 0) { + free((void *)m_advData.uuids32); + m_advData.uuids32 = nullptr; + m_advData.num_uuids32 = 0; + } + + if (m_advData.num_uuids16 > 0) { + free((void *)m_advData.uuids16); + m_advData.uuids16 = nullptr; + m_advData.num_uuids16 = 0; + } + + if (rc != 0) { + return false; + } + + m_advDataSet = true; + } + + rc = ble_gap_adv_start( + BLEDevice::m_ownAddrType, NULL, duration, &m_advParams, (pServer != nullptr) ? BLEServer::handleGATTServerEvent : BLEAdvertising::handleGAPEvent, + (pServer != nullptr) ? (void *)pServer : (void *)this + ); + + switch (rc) { + case 0: break; + + case BLE_HS_EINVAL: log_e("Unable to advertise - Duration too long"); break; + + case BLE_HS_EPREEMPTED: log_e("Unable to advertise - busy"); break; + + case BLE_HS_ETIMEOUT_HCI: + case BLE_HS_EOS: + case BLE_HS_ECONTROLLER: + case BLE_HS_ENOTSYNCED: log_e("Unable to advertise - Host Reset"); break; + + default: log_e("Error enabling advertising; rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); break; + } + + log_d("<< Advertising start"); + return (rc == 0); +} // start + +/** + * @brief Stop advertising. + */ +bool BLEAdvertising::stop() { + log_d(">> stop"); + + int rc = ble_gap_adv_stop(); + if (rc != 0 && rc != BLE_HS_EALREADY) { + log_e("ble_gap_adv_stop rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + + log_d("<< stop"); + return true; +} // stop + +#endif /* CONFIG_NIMBLE_ENABLED */ + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEAdvertising.h b/libraries/BLE/src/BLEAdvertising.h new file mode 100644 index 0000000..2ea112b --- /dev/null +++ b/libraries/BLE/src/BLEAdvertising.h @@ -0,0 +1,258 @@ +/* + * BLEAdvertising.h + * + * Created on: Jun 21, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEADVERTISING_H_ +#define COMPONENTS_CPP_UTILS_BLEADVERTISING_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEUUID.h" +#include +#include "RTOS.h" +#include "BLEUtils.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include + +#define ESP_BLE_ADV_DATA_LEN_MAX BLE_HS_ADV_MAX_SZ +#define ESP_BLE_ADV_FLAG_LIMIT_DISC (0x01 << 0) +#define ESP_BLE_ADV_FLAG_GEN_DISC (0x01 << 1) +#define ESP_BLE_ADV_FLAG_BREDR_NOT_SPT (0x01 << 2) +#define ESP_BLE_ADV_FLAG_DMT_CONTROLLER_SPT (0x01 << 3) +#define ESP_BLE_ADV_FLAG_DMT_HOST_SPT (0x01 << 4) +#define ESP_BLE_ADV_FLAG_NON_LIMIT_DISC (0x00) +#endif /* CONFIG_NIMBLE_ENABLED */ + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef enum { + ESP_BLE_AD_TYPE_FLAG = 0x01, + ESP_BLE_AD_TYPE_16SRV_PART = 0x02, + ESP_BLE_AD_TYPE_16SRV_CMPL = 0x03, + ESP_BLE_AD_TYPE_32SRV_PART = 0x04, + ESP_BLE_AD_TYPE_32SRV_CMPL = 0x05, + ESP_BLE_AD_TYPE_128SRV_PART = 0x06, + ESP_BLE_AD_TYPE_128SRV_CMPL = 0x07, + ESP_BLE_AD_TYPE_NAME_SHORT = 0x08, + ESP_BLE_AD_TYPE_NAME_CMPL = 0x09, + ESP_BLE_AD_TYPE_TX_PWR = 0x0A, + ESP_BLE_AD_TYPE_DEV_CLASS = 0x0D, + ESP_BLE_AD_TYPE_SM_TK = 0x10, + ESP_BLE_AD_TYPE_SM_OOB_FLAG = 0x11, + ESP_BLE_AD_TYPE_INT_RANGE = 0x12, + ESP_BLE_AD_TYPE_SOL_SRV_UUID = 0x14, + ESP_BLE_AD_TYPE_128SOL_SRV_UUID = 0x15, + ESP_BLE_AD_TYPE_SERVICE_DATA = 0x16, + ESP_BLE_AD_TYPE_PUBLIC_TARGET = 0x17, + ESP_BLE_AD_TYPE_RANDOM_TARGET = 0x18, + ESP_BLE_AD_TYPE_APPEARANCE = 0x19, + ESP_BLE_AD_TYPE_ADV_INT = 0x1A, + ESP_BLE_AD_TYPE_LE_DEV_ADDR = 0x1b, + ESP_BLE_AD_TYPE_LE_ROLE = 0x1c, + ESP_BLE_AD_TYPE_SPAIR_C256 = 0x1d, + ESP_BLE_AD_TYPE_SPAIR_R256 = 0x1e, + ESP_BLE_AD_TYPE_32SOL_SRV_UUID = 0x1f, + ESP_BLE_AD_TYPE_32SERVICE_DATA = 0x20, + ESP_BLE_AD_TYPE_128SERVICE_DATA = 0x21, + ESP_BLE_AD_TYPE_LE_SECURE_CONFIRM = 0x22, + ESP_BLE_AD_TYPE_LE_SECURE_RANDOM = 0x23, + ESP_BLE_AD_TYPE_URI = 0x24, + ESP_BLE_AD_TYPE_INDOOR_POSITION = 0x25, + ESP_BLE_AD_TYPE_TRANS_DISC_DATA = 0x26, + ESP_BLE_AD_TYPE_LE_SUPPORT_FEATURE = 0x27, + ESP_BLE_AD_TYPE_CHAN_MAP_UPDATE = 0x28, + ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE = 0xFF, +} esp_ble_adv_data_type; +#endif + +/** + * @brief Advertisement data set by the programmer to be published by the %BLE server. + */ +class BLEAdvertisementData { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + void setAppearance(uint16_t appearance); + void setCompleteServices(BLEUUID uuid); + void setFlags(uint8_t); + void setManufacturerData(String data); + void setName(String name); + void setPartialServices(BLEUUID uuid); + void setServiceData(BLEUUID uuid, String data); + void setShortName(String name); + void setPreferredParams(uint16_t min, uint16_t max); + void addTxPower(); + void addData(String data); + void addData(char *data, size_t length); + String getPayload(); + +private: + friend class BLEAdvertising; + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + String m_payload; +}; + +/** + * @brief Perform and manage %BLE advertising. + */ +class BLEAdvertising { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEAdvertising(); + void addServiceUUID(BLEUUID serviceUUID); + void addServiceUUID(const char *serviceUUID); + bool removeServiceUUID(int index); + bool removeServiceUUID(BLEUUID serviceUUID); + bool removeServiceUUID(const char *serviceUUID); + bool stop(); + void reset(); + void setAppearance(uint16_t appearance); + void setAdvertisementType(uint8_t adv_type); + void setMaxInterval(uint16_t maxinterval); + void setMinInterval(uint16_t mininterval); + bool setAdvertisementData(BLEAdvertisementData &advertisementData); + void setScanFilter(bool scanRequestWhitelistOnly, bool connectWhitelistOnly); + bool setScanResponseData(BLEAdvertisementData &advertisementData); + void setMinPreferred(uint16_t); + void setMaxPreferred(uint16_t); + void setScanResponse(bool); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void setPrivateAddress(esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM); + bool setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM); + void setAdvertisementChannelMap(esp_ble_adv_channel_t channel_map); + void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); + bool start(); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void setName(String name); + void addTxPower(); + void advCompleteCB(); + bool isAdvertising(); + void onHostSync(); + bool start(uint32_t duration = 0, void (*advCompleteCB)(BLEAdvertising *pAdv) = nullptr); + static int handleGAPEvent(ble_gap_event *event, void *arg); +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + std::vector m_serviceUUIDs; + bool m_customAdvData = false; + bool m_customScanResponseData = false; + FreeRTOS::Semaphore m_semaphoreSetAdv = FreeRTOS::Semaphore("startAdvert"); + bool m_scanResp = true; + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_adv_data_t m_advData; + esp_ble_adv_data_t m_scanRespData; + esp_ble_adv_params_t m_advParams; +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + ble_hs_adv_fields m_advData; + ble_hs_adv_fields m_scanData; + ble_gap_adv_params m_advParams; + bool m_advDataSet; + void (*m_advCompCB)(BLEAdvertising *pAdv); + uint8_t m_slaveItvl[4]; + uint32_t m_duration; + String m_name; +#endif +}; + +/*************************************************************************** + * Bluedroid 5.0 specific classes * + ***************************************************************************/ + +#if defined(SOC_BLE_50_SUPPORTED) && defined(CONFIG_BLUEDROID_ENABLED) +class BLEMultiAdvertising { +public: + BLEMultiAdvertising(uint8_t num = 1); + ~BLEMultiAdvertising() {} + + bool setAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data); + bool setScanRspData(uint8_t instance, uint16_t length, const uint8_t *data); + bool start(); + bool start(uint8_t num, uint8_t from); + void setDuration(uint8_t instance, int duration = 0, int max_events = 0); + bool setInstanceAddress(uint8_t instance, uint8_t *rand_addr); + bool stop(uint8_t num_adv, const uint8_t *ext_adv_inst); + bool remove(uint8_t instance); + bool clear(); + bool setPeriodicAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data); + bool startPeriodicAdvertising(uint8_t instance); + bool setAdvertisingParams(uint8_t instance, const esp_ble_gap_ext_adv_params_t *params); + bool setPeriodicAdvertisingParams(uint8_t instance, const esp_ble_gap_periodic_adv_params_t *params); + +private: + esp_ble_gap_ext_adv_params_t *params_arrays; + esp_ble_gap_ext_adv_t *ext_adv; + uint8_t count; +}; +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEADVERTISING_H_ */ diff --git a/libraries/BLE/src/BLEBeacon.cpp b/libraries/BLE/src/BLEBeacon.cpp new file mode 100644 index 0000000..0b10836 --- /dev/null +++ b/libraries/BLE/src/BLEBeacon.cpp @@ -0,0 +1,98 @@ +/* + * BLEBeacon.cpp + * + * Created on: Jan 4, 2018 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes and definitions * + ***************************************************************************/ + +#include "BLEBeacon.h" +#include "esp32-hal-log.h" + +#define ENDIAN_CHANGE_U16(x) ((((x) & 0xFF00) >> 8) + (((x) & 0xFF) << 8)) + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLEBeacon::BLEBeacon() { + m_beaconData.manufacturerId = 0x4c00; + m_beaconData.subType = 0x02; + m_beaconData.subTypeLength = 0x15; + m_beaconData.major = 0; + m_beaconData.minor = 0; + m_beaconData.signalPower = 0; + memset(m_beaconData.proximityUUID, 0, sizeof(m_beaconData.proximityUUID)); +} + +String BLEBeacon::getData() { + return String((char *)&m_beaconData, sizeof(m_beaconData)); +} + +uint16_t BLEBeacon::getMajor() { + return m_beaconData.major; +} + +uint16_t BLEBeacon::getManufacturerId() { + return m_beaconData.manufacturerId; +} + +uint16_t BLEBeacon::getMinor() { + return m_beaconData.minor; +} + +BLEUUID BLEBeacon::getProximityUUID() { + return BLEUUID(m_beaconData.proximityUUID, 16, true); +} + +int8_t BLEBeacon::getSignalPower() { + return m_beaconData.signalPower; +} + +void BLEBeacon::setData(const String &data) { + if (data.length() != sizeof(m_beaconData)) { + log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_beaconData)); + return; + } + memcpy(&m_beaconData, data.c_str(), sizeof(m_beaconData)); +} + +void BLEBeacon::setMajor(uint16_t major) { + m_beaconData.major = ENDIAN_CHANGE_U16(major); +} + +void BLEBeacon::setManufacturerId(uint16_t manufacturerId) { + m_beaconData.manufacturerId = ENDIAN_CHANGE_U16(manufacturerId); +} + +void BLEBeacon::setMinor(uint16_t minor) { + m_beaconData.minor = ENDIAN_CHANGE_U16(minor); +} + +void BLEBeacon::setSignalPower(int8_t signalPower) { + m_beaconData.signalPower = signalPower; +} + +void BLEBeacon::setProximityUUID(BLEUUID uuid) { + uuid = uuid.to128(); +#if defined(CONFIG_BLUEDROID_ENABLED) + memcpy(m_beaconData.proximityUUID, uuid.getNative()->uuid.uuid128, 16); +#elif defined(CONFIG_NIMBLE_ENABLED) + memcpy(m_beaconData.proximityUUID, uuid.getNative()->u128.value, 16); +#endif +} + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEBeacon.h b/libraries/BLE/src/BLEBeacon.h new file mode 100644 index 0000000..b3f3408 --- /dev/null +++ b/libraries/BLE/src/BLEBeacon.h @@ -0,0 +1,69 @@ +/* + * BLEBeacon2.h + * + * Created on: Jan 4, 2018 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEBEACON_H_ +#define COMPONENTS_CPP_UTILS_BLEBEACON_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEUUID.h" +/** + * @brief Representation of a beacon. + * See: + * * https://en.wikipedia.org/wiki/IBeacon + */ +class BLEBeacon { +private: + /*************************************************************************** + * Common types * + ***************************************************************************/ + + struct { + uint16_t manufacturerId; + uint8_t subType; + uint8_t subTypeLength; + uint8_t proximityUUID[16]; + uint16_t major; + uint16_t minor; + int8_t signalPower; + } __attribute__((packed)) m_beaconData; + +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEBeacon(); + String getData(); + uint16_t getMajor(); + uint16_t getMinor(); + uint16_t getManufacturerId(); + BLEUUID getProximityUUID(); + int8_t getSignalPower(); + void setData(const String &data); + void setMajor(uint16_t major); + void setMinor(uint16_t minor); + void setManufacturerId(uint16_t manufacturerId); + void setProximityUUID(BLEUUID uuid); + void setSignalPower(int8_t signalPower); +}; // BLEBeacon + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEBEACON_H_ */ diff --git a/libraries/BLE/src/BLECharacteristic.cpp b/libraries/BLE/src/BLECharacteristic.cpp new file mode 100644 index 0000000..140afa7 --- /dev/null +++ b/libraries/BLE/src/BLECharacteristic.cpp @@ -0,0 +1,1191 @@ +/* + * BLECharacteristic.cpp + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include +#include +#include "sdkconfig.h" +#include +#include "BLECharacteristic.h" +#include "BLEService.h" +#include "BLEDevice.h" +#include "BLEUtils.h" +#include "BLE2902.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * Common definitions * + ***************************************************************************/ + +#define NULL_HANDLE (0xffff) + +/*************************************************************************** + * NimBLE definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#define NIMBLE_SUB_NOTIFY 0x0001 +#define NIMBLE_SUB_INDICATE 0x0002 +#endif + +/*************************************************************************** + * Common global variables * + ***************************************************************************/ + +static BLECharacteristicCallbacks defaultCallback; //null-object-pattern + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Construct a characteristic + * @param [in] uuid - UUID (const char*) for the characteristic. + * @param [in] properties - Properties for the characteristic. + */ +BLECharacteristic::BLECharacteristic(const char *uuid, uint32_t properties) : BLECharacteristic(BLEUUID(uuid), properties) {} + +/** + * @brief Construct a characteristic + * @param [in] uuid - UUID for the characteristic. + * @param [in] properties - Properties for the characteristic. + */ +BLECharacteristic::BLECharacteristic(BLEUUID uuid, uint32_t properties) { + m_bleUUID = uuid; + m_handle = NULL_HANDLE; + m_pCallbacks = &defaultCallback; + +#ifdef CONFIG_BLUEDROID_ENABLED + m_properties = 0; + setBroadcastProperty((properties & BLECharacteristic::PROPERTY_BROADCAST) != 0); + setReadProperty((properties & BLECharacteristic::PROPERTY_READ) != 0); + setWriteProperty((properties & BLECharacteristic::PROPERTY_WRITE) != 0); + setNotifyProperty((properties & BLECharacteristic::PROPERTY_NOTIFY) != 0); + setIndicateProperty((properties & BLECharacteristic::PROPERTY_INDICATE) != 0); + setWriteNoResponseProperty((properties & BLECharacteristic::PROPERTY_WRITE_NR) != 0); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_readMux = portMUX_INITIALIZER_UNLOCKED; + m_removed = 0; + m_properties = properties; +#endif +} // BLECharacteristic + +/** + * @brief Destructor. + */ +BLECharacteristic::~BLECharacteristic() { + //free(m_value.attr_value); // Release the storage for the value. +} // ~BLECharacteristic + +/** + * @brief Associate a descriptor with this characteristic. + * @param [in] pDescriptor + * @return N/A. + */ +void BLECharacteristic::addDescriptor(BLEDescriptor *pDescriptor) { +#ifdef CONFIG_NIMBLE_ENABLED + if (pDescriptor->getUUID() == BLEUUID(uint16_t(0x2902))) { + log_i("NimBLE automatically creates the 0x2902 descriptor if a characteristic has a notification or indication property assigned to it.\n" + "You should check the characteristic properties for notification or indication rather than adding the descriptor manually.\n" + "This will be removed in a future version of the library."); + pDescriptor->executeCreate(this); + return; + } +#endif + log_v(">> addDescriptor(): Adding %s to %s", pDescriptor->toString().c_str(), toString().c_str()); + m_descriptorMap.setByUUID(pDescriptor->getUUID(), pDescriptor); + log_v("<< addDescriptor()"); +} // addDescriptor + +/** + * @brief Return the BLE Descriptor for the given UUID if associated with this characteristic. + * @param [in] descriptorUUID The UUID of the descriptor that we wish to retrieve. + * @return The BLE Descriptor. If no such descriptor is associated with the characteristic, nullptr is returned. + */ +BLEDescriptor *BLECharacteristic::getDescriptorByUUID(const char *descriptorUUID) const { + return m_descriptorMap.getByUUID(BLEUUID(descriptorUUID)); +} // getDescriptorByUUID + +/** + * @brief Return the BLE Descriptor for the given UUID if associated with this characteristic. + * @param [in] descriptorUUID The UUID of the descriptor that we wish to retrieve. + * @return The BLE Descriptor. If no such descriptor is associated with the characteristic, nullptr is returned. + */ +BLEDescriptor *BLECharacteristic::getDescriptorByUUID(BLEUUID descriptorUUID) const { + return m_descriptorMap.getByUUID(descriptorUUID); +} // getDescriptorByUUID + +/** + * @brief Get the handle of the characteristic. + * @return The handle of the characteristic. + */ +uint16_t BLECharacteristic::getHandle() const { + return m_handle; +} // getHandle + +void BLECharacteristic::setAccessPermissions(uint16_t perm) { +#ifdef CONFIG_BLUEDROID_ENABLED + m_permissions = perm; +#endif +} + +esp_gatt_char_prop_t BLECharacteristic::getProperties() const { + return m_properties; +} // getProperties + +/** + * @brief Get the service associated with this characteristic. + */ +BLEService *BLECharacteristic::getService() const { + return m_pService; +} // getService + +/** + * @brief Get the UUID of the characteristic. + * @return The UUID of the characteristic. + */ +BLEUUID BLECharacteristic::getUUID() const { + return m_bleUUID; +} // getUUID + +/** + * @brief Retrieve the current value of the characteristic. + * @return A pointer to storage containing the current characteristic value. + */ +String BLECharacteristic::getValue() const { + return m_value.getValue(); +} // getValue + +/** + * @brief Retrieve the current raw data of the characteristic. + * @return A pointer to storage containing the current characteristic data. + */ +uint8_t *BLECharacteristic::getData() { + return m_value.getData(); +} // getData + +/** + * @brief Retrieve the current length of the data of the characteristic. + * @return Amount of databytes of the characteristic. + */ +size_t BLECharacteristic::getLength() const { + return m_value.getLength(); +} // getLength + +/** + * @brief Register a new characteristic with the ESP runtime. + * @param [in] pService The service with which to associate this characteristic. + */ +void BLECharacteristic::executeCreate(BLEService *pService) { + log_v(">> executeCreate()"); + + if (m_handle != NULL_HANDLE) { + log_e("Characteristic already has a handle."); + return; + } + + m_pService = pService; // Save the service to which this characteristic belongs. + +#ifdef CONFIG_BLUEDROID_ENABLED + log_d("Registering characteristic (esp_ble_gatts_add_char): uuid: %s, service: %s", getUUID().toString().c_str(), m_pService->toString().c_str()); + + esp_attr_control_t control; + control.auto_rsp = ESP_GATT_RSP_BY_APP; + + m_semaphoreCreateEvt.take("executeCreate"); + esp_err_t errRc = ::esp_ble_gatts_add_char( + m_pService->getHandle(), getUUID().getNative(), static_cast(m_permissions), getProperties(), nullptr, + &control + ); // Whether to auto respond or not. + + if (errRc != ESP_OK) { + log_e("<< esp_ble_gatts_add_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return; + } + m_semaphoreCreateEvt.wait("executeCreate"); + +#endif + + BLEDescriptor *pDescriptor = m_descriptorMap.getFirst(); + while (pDescriptor != nullptr) { + pDescriptor->executeCreate(this); + pDescriptor = m_descriptorMap.getNext(); + } // End while + + log_v("<< executeCreate"); +} // executeCreate + +/** + * @brief Send an indication. + * An indication is a transmission of up to the first 20 bytes of the characteristic value. An indication + * will block waiting a positive confirmation from the client. + * @return N/A + */ +void BLECharacteristic::indicate() { + + log_v(">> indicate: length: %d", m_value.getValue().length()); + notify(false); + log_v("<< indicate"); +} // indicate + +/** + * @brief Set the permission to broadcast. + * A characteristics has properties associated with it which define what it is capable of doing. + * One of these is the broadcast flag. + * @param [in] value The flag value of the property. + * @return N/A + */ +void BLECharacteristic::setBroadcastProperty(bool value) { + //log_d("setBroadcastProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_BROADCAST); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_BROADCAST); + } +} // setBroadcastProperty + +/** + * @brief Set the callback handlers for this characteristic. + * @param [in] pCallbacks An instance of a callbacks structure used to define any callbacks for the characteristic. + */ +void BLECharacteristic::setCallbacks(BLECharacteristicCallbacks *pCallbacks) { + log_v(">> setCallbacks: 0x%x", (uint32_t)pCallbacks); + if (pCallbacks != nullptr) { + m_pCallbacks = pCallbacks; + } else { + m_pCallbacks = &defaultCallback; + } + log_v("<< setCallbacks"); +} // setCallbacks + +/** + * @brief Set the BLE handle associated with this characteristic. + * A user program will request that a characteristic be created against a service. When the characteristic has been + * registered, the service will be given a "handle" that it knows the characteristic as. This handle is unique to the + * server/service but it is told to the service, not the characteristic associated with the service. This internally + * exposed function can be invoked by the service against this model of the characteristic to allow the characteristic + * to learn its own handle. Once the characteristic knows its own handle, it will be able to see incoming GATT events + * that will be propagated down to it which contain a handle value and now know that the event is destined for it. + * @param [in] handle The handle associated with this characteristic. + */ +void BLECharacteristic::setHandle(uint16_t handle) { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_v(">> setHandle: handle=0x%.2x, characteristic uuid=%s", handle, getUUID().toString().c_str()); + m_handle = handle; + log_v("<< setHandle"); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + log_w("NimBLE does not support manually setting the handle of a characteristic. Ignoring request."); +#endif +} // setHandle + +/** + * @brief Set the Indicate property value. + * @param [in] value Set to true if we are to allow indicate messages. + */ +void BLECharacteristic::setIndicateProperty(bool value) { + //log_d("setIndicateProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_INDICATE); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_INDICATE); + } +} // setIndicateProperty + +/** + * @brief Set the Notify property value. + * @param [in] value Set to true if we are to allow notification messages. + */ +void BLECharacteristic::setNotifyProperty(bool value) { + //log_d("setNotifyProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_NOTIFY); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_NOTIFY); + } +} // setNotifyProperty + +/** + * @brief Set the Read property value. + * @param [in] value Set to true if we are to allow reads. + */ +void BLECharacteristic::setReadProperty(bool value) { + //log_d("setReadProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_READ); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_READ); + } +} // setReadProperty + +/** + * @brief Set the value of the characteristic. + * @param [in] data The data to set for the characteristic. + * @param [in] length The length of the data in bytes. + */ +void BLECharacteristic::setValue(const uint8_t *data, size_t length) { +// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not +// "VERBOSE". As it is quite CPU intensive, it is much better to not call it if not needed. +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + char *pHex = BLEUtils::buildHexData(nullptr, data, length); + log_v(">> setValue: length=%d, data=%s, characteristic UUID=%s", length, pHex, getUUID().toString().c_str()); + free(pHex); +#endif + if (length > ESP_GATT_MAX_ATTR_LEN) { + log_e("Size %d too large, must be no bigger than %d", length, ESP_GATT_MAX_ATTR_LEN); + return; + } + m_semaphoreSetValue.take(); + m_value.setValue(data, length); + m_semaphoreSetValue.give(); + log_v("<< setValue"); +} // setValue + +/** + * @brief Set the value of the characteristic from string data. + * We set the value of the characteristic from the bytes contained in the + * string. + * @param [in] Set the value of the characteristic. + * @return N/A. + */ +void BLECharacteristic::setValue(const String &value) { + setValue(reinterpret_cast(value.c_str()), value.length()); +} // setValue + +void BLECharacteristic::setValue(uint16_t data16) { + setValue(reinterpret_cast(&data16), sizeof(data16)); +} // setValue + +void BLECharacteristic::setValue(uint32_t data32) { + setValue(reinterpret_cast(&data32), sizeof(data32)); +} // setValue + +void BLECharacteristic::setValue(int data32) { + setValue(reinterpret_cast(&data32), sizeof(data32)); +} // setValue + +void BLECharacteristic::setValue(float data32) { + setValue(reinterpret_cast(&data32), sizeof(data32)); +} // setValue + +void BLECharacteristic::setValue(double data64) { + setValue(reinterpret_cast(&data64), sizeof(data64)); +} // setValue + +/** + * @brief Set the Write No Response property value. + * @param [in] value Set to true if we are to allow writes with no response. + */ +void BLECharacteristic::setWriteNoResponseProperty(bool value) { + //log_d("setWriteNoResponseProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE_NR); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE_NR); + } +} // setWriteNoResponseProperty + +/** + * @brief Set the Write property value. + * @param [in] value Set to true if we are to allow writes. + */ +void BLECharacteristic::setWriteProperty(bool value) { + //log_d("setWriteProperty(%d)", value); + if (value) { + m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE); + } else { + m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE); + } +} // setWriteProperty + +/** + * @brief Return a string representation of the characteristic. + * @return A string representation of the characteristic. + */ +String BLECharacteristic::toString() const { + String res = "UUID: " + m_bleUUID.toString() + ", handle : 0x"; + char hex[5]; + snprintf(hex, sizeof(hex), "%04x", m_handle); + res += hex; + res += " "; + if (m_properties & ESP_GATT_CHAR_PROP_BIT_READ) { + res += "Read "; + } + if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE) { + res += "Write "; + } + if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) { + res += "WriteNoResponse "; + } + if (m_properties & ESP_GATT_CHAR_PROP_BIT_BROADCAST) { + res += "Broadcast "; + } + if (m_properties & ESP_GATT_CHAR_PROP_BIT_NOTIFY) { + res += "Notify "; + } + if (m_properties & ESP_GATT_CHAR_PROP_BIT_INDICATE) { + res += "Indicate "; + } + return res; +} // toString + +BLECharacteristicCallbacks::~BLECharacteristicCallbacks() = default; + +// Common callbacks +void BLECharacteristicCallbacks::onRead(BLECharacteristic *pCharacteristic) { + log_d(">> onRead: default"); + log_d("<< onRead"); +} // onRead + +void BLECharacteristicCallbacks::onWrite(BLECharacteristic *pCharacteristic) { + log_d(">> onWrite: default"); + log_d("<< onWrite"); +} // onWrite + +void BLECharacteristicCallbacks::onNotify(BLECharacteristic *pCharacteristic) { + log_d(">> onNotify: default"); + log_d("<< onNotify"); +} // onNotify + +void BLECharacteristicCallbacks::onStatus(BLECharacteristic *pCharacteristic, Status s, uint32_t code) { + log_d(">> onStatus: default"); + log_d("<< onStatus"); +} // onStatus + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * Handle a GATT server event. + */ +void BLECharacteristic::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + log_v(">> handleGATTServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str()); + + switch (event) { + // Events handled: + // + // ESP_GATTS_ADD_CHAR_EVT + // ESP_GATTS_CONF_EVT + // ESP_GATTS_CONNECT_EVT + // ESP_GATTS_DISCONNECT_EVT + // ESP_GATTS_EXEC_WRITE_EVT + // ESP_GATTS_READ_EVT + // ESP_GATTS_WRITE_EVT + + // + // ESP_GATTS_EXEC_WRITE_EVT + // When we receive this event it is an indication that a previous write long needs to be committed. + // + // exec_write: + // - uint16_t conn_id + // - uint32_t trans_id + // - esp_bd_addr_t bda + // - uint8_t exec_write_flag - Either ESP_GATT_PREP_WRITE_EXEC or ESP_GATT_PREP_WRITE_CANCEL + // + case ESP_GATTS_EXEC_WRITE_EVT: + { + if (m_writeEvt) { + m_writeEvt = false; + if (param->exec_write.exec_write_flag == ESP_GATT_PREP_WRITE_EXEC) { + m_value.commit(); + // Invoke the onWrite callback handler before sending the response. + // This ensures that when the client receives the acknowledgment, the write has been processed. + m_pCallbacks->onWrite(this, param); + } else { + m_value.cancel(); + } + esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->exec_write.conn_id, param->exec_write.trans_id, ESP_GATT_OK, nullptr); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + } + break; + } // ESP_GATTS_EXEC_WRITE_EVT + + // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service. + // add_char: + // - esp_gatt_status_t status + // - uint16_t attr_handle + // - uint16_t service_handle + // - esp_bt_uuid_t char_uuid + case ESP_GATTS_ADD_CHAR_EVT: + { + if (getHandle() == param->add_char.attr_handle) { + // we have created characteristic, now we can create descriptors + // BLEDescriptor* pDescriptor = m_descriptorMap.getFirst(); + // while (pDescriptor != nullptr) { + // pDescriptor->executeCreate(this); + // pDescriptor = m_descriptorMap.getNext(); + // } // End while + m_semaphoreCreateEvt.give(); + } + break; + } // ESP_GATTS_ADD_CHAR_EVT + + // ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived. + // + // write: + // - uint16_t conn_id + // - uint16_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool need_rsp + // - bool is_prep + // - uint16_t len + // - uint8_t *value + // + case ESP_GATTS_WRITE_EVT: + { + // We check if this write request is for us by comparing the handles in the event. If it is for us + // we save the new value. Next we look at the need_rsp flag which indicates whether or not we need + // to send a response. If we do, then we formulate a response and send it. + if (param->write.handle == m_handle) { + + // Check for authorization requirement + if (m_permissions & ESP_GATT_PERM_WRITE_AUTHORIZATION) { + bool authorized = false; + + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("Authorization required for write operation. Checking authorization..."); + authorized = BLEDevice::m_securityCallbacks->onAuthorizationRequest(param->write.conn_id, m_handle, false); + } else { + log_w("onAuthorizationRequest not implemented. Rejecting write authorization request"); + } + + if (!authorized) { + log_i("Write authorization rejected"); + if (param->write.need_rsp) { + esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, ESP_GATT_INSUF_AUTHORIZATION, nullptr); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_send_response (authorization failed): rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + } + return; // Exit early, don't process the write + } else { + log_i("Write authorization granted"); + } + } + + if (param->write.is_prep) { + m_value.addPart(param->write.value, param->write.len); + m_writeEvt = true; + } else { + setValue(param->write.value, param->write.len); + } + + log_d(" - Response to write event: New value: handle: %.2x, uuid: %s", getHandle(), getUUID().toString().c_str()); + +// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not +// "DEBUG". As it is quite CPU intensive, it is much better to not call it if not needed. +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + char *pHexData = BLEUtils::buildHexData(nullptr, param->write.value, param->write.len); + log_d(" - Data: length: %d, data: %s", param->write.len, pHexData); + free(pHexData); +#endif + + // Invoke the onWrite callback handler before sending the response. + // This ensures that when the client receives the acknowledgment, the write has been processed. + if (param->write.is_prep != true) { + m_pCallbacks->onWrite(this, param); + } + + if (param->write.need_rsp) { + esp_gatt_rsp_t rsp; + + rsp.attr_value.len = param->write.len; + rsp.attr_value.handle = m_handle; + rsp.attr_value.offset = param->write.offset; + rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; + memcpy(rsp.attr_value.value, param->write.value, param->write.len); + + esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, ESP_GATT_OK, &rsp); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + } // Response needed + } // Match on handles. + break; + } // ESP_GATTS_WRITE_EVT + + // ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived. + // + // read: + // - uint16_t conn_id + // - uint32_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool is_long + // - bool need_rsp + // + case ESP_GATTS_READ_EVT: + { + if (param->read.handle == m_handle) { + + // Check for authorization requirement + if (m_permissions & ESP_GATT_PERM_READ_AUTHORIZATION) { + bool authorized = false; + + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("Authorization required for read operation. Checking authorization..."); + authorized = BLEDevice::m_securityCallbacks->onAuthorizationRequest(param->read.conn_id, m_handle, true); + } else { + log_w("onAuthorizationRequest not implemented. Rejecting read authorization request"); + } + + if (!authorized) { + log_i("Read authorization rejected"); + if (param->read.need_rsp) { + esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_INSUF_AUTHORIZATION, nullptr); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_send_response (authorization failed): rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + } + return; // Exit early, don't process the read + } else { + log_i("Read authorization granted"); + } + } + + // Here's an interesting thing. The read request has the option of saying whether we need a response + // or not. What would it "mean" to receive a read request and NOT send a response back? That feels like + // a very strange read. + // + // We have to handle the case where the data we wish to send back to the client is greater than the maximum + // packet size of 22 bytes. In this case, we become responsible for chunking the data into units of 22 bytes. + // The apparent algorithm is as follows: + // + // If the is_long flag is set then this is a follow on from an original read and we will already have sent at least 22 bytes. + // If the is_long flag is not set then we need to check how much data we are going to send. If we are sending LESS than + // 22 bytes, then we "just" send it and that's the end of the story. + // If we are sending 22 bytes exactly, we just send it BUT we will get a follow on request. + // If we are sending more than 22 bytes, we send the first 22 bytes and we will get a follow on request. + // Because of follow on request processing, we need to maintain an offset of how much data we have already sent + // so that when a follow on request arrives, we know where to start in the data to send the next sequence. + // Note that the indication that the client will send a follow on request is that we sent exactly 22 bytes as a response. + // If our payload is divisible by 22 then the last response will be a response of 0 bytes in length. + // + // The following code has deliberately not been factored to make it fewer statements because this would cloud the + // the logic flow comprehension. + // + + // get mtu for peer device that we are sending read request to + uint16_t maxOffset = getService()->getServer()->getPeerMTU(param->read.conn_id) - 1; + log_d("mtu value: %d", maxOffset); + if (param->read.need_rsp) { + log_d("Sending a response (esp_ble_gatts_send_response)"); + esp_gatt_rsp_t rsp; + + if (param->read.is_long) { + String value = m_value.getValue(); + + if (value.length() - m_value.getReadOffset() < maxOffset) { + // This is the last in the chain + rsp.attr_value.len = value.length() - m_value.getReadOffset(); + rsp.attr_value.offset = m_value.getReadOffset(); + memcpy(rsp.attr_value.value, value.c_str() + rsp.attr_value.offset, rsp.attr_value.len); + m_value.setReadOffset(0); + } else { + // There will be more to come. + rsp.attr_value.len = maxOffset; + rsp.attr_value.offset = m_value.getReadOffset(); + memcpy(rsp.attr_value.value, value.c_str() + rsp.attr_value.offset, rsp.attr_value.len); + m_value.setReadOffset(rsp.attr_value.offset + maxOffset); + } + } else { // read.is_long == false + + // If is.long is false then this is the first (or only) request to read data, so invoke the callback + // Invoke the read callback. + m_pCallbacks->onRead(this, param); + + String value = m_value.getValue(); + + if (value.length() + 1 > maxOffset) { + // Too big for a single shot entry. + m_value.setReadOffset(maxOffset); + rsp.attr_value.len = maxOffset; + rsp.attr_value.offset = 0; + memcpy(rsp.attr_value.value, value.c_str(), rsp.attr_value.len); + } else { + // Will fit in a single packet with no callbacks required. + rsp.attr_value.len = value.length(); + rsp.attr_value.offset = 0; + memcpy(rsp.attr_value.value, value.c_str(), rsp.attr_value.len); + } + } + rsp.attr_value.handle = param->read.handle; + rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE; + +// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not +// "DEBUG". As it is quite CPU intensive, it is much better to not call it if not needed. +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + char *pHexData = BLEUtils::buildHexData(nullptr, rsp.attr_value.value, rsp.attr_value.len); + log_d(" - Data: length=%d, data=%s, offset=%d", rsp.attr_value.len, pHexData, rsp.attr_value.offset); + free(pHexData); +#endif + + esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_OK, &rsp); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + } // Response needed + } // Handle matches this characteristic. + break; + } // ESP_GATTS_READ_EVT + + // ESP_GATTS_CONF_EVT + // + // conf: + // - esp_gatt_status_t status – The status code. + // - uint16_t conn_id – The connection used. + // + case ESP_GATTS_CONF_EVT: + { + // log_d("m_handle = %d, conf->handle = %d", m_handle, param->conf.handle); + if (param->conf.conn_id + == getService()->getServer()->getConnId()) { // && param->conf.handle == m_handle) // bug in esp-idf and not implemented in arduino yet + m_semaphoreConfEvt.give(param->conf.status); + } + break; + } + + case ESP_GATTS_CONNECT_EVT: + { + break; + } + + case ESP_GATTS_DISCONNECT_EVT: + { + m_semaphoreConfEvt.give(); + break; + } + + default: + { + break; + } // default + + } // switch event + + // Give each of the descriptors associated with this characteristic the opportunity to handle the + // event. + + m_descriptorMap.handleGATTServerEvent(event, gatts_if, param); + log_v("<< handleGATTServerEvent"); +} // handleGATTServerEvent + +/** + * @brief Send a notify. + * A notification is a transmission of up to the first 20 bytes of the characteristic value. An notification + * will not block; it is a fire and forget. + * @return N/A. + */ +void BLECharacteristic::notify(bool is_notification) { + log_v(">> notify: length: %d", m_value.getValue().length()); + + assert(getService() != nullptr); + assert(getService()->getServer() != nullptr); + + m_pCallbacks->onNotify(this); // Invoke the notify callback. + + // GeneralUtils::hexDump() doesn't output anything if the log level is not + // "VERBOSE". Additionally, it is very CPU intensive, even when it doesn't + // output anything! So it is much better to *not* call it at all if not needed. + // In a simple program which calls BLECharacteristic::notify() every 50 ms, + // the performance gain of this little optimization is 37% in release mode + // (-O3) and 57% in debug mode. + // Of course, the "#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE" guard + // could also be put inside the GeneralUtils::hexDump() function itself. But + // it's better to put it here also, as it is clearer (indicating a verbose log + // thing) and it allows to remove the "m_value.getValue().c_str()" call, which + // is, in itself, quite CPU intensive. +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + GeneralUtils::hexDump((uint8_t *)m_value.getValue().c_str(), m_value.getValue().length()); +#endif + + if (getService()->getServer()->getConnectedCount() == 0) { + log_v("<< notify: No connected clients."); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NO_CLIENT, 0); + return; + } + + // Test to see if we have a 0x2902 descriptor. If we do, then check to see if notification is enabled + // and, if not, prevent the notification. + + BLE2902 *p2902 = (BLE2902 *)getDescriptorByUUID((uint16_t)0x2902); + if (is_notification) { + if (p2902 != nullptr && !p2902->getNotifications()) { + log_v("<< notifications disabled; ignoring"); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NOTIFY_DISABLED, 0); // Invoke the notify callback. + return; + } + } else { + if (p2902 != nullptr && !p2902->getIndications()) { + log_v("<< indications disabled; ignoring"); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_DISABLED, 0); // Invoke the notify callback. + return; + } + } + for (auto &myPair : getService()->getServer()->getPeerDevices(false)) { + uint16_t _mtu = (myPair.second.mtu); + if (m_value.getValue().length() > _mtu - 3) { + log_w("- Truncating to %d bytes (maximum notify size)", _mtu - 3); + } + + size_t length = m_value.getValue().length(); + if (!is_notification) { // is indication + m_semaphoreConfEvt.take("indicate"); + } + esp_err_t errRc = ::esp_ble_gatts_send_indicate( + getService()->getServer()->getGattsIf(), myPair.first, getHandle(), length, (uint8_t *)m_value.getValue().c_str(), !is_notification + ); // The need_confirm = false makes this a notify. + if (errRc != ESP_OK) { + log_e("<< esp_ble_gatts_send_ %s: rc=%d %s", is_notification ? "notify" : "indicate", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreConfEvt.give(); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_GATT, errRc); // Invoke the notify callback. + return; + } + if (!is_notification) { // is indication + if (!m_semaphoreConfEvt.timedWait("indicate", indicationTimeout)) { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_TIMEOUT, 0); // Invoke the notify callback. + } else { + auto code = (esp_gatt_status_t)m_semaphoreConfEvt.value(); + if (code == ESP_GATT_OK) { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_INDICATE, code); // Invoke the notify callback. + } else { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_FAILURE, code); + } + } + } else { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_NOTIFY, 0); // Invoke the notify callback. + } + } + log_v("<< notify"); +} // Notify + +void BLECharacteristicCallbacks::onRead(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param) { + onRead(pCharacteristic); +} // onRead + +void BLECharacteristicCallbacks::onWrite(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param) { + onWrite(pCharacteristic); +} // onWrite + +#endif /* CONFIG_BLUEDROID_ENABLED */ + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +int BLECharacteristic::handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, struct ble_gatt_access_ctxt *ctxt, void *arg) { + const ble_uuid_t *uuid; + int rc; + struct ble_gap_conn_desc desc; + BLECharacteristic *pCharacteristic = (BLECharacteristic *)arg; + + log_d("Characteristic %s %s event", pCharacteristic->getUUID().toString().c_str(), ctxt->op == BLE_GATT_ACCESS_OP_READ_CHR ? "Read" : "Write"); + + uuid = ctxt->chr->uuid; + if (ble_uuid_cmp(uuid, &pCharacteristic->getUUID().getNative()->u) == 0) { + switch (ctxt->op) { + case BLE_GATT_ACCESS_OP_READ_CHR: + { + // Only call the onRead() callback if the buffer length is greater than 0 and conn_handle is not NONE + // For long reads, follow-up requests will have om_len == 0 + if (ctxt->om->om_len > 0 && conn_handle != BLE_HS_CONN_HANDLE_NONE) { + rc = ble_gap_conn_find(conn_handle, &desc); + assert(rc == 0); + pCharacteristic->m_pCallbacks->onRead(pCharacteristic, &desc); + } + + portENTER_CRITICAL(&pCharacteristic->m_readMux); + rc = os_mbuf_append(ctxt->om, (uint8_t *)pCharacteristic->m_value.getValue().c_str(), pCharacteristic->m_value.getValue().length()); + portEXIT_CRITICAL(&pCharacteristic->m_readMux); + + return rc == 0 ? 0 : BLE_ATT_ERR_INSUFFICIENT_RES; + } + + case BLE_GATT_ACCESS_OP_WRITE_CHR: + { + if (ctxt->om->om_len > BLE_ATT_ATTR_MAX_LEN) { + return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } + + uint8_t buf[BLE_ATT_ATTR_MAX_LEN]; + size_t len = ctxt->om->om_len; + memcpy(buf, ctxt->om->om_data, len); + + os_mbuf *next; + next = SLIST_NEXT(ctxt->om, om_next); + while (next != NULL) { + if ((len + next->om_len) > BLE_ATT_ATTR_MAX_LEN) { + return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } + memcpy(&buf[len], next->om_data, next->om_len); + len += next->om_len; + next = SLIST_NEXT(next, om_next); + } + rc = ble_gap_conn_find(conn_handle, &desc); + assert(rc == 0); + pCharacteristic->setValue(buf, len); + + // Call the onWrite callback before returning. + // NOTE: This callback is executed synchronously in the NimBLE GATT access context. + // NimBLE sends the write response automatically after this function returns, + // based on its return code. As a result, any work performed in onWrite() + // directly impacts when the client receives the ATT write acknowledgment. + // + // Behavioral change: + // In earlier implementations that used a deferred callback mechanism, the write + // response was sent before the onWrite() callback executed. Applications that + // relied on that behavior (e.g., long-running or blocking onWrite() handlers, + // or handlers that perform notify/indicate operations) may now experience + // delayed write acknowledgments if onWrite() takes significant time to complete. + // + // Recommendation: + // Implement onWrite() as a fast, non-blocking callback. Offload long-running + // processing to another task or queue to avoid increasing write latency or + // causing client timeouts. + pCharacteristic->m_pCallbacks->onWrite(pCharacteristic, &desc); + + return 0; + } + + default: break; + } + } + + return BLE_ATT_ERR_UNLIKELY; + + //m_descriptorMap.handleGATTServerEvent(conn_handle, attr_handle, ctxt, arg); +} + +/** + * @brief Set the subscribe status for this characteristic.\n + * This will maintain a vector of subscribed clients and their indicate/notify status. + */ +void BLECharacteristic::setSubscribe(struct ble_gap_event *event) { + ble_gap_conn_desc desc; + if (ble_gap_conn_find(event->subscribe.conn_handle, &desc) != 0) { + return; + } + + uint16_t subVal = 0; + if (event->subscribe.cur_notify > 0 && (m_properties & BLECharacteristic::PROPERTY_NOTIFY)) { + subVal |= NIMBLE_SUB_NOTIFY; + } + if (event->subscribe.cur_indicate && (m_properties & BLECharacteristic::PROPERTY_INDICATE)) { + subVal |= NIMBLE_SUB_INDICATE; + } + + log_i("New subscribe value for conn: %d val: %d", event->subscribe.conn_handle, subVal); + + if (!event->subscribe.cur_indicate && event->subscribe.prev_indicate) { + BLEDevice::getServer()->clearIndicateWait(event->subscribe.conn_handle); + } + + auto it = m_subscribedVec.begin(); + for (; it != m_subscribedVec.end(); ++it) { + if ((*it).first == event->subscribe.conn_handle) { + break; + } + } + + if (subVal > 0) { + if (it == m_subscribedVec.end()) { + m_subscribedVec.push_back({event->subscribe.conn_handle, subVal}); + } else { + (*it).second = subVal; + } + } else if (it != m_subscribedVec.end()) { + m_subscribedVec.erase(it); + } + + m_pCallbacks->onSubscribe(this, &desc, subVal); +} + +/** + * @brief Send a notify. + * A notification is a transmission of up to the first 20 bytes of the characteristic value. An notification + * will not block; it is a fire and forget. + * @return N/A. + */ +void BLECharacteristic::notify(bool is_notification) { + log_v(">> notify: length: %d", m_value.getValue().length()); + + assert(getService() != nullptr); + assert(getService()->getServer() != nullptr); + + int rc = 0; + m_pCallbacks->onNotify(this); // Invoke the notify callback. + + // GeneralUtils::hexDump() doesn't output anything if the log level is not + // "VERBOSE". Additionally, it is very CPU intensive, even when it doesn't + // output anything! So it is much better to *not* call it at all if not needed. + // In a simple program which calls BLECharacteristic::notify() every 50 ms, + // the performance gain of this little optimization is 37% in release mode + // (-O3) and 57% in debug mode. + // Of course, the "#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE" guard + // could also be put inside the GeneralUtils::hexDump() function itself. But + // it's better to put it here also, as it is clearer (indicating a verbose log + // thing) and it allows to remove the "m_value.getValue().c_str()" call, which + // is, in itself, quite CPU intensive. +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + GeneralUtils::hexDump((uint8_t *)m_value.getValue().c_str(), m_value.getValue().length()); +#endif + + if (getService()->getServer()->getConnectedCount() == 0) { + log_v("<< notify: No connected clients."); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NO_CLIENT, 0); + return; + } + + if (m_subscribedVec.size() == 0) { + log_v("<< notify: No clients subscribed."); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NO_SUBSCRIBER, 0); + return; + } + + if (is_notification) { + if (!(m_properties & BLECharacteristic::PROPERTY_NOTIFY)) { + log_v("<< notifications disabled; ignoring"); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NOTIFY_DISABLED, 0); // Invoke the notify callback. + return; + } + } else { + if (!(m_properties & BLECharacteristic::PROPERTY_INDICATE)) { + log_v("<< indications disabled; ignoring"); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_DISABLED, 0); // Invoke the notify callback. + return; + } + } + + bool reqSec = (m_properties & BLE_GATT_CHR_F_READ_AUTHEN) || (m_properties & BLE_GATT_CHR_F_READ_AUTHOR) || (m_properties & BLE_GATT_CHR_F_READ_ENC); + + for (auto &myPair : m_subscribedVec) { + uint16_t _mtu = getService()->getServer()->getPeerMTU(myPair.first); + + // check if connected and subscribed + if (_mtu == 0 || myPair.second == 0) { + continue; + } + + if (reqSec) { + struct ble_gap_conn_desc desc; + rc = ble_gap_conn_find(myPair.first, &desc); + if (rc != 0 || !desc.sec_state.encrypted) { + continue; + } + } + + String value = getValue(); + size_t length = value.length(); + + if (length > _mtu - 3) { + log_w("- Truncating to %d bytes (maximum notify size)", _mtu - 3); + } + + if (is_notification && (!(myPair.second & NIMBLE_SUB_NOTIFY))) { + log_w("Sending notification to client subscribed to indications, sending indication instead"); + is_notification = false; + } + + if (!is_notification && (!(myPair.second & NIMBLE_SUB_INDICATE))) { + log_w("Sending indication to client subscribed to notification, sending notification instead"); + is_notification = true; + } + + if (!is_notification) { // is indication + m_semaphoreConfEvt.take("indicate"); + } + + // don't create the m_buf until we are sure to send the data or else + // we could be allocating a buffer that doesn't get released. + // We also must create it in each loop iteration because it is consumed with each host call. + os_mbuf *om = ble_hs_mbuf_from_flat((uint8_t *)value.c_str(), length); + + if (!is_notification && (m_properties & BLECharacteristic::PROPERTY_INDICATE)) { + if (!BLEDevice::getServer()->setIndicateWait(myPair.first)) { + log_e("prior Indication in progress"); + os_mbuf_free_chain(om); + return; + } + + rc = ble_gatts_indicate_custom(myPair.first, m_handle, om); + if (rc != 0) { + BLEDevice::getServer()->clearIndicateWait(myPair.first); + } + } else { + rc = ble_gatts_notify_custom(myPair.first, m_handle, om); + } + + if (rc != 0) { + log_e("<< ble_gatts_%s_custom: rc=%d %s", is_notification ? "notify" : "indicate", rc, GeneralUtils::errorToString(rc)); + m_semaphoreConfEvt.give(); + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_GATT, rc); // Invoke the notify callback. + return; + } + + if (!is_notification) { // is indication + if (!m_semaphoreConfEvt.timedWait("indicate", indicationTimeout)) { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_TIMEOUT, 0); // Invoke the notify callback. + } else { + auto code = m_semaphoreConfEvt.value(); + if (code == ESP_OK) { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_INDICATE, code); // Invoke the notify callback. + } else { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_FAILURE, code); + } + } + } else { + m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_NOTIFY, 0); // Invoke the notify callback. + } + } + log_v("<< notify"); +} // Notify + +void BLECharacteristicCallbacks::onRead(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc) { + onRead(pCharacteristic); +} // onRead + +void BLECharacteristicCallbacks::onWrite(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc) { + onWrite(pCharacteristic); +} // onWrite + +void BLECharacteristicCallbacks::onSubscribe(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc, uint16_t subValue) { + log_d(">> onSubscribe: default"); + log_d("<< onSubscribe"); +} // onSubscribe + +#endif /* CONFIG_NIMBLE_ENABLED */ + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLECharacteristic.h b/libraries/BLE/src/BLECharacteristic.h new file mode 100644 index 0000000..cf70e28 --- /dev/null +++ b/libraries/BLE/src/BLECharacteristic.h @@ -0,0 +1,337 @@ +/* + * BLECharacteristic.h + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_ +#define COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include "BLEUUID.h" +#include "BLEDescriptor.h" +#include "BLEValue.h" +#include "RTOS.h" +#include "BLEUtils.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#include "BLEConnInfo.h" +#include +#include +#define ESP_GATT_MAX_ATTR_LEN BLE_ATT_ATTR_MAX_LEN +#define ESP_GATT_CHAR_PROP_BIT_READ BLE_GATT_CHR_PROP_READ +#define ESP_GATT_CHAR_PROP_BIT_WRITE BLE_GATT_CHR_PROP_WRITE +#define ESP_GATT_CHAR_PROP_BIT_WRITE_NR BLE_GATT_CHR_PROP_WRITE_NO_RSP +#define ESP_GATT_CHAR_PROP_BIT_BROADCAST BLE_GATT_CHR_PROP_BROADCAST +#define ESP_GATT_CHAR_PROP_BIT_NOTIFY BLE_GATT_CHR_PROP_NOTIFY +#define ESP_GATT_CHAR_PROP_BIT_INDICATE BLE_GATT_CHR_PROP_INDICATE +#endif + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef uint16_t esp_gatt_char_prop_t; +typedef uint16_t esp_gatt_perm_t; +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEService; +class BLEDescriptor; +class BLECharacteristicCallbacks; + +/** + * @brief A management structure for %BLE descriptors. + */ +class BLEDescriptorMap { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + void setByUUID(const char *uuid, BLEDescriptor *pDescriptor); + void setByUUID(BLEUUID uuid, BLEDescriptor *pDescriptor); + void setByHandle(uint16_t handle, BLEDescriptor *pDescriptor); + BLEDescriptor *getByUUID(const char *uuid) const; + BLEDescriptor *getByUUID(BLEUUID uuid) const; + BLEDescriptor *getByHandle(uint16_t handle) const; + String toString() const; + BLEDescriptor *getFirst(); + BLEDescriptor *getNext(); + int getRegisteredDescriptorCount() const; + void removeDescriptor(BLEDescriptor *pDescriptor); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, ble_gatt_access_ctxt *ctxt, void *arg); +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + std::map m_uuidMap; + std::map m_handleMap; + std::map::iterator m_iterator; +}; + +/** + * @brief The model of a %BLE Characteristic. + * + * A BLE Characteristic is an identified value container that manages a value. It is exposed by a BLE server and + * can be read and written to by a %BLE client. + */ +class BLECharacteristic { +public: + /*************************************************************************** + * Common properties * + ***************************************************************************/ + + static const uint32_t indicationTimeout = 1000; + + /*************************************************************************** + * Bluedroid public properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static const uint32_t PROPERTY_READ = 1 << 0; + static const uint32_t PROPERTY_READ_ENC = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_READ_AUTHEN = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_READ_AUTHOR = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_WRITE = 1 << 1; + static const uint32_t PROPERTY_WRITE_NR = 1 << 5; + static const uint32_t PROPERTY_WRITE_ENC = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_WRITE_AUTHEN = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_WRITE_AUTHOR = 0; // Not supported by Bluedroid. Use setAccessPermissions() instead. + static const uint32_t PROPERTY_NOTIFY = 1 << 2; + static const uint32_t PROPERTY_BROADCAST = 1 << 3; + static const uint32_t PROPERTY_INDICATE = 1 << 4; +#endif + + /*************************************************************************** + * NimBLE public properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static const uint32_t PROPERTY_READ = BLE_GATT_CHR_F_READ; + static const uint32_t PROPERTY_READ_ENC = BLE_GATT_CHR_F_READ_ENC; + static const uint32_t PROPERTY_READ_AUTHEN = BLE_GATT_CHR_F_READ_AUTHEN; + static const uint32_t PROPERTY_READ_AUTHOR = BLE_GATT_CHR_F_READ_AUTHOR; + static const uint32_t PROPERTY_WRITE = BLE_GATT_CHR_F_WRITE; + static const uint32_t PROPERTY_WRITE_NR = BLE_GATT_CHR_F_WRITE_NO_RSP; + static const uint32_t PROPERTY_WRITE_ENC = BLE_GATT_CHR_F_WRITE_ENC; + static const uint32_t PROPERTY_WRITE_AUTHEN = BLE_GATT_CHR_F_WRITE_AUTHEN; + static const uint32_t PROPERTY_WRITE_AUTHOR = BLE_GATT_CHR_F_WRITE_AUTHOR; + static const uint32_t PROPERTY_NOTIFY = BLE_GATT_CHR_F_NOTIFY; + static const uint32_t PROPERTY_BROADCAST = BLE_GATT_CHR_F_BROADCAST; + static const uint32_t PROPERTY_INDICATE = BLE_GATT_CHR_F_INDICATE; +#endif + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLECharacteristic(const char *uuid, uint32_t properties = 0); + BLECharacteristic(BLEUUID uuid, uint32_t properties = 0); + virtual ~BLECharacteristic(); + + void addDescriptor(BLEDescriptor *pDescriptor); + BLEDescriptor *getDescriptorByUUID(const char *descriptorUUID) const; + BLEDescriptor *getDescriptorByUUID(BLEUUID descriptorUUID) const; + BLEUUID getUUID() const; + String getValue() const; + uint8_t *getData(); + size_t getLength() const; + void indicate(); + void notify(bool is_notification = true); + void setCallbacks(BLECharacteristicCallbacks *pCallbacks); + void setValue(const uint8_t *data, size_t size); + void setValue(const String &value); + void setValue(uint16_t data16); + void setValue(uint32_t data32); + void setValue(int data32); + void setValue(float data32); + void setValue(double data64); + String toString() const; + uint16_t getHandle() const; + void setAccessPermissions(uint16_t perm); + esp_gatt_char_prop_t getProperties() const; + void setReadProperty(bool value); + void setWriteProperty(bool value); + void setNotifyProperty(bool value); + void setBroadcastProperty(bool value); + void setIndicateProperty(bool value); + void setWriteNoResponseProperty(bool value); + +private: + friend class BLEServer; + friend class BLEService; + friend class BLEDescriptor; + friend class BLECharacteristicMap; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLEUUID m_bleUUID; + BLEDescriptorMap m_descriptorMap; + uint16_t m_handle; + esp_gatt_char_prop_t m_properties; + BLECharacteristicCallbacks *m_pCallbacks; + BLEService *m_pService; + BLEValue m_value; + bool m_writeEvt = false; + FreeRTOS::Semaphore m_semaphoreConfEvt = FreeRTOS::Semaphore("ConfEvt"); + FreeRTOS::Semaphore m_semaphoreSetValue = FreeRTOS::Semaphore("SetValue"); + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt"); + esp_gatt_perm_t m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE; +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + portMUX_TYPE m_readMux; + uint8_t m_removed; + std::vector> m_subscribedVec; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void executeCreate(BLEService *pService); + BLEService *getService() const; + void setHandle(uint16_t handle); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void setSubscribe(struct ble_gap_event *event); + static int handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, struct ble_gatt_access_ctxt *ctxt, void *arg); +#endif +}; // BLECharacteristic + +/** + * @brief Callbacks that can be associated with a %BLE characteristic to inform of events. + * + * When a server application creates a %BLE characteristic, we may wish to be informed when there is either + * a read or write request to the characteristic's value. An application can register a + * sub-classed instance of this class and will be notified when such an event happens. + */ +class BLECharacteristicCallbacks { +public: + /*************************************************************************** + * Common public types * + ***************************************************************************/ + + typedef enum { + SUCCESS_INDICATE, + SUCCESS_NOTIFY, + ERROR_INDICATE_DISABLED, + ERROR_NOTIFY_DISABLED, + ERROR_GATT, + ERROR_NO_CLIENT, + ERROR_NO_SUBSCRIBER, + ERROR_INDICATE_TIMEOUT, + ERROR_INDICATE_FAILURE + } Status; + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLECharacteristicCallbacks(); + virtual void onRead(BLECharacteristic *pCharacteristic); + virtual void onWrite(BLECharacteristic *pCharacteristic); + virtual void onNotify(BLECharacteristic *pCharacteristic); + virtual void onStatus(BLECharacteristic *pCharacteristic, Status s, uint32_t code); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + virtual void onRead(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param); + virtual void onWrite(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + virtual void onRead(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc); + virtual void onWrite(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc); + virtual void onSubscribe(BLECharacteristic *pCharacteristic, ble_gap_conn_desc *desc, uint16_t subValue); +#endif +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_ */ diff --git a/libraries/BLE/src/BLECharacteristicMap.cpp b/libraries/BLE/src/BLECharacteristicMap.cpp new file mode 100644 index 0000000..f82f5be --- /dev/null +++ b/libraries/BLE/src/BLECharacteristicMap.cpp @@ -0,0 +1,185 @@ +/* + * BLECharacteristicMap.cpp + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include "BLEService.h" +#include "BLEUtils.h" +#ifdef ARDUINO_ARCH_ESP32 +#include "esp32-hal-log.h" +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Return the characteristic by handle. + * @param [in] handle The handle to look up the characteristic. + * @return The characteristic. + */ +BLECharacteristic *BLECharacteristicMap::getByHandle(uint16_t handle) const { + return m_handleMap.at(handle); +} // getByHandle + +/** + * @brief Return the characteristic by UUID. + * @param [in] UUID The UUID to look up the characteristic. + * @return The characteristic. + */ +BLECharacteristic *BLECharacteristicMap::getByUUID(const char *uuid) const { + return getByUUID(BLEUUID(uuid)); +} + +/** + * @brief Return the characteristic by UUID. + * @param [in] UUID The UUID to look up the characteristic. + * @return The characteristic. + */ +BLECharacteristic *BLECharacteristicMap::getByUUID(BLEUUID uuid) const { + for (auto &myPair : m_uuidMap) { + if (myPair.first->getUUID().equals(uuid)) { + return myPair.first; + } + } + //return m_uuidMap.at(uuid.toString()); + return nullptr; +} // getByUUID + +/** + * @brief Get the first characteristic in the map. + * @return The first characteristic in the map. + */ +BLECharacteristic *BLECharacteristicMap::getFirst() { + m_iterator = m_uuidMap.begin(); + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLECharacteristic *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getFirst + +/** + * @brief Get the next characteristic in the map. + * @return The next characteristic in the map. + */ +BLECharacteristic *BLECharacteristicMap::getNext() { + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLECharacteristic *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getNext + +/** + * @brief Get the number of registered characteristics. + * @return The number of registered characteristics. + */ +int BLECharacteristicMap::getRegisteredCharacteristicCount() const { + return m_uuidMap.size(); +} // getRegisteredCharacteristicCount + +/** + * @brief Removes characteristic from maps. + * @param [in] characteristic The characteristic to remove. + * @return N/A. + */ +void BLECharacteristicMap::removeCharacteristic(BLECharacteristic *characteristic) { + m_handleMap.erase(characteristic->getHandle()); + m_uuidMap.erase(characteristic); +} // removeCharacteristic + +/** + * @brief Set the characteristic by handle. + * @param [in] handle The handle of the characteristic. + * @param [in] characteristic The characteristic to cache. + * @return N/A. + */ +void BLECharacteristicMap::setByHandle(uint16_t handle, BLECharacteristic *characteristic) { + m_handleMap.insert(std::pair(handle, characteristic)); +} // setByHandle + +/** + * @brief Set the characteristic by UUID. + * @param [in] uuid The uuid of the characteristic. + * @param [in] characteristic The characteristic to cache. + * @return N/A. + */ +void BLECharacteristicMap::setByUUID(BLECharacteristic *pCharacteristic, BLEUUID uuid) { + m_uuidMap.insert(std::pair(pCharacteristic, uuid.toString())); +} // setByUUID + +/** + * @brief Return a string representation of the characteristic map. + * @return A string representation of the characteristic map. + */ +String BLECharacteristicMap::toString() const { + String res; + int count = 0; + char hex[5]; + for (auto &myPair : m_uuidMap) { + if (count > 0) { + res += "\n"; + } + snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle()); + count++; + res += "handle: 0x"; + res += hex; + res += ", uuid: " + myPair.first->getUUID().toString(); + } + return res; +} // toString + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +/** + * @brief Pass the GATT server event onwards to each of the characteristics found in the mapping + * @param [in] event + * @param [in] gatts_if + * @param [in] param + */ +void BLECharacteristicMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + // Invoke the handler for every Service we have. + for (auto &myPair : m_uuidMap) { + myPair.first->handleGATTServerEvent(event, gatts_if, param); + } +} // handleGATTServerEvent +#endif // CONFIG_BLUEDROID_ENABLED + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +void BLECharacteristicMap::handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, ble_gatt_access_ctxt *ctxt, void *arg) { + // Invoke the handler for every Service we have. + for (auto &myPair : m_uuidMap) { + myPair.first->handleGATTServerEvent(conn_handle, attr_handle, ctxt, arg); + } +} +#endif // CONFIG_NIMBLE_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEClient.cpp b/libraries/BLE/src/BLEClient.cpp new file mode 100644 index 0000000..61cc749 --- /dev/null +++ b/libraries/BLE/src/BLEClient.cpp @@ -0,0 +1,1478 @@ +/* + * BLEDevice.cpp + * + * Created on: Mar 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "Arduino.h" +#if SOC_BLE_SUPPORTED +#include +#endif +#include "BLEClient.h" +#include "BLEUtils.h" +#include "BLEService.h" +#include "GeneralUtils.h" +#include +#include +#include +#include "BLEDevice.h" +#include "esp32-hal-log.h" +#include "BLESecurity.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#include +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#include +#include +#endif + +/*************************************************************************** + * Common global variables * + ***************************************************************************/ + +static BLEClientCallbacks defaultCallbacks; + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/* + * Design + * ------ + * When we perform a searchService() requests, we are asking the BLE server to return each of the services + * that it exposes. For each service, we received an ESP_GATTC_SEARCH_RES_EVT event which contains details + * of the exposed service including its UUID. + * + * The objects we will invent for a BLEClient will be as follows: + * * BLERemoteService - A model of a remote service. + * * BLERemoteCharacteristic - A model of a remote characteristic + * * BLERemoteDescriptor - A model of a remote descriptor. + * + * Since there is a hierarchical relationship here, we will have the idea that from a BLERemoteService will own + * zero or more remote characteristics and a BLERemoteCharacteristic will own zero or more remote BLEDescriptors. + * + * We will assume that a BLERemoteService contains a map that maps BLEUUIDs to the set of owned characteristics + * and that a BLECharacteristic contains a map that maps BLEUUIDs to the set of owned descriptors. + * + * + */ + +BLEClient::BLEClient() { + m_pClientCallbacks = &defaultCallbacks; + m_conn_id = ESP_GATT_IF_NONE; + m_haveServices = false; + m_isConnected = false; // Initially, we are flagged as not connected. + +#if defined(CONFIG_BLUEDROID_ENABLED) + m_gattc_if = ESP_GATT_IF_NONE; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_connectTimeout = 30000; + m_pTaskData = nullptr; + m_lastErr = 0; + m_terminateFailCount = 0; + + m_pConnParams.scan_itvl = 16; // Scan interval in 0.625ms units (NimBLE Default) + m_pConnParams.scan_window = 16; // Scan window in 0.625ms units (NimBLE Default) + m_pConnParams.itvl_min = BLE_GAP_INITIAL_CONN_ITVL_MIN; // min_int = 0x10*1.25ms = 20ms + m_pConnParams.itvl_max = BLE_GAP_INITIAL_CONN_ITVL_MAX; // max_int = 0x20*1.25ms = 40ms + m_pConnParams.latency = BLE_GAP_INITIAL_CONN_LATENCY; // number of packets allowed to skip (extends max interval) + m_pConnParams.supervision_timeout = BLE_GAP_INITIAL_SUPERVISION_TIMEOUT; // timeout = 400*10ms = 4000ms + m_pConnParams.min_ce_len = BLE_GAP_INITIAL_CONN_MIN_CE_LEN; // Minimum length of connection event in 0.625ms units + m_pConnParams.max_ce_len = BLE_GAP_INITIAL_CONN_MAX_CE_LEN; // Maximum length of connection event in 0.625ms units +#endif +} // BLEClient + +/** + * @brief Destructor. + */ +BLEClient::~BLEClient() { + // We may have allocated service references associated with this client. Before we are finished + // with the client, we must release resources. + for (auto &myPair : m_servicesMap) { + delete myPair.second; + } + m_servicesMap.clear(); + m_servicesMapByInstID.clear(); +} // ~BLEClient + +/** + * @brief Clear any existing services. + * + */ +void BLEClient::clearServices() { + log_v(">> clearServices"); + // Delete all the services. + for (auto &myPair : m_servicesMap) { + delete myPair.second; + } + m_servicesMap.clear(); + m_haveServices = false; + log_v("<< clearServices"); +} // clearServices + +/** + * Add overloaded function to ease connect to peer device with not public address + */ +bool BLEClient::connect(BLEAdvertisedDevice *device) { + BLEAddress address = device->getAddress(); + uint8_t type = device->getAddressType(); + return connect(address, type); +} + +/** + * Add overloaded function to ease connect to peer device with not public address + */ +bool BLEClient::connectTimeout(BLEAdvertisedDevice *device, uint32_t timeoutMs) { + BLEAddress address = device->getAddress(); + uint8_t type = device->getAddressType(); + return connect(address, type, timeoutMs); +} + +esp_gatt_if_t BLEClient::getGattcIf() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return m_gattc_if; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + log_e("NimBLE does not support getGattcIf()"); + return ESP_GATT_IF_NONE; +#endif +} // getGattcIf + +/** + * @brief Initiate a secure connection (pair/bond) with the server.\n + * Called automatically when a characteristic or descriptor requires encryption or authentication to access it. + * @return True on success. + */ +bool BLEClient::secureConnection() { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_i("secureConnection() does not need to be called for Bluedroid"); + return true; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + int retryCount = 1; + BLETaskData taskData(const_cast(this), BLE_HS_ENOTCONN); + m_pTaskData = &taskData; + + do { + if (BLESecurity::startSecurity(m_conn_id)) { + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + } + + } while (taskData.m_flags == (BLE_HS_ERR_HCI_BASE + BLE_ERR_PINKEY_MISSING) && retryCount--); + + m_pTaskData = nullptr; + + if (taskData.m_flags == 0) { + log_d("<< secureConnection: success"); + return true; + } + + m_lastErr = taskData.m_flags; + log_e("secureConnection: failed rc=%d", taskData.m_flags); + return false; +#endif +} // secureConnection + +uint16_t BLEClient::getConnId() { + return m_conn_id; +} // getConnId + +/** + * @brief Retrieve the address of the peer. + * + * Returns the Bluetooth device address of the %BLE peer to which this client is connected. + */ +BLEAddress BLEClient::getPeerAddress() { + return m_peerAddress; +} // getAddress + +/** + * @brief Ask the BLE server for the RSSI value. + * @return The RSSI value. + */ +int BLEClient::getRssi() { + log_v(">> getRssi()"); + if (!isConnected()) { + log_v("<< getRssi(): Not connected"); + return 0; + } + +#if defined(CONFIG_BLUEDROID_ENABLED) + // We make the API call to read the RSSI value which is an asynchronous operation. We expect to receive + // an ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT to indicate completion. + // + m_semaphoreRssiCmplEvt.take("getRssi"); + esp_err_t rc = ::esp_ble_gap_read_rssi(getPeerAddress().getNative()); + if (rc != ESP_OK) { + log_e("<< getRssi: esp_ble_gap_read_rssi: rc=%d %s", rc, GeneralUtils::errorToString(rc)); + return 0; + } + int rssiValue = m_semaphoreRssiCmplEvt.wait("getRssi"); +#endif // CONFIG_BLUEDROID_ENABLED + +#if defined(CONFIG_NIMBLE_ENABLED) + int8_t rssiValue = 0; + int rc = ble_gap_conn_rssi(m_conn_id, &rssiValue); + if (rc != 0) { + log_e("<< getRssi: ble_gap_conn_rssi: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + return 0; + } +#endif // CONFIG_BLUEDROID_ENABLED + log_v("<< getRssi(): %d", rssiValue); + return rssiValue; +} // getRssi + +/** + * @brief Get the service BLE Remote Service instance corresponding to the uuid. + * @param [in] uuid The UUID of the service being sought. + * @return A reference to the Service or nullptr if don't know about it. + */ +BLERemoteService *BLEClient::getService(const char *uuid) { + return getService(BLEUUID(uuid)); +} // getService + +/** + * @brief Get the service object corresponding to the uuid. + * @param [in] uuid The UUID of the service being sought. + * @return A reference to the Service or nullptr if don't know about it. + * @throws BLEUuidNotFound + */ +BLERemoteService *BLEClient::getService(BLEUUID uuid) { + log_v(">> getService: uuid: %s", uuid.toString().c_str()); + // Design + // ------ + // We wish to retrieve the service given its UUID. It is possible that we have not yet asked the + // device what services it has in which case we have nothing to match against. If we have not + // asked the device about its services, then we do that now. Once we get the results we can then + // examine the services map to see if it has the service we are looking for. + if (!m_haveServices) { + getServices(); + } + std::string uuidStr = uuid.toString().c_str(); + for (auto &myPair : m_servicesMap) { + if (myPair.first == uuidStr) { + log_v("<< getService: found the service with uuid: %s", uuid.toString().c_str()); + return myPair.second; + } + } // End of each of the services. + log_v("<< getService: not found"); + return nullptr; +} // getService + +/** + * @brief Get the value of a specific characteristic associated with a specific service. + * @param [in] serviceUUID The service that owns the characteristic. + * @param [in] characteristicUUID The characteristic whose value we wish to read. + * @throws BLEUuidNotFound + */ +String BLEClient::getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID) { + log_v(">> getValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str()); + String ret = getService(serviceUUID)->getCharacteristic(characteristicUUID)->readValue(); + log_v("<> setValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str()); + getService(serviceUUID)->getCharacteristic(characteristicUUID)->writeValue(value); + log_v("<< setValue"); +} // setValue + +uint16_t BLEClient::getMTU() { +#ifdef CONFIG_BLUEDROID_ENABLED + return m_mtu; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + return ble_att_mtu(m_conn_id); +#endif +} + +/** + @brief Set the local and remote MTU size. + Should be called once after client connects if MTU size needs to be changed. + @return bool indicating if MTU was successfully set locally and on remote. +*/ +bool BLEClient::setMTU(uint16_t mtu) { + log_v(">> setMTU: %d", mtu); + esp_err_t err = ESP_OK; + +#ifdef CONFIG_BLUEDROID_ENABLED + err = esp_ble_gatt_set_local_mtu(mtu); //First must set local MTU value. +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + err = ble_att_set_preferred_mtu(mtu); +#endif + + if (err == ESP_OK) { +#ifdef CONFIG_BLUEDROID_ENABLED + err = esp_ble_gattc_send_mtu_req(m_gattc_if, m_conn_id); //Once local is set successfully set remote size +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + //err = ble_gattc_exchange_mtu(m_conn_id, nullptr, nullptr); +#endif + + if (err != ESP_OK) { + log_e("Error setting send MTU request MTU: %d err=%d", mtu, err); + return false; + } + } else { + log_e("can't set local mtu value: %d", mtu); + return false; + } + log_v("<< setMTU"); + + m_mtu = mtu; //successfully changed + + return true; +} + +/** + * @brief Return a string representation of this client. + * @return A string representation of this client. + */ +String BLEClient::toString() { + String res = "peer address: " + m_peerAddress.toString(); + res += "\nServices:\n"; + for (auto &myPair : m_servicesMap) { + res += myPair.second->toString() + "\n"; + // myPair.second is the value + } + return res; +} // toString + +void BLEClientCallbacks::onConnect(BLEClient *pClient) { + log_d("BLEClientCallbacks", "onConnect: default"); +} + +void BLEClientCallbacks::onDisconnect(BLEClient *pClient) { + log_d("BLEClientCallbacks", "onDisconnect: default"); +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Connect to the partner (BLE Server). + * @param [in] address The address of the partner. + * @param [in] type The type of the address. + * @param [in] timeoutMs The number of milliseconds to wait for the connection to complete. + * @return True on success. + */ +bool BLEClient::connect(BLEAddress address, uint8_t type, uint32_t timeoutMs) { + log_i(">> connect(%s)", address.toString().c_str()); + + // Use explicitly provided type, or fall back to the address's stored type + if (type == 0xFF) { + type = address.getType(); + } + + // Configuration for retry logic + const int maxRetries = 3; + const int retryDelayMs = 100; + int retryCount = 0; + esp_err_t errRc; + uint32_t rc; + + // Validate address + if (address == BLEAddress("")) { + log_e("Invalid peer address (NULL)"); + return false; + } + + // Check if already connected + if (m_isConnected) { + log_e("Client already connected to %s", m_peerAddress.toString().c_str()); + return false; + } + + // Stop any active scan before connecting - scanning can interfere with connection establishment + BLEScan *pScan = BLEDevice::getScan(); + if (pScan != nullptr && pScan->isScanning()) { + log_i("Stopping scan before connecting..."); + pScan->stop(); + delay(50); // Give the BLE stack time to settle after stopping scan + } + + // We need the connection handle that we get from registering the application. We register the app + // and then block on its completion. When the event has arrived, we will have the handle. + m_appId = BLEDevice::m_appId++; + BLEDevice::addPeerDevice(this, true, m_appId); + m_semaphoreRegEvt.take("connect"); + + // clearServices(); // we dont need to delete services since every client is unique? + log_d("Registering GATT client app (appId=%d)...", m_appId); + errRc = ::esp_ble_gattc_app_register(m_appId); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_app_register: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + BLEDevice::removePeerDevice(m_appId, true); + return false; + } + + rc = m_semaphoreRegEvt.wait("connect"); + + if (rc != ESP_GATT_OK) { + // fixes ESP_GATT_NO_RESOURCES error mostly + log_e("esp_ble_gattc_app_register_error: rc=%d", rc); + BLEDevice::removePeerDevice(m_appId, true); + // not sure if this is needed here + // esp_ble_gattc_app_unregister(m_gattc_if); + // m_gattc_if = ESP_GATT_IF_NONE; + return false; + } + + log_d("GATT client registered (gattc_if=%d)", m_gattc_if); + m_peerAddress = address; + + // Perform the open connection request against the target BLE Server with retry logic. + // This helps handle cases where the BLE stack is busy or needs time to settle. + do { + m_semaphoreOpenEvt.take("connect"); + log_d("Opening connection to %s (attempt %d/%d)...", address.toString().c_str(), retryCount + 1, maxRetries + 1); + errRc = ::esp_ble_gattc_open( + m_gattc_if, + getPeerAddress().getNative(), // address + (esp_ble_addr_type_t)type, // Note: This was added on 2018-04-03 when the latest ESP-IDF was detected to have changed the signature. + 1 // direct connection <-- maybe needs to be changed in case of direct indirect connection??? + ); + + if (errRc == ESP_OK) { + log_d("esp_ble_gattc_open returned OK, waiting for connection event..."); + break; // Success, exit retry loop + } + + // Handle specific error cases that may benefit from retry + if (errRc == ESP_ERR_INVALID_STATE) { + // BLE stack may be busy, retry after delay + log_w("esp_ble_gattc_open: stack busy (ESP_ERR_INVALID_STATE), retry %d/%d", retryCount + 1, maxRetries); + m_semaphoreOpenEvt.give(ESP_GATT_ERROR); // Release semaphore before retry + delay(retryDelayMs); + retryCount++; + } else { + // Other errors, don't retry + log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreOpenEvt.give(ESP_GATT_ERROR); // Release semaphore before cleanup + BLEDevice::removePeerDevice(m_appId, true); + esp_ble_gattc_app_unregister(m_gattc_if); + m_gattc_if = ESP_GATT_IF_NONE; + return false; + } + } while (retryCount < maxRetries); + + // Check if we exhausted retries + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_open failed after %d retries: rc=%d %s", maxRetries, errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreOpenEvt.give(ESP_GATT_ERROR); // Release semaphore before cleanup + BLEDevice::removePeerDevice(m_appId, true); + esp_ble_gattc_app_unregister(m_gattc_if); + m_gattc_if = ESP_GATT_IF_NONE; + return false; + } + + log_d("Waiting for connection event (timeout=%d ms)...", timeoutMs); + bool got_sem = m_semaphoreOpenEvt.timedWait("connect", timeoutMs); // Wait for the connection to complete. + rc = m_semaphoreOpenEvt.value(); + + // check the status of the connection and cleanup in case of failure + if (!got_sem) { + log_e("Connection timeout after %d ms to %s (no OPEN event received)", timeoutMs, address.toString().c_str()); + // Cancel any pending connection attempt + esp_ble_gap_disconnect(getPeerAddress().getNative()); + BLEDevice::removePeerDevice(m_appId, true); + esp_ble_gattc_app_unregister(m_gattc_if); + m_gattc_if = ESP_GATT_IF_NONE; + return false; + } + + if (rc != ESP_GATT_OK) { + log_e("Connection failed to %s, status=%d %s", address.toString().c_str(), rc, GeneralUtils::errorToString(rc)); + BLEDevice::removePeerDevice(m_appId, true); + esp_ble_gattc_app_unregister(m_gattc_if); + m_gattc_if = ESP_GATT_IF_NONE; + return false; + } + + log_i("Connected to %s", address.toString().c_str()); + return true; +} // connect + +/** + * @brief Disconnect from the peer. + * @return error code from bluedroid, 0 = success. + */ +int BLEClient::disconnect(uint8_t reason) { + log_v(">> disconnect()"); + esp_err_t errRc = ::esp_ble_gattc_close(getGattcIf(), getConnId()); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_close: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return errRc; + } + log_v("<< disconnect()"); + return ESP_OK; +} // disconnect + +/** + * @brief Update connection parameters. + * + * As the BLE Central (client), this device controls the connection parameters. + * This method directly sets the connection parameters that will be used. + * The peripheral (server) can request parameter changes, but the central makes + * the final decision. + * + * Can only be called after a connection has been established. + * + * @param [in] minInterval The minimum connection interval in 1.25ms units (e.g., 80 = 100ms). + * @param [in] maxInterval The maximum connection interval in 1.25ms units (e.g., 800 = 1000ms). + * @param [in] latency Number of consecutive connection events the peripheral can skip (0-499). + * Higher values save power but increase response latency. + * @param [in] timeout The supervision timeout in 10ms units (e.g., 400 = 4000ms). + * Must be > (1 + latency) * maxInterval * 2. + * @return True on success, false on failure. + */ +bool BLEClient::updateConnParams(uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + log_v(">> updateConnParams()"); + + if (!isConnected()) { + log_e("Not connected, cannot update connection parameters"); + return false; + } + + esp_ble_conn_update_params_t conn_params; + memcpy(conn_params.bda, m_peerAddress.getNative(), sizeof(esp_bd_addr_t)); + conn_params.latency = latency; + conn_params.max_int = maxInterval; // max_int in 1.25ms units + conn_params.min_int = minInterval; // min_int in 1.25ms units + conn_params.timeout = timeout; // timeout in 10ms units + + esp_err_t errRc = esp_ble_gap_update_conn_params(&conn_params); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_update_conn_params: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + + log_v("<< updateConnParams()"); + return true; +} // updateConnParams + +/** + * @brief Handle GATT Client events + */ +void BLEClient::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) { + + log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s", gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str()); + + // it is possible to receive events from other connections while waiting for registration + if (m_gattc_if == ESP_GATT_IF_NONE && event != ESP_GATTC_REG_EVT) { + return; + } + + // Execute handler code based on the type of event received. + switch (event) { + + case ESP_GATTC_SRVC_CHG_EVT: log_i("SERVICE CHANGED"); break; + + case ESP_GATTC_CLOSE_EVT: + { + // esp_ble_gattc_app_unregister(m_appId); + // BLEDevice::removePeerDevice(m_gattc_if, true); + break; + } + + // + // ESP_GATTC_DISCONNECT_EVT + // + // disconnect: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + case ESP_GATTC_DISCONNECT_EVT: + { + if (evtParam->disconnect.conn_id != getConnId()) { + break; + } + // If we receive a disconnect event, set the class flag that indicates that we are + // no longer connected. + bool m_wasConnected = m_isConnected; + m_isConnected = false; + esp_ble_gattc_app_unregister(m_gattc_if); + m_gattc_if = ESP_GATT_IF_NONE; + m_semaphoreOpenEvt.give(ESP_GATT_IF_NONE); + m_semaphoreRssiCmplEvt.give(); + m_semaphoreSearchCmplEvt.give(1); + BLEDevice::removePeerDevice(m_appId, true); + // Reset security state on disconnect + BLESecurity::resetSecurity(); + if (m_wasConnected && m_pClientCallbacks != nullptr) { + m_pClientCallbacks->onDisconnect(this); + } + break; + } // ESP_GATTC_DISCONNECT_EVT + + // + // ESP_GATTC_OPEN_EVT + // + // open: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + // + case ESP_GATTC_OPEN_EVT: + { + m_conn_id = evtParam->open.conn_id; + if (evtParam->open.status == ESP_GATT_OK) { + m_isConnected = true; // Flag us as connected. + if (m_pClientCallbacks != nullptr) { + m_pClientCallbacks->onConnect(this); + } + } else { + log_e("Failed to connect, status=%s", GeneralUtils::errorToString(evtParam->open.status)); + } + m_semaphoreOpenEvt.give(evtParam->open.status); + break; + } // ESP_GATTC_OPEN_EVT + + // + // ESP_GATTC_REG_EVT + // + // reg: + // esp_gatt_status_t status + // uint16_t app_id + // + case ESP_GATTC_REG_EVT: + { + m_gattc_if = gattc_if; + // pass on the registration status result, in case of failure + m_semaphoreRegEvt.give(evtParam->reg.status); + break; + } // ESP_GATTC_REG_EVT + + case ESP_GATTC_CFG_MTU_EVT: + if (evtParam->cfg_mtu.conn_id != getConnId()) { + break; + } + if (evtParam->cfg_mtu.status != ESP_GATT_OK) { + log_e("Config mtu failed"); + } + m_mtu = evtParam->cfg_mtu.mtu; + break; + + case ESP_GATTC_CONNECT_EVT: + { + if (evtParam->connect.conn_id != getConnId()) { + break; + } + BLEDevice::updatePeerDevice(this, true, m_appId); + esp_err_t errRc = esp_ble_gattc_send_mtu_req(gattc_if, evtParam->connect.conn_id); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_send_mtu_req: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + // Set encryption on connect for BlueDroid when security is enabled + // This ensures security is established before any secure operations + if (BLESecurity::m_securityEnabled && BLESecurity::m_forceSecurity) { + BLESecurity::startSecurity(evtParam->connect.remote_bda); + } + break; + } // ESP_GATTC_CONNECT_EVT + + // + // ESP_GATTC_SEARCH_CMPL_EVT + // + // search_cmpl: + // - esp_gatt_status_t status + // - uint16_t conn_id + // + case ESP_GATTC_SEARCH_CMPL_EVT: + { + if (evtParam->search_cmpl.conn_id != getConnId()) { + break; + } + esp_ble_gattc_cb_param_t *p_data = (esp_ble_gattc_cb_param_t *)evtParam; + if (p_data->search_cmpl.status != ESP_GATT_OK) { + log_e("search service failed, error status = %x", p_data->search_cmpl.status); + break; + } +#ifndef ARDUINO_ARCH_ESP32 +// commented out just for now to keep backward compatibility +// if(p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_REMOTE_DEVICE) { +// log_i("Get service information from remote device"); +// } else if (p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_NVS_FLASH) { +// log_i("Get service information from flash"); +// } else { +// log_i("unknown service source"); +// } +#endif + m_semaphoreSearchCmplEvt.give(0); + break; + } // ESP_GATTC_SEARCH_CMPL_EVT + + // + // ESP_GATTC_SEARCH_RES_EVT + // + // search_res: + // - uint16_t conn_id + // - uint16_t start_handle + // - uint16_t end_handle + // - esp_gatt_id_t srvc_id + // + case ESP_GATTC_SEARCH_RES_EVT: + { + if (evtParam->search_res.conn_id != getConnId()) { + break; + } + BLEUUID uuid = BLEUUID(evtParam->search_res.srvc_id); + BLERemoteService *pRemoteService = + new BLERemoteService(evtParam->search_res.srvc_id, this, evtParam->search_res.start_handle, evtParam->search_res.end_handle); + m_servicesMap.insert(std::pair(uuid.toString().c_str(), pRemoteService)); + m_servicesMapByInstID.insert(std::pair(pRemoteService, evtParam->search_res.srvc_id.inst_id)); + break; + } // ESP_GATTC_SEARCH_RES_EVT + + default: + { + break; + } + } // Switch + + // Pass the request on to all services. + for (auto &myPair : m_servicesMap) { + myPair.second->gattClientEventHandler(event, gattc_if, evtParam); + } + +} // gattClientEventHandler + +/** + * @brief Ask the remote %BLE server for its services. + * A %BLE Server exposes a set of services for its partners. Here we ask the server for its set of + * services and wait until we have received them all. + * @return N/A + */ +std::map *BLEClient::getServices() { + /* + * Design + * ------ + * We invoke esp_ble_gattc_search_service. This will request a list of the service exposed by the + * peer BLE partner to be returned as events. Each event will be an an instance of ESP_GATTC_SEARCH_RES_EVT + * and will culminate with an ESP_GATTC_SEARCH_CMPL_EVT when all have been received. + */ + log_v(">> getServices"); + // TODO implement retrieving services from cache + clearServices(); // Clear any services that may exist. + + esp_err_t errRc = esp_ble_gattc_search_service( + getGattcIf(), getConnId(), + NULL // Filter UUID + ); + + m_semaphoreSearchCmplEvt.take("getServices"); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_search_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return &m_servicesMap; + } + // If successful, remember that we now have services. + m_haveServices = (m_semaphoreSearchCmplEvt.wait("getServices") == 0); + log_v("<< getServices"); + return &m_servicesMap; +} // getServices + +/** + * @brief Handle a received GAP event. + * + * @param [in] event + * @param [in] param + */ +void BLEClient::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + log_d("BLEClient ... handling GAP event!"); + switch (event) { + // + // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT + // + // read_rssi_cmpl + // - esp_bt_status_t status + // - int8_t rssi + // - esp_bd_addr_t remote_addr + // + case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT: + { + m_semaphoreRssiCmplEvt.give((uint32_t)param->read_rssi_cmpl.rssi); + break; + } // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT + + default: break; + } +} // handleGAPEvent + +#endif // CONFIG_BLUEDROID_ENABLED + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief If we have asked to disconnect and the event does not + * occur within the supervision timeout + added delay, this will + * be called to reset the host in the case of a stalled controller. + */ +void BLEClient::dcTimerCb(ble_npl_event *event) { + ble_hs_sched_reset(BLE_HS_ECONTROLLER); +} + +/** + * @brief Connect to the partner (BLE Server). + * @param [in] address The address of the partner. + * @param [in] type The type of the address. + * @param [in] timeoutMs The number of milliseconds to wait for the connection to complete. + * @return True on success. + */ +bool BLEClient::connect(BLEAddress address, uint8_t type, uint32_t timeoutMs) { + log_v(">> connect(%s)", address.toString().c_str()); + + if (!BLEDevice::m_synced) { + log_d("BLEClient", "Host reset, wait for sync."); + return false; + } + + if (m_conn_id != BLE_HS_CONN_HANDLE_NONE || m_isConnected || m_pTaskData != nullptr) { + log_e("Client busy, connected to %s, id=%d", m_peerAddress.toString().c_str(), getConnId()); + return false; + } + + // Use explicitly provided type, or fall back to the address's stored type + if (type == 0xFF) { + type = address.getType(); + } + + ble_addr_t peerAddr_t; + memcpy(&peerAddr_t.val, address.getNative(), 6); + peerAddr_t.type = type; + if (ble_gap_conn_find_by_addr(&peerAddr_t, NULL) == 0) { + log_e("A connection to %s already exists", address.toString().c_str()); + return false; + } + + if (address == BLEAddress("")) { + log_e("Invalid peer address (NULL)"); + return false; + } + + m_appId = BLEDevice::m_appId++; + m_peerAddress = address; + + int rc = 0; + + /* Try to connect the the advertiser. Allow 30 seconds (30000 ms) for + * timeout (default value of m_connectTimeout). + * Loop on BLE_HS_EBUSY if the scan hasn't stopped yet. + */ + do { + rc = ble_gap_connect(BLEDevice::m_ownAddrType, &peerAddr_t, m_connectTimeout, &m_pConnParams, BLEClient::handleGAPEvent, this); + switch (rc) { + case 0: break; + + case BLE_HS_EBUSY: + // Scan was still running, stop it and try again + if (!BLEDevice::getScan()->stop()) { + rc = BLE_HS_EUNKNOWN; + } + break; + + case BLE_HS_EDONE: + // A connection to this device already exists, do not connect twice. + log_e("Already connected to device; addr=%s", m_peerAddress.toString().c_str()); + break; + + case BLE_HS_EALREADY: + // Already attempting to connect to this device, cancel the previous + // attempt and report failure here so we don't get 2 connections. + log_e("Already attempting to connect to %s - canceling", m_peerAddress.toString().c_str()); + ble_gap_conn_cancel(); + break; + + default: log_e("Failed to connect to %s, rc=%d; %s", m_peerAddress.toString().c_str(), rc, BLEUtils::returnCodeToString(rc)); break; + } + + } while (rc == BLE_HS_EBUSY); + + if (rc != 0) { + m_lastErr = rc; + return false; + } + + BLETaskData taskData(this); + m_pTaskData = &taskData; + + // Wait for the connect timeout time +1 second for the connection to complete + if (!BLEUtils::taskWait(taskData, m_connectTimeout + 1000)) { + // If a connection was made but no response from MTU exchange proceed anyway + if (isConnected()) { + taskData.m_flags = 0; + } else { + // workaround; if the controller doesn't cancel the connection at the timeout, cancel it here. + log_e("Connect timeout - canceling"); + ble_gap_conn_cancel(); + taskData.m_flags = BLE_HS_ETIMEOUT; + } + } + + m_pTaskData = nullptr; + rc = taskData.m_flags; + + if (rc != 0) { + log_e("Connection failed; status=%d %s", rc, BLEUtils::returnCodeToString(rc)); + m_lastErr = rc; + return false; + } + + m_isConnected = true; + m_pClientCallbacks->onConnect(this); + + log_i("<< connect()"); + + BLEDevice::addPeerDevice(this, true, m_appId); + // Check if still connected before returning + return isConnected(); +} + +/** + * @brief STATIC Callback for the service discovery API function.\n + * When a service is found or there is none left or there was an error + * the API will call this and report findings. + */ +int BLEClient::serviceDiscoveredCB(uint16_t conn_handle, const struct ble_gatt_error *error, const struct ble_gatt_svc *service, void *arg) { + log_d("Service Discovered >> status: %d handle: %d", error->status, (error->status == 0) ? service->start_handle : -1); + + BLETaskData *pTaskData = (BLETaskData *)arg; + BLEClient *client = (BLEClient *)pTaskData->m_pInstance; + + if (error->status == BLE_HS_ENOTCONN) { + log_e("<< Service Discovered; Disconnected"); + BLEUtils::taskRelease(*pTaskData, error->status); + return error->status; + } + + // Make sure the service discovery is for this device + if (client->getConnId() != conn_handle) { + return 0; + } + + if (error->status == 0) { + // Found a service - add it to the vector + BLERemoteService *pRemoteService = new BLERemoteService(client, service); + client->m_servicesMap.insert(std::pair(pRemoteService->getUUID().toString().c_str(), pRemoteService)); + client->m_servicesMapByInstID.insert(std::pair(pRemoteService, service->start_handle)); + return 0; + } + + BLEUtils::taskRelease(*pTaskData, error->status); + log_d("<< Service Discovered"); + return error->status; +} + +std::map *BLEClient::getServices() { + log_v(">> getServices"); + + clearServices(); // Clear any services that may exist. + + if (!isConnected()) { + log_e("Disconnected, could not retrieve services -aborting"); + return &m_servicesMap; + } + + int errRc = 0; + BLETaskData taskData(this); + + errRc = ble_gattc_disc_all_svcs(m_conn_id, BLEClient::serviceDiscoveredCB, &taskData); + + if (errRc != 0) { + log_e("ble_gattc_disc_all_svcs: rc=%d %s", errRc, BLEUtils::returnCodeToString(errRc)); + m_lastErr = errRc; + return &m_servicesMap; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + errRc = taskData.m_flags; + if (errRc == 0 || errRc == BLE_HS_EDONE) { + // If successful, remember that we now have services. + m_haveServices = m_servicesMap.size() > 0; + log_v("<< getServices"); + return &m_servicesMap; + } + + m_lastErr = errRc; + log_e("Could not retrieve services, rc=%d %s", errRc, BLEUtils::returnCodeToString(errRc)); + return &m_servicesMap; +} // getServices + +int BLEClient::handleGAPEvent(struct ble_gap_event *event, void *arg) { + BLEClient *client = (BLEClient *)arg; + int rc = 0; + BLETaskData *pTaskData = client->m_pTaskData; + + log_d("BLEClient", "Got Client event %s", BLEUtils::gapEventToString(event->type)); + + switch (event->type) { + case BLE_GAP_EVENT_DISCONNECT: + { + rc = event->disconnect.reason; + // If Host reset tell the device now before returning to prevent + // any errors caused by calling host functions before resyncing. + switch (rc) { + case BLE_HS_ECONTROLLER: + case BLE_HS_ETIMEOUT_HCI: + case BLE_HS_ENOTSYNCED: + case BLE_HS_EOS: + log_e("BLEClient", "Disconnect - host reset, rc=%d", rc); + BLEDevice::onReset(rc); + break; + default: + // Check that the event is for this client. + if (client->m_conn_id != event->disconnect.conn.conn_handle) { + return 0; + } + break; + } + + // Remove the device from ignore list so we will scan it again + // BLEDevice::removeIgnored(client->m_peerAddress); + + // No longer connected, clear the connection ID. + client->m_conn_id = BLE_HS_CONN_HANDLE_NONE; + client->m_terminateFailCount = 0; + + // If we received a connected event but did not get established (no PDU) + // then a disconnect event will be sent but we should not send it to the + // app for processing. Instead we will ensure the task is released + // and report the error. + if (!client->m_isConnected) { + break; + } + + log_i("BLEClient", "disconnect; reason=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + + BLEDevice::removePeerDevice(client->m_appId, true); + client->m_isConnected = false; + // Reset security state on disconnect + BLESecurity::resetSecurity(); + if (client->m_pClientCallbacks != nullptr) { + client->m_pClientCallbacks->onDisconnect(client); + } + break; + } // BLE_GAP_EVENT_DISCONNECT + + case BLE_GAP_EVENT_CONNECT: + { + // If we aren't waiting for this connection response + // we should drop the connection immediately. + if (client->isConnected() || client->m_pTaskData == nullptr) { + ble_gap_terminate(event->connect.conn_handle, BLE_ERR_REM_USER_CONN_TERM); + return 0; + } + + rc = event->connect.status; + if (rc == 0) { + log_i("BLEClient: Connected event. Handle: %d", event->connect.conn_handle); + + client->m_conn_id = event->connect.conn_handle; + + rc = ble_gattc_exchange_mtu(client->m_conn_id, nullptr, nullptr); + if (rc != 0) { + log_e("BLEClient", "MTU exchange error; rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + break; + } + + if (BLESecurity::m_securityEnabled) { + BLESecurity::startSecurity(client->m_conn_id); + } + + // In the case of a multiconnecting device we ignore this device when + // scanning since we are already connected to it + // BLEDevice::addIgnored(client->m_peerAddress); + } else { + client->m_conn_id = BLE_HS_CONN_HANDLE_NONE; + break; + } + + return 0; + } // BLE_GAP_EVENT_CONNECT + + case BLE_GAP_EVENT_TERM_FAILURE: + { + if (client->m_conn_id != event->term_failure.conn_handle) { + return 0; + } + + log_e("Connection termination failure; rc=%d - retrying", event->term_failure.status); + if (++client->m_terminateFailCount > 2) { + ble_hs_sched_reset(BLE_HS_ECONTROLLER); + } else { + ble_gap_terminate(event->term_failure.conn_handle, BLE_ERR_REM_USER_CONN_TERM); + } + return 0; + } // BLE_GAP_EVENT_TERM_FAILURE + + case BLE_GAP_EVENT_NOTIFY_RX: + { + if (client->m_conn_id != event->notify_rx.conn_handle) { + return 0; + } + + // If a notification comes before this flag is set we might + // access a vector while it is being cleared in connect() + if (!client->m_isConnected) { + return 0; + } + + log_d("BLEClient", "Notify received for handle: %d", event->notify_rx.attr_handle); + + for (auto &myPair : client->m_servicesMap) { + // Dont waste cycles searching services without this handle in its range + if (myPair.second->getEndHandle() < event->notify_rx.attr_handle) { + continue; + } + + // Use m_characteristicMapByHandle for O(log n) lookup by handle + // This fixes issues with multiple characteristics sharing the same UUID (e.g., HID Report Data) + auto &cMapByHandle = myPair.second->m_characteristicMapByHandle; + auto characteristic = cMapByHandle.find(event->notify_rx.attr_handle); + + if (characteristic != cMapByHandle.end()) { + log_d("BLEClient", "Got Notification for characteristic %s (handle: %d)", characteristic->second->toString().c_str(), event->notify_rx.attr_handle); + + characteristic->second->m_semaphoreReadCharEvt.take(); + characteristic->second->m_value = String((char *)event->notify_rx.om->om_data, event->notify_rx.om->om_len); + characteristic->second->m_semaphoreReadCharEvt.give(); + + if (characteristic->second->m_notifyCallback != nullptr) { + log_d("Invoking callback for notification on characteristic %s", characteristic->second->toString().c_str()); + characteristic->second->m_notifyCallback( + characteristic->second, event->notify_rx.om->om_data, event->notify_rx.om->om_len, !event->notify_rx.indication + ); + } + break; + } + } + + return 0; + } // BLE_GAP_EVENT_NOTIFY_RX + + case BLE_GAP_EVENT_CONN_UPDATE_REQ: + case BLE_GAP_EVENT_L2CAP_UPDATE_REQ: + { + if (client->m_conn_id != event->conn_update_req.conn_handle) { + return 0; + } + log_d("Peer requesting to update connection parameters"); + log_d( + "MinInterval: %d, MaxInterval: %d, Latency: %d, Timeout: %d", event->conn_update_req.peer_params->itvl_min, + event->conn_update_req.peer_params->itvl_max, event->conn_update_req.peer_params->latency, event->conn_update_req.peer_params->supervision_timeout + ); + + rc = client->m_pClientCallbacks->onConnParamsUpdateRequest(client, event->conn_update_req.peer_params) ? 0 : BLE_ERR_CONN_PARMS; + + if (!rc && event->type == BLE_GAP_EVENT_CONN_UPDATE_REQ) { + event->conn_update_req.self_params->itvl_min = client->m_pConnParams.itvl_min; + event->conn_update_req.self_params->itvl_max = client->m_pConnParams.itvl_max; + event->conn_update_req.self_params->latency = client->m_pConnParams.latency; + event->conn_update_req.self_params->supervision_timeout = client->m_pConnParams.supervision_timeout; + } + + log_d("%s peer params", (rc == 0) ? "Accepted" : "Rejected"); + return rc; + } // BLE_GAP_EVENT_CONN_UPDATE_REQ, BLE_GAP_EVENT_L2CAP_UPDATE_REQ + + case BLE_GAP_EVENT_CONN_UPDATE: + { + if (client->m_conn_id != event->conn_update.conn_handle) { + return 0; + } + if (event->conn_update.status == 0) { + log_i("Connection parameters updated."); + } else { + log_e("Update connection parameters failed."); + } + return 0; + } // BLE_GAP_EVENT_CONN_UPDATE + + case BLE_GAP_EVENT_ENC_CHANGE: + { + if (client->m_conn_id != event->enc_change.conn_handle) { + return 0; + } + + if (event->enc_change.status == 0 || event->enc_change.status == (BLE_HS_ERR_HCI_BASE + BLE_ERR_PINKEY_MISSING)) { + struct ble_gap_conn_desc desc; + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + assert(rc == 0); + + if (event->enc_change.status == (BLE_HS_ERR_HCI_BASE + BLE_ERR_PINKEY_MISSING)) { + // Key is missing, try deleting. + ble_store_util_delete_peer(&desc.peer_id_addr); + } else if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onAuthenticationComplete(&desc); + } + } + + rc = event->enc_change.status; + break; + } //BLE_GAP_EVENT_ENC_CHANGE + + case BLE_GAP_EVENT_MTU: + { + if (client->m_conn_id != event->mtu.conn_handle) { + return 0; + } + log_i("mtu update event; conn_handle=%d mtu=%d", event->mtu.conn_handle, event->mtu.value); + rc = 0; + break; + } // BLE_GAP_EVENT_MTU + + case BLE_GAP_EVENT_PASSKEY_ACTION: + { + struct ble_sm_io pkey = {0, 0}; + + if (client->m_conn_id != event->passkey.conn_handle) { + return 0; + } + + if (event->passkey.params.action == BLE_SM_IOACT_DISP) { + // Display the passkey on this device + log_d("BLE_SM_IOACT_DISP"); + + pkey.action = event->passkey.params.action; + pkey.passkey = BLESecurity::getPassKey(); // This is the passkey to be entered on peer + + if (!BLESecurity::m_passkeySet) { + log_w("No passkey set"); + } + + if (BLESecurity::m_staticPasskey && pkey.passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", pkey.passkey); + } + + if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onPassKeyNotify(pkey.passkey); + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_NUMCMP) { + // Check if the passkey on the peer device is correct + log_d("BLE_SM_IOACT_NUMCMP"); + + log_d("Passkey on device's display: %d", event->passkey.params.numcmp); + pkey.action = event->passkey.params.action; + + if (BLEDevice::m_securityCallbacks != nullptr) { + pkey.numcmp_accept = BLEDevice::m_securityCallbacks->onConfirmPIN(event->passkey.params.numcmp); + } else { + log_e("onConfirmPIN not implemented. Rejecting connection"); + pkey.numcmp_accept = 0; + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_OOB) { + // Out of band pairing + // TODO: Handle out of band pairing + log_w("BLE_SM_IOACT_OOB: Not implemented"); + + static uint8_t tem_oob[16] = {0}; + pkey.action = event->passkey.params.action; + for (int i = 0; i < 16; i++) { + pkey.oob[i] = tem_oob[i]; + } + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_INPUT) { + // Input passkey from peer device + log_d("BLE_SM_IOACT_INPUT"); + + pkey.action = event->passkey.params.action; + pkey.passkey = BLESecurity::getPassKey(); + + if (!BLESecurity::m_passkeySet) { + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("No passkey set, getting passkey from onPassKeyRequest"); + pkey.passkey = BLEDevice::m_securityCallbacks->onPassKeyRequest(); + } else { + log_w("*ATTENTION* onPassKeyRequest not implemented and no static passkey set."); + } + } + + if (BLESecurity::m_staticPasskey && pkey.passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", pkey.passkey); + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_NONE) { + log_d("BLE_SM_IOACT_NONE"); + log_i("No passkey action required"); + } + + return 0; + } // BLE_GAP_EVENT_PASSKEY_ACTION + + default: + { + return 0; + } + } // Switch + + if (pTaskData != nullptr) { + BLEUtils::taskRelease(*pTaskData, rc); + } + + return 0; +} // handleGAPEvent + +/** + * @brief Disconnect from the peer. + * @return Error code from NimBLE stack, 0 = success. + */ +int BLEClient::disconnect(uint8_t reason) { + log_d(">> disconnect()"); + int rc = 0; + + if (isConnected()) { + rc = ble_gap_terminate(m_conn_id, reason); + if (rc != 0 && rc != BLE_HS_ENOTCONN && rc != BLE_HS_EALREADY) { + m_lastErr = rc; + log_e("ble_gap_terminate failed: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + } + } else { + log_d("Not connected to any peers"); + } + + log_d("<< disconnect()"); + return rc; +} // disconnect + +/** + * @brief Update connection parameters. + * + * As the BLE Central (client), this device controls the connection parameters. + * This method directly sets the connection parameters that will be used. + * The peripheral (server) can request parameter changes, but the central makes + * the final decision. + * + * Can only be called after a connection has been established. + * + * @param [in] minInterval The minimum connection interval in 1.25ms units (e.g., 80 = 100ms). + * @param [in] maxInterval The maximum connection interval in 1.25ms units (e.g., 800 = 1000ms). + * @param [in] latency Number of consecutive connection events the peripheral can skip (0-499). + * Higher values save power but increase response latency. + * @param [in] timeout The supervision timeout in 10ms units (e.g., 400 = 4000ms). + * Must be > (1 + latency) * maxInterval * 2. + * @return True on success, false on failure. + */ +bool BLEClient::updateConnParams(uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + log_d(">> updateConnParams()"); + + if (!isConnected()) { + log_e("Not connected, cannot update connection parameters"); + return false; + } + + ble_gap_upd_params params; + params.itvl_min = minInterval; // min_int in 1.25ms units + params.itvl_max = maxInterval; // max_int in 1.25ms units + params.latency = latency; // slave latency + params.supervision_timeout = timeout; // timeout in 10ms units + params.min_ce_len = BLE_GAP_INITIAL_CONN_MIN_CE_LEN; // Minimum length of connection event in 0.625ms units + params.max_ce_len = BLE_GAP_INITIAL_CONN_MAX_CE_LEN; // Maximum length of connection event in 0.625ms units + + int rc = ble_gap_update_params(m_conn_id, ¶ms); + if (rc != 0) { + log_e("Update params error: %d, %s", rc, BLEUtils::returnCodeToString(rc)); + m_lastErr = rc; + return false; + } + + log_d("<< updateConnParams()"); + return true; +} // updateConnParams + +bool BLEClientCallbacks::onConnParamsUpdateRequest(BLEClient *pClient, const ble_gap_upd_params *params) { + log_d("BLEClientCallbacks", "onConnParamsUpdateRequest: accepting peer's request by default"); + log_d( + "BLEClientCallbacks", "Min Interval: %d (%.2f ms), Max Interval: %d (%.2f ms), Latency: %d, Timeout: %d (%d ms)", params->itvl_min, params->itvl_min * 1.25, + params->itvl_max, params->itvl_max * 1.25, params->latency, params->supervision_timeout, params->supervision_timeout * 10 + ); + return true; +} + +#endif // CONFIG_NIMBLE_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEClient.h b/libraries/BLE/src/BLEClient.h new file mode 100644 index 0000000..80b0474 --- /dev/null +++ b/libraries/BLE/src/BLEClient.h @@ -0,0 +1,232 @@ +/* + * BLEClient.h + * + * Created on: Mar 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef MAIN_BLECLIENT_H_ +#define MAIN_BLECLIENT_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include +#include "BLERemoteService.h" +#include "BLEService.h" +#include "BLEAddress.h" +#include "BLEAdvertisedDevice.h" +#include "BLEUtils.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#ifndef BLE_ERR_REM_USER_CONN_TERM +#define BLE_ERR_REM_USER_CONN_TERM 0x13 +#endif +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#define ESP_GATT_IF_NONE BLE_HS_CONN_HANDLE_NONE +#endif + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef uint16_t esp_gatt_if_t; +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLERemoteService; +class BLEClientCallbacks; +class BLEAdvertisedDevice; +struct BLETaskData; + +/** + * @brief A model of a %BLE client. + */ +class BLEClient { +public: + /*************************************************************************** + * Common public properties * + ***************************************************************************/ + + uint16_t m_appId; + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEClient(); + ~BLEClient(); + bool connect(BLEAdvertisedDevice *device); + bool connectTimeout(BLEAdvertisedDevice *device, uint32_t timeoutMS = portMAX_DELAY); + bool connect(BLEAddress address, uint8_t type = 0xFF, uint32_t timeoutMS = portMAX_DELAY); + bool secureConnection(); + int disconnect(uint8_t reason = BLE_ERR_REM_USER_CONN_TERM); + BLEAddress getPeerAddress(); + int getRssi(); + std::map *getServices(); + BLERemoteService *getService(const char *uuid); + BLERemoteService *getService(BLEUUID uuid); + String getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID); + bool isConnected(); + void setClientCallbacks(BLEClientCallbacks *pClientCallbacks); + void setValue(BLEUUID serviceUUID, BLEUUID characteristicUUID, String value); + String toString(); + uint16_t getConnId(); + esp_gatt_if_t getGattcIf(); + uint16_t getMTU(); + bool setMTU(uint16_t mtu); + bool updateConnParams(uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static int handleGAPEvent(struct ble_gap_event *event, void *arg); + static int serviceDiscoveredCB(uint16_t conn_handle, const struct ble_gatt_error *error, const struct ble_gatt_svc *service, void *arg); +#endif + +private: + friend class BLEDevice; + friend class BLERemoteService; + friend class BLERemoteCharacteristic; + friend class BLERemoteDescriptor; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLEAddress m_peerAddress = BLEAddress((uint8_t *)"\0\0\0\0\0\0"); + uint16_t m_conn_id; + bool m_haveServices = false; + bool m_isConnected = false; + BLEClientCallbacks *m_pClientCallbacks; + FreeRTOS::Semaphore m_semaphoreRegEvt = FreeRTOS::Semaphore("RegEvt"); + FreeRTOS::Semaphore m_semaphoreOpenEvt = FreeRTOS::Semaphore("OpenEvt"); + FreeRTOS::Semaphore m_semaphoreSearchCmplEvt = FreeRTOS::Semaphore("SearchCmplEvt"); + FreeRTOS::Semaphore m_semaphoreRssiCmplEvt = FreeRTOS::Semaphore("RssiCmplEvt"); + std::map m_servicesMap; + std::map m_servicesMapByInstID; + uint16_t m_mtu = 23; + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_gatt_if_t m_gattc_if; +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + int m_lastErr; + int32_t m_connectTimeout; + uint8_t m_terminateFailCount; + ble_gap_conn_params m_pConnParams; + mutable BLETaskData *m_pTaskData; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void clearServices(); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static void dcTimerCb(ble_npl_event *event); +#endif +}; // class BLEClient + +/** + * @brief Callbacks associated with a %BLE client. + */ +class BLEClientCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEClientCallbacks(){}; + virtual void onConnect(BLEClient *pClient); + virtual void onDisconnect(BLEClient *pClient); + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + /** + * @brief Callback when the server requests connection parameter updates. + * + * This callback is invoked when the peripheral (server) requests to update + * connection parameters. The central (client) can accept or reject the request. + * + * NOTE: This callback is NimBLE-only. Bluedroid handles parameter update + * requests automatically within the Bluetooth stack without application-level + * intervention. + * + * @param [in] pClient Pointer to the BLEClient instance. + * @param [in] params Pointer to the requested connection parameters. + * @return true to accept the request, false to reject it. + */ + virtual bool onConnParamsUpdateRequest(BLEClient *pClient, const ble_gap_upd_params *params); +#endif +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* MAIN_BLECLIENT_H_ */ diff --git a/libraries/BLE/src/BLEConnInfo.h b/libraries/BLE/src/BLEConnInfo.h new file mode 100644 index 0000000..b81ab93 --- /dev/null +++ b/libraries/BLE/src/BLEConnInfo.h @@ -0,0 +1,110 @@ +/* + * Copyright 2020-2025 Ryan Powell and + * esp-nimble-cpp, NimBLE-Arduino contributors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLECONNINFO_H_ +#define BLECONNINFO_H_ + +#if defined(CONFIG_NIMBLE_ENABLED) + +#include +#include "BLEAddress.h" + +/** + * @brief Connection information. + */ +class BLEConnInfo { +public: + /** @brief Gets the over-the-air address of the connected peer */ + BLEAddress getAddress() const { + return BLEAddress(m_desc.peer_ota_addr); + } + + /** @brief Gets the ID address of the connected peer */ + BLEAddress getIdAddress() const { + return BLEAddress(m_desc.peer_id_addr); + } + + /** @brief Gets the connection handle (also known as the connection id) of the connected peer */ + uint16_t getConnHandle() const { + return m_desc.conn_handle; + } + + /** @brief Gets the connection interval for this connection (in 1.25ms units) */ + uint16_t getConnInterval() const { + return m_desc.conn_itvl; + } + + /** @brief Gets the supervision timeout for this connection (in 10ms units) */ + uint16_t getConnTimeout() const { + return m_desc.supervision_timeout; + } + + /** @brief Gets the allowable latency for this connection (unit = number of intervals) */ + uint16_t getConnLatency() const { + return m_desc.conn_latency; + } + + /** @brief Gets the maximum transmission unit size for this connection (in bytes) */ + uint16_t getMTU() const { + return ble_att_mtu(m_desc.conn_handle); + } + + /** @brief Check if we are in the master role in this connection */ + bool isMaster() const { + return (m_desc.role == BLE_GAP_ROLE_MASTER); + } + + /** @brief Check if we are in the slave role in this connection */ + bool isSlave() const { + return (m_desc.role == BLE_GAP_ROLE_SLAVE); + } + + /** @brief Check if we are connected to a bonded peer */ + bool isBonded() const { + return (m_desc.sec_state.bonded == 1); + } + + /** @brief Check if the connection in encrypted */ + bool isEncrypted() const { + return (m_desc.sec_state.encrypted == 1); + } + + /** @brief Check if the the connection has been authenticated */ + bool isAuthenticated() const { + return (m_desc.sec_state.authenticated == 1); + } + + /** @brief Gets the key size used to encrypt the connection */ + uint8_t getSecKeySize() const { + return m_desc.sec_state.key_size; + } + +private: + friend class BLEServer; + friend class BLEClient; + friend class BLECharacteristic; + friend class BLEDescriptor; + + ble_gap_conn_desc m_desc{}; + BLEConnInfo(){}; + BLEConnInfo(ble_gap_conn_desc desc) { + m_desc = desc; + } +}; +#endif + +#endif // BLECONNINFO_H_ diff --git a/libraries/BLE/src/BLEDescriptor.cpp b/libraries/BLE/src/BLEDescriptor.cpp new file mode 100644 index 0000000..ad2112b --- /dev/null +++ b/libraries/BLE/src/BLEDescriptor.cpp @@ -0,0 +1,423 @@ +/* + * BLEDescriptor.cpp + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Apr 3, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include +#include +#include "sdkconfig.h" +#include +#include "BLE2904.h" +#include "BLEService.h" +#include "BLEDescriptor.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include "BLE2902.h" +#include "BLEDevice.h" +#endif + +/*************************************************************************** + * Common definitions * + ***************************************************************************/ + +#define NULL_HANDLE (0xffff) + +/*************************************************************************** + * Common global variables * + ***************************************************************************/ + +static BLEDescriptorCallbacks defaultCallbacks; + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief BLEDescriptor constructor. + */ +BLEDescriptor::BLEDescriptor(const char *uuid, uint16_t len) : BLEDescriptor(BLEUUID(uuid), len) {} + +/** + * @brief BLEDescriptor constructor. + */ +BLEDescriptor::BLEDescriptor(BLEUUID uuid, uint16_t max_len) { + m_bleUUID = uuid; + m_handle = NULL_HANDLE; // Handle is initially unknown. + m_pCharacteristic = nullptr; // No initial characteristic. + m_pCallback = nullptr; // No initial callback. + m_value.attr_len = 0; // Initial length is 0. + m_value.attr_max_len = max_len; // Maximum length of the data. + m_value.attr_value = (uint8_t *)malloc(max_len); // Allocate storage for the value. +#if CONFIG_NIMBLE_ENABLED + m_removed = 0; +#endif +} // BLEDescriptor + +/** + * @brief BLEDescriptor destructor. + */ +BLEDescriptor::~BLEDescriptor() { + free(m_value.attr_value); // Release the storage we created in the constructor. +} // ~BLEDescriptor + +/** + * @brief Execute the creation of the descriptor with the BLE runtime in ESP. + * @param [in] pCharacteristic The characteristic to which to register this descriptor. + */ +void BLEDescriptor::executeCreate(BLECharacteristic *pCharacteristic) { + log_v(">> executeCreate(): %s", toString().c_str()); + + if (m_handle != NULL_HANDLE) { + log_e("Descriptor already has a handle."); + return; + } + + m_pCharacteristic = pCharacteristic; // Save the characteristic associated with this service. + +#if CONFIG_BLUEDROID_ENABLED + esp_attr_control_t control; + control.auto_rsp = ESP_GATT_AUTO_RSP; + m_semaphoreCreateEvt.take("executeCreate"); + esp_err_t errRc = + ::esp_ble_gatts_add_char_descr(pCharacteristic->getService()->getHandle(), getUUID().getNative(), (esp_gatt_perm_t)m_permissions, &m_value, &control); + if (errRc != ESP_OK) { + log_e("<< esp_ble_gatts_add_char_descr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return; + } + + m_semaphoreCreateEvt.wait("executeCreate"); +#endif + log_v("<< executeCreate"); +} // executeCreate + +/** + * @brief Get the BLE handle for this descriptor. + * @return The handle for this descriptor. + */ +uint16_t BLEDescriptor::getHandle() const { + return m_handle; +} // getHandle + +/** + * @brief Get the length of the value of this descriptor. + * @return The length (in bytes) of the value of this descriptor. + */ +size_t BLEDescriptor::getLength() const { + return m_value.attr_len; +} // getLength + +/** + * @brief Get the UUID of the descriptor. + */ +BLEUUID BLEDescriptor::getUUID() const { + return m_bleUUID; +} // getUUID + +/** + * @brief Get the value of this descriptor. + * @return A pointer to the value of this descriptor. + */ +uint8_t *BLEDescriptor::getValue() const { + return m_value.attr_value; +} // getValue + +/** + * @brief Get the characteristic this descriptor belongs to. + * @return A pointer to the characteristic this descriptor belongs to. + */ +BLECharacteristic *BLEDescriptor::getCharacteristic() const { + return m_pCharacteristic; +} // getCharacteristic + +/** + * @brief Set the callback handlers for this descriptor. + * @param [in] pCallbacks An instance of a callback structure used to define any callbacks for the descriptor. + */ +void BLEDescriptor::setCallbacks(BLEDescriptorCallbacks *pCallback) { + log_v(">> setCallbacks: 0x%x", (uint32_t)pCallback); + if (pCallback != nullptr) { + m_pCallback = pCallback; + } else { + m_pCallback = &defaultCallbacks; + } + log_v("<< setCallbacks"); +} // setCallbacks + +/** + * @brief Set the handle of this descriptor. + * Set the handle of this descriptor to be the supplied value. + * @param [in] handle The handle to be associated with this descriptor. + * @return N/A. + */ +void BLEDescriptor::setHandle(uint16_t handle) { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_v(">> setHandle(0x%.2x): Setting descriptor handle to be 0x%.2x", handle, handle); + m_handle = handle; + log_v("<< setHandle()"); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + log_w("NimBLE does not support manually setting the handle of a descriptor. Ignoring request."); +#endif +} // setHandle + +/** + * @brief Set the value of the descriptor. + * @param [in] data The data to set for the descriptor. + * @param [in] length The length of the data in bytes. + */ +void BLEDescriptor::setValue(const uint8_t *data, size_t length) { + if (length > m_value.attr_max_len) { + log_e("Size %d too large, must be no bigger than %d", length, m_value.attr_max_len); + return; + } + + m_semaphoreSetValue.take(); + m_value.attr_len = length; + memcpy(m_value.attr_value, data, length); +#if CONFIG_BLUEDROID_ENABLED + if (m_handle != NULL_HANDLE) { + esp_ble_gatts_set_attr_value(m_handle, length, (const uint8_t *)data); + log_d("Set the value in the GATTS database using handle 0x%x", m_handle); + } +#endif + m_semaphoreSetValue.give(); +} // setValue + +/** + * @brief Set the value of the descriptor. + * @param [in] value The value of the descriptor in string form. + */ +void BLEDescriptor::setValue(const String &value) { + setValue(reinterpret_cast(value.c_str()), value.length()); +} // setValue + +void BLEDescriptor::setAccessPermissions(uint16_t perm) { + m_permissions = perm; +} + +/** + * @brief Return a string representation of the descriptor. + * @return A string representation of the descriptor. + */ +String BLEDescriptor::toString() const { + char hex[5]; + snprintf(hex, sizeof(hex), "%04x", m_handle); + String res = "UUID: " + m_bleUUID.toString() + ", handle: 0x" + hex; + return res; +} // toString + +BLEDescriptorCallbacks::~BLEDescriptorCallbacks() = default; + +/** + * @brief Callback function to support a read request. + * @param [in] pDescriptor The descriptor that is the source of the event. + */ +void BLEDescriptorCallbacks::onRead(BLEDescriptor *pDescriptor) { + log_d("BLEDescriptorCallbacks", ">> onRead: default"); + log_d("BLEDescriptorCallbacks", "<< onRead"); +} // onRead + +/** + * @brief Callback function to support a write request. + * @param [in] pDescriptor The descriptor that is the source of the event. + */ +void BLEDescriptorCallbacks::onWrite(BLEDescriptor *pDescriptor) { + log_d("BLEDescriptorCallbacks", ">> onWrite: default"); + log_d("BLEDescriptorCallbacks", "<< onWrite"); +} // onWrite + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Handle GATT server events for the descripttor. + * @param [in] event + * @param [in] gatts_if + * @param [in] param + */ +void BLEDescriptor::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + switch (event) { + // ESP_GATTS_ADD_CHAR_DESCR_EVT + // + // add_char_descr: + // - esp_gatt_status_t status + // - uint16_t attr_handle + // - uint16_t service_handle + // - esp_bt_uuid_t char_uuid + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + { + if (m_pCharacteristic != nullptr && m_bleUUID.equals(BLEUUID(param->add_char_descr.descr_uuid)) + && m_pCharacteristic->getService()->getHandle() == param->add_char_descr.service_handle + && m_pCharacteristic == m_pCharacteristic->getService()->getLastCreatedCharacteristic()) { + setHandle(param->add_char_descr.attr_handle); + m_semaphoreCreateEvt.give(); + } + break; + } // ESP_GATTS_ADD_CHAR_DESCR_EVT + + // ESP_GATTS_WRITE_EVT - A request to write the value of a descriptor has arrived. + // + // write: + // - uint16_t conn_id + // - uint16_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool need_rsp + // - bool is_prep + // - uint16_t len + // - uint8_t *value + case ESP_GATTS_WRITE_EVT: + { + if (param->write.handle == m_handle) { + setValue(param->write.value, param->write.len); // Set the value of the descriptor. + + // If this is a CCCD (0x2902), persist the value for bonded device reconnection + if (m_bleUUID.equals(BLEUUID((uint16_t)0x2902)) && m_pCharacteristic != nullptr) { + BLE2902 *pCCCD = (BLE2902 *)this; + BLEAddress peerAddr(param->write.bda); + uint16_t charHandle = m_pCharacteristic->getHandle(); + pCCCD->persistValue(peerAddr, charHandle); + log_d( + "CCCD write from %s: notifications=%s, indications=%s", peerAddr.toString().c_str(), pCCCD->getNotifications() ? "enabled" : "disabled", + pCCCD->getIndications() ? "enabled" : "disabled" + ); + } + + if (m_pCallback != nullptr) { // We have completed the write, if there is a user supplied callback handler, invoke it now. + m_pCallback->onWrite(this); // Invoke the onWrite callback handler. + } + } // End of ... this is our handle. + + break; + } // ESP_GATTS_WRITE_EVT + + // ESP_GATTS_READ_EVT - A request to read the value of a descriptor has arrived. + // + // read: + // - uint16_t conn_id + // - uint32_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool is_long + // - bool need_rsp + // + case ESP_GATTS_READ_EVT: + { + if (param->read.handle == m_handle) { // If this event is for this descriptor ... process it + + if (m_pCallback != nullptr) { // If we have a user supplied callback, invoke it now. + m_pCallback->onRead(this); // Invoke the onRead callback method in the callback handler. + } + + } // End of this is our handle + break; + } // ESP_GATTS_READ_EVT + + default: break; + } // switch event +} // handleGATTServerEvent + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Handle GATT server events for the descriptor. + * @param [in] conn_handle The connection handle. + * @param [in] attr_handle The attribute handle. + * @param [in] ctxt The GATT access context. + * @param [in] arg The argument. + */ +int BLEDescriptor::handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, struct ble_gatt_access_ctxt *ctxt, void *arg) { + const ble_uuid_t *uuid; + int rc; + BLEDescriptor *pDescriptor = (BLEDescriptor *)arg; + + log_d("Descriptor %s %s event", pDescriptor->getUUID().toString().c_str(), ctxt->op == BLE_GATT_ACCESS_OP_READ_DSC ? "Read" : "Write"); + + uuid = ctxt->chr->uuid; + if (ble_uuid_cmp(uuid, &pDescriptor->getUUID().getNative()->u) == 0) { + switch (ctxt->op) { + case BLE_GATT_ACCESS_OP_READ_DSC: + { + // Only call the onRead() callback if the buffer length is greater than 0 and conn_handle is not NONE + // For long reads, follow-up requests will have om_len == 0 + if (ctxt->om->om_len > 0 && conn_handle != BLE_HS_CONN_HANDLE_NONE && pDescriptor->m_pCallback != nullptr) { + pDescriptor->m_pCallback->onRead(pDescriptor); + } + + ble_npl_hw_enter_critical(); + rc = os_mbuf_append(ctxt->om, pDescriptor->m_value.attr_value, pDescriptor->m_value.attr_len); + ble_npl_hw_exit_critical(0); + return rc == 0 ? 0 : BLE_ATT_ERR_INSUFFICIENT_RES; + } + + case BLE_GATT_ACCESS_OP_WRITE_DSC: + { + uint16_t att_max_len = pDescriptor->m_value.attr_max_len; + + if (ctxt->om->om_len > att_max_len) { + return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } + + uint8_t buf[att_max_len]; + size_t len = ctxt->om->om_len; + memcpy(buf, ctxt->om->om_data, len); + os_mbuf *next; + next = SLIST_NEXT(ctxt->om, om_next); + while (next != NULL) { + if ((len + next->om_len) > att_max_len) { + return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } + memcpy(&buf[len], next->om_data, next->om_len); + len += next->om_len; + next = SLIST_NEXT(next, om_next); + } + + pDescriptor->setValue(buf, len); + if (pDescriptor->m_pCallback != nullptr) { + pDescriptor->m_pCallback->onWrite(pDescriptor); + } + return 0; + } + + default: break; + } + } + + return BLE_ATT_ERR_UNLIKELY; +} + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEDescriptor.h b/libraries/BLE/src/BLEDescriptor.h new file mode 100644 index 0000000..be10779 --- /dev/null +++ b/libraries/BLE/src/BLEDescriptor.h @@ -0,0 +1,187 @@ +/* + * BLEDescriptor.h + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_ +#define COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLEUUID.h" +#include "BLECharacteristic.h" +#include "RTOS.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include "BLEConnInfo.h" + +// Bluedroid compatibility +// NimBLE does not support signed reads and writes + +#define ESP_GATT_PERM_READ BLE_ATT_F_READ +#define ESP_GATT_PERM_WRITE BLE_ATT_F_WRITE +#define ESP_GATT_PERM_READ_ENCRYPTED BLE_ATT_F_READ_ENC +#define ESP_GATT_PERM_WRITE_ENCRYPTED BLE_ATT_F_WRITE_ENC +#define ESP_GATT_PERM_READ_AUTHORIZATION BLE_ATT_F_READ_AUTHOR +#define ESP_GATT_PERM_WRITE_AUTHORIZATION BLE_ATT_F_WRITE_AUTHOR +#define ESP_GATT_PERM_READ_ENC_MITM BLE_ATT_F_READ_AUTHEN +#define ESP_GATT_PERM_WRITE_ENC_MITM BLE_ATT_F_WRITE_AUTHEN + +#endif + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef struct { + uint16_t attr_max_len; /*!< attribute max value length */ + uint16_t attr_len; /*!< attribute current value length */ + uint8_t *attr_value; /*!< the pointer to attribute value */ +} esp_attr_value_t; +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEService; +class BLECharacteristic; +class BLEDescriptorCallbacks; + +/** + * @brief A model of a %BLE descriptor. + */ +class BLEDescriptor { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEDescriptor(const char *uuid, uint16_t max_len = 100); + BLEDescriptor(BLEUUID uuid, uint16_t max_len = 100); + virtual ~BLEDescriptor(); + + uint16_t getHandle() const; // Get the handle of the descriptor. + size_t getLength() const; // Get the length of the value of the descriptor. + BLEUUID getUUID() const; // Get the UUID of the descriptor. + uint8_t *getValue() const; // Get a pointer to the value of the descriptor. + BLECharacteristic *getCharacteristic() const; // Get the characteristic that this descriptor belongs to. + + void setAccessPermissions(uint16_t perm); // Set the permissions of the descriptor. + void setCallbacks(BLEDescriptorCallbacks *pCallbacks); // Set callbacks to be invoked for the descriptor. + void setValue(const uint8_t *data, size_t size); // Set the value of the descriptor as a pointer to data. + void setValue(const String &value); // Set the value of the descriptor as a data buffer. + + String toString() const; // Convert the descriptor to a string representation. + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static int handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, struct ble_gatt_access_ctxt *ctxt, void *arg); +#endif + +private: + friend class BLEDescriptorMap; + friend class BLECharacteristic; + friend class BLEService; + friend class BLE2901; + friend class BLE2902; + friend class BLE2904; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLEUUID m_bleUUID; + uint16_t m_handle; + esp_attr_value_t m_value; + BLEDescriptorCallbacks *m_pCallback; + BLECharacteristic *m_pCharacteristic; + FreeRTOS::Semaphore m_semaphoreSetValue = FreeRTOS::Semaphore("SetValue"); + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt"); + uint16_t m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE; +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + uint8_t m_permissions = HA_FLAG_PERM_RW; + uint8_t m_removed = 0; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void executeCreate(BLECharacteristic *pCharacteristic); + void setHandle(uint16_t handle); +}; // BLEDescriptor + +/** + * @brief Callbacks that can be associated with a %BLE descriptors to inform of events. + * + * When a server application creates a %BLE descriptor, we may wish to be informed when there is either + * a read or write request to the descriptors value. An application can register a + * sub-classed instance of this class and will be notified when such an event happens. + */ +class BLEDescriptorCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEDescriptorCallbacks(); + virtual void onRead(BLEDescriptor *pDescriptor); + virtual void onWrite(BLEDescriptor *pDescriptor); +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_ */ diff --git a/libraries/BLE/src/BLEDescriptorMap.cpp b/libraries/BLE/src/BLEDescriptorMap.cpp new file mode 100644 index 0000000..39a54dc --- /dev/null +++ b/libraries/BLE/src/BLEDescriptorMap.cpp @@ -0,0 +1,215 @@ +/* + * BLEDescriptorMap.cpp + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include "BLECharacteristic.h" +#include "BLEDescriptor.h" +#ifdef ARDUINO_ARCH_ESP32 +#include "esp32-hal-log.h" +#endif + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include // ESP32 BLE +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include "host/ble_gatt.h" +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Return the descriptor by UUID. + * @param [in] UUID The UUID to look up the descriptor. + * @return The descriptor. If not present, then nullptr is returned. + */ +BLEDescriptor *BLEDescriptorMap::getByUUID(const char *uuid) const { + return getByUUID(BLEUUID(uuid)); +} + +/** + * @brief Return the descriptor by UUID. + * @param [in] UUID The UUID to look up the descriptor. + * @return The descriptor. If not present, then nullptr is returned. + */ +BLEDescriptor *BLEDescriptorMap::getByUUID(BLEUUID uuid) const { + for (auto &myPair : m_uuidMap) { + if (myPair.first->getUUID().equals(uuid)) { + return myPair.first; + } + } + //return m_uuidMap.at(uuid.toString()); + return nullptr; +} // getByUUID + +/** + * @brief Return the descriptor by handle. + * @param [in] handle The handle to look up the descriptor. + * @return The descriptor. + */ +BLEDescriptor *BLEDescriptorMap::getByHandle(uint16_t handle) const { + return m_handleMap.at(handle); +} // getByHandle + +/** + * @brief Set the descriptor by UUID. + * @param [in] uuid The uuid of the descriptor. + * @param [in] characteristic The descriptor to cache. + * @return N/A. + */ +void BLEDescriptorMap::setByUUID(const char *uuid, BLEDescriptor *pDescriptor) { + m_uuidMap.insert(std::pair(pDescriptor, uuid)); +} // setByUUID + +/** + * @brief Set the descriptor by UUID. + * @param [in] uuid The uuid of the descriptor. + * @param [in] characteristic The descriptor to cache. + * @return N/A. + */ +void BLEDescriptorMap::setByUUID(BLEUUID uuid, BLEDescriptor *pDescriptor) { + m_uuidMap.insert(std::pair(pDescriptor, uuid.toString())); +} // setByUUID + +/** + * @brief Set the descriptor by handle. + * @param [in] handle The handle of the descriptor. + * @param [in] descriptor The descriptor to cache. + * @return N/A. + */ +void BLEDescriptorMap::setByHandle(uint16_t handle, BLEDescriptor *pDescriptor) { + m_handleMap.insert(std::pair(handle, pDescriptor)); +} // setByHandle + +/** + * @brief Get the number of registered descriptors. + * @return The number of registered descriptors. + */ +int BLEDescriptorMap::getRegisteredDescriptorCount() const { + return m_uuidMap.size(); +} + +/** + * @brief Remove a descriptor from the map. + * @param [in] pDescriptor The descriptor to remove. + * @return N/A. + */ +void BLEDescriptorMap::removeDescriptor(BLEDescriptor *pDescriptor) { + m_uuidMap.erase(pDescriptor); + m_handleMap.erase(pDescriptor->getHandle()); +} + +/** + * @brief Return a string representation of the descriptor map. + * @return A string representation of the descriptor map. + */ +String BLEDescriptorMap::toString() const { + String res; + char hex[5]; + int count = 0; + for (auto &myPair : m_uuidMap) { + if (count > 0) { + res += "\n"; + } + snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle()); + count++; + res += "handle: 0x"; + res += hex; + res += ", uuid: " + myPair.first->getUUID().toString(); + } + return res; +} // toString + +/** + * @brief Get the first descriptor in the map. + * @return The first descriptor in the map. + */ +BLEDescriptor *BLEDescriptorMap::getFirst() { + m_iterator = m_uuidMap.begin(); + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLEDescriptor *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getFirst + +/** + * @brief Get the next descriptor in the map. + * @return The next descriptor in the map. + */ +BLEDescriptor *BLEDescriptorMap::getNext() { + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLEDescriptor *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getNext + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Pass the GATT server event onwards to each of the descriptors found in the mapping + * @param [in] event + * @param [in] gatts_if + * @param [in] param + */ +void BLEDescriptorMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + // Invoke the handler for every descriptor we have. + for (auto &myPair : m_uuidMap) { + myPair.first->handleGATTServerEvent(event, gatts_if, param); + } +} // handleGATTServerEvent + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +void BLEDescriptorMap::handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, ble_gatt_access_ctxt *ctxt, void *arg) { + // Invoke the handler for every descriptor we have. + for (auto &myPair : m_uuidMap) { + myPair.first->handleGATTServerEvent(conn_handle, attr_handle, ctxt, arg); + } +} + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEDevice.cpp b/libraries/BLE/src/BLEDevice.cpp new file mode 100644 index 0000000..4b30ffd --- /dev/null +++ b/libraries/BLE/src/BLEDevice.cpp @@ -0,0 +1,1505 @@ +/* + * BLEDevice.cpp + * + * Created on: Mar 16, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include +#include +#include +#include + +#if SOC_BLE_SUPPORTED +#include +#endif + +#include +#include +#include +#include + +#include "BLEDevice.h" +#include "BLEClient.h" +#include "BLEUtils.h" +#include "GeneralUtils.h" +#include "BLESecurity.h" +#include "base64.h" + +#if defined(ARDUINO_ARCH_ESP32) +#include "esp32-hal-bt.h" +#include "esp32-hal-bt-mem.h" +#endif + +#include "esp32-hal-log.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#include +#include +#include +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#ifdef CONFIG_BT_NIMBLE_LEGACY_VHCI_ENABLE +#include +#endif +#include +#include +#include +#include +#include +#include "host/ble_hs_pvcy.h" +#include "host/util/util.h" +#include "services/gap/ble_svc_gap.h" +#include "services/gatt/ble_svc_gatt.h" +#endif + +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#include "esp32-hal-hosted.h" +#endif + +/*************************************************************************** + * Common properties * + ***************************************************************************/ + +/** + * Singletons for the BLEDevice. + */ +BLEServer *BLEDevice::m_pServer = nullptr; +BLEScan *BLEDevice::m_pScan = nullptr; +BLEClient *BLEDevice::m_pClient = nullptr; +static bool initialized = false; +BLESecurityCallbacks *BLEDevice::m_securityCallbacks = nullptr; +uint16_t BLEDevice::m_localMTU = 23; // not sure if this variable is useful +BLEAdvertising *BLEDevice::m_bleAdvertising = nullptr; +uint16_t BLEDevice::m_appId = 0; +std::map BLEDevice::m_connectedClientsMap; +gap_event_handler BLEDevice::m_customGapHandler = nullptr; + +/*************************************************************************** + * Bluedroid properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +gattc_event_handler BLEDevice::m_customGattcHandler = nullptr; +gatts_event_handler BLEDevice::m_customGattsHandler = nullptr; +#endif + +/*************************************************************************** + * NimBLE properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +ble_gap_event_listener BLEDevice::m_listener; +BLEDeviceCallbacks BLEDevice::defaultDeviceCallbacks{}; +BLEDeviceCallbacks *BLEDevice::m_pDeviceCallbacks = &defaultDeviceCallbacks; +uint8_t BLEDevice::m_ownAddrType = BLE_OWN_ADDR_PUBLIC; +bool BLEDevice::m_synced = false; +String BLEDevice::m_deviceName; +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Create a new instance of a client. + * @return A new instance of the client. + */ +BLEClient *BLEDevice::createClient() { + log_v(">> createClient"); +#if !defined(CONFIG_GATTC_ENABLE) && !defined(CONFIG_BT_NIMBLE_ROLE_CENTRAL) + log_e("BLE Client not enabled. Check CONFIG_GATTC_ENABLE for BlueDroid or CONFIG_BT_NIMBLE_ROLE_CENTRAL for NimBLE"); + abort(); +#endif // CONFIG_GATTC_ENABLE + + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return nullptr; + } + +#ifdef CONFIG_NIMBLE_ENABLED + if (m_connectedClientsMap.size() >= CONFIG_BT_NIMBLE_MAX_CONNECTIONS) { + log_e("Unable to create client. Max connections reached. Cur=%d Max=%d", m_connectedClientsMap.size(), CONFIG_BT_NIMBLE_MAX_CONNECTIONS); + m_pClient = nullptr; + } else +#endif + { + m_pClient = new BLEClient(); + } + log_v("<< createClient"); + return m_pClient; +} // createClient + +/** + * @brief Create a new instance of a server. + * @return A new instance of the server. + */ +BLEServer *BLEDevice::createServer() { + log_v(">> createServer"); +#if !defined(CONFIG_GATTS_ENABLE) && !defined(CONFIG_BT_NIMBLE_ROLE_PERIPHERAL) + log_e("BLE Server not enabled. Check CONFIG_GATTS_ENABLE for BlueDroid or CONFIG_BT_NIMBLE_ROLE_PERIPHERAL for NimBLE"); + abort(); +#endif // CONFIG_GATTS_ENABLE + + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return nullptr; + } + + if (m_pServer == nullptr) { + m_pServer = new BLEServer(); + m_pServer->createApp(m_appId++); +#if defined(CONFIG_NIMBLE_ENABLED) + ble_gatts_reset(); + ble_svc_gap_init(); + ble_svc_gatt_init(); +#endif + } + log_v("<< createServer"); + return m_pServer; +} // createServer + +/** + * @brief Get the BLE device address. + * @return The BLE device address. + */ +BLEAddress BLEDevice::getAddress() { + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return BLEAddress(); + } +#if defined(CONFIG_BLUEDROID_ENABLED) + const uint8_t *bdAddr = esp_bt_dev_get_address(); + esp_bd_addr_t addr; + memcpy(addr, bdAddr, sizeof(addr)); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + ble_addr_t addr; + int ret = ble_hs_id_copy_addr(m_ownAddrType, addr.val, NULL); + if (ret != 0) { + log_e("No BLE address found. rc=%d", ret); + return BLEAddress(); + } +#endif + return BLEAddress(addr); +} // getAddress + +/** + * @brief Retrieve the Scan object that we use for scanning. + * @return The scanning object reference. This is a singleton object. The caller should not + * try and release/delete it. + */ +BLEScan *BLEDevice::getScan() { + //log_v(">> getScan"); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return nullptr; + } + if (m_pScan == nullptr) { + m_pScan = new BLEScan(); + //log_d(" - creating a new scan object"); + } + //log_v("<< getScan: Returning object at 0x%x", (uint32_t)m_pScan); + return m_pScan; +} // getScan + +/** + * @brief Retrieve the server object + * @return The server object + */ +BLEServer *BLEDevice::getServer() { + return m_pServer; +} // getServer + +/** + * @brief Get the value of a characteristic of a service on a remote device. + * @param [in] bdAddress + * @param [in] serviceUUID + * @param [in] characteristicUUID + */ +String BLEDevice::getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID) { + log_v( + ">> getValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(), + characteristicUUID.toString().c_str() + ); + BLEClient *pClient = createClient(); + if (pClient == nullptr) { + log_e("Failed to create BLE client"); + return String(); + } + pClient->connect(bdAddress); + String ret = pClient->getValue(serviceUUID, characteristicUUID); + pClient->disconnect(); + log_v("<< getValue"); + return ret; +} // getValue + +/** + * @brief Initialize the %BLE environment. + * @param deviceName The device name of the device. + * @return true if initialization was successful, false otherwise. + */ +bool BLEDevice::init(String deviceName) { + if (initialized) { + return true; // Already initialized + } + + log_i("Initializing BLE stack: %s", getBLEStackString().c_str()); + + esp_err_t errRc = ESP_OK; +#if defined(CONFIG_BLUEDROID_ENABLED) +#if defined(ARDUINO_ARCH_ESP32) + if (!btStart()) { + errRc = ESP_FAIL; + return false; + } +#else + btStarted(); + errRc = nvs_flash_init(); + if (errRc == ESP_ERR_NVS_NO_FREE_PAGES || errRc == ESP_ERR_NVS_NEW_VERSION_FOUND) { + errRc = nvs_flash_erase(); + if (errRc == ESP_OK) { + errRc = nvs_flash_init(); + } + } + + if (errRc != ESP_OK) { + log_e("nvs_flash_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + +#ifndef CONFIG_BT_CLASSIC_ENABLED + esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT); +#endif + + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + errRc = esp_bt_controller_init(&bt_cfg); + if (errRc != ESP_OK) { + log_e("esp_bt_controller_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + +#ifndef CONFIG_BT_CLASSIC_ENABLED + errRc = esp_bt_controller_enable(ESP_BT_MODE_BLE); + if (errRc != ESP_OK) { + log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } +#else + errRc = esp_bt_controller_enable(ESP_BT_MODE_BTDM); + if (errRc != ESP_OK) { + log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } +#endif +#endif // !ARDUINO_ARCH_ESP32 + + esp_bluedroid_status_t bt_state = esp_bluedroid_get_status(); + if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) { + errRc = esp_bluedroid_init(); + if (errRc != ESP_OK) { + log_e("esp_bluedroid_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + } + + if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) { + errRc = esp_bluedroid_enable(); + if (errRc != ESP_OK) { + log_e("esp_bluedroid_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + } + + errRc = esp_ble_gap_register_callback(BLEDevice::gapEventHandler); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + +#ifdef CONFIG_GATTC_ENABLE // Check that BLE client is configured in make menuconfig + errRc = esp_ble_gattc_register_callback(BLEDevice::gattClientEventHandler); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } +#endif // CONFIG_GATTC_ENABLE + +#ifdef CONFIG_GATTS_ENABLE // Check that BLE server is configured in make menuconfig + errRc = esp_ble_gatts_register_callback(BLEDevice::gattServerEventHandler); + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } +#endif // CONFIG_GATTS_ENABLE + + errRc = ::esp_ble_gap_set_device_name(deviceName.c_str()); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_set_device_name: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + }; + +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + esp_ble_io_cap_t iocap = ESP_IO_CAP_NONE; + errRc = ::esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t)); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_set_security_param: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + }; +#endif // CONFIG_BLE_SMP_ENABLE +#endif // CONFIG_BLUEDROID_ENABLED + +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) + // Initialize esp-hosted transport for BLE HCI when explicitly enabled + if (!hostedInitBLE()) { + log_e("Failed to initialize ESP-Hosted for BLE"); + return false; + } + + // Hosted HCI driver will be initialized automatically by NimBLE transport layer +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + errRc = nimble_port_init(); + if (errRc != ESP_OK) { + log_e("nimble_port_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + + // Global struct ble_hs_cfg from nimble/host/ble_hs.h needs to be initialized + ble_hs_cfg.reset_cb = BLEDevice::onReset; + ble_hs_cfg.sync_cb = BLEDevice::onSync; + ble_hs_cfg.store_status_cb = [](struct ble_store_status_event *event, void *arg) { + return m_pDeviceCallbacks->onStoreStatus(event, arg); + }; + ble_hs_cfg.sm_io_cap = BLE_HS_IO_NO_INPUT_OUTPUT; + ble_hs_cfg.sm_bonding = 0; + ble_hs_cfg.sm_mitm = 0; + ble_hs_cfg.sm_sc = 1; + ble_hs_cfg.sm_our_key_dist = BLE_SM_PAIR_KEY_DIST_ENC; + ble_hs_cfg.sm_their_key_dist = BLE_SM_PAIR_KEY_DIST_ENC; +#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_PRIVACY) + ble_hs_cfg.sm_our_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; + ble_hs_cfg.sm_their_key_dist |= BLE_SM_PAIR_KEY_DIST_ID; +#endif + + // Store device name to be set after sync (GAP service not ready until then) + m_deviceName = deviceName; + + ble_store_config_init(); + nimble_port_freertos_init(BLEDevice::host_task); + + while (!m_synced) { + ble_npl_time_delay(1); + } +#endif // CONFIG_NIMBLE_ENABLED + + initialized = true; // Set the initialization flag to ensure we are only initialized once. + vTaskDelay(200 / portTICK_PERIOD_MS); // Delay for 200 msecs as a workaround to an apparent Arduino environment issue. + return true; +} // init + +/** + * @brief Set the transmission power. + * The power level can be one of: + * * ESP_PWR_LVL_N14 + * * ESP_PWR_LVL_N11 + * * ESP_PWR_LVL_N8 + * * ESP_PWR_LVL_N5 + * * ESP_PWR_LVL_N2 + * * ESP_PWR_LVL_P1 + * * ESP_PWR_LVL_P4 + * * ESP_PWR_LVL_P7 + * + * The power types can be one of: + * * ESP_BLE_PWR_TYPE_CONN_HDL0 + * * ESP_BLE_PWR_TYPE_CONN_HDL1 + * * ESP_BLE_PWR_TYPE_CONN_HDL2 + * * ESP_BLE_PWR_TYPE_CONN_HDL3 + * * ESP_BLE_PWR_TYPE_CONN_HDL4 + * * ESP_BLE_PWR_TYPE_CONN_HDL5 + * * ESP_BLE_PWR_TYPE_CONN_HDL6 + * * ESP_BLE_PWR_TYPE_CONN_HDL7 + * * ESP_BLE_PWR_TYPE_CONN_HDL8 + * * ESP_BLE_PWR_TYPE_ADV + * * ESP_BLE_PWR_TYPE_SCAN + * * ESP_BLE_PWR_TYPE_DEFAULT + * @param [in] powerType. + * @param [in] powerLevel. + */ +void BLEDevice::setPower(esp_power_level_t powerLevel, esp_ble_power_type_t powerType) { + log_v(">> setPower: %d (type: %d)", powerLevel, powerType); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } +#if defined(SOC_BLE_SUPPORTED) + esp_err_t errRc = ::esp_ble_tx_power_set(powerType, powerLevel); + if (errRc != ESP_OK) { + log_e("esp_ble_tx_power_set: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + }; +#else + log_w("setPower not supported with hosted HCI - power controlled by co-processor"); +#endif + log_v("<< setPower"); +} // setPower + +/** + * @brief Get the transmission power. + * @param [in] powerType The power level to set, can be one of: + * * ESP_BLE_PWR_TYPE_CONN_HDL0 = 0, For connection handle 0 + * * ESP_BLE_PWR_TYPE_CONN_HDL1 = 1, For connection handle 1 + * * ESP_BLE_PWR_TYPE_CONN_HDL2 = 2, For connection handle 2 + * * ESP_BLE_PWR_TYPE_CONN_HDL3 = 3, For connection handle 3 + * * ESP_BLE_PWR_TYPE_CONN_HDL4 = 4, For connection handle 4 + * * ESP_BLE_PWR_TYPE_CONN_HDL5 = 5, For connection handle 5 + * * ESP_BLE_PWR_TYPE_CONN_HDL6 = 6, For connection handle 6 + * * ESP_BLE_PWR_TYPE_CONN_HDL7 = 7, For connection handle 7 + * * ESP_BLE_PWR_TYPE_CONN_HDL8 = 8, For connection handle 8 + * * ESP_BLE_PWR_TYPE_ADV = 9, For advertising + * * ESP_BLE_PWR_TYPE_SCAN = 10, For scan + * * ESP_BLE_PWR_TYPE_DEFAULT = 11, For default, if not set other, it will use default value + * @return the power level currently used by the type specified. + */ + +int BLEDevice::getPower(esp_ble_power_type_t powerType) { + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return -128; // Return error value + } +#if SOC_BLE_SUPPORTED + switch (esp_ble_tx_power_get(powerType)) { + case ESP_PWR_LVL_N12: return -12; + case ESP_PWR_LVL_N9: return -9; + case ESP_PWR_LVL_N6: return -6; + case ESP_PWR_LVL_N3: return -3; + case ESP_PWR_LVL_N0: return 0; + case ESP_PWR_LVL_P3: return 3; + case ESP_PWR_LVL_P6: return 6; + case ESP_PWR_LVL_P9: return 9; + default: return -128; + } +#else + log_w("getPower not supported with hosted HCI - power controlled by co-processor"); + return 0; // Return default power level +#endif +} // getPower + +/** + * @brief Set the value of a characteristic of a service on a remote device. + * @param [in] bdAddress + * @param [in] serviceUUID + * @param [in] characteristicUUID + */ +void BLEDevice::setValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, String value) { + log_v( + ">> setValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(), + characteristicUUID.toString().c_str() + ); + BLEClient *pClient = createClient(); + if (pClient == nullptr) { + log_e("Failed to create BLE client"); + return; + } + pClient->connect(bdAddress); + pClient->setValue(serviceUUID, characteristicUUID, value); + pClient->disconnect(); +} // setValue + +/** + * @brief Return a string representation of the nature of this device. + * @return A string representation of the nature of this device. + */ +String BLEDevice::toString() { + String res = "BD Address: " + getAddress().toString(); + return res; +} // toString + +/** + * @brief Add an entry to the BLE white list. + * @param [in] address The address to add to the white list. + */ +void BLEDevice::whiteListAdd(BLEAddress address) { + log_v(">> whiteListAdd: %s", address.toString().c_str()); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } +#ifdef CONFIG_BLUEDROID_ENABLED +#ifdef ESP_IDF_VERSION_MAJOR + esp_err_t errRc = esp_ble_gap_update_whitelist(true, address.getNative(), BLE_WL_ADDR_TYPE_PUBLIC); // HACK!!! True to add an entry. +#else + esp_err_t errRc = esp_ble_gap_update_whitelist(true, address.getNative()); // True to add an entry. +#endif + if (errRc != ESP_OK) { + log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (!BLEDevice::onWhiteList(address)) { + m_whiteList.push_back(address); + int errRc = ble_gap_wl_set(reinterpret_cast(&m_whiteList[0]), m_whiteList.size()); + if (errRc != 0) { + log_e("Failed adding to whitelist rc=%d", errRc); + m_whiteList.pop_back(); + } + } +#endif + log_v("<< whiteListAdd"); +} // whiteListAdd + +/** + * @brief Remove an entry from the BLE white list. + * @param [in] address The address to remove from the white list. + */ +void BLEDevice::whiteListRemove(BLEAddress address) { + log_v(">> whiteListRemove: %s", address.toString().c_str()); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } +#ifdef CONFIG_BLUEDROID_ENABLED +#ifdef ESP_IDF_VERSION_MAJOR + esp_err_t errRc = esp_ble_gap_update_whitelist(false, address.getNative(), BLE_WL_ADDR_TYPE_PUBLIC); // HACK!!! False to remove an entry. +#else + esp_err_t errRc = esp_ble_gap_update_whitelist(false, address.getNative()); // False to remove an entry. +#endif + if (errRc != ESP_OK) { + log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + for (auto it = m_whiteList.begin(); it < m_whiteList.end(); ++it) { + if (*it == address) { + m_whiteList.erase(it); + int errRc = ble_gap_wl_set(reinterpret_cast(&m_whiteList[0]), m_whiteList.size()); + if (errRc != 0) { + m_whiteList.push_back(address); + log_e("Failed removing from whitelist rc=%d", errRc); + } + std::vector(m_whiteList).swap(m_whiteList); + } + } +#endif + log_v("<< whiteListRemove"); +} // whiteListRemove + +/* + * @brief Set callbacks that will be used to handle encryption negotiation events and authentication events + * @param [in] callbacks Pointer to BLESecurityCallbacks class callback + */ +void BLEDevice::setSecurityCallbacks(BLESecurityCallbacks *callbacks) { + BLEDevice::m_securityCallbacks = callbacks; +} + +/* + * @brief Setup local mtu that will be used to negotiate mtu during request from client peer + * @param [in] mtu Value to set local mtu, should be larger than 23 and lower or equal to 517 + */ +esp_err_t BLEDevice::setMTU(uint16_t mtu) { + log_v(">> setLocalMTU: %d", mtu); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return ESP_FAIL; + } + +#ifdef CONFIG_BLUEDROID_ENABLED + esp_err_t err = esp_ble_gatt_set_local_mtu(mtu); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + int err = ble_att_set_preferred_mtu(mtu); +#endif + + if (err == ESP_OK) { + m_localMTU = mtu; + } else { + log_e("can't set local mtu value: %d, rc=%d", mtu, err); + } + log_v("<< setLocalMTU"); + return err; +} + +/* + * @brief Get local MTU value set during mtu request or default value + */ +uint16_t BLEDevice::getMTU() { + return m_localMTU; +} + +bool BLEDevice::getInitialized() { + return initialized; +} + +/* + * @brief Get a peer device's Identity Resolving Key (IRK). + * @param [in] peerAddress The address of the bonded peer device. + * @param [out] irk Buffer to store the 16-byte IRK. + * @return True if successful, false otherwise. + * @note IRK is only available after bonding has occurred. + */ +bool BLEDevice::getPeerIRK(BLEAddress peerAddress, uint8_t *irk) { + log_v(">> BLEDevice::getPeerIRK()"); + + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return false; + } + + if (irk == nullptr) { + log_e("IRK buffer is null"); + return false; + } + +#if defined(CONFIG_BLUEDROID_ENABLED) + // Get the list of bonded devices + int dev_num = esp_ble_get_bond_device_num(); + if (dev_num == 0) { + log_e("No bonded devices found"); + return false; + } + + esp_ble_bond_dev_t *bond_dev = (esp_ble_bond_dev_t *)malloc(sizeof(esp_ble_bond_dev_t) * dev_num); + if (bond_dev == nullptr) { + log_e("Failed to allocate memory for bond device list"); + return false; + } + + esp_err_t ret = esp_ble_get_bond_device_list(&dev_num, bond_dev); + if (ret != ESP_OK) { + log_e("Failed to get bond device list: %d", ret); + free(bond_dev); + return false; + } + + // Find the bonded device that matches the peer address + bool found = false; + + for (int i = 0; i < dev_num; i++) { + BLEAddress bondAddr(bond_dev[i].bd_addr); + if (bondAddr.equals(peerAddress)) { + // Check if the PID key (which contains the IRK) is present + if (bond_dev[i].bond_key.key_mask & ESP_LE_KEY_PID) { + memcpy(irk, bond_dev[i].bond_key.pid_key.irk, 16); + found = true; + log_d("IRK found for peer: %s", peerAddress.toString().c_str()); + break; + } else { + log_w("PID key not present for peer: %s", peerAddress.toString().c_str()); + } + } + } + + free(bond_dev); + + if (!found) { + log_e("IRK not found for peer"); + return false; + } + + log_v("<< BLEDevice::getPeerIRK()"); + return true; +#endif // CONFIG_BLUEDROID_ENABLED + +#if defined(CONFIG_NIMBLE_ENABLED) + // Prepare the key structure to search for the peer's security information + struct ble_store_key_sec key_sec; + memset(&key_sec, 0, sizeof(key_sec)); + + // Convert BLEAddress to ble_addr_t + // NOTE: BLEAddress stores bytes in INVERSE order for NimBLE, + // but ble_addr_t.val expects them in normal order, so we reverse them + ble_addr_t addr; + uint8_t *peer_addr = peerAddress.getNative(); + for (int i = 0; i < 6; i++) { + addr.val[i] = peer_addr[5 - i]; + } + + // Try public address first, then random if that fails + addr.type = BLE_ADDR_PUBLIC; + memcpy(&key_sec.peer_addr, &addr, sizeof(ble_addr_t)); + + // Read the peer's security information from the store + struct ble_store_value_sec value_sec; + int rc = ble_store_read_peer_sec(&key_sec, &value_sec); + + // If public address failed, try random address type + if (rc != 0) { + addr.type = BLE_ADDR_RANDOM; + memcpy(&key_sec.peer_addr, &addr, sizeof(ble_addr_t)); + rc = ble_store_read_peer_sec(&key_sec, &value_sec); + + if (rc != 0) { + log_e("IRK not found for peer: %s", peerAddress.toString().c_str()); + return false; + } + } + + // Check if the IRK is present + if (!value_sec.irk_present) { + log_e("IRK not present for peer"); + return false; + } + + // Copy the IRK to the output buffer + memcpy(irk, value_sec.irk, 16); + + log_d("IRK found for peer: %s (type=%d)", peerAddress.toString().c_str(), addr.type); + log_v("<< BLEDevice::getPeerIRK()"); + return true; +#endif // CONFIG_NIMBLE_ENABLED +} + +/* + * @brief Get a peer device's IRK as a comma-separated hex string. + * @param [in] peerAddress The address of the bonded peer device. + * @return String in format "0xXX,0xXX,..." or empty string on failure. + */ +String BLEDevice::getPeerIRKString(BLEAddress peerAddress) { + uint8_t irk[16]; + if (!getPeerIRK(peerAddress, irk)) { + return String(); + } + + String result = ""; + for (int i = 0; i < 16; i++) { + result += "0x"; + if (irk[i] < 0x10) { + result += "0"; + } + result += String(irk[i], HEX); + if (i < 15) { + result += ","; + } + } + return result; +} + +/* + * @brief Get a peer device's IRK as a Base64 encoded string. + * @param [in] peerAddress The address of the bonded peer device. + * @return Base64 encoded string or empty string on failure. + */ +String BLEDevice::getPeerIRKBase64(BLEAddress peerAddress) { + uint8_t irk[16]; + if (!getPeerIRK(peerAddress, irk)) { + return String(); + } + + return base64::encode(irk, 16); +} + +/* + * @brief Get a peer device's IRK in reverse hex format. + * @param [in] peerAddress The address of the bonded peer device. + * @return String in reverse hex format (uppercase) or empty string on failure. + */ +String BLEDevice::getPeerIRKReverse(BLEAddress peerAddress) { + uint8_t irk[16]; + if (!getPeerIRK(peerAddress, irk)) { + return String(); + } + + String result = ""; + for (int i = 15; i >= 0; i--) { + if (irk[i] < 0x10) { + result += "0"; + } + result += String(irk[i], HEX); + } + result.toUpperCase(); + return result; +} + +BLEAdvertising *BLEDevice::getAdvertising() { + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return nullptr; + } + if (m_bleAdvertising == nullptr) { + m_bleAdvertising = new BLEAdvertising(); + log_i("create advertising"); + } + log_d("get advertising"); + return m_bleAdvertising; +} + +void BLEDevice::startAdvertising() { + log_v(">> startAdvertising"); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } + getAdvertising()->start(); + log_v("<< startAdvertising"); +} // startAdvertising + +void BLEDevice::stopAdvertising() { + log_v(">> stopAdvertising"); + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } + getAdvertising()->stop(); + log_v("<< stopAdvertising"); +} // stopAdvertising + +/* multi connect support */ +/* requires a little more work */ +std::map BLEDevice::getPeerDevices(bool _client) { + return m_connectedClientsMap; +} + +BLEClient *BLEDevice::getClientByID(uint16_t conn_id) { + return BLEDevice::getClientByGattIf(conn_id); +} + +BLEClient *BLEDevice::getClientByGattIf(uint16_t conn_id) { + return (BLEClient *)m_connectedClientsMap.find(conn_id)->second.peer_device; +} + +BLEClient *BLEDevice::getClientByAddress(BLEAddress address) { + for (auto &it : m_connectedClientsMap) { + if (((BLEClient *)it.second.peer_device)->getPeerAddress() == address) { + return (BLEClient *)it.second.peer_device; + } + } + return nullptr; +} + +void BLEDevice::updatePeerDevice(void *peer, bool _client, uint16_t conn_id) { + log_d("update conn_id: %d, GATT role: %s", conn_id, _client ? "client" : "server"); + std::map::iterator it = m_connectedClientsMap.find(ESP_GATT_IF_NONE); + if (it != m_connectedClientsMap.end()) { + std::swap(m_connectedClientsMap[conn_id], it->second); + m_connectedClientsMap.erase(it); + } else { + it = m_connectedClientsMap.find(conn_id); + if (it != m_connectedClientsMap.end()) { + conn_status_t _st = it->second; + _st.peer_device = peer; + std::swap(m_connectedClientsMap[conn_id], _st); + } + } +} + +void BLEDevice::addPeerDevice(void *peer, bool _client, uint16_t conn_id) { + log_i("add conn_id: %d, GATT role: %s", conn_id, _client ? "client" : "server"); + conn_status_t status = {.peer_device = peer, .connected = true, .mtu = 23}; + + m_connectedClientsMap.insert(std::pair(conn_id, status)); +} + +//there may have some situation that invoking this function simultaneously, that will cause CORRUPT HEAP +//let this function serializable +portMUX_TYPE BLEDevice::mux = portMUX_INITIALIZER_UNLOCKED; +void BLEDevice::removePeerDevice(uint16_t conn_id, bool _client) { + portENTER_CRITICAL(&mux); + log_i("remove: %d, GATT role %s", conn_id, _client ? "client" : "server"); + if (m_connectedClientsMap.find(conn_id) != m_connectedClientsMap.end()) { + m_connectedClientsMap.erase(conn_id); + } + portEXIT_CRITICAL(&mux); +} + +/* multi connect support */ + +/** + * @brief de-Initialize the %BLE environment. + * @param release_memory release the internal BT stack memory (prevents reinitialization) + */ +void BLEDevice::deinit(bool release_memory) { + if (!initialized) { + return; + } + + // Stop advertising and scanning first + if (m_bleAdvertising != nullptr) { + m_bleAdvertising->stop(); + } + + if (m_pScan != nullptr) { + m_pScan->stop(); + } + + // Delete all BLE objects + if (m_bleAdvertising != nullptr) { + delete m_bleAdvertising; + m_bleAdvertising = nullptr; + } + + if (m_pScan != nullptr) { + delete m_pScan; + m_pScan = nullptr; + } + + if (m_pServer != nullptr) { + delete m_pServer; + m_pServer = nullptr; + } + + if (m_pClient != nullptr) { + delete m_pClient; + m_pClient = nullptr; + } + + // Clear the connected clients map + m_connectedClientsMap.clear(); + + // Always deinit the BLE stack +#ifdef CONFIG_BLUEDROID_ENABLED + esp_bluedroid_disable(); + esp_bluedroid_deinit(); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + nimble_port_stop(); + nimble_port_deinit(); +#endif + +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) + hostedDeinitBLE(); +#endif + +#if CONFIG_BT_CONTROLLER_ENABLED + esp_bt_controller_disable(); + esp_bt_controller_deinit(); +#endif + + // Only release memory if requested (this prevents reinitialization) + if (release_memory) { +#ifdef ARDUINO_ARCH_ESP32 + // Require tests because we released classic BT memory and this can cause crash (most likely not, esp-idf takes care of it) +#if CONFIG_BT_CONTROLLER_ENABLED + esp_bt_controller_mem_release(ESP_BT_MODE_BTDM); +#endif +#endif + } + +#ifdef CONFIG_NIMBLE_ENABLED + m_synced = false; +#endif + initialized = false; +} + +void BLEDevice::setCustomGapHandler(gap_event_handler handler) { + m_customGapHandler = handler; +#ifdef CONFIG_NIMBLE_ENABLED + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return; + } + int rc = ble_gap_event_listener_register(&m_listener, handler, NULL); + if (rc == BLE_HS_EALREADY) { + log_i("Already listening to GAP events."); + } else if (rc != 0) { + log_e("ble_gap_event_listener_register: rc=%d %s", rc, GeneralUtils::errorToString(rc)); + } +#endif +} + +BLEStack BLEDevice::getBLEStack() { +#if defined(CONFIG_BLUEDROID_ENABLED) + return BLEStack::BLUEDROID; +#elif defined(CONFIG_NIMBLE_ENABLED) + return BLEStack::NIMBLE; +#else + return BLEStack::UNKNOWN; +#endif +} + +String BLEDevice::getBLEStackString() { + switch (getBLEStack()) { + case BLEStack::BLUEDROID: return "Bluedroid"; + case BLEStack::NIMBLE: return "NimBLE"; + case BLEStack::UNKNOWN: + default: return "Unknown"; + } +} + +bool BLEDevice::isHostedBLE() { +#if defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) + return true; +#else + return false; +#endif +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Handle GATT server events. + * + * @param [in] event The event that has been newly received. + * @param [in] gatts_if The connection to the GATT interface. + * @param [in] param Parameters for the event. + */ +void BLEDevice::gattServerEventHandler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + log_d("gattServerEventHandler [esp_gatt_if: %d] ... %s", gatts_if, BLEUtils::gattServerEventTypeToString(event).c_str()); + + BLEUtils::dumpGattServerEvent(event, gatts_if, param); + + switch (event) { + case ESP_GATTS_CONNECT_EVT: + { + if (BLESecurity::m_securityEnabled && BLESecurity::m_forceSecurity) { + BLESecurity::startSecurity(param->connect.remote_bda); + } + break; + } // ESP_GATTS_CONNECT_EVT + + default: + { + break; + } + } // switch + + if (BLEDevice::m_pServer != nullptr) { + BLEDevice::m_pServer->handleGATTServerEvent(event, gatts_if, param); + } + + if (m_customGattsHandler != nullptr) { + m_customGattsHandler(event, gatts_if, param); + } + +} // gattServerEventHandler + +/** + * @brief Handle GATT client events. + * + * Handler for the GATT client events. + * + * @param [in] event + * @param [in] gattc_if + * @param [in] param + */ +void BLEDevice::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param) { + + log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s", gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str()); + BLEUtils::dumpGattClientEvent(event, gattc_if, param); + + switch (event) { + case ESP_GATTC_CONNECT_EVT: + { + // Set encryption on connect for BlueDroid when security is enabled + // This ensures security is established before any secure operations + if (BLESecurity::m_securityEnabled && BLESecurity::m_forceSecurity) { + BLESecurity::startSecurity(param->connect.remote_bda); + } + break; + } // ESP_GATTS_CONNECT_EVT + + default: break; + } // switch + for (auto &myPair : BLEDevice::getPeerDevices(true)) { + conn_status_t conn_status = (conn_status_t)myPair.second; + if (((BLEClient *)conn_status.peer_device)->getGattcIf() == gattc_if || ((BLEClient *)conn_status.peer_device)->getGattcIf() == ESP_GATT_IF_NONE + || gattc_if == ESP_GATT_IF_NONE) { + ((BLEClient *)conn_status.peer_device)->gattClientEventHandler(event, gattc_if, param); + } + } + + if (m_customGattcHandler != nullptr) { + m_customGattcHandler(event, gattc_if, param); + } + +} // gattClientEventHandler + +/** + * @brief Handle GAP events. + */ +void BLEDevice::gapEventHandler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + + BLEUtils::dumpGapEvent(event, param); + + switch (event) { + + case ESP_GAP_BLE_OOB_REQ_EVT: /* OOB request event */ log_i("ESP_GAP_BLE_OOB_REQ_EVT"); break; + case ESP_GAP_BLE_LOCAL_IR_EVT: /* BLE local IR event */ log_i("ESP_GAP_BLE_LOCAL_IR_EVT"); break; + case ESP_GAP_BLE_LOCAL_ER_EVT: /* BLE local ER event */ log_i("ESP_GAP_BLE_LOCAL_ER_EVT"); break; + case ESP_GAP_BLE_NC_REQ_EVT: /* NUMERIC CONFIRMATION */ + { + log_i("ESP_GAP_BLE_NC_REQ_EVT"); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + if (BLEDevice::m_securityCallbacks != nullptr) { + esp_ble_confirm_reply(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onConfirmPIN(param->ble_security.key_notif.passkey)); + } else { + log_e("onConfirmPIN not implemented. Rejecting connection"); + esp_ble_confirm_reply(param->ble_security.ble_req.bd_addr, false); + } +#endif // CONFIG_BLE_SMP_ENABLE + } break; + case ESP_GAP_BLE_PASSKEY_REQ_EVT: /* passkey request event */ + { + log_i("ESP_GAP_BLE_PASSKEY_REQ_EVT: "); + // esp_log_buffer_hex(m_remote_bda, sizeof(m_remote_bda)); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + uint32_t passkey = BLESecurity::getPassKey(); + + if (!BLESecurity::m_passkeySet) { + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("No passkey set, getting passkey from onPassKeyRequest"); + passkey = BLEDevice::m_securityCallbacks->onPassKeyRequest(); + } else { + log_w("*ATTENTION* onPassKeyRequest not implemented and no static passkey set."); + } + } + + if (BLESecurity::m_staticPasskey && passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", passkey); + } + + esp_ble_passkey_reply(param->ble_security.ble_req.bd_addr, true, passkey); +#endif // CONFIG_BLE_SMP_ENABLE + } break; + /* + * TODO should we add white/black list comparison? + */ + case ESP_GAP_BLE_SEC_REQ_EVT: + { + /* send the positive(true) security response to the peer device to accept the security request. + If not accept the security request, should sent the security response with negative(false) accept value*/ + log_i("ESP_GAP_BLE_SEC_REQ_EVT"); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + if (BLEDevice::m_securityCallbacks != nullptr) { + esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onSecurityRequest()); + } else { + log_w("onSecurityRequest not implemented. Accepting security request"); + esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, true); + } +#endif // CONFIG_BLE_SMP_ENABLE + } break; + /* + * + */ + case ESP_GAP_BLE_PASSKEY_NOTIF_EVT: //the app will receive this evt when the IO has Output capability and the peer device IO has Input capability. + { + //display the passkey number to the user to input it in the peer device within 30 seconds + log_i("ESP_GAP_BLE_PASSKEY_NOTIF_EVT"); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + uint32_t passkey = param->ble_security.key_notif.passkey; + + if (!BLESecurity::m_passkeySet) { + log_w("No passkey set"); + } + + if (BLESecurity::m_staticPasskey && passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", passkey); + } + + if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onPassKeyNotify(passkey); + } +#endif // CONFIG_BLE_SMP_ENABLE + } break; + case ESP_GAP_BLE_KEY_EVT: + { + //shows the ble key type info share with peer device to the user. + log_d("ESP_GAP_BLE_KEY_EVT"); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + log_i("key type = %s", BLESecurity::esp_key_type_to_str(param->ble_security.ble_key.key_type)); +#endif // CONFIG_BLE_SMP_ENABLE + } break; + case ESP_GAP_BLE_AUTH_CMPL_EVT: + { + log_i("ESP_GAP_BLE_AUTH_CMPL_EVT"); +#ifdef CONFIG_BLE_SMP_ENABLE // Check that BLE SMP (security) is configured in make menuconfig + // Signal that authentication has completed + // This unblocks any GATT operations waiting for pairing when bonding is enabled + BLESecurity::signalAuthenticationComplete(); + + // Restore CCCD values for bonded device reconnection + // Per GATT spec, CCCD values should persist for bonded devices + // Windows and other hosts don't re-write CCCD after reconnection + if (param->ble_security.auth_cmpl.success && m_pServer != nullptr) { + BLEAddress peerAddress(param->ble_security.auth_cmpl.bd_addr); + m_pServer->restoreCCCDValues(peerAddress); + } + + if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onAuthenticationComplete(param->ble_security.auth_cmpl); + } +#endif // CONFIG_BLE_SMP_ENABLE + } break; + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + { + log_i( + "ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: status=%d, conn_int=%d, latency=%d, timeout=%d", param->update_conn_params.status, + param->update_conn_params.conn_int, param->update_conn_params.latency, param->update_conn_params.timeout + ); + break; + } + default: + { + break; + } + } // switch + + if (BLEDevice::m_pServer != nullptr) { + BLEDevice::m_pServer->handleGAPEvent(event, param); + } + + if (BLEDevice::m_pClient != nullptr) { + BLEDevice::m_pClient->handleGAPEvent(event, param); + } + + if (BLEDevice::m_pScan != nullptr) { + BLEDevice::getScan()->handleGAPEvent(event, param); + } + + if (m_bleAdvertising != nullptr) { + BLEDevice::getAdvertising()->handleGAPEvent(event, param); + } + + if (m_customGapHandler != nullptr) { + BLEDevice::m_customGapHandler(event, param); + } + +} // gapEventHandler +void BLEDevice::setCustomGattcHandler(gattc_event_handler handler) { + m_customGattcHandler = handler; +} + +void BLEDevice::setCustomGattsHandler(gatts_event_handler handler) { + m_customGattsHandler = handler; +} + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Set the SDIO pins for connection to external ESP MCU when using ESP-Hosted with NimBLE + * @param [in] clk The clock pin + * @param [in] cmd The command pin + * @param [in] d0 The data pin 0 + * @param [in] d1 The data pin 1 + * @param [in] d2 The data pin 2 + * @param [in] d3 The data pin 3 + * @param [in] rst The reset pin + * @return True if the pins were set successfully. + */ +#if CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE +bool BLEDevice::setPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst) { + return hostedSetPins(clk, cmd, d0, d1, d2, d3, rst); +} +#endif + +/** + * @brief Checks if a peer device is whitelisted. + * @param [in] address The address to check for in the whitelist. + * @returns True if the address is in the whitelist. + */ +bool BLEDevice::onWhiteList(BLEAddress &address) { + for (auto &addr : m_whiteList) { + if (addr == address) { + return true; + } + } + return false; +} + +void BLEDevice::host_task(void *param) { + log_i("NimBLE host task started"); + nimble_port_run(); // This function will return only when nimble_port_stop() is executed + nimble_port_freertos_deinit(); +} + +void BLEDevice::onReset(int reason) { + if (!m_synced) { + return; + } + + m_synced = false; + + log_i("onReset, reason=%d, %s", reason, BLEUtils::returnCodeToString(reason)); + + if (initialized) { + if (m_pScan != nullptr) { + m_pScan->onHostReset(); + } + } +} + +void BLEDevice::onSync() { + log_d("onSync"); + + if (m_synced) { + log_d("onSync: already synced"); + return; + } + + // Set device name first, before any other GAP operations + if (m_deviceName.length() > 0) { + int nameRc = ble_svc_gap_device_name_set(m_deviceName.c_str()); + if (nameRc != 0) { + log_e("ble_svc_gap_device_name_set: rc=%d %s", nameRc, BLEUtils::returnCodeToString(nameRc)); + } + } + + int rc = ble_hs_util_ensure_addr(0); + if (rc == 0) { + rc = ble_hs_util_ensure_addr(1); + } + + if (rc != 0) { + log_e("onSync: failed to ensure BLE address. rc=%d", rc); + return; + } + + rc = ble_hs_id_copy_addr(BLE_OWN_ADDR_PUBLIC, NULL, NULL); + if (rc != 0) { + log_d("onSync: no public address available"); + m_ownAddrType = BLE_OWN_ADDR_RANDOM; + } + + // Yield for housekeeping tasks before returning to operations. + // Occasionally triggers exception without. + ble_npl_time_delay(1); + + m_synced = true; + + if (initialized) { + if (m_pScan != nullptr) { + m_pScan->onHostSync(); + } + if (m_bleAdvertising != nullptr) { + m_bleAdvertising->onHostSync(); + } + } +} + +void BLEDevice::setDeviceCallbacks(BLEDeviceCallbacks *cb) { + if (cb == nullptr) { + m_pDeviceCallbacks = &defaultDeviceCallbacks; + } else { + m_pDeviceCallbacks = cb; + } +} + +/** + * @brief Get the device name. + * @return The device name. + */ +String BLEDevice::getDeviceName() { + return m_deviceName; +} + +/** + * @brief Sets the address type to use. + * @param [in] type Bluetooth Device address type. + * The available types are defined as: + * * 0x00: BLE_OWN_ADDR_PUBLIC - Public address; Uses the hardware static address. + * * 0x01: BLE_OWN_ADDR_RANDOM - Random static address; Uses the hardware or generated random static address. + * * 0x02: BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT - Resolvable private address, defaults to public if no RPA available. + * * 0x03: BLE_OWN_ADDR_RPA_RANDOM_DEFAULT - Resolvable private address, defaults to random static if no RPA available. + */ +bool BLEDevice::setOwnAddrType(uint8_t type) { + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return false; + } + int rc = ble_hs_id_copy_addr(type & 1, NULL, NULL); // Odd values are random + if (rc != 0) { + log_e("Unable to set address type %d, rc=%d", type, rc); + return false; + } + + m_ownAddrType = type; + + if (type == BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT || type == BLE_OWN_ADDR_RPA_RANDOM_DEFAULT) { +#ifdef CONFIG_IDF_TARGET_ESP32 + // esp32 controller does not support RPA so we must use the random static for calls to the stack + // the host will take care of the random private address generation/setting. + m_ownAddrType = BLE_OWN_ADDR_RANDOM; + rc = ble_hs_pvcy_rpa_config(NIMBLE_HOST_ENABLE_RPA); +#endif + } else { +#ifdef CONFIG_IDF_TARGET_ESP32 + rc = ble_hs_pvcy_rpa_config(NIMBLE_HOST_DISABLE_PRIVACY); +#endif + } + return rc == 0; +} // setOwnAddrType + +/** + * @brief Set the device address to use. + * @param [in] addr The address to set. + * @return True if the address was set successfully. + * @details To use the address generated the address type must be set to random with `setOwnAddrType`. + */ +bool BLEDevice::setOwnAddr(BLEAddress &addr) { + return setOwnAddr(addr.getNative()); +} // setOwnAddr + +/** + * @brief Set the device address to use. + * @param [in] addr The address to set. + * @return True if the address was set successfully. + * @details To use the address generated the address type must be set to random with `setOwnAddrType`. + */ +bool BLEDevice::setOwnAddr(uint8_t *addr) { + if (!initialized) { + log_e("BLE is not initialized. Call BLEDevice::init() first"); + return false; + } + int rc = ble_hs_id_set_rnd(addr); + if (rc != 0) { + log_e("Failed to set address, rc=%d", rc); + return false; + } + return true; +} // setOwnAddr + +int BLEDeviceCallbacks::onStoreStatus(struct ble_store_status_event *event, void *arg) { + log_d("onStoreStatus: default"); + return ble_store_util_status_rr(event, arg); +} + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEDevice.h b/libraries/BLE/src/BLEDevice.h new file mode 100644 index 0000000..400e32c --- /dev/null +++ b/libraries/BLE/src/BLEDevice.h @@ -0,0 +1,304 @@ +/* + * BLEDevice.h + * + * Created on: Mar 16, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef MAIN_BLEDevice_H_ +#define MAIN_BLEDevice_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include + +#if defined(SOC_BLE_SUPPORTED) +#include +#else +// For ESP32-P4 and other chips without native BLE support +// Define minimal types needed for interface compatibility +typedef int esp_power_level_t; +typedef int esp_ble_power_type_t; +#define ESP_BLE_PWR_TYPE_DEFAULT 0 +#define ESP_PWR_LVL_N12 0 +#endif + +#include "WString.h" +#include "BLEServer.h" +#include "BLEClient.h" +#include "BLEUtils.h" +#include "BLEScan.h" +#include "BLEAdvertising.h" +#include "BLESecurity.h" +#include "BLEAddress.h" +#include "BLEUtils.h" +#include "BLEUUID.h" +#include "BLEAdvertisedDevice.h" + +/*************************************************************************** + * Common definitions * + ***************************************************************************/ + +enum class BLEStack { + BLUEDROID, + NIMBLE, + UNKNOWN +}; + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#include +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#define ESP_GATT_IF_NONE BLE_HS_CONN_HANDLE_NONE + +// Hosted HCI transport implementation is provided in BLEHostedHCI.cpp +// and is automatically linked when building for ESP32-P4 + +// NimBLE configuration compatibility macros +#if defined(CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE) +#define CONFIG_BTDM_SCAN_DUPL_TYPE_DEVICE CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR +#endif + +#if defined(CONFIG_SCAN_DUPLICATE_BY_ADV_DATA) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE_DATA) +#define CONFIG_BTDM_SCAN_DUPL_TYPE_DATA CONFIG_SCAN_DUPLICATE_BY_ADV_DATA +#endif + +#if defined(CONFIG_SCAN_DUPLICATE_BY_ADV_DATA_AND_DEVICE_ADDR) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE) +#define CONFIG_BTDM_SCAN_DUPL_TYPE_DATA_DEVICE CONFIG_SCAN_DUPLICATE_BY_ADV_DATA_AND_DEVICE_ADDR +#endif + +#if defined(CONFIG_SCAN_DUPLICATE_TYPE) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE) +#define CONFIG_BTDM_SCAN_DUPL_TYPE CONFIG_SCAN_DUPLICATE_TYPE +#endif + +#if defined(CONFIG_BT_CTRL_SCAN_DUPL_TYPE) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE) +#define CONFIG_BTDM_SCAN_DUPL_TYPE CONFIG_BT_CTRL_SCAN_DUPL_TYPE +#endif + +#if defined(CONFIG_BT_LE_SCAN_DUPL_TYPE) && !defined(CONFIG_BTDM_SCAN_DUPL_TYPE) +#define CONFIG_BTDM_SCAN_DUPL_TYPE CONFIG_BT_LE_SCAN_DUPL_TYPE +#endif + +#if defined(CONFIG_DUPLICATE_SCAN_CACHE_SIZE) && !defined(CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE) +#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE CONFIG_DUPLICATE_SCAN_CACHE_SIZE +#endif + +#if defined(CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE) && !defined(CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE) +#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE +#endif + +#if defined(CONFIG_BT_LE_LL_DUP_SCAN_LIST_COUNT) && !defined(CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE) +#define CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE CONFIG_BT_LE_LL_DUP_SCAN_LIST_COUNT +#endif + +#if defined(CONFIG_NIMBLE_MAX_CONNECTIONS) && !defined(CONFIG_BT_NIMBLE_MAX_CONNECTIONS) +#define CONFIG_BT_NIMBLE_MAX_CONNECTIONS CONFIG_NIMBLE_MAX_CONNECTIONS +#endif + +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEAddress; +class BLEDeviceCallbacks; +class BLESecurityCallbacks; +class BLEServer; +class BLEScan; +class BLEAdvertising; +class BLEClient; +class BLESecurity; + +/*************************************************************************** + * Bluedroid type definitions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +typedef void (*gap_event_handler)(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +typedef void (*gattc_event_handler)(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param); +typedef void (*gatts_event_handler)(esp_gatts_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gatts_cb_param_t *param); +#endif + +/*************************************************************************** + * NimBLE type definitions and externals * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +extern "C" void ble_store_config_init(void); +typedef int (*gap_event_handler)(struct ble_gap_event *event, void *param); +#endif + +class BLEDevice { +public: + /*************************************************************************** + * Common public properties * + ***************************************************************************/ + + static uint16_t m_appId; + static uint16_t m_localMTU; + static gap_event_handler m_customGapHandler; + + /*************************************************************************** + * Bluedroid public properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static gattc_event_handler m_customGattcHandler; + static gatts_event_handler m_customGattsHandler; +#endif + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + static BLEClient *createClient(); + static BLEServer *createServer(); + static BLEAddress getAddress(); + static BLEServer *getServer(); + static BLEScan *getScan(); + static String getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID); + static bool init(String deviceName = ""); + static void setPower(esp_power_level_t powerLevel, esp_ble_power_type_t powerType = ESP_BLE_PWR_TYPE_DEFAULT); + static int getPower(esp_ble_power_type_t powerType = ESP_BLE_PWR_TYPE_DEFAULT); + static void setValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, String value); + static String toString(); + static void whiteListAdd(BLEAddress address); + static void whiteListRemove(BLEAddress address); + static void setSecurityCallbacks(BLESecurityCallbacks *pCallbacks); + static esp_err_t setMTU(uint16_t mtu); + static uint16_t getMTU(); + static bool getInitialized(); + static bool getPeerIRK(BLEAddress peerAddress, uint8_t *irk); + static String getPeerIRKString(BLEAddress peerAddress); + static String getPeerIRKBase64(BLEAddress peerAddress); + static String getPeerIRKReverse(BLEAddress peerAddress); + static BLEAdvertising *getAdvertising(); + static void startAdvertising(); + static void stopAdvertising(); + static std::map getPeerDevices(bool client); + static void addPeerDevice(void *peer, bool is_client, uint16_t conn_id); + static void updatePeerDevice(void *peer, bool _client, uint16_t conn_id); + static void removePeerDevice(uint16_t conn_id, bool client); + static BLEClient *getClientByID(uint16_t conn_id); + static BLEClient *getClientByAddress(BLEAddress address); + static BLEClient *getClientByGattIf(uint16_t conn_id); + static void setCustomGapHandler(gap_event_handler handler); + static void deinit(bool release_memory = false); + static BLEStack getBLEStack(); + static String getBLEStackString(); + static bool isHostedBLE(); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static void setCustomGattcHandler(gattc_event_handler handler); + static void setCustomGattsHandler(gatts_event_handler handler); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static void onReset(int reason); + static void onSync(void); + static void host_task(void *param); + static String getDeviceName(); + static bool setOwnAddrType(uint8_t type); + static bool setOwnAddr(BLEAddress &addr); + static bool setOwnAddr(uint8_t *addr); + static void setDeviceCallbacks(BLEDeviceCallbacks *cb); + static bool onWhiteList(BLEAddress &address); +#if CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE + // Set SDIO pins for connection to external ESP MCU + static bool setPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst); +#endif +#endif + +private: + friend class BLEClient; + friend class BLEScan; + friend class BLEServer; + friend class BLECharacteristic; + friend class BLEAdvertising; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + static BLEServer *m_pServer; + static BLEScan *m_pScan; + static BLEClient *m_pClient; + static BLESecurityCallbacks *m_securityCallbacks; + static BLEAdvertising *m_bleAdvertising; + static std::map m_connectedClientsMap; + static portMUX_TYPE mux; + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static uint8_t m_ownAddrType; + static bool m_synced; + static std::vector m_whiteList; + static BLEDeviceCallbacks defaultDeviceCallbacks; + static BLEDeviceCallbacks *m_pDeviceCallbacks; + static ble_gap_event_listener m_listener; + static String m_deviceName; +#endif + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static esp_gatt_if_t getGattcIF(); + static void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param); + static void gattServerEventHandler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); + static void gapEventHandler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +#endif +}; // class BLE + +/*************************************************************************** + * NimBLE specific classes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +class BLEDeviceCallbacks { +public: + virtual ~BLEDeviceCallbacks(){}; + virtual int onStoreStatus(struct ble_store_status_event *event, void *arg); +}; +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* MAIN_BLEDevice_H_ */ diff --git a/libraries/BLE/src/BLEEddystoneTLM.cpp b/libraries/BLE/src/BLEEddystoneTLM.cpp new file mode 100644 index 0000000..8b642c8 --- /dev/null +++ b/libraries/BLE/src/BLEEddystoneTLM.cpp @@ -0,0 +1,184 @@ +/* + * BLEEddystoneTLM.cpp + * + * Created on: Mar 12, 2018 + * Author: pcbreflux + * Edited on: Mar 20, 2020 by beegee-tokyo + * Fix temperature value (8.8 fixed format) + * Fix time stamp (0.1 second resolution) + * Fixes based on EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on pcbreflux's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +#include +#include +#include "esp32-hal-log.h" +#include "BLEEddystoneTLM.h" + +static const char LOG_TAG[] = "BLEEddystoneTLM"; + +BLEEddystoneTLM::BLEEddystoneTLM() { + m_eddystoneData.frameType = EDDYSTONE_TLM_FRAME_TYPE; + m_eddystoneData.version = 0; + m_eddystoneData.volt = 3300; // 3300mV = 3.3V + m_eddystoneData.temp = (uint16_t)((float)23.00) / 256; + m_eddystoneData.advCount = 0; + m_eddystoneData.tmil = 0; +} // BLEEddystoneTLM + +BLEEddystoneTLM::BLEEddystoneTLM(BLEAdvertisedDevice *advertisedDevice) { + char *payload = (char *)advertisedDevice->getPayload(); + for (int i = 0; i < advertisedDevice->getPayloadLength(); ++i) { + if (payload[i] == 0x16 && advertisedDevice->getPayloadLength() >= i + 2 + sizeof(m_eddystoneData) && payload[i + 1] == 0xAA && payload[i + 2] == 0xFE + && payload[i + 3] == 0x20) { + log_d("Eddystone TLM data frame starting at byte [%d]", i + 3); + setData(String(payload + i + 3, sizeof(m_eddystoneData))); + break; + } + } +} + +String BLEEddystoneTLM::getData() { + return String((char *)&m_eddystoneData, sizeof(m_eddystoneData)); +} // getData + +BLEUUID BLEEddystoneTLM::getUUID() { + return beaconUUID; +} // getUUID + +uint8_t BLEEddystoneTLM::getVersion() { + return m_eddystoneData.version; +} // getVersion + +uint16_t BLEEddystoneTLM::getVolt() { + return ENDIAN_CHANGE_U16(m_eddystoneData.volt); +} // getVolt + +float BLEEddystoneTLM::getTemp() { + return EDDYSTONE_TEMP_U16_TO_FLOAT(m_eddystoneData.temp); +} // getTemp + +uint16_t BLEEddystoneTLM::getRawTemp() { + return ENDIAN_CHANGE_U16(m_eddystoneData.temp); +} // getRawTemp + +uint32_t BLEEddystoneTLM::getCount() { + return ENDIAN_CHANGE_U32(m_eddystoneData.advCount); +} // getCount + +uint32_t BLEEddystoneTLM::getTime() { + return (ENDIAN_CHANGE_U32(m_eddystoneData.tmil)) / 10; +} // getTime + +String BLEEddystoneTLM::toString() { + String out = ""; + uint32_t rawsec = ENDIAN_CHANGE_U32(m_eddystoneData.tmil); + char val[12]; + + out += "Version " + String(m_eddystoneData.version); + //snprintf(val, sizeof(val), "%d", m_eddystoneData.version); + //out += val; + out += "\n"; + out += "Battery Voltage "; // + ENDIAN_CHANGE_U16(m_eddystoneData.volt); + snprintf(val, sizeof(val), "%d", ENDIAN_CHANGE_U16(m_eddystoneData.volt)); + out += val; + out += " mV\n"; + + out += "Temperature "; + snprintf(val, sizeof(val), "%.2f", ((int16_t)ENDIAN_CHANGE_U16(m_eddystoneData.temp)) / 256.0f); + out += val; + out += " C\n"; + + out += "Adv. Count "; + snprintf(val, sizeof(val), "%ld", ENDIAN_CHANGE_U32(m_eddystoneData.advCount)); + out += val; + out += "\n"; + + out += "Time in seconds "; + snprintf(val, sizeof(val), "%ld", rawsec / 10); + out += val; + out += "\n"; + + out += "Time "; + + snprintf(val, sizeof(val), "%04ld", rawsec / 864000); + out += val; + out += "."; + + snprintf(val, sizeof(val), "%02ld", (rawsec / 36000) % 24); + out += val; + out += ":"; + + snprintf(val, sizeof(val), "%02ld", (rawsec / 600) % 60); + out += val; + out += ":"; + + snprintf(val, sizeof(val), "%02ld", (rawsec / 10) % 60); + out += val; + out += "\n"; + + return out; +} // toString + +/** + * Set the raw data for the beacon record. + * Example: + * uint8_t *payload = advertisedDevice.getPayload(); + * eddystoneTLM.setData(String((char*)payload+22, advertisedDevice.getPayloadLength() - 22)); + * Note: the offset 22 works for current implementation of example BLE_EddystoneTLM Beacon.ino, however + * the position is not static and it is programmers responsibility to align the data. + * Data frame: + * | Field || Len | Type | UUID | EddyStone TLM | + * | Offset || 0 | 1 | 2 | 4 | + * | Len || 1 B | 1 B | 2 B | 14 B | + * | Data || ?? | ?? | 0xAA | 0xFE | ??? | + * + * EddyStone TLM frame: + * | Field || Type | Version | Batt mV | Beacon temp | Cnt since boot | Time since boot | + * | Offset || 0 | 1 | 2 | 4 | 6 | 10 | + * | Len || 1 B | 1 B | 2 B | 2 B | 4 B | 4 B | + * | Data || 0x20 | ?? | ?? | ?? | ?? | ?? | | | | | | | | | + */ +void BLEEddystoneTLM::setData(String data) { + if (data.length() != sizeof(m_eddystoneData)) { + log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_eddystoneData)); + return; + } + memcpy(&m_eddystoneData, data.c_str(), data.length()); +} // setData + +void BLEEddystoneTLM::setUUID(BLEUUID l_uuid) { + beaconUUID = l_uuid; +} // setUUID + +void BLEEddystoneTLM::setVersion(uint8_t version) { + m_eddystoneData.version = version; +} // setVersion + +// Set voltage in ESP32 native Big endian and convert it to little endian used for BLE Frame +void BLEEddystoneTLM::setVolt(uint16_t volt) { + m_eddystoneData.volt = ENDIAN_CHANGE_U16(volt); +} // setVolt + +void BLEEddystoneTLM::setTemp(float temp) { + m_eddystoneData.temp = EDDYSTONE_TEMP_FLOAT_TO_U16(temp); +} // setTemp + +void BLEEddystoneTLM::setCount(uint32_t advCount) { + m_eddystoneData.advCount = advCount; +} // setCount + +void BLEEddystoneTLM::setTime(uint32_t tmil) { + m_eddystoneData.tmil = tmil; +} // setTime + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEEddystoneTLM.h b/libraries/BLE/src/BLEEddystoneTLM.h new file mode 100644 index 0000000..2aa30c2 --- /dev/null +++ b/libraries/BLE/src/BLEEddystoneTLM.h @@ -0,0 +1,70 @@ +/* + * BLEEddystoneTLM.h + * + * Created on: Mar 12, 2018 + * Author: pcbreflux + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on pcbreflux's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef _BLEEddystoneTLM_H_ +#define _BLEEddystoneTLM_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +#include "BLEUUID.h" +#include + +#define EDDYSTONE_TLM_FRAME_TYPE 0x20 +#define ENDIAN_CHANGE_U16(x) ((((x) & 0xFF00) >> 8) + (((x) & 0xFF) << 8)) +#define ENDIAN_CHANGE_U32(x) ((((x) & 0xFF000000) >> 24) + (((x) & 0x00FF0000) >> 8)) + ((((x) & 0xFF00) << 8) + (((x) & 0xFF) << 24)) +#define EDDYSTONE_TEMP_U16_TO_FLOAT(tempU16) (((int16_t)ENDIAN_CHANGE_U16(tempU16)) / 256.0f) +#define EDDYSTONE_TEMP_FLOAT_TO_U16(tempFloat) (ENDIAN_CHANGE_U16(((int)((tempFloat) * 256)))) + +/** + * @brief Representation of a beacon. + * See: + * * https://github.com/google/eddystone + */ +class BLEEddystoneTLM { +public: + BLEEddystoneTLM(); + BLEEddystoneTLM(BLEAdvertisedDevice *advertisedDevice); + String getData(); + BLEUUID getUUID(); + uint8_t getVersion(); + uint16_t getVolt(); + float getTemp(); + uint16_t getRawTemp(); + uint32_t getCount(); + uint32_t getTime(); + String toString(); + void setData(String data); + void setUUID(BLEUUID l_uuid); + void setVersion(uint8_t version); + void setVolt(uint16_t volt); + void setTemp(float temp); + void setCount(uint32_t advCount); + void setTime(uint32_t tmil); + +private: + BLEUUID beaconUUID; + struct { + uint8_t frameType; + uint8_t version; + uint16_t volt; + uint16_t temp; + uint32_t advCount; + uint32_t tmil; + } __attribute__((packed)) m_eddystoneData; +}; // BLEEddystoneTLM + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* _BLEEddystoneTLM_H_ */ diff --git a/libraries/BLE/src/BLEEddystoneURL.cpp b/libraries/BLE/src/BLEEddystoneURL.cpp new file mode 100644 index 0000000..00ca18b --- /dev/null +++ b/libraries/BLE/src/BLEEddystoneURL.cpp @@ -0,0 +1,291 @@ +/* + * BLEEddystoneURL.cpp + * + * Created on: Mar 12, 2018 + * Author: pcbreflux + * + * Upgraded on: Feb 20, 2023 + * By: Tomas Pilny + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on pcbreflux's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +#include +#include "esp32-hal-log.h" +#include "BLEEddystoneURL.h" + +String EDDYSTONE_URL_PREFIX[] = { + "http://www.", // 0x00 + "https://www.", // 0x01 + "http://", // 0x02 + "https://", // 0x03 + "" // Any other code number results in empty string +}; + +String EDDYSTONE_URL_SUFFIX[] = { + ".com/", // 0x00 + ".org/", // 0x01 + ".edu/", // 0x02 + ".net/", // 0x03 + ".info/", // 0x04 + ".biz/", // 0x05 + ".gov/", // 0x06 + ".com", // 0x07 + ".org", // 0x08 + ".edu", // 0x09 + ".net", // 0x0A + ".info", // 0x0B + ".biz", // 0x0C + ".gov", // 0x0D + "" // Any other code number results in empty string +}; + +BLEEddystoneURL::BLEEddystoneURL() { + lengthURL = 0; + m_eddystoneData.advertisedTxPower = 0; + memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url)); + _initHeadder(); +} // BLEEddystoneURL + +BLEEddystoneURL::BLEEddystoneURL(BLEAdvertisedDevice *advertisedDevice) { + const char *payload = (char *)advertisedDevice->getPayload(); + memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url)); + lengthURL = 0; + m_eddystoneData.advertisedTxPower = 0; + for (int i = 0; i < advertisedDevice->getPayloadLength(); ++i) { + if (payload[i] == 0x16 && advertisedDevice->getPayloadLength() >= i + 2 + sizeof(m_eddystoneData) && payload[i + 1] == 0xAA && payload[i + 2] == 0xFE + && payload[i + 3] == 0x10) { + lengthURL = payload[i - 1] - 5; // Subtracting 5 Bytes containing header and other data which are not actual URL data + m_eddystoneData.advertisedTxPower = payload[i + 1]; + if (lengthURL <= 18) { + setData(String(payload + i + 4, lengthURL + 1)); + } else { + log_e("Too long URL %d", lengthURL); + } + } + } + _initHeadder(); +} + +String BLEEddystoneURL::getData() { + return String((char *)&m_eddystoneData, sizeof(m_eddystoneData)); +} // getData + +String BLEEddystoneURL::getFrame() { + BLEHeadder[7] = lengthURL + 5; // Fill in real: Type + 2B UUID + Frame Type + Tx power + URL (note: the Byte holding the length does not count itself) + String frame(BLEHeadder, sizeof(BLEHeadder)); + frame += String((char *)&m_eddystoneData, lengthURL + 1); // + 1 for TX power + + return frame; +} // getFrame + +BLEUUID BLEEddystoneURL::getUUID() { + uint16_t uuid = (((uint16_t)BLEHeadder[10]) << 8) | BLEHeadder[9]; + return BLEUUID(uuid); +} // getUUID + +int8_t BLEEddystoneURL::getPower() { + return m_eddystoneData.advertisedTxPower; +} // getPower + +String BLEEddystoneURL::getURL() { + return String((char *)&m_eddystoneData.url, lengthURL); +} // getURL + +String BLEEddystoneURL::getPrefix() { + if (m_eddystoneData.url[0] <= 0x03) { + return EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]]; + } else { + return ""; + } +} + +String BLEEddystoneURL::getSuffix() { + if (m_eddystoneData.url[lengthURL - 1] <= 0x0D) { + return EDDYSTONE_URL_SUFFIX[m_eddystoneData.url[lengthURL - 1]]; + } else { + return ""; + } +} + +String BLEEddystoneURL::getDecodedURL() { + std::string decodedURL = ""; + decodedURL += getPrefix().c_str(); + if (decodedURL.length() == 0) { // No prefix extracted - interpret byte [0] as character + decodedURL += (char)m_eddystoneData.url[0]; + } + for (int i = 1; i < lengthURL; i++) { + if (m_eddystoneData.url[i] >= 33 && m_eddystoneData.url[i] < 127) { + decodedURL += (char)m_eddystoneData.url[i]; + } else { + if (i != lengthURL - 1 || m_eddystoneData.url[i] > 0x0D) { // Ignore last Byte and values used for suffix + log_e("Unexpected unprintable char in URL 0x%02X: m_eddystoneData.url[%d]", m_eddystoneData.url[i], i); + } + } + } + decodedURL += getSuffix().c_str(); + return String(decodedURL.c_str()); +} // getDecodedURL + +/** + * Set the raw data for the beacon record. + * Example: + * uint8_t *payload = advertisedDevice.getPayload(); + * eddystoneTLM.setData(String((char*)payload+11, advertisedDevice.getPayloadLength() - 11)); + * Note: the offset 11 works for current implementation of example BLE_EddystoneTLM Beacon.ino, however + * the position is not static and it is programmers responsibility to align the data. + * Data frame: + * | Field || Len | Type | UUID | EddyStone URL | + * | Offset || 0 | 1 | 2 | 4 | + * | Len || 1 B | 1 B | 2 B | up to 20 B | + * | Data || ?? | ?? | 0xAA | 0xFE | ??? | + * + * EddyStone TLM frame: + * | Field || Type | TX Power | URL prefix | URL | + * | Offset || 0 | 1 | 2 | 3 | + * | Len || 1 B | 1 B | 1 B | 0-17 B | + * | Data || 0x10 | ?? | ?? | ?? | + */ +void BLEEddystoneURL::setData(String data) { + if (data.length() > sizeof(m_eddystoneData)) { + log_e("Unable to set the data ... length passed in was %d and max expected %d", data.length(), sizeof(m_eddystoneData)); + return; + } + memset(&m_eddystoneData, 0, sizeof(m_eddystoneData)); + memcpy(&m_eddystoneData, data.c_str(), data.length()); + lengthURL = data.length() - (sizeof(m_eddystoneData) - sizeof(m_eddystoneData.url)); +} // setData + +void BLEEddystoneURL::setUUID(BLEUUID l_uuid) { +#if defined(CONFIG_BLUEDROID_ENABLED) + uint16_t beaconUUID = l_uuid.getNative()->uuid.uuid16; +#elif defined(CONFIG_NIMBLE_ENABLED) + uint16_t beaconUUID = l_uuid.getNative()->u16.value; +#endif + BLEHeadder[10] = beaconUUID >> 8; + BLEHeadder[9] = beaconUUID & 0x00FF; +} // setUUID + +void BLEEddystoneURL::setPower(esp_power_level_t advertisedTxPower) { + int tx_power = 0; +#if SOC_BLE_SUPPORTED + switch (advertisedTxPower) { + case ESP_PWR_LVL_N12: tx_power = -12; break; + case ESP_PWR_LVL_N9: tx_power = -9; break; + case ESP_PWR_LVL_N6: tx_power = -6; break; + case ESP_PWR_LVL_N3: tx_power = -3; break; + case ESP_PWR_LVL_N0: tx_power = 0; break; + case ESP_PWR_LVL_P3: tx_power = +3; break; + case ESP_PWR_LVL_P6: tx_power = +6; break; + case ESP_PWR_LVL_P9: tx_power = +9; break; + default: tx_power = 0; break; + } +#else + log_w("setPower not supported with hosted HCI - power controlled by co-processor"); +#endif + m_eddystoneData.advertisedTxPower = int8_t((tx_power - -100) / 2); +} // setPower + +void BLEEddystoneURL::setPower(int8_t advertisedTxPower) { + m_eddystoneData.advertisedTxPower = advertisedTxPower; +} // setPower + +// Set URL bytes including prefix and optional suffix +// | Field | Prefix | URL + optional Suffix | +// | Offset | 0 | 1 | +// | Length | 1 B | 0 - 17 B | +// | Example | 0x02 | 0x676F6F676C65 0x07 | +// | Decoded | http:// | g o o g l e .com | +void BLEEddystoneURL::setURL(String url) { + if (url.length() > sizeof(m_eddystoneData.url)) { + log_e("Unable to set the url ... length passed in was %d and max expected %d", url.length(), sizeof(m_eddystoneData.url)); + return; + } + memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url)); + memcpy(m_eddystoneData.url, url.c_str(), url.length()); + lengthURL = url.length(); +} // setURL + +int BLEEddystoneURL::setSmartURL(String url) { + if (url.length() == 0) { + log_e("URL String has 0 length"); + return 0; // ERROR + } + for (auto character : url) { + if (!isPrintable(character)) { + log_e("URL contains unprintable character(s)"); + return 0; // ERROR + } + } + bool hasPrefix = false; + bool hasSuffix = false; + m_eddystoneData.url[0] = 0x00; // Init with default prefix "http://www." + uint8_t suffix = 0x0E; // Init with empty string + log_d("Encode url \"%s\" with length %d", url.c_str(), url.length()); + for (uint8_t i = 0; i < 4; ++i) { + if (url.substring(0, EDDYSTONE_URL_PREFIX[i].length()) == EDDYSTONE_URL_PREFIX[i]) { + m_eddystoneData.url[0] = i; + hasPrefix = true; + break; + } + } + + if (hasPrefix == false) { + log_w("Prefix not found - using default prefix \"http://www.\" = 0x00\n\tNote: URL must contain one of the prefixes: \"http://www.\", \"https://www.\", " + "\"http://\", \"https://\""); + } + + for (uint8_t i = 0; i < 0x0E; ++i) { + std::string std_url(url.c_str()); + std::string std_suffix(EDDYSTONE_URL_SUFFIX[i].c_str()); + size_t found_pos = std_url.find(std_suffix); + if (found_pos != std::string::npos) { + hasSuffix = true; + suffix = i; + break; + } + } + + size_t baseUrlLen = url.length() - (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0) - EDDYSTONE_URL_SUFFIX[suffix].length(); + lengthURL = baseUrlLen + 1 + (hasSuffix ? 1 : 0); + if (lengthURL > 18) { + log_e("Encoded URL is too long %d B - max 18 B", lengthURL); + return 0; // ERROR + } + String baseUrl = url.substring( + (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0), + baseUrlLen + (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0) + ); + memcpy((void *)(m_eddystoneData.url + 1), (void *)baseUrl.c_str(), baseUrl.length()); // substr for Arduino String + + if (hasSuffix) { + m_eddystoneData.url[1 + baseUrlLen] = suffix; + } + + return 1; // OK +} // setSmartURL + +void BLEEddystoneURL::_initHeadder() { + BLEHeadder[0] = 0x02; // Len + BLEHeadder[1] = 0x01; // Type Flags + BLEHeadder[2] = 0x06; // GENERAL_DISC_MODE 0x02 | BR_EDR_NOT_SUPPORTED 0x04 + BLEHeadder[3] = 0x03; // Len + BLEHeadder[4] = 0x03; // Type 16-Bit UUID + BLEHeadder[5] = 0xAA; // Eddystone UUID 2 -> 0xFEAA LSB + BLEHeadder[6] = 0xFE; // Eddystone UUID 1 MSB + BLEHeadder[7] = 0x00; // Length of Beacon Data shall be calculated later + BLEHeadder[8] = 0x16; // Type Service Data + BLEHeadder[9] = 0xAA; // Eddystone UUID 2 -> 0xFEAA LSB + BLEHeadder[10] = 0xFE; // Eddystone UUID 1 MSB + BLEHeadder[11] = 0x10; // Eddystone Frame Type - URL +} + +#endif +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEEddystoneURL.h b/libraries/BLE/src/BLEEddystoneURL.h new file mode 100644 index 0000000..f220350 --- /dev/null +++ b/libraries/BLE/src/BLEEddystoneURL.h @@ -0,0 +1,72 @@ +/* + * BLEEddystoneURL.cpp + * + * Created on: Mar 12, 2018 + * Author: pcbreflux + * + * Upgraded on: Feb 20, 2023 + * By: Tomas Pilny + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on pcbreflux's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef _BLEEddystoneURL_H_ +#define _BLEEddystoneURL_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +#include "BLEUUID.h" +#include +#if SOC_BLE_SUPPORTED +#include +#endif + +#define EDDYSTONE_URL_FRAME_TYPE 0x10 + +extern String EDDYSTONE_URL_PREFIX[]; +extern String EDDYSTONE_URL_SUFFIX[]; + +/** + * @brief Representation of a beacon. + * See: + * * https://github.com/google/eddystone + */ +class BLEEddystoneURL { +public: + BLEEddystoneURL(); + BLEEddystoneURL(BLEAdvertisedDevice *advertisedDevice); + String getData(); + String getFrame(); + BLEUUID getUUID(); + int8_t getPower(); + String getURL(); + String getPrefix(); + String getSuffix(); + String getDecodedURL(); + void setData(String data); + void setUUID(BLEUUID l_uuid); + void setPower(int8_t advertisedTxPower); + void setPower(esp_power_level_t advertisedTxPower); + void setURL(String url); + int setSmartURL(String url); + +private: + uint8_t + lengthURL; // Describes the length of the URL part including prefix and optional suffix - max 18 B (excluding TX power, frame type and preceding header) + struct { + int8_t advertisedTxPower; + uint8_t url[18]; // Byte [0] is for prefix. Last valid byte **can** contain suffix - i.e. the next byte after the URL + } __attribute__((packed)) m_eddystoneData; + void _initHeadder(); + char BLEHeadder[12]; +}; // BLEEddystoneURL + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* _BLEEddystoneURL_H_ */ diff --git a/libraries/BLE/src/BLEExceptions.cpp b/libraries/BLE/src/BLEExceptions.cpp new file mode 100644 index 0000000..f566f78 --- /dev/null +++ b/libraries/BLE/src/BLEExceptions.cpp @@ -0,0 +1,14 @@ +/* + * BLExceptions.cpp + * + * Created on: Nov 27, 2017 + * Author: kolban + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) + +//#include "BLEExceptions.h" + +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEExceptions.h b/libraries/BLE/src/BLEExceptions.h new file mode 100644 index 0000000..91cb184 --- /dev/null +++ b/libraries/BLE/src/BLEExceptions.h @@ -0,0 +1,35 @@ +/* + * BLExceptions.h + * + * Created on: Nov 27, 2017 + * Author: kolban + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_ +#define COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) + +#if CONFIG_CXX_EXCEPTIONS != 1 +#error "C++ exception handling must be enabled within make menuconfig. See Compiler Options > Enable C++ Exceptions." +#endif + +#include + +class BLEDisconnectedException : public std::exception { + const char *what() const throw() { + return "BLE Disconnected"; + } +}; + +class BLEUuidNotFoundException : public std::exception { + const char *what() const throw() { + return "No such UUID"; + } +}; + +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_ */ diff --git a/libraries/BLE/src/BLEHIDDevice.cpp b/libraries/BLE/src/BLEHIDDevice.cpp new file mode 100644 index 0000000..7fff815 --- /dev/null +++ b/libraries/BLE/src/BLEHIDDevice.cpp @@ -0,0 +1,326 @@ +/* + * BLEHIDDevice.cpp + * + * Created on: Jan 03, 2018 + * Author: chegewara + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "BLEHIDDevice.h" +#include "BLE2904.h" +#include "BLEDescriptor.h" + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#ifdef CONFIG_NIMBLE_ENABLED +#include +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLEHIDDevice::BLEHIDDevice(BLEServer *server) { + m_server = server; + /* + * Here we create mandatory services described in bluetooth specification + */ + m_deviceInfoService = server->createService(BLEUUID((uint16_t)0x180a)); + m_hidService = server->createService(BLEUUID((uint16_t)0x1812), 40); + m_batteryService = server->createService(BLEUUID((uint16_t)0x180f)); + + /* + * Mandatory characteristic for device info service + */ + m_pnpCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t)0x2a50, BLECharacteristic::PROPERTY_READ); + + /* + * Mandatory characteristics for HID service + */ + m_hidInfoCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4a, BLECharacteristic::PROPERTY_READ); + m_reportMapCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4b, BLECharacteristic::PROPERTY_READ); + m_hidControlCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4c, BLECharacteristic::PROPERTY_WRITE_NR); + m_protocolModeCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4e, BLECharacteristic::PROPERTY_WRITE_NR | BLECharacteristic::PROPERTY_READ); + + /* + * Mandatory battery level characteristic with notification and presence descriptor + */ + BLE2904 *batteryLevelDescriptor = new BLE2904(); + batteryLevelDescriptor->setFormat(BLE2904::FORMAT_UINT8); + batteryLevelDescriptor->setNamespace(1); + batteryLevelDescriptor->setUnit(0x27ad); + + m_batteryLevelCharacteristic = + m_batteryService->createCharacteristic((uint16_t)0x2a19, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY); + m_batteryLevelCharacteristic->addDescriptor(batteryLevelDescriptor); +#if CONFIG_BLUEDROID_ENABLED + BLE2902 *batLevelIndicator = new BLE2902(); + // Battery Level Notification is ON by default, making it work always on BLE Pairing and Bonding + batLevelIndicator->setNotifications(true); + // IMPORTANT: CCCD must be accessible without encryption for HID enumeration + batLevelIndicator->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + m_batteryLevelCharacteristic->addDescriptor(batLevelIndicator); +#endif + + /* + * This value is setup here because its default value in most usage cases, its very rare to use boot mode + * and we want to simplify library using as much as possible + */ + const uint8_t pMode[] = {0x01}; + protocolMode()->setValue((uint8_t *)pMode, 1); +} + +BLEHIDDevice::~BLEHIDDevice() {} + +/* + * @brief + */ +void BLEHIDDevice::reportMap(uint8_t *map, uint16_t size) { + m_reportMapCharacteristic->setValue(map, size); +} + +/* + * @brief This function suppose to be called at the end, when we have created all characteristics we need to build HID service + */ +void BLEHIDDevice::startServices() { + m_deviceInfoService->start(); + m_hidService->start(); + m_batteryService->start(); + m_server->start(); +} + +/* + * @brief Create manufacturer characteristic (this characteristic is optional) + */ +BLECharacteristic *BLEHIDDevice::manufacturer() { + m_manufacturerCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t)0x2a29, BLECharacteristic::PROPERTY_READ); + return m_manufacturerCharacteristic; +} + +/* + * @brief Set manufacturer name + * @param [in] name manufacturer name + */ +void BLEHIDDevice::manufacturer(String name) { + m_manufacturerCharacteristic->setValue(name); +} + +/* + * @brief + */ +void BLEHIDDevice::pnp(uint8_t sig, uint16_t vid, uint16_t pid, uint16_t version) { + uint8_t pnp[] = {sig, (uint8_t)(vid >> 8), (uint8_t)vid, (uint8_t)(pid >> 8), (uint8_t)pid, (uint8_t)(version >> 8), (uint8_t)version}; + m_pnpCharacteristic->setValue(pnp, sizeof(pnp)); +} + +/* + * @brief + */ +void BLEHIDDevice::hidInfo(uint8_t country, uint8_t flags) { + uint8_t info[] = {0x11, 0x1, country, flags}; + m_hidInfoCharacteristic->setValue(info, sizeof(info)); +} + +/* + * @brief Create input report characteristic that need to be saved as new characteristic object so can be further used + * @param [in] reportID input report ID, the same as in report map for input object related to created characteristic + * @return pointer to new input report characteristic + */ +BLECharacteristic *BLEHIDDevice::inputReport(uint8_t reportID) { + // Note: READ_ENC removed per HOGP specification - characteristics must be readable without encryption for enumeration + // Actual report data is still encrypted via BLE connection encryption after pairing + uint32_t properties = BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY; + // For NimBLE: Characteristic encryption properties can be added if needed + // For Bluedroid: Standard properties, permissions set separately below + + BLECharacteristic *inputReportCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4d, properties); + BLEDescriptor *inputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908)); + + // For Bluedroid: Set access permissions (ignored by NimBLE, but doesn't hurt) + inputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED); + + // IMPORTANT: Report Reference Descriptor must be readable without encryption per HOGP specification + // HID hosts must read Report ID and Report Type during enumeration (before encryption is established) + // The descriptor only contains metadata; actual HID reports are encrypted via BLE connection + inputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + + uint8_t desc1_val[] = {reportID, 0x01}; + inputReportDescriptor->setValue((uint8_t *)desc1_val, 2); + inputReportCharacteristic->addDescriptor(inputReportDescriptor); + +#if CONFIG_BLUEDROID_ENABLED + BLE2902 *p2902 = new BLE2902(); + // IMPORTANT: CCCD must be readable/writable without encryption for HID enumeration + // Host needs to enable notifications before encryption is established + p2902->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + inputReportCharacteristic->addDescriptor(p2902); +#endif + + return inputReportCharacteristic; +} + +/* + * @brief Create output report characteristic that need to be saved as new characteristic object so can be further used + * @param [in] reportID Output report ID, the same as in report map for output object related to created characteristic + * @return Pointer to new output report characteristic + */ +BLECharacteristic *BLEHIDDevice::outputReport(uint8_t reportID) { + // Note: Encryption properties removed per HOGP specification - characteristics must be readable without encryption for enumeration + // Actual report data is still encrypted via BLE connection encryption after pairing + uint32_t properties = BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR; + // For NimBLE: Characteristic encryption properties can be added if needed + // For Bluedroid: Standard properties, permissions set separately below + + BLECharacteristic *outputReportCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4d, properties); + BLEDescriptor *outputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908)); + + // For Bluedroid: Set access permissions (ignored by NimBLE, but doesn't hurt) + outputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED); + + // IMPORTANT: Report Reference Descriptor must be readable without encryption for HID enumeration + outputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + + uint8_t desc1_val[] = {reportID, 0x02}; + outputReportDescriptor->setValue((uint8_t *)desc1_val, 2); + outputReportCharacteristic->addDescriptor(outputReportDescriptor); + + return outputReportCharacteristic; +} + +/* + * @brief Create feature report characteristic that need to be saved as new characteristic object so can be further used + * @param [in] reportID Feature report ID, the same as in report map for feature object related to created characteristic + * @return Pointer to new feature report characteristic + */ +BLECharacteristic *BLEHIDDevice::featureReport(uint8_t reportID) { + // Note: Encryption properties removed per HOGP specification - characteristics must be readable without encryption for enumeration + // Actual report data is still encrypted via BLE connection encryption after pairing + uint32_t properties = BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE; + // For NimBLE: Characteristic encryption properties can be added if needed + // For Bluedroid: Standard properties, permissions set separately below + + BLECharacteristic *featureReportCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4d, properties); + BLEDescriptor *featureReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908)); + + // For Bluedroid: Set access permissions (ignored by NimBLE, but doesn't hurt) + featureReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED); + + // IMPORTANT: Report Reference Descriptor must be readable without encryption for HID enumeration + featureReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + + uint8_t desc1_val[] = {reportID, 0x03}; + featureReportDescriptor->setValue((uint8_t *)desc1_val, 2); + featureReportCharacteristic->addDescriptor(featureReportDescriptor); + + return featureReportCharacteristic; +} + +/* + * @brief Create boot input characteristic + */ +BLECharacteristic *BLEHIDDevice::bootInput() { + // Note: READ_ENC removed to match input report behavior + // Boot mode characteristics follow same security model as report mode + uint32_t properties = BLECharacteristic::PROPERTY_NOTIFY; + + BLECharacteristic *bootInputCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a22, properties); +#if CONFIG_BLUEDROID_ENABLED + BLE2902 *bootInputCCCD = new BLE2902(); + // IMPORTANT: CCCD must be accessible without encryption for HID enumeration + bootInputCCCD->setAccessPermissions(ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE); + bootInputCharacteristic->addDescriptor(bootInputCCCD); +#endif + + return bootInputCharacteristic; +} + +/* + * @brief + */ +BLECharacteristic *BLEHIDDevice::bootOutput() { + return m_hidService->createCharacteristic( + (uint16_t)0x2a32, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR + ); +} + +/* + * @brief + */ +BLECharacteristic *BLEHIDDevice::hidControl() { + return m_hidControlCharacteristic; +} + +/* + * @brief + */ +BLECharacteristic *BLEHIDDevice::protocolMode() { + return m_protocolModeCharacteristic; +} + +void BLEHIDDevice::setBatteryLevel(uint8_t level) { + m_batteryLevelCharacteristic->setValue(&level, 1); + if (m_server->isStarted()) { + m_batteryLevelCharacteristic->notify(); + } +} +/* + * @brief Returns battery level characteristic + * @ return battery level characteristic + */ +/* +BLECharacteristic* BLEHIDDevice::batteryLevel() { + return m_batteryLevelCharacteristic; +} + + + +BLECharacteristic* BLEHIDDevice::reportMap() { + return m_reportMapCharacteristic; +} + +BLECharacteristic* BLEHIDDevice::pnp() { + return m_pnpCharacteristic; +} + + +BLECharacteristic* BLEHIDDevice::hidInfo() { + return m_hidInfoCharacteristic; +} +*/ +/* + * @brief + */ +BLEService *BLEHIDDevice::deviceInfo() { + return m_deviceInfoService; +} + +/* + * @brief + */ +BLEService *BLEHIDDevice::hidService() { + return m_hidService; +} + +/* + * @brief + */ +BLEService *BLEHIDDevice::batteryService() { + return m_batteryService; +} + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEHIDDevice.h b/libraries/BLE/src/BLEHIDDevice.h new file mode 100644 index 0000000..5239ca5 --- /dev/null +++ b/libraries/BLE/src/BLEHIDDevice.h @@ -0,0 +1,85 @@ +/* + * BLEHIDDevice.h + * + * Created on: Jan 03, 2018 + * Author: chegewara + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef _BLEHIDDEVICE_H_ +#define _BLEHIDDEVICE_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +#include "BLECharacteristic.h" +#include "BLEService.h" +#include "BLEDescriptor.h" +#include "BLE2902.h" +#include "HIDTypes.h" + +#define GENERIC_HID 0x03C0 +#define HID_KEYBOARD 0x03C1 +#define HID_MOUSE 0x03C2 +#define HID_JOYSTICK 0x03C3 +#define HID_GAMEPAD 0x03C4 +#define HID_TABLET 0x03C5 +#define HID_CARD_READER 0x03C6 +#define HID_DIGITAL_PEN 0x03C7 +#define HID_BARCODE 0x03C8 +#define HID_BRAILLE_DISPLAY 0x03C9 + +class BLEHIDDevice { +public: + BLEHIDDevice(BLEServer *); + virtual ~BLEHIDDevice(); + + void reportMap(uint8_t *map, uint16_t); + void startServices(); + + BLEService *deviceInfo(); + BLEService *hidService(); + BLEService *batteryService(); + + BLECharacteristic *manufacturer(); + void manufacturer(String name); + //BLECharacteristic* pnp(); + void pnp(uint8_t sig, uint16_t vid, uint16_t pid, uint16_t version); + //BLECharacteristic* hidInfo(); + void hidInfo(uint8_t country, uint8_t flags); + //BLECharacteristic* batteryLevel(); + void setBatteryLevel(uint8_t level); + + //BLECharacteristic* reportMap(); + BLECharacteristic *hidControl(); + BLECharacteristic *inputReport(uint8_t reportID); + BLECharacteristic *outputReport(uint8_t reportID); + BLECharacteristic *featureReport(uint8_t reportID); + BLECharacteristic *protocolMode(); + BLECharacteristic *bootInput(); + BLECharacteristic *bootOutput(); + +private: + BLEServer *m_server; + BLEService *m_deviceInfoService; //0x180a + BLEService *m_hidService; //0x1812 + BLEService *m_batteryService = 0; //0x180f + + BLECharacteristic *m_manufacturerCharacteristic; //0x2a29 + BLECharacteristic *m_pnpCharacteristic; //0x2a50 + BLECharacteristic *m_hidInfoCharacteristic; //0x2a4a + BLECharacteristic *m_reportMapCharacteristic; //0x2a4b + BLECharacteristic *m_hidControlCharacteristic; //0x2a4c + BLECharacteristic *m_protocolModeCharacteristic; //0x2a4e + BLECharacteristic *m_batteryLevelCharacteristic; //0x2a19 +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* _BLEHIDDEVICE_H_ */ diff --git a/libraries/BLE/src/BLERemoteCharacteristic.cpp b/libraries/BLE/src/BLERemoteCharacteristic.cpp new file mode 100644 index 0000000..70a9128 --- /dev/null +++ b/libraries/BLE/src/BLERemoteCharacteristic.cpp @@ -0,0 +1,1036 @@ +/* + * BLERemoteCharacteristic.cpp + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include + +#include +#include "WString.h" +//#include "BLEExceptions.h" +#include "BLEUtils.h" +#include "GeneralUtils.h" +#include "BLERemoteCharacteristic.h" +#include "BLERemoteDescriptor.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#include +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + *@brief Destructor. + */ +BLERemoteCharacteristic::~BLERemoteCharacteristic() { + removeDescriptors(); // Release resources for any descriptor information we may have allocated. + free(m_rawData); +} // ~BLERemoteCharacteristic + +/** + * @brief Does the characteristic support broadcasting? + * @return True if the characteristic supports broadcasting. + */ +bool BLERemoteCharacteristic::canBroadcast() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_BROADCAST) != 0; +} // canBroadcast + +/** + * @brief Does the characteristic support indications? + * @return True if the characteristic supports indications. + */ +bool BLERemoteCharacteristic::canIndicate() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_INDICATE) != 0; +} // canIndicate + +/** + * @brief Does the characteristic support notifications? + * @return True if the characteristic supports notifications. + */ +bool BLERemoteCharacteristic::canNotify() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_NOTIFY) != 0; +} // canNotify + +/** + * @brief Does the characteristic support reading? + * @return True if the characteristic supports reading. + */ +bool BLERemoteCharacteristic::canRead() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_READ) != 0; +} // canRead + +/** + * @brief Does the characteristic support writing? + * @return True if the characteristic supports writing. + */ +bool BLERemoteCharacteristic::canWrite() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE) != 0; +} // canWrite + +/** + * @brief Does the characteristic support writing with no response? + * @return True if the characteristic supports writing with no response. + */ +bool BLERemoteCharacteristic::canWriteNoResponse() { + return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) != 0; +} // canWriteNoResponse + +/** + * @brief Retrieve the map of descriptors keyed by UUID. + */ +std::map *BLERemoteCharacteristic::getDescriptors() { + // Retrieve descriptors if not already done (lazy loading) + if (!m_descriptorsRetrieved) { + log_d("Descriptors not yet retrieved, retrieving now..."); + retrieveDescriptors(); + } + return &m_descriptorMap; +} // getDescriptors + +/** + * @brief Get the handle for this characteristic. + * @return The handle for this characteristic. + */ +uint16_t BLERemoteCharacteristic::getHandle() { + //log_v(">> getHandle: Characteristic: %s", getUUID().toString().c_str()); + //log_v("<< getHandle: %d 0x%.2x", m_handle, m_handle); + return m_handle; +} // getHandle + +/** + * @brief Get the descriptor instance with the given UUID that belongs to this characteristic. + * @param [in] uuid The UUID of the descriptor to find. + * @return The Remote descriptor (if present) or null if not present. + */ +BLERemoteDescriptor *BLERemoteCharacteristic::getDescriptor(BLEUUID uuid) { + log_v(">> getDescriptor: uuid: %s", uuid.toString().c_str()); + // Retrieve descriptors if not already done (lazy loading) + if (!m_descriptorsRetrieved) { + log_d("Descriptors not yet retrieved, retrieving now..."); + retrieveDescriptors(); + } + std::string v = uuid.toString().c_str(); + for (auto &myPair : m_descriptorMap) { + if (myPair.first == v) { + log_v("<< getDescriptor: found"); + return myPair.second; + } + } + log_v("<< getDescriptor: Not found"); + return nullptr; +} // getDescriptor + +/** + * @brief Get the remote service associated with this characteristic. + * @return The remote service associated with this characteristic. + */ +BLERemoteService *BLERemoteCharacteristic::getRemoteService() { + return m_pRemoteService; +} // getRemoteService + +/** + * @brief Get the UUID for this characteristic. + * @return The UUID for this characteristic. + */ +BLEUUID BLERemoteCharacteristic::getUUID() { + return m_uuid; +} // getUUID + +/** + * @brief Read an unsigned 16 bit value + * @return The unsigned 16 bit value. + */ +uint16_t BLERemoteCharacteristic::readUInt16() { + String value = readValue(); + if (value.length() >= 2) { + return *(uint16_t *)(value.c_str()); + } + return 0; +} // readUInt16 + +/** + * @brief Read an unsigned 32 bit value. + * @return the unsigned 32 bit value. + */ +uint32_t BLERemoteCharacteristic::readUInt32() { + String value = readValue(); + if (value.length() >= 4) { + return *(uint32_t *)(value.c_str()); + } + return 0; +} // readUInt32 + +/** + * @brief Read a byte value + * @return The value as a byte + */ +uint8_t BLERemoteCharacteristic::readUInt8() { + String value = readValue(); + if (value.length() >= 1) { + return (uint8_t)value[0]; + } + return 0; +} // readUInt8 + +/** + * @brief Read a float value. + * @return the float value. + */ +float BLERemoteCharacteristic::readFloat() { + String value = readValue(); + if (value.length() >= 4) { + return *(float *)(value.c_str()); + } + return 0.0; +} // readFloat + +/** + * @brief Register for notifications. + * @param [in] notifyCallback A callback to be invoked for a notification. If NULL is provided then we are + * unregistering a notification. + * @return N/A. + */ +void BLERemoteCharacteristic::registerForNotify(notify_callback notifyCallback, bool notifications, bool descriptorRequiresRegistration) { + log_v(">> registerForNotify(): %s", toString().c_str()); + +#if defined(CONFIG_BLUEDROID_ENABLED) + m_notifyCallback = notifyCallback; // Save the notification callback. + + m_semaphoreRegForNotifyEvt.take("registerForNotify"); + + if (notifyCallback != nullptr) { // If we have a callback function, then this is a registration. + esp_err_t errRc = ::esp_ble_gattc_register_for_notify( + m_pRemoteService->getClient()->getGattcIf(), m_pRemoteService->getClient()->getPeerAddress().getNative(), getHandle() + ); + + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_register_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + + uint8_t val[] = {0x01, 0x00}; + if (!notifications) { + val[0] = 0x02; + } + BLERemoteDescriptor *desc = getDescriptor(BLEUUID((uint16_t)0x2902)); + if (desc != nullptr && descriptorRequiresRegistration) { + desc->writeValue(val, 2, true); + } + } // End Register + else { // If we weren't passed a callback function, then this is an unregistration. + esp_err_t errRc = ::esp_ble_gattc_unregister_for_notify( + m_pRemoteService->getClient()->getGattcIf(), m_pRemoteService->getClient()->getPeerAddress().getNative(), getHandle() + ); + + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_unregister_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + } + + uint8_t val[] = {0x00, 0x00}; + BLERemoteDescriptor *desc = getDescriptor((uint16_t)0x2902); + if (desc != nullptr && descriptorRequiresRegistration) { + desc->writeValue(val, 2, true); + } + } // End Unregister + + m_semaphoreRegForNotifyEvt.wait("registerForNotify"); + +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + bool success; + if (notifyCallback != nullptr) { + success = subscribe(notifications, notifyCallback, descriptorRequiresRegistration); + } else { + success = unsubscribe(descriptorRequiresRegistration); + } + + if (!success) { + log_e("Failed to subscribe/unsubscribe for notify"); + } +#endif + log_v("<< registerForNotify()"); +} // registerForNotify + +/** + * @brief Delete the descriptors in the descriptor map. + * We maintain a map called m_descriptorMap that contains pointers to BLERemoteDescriptors + * object references. Since we allocated these in this class, we are also responsible for deleting + * them. This method does just that. + * @return N/A. + */ +void BLERemoteCharacteristic::removeDescriptors() { + // Iterate through all the descriptors releasing their storage and erasing them from the map. + for (auto &myPair : m_descriptorMap) { + delete myPair.second; + } + m_descriptorMap.clear(); + m_descriptorsRetrieved = false; // Allow descriptors to be retrieved again +} // removeCharacteristics + +/** + * @brief Convert a BLERemoteCharacteristic to a string representation; + * @return a String representation. + */ +String BLERemoteCharacteristic::toString() { + String res = "Characteristic: uuid: " + m_uuid.toString(); + char val[6]; + res += ", handle: "; + snprintf(val, sizeof(val), "%d", getHandle()); + res += val; + res += " 0x"; + snprintf(val, sizeof(val), "%04x", getHandle()); + res += val; + res += ", props: " + BLEUtils::characteristicPropertiesToString(m_charProp); + return res; +} // toString + +/** + * @brief Write the new value for the characteristic. + * @param [in] newValue The new value to write. + * @param [in] response Do we expect a response? + * @return N/A. + */ +bool BLERemoteCharacteristic::writeValue(String newValue, bool response) { + return writeValue((uint8_t *)newValue.c_str(), newValue.length(), response); +} // writeValue + +/** + * @brief Write the new value for the characteristic. + * + * This is a convenience function. Many BLE characteristics are a single byte of data. + * @param [in] newValue The new byte value to write. + * @param [in] response Whether we require a response from the write. + * @return N/A. + */ +bool BLERemoteCharacteristic::writeValue(uint8_t newValue, bool response) { + return writeValue(&newValue, 1, response); +} // writeValue + +/** + * @brief Read raw data from remote characteristic as hex bytes + * @return return pointer data read + */ +uint8_t *BLERemoteCharacteristic::readRawData() { + return m_rawData; +} + +/** + * @brief Set authentication request type for characteristic + * @param [in] auth Authentication request type. + */ +void BLERemoteCharacteristic::setAuth(uint8_t auth) { + m_auth = auth; +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Constructor. + * @param [in] handle The BLE server side handle of this characteristic. + * @param [in] uuid The UUID of this characteristic. + * @param [in] charProp The properties of this characteristic. + * @param [in] pRemoteService A reference to the remote service to which this remote characteristic pertains. + */ +BLERemoteCharacteristic::BLERemoteCharacteristic(uint16_t handle, BLEUUID uuid, esp_gatt_char_prop_t charProp, BLERemoteService *pRemoteService) { + log_v(">> BLERemoteCharacteristic: handle: %d 0x%d, uuid: %s", handle, handle, uuid.toString().c_str()); + m_handle = handle; + m_uuid = uuid; + m_charProp = charProp; + m_pRemoteService = pRemoteService; + m_notifyCallback = nullptr; + m_rawData = nullptr; + m_auth = ESP_GATT_AUTH_REQ_NONE; + m_descriptorsRetrieved = false; + + retrieveDescriptors(); // Get the descriptors for this characteristic + log_v("<< BLERemoteCharacteristic"); +} // BLERemoteCharacteristic + +/** + * @brief Handle GATT Client events. + * When an event arrives for a GATT client we give this characteristic the opportunity to + * take a look at it to see if there is interest in it. + * @param [in] event The type of event. + * @param [in] gattc_if The interface on which the event was received. + * @param [in] evtParam Payload data for the event. + * @returns N/A + */ +void BLERemoteCharacteristic::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) { + switch (event) { + // ESP_GATTC_NOTIFY_EVT + // + // notify + // - uint16_t conn_id - The connection identifier of the server. + // - esp_bd_addr_t remote_bda - The device address of the BLE server. + // - uint16_t handle - The handle of the characteristic for which the event is being received. + // - uint16_t value_len - The length of the received data. + // - uint8_t* value - The received data. + // - bool is_notify - True if this is a notify, false if it is an indicate. + // + // We have received a notification event which means that the server wishes us to know about a notification + // piece of data. What we must now do is find the characteristic with the associated handle and then + // invoke its notification callback (if it has one). + case ESP_GATTC_NOTIFY_EVT: + { + if (evtParam->notify.handle != getHandle()) { + break; + } + if (m_notifyCallback != nullptr) { + log_d("Invoking callback for notification on characteristic %s", toString().c_str()); + m_notifyCallback(this, evtParam->notify.value, evtParam->notify.value_len, evtParam->notify.is_notify); + } // End we have a callback function ... + break; + } // ESP_GATTC_NOTIFY_EVT + + // ESP_GATTC_READ_CHAR_EVT + // This event indicates that the server has responded to the read request. + // + // read: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - uint16_t handle + // - uint8_t* value + // - uint16_t value_len + case ESP_GATTC_READ_CHAR_EVT: + { + // If this event is not for us, then nothing further to do. + if (evtParam->read.handle != getHandle()) { + break; + } + + // At this point, we have determined that the event is for us, so now we save the value + // and unlock the semaphore to ensure that the requester of the data can continue. + if (evtParam->read.status == ESP_GATT_OK) { + m_value = String((char *)evtParam->read.value, evtParam->read.value_len); + if (m_rawData != nullptr) { + free(m_rawData); + } + m_rawData = (uint8_t *)calloc(evtParam->read.value_len, sizeof(uint8_t)); + memcpy(m_rawData, evtParam->read.value, evtParam->read.value_len); + } else { + m_value = ""; + } + + m_semaphoreReadCharEvt.give(); + break; + } // ESP_GATTC_READ_CHAR_EVT + + // ESP_GATTC_REG_FOR_NOTIFY_EVT + // + // reg_for_notify: + // - esp_gatt_status_t status + // - uint16_t handle + case ESP_GATTC_REG_FOR_NOTIFY_EVT: + { + // If the request is not for this BLERemoteCharacteristic then move on to the next. + if (evtParam->reg_for_notify.handle != getHandle()) { + break; + } + + // We have processed the notify registration and can unlock the semaphore. + m_semaphoreRegForNotifyEvt.give(); + break; + } // ESP_GATTC_REG_FOR_NOTIFY_EVT + + // ESP_GATTC_UNREG_FOR_NOTIFY_EVT + // + // unreg_for_notify: + // - esp_gatt_status_t status + // - uint16_t handle + case ESP_GATTC_UNREG_FOR_NOTIFY_EVT: + { + if (evtParam->unreg_for_notify.handle != getHandle()) { + break; + } + // We have processed the notify un-registration and can unlock the semaphore. + m_semaphoreRegForNotifyEvt.give(); + break; + } // ESP_GATTC_UNREG_FOR_NOTIFY_EVT: + + // ESP_GATTC_WRITE_CHAR_EVT + // + // write: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - uint16_t handle + case ESP_GATTC_WRITE_CHAR_EVT: + { + // Determine if this event is for us and, if not, pass onwards. + if (evtParam->write.handle != getHandle()) { + break; + } + + // There is nothing further we need to do here. This is merely an indication + // that the write has completed and we can unlock the caller. + m_semaphoreWriteCharEvt.give(); + break; + } // ESP_GATTC_WRITE_CHAR_EVT + + case ESP_GATTC_READ_DESCR_EVT: + case ESP_GATTC_WRITE_DESCR_EVT: + for (auto &myPair : m_descriptorMap) { + myPair.second->gattClientEventHandler(event, gattc_if, evtParam); + } + break; + + case ESP_GATTC_DISCONNECT_EVT: + // Cleanup semaphores to avoid deadlocks. + m_semaphoreReadCharEvt.give(1); + m_semaphoreWriteCharEvt.give(1); + break; + + default: break; + } // End switch +}; // gattClientEventHandler + +/** + * @brief Populate the descriptors (if any) for this characteristic. + */ +void BLERemoteCharacteristic::retrieveDescriptors() { + log_v(">> retrieveDescriptors() for characteristic: %s", getUUID().toString().c_str()); + + removeDescriptors(); // Remove any existing descriptors. + + // Loop over each of the descriptors within the service associated with this characteristic. + // For each descriptor we find, create a BLERemoteDescriptor instance. + uint16_t offset = 0; + esp_gattc_descr_elem_t result; + while (true) { + uint16_t count = 10; + esp_gatt_status_t status = ::esp_ble_gattc_get_all_descr( + getRemoteService()->getClient()->getGattcIf(), getRemoteService()->getClient()->getConnId(), getHandle(), &result, &count, offset + ); + + if (status == ESP_GATT_INVALID_OFFSET) { // We have reached the end of the entries. + break; + } + + if (status != ESP_GATT_OK) { + log_e("esp_ble_gattc_get_all_descr: %s", BLEUtils::gattStatusToString(status).c_str()); + break; + } + + if (count == 0) { + break; + } + + log_d("Found a descriptor: Handle: %d, UUID: %s", result.handle, BLEUUID(result.uuid).toString().c_str()); + + // We now have a new characteristic ... let us add that to our set of known characteristics + BLERemoteDescriptor *pNewRemoteDescriptor = new BLERemoteDescriptor(result.handle, BLEUUID(result.uuid), this); + + m_descriptorMap.insert(std::pair(pNewRemoteDescriptor->getUUID().toString().c_str(), pNewRemoteDescriptor)); + + offset++; + } // while true + //m_haveCharacteristics = true; // Remember that we have received the characteristics. + m_descriptorsRetrieved = true; + log_v("<< retrieveDescriptors(): Found %d descriptors.", offset); +} // getDescriptors + +/** + * @brief Read the value of the remote characteristic. + * @return The value of the remote characteristic. + */ +String BLERemoteCharacteristic::readValue() { + log_v(">> readValue(): uuid: %s, handle: %d 0x%.2x", getUUID().toString().c_str(), getHandle(), getHandle()); + + // Check to see that we are connected. + if (!getRemoteService()->getClient()->isConnected()) { + log_e("Disconnected"); + return String(); + } + + // Wait for authentication to complete if bonding is enabled + // This prevents the read request from being made while pairing is in progress + BLESecurity::waitForAuthenticationComplete(); + + m_semaphoreReadCharEvt.take("readValue"); + + // Ask the BLE subsystem to retrieve the value for the remote hosted characteristic. + // This is an asynchronous request which means that we must block waiting for the response + // to become available. + esp_err_t errRc = ::esp_ble_gattc_read_char( + m_pRemoteService->getClient()->getGattcIf(), + m_pRemoteService->getClient()->getConnId(), // The connection ID to the BLE server + getHandle(), // The handle of this characteristic + (esp_gatt_auth_req_t)m_auth + ); // Security + + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return ""; + } + + // Block waiting for the event that indicates that the read has completed. When it has, the String found + // in m_value will contain our data. + m_semaphoreReadCharEvt.wait("readValue"); + + log_v("<< readValue(): length: %d", m_value.length()); + return m_value; +} // readValue + +/** + * @brief Write the new value for the characteristic from a data buffer. + * @param [in] data A pointer to a data buffer. + * @param [in] length The length of the data in the data buffer. + * @param [in] response Whether we require a response from the write. + * @return True if successful + */ +bool BLERemoteCharacteristic::writeValue(uint8_t *data, size_t length, bool response) { + // writeValue(String((char*)data, length), response); + log_v(">> writeValue(), length: %d", length); + + // Check to see that we are connected. + if (!getRemoteService()->getClient()->isConnected()) { + log_e("Disconnected"); + return false; + } + + // Wait for authentication to complete if bonding is enabled + // This prevents the write request from being made while pairing is in progress + BLESecurity::waitForAuthenticationComplete(); + + m_semaphoreWriteCharEvt.take("writeValue"); + // Invoke the ESP-IDF API to perform the write. + esp_err_t errRc = ::esp_ble_gattc_write_char( + m_pRemoteService->getClient()->getGattcIf(), m_pRemoteService->getClient()->getConnId(), getHandle(), length, data, + response ? ESP_GATT_WRITE_TYPE_RSP : ESP_GATT_WRITE_TYPE_NO_RSP, (esp_gatt_auth_req_t)m_auth + ); + + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_write_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + + m_semaphoreWriteCharEvt.wait("writeValue"); + + log_v("<< writeValue"); + return true; +} // writeValue + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Constructor. + * @param [in] reference to the service this characteristic belongs to. + * @param [in] ble_gatt_chr struct defined as: + * struct ble_gatt_chr { + * uint16_t def_handle; + * uint16_t val_handle; + * uint8_t properties; + * ble_uuid_any_t uuid; + * }; + */ +BLERemoteCharacteristic::BLERemoteCharacteristic(BLERemoteService *pRemoteService, const struct ble_gatt_chr *chr) { + log_v(">> BLERemoteCharacteristic()"); + switch (chr->uuid.u.type) { + case BLE_UUID_TYPE_16: m_uuid = BLEUUID(chr->uuid.u16.value); break; + case BLE_UUID_TYPE_32: m_uuid = BLEUUID(chr->uuid.u32.value); break; + case BLE_UUID_TYPE_128: m_uuid = BLEUUID(const_cast(&chr->uuid.u128)); break; + default: break; + } + + m_handle = chr->val_handle; + m_defHandle = chr->def_handle; + m_charProp = chr->properties; + m_pRemoteService = pRemoteService; + m_notifyCallback = nullptr; + m_rawData = nullptr; + m_auth = 0; + m_descriptorsRetrieved = false; + + // Don't retrieve descriptors in constructor for NimBLE to avoid deadlock + // Descriptors will be retrieved on-demand when needed (e.g., for notifications) + + log_v("<< BLERemoteCharacteristic(): %s", m_uuid.toString().c_str()); +} // BLERemoteCharacteristic + +/** + * @brief Callback used by the API when a descriptor is discovered or search complete. + */ +int BLERemoteCharacteristic::descriptorDiscCB( + uint16_t conn_handle, const struct ble_gatt_error *error, uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, void *arg +) { + int rc = error->status; + log_d("Descriptor Discovered >> status: %d handle: %d", rc, (rc == 0) ? dsc->handle : -1); + + desc_filter_t *filter = (desc_filter_t *)arg; + const BLEUUID *uuid_filter = filter->uuid; + BLETaskData *pTaskData = (BLETaskData *)filter->task_data; + BLERemoteCharacteristic *characteristic = (BLERemoteCharacteristic *)pTaskData->m_pInstance; + + if (characteristic->getRemoteService()->getClient()->getConnId() != conn_handle) { + return 0; + } + + if (rc == 0 && characteristic->getHandle() == chr_val_handle && (!uuid_filter || ble_uuid_cmp(&uuid_filter->getNative()->u, &dsc->uuid.u) == 0)) { + BLERemoteDescriptor *pNewRemoteDescriptor = new BLERemoteDescriptor(characteristic, dsc); + characteristic->m_descriptorMap.insert( + std::pair(pNewRemoteDescriptor->getUUID().toString().c_str(), pNewRemoteDescriptor) + ); + rc = !!uuid_filter * BLE_HS_EDONE; + } + + if (rc != 0) { + BLEUtils::taskRelease(*pTaskData, rc); + log_d("<< Descriptor Discovery"); + } + + return rc; +} + +/** + * @brief Callback for characteristic read operation. + * @return success == 0 or error code. + */ +int BLERemoteCharacteristic::onReadCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg) { + BLETaskData *pTaskData = static_cast(arg); + BLERemoteCharacteristic *characteristic = static_cast(pTaskData->m_pInstance); + + if (error->status == BLE_HS_ENOTCONN) { + log_e("<< Characteristic Read; Not connected"); + BLEUtils::taskRelease(*pTaskData, error->status); + return error->status; + } + + if (characteristic->getRemoteService()->getClient()->getConnId() != conn_handle) { + return 0; + } + + int rc = error->status; + log_i("Read complete; status=%d conn_handle=%d", rc, conn_handle); + + String *strBuf = (String *)pTaskData->m_pBuf; + + if (rc == 0) { + if (attr) { + uint32_t data_len = OS_MBUF_PKTLEN(attr->om); + if (((*strBuf).length() + data_len) > BLE_ATT_ATTR_MAX_LEN) { + rc = BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } else { + log_i("Got %d bytes", data_len); + (*strBuf) += String((char *)attr->om->om_data, data_len); + return 0; + } + } + } + + BLEUtils::taskRelease(*pTaskData, rc); + return rc; +} + +/** + * @brief Callback for characteristic write operation. + * @return success == 0 or error code. + */ +int BLERemoteCharacteristic::onWriteCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg) { + BLETaskData *pTaskData = static_cast(arg); + BLERemoteCharacteristic *characteristic = static_cast(pTaskData->m_pInstance); + + if (error->status == BLE_HS_ENOTCONN) { + log_e("<< Characteristic Write; Not connected"); + BLEUtils::taskRelease(*pTaskData, error->status); + return error->status; + } + + if (characteristic->getRemoteService()->getClient()->getConnId() != conn_handle) { + return 0; + } + + log_i("Write complete; status=%d conn_handle=%d", error->status, conn_handle); + BLEUtils::taskRelease(*pTaskData, error->status); + return 0; +} + +/** + * @brief Populate the descriptors (if any) for this characteristic. + * @param [in] the end handle of the characteristic, or the service, whichever comes first. + */ +bool BLERemoteCharacteristic::retrieveDescriptors(const BLEUUID *uuid_filter) { + log_d(">> retrieveDescriptors() for characteristic: %s", getUUID().toString().c_str()); + + // If this is the last handle then there are no descriptors + if (m_handle == getRemoteService()->getEndHandle()) { + m_descriptorsRetrieved = true; + log_d("<< retrieveDescriptors(): No descriptors found"); + return true; + } + + BLETaskData taskData(const_cast(this)); + desc_filter_t filter = {uuid_filter, &taskData}; + int rc = 0; + + rc = ble_gattc_disc_all_dscs( + getRemoteService()->getClient()->getConnId(), m_handle, getRemoteService()->getEndHandle(), BLERemoteCharacteristic::descriptorDiscCB, &filter + ); + + if (rc != 0) { + log_e("ble_gattc_disc_all_dscs: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + + [[maybe_unused]] + size_t prevDscCount = m_descriptorMap.size(); + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = ((BLETaskData *)filter.task_data)->m_flags; + + if (rc != BLE_HS_EDONE) { + log_e("<< retrieveDescriptors(): failed: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + + m_descriptorsRetrieved = true; + log_d("<< retrieveDescriptors(): Found %d descriptors.", m_descriptorMap.size() - prevDscCount); + return true; +} // retrieveDescriptors + +/** + * @brief Read the value of the remote characteristic. + * @return The value of the remote characteristic. + */ +String BLERemoteCharacteristic::readValue() { + log_d(">> readValue(): uuid: %s, handle: %d 0x%.2x", getUUID().toString().c_str(), getHandle(), getHandle()); + + BLEClient *pClient = getRemoteService()->getClient(); + String value{}; + + if (!pClient->isConnected()) { + log_e("Disconnected"); + return value; + } + + int rc = 0; + int retryCount = 1; + BLETaskData taskData(const_cast(this), 0, &value); + + do { + rc = ble_gattc_read_long(pClient->getConnId(), m_handle, 0, BLERemoteCharacteristic::onReadCB, &taskData); + if (rc != 0) { + goto exit; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = taskData.m_flags; + + switch (rc) { + case 0: + case BLE_HS_EDONE: rc = 0; break; + // Characteristic is not long-readable, return with what we have. + case BLE_HS_ATT_ERR(BLE_ATT_ERR_ATTR_NOT_LONG): + log_i("Attribute not long"); + rc = ble_gattc_read(pClient->getConnId(), m_handle, BLERemoteCharacteristic::onReadCB, &taskData); + if (rc != 0) { + goto exit; + } + retryCount++; + break; + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHEN): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHOR): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_ENC): + if (BLESecurity::m_securityEnabled && retryCount && pClient->secureConnection()) { + break; + } + /* Else falls through. */ + default: goto exit; + } + } while (rc != 0 && retryCount--); + + m_semaphoreReadCharEvt.take("readValue"); + m_value = value; + m_rawData = (uint8_t *)calloc(value.length(), sizeof(uint8_t)); + for (size_t i = 0; i < value.length(); i++) { + m_rawData[i] = value[i]; + } + m_semaphoreReadCharEvt.give(); + +exit: + if (rc != 0) { + log_e("<< readValue failed rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + } else { + log_d("<< readValue length: %d rc=%d", value.length(), rc); + } + + return value; +} // readValue + +/** + * @brief Write the new value for the characteristic from a data buffer. + * @param [in] data A pointer to a data buffer. + * @param [in] length The length of the data in the data buffer. + * @param [in] response Whether we require a response from the write. + * @return false if not connected or cant perform write for some reason. + */ +bool BLERemoteCharacteristic::writeValue(uint8_t *data, size_t length, bool response) { + log_d(">> writeValue(), length: %d", length); + + BLEClient *pClient = getRemoteService()->getClient(); + + if (!pClient->isConnected()) { + log_e("Disconnected"); + return false; + } + + int rc = 0; + int retryCount = 1; + uint16_t mtu = ble_att_mtu(pClient->getConnId()) - 3; + BLETaskData taskData(const_cast(this)); + + // Check if the data length is longer than we can write in one connection event. + // If so we must do a long write which requires a response. + if (length <= mtu && !response) { + rc = ble_gattc_write_no_rsp_flat(pClient->getConnId(), m_handle, data, length); + goto exit; + } + + do { + if (length > mtu) { + log_i("long write %d bytes", length); + os_mbuf *om = ble_hs_mbuf_from_flat(data, length); + rc = ble_gattc_write_long(pClient->getConnId(), m_handle, 0, om, BLERemoteCharacteristic::onWriteCB, &taskData); + } else { + rc = ble_gattc_write_flat(pClient->getConnId(), m_handle, data, length, BLERemoteCharacteristic::onWriteCB, &taskData); + } + if (rc != 0) { + goto exit; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = taskData.m_flags; + + switch (rc) { + case 0: + case BLE_HS_EDONE: rc = 0; break; + case BLE_HS_ATT_ERR(BLE_ATT_ERR_ATTR_NOT_LONG): + log_e("Long write not supported by peer; Truncating length to %d", mtu); + retryCount++; + length = mtu; + break; + + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHEN): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHOR): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_ENC): + if (BLESecurity::m_securityEnabled && retryCount && pClient->secureConnection()) { + break; + } + /* Else falls through. */ + default: goto exit; + } + } while (rc != 0 && retryCount--); + +exit: + if (rc != 0) { + log_e("<< writeValue failed rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + } else { + log_d("<< writeValue success. length: %d rc=%d", length, rc); + } + + return (rc == 0); +} // writeValue + +/** + * @brief Subscribe or unsubscribe for notifications or indications. + * @param [in] val 0x00 to unsubscribe, 0x01 for notifications, 0x02 for indications. + * @param [in] notifyCallback A callback to be invoked for a notification. + * @param [in] response If write response required set this to true. + * If NULL is provided then no callback is performed. + * @return false if writing to the descriptor failed. + */ +bool BLERemoteCharacteristic::setNotify(uint16_t val, notify_callback notifyCallback, bool response) { + log_v(">> setNotify(): %s, %02x", toString().c_str(), val); + + m_notifyCallback = notifyCallback; + + // Retrieve descriptors if not already done (lazy loading) + if (!m_descriptorsRetrieved) { + log_d("Descriptors not yet retrieved, retrieving now..."); + if (!retrieveDescriptors()) { + log_e("<< setNotify(): Failed to retrieve descriptors"); + return false; + } + } + + BLERemoteDescriptor *desc = getDescriptor(BLEUUID((uint16_t)0x2902)); + if (desc == nullptr) { + log_w("<< setNotify(): Callback set, CCCD not found"); + return true; + } + + log_d("<< setNotify()"); + + response = true; // Always write with response as per Bluetooth core specification. + return desc->writeValue((uint8_t *)&val, 2, response); +} // setNotify + +/** + * @brief Subscribe for notifications or indications. + * @param [in] notifications If true, subscribe for notifications, false subscribe for indications. + * @param [in] notifyCallback A callback to be invoked for a notification. + * @param [in] response If true, require a write response from the descriptor write operation. + * If NULL is provided then no callback is performed. + * @return false if writing to the descriptor failed. + */ +bool BLERemoteCharacteristic::subscribe(bool notifications, notify_callback notifyCallback, bool response) { + if (notifications) { + return setNotify(0x01, notifyCallback, response); + } else { + return setNotify(0x02, notifyCallback, response); + } +} // subscribe + +/** + * @brief Unsubscribe for notifications or indications. + * @param [in] response bool if true, require a write response from the descriptor write operation. + * @return false if writing to the descriptor failed. + */ +bool BLERemoteCharacteristic::unsubscribe(bool response) { + return setNotify(0x00, nullptr, response); +} // unsubscribe + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLERemoteCharacteristic.h b/libraries/BLE/src/BLERemoteCharacteristic.h new file mode 100644 index 0000000..7b04a15 --- /dev/null +++ b/libraries/BLE/src/BLERemoteCharacteristic.h @@ -0,0 +1,198 @@ +/* + * BLERemoteCharacteristic.h + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_ +#define COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLERemoteService.h" +#include "BLERemoteDescriptor.h" +#include "BLEUUID.h" +#include "RTOS.h" +#include "BLEUtils.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes and definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include + +// Bluedroid Compatibility +#define ESP_GATT_MAX_ATTR_LEN BLE_ATT_ATTR_MAX_LEN +#define ESP_GATT_CHAR_PROP_BIT_READ BLE_GATT_CHR_PROP_READ +#define ESP_GATT_CHAR_PROP_BIT_WRITE BLE_GATT_CHR_PROP_WRITE +#define ESP_GATT_CHAR_PROP_BIT_WRITE_NR BLE_GATT_CHR_PROP_WRITE_NO_RSP +#define ESP_GATT_CHAR_PROP_BIT_BROADCAST BLE_GATT_CHR_PROP_BROADCAST +#define ESP_GATT_CHAR_PROP_BIT_NOTIFY BLE_GATT_CHR_PROP_NOTIFY +#define ESP_GATT_CHAR_PROP_BIT_INDICATE BLE_GATT_CHR_PROP_INDICATE + +#define ESP_GATT_AUTH_REQ_NONE 0 +#define ESP_GATT_AUTH_REQ_NO_MITM 1 +#define ESP_GATT_AUTH_REQ_MITM 2 +#define ESP_GATT_AUTH_REQ_SIGNED_NO_MITM 3 +#define ESP_GATT_AUTH_REQ_SIGNED_MITM 4 + +#endif + +/*************************************************************************** + * Common types * + ***************************************************************************/ + +typedef std::function notify_callback; + +/*************************************************************************** + * NimBLE types * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +typedef struct { + const BLEUUID *uuid; + void *task_data; +} desc_filter_t; +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLERemoteService; +class BLERemoteDescriptor; + +/** + * @brief A model of a remote %BLE characteristic. + */ +class BLERemoteCharacteristic { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + ~BLERemoteCharacteristic(); + bool canBroadcast(); + bool canIndicate(); + bool canNotify(); + bool canRead(); + bool canWrite(); + bool canWriteNoResponse(); + BLERemoteDescriptor *getDescriptor(BLEUUID uuid); + std::map *getDescriptors(); + BLERemoteService *getRemoteService(); + uint16_t getHandle(); + BLEUUID getUUID(); + String readValue(); + uint8_t readUInt8(); + uint16_t readUInt16(); + uint32_t readUInt32(); + float readFloat(); + void registerForNotify(notify_callback _callback, bool notifications = true, bool descriptorRequiresRegistration = true); + bool writeValue(uint8_t *data, size_t length, bool response = false); + bool writeValue(String newValue, bool response = false); + bool writeValue(uint8_t newValue, bool response = false); + String toString(); + uint8_t *readRawData(); + void setAuth(uint8_t auth); + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + bool subscribe(bool notifications = true, notify_callback notifyCallback = nullptr, bool response = true); + bool unsubscribe(bool response = true); +#endif + +private: + friend class BLEClient; + friend class BLERemoteService; + friend class BLERemoteDescriptor; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLEUUID m_uuid; + uint8_t m_charProp; + uint8_t m_auth; + uint16_t m_handle; + BLERemoteService *m_pRemoteService; + FreeRTOS::Semaphore m_semaphoreReadCharEvt = FreeRTOS::Semaphore("ReadCharEvt"); + FreeRTOS::Semaphore m_semaphoreRegForNotifyEvt = FreeRTOS::Semaphore("RegForNotifyEvt"); + FreeRTOS::Semaphore m_semaphoreWriteCharEvt = FreeRTOS::Semaphore("WriteCharEvt"); + String m_value; + uint8_t *m_rawData; + notify_callback m_notifyCallback; + + // We maintain a map of descriptors owned by this characteristic keyed by a string representation of the UUID. + std::map m_descriptorMap; + bool m_descriptorsRetrieved; // Flag to track if descriptor retrieval has been attempted + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + uint16_t m_defHandle; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void removeDescriptors(); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + BLERemoteCharacteristic(uint16_t handle, BLEUUID uuid, uint8_t charProp, BLERemoteService *pRemoteService); + void retrieveDescriptors(); + void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam); +#endif + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + BLERemoteCharacteristic(BLERemoteService *pRemoteservice, const struct ble_gatt_chr *chr); + bool setNotify(uint16_t val, notify_callback notifyCallback = nullptr, bool response = true); + bool retrieveDescriptors(const BLEUUID *uuid_filter = nullptr); + static int onReadCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg); + static int onWriteCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg); + static int descriptorDiscCB(uint16_t conn_handle, const struct ble_gatt_error *error, uint16_t chr_val_handle, const struct ble_gatt_dsc *dsc, void *arg); +#endif +}; // BLERemoteCharacteristic + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_ */ diff --git a/libraries/BLE/src/BLERemoteDescriptor.cpp b/libraries/BLE/src/BLERemoteDescriptor.cpp new file mode 100644 index 0000000..e7cd3af --- /dev/null +++ b/libraries/BLE/src/BLERemoteDescriptor.cpp @@ -0,0 +1,482 @@ +/* + * BLERemoteDescriptor.cpp + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "WString.h" +#include +#include "BLERemoteDescriptor.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#include +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLERemoteDescriptor::BLERemoteDescriptor(uint16_t handle, BLEUUID uuid, BLERemoteCharacteristic *pRemoteCharacteristic) { + m_handle = handle; + m_uuid = uuid; + m_pRemoteCharacteristic = pRemoteCharacteristic; + m_auth = 0; +} + +/** + * @brief Retrieve the handle associated with this remote descriptor. + * @return The handle associated with this remote descriptor. + */ +uint16_t BLERemoteDescriptor::getHandle() { + return m_handle; +} // getHandle + +/** + * @brief Get the characteristic that owns this descriptor. + * @return The characteristic that owns this descriptor. + */ +BLERemoteCharacteristic *BLERemoteDescriptor::getRemoteCharacteristic() { + return m_pRemoteCharacteristic; +} // getRemoteCharacteristic + +/** + * @brief Retrieve the UUID associated this remote descriptor. + * @return The UUID associated this remote descriptor. + */ +BLEUUID BLERemoteDescriptor::getUUID() { + return m_uuid; +} // getUUID + +uint8_t BLERemoteDescriptor::readUInt8() { + String value = readValue(); + if (value.length() >= 1) { + return (uint8_t)value[0]; + } + return 0; +} // readUInt8 + +uint16_t BLERemoteDescriptor::readUInt16() { + String value = readValue(); + if (value.length() >= 2) { + return *(uint16_t *)value.c_str(); + } + return 0; +} // readUInt16 + +uint32_t BLERemoteDescriptor::readUInt32() { + String value = readValue(); + if (value.length() >= 4) { + return *(uint32_t *)value.c_str(); + } + return 0; +} // readUInt32 + +/** + * @brief Return a string representation of this BLE Remote Descriptor. + * @return A string representation of this BLE Remote Descriptor. + */ +String BLERemoteDescriptor::toString() { + char val[6]; + snprintf(val, sizeof(val), "%d", getHandle()); + String res = "handle: "; + res += val; + res += ", uuid: " + getUUID().toString(); + return res; +} // toString + +/** + * @brief Write data represented as a string to the BLE Remote Descriptor. + * @param [in] newValue The data to send to the remote descriptor. + * @param [in] response True if we expect a response. + */ +bool BLERemoteDescriptor::writeValue(String newValue, bool response) { + return writeValue((uint8_t *)newValue.c_str(), newValue.length(), response); +} // writeValue + +/** + * @brief Write a byte value to the Descriptor. + * @param [in] The single byte to write. + * @param [in] True if we expect a response. + */ +bool BLERemoteDescriptor::writeValue(uint8_t newValue, bool response) { + return writeValue(&newValue, 1, response); +} // writeValue + +/** + * @brief Set authentication request type for characteristic + * @param [in] auth Authentication request type. + */ +void BLERemoteDescriptor::setAuth(uint8_t auth) { + m_auth = auth; +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +void BLERemoteDescriptor::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) { + switch (event) { + // ESP_GATTC_READ_DESCR_EVT + // This event indicates that the server has responded to the read request. + // + // read: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - uint16_t handle + // - uint8_t* value + // - uint16_t value_len + case ESP_GATTC_READ_DESCR_EVT: + // If this event is not for us, then nothing further to do. + if (evtParam->read.handle != getHandle()) { + break; + } + // At this point, we have determined that the event is for us, so now we save the value + if (evtParam->read.status == ESP_GATT_OK) { + // it will read the cached value of the descriptor + m_value = String((char *)evtParam->read.value, evtParam->read.value_len); + } else { + m_value = ""; + } + // Unlock the semaphore to ensure that the requester of the data can continue. + m_semaphoreReadDescrEvt.give(); + break; + + case ESP_GATTC_WRITE_DESCR_EVT: + if (evtParam->write.handle != getHandle()) { + break; + } + m_semaphoreWriteDescrEvt.give(); + break; + default: break; + } +} + +String BLERemoteDescriptor::readValue() { + log_v(">> readValue: %s", toString().c_str()); + + // Check to see that we are connected. + if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) { + log_e("Disconnected"); + return String(); + } + + m_semaphoreReadDescrEvt.take("readValue"); + + // Ask the BLE subsystem to retrieve the value for the remote hosted characteristic. + esp_err_t errRc = ::esp_ble_gattc_read_char_descr( + m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(), + m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(), // The connection ID to the BLE server + getHandle(), // The handle of this characteristic + (esp_gatt_auth_req_t)m_auth + ); // Security + + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return ""; + } + + // Block waiting for the event that indicates that the read has completed. When it has, the String found + // in m_value will contain our data. + m_semaphoreReadDescrEvt.wait("readValue"); + + log_v("<< readValue(): length: %d", m_value.length()); + return m_value; +} // readValue + +/** + * @brief Write data to the BLE Remote Descriptor. + * @param [in] data The data to send to the remote descriptor. + * @param [in] length The length of the data to send. + * @param [in] response True if we expect a response. + * @return True if successful + */ +bool BLERemoteDescriptor::writeValue(uint8_t *data, size_t length, bool response) { + log_v(">> writeValue: %s", toString().c_str()); + // Check to see that we are connected. + if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) { + log_e("Disconnected"); + return false; + } + + m_semaphoreWriteDescrEvt.take("writeValue"); + + esp_err_t errRc = ::esp_ble_gattc_write_char_descr( + m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(), m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(), getHandle(), + length, // Data length + data, // Data + response ? ESP_GATT_WRITE_TYPE_RSP : ESP_GATT_WRITE_TYPE_NO_RSP, (esp_gatt_auth_req_t)m_auth + ); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_write_char_descr: %d", errRc); + } + + m_semaphoreWriteDescrEvt.wait("writeValue"); + log_v("<< writeValue"); + return (errRc == ESP_OK); +} // writeValue + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Remote descriptor constructor. + * @param [in] pRemoteCharacteristic A pointer to the Characteristic that this belongs to. + * @param [in] dsc A pointer to the struct that contains the descriptor information. + */ +BLERemoteDescriptor::BLERemoteDescriptor(BLERemoteCharacteristic *pRemoteCharacteristic, const struct ble_gatt_dsc *dsc) { + log_d(">> BLERemoteDescriptor()"); + switch (dsc->uuid.u.type) { + case BLE_UUID_TYPE_16: m_uuid = BLEUUID(dsc->uuid.u16.value); break; + case BLE_UUID_TYPE_32: m_uuid = BLEUUID(dsc->uuid.u32.value); break; + case BLE_UUID_TYPE_128: m_uuid = BLEUUID(const_cast(&dsc->uuid.u128)); break; + default: break; + } + + m_handle = dsc->handle; + m_pRemoteCharacteristic = pRemoteCharacteristic; + m_auth = 0; + + log_d("<< BLERemoteDescriptor(): %s", m_uuid.toString().c_str()); +} + +/** + * @brief Read the value of the remote descriptor. + * @return The value of the remote descriptor. + */ +String BLERemoteDescriptor::readValue() { + log_d(">> Descriptor readValue: %s", toString().c_str()); + + BLEClient *pClient = getRemoteCharacteristic()->getRemoteService()->getClient(); + String value{}; + + if (!pClient->isConnected()) { + log_e("Disconnected"); + return value; + } + + int rc = 0; + int retryCount = 1; + BLETaskData taskData(const_cast(this), 0, &value); + + do { + rc = ble_gattc_read_long(pClient->getConnId(), m_handle, 0, BLERemoteDescriptor::onReadCB, &taskData); + if (rc != 0) { + goto exit; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = taskData.m_flags; + + switch (rc) { + case 0: + case BLE_HS_EDONE: rc = 0; break; + // Descriptor is not long-readable, return with what we have. + case BLE_HS_ATT_ERR(BLE_ATT_ERR_ATTR_NOT_LONG): + log_i("Attribute not long"); + rc = ble_gattc_read(pClient->getConnId(), m_handle, BLERemoteDescriptor::onReadCB, &taskData); + if (rc != 0) { + goto exit; + } + retryCount++; + break; + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHEN): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHOR): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_ENC): + if (BLESecurity::m_securityEnabled && retryCount && pClient->secureConnection()) { + break; + } + /* Else falls through. */ + default: goto exit; + } + } while (rc != 0 && retryCount--); + + m_semaphoreReadDescrEvt.take("readValue"); + m_value = value; + m_semaphoreReadDescrEvt.give(); + +exit: + if (rc != 0) { + log_e("<< readValue failed rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + } else { + log_d("<< Descriptor readValue(): length: %d rc=%d", value.length(), rc); + } + + return value; +} // readValue + +/** + * @brief Callback for Descriptor read operation. + * @return success == 0 or error code. + */ +int BLERemoteDescriptor::onReadCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg) { + BLETaskData *pTaskData = static_cast(arg); + BLERemoteDescriptor *desc = static_cast(pTaskData->m_pInstance); + uint16_t conn_id = desc->getRemoteCharacteristic()->getRemoteService()->getClient()->getConnId(); + + if (error->status == BLE_HS_ENOTCONN) { + log_e("<< Descriptor Read; Not connected"); + BLEUtils::taskRelease(*pTaskData, error->status); + return error->status; + } + + if (conn_id != conn_handle) { + return 0; + } + + log_d("Read complete; status=%d conn_handle=%d", error->status, conn_handle); + + String *strBuf = static_cast(pTaskData->m_pBuf); + int rc = error->status; + + if (rc == 0) { + if (attr) { + uint32_t data_len = OS_MBUF_PKTLEN(attr->om); + if (((*strBuf).length() + data_len) > BLE_ATT_ATTR_MAX_LEN) { + rc = BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN; + } else { + log_d("Got %d bytes", data_len); + (*strBuf) += String((char *)attr->om->om_data, data_len); + return 0; + } + } + } + + BLEUtils::taskRelease(*pTaskData, rc); + return rc; +} + +/** + * @brief Callback for descriptor write operation. + * @return success == 0 or error code. + */ +int BLERemoteDescriptor::onWriteCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg) { + BLETaskData *pTaskData = static_cast(arg); + BLERemoteDescriptor *descriptor = static_cast(pTaskData->m_pInstance); + int rc = error->status; + + if (rc == BLE_HS_ENOTCONN) { + log_e("<< Descriptor Write; Not connected"); + BLEUtils::taskRelease(*pTaskData, rc); + return rc; + } + + if (descriptor->getRemoteCharacteristic()->getRemoteService()->getClient()->getConnId() != conn_handle) { + return 0; + } + + log_i("Write complete; status=%d conn_handle=%d", rc, conn_handle); + + BLEUtils::taskRelease(*pTaskData, rc); + return 0; +} + +/** + * @brief Write data to the BLE Remote Descriptor. + * @param [in] data The data to send to the remote descriptor. + * @param [in] length The length of the data to send. + * @param [in] response True if we expect a write response. + * @return True if successful + */ +bool BLERemoteDescriptor::writeValue(uint8_t *data, size_t length, bool response) { + log_d(">> Descriptor writeValue: %s", toString().c_str()); + + BLEClient *pClient = getRemoteCharacteristic()->getRemoteService()->getClient(); + + // Check to see that we are connected. + if (!pClient->isConnected()) { + log_e("Disconnected"); + return false; + } + + int rc = 0; + int retryCount = 1; + uint16_t mtu = ble_att_mtu(pClient->getConnId()) - 3; + BLETaskData taskData(const_cast(this)); + + // Check if the data length is longer than we can write in 1 connection event. + // If so we must do a long write which requires a response. + if (length <= mtu && !response) { + rc = ble_gattc_write_no_rsp_flat(pClient->getConnId(), m_handle, data, length); + goto exit; + } + + do { + if (length > mtu) { + log_i("long write %d bytes", length); + os_mbuf *om = ble_hs_mbuf_from_flat(data, length); + rc = ble_gattc_write_long(pClient->getConnId(), m_handle, 0, om, BLERemoteDescriptor::onWriteCB, &taskData); + } else { + rc = ble_gattc_write_flat(pClient->getConnId(), m_handle, data, length, BLERemoteDescriptor::onWriteCB, &taskData); + } + + if (rc != 0) { + goto exit; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = taskData.m_flags; + + switch (rc) { + case 0: + case BLE_HS_EDONE: rc = 0; break; + case BLE_HS_ATT_ERR(BLE_ATT_ERR_ATTR_NOT_LONG): + log_e("Long write not supported by peer; Truncating length to %d", mtu); + retryCount++; + length = mtu; + break; + + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHEN): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_AUTHOR): + case BLE_HS_ATT_ERR(BLE_ATT_ERR_INSUFFICIENT_ENC): + if (BLESecurity::m_securityEnabled && retryCount && pClient->secureConnection()) { + break; + } + /* Else falls through. */ + default: goto exit; + } + } while (rc != 0 && retryCount--); + +exit: + if (rc != 0) { + log_e("<< writeValue failed rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + } else { + log_d("<< writeValue success. length: %d rc=%d", length, rc); + } + + return (rc == 0); +} // writeValue + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLERemoteDescriptor.h b/libraries/BLE/src/BLERemoteDescriptor.h new file mode 100644 index 0000000..ea55fb8 --- /dev/null +++ b/libraries/BLE/src/BLERemoteDescriptor.h @@ -0,0 +1,108 @@ +/* + * BLERemoteDescriptor.h + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_ +#define COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLERemoteCharacteristic.h" +#include "BLEUUID.h" +#include "RTOS.h" +#include "BLEUtils.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLERemoteCharacteristic; + +/** + * @brief A model of remote %BLE descriptor. + */ +class BLERemoteDescriptor { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + uint16_t getHandle(); + BLERemoteCharacteristic *getRemoteCharacteristic(); + BLEUUID getUUID(); + String readValue(void); + uint8_t readUInt8(void); + uint16_t readUInt16(void); + uint32_t readUInt32(void); + String toString(void); + bool writeValue(uint8_t *data, size_t length, bool response = false); + bool writeValue(String newValue, bool response = false); + bool writeValue(uint8_t newValue, bool response = false); + void setAuth(uint8_t auth); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam); +#endif + +private: + friend class BLERemoteCharacteristic; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + uint16_t m_handle; // Server handle of this descriptor. + BLEUUID m_uuid; // UUID of this descriptor. + String m_value; // Last received value of the descriptor. + uint8_t m_auth; + BLERemoteCharacteristic *m_pRemoteCharacteristic; // Reference to the Remote characteristic of which this descriptor is associated. + FreeRTOS::Semaphore m_semaphoreReadDescrEvt = FreeRTOS::Semaphore("ReadDescrEvt"); + FreeRTOS::Semaphore m_semaphoreWriteDescrEvt = FreeRTOS::Semaphore("WriteDescrEvt"); + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + BLERemoteDescriptor(uint16_t handle, BLEUUID uuid, BLERemoteCharacteristic *pRemoteCharacteristic); + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + BLERemoteDescriptor(BLERemoteCharacteristic *pRemoteCharacteristic, const struct ble_gatt_dsc *dsc); + static int onWriteCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg); + static int onReadCB(uint16_t conn_handle, const struct ble_gatt_error *error, struct ble_gatt_attr *attr, void *arg); +#endif +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_ */ diff --git a/libraries/BLE/src/BLERemoteService.cpp b/libraries/BLE/src/BLERemoteService.cpp new file mode 100644 index 0000000..3cec816 --- /dev/null +++ b/libraries/BLE/src/BLERemoteService.cpp @@ -0,0 +1,426 @@ +/* + * BLERemoteService.cpp + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLERemoteService.h" +#include "BLEUtils.h" +#include "GeneralUtils.h" +#include +#include "esp32-hal-log.h" + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +BLERemoteService::~BLERemoteService() { + removeCharacteristics(); +} + +/** + * @brief Get the remote characteristic object for the characteristic UUID. + * @param [in] uuid Remote characteristic uuid. + * @return Reference to the remote characteristic object. + * @throws BLEUuidNotFoundException + */ +BLERemoteCharacteristic *BLERemoteService::getCharacteristic(const char *uuid) { + return getCharacteristic(BLEUUID(uuid)); +} // getCharacteristic + +/** + * @brief Get the characteristic object for the UUID. + * @param [in] uuid Characteristic uuid. + * @return Reference to the characteristic object. + * @throws BLEUuidNotFoundException + */ +BLERemoteCharacteristic *BLERemoteService::getCharacteristic(BLEUUID uuid) { + // Design + // ------ + // We wish to retrieve the characteristic given its UUID. It is possible that we have not yet asked the + // device what characteristics it has in which case we have nothing to match against. If we have not + // asked the device about its characteristics, then we do that now. Once we get the results we can then + // examine the characteristics map to see if it has the characteristic we are looking for. + if (!m_haveCharacteristics) { + retrieveCharacteristics(); + } + std::string v = uuid.toString().c_str(); + for (auto &myPair : m_characteristicMap) { + if (myPair.first == v) { + return myPair.second; + } + } + // throw new BLEUuidNotFoundException(); // <-- we dont want exception here, which will cause app crash, we want to search if any characteristic can be found one after another + return nullptr; +} // getCharacteristic + +/** + * @brief Retrieve a map of all the characteristics of this service. + * @return A map of all the characteristics of this service. + */ +std::map *BLERemoteService::getCharacteristics() { + log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str()); + // If is possible that we have not read the characteristics associated with the service so do that + // now. The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking + // call and does not return until all the characteristics are available. + if (!m_haveCharacteristics) { + retrieveCharacteristics(); + } + log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str()); + return &m_characteristicMap; +} // getCharacteristics + +/** + * @brief Retrieve a map of all the characteristics of this service. + * @return A map of all the characteristics of this service. + */ +std::map *BLERemoteService::getCharacteristicsByHandle() { + // If is possible that we have not read the characteristics associated with the service so do that + // now. The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking + // call and does not return until all the characteristics are available. + if (!m_haveCharacteristics) { + retrieveCharacteristics(); + } + return &m_characteristicMapByHandle; +} // getCharacteristicsByHandle + +/** + * @brief This function is designed to get characteristics map when we have multiple characteristics with the same UUID + */ +void BLERemoteService::getCharacteristics(std::map **pCharacteristicMap) { + log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str()); + (void)pCharacteristicMap; + // If is possible that we have not read the characteristics associated with the service so do that + // now. The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking + // call and does not return until all the characteristics are available. + if (!m_haveCharacteristics) { + retrieveCharacteristics(); + } + log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str()); + *pCharacteristicMap = &m_characteristicMapByHandle; +} // Get the characteristics map. + +/** + * @brief Get the client associated with this service. + * @return A reference to the client associated with this service. + */ +BLEClient *BLERemoteService::getClient() { + return m_pClient; +} // getClient + +uint16_t BLERemoteService::getEndHandle() { + return m_endHandle; +} // getEndHandle + +uint16_t BLERemoteService::getStartHandle() { + return m_startHandle; +} // getStartHandle + +uint16_t BLERemoteService::getHandle() { + log_v(">> getHandle: service: %s", getUUID().toString().c_str()); + log_v("<< getHandle: %d 0x%.2x", getStartHandle(), getStartHandle()); + return getStartHandle(); +} // getHandle + +BLEUUID BLERemoteService::getUUID() { + return m_uuid; +} + +/** + * @brief Read the value of a characteristic associated with this service. + */ +String BLERemoteService::getValue(BLEUUID characteristicUuid) { + log_v(">> readValue: uuid: %s", characteristicUuid.toString().c_str()); + String ret = getCharacteristic(characteristicUuid)->readValue(); + log_v("<< readValue"); + return ret; +} // readValue + +/** + * @brief Delete the characteristics in the characteristics map. + * We maintain a map called m_characteristicsMap that contains pointers to BLERemoteCharacteristic + * object references. Since we allocated these in this class, we are also responsible for deleting + * them. This method does just that. + * @return N/A. + */ +void BLERemoteService::removeCharacteristics() { + m_characteristicMap.clear(); // Clear the map + for (auto &myPair : m_characteristicMapByHandle) { + delete myPair.second; + // delete the characteristics only once + } + m_characteristicMapByHandle.clear(); // Clear the map +} // removeCharacteristics + +/** + * @brief Set the value of a characteristic. + * @param [in] characteristicUuid The characteristic to set. + * @param [in] value The value to set. + * @throws BLEUuidNotFound + */ +void BLERemoteService::setValue(BLEUUID characteristicUuid, String value) { + log_v(">> setValue: uuid: %s", characteristicUuid.toString().c_str()); + getCharacteristic(characteristicUuid)->writeValue(value); + log_v("<< setValue"); +} // setValue + +/** + * @brief Create a string representation of this remote service. + * @return A string representation of this remote service. + */ +String BLERemoteService::toString() { + String res = "Service: uuid: " + m_uuid.toString(); + char val[6]; + res += ", start_handle: "; + snprintf(val, sizeof(val), "%d", m_startHandle); + res += val; + snprintf(val, sizeof(val), "%04x", m_startHandle); + res += " 0x"; + res += val; + res += ", end_handle: "; + snprintf(val, sizeof(val), "%d", m_endHandle); + res += val; + snprintf(val, sizeof(val), "%04x", m_endHandle); + res += " 0x"; + res += val; + for (auto &myPair : m_characteristicMap) { + res += "\n" + myPair.second->toString(); + // myPair.second is the value + } + return res; +} // toString + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +BLERemoteService::BLERemoteService(esp_gatt_id_t srvcId, BLEClient *pClient, uint16_t startHandle, uint16_t endHandle) { + log_v(">> BLERemoteService()"); + m_srvcId = srvcId; + m_pClient = pClient; + m_uuid = BLEUUID(m_srvcId); + m_haveCharacteristics = false; + m_startHandle = startHandle; + m_endHandle = endHandle; + + log_v("<< BLERemoteService()"); +} + +esp_gatt_id_t *BLERemoteService::getSrvcId() { + return &m_srvcId; +} // getSrvcId + +/** + * @brief Retrieve all the characteristics for this service. + * This function will not return until we have all the characteristics. + * @return N/A + */ +void BLERemoteService::retrieveCharacteristics() { + log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str()); + + removeCharacteristics(); // Forget any previous characteristics. + + uint16_t offset = 0; + esp_gattc_char_elem_t result; + while (true) { + uint16_t count = 1; // only room for 1 result allocated, so go one by one + esp_gatt_status_t status = + ::esp_ble_gattc_get_all_char(getClient()->getGattcIf(), getClient()->getConnId(), m_startHandle, m_endHandle, &result, &count, offset); + + if (status == ESP_GATT_INVALID_OFFSET) { // We have reached the end of the entries. + break; + } + + if (status != ESP_GATT_OK) { // If we got an error, end. + log_e("esp_ble_gattc_get_all_char: %s", BLEUtils::gattStatusToString(status).c_str()); + break; + } + + if (count == 0) { // If we failed to get any new records, end. + break; + } + + log_d("Found a characteristic: Handle: %d, UUID: %s", result.char_handle, BLEUUID(result.uuid).toString().c_str()); + + // We now have a new characteristic ... let us add that to our set of known characteristics + BLERemoteCharacteristic *pNewRemoteCharacteristic = new BLERemoteCharacteristic(result.char_handle, BLEUUID(result.uuid), result.properties, this); + + m_characteristicMap.insert( + std::pair(pNewRemoteCharacteristic->getUUID().toString().c_str(), pNewRemoteCharacteristic) + ); + m_characteristicMapByHandle.insert(std::pair(result.char_handle, pNewRemoteCharacteristic)); + offset++; // Increment our count of number of descriptors found. + } // Loop forever (until we break inside the loop). + + m_haveCharacteristics = true; // Remember that we have received the characteristics. + log_v("<< getCharacteristics()"); +} // getCharacteristics + +/** + * @brief Handle GATT Client events + */ +void BLERemoteService::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) { + switch (event) { + // + // ESP_GATTC_GET_CHAR_EVT + // + // get_char: + // - esp_gatt_status_t status + // - uin1t6_t conn_id + // - esp_gatt_srvc_id_t srvc_id + // - esp_gatt_id_t char_id + // - esp_gatt_char_prop_t char_prop + // + /* + case ESP_GATTC_GET_CHAR_EVT: { + // Is this event for this service? If yes, then the local srvc_id and the event srvc_id will be + // the same. + if (compareSrvcId(m_srvcId, evtParam->get_char.srvc_id) == false) { + break; + } + + // If the status is NOT OK then we have a problem and continue. + if (evtParam->get_char.status != ESP_GATT_OK) { + m_semaphoreGetCharEvt.give(); + break; + } + + // This is an indication that we now have the characteristic details for a characteristic owned + // by this service so remember it. + m_characteristicMap.insert(std::pair( + BLEUUID(evtParam->get_char.char_id.uuid).toString().c_str(), + new BLERemoteCharacteristic(evtParam->get_char.char_id, evtParam->get_char.char_prop, this) )); + + + // Now that we have received a characteristic, lets ask for the next one. + esp_err_t errRc = ::esp_ble_gattc_get_characteristic( + m_pClient->getGattcIf(), + m_pClient->getConnId(), + &m_srvcId, + &evtParam->get_char.char_id); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_get_characteristic: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + break; + } + + //m_semaphoreGetCharEvt.give(); + break; + } // ESP_GATTC_GET_CHAR_EVT +*/ + default: break; + } // switch + + // Send the event to each of the characteristics owned by this service. + for (auto &myPair : m_characteristicMapByHandle) { + myPair.second->gattClientEventHandler(event, gattc_if, evtParam); + } +} // gattClientEventHandler + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +BLERemoteService::BLERemoteService(BLEClient *pClient, const struct ble_gatt_svc *service) { + log_v(">> BLERemoteService()"); + m_pClient = pClient; + switch (service->uuid.u.type) { + case BLE_UUID_TYPE_16: m_uuid = BLEUUID(service->uuid.u16.value); break; + case BLE_UUID_TYPE_32: m_uuid = BLEUUID(service->uuid.u32.value); break; + case BLE_UUID_TYPE_128: m_uuid = BLEUUID(const_cast(&service->uuid.u128)); break; + default: break; + } + m_startHandle = service->start_handle; + m_endHandle = service->end_handle; + m_haveCharacteristics = false; + log_v("<< BLERemoteService(): %s", m_uuid.toString().c_str()); +} + +/** + * @brief Retrieve all the characteristics for this service. + * This function will not return until we have all the characteristics. + */ +void BLERemoteService::retrieveCharacteristics() { + log_v(">> retrieveCharacteristics() for service: %s", getUUID().toString().c_str()); + + int rc = 0; + BLETaskData taskData(const_cast(this)); + + rc = ble_gattc_disc_all_chrs(m_pClient->getConnId(), m_startHandle, m_endHandle, BLERemoteService::characteristicDiscCB, &taskData); + + if (rc != 0) { + log_e("ble_gattc_disc_all_chrs: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + return; + } + + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + rc = taskData.m_flags; + if (rc == 0 || rc == BLE_HS_EDONE) { + log_d("<< retrieveCharacteristics()"); + return; + } + + log_e("<< retrieveCharacteristics() rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); +} // retrieveCharacteristics + +/** + * @brief Callback for characteristic discovery. + * @return success == 0 or error code. + */ +int BLERemoteService::characteristicDiscCB(uint16_t conn_handle, const struct ble_gatt_error *error, const struct ble_gatt_chr *chr, void *arg) { + log_d("Characteristic Discovered >> status: %d handle: %d", error->status, (error->status == 0) ? chr->val_handle : -1); + + BLETaskData *pTaskData = (BLETaskData *)arg; + BLERemoteService *service = (BLERemoteService *)pTaskData->m_pInstance; + + if (error->status == BLE_HS_ENOTCONN) { + log_e("<< Characteristic Discovery; Not connected"); + BLEUtils::taskRelease(*pTaskData, error->status); + return error->status; + } + + // Make sure the discovery is for this device + if (service->getClient()->getConnId() != conn_handle) { + return 0; + } + + if (error->status == 0) { + // Found a service - add it to the vector + BLERemoteCharacteristic *pRemoteCharacteristic = new BLERemoteCharacteristic(service, chr); + service->m_characteristicMap.insert( + std::pair(pRemoteCharacteristic->getUUID().toString().c_str(), pRemoteCharacteristic) + ); + service->m_characteristicMapByHandle.insert(std::pair(chr->val_handle, pRemoteCharacteristic)); + return 0; + } + + BLEUtils::taskRelease(*pTaskData, error->status); + service->m_haveCharacteristics = true; + log_d("<< Characteristic Discovered"); + return error->status; +} + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLERemoteService.h b/libraries/BLE/src/BLERemoteService.h new file mode 100644 index 0000000..977ccc8 --- /dev/null +++ b/libraries/BLE/src/BLERemoteService.h @@ -0,0 +1,133 @@ +/* + * BLERemoteService.h + * + * Created on: Jul 8, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_ +#define COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include + +#include "BLEClient.h" +#include "BLERemoteCharacteristic.h" +#include "BLEUUID.h" +#include "RTOS.h" +#include "BLEUtils.h" + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEClient; +class BLERemoteCharacteristic; + +/** + * @brief A model of a remote %BLE service. + */ +class BLERemoteService { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLERemoteService(); + BLERemoteCharacteristic *getCharacteristic(const char *uuid); // Get the specified characteristic reference. + BLERemoteCharacteristic *getCharacteristic(BLEUUID uuid); // Get the specified characteristic reference. + BLERemoteCharacteristic *getCharacteristic(uint16_t uuid); // Get the specified characteristic reference. + std::map *getCharacteristics(); + std::map *getCharacteristicsByHandle(); // Get the characteristics map. + void getCharacteristics(std::map **pCharacteristicMap); + void retrieveCharacteristics(); + + BLEClient *getClient(void); // Get a reference to the client associated with this service. + uint16_t getHandle(); // Get the handle of this service. + BLEUUID getUUID(void); // Get the UUID of this service. + String getValue(BLEUUID characteristicUuid); // Get the value of a characteristic. + void setValue(BLEUUID characteristicUuid, String value); // Set the value of a characteristic. + String toString(void); + +private: + friend class BLEClient; + friend class BLERemoteCharacteristic; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + // We maintain a map of characteristics owned by this service keyed by a string representation of the UUID. + std::map m_characteristicMap; + + // We maintain a map of characteristics owned by this service keyed by a handle. + std::map m_characteristicMapByHandle; + + bool m_haveCharacteristics; // Have we previously obtained the characteristics. + BLEClient *m_pClient; + FreeRTOS::Semaphore m_semaphoreGetCharEvt = FreeRTOS::Semaphore("GetCharEvt"); + BLEUUID m_uuid; // The UUID of this service. + uint16_t m_startHandle; // The starting handle of this service. + uint16_t m_endHandle; // The ending handle of this service. + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_gatt_id_t m_srvcId; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + uint16_t getStartHandle(); // Get the start handle for this service. + uint16_t getEndHandle(); // Get the end handle for this service. + void removeCharacteristics(); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + // Private constructor ... never meant to be created by a user application. + BLERemoteService(esp_gatt_id_t srvcId, BLEClient *pClient, uint16_t startHandle, uint16_t endHandle); + esp_gatt_id_t *getSrvcId(); + void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam); +#endif + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + BLERemoteService(BLEClient *pClient, const struct ble_gatt_svc *service); + static int characteristicDiscCB(uint16_t conn_handle, const struct ble_gatt_error *error, const struct ble_gatt_chr *chr, void *arg); +#endif +}; // BLERemoteService + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_ */ diff --git a/libraries/BLE/src/BLEScan.cpp b/libraries/BLE/src/BLEScan.cpp new file mode 100644 index 0000000..081de0c --- /dev/null +++ b/libraries/BLE/src/BLEScan.cpp @@ -0,0 +1,870 @@ +/* + * BLEScan.cpp + * + * Created on: Jul 1, 2017 + * Author: kolban + * + * Update: April, 2021 + * add BLE5 support + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include + +#include + +#include "BLEAdvertisedDevice.h" +#include "BLEScan.h" +#include "BLEUtils.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Constructor + */ +BLEScan::BLEScan() { + memset(&m_scan_params, 0, sizeof(m_scan_params)); // Initialize all params +#if defined(CONFIG_BLUEDROID_ENABLED) + m_scan_params.scan_type = BLE_SCAN_TYPE_PASSIVE; // Default is a passive scan. + m_scan_params.own_addr_type = BLE_ADDR_TYPE_PUBLIC; + m_scan_params.scan_filter_policy = BLE_SCAN_FILTER_ALLOW_ALL; + m_scan_params.scan_duplicate = BLE_SCAN_DUPLICATE_DISABLE; + m_pAdvertisedDeviceCallbacks = nullptr; + m_stopped = true; + m_wantDuplicates = false; + m_shouldParse = true; + setInterval(100); + setWindow(100); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_scan_params.filter_policy = BLE_HCI_SCAN_FILT_NO_WL; + m_scan_params.passive = 1; // If set, don’t send scan requests to advertisers (i.e., don’t request additional advertising data). + m_scan_params.limited = 0; // If set, only discover devices in limited discoverable mode. + m_scan_params.filter_duplicates = 1; // If set, the controller ignores all but the first advertisement from each device. + m_pAdvertisedDeviceCallbacks = nullptr; + m_ignoreResults = false; + m_pTaskData = nullptr; + m_duration = BLE_HS_FOREVER; // make sure this is non-zero in the event of a host reset + m_maxResults = 0xFF; + m_stopped = true; + m_wantDuplicates = false; + m_shouldParse = true; + // This is defined as the time interval from when the Controller started its last LE scan until it begins the subsequent LE scan. (units=0.625 msec) + setInterval(100); + // The duration of the LE scan. LE_Scan_Window shall be less than or equal to LE_Scan_Interval (units=0.625 msec) + setWindow(100); +#endif +} // BLEScan + +/** + * @brief Scan destructor, release any allocated resources. + */ +BLEScan::~BLEScan() { + clearResults(); +} + +/** + * @brief Should we perform an active or passive scan? + * The default is a passive scan. An active scan means that we will wish a scan response. + * @param [in] active If true, we perform an active scan otherwise a passive scan. + * @return N/A. + */ +void BLEScan::setActiveScan(bool active) { +#if defined(CONFIG_BLUEDROID_ENABLED) + if (active) { + m_scan_params.scan_type = BLE_SCAN_TYPE_ACTIVE; + } else { + m_scan_params.scan_type = BLE_SCAN_TYPE_PASSIVE; + } +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_scan_params.passive = !active; +#endif +} // setActiveScan + +/** + * @brief Set the call backs to be invoked. + * @param [in] pAdvertisedDeviceCallbacks Call backs to be invoked. + * @param [in] wantDuplicates True if we wish to be called back with duplicates. Default is false. + * @param [in] shouldParse True if we wish to parse advertised package or raw payload. Default is true. + */ +void BLEScan::setAdvertisedDeviceCallbacks(BLEAdvertisedDeviceCallbacks *pAdvertisedDeviceCallbacks, bool wantDuplicates, bool shouldParse) { + m_wantDuplicates = wantDuplicates; +#if defined(CONFIG_NIMBLE_ENABLED) + setDuplicateFilter(!wantDuplicates); +#endif + m_pAdvertisedDeviceCallbacks = pAdvertisedDeviceCallbacks; + m_shouldParse = shouldParse; +} // setAdvertisedDeviceCallbacks + +/** + * @brief Set the interval to scan. + * @param [in] The interval in msecs. + */ +void BLEScan::setInterval(uint16_t intervalMSecs) { +#if defined(CONFIG_BLUEDROID_ENABLED) + m_scan_params.scan_interval = intervalMSecs / 0.625; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_scan_params.itvl = intervalMSecs / 0.625; +#endif +} // setInterval + +/** + * @brief Set the window to actively scan. + * @param [in] windowMSecs How long to actively scan. + */ +void BLEScan::setWindow(uint16_t windowMSecs) { +#if defined(CONFIG_BLUEDROID_ENABLED) + m_scan_params.scan_window = windowMSecs / 0.625; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + m_scan_params.window = windowMSecs / 0.625; +#endif +} // setWindow + +// delete peer device from cache after disconnecting, it is required in case we are connecting to devices with not public address +void BLEScan::erase(BLEAddress address) { + log_i("erase device: %s", address.toString().c_str()); + BLEAdvertisedDevice *advertisedDevice = m_scanResults.m_vectorAdvertisedDevices.find(address.toString().c_str())->second; + m_scanResults.m_vectorAdvertisedDevices.erase(address.toString().c_str()); + delete advertisedDevice; +} + +/** + * @brief Dump the scan results to the log. + */ +void BLEScanResults::dump() { + log_v(">> Dump scan results:"); + for (int i = 0; i < getCount(); i++) { + log_d("- %s", getDevice(i).toString().c_str()); + } +} // dump + +/** + * @brief Return the count of devices found in the last scan. + * @return The number of devices found in the last scan. + */ +int BLEScanResults::getCount() { + return m_vectorAdvertisedDevices.size(); +} // getCount + +/** + * @brief Return the specified device at the given index. + * The index should be between 0 and getCount()-1. + * @param [in] i The index of the device. + * @return The device at the specified index. + */ +BLEAdvertisedDevice BLEScanResults::getDevice(uint32_t i) { + uint32_t x = 0; + BLEAdvertisedDevice dev = *m_vectorAdvertisedDevices.begin()->second; + for (auto it = m_vectorAdvertisedDevices.begin(); it != m_vectorAdvertisedDevices.end(); it++) { + dev = *it->second; + if (x == i) { + break; + } + x++; + } + return dev; +} + +BLEScanResults *BLEScan::getResults() { + return &m_scanResults; +} + +void BLEScan::clearResults() { + for (auto _dev : m_scanResults.m_vectorAdvertisedDevices) { + delete _dev.second; + } + m_scanResults.m_vectorAdvertisedDevices.clear(); +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +#if defined(SOC_BLE_50_SUPPORTED) + +void BLEScan::setExtendedScanCallback(BLEExtAdvertisingCallbacks *cb) { + m_pExtendedScanCb = cb; +} + +/** +* @brief This function is used to enable scanning. +* +* @param[in] duration : Scan duration +* @param[in] period : Time interval from when the Controller started its last Scan Duration until it begins the subsequent Scan Duration. +* +* @return - ESP_OK : success +* - other : failed +* +*/ +esp_err_t BLEScan::startExtScan(uint32_t duration, uint16_t period) { + esp_err_t rc = esp_ble_gap_start_ext_scan(duration, period); + if (rc) { + log_e("extended scan start failed: %d", rc); + } + return rc; +} + +esp_err_t BLEScan::stopExtScan() { + esp_err_t rc = esp_ble_gap_stop_ext_scan(); + if (rc) { + log_e("extended scan stop failed: %d", rc); + } + return rc; +} + +void BLEScan::setPeriodicScanCallback(BLEPeriodicScanCallbacks *cb) { + m_pPeriodicScanCb = cb; +} + +/** +* @brief This function is used to set the extended scan parameters to be used on the advertising channels. +* +* +* @return - ESP_OK : success +* - other : failed +* +*/ +esp_err_t BLEScan::setExtScanParams() { + esp_ble_ext_scan_params_t ext_scan_params = { + .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .filter_policy = BLE_SCAN_FILTER_ALLOW_ALL, + .scan_duplicate = BLE_SCAN_DUPLICATE_DISABLE, + .cfg_mask = ESP_BLE_GAP_EXT_SCAN_CFG_UNCODE_MASK | ESP_BLE_GAP_EXT_SCAN_CFG_CODE_MASK, + .uncoded_cfg = {BLE_SCAN_TYPE_ACTIVE, 40, 40}, + .coded_cfg = {BLE_SCAN_TYPE_ACTIVE, 40, 40}, + }; + + esp_err_t rc = esp_ble_gap_set_ext_scan_params(&ext_scan_params); + if (rc) { + log_e("set extend scan params error, error code = %x", rc); + } + return rc; +} + +/** +* @brief This function is used to set the extended scan parameters to be used on the advertising channels. +* +* @param[in] params : scan parameters +* +* @return - ESP_OK : success +* - other : failed +* +*/ +esp_err_t BLEScan::setExtScanParams(esp_ble_ext_scan_params_t *ext_scan_params) { + esp_err_t rc = esp_ble_gap_set_ext_scan_params(ext_scan_params); + if (rc) { + log_e("set extend scan params error, error code = %x", rc); + } + return rc; +} + +#endif // SOC_BLE_50_SUPPORTED + +/** + * @brief Handle GAP events related to scans. + * @param [in] event The event type for this event. + * @param [in] param Parameter data for this event. + */ +void BLEScan::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + switch (event) { + + // --------------------------- + // scan_rst: + // esp_gap_search_evt_t search_evt + // esp_bd_addr_t bda + // esp_bt_dev_type_t dev_type + // esp_ble_addr_type_t ble_addr_type + // esp_ble_evt_type_t ble_evt_type + // int rssi + // uint8_t ble_adv[ESP_BLE_ADV_DATA_LEN_MAX] + // int flag + // int num_resps + // uint8_t adv_data_len + // uint8_t scan_rsp_len + case ESP_GAP_BLE_SCAN_RESULT_EVT: + { + + switch (param->scan_rst.search_evt) { + // + // ESP_GAP_SEARCH_INQ_CMPL_EVT + // + // Event that indicates that the duration allowed for the search has completed or that we have been + // asked to stop. + case ESP_GAP_SEARCH_INQ_CMPL_EVT: + { + log_w("ESP_GAP_SEARCH_INQ_CMPL_EVT"); + m_stopped = true; + m_semaphoreScanEnd.give(); + if (m_scanCompleteCB != nullptr) { + m_scanCompleteCB(m_scanResults); + } + break; + } // ESP_GAP_SEARCH_INQ_CMPL_EVT + + // + // ESP_GAP_SEARCH_INQ_RES_EVT + // + // Result that has arrived back from a Scan inquiry. + case ESP_GAP_SEARCH_INQ_RES_EVT: + { + if (m_stopped) { // If we are not scanning, nothing to do with the extra results. + break; + } + + // Examine our list of previously scanned addresses and, if we found this one already, + // ignore it. + BLEAddress advertisedAddress(param->scan_rst.bda, param->scan_rst.ble_addr_type); + bool found = false; + bool shouldDelete = true; + + if (!m_wantDuplicates) { + if (m_scanResults.m_vectorAdvertisedDevices.count(advertisedAddress.toString().c_str()) != 0) { + found = true; + } + + if (found) { // If we found a previous entry AND we don't want duplicates, then we are done. + log_d("Ignoring %s, already seen it.", advertisedAddress.toString().c_str()); + vTaskDelay(1); // <--- allow to switch task in case we scan infinity and dont have new devices to report, or we are blocked here + break; + } + } + + // We now construct a model of the advertised device that we have just found for the first + // time. + // ESP_LOG_BUFFER_HEXDUMP((uint8_t*)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len, ESP_LOG_DEBUG); + // log_w("bytes length: %d + %d, addr type: %d", param->scan_rst.adv_data_len, param->scan_rst.scan_rsp_len, param->scan_rst.ble_addr_type); + BLEAdvertisedDevice *advertisedDevice = new BLEAdvertisedDevice(); + advertisedDevice->setAddress(advertisedAddress); + advertisedDevice->setRSSI(param->scan_rst.rssi); + advertisedDevice->setAdFlag(param->scan_rst.flag); + advertisedDevice->setAdvType(param->scan_rst.ble_evt_type); + if (m_shouldParse) { + advertisedDevice->parseAdvertisement((uint8_t *)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len); + } else { + advertisedDevice->setPayload((uint8_t *)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len); + } + advertisedDevice->setScan(this); + advertisedDevice->setAddressType(param->scan_rst.ble_addr_type); + + if (m_pAdvertisedDeviceCallbacks) { // if has callback, no need to record to vector + m_pAdvertisedDeviceCallbacks->onResult(*advertisedDevice); + } + if (!m_wantDuplicates && !found) { // if no callback and not want duplicate, and not already in vector, record it + m_scanResults.m_vectorAdvertisedDevices.insert(std::pair(advertisedAddress.toString().c_str(), advertisedDevice) + ); + shouldDelete = false; + } + if (shouldDelete) { + delete advertisedDevice; + } + + break; + } // ESP_GAP_SEARCH_INQ_RES_EVT + + default: + { + break; + } + } // switch - search_evt + + break; + } // ESP_GAP_BLE_SCAN_RESULT_EVT +#ifdef SOC_BLE_50_SUPPORTED + case ESP_GAP_BLE_EXT_ADV_REPORT_EVT: + { + if (param->ext_adv_report.params.event_type & ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY) { + log_v("legacy adv, adv type 0x%x data len %d", param->ext_adv_report.params.event_type, param->ext_adv_report.params.adv_data_len); + } else { + log_v( + "extend adv, adv type 0x%x data len %d, data status: %d", param->ext_adv_report.params.event_type, param->ext_adv_report.params.adv_data_len, + param->ext_adv_report.params.data_status + ); + } + + if (m_pExtendedScanCb != nullptr) { + m_pExtendedScanCb->onResult(param->ext_adv_report.params); + } + + break; + } + + case ESP_GAP_BLE_SET_EXT_SCAN_PARAMS_COMPLETE_EVT: + { + if (param->set_ext_scan_params.status != ESP_BT_STATUS_SUCCESS) { + log_e("extend scan parameters set failed, error status = %x", param->set_ext_scan_params.status); + break; + } + log_v("extend scan params set successfully"); + break; + } + + case ESP_GAP_BLE_EXT_SCAN_START_COMPLETE_EVT: + if (param->ext_scan_start.status != ESP_BT_STATUS_SUCCESS) { + log_e("scan start failed, error status = %x", param->scan_start_cmpl.status); + break; + } + log_v("Scan start success"); + break; + + case ESP_GAP_BLE_EXT_SCAN_STOP_COMPLETE_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onStop(param->ext_scan_stop.status); + } + + if (param->ext_scan_stop.status != ESP_BT_STATUS_SUCCESS) { + log_e("extend Scan stop failed, error status = %x", param->ext_scan_stop.status); + break; + } + log_v("Stop extend scan successfully"); + break; + + case ESP_GAP_BLE_PERIODIC_ADV_CREATE_SYNC_COMPLETE_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onCreateSync(param->period_adv_create_sync.status); + } + + log_v("ESP_GAP_BLE_PERIODIC_ADV_CREATE_SYNC_COMPLETE_EVT, status %d", param->period_adv_create_sync.status); + break; + case ESP_GAP_BLE_PERIODIC_ADV_SYNC_CANCEL_COMPLETE_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onCancelSync(param->period_adv_sync_cancel.status); + } + log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_CANCEL_COMPLETE_EVT, status %d", param->period_adv_sync_cancel.status); + break; + case ESP_GAP_BLE_PERIODIC_ADV_SYNC_TERMINATE_COMPLETE_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onTerminateSync(param->period_adv_sync_term.status); + } + log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_TERMINATE_COMPLETE_EVT, status %d", param->period_adv_sync_term.status); + break; + case ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onLostSync(param->periodic_adv_sync_lost.sync_handle); + } + log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT, sync handle %d", param->periodic_adv_sync_lost.sync_handle); + break; + case ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onSync(*(esp_ble_periodic_adv_sync_estab_param_t *)¶m->periodic_adv_sync_estab); + } + log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT, status %d", param->periodic_adv_sync_estab.status); + break; + + case ESP_GAP_BLE_PERIODIC_ADV_REPORT_EVT: + if (m_pPeriodicScanCb != nullptr) { + m_pPeriodicScanCb->onReport(param->period_adv_report.params); + } + break; + +#endif // SOC_BLE_50_SUPPORTED + + default: + { + break; + } // default + } // End switch +} // gapEventHandler + +/** + * @brief Start scanning. + * @param [in] duration The duration in seconds for which to scan. + * @param [in] scanCompleteCB A function to be called when scanning has completed. + * @param [in] are we continue scan (true) or we want to clear stored devices (false) + * @return True if scan started or false if there was an error. + */ +bool BLEScan::start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue) { + log_v(">> start(duration=%d)", duration); + + m_semaphoreScanEnd.take(String("start")); + m_scanCompleteCB = scanCompleteCB; // Save the callback to be invoked when the scan completes. + + // if we are connecting to devices that are advertising even after being connected, multiconnecting peripherals + // then we should not clear map or we will connect the same device few times + if (!is_continue) { + for (auto _dev : m_scanResults.m_vectorAdvertisedDevices) { + delete _dev.second; + } + m_scanResults.m_vectorAdvertisedDevices.clear(); + } + + esp_err_t errRc = ::esp_ble_gap_set_scan_params(&m_scan_params); + + if (errRc != ESP_OK) { + log_e("esp_ble_gap_set_scan_params: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreScanEnd.give(); + return false; + } + + errRc = ::esp_ble_gap_start_scanning(duration); + + if (errRc != ESP_OK) { + log_e("esp_ble_gap_start_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc)); + m_semaphoreScanEnd.give(); + return false; + } + + m_stopped = false; + + log_v("<< start()"); + return true; +} // start + +/** + * @brief Start scanning and block until scanning has been completed. + * @param [in] duration The duration in seconds for which to scan. + * @return The BLEScanResults. + */ +BLEScanResults *BLEScan::start(uint32_t duration, bool is_continue) { + if (start(duration, nullptr, is_continue)) { + m_semaphoreScanEnd.wait("start"); // Wait for the semaphore to release. + } + return &m_scanResults; +} // start + +/** + * @brief Stop an in progress scan. + * @return N/A. + */ +bool BLEScan::stop() { + log_v(">> stop()"); + + esp_err_t errRc = ::esp_ble_gap_stop_scanning(); + + m_stopped = true; + m_semaphoreScanEnd.give(); + + if (errRc != ESP_OK) { + log_e("esp_ble_gap_stop_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + + log_v("<< stop()"); + return true; +} // stop + +/** + * @brief Get the status of the scanner. + * @return true if scanning is active. + */ +bool BLEScan::isScanning() { + return !m_stopped; +} // isScanning + +#endif // CONFIG_BLUEDROID_ENABLED + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Set whether or not the BLE controller should only report results + * from devices it has not already seen. + * @param [in] enabled If true, scanned devices will only be reported once. + * @details The controller has a limited buffer and will start reporting + * duplicate devices once the limit is reached. + */ +void BLEScan::setDuplicateFilter(bool enabled) { + m_scan_params.filter_duplicates = enabled; +} // setDuplicateFilter + +/** + * @brief Get the status of the scanner. + * @return true if scanning or scan starting. + */ +bool BLEScan::isScanning() { + return ble_gap_disc_active(); +} + +/** + * @brief Handle GAP events related to scans. + * @param [in] event The event type for this event. + * @param [in] param Parameter data for this event. + */ +int BLEScan::handleGAPEvent(ble_gap_event *event, void *arg) { + BLEScan *pScan = (BLEScan *)arg; + + switch (event->type) { + case BLE_GAP_EVENT_DISC: + { + if (pScan->m_ignoreResults) { + log_i("Scan op in progress - ignoring results"); + return 0; + } + + const auto &disc = event->disc; + const auto event_type = disc.event_type; + const bool isLegacyAdv = true; + BLEAddress advertisedAddress(disc.addr); + + BLEClient *client = BLEDevice::getClientByAddress(advertisedAddress); + if (client != nullptr && client->isConnected()) { + log_i("Client %s connected - ignoring event", advertisedAddress.toString().c_str()); + return 0; + } + + BLEAdvertisedDevice *advertisedDevice = nullptr; + + // If we've seen this device before get a pointer to it from the vector + for (auto &it : pScan->m_scanResults.m_vectorAdvertisedDevices) { + if (it.second->getAddress() == advertisedAddress) { + advertisedDevice = it.second; + break; + } + } + + // If we haven't seen this device before; create a new instance and insert it in the vector. + // Otherwise just update the relevant parameters of the already known device. + if (advertisedDevice == nullptr) { + // Check if we have reach the scan results limit, ignore this one if so. + // We still need to store each device when maxResults is 0 to be able to append the scan results + if (pScan->m_maxResults > 0 && pScan->m_maxResults < 0xFF && (pScan->m_scanResults.m_vectorAdvertisedDevices.size() >= pScan->m_maxResults)) { + return 0; + } + + if (isLegacyAdv && event_type == BLE_HCI_ADV_RPT_EVTYPE_SCAN_RSP) { + log_i("Scan response without advertisement: %s", advertisedAddress.toString().c_str()); + } + + advertisedDevice = new BLEAdvertisedDevice(); + advertisedDevice->setAddress(advertisedAddress); + advertisedDevice->setAddressType(event->disc.addr.type); + advertisedDevice->setAdvType(event_type); + pScan->m_scanResults.m_vectorAdvertisedDevices.insert( + std::pair(advertisedAddress.toString().c_str(), advertisedDevice) + ); + log_i("New advertiser: %s", advertisedAddress.toString().c_str()); + } else if (advertisedDevice != nullptr) { + log_i("Updated advertiser: %s", advertisedAddress.toString().c_str()); + } else { + // Scan response from unknown device + return 0; + } + + advertisedDevice->setRSSI(event->disc.rssi); + + if (pScan->m_shouldParse) { + advertisedDevice->parseAdvertisement((uint8_t *)event->disc.data, event->disc.length_data); + } else { + advertisedDevice->setPayload((uint8_t *)event->disc.data, event->disc.length_data, event_type == BLE_HCI_ADV_RPT_EVTYPE_SCAN_RSP); + } + + advertisedDevice->setScan(pScan); + + if (pScan->m_pAdvertisedDeviceCallbacks) { + // If not active scanning or scan response is not available + // report the result to the callback now. + if (pScan->m_scan_params.passive || !isLegacyAdv || !advertisedDevice->isScannable()) { + advertisedDevice->m_callbackSent = true; + pScan->m_pAdvertisedDeviceCallbacks->onResult(*advertisedDevice); + + // Otherwise, wait for the scan response so we can report the complete data. + } else if (isLegacyAdv && event_type == BLE_HCI_ADV_RPT_EVTYPE_SCAN_RSP) { + advertisedDevice->m_callbackSent = true; + pScan->m_pAdvertisedDeviceCallbacks->onResult(*advertisedDevice); + } + } + + // If not storing results and we have invoked the callback, delete the device. + if (pScan->m_maxResults == 0 && advertisedDevice->m_callbackSent) { + pScan->erase(advertisedAddress); + } + + return 0; + } + + case BLE_GAP_EVENT_DISC_COMPLETE: + { + log_d("discovery complete; reason=%d", event->disc_complete.reason); + + // If a device advertised with scan response available and it was not received + // the callback would not have been invoked, so do it here. + if (pScan->m_pAdvertisedDeviceCallbacks) { + for (auto &it : pScan->m_scanResults.m_vectorAdvertisedDevices) { + if (!it.second->m_callbackSent) { + pScan->m_pAdvertisedDeviceCallbacks->onResult(*(it.second)); + } + } + } + + if (pScan->m_maxResults == 0) { + pScan->clearResults(); + } + + if (pScan->m_scanCompleteCB != nullptr) { + pScan->m_scanCompleteCB(pScan->m_scanResults); + } + + if (pScan->m_pTaskData != nullptr) { + BLEUtils::taskRelease(*pScan->m_pTaskData, event->disc_complete.reason); + } + + return 0; + } + + default: return 0; + } +} // gapEventHandler + +/** + * @brief Start scanning. + * @param [in] duration The duration in seconds for which to scan. + * @param [in] scanCompleteCB A function to be called when scanning has completed. + * @param [in] is_continue Set to true to save previous scan results, false to clear them. + * @return True if scan started or false if there was an error. + */ +bool BLEScan::start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue) { + log_d(">> start(duration=%d)", duration); + + if (!is_continue) { + clearResults(); + } + + // Save the callback to be invoked when the scan completes. + m_scanCompleteCB = scanCompleteCB; + // Save the duration in the case that the host is reset so we can reuse it. + m_duration = duration; + + // If 0 duration specified then we assume a continuous scan is desired. + if (duration == 0) { + duration = BLE_HS_FOREVER; + } else { + // convert duration to milliseconds + duration = duration * 1000; + } + + // Set the flag to ignore the results while we are deleting the vector + if (!is_continue) { + m_ignoreResults = true; + } + + int rc = ble_gap_disc(BLEDevice::m_ownAddrType, duration, &m_scan_params, BLEScan::handleGAPEvent, this); + + switch (rc) { + case 0: + case BLE_HS_EALREADY: break; + + case BLE_HS_EBUSY: log_e("Unable to scan - connection in progress."); break; + + case BLE_HS_ETIMEOUT_HCI: + case BLE_HS_EOS: + case BLE_HS_ECONTROLLER: + case BLE_HS_ENOTSYNCED: log_e("Unable to scan - Host Reset"); break; + + default: log_e("Error initiating GAP discovery procedure; rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); break; + } + + m_ignoreResults = false; + log_d("<< start()"); + + if (rc != 0 && rc != BLE_HS_EALREADY) { + return false; + } + return true; +} // start + +/** + * @brief Start scanning and block until scanning has been completed. + * @param [in] duration The duration in seconds for which to scan. + * @param [in] is_continue Set to true to save previous scan results, false to clear them. + * @return The BLEScanResults. + */ +BLEScanResults *BLEScan::start(uint32_t duration, bool is_continue) { + if (duration == 0) { + log_w("Blocking scan called with duration = forever"); + } + + if (m_pTaskData != nullptr) { + log_e("Scan already in progress"); + return &m_scanResults; + } + + BLETaskData taskData(this); + m_pTaskData = &taskData; + + if (start(duration, nullptr, is_continue)) { + BLEUtils::taskWait(taskData, BLE_NPL_TIME_FOREVER); + } + + m_pTaskData = nullptr; + return &m_scanResults; +} // start + +/** + * @brief Stop an in progress scan. + * @return True if successful. + */ +bool BLEScan::stop() { + log_d(">> stop()"); + + int rc = ble_gap_disc_cancel(); + if (rc != 0 && rc != BLE_HS_EALREADY) { + log_e("Failed to cancel scan; rc=%d", rc); + return false; + } + + if (m_maxResults == 0) { + clearResults(); + } + + if (rc != BLE_HS_EALREADY && m_scanCompleteCB != nullptr) { + m_scanCompleteCB(m_scanResults); + } + + if (m_pTaskData != nullptr) { + BLEUtils::taskRelease(*m_pTaskData); + } + + log_d("<< stop()"); + return true; +} // stop + +/** + * @brief Called when host reset, we set a flag to stop scanning until synced. + */ +void BLEScan::onHostReset() { + m_ignoreResults = true; +} + +/** + * @brief If the host reset and re-synced this is called. + * If the application was scanning indefinitely with a callback, restart it. + */ +void BLEScan::onHostSync() { + m_ignoreResults = false; + + if (m_duration == 0 && m_pAdvertisedDeviceCallbacks != nullptr) { + start(m_duration, m_scanCompleteCB); + } +} + +#endif // CONFIG_NIMBLE_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEScan.h b/libraries/BLE/src/BLEScan.h new file mode 100644 index 0000000..569e109 --- /dev/null +++ b/libraries/BLE/src/BLEScan.h @@ -0,0 +1,238 @@ +/* + * BLEScan.h + * + * Created on: Jul 1, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLESCAN_H_ +#define COMPONENTS_CPP_UTILS_BLESCAN_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include +#include "BLEAdvertisedDevice.h" +#include "BLEClient.h" +#include "BLEUtils.h" +#include "RTOS.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEAdvertisedDevice; +class BLEAdvertisedDeviceCallbacks; +class BLEExtAdvertisingCallbacks; +class BLEClient; +class BLEScan; +class BLEPeriodicScanCallbacks; +struct BLETaskData; + +/*************************************************************************** + * Bluedroid type definitions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +struct esp_ble_periodic_adv_sync_estab_param_t { + uint8_t status; /*!< periodic advertising sync status */ + uint16_t sync_handle; /*!< periodic advertising sync handle */ + uint8_t sid; /*!< periodic advertising sid */ + esp_ble_addr_type_t adv_addr_type; /*!< periodic advertising address type */ + esp_bd_addr_t adv_addr; /*!< periodic advertising address */ + esp_ble_gap_phy_t adv_phy; /*!< periodic advertising phy type */ + uint16_t period_adv_interval; /*!< periodic advertising interval */ + uint8_t adv_clk_accuracy; /*!< periodic advertising clock accuracy */ +}; +#endif + +/** + * @brief The result of having performed a scan. + * When a scan completes, we have a set of found devices. Each device is described + * by a BLEAdvertisedDevice object. The number of items in the set is given by + * getCount(). We can retrieve a device by calling getDevice() passing in the + * index (starting at 0) of the desired device. + */ +class BLEScanResults { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + void dump(); + int getCount(); + BLEAdvertisedDevice getDevice(uint32_t i); + +private: + friend BLEScan; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + std::map m_vectorAdvertisedDevices; +}; + +/** + * @brief Perform and manage %BLE scans. + * + * Scanning is associated with a %BLE client that is attempting to locate BLE servers. + */ +class BLEScan { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + ~BLEScan(); + void setActiveScan(bool active); + void setAdvertisedDeviceCallbacks(BLEAdvertisedDeviceCallbacks *pAdvertisedDeviceCallbacks, bool wantDuplicates = false, bool shouldParse = true); + void setInterval(uint16_t intervalMSecs); + void setWindow(uint16_t windowMSecs); + bool start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue = false); + BLEScanResults *start(uint32_t duration, bool is_continue = false); + bool stop(); + void erase(BLEAddress address); + BLEScanResults *getResults(); + void clearResults(); + bool isScanning(); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(SOC_BLE_50_SUPPORTED) && defined(CONFIG_BLUEDROID_ENABLED) + void setExtendedScanCallback(BLEExtAdvertisingCallbacks *cb); + void setPeriodicScanCallback(BLEPeriodicScanCallbacks *cb); + esp_err_t stopExtScan(); + esp_err_t setExtScanParams(); + esp_err_t startExtScan(uint32_t duration, uint16_t period); + esp_err_t setExtScanParams(esp_ble_ext_scan_params_t *ext_scan_params); +#endif // SOC_BLE_50_SUPPORTED + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void setDuplicateFilter(bool enabled); + void clearDuplicateCache(); +#endif + +private: + friend class BLEDevice; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLEAdvertisedDeviceCallbacks *m_pAdvertisedDeviceCallbacks = nullptr; + bool m_stopped = true; + bool m_shouldParse = true; + FreeRTOS::Semaphore m_semaphoreScanEnd = FreeRTOS::Semaphore("ScanEnd"); + BLEScanResults m_scanResults; + bool m_wantDuplicates; + void (*m_scanCompleteCB)(BLEScanResults scanResults); + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_scan_params_t m_scan_params; +#if defined(SOC_BLE_50_SUPPORTED) + BLEExtAdvertisingCallbacks *m_pExtendedScanCb = nullptr; + BLEPeriodicScanCallbacks *m_pPeriodicScanCb = nullptr; +#endif // SOC_BLE_50_SUPPORTED +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + uint32_t m_duration; + ble_gap_disc_params m_scan_params; + bool m_ignoreResults; + BLETaskData *m_pTaskData; + uint8_t m_maxResults; +#endif + + /*************************************************************************** + * Common private definitions * + ***************************************************************************/ + + BLEScan(); // One doesn't create a new instance instead one asks the BLEDevice for the singleton. + + /*************************************************************************** + * Bluedroid private definitions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE private definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void onHostReset(); + void onHostSync(); + static int handleGAPEvent(ble_gap_event *event, void *arg); +#endif +}; // BLEScan + +class BLEPeriodicScanCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEPeriodicScanCallbacks() {} + virtual void onLostSync(uint16_t sync_handle) {} + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + virtual void onCreateSync(esp_bt_status_t status) {} + virtual void onCancelSync(esp_bt_status_t status) {} + virtual void onTerminateSync(esp_bt_status_t status) {} + virtual void onSync(esp_ble_periodic_adv_sync_estab_param_t) {} + virtual void onReport(esp_ble_gap_periodic_adv_report_t params) {} + virtual void onStop(esp_bt_status_t status) {} +#endif +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLESCAN_H_ */ diff --git a/libraries/BLE/src/BLESecurity.cpp b/libraries/BLE/src/BLESecurity.cpp new file mode 100644 index 0000000..76757f5 --- /dev/null +++ b/libraries/BLE/src/BLESecurity.cpp @@ -0,0 +1,435 @@ +/* + * BLESecurity.cpp + * + * Created on: Dec 17, 2017 + * Author: chegewara + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on chegewara's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "Arduino.h" +#include "BLESecurity.h" +#include "BLEUtils.h" +#include "BLEDevice.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#endif + +/*************************************************************************** + * Common properties * + ***************************************************************************/ + +// If true, the security will be enforced on connection even if no security is needed +// TODO: Make this configurable without breaking Bluedroid/NimBLE compatibility +bool BLESecurity::m_forceSecurity = true; + +bool BLESecurity::m_securityEnabled = false; +bool BLESecurity::m_securityStarted = false; +bool BLESecurity::m_passkeySet = false; +bool BLESecurity::m_staticPasskey = true; +bool BLESecurity::m_regenOnConnect = false; +bool BLESecurity::m_authenticationComplete = false; +uint8_t BLESecurity::m_iocap = ESP_IO_CAP_NONE; +uint8_t BLESecurity::m_authReq = 0; +uint8_t BLESecurity::m_initKey = 0; +uint8_t BLESecurity::m_respKey = 0; +uint32_t BLESecurity::m_passkey = BLE_SM_DEFAULT_PASSKEY; + +/*************************************************************************** + * Bluedroid properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +uint8_t BLESecurity::m_keySize = 16; +esp_ble_sec_act_t BLESecurity::m_securityLevel; +FreeRTOS::Semaphore *BLESecurity::m_authCompleteSemaphore = nullptr; +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +// This function initializes the BLESecurity class. +BLESecurity::BLESecurity() { + log_d("BLESecurity: Initializing"); + setKeySize(); + setInitEncryptionKey(); + setRespEncryptionKey(); + setCapability(ESP_IO_CAP_NONE); +} + +// This function sets the authentication mode for the BLE security. +void BLESecurity::setAuthenticationMode(uint8_t auth_req) { + log_d("setAuthenticationMode: auth_req=%d", auth_req); + m_authReq = auth_req; +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_AUTHEN_REQ_MODE, &m_authReq, sizeof(uint8_t)); +#elif defined(CONFIG_NIMBLE_ENABLED) + BLESecurity::setAuthenticationMode( + (auth_req & BLE_SM_PAIR_AUTHREQ_BOND) != 0, (auth_req & BLE_SM_PAIR_AUTHREQ_MITM) != 0, (auth_req & BLE_SM_PAIR_AUTHREQ_SC) != 0 + ); +#endif +} + +// This function sets the Input/Output capability for the BLE security. +void BLESecurity::setCapability(uint8_t iocap) { + log_d("setCapability: iocap=%d", iocap); + m_iocap = iocap; +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t)); +#elif defined(CONFIG_NIMBLE_ENABLED) + ble_hs_cfg.sm_io_cap = iocap; +#endif +} + +// This sets the initiator key distribution flags. +// ESP_BLE_ENC_KEY_MASK indicates that the device should distribute the Encryption Key to the peer device. +// ESP_BLE_ID_KEY_MASK indicates that the device should distribute the Identity Key to the peer device. +// Both are set by default. +void BLESecurity::setInitEncryptionKey(uint8_t init_key) { + log_d("setInitEncryptionKey: init_key=%d", init_key); + m_initKey = init_key; +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_SET_INIT_KEY, &m_initKey, sizeof(uint8_t)); +#elif defined(CONFIG_NIMBLE_ENABLED) + ble_hs_cfg.sm_our_key_dist = init_key; +#endif +} + +// This sets the responder key distribution flags. +// ESP_BLE_ENC_KEY_MASK indicates that the device should distribute the Encryption Key to the peer device. +// ESP_BLE_ID_KEY_MASK indicates that the device should distribute the Identity Key to the peer device. +// Both are set by default. +void BLESecurity::setRespEncryptionKey(uint8_t resp_key) { + log_d("setRespEncryptionKey: resp_key=%d", resp_key); + m_respKey = resp_key; +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_SET_RSP_KEY, &m_respKey, sizeof(uint8_t)); +#elif defined(CONFIG_NIMBLE_ENABLED) + ble_hs_cfg.sm_their_key_dist = resp_key; +#endif +} + +// This function sets the key size for the BLE security. +void BLESecurity::setKeySize(uint8_t key_size) { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_d("setKeySize: key_size=%d", key_size); + m_keySize = key_size; + esp_ble_gap_set_security_param(ESP_BLE_SM_MAX_KEY_SIZE, &m_keySize, sizeof(uint8_t)); +#endif +} + +// This function generates a random passkey between 000000 and 999999. +uint32_t BLESecurity::generateRandomPassKey() { + return random(0, 999999); +} + +// This function sets a passkey for the BLE security. +// The first argument defines if the passkey is static or random. +// The second argument is the passkey (ignored when using a random passkey). +// The function returns the passkey that was set. +uint32_t BLESecurity::setPassKey(bool staticPasskey, uint32_t passkey) { + log_d("setPassKey: staticPasskey=%d, passkey=%d", staticPasskey, passkey); + m_staticPasskey = staticPasskey; + + if (m_staticPasskey) { + m_passkey = passkey; + if (m_passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*WARNING* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*WARNING* Please use a random passkey or set a different static passkey"); + } + } else { + m_passkey = generateRandomPassKey(); + } + + m_passkeySet = true; + +#if defined(CONFIG_BLUEDROID_ENABLED) + // Workaround for making Bluedroid and NimBLE manage the random passkey similarly. + esp_ble_gap_set_security_param(ESP_BLE_SM_SET_STATIC_PASSKEY, &m_passkey, sizeof(uint32_t)); +#endif + + return m_passkey; +} + +// This function gets the passkey being used for the BLE security. +// If a static passkey is set, it will return the static passkey. +// If using a random passkey, it will generate a new random passkey if m_regenOnConnect is true. +// Otherwise, it will return the current passkey being used. +uint32_t BLESecurity::getPassKey() { + if (m_passkeySet && !m_staticPasskey && m_regenOnConnect) { + m_passkey = generateRandomPassKey(); +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_SET_STATIC_PASSKEY, &m_passkey, sizeof(uint32_t)); +#endif + } + return m_passkey; +} + +// This function sets if the passkey should be regenerated on each connection. +void BLESecurity::regenPassKeyOnConnect(bool enable) { + m_regenOnConnect = enable; +} + +// This function resets the security state on disconnect. +void BLESecurity::resetSecurity() { + log_d("resetSecurity: Resetting security state"); + m_securityStarted = false; + m_authenticationComplete = false; +} + +// This function sets the authentication mode with bonding, MITM, and secure connection options. +void BLESecurity::setAuthenticationMode(bool bonding, bool mitm, bool sc) { + log_d("setAuthenticationMode: bonding=%d, mitm=%d, sc=%d", bonding, mitm, sc); + m_authReq = bonding ? ESP_LE_AUTH_BOND : 0; + m_authReq |= mitm ? ESP_LE_AUTH_REQ_MITM : 0; + m_authReq |= sc ? ESP_LE_AUTH_REQ_SC_ONLY : 0; + m_securityEnabled = (m_authReq != 0); +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_ble_gap_set_security_param(ESP_BLE_SM_AUTHEN_REQ_MODE, &m_authReq, sizeof(uint8_t)); + if (sc) { + if (mitm) { + setEncryptionLevel(ESP_BLE_SEC_ENCRYPT_MITM); + } else { + setEncryptionLevel(ESP_BLE_SEC_ENCRYPT_NO_MITM); + } + } +#elif defined(CONFIG_NIMBLE_ENABLED) + ble_hs_cfg.sm_bonding = bonding; + ble_hs_cfg.sm_mitm = mitm; + ble_hs_cfg.sm_sc = sc; +#endif +} + +// This callback is called by the device that has Input capability when the peer device has Output capability +// It can also be called in NimBLE when there is no passkey set. +// It should return the passkey that the peer device is showing on its output. +// This might not be called if the client has a static passkey set. +uint32_t BLESecurityCallbacks::onPassKeyRequest() { + Serial.println("BLESecurityCallbacks: *ATTENTION* Using insecure onPassKeyRequest."); + Serial.println("BLESecurityCallbacks: *ATTENTION* Please implement onPassKeyRequest with a suitable passkey in your BLESecurityCallbacks class"); + Serial.printf("BLESecurityCallbacks: Default passkey: %06d\n", BLE_SM_DEFAULT_PASSKEY); + return BLE_SM_DEFAULT_PASSKEY; +} + +// This callback is called by the device that has Output capability when the peer device has Input capability +// It should display the passkey that will need to be entered on the peer device +void BLESecurityCallbacks::onPassKeyNotify(uint32_t passkey) { + Serial.printf("BLESecurityCallbacks: Using default onPassKeyNotify. Passkey: %06lu\n", passkey); +} + +// This callback is called when the peer device requests a secure connection. +// Usually the client accepts the server's security request. +// It should return true if the connection is accepted, false otherwise. +bool BLESecurityCallbacks::onSecurityRequest() { + Serial.println("BLESecurityCallbacks: Using default onSecurityRequest. It will accept any security request."); + return true; +} + +// This callback is called by both devices when both have the DisplayYesNo capability. +// It should return true if both devices display the same passkey. +bool BLESecurityCallbacks::onConfirmPIN(uint32_t pin) { + Serial.println("BLESecurityCallbacks: *ATTENTION* Using insecure onConfirmPIN. It will accept any passkey."); + Serial.println("BLESecurityCallbacks: *ATTENTION* Please implement onConfirmPIN with a suitable confirmation logic in your BLESecurityCallbacks class"); + return true; +} + +// This callback is called when the characteristic requires authorization. +// connHandle is the connection handle of the peer device. +// attrHandle is the handle of the characteristic. +// If isRead is true, the peer device is requesting to read the characteristic, +// otherwise it is requesting to write. +// It should return true if the authorization is granted, false otherwise. +bool BLESecurityCallbacks::onAuthorizationRequest(uint16_t connHandle, uint16_t attrHandle, bool isRead) { + Serial.println("BLESecurityCallbacks: *ATTENTION* Using insecure onAuthorizationRequest. It will accept any authorization request."); + Serial.println( + "BLESecurityCallbacks: *ATTENTION* Please implement onAuthorizationRequest with a suitable authorization logic in your BLESecurityCallbacks class" + ); + return true; +} + +// This function waits for authentication to complete when bonding is enabled +// It prevents GATT operations from proceeding before pairing completes +void BLESecurity::waitForAuthenticationComplete(uint32_t timeoutMs) { +#if defined(CONFIG_BLUEDROID_ENABLED) + // Only wait if bonding is enabled + if ((m_authReq & ESP_LE_AUTH_BOND) == 0) { + return; + } + + // If already authenticated, no need to wait + if (m_authenticationComplete) { + return; + } + + // Semaphore should have been created in startSecurity() + if (m_authCompleteSemaphore == nullptr) { + log_e("Authentication semaphore not initialized"); + return; + } + + // Wait for authentication with timeout + bool success = m_authCompleteSemaphore->timedWait("waitForAuthenticationComplete", timeoutMs / portTICK_PERIOD_MS); + + if (!success) { + log_w("Timeout waiting for authentication to complete"); + } +#endif +} + +// This function signals that authentication has completed +// Called from ESP_GAP_BLE_AUTH_CMPL_EVT handler +void BLESecurity::signalAuthenticationComplete() { +#if defined(CONFIG_BLUEDROID_ENABLED) + m_authenticationComplete = true; + + // Signal waiting threads if semaphore exists + if (m_authCompleteSemaphore != nullptr) { + m_authCompleteSemaphore->give(); + } +#endif +} + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +// This function sets the encryption level that will be negotiated with peer device during connection +void BLESecurity::setEncryptionLevel(esp_ble_sec_act_t level) { + m_securityLevel = level; +} + +bool BLESecurity::startSecurity(esp_bd_addr_t bd_addr, int *rcPtr) { +#ifdef CONFIG_BLE_SMP_ENABLE + log_d("startSecurity: bd_addr=%s", BLEAddress(bd_addr).toString().c_str()); + if (m_securityStarted) { + log_w("Security already started for bd_addr=%s", BLEAddress(bd_addr).toString().c_str()); + if (rcPtr) { + *rcPtr = ESP_OK; + } + return true; + } + + if (m_securityEnabled) { + // Initialize semaphore before starting security to avoid race condition + if (m_authCompleteSemaphore == nullptr) { + m_authCompleteSemaphore = new FreeRTOS::Semaphore("AuthComplete"); + } + + // Reset authentication complete flag when starting new security negotiation + m_authenticationComplete = false; + + // Consume any pending semaphore signals from previous operations + // This ensures the next wait will block until the new auth completes + m_authCompleteSemaphore->take("startSecurity-reset"); + + int rc = esp_ble_set_encryption(bd_addr, m_securityLevel); + if (rc != ESP_OK) { + log_e("esp_ble_set_encryption: rc=%d %s", rc, GeneralUtils::errorToString(rc)); + } + if (rcPtr) { + *rcPtr = rc; + } + m_securityStarted = (rc == ESP_OK); + } else { + log_e("Security is not enabled. Can't start security."); + if (rcPtr) { + *rcPtr = ESP_FAIL; + } + return false; + } + return m_securityStarted; +#else + log_e("Bluedroid SMP is not enabled. Can't start security."); + return false; +#endif +} + +// This function converts an ESP BLE key type to a string representation. +char *BLESecurity::esp_key_type_to_str(esp_ble_key_type_t key_type) { + char *key_str = nullptr; + switch (key_type) { + case ESP_LE_KEY_NONE: key_str = (char *)"ESP_LE_KEY_NONE"; break; + case ESP_LE_KEY_PENC: key_str = (char *)"ESP_LE_KEY_PENC"; break; + case ESP_LE_KEY_PID: key_str = (char *)"ESP_LE_KEY_PID"; break; + case ESP_LE_KEY_PCSRK: key_str = (char *)"ESP_LE_KEY_PCSRK"; break; + case ESP_LE_KEY_PLK: key_str = (char *)"ESP_LE_KEY_PLK"; break; + case ESP_LE_KEY_LLK: key_str = (char *)"ESP_LE_KEY_LLK"; break; + case ESP_LE_KEY_LENC: key_str = (char *)"ESP_LE_KEY_LENC"; break; + case ESP_LE_KEY_LID: key_str = (char *)"ESP_LE_KEY_LID"; break; + case ESP_LE_KEY_LCSRK: key_str = (char *)"ESP_LE_KEY_LCSRK"; break; + default: key_str = (char *)"INVALID BLE KEY TYPE"; break; + } + return key_str; +} + +// This function is called when authentication is complete. +void BLESecurityCallbacks::onAuthenticationComplete(esp_ble_auth_cmpl_t param) { + bool success = param.success; + Serial.printf("Using default onAuthenticationComplete. Authentication %s.\n", success ? "successful" : "failed"); +} +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +// This function initiates security for a given connection handle. +bool BLESecurity::startSecurity(uint16_t connHandle, int *rcPtr) { + log_d("startSecurity: connHandle=%d", connHandle); + if (m_securityStarted) { + log_w("Security already started for connHandle=%d", connHandle); + if (rcPtr) { + *rcPtr = 0; + } + return true; + } + + if (m_securityEnabled) { + int rc = ble_gap_security_initiate(connHandle); + if (rc != 0) { + log_e("ble_gap_security_initiate: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + } + if (rcPtr) { + *rcPtr = rc; + } + m_securityStarted = (rc == 0 || rc == BLE_HS_EALREADY); + } else { + log_e("Security is not enabled. Can't start security."); + if (rcPtr) { + *rcPtr = ESP_FAIL; + } + return false; + } + return m_securityStarted; +} + +// This function is called when authentication is complete for NimBLE. +void BLESecurityCallbacks::onAuthenticationComplete(ble_gap_conn_desc *desc) { + bool success = desc != nullptr; + Serial.printf("Using default onAuthenticationComplete. Authentication %s.\n", success ? "successful" : "failed"); +} +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLESecurity.h b/libraries/BLE/src/BLESecurity.h new file mode 100644 index 0000000..fc6ff38 --- /dev/null +++ b/libraries/BLE/src/BLESecurity.h @@ -0,0 +1,227 @@ +/* + * BLESecurity.h + * + * Created on: Dec 17, 2017 + * Author: chegewara + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on chegewara's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLESECURITY_H_ +#define COMPONENTS_CPP_UTILS_BLESECURITY_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#include "WString.h" +#include "BLEDevice.h" +#include "BLEClient.h" +#include "BLEServer.h" +#include "RTOS.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#endif + +/*************************************************************************** + * Common definitions * + ***************************************************************************/ + +#define BLE_SM_DEFAULT_PASSKEY 123456 + +/*************************************************************************** + * NimBLE definitions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +// Compatibility with Bluedroid definitions + +#define ESP_IO_CAP_OUT BLE_HS_IO_DISPLAY_ONLY +#define ESP_IO_CAP_IO BLE_HS_IO_DISPLAY_YESNO +#define ESP_IO_CAP_IN BLE_HS_IO_KEYBOARD_ONLY +#define ESP_IO_CAP_NONE BLE_HS_IO_NO_INPUT_OUTPUT +#define ESP_IO_CAP_KBDISP BLE_HS_IO_KEYBOARD_DISPLAY + +#define ESP_LE_AUTH_NO_BOND 0x00 +#define ESP_LE_AUTH_BOND BLE_SM_PAIR_AUTHREQ_BOND +#define ESP_LE_AUTH_REQ_MITM BLE_SM_PAIR_AUTHREQ_MITM +#define ESP_LE_AUTH_REQ_SC_ONLY BLE_SM_PAIR_AUTHREQ_SC +#define ESP_LE_AUTH_REQ_BOND_MITM (BLE_SM_PAIR_AUTHREQ_BOND | BLE_SM_PAIR_AUTHREQ_MITM) +#define ESP_LE_AUTH_REQ_SC_BOND (BLE_SM_PAIR_AUTHREQ_BOND | BLE_SM_PAIR_AUTHREQ_SC) +#define ESP_LE_AUTH_REQ_SC_MITM (BLE_SM_PAIR_AUTHREQ_MITM | BLE_SM_PAIR_AUTHREQ_SC) +#define ESP_LE_AUTH_REQ_SC_MITM_BOND (BLE_SM_PAIR_AUTHREQ_MITM | BLE_SM_PAIR_AUTHREQ_SC | BLE_SM_PAIR_AUTHREQ_BOND) + +#define ESP_BLE_ENC_KEY_MASK BLE_HS_KEY_DIST_ENC_KEY +#define ESP_BLE_ID_KEY_MASK BLE_HS_KEY_DIST_ID_KEY +#endif + +/*************************************************************************** + * Forward declarations * + ***************************************************************************/ + +class BLEDevice; +class BLEServer; +class BLEClient; + +/** + * @brief Security management class + */ +class BLESecurity { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLESecurity(); + virtual ~BLESecurity() = default; + static void setAuthenticationMode(uint8_t auth_req); + static void setCapability(uint8_t iocap); + static void setInitEncryptionKey(uint8_t init_key = (ESP_BLE_ENC_KEY_MASK | ESP_BLE_ID_KEY_MASK)); + static void setRespEncryptionKey(uint8_t resp_key = (ESP_BLE_ENC_KEY_MASK | ESP_BLE_ID_KEY_MASK)); + static void setKeySize(uint8_t key_size = 16); + static uint32_t setPassKey(bool staticPasskey = false, uint32_t passkey = BLE_SM_DEFAULT_PASSKEY); + static void setAuthenticationMode(bool bonding, bool mitm, bool sc); + static uint32_t getPassKey(); + static uint32_t generateRandomPassKey(); + static void regenPassKeyOnConnect(bool enable = false); + static void resetSecurity(); + static void waitForAuthenticationComplete(uint32_t timeoutMs = 10000); + static void signalAuthenticationComplete(); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static char *esp_key_type_to_str(esp_ble_key_type_t key_type); + static void setEncryptionLevel(esp_ble_sec_act_t level); + static bool startSecurity(esp_bd_addr_t bd_addr, int *rcPtr = nullptr); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static bool startSecurity(uint16_t connHandle, int *rcPtr = nullptr); +#endif + +private: + friend class BLEDevice; + friend class BLEServer; + friend class BLEClient; + friend class BLERemoteCharacteristic; + friend class BLERemoteDescriptor; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + static bool m_securityEnabled; + static bool m_securityStarted; + static bool m_forceSecurity; + static bool m_passkeySet; + static bool m_staticPasskey; + static bool m_regenOnConnect; + static bool m_authenticationComplete; + static uint8_t m_iocap; + static uint8_t m_authReq; + static uint8_t m_initKey; + static uint8_t m_respKey; + static uint32_t m_passkey; + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static uint8_t m_keySize; + static esp_ble_sec_act_t m_securityLevel; + static class FreeRTOS::Semaphore *m_authCompleteSemaphore; +#endif + +}; // BLESecurity + +/** + * @brief Callbacks to handle GAP events related to authorization + */ +class BLESecurityCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLESecurityCallbacks() = default; + virtual ~BLESecurityCallbacks() = default; + + // This callback is called by the device that has Input capability when the peer device has Output capability + // and the passkey is not set. + // It should return the passkey that the peer device is showing on its output. + // This MUST be replaced with a custom implementation when being used. + virtual uint32_t onPassKeyRequest(); + + // This callback is called by the device that has Output capability when the peer device has Input capability + // It should display the passkey that will need to be entered on the peer device + virtual void onPassKeyNotify(uint32_t pass_key); + + // This callback is called when the peer device requests a secure connection. + // Usually the client accepts the server's security request. + // It should return true if the connection is accepted, false otherwise. + virtual bool onSecurityRequest(); + + // This callback is called by both devices when both have the DisplayYesNo capability. + // It should return true if both devices display the same passkey. + // This MUST be replaced with a custom implementation when being used. + virtual bool onConfirmPIN(uint32_t pin); + + // This callback is called when the peer device requests authorization to read or write a characteristic. + // It should return true if the authorization is granted, false otherwise. + // This MUST be replaced with a custom implementation when being used. + virtual bool onAuthorizationRequest(uint16_t connHandle, uint16_t attrHandle, bool isRead); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + // This callback is called when the authentication is complete. + // Status can be checked in the desc parameter. + virtual void onAuthenticationComplete(esp_ble_auth_cmpl_t desc); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + // This callback is called when the authentication is complete. + // Status can be checked in the desc parameter. + virtual void onAuthenticationComplete(ble_gap_conn_desc *desc); +#endif + +}; // BLESecurityCallbacks + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif // COMPONENTS_CPP_UTILS_BLESECURITY_H_ diff --git a/libraries/BLE/src/BLEServer.cpp b/libraries/BLE/src/BLEServer.cpp new file mode 100644 index 0000000..85e59fb --- /dev/null +++ b/libraries/BLE/src/BLEServer.cpp @@ -0,0 +1,1217 @@ +/* + * BLEServer.cpp + * + * Created on: Apr 16, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/*************************************************************************** + * Common includes * + ***************************************************************************/ + +#if SOC_BLE_SUPPORTED +#include +#endif +#include "GeneralUtils.h" +#include "BLEDevice.h" +#include "BLEServer.h" +#include "BLEService.h" +#include "BLEUtils.h" +#include +#include +#include +#include "esp32-hal-log.h" + +/*************************************************************************** + * Bluedroid includes * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include "BLE2902.h" +#endif + +/*************************************************************************** + * NimBLE includes * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#endif + +/*************************************************************************** + * Common functions * + ***************************************************************************/ + +/** + * @brief Construct a %BLE Server + * + * This class is not designed to be individually instantiated. Instead one should create a server by asking + * the BLEDevice class. + */ +BLEServer::BLEServer() { +#ifdef CONFIG_BLUEDROID_ENABLED + m_gatts_if = ESP_GATT_IF_NONE; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + memset(m_indWait, BLE_HS_CONN_HANDLE_NONE, sizeof(m_indWait)); + m_svcChanged = false; +#endif + +#if !defined(CONFIG_BT_NIMBLE_EXT_ADV) || defined(CONFIG_BLUEDROID_ENABLED) + m_advertiseOnDisconnect = false; +#endif + + m_appId = ESP_GATT_IF_NONE; + m_gattsStarted = false; + m_connectedCount = 0; + m_connId = ESP_GATT_IF_NONE; + m_pServerCallbacks = nullptr; +} // BLEServer + +void BLEServer::createApp(uint16_t appId) { + m_appId = appId; +#ifdef CONFIG_BLUEDROID_ENABLED + registerApp(appId); +#endif +} // createApp + +/** + * @brief Create a %BLE Service. + * + * With a %BLE server, we can host one or more services. Invoking this function causes the creation of a definition + * of a new service. Every service must have a unique UUID. + * @param [in] uuid The UUID of the new service. + * @return A reference to the new service object. + */ +BLEService *BLEServer::createService(const char *uuid) { + return createService(BLEUUID(uuid)); +} + +/** + * @brief Create a %BLE Service. + * + * With a %BLE server, we can host one or more services. Invoking this function causes the creation of a definition + * of a new service. Every service must have a unique UUID. + * @param [in] uuid The UUID of the new service. + * @param [in] numHandles The maximum number of handles associated with this service. + * @param [in] inst_id With multiple services with the same UUID we need to provide inst_id value different for each service. + * @return A reference to the new service object. + */ +BLEService *BLEServer::createService(BLEUUID uuid, uint32_t numHandles, uint8_t inst_id) { + log_v(">> createService - %s", uuid.toString().c_str()); +#ifdef CONFIG_BLUEDROID_ENABLED + m_semaphoreCreateEvt.take("createService"); +#endif + + // Check that a service with the supplied UUID does not already exist. + if (m_serviceMap.getByUUID(uuid) != nullptr) { + log_w("<< Attempt to create a new service with uuid %s but a service with that UUID already exists.", uuid.toString().c_str()); + } + + BLEService *pService = new BLEService(uuid, numHandles); + pService->m_instId = inst_id; + m_serviceMap.setByUUID(uuid, pService); // Save a reference to this service being on this server. + pService->executeCreate(this); // Perform the API calls to actually create the service. + +#ifdef CONFIG_BLUEDROID_ENABLED + m_semaphoreCreateEvt.wait("createService"); +#endif + +#ifdef CONFIG_NIMBLE_ENABLED + m_semaphoreCreateEvt.give(); + serviceChanged(); +#endif + + log_v("<< createService"); + return pService; +} // createService + +/** + * @brief Get a %BLE Service by its UUID + * @param [in] uuid The UUID of the new service. + * @return A reference to the service object. + */ +BLEService *BLEServer::getServiceByUUID(const char *uuid) { + return m_serviceMap.getByUUID(uuid); +} + +/** + * @brief Get a %BLE Service by its UUID + * @param [in] uuid The UUID of the new service. + * @return A reference to the service object. + */ +BLEService *BLEServer::getServiceByUUID(BLEUUID uuid) { + return m_serviceMap.getByUUID(uuid); +} + +/** + * @brief Retrieve the advertising object that can be used to advertise the existence of the server. + * + * @return An advertising object. + */ +BLEAdvertising *BLEServer::getAdvertising() { + return BLEDevice::getAdvertising(); +} + +uint16_t BLEServer::getConnId() { + return m_connId; +} + +/** + * @brief Return the number of connected clients. + * @return The number of connected clients. + */ +uint32_t BLEServer::getConnectedCount() { + return m_connectedCount; +} // getConnectedCount + +void BLEServer::start() { + if (m_gattsStarted) { + return; + } + +#ifdef CONFIG_NIMBLE_ENABLED + int rc = ble_gatts_start(); + if (rc != 0) { + log_e("ble_gatts_start; rc=%d, %s", rc, BLEUtils::returnCodeToString(rc)); + return; + } + + // Re-set the device name after ble_gatts_start() because ble_svc_gap_init() + // (called in createServer) resets it to the default "nimble" from sdkconfig. + // The GAP service device name must be set after the GATT server is started. + String deviceName = BLEDevice::getDeviceName(); + if (deviceName.length() > 0) { + rc = ble_svc_gap_device_name_set(deviceName.c_str()); + if (rc != 0) { + log_e("ble_svc_gap_device_name_set: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + } + } + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + ble_gatts_show_local(); +#endif + + BLEService *svc = m_serviceMap.getFirst(); + while (svc != nullptr) { + if (svc->m_removed == 0) { + rc = ble_gatts_find_svc(&svc->getUUID().getNative()->u, &svc->m_handle); + if (rc != 0) { + abort(); + } + } + + BLECharacteristic *chr = svc->m_characteristicMap.getFirst(); + while (chr != nullptr) { + if ((chr->m_properties & BLE_GATT_CHR_F_INDICATE) || (chr->m_properties & BLE_GATT_CHR_F_NOTIFY)) { + m_notifyChrVec.push_back(chr); + } + chr = svc->m_characteristicMap.getNext(); + } + + svc = m_serviceMap.getNext(); + } + +#endif + + m_gattsStarted = true; +} + +/** + * @brief Check if the GATT server has been started. + * + * This method indicates whether the GATT server is ready to handle + * operations like notifications and indications. + * + * @return true if the server is started and ready, false otherwise. + */ +bool BLEServer::isStarted() { + return m_gattsStarted; +} + +/** + * @brief Set the server callbacks. + * + * As a %BLE server operates, it will generate server level events such as a new client connecting or a previous client + * disconnecting. This function can be called to register a callback handler that will be invoked when these + * events are detected. + * + * @param [in] pCallbacks The callbacks to be invoked. + */ +void BLEServer::setCallbacks(BLEServerCallbacks *pCallbacks) { + m_pServerCallbacks = pCallbacks; +} // setCallbacks + +/* + * Remove service + */ +void BLEServer::removeService(BLEService *service) { +#if defined(CONFIG_BLUEDROID_ENABLED) + service->stop(); + service->executeDelete(); + m_serviceMap.removeService(service); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + if (service->m_removed == 0) { + int rc = ble_gatts_svc_set_visibility(service->getHandle(), 0); + if (rc != 0) { + return; + } + service->m_removed = NIMBLE_ATT_REMOVE_DELETE; + serviceChanged(); + m_serviceMap.removeService(service); + BLEDevice::getAdvertising()->removeServiceUUID(service->getUUID()); + } +#endif +} + +/** + * @brief Start advertising. + * + * Start the server advertising its existence. This is a convenience function and is equivalent to + * retrieving the advertising object and invoking start upon it. + */ +void BLEServer::startAdvertising() { + log_v(">> startAdvertising"); + BLEDevice::startAdvertising(); + log_v("<< startAdvertising"); +} // startAdvertising + +/* multi connect support */ +/* TODO do some more tweaks */ +void BLEServer::updatePeerMTU(uint16_t conn_id, uint16_t mtu) { + // set mtu in conn_status_t + const std::map::iterator it = m_connectedServersMap.find(conn_id); + if (it != m_connectedServersMap.end()) { + it->second.mtu = mtu; + std::swap(m_connectedServersMap[conn_id], it->second); + } +} + +std::map BLEServer::getPeerDevices(bool _client) { + return m_connectedServersMap; +} + +uint16_t BLEServer::getPeerMTU(uint16_t conn_id) { +#if defined(CONFIG_BLUEDROID_ENABLED) + return m_connectedServersMap.find(conn_id)->second.mtu; +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + return ble_att_mtu(conn_id); +#endif +} + +void BLEServer::addPeerDevice(void *peer, bool _client, uint16_t conn_id) { + conn_status_t status = {.peer_device = peer, .connected = true, .mtu = 23}; + + m_connectedServersMap.insert(std::pair(conn_id, status)); +} + +bool BLEServer::removePeerDevice(uint16_t conn_id, bool _client) { + return m_connectedServersMap.erase(conn_id) > 0; +} + +#if !defined(CONFIG_BT_NIMBLE_EXT_ADV) || defined(CONFIG_BLUEDROID_ENABLED) +void BLEServer::advertiseOnDisconnect(bool enable) { + m_advertiseOnDisconnect = enable; +} +#endif + +void BLEServerCallbacks::onConnect(BLEServer *pServer) { + log_d("BLEServerCallbacks", ">> onConnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onConnect()"); +} // onConnect + +void BLEServerCallbacks::onDisconnect(BLEServer *pServer) { + log_d("BLEServerCallbacks", ">> onDisconnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onDisconnect()"); +} // onDisconnect + +/*************************************************************************** + * Bluedroid functions * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * Allow to connect GATT server to peer device + * Probably can be used in ANCS for iPhone + */ +bool BLEServer::connect(BLEAddress address) { + esp_bd_addr_t addr; + memcpy(&addr, address.getNative(), 6); + // Perform the open connection request against the target BLE Server. + m_semaphoreOpenEvt.take("connect"); + esp_err_t errRc = ::esp_ble_gatts_open( + getGattsIf(), + addr, // address + 1 // direct connection + ); + if (errRc != ESP_OK) { + log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + + uint32_t rc = m_semaphoreOpenEvt.wait("connect"); // Wait for the connection to complete. + log_v("<< connect(), rc=%d", rc == ESP_GATT_OK); + return rc == ESP_GATT_OK; +} // connect + +/** + * @brief Request an update to the connection parameters. + * + * As the BLE Peripheral (server), this device can request connection parameter + * changes from the central. However, the central (client) makes the final decision + * and may accept, reject, or negotiate different parameters. + * + * Can only be called after a connection has been established. + * + * @param [in] remote_bda The Bluetooth device address of the peer. + * @param [in] minInterval The minimum connection interval in 1.25ms units (e.g., 80 = 100ms). + * @param [in] maxInterval The maximum connection interval in 1.25ms units (e.g., 800 = 1000ms). + * @param [in] latency Number of consecutive connection events the peripheral can skip (0-499). + * Higher values save power but increase response latency. + * @param [in] timeout The supervision timeout in 10ms units (e.g., 400 = 4000ms). + * Must be > (1 + latency) * maxInterval * 2. + * @return True on success, false on failure. + */ +bool BLEServer::requestConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + esp_ble_conn_update_params_t conn_params; + memcpy(conn_params.bda, remote_bda, sizeof(esp_bd_addr_t)); + conn_params.latency = latency; + conn_params.max_int = maxInterval; // max_int = 0x20*1.25ms = 40ms + conn_params.min_int = minInterval; // min_int = 0x10*1.25ms = 20ms + conn_params.timeout = timeout; // timeout = 400*10ms = 4000ms + + esp_err_t errRc = esp_ble_gap_update_conn_params(&conn_params); + if (errRc != ESP_OK) { + log_e("esp_ble_gap_update_conn_params: rc=%d", errRc); + return false; + } + return true; +} + +/** + * @brief Request an update to the connection parameters. + * @deprecated Use requestConnParams() instead. This method is kept for backward compatibility. + */ +void BLEServer::updateConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + requestConnParams(remote_bda, minInterval, maxInterval, latency, timeout); +} + +void BLEServer::disconnect(uint16_t connId) { + esp_ble_gatts_close(m_gatts_if, connId); +} + +/** + * @brief Handle a received GAP event for the server. + * @param [in] event The GAP event type. + * @param [in] param The GAP event parameter. + */ +void BLEServer::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + log_v(">> BLEServer::handleGAPEvent"); + + switch (event) { + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + { + if (m_pServerCallbacks != nullptr) { + m_pServerCallbacks->onConnParamsUpdate( + param->update_conn_params.bda, param->update_conn_params.conn_int, param->update_conn_params.latency, param->update_conn_params.timeout, + param->update_conn_params.status + ); + } + break; + } + default: break; + } + + log_v("<< BLEServer::handleGAPEvent"); +} + +uint16_t BLEServer::getGattsIf() { + return m_gatts_if; +} + +/** + * @brief Handle a GATT Server Event. + * + * @param [in] event + * @param [in] gatts_if + * @param [in] param + * + */ +void BLEServer::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + log_v(">> handleGATTServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str()); + + switch (event) { + // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service. + // add_char: + // - esp_gatt_status_t status + // - uint16_t attr_handle + // - uint16_t service_handle + // - esp_bt_uuid_t char_uuid + // + case ESP_GATTS_ADD_CHAR_EVT: + { + break; + } // ESP_GATTS_ADD_CHAR_EVT + + case ESP_GATTS_MTU_EVT: + updatePeerMTU(param->mtu.conn_id, param->mtu.mtu); + if (m_pServerCallbacks != nullptr) { + m_pServerCallbacks->onMtuChanged(this, param); + } + break; + + // ESP_GATTS_CONNECT_EVT + // connect: + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + // + case ESP_GATTS_CONNECT_EVT: + { + log_i("Client connected, conn_id=%d", param->connect.conn_id); + m_connId = param->connect.conn_id; + addPeerDevice((void *)this, false, m_connId); + if (m_pServerCallbacks != nullptr) { + m_pServerCallbacks->onConnect(this); + m_pServerCallbacks->onConnect(this, param); + } + m_connectedCount++; // Increment the number of connected devices count. + break; + } // ESP_GATTS_CONNECT_EVT + + // ESP_GATTS_CREATE_EVT + // Called when a new service is registered as having been created. + // + // create: + // * esp_gatt_status_t status + // * uint16_t service_handle + // * esp_gatt_srvc_id_t service_id + // + case ESP_GATTS_CREATE_EVT: + { + BLEService *pService = m_serviceMap.getByUUID( + param->create.service_id.id.uuid, param->create.service_id.id.inst_id + ); // <--- very big bug for multi services with the same uuid + m_serviceMap.setByHandle(param->create.service_handle, pService); + m_semaphoreCreateEvt.give(); + break; + } // ESP_GATTS_CREATE_EVT + + // ESP_GATTS_DISCONNECT_EVT + // + // disconnect + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + // - esp_gatt_conn_reason_t reason + // + // If we receive a disconnect event then invoke the callback for disconnects (if one is present). + // we also want to start advertising again. + case ESP_GATTS_DISCONNECT_EVT: + { + log_i("Client disconnected, conn_id=%d, reason=%d", param->disconnect.conn_id, param->disconnect.reason); + if (m_pServerCallbacks != nullptr) { // If we have callbacks, call now. + m_pServerCallbacks->onDisconnect(this); + m_pServerCallbacks->onDisconnect(this, param); + } + if (m_connId == ESP_GATT_IF_NONE) { + return; + } + + // only decrement if connection is found in map and removed + // sometimes this event triggers w/o a valid connection + if (removePeerDevice(param->disconnect.conn_id, false)) { + m_connectedCount--; // Decrement the number of connected devices count. + } + + // Reset security state on disconnect + BLESecurity::resetSecurity(); + + // Start advertising again if enabled + if (m_advertiseOnDisconnect) { + log_i("Start advertising again after disconnect"); + startAdvertising(); + } + + break; + } // ESP_GATTS_DISCONNECT_EVT + + // ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived. + // + // read: + // - uint16_t conn_id + // - uint32_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool is_long + // - bool need_rsp + // + case ESP_GATTS_READ_EVT: + { + break; + } // ESP_GATTS_READ_EVT + + // ESP_GATTS_REG_EVT + // reg: + // - esp_gatt_status_t status + // - uint16_t app_id + // + case ESP_GATTS_REG_EVT: + { + log_i("GATT server registered, status=%d, app_id=%d, gatts_if=%d", param->reg.status, param->reg.app_id, gatts_if); + m_gatts_if = gatts_if; + m_semaphoreRegisterAppEvt.give(); // Unlock the mutex waiting for the registration of the app. + break; + } // ESP_GATTS_REG_EVT + + // ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived. + // + // write: + // - uint16_t conn_id + // - uint16_t trans_id + // - esp_bd_addr_t bda + // - uint16_t handle + // - uint16_t offset + // - bool need_rsp + // - bool is_prep + // - uint16_t len + // - uint8_t* value + // + case ESP_GATTS_WRITE_EVT: + { + break; + } + + case ESP_GATTS_OPEN_EVT: m_semaphoreOpenEvt.give(param->open.status); break; + + default: break; + } + + // Invoke the handler for every Service we have. + m_serviceMap.handleGATTServerEvent(event, gatts_if, param); + + log_v("<< handleGATTServerEvent"); +} // handleGATTServerEvent + +/** + * @brief Register the app. + * + * @return N/A + */ +void BLEServer::registerApp(uint16_t m_appId) { + log_v(">> registerApp - %d", m_appId); + m_semaphoreRegisterAppEvt.take("registerApp"); // Take the mutex, will be released by ESP_GATTS_REG_EVT event. + ::esp_ble_gatts_app_register(m_appId); + m_semaphoreRegisterAppEvt.wait("registerApp"); + log_v("<< registerApp"); +} // registerApp + +// Bluedroid callbacks + +void BLEServerCallbacks::onConnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) { + log_d("BLEServerCallbacks", ">> onConnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onConnect()"); +} // onConnect + +void BLEServerCallbacks::onDisconnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) { + log_d("BLEServerCallbacks", ">> onDisconnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onDisconnect()"); +} // onDisconnect + +void BLEServerCallbacks::onMtuChanged(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) { + [[maybe_unused]] + uint16_t mtu = param->mtu.mtu; + log_d("BLEServerCallbacks", ">> onMtuChanged(): Default"); + log_d("BLEServerCallbacks", "Device: %s MTU: %d", BLEDevice::toString().c_str(), mtu); + log_d("BLEServerCallbacks", "<< onMtuChanged()"); +} // onMtuChanged + +/** + * @brief Restore CCCD values for a bonded device from NVS. + * + * Iterates through all services and their characteristics, restoring any + * persisted CCCD values for the given peer address. This enables notifications + * and indications to work correctly after a bonded device reconnects. + * + * @param [in] peerAddress The address of the bonded peer device. + */ +void BLEServer::restoreCCCDValues(const BLEAddress &peerAddress) { + log_i("Restoring CCCD values for bonded device: %s", peerAddress.toString().c_str()); + + int restoredCount = 0; + + // Iterate through all services + BLEService *pService = m_serviceMap.getFirst(); + while (pService != nullptr) { + // Get the characteristic map from the service + BLECharacteristic *pChar = pService->m_characteristicMap.getFirst(); + while (pChar != nullptr) { + // Check if this characteristic has a CCCD descriptor + BLEDescriptor *pDesc = pChar->getDescriptorByUUID(BLEUUID((uint16_t)0x2902)); + if (pDesc != nullptr) { + BLE2902 *pCCCD = (BLE2902 *)pDesc; + uint16_t charHandle = pChar->getHandle(); + + // Try to restore the CCCD value from NVS + if (pCCCD->restoreValue(peerAddress, charHandle)) { + restoredCount++; + log_d("Restored CCCD for characteristic handle 0x%04x: notify=%d, indicate=%d", charHandle, pCCCD->getNotifications(), pCCCD->getIndications()); + } + } + pChar = pService->m_characteristicMap.getNext(); + } + pService = m_serviceMap.getNext(); + } + + log_i("Restored %d CCCD value(s) for peer %s", restoredCount, peerAddress.toString().c_str()); +} + +void BLEServerCallbacks::onConnParamsUpdate(esp_bd_addr_t remote_bda, uint16_t interval, uint16_t latency, uint16_t timeout, esp_bt_status_t status) { + log_d("BLEServerCallbacks", ">> onConnParamsUpdate(): Default"); + log_d( + "BLEServerCallbacks", "Interval: %d (%.2f ms), Latency: %d, Timeout: %d (%d ms), Status: %d", interval, interval * 1.25, latency, timeout, timeout * 10, + status + ); + log_d("BLEServerCallbacks", "<< onConnParamsUpdate()"); +} // onConnParamsUpdate + +#endif + +/*************************************************************************** + * NimBLE functions * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +uint16_t BLEServer::getHandle() { + return getConnId(); +} + +/** + * @brief Resets the GATT server, used when services are added/removed after initialization. + */ +void BLEServer::resetGATT() { + if (getConnectedCount() > 0) { + return; + } + + BLEDevice::stopAdvertising(); + ble_gatts_reset(); + ble_svc_gap_init(); + ble_svc_gatt_init(); + + BLEService *svc = m_serviceMap.getFirst(); + while (svc != nullptr) { + if (svc->m_removed > 0) { + if (svc->m_removed == NIMBLE_ATT_REMOVE_DELETE) { + m_serviceMap.removeService(svc); + delete svc; + } + } else { + svc->start(); + } + + svc = m_serviceMap.getNext(); + } + + m_svcChanged = false; + m_gattsStarted = false; +} + +/** + * @brief Handle a GATT Server Event. + * + * @param [in] event + * @param [in] gatts_if + * @param [in] param + * + */ +int BLEServer::handleGATTServerEvent(struct ble_gap_event *event, void *arg) { + BLEServer *server = (BLEServer *)arg; + log_v(">> handleGAPEvent: %s", BLEUtils::gapEventToString(event->type)); + int rc = 0; + struct ble_gap_conn_desc desc; + + switch (event->type) { + case BLE_GAP_EVENT_CONNECT: + { + if (event->connect.status != 0) { + /* Connection failed; resume advertising */ + log_e("Connection failed"); + BLEDevice::startAdvertising(); + } else { + server->m_connId = event->connect.conn_handle; + server->addPeerDevice((void *)server, false, event->connect.conn_handle); + rc = ble_gap_conn_find(event->connect.conn_handle, &desc); + if (rc != 0) { + return 0; + } + + if (server->m_pServerCallbacks != nullptr) { + server->m_pServerCallbacks->onConnect(server); + server->m_pServerCallbacks->onConnect(server, &desc); + } + + if (BLESecurity::m_securityEnabled && BLESecurity::m_forceSecurity) { + BLESecurity::startSecurity(event->connect.conn_handle); + } + + server->m_connectedCount++; + } + + return 0; + } // BLE_GAP_EVENT_CONNECT + + case BLE_GAP_EVENT_DISCONNECT: + { + // If Host reset tell the device now before returning to prevent + // any errors caused by calling host functions before resyncing. + switch (event->disconnect.reason) { + case BLE_HS_ETIMEOUT_HCI: + case BLE_HS_EOS: + case BLE_HS_ECONTROLLER: + case BLE_HS_ENOTSYNCED: + log_d("Disconnect - host reset, rc=%d", event->disconnect.reason); + BLEDevice::onReset(event->disconnect.reason); + break; + default: break; + } + + if (server->removePeerDevice(event->disconnect.conn.conn_handle, false)) { + server->m_connectedCount--; + } + + if (server->m_svcChanged) { + server->resetGATT(); + } + + if (server->m_pServerCallbacks != nullptr) { + server->m_pServerCallbacks->onDisconnect(server); + server->m_pServerCallbacks->onDisconnect(server, &event->disconnect.conn); + } + + // Reset security state on disconnect + BLESecurity::resetSecurity(); + +#if !defined(CONFIG_BT_NIMBLE_EXT_ADV) + if (server->m_advertiseOnDisconnect) { + log_i("Start advertising again after disconnect"); + server->startAdvertising(); + } +#endif + + return 0; + } // BLE_GAP_EVENT_DISCONNECT + + case BLE_GAP_EVENT_SUBSCRIBE: + { + log_i("subscribe event; attr_handle=%d, subscribed: %s", event->subscribe.attr_handle, (event->subscribe.cur_notify ? "true" : "false")); + + for (auto &it : server->m_notifyChrVec) { + if (it->getHandle() == event->subscribe.attr_handle) { + uint16_t properties = it->getProperties(); + if ((properties & BLE_GATT_CHR_F_READ_AUTHEN) || (properties & BLE_GATT_CHR_F_READ_AUTHOR) || (properties & BLE_GATT_CHR_F_READ_ENC)) { + rc = ble_gap_conn_find(event->subscribe.conn_handle, &desc); + if (rc != 0) { + break; + } + + if (!desc.sec_state.encrypted) { + BLESecurity::startSecurity(event->subscribe.conn_handle); + } + } + + it->setSubscribe(event); + break; + } + } + + return 0; + } // BLE_GAP_EVENT_SUBSCRIBE + + case BLE_GAP_EVENT_MTU: + { + log_i("mtu update event; conn_handle=%d mtu=%d", event->mtu.conn_handle, event->mtu.value); + rc = ble_gap_conn_find(event->mtu.conn_handle, &desc); + if (rc != 0) { + return 0; + } + + if (server->m_pServerCallbacks != nullptr) { + server->m_pServerCallbacks->onMtuChanged(server, &desc, event->mtu.value); + } + return 0; + } // BLE_GAP_EVENT_MTU + + case BLE_GAP_EVENT_NOTIFY_TX: + { + BLECharacteristic *pChar = nullptr; + + for (auto &it : server->m_notifyChrVec) { + if (it->getHandle() == event->notify_tx.attr_handle) { + pChar = it; + } + } + + if (pChar == nullptr) { + return 0; + } + + BLECharacteristicCallbacks::Status statusRC; + + if (event->notify_tx.indication) { + if (event->notify_tx.status != 0) { + if (event->notify_tx.status == BLE_HS_EDONE) { + statusRC = BLECharacteristicCallbacks::Status::SUCCESS_INDICATE; + } else if (rc == BLE_HS_ETIMEOUT) { + statusRC = BLECharacteristicCallbacks::Status::ERROR_INDICATE_TIMEOUT; + } else { + statusRC = BLECharacteristicCallbacks::Status::ERROR_INDICATE_FAILURE; + } + } else { + return 0; + } + + server->clearIndicateWait(event->notify_tx.conn_handle); + } else { + if (event->notify_tx.status == 0) { + statusRC = BLECharacteristicCallbacks::Status::SUCCESS_NOTIFY; + } else { + statusRC = BLECharacteristicCallbacks::Status::ERROR_GATT; + } + } + + pChar->m_pCallbacks->onStatus(pChar, statusRC, event->notify_tx.status); + + return 0; + } // BLE_GAP_EVENT_NOTIFY_TX + + case BLE_GAP_EVENT_ADV_COMPLETE: + { + log_d("Advertising Complete"); + BLEDevice::getAdvertising()->advCompleteCB(); + return 0; + } + + case BLE_GAP_EVENT_CONN_UPDATE: + { + log_d("Connection parameters updated."); + if (server->m_pServerCallbacks != nullptr) { + rc = ble_gap_conn_find(event->conn_update.conn_handle, &desc); + if (rc == 0) { + server->m_pServerCallbacks->onConnParamsUpdate( + event->conn_update.conn_handle, desc.conn_itvl, desc.conn_latency, desc.supervision_timeout, event->conn_update.status + ); + } + } + return 0; + } // BLE_GAP_EVENT_CONN_UPDATE + + case BLE_GAP_EVENT_REPEAT_PAIRING: + { + /* We already have a bond with the peer, but it is attempting to + * establish a new secure link. This app sacrifices security for + * convenience: just throw away the old bond and accept the new link. + */ + + /* Delete the old bond. */ + rc = ble_gap_conn_find(event->repeat_pairing.conn_handle, &desc); + if (rc != 0) { + return BLE_GAP_REPEAT_PAIRING_IGNORE; + } + + ble_store_util_delete_peer(&desc.peer_id_addr); + + /* Return BLE_GAP_REPEAT_PAIRING_RETRY to indicate that the host should + * continue with the pairing operation. + */ + return BLE_GAP_REPEAT_PAIRING_RETRY; + } // BLE_GAP_EVENT_REPEAT_PAIRING + + case BLE_GAP_EVENT_ENC_CHANGE: + { + rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc); + if (rc != 0) { + return BLE_ATT_ERR_INVALID_HANDLE; + } + + if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onAuthenticationComplete(&desc); + } + + return 0; + } // BLE_GAP_EVENT_ENC_CHANGE + + case BLE_GAP_EVENT_PASSKEY_ACTION: + { + struct ble_sm_io pkey = {0, 0}; + + if (event->passkey.params.action == BLE_SM_IOACT_DISP) { + // Display the passkey on this device + log_d("BLE_SM_IOACT_DISP"); + + pkey.action = event->passkey.params.action; + pkey.passkey = BLESecurity::getPassKey(); + + if (!BLESecurity::m_passkeySet) { + log_w("No passkey set"); + } + + if (BLESecurity::m_staticPasskey && pkey.passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", pkey.passkey); + } + + if (BLEDevice::m_securityCallbacks != nullptr) { + BLEDevice::m_securityCallbacks->onPassKeyNotify(pkey.passkey); + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("BLE_SM_IOACT_DISP; ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_NUMCMP) { + // Check if the passkey on the peer device is correct + log_d("BLE_SM_IOACT_NUMCMP"); + + log_d("Passkey on device's display: %d", event->passkey.params.numcmp); + pkey.action = event->passkey.params.action; + + if (BLEDevice::m_securityCallbacks != nullptr) { + pkey.numcmp_accept = BLEDevice::m_securityCallbacks->onConfirmPIN(event->passkey.params.numcmp); + } else { + log_e("onConfirmPIN not implemented. Rejecting connection"); + pkey.numcmp_accept = 0; + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("BLE_SM_IOACT_NUMCMP; ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_OOB) { + // Out of band pairing + // TODO: Handle out of band pairing + log_w("BLE_SM_IOACT_OOB: Not implemented"); + + static uint8_t tem_oob[16] = {0}; + pkey.action = event->passkey.params.action; + for (int i = 0; i < 16; i++) { + pkey.oob[i] = tem_oob[i]; + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("BLE_SM_IOACT_OOB; ble_sm_inject_io result: %d", rc); + } else if (event->passkey.params.action == BLE_SM_IOACT_INPUT) { + // Input passkey from peer device + log_d("BLE_SM_IOACT_INPUT"); + + pkey.action = event->passkey.params.action; + pkey.passkey = BLESecurity::getPassKey(); + + if (!BLESecurity::m_passkeySet) { + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("No passkey set, getting passkey from onPassKeyRequest"); + pkey.passkey = BLEDevice::m_securityCallbacks->onPassKeyRequest(); + } else { + log_w("*ATTENTION* onPassKeyRequest not implemented and no static passkey set."); + } + } + + if (BLESecurity::m_staticPasskey && pkey.passkey == BLE_SM_DEFAULT_PASSKEY) { + log_w("*ATTENTION* Using default passkey: %06d", BLE_SM_DEFAULT_PASSKEY); + log_w("*ATTENTION* Please use a random passkey or set a different static passkey"); + } else { + log_i("Passkey: %d", pkey.passkey); + } + + rc = ble_sm_inject_io(event->passkey.conn_handle, &pkey); + log_d("BLE_SM_IOACT_INPUT; ble_sm_inject_io result: %d", rc); + + } else if (event->passkey.params.action == BLE_SM_IOACT_NONE) { + log_d("BLE_SM_IOACT_NONE"); + log_i("No passkey action required"); + } + + log_d("<< handleGATTServerEvent"); + return 0; + } // BLE_GAP_EVENT_PASSKEY_ACTION + + case BLE_GAP_EVENT_AUTHORIZE: + { + log_d("BLE_GAP_EVENT_AUTHORIZE"); + + log_i( + "Authorization request: conn_handle=%d attr_handle=%d is_read=%d", event->authorize.conn_handle, event->authorize.attr_handle, event->authorize.is_read + ); + + bool authorized = false; + + if (BLEDevice::m_securityCallbacks != nullptr) { + log_i("Asking for authorization from onAuthorizationRequest"); + authorized = + BLEDevice::m_securityCallbacks->onAuthorizationRequest(event->authorize.conn_handle, event->authorize.attr_handle, event->authorize.is_read); + } else { + log_w("onAuthorizationRequest not implemented. Rejecting authorization request"); + } + + if (authorized) { + log_i("Authorization granted"); + event->authorize.out_response = BLE_GAP_AUTHORIZE_ACCEPT; + } else { + log_i("Authorization rejected"); + event->authorize.out_response = BLE_GAP_AUTHORIZE_REJECT; + } + + return 0; + } // BLE_GAP_EVENT_AUTHORIZE + + default: break; + } + + log_d("<< handleGATTServerEvent"); + return 0; +} + +/** + * @brief Request an update to the connection parameters. + * + * As the BLE Peripheral (server), this device can request connection parameter + * changes from the central. However, the central (client) makes the final decision + * and may accept, reject, or negotiate different parameters. + * + * Can only be called after a connection has been established. + * + * @param [in] conn_handle The connection handle of the peer to send the request to. + * @param [in] minInterval The minimum connection interval in 1.25ms units (e.g., 80 = 100ms). + * @param [in] maxInterval The maximum connection interval in 1.25ms units (e.g., 800 = 1000ms). + * @param [in] latency Number of consecutive connection events the peripheral can skip (0-499). + * Higher values save power but increase response latency. + * @param [in] timeout The supervision timeout in 10ms units (e.g., 400 = 4000ms). + * Must be > (1 + latency) * maxInterval * 2. + * @return True on success, false on failure. + */ +bool BLEServer::requestConnParams(uint16_t conn_handle, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + ble_gap_upd_params params; + + params.latency = latency; + params.itvl_max = maxInterval; // max_int = 0x20*1.25ms = 40ms + params.itvl_min = minInterval; // min_int = 0x10*1.25ms = 20ms + params.supervision_timeout = timeout; // timeout = 400*10ms = 4000ms + params.min_ce_len = BLE_GAP_INITIAL_CONN_MIN_CE_LEN; // Minimum length of connection event in 0.625ms units + params.max_ce_len = BLE_GAP_INITIAL_CONN_MAX_CE_LEN; // Maximum length of connection event in 0.625ms units + + int rc = ble_gap_update_params(conn_handle, ¶ms); + if (rc != 0) { + log_e("Request params error: %d, %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + return true; +} // requestConnParams + +/** + * @brief Request an update to the connection parameters. + * @deprecated Use requestConnParams() instead. This method is kept for backward compatibility. + */ +void BLEServer::updateConnParams(uint16_t conn_handle, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) { + requestConnParams(conn_handle, minInterval, maxInterval, latency, timeout); +} // updateConnParams + +bool BLEServer::setIndicateWait(uint16_t conn_handle) { + for (auto i = 0; i < CONFIG_BT_NIMBLE_MAX_CONNECTIONS; i++) { + if (m_indWait[i] == conn_handle) { + return false; + } + } + + return true; +} + +void BLEServer::clearIndicateWait(uint16_t conn_handle) { + for (auto i = 0; i < CONFIG_BT_NIMBLE_MAX_CONNECTIONS; i++) { + if (m_indWait[i] == conn_handle) { + m_indWait[i] = BLE_HS_CONN_HANDLE_NONE; + return; + } + } +} + +/** + * @brief Disconnect the specified client with optional reason. + * @param [in] connId Connection Id of the client to disconnect. + * @param [in] reason code for disconnecting. + * @return NimBLE host return code. + */ +int BLEServer::disconnect(uint16_t connId, uint8_t reason) { + log_d(">> disconnect()"); + + int rc = ble_gap_terminate(connId, reason); + if (rc != 0) { + log_e("ble_gap_terminate failed: rc=%d %s", rc, BLEUtils::returnCodeToString(rc)); + } + + log_d("<< disconnect()"); + return rc; +} // disconnect + +/** + * @brief Set the service changed flag + */ +void BLEServer::serviceChanged() { + if (m_gattsStarted) { + m_svcChanged = true; + } +} // serviceChanged + +// NimBLE callbacks + +void BLEServerCallbacks::onConnect(BLEServer *pServer, struct ble_gap_conn_desc *desc) { + log_d("BLEServerCallbacks", ">> onConnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onConnect()"); +} // onConnect + +void BLEServerCallbacks::onDisconnect(BLEServer *pServer, struct ble_gap_conn_desc *desc) { + log_d("BLEServerCallbacks", ">> onDisconnect(): Default"); + log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str()); + log_d("BLEServerCallbacks", "<< onDisconnect()"); +} // onDisconnect + +void BLEServerCallbacks::onMtuChanged(BLEServer *pServer, ble_gap_conn_desc *desc, uint16_t mtu) { + log_d("BLEServerCallbacks", ">> onMtuChanged(): Default"); + log_d("BLEServerCallbacks", "Device: %s MTU: %d", BLEDevice::toString().c_str(), mtu); + log_d("BLEServerCallbacks", "<< onMtuChanged()"); +} // onMtuChanged + +void BLEServerCallbacks::onConnParamsUpdate(uint16_t conn_handle, uint16_t interval, uint16_t latency, uint16_t timeout, uint8_t status) { + log_d("BLEServerCallbacks", ">> onConnParamsUpdate(): Default"); + log_d( + "BLEServerCallbacks", "Conn Handle: %d, Interval: %d (%.2f ms), Latency: %d, Timeout: %d (%d ms), Status: %d", conn_handle, interval, interval * 1.25, + latency, timeout, timeout * 10, status + ); + log_d("BLEServerCallbacks", "<< onConnParamsUpdate()"); +} // onConnParamsUpdate + +#endif // CONFIG_NIMBLE_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEServer.h b/libraries/BLE/src/BLEServer.h new file mode 100644 index 0000000..654c664 --- /dev/null +++ b/libraries/BLE/src/BLEServer.h @@ -0,0 +1,297 @@ +/* + * BLEServer.h + * + * Created on: Apr 16, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLESERVER_H_ +#define COMPONENTS_CPP_UTILS_BLESERVER_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include +#include +#include "Arduino.h" +#include "BLEDevice.h" +#include "BLEConnInfo.h" +#include "BLEUUID.h" +#include "BLEAdvertising.h" +#include "BLECharacteristic.h" +#include "BLEService.h" +#include "BLESecurity.h" +#include "RTOS.h" +#include "BLEAddress.h" +#include "BLEUtils.h" +#include "BLEUtils.h" + +/***************************************************************************** + * Bluedroid includes * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/***************************************************************************** + * NimBLE includes and definitions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#define ESP_GATT_IF_NONE BLE_HS_CONN_HANDLE_NONE +#define NIMBLE_ATT_REMOVE_HIDE 1 +#define NIMBLE_ATT_REMOVE_DELETE 2 +#endif + +/***************************************************************************** + * Forward declarations * + *****************************************************************************/ + +class BLEServerCallbacks; +class BLEService; +class BLECharacteristic; +class BLEDevice; +class BLESecurity; +class BLEAdvertising; + +/** + * @brief A data structure that manages the %BLE services owned by a BLE server. + */ +class BLEServiceMap { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEService *getByHandle(uint16_t handle); + BLEService *getByUUID(const char *uuid); + BLEService *getByUUID(BLEUUID uuid, uint8_t inst_id = 0); + void setByHandle(uint16_t handle, BLEService *service); + void setByUUID(const char *uuid, BLEService *service); + void setByUUID(BLEUUID uuid, BLEService *service); + String toString(); + BLEService *getFirst(); + BLEService *getNext(); + void removeService(BLEService *service); + int getRegisteredServiceCount(); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + std::map m_handleMap; + std::map m_uuidMap; + std::map::iterator m_iterator; +}; + +/** + * @brief The model of a %BLE server. + */ +class BLEServer { +public: + /*************************************************************************** + * Common public properties * + ***************************************************************************/ + + uint16_t m_appId; + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + uint32_t getConnectedCount(); + BLEService *createService(const char *uuid); + BLEService *createService(BLEUUID uuid, uint32_t numHandles = 15, uint8_t inst_id = 0); + BLEAdvertising *getAdvertising(); + void setCallbacks(BLEServerCallbacks *pCallbacks); + void startAdvertising(); + void removeService(BLEService *service); + BLEService *getServiceByUUID(const char *uuid); + BLEService *getServiceByUUID(BLEUUID uuid); + void start(); + bool isStarted(); +#if !defined(CONFIG_BT_NIMBLE_EXT_ADV) || defined(CONFIG_BLUEDROID_ENABLED) + void advertiseOnDisconnect(bool enable); +#endif + + // Connection management functions + std::map getPeerDevices(bool client); + void addPeerDevice(void *peer, bool is_client, uint16_t conn_id); + bool removePeerDevice(uint16_t conn_id, bool client); + BLEServer *getServerByConnId(uint16_t conn_id); + void updatePeerMTU(uint16_t connId, uint16_t mtu); + uint16_t getPeerMTU(uint16_t conn_id); + uint16_t getConnId(); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + bool connect(BLEAddress address); + bool requestConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout); + [[deprecated("Use requestConnParams() instead.")]] + void updateConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout); + void disconnect(uint16_t connId); + + /** + * @brief Restore CCCD values for a bonded device from NVS. + * + * This should be called after a bonded device reconnects and authentication completes. + * It restores the notification/indication subscription state that was persisted + * when the client originally wrote to the CCCD descriptors. + * + * @param [in] peerAddress The address of the bonded peer device. + */ + void restoreCCCDValues(const BLEAddress &peerAddress); + + void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + uint16_t getHandle(); + bool requestConnParams(uint16_t conn_handle, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout); + [[deprecated("Use requestConnParams() instead.")]] + void updateConnParams(uint16_t conn_handle, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout); + int disconnect(uint16_t connId, uint8_t reason = BLE_ERR_REM_USER_CONN_TERM); +#endif + +private: + friend class BLEService; + friend class BLECharacteristic; + friend class BLEDevice; + friend class BLESecurity; + friend class BLEAdvertising; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + uint16_t m_connId; + uint32_t m_connectedCount; + bool m_gattsStarted; + std::map m_connectedServersMap; +#if !defined(CONFIG_BT_NIMBLE_EXT_ADV) || defined(CONFIG_BLUEDROID_ENABLED) + bool m_advertiseOnDisconnect; +#endif + FreeRTOS::Semaphore m_semaphoreRegisterAppEvt = FreeRTOS::Semaphore("RegisterAppEvt"); + FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt"); + FreeRTOS::Semaphore m_semaphoreOpenEvt = FreeRTOS::Semaphore("OpenEvt"); + BLEServiceMap m_serviceMap; + BLEServerCallbacks *m_pServerCallbacks = nullptr; + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + uint16_t m_gatts_if; + esp_ble_adv_data_t m_adv_data; +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + bool m_svcChanged; + uint16_t m_indWait[CONFIG_BT_NIMBLE_MAX_CONNECTIONS]; + std::vector m_notifyChrVec; + ble_hs_adv_fields m_adv_data; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + BLEServer(); + void createApp(uint16_t appId); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + uint16_t getGattsIf(); + void registerApp(uint16_t); + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE private declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void serviceChanged(); + void resetGATT(); + bool setIndicateWait(uint16_t conn_handle); + void clearIndicateWait(uint16_t conn_handle); + static int handleGATTServerEvent(struct ble_gap_event *event, void *arg); +#endif +}; // BLEServer + +/** + * @brief Callbacks associated with the operation of a %BLE server. + */ +class BLEServerCallbacks { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + virtual ~BLEServerCallbacks(){}; + virtual void onConnect(BLEServer *pServer); + virtual void onDisconnect(BLEServer *pServer); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + virtual void onConnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param); + virtual void onDisconnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param); + virtual void onMtuChanged(BLEServer *pServer, esp_ble_gatts_cb_param_t *param); + virtual void onConnParamsUpdate(esp_bd_addr_t remote_bda, uint16_t interval, uint16_t latency, uint16_t timeout, esp_bt_status_t status); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + virtual void onConnect(BLEServer *pServer, ble_gap_conn_desc *desc); + virtual void onDisconnect(BLEServer *pServer, ble_gap_conn_desc *desc); + virtual void onMtuChanged(BLEServer *pServer, ble_gap_conn_desc *desc, uint16_t mtu); + virtual void onConnParamsUpdate(uint16_t conn_handle, uint16_t interval, uint16_t latency, uint16_t timeout, uint8_t status); +#endif +}; // BLEServerCallbacks + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLESERVER_H_ */ diff --git a/libraries/BLE/src/BLEService.cpp b/libraries/BLE/src/BLEService.cpp new file mode 100644 index 0000000..438c9aa --- /dev/null +++ b/libraries/BLE/src/BLEService.cpp @@ -0,0 +1,652 @@ +/* + * BLEService.cpp + * + * Created on: Mar 25, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +// A service is identified by a UUID. A service is also the container for one or more characteristics. + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include +#include +#include +#include + +#include "BLEServer.h" +#include "BLEService.h" +#include "BLEUtils.h" +#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +/***************************************************************************** + * Bluedroid includes * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/***************************************************************************** + * Common definitions * + *****************************************************************************/ + +#define NULL_HANDLE (0xffff) + +/***************************************************************************** + * Common functions * + *****************************************************************************/ + +/** + * @brief Construct an instance of the BLEService + * @param [in] uuid The UUID of the service. + * @param [in] numHandles The maximum number of handles associated with the service. + */ +BLEService::BLEService(const char *uuid, uint16_t numHandles) : BLEService(BLEUUID(uuid), numHandles) {} + +/** + * @brief Construct an instance of the BLEService + * @param [in] uuid The UUID of the service. + * @param [in] numHandles The maximum number of handles associated with the service. + */ +BLEService::BLEService(BLEUUID uuid, uint16_t numHandles) { + m_uuid = uuid; + m_handle = NULL_HANDLE; + m_pServer = nullptr; + //m_serializeMutex.setName("BLEService"); + m_numHandles = numHandles; +#ifdef CONFIG_BLUEDROID_ENABLED + m_lastCreatedCharacteristic = nullptr; +#endif +#if defined(CONFIG_NIMBLE_ENABLED) + m_pSvcDef = nullptr; +#endif +} // BLEService + +BLEService::~BLEService() { +#if defined(CONFIG_NIMBLE_ENABLED) + if (m_pSvcDef != nullptr) { + if (m_pSvcDef->characteristics != nullptr) { + for (int i = 0; m_pSvcDef->characteristics[i].uuid != NULL; ++i) { + if (m_pSvcDef->characteristics[i].descriptors) { + delete (m_pSvcDef->characteristics[i].descriptors); + } + } + delete (m_pSvcDef->characteristics); + } + + delete (m_pSvcDef); + } +#endif +} + +/** + * @brief Create the service. + * Create the service. + * @param [in] gatts_if The handle of the GATT server interface. + * @return N/A. + */ + +void BLEService::executeCreate(BLEServer *pServer) { + log_v(">> executeCreate() - Creating service with uuid: %s", getUUID().toString().c_str()); + m_pServer = pServer; +#if defined(CONFIG_BLUEDROID_ENABLED) + m_semaphoreCreateEvt.take("executeCreate"); // Take the mutex and release at event ESP_GATTS_CREATE_EVT + + esp_gatt_srvc_id_t srvc_id; + srvc_id.is_primary = true; + srvc_id.id.inst_id = m_instId; + srvc_id.id.uuid = *m_uuid.getNative(); + esp_err_t errRc = + ::esp_ble_gatts_create_service(getServer()->getGattsIf(), &srvc_id, m_numHandles); // The maximum number of handles associated with the service. + + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_create_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return; + } + + m_semaphoreCreateEvt.wait("executeCreate"); +#endif + log_v("<< executeCreate"); +} // executeCreate + +/** + * @brief Delete the service. + * Delete the service. + * @return N/A. + */ + +void BLEService::executeDelete() { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_v(">> executeDelete()"); + m_semaphoreDeleteEvt.take("executeDelete"); // Take the mutex and release at event ESP_GATTS_DELETE_EVT + + esp_err_t errRc = ::esp_ble_gatts_delete_service(getHandle()); + + if (errRc != ESP_OK) { + log_e("esp_ble_gatts_delete_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return; + } + + m_semaphoreDeleteEvt.wait("executeDelete"); + log_v("<< executeDelete"); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) && CONFIG_BT_NIMBLE_DYNAMIC_SERVICE + ble_gatts_delete_svc(&m_uuid.getNative()->u); +#endif +} // executeDelete + +/** + * @brief Dump details of this BLE GATT service. + * @return N/A. + */ +void BLEService::dump() { + log_d("Service: uuid:%s, handle: 0x%.2x", m_uuid.toString().c_str(), m_handle); + log_d("Characteristics:\n%s", m_characteristicMap.toString().c_str()); +} // dump + +/** + * @brief Get the UUID of the service. + * @return the UUID of the service. + */ +BLEUUID BLEService::getUUID() { + return m_uuid; +} // getUUID + +/** + * @brief Stop the service. + */ +void BLEService::stop() { +#if defined(CONFIG_BLUEDROID_ENABLED) + // We ask the BLE runtime to start the service and then create each of the characteristics. + // We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event + // obtained as a result of calling esp_ble_gatts_create_service(). + log_v(">> stop(): Stopping service (esp_ble_gatts_stop_service): %s", toString().c_str()); + if (m_handle == NULL_HANDLE) { + log_e("<< !!! We attempted to stop a service but don't know its handle!"); + return; + } + + m_semaphoreStopEvt.take("stop"); + esp_err_t errRc = ::esp_ble_gatts_stop_service(m_handle); + + if (errRc != ESP_OK) { + log_e("<< esp_ble_gatts_stop_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return; + } + m_semaphoreStopEvt.wait("stop"); + + log_v("<< stop()"); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + log_w("NimBLE does not support stopping a service. Ignoring request."); +#endif +} // stop + +/** + * @brief Set the handle associated with this service. + * @param [in] handle The handle associated with the service. + */ +void BLEService::setHandle(uint16_t handle) { +#if defined(CONFIG_BLUEDROID_ENABLED) + log_v(">> setHandle - Handle=0x%.2x, service UUID=%s)", handle, getUUID().toString().c_str()); + if (m_handle != NULL_HANDLE) { + log_e("!!! Handle is already set %.2x", m_handle); + return; + } + m_handle = handle; + log_v("<< setHandle"); +#endif + +#if defined(CONFIG_NIMBLE_ENABLED) + log_w("NimBLE does not support manually setting the handle of a service. Ignoring request."); +#endif +} // setHandle + +/** + * @brief Get the handle associated with this service. + * @return The handle associated with this service. + */ +uint16_t BLEService::getHandle() { + return m_handle; +} // getHandle + +/** + * @brief Add a characteristic to the service. + * @param [in] pCharacteristic A pointer to the characteristic to be added. + */ +void BLEService::addCharacteristic(BLECharacteristic *pCharacteristic) { + // We maintain a mapping of characteristics owned by this service. These are managed by the + // BLECharacteristicMap class instance found in m_characteristicMap. We add the characteristic + // to the map and then ask the service to add the characteristic at the BLE level (ESP-IDF). + + log_v(">> addCharacteristic()"); + log_d("Adding characteristic: uuid=%s to service: %s", pCharacteristic->getUUID().toString().c_str(), toString().c_str()); + + // Check that we don't add the same characteristic twice. + BLECharacteristic *pExisting = m_characteristicMap.getByUUID(pCharacteristic->getUUID()); + if (pExisting != nullptr) { + log_w("<< Adding a new characteristic with the same UUID as a previous one"); + } + +#if defined(CONFIG_NIMBLE_ENABLED) + if (pExisting != nullptr) { + pExisting->m_removed = 0; + } else +#endif + { + // Remember this characteristic in our map of characteristics. At this point, we can lookup by UUID + // but not by handle. The handle is allocated to us on the ESP_GATTS_ADD_CHAR_EVT. + m_characteristicMap.setByUUID(pCharacteristic, pCharacteristic->getUUID()); + } + +#if defined(CONFIG_NIMBLE_ENABLED) + getServer()->serviceChanged(); +#endif + + log_v("<< addCharacteristic()"); +} // addCharacteristic + +/** + * @brief Create a new BLE Characteristic associated with this service. + * @param [in] uuid - The UUID of the characteristic. + * @param [in] properties - The properties of the characteristic. + * @return The new BLE characteristic. + */ +BLECharacteristic *BLEService::createCharacteristic(const char *uuid, uint32_t properties) { + return createCharacteristic(BLEUUID(uuid), properties); +} + +/** + * @brief Create a new BLE Characteristic associated with this service. + * @param [in] uuid - The UUID of the characteristic. + * @param [in] properties - The properties of the characteristic. + * @return The new BLE characteristic. + */ +BLECharacteristic *BLEService::createCharacteristic(BLEUUID uuid, uint32_t properties) { + BLECharacteristic *pCharacteristic = new BLECharacteristic(uuid, properties); + addCharacteristic(pCharacteristic); + return pCharacteristic; +} // createCharacteristic + +BLECharacteristic *BLEService::getCharacteristic(const char *uuid) { + return getCharacteristic(BLEUUID(uuid)); +} + +BLECharacteristic *BLEService::getCharacteristic(BLEUUID uuid) { + return m_characteristicMap.getByUUID(uuid); +} + +/** + * @brief Return a string representation of this service. + * A service is defined by: + * * Its UUID + * * Its handle + * @return A string representation of this service. + */ +String BLEService::toString() { + String res = "UUID: " + getUUID().toString(); + char hex[5]; + snprintf(hex, sizeof(hex), "%04x", getHandle()); + res += ", handle: 0x"; + res += hex; + return res; +} // toString + +/** + * @brief Get the BLE server associated with this service. + * @return The BLEServer associated with this service. + */ +BLEServer *BLEService::getServer() { + return m_pServer; +} // getServer + +/***************************************************************************** + * Bluedroid functions * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +/** + * @brief Get the last created characteristic. + * It is lamentable that this function has to exist. It returns the last created characteristic. + * We need this because the descriptor API is built around the notion that a new descriptor, when created, + * is associated with the last characteristics created and we need that information. + * @return The last created characteristic. + */ +BLECharacteristic *BLEService::getLastCreatedCharacteristic() { + return m_lastCreatedCharacteristic; +} // getLastCreatedCharacteristic + +/** + * @brief Handle a GATTS server event. + */ +void BLEService::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + switch (event) { + // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service. + // add_char: + // - esp_gatt_status_t status + // - uint16_t attr_handle + // - uint16_t service_handle + // - esp_bt_uuid_t char_uuid + + // If we have reached the correct service, then locate the characteristic and remember the handle + // for that characteristic. + case ESP_GATTS_ADD_CHAR_EVT: + { + if (m_handle == param->add_char.service_handle) { + BLECharacteristic *pCharacteristic = getLastCreatedCharacteristic(); + if (pCharacteristic == nullptr) { + log_e("Expected to find characteristic with UUID: %s, but didn't!", BLEUUID(param->add_char.char_uuid).toString().c_str()); + dump(); + break; + } + pCharacteristic->setHandle(param->add_char.attr_handle); + m_characteristicMap.setByHandle(param->add_char.attr_handle, pCharacteristic); + break; + } // Reached the correct service. + break; + } // ESP_GATTS_ADD_CHAR_EVT + + // ESP_GATTS_START_EVT + // + // start: + // esp_gatt_status_t status + // uint16_t service_handle + case ESP_GATTS_START_EVT: + { + if (param->start.service_handle == getHandle()) { + m_semaphoreStartEvt.give(); + } + break; + } // ESP_GATTS_START_EVT + + // ESP_GATTS_STOP_EVT + // + // stop: + // esp_gatt_status_t status + // uint16_t service_handle + // + case ESP_GATTS_STOP_EVT: + { + if (param->stop.service_handle == getHandle()) { + m_semaphoreStopEvt.give(); + } + break; + } // ESP_GATTS_STOP_EVT + + // ESP_GATTS_CREATE_EVT + // Called when a new service is registered as having been created. + // + // create: + // * esp_gatt_status_t status + // * uint16_t service_handle + // * esp_gatt_srvc_id_t service_id + // * - esp_gatt_id id + // * - esp_bt_uuid uuid + // * - uint8_t inst_id + // * - bool is_primary + // + case ESP_GATTS_CREATE_EVT: + { + if (getUUID().equals(BLEUUID(param->create.service_id.id.uuid)) && m_instId == param->create.service_id.id.inst_id) { + setHandle(param->create.service_handle); + m_semaphoreCreateEvt.give(); + } + break; + } // ESP_GATTS_CREATE_EVT + + // ESP_GATTS_DELETE_EVT + // Called when a service is deleted. + // + // delete: + // * esp_gatt_status_t status + // * uint16_t service_handle + // + case ESP_GATTS_DELETE_EVT: + { + if (param->del.service_handle == getHandle()) { + m_semaphoreDeleteEvt.give(); + } + break; + } // ESP_GATTS_DELETE_EVT + + default: break; + } // Switch + + // Invoke the GATTS handler in each of the associated characteristics. + m_characteristicMap.handleGATTServerEvent(event, gatts_if, param); +} // handleGATTServerEvent + +/** + * @brief Start the service. + * Here we wish to start the service which means that we will respond to partner requests about it. + * Starting a service also means that we can create the corresponding characteristics. + * @return Start the service. + */ + +bool BLEService::start() { + // We ask the BLE runtime to start the service and then create each of the characteristics. + // We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event + // obtained as a result of calling esp_ble_gatts_create_service(). + // + log_v(">> start(): Starting service (esp_ble_gatts_start_service): %s", toString().c_str()); + if (m_handle == NULL_HANDLE) { + log_e("<< !!! We attempted to start a service but don't know its handle!"); + return false; + } + + BLECharacteristic *pCharacteristic = m_characteristicMap.getFirst(); + + while (pCharacteristic != nullptr) { + m_lastCreatedCharacteristic = pCharacteristic; + pCharacteristic->executeCreate(this); + + pCharacteristic = m_characteristicMap.getNext(); + } + // Start each of the characteristics ... these are found in the m_characteristicMap. + + m_semaphoreStartEvt.take("start"); + esp_err_t errRc = ::esp_ble_gatts_start_service(m_handle); + + if (errRc != ESP_OK) { + log_e("<< esp_ble_gatts_start_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc)); + return false; + } + m_semaphoreStartEvt.wait("start"); + + log_v("<< start()"); + return true; +} // start + +#endif // CONFIG_BLUEDROID_ENABLED + +/***************************************************************************** + * NimBLE functions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +/** + * @brief Remove a characteristic from the service. Check if the characteristic was already removed and if so, check if this + * is being called to delete the object and do so if requested. Otherwise, ignore the call and return. + * @param [in] pCharacteristic - The characteristic to remove. + * @param [in] deleteChr - If true, delete the characteristic. + */ +void BLEService::removeCharacteristic(BLECharacteristic *pCharacteristic, bool deleteChr) { + if (pCharacteristic->m_removed > 0) { + if (deleteChr) { + BLECharacteristic *pExisting = m_characteristicMap.getByUUID(pCharacteristic->getUUID()); + if (pExisting != nullptr) { + m_characteristicMap.removeCharacteristic(pExisting); + delete pExisting; + } + } + + return; + } + + pCharacteristic->m_removed = deleteChr ? NIMBLE_ATT_REMOVE_DELETE : NIMBLE_ATT_REMOVE_HIDE; + getServer()->serviceChanged(); +} + +/** + * @brief Builds the database of characteristics/descriptors for the service + * and registers it with the NimBLE stack. + * @return bool success/failure . + */ +bool BLEService::start() { + log_d(">> start(): Starting service: %s", toString().c_str()); + + // Rebuild the service definition if the server attributes have changed. + if (getServer()->m_svcChanged && m_pSvcDef != nullptr) { + if (m_pSvcDef[0].characteristics) { + if (m_pSvcDef[0].characteristics[0].descriptors) { + delete (m_pSvcDef[0].characteristics[0].descriptors); + } + delete (m_pSvcDef[0].characteristics); + } + delete (m_pSvcDef); + m_pSvcDef = nullptr; + } + + if (m_pSvcDef == nullptr) { + // Nimble requires an array of services to be sent to the api + // Since we are adding 1 at a time we create an array of 2 and set the type + // of the second service to 0 to indicate the end of the array. + ble_gatt_svc_def *svc = new ble_gatt_svc_def[2]{}; + ble_gatt_chr_def *pChr_a = nullptr; + ble_gatt_dsc_def *pDsc_a = nullptr; + + svc[0].type = BLE_GATT_SVC_TYPE_PRIMARY; + svc[0].uuid = (const ble_uuid_t *)&(m_uuid.getNative()->u); + svc[0].includes = nullptr; + + int removedCount = 0; + BLECharacteristic *pCharacteristic; + + pCharacteristic = m_characteristicMap.getFirst(); + while (pCharacteristic != nullptr) { + if (pCharacteristic->m_removed > 0) { + if (pCharacteristic->m_removed == NIMBLE_ATT_REMOVE_DELETE) { + m_characteristicMap.removeCharacteristic(pCharacteristic); + delete pCharacteristic; + } else { + ++removedCount; + } + } else { + pCharacteristic->executeCreate(this); + } + + pCharacteristic = m_characteristicMap.getNext(); + } + + size_t numChrs = m_characteristicMap.getRegisteredCharacteristicCount() - removedCount; + log_d("Adding %d characteristics for service %s", numChrs, toString().c_str()); + + if (!numChrs) { + svc[0].characteristics = nullptr; + } else { + // Nimble requires the last characteristic to have it's uuid = 0 to indicate the end + // of the characteristics for the service. We create 1 extra and set it to null + // for this purpose. + pChr_a = new ble_gatt_chr_def[numChrs + 1]{}; + uint8_t i = 0; + pCharacteristic = m_characteristicMap.getFirst(); + while (pCharacteristic != nullptr) { + if (pCharacteristic->m_removed <= 0) { + removedCount = 0; + BLEDescriptor *pDescriptor; + + pDescriptor = pCharacteristic->m_descriptorMap.getFirst(); + while (pDescriptor != nullptr) { + if (pDescriptor->m_removed > 0) { + if (pDescriptor->m_removed == NIMBLE_ATT_REMOVE_DELETE) { + pCharacteristic->m_descriptorMap.removeDescriptor(pDescriptor); + delete pDescriptor; + } else { + ++removedCount; + } + } + pDescriptor = pCharacteristic->m_descriptorMap.getNext(); + } + + size_t numDscs = pCharacteristic->m_descriptorMap.getRegisteredDescriptorCount() - removedCount; + log_d("Adding %d descriptors for characteristic %s", numDscs, pCharacteristic->getUUID().toString().c_str()); + + if (!numDscs) { + pChr_a[i].descriptors = nullptr; + } else { + // Must have last descriptor uuid = 0 so we have to create 1 extra + pDsc_a = new ble_gatt_dsc_def[numDscs + 1]{}; + uint8_t d = 0; + pDescriptor = pCharacteristic->m_descriptorMap.getFirst(); + while (pDescriptor != nullptr) { + if (pDescriptor->m_removed <= 0) { + pDsc_a[d].uuid = (const ble_uuid_t *)&(pDescriptor->m_bleUUID.getNative()->u); + pDsc_a[d].att_flags = pDescriptor->m_permissions; + pDsc_a[d].min_key_size = 0; + pDsc_a[d].access_cb = BLEDescriptor::handleGATTServerEvent; + pDsc_a[d].arg = pDescriptor; + ++d; + } + pDescriptor = pCharacteristic->m_descriptorMap.getNext(); + } + + pDsc_a[numDscs].uuid = nullptr; + pChr_a[i].descriptors = pDsc_a; + } + + pChr_a[i].uuid = (const ble_uuid_t *)&(pCharacteristic->m_bleUUID.getNative()->u); + pChr_a[i].access_cb = BLECharacteristic::handleGATTServerEvent; + pChr_a[i].arg = pCharacteristic; + pChr_a[i].flags = pCharacteristic->m_properties; + pChr_a[i].min_key_size = 0; + pChr_a[i].val_handle = &pCharacteristic->m_handle; + ++i; + } + + pCharacteristic = m_characteristicMap.getNext(); + } + + pChr_a[numChrs].uuid = nullptr; + svc[0].characteristics = pChr_a; + } + + // end of services must indicate to api with type = 0 + svc[1].type = 0; + m_pSvcDef = svc; + } + + int rc = ble_gatts_count_cfg((const ble_gatt_svc_def *)m_pSvcDef); + if (rc != 0) { + log_e("ble_gatts_count_cfg failed, rc= %d, %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + + rc = ble_gatts_add_svcs((const ble_gatt_svc_def *)m_pSvcDef); + if (rc != 0) { + log_e("ble_gatts_add_svcs, rc= %d, %s", rc, BLEUtils::returnCodeToString(rc)); + return false; + } + + log_d("<< start()"); + return true; +} // start + +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEService.h b/libraries/BLE/src/BLEService.h new file mode 100644 index 0000000..a3d3f14 --- /dev/null +++ b/libraries/BLE/src/BLEService.h @@ -0,0 +1,202 @@ +/* + * BLEService.h + * + * Created on: Mar 25, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLESERVICE_H_ +#define COMPONENTS_CPP_UTILS_BLESERVICE_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include "BLECharacteristic.h" +#include "BLEServer.h" +#include "BLEUUID.h" +#include "BLEUtils.h" +#include "RTOS.h" + +/***************************************************************************** + * Bluedroid includes * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#endif + +/***************************************************************************** + * NimBLE includes * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#endif + +/***************************************************************************** + * Forward declarations * + *****************************************************************************/ + +class BLEServer; + +/** + * @brief A data mapping used to manage the set of %BLE characteristics known to the server. + */ +class BLECharacteristicMap { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + void setByUUID(BLECharacteristic *pCharacteristic, const char *uuid); + void setByUUID(BLECharacteristic *pCharacteristic, BLEUUID uuid); + void setByHandle(uint16_t handle, BLECharacteristic *pCharacteristic); + BLECharacteristic *getByUUID(const char *uuid) const; + BLECharacteristic *getByUUID(BLEUUID uuid) const; + BLECharacteristic *getByHandle(uint16_t handle) const; + BLECharacteristic *getFirst(); + BLECharacteristic *getNext(); + String toString() const; + int getRegisteredCharacteristicCount() const; + void removeCharacteristic(BLECharacteristic *characteristic); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void handleGATTServerEvent(uint16_t conn_handle, uint16_t attr_handle, ble_gatt_access_ctxt *ctxt, void *arg); +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + std::map m_uuidMap; + std::map m_handleMap; + std::map::iterator m_iterator; +}; + +/** + * @brief The model of a %BLE service. + */ +class BLEService { +public: + /*************************************************************************** + * Common properties * + ***************************************************************************/ + + uint8_t m_instId = 0; + + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + void addCharacteristic(BLECharacteristic *pCharacteristic); + BLECharacteristic *createCharacteristic(const char *uuid, uint32_t properties); + BLECharacteristic *createCharacteristic(BLEUUID uuid, uint32_t properties); + void dump(); + void executeCreate(BLEServer *pServer); + void executeDelete(); + BLECharacteristic *getCharacteristic(const char *uuid); + BLECharacteristic *getCharacteristic(BLEUUID uuid); + BLEUUID getUUID(); + BLEServer *getServer(); + bool start(); + void stop(); + String toString(); + uint16_t getHandle(); + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + void removeCharacteristic(BLECharacteristic *pCharacteristic, bool deleteChr = false); +#endif + +private: + friend class BLEServer; + friend class BLEServiceMap; + friend class BLEDescriptor; + friend class BLECharacteristic; + friend class BLEDevice; + + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + BLECharacteristicMap m_characteristicMap; + uint16_t m_handle; + BLECharacteristic *m_lastCreatedCharacteristic = nullptr; + BLEServer *m_pServer = nullptr; + BLEUUID m_uuid; + FreeRTOS::Semaphore m_semaphoreStartEvt = FreeRTOS::Semaphore("StartEvt"); + uint16_t m_numHandles; + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt"); + FreeRTOS::Semaphore m_semaphoreDeleteEvt = FreeRTOS::Semaphore("DeleteEvt"); + FreeRTOS::Semaphore m_semaphoreStopEvt = FreeRTOS::Semaphore("StopEvt"); +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + uint8_t m_removed; + ble_gatt_svc_def *m_pSvcDef; +#endif + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + BLEService(const char *uuid, uint16_t numHandles); + BLEService(BLEUUID uuid, uint16_t numHandles); + ~BLEService(); + + /*************************************************************************** + * Common private declarations * + ***************************************************************************/ + + void setHandle(uint16_t handle); + + /*************************************************************************** + * Bluedroid private declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + BLECharacteristic *getLastCreatedCharacteristic(); + void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +#endif +}; // BLEService + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLESERVICE_H_ */ diff --git a/libraries/BLE/src/BLEServiceMap.cpp b/libraries/BLE/src/BLEServiceMap.cpp new file mode 100644 index 0000000..ee58aa2 --- /dev/null +++ b/libraries/BLE/src/BLEServiceMap.cpp @@ -0,0 +1,156 @@ +/* + * BLEServiceMap.cpp + * + * Created on: Jun 22, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include +#include +#include "BLEService.h" + +/***************************************************************************** + * Common functions * + *****************************************************************************/ + +/** + * @brief Return the service by UUID. + * @param [in] UUID The UUID to look up the service. + * @return The characteristic. + */ +BLEService *BLEServiceMap::getByUUID(const char *uuid) { + return getByUUID(BLEUUID(uuid)); +} + +/** + * @brief Return the service by UUID. + * @param [in] UUID The UUID to look up the service. + * @return The characteristic. + */ +BLEService *BLEServiceMap::getByUUID(BLEUUID uuid, uint8_t inst_id) { + for (auto &myPair : m_uuidMap) { + if (myPair.first->getUUID().equals(uuid)) { + return myPair.first; + } + } + //return m_uuidMap.at(uuid.toString()); + return nullptr; +} // getByUUID + +/** + * @brief Return the service by handle. + * @param [in] handle The handle to look up the service. + * @return The service. + */ +BLEService *BLEServiceMap::getByHandle(uint16_t handle) { + return m_handleMap.at(handle); +} // getByHandle + +/** + * @brief Set the service by UUID. + * @param [in] uuid The uuid of the service. + * @param [in] characteristic The service to cache. + * @return N/A. + */ +void BLEServiceMap::setByUUID(BLEUUID uuid, BLEService *service) { + m_uuidMap.insert(std::pair(service, uuid.toString())); +} // setByUUID + +/** + * @brief Set the service by handle. + * @param [in] handle The handle of the service. + * @param [in] service The service to cache. + * @return N/A. + */ +void BLEServiceMap::setByHandle(uint16_t handle, BLEService *service) { + m_handleMap.insert(std::pair(handle, service)); +} // setByHandle + +/** + * @brief Return a string representation of the service map. + * @return A string representation of the service map. + */ +String BLEServiceMap::toString() { + String res; + char hex[5]; + for (auto &myPair : m_handleMap) { + res += "handle: 0x"; + snprintf(hex, sizeof(hex), "%04x", myPair.first); + res += hex; + res += ", uuid: " + myPair.second->getUUID().toString() + "\n"; + } + return res; +} // toString + +/** + * @brief Get the first service in the map. + * @return The first service in the map. + */ +BLEService *BLEServiceMap::getFirst() { + m_iterator = m_uuidMap.begin(); + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLEService *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getFirst + +/** + * @brief Get the next service in the map. + * @return The next service in the map. + */ +BLEService *BLEServiceMap::getNext() { + if (m_iterator == m_uuidMap.end()) { + return nullptr; + } + BLEService *pRet = m_iterator->first; + m_iterator++; + return pRet; +} // getNext + +/** + * @brief Removes service from maps. + * @return N/A. + */ +void BLEServiceMap::removeService(BLEService *service) { + m_handleMap.erase(service->getHandle()); + m_uuidMap.erase(service); +} // removeService + +/** + * @brief Returns the amount of registered services + * @return amount of registered services + */ +int BLEServiceMap::getRegisteredServiceCount() { + return m_uuidMap.size(); +} + +/***************************************************************************** + * Bluedroid functions * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +void BLEServiceMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) { + // Invoke the handler for every Service we have. + for (auto &myPair : m_uuidMap) { + myPair.first->handleGATTServerEvent(event, gatts_if, param); + } +} +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEUUID.cpp b/libraries/BLE/src/BLEUUID.cpp new file mode 100644 index 0000000..5dd3833 --- /dev/null +++ b/libraries/BLE/src/BLEUUID.cpp @@ -0,0 +1,335 @@ +/* + * BLEUUID.cpp + * + * Created on: Jun 21, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include "BLEUUID.h" +#include "esp32-hal-log.h" + +/***************************************************************************** + * Common functions * + *****************************************************************************/ + +static void memrcpy(uint8_t *target, uint8_t *source, uint32_t size) { + assert(size > 0); + target += (size - 1); // Point target to the last byte of the target data + while (size > 0) { + *target = *source; + target--; + source++; + size--; + } +} // memrcpy + +BLEUUID::BLEUUID() { + m_valueSet = false; +} // BLEUUID + +BLEUUID::BLEUUID(String value) { + m_valueSet = true; + if (value.length() == 4) { + UUID_LEN(m_uuid) = BLE_UUID_16_BITS; + UUID_VAL_16(m_uuid) = 0; + for (int i = 0; i < value.length();) { + uint8_t MSB = value.c_str()[i]; + uint8_t LSB = value.c_str()[i + 1]; + + if (MSB > '9') { + MSB -= 7; + } + if (LSB > '9') { + LSB -= 7; + } + UUID_VAL_16(m_uuid) += (((MSB & 0x0F) << 4) | (LSB & 0x0F)) << (2 - i) * 4; + i += 2; + } + } else if (value.length() == 8) { + UUID_LEN(m_uuid) = BLE_UUID_32_BITS; + UUID_VAL_32(m_uuid) = 0; + for (int i = 0; i < value.length();) { + uint8_t MSB = value.c_str()[i]; + uint8_t LSB = value.c_str()[i + 1]; + + if (MSB > '9') { + MSB -= 7; + } + if (LSB > '9') { + LSB -= 7; + } + UUID_VAL_32(m_uuid) += (((MSB & 0x0F) << 4) | (LSB & 0x0F)) << (6 - i) * 4; + i += 2; + } + } else if (value.length() == 16) { + UUID_LEN(m_uuid) = BLE_UUID_128_BITS; + memrcpy(UUID_VAL_128(m_uuid), (uint8_t *)value.c_str(), 16); + } else if (value.length() == 36) { + UUID_LEN(m_uuid) = BLE_UUID_128_BITS; + int n = 0; + for (int i = 0; i < value.length();) { + if (value.c_str()[i] == '-') { + i++; + } + uint8_t MSB = value.c_str()[i]; + uint8_t LSB = value.c_str()[i + 1]; + + if (MSB > '9') { + MSB -= 7; + } + if (LSB > '9') { + LSB -= 7; + } + UUID_VAL_128(m_uuid)[15 - n++] = ((MSB & 0x0F) << 4) | (LSB & 0x0F); + i += 2; + } + } else { + log_e("ERROR: UUID value not 2, 4, 16 or 36 bytes"); + m_valueSet = false; + } +} //BLEUUID(String) + +BLEUUID::BLEUUID(uint8_t *pData, size_t size, bool msbFirst) { + if (size != 16) { + log_e("ERROR: UUID length not 16 bytes"); + return; + } + UUID_LEN(m_uuid) = BLE_UUID_128_BITS; + if (msbFirst) { + memrcpy(UUID_VAL_128(m_uuid), pData, 16); + } else { + memcpy(UUID_VAL_128(m_uuid), pData, 16); + } + m_valueSet = true; +} // BLEUUID + +BLEUUID::BLEUUID(uint16_t uuid) { + UUID_LEN(m_uuid) = BLE_UUID_16_BITS; + UUID_VAL_16(m_uuid) = uuid; + m_valueSet = true; +} // BLEUUID + +BLEUUID::BLEUUID(uint32_t uuid) { + UUID_LEN(m_uuid) = BLE_UUID_32_BITS; + UUID_VAL_32(m_uuid) = uuid; + m_valueSet = true; +} // BLEUUID + +BLEUUID::BLEUUID(uint32_t first, uint16_t second, uint16_t third, uint64_t fourth) { + UUID_LEN(m_uuid) = BLE_UUID_128_BITS; + memcpy(UUID_VAL_128(m_uuid) + 12, &first, 4); + memcpy(UUID_VAL_128(m_uuid) + 10, &second, 2); + memcpy(UUID_VAL_128(m_uuid) + 8, &third, 2); + memcpy(UUID_VAL_128(m_uuid), &fourth, 8); + m_valueSet = true; +} + +uint8_t BLEUUID::bitSize() { + if (!m_valueSet) { + return 0; + } + switch (UUID_LEN(m_uuid)) { + case BLE_UUID_16_BITS: return 16; + case BLE_UUID_32_BITS: return 32; + case BLE_UUID_128_BITS: return 128; + default: log_e("Unknown UUID length: %d", UUID_LEN(m_uuid)); return 0; + } // End of switch +} // bitSize + +bool BLEUUID::equals(const BLEUUID &uuid) const { + if (!m_valueSet || !uuid.m_valueSet) { + return false; + } + + if (UUID_LEN(uuid.m_uuid) != UUID_LEN(m_uuid)) { + return uuid.toString() == toString(); + } + + if (UUID_LEN(uuid.m_uuid) == BLE_UUID_16_BITS) { + return UUID_VAL_16(uuid.m_uuid) == UUID_VAL_16(m_uuid); + } + + if (UUID_LEN(uuid.m_uuid) == BLE_UUID_32_BITS) { + return UUID_VAL_32(uuid.m_uuid) == UUID_VAL_32(m_uuid); + } + + return memcmp(UUID_VAL_128(uuid.m_uuid), UUID_VAL_128(m_uuid), 16) == 0; +} // equals + +BLEUUID BLEUUID::fromString(String _uuid) { + uint8_t start = 0; + if (strstr(_uuid.c_str(), "0x") != nullptr) { // If the string starts with 0x, skip those characters. + start = 2; + } + uint8_t len = _uuid.length() - start; // Calculate the length of the string we are going to use. + + if (len == 4) { + uint16_t x = strtoul(_uuid.substring(start, start + len).c_str(), NULL, 16); + return BLEUUID(x); + } else if (len == 8) { + uint32_t x = strtoul(_uuid.substring(start, start + len).c_str(), NULL, 16); + return BLEUUID(x); + } else if (len == 36) { + return BLEUUID(_uuid); + } + return BLEUUID(); +} // fromString + +BLEUUID BLEUUID::to128() { + if (!m_valueSet || UUID_LEN(m_uuid) == BLE_UUID_128_BITS) { + return *this; + } + + if (UUID_LEN(m_uuid) == BLE_UUID_16_BITS) { + uint16_t temp = UUID_VAL_16(m_uuid); + UUID_VAL_128(m_uuid)[15] = 0; + UUID_VAL_128(m_uuid)[14] = 0; + UUID_VAL_128(m_uuid)[13] = (temp >> 8) & 0xff; + UUID_VAL_128(m_uuid)[12] = temp & 0xff; + } else if (UUID_LEN(m_uuid) == BLE_UUID_32_BITS) { + uint16_t temp = UUID_VAL_32(m_uuid); + UUID_VAL_128(m_uuid)[15] = (temp >> 24) & 0xff; + UUID_VAL_128(m_uuid)[14] = (temp >> 16) & 0xff; + UUID_VAL_128(m_uuid)[13] = (temp >> 8) & 0xff; + UUID_VAL_128(m_uuid)[12] = temp & 0xff; + } + + UUID_VAL_128(m_uuid)[11] = 0x00; + UUID_VAL_128(m_uuid)[10] = 0x00; + UUID_VAL_128(m_uuid)[9] = 0x10; + UUID_VAL_128(m_uuid)[8] = 0x00; + UUID_VAL_128(m_uuid)[7] = 0x80; + UUID_VAL_128(m_uuid)[6] = 0x00; + UUID_VAL_128(m_uuid)[5] = 0x00; + UUID_VAL_128(m_uuid)[4] = 0x80; + UUID_VAL_128(m_uuid)[3] = 0x5f; + UUID_VAL_128(m_uuid)[2] = 0x9b; + UUID_VAL_128(m_uuid)[1] = 0x34; + UUID_VAL_128(m_uuid)[0] = 0xfb; + + UUID_LEN(m_uuid) = BLE_UUID_128_BITS; + return *this; +} // to128 + +BLEUUID BLEUUID::to16() { + if (!m_valueSet || UUID_LEN(m_uuid) == BLE_UUID_16_BITS) { + return *this; + } + + if (UUID_LEN(m_uuid) == BLE_UUID_128_BITS) { + uint8_t base128[] = {0xfb, 0x34, 0x9b, 0x5f, 0x80, 0x00, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00}; + if (memcmp(UUID_VAL_128(m_uuid), base128, sizeof(base128)) == 0) { + *this = BLEUUID(*(uint16_t *)(UUID_VAL_128(m_uuid) + 12)); + } + } + + return *this; +} + +String BLEUUID::toString() const { + if (!m_valueSet) { + return ""; // If we have no value, nothing to format. + } + + if (UUID_LEN(m_uuid) == BLE_UUID_16_BITS) { // If the UUID is 16bit, pad correctly. + char hex[9]; + snprintf(hex, sizeof(hex), "%08x", UUID_VAL_16(m_uuid)); + return String(hex) + "-0000-1000-8000-00805f9b34fb"; + } // End 16bit UUID + + if (UUID_LEN(m_uuid) == BLE_UUID_32_BITS) { // If the UUID is 32bit, pad correctly. + char hex[9]; + snprintf(hex, sizeof(hex), "%08lx", UUID_VAL_32(m_uuid)); + return String(hex) + "-0000-1000-8000-00805f9b34fb"; + } // End 32bit UUID + + // The UUID is not 16bit or 32bit which means that it is 128bit. + auto size = 37; // 32 for UUID data, 4 for '-' delimiters and one for a terminator == 37 chars + char *hex = (char *)malloc(size); + snprintf( + hex, size, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", UUID_VAL_128(m_uuid)[15], UUID_VAL_128(m_uuid)[14], + UUID_VAL_128(m_uuid)[13], UUID_VAL_128(m_uuid)[12], UUID_VAL_128(m_uuid)[11], UUID_VAL_128(m_uuid)[10], UUID_VAL_128(m_uuid)[9], UUID_VAL_128(m_uuid)[8], + UUID_VAL_128(m_uuid)[7], UUID_VAL_128(m_uuid)[6], UUID_VAL_128(m_uuid)[5], UUID_VAL_128(m_uuid)[4], UUID_VAL_128(m_uuid)[3], UUID_VAL_128(m_uuid)[2], + UUID_VAL_128(m_uuid)[1], UUID_VAL_128(m_uuid)[0] + ); + + String res(hex); + free(hex); + return res; +} // toString + +bool BLEUUID::operator==(const BLEUUID &rhs) const { + return equals(rhs); +} + +bool BLEUUID::operator!=(const BLEUUID &rhs) const { + return !equals(rhs); +} + +/***************************************************************************** + * Bluedroid functions * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +BLEUUID::BLEUUID(esp_bt_uuid_t uuid) { + m_uuid = uuid; + m_valueSet = true; +} // BLEUUID + +BLEUUID::BLEUUID(esp_gatt_id_t gattId) : BLEUUID(gattId.uuid) {} // BLEUUID + +esp_bt_uuid_t *BLEUUID::getNative() { + if (m_valueSet == false) { + log_v("<< Return of un-initialized UUID!"); + return nullptr; + } + return &m_uuid; +} // getNative +#endif + +/***************************************************************************** + * NimBLE functions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +BLEUUID::BLEUUID(ble_uuid_any_t uuid) { + m_uuid = uuid; + m_valueSet = true; +} // BLEUUID + +BLEUUID::BLEUUID(const ble_uuid128_t *uuid) { + m_uuid.u.type = BLE_UUID_TYPE_128; + memcpy(m_uuid.u128.value, uuid->value, 16); + m_valueSet = true; +} // BLEUUID + +const ble_uuid_any_t *BLEUUID::getNative() const { + if (m_valueSet == false) { + log_v("<< Return of un-initialized UUID!"); + return nullptr; + } + return &m_uuid; +} // getNative +#endif + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEUUID.h b/libraries/BLE/src/BLEUUID.h new file mode 100644 index 0000000..da7c389 --- /dev/null +++ b/libraries/BLE/src/BLEUUID.h @@ -0,0 +1,128 @@ +/* + * BLEUUID.h + * + * Created on: Jun 21, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEUUID_H_ +#define COMPONENTS_CPP_UTILS_BLEUUID_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include "WString.h" + +/***************************************************************************** + * Bluedroid includes and definitions * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#define BLE_UUID_16_BITS ESP_UUID_LEN_16 +#define BLE_UUID_32_BITS ESP_UUID_LEN_32 +#define BLE_UUID_128_BITS ESP_UUID_LEN_128 +#define UUID_LEN(s) s.len +#define UUID_VAL_16(s) s.uuid.uuid16 +#define UUID_VAL_32(s) s.uuid.uuid32 +#define UUID_VAL_128(s) s.uuid.uuid128 +#endif + +/***************************************************************************** + * NimBLE includes and definitions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#define BLE_UUID_16_BITS BLE_UUID_TYPE_16 +#define BLE_UUID_32_BITS BLE_UUID_TYPE_32 +#define BLE_UUID_128_BITS BLE_UUID_TYPE_128 +#define UUID_LEN(s) s.u.type +#define UUID_VAL_16(s) s.u16.value +#define UUID_VAL_32(s) s.u32.value +#define UUID_VAL_128(s) s.u128.value +#endif + +/** + * @brief A model of a %BLE UUID. + */ +class BLEUUID { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEUUID(String uuid); + BLEUUID(uint16_t uuid); + BLEUUID(uint32_t uuid); + BLEUUID(uint8_t *pData, size_t size, bool msbFirst); + BLEUUID(uint32_t first, uint16_t second, uint16_t third, uint64_t fourth); + BLEUUID(); + uint8_t bitSize(); // Get the number of bits in this uuid. + bool equals(const BLEUUID &uuid) const; + BLEUUID to128(); + BLEUUID to16(); + String toString() const; + static BLEUUID fromString(String uuid); // Create a BLEUUID from a string + + bool operator==(const BLEUUID &rhs) const; + bool operator!=(const BLEUUID &rhs) const; + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + BLEUUID(esp_bt_uuid_t uuid); + BLEUUID(esp_gatt_id_t gattId); + esp_bt_uuid_t *getNative(); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + BLEUUID(ble_uuid_any_t uuid); + BLEUUID(const ble_uuid128_t *uuid); + const ble_uuid_any_t *getNative() const; +#endif + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + bool m_valueSet = false; // Is there a value set for this instance. + + /*************************************************************************** + * Bluedroid private properties * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + esp_bt_uuid_t m_uuid; // The underlying UUID structure that this class wraps. +#endif + + /*************************************************************************** + * NimBLE private properties * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + ble_uuid_any_t m_uuid; // The underlying UUID structure that this class wraps. +#endif +}; // BLEUUID + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEUUID_H_ */ diff --git a/libraries/BLE/src/BLEUtils.cpp b/libraries/BLE/src/BLEUtils.cpp new file mode 100644 index 0000000..f4b3ac6 --- /dev/null +++ b/libraries/BLE/src/BLEUtils.cpp @@ -0,0 +1,2260 @@ +/* + * BLEUtils.cpp + * + * Created on: Mar 25, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include "BLEAddress.h" +#include "BLEClient.h" +#include "BLEUtils.h" +#include "BLEUUID.h" +#include "GeneralUtils.h" + +#include +#include +#if SOC_BLE_SUPPORTED +#include +#endif + +#include +#include +#include +#include + +#include "esp32-hal-log.h" + +/***************************************************************************** + * Bluedroid includes * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#include +#endif + +/***************************************************************************** + * NimBLE includes and definitions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#include +#include +#include +#include + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG +#define CONFIG_NIMBLE_ENABLE_RETURN_CODE_TEXT +#define CONFIG_NIMBLE_ENABLE_ADVERTISMENT_TYPE_TEXT +#define CONFIG_NIMBLE_ENABLE_GAP_EVENT_CODE_TEXT +#endif + +#ifndef CONFIG_NIMBLE_FREERTOS_TASK_BLOCK_BIT +#define CONFIG_NIMBLE_FREERTOS_TASK_BLOCK_BIT 31 +#endif + +constexpr uint32_t TASK_BLOCK_BIT = (1 << CONFIG_NIMBLE_FREERTOS_TASK_BLOCK_BIT); +#endif + +/***************************************************************************** + * Bluedroid types and constants * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +typedef struct { + uint32_t assignedNumber; + const char *name; +} member_t; + +static const member_t members_ids[] = { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + {0xFE08, "Microsoft"}, + {0xFE09, "Pillsy, Inc."}, + {0xFE0A, "ruwido austria gmbh"}, + {0xFE0B, "ruwido austria gmbh"}, + {0xFE0C, "Procter & Gamble"}, + {0xFE0D, "Procter & Gamble"}, + {0xFE0E, "Setec Pty Ltd"}, + {0xFE0F, "Philips Lighting B.V."}, + {0xFE10, "Lapis Semiconductor Co., Ltd."}, + {0xFE11, "GMC-I Messtechnik GmbH"}, + {0xFE12, "M-Way Solutions GmbH"}, + {0xFE13, "Apple Inc."}, + {0xFE14, "Flextronics International USA Inc."}, + {0xFE15, "Amazon Fulfillment Services, Inc."}, + {0xFE16, "Footmarks, Inc."}, + {0xFE17, "Telit Wireless Solutions GmbH"}, + {0xFE18, "Runtime, Inc."}, + {0xFE19, "Google Inc."}, + {0xFE1A, "Tyto Life LLC"}, + {0xFE1B, "Tyto Life LLC"}, + {0xFE1C, "NetMedia, Inc."}, + {0xFE1D, "Illuminati Instrument Corporation"}, + {0xFE1E, "Smart Innovations Co., Ltd"}, + {0xFE1F, "Garmin International, Inc."}, + {0xFE20, "Emerson"}, + {0xFE21, "Bose Corporation"}, + {0xFE22, "Zoll Medical Corporation"}, + {0xFE23, "Zoll Medical Corporation"}, + {0xFE24, "August Home Inc"}, + {0xFE25, "Apple, Inc. "}, + {0xFE26, "Google Inc."}, + {0xFE27, "Google Inc."}, + {0xFE28, "Ayla Networks"}, + {0xFE29, "Gibson Innovations"}, + {0xFE2A, "DaisyWorks, Inc."}, + {0xFE2B, "ITT Industries"}, + {0xFE2C, "Google Inc."}, + {0xFE2D, "SMART INNOVATION Co.,Ltd"}, + {0xFE2E, "ERi,Inc."}, + {0xFE2F, "CRESCO Wireless, Inc"}, + {0xFE30, "Volkswagen AG"}, + {0xFE31, "Volkswagen AG"}, + {0xFE32, "Pro-Mark, Inc."}, + {0xFE33, "CHIPOLO d.o.o."}, + {0xFE34, "SmallLoop LLC"}, + {0xFE35, "HUAWEI Technologies Co., Ltd"}, + {0xFE36, "HUAWEI Technologies Co., Ltd"}, + {0xFE37, "Spaceek LTD"}, + {0xFE38, "Spaceek LTD"}, + {0xFE39, "TTS Tooltechnic Systems AG & Co. KG"}, + {0xFE3A, "TTS Tooltechnic Systems AG & Co. KG"}, + {0xFE3B, "Dolby Laboratories"}, + {0xFE3C, "Alibaba"}, + {0xFE3D, "BD Medical"}, + {0xFE3E, "BD Medical"}, + {0xFE3F, "Friday Labs Limited"}, + {0xFE40, "Inugo Systems Limited"}, + {0xFE41, "Inugo Systems Limited"}, + {0xFE42, "Nets A/S "}, + {0xFE43, "Andreas Stihl AG & Co. KG"}, + {0xFE44, "SK Telecom "}, + {0xFE45, "Snapchat Inc"}, + {0xFE46, "B&O Play A/S "}, + {0xFE47, "General Motors"}, + {0xFE48, "General Motors"}, + {0xFE49, "SenionLab AB"}, + {0xFE4A, "OMRON HEALTHCARE Co., Ltd."}, + {0xFE4B, "Philips Lighting B.V."}, + {0xFE4C, "Volkswagen AG"}, + {0xFE4D, "Casambi Technologies Oy"}, + {0xFE4E, "NTT docomo"}, + {0xFE4F, "Molekule, Inc."}, + {0xFE50, "Google Inc."}, + {0xFE51, "SRAM"}, + {0xFE52, "SetPoint Medical"}, + {0xFE53, "3M"}, + {0xFE54, "Motiv, Inc."}, + {0xFE55, "Google Inc."}, + {0xFE56, "Google Inc."}, + {0xFE57, "Dotted Labs"}, + {0xFE58, "Nordic Semiconductor ASA"}, + {0xFE59, "Nordic Semiconductor ASA"}, + {0xFE5A, "Chronologics Corporation"}, + {0xFE5B, "GT-tronics HK Ltd"}, + {0xFE5C, "million hunters GmbH"}, + {0xFE5D, "Grundfos A/S"}, + {0xFE5E, "Plastc Corporation"}, + {0xFE5F, "Eyefi, Inc."}, + {0xFE60, "Lierda Science & Technology Group Co., Ltd."}, + {0xFE61, "Logitech International SA"}, + {0xFE62, "Indagem Tech LLC"}, + {0xFE63, "Connected Yard, Inc."}, + {0xFE64, "Siemens AG"}, + {0xFE65, "CHIPOLO d.o.o."}, + {0xFE66, "Intel Corporation"}, + {0xFE67, "Lab Sensor Solutions"}, + {0xFE68, "Qualcomm Life Inc"}, + {0xFE69, "Qualcomm Life Inc"}, + {0xFE6A, "Kontakt Micro-Location Sp. z o.o."}, + {0xFE6B, "TASER International, Inc."}, + {0xFE6C, "TASER International, Inc."}, + {0xFE6D, "The University of Tokyo"}, + {0xFE6E, "The University of Tokyo"}, + {0xFE6F, "LINE Corporation"}, + {0xFE70, "Beijing Jingdong Century Trading Co., Ltd."}, + {0xFE71, "Plume Design Inc"}, + {0xFE72, "St. Jude Medical, Inc."}, + {0xFE73, "St. Jude Medical, Inc."}, + {0xFE74, "unwire"}, + {0xFE75, "TangoMe"}, + {0xFE76, "TangoMe"}, + {0xFE77, "Hewlett-Packard Company"}, + {0xFE78, "Hewlett-Packard Company"}, + {0xFE79, "Zebra Technologies"}, + {0xFE7A, "Bragi GmbH"}, + {0xFE7B, "Orion Labs, Inc."}, + {0xFE7C, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"}, + {0xFE7D, "Aterica Health Inc."}, + {0xFE7E, "Awear Solutions Ltd"}, + {0xFE7F, "Doppler Lab"}, + {0xFE80, "Doppler Lab"}, + {0xFE81, "Medtronic Inc."}, + {0xFE82, "Medtronic Inc."}, + {0xFE83, "Blue Bite"}, + {0xFE84, "RF Digital Corp"}, + {0xFE85, "RF Digital Corp"}, + {0xFE86, "HUAWEI Technologies Co., Ltd. ( )"}, + {0xFE87, "Qingdao Yeelink Information Technology Co., Ltd. ( )"}, + {0xFE88, "SALTO SYSTEMS S.L."}, + {0xFE89, "B&O Play A/S"}, + {0xFE8A, "Apple, Inc."}, + {0xFE8B, "Apple, Inc."}, + {0xFE8C, "TRON Forum"}, + {0xFE8D, "Interaxon Inc."}, + {0xFE8E, "ARM Ltd"}, + {0xFE8F, "CSR"}, + {0xFE90, "JUMA"}, + {0xFE91, "Shanghai Imilab Technology Co.,Ltd"}, + {0xFE92, "Jarden Safety & Security"}, + {0xFE93, "OttoQ Inc."}, + {0xFE94, "OttoQ Inc."}, + {0xFE95, "Xiaomi Inc."}, + {0xFE96, "Tesla Motor Inc."}, + {0xFE97, "Tesla Motor Inc."}, + {0xFE98, "Currant, Inc."}, + {0xFE99, "Currant, Inc."}, + {0xFE9A, "Estimote"}, + {0xFE9B, "Samsara Networks, Inc"}, + {0xFE9C, "GSI Laboratories, Inc."}, + {0xFE9D, "Mobiquity Networks Inc"}, + {0xFE9E, "Dialog Semiconductor B.V."}, + {0xFE9F, "Google Inc."}, + {0xFEA0, "Google Inc."}, + {0xFEA1, "Intrepid Control Systems, Inc."}, + {0xFEA2, "Intrepid Control Systems, Inc."}, + {0xFEA3, "ITT Industries"}, + {0xFEA4, "Paxton Access Ltd"}, + {0xFEA5, "GoPro, Inc."}, + {0xFEA6, "GoPro, Inc."}, + {0xFEA7, "UTC Fire and Security"}, + {0xFEA8, "Savant Systems LLC"}, + {0xFEA9, "Savant Systems LLC"}, + {0xFEAA, "Google Inc."}, + {0xFEAB, "Nokia Corporation"}, + {0xFEAC, "Nokia Corporation"}, + {0xFEAD, "Nokia Corporation"}, + {0xFEAE, "Nokia Corporation"}, + {0xFEAF, "Nest Labs Inc."}, + {0xFEB0, "Nest Labs Inc."}, + {0xFEB1, "Electronics Tomorrow Limited"}, + {0xFEB2, "Microsoft Corporation"}, + {0xFEB3, "Taobao"}, + {0xFEB4, "WiSilica Inc."}, + {0xFEB5, "WiSilica Inc."}, + {0xFEB6, "Vencer Co, Ltd"}, + {0xFEB7, "Facebook, Inc."}, + {0xFEB8, "Facebook, Inc."}, + {0xFEB9, "LG Electronics"}, + {0xFEBA, "Tencent Holdings Limited"}, + {0xFEBB, "adafruit industries"}, + {0xFEBC, "Dexcom, Inc. "}, + {0xFEBD, "Clover Network, Inc."}, + {0xFEBE, "Bose Corporation"}, + {0xFEBF, "Nod, Inc."}, + {0xFEC0, "KDDI Corporation"}, + {0xFEC1, "KDDI Corporation"}, + {0xFEC2, "Blue Spark Technologies, Inc."}, + {0xFEC3, "360fly, Inc."}, + {0xFEC4, "PLUS Location Systems"}, + {0xFEC5, "Realtek Semiconductor Corp."}, + {0xFEC6, "Kocomojo, LLC"}, + {0xFEC7, "Apple, Inc."}, + {0xFEC8, "Apple, Inc."}, + {0xFEC9, "Apple, Inc."}, + {0xFECA, "Apple, Inc."}, + {0xFECB, "Apple, Inc."}, + {0xFECC, "Apple, Inc."}, + {0xFECD, "Apple, Inc."}, + {0xFECE, "Apple, Inc."}, + {0xFECF, "Apple, Inc."}, + {0xFED0, "Apple, Inc."}, + {0xFED1, "Apple, Inc."}, + {0xFED2, "Apple, Inc."}, + {0xFED3, "Apple, Inc."}, + {0xFED4, "Apple, Inc."}, + {0xFED5, "Plantronics Inc."}, + {0xFED6, "Broadcom Corporation"}, + {0xFED7, "Broadcom Corporation"}, + {0xFED8, "Google Inc."}, + {0xFED9, "Pebble Technology Corporation"}, + {0xFEDA, "ISSC Technologies Corporation"}, + {0xFEDB, "Perka, Inc."}, + {0xFEDC, "Jawbone"}, + {0xFEDD, "Jawbone"}, + {0xFEDE, "Coin, Inc."}, + {0xFEDF, "Design SHIFT"}, + {0xFEE0, "Anhui Huami Information Technology Co."}, + {0xFEE1, "Anhui Huami Information Technology Co."}, + {0xFEE2, "Anki, Inc."}, + {0xFEE3, "Anki, Inc."}, + {0xFEE4, "Nordic Semiconductor ASA"}, + {0xFEE5, "Nordic Semiconductor ASA"}, + {0xFEE6, "Silvair, Inc."}, + {0xFEE7, "Tencent Holdings Limited"}, + {0xFEE8, "Quintic Corp."}, + {0xFEE9, "Quintic Corp."}, + {0xFEEA, "Swirl Networks, Inc."}, + {0xFEEB, "Swirl Networks, Inc."}, + {0xFEEC, "Tile, Inc."}, + {0xFEED, "Tile, Inc."}, + {0xFEEE, "Polar Electro Oy"}, + {0xFEEF, "Polar Electro Oy"}, + {0xFEF0, "Intel"}, + {0xFEF1, "CSR"}, + {0xFEF2, "CSR"}, + {0xFEF3, "Google Inc."}, + {0xFEF4, "Google Inc."}, + {0xFEF5, "Dialog Semiconductor GmbH"}, + {0xFEF6, "Wicentric, Inc."}, + {0xFEF7, "Aplix Corporation"}, + {0xFEF8, "Aplix Corporation"}, + {0xFEF9, "PayPal, Inc."}, + {0xFEFA, "PayPal, Inc."}, + {0xFEFB, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"}, + {0xFEFC, "Gimbal, Inc."}, + {0xFEFD, "Gimbal, Inc."}, + {0xFEFE, "GN ReSound A/S"}, + {0xFEFF, "GN Netcom"}, + {0xFFFF, "Reserved"}, /*for testing purposes only*/ +#endif + {0, ""} +}; + +typedef struct { + uint32_t assignedNumber; + const char *name; +} gattdescriptor_t; + +static const gattdescriptor_t g_descriptor_ids[] = { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + {0x2905, "Characteristic Aggregate Format"}, + {0x2900, "Characteristic Extended Properties"}, + {0x2904, "Characteristic Presentation Format"}, + {0x2901, "Characteristic User Description"}, + {0x2902, "Client Characteristic Configuration"}, + {0x290B, "Environmental Sensing Configuration"}, + {0x290C, "Environmental Sensing Measurement"}, + {0x290D, "Environmental Sensing Trigger Setting"}, + {0x2907, "External Report Reference"}, + {0x2909, "Number of Digitals"}, + {0x2908, "Report Reference"}, + {0x2903, "Server Characteristic Configuration"}, + {0x290E, "Time Trigger Setting"}, + {0x2906, "Valid Range"}, + {0x290A, "Value Trigger Setting"}, +#endif + {0, ""} +}; + +typedef struct { + uint32_t assignedNumber; + const char *name; +} characteristicMap_t; + +static const characteristicMap_t g_characteristicsMappings[] = { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + {0x2A7E, "Aerobic Heart Rate Lower Limit"}, + {0x2A84, "Aerobic Heart Rate Upper Limit"}, + {0x2A7F, "Aerobic Threshold"}, + {0x2A80, "Age"}, + {0x2A5A, "Aggregate"}, + {0x2A43, "Alert Category ID"}, + {0x2A42, "Alert Category ID Bit Mask"}, + {0x2A06, "Alert Level"}, + {0x2A44, "Alert Notification Control Point"}, + {0x2A3F, "Alert Status"}, + {0x2AB3, "Altitude"}, + {0x2A81, "Anaerobic Heart Rate Lower Limit"}, + {0x2A82, "Anaerobic Heart Rate Upper Limit"}, + {0x2A83, "Anaerobic Threshold"}, + {0x2A58, "Analog"}, + {0x2A59, "Analog Output"}, + {0x2A73, "Apparent Wind Direction"}, + {0x2A72, "Apparent Wind Speed"}, + {0x2A01, "Appearance"}, + {0x2AA3, "Barometric Pressure Trend"}, + {0x2A19, "Battery Level"}, + {0x2A1B, "Battery Level State"}, + {0x2A1A, "Battery Power State"}, + {0x2A49, "Blood Pressure Feature"}, + {0x2A35, "Blood Pressure Measurement"}, + {0x2A9B, "Body Composition Feature"}, + {0x2A9C, "Body Composition Measurement"}, + {0x2A38, "Body Sensor Location"}, + {0x2AA4, "Bond Management Control Point"}, + {0x2AA5, "Bond Management Features"}, + {0x2A22, "Boot Keyboard Input Report"}, + {0x2A32, "Boot Keyboard Output Report"}, + {0x2A33, "Boot Mouse Input Report"}, + {0x2AA6, "Central Address Resolution"}, + {0x2AA8, "CGM Feature"}, + {0x2AA7, "CGM Measurement"}, + {0x2AAB, "CGM Session Run Time"}, + {0x2AAA, "CGM Session Start Time"}, + {0x2AAC, "CGM Specific Ops Control Point"}, + {0x2AA9, "CGM Status"}, + {0x2ACE, "Cross Trainer Data"}, + {0x2A5C, "CSC Feature"}, + {0x2A5B, "CSC Measurement"}, + {0x2A2B, "Current Time"}, + {0x2A66, "Cycling Power Control Point"}, + {0x2A66, "Cycling Power Control Point"}, + {0x2A65, "Cycling Power Feature"}, + {0x2A65, "Cycling Power Feature"}, + {0x2A63, "Cycling Power Measurement"}, + {0x2A64, "Cycling Power Vector"}, + {0x2A99, "Database Change Increment"}, + {0x2A85, "Date of Birth"}, + {0x2A86, "Date of Threshold Assessment"}, + {0x2A08, "Date Time"}, + {0x2A0A, "Day Date Time"}, + {0x2A09, "Day of Week"}, + {0x2A7D, "Descriptor Value Changed"}, + {0x2A00, "Device Name"}, + {0x2A7B, "Dew Point"}, + {0x2A56, "Digital"}, + {0x2A57, "Digital Output"}, + {0x2A0D, "DST Offset"}, + {0x2A6C, "Elevation"}, + {0x2A87, "Email Address"}, + {0x2A0B, "Exact Time 100"}, + {0x2A0C, "Exact Time 256"}, + {0x2A88, "Fat Burn Heart Rate Lower Limit"}, + {0x2A89, "Fat Burn Heart Rate Upper Limit"}, + {0x2A26, "Firmware Revision String"}, + {0x2A8A, "First Name"}, + {0x2AD9, "Fitness Machine Control Point"}, + {0x2ACC, "Fitness Machine Feature"}, + {0x2ADA, "Fitness Machine Status"}, + {0x2A8B, "Five Zone Heart Rate Limits"}, + {0x2AB2, "Floor Number"}, + {0x2A8C, "Gender"}, + {0x2A51, "Glucose Feature"}, + {0x2A18, "Glucose Measurement"}, + {0x2A34, "Glucose Measurement Context"}, + {0x2A74, "Gust Factor"}, + {0x2A27, "Hardware Revision String"}, + {0x2A39, "Heart Rate Control Point"}, + {0x2A8D, "Heart Rate Max"}, + {0x2A37, "Heart Rate Measurement"}, + {0x2A7A, "Heat Index"}, + {0x2A8E, "Height"}, + {0x2A4C, "HID Control Point"}, + {0x2A4A, "HID Information"}, + {0x2A8F, "Hip Circumference"}, + {0x2ABA, "HTTP Control Point"}, + {0x2AB9, "HTTP Entity Body"}, + {0x2AB7, "HTTP Headers"}, + {0x2AB8, "HTTP Status Code"}, + {0x2ABB, "HTTPS Security"}, + {0x2A6F, "Humidity"}, + {0x2A2A, "IEEE 11073-20601 Regulatory Certification Data List"}, + {0x2AD2, "Indoor Bike Data"}, + {0x2AAD, "Indoor Positioning Configuration"}, + {0x2A36, "Intermediate Cuff Pressure"}, + {0x2A1E, "Intermediate Temperature"}, + {0x2A77, "Irradiance"}, + {0x2AA2, "Language"}, + {0x2A90, "Last Name"}, + {0x2AAE, "Latitude"}, + {0x2A6B, "LN Control Point"}, + {0x2A6A, "LN Feature"}, + {0x2AB1, "Local East Coordinate"}, + {0x2AB0, "Local North Coordinate"}, + {0x2A0F, "Local Time Information"}, + {0x2A67, "Location and Speed Characteristic"}, + {0x2AB5, "Location Name"}, + {0x2AAF, "Longitude"}, + {0x2A2C, "Magnetic Declination"}, + {0x2AA0, "Magnetic Flux Density - 2D"}, + {0x2AA1, "Magnetic Flux Density - 3D"}, + {0x2A29, "Manufacturer Name String"}, + {0x2A91, "Maximum Recommended Heart Rate"}, + {0x2A21, "Measurement Interval"}, + {0x2A24, "Model Number String"}, + {0x2A68, "Navigation"}, + {0x2A3E, "Network Availability"}, + {0x2A46, "New Alert"}, + {0x2AC5, "Object Action Control Point"}, + {0x2AC8, "Object Changed"}, + {0x2AC1, "Object First-Created"}, + {0x2AC3, "Object ID"}, + {0x2AC2, "Object Last-Modified"}, + {0x2AC6, "Object List Control Point"}, + {0x2AC7, "Object List Filter"}, + {0x2ABE, "Object Name"}, + {0x2AC4, "Object Properties"}, + {0x2AC0, "Object Size"}, + {0x2ABF, "Object Type"}, + {0x2ABD, "OTS Feature"}, + {0x2A04, "Peripheral Preferred Connection Parameters"}, + {0x2A02, "Peripheral Privacy Flag"}, + {0x2A5F, "PLX Continuous Measurement Characteristic"}, + {0x2A60, "PLX Features"}, + {0x2A5E, "PLX Spot-Check Measurement"}, + {0x2A50, "PnP ID"}, + {0x2A75, "Pollen Concentration"}, + {0x2A2F, "Position 2D"}, + {0x2A30, "Position 3D"}, + {0x2A69, "Position Quality"}, + {0x2A6D, "Pressure"}, + {0x2A4E, "Protocol Mode"}, + {0x2A62, "Pulse Oximetry Control Point"}, + {0x2A60, "Pulse Oximetry Pulsatile Event Characteristic"}, + {0x2A78, "Rainfall"}, + {0x2A03, "Reconnection Address"}, + {0x2A52, "Record Access Control Point"}, + {0x2A14, "Reference Time Information"}, + {0x2A3A, "Removable"}, + {0x2A4D, "Report"}, + {0x2A4B, "Report Map"}, + {0x2AC9, "Resolvable Private Address Only"}, + {0x2A92, "Resting Heart Rate"}, + {0x2A40, "Ringer Control point"}, + {0x2A41, "Ringer Setting"}, + {0x2AD1, "Rower Data"}, + {0x2A54, "RSC Feature"}, + {0x2A53, "RSC Measurement"}, + {0x2A55, "SC Control Point"}, + {0x2A4F, "Scan Interval Window"}, + {0x2A31, "Scan Refresh"}, + {0x2A3C, "Scientific Temperature Celsius"}, + {0x2A10, "Secondary Time Zone"}, + {0x2A5D, "Sensor Location"}, + {0x2A25, "Serial Number String"}, + {0x2A05, "Service Changed"}, + {0x2A3B, "Service Required"}, + {0x2A28, "Software Revision String"}, + {0x2A93, "Sport Type for Aerobic and Anaerobic Thresholds"}, + {0x2AD0, "Stair Climber Data"}, + {0x2ACF, "Step Climber Data"}, + {0x2A3D, "String"}, + {0x2AD7, "Supported Heart Rate Range"}, + {0x2AD5, "Supported Inclination Range"}, + {0x2A47, "Supported New Alert Category"}, + {0x2AD8, "Supported Power Range"}, + {0x2AD6, "Supported Resistance Level Range"}, + {0x2AD4, "Supported Speed Range"}, + {0x2A48, "Supported Unread Alert Category"}, + {0x2A23, "System ID"}, + {0x2ABC, "TDS Control Point"}, + {0x2A6E, "Temperature"}, + {0x2A1F, "Temperature Celsius"}, + {0x2A20, "Temperature Fahrenheit"}, + {0x2A1C, "Temperature Measurement"}, + {0x2A1D, "Temperature Type"}, + {0x2A94, "Three Zone Heart Rate Limits"}, + {0x2A12, "Time Accuracy"}, + {0x2A15, "Time Broadcast"}, + {0x2A13, "Time Source"}, + {0x2A16, "Time Update Control Point"}, + {0x2A17, "Time Update State"}, + {0x2A11, "Time with DST"}, + {0x2A0E, "Time Zone"}, + {0x2AD3, "Training Status"}, + {0x2ACD, "Treadmill Data"}, + {0x2A71, "True Wind Direction"}, + {0x2A70, "True Wind Speed"}, + {0x2A95, "Two Zone Heart Rate Limit"}, + {0x2A07, "Tx Power Level"}, + {0x2AB4, "Uncertainty"}, + {0x2A45, "Unread Alert Status"}, + {0x2AB6, "URI"}, + {0x2A9F, "User Control Point"}, + {0x2A9A, "User Index"}, + {0x2A76, "UV Index"}, + {0x2A96, "VO2 Max"}, + {0x2A97, "Waist Circumference"}, + {0x2A98, "Weight"}, + {0x2A9D, "Weight Measurement"}, + {0x2A9E, "Weight Scale Feature"}, + {0x2A79, "Wind Chill"}, +#endif + {0, ""} +}; + +/** + * @brief Mapping from service ids to names + */ +typedef struct { + const char *name; + const char *type; + uint32_t assignedNumber; +} gattService_t; + +/** + * Definition of the service ids to names that we know about. + */ +static const gattService_t g_gattServices[] = { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + {"Alert Notification Service", "org.bluetooth.service.alert_notification", 0x1811}, + {"Automation IO", "org.bluetooth.service.automation_io", 0x1815}, + {"Battery Service", "org.bluetooth.service.battery_service", 0x180F}, + {"Blood Pressure", "org.bluetooth.service.blood_pressure", 0x1810}, + {"Body Composition", "org.bluetooth.service.body_composition", 0x181B}, + {"Bond Management", "org.bluetooth.service.bond_management", 0x181E}, + {"Continuous Glucose Monitoring", "org.bluetooth.service.continuous_glucose_monitoring", 0x181F}, + {"Current Time Service", "org.bluetooth.service.current_time", 0x1805}, + {"Cycling Power", "org.bluetooth.service.cycling_power", 0x1818}, + {"Cycling Speed and Cadence", "org.bluetooth.service.cycling_speed_and_cadence", 0x1816}, + {"Device Information", "org.bluetooth.service.device_information", 0x180A}, + {"Environmental Sensing", "org.bluetooth.service.environmental_sensing", 0x181A}, + {"Generic Access", "org.bluetooth.service.generic_access", 0x1800}, + {"Generic Attribute", "org.bluetooth.service.generic_attribute", 0x1801}, + {"Glucose", "org.bluetooth.service.glucose", 0x1808}, + {"Health Thermometer", "org.bluetooth.service.health_thermometer", 0x1809}, + {"Heart Rate", "org.bluetooth.service.heart_rate", 0x180D}, + {"HTTP Proxy", "org.bluetooth.service.http_proxy", 0x1823}, + {"Human Interface Device", "org.bluetooth.service.human_interface_device", 0x1812}, + {"Immediate Alert", "org.bluetooth.service.immediate_alert", 0x1802}, + {"Indoor Positioning", "org.bluetooth.service.indoor_positioning", 0x1821}, + {"Internet Protocol Support", "org.bluetooth.service.internet_protocol_support", 0x1820}, + {"Link Loss", "org.bluetooth.service.link_loss", 0x1803}, + {"Location and Navigation", "org.bluetooth.service.location_and_navigation", 0x1819}, + {"Next DST Change Service", "org.bluetooth.service.next_dst_change", 0x1807}, + {"Object Transfer", "org.bluetooth.service.object_transfer", 0x1825}, + {"Phone Alert Status Service", "org.bluetooth.service.phone_alert_status", 0x180E}, + {"Pulse Oximeter", "org.bluetooth.service.pulse_oximeter", 0x1822}, + {"Reference Time Update Service", "org.bluetooth.service.reference_time_update", 0x1806}, + {"Running Speed and Cadence", "org.bluetooth.service.running_speed_and_cadence", 0x1814}, + {"Scan Parameters", "org.bluetooth.service.scan_parameters", 0x1813}, + {"Transport Discovery", "org.bluetooth.service.transport_discovery", 0x1824}, + {"Tx Power", "org.bluetooth.service.tx_power", 0x1804}, + {"User Data", "org.bluetooth.service.user_data", 0x181C}, + {"Weight Scale", "org.bluetooth.service.weight_scale", 0x181D}, +#endif + {"", "", 0} +}; +#endif + +/***************************************************************************** + * Common functions * + *****************************************************************************/ + +/** + * @brief Create a hex representation of data. + * + * @param [in] target Where to write the hex string. If this is null, we malloc storage. + * @param [in] source The start of the binary data. + * @param [in] length The length of the data to convert. + * @return A pointer to the formatted buffer. + */ +char *BLEUtils::buildHexData(uint8_t *target, const uint8_t *source, uint8_t length) { + // Guard against too much data. + if (length > 100) { + length = 100; + } + + if (target == nullptr) { + target = (uint8_t *)malloc(length * 2 + 1); + if (target == nullptr) { + log_e("buildHexData: malloc failed"); + return nullptr; + } + } + char *startOfData = (char *)target; + + for (int i = 0; i < length; i++) { + sprintf((char *)target, "%.2x", (char)source[i]); + target += 2; + } + + // Handle the special case where there was no data. + if (length == 0) { + *startOfData = 0; + } + + return startOfData; +} // buildHexData + +/** + * @brief Given an advertising data type, return a string representation of the type. + * + * For details see ... + * https://www.bluetooth.com/specifications/assigned-numbers/generic-access-profile + * + * @return A string representation of the type. + */ +const char *BLEUtils::advDataTypeToString(uint8_t advType) { + switch (advType) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_BLE_AD_TYPE_FLAG: // 0x01 + return "ESP_BLE_AD_TYPE_FLAG"; + case ESP_BLE_AD_TYPE_16SRV_PART: // 0x02 + return "ESP_BLE_AD_TYPE_16SRV_PART"; + case ESP_BLE_AD_TYPE_16SRV_CMPL: // 0x03 + return "ESP_BLE_AD_TYPE_16SRV_CMPL"; + case ESP_BLE_AD_TYPE_32SRV_PART: // 0x04 + return "ESP_BLE_AD_TYPE_32SRV_PART"; + case ESP_BLE_AD_TYPE_32SRV_CMPL: // 0x05 + return "ESP_BLE_AD_TYPE_32SRV_CMPL"; + case ESP_BLE_AD_TYPE_128SRV_PART: // 0x06 + return "ESP_BLE_AD_TYPE_128SRV_PART"; + case ESP_BLE_AD_TYPE_128SRV_CMPL: // 0x07 + return "ESP_BLE_AD_TYPE_128SRV_CMPL"; + case ESP_BLE_AD_TYPE_NAME_SHORT: // 0x08 + return "ESP_BLE_AD_TYPE_NAME_SHORT"; + case ESP_BLE_AD_TYPE_NAME_CMPL: // 0x09 + return "ESP_BLE_AD_TYPE_NAME_CMPL"; + case ESP_BLE_AD_TYPE_TX_PWR: // 0x0a + return "ESP_BLE_AD_TYPE_TX_PWR"; + case ESP_BLE_AD_TYPE_DEV_CLASS: // 0x0b + return "ESP_BLE_AD_TYPE_DEV_CLASS"; + case ESP_BLE_AD_TYPE_SM_TK: // 0x10 + return "ESP_BLE_AD_TYPE_SM_TK"; + case ESP_BLE_AD_TYPE_SM_OOB_FLAG: // 0x11 + return "ESP_BLE_AD_TYPE_SM_OOB_FLAG"; + case ESP_BLE_AD_TYPE_INT_RANGE: // 0x12 + return "ESP_BLE_AD_TYPE_INT_RANGE"; + case ESP_BLE_AD_TYPE_SOL_SRV_UUID: // 0x14 + return "ESP_BLE_AD_TYPE_SOL_SRV_UUID"; + case ESP_BLE_AD_TYPE_128SOL_SRV_UUID: // 0x15 + return "ESP_BLE_AD_TYPE_128SOL_SRV_UUID"; + case ESP_BLE_AD_TYPE_SERVICE_DATA: // 0x16 + return "ESP_BLE_AD_TYPE_SERVICE_DATA"; + case ESP_BLE_AD_TYPE_PUBLIC_TARGET: // 0x17 + return "ESP_BLE_AD_TYPE_PUBLIC_TARGET"; + case ESP_BLE_AD_TYPE_RANDOM_TARGET: // 0x18 + return "ESP_BLE_AD_TYPE_RANDOM_TARGET"; + case ESP_BLE_AD_TYPE_APPEARANCE: // 0x19 + return "ESP_BLE_AD_TYPE_APPEARANCE"; + case ESP_BLE_AD_TYPE_ADV_INT: // 0x1a + return "ESP_BLE_AD_TYPE_ADV_INT"; + case ESP_BLE_AD_TYPE_32SOL_SRV_UUID: // 0x1f + return "ESP_BLE_AD_TYPE_32SOL_SRV_UUID"; + case ESP_BLE_AD_TYPE_32SERVICE_DATA: // 0x20 + return "ESP_BLE_AD_TYPE_32SERVICE_DATA"; + case ESP_BLE_AD_TYPE_128SERVICE_DATA: // 0x21 + return "ESP_BLE_AD_TYPE_128SERVICE_DATA"; + case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE: // 0xff + return "ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE"; +#endif + default: log_v(" adv data type: 0x%x", advType); return ""; + } // End switch +} // advDataTypeToString + +/***************************************************************************** + * Bluedroid functions * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + +/** + * @brief Convert characteristic properties into a string representation. + * @param [in] prop Characteristic properties. + * @return A string representation of characteristic properties. + */ +String BLEUtils::characteristicPropertiesToString(uint8_t prop) { + String res = "broadcast: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_BROADCAST) ? "1" : "0"); + res += ", read: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_READ) ? "1" : "0"); + res += ", write_nr: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) ? "1" : "0"); + res += ", write: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE) ? "1" : "0"); + res += ", notify: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_NOTIFY) ? "1" : "0"); + res += ", indicate: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_INDICATE) ? "1" : "0"); + res += ", auth: "; + res += ((prop & ESP_GATT_CHAR_PROP_BIT_AUTH) ? "1" : "0"); + return res; +} // characteristicPropertiesToString + +/** + * @brief Build a printable string of memory range. + * Create a string representation of a piece of memory. Only printable characters will be included + * while those that are not printable will be replaced with '.'. + * @param [in] source Start of memory. + * @param [in] length Length of memory. + * @return A string representation of a piece of memory. + */ +String BLEUtils::buildPrintData(uint8_t *source, size_t length) { + String res; + for (int i = 0; i < length; i++) { + char c = *source; + res += (isprint(c) ? c : '.'); + source++; + } + return res; +} // buildPrintData + +/** + * @brief Convert an esp_gatt_id_t to a string. + */ +static String gattIdToString(esp_gatt_id_t gattId) { + String res = "uuid: " + BLEUUID(gattId.uuid).toString() + ", inst_id: "; + char val[8]; + snprintf(val, sizeof(val), "%d", (int)gattId.inst_id); + res += val; + return res; +} // gattIdToString + +/** + * @brief Convert an esp_ble_addr_type_t to a string representation. + */ +const char *BLEUtils::addressTypeToString(esp_ble_addr_type_t type) { + switch (type) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case BLE_ADDR_TYPE_PUBLIC: return "BLE_ADDR_TYPE_PUBLIC"; + case BLE_ADDR_TYPE_RANDOM: return "BLE_ADDR_TYPE_RANDOM"; + case BLE_ADDR_TYPE_RPA_PUBLIC: return "BLE_ADDR_TYPE_RPA_PUBLIC"; + case BLE_ADDR_TYPE_RPA_RANDOM: return "BLE_ADDR_TYPE_RPA_RANDOM"; +#endif + default: return " esp_ble_addr_type_t"; + } +} // addressTypeToString + +/** + * @brief Convert the BLE Advertising Data flags to a string. + * @param adFlags The flags to convert + * @return String A string representation of the advertising flags. + */ +String BLEUtils::adFlagsToString(uint8_t adFlags) { + String res; + if (adFlags & (1 << 0)) { + res += "[LE Limited Discoverable Mode] "; + } + if (adFlags & (1 << 1)) { + res += "[LE General Discoverable Mode] "; + } + if (adFlags & (1 << 2)) { + res += "[BR/EDR Not Supported] "; + } + if (adFlags & (1 << 3)) { + res += "[Simultaneous LE and BR/EDR to Same Device Capable (Controller)] "; + } + if (adFlags & (1 << 4)) { + res += "[Simultaneous LE and BR/EDR to Same Device Capable (Host)] "; + } + return res; +} // adFlagsToString + +esp_gatt_id_t BLEUtils::buildGattId(esp_bt_uuid_t uuid, uint8_t inst_id) { + esp_gatt_id_t retGattId; + retGattId.uuid = uuid; + retGattId.inst_id = inst_id; + return retGattId; +} + +esp_gatt_srvc_id_t BLEUtils::buildGattSrvcId(esp_gatt_id_t gattId, bool is_primary) { + esp_gatt_srvc_id_t retSrvcId; + retSrvcId.id = gattId; + retSrvcId.is_primary = is_primary; + return retSrvcId; +} + +/** + * @brief Convert a close/disconnect reason to a string. + * @param [in] reason The close reason. + * @return A string representation of the reason. + */ +String BLEUtils::gattCloseReasonToString(esp_gatt_conn_reason_t reason) { + switch (reason) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GATT_CONN_UNKNOWN: + { + return "ESP_GATT_CONN_UNKNOWN"; + } + case ESP_GATT_CONN_L2C_FAILURE: + { + return "ESP_GATT_CONN_L2C_FAILURE"; + } + case ESP_GATT_CONN_TIMEOUT: + { + return "ESP_GATT_CONN_TIMEOUT"; + } + case ESP_GATT_CONN_TERMINATE_PEER_USER: + { + return "ESP_GATT_CONN_TERMINATE_PEER_USER"; + } + case ESP_GATT_CONN_TERMINATE_LOCAL_HOST: + { + return "ESP_GATT_CONN_TERMINATE_LOCAL_HOST"; + } + case ESP_GATT_CONN_FAIL_ESTABLISH: + { + return "ESP_GATT_CONN_FAIL_ESTABLISH"; + } + case ESP_GATT_CONN_LMP_TIMEOUT: + { + return "ESP_GATT_CONN_LMP_TIMEOUT"; + } + case ESP_GATT_CONN_CONN_CANCEL: + { + return "ESP_GATT_CONN_CONN_CANCEL"; + } + case ESP_GATT_CONN_NONE: + { + return "ESP_GATT_CONN_NONE"; + } +#endif + default: + { + return "Unknown"; + } + } +} // gattCloseReasonToString + +String BLEUtils::gattClientEventTypeToString(esp_gattc_cb_event_t eventType) { + switch (eventType) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GATTC_ACL_EVT: return "ESP_GATTC_ACL_EVT"; + case ESP_GATTC_ADV_DATA_EVT: return "ESP_GATTC_ADV_DATA_EVT"; + case ESP_GATTC_ADV_VSC_EVT: return "ESP_GATTC_ADV_VSC_EVT"; + case ESP_GATTC_BTH_SCAN_CFG_EVT: return "ESP_GATTC_BTH_SCAN_CFG_EVT"; + case ESP_GATTC_BTH_SCAN_DIS_EVT: return "ESP_GATTC_BTH_SCAN_DIS_EVT"; + case ESP_GATTC_BTH_SCAN_ENB_EVT: return "ESP_GATTC_BTH_SCAN_ENB_EVT"; + case ESP_GATTC_BTH_SCAN_PARAM_EVT: return "ESP_GATTC_BTH_SCAN_PARAM_EVT"; + case ESP_GATTC_BTH_SCAN_RD_EVT: return "ESP_GATTC_BTH_SCAN_RD_EVT"; + case ESP_GATTC_BTH_SCAN_THR_EVT: return "ESP_GATTC_BTH_SCAN_THR_EVT"; + case ESP_GATTC_CANCEL_OPEN_EVT: return "ESP_GATTC_CANCEL_OPEN_EVT"; + case ESP_GATTC_CFG_MTU_EVT: return "ESP_GATTC_CFG_MTU_EVT"; + case ESP_GATTC_CLOSE_EVT: return "ESP_GATTC_CLOSE_EVT"; + case ESP_GATTC_CONGEST_EVT: return "ESP_GATTC_CONGEST_EVT"; + case ESP_GATTC_CONNECT_EVT: return "ESP_GATTC_CONNECT_EVT"; + case ESP_GATTC_DISCONNECT_EVT: return "ESP_GATTC_DISCONNECT_EVT"; + case ESP_GATTC_ENC_CMPL_CB_EVT: return "ESP_GATTC_ENC_CMPL_CB_EVT"; + case ESP_GATTC_EXEC_EVT: + return "ESP_GATTC_EXEC_EVT"; + //case ESP_GATTC_GET_CHAR_EVT: + // return "ESP_GATTC_GET_CHAR_EVT"; + //case ESP_GATTC_GET_DESCR_EVT: + // return "ESP_GATTC_GET_DESCR_EVT"; + //case ESP_GATTC_GET_INCL_SRVC_EVT: + // return "ESP_GATTC_GET_INCL_SRVC_EVT"; + case ESP_GATTC_MULT_ADV_DATA_EVT: return "ESP_GATTC_MULT_ADV_DATA_EVT"; + case ESP_GATTC_MULT_ADV_DIS_EVT: return "ESP_GATTC_MULT_ADV_DIS_EVT"; + case ESP_GATTC_MULT_ADV_ENB_EVT: return "ESP_GATTC_MULT_ADV_ENB_EVT"; + case ESP_GATTC_MULT_ADV_UPD_EVT: return "ESP_GATTC_MULT_ADV_UPD_EVT"; + case ESP_GATTC_NOTIFY_EVT: return "ESP_GATTC_NOTIFY_EVT"; + case ESP_GATTC_OPEN_EVT: return "ESP_GATTC_OPEN_EVT"; + case ESP_GATTC_PREP_WRITE_EVT: return "ESP_GATTC_PREP_WRITE_EVT"; + case ESP_GATTC_READ_CHAR_EVT: return "ESP_GATTC_READ_CHAR_EVT"; + case ESP_GATTC_REG_EVT: return "ESP_GATTC_REG_EVT"; + case ESP_GATTC_REG_FOR_NOTIFY_EVT: return "ESP_GATTC_REG_FOR_NOTIFY_EVT"; + case ESP_GATTC_SCAN_FLT_CFG_EVT: return "ESP_GATTC_SCAN_FLT_CFG_EVT"; + case ESP_GATTC_SCAN_FLT_PARAM_EVT: return "ESP_GATTC_SCAN_FLT_PARAM_EVT"; + case ESP_GATTC_SCAN_FLT_STATUS_EVT: return "ESP_GATTC_SCAN_FLT_STATUS_EVT"; + case ESP_GATTC_SEARCH_CMPL_EVT: return "ESP_GATTC_SEARCH_CMPL_EVT"; + case ESP_GATTC_SEARCH_RES_EVT: return "ESP_GATTC_SEARCH_RES_EVT"; + case ESP_GATTC_SRVC_CHG_EVT: return "ESP_GATTC_SRVC_CHG_EVT"; + case ESP_GATTC_READ_DESCR_EVT: return "ESP_GATTC_READ_DESCR_EVT"; + case ESP_GATTC_UNREG_EVT: return "ESP_GATTC_UNREG_EVT"; + case ESP_GATTC_UNREG_FOR_NOTIFY_EVT: return "ESP_GATTC_UNREG_FOR_NOTIFY_EVT"; + case ESP_GATTC_WRITE_CHAR_EVT: return "ESP_GATTC_WRITE_CHAR_EVT"; + case ESP_GATTC_WRITE_DESCR_EVT: return "ESP_GATTC_WRITE_DESCR_EVT"; +#endif + default: log_v("Unknown GATT Client event type: %d", eventType); return "Unknown"; + } +} // gattClientEventTypeToString + +/** + * @brief Return a string representation of a GATT server event code. + * @param [in] eventType A GATT server event code. + * @return A string representation of the GATT server event code. + */ +String BLEUtils::gattServerEventTypeToString(esp_gatts_cb_event_t eventType) { + switch (eventType) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GATTS_REG_EVT: return "ESP_GATTS_REG_EVT"; + case ESP_GATTS_READ_EVT: return "ESP_GATTS_READ_EVT"; + case ESP_GATTS_WRITE_EVT: return "ESP_GATTS_WRITE_EVT"; + case ESP_GATTS_EXEC_WRITE_EVT: return "ESP_GATTS_EXEC_WRITE_EVT"; + case ESP_GATTS_MTU_EVT: return "ESP_GATTS_MTU_EVT"; + case ESP_GATTS_CONF_EVT: return "ESP_GATTS_CONF_EVT"; + case ESP_GATTS_UNREG_EVT: return "ESP_GATTS_UNREG_EVT"; + case ESP_GATTS_CREATE_EVT: return "ESP_GATTS_CREATE_EVT"; + case ESP_GATTS_ADD_INCL_SRVC_EVT: return "ESP_GATTS_ADD_INCL_SRVC_EVT"; + case ESP_GATTS_ADD_CHAR_EVT: return "ESP_GATTS_ADD_CHAR_EVT"; + case ESP_GATTS_ADD_CHAR_DESCR_EVT: return "ESP_GATTS_ADD_CHAR_DESCR_EVT"; + case ESP_GATTS_DELETE_EVT: return "ESP_GATTS_DELETE_EVT"; + case ESP_GATTS_START_EVT: return "ESP_GATTS_START_EVT"; + case ESP_GATTS_STOP_EVT: return "ESP_GATTS_STOP_EVT"; + case ESP_GATTS_CONNECT_EVT: return "ESP_GATTS_CONNECT_EVT"; + case ESP_GATTS_DISCONNECT_EVT: return "ESP_GATTS_DISCONNECT_EVT"; + case ESP_GATTS_OPEN_EVT: return "ESP_GATTS_OPEN_EVT"; + case ESP_GATTS_CANCEL_OPEN_EVT: return "ESP_GATTS_CANCEL_OPEN_EVT"; + case ESP_GATTS_CLOSE_EVT: return "ESP_GATTS_CLOSE_EVT"; + case ESP_GATTS_LISTEN_EVT: return "ESP_GATTS_LISTEN_EVT"; + case ESP_GATTS_CONGEST_EVT: return "ESP_GATTS_CONGEST_EVT"; + case ESP_GATTS_RESPONSE_EVT: return "ESP_GATTS_RESPONSE_EVT"; + case ESP_GATTS_CREAT_ATTR_TAB_EVT: return "ESP_GATTS_CREAT_ATTR_TAB_EVT"; + case ESP_GATTS_SET_ATTR_VAL_EVT: return "ESP_GATTS_SET_ATTR_VAL_EVT"; + case ESP_GATTS_SEND_SERVICE_CHANGE_EVT: return "ESP_GATTS_SEND_SERVICE_CHANGE_EVT"; +#endif + default: return "Unknown"; + } +} // gattServerEventTypeToString + +/** + * @brief Convert a BLE device type to a string. + * @param [in] type The device type. + */ +const char *BLEUtils::devTypeToString(esp_bt_dev_type_t type) { + switch (type) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_BT_DEVICE_TYPE_BREDR: return "ESP_BT_DEVICE_TYPE_BREDR"; + case ESP_BT_DEVICE_TYPE_BLE: return "ESP_BT_DEVICE_TYPE_BLE"; + case ESP_BT_DEVICE_TYPE_DUMO: return "ESP_BT_DEVICE_TYPE_DUMO"; +#endif + default: return "Unknown"; + } +} // devTypeToString + +/** + * @brief Dump the GAP event to the log. + */ +void BLEUtils::dumpGapEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) { + log_v("Received a GAP event: %s", gapEventToString(event)); + switch (event) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + // ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT + // adv_data_cmpl + // - esp_bt_status_t + case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: + { + log_v("[status: %d]", param->adv_data_cmpl.status); + break; + } // ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT + + // ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT + // + // adv_data_raw_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: + { + log_v("[status: %d]", param->adv_data_raw_cmpl.status); + break; + } // ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT + + // ESP_GAP_BLE_ADV_START_COMPLETE_EVT + // + // adv_start_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + { + log_v("[status: %d]", param->adv_start_cmpl.status); + break; + } // ESP_GAP_BLE_ADV_START_COMPLETE_EVT + + // ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT + // + // adv_stop_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: + { + log_v("[status: %d]", param->adv_stop_cmpl.status); + break; + } // ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT + + // ESP_GAP_BLE_AUTH_CMPL_EVT + // + // auth_cmpl + // - esp_bd_addr_t bd_addr + // - bool key_present + // - esp_link_key key + // - bool success + // - uint8_t fail_reason + // - esp_bd_addr_type_t addr_type + // - esp_bt_dev_type_t dev_type + case ESP_GAP_BLE_AUTH_CMPL_EVT: + { + log_v( + "[bd_addr: %s, key_present: %d, key: ***, key_type: %d, success: %d, fail_reason: %d, addr_type: ***, dev_type: %s]", + BLEAddress(param->ble_security.auth_cmpl.bd_addr).toString().c_str(), param->ble_security.auth_cmpl.key_present, param->ble_security.auth_cmpl.key_type, + param->ble_security.auth_cmpl.success, param->ble_security.auth_cmpl.fail_reason, BLEUtils::devTypeToString(param->ble_security.auth_cmpl.dev_type) + ); + break; + } // ESP_GAP_BLE_AUTH_CMPL_EVT + + // ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT + // + // clear_bond_dev_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT: + { + log_v("[status: %d]", param->clear_bond_dev_cmpl.status); + break; + } // ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT + + // ESP_GAP_BLE_LOCAL_IR_EVT + case ESP_GAP_BLE_LOCAL_IR_EVT: + { + break; + } // ESP_GAP_BLE_LOCAL_IR_EVT + + // ESP_GAP_BLE_LOCAL_ER_EVT + case ESP_GAP_BLE_LOCAL_ER_EVT: + { + break; + } // ESP_GAP_BLE_LOCAL_ER_EVT + + // ESP_GAP_BLE_NC_REQ_EVT + case ESP_GAP_BLE_NC_REQ_EVT: + { + log_v("[bd_addr: %s, passkey: %d]", BLEAddress(param->ble_security.key_notif.bd_addr).toString().c_str(), param->ble_security.key_notif.passkey); + break; + } // ESP_GAP_BLE_NC_REQ_EVT + + // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT + // + // read_rssi_cmpl + // - esp_bt_status_t status + // - int8_t rssi + // - esp_bd_addr_t remote_addr + case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT: + { + log_v( + "[status: %d, rssi: %d, remote_addr: %s]", param->read_rssi_cmpl.status, param->read_rssi_cmpl.rssi, + BLEAddress(param->read_rssi_cmpl.remote_addr).toString().c_str() + ); + break; + } // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT + + // ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT + // + // scan_param_cmpl. + // - esp_bt_status_t status + case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT: + { + log_v("[status: %d]", param->scan_param_cmpl.status); + break; + } // ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT + + // ESP_GAP_BLE_SCAN_RESULT_EVT + // + // scan_rst: + // - search_evt + // - bda + // - dev_type + // - ble_addr_type + // - ble_evt_type + // - rssi + // - ble_adv + // - flag + // - num_resps + // - adv_data_len + // - scan_rsp_len + case ESP_GAP_BLE_SCAN_RESULT_EVT: + { + switch (param->scan_rst.search_evt) { + case ESP_GAP_SEARCH_INQ_RES_EVT: + { + log_v( + "search_evt: %s, bda: %s, dev_type: %s, ble_addr_type: %s, ble_evt_type: %s, rssi: %d, ble_adv: ??, flag: %d (%s), num_resps: %d, adv_data_len: " + "%d, scan_rsp_len: %d", + searchEventTypeToString(param->scan_rst.search_evt), BLEAddress(param->scan_rst.bda).toString().c_str(), devTypeToString(param->scan_rst.dev_type), + addressTypeToString(param->scan_rst.ble_addr_type), eventTypeToString(param->scan_rst.ble_evt_type), param->scan_rst.rssi, param->scan_rst.flag, + adFlagsToString(param->scan_rst.flag).c_str(), param->scan_rst.num_resps, param->scan_rst.adv_data_len, param->scan_rst.scan_rsp_len + ); + break; + } // ESP_GAP_SEARCH_INQ_RES_EVT + + default: + { + log_v("search_evt: %s", searchEventTypeToString(param->scan_rst.search_evt)); + break; + } + } + break; + } // ESP_GAP_BLE_SCAN_RESULT_EVT + + // ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT + // + // scan_rsp_data_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: + { + log_v("[status: %d]", param->scan_rsp_data_cmpl.status); + break; + } // ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT + + // ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT + case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: + { + log_v("[status: %d]", param->scan_rsp_data_raw_cmpl.status); + break; + } // ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT + + // ESP_GAP_BLE_SCAN_START_COMPLETE_EVT + // + // scan_start_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT: + { + log_v("[status: %d]", param->scan_start_cmpl.status); + break; + } // ESP_GAP_BLE_SCAN_START_COMPLETE_EVT + + // ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT + // + // scan_stop_cmpl + // - esp_bt_status_t status + case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT: + { + log_v("[status: %d]", param->scan_stop_cmpl.status); + break; + } // ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT + + // ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT + // + // update_conn_params + // - esp_bt_status_t status + // - esp_bd_addr_t bda + // - uint16_t min_int + // - uint16_t max_int + // - uint16_t latency + // - uint16_t conn_int + // - uint16_t timeout + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + { + log_v( + "[status: %d, bd_addr: %s, min_int: %d, max_int: %d, latency: %d, conn_int: %d, timeout: %d]", param->update_conn_params.status, + BLEAddress(param->update_conn_params.bda).toString().c_str(), param->update_conn_params.min_int, param->update_conn_params.max_int, + param->update_conn_params.latency, param->update_conn_params.conn_int, param->update_conn_params.timeout + ); + break; + } // ESP_GAP_BLE_SCAN_UPDATE_CONN_PARAMS_EVT + + // ESP_GAP_BLE_SEC_REQ_EVT + case ESP_GAP_BLE_SEC_REQ_EVT: + { + log_v("[bd_addr: %s]", BLEAddress(param->ble_security.ble_req.bd_addr).toString().c_str()); + break; + } // ESP_GAP_BLE_SEC_REQ_EVT +#endif + default: + { + log_v("*** dumpGapEvent: Logger not coded ***"); + break; + } // default + } // switch +} // dumpGapEvent + +/** + * @brief Decode and dump a GATT client event + * + * @param [in] event The type of event received. + * @param [in] evtParam The data associated with the event. + */ +void BLEUtils::dumpGattClientEvent(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) { + + //esp_ble_gattc_cb_param_t* evtParam = (esp_ble_gattc_cb_param_t*) param; + log_v("GATT Event: %s", BLEUtils::gattClientEventTypeToString(event).c_str()); + switch (event) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + // ESP_GATTC_CLOSE_EVT + // + // close: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + // - esp_gatt_conn_reason_t reason + case ESP_GATTC_CLOSE_EVT: + { + log_v( + "[status: %s, reason:%s, conn_id: %d]", BLEUtils::gattStatusToString(evtParam->close.status).c_str(), + BLEUtils::gattCloseReasonToString(evtParam->close.reason).c_str(), evtParam->close.conn_id + ); + break; + } + + // ESP_GATTC_CONNECT_EVT + // + // connect: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + case ESP_GATTC_CONNECT_EVT: + { + log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str()); + break; + } + + // ESP_GATTC_DISCONNECT_EVT + // + // disconnect: + // - esp_gatt_conn_reason_t reason + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + case ESP_GATTC_DISCONNECT_EVT: + { + log_v( + "[reason: %s, conn_id: %d, remote_bda: %s]", BLEUtils::gattCloseReasonToString(evtParam->disconnect.reason).c_str(), evtParam->disconnect.conn_id, + BLEAddress(evtParam->disconnect.remote_bda).toString().c_str() + ); + break; + } // ESP_GATTC_DISCONNECT_EVT + + // ESP_GATTC_GET_CHAR_EVT + // + // get_char: + // - esp_gatt_status_t status + // - uin1t6_t conn_id + // - esp_gatt_srvc_id_t srvc_id + // - esp_gatt_id_t char_id + // - esp_gatt_char_prop_t char_prop + /* + case ESP_GATTC_GET_CHAR_EVT: { + + // If the status of the event shows that we have a value other than ESP_GATT_OK then the + // characteristic fields are not set to a usable value .. so don't try and log them. + if (evtParam->get_char.status == ESP_GATT_OK) { + String description = "Unknown"; + if (evtParam->get_char.char_id.uuid.len == ESP_UUID_LEN_16) { + description = BLEUtils::gattCharacteristicUUIDToString(evtParam->get_char.char_id.uuid.uuid.uuid16); + } + log_v("[status: %s, conn_id: %d, srvc_id: %s, char_id: %s [description: %s]\nchar_prop: %s]", + BLEUtils::gattStatusToString(evtParam->get_char.status).c_str(), + evtParam->get_char.conn_id, + BLEUtils::gattServiceIdToString(evtParam->get_char.srvc_id).c_str(), + gattIdToString(evtParam->get_char.char_id).c_str(), + description.c_str(), + BLEUtils::characteristicPropertiesToString(evtParam->get_char.char_prop).c_str() + ); + } else { + log_v("[status: %s, conn_id: %d, srvc_id: %s]", + BLEUtils::gattStatusToString(evtParam->get_char.status).c_str(), + evtParam->get_char.conn_id, + BLEUtils::gattServiceIdToString(evtParam->get_char.srvc_id).c_str() + ); + } + break; + } // ESP_GATTC_GET_CHAR_EVT + */ + + // ESP_GATTC_NOTIFY_EVT + // + // notify + // uint16_t conn_id + // esp_bd_addr_t remote_bda + // handle handle + // uint16_t value_len + // uint8_t* value + // bool is_notify + // + case ESP_GATTC_NOTIFY_EVT: + { + log_v( + "[conn_id: %d, remote_bda: %s, handle: %d 0x%.2x, value_len: %d, is_notify: %d]", evtParam->notify.conn_id, + BLEAddress(evtParam->notify.remote_bda).toString().c_str(), evtParam->notify.handle, evtParam->notify.handle, evtParam->notify.value_len, + evtParam->notify.is_notify + ); + break; + } + + // ESP_GATTC_OPEN_EVT + // + // open: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - esp_bd_addr_t remote_bda + // - uint16_t mtu + // + case ESP_GATTC_OPEN_EVT: + { + log_v( + "[status: %s, conn_id: %d, remote_bda: %s, mtu: %d]", BLEUtils::gattStatusToString(evtParam->open.status).c_str(), evtParam->open.conn_id, + BLEAddress(evtParam->open.remote_bda).toString().c_str(), evtParam->open.mtu + ); + break; + } // ESP_GATTC_OPEN_EVT + + // ESP_GATTC_READ_CHAR_EVT + // + // Callback to indicate that requested data that we wanted to read is now available. + // + // read: + // esp_gatt_status_t status + // uint16_t conn_id + // uint16_t handle + // uint8_t* value + // uint16_t value_type + // uint16_t value_len + case ESP_GATTC_READ_CHAR_EVT: + { + log_v( + "[status: %s, conn_id: %d, handle: %d 0x%.2x, value_len: %d]", BLEUtils::gattStatusToString(evtParam->read.status).c_str(), evtParam->read.conn_id, + evtParam->read.handle, evtParam->read.handle, evtParam->read.value_len + ); + if (evtParam->read.status == ESP_GATT_OK) { + GeneralUtils::hexDump(evtParam->read.value, evtParam->read.value_len); + /* + char* pHexData = BLEUtils::buildHexData(nullptr, evtParam->read.value, evtParam->read.value_len); + log_v("value: %s \"%s\"", pHexData, BLEUtils::buildPrintData(evtParam->read.value, evtParam->read.value_len).c_str()); + free(pHexData); + */ + } + break; + } // ESP_GATTC_READ_CHAR_EVT + + // ESP_GATTC_REG_EVT + // + // reg: + // - esp_gatt_status_t status + // - uint16_t app_id + case ESP_GATTC_REG_EVT: + { + log_v("[status: %s, app_id: 0x%x]", BLEUtils::gattStatusToString(evtParam->reg.status).c_str(), evtParam->reg.app_id); + break; + } // ESP_GATTC_REG_EVT + + // ESP_GATTC_REG_FOR_NOTIFY_EVT + // + // reg_for_notify: + // - esp_gatt_status_t status + // - uint16_t handle + case ESP_GATTC_REG_FOR_NOTIFY_EVT: + { + log_v( + "[status: %s, handle: %d 0x%.2x]", BLEUtils::gattStatusToString(evtParam->reg_for_notify.status).c_str(), evtParam->reg_for_notify.handle, + evtParam->reg_for_notify.handle + ); + break; + } // ESP_GATTC_REG_FOR_NOTIFY_EVT + + // ESP_GATTC_SEARCH_CMPL_EVT + // + // search_cmpl: + // - esp_gatt_status_t status + // - uint16_t conn_id + case ESP_GATTC_SEARCH_CMPL_EVT: + { + log_v("[status: %s, conn_id: %d]", BLEUtils::gattStatusToString(evtParam->search_cmpl.status).c_str(), evtParam->search_cmpl.conn_id); + break; + } // ESP_GATTC_SEARCH_CMPL_EVT + + // ESP_GATTC_SEARCH_RES_EVT + // + // search_res: + // - uint16_t conn_id + // - uint16_t start_handle + // - uint16_t end_handle + // - esp_gatt_id_t srvc_id + case ESP_GATTC_SEARCH_RES_EVT: + { + log_v( + "[conn_id: %d, start_handle: %d 0x%.2x, end_handle: %d 0x%.2x, srvc_id: %s", evtParam->search_res.conn_id, evtParam->search_res.start_handle, + evtParam->search_res.start_handle, evtParam->search_res.end_handle, evtParam->search_res.end_handle, + gattIdToString(evtParam->search_res.srvc_id).c_str() + ); + break; + } // ESP_GATTC_SEARCH_RES_EVT + + // ESP_GATTC_WRITE_CHAR_EVT + // + // write: + // - esp_gatt_status_t status + // - uint16_t conn_id + // - uint16_t handle + // - uint16_t offset + case ESP_GATTC_WRITE_CHAR_EVT: + { + log_v( + "[status: %s, conn_id: %d, handle: %d 0x%.2x, offset: %d]", BLEUtils::gattStatusToString(evtParam->write.status).c_str(), evtParam->write.conn_id, + evtParam->write.handle, evtParam->write.handle, evtParam->write.offset + ); + break; + } // ESP_GATTC_WRITE_CHAR_EVT +#endif + default: break; + } +} // dumpGattClientEvent + +/** + * @brief Dump the details of a GATT server event. + * A GATT Server event is a callback received from the BLE subsystem when we are acting as a BLE + * server. The callback indicates the type of event in the `event` field. The `evtParam` is a + * union of structures where we can use the `event` to indicate which of the structures has been + * populated and hence is valid. + * + * @param [in] event The event type that was posted. + * @param [in] evtParam A union of structures only one of which is populated. + */ +void BLEUtils::dumpGattServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *evtParam) { + log_v("GATT ServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str()); + switch (event) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + { + log_v( + "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char_descr.status).c_str(), + evtParam->add_char_descr.attr_handle, evtParam->add_char_descr.attr_handle, evtParam->add_char_descr.service_handle, + evtParam->add_char_descr.service_handle, BLEUUID(evtParam->add_char_descr.descr_uuid).toString().c_str() + ); + break; + } // ESP_GATTS_ADD_CHAR_DESCR_EVT + + case ESP_GATTS_ADD_CHAR_EVT: + { + if (evtParam->add_char.status == ESP_GATT_OK) { + log_v( + "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char.status).c_str(), + evtParam->add_char.attr_handle, evtParam->add_char.attr_handle, evtParam->add_char.service_handle, evtParam->add_char.service_handle, + BLEUUID(evtParam->add_char.char_uuid).toString().c_str() + ); + } else { + log_e( + "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char.status).c_str(), + evtParam->add_char.attr_handle, evtParam->add_char.attr_handle, evtParam->add_char.service_handle, evtParam->add_char.service_handle, + BLEUUID(evtParam->add_char.char_uuid).toString().c_str() + ); + } + break; + } // ESP_GATTS_ADD_CHAR_EVT + + // ESP_GATTS_CONF_EVT + // + // conf: + // - esp_gatt_status_t status – The status code. + // - uint16_t conn_id – The connection used. + case ESP_GATTS_CONF_EVT: + { + log_v("[status: %s, conn_id: 0x%.2x]", gattStatusToString(evtParam->conf.status).c_str(), evtParam->conf.conn_id); + break; + } // ESP_GATTS_CONF_EVT + + case ESP_GATTS_CONGEST_EVT: + { + log_v("[conn_id: %d, congested: %d]", evtParam->congest.conn_id, evtParam->congest.congested); + break; + } // ESP_GATTS_CONGEST_EVT + + case ESP_GATTS_CONNECT_EVT: + { + log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str()); + break; + } // ESP_GATTS_CONNECT_EVT + + case ESP_GATTS_CREATE_EVT: + { + log_v( + "[status: %s, service_handle: %d 0x%.2x, service_id: [%s]]", gattStatusToString(evtParam->create.status).c_str(), evtParam->create.service_handle, + evtParam->create.service_handle, gattServiceIdToString(evtParam->create.service_id).c_str() + ); + break; + } // ESP_GATTS_CREATE_EVT + + case ESP_GATTS_DISCONNECT_EVT: + { + log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str()); + break; + } // ESP_GATTS_DISCONNECT_EVT + + // ESP_GATTS_EXEC_WRITE_EVT + // exec_write: + // - uint16_t conn_id + // - uint32_t trans_id + // - esp_bd_addr_t bda + // - uint8_t exec_write_flag +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + case ESP_GATTS_EXEC_WRITE_EVT: + { + char *pWriteFlagText; + switch (evtParam->exec_write.exec_write_flag) { + case ESP_GATT_PREP_WRITE_EXEC: + { + pWriteFlagText = (char *)"WRITE"; + break; + } + + case ESP_GATT_PREP_WRITE_CANCEL: + { + pWriteFlagText = (char *)"CANCEL"; + break; + } + + default: pWriteFlagText = (char *)""; break; + } + + log_v( + "[conn_id: %d, trans_id: %d, bda: %s, exec_write_flag: 0x%.2x=%s]", evtParam->exec_write.conn_id, evtParam->exec_write.trans_id, + BLEAddress(evtParam->exec_write.bda).toString().c_str(), evtParam->exec_write.exec_write_flag, pWriteFlagText + ); + break; + } // ESP_GATTS_DISCONNECT_EVT +#endif + + case ESP_GATTS_MTU_EVT: + { + log_v("[conn_id: %d, mtu: %d]", evtParam->mtu.conn_id, evtParam->mtu.mtu); + break; + } // ESP_GATTS_MTU_EVT + + case ESP_GATTS_READ_EVT: + { + log_v( + "[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, is_long: %d, need_rsp:%d]", evtParam->read.conn_id, evtParam->read.trans_id, + BLEAddress(evtParam->read.bda).toString().c_str(), evtParam->read.handle, evtParam->read.is_long, evtParam->read.need_rsp + ); + break; + } // ESP_GATTS_READ_EVT + + case ESP_GATTS_RESPONSE_EVT: + { + log_v("[status: %s, handle: 0x%.2x]", gattStatusToString(evtParam->rsp.status).c_str(), evtParam->rsp.handle); + break; + } // ESP_GATTS_RESPONSE_EVT + + case ESP_GATTS_REG_EVT: + { + log_v("[status: %s, app_id: %d]", gattStatusToString(evtParam->reg.status).c_str(), evtParam->reg.app_id); + break; + } // ESP_GATTS_REG_EVT + + // ESP_GATTS_START_EVT + // + // start: + // - esp_gatt_status_t status + // - uint16_t service_handle + case ESP_GATTS_START_EVT: + { + log_v("[status: %s, service_handle: 0x%.2x]", gattStatusToString(evtParam->start.status).c_str(), evtParam->start.service_handle); + break; + } // ESP_GATTS_START_EVT + + // ESP_GATTS_WRITE_EVT + // + // write: + // - uint16_t conn_id – The connection id. + // - uint16_t trans_id – The transfer id. + // - esp_bd_addr_t bda – The address of the partner. + // - uint16_t handle – The attribute handle. + // - uint16_t offset – The offset of the currently received within the whole value. + // - bool need_rsp – Do we need a response? + // - bool is_prep – Is this a write prepare? If set, then this is to be considered part of the received value and not the whole value. A subsequent ESP_GATTS_EXEC_WRITE will mark the total. + // - uint16_t len – The length of the incoming value part. + // - uint8_t* value – The data for this value part. + case ESP_GATTS_WRITE_EVT: + { + log_v( + "[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, offset: %d, need_rsp: %d, is_prep: %d, len: %d]", evtParam->write.conn_id, + evtParam->write.trans_id, BLEAddress(evtParam->write.bda).toString().c_str(), evtParam->write.handle, evtParam->write.offset, evtParam->write.need_rsp, + evtParam->write.is_prep, evtParam->write.len + ); + char *pHex = buildHexData(nullptr, evtParam->write.value, evtParam->write.len); + log_v("[Data: %s]", pHex); + free(pHex); + break; + } // ESP_GATTS_WRITE_EVT +#endif + default: log_v("dumpGattServerEvent: *** NOT CODED ***"); break; + } +} // dumpGattServerEvent + +/** + * @brief Convert a BLE event type to a string. + * @param [in] eventType The event type. + * @return The event type as a string. + */ +const char *BLEUtils::eventTypeToString(esp_ble_evt_type_t eventType) { + switch (eventType) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_BLE_EVT_CONN_ADV: return "ESP_BLE_EVT_CONN_ADV"; + case ESP_BLE_EVT_CONN_DIR_ADV: return "ESP_BLE_EVT_CONN_DIR_ADV"; + case ESP_BLE_EVT_DISC_ADV: return "ESP_BLE_EVT_DISC_ADV"; + case ESP_BLE_EVT_NON_CONN_ADV: return "ESP_BLE_EVT_NON_CONN_ADV"; + case ESP_BLE_EVT_SCAN_RSP: return "ESP_BLE_EVT_SCAN_RSP"; +#endif + default: log_v("Unknown esp_ble_evt_type_t: %d (0x%.2x)", eventType, eventType); return "*** Unknown ***"; + } +} // eventTypeToString + +/** + * @brief Convert a BT GAP event type to a string representation. + * @param [in] eventType The type of event. + * @return A string representation of the event type. + */ +const char *BLEUtils::gapEventToString(uint32_t eventType) { + switch (eventType) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: return "ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT"; + case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: return "ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT"; + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: return "ESP_GAP_BLE_ADV_START_COMPLETE_EVT"; + case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: /* !< When stop adv complete, the event comes */ return "ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT"; + case ESP_GAP_BLE_AUTH_CMPL_EVT: /* Authentication complete indication. */ return "ESP_GAP_BLE_AUTH_CMPL_EVT"; + case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT: return "ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT"; + case ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT: return "ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT"; + case ESP_GAP_BLE_KEY_EVT: /* BLE key event for peer device keys */ return "ESP_GAP_BLE_KEY_EVT"; + case ESP_GAP_BLE_LOCAL_IR_EVT: /* BLE local IR event */ return "ESP_GAP_BLE_LOCAL_IR_EVT"; + case ESP_GAP_BLE_LOCAL_ER_EVT: /* BLE local ER event */ return "ESP_GAP_BLE_LOCAL_ER_EVT"; + case ESP_GAP_BLE_NC_REQ_EVT: /* Numeric Comparison request event */ return "ESP_GAP_BLE_NC_REQ_EVT"; + case ESP_GAP_BLE_OOB_REQ_EVT: /* OOB request event */ return "ESP_GAP_BLE_OOB_REQ_EVT"; + case ESP_GAP_BLE_PASSKEY_NOTIF_EVT: /* passkey notification event */ return "ESP_GAP_BLE_PASSKEY_NOTIF_EVT"; + case ESP_GAP_BLE_PASSKEY_REQ_EVT: /* passkey request event */ return "ESP_GAP_BLE_PASSKEY_REQ_EVT"; + case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT: return "ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT"; + case ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT: return "ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT"; + case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT"; + case ESP_GAP_BLE_SCAN_RESULT_EVT: return "ESP_GAP_BLE_SCAN_RESULT_EVT"; + case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT"; + case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT"; + case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_START_COMPLETE_EVT"; + case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT"; + case ESP_GAP_BLE_SEC_REQ_EVT: /* BLE security request */ return "ESP_GAP_BLE_SEC_REQ_EVT"; + case ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT: return "ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT"; + case ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT: return "ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT"; + case ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT: return "ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT"; + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: return "ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT"; +#endif + default: log_v("gapEventToString: Unknown event type %d 0x%.2x", eventType, eventType); return "Unknown event type"; + } +} // gapEventToString + +String BLEUtils::gattCharacteristicUUIDToString(uint32_t characteristicUUID) { + const characteristicMap_t *p = g_characteristicsMappings; + while (strlen(p->name) > 0) { + if (p->assignedNumber == characteristicUUID) { + return String(p->name); + } + p++; + } + return "Unknown"; +} // gattCharacteristicUUIDToString + +/** + * @brief Given the UUID for a BLE defined descriptor, return its string representation. + * @param [in] descriptorUUID UUID of the descriptor to be returned as a string. + * @return The string representation of a descriptor UUID. + */ +String BLEUtils::gattDescriptorUUIDToString(uint32_t descriptorUUID) { + gattdescriptor_t *p = (gattdescriptor_t *)g_descriptor_ids; + while (strlen(p->name) > 0) { + if (p->assignedNumber == descriptorUUID) { + return String(p->name); + } + p++; + } + return ""; +} // gattDescriptorUUIDToString + +/** + * @brief Return a string representation of an esp_gattc_service_elem_t. + * @return A string representation of an esp_gattc_service_elem_t. + */ +String BLEUtils::gattcServiceElementToString(esp_gattc_service_elem_t *pGATTCServiceElement) { + String res; + char val[6]; + res += "[uuid: " + BLEUUID(pGATTCServiceElement->uuid).toString() + ", start_handle: "; + snprintf(val, sizeof(val), "%d", pGATTCServiceElement->start_handle); + res += val; + res += " 0x"; + snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->start_handle); + res += val; + res += ", end_handle: "; + snprintf(val, sizeof(val), "%d", pGATTCServiceElement->end_handle); + res += val; + res += " 0x"; + snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->end_handle); + res += val; + res += "]"; + return res; +} // gattcServiceElementToString + +/** + * @brief Convert an esp_gatt_srvc_id_t to a string. + */ +String BLEUtils::gattServiceIdToString(esp_gatt_srvc_id_t srvcId) { + return gattIdToString(srvcId.id); +} // gattServiceIdToString + +String BLEUtils::gattServiceToString(uint32_t serviceId) { + gattService_t *p = (gattService_t *)g_gattServices; + while (strlen(p->name) > 0) { + if (p->assignedNumber == serviceId) { + return String(p->name); + } + p++; + } + return "Unknown"; +} // gattServiceToString + +/** + * @brief Convert a GATT status to a string. + * + * @param [in] status The status to convert. + * @return A string representation of the status. + */ +String BLEUtils::gattStatusToString(esp_gatt_status_t status) { + switch (status) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GATT_OK: return "ESP_GATT_OK"; + case ESP_GATT_INVALID_HANDLE: return "ESP_GATT_INVALID_HANDLE"; + case ESP_GATT_READ_NOT_PERMIT: return "ESP_GATT_READ_NOT_PERMIT"; + case ESP_GATT_WRITE_NOT_PERMIT: return "ESP_GATT_WRITE_NOT_PERMIT"; + case ESP_GATT_INVALID_PDU: return "ESP_GATT_INVALID_PDU"; + case ESP_GATT_INSUF_AUTHENTICATION: return "ESP_GATT_INSUF_AUTHENTICATION"; + case ESP_GATT_REQ_NOT_SUPPORTED: return "ESP_GATT_REQ_NOT_SUPPORTED"; + case ESP_GATT_INVALID_OFFSET: return "ESP_GATT_INVALID_OFFSET"; + case ESP_GATT_INSUF_AUTHORIZATION: return "ESP_GATT_INSUF_AUTHORIZATION"; + case ESP_GATT_PREPARE_Q_FULL: return "ESP_GATT_PREPARE_Q_FULL"; + case ESP_GATT_NOT_FOUND: return "ESP_GATT_NOT_FOUND"; + case ESP_GATT_NOT_LONG: return "ESP_GATT_NOT_LONG"; + case ESP_GATT_INSUF_KEY_SIZE: return "ESP_GATT_INSUF_KEY_SIZE"; + case ESP_GATT_INVALID_ATTR_LEN: return "ESP_GATT_INVALID_ATTR_LEN"; + case ESP_GATT_ERR_UNLIKELY: return "ESP_GATT_ERR_UNLIKELY"; + case ESP_GATT_INSUF_ENCRYPTION: return "ESP_GATT_INSUF_ENCRYPTION"; + case ESP_GATT_UNSUPPORT_GRP_TYPE: return "ESP_GATT_UNSUPPORT_GRP_TYPE"; + case ESP_GATT_INSUF_RESOURCE: return "ESP_GATT_INSUF_RESOURCE"; + case ESP_GATT_NO_RESOURCES: return "ESP_GATT_NO_RESOURCES"; + case ESP_GATT_INTERNAL_ERROR: return "ESP_GATT_INTERNAL_ERROR"; + case ESP_GATT_WRONG_STATE: return "ESP_GATT_WRONG_STATE"; + case ESP_GATT_DB_FULL: return "ESP_GATT_DB_FULL"; + case ESP_GATT_BUSY: return "ESP_GATT_BUSY"; + case ESP_GATT_ERROR: return "ESP_GATT_ERROR"; + case ESP_GATT_CMD_STARTED: return "ESP_GATT_CMD_STARTED"; + case ESP_GATT_ILLEGAL_PARAMETER: return "ESP_GATT_ILLEGAL_PARAMETER"; + case ESP_GATT_PENDING: return "ESP_GATT_PENDING"; + case ESP_GATT_AUTH_FAIL: return "ESP_GATT_AUTH_FAIL"; + case ESP_GATT_MORE: return "ESP_GATT_MORE"; + case ESP_GATT_INVALID_CFG: return "ESP_GATT_INVALID_CFG"; + case ESP_GATT_SERVICE_STARTED: return "ESP_GATT_SERVICE_STARTED"; + case ESP_GATT_ENCRYPTED_NO_MITM: return "ESP_GATT_ENCRYPTED_NO_MITM"; + case ESP_GATT_NOT_ENCRYPTED: return "ESP_GATT_NOT_ENCRYPTED"; + case ESP_GATT_CONGESTED: return "ESP_GATT_CONGESTED"; + case ESP_GATT_DUP_REG: return "ESP_GATT_DUP_REG"; + case ESP_GATT_ALREADY_OPEN: return "ESP_GATT_ALREADY_OPEN"; + case ESP_GATT_CANCEL: return "ESP_GATT_CANCEL"; + case ESP_GATT_STACK_RSP: return "ESP_GATT_STACK_RSP"; + case ESP_GATT_APP_RSP: return "ESP_GATT_APP_RSP"; + case ESP_GATT_UNKNOWN_ERROR: return "ESP_GATT_UNKNOWN_ERROR"; + case ESP_GATT_CCC_CFG_ERR: return "ESP_GATT_CCC_CFG_ERR"; + case ESP_GATT_PRC_IN_PROGRESS: return "ESP_GATT_PRC_IN_PROGRESS"; + case ESP_GATT_OUT_OF_RANGE: return "ESP_GATT_OUT_OF_RANGE"; +#endif + default: return "Unknown"; + } +} // gattStatusToString + +String BLEUtils::getMember(uint32_t memberId) { + member_t *p = (member_t *)members_ids; + + while (strlen(p->name) > 0) { + if (p->assignedNumber == memberId) { + return String(p->name); + } + p++; + } + return "Unknown"; +} + +/** + * @brief convert a GAP search event to a string. + * @param [in] searchEvt + * @return The search event type as a string. + */ +const char *BLEUtils::searchEventTypeToString(esp_gap_search_evt_t searchEvt) { + switch (searchEvt) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_GAP_SEARCH_INQ_RES_EVT: return "ESP_GAP_SEARCH_INQ_RES_EVT"; + case ESP_GAP_SEARCH_INQ_CMPL_EVT: return "ESP_GAP_SEARCH_INQ_CMPL_EVT"; + case ESP_GAP_SEARCH_DISC_RES_EVT: return "ESP_GAP_SEARCH_DISC_RES_EVT"; + case ESP_GAP_SEARCH_DISC_BLE_RES_EVT: return "ESP_GAP_SEARCH_DISC_BLE_RES_EVT"; + case ESP_GAP_SEARCH_DISC_CMPL_EVT: return "ESP_GAP_SEARCH_DISC_CMPL_EVT"; + case ESP_GAP_SEARCH_DI_DISC_CMPL_EVT: return "ESP_GAP_SEARCH_DI_DISC_CMPL_EVT"; + case ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT: return "ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT"; +#endif + default: log_v("Unknown event type: 0x%x", searchEvt); return "Unknown event type"; + } +} // searchEventTypeToString + +#endif // CONFIG_BLUEDROID_ENABLED + +/***************************************************************************** + * NimBLE functions * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief Construct a BLETaskData instance. + * @param [in] pInstance An instance of the class that will be waiting. + * @param [in] flags General purpose flags for the caller. + * @param [in] buf A buffer for data. + */ +BLETaskData::BLETaskData(void *pInstance, int flags, void *buf) : m_pInstance{pInstance}, m_flags{flags}, m_pBuf{buf}, m_pHandle{xTaskGetCurrentTaskHandle()} {} + +/** + * @brief Destructor. + */ +BLETaskData::~BLETaskData() {} + +/** + * @brief A function for checking validity of connection parameters. + * @param [in] params A pointer to the structure containing the parameters to check. + * @return valid == 0 or error code. + */ +int BLEUtils::checkConnParams(ble_gap_conn_params *params) { + /* Check connection interval min */ + if ((params->itvl_min < BLE_HCI_CONN_ITVL_MIN) || (params->itvl_min > BLE_HCI_CONN_ITVL_MAX)) { + return BLE_ERR_INV_HCI_CMD_PARMS; + } + /* Check connection interval max */ + if ((params->itvl_max < BLE_HCI_CONN_ITVL_MIN) || (params->itvl_max > BLE_HCI_CONN_ITVL_MAX) || (params->itvl_max < params->itvl_min)) { + return BLE_ERR_INV_HCI_CMD_PARMS; + } + + /* Check connection latency */ + if (params->latency > BLE_HCI_CONN_LATENCY_MAX) { + return BLE_ERR_INV_HCI_CMD_PARMS; + } + + /* Check supervision timeout */ + if ((params->supervision_timeout < BLE_HCI_CONN_SPVN_TIMEOUT_MIN) || (params->supervision_timeout > BLE_HCI_CONN_SPVN_TIMEOUT_MAX)) { + return BLE_ERR_INV_HCI_CMD_PARMS; + } + + /* Check connection event length */ + if (params->min_ce_len > params->max_ce_len) { + return BLE_ERR_INV_HCI_CMD_PARMS; + } + + return 0; +} + +/** + * @brief Converts a return code from the NimBLE stack to a text string. + * @param [in] rc The return code to convert. + * @return A string representation of the return code. + */ +const char *BLEUtils::returnCodeToString(int rc) { +#if defined(CONFIG_NIMBLE_ENABLE_RETURN_CODE_TEXT) + switch (rc) { + case 0: return "SUCCESS"; + case BLE_HS_EAGAIN: return "Temporary failure; try again."; + case BLE_HS_EALREADY: return "Operation already in progress or completed."; + case BLE_HS_EINVAL: return "One or more arguments are invalid."; + case BLE_HS_EMSGSIZE: return "The provided buffer is too small."; + case BLE_HS_ENOENT: return "No entry matching the specified criteria."; + case BLE_HS_ENOMEM: return "Operation failed due to resource exhaustion."; + case BLE_HS_ENOTCONN: return "No open connection with the specified handle."; + case BLE_HS_ENOTSUP: return "Operation disabled at compile time."; + case BLE_HS_EAPP: return "Application callback behaved unexpectedly."; + case BLE_HS_EBADDATA: return "Command from peer is invalid."; + case BLE_HS_EOS: return "Mynewt OS error."; + case BLE_HS_ECONTROLLER: return "Event from controller is invalid."; + case BLE_HS_ETIMEOUT: return "Operation timed out."; + case BLE_HS_EDONE: return "Operation completed successfully."; + case BLE_HS_EBUSY: return "Operation cannot be performed until procedure completes."; + case BLE_HS_EREJECT: return "Peer rejected a connection parameter update request."; + case BLE_HS_EUNKNOWN: return "Unexpected failure; catch all."; + case BLE_HS_EROLE: return "Operation requires different role (e.g., central vs. peripheral)."; + case BLE_HS_ETIMEOUT_HCI: return "HCI request timed out; controller unresponsive."; + case BLE_HS_ENOMEM_EVT: return "Controller failed to send event due to memory exhaustion (combined host-controller only)."; + case BLE_HS_ENOADDR: return "Operation requires an identity address but none configured."; + case BLE_HS_ENOTSYNCED: return "Attempt to use the host before it is synced with controller."; + case BLE_HS_EAUTHEN: return "Insufficient authentication."; + case BLE_HS_EAUTHOR: return "Insufficient authorization."; + case BLE_HS_EENCRYPT: return "Insufficient encryption level."; + case BLE_HS_EENCRYPT_KEY_SZ: return "Insufficient key size."; + case BLE_HS_ESTORE_CAP: return "Storage at capacity."; + case BLE_HS_ESTORE_FAIL: return "Storage IO error."; + case BLE_HS_EPREEMPTED: return "Operation was preempted."; + case BLE_HS_EDISABLED: return "Operation disabled."; + case BLE_HS_ESTALLED: return "Operation stalled."; + case (0x0100 + BLE_ATT_ERR_INVALID_HANDLE): return "The attribute handle given was not valid on this server."; + case (0x0100 + BLE_ATT_ERR_READ_NOT_PERMITTED): return "The attribute cannot be read."; + case (0x0100 + BLE_ATT_ERR_WRITE_NOT_PERMITTED): return "The attribute cannot be written."; + case (0x0100 + BLE_ATT_ERR_INVALID_PDU): return "The attribute PDU was invalid."; + case (0x0100 + BLE_ATT_ERR_INSUFFICIENT_AUTHEN): return "The attribute requires authentication before it can be read or written."; + case (0x0100 + BLE_ATT_ERR_REQ_NOT_SUPPORTED): return "Attribute server does not support the request received from the client."; + case (0x0100 + BLE_ATT_ERR_INVALID_OFFSET): return "Offset specified was past the end of the attribute."; + case (0x0100 + BLE_ATT_ERR_INSUFFICIENT_AUTHOR): return "The attribute requires authorization before it can be read or written."; + case (0x0100 + BLE_ATT_ERR_PREPARE_QUEUE_FULL): return "Too many prepare writes have been queued."; + case (0x0100 + BLE_ATT_ERR_ATTR_NOT_FOUND): return "No attribute found within the given attribute handle range."; + case (0x0100 + BLE_ATT_ERR_ATTR_NOT_LONG): return "The attribute cannot be read or written using the Read Blob Request."; + case (0x0100 + BLE_ATT_ERR_INSUFFICIENT_KEY_SZ): return "The Encryption Key Size used for encrypting this link is insufficient."; + case (0x0100 + BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN): return "The attribute value length is invalid for the operation."; + case (0x0100 + BLE_ATT_ERR_UNLIKELY): return "The attribute request has encountered an error that was unlikely, could not be completed as requested."; + case (0x0100 + BLE_ATT_ERR_INSUFFICIENT_ENC): return "The attribute requires encryption before it can be read or written."; + case (0x0100 + BLE_ATT_ERR_UNSUPPORTED_GROUP): + return "The attribute type is not a supported grouping attribute as defined by a higher layer specification."; + case (0x0100 + BLE_ATT_ERR_INSUFFICIENT_RES): return "Insufficient Resources to complete the request."; + case (0x0200 + BLE_ERR_UNKNOWN_HCI_CMD): return "Unknown HCI Command"; + case (0x0200 + BLE_ERR_UNK_CONN_ID): return "Unknown Connection Identifier"; + case (0x0200 + BLE_ERR_HW_FAIL): return "Hardware Failure"; + case (0x0200 + BLE_ERR_PAGE_TMO): return "Page Timeout"; + case (0x0200 + BLE_ERR_AUTH_FAIL): return "Authentication Failure"; + case (0x0200 + BLE_ERR_PINKEY_MISSING): return "PIN or Key Missing"; + case (0x0200 + BLE_ERR_MEM_CAPACITY): return "Memory Capacity Exceeded"; + case (0x0200 + BLE_ERR_CONN_SPVN_TMO): return "Connection Timeout"; + case (0x0200 + BLE_ERR_CONN_LIMIT): return "Connection Limit Exceeded"; + case (0x0200 + BLE_ERR_SYNCH_CONN_LIMIT): return "Synchronous Connection Limit To A Device Exceeded"; + case (0x0200 + BLE_ERR_ACL_CONN_EXISTS): return "ACL Connection Already Exists"; + case (0x0200 + BLE_ERR_CMD_DISALLOWED): return "Command Disallowed"; + case (0x0200 + BLE_ERR_CONN_REJ_RESOURCES): return "Connection Rejected due to Limited Resources"; + case (0x0200 + BLE_ERR_CONN_REJ_SECURITY): return "Connection Rejected Due To Security Reasons"; + case (0x0200 + BLE_ERR_CONN_REJ_BD_ADDR): return "Connection Rejected due to Unacceptable BD_ADDR"; + case (0x0200 + BLE_ERR_CONN_ACCEPT_TMO): return "Connection Accept Timeout Exceeded"; + case (0x0200 + BLE_ERR_UNSUPPORTED): return "Unsupported Feature or Parameter Value"; + case (0x0200 + BLE_ERR_INV_HCI_CMD_PARMS): return "Invalid HCI Command Parameters"; + case (0x0200 + BLE_ERR_REM_USER_CONN_TERM): return "Remote User Terminated Connection"; + case (0x0200 + BLE_ERR_RD_CONN_TERM_RESRCS): return "Remote Device Terminated Connection due to Low Resources"; + case (0x0200 + BLE_ERR_RD_CONN_TERM_PWROFF): return "Remote Device Terminated Connection due to Power Off"; + case (0x0200 + BLE_ERR_CONN_TERM_LOCAL): return "Connection Terminated By Local Host"; + case (0x0200 + BLE_ERR_REPEATED_ATTEMPTS): return "Repeated Attempts"; + case (0x0200 + BLE_ERR_NO_PAIRING): return "Pairing Not Allowed"; + case (0x0200 + BLE_ERR_UNK_LMP): return "Unknown LMP PDU"; + case (0x0200 + BLE_ERR_UNSUPP_REM_FEATURE): return "Unsupported Remote Feature / Unsupported LMP Feature"; + case (0x0200 + BLE_ERR_SCO_OFFSET): return "SCO Offset Rejected"; + case (0x0200 + BLE_ERR_SCO_ITVL): return "SCO Interval Rejected"; + case (0x0200 + BLE_ERR_SCO_AIR_MODE): return "SCO Air Mode Rejected"; + case (0x0200 + BLE_ERR_INV_LMP_LL_PARM): return "Invalid LMP Parameters / Invalid LL Parameters"; + case (0x0200 + BLE_ERR_UNSPECIFIED): return "Unspecified Error"; + case (0x0200 + BLE_ERR_UNSUPP_LMP_LL_PARM): return "Unsupported LMP Parameter Value / Unsupported LL Parameter Value"; + case (0x0200 + BLE_ERR_NO_ROLE_CHANGE): return "Role Change Not Allowed"; + case (0x0200 + BLE_ERR_LMP_LL_RSP_TMO): return "LMP Response Timeout / LL Response Timeout"; + case (0x0200 + BLE_ERR_LMP_COLLISION): return "LMP Error Transaction Collision"; + case (0x0200 + BLE_ERR_LMP_PDU): return "LMP PDU Not Allowed"; + case (0x0200 + BLE_ERR_ENCRYPTION_MODE): return "Encryption Mode Not Acceptable"; + case (0x0200 + BLE_ERR_LINK_KEY_CHANGE): return "Link Key cannot be Changed"; + case (0x0200 + BLE_ERR_UNSUPP_QOS): return "Requested QoS Not Supported"; + case (0x0200 + BLE_ERR_INSTANT_PASSED): return "Instant Passed"; + case (0x0200 + BLE_ERR_UNIT_KEY_PAIRING): return "Pairing With Unit Key Not Supported"; + case (0x0200 + BLE_ERR_DIFF_TRANS_COLL): return "Different Transaction Collision"; + case (0x0200 + BLE_ERR_QOS_PARM): return "QoS Unacceptable Parameter"; + case (0x0200 + BLE_ERR_QOS_REJECTED): return "QoS Rejected"; + case (0x0200 + BLE_ERR_CHAN_CLASS): return "Channel Classification Not Supported"; + case (0x0200 + BLE_ERR_INSUFFICIENT_SEC): return "Insufficient Security"; + case (0x0200 + BLE_ERR_PARM_OUT_OF_RANGE): return "Parameter Out Of Mandatory Range"; + case (0x0200 + BLE_ERR_PENDING_ROLE_SW): return "Role Switch Pending"; + case (0x0200 + BLE_ERR_RESERVED_SLOT): return "Reserved Slot Violation"; + case (0x0200 + BLE_ERR_ROLE_SW_FAIL): return "Role Switch Failed"; + case (0x0200 + BLE_ERR_INQ_RSP_TOO_BIG): return "Extended Inquiry Response Too Large"; + case (0x0200 + BLE_ERR_SEC_SIMPLE_PAIR): return "Secure Simple Pairing Not Supported By Host"; + case (0x0200 + BLE_ERR_HOST_BUSY_PAIR): return "Host Busy - Pairing"; + case (0x0200 + BLE_ERR_CONN_REJ_CHANNEL): return "Connection Rejected, No Suitable Channel Found"; + case (0x0200 + BLE_ERR_CTLR_BUSY): return "Controller Busy"; + case (0x0200 + BLE_ERR_CONN_PARMS): return "Unacceptable Connection Parameters"; + case (0x0200 + BLE_ERR_DIR_ADV_TMO): return "Directed Advertising Timeout"; + case (0x0200 + BLE_ERR_CONN_TERM_MIC): return "Connection Terminated due to MIC Failure"; + case (0x0200 + BLE_ERR_CONN_ESTABLISHMENT): return "Connection Failed to be Established"; + case (0x0200 + BLE_ERR_MAC_CONN_FAIL): return "MAC Connection Failed"; + case (0x0200 + BLE_ERR_COARSE_CLK_ADJ): return "Coarse Clock Adjustment Rejected"; + case (0x0300 + BLE_L2CAP_SIG_ERR_CMD_NOT_UNDERSTOOD): return "Invalid or unsupported incoming L2CAP sig command."; + case (0x0300 + BLE_L2CAP_SIG_ERR_MTU_EXCEEDED): return "Incoming packet too large."; + case (0x0300 + BLE_L2CAP_SIG_ERR_INVALID_CID): return "No channel with specified ID."; + case (0x0400 + BLE_SM_ERR_PASSKEY): return "The user input of passkey failed, for example, the user canceled the operation."; + case (0x0400 + BLE_SM_ERR_OOB): return "The OOB data is not available."; + case (0x0400 + BLE_SM_ERR_AUTHREQ): + return "The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices."; + case (0x0400 + BLE_SM_ERR_CONFIRM_MISMATCH): return "The confirm value does not match the calculated compare value."; + case (0x0400 + BLE_SM_ERR_PAIR_NOT_SUPP): return "Pairing is not supported by the device."; + case (0x0400 + BLE_SM_ERR_ENC_KEY_SZ): return "The resultant encryption key size is insufficient for the security requirements of this device."; + case (0x0400 + BLE_SM_ERR_CMD_NOT_SUPP): return "The SMP command received is not supported on this device."; + case (0x0400 + BLE_SM_ERR_UNSPECIFIED): return "Pairing failed due to an unspecified reason."; + case (0x0400 + BLE_SM_ERR_REPEATED): + return "Pairing or authentication procedure disallowed, too little time has elapsed since last pairing request or security request."; + case (0x0400 + BLE_SM_ERR_INVAL): return "Command length is invalid or that a parameter is outside of the specified range."; + case (0x0400 + BLE_SM_ERR_DHKEY): return "DHKey Check value received doesn't match the one calculated by the local device."; + case (0x0400 + BLE_SM_ERR_NUMCMP): return "Confirm values in the numeric comparison protocol do not match."; + case (0x0400 + BLE_SM_ERR_ALREADY): return "Pairing over the LE transport failed - Pairing Request sent over the BR/EDR transport in process."; + case (0x0400 + BLE_SM_ERR_CROSS_TRANS): + return "BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport."; + case (0x0500 + BLE_SM_ERR_PASSKEY): return "The user input of passkey failed or the user canceled the operation."; + case (0x0500 + BLE_SM_ERR_OOB): return "The OOB data is not available."; + case (0x0500 + BLE_SM_ERR_AUTHREQ): + return "The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices."; + case (0x0500 + BLE_SM_ERR_CONFIRM_MISMATCH): return "The confirm value does not match the calculated compare value."; + case (0x0500 + BLE_SM_ERR_PAIR_NOT_SUPP): return "Pairing is not supported by the device."; + case (0x0500 + BLE_SM_ERR_ENC_KEY_SZ): return "The resultant encryption key size is insufficient for the security requirements of this device."; + case (0x0500 + BLE_SM_ERR_CMD_NOT_SUPP): return "The SMP command received is not supported on this device."; + case (0x0500 + BLE_SM_ERR_UNSPECIFIED): return "Pairing failed due to an unspecified reason."; + case (0x0500 + BLE_SM_ERR_REPEATED): + return "Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request."; + case (0x0500 + BLE_SM_ERR_INVAL): return "Command length is invalid or a parameter is outside of the specified range."; + case (0x0500 + BLE_SM_ERR_DHKEY): + return "Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device."; + case (0x0500 + BLE_SM_ERR_NUMCMP): return "Confirm values in the numeric comparison protocol do not match."; + case (0x0500 + BLE_SM_ERR_ALREADY): return "Pairing over the LE transport failed - Pairing Request sent over the BR/EDR transport in process."; + case (0x0500 + BLE_SM_ERR_CROSS_TRANS): + return "BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport."; + default: return "Unknown"; + } +#else // #if defined(CONFIG_NIMBLE_ENABLE_RETURN_CODE_TEXT) + return ""; +#endif // #if defined(CONFIG_NIMBLE_ENABLE_RETURN_CODE_TEXT) +} + +/** + * @brief Utility function to log the gap event info. + * @param [in] event A pointer to the gap event structure. + * @param [in] arg Unused. + */ +void BLEUtils::dumpGapEvent(ble_gap_event *event, void *arg) { +#if defined(CONFIG_NIMBLE_ENABLE_GAP_EVENT_CODE_TEXT) + log_d("Received a GAP event: %s", gapEventToString(event->type)); +#endif +} + +/** + * @brief Convert a GAP event type to a string representation. + * @param [in] eventType The type of event. + * @return A string representation of the event type. + */ +const char *BLEUtils::gapEventToString(uint8_t eventType) { +#if defined(CONFIG_NIMBLE_ENABLE_GAP_EVENT_CODE_TEXT) + switch (eventType) { + case BLE_GAP_EVENT_CONNECT: //0 + return "BLE_GAP_EVENT_CONNECT "; + + case BLE_GAP_EVENT_DISCONNECT: //1 + return "BLE_GAP_EVENT_DISCONNECT"; + + case BLE_GAP_EVENT_CONN_UPDATE: //3 + return "BLE_GAP_EVENT_CONN_UPDATE"; + + case BLE_GAP_EVENT_CONN_UPDATE_REQ: //4 + return "BLE_GAP_EVENT_CONN_UPDATE_REQ"; + + case BLE_GAP_EVENT_L2CAP_UPDATE_REQ: //5 + return "BLE_GAP_EVENT_L2CAP_UPDATE_REQ"; + + case BLE_GAP_EVENT_TERM_FAILURE: //6 + return "BLE_GAP_EVENT_TERM_FAILURE"; + + case BLE_GAP_EVENT_DISC: //7 + return "BLE_GAP_EVENT_DISC"; + + case BLE_GAP_EVENT_DISC_COMPLETE: //8 + return "BLE_GAP_EVENT_DISC_COMPLETE"; + + case BLE_GAP_EVENT_ADV_COMPLETE: //9 + return "BLE_GAP_EVENT_ADV_COMPLETE"; + + case BLE_GAP_EVENT_ENC_CHANGE: //10 + return "BLE_GAP_EVENT_ENC_CHANGE"; + + case BLE_GAP_EVENT_PASSKEY_ACTION: //11 + return "BLE_GAP_EVENT_PASSKEY_ACTION"; + + case BLE_GAP_EVENT_NOTIFY_RX: //12 + return "BLE_GAP_EVENT_NOTIFY_RX"; + + case BLE_GAP_EVENT_NOTIFY_TX: //13 + return "BLE_GAP_EVENT_NOTIFY_TX"; + + case BLE_GAP_EVENT_SUBSCRIBE: //14 + return "BLE_GAP_EVENT_SUBSCRIBE"; + + case BLE_GAP_EVENT_MTU: //15 + return "BLE_GAP_EVENT_MTU"; + + case BLE_GAP_EVENT_IDENTITY_RESOLVED: //16 + return "BLE_GAP_EVENT_IDENTITY_RESOLVED"; + + case BLE_GAP_EVENT_REPEAT_PAIRING: //17 + return "BLE_GAP_EVENT_REPEAT_PAIRING"; + + case BLE_GAP_EVENT_PHY_UPDATE_COMPLETE: //18 + return "BLE_GAP_EVENT_PHY_UPDATE_COMPLETE"; + + case BLE_GAP_EVENT_EXT_DISC: //19 + return "BLE_GAP_EVENT_EXT_DISC"; + + case BLE_GAP_EVENT_AUTHORIZE: //32 + return "BLE_GAP_EVENT_AUTHORIZE"; +#ifdef BLE_GAP_EVENT_PERIODIC_SYNC // IDF 4.0 does not support these + case BLE_GAP_EVENT_PERIODIC_SYNC: //20 + return "BLE_GAP_EVENT_PERIODIC_SYNC"; + + case BLE_GAP_EVENT_PERIODIC_REPORT: //21 + return "BLE_GAP_EVENT_PERIODIC_REPORT"; + + case BLE_GAP_EVENT_PERIODIC_SYNC_LOST: //22 + return "BLE_GAP_EVENT_PERIODIC_SYNC_LOST"; + + case BLE_GAP_EVENT_SCAN_REQ_RCVD: //23 + return "BLE_GAP_EVENT_SCAN_REQ_RCVD"; +#endif + default: log_d("gapEventToString: Unknown event type %d 0x%.2x", eventType, eventType); return "Unknown event type"; + } +#else // #if defined(CONFIG_NIMBLE_ENABLE_GAP_EVENT_CODE_TEXT) + return ""; +#endif // #if defined(CONFIG_NIMBLE_ENABLE_GAP_EVENT_CODE_TEXT) +} // gapEventToString + +/** + * @brief Convert characteristic properties into a string representation. + * @param [in] prop Characteristic properties. + * @return A string representation of characteristic properties. + */ +String BLEUtils::characteristicPropertiesToString(uint8_t prop) { + String res = "broadcast: "; + res += ((prop & BLE_GATT_CHR_PROP_BROADCAST) ? "1" : "0"); + res += ", read: "; + res += ((prop & BLE_GATT_CHR_PROP_READ) ? "1" : "0"); + res += ", write_nr: "; + res += ((prop & BLE_GATT_CHR_PROP_WRITE_NO_RSP) ? "1" : "0"); + res += ", write: "; + res += ((prop & BLE_GATT_CHR_PROP_WRITE) ? "1" : "0"); + res += ", notify: "; + res += ((prop & BLE_GATT_CHR_PROP_NOTIFY) ? "1" : "0"); + res += ", indicate: "; + res += ((prop & BLE_GATT_CHR_PROP_INDICATE) ? "1" : "0"); + res += ", auth_sign_write: "; + res += ((prop & BLE_GATT_CHR_PROP_AUTH_SIGN_WRITE) ? "1" : "0"); + res += ", extended: "; + res += ((prop & BLE_GATT_CHR_PROP_EXTENDED) ? "1" : "0"); + return res; +} // characteristicPropertiesToString + +/** + * @brief Blocks the calling task until released or timeout. + * @param [in] taskData A pointer to the task data structure. + * @param [in] timeout The time to wait in milliseconds. + * @return True if the task completed, false if the timeout was reached. + */ +bool BLEUtils::taskWait(const BLETaskData &taskData, uint32_t timeout) { + ble_npl_time_t ticks; + if (timeout == BLE_NPL_TIME_FOREVER) { + ticks = BLE_NPL_TIME_FOREVER; + } else { + ble_npl_time_ms_to_ticks(timeout, &ticks); + } + + uint32_t notificationValue; + xTaskNotifyWait(0, TASK_BLOCK_BIT, ¬ificationValue, 0); + if (notificationValue & TASK_BLOCK_BIT) { + return true; + } + + return xTaskNotifyWait(0, TASK_BLOCK_BIT, nullptr, ticks) == pdTRUE; +} // taskWait + +/** + * @brief Release a task. + * @param [in] taskData A pointer to the task data structure. + * @param [in] flags A return value to set in the task data structure. + */ +void BLEUtils::taskRelease(const BLETaskData &taskData, int flags) { + taskData.m_flags = flags; + if (taskData.m_pHandle != nullptr) { + xTaskNotify(static_cast(taskData.m_pHandle), TASK_BLOCK_BIT, eSetBits); + } +} // taskRelease + +#endif // CONFIG_NIMBLE_ENABLED + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEUtils.h b/libraries/BLE/src/BLEUtils.h new file mode 100644 index 0000000..f66cdcf --- /dev/null +++ b/libraries/BLE/src/BLEUtils.h @@ -0,0 +1,153 @@ +/* + * BLEUtils.h + * + * Created on: Mar 25, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEUTILS_H_ +#define COMPONENTS_CPP_UTILS_BLEUTILS_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include +#include "BLEAddress.h" +#include "WString.h" +#include + +/***************************************************************************** + * Bluedroid includes * + *****************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) +#include +#include +#include +#endif + +/***************************************************************************** + * NimBLE includes * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) +#include +#include +#include +#endif + +/***************************************************************************** + * Common types * + *****************************************************************************/ + +typedef struct { + void *peer_device; // peer device BLEClient or BLEServer + bool connected; // connection status + uint16_t mtu; // negotiated MTU per peer device +} conn_status_t; + +/***************************************************************************** + * NimBLE types * + *****************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + +/** + * @brief A structure to hold data for a task that is waiting for a response. + * @details This structure is used in conjunction with BLEUtils::taskWait() and BLEUtils::taskRelease(). + * All items are optional, the m_pHandle will be set in taskWait(). + */ +struct BLETaskData { + BLETaskData(void *pInstance = nullptr, int flags = 0, void *buf = nullptr); + ~BLETaskData(); + void *m_pInstance{nullptr}; + mutable int m_flags{0}; + void *m_pBuf{nullptr}; + +private: + mutable void *m_pHandle{nullptr}; // semaphore or task handle + friend class BLEUtils; +}; + +#endif + +/***************************************************************************** + * Forward declarations * + *****************************************************************************/ + +class BLEClient; + +/** + * @brief A set of general %BLE utilities. + */ +class BLEUtils { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + static char *buildHexData(uint8_t *target, const uint8_t *source, uint8_t length); + static String buildPrintData(uint8_t *source, size_t length); + static const char *advDataTypeToString(uint8_t advType); + static String characteristicPropertiesToString(uint8_t prop); + + /*************************************************************************** + * Bluedroid public declarations * + ***************************************************************************/ + +#if defined(CONFIG_BLUEDROID_ENABLED) + static const char *addressTypeToString(esp_ble_addr_type_t type); + static String adFlagsToString(uint8_t adFlags); + static const char *devTypeToString(esp_bt_dev_type_t type); + static esp_gatt_id_t buildGattId(esp_bt_uuid_t uuid, uint8_t inst_id = 0); + static esp_gatt_srvc_id_t buildGattSrvcId(esp_gatt_id_t gattId, bool is_primary = true); + static void dumpGapEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); + static void dumpGattClientEvent(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam); + static void dumpGattServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *evtParam); + static const char *eventTypeToString(esp_ble_evt_type_t eventType); + static BLEClient *findByAddress(BLEAddress address); + static BLEClient *findByConnId(uint16_t conn_id); + static const char *gapEventToString(uint32_t eventType); + static String gattCharacteristicUUIDToString(uint32_t characteristicUUID); + static String gattClientEventTypeToString(esp_gattc_cb_event_t eventType); + static String gattCloseReasonToString(esp_gatt_conn_reason_t reason); + static String gattcServiceElementToString(esp_gattc_service_elem_t *pGATTCServiceElement); + static String gattDescriptorUUIDToString(uint32_t descriptorUUID); + static String gattServerEventTypeToString(esp_gatts_cb_event_t eventType); + static String gattServiceIdToString(esp_gatt_srvc_id_t srvcId); + static String gattServiceToString(uint32_t serviceId); + static String gattStatusToString(esp_gatt_status_t status); + static String getMember(uint32_t memberId); + static void registerByAddress(BLEAddress address, BLEClient *pDevice); + static void registerByConnId(uint16_t conn_id, BLEClient *pDevice); + static const char *searchEventTypeToString(esp_gap_search_evt_t searchEvt); +#endif + + /*************************************************************************** + * NimBLE public declarations * + ***************************************************************************/ + +#if defined(CONFIG_NIMBLE_ENABLED) + static void dumpGapEvent(ble_gap_event *event, void *arg); + static const char *gapEventToString(uint8_t eventType); + static const char *returnCodeToString(int rc); + static int checkConnParams(ble_gap_conn_params *params); + static bool taskWait(const BLETaskData &taskData, uint32_t timeout); + static void taskRelease(const BLETaskData &taskData, int rc = 0); +#endif +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEUTILS_H_ */ diff --git a/libraries/BLE/src/BLEValue.cpp b/libraries/BLE/src/BLEValue.cpp new file mode 100644 index 0000000..47a7b3d --- /dev/null +++ b/libraries/BLE/src/BLEValue.cpp @@ -0,0 +1,137 @@ +/* + * BLEValue.cpp + * + * Created on: Jul 17, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include "BLEValue.h" +#include "esp32-hal-log.h" + +/***************************************************************************** + * Common functions * + *****************************************************************************/ + +BLEValue::BLEValue() { + m_accumulation = ""; + m_value = ""; + m_readOffset = 0; +} // BLEValue + +/** + * @brief Add a message part to the accumulation. + * The accumulation is a growing set of data that is added to until a commit or cancel. + * @param [in] part A message part being added. + */ +void BLEValue::addPart(const String &part) { + log_v(">> addPart: length=%d", part.length()); + m_accumulation += part; +} // addPart + +/** + * @brief Add a message part to the accumulation. + * The accumulation is a growing set of data that is added to until a commit or cancel. + * @param [in] pData A message part being added. + * @param [in] length The number of bytes being added. + */ +void BLEValue::addPart(const uint8_t *pData, size_t length) { + log_v(">> addPart: length=%d", length); + m_accumulation += String((char *)pData, length); +} // addPart + +/** + * @brief Cancel the current accumulation. + */ +void BLEValue::cancel() { + log_v(">> cancel"); + m_accumulation = ""; + m_readOffset = 0; +} // cancel + +/** + * @brief Commit the current accumulation. + * When writing a value, we may find that we write it in "parts" meaning that the writes come in in pieces + * of the overall message. After the last part has been received, we may perform a commit which means that + * we now have the complete message and commit the change as a unit. + */ +void BLEValue::commit() { + log_v(">> commit"); + // If there is nothing to commit, do nothing. + if (m_accumulation.length() == 0) { + return; + } + setValue(m_accumulation); + m_accumulation = ""; + m_readOffset = 0; +} // commit + +/** + * @brief Get a pointer to the data. + * @return A pointer to the data. + */ +uint8_t *BLEValue::getData() { + return (uint8_t *)m_value.c_str(); +} + +/** + * @brief Get the length of the data in bytes. + * @return The length of the data in bytes. + */ +size_t BLEValue::getLength() const { + return m_value.length(); +} // getLength + +/** + * @brief Get the read offset. + * @return The read offset into the read. + */ +uint16_t BLEValue::getReadOffset() const { + return m_readOffset; +} // getReadOffset + +/** + * @brief Get the current value. + */ +String BLEValue::getValue() const { + return m_value; +} // getValue + +/** + * @brief Set the read offset + * @param [in] readOffset The offset into the read. + */ +void BLEValue::setReadOffset(uint16_t readOffset) { + m_readOffset = readOffset; +} // setReadOffset + +/** + * @brief Set the current value. + */ +void BLEValue::setValue(const String &value) { + m_value = value; +} // setValue + +/** + * @brief Set the current value. + * @param [in] pData The data for the current value. + * @param [in] The length of the new current value. + */ +void BLEValue::setValue(const uint8_t *pData, size_t length) { + m_value = String((char *)pData, length); +} // setValue + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ diff --git a/libraries/BLE/src/BLEValue.h b/libraries/BLE/src/BLEValue.h new file mode 100644 index 0000000..99147db --- /dev/null +++ b/libraries/BLE/src/BLEValue.h @@ -0,0 +1,61 @@ +/* + * BLEValue.h + * + * Created on: Jul 17, 2017 + * Author: kolban + * + * Modified on: Feb 18, 2025 + * Author: lucasssvaz (based on kolban's and h2zero's work) + * Description: Added support for NimBLE + */ + +#ifndef COMPONENTS_CPP_UTILS_BLEVALUE_H_ +#define COMPONENTS_CPP_UTILS_BLEVALUE_H_ + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if defined(SOC_BLE_SUPPORTED) || defined(CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE) +#if defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED) + +/***************************************************************************** + * Common includes * + *****************************************************************************/ + +#include "WString.h" + +/** + * @brief The model of a %BLE value. + */ +class BLEValue { +public: + /*************************************************************************** + * Common public declarations * + ***************************************************************************/ + + BLEValue(); + void addPart(const String &part); + void addPart(const uint8_t *pData, size_t length); + void cancel(); + void commit(); + uint8_t *getData(); + size_t getLength() const; + uint16_t getReadOffset() const; + String getValue() const; + void setReadOffset(uint16_t readOffset); + void setValue(const String &value); + void setValue(const uint8_t *pData, size_t length); + +private: + /*************************************************************************** + * Common private properties * + ***************************************************************************/ + + String m_accumulation; + uint16_t m_readOffset; + String m_value; +}; + +#endif /* CONFIG_BLUEDROID_ENABLED || CONFIG_NIMBLE_ENABLED */ +#endif /* SOC_BLE_SUPPORTED || CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE */ + +#endif /* COMPONENTS_CPP_UTILS_BLEVALUE_H_ */ diff --git a/libraries/BLE/src/FreeRTOS.cpp b/libraries/BLE/src/FreeRTOS.cpp new file mode 100644 index 0000000..b1f8760 --- /dev/null +++ b/libraries/BLE/src/FreeRTOS.cpp @@ -0,0 +1,285 @@ +/* + * FreeRTOS.cpp + * + * Created on: Feb 24, 2017 + * Author: kolban + */ +#include // Include the base FreeRTOS definitions +#include // Include the task definitions +#include // Include the semaphore definitions +#include +#include +#include +#include "RTOS.h" +#include "sdkconfig.h" +#include "esp32-hal-log.h" + +/** + * Sleep for the specified number of milliseconds. + * @param[in] ms The period in milliseconds for which to sleep. + */ +void FreeRTOS::sleep(uint32_t ms) { + ::vTaskDelay(ms / portTICK_PERIOD_MS); +} // sleep + +/** + * Start a new task. + * @param[in] task The function pointer to the function to be run in the task. + * @param[in] taskName A string identifier for the task. + * @param[in] param An optional parameter to be passed to the started task. + * @param[in] stackSize An optional parameter supplying the size of the stack in which to run the task. + */ +void FreeRTOS::startTask(void task(void *), String taskName, void *param, uint32_t stackSize) { + ::xTaskCreate(task, taskName.c_str(), stackSize, param, 5, NULL); +} // startTask + +/** + * Delete the task. + * @param[in] pTask An optional handle to the task to be deleted. If not supplied the calling task will be deleted. + */ +void FreeRTOS::deleteTask(TaskHandle_t pTask) { + ::vTaskDelete(pTask); +} // deleteTask + +/** + * Get the time in milliseconds since the %FreeRTOS scheduler started. + * @return The time in milliseconds since the %FreeRTOS scheduler started. + */ +uint32_t FreeRTOS::getTimeSinceStart() { + return (uint32_t)(xTaskGetTickCount() * portTICK_PERIOD_MS); +} // getTimeSinceStart + +/** + * @brief Wait for a semaphore to be released by trying to take it and + * then releasing it again. + * @param [in] owner A debug tag. + * @return The value associated with the semaphore. + */ +uint32_t FreeRTOS::Semaphore::wait(String owner) { + log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str()); + + if (m_usePthreads) { + pthread_mutex_lock(&m_pthread_mutex); + } else { + xSemaphoreTake(m_semaphore, portMAX_DELAY); + } + + if (m_usePthreads) { + pthread_mutex_unlock(&m_pthread_mutex); + } else { + xSemaphoreGive(m_semaphore); + } + + log_v("<< wait: Semaphore released: %s", toString().c_str()); + return m_value; +} // wait + +/** + * @brief Wait for a semaphore to be released in a given period of time by trying to take it and + * then releasing it again. The value associated with the semaphore can be taken by value() call after return + * @param [in] owner A debug tag. + * @param [in] timeoutMs timeout to wait in ms. + * @return True if we took the semaphore within timeframe. + */ +bool FreeRTOS::Semaphore::timedWait(String owner, uint32_t timeoutMs) { + log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str()); + + if (m_usePthreads && timeoutMs != portMAX_DELAY) { + assert(false); // We apparently don't have a timed wait for pthreads. + } + + auto ret = pdTRUE; + + if (m_usePthreads) { + pthread_mutex_lock(&m_pthread_mutex); + } else { + ret = xSemaphoreTake(m_semaphore, timeoutMs); + } + + if (m_usePthreads) { + pthread_mutex_unlock(&m_pthread_mutex); + } else { + xSemaphoreGive(m_semaphore); + } + + log_v("<< wait: Semaphore %s released: %d", toString().c_str(), ret); + return ret; +} // wait + +FreeRTOS::Semaphore::Semaphore(String name) { + m_usePthreads = false; // Are we using pThreads or FreeRTOS? + if (m_usePthreads) { + pthread_mutex_init(&m_pthread_mutex, nullptr); + } else { + m_semaphore = xSemaphoreCreateBinary(); + xSemaphoreGive(m_semaphore); + } + + m_name = name; + m_owner = String(""); + m_value = 0; +} + +FreeRTOS::Semaphore::~Semaphore() { + if (m_usePthreads) { + pthread_mutex_destroy(&m_pthread_mutex); + } else { + vSemaphoreDelete(m_semaphore); + } +} + +/** + * @brief Give a semaphore. + * The Semaphore is given. + */ +void FreeRTOS::Semaphore::give() { + log_v("Semaphore giving: %s", toString().c_str()); + m_owner = String(""); + + if (m_usePthreads) { + pthread_mutex_unlock(&m_pthread_mutex); + } else { + xSemaphoreGive(m_semaphore); + } + // #ifdef ARDUINO_ARCH_ESP32 + // FreeRTOS::sleep(10); + // #endif + +} // Semaphore::give + +/** + * @brief Give a semaphore. + * The Semaphore is given with an associated value. + * @param [in] value The value to associate with the semaphore. + */ +void FreeRTOS::Semaphore::give(uint32_t value) { + m_value = value; + give(); +} // give + +/** + * @brief Give a semaphore from an ISR. + */ +void FreeRTOS::Semaphore::giveFromISR() { + BaseType_t higherPriorityTaskWoken; + if (m_usePthreads) { + assert(false); + } else { + xSemaphoreGiveFromISR(m_semaphore, &higherPriorityTaskWoken); + } +} // giveFromISR + +/** + * @brief Take a semaphore. + * Take a semaphore and wait indefinitely. + * @param [in] owner The new owner (for debugging) + * @return True if we took the semaphore. + */ +bool FreeRTOS::Semaphore::take(String owner) { + log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str()); + bool rc = false; + if (m_usePthreads) { + pthread_mutex_lock(&m_pthread_mutex); + } else { + rc = ::xSemaphoreTake(m_semaphore, portMAX_DELAY) == pdTRUE; + } + if (rc) { + m_owner = owner; + log_v("Semaphore taken: %s", toString().c_str()); + } else { + log_e("Semaphore NOT taken: %s", toString().c_str()); + } + return rc; +} // Semaphore::take + +/** + * @brief Take a semaphore. + * Take a semaphore but return if we haven't obtained it in the given period of milliseconds. + * @param [in] timeoutMs Timeout in milliseconds. + * @param [in] owner The new owner (for debugging) + * @return True if we took the semaphore. + */ +bool FreeRTOS::Semaphore::take(uint32_t timeoutMs, String owner) { + log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str()); + bool rc = false; + if (m_usePthreads) { + assert(false); // We apparently don't have a timed wait for pthreads. + } else { + rc = ::xSemaphoreTake(m_semaphore, timeoutMs / portTICK_PERIOD_MS) == pdTRUE; + } + if (rc) { + m_owner = owner; + log_v("Semaphore taken: %s", toString().c_str()); + } else { + log_e("Semaphore NOT taken: %s", toString().c_str()); + } + return rc; +} // Semaphore::take + +/** + * @brief Create a string representation of the semaphore. + * @return A string representation of the semaphore. + */ +String FreeRTOS::Semaphore::toString() { + char hex[9]; + String res = "name: " + m_name + " (0x"; + snprintf(hex, sizeof(hex), "%08lx", (uint32_t)m_semaphore); + res += hex; + res += "), owner: " + m_owner; + return res; +} // toString + +/** + * @brief Set the name of the semaphore. + * @param [in] name The name of the semaphore. + */ +void FreeRTOS::Semaphore::setName(String name) { + m_name = name; +} // setName + +/** + * @brief Create a ring buffer. + * @param [in] length The amount of storage to allocate for the ring buffer. + * @param [in] type The type of buffer. One of RINGBUF_TYPE_NOSPLIT, RINGBUF_TYPE_ALLOWSPLIT, RINGBUF_TYPE_BYTEBUF. + */ +#ifdef ESP_IDF_VERSION_MAJOR +Ringbuffer::Ringbuffer(size_t length, RingbufferType_t type) +#else +Ringbuffer::Ringbuffer(size_t length, ringbuf_type_t type) +#endif +{ + m_handle = ::xRingbufferCreate(length, type); +} // Ringbuffer + +Ringbuffer::~Ringbuffer() { + ::vRingbufferDelete(m_handle); +} // ~Ringbuffer + +/** + * @brief Receive data from the buffer. + * @param [out] size On return, the size of data returned. + * @param [in] wait How long to wait. + * @return A pointer to the storage retrieved. + */ +void *Ringbuffer::receive(size_t *size, TickType_t wait) { + return ::xRingbufferReceive(m_handle, size, wait); +} // receive + +/** + * @brief Return an item. + * @param [in] item The item to be returned/released. + */ +void Ringbuffer::returnItem(void *item) { + ::vRingbufferReturnItem(m_handle, item); +} // returnItem + +/** + * @brief Send data to the buffer. + * @param [in] data The data to place into the buffer. + * @param [in] length The length of data to place into the buffer. + * @param [in] wait How long to wait before giving up. The default is to wait indefinitely. + * @return + */ +bool Ringbuffer::send(void *data, size_t length, TickType_t wait) { + return ::xRingbufferSend(m_handle, data, length, wait) == pdTRUE; +} // send diff --git a/libraries/BLE/src/GeneralUtils.cpp b/libraries/BLE/src/GeneralUtils.cpp new file mode 100644 index 0000000..1bb474f --- /dev/null +++ b/libraries/BLE/src/GeneralUtils.cpp @@ -0,0 +1,490 @@ +/* + * GeneralUtils.cpp + * + * Created on: May 20, 2017 + * Author: kolban + */ + +#include "GeneralUtils.h" +#include +#include +#include +#include +#include +#include +#include "RTOS.h" +#include +#include +#include +#include +#include +#include "esp_chip_info.h" +#include "esp32-hal-log.h" + +static const char kBase64Alphabet[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdefghijklmnopqrstuvwxyz" + "0123456789+/"; + +static int base64EncodedLength(size_t length) { + return (length + 2 - ((length + 2) % 3)) / 3 * 4; +} // base64EncodedLength + +static int base64EncodedLength(const String &in) { + return base64EncodedLength(in.length()); +} // base64EncodedLength + +static void a3_to_a4(unsigned char *a4, unsigned char *a3) { + a4[0] = (a3[0] & 0xfc) >> 2; + a4[1] = ((a3[0] & 0x03) << 4) + ((a3[1] & 0xf0) >> 4); + a4[2] = ((a3[1] & 0x0f) << 2) + ((a3[2] & 0xc0) >> 6); + a4[3] = (a3[2] & 0x3f); +} // a3_to_a4 + +static void a4_to_a3(unsigned char *a3, unsigned char *a4) { + a3[0] = (a4[0] << 2) + ((a4[1] & 0x30) >> 4); + a3[1] = ((a4[1] & 0xf) << 4) + ((a4[2] & 0x3c) >> 2); + a3[2] = ((a4[2] & 0x3) << 6) + a4[3]; +} // a4_to_a3 + +/** + * @brief Encode a string into base 64. + * @param [in] in + * @param [out] out + */ +bool GeneralUtils::base64Encode(const String &in, String *out) { + std::string std_in(in.c_str()); + std::string std_out(out->c_str()); + int i = 0, j = 0; + size_t enc_len = 0; + unsigned char a3[3]; + unsigned char a4[4]; + std_out.resize(base64EncodedLength(in)); + + int input_len = std_in.length(); + std::string::const_iterator input = std_in.begin(); + + while (input_len--) { + a3[i++] = *(input++); + if (i == 3) { + a3_to_a4(a4, a3); + + for (i = 0; i < 4; i++) { + (std_out)[enc_len++] = kBase64Alphabet[a4[i]]; + } + + i = 0; + } + } + + if (i) { + for (j = i; j < 3; j++) { + a3[j] = '\0'; + } + + a3_to_a4(a4, a3); + + for (j = 0; j < i + 1; j++) { + (std_out)[enc_len++] = kBase64Alphabet[a4[j]]; + } + + while ((i++ < 3)) { + (std_out)[enc_len++] = '='; + } + } + *out = String(std_out.c_str()); + + return (enc_len == out->length()); +} // base64Encode + +/** + * @brief Dump general info to the log. + * Data includes: + * * Amount of free RAM + */ +void GeneralUtils::dumpInfo() { + esp_chip_info_t chipInfo; + esp_chip_info(&chipInfo); + log_v("--- dumpInfo ---"); + log_v("Free heap: %d", heap_caps_get_free_size(MALLOC_CAP_8BIT)); + log_v("Chip Info: Model: %d, cores: %d, revision: %d", chipInfo.model, chipInfo.cores, chipInfo.revision); + log_v("ESP-IDF version: %s", esp_get_idf_version()); + log_v("---"); +} // dumpInfo + +/** + * @brief Does the string end with a specific character? + * @param [in] str The string to examine. + * @param [in] c The character to look form. + * @return True if the string ends with the given character. + */ +bool GeneralUtils::endsWith(String str, char c) { + if (str.length() == 0) { + return false; + } + if (str.charAt(str.length() - 1) == c) { + return true; + } + return false; +} // endsWidth + +/* +static int DecodedLength(const String& in) { + int numEq = 0; + int n = (int) in.length(); + + //for (String::const_reverse_iterator it = in.rbegin(); *it == '='; ++it) { + for (int it = in.length()-1; in.charAt(it) == '='; --it) { + ++numEq; + } + return ((6 * n) / 8) - numEq; +} // DecodedLength +*/ + +static unsigned char b64_lookup(unsigned char c) { + if (c >= 'A' && c <= 'Z') { + return c - 'A'; + } + if (c >= 'a' && c <= 'z') { + return c - 71; + } + if (c >= '0' && c <= '9') { + return c + 4; + } + if (c == '+') { + return 62; + } + if (c == '/') { + return 63; + } + return 255; +}; // b64_lookup + +/** + * @brief Decode a chunk of data that is base64 encoded. + * @param [in] in The string to be decoded. + * @param [out] out The resulting data. + */ +bool GeneralUtils::base64Decode(const String &in, String *out) { + int i = 0, j = 0; + size_t dec_len = 0; + unsigned char a3[3]; + unsigned char a4[4]; + + int input_len = in.length(); + int input_iterator = 0; + + //out->resize(DecodedLength(in)); + + while (input_len--) { + //if (*input == '=') { + if (in[input_iterator] == '=') { + break; + } + + a4[i++] = in[input_iterator++]; + if (i == 4) { + for (i = 0; i < 4; i++) { + a4[i] = b64_lookup(a4[i]); + } + + a4_to_a3(a3, a4); + + for (i = 0; i < 3; i++) { + out->concat(a3[i]); + dec_len++; + } + + i = 0; + } + } + + if (i) { + for (j = i; j < 4; j++) { + a4[j] = '\0'; + } + + for (j = 0; j < 4; j++) { + a4[j] = b64_lookup(a4[j]); + } + + a4_to_a3(a3, a4); + + for (j = 0; j < i - 1; j++) { + (*out)[dec_len++] = a3[j]; + } + } + + return (dec_len == out->length()); +} // base64Decode + +/* +void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) { + uint32_t index=0; + Stringstream ascii; + Stringstream hex; + char asciiBuf[80]; + char hexBuf[80]; + hex.str(""); + ascii.str(""); + while(index < length) { + hex << std::setfill('0') << std::setw(2) << std::hex << (int)pData[index] << ' '; + if (std::isprint(pData[index])) { + ascii << pData[index]; + } else { + ascii << '.'; + } + index++; + if (index % 16 == 0) { + strcpy(hexBuf, hex.str().c_str()); + strcpy(asciiBuf, ascii.str().c_str()); + log_v("%s %s", hexBuf, asciiBuf); + hex.str(""); + ascii.str(""); + } + } + if (index %16 != 0) { + while(index % 16 != 0) { + hex << " "; + index++; + } + strcpy(hexBuf, hex.str().c_str()); + strcpy(asciiBuf, ascii.str().c_str()); + log_v("%s %s", hexBuf, asciiBuf); + //log_v("%s %s", hex.str().c_str(), ascii.str().c_str()); + } + FreeRTOS::sleep(1000); +} +*/ + +/* +void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) { + uint32_t index=0; + static Stringstream ascii; + static Stringstream hex; + hex.str(""); + ascii.str(""); + while(index < length) { + hex << std::setfill('0') << std::setw(2) << std::hex << (int)pData[index] << ' '; + if (std::isprint(pData[index])) { + ascii << pData[index]; + } else { + ascii << '.'; + } + index++; + if (index % 16 == 0) { + log_v("%s %s", hex.str().c_str(), ascii.str().c_str()); + hex.str(""); + ascii.str(""); + } + } + if (index %16 != 0) { + while(index % 16 != 0) { + hex << " "; + index++; + } + log_v("%s %s", hex.str().c_str(), ascii.str().c_str()); + } + FreeRTOS::sleep(1000); +} +*/ + +/** + * @brief Dump a representation of binary data to the console. + * + * @param [in] pData Pointer to the start of data to be logged. + * @param [in] length Length of the data (in bytes) to be logged. + * @return N/A. + */ +void GeneralUtils::hexDump(const uint8_t *pData, uint32_t length) { + char ascii[80]; + char hex[80]; + char tempBuf[80]; + uint32_t lineNumber = 0; + + log_v(" 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f"); + log_v(" -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --"); + strcpy(ascii, ""); + strcpy(hex, ""); + uint32_t index = 0; + while (index < length) { + sprintf(tempBuf, "%.2x ", pData[index]); + strcat(hex, tempBuf); + if (isprint(pData[index])) { + sprintf(tempBuf, "%c", pData[index]); + } else { + sprintf(tempBuf, "."); + } + strcat(ascii, tempBuf); + index++; + if (index % 16 == 0) { + log_v("%.4x %s %s", lineNumber * 16, hex, ascii); + strcpy(ascii, ""); + strcpy(hex, ""); + lineNumber++; + } + } + if (index % 16 != 0) { + while (index % 16 != 0) { + strcat(hex, " "); + index++; + } + log_v("%.4x %s %s", lineNumber * 16, hex, ascii); + } +} // hexDump + +/** + * @brief Convert an IP address to string. + * @param ip The 4 byte IP address. + * @return A string representation of the IP address. + */ +String GeneralUtils::ipToString(uint8_t *ip) { + auto size = 16; + char *val = (char *)malloc(size); + snprintf(val, size, "%d.%d.%d.%d", ip[0], ip[1], ip[2], ip[3]); + String res(val); + free(val); + return res; +} // ipToString + +/** + * @brief Split a string into parts based on a delimiter. + * @param [in] source The source string to split. + * @param [in] delimiter The delimiter characters. + * @return A vector of strings that are the split of the input. + */ +std::vector GeneralUtils::split(String source, char delimiter) { + // See also: https://stackoverflow.com/questions/5167625/splitting-a-c-stdstring-using-tokens-e-g + std::vector strings; + std::size_t current, previous = 0; + std::string std_source(source.c_str()); + current = std_source.find(delimiter); + while (current != std::string::npos) { + strings.push_back(trim(source.substring(previous, current))); + previous = current + 1; + current = std_source.find(delimiter, previous); + } + strings.push_back(trim(source.substring(previous, current))); + return strings; +} // split + +/** + * @brief Convert an ESP error code to a string. + * @param [in] errCode The errCode to be converted. + * @return A string representation of the error code. + */ +const char *GeneralUtils::errorToString(esp_err_t errCode) { + switch (errCode) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case ESP_OK: return "ESP_OK"; + case ESP_FAIL: return "ESP_FAIL"; + case ESP_ERR_NO_MEM: return "ESP_ERR_NO_MEM"; + case ESP_ERR_INVALID_ARG: return "ESP_ERR_INVALID_ARG"; + case ESP_ERR_INVALID_SIZE: return "ESP_ERR_INVALID_SIZE"; + case ESP_ERR_INVALID_STATE: return "ESP_ERR_INVALID_STATE"; + case ESP_ERR_NOT_FOUND: return "ESP_ERR_NOT_FOUND"; + case ESP_ERR_NOT_SUPPORTED: return "ESP_ERR_NOT_SUPPORTED"; + case ESP_ERR_TIMEOUT: return "ESP_ERR_TIMEOUT"; + case ESP_ERR_NVS_NOT_INITIALIZED: return "ESP_ERR_NVS_NOT_INITIALIZED"; + case ESP_ERR_NVS_NOT_FOUND: return "ESP_ERR_NVS_NOT_FOUND"; + case ESP_ERR_NVS_TYPE_MISMATCH: return "ESP_ERR_NVS_TYPE_MISMATCH"; + case ESP_ERR_NVS_READ_ONLY: return "ESP_ERR_NVS_READ_ONLY"; + case ESP_ERR_NVS_NOT_ENOUGH_SPACE: return "ESP_ERR_NVS_NOT_ENOUGH_SPACE"; + case ESP_ERR_NVS_INVALID_NAME: return "ESP_ERR_NVS_INVALID_NAME"; + case ESP_ERR_NVS_INVALID_HANDLE: return "ESP_ERR_NVS_INVALID_HANDLE"; + case ESP_ERR_NVS_REMOVE_FAILED: return "ESP_ERR_NVS_REMOVE_FAILED"; + case ESP_ERR_NVS_KEY_TOO_LONG: return "ESP_ERR_NVS_KEY_TOO_LONG"; + case ESP_ERR_NVS_PAGE_FULL: return "ESP_ERR_NVS_PAGE_FULL"; + case ESP_ERR_NVS_INVALID_STATE: return "ESP_ERR_NVS_INVALID_STATE"; + case ESP_ERR_NVS_INVALID_LENGTH: return "ESP_ERR_NVS_INVALID_LENGTH"; + case ESP_ERR_WIFI_NOT_INIT: return "ESP_ERR_WIFI_NOT_INIT"; + //case ESP_ERR_WIFI_NOT_START: + // return "ESP_ERR_WIFI_NOT_START"; + case ESP_ERR_WIFI_IF: return "ESP_ERR_WIFI_IF"; + case ESP_ERR_WIFI_MODE: return "ESP_ERR_WIFI_MODE"; + case ESP_ERR_WIFI_STATE: return "ESP_ERR_WIFI_STATE"; + case ESP_ERR_WIFI_CONN: return "ESP_ERR_WIFI_CONN"; + case ESP_ERR_WIFI_NVS: return "ESP_ERR_WIFI_NVS"; + case ESP_ERR_WIFI_MAC: return "ESP_ERR_WIFI_MAC"; + case ESP_ERR_WIFI_SSID: return "ESP_ERR_WIFI_SSID"; + case ESP_ERR_WIFI_PASSWORD: return "ESP_ERR_WIFI_PASSWORD"; + case ESP_ERR_WIFI_TIMEOUT: return "ESP_ERR_WIFI_TIMEOUT"; + case ESP_ERR_WIFI_WAKE_FAIL: return "ESP_ERR_WIFI_WAKE_FAIL"; +#endif + default: return "Unknown ESP_ERR error"; + } +} // errorToString + +/** + * @brief Convert a wifi_err_reason_t code to a string. + * @param [in] errCode The errCode to be converted. + * @return A string representation of the error code. + * + * @note: wifi_err_reason_t values as of April 2018 are: (1-24, 200-204) and are defined in ~/esp-idf/components/esp32/include/esp_wifi_types.h. + */ +const char *GeneralUtils::wifiErrorToString(uint8_t errCode) { + if (errCode == ESP_OK) { + return "ESP_OK (received SYSTEM_EVENT_STA_GOT_IP event)"; + } + if (errCode == UINT8_MAX) { + return "Not Connected (default value)"; + } + + switch ((wifi_err_reason_t)errCode) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG + case WIFI_REASON_UNSPECIFIED: return "WIFI_REASON_UNSPECIFIED"; + case WIFI_REASON_AUTH_EXPIRE: return "WIFI_REASON_AUTH_EXPIRE"; + case WIFI_REASON_AUTH_LEAVE: return "WIFI_REASON_AUTH_LEAVE"; + case WIFI_REASON_ASSOC_EXPIRE: return "WIFI_REASON_ASSOC_EXPIRE"; + case WIFI_REASON_ASSOC_TOOMANY: return "WIFI_REASON_ASSOC_TOOMANY"; + case WIFI_REASON_NOT_AUTHED: return "WIFI_REASON_NOT_AUTHED"; + case WIFI_REASON_NOT_ASSOCED: return "WIFI_REASON_NOT_ASSOCED"; + case WIFI_REASON_ASSOC_LEAVE: return "WIFI_REASON_ASSOC_LEAVE"; + case WIFI_REASON_ASSOC_NOT_AUTHED: return "WIFI_REASON_ASSOC_NOT_AUTHED"; + case WIFI_REASON_DISASSOC_PWRCAP_BAD: return "WIFI_REASON_DISASSOC_PWRCAP_BAD"; + case WIFI_REASON_DISASSOC_SUPCHAN_BAD: return "WIFI_REASON_DISASSOC_SUPCHAN_BAD"; + case WIFI_REASON_IE_INVALID: return "WIFI_REASON_IE_INVALID"; + case WIFI_REASON_MIC_FAILURE: return "WIFI_REASON_MIC_FAILURE"; + case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT: return "WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT"; + case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT: return "WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT"; + case WIFI_REASON_IE_IN_4WAY_DIFFERS: return "WIFI_REASON_IE_IN_4WAY_DIFFERS"; + case WIFI_REASON_GROUP_CIPHER_INVALID: return "WIFI_REASON_GROUP_CIPHER_INVALID"; + case WIFI_REASON_PAIRWISE_CIPHER_INVALID: return "WIFI_REASON_PAIRWISE_CIPHER_INVALID"; + case WIFI_REASON_AKMP_INVALID: return "WIFI_REASON_AKMP_INVALID"; + case WIFI_REASON_UNSUPP_RSN_IE_VERSION: return "WIFI_REASON_UNSUPP_RSN_IE_VERSION"; + case WIFI_REASON_INVALID_RSN_IE_CAP: return "WIFI_REASON_INVALID_RSN_IE_CAP"; + case WIFI_REASON_802_1X_AUTH_FAILED: return "WIFI_REASON_802_1X_AUTH_FAILED"; + case WIFI_REASON_CIPHER_SUITE_REJECTED: return "WIFI_REASON_CIPHER_SUITE_REJECTED"; + case WIFI_REASON_BEACON_TIMEOUT: return "WIFI_REASON_BEACON_TIMEOUT"; + case WIFI_REASON_NO_AP_FOUND: return "WIFI_REASON_NO_AP_FOUND"; + case WIFI_REASON_AUTH_FAIL: return "WIFI_REASON_AUTH_FAIL"; + case WIFI_REASON_ASSOC_FAIL: return "WIFI_REASON_ASSOC_FAIL"; + case WIFI_REASON_HANDSHAKE_TIMEOUT: return "WIFI_REASON_HANDSHAKE_TIMEOUT"; +#endif + default: return "Unknown ESP_ERR error"; + } +} // wifiErrorToString + +/** + * @brief Convert a string to lower case. + * @param [in] value The string to convert to lower case. + * @return A lower case representation of the string. + */ +String GeneralUtils::toLower(String &value) { + // Question: Could this be improved with a signature of: + // String& GeneralUtils::toLower(String& value) + std::transform(value.begin(), value.end(), value.begin(), ::tolower); + return value; +} // toLower + +/** + * @brief Remove white space from a string. + */ +String GeneralUtils::trim(const String &str) { + std::string std_str(str.c_str()); + size_t first = std_str.find_first_not_of(' '); + if (std::string::npos == first) { + return str; + } + size_t last = std_str.find_last_not_of(' '); + return str.substring(first, (last + 1)); +} // trim diff --git a/libraries/BLE/src/GeneralUtils.h b/libraries/BLE/src/GeneralUtils.h new file mode 100644 index 0000000..c22d6f9 --- /dev/null +++ b/libraries/BLE/src/GeneralUtils.h @@ -0,0 +1,35 @@ +/* + * GeneralUtils.h + * + * Created on: May 20, 2017 + * Author: kolban + */ + +#ifndef COMPONENTS_CPP_UTILS_GENERALUTILS_H_ +#define COMPONENTS_CPP_UTILS_GENERALUTILS_H_ +#include "Arduino.h" +#include +#include +#include +#include +#include + +/** + * @brief General utilities. + */ +class GeneralUtils { +public: + static bool base64Decode(const String &in, String *out); + static bool base64Encode(const String &in, String *out); + static void dumpInfo(); + static bool endsWith(String str, char c); + static const char *errorToString(esp_err_t errCode); + static const char *wifiErrorToString(uint8_t value); + static void hexDump(const uint8_t *pData, uint32_t length); + static String ipToString(uint8_t *ip); + static std::vector split(String source, char delimiter); + static String toLower(String &value); + static String trim(const String &str); +}; + +#endif /* COMPONENTS_CPP_UTILS_GENERALUTILS_H_ */ diff --git a/libraries/BLE/src/HIDKeyboardTypes.h b/libraries/BLE/src/HIDKeyboardTypes.h new file mode 100644 index 0000000..e0b40eb --- /dev/null +++ b/libraries/BLE/src/HIDKeyboardTypes.h @@ -0,0 +1,421 @@ +/* Copyright (c) 2015 mbed.org, MIT License + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software + * and associated documentation files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this file was pulled from different parts of the USBHID library, in mbed SDK + */ + +#ifndef KEYBOARD_DEFS_H +#define KEYBOARD_DEFS_H + +#include "esp_bit_defs.h" + +#define REPORT_ID_KEYBOARD 1 +#define REPORT_ID_VOLUME 3 + +/* Modifiers */ +enum MODIFIER_KEY { + /* Aliases for the left modifiers */ + KEY_CTRL = BIT(0), + KEY_SHIFT = BIT(1), + KEY_ALT = BIT(2), + KEY_GUI = BIT(3), /*!< GUI key (Command on macOS, Windows key on Windows) */ + /* Left modifiers */ + KEY_LEFT_CTRL = BIT(0), + KEY_LEFT_SHIFT = BIT(1), + KEY_LEFT_ALT = BIT(2), + KEY_LEFT_GUI = BIT(3), + /* Right modifiers */ + KEY_RIGHT_CTRL = BIT(4), + KEY_RIGHT_SHIFT = BIT(5), + KEY_RIGHT_ALT = BIT(6), + KEY_RIGHT_GUI = BIT(7), +}; + +enum MEDIA_KEY { + KEY_NEXT_TRACK, /*!< next Track Button */ + KEY_PREVIOUS_TRACK, /*!< Previous track Button */ + KEY_STOP, /*!< Stop Button */ + KEY_PLAY_PAUSE, /*!< Play/Pause Button */ + KEY_MUTE, /*!< Mute Button */ + KEY_VOLUME_UP, /*!< Volume Up Button */ + KEY_VOLUME_DOWN, /*!< Volume Down Button */ +}; + +enum FUNCTION_KEY { + KEY_F1 = 128, /* F1 key */ + KEY_F2, /* F2 key */ + KEY_F3, /* F3 key */ + KEY_F4, /* F4 key */ + KEY_F5, /* F5 key */ + KEY_F6, /* F6 key */ + KEY_F7, /* F7 key */ + KEY_F8, /* F8 key */ + KEY_F9, /* F9 key */ + KEY_F10, /* F10 key */ + KEY_F11, /* F11 key */ + KEY_F12, /* F12 key */ + + KEY_PRINT_SCREEN, /* Print Screen key */ + KEY_SCROLL_LOCK, /* Scroll lock */ + KEY_CAPS_LOCK, /* caps lock */ + KEY_NUM_LOCK, /* num lock */ + KEY_INSERT, /* Insert key */ + KEY_HOME, /* Home key */ + KEY_PAGE_UP, /* Page Up key */ + KEY_PAGE_DOWN, /* Page Down key */ + + RIGHT_ARROW, /* Right arrow */ + LEFT_ARROW, /* Left arrow */ + DOWN_ARROW, /* Down arrow */ + UP_ARROW, /* Up arrow */ +}; + +typedef struct { + unsigned char usage; + unsigned char modifier; +} KEYMAP; + +#ifdef US_KEYBOARD +/* US keyboard (as HID standard) */ +#define KEYMAP_SIZE (152) +const KEYMAP keymap[KEYMAP_SIZE] = { + {0, 0}, /* NUL */ + {0, 0}, /* SOH */ + {0, 0}, /* STX */ + {0, 0}, /* ETX */ + {0, 0}, /* EOT */ + {0, 0}, /* ENQ */ + {0, 0}, /* ACK */ + {0, 0}, /* BEL */ + {0x2a, 0}, + /* BS */ /* Keyboard Delete (Backspace) */ + {0x2b, 0}, + /* TAB */ /* Keyboard Tab */ + {0x28, 0}, + /* LF */ /* Keyboard Return (Enter) */ + {0, 0}, /* VT */ + {0, 0}, /* FF */ + {0, 0}, /* CR */ + {0, 0}, /* SO */ + {0, 0}, /* SI */ + {0, 0}, /* DEL */ + {0, 0}, /* DC1 */ + {0, 0}, /* DC2 */ + {0, 0}, /* DC3 */ + {0, 0}, /* DC4 */ + {0, 0}, /* NAK */ + {0, 0}, /* SYN */ + {0, 0}, /* ETB */ + {0, 0}, /* CAN */ + {0, 0}, /* EM */ + {0, 0}, /* SUB */ + {0, 0}, /* ESC */ + {0, 0}, /* FS */ + {0, 0}, /* GS */ + {0, 0}, /* RS */ + {0, 0}, /* US */ + {0x2c, 0}, /* */ + {0x1e, KEY_SHIFT}, /* ! */ + {0x34, KEY_SHIFT}, /* " */ + {0x20, KEY_SHIFT}, /* # */ + {0x21, KEY_SHIFT}, /* $ */ + {0x22, KEY_SHIFT}, /* % */ + {0x24, KEY_SHIFT}, /* & */ + {0x34, 0}, /* ' */ + {0x26, KEY_SHIFT}, /* ( */ + {0x27, KEY_SHIFT}, /* ) */ + {0x25, KEY_SHIFT}, /* * */ + {0x2e, KEY_SHIFT}, /* + */ + {0x36, 0}, /* , */ + {0x2d, 0}, /* - */ + {0x37, 0}, /* . */ + {0x38, 0}, /* / */ + {0x27, 0}, /* 0 */ + {0x1e, 0}, /* 1 */ + {0x1f, 0}, /* 2 */ + {0x20, 0}, /* 3 */ + {0x21, 0}, /* 4 */ + {0x22, 0}, /* 5 */ + {0x23, 0}, /* 6 */ + {0x24, 0}, /* 7 */ + {0x25, 0}, /* 8 */ + {0x26, 0}, /* 9 */ + {0x33, KEY_SHIFT}, /* : */ + {0x33, 0}, /* ; */ + {0x36, KEY_SHIFT}, /* < */ + {0x2e, 0}, /* = */ + {0x37, KEY_SHIFT}, /* > */ + {0x38, KEY_SHIFT}, /* ? */ + {0x1f, KEY_SHIFT}, /* @ */ + {0x04, KEY_SHIFT}, /* A */ + {0x05, KEY_SHIFT}, /* B */ + {0x06, KEY_SHIFT}, /* C */ + {0x07, KEY_SHIFT}, /* D */ + {0x08, KEY_SHIFT}, /* E */ + {0x09, KEY_SHIFT}, /* F */ + {0x0a, KEY_SHIFT}, /* G */ + {0x0b, KEY_SHIFT}, /* H */ + {0x0c, KEY_SHIFT}, /* I */ + {0x0d, KEY_SHIFT}, /* J */ + {0x0e, KEY_SHIFT}, /* K */ + {0x0f, KEY_SHIFT}, /* L */ + {0x10, KEY_SHIFT}, /* M */ + {0x11, KEY_SHIFT}, /* N */ + {0x12, KEY_SHIFT}, /* O */ + {0x13, KEY_SHIFT}, /* P */ + {0x14, KEY_SHIFT}, /* Q */ + {0x15, KEY_SHIFT}, /* R */ + {0x16, KEY_SHIFT}, /* S */ + {0x17, KEY_SHIFT}, /* T */ + {0x18, KEY_SHIFT}, /* U */ + {0x19, KEY_SHIFT}, /* V */ + {0x1a, KEY_SHIFT}, /* W */ + {0x1b, KEY_SHIFT}, /* X */ + {0x1c, KEY_SHIFT}, /* Y */ + {0x1d, KEY_SHIFT}, /* Z */ + {0x2f, 0}, /* [ */ + {0x31, 0}, /* \ */ + {0x30, 0}, /* ] */ + {0x23, KEY_SHIFT}, /* ^ */ + {0x2d, KEY_SHIFT}, /* _ */ + {0x35, 0}, /* ` */ + {0x04, 0}, /* a */ + {0x05, 0}, /* b */ + {0x06, 0}, /* c */ + {0x07, 0}, /* d */ + {0x08, 0}, /* e */ + {0x09, 0}, /* f */ + {0x0a, 0}, /* g */ + {0x0b, 0}, /* h */ + {0x0c, 0}, /* i */ + {0x0d, 0}, /* j */ + {0x0e, 0}, /* k */ + {0x0f, 0}, /* l */ + {0x10, 0}, /* m */ + {0x11, 0}, /* n */ + {0x12, 0}, /* o */ + {0x13, 0}, /* p */ + {0x14, 0}, /* q */ + {0x15, 0}, /* r */ + {0x16, 0}, /* s */ + {0x17, 0}, /* t */ + {0x18, 0}, /* u */ + {0x19, 0}, /* v */ + {0x1a, 0}, /* w */ + {0x1b, 0}, /* x */ + {0x1c, 0}, /* y */ + {0x1d, 0}, /* z */ + {0x2f, KEY_SHIFT}, /* { */ + {0x31, KEY_SHIFT}, /* | */ + {0x30, KEY_SHIFT}, /* } */ + {0x35, KEY_SHIFT}, /* ~ */ + {0, 0}, /* DEL */ + + {0x3a, 0}, /* F1 */ + {0x3b, 0}, /* F2 */ + {0x3c, 0}, /* F3 */ + {0x3d, 0}, /* F4 */ + {0x3e, 0}, /* F5 */ + {0x3f, 0}, /* F6 */ + {0x40, 0}, /* F7 */ + {0x41, 0}, /* F8 */ + {0x42, 0}, /* F9 */ + {0x43, 0}, /* F10 */ + {0x44, 0}, /* F11 */ + {0x45, 0}, /* F12 */ + + {0x46, 0}, /* PRINT_SCREEN */ + {0x47, 0}, /* SCROLL_LOCK */ + {0x39, 0}, /* CAPS_LOCK */ + {0x53, 0}, /* NUM_LOCK */ + {0x49, 0}, /* INSERT */ + {0x4a, 0}, /* HOME */ + {0x4b, 0}, /* PAGE_UP */ + {0x4e, 0}, /* PAGE_DOWN */ + + {0x4f, 0}, /* RIGHT_ARROW */ + {0x50, 0}, /* LEFT_ARROW */ + {0x51, 0}, /* DOWN_ARROW */ + {0x52, 0}, /* UP_ARROW */ +}; + +#else +/* UK keyboard */ +#define KEYMAP_SIZE (152) +const KEYMAP keymap[KEYMAP_SIZE] = { + {0, 0}, /* NUL */ + {0, 0}, /* SOH */ + {0, 0}, /* STX */ + {0, 0}, /* ETX */ + {0, 0}, /* EOT */ + {0, 0}, /* ENQ */ + {0, 0}, /* ACK */ + {0, 0}, /* BEL */ + {0x2a, 0}, + /* BS */ /* Keyboard Delete (Backspace) */ + {0x2b, 0}, + /* TAB */ /* Keyboard Tab */ + {0x28, 0}, + /* LF */ /* Keyboard Return (Enter) */ + {0, 0}, /* VT */ + {0, 0}, /* FF */ + {0, 0}, /* CR */ + {0, 0}, /* SO */ + {0, 0}, /* SI */ + {0, 0}, /* DEL */ + {0, 0}, /* DC1 */ + {0, 0}, /* DC2 */ + {0, 0}, /* DC3 */ + {0, 0}, /* DC4 */ + {0, 0}, /* NAK */ + {0, 0}, /* SYN */ + {0, 0}, /* ETB */ + {0, 0}, /* CAN */ + {0, 0}, /* EM */ + {0, 0}, /* SUB */ + {0, 0}, /* ESC */ + {0, 0}, /* FS */ + {0, 0}, /* GS */ + {0, 0}, /* RS */ + {0, 0}, /* US */ + {0x2c, 0}, /* */ + {0x1e, KEY_SHIFT}, /* ! */ + {0x1f, KEY_SHIFT}, /* " */ + {0x32, 0}, /* # */ + {0x21, KEY_SHIFT}, /* $ */ + {0x22, KEY_SHIFT}, /* % */ + {0x24, KEY_SHIFT}, /* & */ + {0x34, 0}, /* ' */ + {0x26, KEY_SHIFT}, /* ( */ + {0x27, KEY_SHIFT}, /* ) */ + {0x25, KEY_SHIFT}, /* * */ + {0x2e, KEY_SHIFT}, /* + */ + {0x36, 0}, /* , */ + {0x2d, 0}, /* - */ + {0x37, 0}, /* . */ + {0x38, 0}, /* / */ + {0x27, 0}, /* 0 */ + {0x1e, 0}, /* 1 */ + {0x1f, 0}, /* 2 */ + {0x20, 0}, /* 3 */ + {0x21, 0}, /* 4 */ + {0x22, 0}, /* 5 */ + {0x23, 0}, /* 6 */ + {0x24, 0}, /* 7 */ + {0x25, 0}, /* 8 */ + {0x26, 0}, /* 9 */ + {0x33, KEY_SHIFT}, /* : */ + {0x33, 0}, /* ; */ + {0x36, KEY_SHIFT}, /* < */ + {0x2e, 0}, /* = */ + {0x37, KEY_SHIFT}, /* > */ + {0x38, KEY_SHIFT}, /* ? */ + {0x34, KEY_SHIFT}, /* @ */ + {0x04, KEY_SHIFT}, /* A */ + {0x05, KEY_SHIFT}, /* B */ + {0x06, KEY_SHIFT}, /* C */ + {0x07, KEY_SHIFT}, /* D */ + {0x08, KEY_SHIFT}, /* E */ + {0x09, KEY_SHIFT}, /* F */ + {0x0a, KEY_SHIFT}, /* G */ + {0x0b, KEY_SHIFT}, /* H */ + {0x0c, KEY_SHIFT}, /* I */ + {0x0d, KEY_SHIFT}, /* J */ + {0x0e, KEY_SHIFT}, /* K */ + {0x0f, KEY_SHIFT}, /* L */ + {0x10, KEY_SHIFT}, /* M */ + {0x11, KEY_SHIFT}, /* N */ + {0x12, KEY_SHIFT}, /* O */ + {0x13, KEY_SHIFT}, /* P */ + {0x14, KEY_SHIFT}, /* Q */ + {0x15, KEY_SHIFT}, /* R */ + {0x16, KEY_SHIFT}, /* S */ + {0x17, KEY_SHIFT}, /* T */ + {0x18, KEY_SHIFT}, /* U */ + {0x19, KEY_SHIFT}, /* V */ + {0x1a, KEY_SHIFT}, /* W */ + {0x1b, KEY_SHIFT}, /* X */ + {0x1c, KEY_SHIFT}, /* Y */ + {0x1d, KEY_SHIFT}, /* Z */ + {0x2f, 0}, /* [ */ + {0x64, 0}, /* \ */ + {0x30, 0}, /* ] */ + {0x23, KEY_SHIFT}, /* ^ */ + {0x2d, KEY_SHIFT}, /* _ */ + {0x35, 0}, /* ` */ + {0x04, 0}, /* a */ + {0x05, 0}, /* b */ + {0x06, 0}, /* c */ + {0x07, 0}, /* d */ + {0x08, 0}, /* e */ + {0x09, 0}, /* f */ + {0x0a, 0}, /* g */ + {0x0b, 0}, /* h */ + {0x0c, 0}, /* i */ + {0x0d, 0}, /* j */ + {0x0e, 0}, /* k */ + {0x0f, 0}, /* l */ + {0x10, 0}, /* m */ + {0x11, 0}, /* n */ + {0x12, 0}, /* o */ + {0x13, 0}, /* p */ + {0x14, 0}, /* q */ + {0x15, 0}, /* r */ + {0x16, 0}, /* s */ + {0x17, 0}, /* t */ + {0x18, 0}, /* u */ + {0x19, 0}, /* v */ + {0x1a, 0}, /* w */ + {0x1b, 0}, /* x */ + {0x1c, 0}, /* y */ + {0x1d, 0}, /* z */ + {0x2f, KEY_SHIFT}, /* { */ + {0x64, KEY_SHIFT}, /* | */ + {0x30, KEY_SHIFT}, /* } */ + {0x32, KEY_SHIFT}, /* ~ */ + {0, 0}, /* DEL */ + + {0x3a, 0}, /* F1 */ + {0x3b, 0}, /* F2 */ + {0x3c, 0}, /* F3 */ + {0x3d, 0}, /* F4 */ + {0x3e, 0}, /* F5 */ + {0x3f, 0}, /* F6 */ + {0x40, 0}, /* F7 */ + {0x41, 0}, /* F8 */ + {0x42, 0}, /* F9 */ + {0x43, 0}, /* F10 */ + {0x44, 0}, /* F11 */ + {0x45, 0}, /* F12 */ + + {0x46, 0}, /* PRINT_SCREEN */ + {0x47, 0}, /* SCROLL_LOCK */ + {0x39, 0}, /* CAPS_LOCK */ + {0x53, 0}, /* NUM_LOCK */ + {0x49, 0}, /* INSERT */ + {0x4a, 0}, /* HOME */ + {0x4b, 0}, /* PAGE_UP */ + {0x4e, 0}, /* PAGE_DOWN */ + + {0x4f, 0}, /* RIGHT_ARROW */ + {0x50, 0}, /* LEFT_ARROW */ + {0x51, 0}, /* DOWN_ARROW */ + {0x52, 0}, /* UP_ARROW */ +}; +#endif + +#endif diff --git a/libraries/BLE/src/HIDTypes.h b/libraries/BLE/src/HIDTypes.h new file mode 100644 index 0000000..2dbdadc --- /dev/null +++ b/libraries/BLE/src/HIDTypes.h @@ -0,0 +1,96 @@ +/* Copyright (c) 2010-2011 mbed.org, MIT License +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* and associated documentation files (the "Software"), to deal in the Software without +* restriction, including without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#ifndef USBCLASS_HID_TYPES +#define USBCLASS_HID_TYPES + +#include + +/* */ +#define HID_VERSION_1_11 (0x0111) + +/* HID Class */ +#define BLE_HID_CLASS (3) +#define BLE_HID_SUBCLASS_NONE (0) +#define BLE_HID_PROTOCOL_NONE (0) + +/* Descriptors */ +#define HID_DESCRIPTOR (33) +#define HID_DESCRIPTOR_LENGTH (0x09) +#define REPORT_DESCRIPTOR (34) + +/* Class requests */ +#define GET_REPORT (0x1) +#define GET_IDLE (0x2) +#define SET_REPORT (0x9) +#define SET_IDLE (0xa) + +/* HID Class Report Descriptor */ +/* Short items: size is 0, 1, 2 or 3 specifying 0, 1, 2 or 4 (four) bytes */ +/* of data as per HID Class standard */ + +/* Main items */ +#ifdef ARDUINO_ARCH_ESP32 +#define HIDINPUT(size) (0x80 | size) +#define HIDOUTPUT(size) (0x90 | size) +#else +#define INPUT(size) (0x80 | size) +#define OUTPUT(size) (0x90 | size) +#endif +#define FEATURE(size) (0xb0 | size) +#define COLLECTION(size) (0xa0 | size) +#define END_COLLECTION(size) (0xc0 | size) + +/* Global items */ +#define USAGE_PAGE(size) (0x04 | size) +#define LOGICAL_MINIMUM(size) (0x14 | size) +#define LOGICAL_MAXIMUM(size) (0x24 | size) +#define PHYSICAL_MINIMUM(size) (0x34 | size) +#define PHYSICAL_MAXIMUM(size) (0x44 | size) +#define UNIT_EXPONENT(size) (0x54 | size) +#define UNIT(size) (0x64 | size) +#define REPORT_SIZE(size) (0x74 | size) //bits +#define REPORT_ID(size) (0x84 | size) +#define REPORT_COUNT(size) (0x94 | size) //bytes +#define PUSH(size) (0xa4 | size) +#define POP(size) (0xb4 | size) + +/* Local items */ +#define USAGE(size) (0x08 | size) +#define USAGE_MINIMUM(size) (0x18 | size) +#define USAGE_MAXIMUM(size) (0x28 | size) +#define DESIGNATOR_INDEX(size) (0x38 | size) +#define DESIGNATOR_MINIMUM(size) (0x48 | size) +#define DESIGNATOR_MAXIMUM(size) (0x58 | size) +#define STRING_INDEX(size) (0x78 | size) +#define STRING_MINIMUM(size) (0x88 | size) +#define STRING_MAXIMUM(size) (0x98 | size) +#define DELIMITER(size) (0xa8 | size) + +/* HID Report */ +/* Where report IDs are used the first byte of 'data' will be the */ +/* report ID and 'length' will include this report ID byte. */ + +#define MAX_HID_REPORT_SIZE (64) + +typedef struct { + uint32_t length; + uint8_t data[MAX_HID_REPORT_SIZE]; +} HID_REPORT; + +#endif diff --git a/libraries/BLE/src/RTOS.h b/libraries/BLE/src/RTOS.h new file mode 100644 index 0000000..0f798c5 --- /dev/null +++ b/libraries/BLE/src/RTOS.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS.h + * + * Created on: Feb 24, 2017 + * Author: kolban + */ + +#ifdef __cplusplus +#ifndef MAIN_FREERTOS_H_ +#define MAIN_FREERTOS_H_ +#include "Arduino.h" +#include +#include + +#include // Include the base FreeRTOS definitions. +#include // Include the task definitions. +#include // Include the semaphore definitions. +#include // Include the ringbuffer definitions. + +/** + * @brief Interface to %FreeRTOS functions. + */ +class FreeRTOS { +public: + static void sleep(uint32_t ms); + static void startTask(void task(void *), String taskName, void *param = nullptr, uint32_t stackSize = 2048); + static void deleteTask(TaskHandle_t pTask = nullptr); + + static uint32_t getTimeSinceStart(); + + class Semaphore { + public: + Semaphore(String owner = ""); + ~Semaphore(); + void give(); + void give(uint32_t value); + void giveFromISR(); + void setName(String name); + bool take(String owner = ""); + bool take(uint32_t timeoutMs, String owner = ""); + String toString(); + uint32_t wait(String owner = ""); + bool timedWait(String owner = "", uint32_t timeoutMs = portMAX_DELAY); + uint32_t value() { + return m_value; + }; + + private: + SemaphoreHandle_t m_semaphore; + pthread_mutex_t m_pthread_mutex; + String m_name; + String m_owner; + uint32_t m_value; + bool m_usePthreads; + }; +}; + +/** + * @brief Ringbuffer. + */ +class Ringbuffer { +public: +#ifdef ESP_IDF_VERSION_MAJOR + Ringbuffer(size_t length, RingbufferType_t type = RINGBUF_TYPE_NOSPLIT); +#else + Ringbuffer(size_t length, ringbuf_type_t type = RINGBUF_TYPE_NOSPLIT); +#endif + ~Ringbuffer(); + + void *receive(size_t *size, TickType_t wait = portMAX_DELAY); + void returnItem(void *item); + bool send(void *data, size_t length, TickType_t wait = portMAX_DELAY); + +private: + RingbufHandle_t m_handle; +}; + +#endif /* MAIN_FREERTOS_H_ */ +#else +#include "freertos/FreeRTOS.h" +#endif diff --git a/libraries/BluetoothSerial/README.md b/libraries/BluetoothSerial/README.md new file mode 100644 index 0000000..218c147 --- /dev/null +++ b/libraries/BluetoothSerial/README.md @@ -0,0 +1,78 @@ +## Bluetooth Serial Library + +A simple Serial compatible library using ESP32 classical Bluetooth Serial Port Profile (SPP) + +Note: Since version 3.0.0 this library does not support legacy pairing (using fixed PIN consisting of 4 digits). + +### How to use it? + +There are 3 basic use cases: phone, other ESP32 or any MCU with a Bluetooth serial module + +#### Phone + +- Download one of the Bluetooth terminal apps to your smartphone + + - For [Android](https://play.google.com/store/apps/details?id=de.kai_morich.serial_bluetooth_terminal) + - For [iOS](https://itunes.apple.com/us/app/hm10-bluetooth-serial-lite/id1030454675) + +- Flash an example sketch to your ESP32 + +- Scan and pair the device to your smartphone + +- Open the Bluetooth terminal app and connect + +- Enjoy + +#### ESP32 + +You can flash one of the ESP32 with the example [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) (the Master) and another ESP32 with [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino) (the Slave). +Those examples are preset to work out-of-the-box but they should be scalable to connect multiple Slaves to the Master. + +#### 3rd party Serial Bluetooth module + +Using a 3rd party Serial Bluetooth module will require to study the documentation of the particular module in order to make it work, however, one side can utilize the mentioned [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) (the Master) or [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino) (the Slave). + +### Pairing options + +There are two easy options and one difficult. + +The easy options can be used as usual. These offer pairing with and without Secure Simple Pairing (SSP). + +The difficult option offers legacy pairing (using fixed PIN) however this must be compiled with Arduino as an IDF component with disabled sdkconfig option `CONFIG_BT_SSP_ENABLED`. + +#### Without SSP + +This method will authenticate automatically any attempt to pair and should not be used if security is a concern! This option is used for the examples [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) and [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino). + +### With SSP + +The usage of SSP provides a secure connection. This option is demonstrated in the example `SerialToSerialBT_SSP``](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino) + +The Secure Simple Pairing is enabled by calling method `enableSSP` which has two variants - one is backward compatible without parameter `enableSSP()` and second with parameters `enableSSP(bool inputCapability, bool outputCapability)`. Similarly, the SSP can be disabled by calling `disableSSP()`. + +Both options must be called before `begin()` or if it is called after `begin()` the driver needs to be restarted (call `end()` followed by `begin()`) in order to take in effect enabling or disabling the SSP. + +#### The parameters define the method of authentication: + +**inputCapability** - Defines if ESP32 device has input method (Serial terminal, keyboard or similar) + +**outputCapability** - Defines if ESP32 device has output method (Serial terminal, display or similar) + +* **inputCapability=true and outputCapability=true** + * Both devices display randomly generated code and if they match the user will authenticate pairing on both devices. + * This must be implemented by registering a callback via `onConfirmRequest()` and in this callback the user will input the response and call `confirmReply(true)` if the authenticated, otherwise call `confirmReply(false)` to reject the pairing. +* **inputCapability=false and outputCapability=false** + * Only the other device authenticates pairing without any pin. +* **inputCapability=false and outputCapability=true** + * Only the other device authenticates pairing without any pin. +* **inputCapability=true and outputCapability=false** + * The user will be required to input the passkey to the ESP32 device to authenticate. + * This must be implemented by registering a callback via `onKeyRequest`()` and in this callback the entered passkey will be responded via `respondPasskey(passkey)` + +### Legacy Pairing (IDF component) + +To use Legacy pairing you will have to use [Arduino as an IDF component](https://espressif-docs.readthedocs-hosted.com/projects/arduino-esp32/en/latest/esp-idf_component.html) and disable option `CONFIG_BT_SSP_ENABLED`. +Please refer to the documentation on how to setup Arduino as an IDF component and when you are done, run `idf.py menuconfig` navigate to `Component Config -> Bluetooth -> Bluedroid -> [ ] Secure Simple Pairing` and disable it. +While in the menuconfig you will also need to change the partition scheme `Partition Table -> Partition Table -> (X) Single Factory app (large), no OTA`. +After these changes save & quit menuconfig and you are ready to go: `idf.py monitor flash`. +Please note that to use the PIN in smartphones and computers you need to use characters `SerialBT.setPin("1234", 4);` not a number `SerialBT.setPin(1234, 4);` . Numbers CAN be used if the other side uses them too, but phones and computers use characters. diff --git a/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino b/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino new file mode 100644 index 0000000..6c91cf2 --- /dev/null +++ b/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino @@ -0,0 +1,110 @@ +/** + * Bluetooth Classic Example + * Scan for devices - asynchronously, print device as soon as found + * query devices for SPP - SDP profile + * connect to first device offering a SPP connection + * + * Example python server: + * source: https://gist.github.com/ukBaz/217875c83c2535d22a16ba38fc8f2a91 + * + * Tested with Raspberry Pi onboard Wifi/BT, USB BT 4.0 dongles, USB BT 1.1 dongles, + * 202202: does NOT work with USB BT 2.0 dongles when esp32 arduino lib is compiled with SSP support! + * see https://github.com/espressif/esp-idf/issues/8394 + * + * use ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE in connect() if remote side requests 'RequireAuthentication': dbus.Boolean(True), + * use ESP_SPP_SEC_NONE or ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE in connect() if remote side has Authentication: False + */ + +#include +#include + +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip. +#endif + +BluetoothSerial SerialBT; + +#define BT_DISCOVER_TIME 10000 +esp_spp_sec_t sec_mask = ESP_SPP_SEC_NONE; // or ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE to request pincode confirmation +esp_spp_role_t role = ESP_SPP_ROLE_SLAVE; // or ESP_SPP_ROLE_MASTER + +// std::map btDeviceList; + +void setup() { + Serial.begin(115200); + if (!SerialBT.begin("ESP32test", true)) { + Serial.println("========== serialBT failed!"); + abort(); + } + // SerialBT.setPin("1234"); // doesn't seem to change anything + // SerialBT.enableSSP(); // doesn't seem to change anything + + Serial.println("Starting discoverAsync..."); + BTScanResults *btDeviceList = SerialBT.getScanResults(); // maybe accessing from different threads! + if (SerialBT.discoverAsync([](BTAdvertisedDevice *pDevice) { + // BTAdvertisedDeviceSet*set = reinterpret_cast(pDevice); + // btDeviceList[pDevice->getAddress()] = * set; + Serial.printf(">>>>>>>>>>>Found a new device asynchronously: %s\n", pDevice->toString().c_str()); + })) { + delay(BT_DISCOVER_TIME); + Serial.print("Stopping discoverAsync... "); + SerialBT.discoverAsyncStop(); + Serial.println("discoverAsync stopped"); + delay(5000); + if (btDeviceList->getCount() > 0) { + BTAddress addr; + int channel = 0; + Serial.println("Found devices:"); + for (int i = 0; i < btDeviceList->getCount(); i++) { + BTAdvertisedDevice *device = btDeviceList->getDevice(i); + Serial.printf(" ----- %s %s %d\n", device->getAddress().toString().c_str(), device->getName().c_str(), device->getRSSI()); + std::map channels = SerialBT.getChannels(device->getAddress()); + Serial.printf("scanned for services, found %zu\n", channels.size()); + for (auto const &entry : channels) { + Serial.printf(" channel %d (%s)\n", entry.first, entry.second.c_str()); + } + if (channels.size() > 0) { + addr = device->getAddress(); + channel = channels.begin()->first; + } + } + if (addr) { + Serial.printf("connecting to %s - %d\n", addr.toString().c_str(), channel); + SerialBT.connect(addr, channel, sec_mask, role); + } + } else { + Serial.println("Didn't find any devices"); + } + } else { + Serial.println("Error on discoverAsync f.e. not working after a \"connect\""); + } +} + +String sendData = "Hi from esp32!\n"; + +void loop() { + if (!SerialBT.isClosed() && SerialBT.connected()) { + if (SerialBT.write((const uint8_t *)sendData.c_str(), sendData.length()) != sendData.length()) { + Serial.println("tx: error"); + } else { + Serial.printf("tx: %s", sendData.c_str()); + } + if (SerialBT.available()) { + Serial.print("rx: "); + while (SerialBT.available()) { + int c = SerialBT.read(); + if (c >= 0) { + Serial.print((char)c); + } + } + Serial.println(); + } + } else { + Serial.println("not connected"); + } + delay(1000); +} diff --git a/libraries/BluetoothSerial/examples/DiscoverConnect/ci.yml b/libraries/BluetoothSerial/examples/DiscoverConnect/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/DiscoverConnect/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino b/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino new file mode 100644 index 0000000..32e782b --- /dev/null +++ b/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino @@ -0,0 +1,49 @@ +// This example demonstrates usage of BluetoothSerial method to retrieve MAC address of local BT device in various formats. +// By Tomas Pilny - 2023 + +#include "BluetoothSerial.h" + +String device_name = "ESP32-example"; + +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip. +#endif + +BluetoothSerial SerialBT; + +void setup() { + Serial.begin(115200); + SerialBT.begin(device_name); //Bluetooth device name + + uint8_t mac_arr[6]; // Byte array to hold the MAC address from getBtAddress() + BTAddress mac_obj; // Object holding instance of BTAddress with the MAC (for more details see libraries/BluetoothSerial/src/BTAddress.h) + String mac_str; // String holding the text version of MAC in format AA:BB:CC:DD:EE:FF + + SerialBT.getBtAddress(mac_arr); // Fill in the array + mac_obj = SerialBT.getBtAddressObject(); // Instantiate the object + mac_str = SerialBT.getBtAddressString(); // Copy the string + + Serial.print("This device is instantiated with name "); + Serial.println(device_name); + + Serial.print("The mac address using byte array: "); + for (int i = 0; i < ESP_BD_ADDR_LEN - 1; i++) { + Serial.print(mac_arr[i], HEX); + Serial.print(":"); + } + Serial.println(mac_arr[ESP_BD_ADDR_LEN - 1], HEX); + + Serial.print("The mac address using BTAddress object using default method `toString()`: "); + Serial.println(mac_obj.toString().c_str()); + Serial.print("The mac address using BTAddress object using method `toString(true)`\n\twhich prints the MAC with capital letters: "); + Serial.println(mac_obj.toString(true).c_str()); // This actually what is used inside the getBtAddressString() + + Serial.print("The mac address using string: "); + Serial.println(mac_str.c_str()); +} + +void loop() {} diff --git a/libraries/BluetoothSerial/examples/GetLocalMAC/ci.yml b/libraries/BluetoothSerial/examples/GetLocalMAC/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/GetLocalMAC/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino new file mode 100644 index 0000000..53579c7 --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino @@ -0,0 +1,39 @@ +// This example code is in the Public Domain (or CC0 licensed, at your option.) +// By Evandro Copercini - 2018 +// +// This example creates a bridge between Serial and Classical Bluetooth (SPP) +// and also demonstrate that SerialBT have the same functionalities of a normal Serial +// Note: Pairing is authenticated automatically by this device + +#include "BluetoothSerial.h" + +String device_name = "ESP32-BT-Slave"; + +// Check if Bluetooth is available +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +// Check Serial Port Profile +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip. +#endif + +BluetoothSerial SerialBT; + +void setup() { + Serial.begin(115200); + SerialBT.begin(device_name); //Bluetooth device name + //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin + Serial.printf("The device with name \"%s\" is started.\nNow you can pair it with Bluetooth!\n", device_name.c_str()); +} + +void loop() { + if (Serial.available()) { + SerialBT.write(Serial.read()); + } + if (SerialBT.available()) { + Serial.write(SerialBT.read()); + } + delay(20); +} diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.yml b/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino b/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino new file mode 100644 index 0000000..64774d4 --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino @@ -0,0 +1,97 @@ +// This example code is in the Public Domain (or CC0 licensed, at your option.) +// By Victor Tchistiak - 2019 +// +// This example demonstrates master mode Bluetooth connection to a slave BT device +// defined either by String "slaveName" by default "ESP32-BT-Slave" or by MAC address +// +// This example creates a bridge between Serial and Classical Bluetooth (SPP) +// This is an extension of the SerialToSerialBT example by Evandro Copercini - 2018 +// +// DO NOT try to connect to phone or laptop - they are master +// devices, same as the ESP using this code - you will be able +// to pair, but the serial communication will NOT work! +// +// You can try to flash a second ESP32 with the example SerialToSerialBT - it should +// automatically pair with ESP32 running this code +// Note: Pairing is authenticated automatically by this device + +#include "BluetoothSerial.h" + +#define USE_NAME // Comment this to use MAC address instead of a slaveName + +// Check if Bluetooth is available +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +// Check Serial Port Profile +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip. +#endif +BluetoothSerial SerialBT; + +#ifdef USE_NAME +String slaveName = "ESP32-BT-Slave"; // Change this to reflect the real name of your slave BT device +#else +String MACadd = "AA:BB:CC:11:22:33"; // This only for printing +uint8_t address[6] = {0xAA, 0xBB, 0xCC, 0x11, 0x22, 0x33}; // Change this to reflect real MAC address of your slave BT device +#endif + +String myName = "ESP32-BT-Master"; + +void setup() { + bool connected; + Serial.begin(115200); + + SerialBT.begin(myName, true); + //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin + Serial.printf("The device \"%s\" started in master mode, make sure slave BT device is on!\n", myName.c_str()); + +#ifndef USE_NAME + SerialBT.setPin(pin); + Serial.println("Using PIN"); +#endif + +// connect(address) is fast (up to 10 secs max), connect(slaveName) is slow (up to 30 secs max) as it needs +// to resolve slaveName to address first, but it allows to connect to different devices with the same name. +// Set CoreDebugLevel to Info to view devices Bluetooth address and device names +#ifdef USE_NAME + connected = SerialBT.connect(slaveName); + Serial.printf("Connecting to slave BT device named \"%s\"\n", slaveName.c_str()); +#else + connected = SerialBT.connect(address); + Serial.print("Connecting to slave BT device with MAC "); + Serial.println(MACadd); +#endif + + if (connected) { + Serial.println("Connected Successfully!"); + } else { + while (!SerialBT.connected(10000)) { + Serial.println("Failed to connect. Make sure remote device is available and in range, then restart app."); + } + } + // Disconnect() may take up to 10 secs max + if (SerialBT.disconnect()) { + Serial.println("Disconnected Successfully!"); + } + // This would reconnect to the slaveName(will use address, if resolved) or address used with connect(slaveName/address). + SerialBT.connect(); + if (connected) { + Serial.println("Reconnected Successfully!"); + } else { + while (!SerialBT.connected(10000)) { + Serial.println("Failed to reconnect. Make sure remote device is available and in range, then restart app."); + } + } +} + +void loop() { + if (Serial.available()) { + SerialBT.write(Serial.read()); + } + if (SerialBT.available()) { + Serial.write(SerialBT.read()); + } + delay(20); +} diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.yml b/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino new file mode 100644 index 0000000..d184a4e --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino @@ -0,0 +1,58 @@ +// This example code is in the Public Domain (or CC0 licensed, at your option.) +// +// This example creates a bridge between Serial and Classical Bluetooth (SPP with authentication) +// and also demonstrate that SerialBT have the same functionalities of a normal Serial +// Legacy pairing TODO +// Must be run as idf component ... todo + +#include "BluetoothSerial.h" + +// Check if Bluetooth is available +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +// Check Serial Port Profile +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip. +#endif + +const char *deviceName = "ESP32_Legacy_example"; + +BluetoothSerial SerialBT; +bool confirmRequestDone = false; + +void BTAuthCompleteCallback(boolean success) { + if (success) { + confirmRequestDone = true; + Serial.println("Pairing success!!"); + } else { + Serial.println("Pairing failed, rejected by user!!"); + } +} + +void serial_response() { + if (Serial.available()) { + SerialBT.write(Serial.read()); + } + if (SerialBT.available()) { + Serial.write(SerialBT.read()); + } + delay(20); +} + +void setup() { + Serial.begin(115200); + SerialBT.onAuthComplete(BTAuthCompleteCallback); + SerialBT.begin(deviceName); // Initiate Bluetooth device with name in parameter + SerialBT.setPin("1234", 4); + Serial.printf("The device started with name \"%s\", now you can pair it with Bluetooth!\n", deviceName); +} + +void loop() { + if (confirmRequestDone) { + serial_response(); + } else { + delay(1); // Feed the watchdog + } +} diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.yml b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino new file mode 100644 index 0000000..e5d05ee --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino @@ -0,0 +1,131 @@ +// This example code is in the Public Domain (or CC0 licensed, at your option.) +// By Richard Li - 2020 +// +// This example creates a bridge between Serial and Classical Bluetooth (SPP with authentication) +// and also demonstrate that SerialBT have the same functionalities of a normal Serial +// SSP - Simple Secure Pairing - The device (ESP32) will display random number and the user is responsible of comparing it to the number +// displayed on the other device (for example phone). +// If the numbers match the user authenticates the pairing on both devices - on phone simply press "Pair" and in terminal for the sketch send 'Y' or 'y' to confirm. +// Alternatively uncomment AUTO_PAIR to skip the terminal confirmation. + +#include "BluetoothSerial.h" + +//#define AUTO_PAIR // Uncomment to automatically authenticate ESP32 side + +// Check if Bluetooth is available +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +// Check Serial Port Profile +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip. +#endif + +const char *deviceName = "ESP32_SSP_example"; + +// The following lines defines the method of pairing +// When both Input and Output are false only the other device authenticates pairing without any pin. +// When Output is true and Input is false only the other device authenticates pairing without any pin. +// When both Input and Output are true both devices display randomly generated code and if they match authenticate pairing on both devices +// - This must be implemented by registering callback via onConfirmRequest() and in this callback request user input and call confirmReply(true); if the authenticated +// otherwise call `confirmReply(false)` to reject the pairing. +// When Input is true and Output is false User will be required to input the passkey to the ESP32 device to authenticate. +// - This must be implemented by registering callback via onKeyRequest() and in this callback the entered passkey will be responded via respondPasskey(passkey); +const bool INPUT_CAPABILITY = false; // Defines if ESP32 device has input method (Serial terminal, keyboard or similar) +const bool OUTPUT_CAPABILITY = true; // Defines if ESP32 device has output method (Serial terminal, display or similar) + +BluetoothSerial SerialBT; +bool confirmRequestDone = false; + +void BTConfirmRequestCallback(uint32_t numVal) { + confirmRequestDone = false; +#ifndef AUTO_PAIR + Serial.printf( + "The PIN is: %06lu. If it matches number displayed on the other device write \'Y\' or \'y\':\n", numVal + ); // Note the formatting "%06lu" - PIN can start with zero(s) which would be ignored with simple "%lu" + while (!Serial.available()) { + delay(1); // Feed the watchdog + // Wait until data is available on the Serial port. + } + Serial.printf("Oh you sent %d Bytes, lets see...", Serial.available()); + int dat = Serial.read(); + if (dat == 'Y' || dat == 'y') { + SerialBT.confirmReply(true); + } else { + SerialBT.confirmReply(false); + } +#else + SerialBT.confirmReply(true); +#endif +} + +void BTKeyRequestCallback() { + Serial.println("BTKeyRequestCallback"); // debug + char buffer[7] = {0}; // 6 bytes for number, one for termination '0' + while (1) { + Serial.print("Enter the passkey displayed on the other device: "); + while (!Serial.available()) { + delay(1); // Feed the watchdog + // Wait until data is available on the Serial port. + } + size_t len = Serial.readBytesUntil('\n', buffer, sizeof(buffer) - 1); + buffer[len] = '\0'; // Null-terminate the string. + try { + uint32_t passkey = std::stoi(buffer); + Serial.printf("Entered PIN: %lu\n", passkey); + SerialBT.respondPasskey(passkey); + return; + } catch (...) { + Serial.print("Wrong PIN! Try again."); + } // try + } // while(1) +} + +void BTAuthCompleteCallback(boolean success) { + if (success) { + confirmRequestDone = true; + Serial.println("Pairing success!!"); + } else { + Serial.println("Pairing failed, rejected by user!!"); + } +} + +void serial_response() { + if (Serial.available()) { + SerialBT.write(Serial.read()); + } + if (SerialBT.available()) { + Serial.write(SerialBT.read()); + } + delay(20); +} + +void setup() { + Serial.begin(115200); + SerialBT.enableSSP(INPUT_CAPABILITY, OUTPUT_CAPABILITY); // Must be called before begin + SerialBT.onConfirmRequest(BTConfirmRequestCallback); + SerialBT.onKeyRequest(BTKeyRequestCallback); + SerialBT.onAuthComplete(BTAuthCompleteCallback); + SerialBT.begin(deviceName); // Initiate Bluetooth device with name in parameter + //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin + Serial.printf("The device started with name \"%s\", now you can pair it with Bluetooth!\n", deviceName); + if (INPUT_CAPABILITY and OUTPUT_CAPABILITY) { + Serial.println("Both devices will display randomly generated code and if they match authenticate pairing on both devices"); + } else if (not INPUT_CAPABILITY and not OUTPUT_CAPABILITY) { + Serial.println("Authenticate pairing on the other device. No PIN is used"); + } else if (not INPUT_CAPABILITY and OUTPUT_CAPABILITY) { + Serial.println("Authenticate pairing on the other device. No PIN is used"); + } else if (INPUT_CAPABILITY and not OUTPUT_CAPABILITY) { + Serial.println("After pairing is initiated you will be required to enter the passkey to the ESP32 device to authenticate\n > The Passkey will displayed on " + "the other device"); + } +} + +void loop() { + if (confirmRequestDone) { + serial_response(); + } else { + delay(1); // Feed the watchdog + } +} diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.yml b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino new file mode 100644 index 0000000..226cbd8 --- /dev/null +++ b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino @@ -0,0 +1,53 @@ +#include + +#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED) +#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it +#endif + +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip. +#endif + +BluetoothSerial SerialBT; + +#define BT_DISCOVER_TIME 10000 + +static bool btScanAsync = true; +static bool btScanSync = true; + +void btAdvertisedDeviceFound(BTAdvertisedDevice *pDevice) { + Serial.printf("Found a device asynchronously: %s\n", pDevice->toString().c_str()); +} + +void setup() { + Serial.begin(115200); + SerialBT.begin("ESP32test"); //Bluetooth device name + Serial.println("The device started, now you can pair it with bluetooth!"); + + if (btScanAsync) { + Serial.print("Starting asynchronous discovery... "); + if (SerialBT.discoverAsync(btAdvertisedDeviceFound)) { + Serial.println("Findings will be reported in \"btAdvertisedDeviceFound\""); + delay(10000); + Serial.print("Stopping discoverAsync... "); + SerialBT.discoverAsyncStop(); + Serial.println("stopped"); + } else { + Serial.println("Error on discoverAsync f.e. not working after a \"connect\""); + } + } + + if (btScanSync) { + Serial.println("Starting synchronous discovery... "); + BTScanResults *pResults = SerialBT.discover(BT_DISCOVER_TIME); + if (pResults) { + pResults->dump(&Serial); + } else { + Serial.println("Error on BT Scan, no result!"); + } + } +} + +void loop() { + delay(100); +} diff --git a/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.yml b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino new file mode 100644 index 0000000..6f301bd --- /dev/null +++ b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino @@ -0,0 +1,73 @@ +// This example code is in the Public Domain (or CC0 licensed, at your option.) +// Originally by Victor Tchistiak - 2019 +// Rewritten with new API by Tomas Pilny - 2023 +// +// This example demonstrates reading and removing paired devices stored on the ESP32 flash memory +// Sometimes you may find your ESP32 device could not connect to the remote device despite +// many successful connections earlier. This is most likely a result of client replacing your paired +// device info with new one from other device. The BT clients store connection info for paired devices, +// but it is limited to a few devices only. When new device pairs and number of stored devices is exceeded, +// one of the previously paired devices would be replaced with new one. +// The only remedy is to delete this saved bound device from your device flash memory +// and pair with the other device again. + +#include "BluetoothSerial.h" +//#include "esp_bt_device.h" + +#if !defined(CONFIG_BT_SPP_ENABLED) +#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip. +#endif + +#define REMOVE_BONDED_DEVICES true // <- Set to `false` to view all bonded devices addresses, set to `true` to remove +#define PAIR_MAX_DEVICES 20 +BluetoothSerial SerialBT; + +char *bda2str(const uint8_t *bda, char *str, size_t size) { + if (bda == NULL || str == NULL || size < 18) { + return NULL; + } + sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x", bda[0], bda[1], bda[2], bda[3], bda[4], bda[5]); + return str; +} + +void setup() { + char bda_str[18]; + uint8_t pairedDeviceBtAddr[PAIR_MAX_DEVICES][6]; + Serial.begin(115200); + + SerialBT.begin(); + Serial.printf("ESP32 bluetooth address: %s\n", SerialBT.getBtAddressString().c_str()); + // SerialBT.deleteAllBondedDevices(); // If you want just delete all, this is the way + // Get the numbers of bonded/paired devices in the BT module + int count = SerialBT.getNumberOfBondedDevices(); + if (!count) { + Serial.println("No bonded devices found."); + } else { + Serial.printf("Bonded device count: %d\n", count); + if (PAIR_MAX_DEVICES < count) { + count = PAIR_MAX_DEVICES; + Serial.printf("Reset %d bonded devices\n", count); + } + count = SerialBT.getBondedDevices(count, pairedDeviceBtAddr); + char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]; + if (count > 0) { + for (int i = 0; i < count; i++) { + SerialBT.requestRemoteName(pairedDeviceBtAddr[i]); + while (!SerialBT.readRemoteName(rmt_name)) { + delay(1); // Wait for response with the device name + } + Serial.printf("Found bonded device #%d BDA:%s; Name:\"%s\"\n", i, bda2str(pairedDeviceBtAddr[i], bda_str, 18), rmt_name); + SerialBT.invalidateRemoteName(); // Allows waiting for next reading + if (REMOVE_BONDED_DEVICES) { + if (SerialBT.deleteBondedDevice(pairedDeviceBtAddr[i])) { + Serial.printf("Removed bonded device # %d\n", i); + } else { + Serial.printf("Failed to remove bonded device # %d", i); + } // if(ESP_OK == tError) + } // if(REMOVE_BONDED_DEVICES) + } // for(int i = 0; i < count; i++) + } // if(ESP_OK == tError) + } // if(!count) +} + +void loop() {} diff --git a/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.yml b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.yml new file mode 100644 index 0000000..335e5be --- /dev/null +++ b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_BT_SPP_ENABLED=y diff --git a/libraries/BluetoothSerial/keywords.txt b/libraries/BluetoothSerial/keywords.txt new file mode 100644 index 0000000..563e35d --- /dev/null +++ b/libraries/BluetoothSerial/keywords.txt @@ -0,0 +1,26 @@ +####################################### +# Syntax Coloring Map For BluetoothSerial +####################################### + +####################################### +# Library (KEYWORD3) +####################################### + +BluetoothSerial KEYWORD3 + +####################################### +# Datatypes (KEYWORD1) +####################################### + +BluetoothSerial KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +SerialBT KEYWORD2 +hasClient KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/BluetoothSerial/library.properties b/libraries/BluetoothSerial/library.properties new file mode 100644 index 0000000..98f587d --- /dev/null +++ b/libraries/BluetoothSerial/library.properties @@ -0,0 +1,9 @@ +name=BluetoothSerial +version=3.3.7 +author=Evandro Copercini +maintainer=Evandro Copercini +sentence=Simple UART to Classical Bluetooth bridge for ESP32 +paragraph= +category=Communication +url= +architectures=esp32 diff --git a/libraries/BluetoothSerial/src/BTAddress.cpp b/libraries/BluetoothSerial/src/BTAddress.cpp new file mode 100644 index 0000000..6dc05f3 --- /dev/null +++ b/libraries/BluetoothSerial/src/BTAddress.cpp @@ -0,0 +1,114 @@ +/* + * BTAddress.cpp + * + * Created on: Jul 2, 2017 + * Author: kolban + * Ported on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +#include "BTAddress.h" +#include +#include +#include +#include +#include +#include +#ifdef ARDUINO_ARCH_ESP32 +#include "esp32-hal-log.h" +#endif + +/** + * @brief Create an address from the native ESP32 representation. + * @param [in] address The native representation. + */ +BTAddress::BTAddress(esp_bd_addr_t address) { + memcpy(m_address, address, ESP_BD_ADDR_LEN); +} // BTAddress + +BTAddress::BTAddress() { + bzero(m_address, ESP_BD_ADDR_LEN); +} // BTAddress + +/** + * @brief Create an address from a hex string + * + * A hex string is of the format: + * ``` + * 00:00:00:00:00:00 + * ``` + * which is 17 characters in length. + * + * @param [in] stringAddress The hex representation of the address. + */ +BTAddress::BTAddress(String stringAddress) { + if (stringAddress.length() != 17) { + return; + } + + int data[6]; + sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[0], &data[1], &data[2], &data[3], &data[4], &data[5]); + m_address[0] = (uint8_t)data[0]; + m_address[1] = (uint8_t)data[1]; + m_address[2] = (uint8_t)data[2]; + m_address[3] = (uint8_t)data[3]; + m_address[4] = (uint8_t)data[4]; + m_address[5] = (uint8_t)data[5]; +} // BTAddress + +/** + * @brief Determine if this address equals another. + * @param [in] otherAddress The other address to compare against. + * @return True if the addresses are equal. + */ +bool BTAddress::equals(BTAddress otherAddress) { + return memcmp(otherAddress.getNative(), m_address, 6) == 0; +} // equals + +BTAddress::operator bool() const { + for (int i = 0; i < ESP_BD_ADDR_LEN; i++) { + if (this->m_address[i]) { + return true; + } + } + return false; +} // operator () + +/** + * @brief Return the native representation of the address. + * @return The native representation of the address. + */ +esp_bd_addr_t *BTAddress::getNative() const { + return const_cast(&m_address); +} // getNative + +/** + * @brief Convert a BT address to a string. + * @param [in] capital changes the letter size + * By default the parameter `capital` == false and the string representation of an address is in the format: + * ``` + * xx:xx:xx:xx:xx:xx + * ``` + * When the parameter `capital` == true the format uses capital letters: + * ``` + * XX:XX:XX:XX:XX:XX + * ``` + * @return The string representation of the address. + */ +String BTAddress::toString(bool capital) const { + auto size = 18; + char *res = (char *)malloc(size); + if (capital) { + snprintf(res, size, "%02X:%02X:%02X:%02X:%02X:%02X", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]); + } else { + snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]); + } + String ret(res); + free(res); + return ret; +} // toString +#endif diff --git a/libraries/BluetoothSerial/src/BTAddress.h b/libraries/BluetoothSerial/src/BTAddress.h new file mode 100644 index 0000000..ece3ae8 --- /dev/null +++ b/libraries/BluetoothSerial/src/BTAddress.h @@ -0,0 +1,40 @@ +/* + * BTAddress.h + * + * Created on: Jul 2, 2017 + * Author: kolban + * Ported on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ + +#ifndef COMPONENTS_CPP_UTILS_BTADDRESS_H_ +#define COMPONENTS_CPP_UTILS_BTADDRESS_H_ +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) +#include // ESP32 BT +#include + +/** + * @brief A %BT device address. + * + * Every %BT device has a unique address which can be used to identify it and form connections. + */ +class BTAddress { +public: + BTAddress(); + BTAddress(esp_bd_addr_t address); + BTAddress(String stringAddress); + bool equals(BTAddress otherAddress); + operator bool() const; + + esp_bd_addr_t *getNative() const; + String toString(bool capital = false) const; + +private: + esp_bd_addr_t m_address; +}; + +#endif /* CONFIG_BT_ENABLED */ +#endif /* COMPONENTS_CPP_UTILS_BTADDRESS_H_ */ diff --git a/libraries/BluetoothSerial/src/BTAdvertisedDevice.h b/libraries/BluetoothSerial/src/BTAdvertisedDevice.h new file mode 100644 index 0000000..53aa262 --- /dev/null +++ b/libraries/BluetoothSerial/src/BTAdvertisedDevice.h @@ -0,0 +1,63 @@ +/* + * BTAdvertisedDevice.h + * + * Created on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ + +#pragma once +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) +#include "BTAddress.h" +#include + +class BTAdvertisedDevice { +public: + virtual ~BTAdvertisedDevice() = default; + + virtual BTAddress getAddress() = 0; + virtual uint32_t getCOD() const = 0; + virtual std::string getName() const = 0; + virtual int8_t getRSSI() const = 0; + + virtual bool haveCOD() const = 0; + virtual bool haveName() const = 0; + virtual bool haveRSSI() const = 0; + + virtual std::string toString() = 0; +}; + +class BTAdvertisedDeviceSet : public virtual BTAdvertisedDevice { +public: + BTAdvertisedDeviceSet(); + //~BTAdvertisedDeviceSet() = default; + + BTAddress getAddress(); + uint32_t getCOD() const; + std::string getName() const; + int8_t getRSSI() const; + + bool haveCOD() const; + bool haveName() const; + bool haveRSSI() const; + + std::string toString(); + + void setAddress(BTAddress address); + void setCOD(uint32_t cod); + void setName(std::string name); + void setRSSI(int8_t rssi); + + bool m_haveCOD; + bool m_haveName; + bool m_haveRSSI; + + BTAddress m_address = BTAddress((uint8_t *)"\0\0\0\0\0\0"); + uint32_t m_cod; + std::string m_name; + int8_t m_rssi; +}; + +#endif diff --git a/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp b/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp new file mode 100644 index 0000000..9afc285 --- /dev/null +++ b/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp @@ -0,0 +1,91 @@ +/* + * BTAdvertisedDeviceSet.cpp + * + * Created on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ + +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +//#include + +#include "BTAdvertisedDevice.h" +//#include "BTScan.h" + +BTAdvertisedDeviceSet::BTAdvertisedDeviceSet() { + m_cod = 0; + m_name = ""; + m_rssi = 0; + + m_haveCOD = false; + m_haveName = false; + m_haveRSSI = false; +} // BTAdvertisedDeviceSet + +BTAddress BTAdvertisedDeviceSet::getAddress() { + return m_address; +} +uint32_t BTAdvertisedDeviceSet::getCOD() const { + return m_cod; +} +std::string BTAdvertisedDeviceSet::getName() const { + return m_name; +} +int8_t BTAdvertisedDeviceSet::getRSSI() const { + return m_rssi; +} + +bool BTAdvertisedDeviceSet::haveCOD() const { + return m_haveCOD; +} +bool BTAdvertisedDeviceSet::haveName() const { + return m_haveName; +} +bool BTAdvertisedDeviceSet::haveRSSI() const { + return m_haveRSSI; +} + +/** + * @brief Create a string representation of this device. + * @return A string representation of this device. + */ +std::string BTAdvertisedDeviceSet::toString() { + std::string res = "Name: " + getName() + ", Address: " + std::string(getAddress().toString().c_str(), getAddress().toString().length()); + if (haveCOD()) { + char val[7]; //6 hex digits + null + snprintf(val, sizeof(val), "%06lx", getCOD() & 0xFFFFFF); + res += ", cod: 0x"; + res += val; + } + if (haveRSSI()) { + char val[6]; + snprintf(val, sizeof(val), "%d", (int8_t)getRSSI()); + res += ", rssi: "; + res += val; + } + return res; +} // toString + +void BTAdvertisedDeviceSet::setAddress(BTAddress address) { + m_address = address; +} + +void BTAdvertisedDeviceSet::setCOD(uint32_t cod) { + m_cod = cod; + m_haveCOD = true; +} + +void BTAdvertisedDeviceSet::setName(std::string name) { + m_name = name; + m_haveName = true; +} + +void BTAdvertisedDeviceSet::setRSSI(int8_t rssi) { + m_rssi = rssi; + m_haveRSSI = true; +} + +#endif /* CONFIG_BT_ENABLED */ diff --git a/libraries/BluetoothSerial/src/BTScan.h b/libraries/BluetoothSerial/src/BTScan.h new file mode 100644 index 0000000..6fd2daf --- /dev/null +++ b/libraries/BluetoothSerial/src/BTScan.h @@ -0,0 +1,44 @@ +/* + * BTScan.h + * + * Created on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ + +#pragma once +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +#include +#include +#include +#include "BTAddress.h" +#include "BTAdvertisedDevice.h" + +class BTAdvertisedDevice; +class BTAdvertisedDeviceSet; + +class BTScanResults { +public: + virtual ~BTScanResults() = default; + + virtual void dump(Print *print = nullptr) = 0; + virtual int getCount() = 0; + virtual BTAdvertisedDevice *getDevice(int i) = 0; +}; + +class BTScanResultsSet : public BTScanResults { +public: + void dump(Print *print = nullptr); + int getCount(); + BTAdvertisedDevice *getDevice(int i); + + bool add(BTAdvertisedDeviceSet advertisedDevice, bool unique = true); + void clear(); + + std::map m_vectorAdvertisedDevices; +}; + +#endif diff --git a/libraries/BluetoothSerial/src/BTScanResultsSet.cpp b/libraries/BluetoothSerial/src/BTScanResultsSet.cpp new file mode 100644 index 0000000..02459b0 --- /dev/null +++ b/libraries/BluetoothSerial/src/BTScanResultsSet.cpp @@ -0,0 +1,99 @@ +/* + * BTScanResultsSet.cpp + * + * Created on: Feb 5, 2021 + * Author: Thomas M. (ArcticSnowSky) + */ + +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +#include + +#include "BTAdvertisedDevice.h" +#include "BTScan.h" +//#include "GeneralUtils.h" +#include "esp32-hal-log.h" + +class BTAdvertisedDevice; + +/** + * @brief Dump the scan results to the log. + */ +void BTScanResultsSet::dump(Print *print) { + int cnt = getCount(); + if (print == nullptr) { + log_v(">> Dump scan results : %d", cnt); + for (int i = 0; i < cnt; i++) { + BTAdvertisedDevice *dev = getDevice(i); + if (dev) { + log_d("- %d: %s\n", i + 1, dev->toString().c_str()); + } else { + log_d("- %d is null\n", i + 1); + } + } + log_v("-- dump finished --"); + } else { + print->printf(">> Dump scan results: %d\n", cnt); + for (int i = 0; i < cnt; i++) { + BTAdvertisedDevice *dev = getDevice(i); + if (dev) { + print->printf("- %d: %s\n", i + 1, dev->toString().c_str()); + } else { + print->printf("- %d is null\n", i + 1); + } + } + print->println("-- Dump finished --"); + } +} // dump + +/** + * @brief Return the count of devices found in the last scan. + * @return The number of devices found in the last scan. + */ +int BTScanResultsSet::getCount() { + return m_vectorAdvertisedDevices.size(); +} // getCount + +/** + * @brief Return the specified device at the given index. + * The index should be between 0 and getCount()-1. + * @param [in] i The index of the device. + * @return The device at the specified index. + */ +BTAdvertisedDevice *BTScanResultsSet::getDevice(int i) { + if (i < 0) { + return nullptr; + } + + int x = 0; + BTAdvertisedDeviceSet *pDev = &m_vectorAdvertisedDevices.begin()->second; + for (auto it = m_vectorAdvertisedDevices.begin(); it != m_vectorAdvertisedDevices.end(); it++) { + pDev = &it->second; + if (x == i) { + break; + } + x++; + } + return x == i ? pDev : nullptr; +} + +void BTScanResultsSet::clear() { + //for(auto _dev : m_vectorAdvertisedDevices) + // delete _dev.second; + m_vectorAdvertisedDevices.clear(); +} + +bool BTScanResultsSet::add(BTAdvertisedDeviceSet advertisedDevice, bool unique) { + std::string key = std::string(advertisedDevice.getAddress().toString().c_str(), advertisedDevice.getAddress().toString().length()); + if (!unique || m_vectorAdvertisedDevices.count(key) == 0) { + m_vectorAdvertisedDevices.insert(std::pair(key, advertisedDevice)); + return true; + } else { + return false; + } +} + +#endif diff --git a/libraries/BluetoothSerial/src/BluetoothSerial.cpp b/libraries/BluetoothSerial/src/BluetoothSerial.cpp new file mode 100644 index 0000000..9ff1cee --- /dev/null +++ b/libraries/BluetoothSerial/src/BluetoothSerial.cpp @@ -0,0 +1,1361 @@ +// Copyright 2018 Evandro Luis Copercini +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "sdkconfig.h" +#include +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +#ifdef ARDUINO_ARCH_ESP32 +#include "esp32-hal-log.h" +#include "esp32-hal-bt-mem.h" +#endif + +#include "BluetoothSerial.h" +#include "BTAdvertisedDevice.h" + +#include "esp_bt.h" +#include "esp_bt_main.h" +#include "esp_gap_bt_api.h" +#include "esp_bt_device.h" +#include "esp_spp_api.h" +#include + +#include "esp32-hal-log.h" + +const char *_spp_server_name = "ESP32SPP"; + +#define RX_QUEUE_SIZE 512 +#define TX_QUEUE_SIZE 32 +#define SPP_TX_QUEUE_TIMEOUT 1000 +#define SPP_TX_DONE_TIMEOUT 1000 +#define SPP_CONGESTED_TIMEOUT 1000 + +static uint32_t _spp_client = 0; +static QueueHandle_t _spp_rx_queue = NULL; +static QueueHandle_t _spp_tx_queue = NULL; +static SemaphoreHandle_t _spp_tx_done = NULL; +static TaskHandle_t _spp_task_handle = NULL; +static EventGroupHandle_t _spp_event_group = NULL; +static EventGroupHandle_t _bt_event_group = NULL; +static boolean secondConnectionAttempt; +static esp_spp_cb_t custom_spp_callback = NULL; +static BluetoothSerialDataCb custom_data_callback = NULL; +static esp_bd_addr_t current_bd_addr; +static ConfirmRequestCb confirm_request_callback = NULL; +static KeyRequestCb key_request_callback = NULL; +static AuthCompleteCb auth_complete_callback = NULL; +static bool _rmt_name_valid = false; +static uint8_t _rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1] = {0}; + +#define INQ_LEN 0x10 +#define INQ_NUM_RSPS 20 +#define READY_TIMEOUT (10 * 1000) +#define SCAN_TIMEOUT (INQ_LEN * 2 * 1000) +static esp_bd_addr_t _peer_bd_addr; +static char _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]; +static bool _isRemoteAddressSet; +static bool _isMaster; +static bool _enableSSP; +static bool _IO_CAP_INPUT; +static bool _IO_CAP_OUTPUT; +esp_bt_pin_code_t _pin_code = {0}; +uint8_t _pin_code_len = 0; // Number of valid Bytes in the esp_bt_pin_code_t array +static esp_spp_sec_t _sec_mask; +static esp_spp_role_t _role; +// start connect on ESP_SPP_DISCOVERY_COMP_EVT or save entry for getChannels +static bool _doConnect; +static std::map sdpRecords; + +static BTScanResultsSet scanResults; +static BTAdvertisedDeviceCb advertisedDeviceCb = nullptr; + +// _spp_event_group +#define SPP_RUNNING 0x01 +#define SPP_CONNECTED 0x02 +#define SPP_CONGESTED 0x04 +// true until OPEN successful, changes to false on CLOSE +#define SPP_DISCONNECTED 0x08 +// true until connect(), changes to true on CLOSE +#define SPP_CLOSED 0x10 + +// _bt_event_group +#define BT_DISCOVERY_RUNNING 0x01 +#define BT_DISCOVERY_COMPLETED 0x02 + +#define BT_SDP_RUNNING 0x04 +#define BT_SDP_COMPLETED 0x08 + +typedef struct { + size_t len; + uint8_t data[]; +} spp_packet_t; + +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) +static char *bda2str(esp_bd_addr_t bda, char *str, size_t size) { + if (bda == NULL || str == NULL || size < 18) { + return NULL; + } + + uint8_t *p = bda; + snprintf(str, size, "%02x:%02x:%02x:%02x:%02x:%02x", p[0], p[1], p[2], p[3], p[4], p[5]); + return str; +} +#endif + +static bool get_name_from_eir(uint8_t *eir, char *bdname, uint8_t *bdname_len) { + if (!eir || !bdname || !bdname_len) { + return false; + } + + uint8_t *rmt_bdname, rmt_bdname_len; + *bdname = *bdname_len = rmt_bdname_len = 0; + + rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_CMPL_LOCAL_NAME, &rmt_bdname_len); + if (!rmt_bdname) { + rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_SHORT_LOCAL_NAME, &rmt_bdname_len); + } + if (rmt_bdname) { + rmt_bdname_len = rmt_bdname_len > ESP_BT_GAP_MAX_BDNAME_LEN ? ESP_BT_GAP_MAX_BDNAME_LEN : rmt_bdname_len; + memcpy(bdname, rmt_bdname, rmt_bdname_len); + bdname[rmt_bdname_len] = 0; + *bdname_len = rmt_bdname_len; + return true; + } + return false; +} + +static esp_err_t _spp_queue_packet(uint8_t *data, size_t len) { + if (!data || !len) { + log_w("No data provided"); + return ESP_OK; + } + spp_packet_t *packet = (spp_packet_t *)malloc(sizeof(spp_packet_t) + len); + if (!packet) { + log_e("SPP TX Packet Malloc Failed!"); + return ESP_FAIL; + } + packet->len = len; + memcpy(packet->data, data, len); + if (!_spp_tx_queue || xQueueSend(_spp_tx_queue, &packet, SPP_TX_QUEUE_TIMEOUT) != pdPASS) { + log_e("SPP TX Queue Send Failed!"); + free(packet); + return ESP_FAIL; + } + return ESP_OK; +} + +const uint16_t SPP_TX_MAX = 330; +static uint8_t _spp_tx_buffer[SPP_TX_MAX]; +static uint16_t _spp_tx_buffer_len = 0; + +static bool _spp_send_buffer() { + if ((xEventGroupWaitBits(_spp_event_group, SPP_CONGESTED, pdFALSE, pdTRUE, SPP_CONGESTED_TIMEOUT) & SPP_CONGESTED) != 0) { + if (!_spp_client) { + log_v("SPP Client Gone!"); + return false; + } + log_v("SPP Write %u", _spp_tx_buffer_len); + esp_err_t err = esp_spp_write(_spp_client, _spp_tx_buffer_len, _spp_tx_buffer); + if (err != ESP_OK) { + log_e("SPP Write Failed! [0x%X]", err); + return false; + } + _spp_tx_buffer_len = 0; + if (xSemaphoreTake(_spp_tx_done, SPP_TX_DONE_TIMEOUT) != pdTRUE) { + log_e("SPP Ack Failed!"); + return false; + } + return true; + } + log_e("SPP Write Congested!"); + return false; +} + +static void _spp_tx_task(void *arg) { + spp_packet_t *packet = NULL; + size_t len = 0, to_send = 0; + uint8_t *data = NULL; + for (;;) { + if (_spp_tx_queue && xQueueReceive(_spp_tx_queue, &packet, portMAX_DELAY) == pdTRUE && packet) { + if (packet->len <= (SPP_TX_MAX - _spp_tx_buffer_len)) { + memcpy(_spp_tx_buffer + _spp_tx_buffer_len, packet->data, packet->len); + _spp_tx_buffer_len += packet->len; + free(packet); + packet = NULL; + if (SPP_TX_MAX == _spp_tx_buffer_len || uxQueueMessagesWaiting(_spp_tx_queue) == 0) { + _spp_send_buffer(); + } + } else { + len = packet->len; + data = packet->data; + to_send = SPP_TX_MAX - _spp_tx_buffer_len; + memcpy(_spp_tx_buffer + _spp_tx_buffer_len, data, to_send); + _spp_tx_buffer_len = SPP_TX_MAX; + data += to_send; + len -= to_send; + if (!_spp_send_buffer()) { + len = 0; + } + while (len >= SPP_TX_MAX) { + memcpy(_spp_tx_buffer, data, SPP_TX_MAX); + _spp_tx_buffer_len = SPP_TX_MAX; + data += SPP_TX_MAX; + len -= SPP_TX_MAX; + if (!_spp_send_buffer()) { + len = 0; + break; + } + } + if (len) { + memcpy(_spp_tx_buffer, data, len); + _spp_tx_buffer_len += len; + if (uxQueueMessagesWaiting(_spp_tx_queue) == 0) { + _spp_send_buffer(); + } + } + free(packet); + packet = NULL; + } + } else { + log_e("Something went horribly wrong"); + } + } + vTaskDelete(NULL); + _spp_task_handle = NULL; +} + +static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param) { + switch (event) { + case ESP_SPP_INIT_EVT: // Enum 0 - When SPP is initialized + log_i("ESP_SPP_INIT_EVT"); +#ifdef ESP_IDF_VERSION_MAJOR + esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); +#else + esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE); +#endif + log_i("ESP_SPP_INIT_EVT: %s: start", _isMaster ? "master" : "slave"); + esp_spp_start_srv(ESP_SPP_SEC_NONE, _isMaster ? ESP_SPP_ROLE_MASTER : ESP_SPP_ROLE_SLAVE, 0, _spp_server_name); + xEventGroupSetBits(_spp_event_group, SPP_RUNNING); + break; + + case ESP_SPP_UNINIT_EVT: // Enum 1 - When SPP is deinitialized + log_i("ESP_SPP_UNINIT_EVT: SPP is deinitialized"); + break; + + case ESP_SPP_DISCOVERY_COMP_EVT: // Enum 8 - When SDP discovery complete + log_i("ESP_SPP_DISCOVERY_COMP_EVT num=%d", param->disc_comp.scn_num); + if (param->disc_comp.status == ESP_SPP_SUCCESS) { + for (int i = 0; i < param->disc_comp.scn_num; i++) { + log_d("ESP_SPP_DISCOVERY_COMP_EVT: spp [%d] channel: %d service name:%s", i, param->disc_comp.scn[i], param->disc_comp.service_name[0]); + } + if (_doConnect) { + if (param->disc_comp.scn_num > 0) { +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) + char bda_str[18]; + log_i("ESP_SPP_DISCOVERY_COMP_EVT: spp connect to remote %s channel %d", bda2str(_peer_bd_addr, bda_str, sizeof(bda_str)), param->disc_comp.scn[0]); +#endif + xEventGroupClearBits(_spp_event_group, SPP_CLOSED); + if (esp_spp_connect(_sec_mask, _role, param->disc_comp.scn[0], _peer_bd_addr) != ESP_OK) { + log_e("ESP_SPP_DISCOVERY_COMP_EVT connect failed"); + xEventGroupSetBits(_spp_event_group, SPP_CLOSED); + } + } else { + log_e("ESP_SPP_DISCOVERY_COMP_EVT remote doesn't offer an SPP channel"); + xEventGroupSetBits(_spp_event_group, SPP_CLOSED); + } + } else { + for (int i = 0; i < param->disc_comp.scn_num; i++) { + sdpRecords[param->disc_comp.scn[i]] = param->disc_comp.service_name[0]; + } + } + } else { + log_e("ESP_SPP_DISCOVERY_COMP_EVT failed!, status:%d", param->disc_comp.status); + } + xEventGroupSetBits(_bt_event_group, BT_SDP_COMPLETED); + break; + + case ESP_SPP_OPEN_EVT: // Enum 26 - When SPP Client connection open + log_i("ESP_SPP_OPEN_EVT"); + if (!_spp_client) { + _spp_client = param->open.handle; + } else { + secondConnectionAttempt = true; + esp_spp_disconnect(param->open.handle); + } + xEventGroupClearBits(_spp_event_group, SPP_DISCONNECTED); + xEventGroupSetBits(_spp_event_group, SPP_CONNECTED); + xEventGroupSetBits(_spp_event_group, SPP_CONGESTED); + break; + + case ESP_SPP_CLOSE_EVT: // Enum 27 - When SPP connection closed + if ((param->close.async == false && param->close.status == ESP_SPP_SUCCESS) || param->close.async) { + log_i( + "ESP_SPP_CLOSE_EVT status:%d handle:%d close_by_remote:%d attempt %u", param->close.status, param->close.handle, param->close.async, + secondConnectionAttempt + ); + if (secondConnectionAttempt) { + secondConnectionAttempt = false; + } else { + _spp_client = 0; + xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED); + xEventGroupSetBits(_spp_event_group, SPP_CONGESTED); + xEventGroupSetBits(_spp_event_group, SPP_CLOSED); + xEventGroupClearBits(_spp_event_group, SPP_CONNECTED); + } + } else { + log_e("ESP_SPP_CLOSE_EVT failed!, status:%d", param->close.status); + } + break; + + case ESP_SPP_START_EVT: // Enum 28 - When SPP server started + log_i("ESP_SPP_START_EVT"); + break; + + case ESP_SPP_CL_INIT_EVT: // Enum 29 - When SPP client initiated a connection + if (param->cl_init.status == ESP_SPP_SUCCESS) { + log_i("ESP_SPP_CL_INIT_EVT handle:%d sec_id:%d", param->cl_init.handle, param->cl_init.sec_id); + } else { + log_i("ESP_SPP_CL_INIT_EVT status:%d", param->cl_init.status); + } + break; + + case ESP_SPP_DATA_IND_EVT: // Enum 30 - When SPP connection received data, only for ESP_SPP_MODE_CB + log_v("ESP_SPP_DATA_IND_EVT len=%d handle=%d", param->data_ind.len, param->data_ind.handle); + //esp_log_buffer_hex("",param->data_ind.data,param->data_ind.len); //for low level debug + //ets_printf("r:%u\n", param->data_ind.len); + + if (custom_data_callback) { + custom_data_callback(param->data_ind.data, param->data_ind.len); + } else if (_spp_rx_queue != NULL) { + for (int i = 0; i < param->data_ind.len; i++) { + if (xQueueSend(_spp_rx_queue, param->data_ind.data + i, (TickType_t)0) != pdTRUE) { + log_e("RX Full! Discarding %u bytes", param->data_ind.len - i); + break; + } + } + } + break; + + case ESP_SPP_CONG_EVT: // Enum 31 - When SPP connection congestion status changed, only for ESP_SPP_MODE_CB + if (param->cong.cong) { + xEventGroupClearBits(_spp_event_group, SPP_CONGESTED); + } else { + xEventGroupSetBits(_spp_event_group, SPP_CONGESTED); + } + log_v("ESP_SPP_CONG_EVT: %s", param->cong.cong ? "CONGESTED" : "FREE"); + break; + + case ESP_SPP_WRITE_EVT: // Enum 33 - When SPP write operation completes, only for ESP_SPP_MODE_CB + if (param->write.status == ESP_SPP_SUCCESS) { + if (param->write.cong) { + xEventGroupClearBits(_spp_event_group, SPP_CONGESTED); + } + log_v("ESP_SPP_WRITE_EVT: %u %s", param->write.len, param->write.cong ? "CONGESTED" : ""); + } else { + log_e("ESP_SPP_WRITE_EVT failed!, status:%d", param->write.status); + } + xSemaphoreGive(_spp_tx_done); //we can try to send another packet + break; + + case ESP_SPP_SRV_OPEN_EVT: // Enum 34 - When SPP Server connection open + if (param->srv_open.status == ESP_SPP_SUCCESS) { + log_i("ESP_SPP_SRV_OPEN_EVT: %u", _spp_client); + if (!_spp_client) { + _spp_client = param->srv_open.handle; + _spp_tx_buffer_len = 0; + } else { + secondConnectionAttempt = true; + esp_spp_disconnect(param->srv_open.handle); + } + xEventGroupClearBits(_spp_event_group, SPP_DISCONNECTED); + xEventGroupSetBits(_spp_event_group, SPP_CONNECTED); + } else { + log_e("ESP_SPP_SRV_OPEN_EVT Failed!, status:%d", param->srv_open.status); + } + break; + + case ESP_SPP_SRV_STOP_EVT: // Enum 35 - When SPP server stopped + log_i("ESP_SPP_SRV_STOP_EVT"); + break; + + case ESP_SPP_VFS_REGISTER_EVT: // Enum 36 - When SPP VFS register + log_i("ESP_SPP_VFS_REGISTER_EVT"); + break; + + case ESP_SPP_VFS_UNREGISTER_EVT: // Enum 37 - When SPP VFS unregister + log_i("ESP_SPP_VFS_UNREGISTER_EVT"); + break; + + default: log_i("ESP_SPP_* event #%d unhandled", event); break; + } + if (custom_spp_callback) { + (*custom_spp_callback)(event, param); + } +} + +void BluetoothSerial::onData(BluetoothSerialDataCb cb) { + custom_data_callback = cb; +} + +static void esp_bt_gap_cb(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param) { + switch (event) { + case ESP_BT_GAP_DISC_RES_EVT: + { // Enum 0 - Device discovery result event + log_i("ESP_BT_GAP_DISC_RES_EVT properties=%d", param->disc_res.num_prop); +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) + char bda_str[18]; + log_i("Scanned device: %s", bda2str(param->disc_res.bda, bda_str, 18)); +#endif + BTAdvertisedDeviceSet advertisedDevice; + uint8_t peer_bdname_len = 0; + char peer_bdname[ESP_BT_GAP_MAX_BDNAME_LEN + 1]; + for (int i = 0; i < param->disc_res.num_prop; i++) { + switch (param->disc_res.prop[i].type) { + case ESP_BT_GAP_DEV_PROP_BDNAME: // Enum 1 - Bluetooth device name, value type is int8_t [] + peer_bdname_len = param->disc_res.prop[i].len; + memcpy(peer_bdname, param->disc_res.prop[i].val, peer_bdname_len); + peer_bdname_len--; // len includes 0 terminator + log_v("ESP_BT_GAP_DISC_RES_EVT : BDNAME : %s : %d", peer_bdname, peer_bdname_len); + if (strlen(_remote_name) == peer_bdname_len && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) { + log_i("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_BDNAME : %s", peer_bdname); + _isRemoteAddressSet = true; + memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN); + esp_bt_gap_cancel_discovery(); + esp_spp_start_discovery(_peer_bd_addr); + } + break; + + case ESP_BT_GAP_DEV_PROP_COD: // Enum 2 - Class of Device, value type is uint32_t + if (param->disc_res.prop[i].len <= sizeof(int)) { + uint32_t cod = 0; + memcpy(&cod, param->disc_res.prop[i].val, param->disc_res.prop[i].len); + advertisedDevice.setCOD(cod); + log_d("ESP_BT_GAP_DEV_PROP_COD 0x%x", cod); + } else { + log_d("ESP_BT_GAP_DEV_PROP_COD invalid COD: Value size larger than integer"); + } + break; + + case ESP_BT_GAP_DEV_PROP_RSSI: // Enum 3 - Received Signal strength Indication, value type is int8_t, ranging from -128 to 127 + if (param->disc_res.prop[i].len <= sizeof(int)) { + uint8_t rssi = 0; + memcpy(&rssi, param->disc_res.prop[i].val, param->disc_res.prop[i].len); + log_d("ESP_BT_GAP_DEV_PROP_RSSI %d", rssi); + advertisedDevice.setRSSI(rssi); + } else { + log_d("ESP_BT_GAP_DEV_PROP_RSSI invalid RSSI: Value size larger than integer"); + } + break; + + case ESP_BT_GAP_DEV_PROP_EIR: // Enum 4 - Extended Inquiry Response, value type is uint8_t [] + if (get_name_from_eir((uint8_t *)param->disc_res.prop[i].val, peer_bdname, &peer_bdname_len)) { + log_i("ESP_BT_GAP_DISC_RES_EVT : EIR : %s : %d", peer_bdname, peer_bdname_len); + if (strlen(_remote_name) == peer_bdname_len && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) { + log_v("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_EIR : %s", peer_bdname, peer_bdname_len); + _isRemoteAddressSet = true; + memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN); + esp_bt_gap_cancel_discovery(); + esp_spp_start_discovery(_peer_bd_addr); + } + } + break; + + default: log_i("ESP_BT_GAP_DISC_RES_EVT unknown property [%d]:type:%d", i, param->disc_res.prop[i].type); break; + } + if (_isRemoteAddressSet) { + break; + } + } + if (peer_bdname_len) { + advertisedDevice.setName(peer_bdname); + } + esp_bd_addr_t addr; + memcpy(addr, param->disc_res.bda, ESP_BD_ADDR_LEN); + advertisedDevice.setAddress(BTAddress(addr)); + if (scanResults.add(advertisedDevice) && advertisedDeviceCb) { + advertisedDeviceCb(&advertisedDevice); + } + } break; + + case ESP_BT_GAP_DISC_STATE_CHANGED_EVT: // Enum 1 - Discovery state changed event + if (param->disc_st_chg.state == ESP_BT_GAP_DISCOVERY_STOPPED) { + log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT stopped"); + xEventGroupClearBits(_bt_event_group, BT_DISCOVERY_RUNNING); + xEventGroupSetBits(_bt_event_group, BT_DISCOVERY_COMPLETED); + } else { // ESP_BT_GAP_DISCOVERY_STARTED + log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT started"); + xEventGroupClearBits(_bt_event_group, BT_DISCOVERY_COMPLETED); + xEventGroupSetBits(_bt_event_group, BT_DISCOVERY_RUNNING); + } + break; + + case ESP_BT_GAP_RMT_SRVCS_EVT: // Enum 2 - Get remote services event + log_i("ESP_BT_GAP_RMT_SRVCS_EVT: status = %d, num_uuids = %d", param->rmt_srvcs.stat, param->rmt_srvcs.num_uuids); + break; + + case ESP_BT_GAP_RMT_SRVC_REC_EVT: // Enum 3 - Get remote service record event + log_i("ESP_BT_GAP_RMT_SRVC_REC_EVT: status = %d", param->rmt_srvc_rec.stat); + break; + + case ESP_BT_GAP_AUTH_CMPL_EVT: // Enum 4 - Authentication complete event + if (param->auth_cmpl.stat == ESP_BT_STATUS_SUCCESS) { + log_v("authentication success: %s", param->auth_cmpl.device_name); + if (auth_complete_callback) { + auth_complete_callback(true); + } + } else { + log_e("authentication failed, status:%d", param->auth_cmpl.stat); + if (auth_complete_callback) { + auth_complete_callback(false); + } + } + break; + case ESP_BT_GAP_PIN_REQ_EVT: // Enum 5 - Legacy Pairing Pin code request + log_i("ESP_BT_GAP_PIN_REQ_EVT (min_16_digit=%d)", param->pin_req.min_16_digit); + if (param->pin_req.min_16_digit && _pin_code_len < 16) { + esp_bt_gap_pin_reply(param->pin_req.bda, false, 0, NULL); + } else { + //log_i("Input pin code: \"%s\"=0x%x", _pin_code); + log_i("Input pin code: \"%.*s\"=0x%x", _pin_code_len, _pin_code, *(int *)_pin_code); + esp_bt_gap_pin_reply(param->pin_req.bda, true, _pin_code_len, _pin_code); + } + break; + case ESP_BT_GAP_CFM_REQ_EVT: // Enum 6 - Security Simple Pairing User Confirmation request. + log_i("ESP_BT_GAP_CFM_REQ_EVT Please compare the numeric value: %d", param->cfm_req.num_val); + if (confirm_request_callback) { + memcpy(current_bd_addr, param->cfm_req.bda, sizeof(esp_bd_addr_t)); + confirm_request_callback(param->cfm_req.num_val); + } else { + log_w("ESP_BT_GAP_CFM_REQ_EVT: confirm_request_callback does not exist - refusing pairing"); + esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, false); + } + break; + + case ESP_BT_GAP_KEY_NOTIF_EVT: // Enum 7 - Security Simple Pairing Passkey Notification + log_i("ESP_BT_GAP_KEY_NOTIF_EVT passkey:%d", param->key_notif.passkey); + break; + case ESP_BT_GAP_KEY_REQ_EVT: // Enum 8 - Security Simple Pairing Passkey request + log_i("ESP_BT_GAP_KEY_REQ_EVT Please enter passkey!"); + if (key_request_callback) { + memcpy(current_bd_addr, param->cfm_req.bda, sizeof(esp_bd_addr_t)); + key_request_callback(); + } else { + log_w("ESP_BT_GAP_KEY_REQ_EVT: key_request_callback does not exist - refuseing pairing"); + esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, false); + } + break; + + case ESP_BT_GAP_READ_RSSI_DELTA_EVT: // Enum 9 - Read rssi event + log_i("ESP_BT_GAP_READ_RSSI_DELTA_EVT Read rssi event"); + break; + case ESP_BT_GAP_CONFIG_EIR_DATA_EVT: // Enum 10 - Config EIR data event + log_i("ESP_BT_GAP_CONFIG_EIR_DATA_EVT: stat:%d num:%d", param->config_eir_data.stat, param->config_eir_data.eir_type_num); + break; + + case ESP_BT_GAP_SET_AFH_CHANNELS_EVT: // Enum 11 - Set AFH channels event + log_i("ESP_BT_GAP_SET_AFH_CHANNELS_EVT Set AFH channels event"); + break; + + case ESP_BT_GAP_READ_REMOTE_NAME_EVT: // Enum 12 - Read Remote Name event + if (param->read_rmt_name.stat == ESP_BT_STATUS_SUCCESS) { + log_i("ESP_BT_GAP_READ_REMOTE_NAME_EVT: %s", param->read_rmt_name.rmt_name); + memcpy(_rmt_name, param->read_rmt_name.rmt_name, ESP_BT_GAP_MAX_BDNAME_LEN + 1); + _rmt_name_valid = true; + } else { + log_i("ESP_BT_GAP_READ_REMOTE_NAME_EVT: no success stat:%d", param->read_rmt_name.stat); + } + break; + + case ESP_BT_GAP_MODE_CHG_EVT: // Enum 13 + log_i("ESP_BT_GAP_MODE_CHG_EVT: mode: %d", param->mode_chg.mode); + break; + + case ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT: // Enum - 14 remove bond device complete event + log_i("ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT remove bond device complete event"); + break; + + case ESP_BT_GAP_QOS_CMPL_EVT: // Enum 15 - QOS complete event + log_i("ESP_BT_GAP_QOS_CMPL_EVT QOS complete event"); + break; + + case ESP_BT_GAP_ACL_CONN_CMPL_STAT_EVT: // Enum 16 - ACL connection complete status event + log_i("ESP_BT_GAP_ACL_CONN_CMPL_STAT_EVT ACL connection complete status event"); + break; + + case ESP_BT_GAP_ACL_DISCONN_CMPL_STAT_EVT: // Enum 17 - ACL disconnection complete status event + log_i( + "ESP_BT_GAP_ACL_DISCONN_CMPL_STAT_EVT ACL disconnection complete status event: reason %d, handle %d", param->acl_disconn_cmpl_stat.reason, + param->acl_disconn_cmpl_stat.handle + ); + break; + + default: log_i("ESP-BT_GAP_* unknown message: %d", event); break; + } +} + +static bool _init_bt(const char *deviceName, bt_mode mode) { + if (!_bt_event_group) { + _bt_event_group = xEventGroupCreate(); + if (!_bt_event_group) { + log_e("BT Event Group Create Failed!"); + return false; + } + xEventGroupClearBits(_bt_event_group, 0xFFFFFF); + } + if (!_spp_event_group) { + _spp_event_group = xEventGroupCreate(); + if (!_spp_event_group) { + log_e("SPP Event Group Create Failed!"); + return false; + } + xEventGroupClearBits(_spp_event_group, 0xFFFFFF); + xEventGroupSetBits(_spp_event_group, SPP_CONGESTED); + xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED); + xEventGroupSetBits(_spp_event_group, SPP_CLOSED); + } + if (_spp_rx_queue == NULL) { + _spp_rx_queue = xQueueCreate(RX_QUEUE_SIZE, sizeof(uint8_t)); //initialize the queue + if (_spp_rx_queue == NULL) { + log_e("RX Queue Create Failed"); + return false; + } + } + if (_spp_tx_queue == NULL) { + _spp_tx_queue = xQueueCreate(TX_QUEUE_SIZE, sizeof(spp_packet_t *)); //initialize the queue + if (_spp_tx_queue == NULL) { + log_e("TX Queue Create Failed"); + return false; + } + } + if (_spp_tx_done == NULL) { + _spp_tx_done = xSemaphoreCreateBinary(); + if (_spp_tx_done == NULL) { + log_e("TX Semaphore Create Failed"); + return false; + } + xSemaphoreTake(_spp_tx_done, 0); + } + + if (!_spp_task_handle) { + xTaskCreatePinnedToCore(_spp_tx_task, "spp_tx", 4096, NULL, configMAX_PRIORITIES - 1, &_spp_task_handle, 0); + if (!_spp_task_handle) { + log_e("Network Event Task Start Failed!"); + return false; + } + } + + if (!btStarted() && !btStartMode(mode)) { + log_e("initialize controller failed"); + return false; + } + + esp_bluedroid_status_t bt_state = esp_bluedroid_get_status(); + if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) { + if (esp_bluedroid_init()) { + log_e("initialize bluedroid failed"); + return false; + } + } + + if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) { + if (esp_bluedroid_enable()) { + log_e("enable bluedroid failed"); + return false; + } + } + + if (esp_bt_gap_register_callback(esp_bt_gap_cb) != ESP_OK) { + log_e("gap register failed"); + return false; + } + + if (esp_spp_register_callback(esp_spp_cb) != ESP_OK) { + log_e("spp register failed"); + return false; + } + + esp_spp_cfg_t cfg = BT_SPP_DEFAULT_CONFIG(); + cfg.mode = ESP_SPP_MODE_CB; + if (esp_spp_enhanced_init(&cfg) != ESP_OK) { + log_e("spp init failed"); + return false; + } + + log_i("device name set"); + esp_bt_gap_set_device_name(deviceName); + + if (_enableSSP) { + log_i("Simple Secure Pairing"); + esp_bt_sp_param_t param_type = ESP_BT_SP_IOCAP_MODE; + esp_bt_io_cap_t iocap; + if (_IO_CAP_INPUT && _IO_CAP_OUTPUT) { + iocap = ESP_BT_IO_CAP_IO; // Display with prompt + } else if (!_IO_CAP_INPUT && _IO_CAP_OUTPUT) { + iocap = ESP_BT_IO_CAP_OUT; // DisplayOnly + } else if (_IO_CAP_INPUT && !_IO_CAP_OUTPUT) { + iocap = ESP_BT_IO_CAP_IN; // Input only + } else if (!_IO_CAP_INPUT && !_IO_CAP_OUTPUT) { + iocap = ESP_BT_IO_CAP_NONE; // No input/output + } + esp_bt_gap_set_security_param(param_type, &iocap, sizeof(uint8_t)); + } + + // the default BTA_DM_COD_LOUDSPEAKER does not work with the macOS BT stack + esp_bt_cod_t cod; + cod.major = 0b00001; + cod.minor = 0b000100; + cod.service = 0b00000010110; + if (esp_bt_gap_set_cod(cod, ESP_BT_INIT_COD) != ESP_OK) { + log_e("set cod failed"); + return false; + } + return true; +} + +static bool _stop_bt() { + if (btStarted()) { + if (_spp_client) { + esp_spp_disconnect(_spp_client); + } + esp_spp_deinit(); + esp_bluedroid_disable(); + esp_bluedroid_deinit(); + btStop(); + } + _spp_client = 0; + if (_spp_task_handle) { + vTaskDelete(_spp_task_handle); + _spp_task_handle = NULL; + } + if (_spp_event_group) { + vEventGroupDelete(_spp_event_group); + _spp_event_group = NULL; + } + if (_spp_rx_queue) { + vQueueDelete(_spp_rx_queue); + //ToDo: clear RX queue when in packet mode + _spp_rx_queue = NULL; + } + if (_spp_tx_queue) { + spp_packet_t *packet = NULL; + while (xQueueReceive(_spp_tx_queue, &packet, 0) == pdTRUE) { + free(packet); + } + vQueueDelete(_spp_tx_queue); + _spp_tx_queue = NULL; + } + if (_spp_tx_done) { + vSemaphoreDelete(_spp_tx_done); + _spp_tx_done = NULL; + } + if (_bt_event_group) { + vEventGroupDelete(_bt_event_group); + _bt_event_group = NULL; + } + return true; +} + +static bool waitForConnect(int timeout) { + TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS; + // wait for connected or closed + EventBits_t rc = xEventGroupWaitBits(_spp_event_group, SPP_CONNECTED | SPP_CLOSED, pdFALSE, pdFALSE, xTicksToWait); + if ((rc & SPP_CONNECTED) != 0) { + return true; + } else if ((rc & SPP_CLOSED) != 0) { + log_d("connection closed!"); + return false; + } + log_d("timeout"); + return false; +} + +static bool waitForDiscovered(int timeout) { + TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS; + return (xEventGroupWaitBits(_spp_event_group, BT_DISCOVERY_COMPLETED, pdFALSE, pdTRUE, xTicksToWait) & BT_DISCOVERY_COMPLETED) != 0; +} + +static bool waitForSDPRecord(int timeout) { + TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS; + return (xEventGroupWaitBits(_bt_event_group, BT_SDP_COMPLETED, pdFALSE, pdTRUE, xTicksToWait) & BT_SDP_COMPLETED) != 0; +} + +/** + * Serial Bluetooth Arduino + * + */ +BluetoothSerial::BluetoothSerial() { + local_name = "ESP32"; //default bluetooth name +} + +BluetoothSerial::~BluetoothSerial(void) { + _stop_bt(); +} + +/** + * @param isMaster set to true if you want to connect to an other device + * @param disableBLE if BLE is not used, its ram can be freed to get +10kB free ram + */ +bool BluetoothSerial::begin(String localName, bool isMaster, bool disableBLE) { + _isMaster = isMaster; + if (localName.length()) { + local_name = localName; + } + return _init_bt(local_name.c_str(), disableBLE ? BT_MODE_CLASSIC_BT : BT_MODE_BTDM); +} + +int BluetoothSerial::available(void) { + if (_spp_rx_queue == NULL) { + return 0; + } + return uxQueueMessagesWaiting(_spp_rx_queue); +} + +int BluetoothSerial::peek(void) { + uint8_t c; + if (_spp_rx_queue && xQueuePeek(_spp_rx_queue, &c, this->timeoutTicks)) { + return c; + } + return -1; +} + +bool BluetoothSerial::hasClient(void) { + return _spp_client > 0; +} + +int BluetoothSerial::read() { + + uint8_t c = 0; + if (_spp_rx_queue && xQueueReceive(_spp_rx_queue, &c, this->timeoutTicks)) { + return c; + } + return -1; +} + +/** + * Set timeout for read / peek + */ +void BluetoothSerial::setTimeout(int timeoutMS) { + Stream::setTimeout(timeoutMS); + this->timeoutTicks = timeoutMS / portTICK_PERIOD_MS; +} + +size_t BluetoothSerial::write(uint8_t c) { + return write(&c, 1); +} + +size_t BluetoothSerial::write(const uint8_t *buffer, size_t size) { + if (!_spp_client) { + return 0; + } + return (_spp_queue_packet((uint8_t *)buffer, size) == ESP_OK) ? size : 0; +} + +void BluetoothSerial::flush() { + if (_spp_tx_queue != NULL) { + while (uxQueueMessagesWaiting(_spp_tx_queue) > 0) { + delay(2); + } + } +} + +void BluetoothSerial::end() { + _stop_bt(); +} + +/** + * free additional ~30kB ram, reset is required to enable BT again + */ +void BluetoothSerial::memrelease() { + esp_bt_mem_release(ESP_BT_MODE_BTDM); +} + +void BluetoothSerial::onConfirmRequest(ConfirmRequestCb cb) { + confirm_request_callback = cb; +} + +void BluetoothSerial::onKeyRequest(KeyRequestCb cb) { + key_request_callback = cb; +} + +void BluetoothSerial::respondPasskey(uint32_t passkey) { + esp_bt_gap_ssp_passkey_reply(current_bd_addr, true, passkey); +} + +void BluetoothSerial::onAuthComplete(AuthCompleteCb cb) { + auth_complete_callback = cb; +} + +void BluetoothSerial::confirmReply(boolean confirm) { + esp_bt_gap_ssp_confirm_reply(current_bd_addr, confirm); +} + +esp_err_t BluetoothSerial::register_callback(esp_spp_cb_t callback) { + custom_spp_callback = callback; + return ESP_OK; +} + +// Enable Simple Secure Pairing (using generated PIN) +// This must be called before calling begin, otherwise has no effect! +void BluetoothSerial::enableSSP() { + if (isReady(false, READY_TIMEOUT)) { + log_i("Attempted to enable SSP for already initialized driver. Restart to take effect with end() followed by begin()"); + return; + } + _enableSSP = true; + _IO_CAP_INPUT = true; + _IO_CAP_OUTPUT = true; +} + +// Enable Simple Secure Pairing (using generated PIN) +// This must be called before calling begin, otherwise has no effect! +// Behavior description: +// When both Input and Output are false only the other device authenticates pairing without any pin. +// When Output is true and Input is false only the other device authenticates pairing without any pin. +// When both Input and Output are true both devices display randomly generated code and if they match authenticate pairing on both devices +// - This must be implemented by registering callback via onConfirmRequest() and in this callback request user input and call confirmReply(true); if the authenticated +// otherwise call `confirmReply(false)` to reject the pairing. +// When Input is true and Output is false User will be required to input the passkey to the ESP32 device to authenticate. +// - This must be implemented by registering callback via onKeyRequest() and in this callback the entered passkey will be responded via respondPasskey(passkey); +void BluetoothSerial::enableSSP(bool inputCpability, bool outputCapability) { + log_i("Enabling SSP: input capability=%d; output capability=%d", inputCpability, outputCapability); + _enableSSP = true; + _IO_CAP_INPUT = inputCpability; + _IO_CAP_OUTPUT = outputCapability; +} + +// Disable Simple Secure Pairing (using generated PIN) +// This must be called before calling begin, otherwise has no effect! +void BluetoothSerial::disableSSP() { + _enableSSP = false; +} + +bool BluetoothSerial::setPin(const char *pin, uint8_t pin_code_len) { + if (pin_code_len == 0 || pin_code_len > 16) { + log_e("PIN code must be 1-16 Bytes long! Called with length %d", pin_code_len); + return false; + } + _pin_code_len = pin_code_len; + memcpy(_pin_code, pin, pin_code_len); + return (esp_bt_gap_set_pin(ESP_BT_PIN_TYPE_FIXED, _pin_code_len, _pin_code) == ESP_OK); +} + +bool BluetoothSerial::connect(String remoteName) { + bool retval = false; + + if (!isReady(true, READY_TIMEOUT)) { + return false; + } + if (remoteName && remoteName.length() < 1) { + log_e("No remote name is provided"); + return false; + } + disconnect(); + _doConnect = true; + _isRemoteAddressSet = true; + _sec_mask = ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE; + _role = ESP_SPP_ROLE_MASTER; + strncpy(_remote_name, remoteName.c_str(), ESP_BT_GAP_MAX_BDNAME_LEN); + _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN] = 0; + log_i("master : remoteName"); + // will first resolve name to address +#ifdef ESP_IDF_VERSION_MAJOR + esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); +#else + esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE); +#endif + xEventGroupClearBits(_spp_event_group, SPP_CLOSED); + if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) { + retval = waitForConnect(SCAN_TIMEOUT); + } + if (retval == false) { + _isRemoteAddressSet = false; + } + return retval; +} + +/** + * Connect to an other bluetooth device + * + * @param channel specify channel or 0 for auto-detect + * @param sec_mask + * ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE + * ESP_SPP_SEC_NONE + * @param role + * ESP_SPP_ROLE_MASTER master can handle up to 7 connections to slaves + * ESP_SPP_ROLE_SLAVE can only have one connection to a master + */ +bool BluetoothSerial::connect(uint8_t remoteAddress[], int channel, esp_spp_sec_t sec_mask, esp_spp_role_t role) { + bool retval = false; + if (!isReady(true, READY_TIMEOUT)) { + return false; + } + if (!remoteAddress) { + log_e("No remote address is provided"); + return false; + } + disconnect(); + _doConnect = true; + _remote_name[0] = 0; + _isRemoteAddressSet = true; + _sec_mask = sec_mask; + _role = role; + memcpy(_peer_bd_addr, remoteAddress, ESP_BD_ADDR_LEN); + log_i("master : remoteAddress"); + xEventGroupClearBits(_spp_event_group, SPP_CLOSED); + if (channel > 0) { +#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) + char bda_str[18]; + log_i("spp connect to remote %s channel %d", bda2str(_peer_bd_addr, bda_str, sizeof(bda_str)), channel); +#endif + if (esp_spp_connect(sec_mask, role, channel, _peer_bd_addr) != ESP_OK) { + log_e("spp connect failed"); + retval = false; + } else { + retval = waitForConnect(READY_TIMEOUT); + if (retval) { + log_i("connected"); + } else { + if (this->isClosed()) { + log_e("connect failed"); + } else { + log_e("connect timed out after %dms", READY_TIMEOUT); + } + } + } + } else if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) { + retval = waitForConnect(READY_TIMEOUT); + } + + if (!retval) { + _isRemoteAddressSet = false; + } + return retval; +} + +bool BluetoothSerial::connect() { + if (!isReady(true, READY_TIMEOUT)) { + return false; + } + _doConnect = true; + if (_isRemoteAddressSet) { + disconnect(); + // use resolved or set address first + log_i("master : remoteAddress"); + if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) { + return waitForConnect(READY_TIMEOUT); + } + return false; + } else if (_remote_name[0]) { + disconnect(); + log_i("master : remoteName"); + // will resolve name to address first - it may take a while +#ifdef ESP_IDF_VERSION_MAJOR + esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); +#else + esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE); +#endif + if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) { + return waitForConnect(SCAN_TIMEOUT); + } + return false; + } + log_e("Neither Remote name nor address was provided"); + return false; +} + +bool BluetoothSerial::disconnect() { + if (_spp_client) { + flush(); + log_i("disconnecting"); + if (esp_spp_disconnect(_spp_client) == ESP_OK) { + TickType_t xTicksToWait = READY_TIMEOUT / portTICK_PERIOD_MS; + return (xEventGroupWaitBits(_spp_event_group, SPP_DISCONNECTED, pdFALSE, pdTRUE, xTicksToWait) & SPP_DISCONNECTED) != 0; + } + } + return false; +} + +bool BluetoothSerial::unpairDevice(uint8_t remoteAddress[]) { + if (isReady(false, READY_TIMEOUT)) { + log_i("removing bonded device"); + return (esp_bt_gap_remove_bond_device(remoteAddress) == ESP_OK); + } + return false; +} + +bool BluetoothSerial::connected(int timeout) { + return waitForConnect(timeout); +} + +/** + * true if a connection terminated or a connection attempt failed + */ +bool BluetoothSerial::isClosed() { + return xEventGroupGetBits(_spp_event_group) & SPP_CLOSED; +} + +bool BluetoothSerial::isReady(bool checkMaster, int timeout) { + if (checkMaster && !_isMaster) { + log_e("Master mode is not active. Call begin(localName, true) to enable Master mode"); + return false; + } + if (!btStarted()) { + log_e("BT is not initialized. Call begin() first"); + return false; + } + TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS; + return (xEventGroupWaitBits(_spp_event_group, SPP_RUNNING, pdFALSE, pdTRUE, xTicksToWait) & SPP_RUNNING) != 0; +} + +/** + * @brief RemoteName or address are not allowed to be set during discovery + * (otherwise it might connect automatically and stop discovery) + * @param[in] timeoutMs can range from MIN_INQ_TIME to MAX_INQ_TIME + * @return in case of Error immediately Empty ScanResults. + */ +BTScanResults *BluetoothSerial::discover(int timeoutMs) { + scanResults.clear(); + if (timeoutMs < MIN_INQ_TIME || timeoutMs > MAX_INQ_TIME) { + log_e("Timeout out of bounds: MIN=%d; MAX=%d; requested=%d", MIN_INQ_TIME, MAX_INQ_TIME, timeoutMs); + return nullptr; + } + int timeout = timeoutMs / INQ_TIME; + log_i("discover::disconnect"); + disconnect(); + log_i("discovering"); + // will resolve name to address first - it may take a while + esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); + if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, timeout, 0) == ESP_OK) { + waitForDiscovered(timeoutMs); + log_i("gap_cancel_discovery()"); + esp_bt_gap_cancel_discovery(); + } + return &scanResults; +} + +/** + * @brief RemoteName or address are not allowed to be set during discovery + * (otherwise it might connect automatically and stop discovery) + * @param[in] cb called when a [b]new[/b] device has been discovered + * @param[in] timeoutMs can be 0 or range from MIN_INQ_TIME to MAX_INQ_TIME + * + * @return Whether start was successful or problems with params + */ +bool BluetoothSerial::discoverAsync(BTAdvertisedDeviceCb cb, int timeoutMs) { + scanResults.clear(); + if (strlen(_remote_name) || _isRemoteAddressSet) { + return false; + } + int timeout = timeoutMs / INQ_TIME; + disconnect(); + advertisedDeviceCb = cb; + log_i("discovering"); + // will resolve name to address first - it may take a while + esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE); + if (timeout > 0) { + return esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, timeout, 0) == ESP_OK; + } else { + return esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, ESP_BT_GAP_MAX_INQ_LEN, 0) == ESP_OK; + } +} + +/** @brief Stops the asynchronous discovery and clears the callback */ +void BluetoothSerial::discoverAsyncStop() { + esp_bt_gap_cancel_discovery(); + advertisedDeviceCb = nullptr; +} + +/** @brief Clears scanResult entries */ +void BluetoothSerial::discoverClear() { + scanResults.clear(); +} + +/** @brief Can be used while discovering asynchronously + * Will be returned also on synchronous discovery. + * + * @return BTScanResults contains several information of found devices + */ +BTScanResults *BluetoothSerial::getScanResults() { + return &scanResults; +} + +BluetoothSerial::operator bool() const { + return true; +} + +/** + * SDP scan address + * esp_spp_start_discovery doesn't tell us the btAddress in the callback, so we have to wait until it's finished + */ +std::map BluetoothSerial::getChannels(const BTAddress &remoteAddress) { + if (xEventGroupGetBits(_bt_event_group) & BT_SDP_RUNNING) { + log_e("getChannels failed - already running"); + } + xEventGroupSetBits(_bt_event_group, BT_SDP_RUNNING); + xEventGroupClearBits(_bt_event_group, BT_SDP_COMPLETED); + _doConnect = false; + sdpRecords.clear(); + log_d("esp_spp_start_discovery"); + if (esp_spp_start_discovery(*remoteAddress.getNative()) != ESP_OK) { + log_e("esp_spp_start_discovery failed"); + } else { + if (!waitForSDPRecord(READY_TIMEOUT)) { + log_e("getChannels failed timeout"); + } + log_d("esp_spp_start_discovery wait for BT_SDP_COMPLETED done (%dms)", READY_TIMEOUT); + } + log_d("esp_spp_start_discovery done, found %d services", sdpRecords.size()); + xEventGroupClearBits(_bt_event_group, BT_SDP_RUNNING); + return sdpRecords; +} + +/** + * @brief Gets the MAC address of local BT device in byte array. + * + * @param mac [out] The mac + */ +void BluetoothSerial::getBtAddress(uint8_t *mac) { + const uint8_t *dev_mac = esp_bt_dev_get_address(); + memcpy(mac, dev_mac, ESP_BD_ADDR_LEN); +} +/** + * @brief Gets the MAC address of local BT device as BTAddress object. + * + * @return The BTAddress object. + */ +BTAddress BluetoothSerial::getBtAddressObject() { + uint8_t mac_arr[ESP_BD_ADDR_LEN]; + getBtAddress(mac_arr); + return BTAddress(mac_arr); +} +/** + * @brief Gets the MAC address of local BT device as string. + * + * @return The BT MAC address string. + */ +String BluetoothSerial::getBtAddressString() { + return getBtAddressObject().toString(true); +} + +// Send a request to the remote device defined by the remoteAddress to send back its name. +// The name will be read by background task and stored. It can be later read with radRemoteName() +void BluetoothSerial::requestRemoteName(uint8_t remoteAddress[]) { + if (isReady(false, READY_TIMEOUT)) { + esp_bt_gap_read_remote_name(remoteAddress); + } +} + +// If remote name is valid (was already received) this function will copy the name to the aprameter rmt_name +// The buffer must have size at least ESP_BT_GAP_MAX_BDNAME_LEN + 1 +// If the name is valid the function will return true +// If the name is not valid (was not read yet) returns false +bool BluetoothSerial::readRemoteName(char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]) { + if (_rmt_name_valid) { + memcpy(rmt_name, _rmt_name, ESP_BT_GAP_MAX_BDNAME_LEN + 1); + return true; + } + return false; +} + +// Set validity of remote name before reading name from different device +void BluetoothSerial::invalidateRemoteName() { + _rmt_name_valid = false; +} + +int BluetoothSerial::getNumberOfBondedDevices() { + return esp_bt_gap_get_bond_device_num(); +} + +// Accepts the maximum number of devices that can fit in given array dev_list. +// Create you list this way: esp_bd_addr_t dev_list[dev_num]; +// Returns number of retrieved devices (on error returns 0) +int BluetoothSerial::getBondedDevices(uint dev_num, esp_bd_addr_t *dev_list) { + // typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN] + if (dev_list == NULL) { + log_e("Device list is NULL"); + return 0; + } + if (dev_num == 0) { + log_e("Device number must be larger than 0!"); + return 0; + } + int _dev_num = dev_num; + esp_bt_gap_get_bond_device_list(&_dev_num, dev_list); + return _dev_num; +} + +bool BluetoothSerial::deleteBondedDevice(uint8_t *remoteAddress) { + esp_err_t ret = esp_bt_gap_remove_bond_device(remoteAddress); + if (ret == ESP_OK) { + return true; + } else { + return false; + } +} + +void BluetoothSerial::deleteAllBondedDevices() { + if (!isReady(false, READY_TIMEOUT)) { + log_w("Attempted to drop cache for uninitialized driver. First call begin()"); + return; + } + + int expected_dev_num = esp_bt_gap_get_bond_device_num(); + if (expected_dev_num == 0) { + log_i("No devices in cache."); + return; + } else { + log_d("Found %d bonded devices", expected_dev_num); + } + esp_err_t ret; + + // typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN] // ESP_BD_ADDR_LEN = 6 + esp_bd_addr_t *dev_list = NULL; + log_d("Allocate buffer: sizeof(esp_bd_addr_t)=%d * expected_dev_num=%d", sizeof(esp_bd_addr_t), expected_dev_num); + dev_list = (esp_bd_addr_t *)malloc(sizeof(esp_bd_addr_t) * expected_dev_num); + if (dev_list == NULL) { + log_e("Could not allocated BT device buffer!"); + return; + } + //uint8_t dev_list [20][6]; + + int dev_num; + ret = esp_bt_gap_get_bond_device_list(&dev_num, dev_list); + log_d("esp_bt_gap_get_bond_device_list ret = %d", ret); + if (ret == ESP_OK) { + if (dev_num != expected_dev_num) { + log_w("Inconsistent number of bonded devices. Expected %d; returned %d", expected_dev_num, dev_num); + } + for (int i = 0; i < dev_num; ++i) { + ret = esp_bt_gap_remove_bond_device(dev_list[i]); + log_d("esp_bt_gap_remove_bond_device ret = %d", ret); + if (ret == ESP_OK) { + log_d("Removed bonded device #%d", i); + } else { + log_w("Failed to removed bonded device #%d", i); + } + //btc_storage_remove_bonded_device(dev_list[i]); + } + log_d("device num after delete = %d", esp_bt_gap_get_bond_device_num()); + } else { + log_w("Function esp_bt_gap_get_bond_device_list() returned code %d", ret); + } +} +#endif // defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) diff --git a/libraries/BluetoothSerial/src/BluetoothSerial.h b/libraries/BluetoothSerial/src/BluetoothSerial.h new file mode 100644 index 0000000..68ddd3c --- /dev/null +++ b/libraries/BluetoothSerial/src/BluetoothSerial.h @@ -0,0 +1,120 @@ +// Copyright 2018 Evandro Luis Copercini +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _BLUETOOTH_SERIAL_H_ +#define _BLUETOOTH_SERIAL_H_ + +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_BT_SUPPORTED && defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED) + +#include "Arduino.h" +#include "Stream.h" +#include +#include +#include +#include +#include "BTScan.h" +#include "BTAdvertisedDevice.h" + +typedef std::function BluetoothSerialDataCb; +typedef std::function ConfirmRequestCb; +typedef std::function KeyRequestCb; +typedef std::function AuthCompleteCb; +typedef std::function BTAdvertisedDeviceCb; + +class [[deprecated("BluetoothSerial won't be supported in version 4.0.0 by default")]] BluetoothSerial : public Stream { +public: + BluetoothSerial(void); + ~BluetoothSerial(void); + + bool begin(String localName = String(), bool isMaster = false, bool disableBLE = false); + bool begin(unsigned long baud) { //compatibility + return begin(); + } + int available(void); + int peek(void); + bool hasClient(void); + int read(void); + size_t write(uint8_t c); + size_t write(const uint8_t *buffer, size_t size); + void flush(); + void end(void); + void memrelease(); + void setTimeout(int timeoutMS); + void onData(BluetoothSerialDataCb cb); + esp_err_t register_callback(esp_spp_cb_t callback); + + void onConfirmRequest(ConfirmRequestCb cb); + void onKeyRequest(KeyRequestCb cb); + void respondPasskey(uint32_t passkey); + void onAuthComplete(AuthCompleteCb cb); + void confirmReply(boolean confirm); + + void enableSSP(); + void enableSSP(bool inputCapability, bool outputCapability); + void disableSSP(); + bool setPin(const char *pin, uint8_t pin_code_len); + bool connect(String remoteName); + bool connect( + uint8_t remoteAddress[], int channel = 0, esp_spp_sec_t sec_mask = (ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE), + esp_spp_role_t role = ESP_SPP_ROLE_MASTER + ); + bool connect( + const BTAddress &remoteAddress, int channel = 0, esp_spp_sec_t sec_mask = (ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE), + esp_spp_role_t role = ESP_SPP_ROLE_MASTER + ) { + return connect(*remoteAddress.getNative(), channel, sec_mask); + }; + bool connect(); + bool connected(int timeout = 0); + bool isClosed(); + bool isReady(bool checkMaster = false, int timeout = 0); + bool disconnect(); + bool unpairDevice(uint8_t remoteAddress[]); + + BTScanResults *discover(int timeout = 0x30 * 1280); + bool discoverAsync(BTAdvertisedDeviceCb cb, int timeout = 0x30 * 1280); + void discoverAsyncStop(); + void discoverClear(); + BTScanResults *getScanResults(); + + std::map getChannels(const BTAddress &remoteAddress); + + const int INQ_TIME = 1280; // Inquire Time unit 1280 ms + const int MIN_INQ_TIME = (ESP_BT_GAP_MIN_INQ_LEN * INQ_TIME); + const int MAX_INQ_TIME = (ESP_BT_GAP_MAX_INQ_LEN * INQ_TIME); + + operator bool() const; + void getBtAddress(uint8_t *mac); + BTAddress getBtAddressObject(); + String getBtAddressString(); + //void dropCache(); // To be replaced + void requestRemoteName(uint8_t *remoteAddress); + bool readRemoteName(char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]); + void invalidateRemoteName(); + int getNumberOfBondedDevices(); + int getBondedDevices(uint dev_num, esp_bd_addr_t *dev_list); + bool deleteBondedDevice(uint8_t *remoteAddress); + void deleteAllBondedDevices(); + +private: + String local_name; + int timeoutTicks = 0; +}; + +#endif + +#endif diff --git a/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino b/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino new file mode 100644 index 0000000..7759aa0 --- /dev/null +++ b/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino @@ -0,0 +1,65 @@ +/* +This example enables catch-all Captive portal for ESP32 Access-Point +It will allow modern devices/OSes to detect that WiFi connection is +limited and offer a user to access a banner web-page. +There is no need to find and open device's IP address/URL, i.e. http://192.168.4.1/ +This works for Android, Ubuntu, FireFox, Windows, maybe others... +*/ + +#include +#include +#include +#include + +DNSServer dnsServer; +WebServer server(80); + +static const char responsePortal[] = R"===( +ESP32 CaptivePortal +

Hello World!

This is a captive portal example page. All unknown http requests will +be redirected here.

+)==="; + +// index page handler +void handleRoot() { + server.send(200, "text/plain", "Hello from esp32!"); +} + +// this will redirect unknown http req's to our captive portal page +// based on this redirect various systems could detect that WiFi AP has a captive portal page +void handleNotFound() { + server.sendHeader("Location", "/portal"); + server.send(302, "text/plain", "redirect to captive portal"); +} + +void setup() { + Serial.begin(115200); + WiFi.AP.begin(); + WiFi.AP.create("ESP32-DNSServer"); + WiFi.AP.enableDhcpCaptivePortal(); + + // by default DNSServer is started serving any "*" domain name. It will reply + // AccessPoint's IP to all DNS request (this is required for Captive Portal detection) + if (dnsServer.start()) { + Serial.println("Started DNS server in captive portal-mode"); + } else { + Serial.println("Err: Can't start DNS server!"); + } + + // serve a simple root page + server.on("/", handleRoot); + + // serve portal page + server.on("/portal", []() { + server.send(200, "text/html", responsePortal); + }); + + // all unknown pages are redirected to captive portal + server.onNotFound(handleNotFound); + server.begin(); +} + +void loop() { + server.handleClient(); + delay(5); // give CPU some idle time +} diff --git a/libraries/DNSServer/examples/CaptivePortal/ci.yml b/libraries/DNSServer/examples/CaptivePortal/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/DNSServer/examples/CaptivePortal/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/DNSServer/library.properties b/libraries/DNSServer/library.properties new file mode 100644 index 0000000..17dee29 --- /dev/null +++ b/libraries/DNSServer/library.properties @@ -0,0 +1,9 @@ +name=DNSServer +version=3.3.7 +author=Kristijan Novoselić +maintainer=Kristijan Novoselić, +sentence=A simple DNS server for ESP32. +paragraph=This library implements a simple DNS server. +category=Communication +url= +architectures=esp32 diff --git a/libraries/DNSServer/src/DNSServer.cpp b/libraries/DNSServer/src/DNSServer.cpp new file mode 100644 index 0000000..795e735 --- /dev/null +++ b/libraries/DNSServer/src/DNSServer.cpp @@ -0,0 +1,267 @@ +#include "DNSServer.h" +#include +#include +#include + +// #define DEBUG_ESP_DNS +#ifdef DEBUG_ESP_PORT +#define DEBUG_OUTPUT DEBUG_ESP_PORT +#else +#define DEBUG_OUTPUT Serial +#endif + +#define DNS_MIN_REQ_LEN 17 // minimal size for DNS request asking ROOT = DNS_HEADER_SIZE + 1 null byte for Name + 4 bytes type/class + +DNSServer::DNSServer() : _port(DNS_DEFAULT_PORT), _ttl(htonl(DNS_DEFAULT_TTL)), _errorReplyCode(DNSReplyCode::NonExistentDomain) {} + +DNSServer::DNSServer(const String &domainName) + : _port(DNS_DEFAULT_PORT), _ttl(htonl(DNS_DEFAULT_TTL)), _errorReplyCode(DNSReplyCode::NonExistentDomain), _domainName(domainName){}; + +bool DNSServer::start() { + if (_resolvedIP.operator uint32_t() == 0) { // no address is set, try to obtain AP interface's IP +#if SOC_WIFI_SUPPORTED + if (WiFi.getMode() & WIFI_AP) { + _resolvedIP = WiFi.softAPIP(); + } else { + return false; // won't run if WiFi is not in AP mode, or no WiFi + } +#else + return false; // for other non WiFi-AP networking an overloaded method must be used to get device's IP + // start(uint16_t port, const String &domainName, const IPAddress &resolvedIP) +#endif + } + + _udp.close(); + _udp.onPacket([this](AsyncUDPPacket &pkt) { + this->_handleUDP(pkt); + }); + return _udp.listen(_port); +} + +bool DNSServer::start(uint16_t port, const String &domainName, const IPAddress &resolvedIP) { + _port = port; + if (domainName != "*") { + _domainName = domainName; + downcaseAndRemoveWwwPrefix(_domainName); + } else { + _domainName.clear(); + } + + _resolvedIP = resolvedIP; + _udp.close(); + _udp.onPacket([this](AsyncUDPPacket &pkt) { + this->_handleUDP(pkt); + }); + return _udp.listen(_port); +} + +void DNSServer::setErrorReplyCode(const DNSReplyCode &replyCode) { + _errorReplyCode = replyCode; +} + +void DNSServer::setTTL(const uint32_t &ttl) { + _ttl = htonl(ttl); +} + +void DNSServer::stop() { + _udp.close(); +} + +void DNSServer::downcaseAndRemoveWwwPrefix(String &domainName) { + domainName.toLowerCase(); + domainName.replace("www.", ""); +} + +void DNSServer::_handleUDP(AsyncUDPPacket &pkt) { + if (pkt.length() < DNS_MIN_REQ_LEN) { + return; // truncated packet or not a DNS req + } + + // get DNS header (beginning of message) + DNSHeader dnsHeader; + DNSQuestion dnsQuestion; + memcpy(&dnsHeader, pkt.data(), DNS_HEADER_SIZE); + if (dnsHeader.QR != DNS_QR_QUERY) { + return; // ignore non-query messages + } + + if (requestIncludesOnlyOneQuestion(dnsHeader)) { + /* + // The QName has a variable length, maximum 255 bytes and is comprised of multiple labels. + // Each label contains a byte to describe its length and the label itself. The list of + // labels terminates with a zero-valued byte. In "github.com", we have two labels "github" & "com" +*/ + const char *enoflbls = strchr(reinterpret_cast(pkt.data()) + DNS_HEADER_SIZE, 0); // find end_of_label marker + ++enoflbls; // advance after null terminator + dnsQuestion.QName = pkt.data() + DNS_HEADER_SIZE; // we can reference labels from the request + dnsQuestion.QNameLength = enoflbls - (char *)pkt.data() - DNS_HEADER_SIZE; + /* + check if we aint going out of pkt bounds + proper dns req should have label terminator at least 4 bytes before end of packet + */ + if (dnsQuestion.QNameLength > pkt.length() - DNS_HEADER_SIZE - sizeof(dnsQuestion.QType) - sizeof(dnsQuestion.QClass)) { + return; // malformed packet + } + + // Copy the QType and QClass + memcpy(&dnsQuestion.QType, enoflbls, sizeof(dnsQuestion.QType)); + memcpy(&dnsQuestion.QClass, enoflbls + sizeof(dnsQuestion.QType), sizeof(dnsQuestion.QClass)); + } + + // will reply with IP only to "*" or if domain matches without www. subdomain + if (dnsHeader.OPCode == DNS_OPCODE_QUERY && requestIncludesOnlyOneQuestion(dnsHeader) + && (_domainName.isEmpty() || getDomainNameWithoutWwwPrefix(static_cast(dnsQuestion.QName), dnsQuestion.QNameLength) == _domainName)) { + + // Qtype = A (1) or ANY (255): send an A record otherwise an empty response + if (ntohs(dnsQuestion.QType) == 1 || ntohs(dnsQuestion.QType) == 255) { + replyWithIP(pkt, dnsHeader, dnsQuestion); + } else { + replyWithNoAnsw(pkt, dnsHeader, dnsQuestion); + } + return; + } + // otherwise reply with custom code + replyWithCustomCode(pkt, dnsHeader); +} + +bool DNSServer::requestIncludesOnlyOneQuestion(DNSHeader &dnsHeader) { + dnsHeader.ARCount = 0; // We assume that if ARCount !=0 there is a EDNS OPT packet, just ignore + return ntohs(dnsHeader.QDCount) == 1 && dnsHeader.ANCount == 0 && dnsHeader.NSCount == 0; +} + +String DNSServer::getDomainNameWithoutWwwPrefix(const unsigned char *start, size_t len) { + String parsedDomainName(start, --len); // exclude trailing null byte from labels length, String constructor will add it anyway + + size_t pos = 0; + while (pos < len) { + parsedDomainName.setCharAt(pos, 0x2e); // replace label len byte with dot char "." + pos += *(start + pos); + ++pos; + } + parsedDomainName.remove(0, 1); // remove first "." char + downcaseAndRemoveWwwPrefix(parsedDomainName); + return parsedDomainName; +} + +void DNSServer::replyWithIP(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion) { + AsyncUDPMessage rpl; + // Change the type of message to a response and set the number of answers equal to + // the number of questions in the header + dnsHeader.QR = DNS_QR_RESPONSE; + dnsHeader.ANCount = dnsHeader.QDCount; + rpl.write((unsigned char *)&dnsHeader, DNS_HEADER_SIZE); + + // Write the question + rpl.write(dnsQuestion.QName, dnsQuestion.QNameLength); + rpl.write((uint8_t *)&dnsQuestion.QType, 2); + rpl.write((uint8_t *)&dnsQuestion.QClass, 2); + + // Write the answer + // Use DNS name compression : instead of repeating the name in this RNAME occurrence, + // set the two MSB of the byte corresponding normally to the length to 1. The following + // 14 bits must be used to specify the offset of the domain name in the message + // (<255 here so the first byte has the 6 LSB at 0) + rpl.write((uint8_t)0xC0); + rpl.write((uint8_t)DNS_OFFSET_DOMAIN_NAME); + + // DNS type A : host address, DNS class IN for INternet, returning an IPv4 address + uint16_t answerType = htons(DNS_TYPE_A), answerClass = htons(DNS_CLASS_IN), answerIPv4 = htons(DNS_RDLENGTH_IPV4); + rpl.write((unsigned char *)&answerType, 2); + rpl.write((unsigned char *)&answerClass, 2); + rpl.write((unsigned char *)&_ttl, 4); // DNS Time To Live + rpl.write((unsigned char *)&answerIPv4, 2); + uint32_t ip = _resolvedIP; + rpl.write(reinterpret_cast(&ip), sizeof(uint32_t)); // The IPv4 address to return + + _udp.sendTo(rpl, req.remoteIP(), req.remotePort()); + +#ifdef DEBUG_ESP_DNS + DEBUG_OUTPUT.printf( + "DNS responds: %s for %s\n", _resolvedIP.toString().c_str(), + getDomainNameWithoutWwwPrefix(static_cast(dnsQuestion.QName), dnsQuestion.QNameLength).c_str() + ); +#endif +} + +void DNSServer::replyWithCustomCode(AsyncUDPPacket &req, DNSHeader &dnsHeader) { + dnsHeader.QR = DNS_QR_RESPONSE; + dnsHeader.RCode = static_cast(_errorReplyCode); + dnsHeader.QDCount = 0; + + AsyncUDPMessage rpl(sizeof(DNSHeader)); + rpl.write(reinterpret_cast(&dnsHeader), sizeof(DNSHeader)); + _udp.sendTo(rpl, req.remoteIP(), req.remotePort()); +} + +void DNSServer::replyWithNoAnsw(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion) { + + dnsHeader.QR = DNS_QR_RESPONSE; + dnsHeader.ANCount = 0; + dnsHeader.NSCount = htons(1); + + AsyncUDPMessage rpl; + rpl.write(reinterpret_cast(&dnsHeader), sizeof(DNSHeader)); + + // Write the question + rpl.write(dnsQuestion.QName, dnsQuestion.QNameLength); + rpl.write((uint8_t *)&dnsQuestion.QType, 2); + rpl.write((uint8_t *)&dnsQuestion.QClass, 2); + + // An empty answer contains an authority section with a SOA, + // We take the name of the query as the root of the zone for which the SOA is generated + // and use a value of DNS_MINIMAL_TTL seconds in order to minimize negative caching + // Write the authority section: + // The SOA RR's ownername is set equal to the query name, and we use made up names for + // the MNAME and RNAME - it doesn't really matter from a protocol perspective - as for + // a no such QTYPE answer only the timing fields are used. + // a protocol perspective - it + // Use DNS name compression : instead of repeating the name in this RNAME occurrence, + // set the two MSB of the byte corresponding normally to the length to 1. The following + // 14 bits must be used to specify the offset of the domain name in the message + // (<255 here so the first byte has the 6 LSB at 0) + rpl.write((uint8_t)0xC0); + rpl.write((uint8_t)DNS_OFFSET_DOMAIN_NAME); + + // DNS type A : host address, DNS class IN for INternet, returning an IPv4 address + uint16_t answerType = htons(DNS_TYPE_SOA), answerClass = htons(DNS_CLASS_IN); + uint32_t Serial = htonl(DNS_SOA_SERIAL); // Date type serial based on the date this piece of code was written + uint32_t Refresh = htonl(DNS_SOA_REFRESH); // These timers don't matter, we don't serve zone transfers + uint32_t Retry = htonl(DNS_SOA_RETRY); + uint32_t Expire = htonl(DNS_SOA_EXPIRE); + uint32_t MinTTL = htonl(DNS_MINIMAL_TTL); // See RFC2308 section 5 + char MLabel[] = DNS_SOA_MNAME_LABEL; + char RLabel[] = DNS_SOA_RNAME_LABEL; + char PostFixLabel[] = DNS_SOA_POSTFIX_LABEL; + + // 4 accounts for len fields and for both rname + // and lname and their postfix labels and there are 5 32 bit fields + + uint16_t RdataLength = htons((uint16_t)(strlen(MLabel) + strlen(RLabel) + 2 * strlen(PostFixLabel) + 4 + 5 * sizeof(Serial))); + + rpl.write((unsigned char *)&answerType, 2); + rpl.write((unsigned char *)&answerClass, 2); + rpl.write((unsigned char *)&MinTTL, 4); // DNS Time To Live + + rpl.write((unsigned char *)&RdataLength, 2); + + rpl.write((uint8_t)strlen(MLabel)); + rpl.write((unsigned char *)&MLabel, strlen(MLabel)); + + rpl.write((unsigned char *)&PostFixLabel, strlen(PostFixLabel)); + rpl.write((uint8_t)0); + // rpl.write((uint8_t)0xC0); + // rpl.write((uint8_t)DNS_OFFSET_DOMAIN_NAME); + + rpl.write((uint8_t)strlen(RLabel)); + rpl.write((unsigned char *)&RLabel, strlen(RLabel)); + rpl.write((unsigned char *)&PostFixLabel, strlen(PostFixLabel)); + rpl.write((uint8_t)0); + + rpl.write((unsigned char *)&Serial, 4); + rpl.write((unsigned char *)&Refresh, 4); + rpl.write((unsigned char *)&Retry, 4); + rpl.write((unsigned char *)&Expire, 4); + rpl.write((unsigned char *)&MinTTL, 4); + + _udp.sendTo(rpl, req.remoteIP(), req.remotePort()); +} diff --git a/libraries/DNSServer/src/DNSServer.h b/libraries/DNSServer/src/DNSServer.h new file mode 100644 index 0000000..f2716de --- /dev/null +++ b/libraries/DNSServer/src/DNSServer.h @@ -0,0 +1,205 @@ +#pragma once +#include + +#define DNS_QR_QUERY 0 +#define DNS_QR_RESPONSE 1 +#define DNS_OPCODE_QUERY 0 +#define DNS_DEFAULT_TTL 60 // Default Time To Live : time interval in seconds that the resource record should be cached before being discarded +#define DNS_HEADER_SIZE 12 +#define DNS_OFFSET_DOMAIN_NAME DNS_HEADER_SIZE // Offset in bytes to reach the domain name labels in the DNS message +#define DNS_DEFAULT_PORT 53 + +#define DNS_SOA_MNAME_LABEL "ns" +#define DNS_SOA_RNAME_LABEL "esp32" +// The POSTFIX_LABEL will be concatenated to the RName and MName Label label +// do not use a multilabel name here. "local" is a good choice as it is reserved for +// local use by IANA +// The postfix label is defined as an array of characters that follows the +// definition of RFC1035 3.1 +// for instance, a postfix of example.com would be defined as: +// #define DNS_SOA_POSTFIX_LABEL {'\7', 'e', 'x', 'a', 'm', 'p', 'l', 'e', '\3', 'c', 'o', 'm', '\0'} +#define DNS_SOA_POSTFIX_LABEL \ + { '\5', 'l', 'o', 'c', 'a', 'l', '\0' } +// From the following values only the MINIMAL_TTL has relevance +// in the context of client-server protocol interactions. +// The other values are arbitrary chosen as they are only relevant for +// in a zone-transfer scenario. +#define DNS_SOA_SERIAL 2025052900 // Arbitrary serial (format: YYYYMMDDnn) +#define DNS_SOA_REFRESH 100000 // Arbitrary (seconds) +#define DNS_SOA_RETRY 10000 // Arbitrary (seconds) +#define DNS_SOA_EXPIRE 1000000 // Arbitrary (seconds) +#define DNS_MINIMAL_TTL 5 // Time to live for negative answers RFC2308 +enum class DNSReplyCode : uint16_t { + NoError = 0, + FormError = 1, + ServerFailure = 2, + NonExistentDomain = 3, + NotImplemented = 4, + Refused = 5, + YXDomain = 6, + YXRRSet = 7, + NXRRSet = 8 +}; + +enum DNSType { + DNS_TYPE_A = 1, // Host Address + DNS_TYPE_AAAA = 28, // IPv6 Address + DNS_TYPE_SOA = 6, // Start Of a zone of Authority + DNS_TYPE_PTR = 12, // Domain name PoinTeR + DNS_TYPE_DNAME = 39 // Delegation Name +}; + +enum DNSClass { + DNS_CLASS_IN = 1, // INternet + DNS_CLASS_CH = 3 // CHaos +}; + +enum DNSRDLength { + DNS_RDLENGTH_IPV4 = 4 // 4 bytes for an IPv4 address +}; + +struct DNSHeader { + uint16_t ID; // identification number + union { + struct { + uint16_t RD : 1; // recursion desired + uint16_t TC : 1; // truncated message + uint16_t AA : 1; // authoritative answer + uint16_t OPCode : 4; // message_type + uint16_t QR : 1; // query/response flag + uint16_t RCode : 4; // response code + uint16_t Z : 3; // its z! reserved + uint16_t RA : 1; // recursion available + }; + uint16_t Flags; + }; + uint16_t QDCount; // number of question entries + uint16_t ANCount; // number of ANswer entries + uint16_t NSCount; // number of authority entries + uint16_t ARCount; // number of Additional Resource entries +}; + +struct DNSQuestion { + const uint8_t *QName; + uint16_t QNameLength; + uint16_t QType; + uint16_t QClass; +}; + +class DNSServer { +public: + /** + * @brief Construct a new DNSServer object + * by default server is configured to run in "Captive-portal" mode + * it must be started with start() call to establish a listening socket + * + */ + DNSServer(); + + /** + * @brief Construct a new DNSServer object + * builds DNS server with default parameters + * @param domainName - domain name to serve + */ + DNSServer(const String &domainName); + ~DNSServer(){}; // default d-tor + + // Copy semantics not implemented (won't run on same UDP port anyway) + DNSServer(const DNSServer &) = delete; + DNSServer &operator=(const DNSServer &) = delete; + + /** + * @brief stub, left for compatibility with an old version + * does nothing actually + * + */ + void processNextRequest() {}; + + /** + * @brief Set the Error Reply Code for all req's not matching predefined domain + * + * @param replyCode + */ + void setErrorReplyCode(const DNSReplyCode &replyCode); + + /** + * @brief set TTL for successful replies + * + * @param ttl in seconds + */ + void setTTL(const uint32_t &ttl); + + /** + * @brief (re)Starts a server with current configuration or with default parameters + * if it's the first call. + * Defaults are: + * port: 53 + * domainName: any + * ip: WiFi AP's IP address + * + * @return true on success + * @return false if IP or socket error + */ + bool start(); + + /** + * @brief (re)Starts a server with provided configuration + * + * @return true on success + * @return false if IP or socket error + */ + bool start(uint16_t port, const String &domainName, const IPAddress &resolvedIP); + + /** + * @brief stops the server and close UDP socket + * + */ + void stop(); + + /** + * @brief returns true if DNS server runs in captive-portal mode + * i.e. all requests are served with AP's ip address + * + * @return true if catch-all mode active + * @return false otherwise + */ + inline bool isCaptive() const { + return _domainName.isEmpty(); + }; + + /** + * @brief returns 'true' if server is up and UDP socket is listening for UDP req's + * + * @return true if server is up + * @return false otherwise + */ + inline bool isUp() { + return _udp.connected(); + }; + +private: + AsyncUDP _udp; + uint16_t _port; + uint32_t _ttl; + DNSReplyCode _errorReplyCode; + String _domainName; + IPAddress _resolvedIP; + + void downcaseAndRemoveWwwPrefix(String &domainName); + + /** + * @brief Get the Domain Name Without Www Prefix object + * scan labels in DNS packet and build a string of a domain name + * truncate any www. label if found + * @param start a pointer to the start of labels records in DNS packet + * @param len labels length + * @return String + */ + String getDomainNameWithoutWwwPrefix(const unsigned char *start, size_t len); + inline bool requestIncludesOnlyOneQuestion(DNSHeader &dnsHeader); + void replyWithIP(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion); + inline void replyWithCustomCode(AsyncUDPPacket &req, DNSHeader &dnsHeader); + inline void replyWithNoAnsw(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion); + + void _handleUDP(AsyncUDPPacket &pkt); +}; diff --git a/libraries/EEPROM/README.md b/libraries/EEPROM/README.md new file mode 100644 index 0000000..577e2ea --- /dev/null +++ b/libraries/EEPROM/README.md @@ -0,0 +1,4 @@ +## EEPROM + +EEPROM is deprecated. For new applications on ESP32, use Preferences. EEPROM is provided for backwards compatibility with existing Arduino applications. +EEPROM is implemented using a single blob within NVS, so it is a container within a container. As such, it is not going to be a high performance storage method. Preferences will directly use nvs, and store each entry as a single object therein. diff --git a/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino b/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino new file mode 100644 index 0000000..386360a --- /dev/null +++ b/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino @@ -0,0 +1,86 @@ +/* + ESP32 eeprom_class example with EEPROM library + This simple example demonstrates using EEPROM library to store different data in + ESP32 Flash memory in a multiple user-defined EEPROM class objects. + + Created for arduino-esp32 on 25 Dec, 2017 + by Elochukwu Ifediora (fedy0) + converted to nvs by lbernstone - 06/22/2019 +*/ + +#include "EEPROM.h" + +// Instantiate eeprom objects with parameter/argument names and sizes +EEPROMClass NAMES("eeprom0"); +EEPROMClass HEIGHT("eeprom1"); +EEPROMClass AGE("eeprom2"); + +void setup() { + Serial.begin(115200); + delay(1000); + Serial.println("Testing EEPROMClass\n"); + if (!NAMES.begin(0x500)) { + Serial.println("Failed to initialize NAMES"); + Serial.println("Restarting..."); + delay(1000); + ESP.restart(); + } + if (!HEIGHT.begin(0x200)) { + Serial.println("Failed to initialize HEIGHT"); + Serial.println("Restarting..."); + delay(1000); + ESP.restart(); + } + if (!AGE.begin(0x100)) { + Serial.println("Failed to initialize AGE"); + Serial.println("Restarting..."); + delay(1000); + ESP.restart(); + } + + const char *name = "Teo Swee Ann"; + char rname[32]; + double height = 5.8; + uint32_t age = 47; + + // Write: Variables ---> EEPROM stores + NAMES.writeString(0, name); + HEIGHT.put(0, height); + AGE.put(0, age); + Serial.print("name: "); + Serial.println(name); + Serial.print("height: "); + Serial.println(height); + Serial.print("age: "); + Serial.println(age); + Serial.println("------------------------------------\n"); + + // Clear variables + rname[0] = '\0'; + height = 0; + age = 0; + Serial.print("name: "); + Serial.println(rname); + Serial.print("height: "); + Serial.println(height); + Serial.print("age: "); + Serial.println(age); + Serial.println("------------------------------------\n"); + + // Read: Variables <--- EEPROM stores + NAMES.get(0, rname); + HEIGHT.get(0, height); + AGE.get(0, age); + Serial.print("name: "); + Serial.println(rname); + Serial.print("height: "); + Serial.println(height); + Serial.print("age: "); + Serial.println(age); + + Serial.println("Done!"); +} + +void loop() { + delay(0xFFFFFFFF); +} diff --git a/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino b/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino new file mode 100644 index 0000000..78e8b26 --- /dev/null +++ b/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino @@ -0,0 +1,138 @@ +/* + ESP32 eeprom_extra example with EEPROM library + + This simple example demonstrates using other EEPROM library resources + + Created for arduino-esp32 on 25 Dec, 2017 + by Elochukwu Ifediora (fedy0) +*/ + +#include "EEPROM.h" + +void setup() { + // put your setup code here, to run once: + Serial.begin(115200); + Serial.println("\nTesting EEPROM Library\n"); + if (!EEPROM.begin(1000)) { + Serial.println("Failed to initialize EEPROM"); + Serial.println("Restarting..."); + delay(1000); + ESP.restart(); + } + + int address = 0; + + EEPROM.writeByte(address, -128); // -2^7 + address += sizeof(byte); + + EEPROM.writeChar(address, 'A'); // Same as writyByte and readByte + address += sizeof(char); + + EEPROM.writeUChar(address, 255); // 2^8 - 1 + address += sizeof(unsigned char); + + EEPROM.writeShort(address, -32768); // -2^15 + address += sizeof(short); + + EEPROM.writeUShort(address, 65535); // 2^16 - 1 + address += sizeof(unsigned short); + + EEPROM.writeInt(address, -2147483648); // -2^31 + address += sizeof(int); + + EEPROM.writeUInt(address, 4294967295); // 2^32 - 1 + address += sizeof(unsigned int); + + EEPROM.writeLong(address, -2147483648); // Same as writeInt and readInt + address += sizeof(long); + + EEPROM.writeULong(address, 4294967295); // Same as writeUInt and readUInt + address += sizeof(unsigned long); + + int64_t value = -1223372036854775808LL; // -2^63 + EEPROM.writeLong64(address, value); + address += sizeof(int64_t); + + uint64_t Value = 18446744073709551615ULL; // 2^64 - 1 + EEPROM.writeULong64(address, Value); + address += sizeof(uint64_t); + + EEPROM.writeFloat(address, 1234.1234); + address += sizeof(float); + + EEPROM.writeDouble(address, 123456789.123456789); + address += sizeof(double); + + EEPROM.writeBool(address, true); + address += sizeof(bool); + + String sentence = "I love ESP32."; + EEPROM.writeString(address, sentence); + address += sentence.length() + 1; + + char gratitude[21] = "Thank You Espressif!"; + EEPROM.writeString(address, gratitude); + address += 21; + + // See also the general purpose writeBytes() and readBytes() for BLOB in EEPROM library + EEPROM.commit(); + address = 0; + + Serial.println(EEPROM.readByte(address)); + address += sizeof(byte); + + Serial.println((char)EEPROM.readChar(address)); + address += sizeof(char); + + Serial.println(EEPROM.readUChar(address)); + address += sizeof(unsigned char); + + Serial.println(EEPROM.readShort(address)); + address += sizeof(short); + + Serial.println(EEPROM.readUShort(address)); + address += sizeof(unsigned short); + + Serial.println(EEPROM.readInt(address)); + address += sizeof(int); + + Serial.println(EEPROM.readUInt(address)); + address += sizeof(unsigned int); + + Serial.println(EEPROM.readLong(address)); + address += sizeof(long); + + Serial.println(EEPROM.readULong(address)); + address += sizeof(unsigned long); + + value = 0; + value = EEPROM.readLong64(value); + Serial.printf("0x%08lX", (uint32_t)(value >> 32)); // Print High 4 bytes in HEX + Serial.printf("%08lX\n", (uint32_t)value); // Print Low 4 bytes in HEX + address += sizeof(int64_t); + + Value = 0; // Clear Value + Value = EEPROM.readULong64(Value); + Serial.printf("0x%08lX", (uint32_t)(Value >> 32)); // Print High 4 bytes in HEX + Serial.printf("%08lX\n", (uint32_t)Value); // Print Low 4 bytes in HEX + address += sizeof(uint64_t); + + Serial.println(EEPROM.readFloat(address), 4); + address += sizeof(float); + + Serial.println(EEPROM.readDouble(address), 8); + address += sizeof(double); + + Serial.println(EEPROM.readBool(address)); + address += sizeof(bool); + + Serial.println(EEPROM.readString(address)); + address += sentence.length() + 1; + + Serial.println(EEPROM.readString(address)); + address += 21; +} + +void loop() { + // put your main code here, to run repeatedly: +} diff --git a/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino b/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino new file mode 100644 index 0000000..b931467 --- /dev/null +++ b/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino @@ -0,0 +1,62 @@ +/* + EEPROM Write + + Stores random values into the EEPROM. + These values will stay in the EEPROM when the board is + turned off and may be retrieved later by another sketch. +*/ + +#include "EEPROM.h" + +// the current address in the EEPROM (i.e. which byte +// we're going to write to next) +int addr = 0; +#define EEPROM_SIZE 64 +void setup() { + Serial.begin(115200); + Serial.println("start..."); + if (!EEPROM.begin(EEPROM_SIZE)) { + Serial.println("failed to initialize EEPROM"); + delay(1000000); + } + Serial.println(" bytes read from Flash . Values are:"); + for (int i = 0; i < EEPROM_SIZE; i++) { + Serial.print(byte(EEPROM.read(i))); + Serial.print(" "); + } + Serial.println(); + Serial.println("writing random n. in memory"); +} + +void loop() { + // need to divide by 4 because analog inputs range from + // 0 to 1023 and each byte of the EEPROM can only hold a + // value from 0 to 255. + // int val = analogRead(10) / 4; + int val = byte(random(10020)); + // write the value to the appropriate byte of the EEPROM. + // these values will remain there when the board is + // turned off. + EEPROM.write(addr, val); + Serial.print(val); + Serial.print(" "); + // advance to the next address. there are 512 bytes in + // the EEPROM, so go back to 0 when we hit 512. + // save all changes to the flash. + addr = addr + 1; + if (addr == EEPROM_SIZE) { + Serial.println(); + addr = 0; + EEPROM.commit(); + Serial.print(EEPROM_SIZE); + Serial.println(" bytes written on Flash . Values are:"); + for (int i = 0; i < EEPROM_SIZE; i++) { + Serial.print(byte(EEPROM.read(i))); + Serial.print(" "); + } + Serial.println(); + Serial.println("----------------------------------"); + } + + delay(100); +} diff --git a/libraries/EEPROM/keywords.txt b/libraries/EEPROM/keywords.txt new file mode 100644 index 0000000..d14b497 --- /dev/null +++ b/libraries/EEPROM/keywords.txt @@ -0,0 +1,18 @@ +####################################### +# Syntax Coloring Map For Ultrasound +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +EEPROM KEYWORD1 +EEPROMClass KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/EEPROM/library.properties b/libraries/EEPROM/library.properties new file mode 100644 index 0000000..65e6416 --- /dev/null +++ b/libraries/EEPROM/library.properties @@ -0,0 +1,9 @@ +name=EEPROM +version=3.3.7 +author=Ivan Grokhotkov +maintainer=Paolo Becchi +sentence=Enables reading and writing data a sequential, addressable FLASH storage +paragraph= +category=Data Storage +url=http://arduino.cc/en/Reference/EEPROM +architectures=esp32 diff --git a/libraries/EEPROM/src/EEPROM.cpp b/libraries/EEPROM/src/EEPROM.cpp new file mode 100644 index 0000000..05b9d3a --- /dev/null +++ b/libraries/EEPROM/src/EEPROM.cpp @@ -0,0 +1,526 @@ +/* + EEPROM.h -ported by Paolo Becchi to Esp32 from esp8266 EEPROM + -Modified by Elochukwu Ifediora + -Converted to nvs lbernstone@gmail.com + + Uses a nvs byte array to emulate EEPROM + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "EEPROM.h" +#include +#include +#include +#include + +EEPROMClass::EEPROMClass(void) : _handle(0), _data(0), _size(0), _dirty(false), _name("eeprom") {} + +EEPROMClass::EEPROMClass(uint32_t sector) + // Only for compatiility, no sectors in nvs! + : _handle(0), _data(0), _size(0), _dirty(false), _name("eeprom") {} + +EEPROMClass::EEPROMClass(const char *name) : _handle(0), _data(0), _size(0), _dirty(false), _name(name) {} + +EEPROMClass::~EEPROMClass() { + end(); +} + +bool EEPROMClass::begin(size_t size) { + if (!size) { + return false; + } + + esp_err_t res = nvs_open(_name, NVS_READWRITE, &_handle); + if (res != ESP_OK) { + log_e("Unable to open NVS namespace: %d", res); + return false; + } + + size_t key_size = 0; + res = nvs_get_blob(_handle, _name, NULL, &key_size); + if (res != ESP_OK && res != ESP_ERR_NVS_NOT_FOUND) { + log_e("Unable to read NVS key: %d", res); + return false; + } + if (size < key_size) { // truncate + log_w("truncating EEPROM from %d to %d", key_size, size); + uint8_t *key_data = new (std::nothrow) uint8_t[key_size]; + if (!key_data) { + log_e("Not enough memory to truncate EEPROM!"); + return false; + } + nvs_get_blob(_handle, _name, key_data, &key_size); + nvs_set_blob(_handle, _name, key_data, size); + nvs_commit(_handle); + delete[] key_data; + } else if (size > key_size) { // expand or new + size_t expand_size = size - key_size; + uint8_t *expand_key = new (std::nothrow) uint8_t[expand_size]; + if (!expand_key) { + log_e("Not enough memory to expand EEPROM!"); + return false; + } + // check for adequate free space + if (nvs_set_blob(_handle, "expand", expand_key, expand_size)) { + log_e("Not enough space to expand EEPROM from %d to %d", key_size, size); + delete[] expand_key; + return false; + } + delete[] expand_key; + nvs_erase_key(_handle, "expand"); + uint8_t *key_data = new (std::nothrow) uint8_t[size]; + if (!key_data) { + log_e("Not enough memory to expand EEPROM!"); + return false; + } + memset(key_data, 0xFF, size); + if (key_size) { + log_i("Expanding EEPROM from %d to %d", key_size, size); + // hold data while key is deleted + nvs_get_blob(_handle, _name, key_data, &key_size); + nvs_erase_key(_handle, _name); + } else { + log_i("New EEPROM of %d bytes", size); + } + nvs_commit(_handle); + nvs_set_blob(_handle, _name, key_data, size); + delete[] key_data; + nvs_commit(_handle); + } + + if (_data) { + delete[] _data; + } + + _data = new (std::nothrow) uint8_t[size]; + if (!_data) { + log_e("Not enough memory for %d bytes in EEPROM", size); + return false; + } + _size = size; + nvs_get_blob(_handle, _name, _data, &_size); + return true; +} + +void EEPROMClass::end() { + if (!_size) { + return; + } + + commit(); + if (_data) { + delete[] _data; + } + _data = 0; + _size = 0; + + nvs_close(_handle); + _handle = 0; +} + +bool EEPROMClass::isDirty() { + return _dirty; +} + +uint8_t EEPROMClass::read(int address) { + if (address < 0 || (size_t)address >= _size) { + return 0; + } + if (!_data) { + return 0; + } + + return _data[address]; +} + +void EEPROMClass::write(int address, uint8_t value) { + if (address < 0 || (size_t)address >= _size) { + return; + } + if (!_data) { + return; + } + + // Optimize _dirty. Only flagged if data written is different. + uint8_t *pData = &_data[address]; + if (*pData != value) { + *pData = value; + _dirty = true; + } +} + +bool EEPROMClass::commit() { + bool ret = false; + if (!_size) { + return false; + } + if (!_data) { + return false; + } + if (!_dirty) { + return true; + } + + esp_err_t err = nvs_set_blob(_handle, _name, _data, _size); + if (err != ESP_OK) { + log_e("error in write: %s", esp_err_to_name(err)); + } else { + _dirty = false; + ret = true; + } + + return ret; +} + +uint8_t *EEPROMClass::getDataPtr() { + _dirty = true; + return &_data[0]; +} + +/* + Get EEPROM total size in byte defined by the user +*/ +uint16_t EEPROMClass::length() { + return _size; +} + +/* + Convert EEPROM partition into nvs blob + Call convert before you call begin +*/ +uint16_t EEPROMClass::convert(bool clear, const char *EEPROMname, const char *nvsname) { + uint16_t result = 0; + const esp_partition_t *mypart = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, EEPROMname); + if (mypart == NULL) { + log_i("EEPROM partition not found for conversion"); + return result; + } + + size_t size = mypart->size; + uint8_t *data = new (std::nothrow) uint8_t[size]; + if (!data) { + log_e("Not enough memory to convert EEPROM!"); + goto exit; + } + + if (esp_partition_read(mypart, 0, (void *)data, size) != ESP_OK) { + log_e("Unable to read EEPROM partition"); + goto exit; + } + + bool empty; + empty = true; + for (int x = 0; x < size; x++) { + if (data[x] != 0xFF) { + empty = false; + break; + } + } + if (empty) { + log_i("EEPROM partition is empty, will not convert"); + goto exit; + } + + nvs_handle handle; + if (nvs_open(nvsname, NVS_READWRITE, &handle) != ESP_OK) { + log_e("Unable to open NVS"); + goto exit; + } + esp_err_t err; + err = nvs_set_blob(handle, nvsname, data, size); + if (err != ESP_OK) { + log_e("Unable to add EEPROM data to NVS: %s", esp_err_to_name(err)); + goto exit; + } + result = size; + + if (clear) { + if (esp_partition_erase_range(mypart, 0, size) != ESP_OK) { + log_w("Unable to clear EEPROM partition"); + } + } +exit: + delete[] data; + return result; +} + +/* + Read 'value' from 'address' +*/ +uint8_t EEPROMClass::readByte(int address) { + uint8_t value = 0; + return EEPROMClass::readAll(address, value); +} + +int8_t EEPROMClass::readChar(int address) { + int8_t value = 0; + return EEPROMClass::readAll(address, value); +} + +uint8_t EEPROMClass::readUChar(int address) { + uint8_t value = 0; + return EEPROMClass::readAll(address, value); +} + +int16_t EEPROMClass::readShort(int address) { + int16_t value = 0; + return EEPROMClass::readAll(address, value); +} + +uint16_t EEPROMClass::readUShort(int address) { + uint16_t value = 0; + return EEPROMClass::readAll(address, value); +} + +int32_t EEPROMClass::readInt(int address) { + int32_t value = 0; + return EEPROMClass::readAll(address, value); +} + +uint32_t EEPROMClass::readUInt(int address) { + uint32_t value = 0; + return EEPROMClass::readAll(address, value); +} + +int32_t EEPROMClass::readLong(int address) { + int32_t value = 0; + return EEPROMClass::readAll(address, value); +} + +uint32_t EEPROMClass::readULong(int address) { + uint32_t value = 0; + return EEPROMClass::readAll(address, value); +} + +int64_t EEPROMClass::readLong64(int address) { + int64_t value = 0; + return EEPROMClass::readAll(address, value); +} + +uint64_t EEPROMClass::readULong64(int address) { + uint64_t value = 0; + return EEPROMClass::readAll(address, value); +} + +float_t EEPROMClass::readFloat(int address) { + float_t value = 0; + return EEPROMClass::readAll(address, value); +} + +double_t EEPROMClass::readDouble(int address) { + double_t value = 0; + return EEPROMClass::readAll(address, value); +} + +bool EEPROMClass::readBool(int address) { + int8_t value = 0; + return EEPROMClass::readAll(address, value) ? 1 : 0; +} + +size_t EEPROMClass::readString(int address, char *value, size_t maxLen) { + if (!value) { + return 0; + } + + if (address < 0 || address + maxLen > _size) { + return 0; + } + + uint16_t len; + for (len = 0; len <= _size; len++) { + if (_data[address + len] == 0) { + break; + } + } + + if (address + len > _size) { + return 0; + } + + if (len > maxLen) { + return 0; //Maybe return part of the string instead? + } + + memcpy((uint8_t *)value, _data + address, len); + value[len] = 0; + return len; +} + +String EEPROMClass::readString(int address) { + if (address < 0 || address > _size) { + return String(); + } + + uint16_t len; + for (len = 0; len <= _size; len++) { + if (_data[address + len] == 0) { + break; + } + } + + if (address + len > _size) { + return String(); + } + + char value[len + 1]; + memcpy((uint8_t *)value, _data + address, len); + value[len] = 0; + return String(value); +} + +size_t EEPROMClass::readBytes(int address, void *value, size_t maxLen) { + if (!value || !maxLen) { + return 0; + } + + if (address < 0 || address + maxLen > _size) { + return 0; + } + + memcpy((void *)value, _data + address, maxLen); + return maxLen; +} + +template T EEPROMClass::readAll(int address, T &value) { + if (address < 0 || address + sizeof(T) > _size) { + return value; + } + + memcpy((uint8_t *)&value, _data + address, sizeof(T)); + return value; +} + +/* + Write 'value' to 'address' +*/ +size_t EEPROMClass::writeByte(int address, uint8_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeChar(int address, int8_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeUChar(int address, uint8_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeShort(int address, int16_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeUShort(int address, uint16_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeInt(int address, int32_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeUInt(int address, uint32_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeLong(int address, int32_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeULong(int address, uint32_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeLong64(int address, int64_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeULong64(int address, uint64_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeFloat(int address, float_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeDouble(int address, double_t value) { + return EEPROMClass::writeAll(address, value); +} + +size_t EEPROMClass::writeBool(int address, bool value) { + int8_t Bool; + value ? Bool = 1 : Bool = 0; + return EEPROMClass::writeAll(address, Bool); +} + +size_t EEPROMClass::writeString(int address, const char *value) { + if (!value) { + return 0; + } + + if (address < 0 || address > _size) { + return 0; + } + + uint16_t len; + for (len = 0; len <= _size; len++) { + if (value[len] == 0) { + break; + } + } + + if (address + len > _size) { + return 0; + } + + memcpy(_data + address, (const uint8_t *)value, len + 1); + _dirty = true; + return strlen(value); +} + +size_t EEPROMClass::writeString(int address, String value) { + return EEPROMClass::writeString(address, value.c_str()); +} + +size_t EEPROMClass::writeBytes(int address, const void *value, size_t len) { + if (!value || !len) { + return 0; + } + + if (address < 0 || address + len > _size) { + return 0; + } + + memcpy(_data + address, (const void *)value, len); + _dirty = true; + return len; +} + +template size_t EEPROMClass::writeAll(int address, const T &value) { + if (address < 0 || address + sizeof(T) > _size) { + return 0; + } + + memcpy(_data + address, (const uint8_t *)&value, sizeof(T)); + _dirty = true; + + return sizeof(value); +} + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_EEPROM) +EEPROMClass EEPROM; +#endif diff --git a/libraries/EEPROM/src/EEPROM.h b/libraries/EEPROM/src/EEPROM.h new file mode 100644 index 0000000..45222b0 --- /dev/null +++ b/libraries/EEPROM/src/EEPROM.h @@ -0,0 +1,122 @@ +/* + EEPROM.h -ported by Paolo Becchi to Esp32 from esp8266 EEPROM + -Modified by Elochukwu Ifediora + -Converted to nvs lbernstone@gmail.com + + Uses a nvs byte array to emulate EEPROM + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef EEPROM_h +#define EEPROM_h +#ifndef EEPROM_FLASH_PARTITION_NAME +#define EEPROM_FLASH_PARTITION_NAME "eeprom" +#endif +#include + +typedef uint32_t nvs_handle; + +class EEPROMClass { +public: + EEPROMClass(uint32_t sector); + EEPROMClass(const char *name); + EEPROMClass(void); + ~EEPROMClass(void); + + bool begin(size_t size); + uint8_t read(int address); + void write(int address, uint8_t val); + uint16_t length(); + bool commit(); + void end(); + bool isDirty(); + + uint8_t *getDataPtr(); + uint16_t convert(bool clear, const char *EEPROMname = "eeprom", const char *nvsname = "eeprom"); + + template T &get(int address, T &t) { + if (address < 0 || address + sizeof(T) > _size) { + return t; + } + + memcpy((uint8_t *)&t, _data + address, sizeof(T)); + return t; + } + + template const T &put(int address, const T &t) { + if (address < 0 || address + sizeof(T) > _size) { + return t; + } + + memcpy(_data + address, (const uint8_t *)&t, sizeof(T)); + _dirty = true; + return t; + } + + uint8_t readByte(int address); + int8_t readChar(int address); + uint8_t readUChar(int address); + int16_t readShort(int address); + uint16_t readUShort(int address); + int32_t readInt(int address); + uint32_t readUInt(int address); + int32_t readLong(int address); + uint32_t readULong(int address); + int64_t readLong64(int address); + uint64_t readULong64(int address); + float_t readFloat(int address); + double_t readDouble(int address); + bool readBool(int address); + size_t readString(int address, char *value, size_t maxLen); + String readString(int address); + size_t readBytes(int address, void *value, size_t maxLen); + template T readAll(int address, T &); + + size_t writeByte(int address, uint8_t value); + size_t writeChar(int address, int8_t value); + size_t writeUChar(int address, uint8_t value); + size_t writeShort(int address, int16_t value); + size_t writeUShort(int address, uint16_t value); + size_t writeInt(int address, int32_t value); + size_t writeUInt(int address, uint32_t value); + size_t writeLong(int address, int32_t value); + size_t writeULong(int address, uint32_t value); + size_t writeLong64(int address, int64_t value); + size_t writeULong64(int address, uint64_t value); + size_t writeFloat(int address, float_t value); + size_t writeDouble(int address, double_t value); + size_t writeBool(int address, bool value); + size_t writeString(int address, const char *value); + size_t writeString(int address, String value); + size_t writeBytes(int address, const void *value, size_t len); + template size_t writeAll(int address, const T &); + +protected: + nvs_handle _handle; + uint8_t *_data; + size_t _size; + bool _dirty; + const char *_name; +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_EEPROM) +extern EEPROMClass EEPROM; +#endif + +#endif diff --git a/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino b/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino new file mode 100644 index 0000000..ea190e4 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino @@ -0,0 +1,66 @@ +/* LEDC Fade Arduino Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ + +// use 12 bit precision for LEDC timer +#define LEDC_TIMER_12_BIT 12 + +// use 5000 Hz as a LEDC base frequency +#define LEDC_BASE_FREQ 5000 + +// fade LED PIN (replace with LED_BUILTIN constant for built-in LED) +#define LED_PIN 4 + +// define starting duty, target duty and maximum fade time +#define LEDC_START_DUTY (0) +#define LEDC_TARGET_DUTY (4095) +#define LEDC_FADE_TIME (3000) + +bool fade_ended = false; // status of LED fade +bool fade_in = true; + +void ARDUINO_ISR_ATTR LED_FADE_ISR() { + fade_ended = true; +} + +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + // Setup timer with given frequency, resolution and attach it to a led pin with auto-selected channel + ledcAttach(LED_PIN, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT); + + // Setup and start fade on led (duty from 0 to 4095) + ledcFade(LED_PIN, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME); + Serial.println("LED Fade on started."); + + // Wait for fade to end + delay(LEDC_FADE_TIME); + + // Setup and start fade off led and use ISR (duty from 4095 to 0) + ledcFadeWithInterrupt(LED_PIN, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Fade off started."); +} + +void loop() { + // Check if fade_ended flag was set to true in ISR + if (fade_ended) { + Serial.println("LED fade ended"); + fade_ended = false; + + // Check what fade should be started next + if (fade_in) { + ledcFadeWithInterrupt(LED_PIN, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Fade in started."); + fade_in = false; + } else { + ledcFadeWithInterrupt(LED_PIN, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Fade out started."); + fade_in = true; + } + } +} diff --git a/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/LEDCGammaFade.ino b/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/LEDCGammaFade.ino new file mode 100644 index 0000000..4ca6c13 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/LEDCGammaFade.ino @@ -0,0 +1,111 @@ +/* LEDC Gamma Curve Fade Arduino Example + + This example demonstrates gamma curve fading on ESP32 variants that support it. + Gamma correction makes LED brightness changes appear more gradual and natural + to human eyes compared to linear fading. + + Two methods are supported: + 1. Using a pre-computed Gamma Look-Up Table (LUT) for better performance + 2. Using mathematical gamma correction with a gamma factor + + Supported chips: ESP32-C6, ESP32-C5, ESP32-H2, ESP32-P4 and future chips with Gamma Fade support + + Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) +*/ + +// use 12 bit precision for LEDC timer +#define LEDC_TIMER_12_BIT 12 + +// use 5000 Hz as a LEDC base frequency +#define LEDC_BASE_FREQ 5000 + +// define starting duty, target duty and maximum fade time +#define LEDC_START_DUTY (0) +#define LEDC_TARGET_DUTY (4095) +#define LEDC_FADE_TIME (2000) + +// gamma factor for mathematical calculation +#define LEDC_GAMMA_FACTOR (2.6) + +// use gamma LUT for better performance instead of mathematical calculation (gamma factor) +#define USE_GAMMA_LUT 1 + +// fade LED pins +const uint8_t ledPinR = 4; +const uint8_t ledPinG = 5; +const uint8_t ledPinB = 6; + +uint8_t fade_ended = 0; // status of LED gamma fade +bool fade_in = true; + +#ifdef USE_GAMMA_LUT +// Custom Gamma LUT demonstration with 101 steps (Brightness 0 - 100% gamma correction look up table (gamma = 2.6)) +// Y = B ^ 2.6 - Pre-computed LUT to save runtime computation +static const float ledcGammaLUT[101] = { + 0.000000, 0.000006, 0.000038, 0.000110, 0.000232, 0.000414, 0.000666, 0.000994, 0.001406, 0.001910, 0.002512, 0.003218, 0.004035, 0.004969, 0.006025, + 0.007208, 0.008525, 0.009981, 0.011580, 0.013328, 0.015229, 0.017289, 0.019512, 0.021902, 0.024465, 0.027205, 0.030125, 0.033231, 0.036527, 0.040016, + 0.043703, 0.047593, 0.051688, 0.055993, 0.060513, 0.065249, 0.070208, 0.075392, 0.080805, 0.086451, 0.092333, 0.098455, 0.104821, 0.111434, 0.118298, + 0.125416, 0.132792, 0.140428, 0.148329, 0.156498, 0.164938, 0.173653, 0.182645, 0.191919, 0.201476, 0.211321, 0.221457, 0.231886, 0.242612, 0.253639, + 0.264968, 0.276603, 0.288548, 0.300805, 0.313378, 0.326268, 0.339480, 0.353016, 0.366879, 0.381073, 0.395599, 0.410461, 0.425662, 0.441204, 0.457091, + 0.473325, 0.489909, 0.506846, 0.524138, 0.541789, 0.559801, 0.578177, 0.596920, 0.616032, 0.635515, 0.655374, 0.675610, 0.696226, 0.717224, 0.738608, + 0.760380, 0.782542, 0.805097, 0.828048, 0.851398, 0.875148, 0.899301, 0.923861, 0.948829, 0.974208, 1.000000, +}; +#endif + +void ARDUINO_ISR_ATTR LED_FADE_ISR() { + fade_ended += 1; +} + +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + // Setup timer with given frequency, resolution and attach it to a led pin with auto-selected channel + ledcAttach(ledPinR, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT); + ledcAttach(ledPinG, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT); + ledcAttach(ledPinB, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT); + +#if USE_GAMMA_LUT // Use default gamma LUT for better performance + ledcSetGammaTable(ledcGammaLUT, 101); +#else // Use mathematical gamma correction (default, more flexible) + ledcSetGammaFactor(LEDC_GAMMA_FACTOR); // This is optional to set custom gamma factor (default is 2.8) +#endif + + // Setup and start gamma curve fade on led (duty from 0 to 4095) + ledcFadeGamma(ledPinR, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME); + ledcFadeGamma(ledPinG, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME); + ledcFadeGamma(ledPinB, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME); + Serial.println("LED Gamma Fade on started."); + + // Wait for fade to end + delay(LEDC_FADE_TIME); + + // Setup and start gamma curve fade off led and use ISR (duty from 4095 to 0) + ledcFadeGammaWithInterrupt(ledPinR, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinG, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinB, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Gamma Fade off started."); +} + +void loop() { + // Check if fade_ended flag was set to true in ISR + if (fade_ended == 3) { + Serial.println("LED gamma fade ended"); + fade_ended = 0; + + // Check what gamma fade should be started next + if (fade_in) { + ledcFadeGammaWithInterrupt(ledPinR, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinG, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinB, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Gamma Fade in started."); + fade_in = false; + } else { + ledcFadeGammaWithInterrupt(ledPinR, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinG, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + ledcFadeGammaWithInterrupt(ledPinB, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR); + Serial.println("LED Gamma Fade out started."); + fade_in = true; + } + } +} diff --git a/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/ci.yml b/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/ci.yml new file mode 100644 index 0000000..b001ab0 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/LEDCGammaFade/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED=y diff --git a/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino b/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino new file mode 100644 index 0000000..2317e32 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino @@ -0,0 +1,50 @@ +/* + LEDC Software Fade on shared channel with multiple pins + + This example shows how to software fade LED + using the ledcWriteChannel function on multiple pins. + This example is useful if you need to control synchronously + multiple LEDs on different pins. + + Code adapted from original Arduino Fade example: + https://www.arduino.cc/en/Tutorial/Fade + + This example code is in the public domain. + */ + +// use 8 bit precision for LEDC timer +#define LEDC_TIMER_8_BIT 8 + +// use 5000 Hz as a LEDC base frequency +#define LEDC_BASE_FREQ 5000 + +// LED pins +#define LED_PIN_1 4 +#define LED_PIN_2 5 + +// LED channel that will be used instead of automatic selection. +#define LEDC_CHANNEL 0 + +int brightness = 0; // how bright the LED is +int fadeAmount = 5; // how many points to fade the LED by + +void setup() { + // Use single LEDC channel 0 for both pins + ledcAttachChannel(LED_PIN_1, LEDC_BASE_FREQ, LEDC_TIMER_8_BIT, LEDC_CHANNEL); + ledcAttachChannel(LED_PIN_2, LEDC_BASE_FREQ, LEDC_TIMER_8_BIT, LEDC_CHANNEL); +} + +void loop() { + // set the brightness on LEDC channel 0 + ledcWriteChannel(LEDC_CHANNEL, brightness); + + // change the brightness for next time through the loop: + brightness = brightness + fadeAmount; + + // reverse the direction of the fading at the ends of the fade: + if (brightness <= 0 || brightness >= 255) { + fadeAmount = -fadeAmount; + } + // wait for 30 milliseconds to see the dimming effect + delay(30); +} diff --git a/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino b/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino new file mode 100644 index 0000000..c605a89 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino @@ -0,0 +1,53 @@ +/* + LEDC Software Fade + + This example shows how to software fade LED + using the ledcWrite function. + + Code adapted from original Arduino Fade example: + https://www.arduino.cc/en/Tutorial/Fade + + This example code is in the public domain. + */ + +// use 12 bit precision for LEDC timer +#define LEDC_TIMER_12_BIT 12 + +// use 5000 Hz as a LEDC base frequency +#define LEDC_BASE_FREQ 5000 + +// fade LED PIN (replace with LED_BUILTIN constant for built-in LED) +#define LED_PIN 5 + +int brightness = 0; // how bright the LED is +int fadeAmount = 5; // how many points to fade the LED by + +// Arduino like analogWrite +// value has to be between 0 and valueMax +void ledcAnalogWrite(uint8_t pin, uint32_t value, uint32_t valueMax = 255) { + // calculate duty, 4095 from 2 ^ 12 - 1 + uint32_t duty = (4095 / valueMax) * min(value, valueMax); + + // write duty to LEDC + ledcWrite(pin, duty); +} + +void setup() { + // Setup timer and attach timer to a led pin + ledcAttach(LED_PIN, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT); +} + +void loop() { + // set the brightness on LEDC channel 0 + ledcAnalogWrite(LED_PIN, brightness); + + // change the brightness for next time through the loop: + brightness = brightness + fadeAmount; + + // reverse the direction of the fading at the ends of the fade: + if (brightness <= 0 || brightness >= 255) { + fadeAmount = -fadeAmount; + } + // wait for 30 milliseconds to see the dimming effect + delay(30); +} diff --git a/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino b/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino new file mode 100644 index 0000000..d244a4e --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino @@ -0,0 +1,14 @@ +void setup() { + //setup on pin 18 with frequency 312500 Hz + sigmaDeltaAttach(18, 312500); + //set pin 18 to off + sigmaDeltaWrite(18, 0); +} + +void loop() { + //slowly ramp-up the value + //will overflow at 256 + static uint8_t i = 0; + sigmaDeltaWrite(18, i++); + delay(100); +} diff --git a/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino b/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino new file mode 100644 index 0000000..8e86c66 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino @@ -0,0 +1,77 @@ +/* + * This sketch will map the maximum frequency depending on the bit resolution for the current SoC. + * Run the sketch and wait for the Final report. + * Ignore the error messages from incorrect settings such as these: + * "E (4190) ledc: requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=255" + * + * Date: 11 Nov 2022 + * Author: Tomas Pilny + */ + +#include "soc/soc_caps.h" +#include + +#define PIN 2 + +void setup() { + ledcAttach(PIN, 1000, 8); + + uint32_t min_frequency; + uint32_t max_frequency; + uint32_t frequency; + uint32_t successful_frequency; + uint32_t max_freq_array[SOC_LEDC_TIMER_BIT_WIDTH]; + uint32_t min_freq_array[SOC_LEDC_TIMER_BIT_WIDTH]; + + // Find Max Frequency + for (uint8_t resolution = 1; resolution <= SOC_LEDC_TIMER_BIT_WIDTH; ++resolution) { + max_freq_array[resolution - 1] = 0; + min_frequency = 0; + max_frequency = UINT32_MAX; + successful_frequency = 0; + while (min_frequency != max_frequency && min_frequency + 1 != max_frequency) { + frequency = min_frequency + ((max_frequency - min_frequency) / 2); + if (ledcChangeFrequency(PIN, frequency, resolution)) { + min_frequency = frequency; + successful_frequency = frequency; + } else { + max_frequency = frequency; + } + } // while not found the maximum + max_freq_array[resolution - 1] = successful_frequency; + } // for all resolutions + + // Find Min Frequency + for (uint8_t resolution = 1; resolution <= SOC_LEDC_TIMER_BIT_WIDTH; ++resolution) { + min_freq_array[resolution - 1] = 0; + min_frequency = 0; + max_frequency = max_freq_array[resolution - 1]; + successful_frequency = max_frequency; + while (min_frequency != max_frequency && min_frequency + 1 != max_frequency) { + frequency = min_frequency + ((max_frequency - min_frequency) / 2); + if (ledcChangeFrequency(PIN, frequency, resolution)) { + max_frequency = frequency; + successful_frequency = frequency; + } else { + min_frequency = frequency; + } + } // while not found the maximum + min_freq_array[resolution - 1] = successful_frequency; + } // for all resolutions + + printf("Bit resolution | Min Frequency [Hz] | Max Frequency [Hz]\n"); + for (uint8_t r = 1; r <= SOC_LEDC_TIMER_BIT_WIDTH; ++r) { + size_t max_len = std::to_string(UINT32_MAX).length(); + printf( + " %s%d | %s%lu | %s%lu\n", std::string(2 - std::to_string(r).length(), ' ').c_str(), r, + std::string(max_len - std::to_string(min_freq_array[r - 1]).length(), ' ').c_str(), min_freq_array[r - 1], + std::string(max_len - std::to_string(max_freq_array[r - 1]).length(), ' ').c_str(), max_freq_array[r - 1] + ); + } + + ledcDetach(PIN); +} + +void loop() { + delay(1000); +} diff --git a/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino b/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino new file mode 100644 index 0000000..b7ea894 --- /dev/null +++ b/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino @@ -0,0 +1,117 @@ +/* + ledcWrite_RGB.ino + Runs through the full 255 color spectrum for an rgb led + Demonstrate ledcWrite functionality for driving leds with PWM on ESP32 + + This example code is in the public domain. + + Some basic modifications were made by vseven, mostly commenting. + */ + +// Set up the rgb led names +uint8_t ledR = 0; +uint8_t ledG = 2; +uint8_t ledB = 4; + +const boolean invert = true; // set true if common anode, false if common cathode + +uint8_t color = 0; // a value from 0 to 255 representing the hue +uint32_t R, G, B; // the Red Green and Blue color components +uint8_t brightness = 255; // 255 is maximum brightness, but can be changed. Might need 256 for common anode to fully turn off. + +// the setup routine runs once when you press reset: +void setup() { + Serial.begin(115200); + delay(10); + + // Initialize pins as LEDC channels + // resolution 1-16 bits, freq limits depend on resolution, channel is automatically selected + ledcAttach(ledR, 12000, 8); // 12 kHz PWM, 8-bit resolution + ledcAttach(ledG, 12000, 8); + ledcAttach(ledB, 12000, 8); +} + +// void loop runs over and over again +void loop() { + Serial.println("Send all LEDs a 255 and wait 2 seconds."); + // If your RGB LED turns off instead of on here you should check if the LED is common anode or cathode. + // If it doesn't fully turn off and is common anode try using 256. + ledcWrite(ledR, 255); + ledcWrite(ledG, 255); + ledcWrite(ledB, 255); + delay(2000); + Serial.println("Send all LEDs a 0 and wait 2 seconds."); + ledcWrite(ledR, 0); + ledcWrite(ledG, 0); + ledcWrite(ledB, 0); + delay(2000); + + Serial.println("Starting color fade loop."); + + for (color = 0; color < 255; color++) { // Slew through the color spectrum + + hueToRGB(color, brightness); // call function to convert hue to RGB + + // write the RGB values to the pins + ledcWrite(ledR, R); // write red component to channel 1, etc. + ledcWrite(ledG, G); + ledcWrite(ledB, B); + + delay(100); // full cycle of rgb over 256 colors takes 26 seconds + } +} + +// Courtesy http://www.instructables.com/id/How-to-Use-an-RGB-LED/?ALLSTEPS +// function to convert a color to its Red, Green, and Blue components. + +void hueToRGB(uint8_t hue, uint8_t brightness) { + uint16_t scaledHue = (hue * 6); + uint8_t segment = scaledHue / 256; // segment 0 to 5 around the + // color wheel + uint16_t segmentOffset = scaledHue - (segment * 256); // position within the segment + + uint8_t complement = 0; + uint16_t prev = (brightness * (255 - segmentOffset)) / 256; + uint16_t next = (brightness * segmentOffset) / 256; + + if (invert) { + brightness = 255 - brightness; + complement = 255; + prev = 255 - prev; + next = 255 - next; + } + + switch (segment) { + case 0: // red + R = brightness; + G = next; + B = complement; + break; + case 1: // yellow + R = prev; + G = brightness; + B = complement; + break; + case 2: // green + R = complement; + G = brightness; + B = next; + break; + case 3: // cyan + R = complement; + G = prev; + B = brightness; + break; + case 4: // blue + R = next; + G = complement; + B = brightness; + break; + case 5: // magenta + default: + R = brightness; + G = complement; + B = prev; + break; + } +} diff --git a/libraries/ESP32/examples/AnalogRead/AnalogRead.ino b/libraries/ESP32/examples/AnalogRead/AnalogRead.ino new file mode 100644 index 0000000..f887305 --- /dev/null +++ b/libraries/ESP32/examples/AnalogRead/AnalogRead.ino @@ -0,0 +1,19 @@ +void setup() { + // initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + //set the resolution to 12 bits (0-4095) + analogReadResolution(12); +} + +void loop() { + // read the analog / millivolts value for pin 2: + int analogValue = analogRead(2); + int analogVolts = analogReadMilliVolts(2); + + // print out the values you read: + Serial.printf("ADC analog value = %d\n", analogValue); + Serial.printf("ADC millivolts value = %d\n", analogVolts); + + delay(100); // delay in between reads for clear read from serial +} diff --git a/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino b/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino new file mode 100644 index 0000000..80c057a --- /dev/null +++ b/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino @@ -0,0 +1,70 @@ +// Define how many conversion per pin will happen and reading the data will be and average of all conversions +#define CONVERSIONS_PER_PIN 5 + +// Declare array of ADC pins that will be used for ADC Continuous mode - ONLY ADC1 pins are supported +// Number of selected pins can be from 1 to ALL ADC1 pins. +#ifdef CONFIG_IDF_TARGET_ESP32 +uint8_t adc_pins[] = {36, 39, 34, 35}; //some of ADC1 pins for ESP32 +#else +uint8_t adc_pins[] = {1, 2, 3, 4}; //ADC1 common pins for ESP32S2/S3 + ESP32C3/C6 + ESP32H2 +#endif + +// Calculate how many pins are declared in the array - needed as input for the setup function of ADC Continuous +uint8_t adc_pins_count = sizeof(adc_pins) / sizeof(uint8_t); + +// Flag which will be set in ISR when conversion is done +volatile bool adc_coversion_done = false; + +// Result structure for ADC Continuous reading +adc_continuous_result_t *result = NULL; + +// ISR Function that will be triggered when ADC conversion is done +void ARDUINO_ISR_ATTR adcComplete() { + adc_coversion_done = true; +} + +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + // Optional for ESP32: Set the resolution to 9-12 bits (default is 12 bits) + analogContinuousSetWidth(12); + + // Optional: Set different attenaution (default is ADC_11db) + analogContinuousSetAtten(ADC_11db); + + // Setup ADC Continuous with following input: + // array of pins, count of the pins, how many conversions per pin in one cycle will happen, sampling frequency, callback function + analogContinuous(adc_pins, adc_pins_count, CONVERSIONS_PER_PIN, 20000, &adcComplete); + + // Start ADC Continuous conversions + analogContinuousStart(); +} + +void loop() { + // Check if conversion is done and try to read data + if (adc_coversion_done == true) { + // Set ISR flag back to false + adc_coversion_done = false; + // Read data from ADC + if (analogContinuousRead(&result, 0)) { + + // Optional: Stop ADC Continuous conversions to have more time to process (print) the data + analogContinuousStop(); + + for (int i = 0; i < adc_pins_count; i++) { + Serial.printf("\nADC PIN %d data:", result[i].pin); + Serial.printf("\n Avg raw value = %d", result[i].avg_read_raw); + Serial.printf("\n Avg millivolts value = %d", result[i].avg_read_mvolts); + } + + // Delay for better readability of ADC data + delay(1000); + + // Optional: If ADC was stopped, start ADC conversions and wait for callback function to set adc_coversion_done flag to true + analogContinuousStart(); + } else { + Serial.println("Error occurred during reading data. Set Core Debug Level to error or lower for more information."); + } + } +} diff --git a/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino b/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino new file mode 100644 index 0000000..8b04f8b --- /dev/null +++ b/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino @@ -0,0 +1,35 @@ +/* + ESP32 Arduino creates a task to run setup() and then to execute loop() continuously + This task can be found at https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/main.cpp + + By default "loopTask" will be created with a stack size of 8KB. + This should be plenty for most general sketches. + + There is a way to change the stack size of this task by using + SET_LOOP_TASK_STACK_SIZE(size); + It will bypass the default stack size of 8KB and allow the user to define a new size. + + It is recommend this value to be higher than 8KB, for instance 16KB. + This increasing may be necessary for the sketches that use deep recursion for instance. + + In this example, you can verify it by changing or just commenting out SET_LOOP_TASK_STACK_SIZE(); +*/ + +// This sets Arduino Stack Size - comment this line to use default 8K stack size +SET_LOOP_TASK_STACK_SIZE(16 * 1024); // 16KB + +void setup() { + Serial.begin(115200); + + Serial.printf("Arduino Stack was set to %zu bytes", getArduinoLoopTaskStackSize()); + + // Print unused stack for the task that is running setup() + Serial.printf("\nSetup() - Free Stack Space: %u", uxTaskGetStackHighWaterMark(NULL)); +} + +void loop() { + delay(1000); + + // Print unused stack for the task that is running loop() - the same as for setup() + Serial.printf("\nLoop() - Free Stack Space: %u", uxTaskGetStackHighWaterMark(NULL)); +} diff --git a/libraries/ESP32/examples/ArduinoWaitTimeBeforeStartingSketch/ArduinoWaitTimeBeforeStartingSketch.ino b/libraries/ESP32/examples/ArduinoWaitTimeBeforeStartingSketch/ArduinoWaitTimeBeforeStartingSketch.ino new file mode 100644 index 0000000..7b23e25 --- /dev/null +++ b/libraries/ESP32/examples/ArduinoWaitTimeBeforeStartingSketch/ArduinoWaitTimeBeforeStartingSketch.ino @@ -0,0 +1,13 @@ +// macro SET_TIME_BEFORE_STARTING_SKETCH_MS(time_ms) can set a time in milliseconds +// before the sketch would start its execution. It gives the user time to open the Serial Monitor + +// This will force the Sketch execution to wait for 5 seconds before starting it execution +// setup() will be executed only after this time +SET_TIME_BEFORE_STARTING_SKETCH_MS(5000); + +void setup() { + Serial.begin(115200); + Serial.println("After 5 seconds... this message will be seen in the Serial Monitor."); +} + +void loop() {} diff --git a/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino b/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino new file mode 100644 index 0000000..748deaa --- /dev/null +++ b/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino @@ -0,0 +1,45 @@ +#include +#include + +void setup() { + // UART initialization + Serial.begin(9600); + + // I2C initialization + Wire.begin(); + + // SPI initialization + SPI.begin(); +} + +void loop() { + // UART echo + if (Serial.available()) { + Serial.write(Serial.read()); + } + + // I2C read/write + Wire.beginTransmission(0x68); // I2C address of device + Wire.write(0x00); // register to read/write + Wire.write(0xFF); // data to write (if writing) + Wire.endTransmission(); + + Wire.requestFrom(0x68, 1); // number of bytes to read + + while (Wire.available()) { + Serial.println(Wire.read()); + } + + // SPI read/write + digitalWrite(SS, LOW); // select slave device + SPI.transfer(0x01); // data to write + digitalWrite(SS, HIGH); // deselect slave device + + digitalWrite(SS, LOW); // select slave device + byte data = SPI.transfer(0x00); // data to read + digitalWrite(SS, HIGH); // deselect slave device + + Serial.println(data); + + delay(1000); // wait for 1 second before repeating loop +} diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino b/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino new file mode 100644 index 0000000..83733d4 --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino @@ -0,0 +1,130 @@ +#include "esp_camera.h" +#include + +// =========================== +// Select camera model in board_config.h +// =========================== +#include "board_config.h" + +// =========================== +// Enter your WiFi credentials +// =========================== +const char *ssid = "**********"; +const char *password = "**********"; + +void startCameraServer(); +void setupLedFlash(); + +void setup() { + Serial.begin(115200); + Serial.setDebugOutput(true); + Serial.println(); + + camera_config_t config; + config.ledc_channel = LEDC_CHANNEL_0; + config.ledc_timer = LEDC_TIMER_0; + config.pin_d0 = Y2_GPIO_NUM; + config.pin_d1 = Y3_GPIO_NUM; + config.pin_d2 = Y4_GPIO_NUM; + config.pin_d3 = Y5_GPIO_NUM; + config.pin_d4 = Y6_GPIO_NUM; + config.pin_d5 = Y7_GPIO_NUM; + config.pin_d6 = Y8_GPIO_NUM; + config.pin_d7 = Y9_GPIO_NUM; + config.pin_xclk = XCLK_GPIO_NUM; + config.pin_pclk = PCLK_GPIO_NUM; + config.pin_vsync = VSYNC_GPIO_NUM; + config.pin_href = HREF_GPIO_NUM; + config.pin_sccb_sda = SIOD_GPIO_NUM; + config.pin_sccb_scl = SIOC_GPIO_NUM; + config.pin_pwdn = PWDN_GPIO_NUM; + config.pin_reset = RESET_GPIO_NUM; + config.xclk_freq_hz = 20000000; + config.frame_size = FRAMESIZE_UXGA; + config.pixel_format = PIXFORMAT_JPEG; // for streaming + //config.pixel_format = PIXFORMAT_RGB565; // for face detection/recognition + config.grab_mode = CAMERA_GRAB_WHEN_EMPTY; + config.fb_location = CAMERA_FB_IN_PSRAM; + config.jpeg_quality = 12; + config.fb_count = 1; + + // if PSRAM IC present, init with UXGA resolution and higher JPEG quality + // for larger pre-allocated frame buffer. + if (config.pixel_format == PIXFORMAT_JPEG) { + if (psramFound()) { + config.jpeg_quality = 10; + config.fb_count = 2; + config.grab_mode = CAMERA_GRAB_LATEST; + } else { + // Limit the frame size when PSRAM is not available + config.frame_size = FRAMESIZE_SVGA; + config.fb_location = CAMERA_FB_IN_DRAM; + } + } else { + // Best option for face detection/recognition + config.frame_size = FRAMESIZE_240X240; +#if CONFIG_IDF_TARGET_ESP32S3 + config.fb_count = 2; +#endif + } + +#if defined(CAMERA_MODEL_ESP_EYE) + pinMode(13, INPUT_PULLUP); + pinMode(14, INPUT_PULLUP); +#endif + + // camera init + esp_err_t err = esp_camera_init(&config); + if (err != ESP_OK) { + Serial.printf("Camera init failed with error 0x%x", err); + return; + } + + sensor_t *s = esp_camera_sensor_get(); + // initial sensors are flipped vertically and colors are a bit saturated + if (s->id.PID == OV3660_PID) { + s->set_vflip(s, 1); // flip it back + s->set_brightness(s, 1); // up the brightness just a bit + s->set_saturation(s, -2); // lower the saturation + } + // drop down frame size for higher initial frame rate + if (config.pixel_format == PIXFORMAT_JPEG) { + s->set_framesize(s, FRAMESIZE_QVGA); + } + +#if defined(CAMERA_MODEL_M5STACK_WIDE) || defined(CAMERA_MODEL_M5STACK_ESP32CAM) + s->set_vflip(s, 1); + s->set_hmirror(s, 1); +#endif + +#if defined(CAMERA_MODEL_ESP32S3_EYE) + s->set_vflip(s, 1); +#endif + +// Setup LED FLash if LED pin is defined in camera_pins.h +#if defined(LED_GPIO_NUM) + setupLedFlash(); +#endif + + WiFi.begin(ssid, password); + WiFi.setSleep(false); + + Serial.print("WiFi connecting"); + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.println("WiFi connected"); + + startCameraServer(); + + Serial.print("Camera Ready! Use 'http://"); + Serial.print(WiFi.localIP()); + Serial.println("' to connect"); +} + +void loop() { + // Do nothing. Everything is done in another task by the web server + delay(10000); +} diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp b/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp new file mode 100644 index 0000000..589fea3 --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp @@ -0,0 +1,848 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "esp_http_server.h" +#include "esp_timer.h" +#include "esp_camera.h" +#include "img_converters.h" +#include "fb_gfx.h" +#include "esp32-hal-ledc.h" +#include "sdkconfig.h" +#include "camera_index.h" +#include "board_config.h" + +#if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG) +#include "esp32-hal-log.h" +#endif + +// LED FLASH setup +#if defined(LED_GPIO_NUM) +#define CONFIG_LED_MAX_INTENSITY 255 + +int led_duty = 0; +bool isStreaming = false; + +#endif + +typedef struct { + httpd_req_t *req; + size_t len; +} jpg_chunking_t; + +#define PART_BOUNDARY "123456789000000000000987654321" +static const char *_STREAM_CONTENT_TYPE = "multipart/x-mixed-replace;boundary=" PART_BOUNDARY; +static const char *_STREAM_BOUNDARY = "\r\n--" PART_BOUNDARY "\r\n"; +static const char *_STREAM_PART = "Content-Type: image/jpeg\r\nContent-Length: %u\r\nX-Timestamp: %d.%06d\r\n\r\n"; + +httpd_handle_t stream_httpd = NULL; +httpd_handle_t camera_httpd = NULL; + +typedef struct { + size_t size; //number of values used for filtering + size_t index; //current value index + size_t count; //value count + int sum; + int *values; //array to be filled with values +} ra_filter_t; + +static ra_filter_t ra_filter; + +static ra_filter_t *ra_filter_init(ra_filter_t *filter, size_t sample_size) { + memset(filter, 0, sizeof(ra_filter_t)); + + filter->values = (int *)malloc(sample_size * sizeof(int)); + if (!filter->values) { + return NULL; + } + memset(filter->values, 0, sample_size * sizeof(int)); + + filter->size = sample_size; + return filter; +} + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO +static int ra_filter_run(ra_filter_t *filter, int value) { + if (!filter->values) { + return value; + } + filter->sum -= filter->values[filter->index]; + filter->values[filter->index] = value; + filter->sum += filter->values[filter->index]; + filter->index++; + filter->index = filter->index % filter->size; + if (filter->count < filter->size) { + filter->count++; + } + return filter->sum / filter->count; +} +#endif + +#if defined(LED_GPIO_NUM) +void enable_led(bool en) { // Turn LED On or Off + int duty = en ? led_duty : 0; + if (en && isStreaming && (led_duty > CONFIG_LED_MAX_INTENSITY)) { + duty = CONFIG_LED_MAX_INTENSITY; + } + ledcWrite(LED_GPIO_NUM, duty); + //ledc_set_duty(CONFIG_LED_LEDC_SPEED_MODE, CONFIG_LED_LEDC_CHANNEL, duty); + //ledc_update_duty(CONFIG_LED_LEDC_SPEED_MODE, CONFIG_LED_LEDC_CHANNEL); + log_i("Set LED intensity to %d", duty); +} +#endif + +static esp_err_t bmp_handler(httpd_req_t *req) { + camera_fb_t *fb = NULL; + esp_err_t res = ESP_OK; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + uint64_t fr_start = esp_timer_get_time(); +#endif + fb = esp_camera_fb_get(); + if (!fb) { + log_e("Camera capture failed"); + httpd_resp_send_500(req); + return ESP_FAIL; + } + + httpd_resp_set_type(req, "image/x-windows-bmp"); + httpd_resp_set_hdr(req, "Content-Disposition", "inline; filename=capture.bmp"); + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + + char ts[32]; + snprintf(ts, 32, "%lld.%06ld", fb->timestamp.tv_sec, fb->timestamp.tv_usec); + httpd_resp_set_hdr(req, "X-Timestamp", (const char *)ts); + + uint8_t *buf = NULL; + size_t buf_len = 0; + bool converted = frame2bmp(fb, &buf, &buf_len); + esp_camera_fb_return(fb); + if (!converted) { + log_e("BMP Conversion failed"); + httpd_resp_send_500(req); + return ESP_FAIL; + } + res = httpd_resp_send(req, (const char *)buf, buf_len); + free(buf); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + uint64_t fr_end = esp_timer_get_time(); +#endif + log_i("BMP: %llums, %uB", (uint64_t)((fr_end - fr_start) / 1000), buf_len); + return res; +} + +static size_t jpg_encode_stream(void *arg, size_t index, const void *data, size_t len) { + jpg_chunking_t *j = (jpg_chunking_t *)arg; + if (!index) { + j->len = 0; + } + if (httpd_resp_send_chunk(j->req, (const char *)data, len) != ESP_OK) { + return 0; + } + j->len += len; + return len; +} + +static esp_err_t capture_handler(httpd_req_t *req) { + camera_fb_t *fb = NULL; + esp_err_t res = ESP_OK; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + int64_t fr_start = esp_timer_get_time(); +#endif + +#if defined(LED_GPIO_NUM) + enable_led(true); + vTaskDelay(150 / portTICK_PERIOD_MS); // The LED needs to be turned on ~150ms before the call to esp_camera_fb_get() + fb = esp_camera_fb_get(); // or it won't be visible in the frame. A better way to do this is needed. + enable_led(false); +#else + fb = esp_camera_fb_get(); +#endif + + if (!fb) { + log_e("Camera capture failed"); + httpd_resp_send_500(req); + return ESP_FAIL; + } + + httpd_resp_set_type(req, "image/jpeg"); + httpd_resp_set_hdr(req, "Content-Disposition", "inline; filename=capture.jpg"); + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + + char ts[32]; + snprintf(ts, 32, "%lld.%06ld", fb->timestamp.tv_sec, fb->timestamp.tv_usec); + httpd_resp_set_hdr(req, "X-Timestamp", (const char *)ts); + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + size_t fb_len = 0; +#endif + if (fb->format == PIXFORMAT_JPEG) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + fb_len = fb->len; +#endif + res = httpd_resp_send(req, (const char *)fb->buf, fb->len); + } else { + jpg_chunking_t jchunk = {req, 0}; + res = frame2jpg_cb(fb, 80, jpg_encode_stream, &jchunk) ? ESP_OK : ESP_FAIL; + httpd_resp_send_chunk(req, NULL, 0); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + fb_len = jchunk.len; +#endif + } + esp_camera_fb_return(fb); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + int64_t fr_end = esp_timer_get_time(); +#endif + log_i("JPG: %uB %ums", (uint32_t)(fb_len), (uint32_t)((fr_end - fr_start) / 1000)); + return res; +} + +static esp_err_t stream_handler(httpd_req_t *req) { + camera_fb_t *fb = NULL; + struct timeval _timestamp; + esp_err_t res = ESP_OK; + size_t _jpg_buf_len = 0; + uint8_t *_jpg_buf = NULL; + char *part_buf[128]; + + static int64_t last_frame = 0; + if (!last_frame) { + last_frame = esp_timer_get_time(); + } + + res = httpd_resp_set_type(req, _STREAM_CONTENT_TYPE); + if (res != ESP_OK) { + return res; + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + httpd_resp_set_hdr(req, "X-Framerate", "60"); + +#if defined(LED_GPIO_NUM) + isStreaming = true; + enable_led(true); +#endif + + while (true) { + fb = esp_camera_fb_get(); + if (!fb) { + log_e("Camera capture failed"); + res = ESP_FAIL; + } else { + _timestamp.tv_sec = fb->timestamp.tv_sec; + _timestamp.tv_usec = fb->timestamp.tv_usec; + if (fb->format != PIXFORMAT_JPEG) { + bool jpeg_converted = frame2jpg(fb, 80, &_jpg_buf, &_jpg_buf_len); + esp_camera_fb_return(fb); + fb = NULL; + if (!jpeg_converted) { + log_e("JPEG compression failed"); + res = ESP_FAIL; + } + } else { + _jpg_buf_len = fb->len; + _jpg_buf = fb->buf; + } + } + if (res == ESP_OK) { + res = httpd_resp_send_chunk(req, _STREAM_BOUNDARY, strlen(_STREAM_BOUNDARY)); + } + if (res == ESP_OK) { + size_t hlen = snprintf((char *)part_buf, 128, _STREAM_PART, _jpg_buf_len, _timestamp.tv_sec, _timestamp.tv_usec); + res = httpd_resp_send_chunk(req, (const char *)part_buf, hlen); + } + if (res == ESP_OK) { + res = httpd_resp_send_chunk(req, (const char *)_jpg_buf, _jpg_buf_len); + } + if (fb) { + esp_camera_fb_return(fb); + fb = NULL; + _jpg_buf = NULL; + } else if (_jpg_buf) { + free(_jpg_buf); + _jpg_buf = NULL; + } + if (res != ESP_OK) { + log_e("Send frame failed"); + break; + } + int64_t fr_end = esp_timer_get_time(); + + int64_t frame_time = fr_end - last_frame; + last_frame = fr_end; + + frame_time /= 1000; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + uint32_t avg_frame_time = ra_filter_run(&ra_filter, frame_time); +#endif + log_i( + "MJPG: %uB %ums (%.1ffps), AVG: %ums (%.1ffps)", (uint32_t)(_jpg_buf_len), (uint32_t)frame_time, 1000.0 / (uint32_t)frame_time, avg_frame_time, + 1000.0 / avg_frame_time + ); + } + +#if defined(LED_GPIO_NUM) + isStreaming = false; + enable_led(false); +#endif + + return res; +} + +static esp_err_t parse_get(httpd_req_t *req, char **obuf) { + char *buf = NULL; + size_t buf_len = 0; + + buf_len = httpd_req_get_url_query_len(req) + 1; + if (buf_len > 1) { + buf = (char *)malloc(buf_len); + if (!buf) { + httpd_resp_send_500(req); + return ESP_FAIL; + } + if (httpd_req_get_url_query_str(req, buf, buf_len) == ESP_OK) { + *obuf = buf; + return ESP_OK; + } + free(buf); + } + httpd_resp_send_404(req); + return ESP_FAIL; +} + +static esp_err_t cmd_handler(httpd_req_t *req) { + char *buf = NULL; + char variable[32]; + char value[32]; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + if (httpd_query_key_value(buf, "var", variable, sizeof(variable)) != ESP_OK || httpd_query_key_value(buf, "val", value, sizeof(value)) != ESP_OK) { + free(buf); + httpd_resp_send_404(req); + return ESP_FAIL; + } + free(buf); + + int val = atoi(value); + log_i("%s = %d", variable, val); + sensor_t *s = esp_camera_sensor_get(); + int res = 0; + + if (!strcmp(variable, "framesize")) { + if (s->pixformat == PIXFORMAT_JPEG) { + res = s->set_framesize(s, (framesize_t)val); + } + } else if (!strcmp(variable, "quality")) { + res = s->set_quality(s, val); + } else if (!strcmp(variable, "contrast")) { + res = s->set_contrast(s, val); + } else if (!strcmp(variable, "brightness")) { + res = s->set_brightness(s, val); + } else if (!strcmp(variable, "saturation")) { + res = s->set_saturation(s, val); + } else if (!strcmp(variable, "gainceiling")) { + res = s->set_gainceiling(s, (gainceiling_t)val); + } else if (!strcmp(variable, "colorbar")) { + res = s->set_colorbar(s, val); + } else if (!strcmp(variable, "awb")) { + res = s->set_whitebal(s, val); + } else if (!strcmp(variable, "agc")) { + res = s->set_gain_ctrl(s, val); + } else if (!strcmp(variable, "aec")) { + res = s->set_exposure_ctrl(s, val); + } else if (!strcmp(variable, "hmirror")) { + res = s->set_hmirror(s, val); + } else if (!strcmp(variable, "vflip")) { + res = s->set_vflip(s, val); + } else if (!strcmp(variable, "awb_gain")) { + res = s->set_awb_gain(s, val); + } else if (!strcmp(variable, "agc_gain")) { + res = s->set_agc_gain(s, val); + } else if (!strcmp(variable, "aec_value")) { + res = s->set_aec_value(s, val); + } else if (!strcmp(variable, "aec2")) { + res = s->set_aec2(s, val); + } else if (!strcmp(variable, "dcw")) { + res = s->set_dcw(s, val); + } else if (!strcmp(variable, "bpc")) { + res = s->set_bpc(s, val); + } else if (!strcmp(variable, "wpc")) { + res = s->set_wpc(s, val); + } else if (!strcmp(variable, "raw_gma")) { + res = s->set_raw_gma(s, val); + } else if (!strcmp(variable, "lenc")) { + res = s->set_lenc(s, val); + } else if (!strcmp(variable, "special_effect")) { + res = s->set_special_effect(s, val); + } else if (!strcmp(variable, "wb_mode")) { + res = s->set_wb_mode(s, val); + } else if (!strcmp(variable, "ae_level")) { + res = s->set_ae_level(s, val); + } +#if defined(LED_GPIO_NUM) + else if (!strcmp(variable, "led_intensity")) { + led_duty = val; + if (isStreaming) { + enable_led(true); + } + } +#endif + else { + log_i("Unknown command: %s", variable); + res = -1; + } + + if (res < 0) { + return httpd_resp_send_500(req); + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, NULL, 0); +} + +static int print_reg(char *p, sensor_t *s, uint16_t reg, uint32_t mask) { + return sprintf(p, "\"0x%x\":%u,", reg, s->get_reg(s, reg, mask)); +} + +static esp_err_t status_handler(httpd_req_t *req) { + static char json_response[1024]; + + sensor_t *s = esp_camera_sensor_get(); + char *p = json_response; + *p++ = '{'; + + if (s->id.PID == OV5640_PID || s->id.PID == OV3660_PID) { + for (int reg = 0x3400; reg < 0x3406; reg += 2) { + p += print_reg(p, s, reg, 0xFFF); //12 bit + } + p += print_reg(p, s, 0x3406, 0xFF); + + p += print_reg(p, s, 0x3500, 0xFFFF0); //16 bit + p += print_reg(p, s, 0x3503, 0xFF); + p += print_reg(p, s, 0x350a, 0x3FF); //10 bit + p += print_reg(p, s, 0x350c, 0xFFFF); //16 bit + + for (int reg = 0x5480; reg <= 0x5490; reg++) { + p += print_reg(p, s, reg, 0xFF); + } + + for (int reg = 0x5380; reg <= 0x538b; reg++) { + p += print_reg(p, s, reg, 0xFF); + } + + for (int reg = 0x5580; reg < 0x558a; reg++) { + p += print_reg(p, s, reg, 0xFF); + } + p += print_reg(p, s, 0x558a, 0x1FF); //9 bit + } else if (s->id.PID == OV2640_PID) { + p += print_reg(p, s, 0xd3, 0xFF); + p += print_reg(p, s, 0x111, 0xFF); + p += print_reg(p, s, 0x132, 0xFF); + } + + p += sprintf(p, "\"xclk\":%u,", s->xclk_freq_hz / 1000000); + p += sprintf(p, "\"pixformat\":%u,", s->pixformat); + p += sprintf(p, "\"framesize\":%u,", s->status.framesize); + p += sprintf(p, "\"quality\":%u,", s->status.quality); + p += sprintf(p, "\"brightness\":%d,", s->status.brightness); + p += sprintf(p, "\"contrast\":%d,", s->status.contrast); + p += sprintf(p, "\"saturation\":%d,", s->status.saturation); + p += sprintf(p, "\"sharpness\":%d,", s->status.sharpness); + p += sprintf(p, "\"special_effect\":%u,", s->status.special_effect); + p += sprintf(p, "\"wb_mode\":%u,", s->status.wb_mode); + p += sprintf(p, "\"awb\":%u,", s->status.awb); + p += sprintf(p, "\"awb_gain\":%u,", s->status.awb_gain); + p += sprintf(p, "\"aec\":%u,", s->status.aec); + p += sprintf(p, "\"aec2\":%u,", s->status.aec2); + p += sprintf(p, "\"ae_level\":%d,", s->status.ae_level); + p += sprintf(p, "\"aec_value\":%u,", s->status.aec_value); + p += sprintf(p, "\"agc\":%u,", s->status.agc); + p += sprintf(p, "\"agc_gain\":%u,", s->status.agc_gain); + p += sprintf(p, "\"gainceiling\":%u,", s->status.gainceiling); + p += sprintf(p, "\"bpc\":%u,", s->status.bpc); + p += sprintf(p, "\"wpc\":%u,", s->status.wpc); + p += sprintf(p, "\"raw_gma\":%u,", s->status.raw_gma); + p += sprintf(p, "\"lenc\":%u,", s->status.lenc); + p += sprintf(p, "\"hmirror\":%u,", s->status.hmirror); + p += sprintf(p, "\"vflip\":%u,", s->status.vflip); + p += sprintf(p, "\"dcw\":%u,", s->status.dcw); + p += sprintf(p, "\"colorbar\":%u", s->status.colorbar); +#if defined(LED_GPIO_NUM) + p += sprintf(p, ",\"led_intensity\":%u", led_duty); +#else + p += sprintf(p, ",\"led_intensity\":%d", -1); +#endif + *p++ = '}'; + *p++ = 0; + httpd_resp_set_type(req, "application/json"); + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, json_response, strlen(json_response)); +} + +static esp_err_t xclk_handler(httpd_req_t *req) { + char *buf = NULL; + char _xclk[32]; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + if (httpd_query_key_value(buf, "xclk", _xclk, sizeof(_xclk)) != ESP_OK) { + free(buf); + httpd_resp_send_404(req); + return ESP_FAIL; + } + free(buf); + + int xclk = atoi(_xclk); + log_i("Set XCLK: %d MHz", xclk); + + sensor_t *s = esp_camera_sensor_get(); + int res = s->set_xclk(s, LEDC_TIMER_0, xclk); + if (res) { + return httpd_resp_send_500(req); + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, NULL, 0); +} + +static esp_err_t reg_handler(httpd_req_t *req) { + char *buf = NULL; + char _reg[32]; + char _mask[32]; + char _val[32]; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + if (httpd_query_key_value(buf, "reg", _reg, sizeof(_reg)) != ESP_OK || httpd_query_key_value(buf, "mask", _mask, sizeof(_mask)) != ESP_OK + || httpd_query_key_value(buf, "val", _val, sizeof(_val)) != ESP_OK) { + free(buf); + httpd_resp_send_404(req); + return ESP_FAIL; + } + free(buf); + + int reg = atoi(_reg); + int mask = atoi(_mask); + int val = atoi(_val); + log_i("Set Register: reg: 0x%02x, mask: 0x%02x, value: 0x%02x", reg, mask, val); + + sensor_t *s = esp_camera_sensor_get(); + int res = s->set_reg(s, reg, mask, val); + if (res) { + return httpd_resp_send_500(req); + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, NULL, 0); +} + +static esp_err_t greg_handler(httpd_req_t *req) { + char *buf = NULL; + char _reg[32]; + char _mask[32]; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + if (httpd_query_key_value(buf, "reg", _reg, sizeof(_reg)) != ESP_OK || httpd_query_key_value(buf, "mask", _mask, sizeof(_mask)) != ESP_OK) { + free(buf); + httpd_resp_send_404(req); + return ESP_FAIL; + } + free(buf); + + int reg = atoi(_reg); + int mask = atoi(_mask); + sensor_t *s = esp_camera_sensor_get(); + int res = s->get_reg(s, reg, mask); + if (res < 0) { + return httpd_resp_send_500(req); + } + log_i("Get Register: reg: 0x%02x, mask: 0x%02x, value: 0x%02x", reg, mask, res); + + char buffer[20]; + const char *val = itoa(res, buffer, 10); + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, val, strlen(val)); +} + +static int parse_get_var(char *buf, const char *key, int def) { + char _int[16]; + if (httpd_query_key_value(buf, key, _int, sizeof(_int)) != ESP_OK) { + return def; + } + return atoi(_int); +} + +static esp_err_t pll_handler(httpd_req_t *req) { + char *buf = NULL; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + + int bypass = parse_get_var(buf, "bypass", 0); + int mul = parse_get_var(buf, "mul", 0); + int sys = parse_get_var(buf, "sys", 0); + int root = parse_get_var(buf, "root", 0); + int pre = parse_get_var(buf, "pre", 0); + int seld5 = parse_get_var(buf, "seld5", 0); + int pclken = parse_get_var(buf, "pclken", 0); + int pclk = parse_get_var(buf, "pclk", 0); + free(buf); + + log_i("Set Pll: bypass: %d, mul: %d, sys: %d, root: %d, pre: %d, seld5: %d, pclken: %d, pclk: %d", bypass, mul, sys, root, pre, seld5, pclken, pclk); + sensor_t *s = esp_camera_sensor_get(); + int res = s->set_pll(s, bypass, mul, sys, root, pre, seld5, pclken, pclk); + if (res) { + return httpd_resp_send_500(req); + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, NULL, 0); +} + +static esp_err_t win_handler(httpd_req_t *req) { + char *buf = NULL; + + if (parse_get(req, &buf) != ESP_OK) { + return ESP_FAIL; + } + + int startX = parse_get_var(buf, "sx", 0); + int startY = parse_get_var(buf, "sy", 0); + int endX = parse_get_var(buf, "ex", 0); + int endY = parse_get_var(buf, "ey", 0); + int offsetX = parse_get_var(buf, "offx", 0); + int offsetY = parse_get_var(buf, "offy", 0); + int totalX = parse_get_var(buf, "tx", 0); + int totalY = parse_get_var(buf, "ty", 0); // codespell:ignore totaly + int outputX = parse_get_var(buf, "ox", 0); + int outputY = parse_get_var(buf, "oy", 0); + bool scale = parse_get_var(buf, "scale", 0) == 1; + bool binning = parse_get_var(buf, "binning", 0) == 1; + free(buf); + + log_i( + "Set Window: Start: %d %d, End: %d %d, Offset: %d %d, Total: %d %d, Output: %d %d, Scale: %u, Binning: %u", startX, startY, endX, endY, offsetX, offsetY, + totalX, totalY, outputX, outputY, scale, binning // codespell:ignore totaly + ); + sensor_t *s = esp_camera_sensor_get(); + int res = s->set_res_raw(s, startX, startY, endX, endY, offsetX, offsetY, totalX, totalY, outputX, outputY, scale, binning); // codespell:ignore totaly + if (res) { + return httpd_resp_send_500(req); + } + + httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*"); + return httpd_resp_send(req, NULL, 0); +} + +static esp_err_t index_handler(httpd_req_t *req) { + httpd_resp_set_type(req, "text/html"); + httpd_resp_set_hdr(req, "Content-Encoding", "gzip"); + sensor_t *s = esp_camera_sensor_get(); + if (s != NULL) { + if (s->id.PID == OV3660_PID) { + return httpd_resp_send(req, (const char *)index_ov3660_html_gz, index_ov3660_html_gz_len); + } else if (s->id.PID == OV5640_PID) { + return httpd_resp_send(req, (const char *)index_ov5640_html_gz, index_ov5640_html_gz_len); + } else { + return httpd_resp_send(req, (const char *)index_ov2640_html_gz, index_ov2640_html_gz_len); + } + } else { + log_e("Camera sensor not found"); + return httpd_resp_send_500(req); + } +} + +void startCameraServer() { + httpd_config_t config = HTTPD_DEFAULT_CONFIG(); + config.max_uri_handlers = 16; + + httpd_uri_t index_uri = { + .uri = "/", + .method = HTTP_GET, + .handler = index_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t status_uri = { + .uri = "/status", + .method = HTTP_GET, + .handler = status_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t cmd_uri = { + .uri = "/control", + .method = HTTP_GET, + .handler = cmd_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t capture_uri = { + .uri = "/capture", + .method = HTTP_GET, + .handler = capture_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t stream_uri = { + .uri = "/stream", + .method = HTTP_GET, + .handler = stream_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t bmp_uri = { + .uri = "/bmp", + .method = HTTP_GET, + .handler = bmp_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t xclk_uri = { + .uri = "/xclk", + .method = HTTP_GET, + .handler = xclk_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t reg_uri = { + .uri = "/reg", + .method = HTTP_GET, + .handler = reg_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t greg_uri = { + .uri = "/greg", + .method = HTTP_GET, + .handler = greg_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t pll_uri = { + .uri = "/pll", + .method = HTTP_GET, + .handler = pll_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + httpd_uri_t win_uri = { + .uri = "/resolution", + .method = HTTP_GET, + .handler = win_handler, + .user_ctx = NULL +#ifdef CONFIG_HTTPD_WS_SUPPORT + , + .is_websocket = true, + .handle_ws_control_frames = false, + .supported_subprotocol = NULL +#endif + }; + + ra_filter_init(&ra_filter, 20); + + log_i("Starting web server on port: '%d'", config.server_port); + if (httpd_start(&camera_httpd, &config) == ESP_OK) { + httpd_register_uri_handler(camera_httpd, &index_uri); + httpd_register_uri_handler(camera_httpd, &cmd_uri); + httpd_register_uri_handler(camera_httpd, &status_uri); + httpd_register_uri_handler(camera_httpd, &capture_uri); + httpd_register_uri_handler(camera_httpd, &bmp_uri); + + httpd_register_uri_handler(camera_httpd, &xclk_uri); + httpd_register_uri_handler(camera_httpd, ®_uri); + httpd_register_uri_handler(camera_httpd, &greg_uri); + httpd_register_uri_handler(camera_httpd, &pll_uri); + httpd_register_uri_handler(camera_httpd, &win_uri); + } + + config.server_port += 1; + config.ctrl_port += 1; + log_i("Starting stream server on port: '%d'", config.server_port); + if (httpd_start(&stream_httpd, &config) == ESP_OK) { + httpd_register_uri_handler(stream_httpd, &stream_uri); + } +} + +void setupLedFlash() { +#if defined(LED_GPIO_NUM) + ledcAttach(LED_GPIO_NUM, 5000, 8); +#else + log_i("LED flash is disabled -> LED_GPIO_NUM undefined"); +#endif +} diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/board_config.h b/libraries/ESP32/examples/Camera/CameraWebServer/board_config.h new file mode 100644 index 0000000..ca7edba --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/board_config.h @@ -0,0 +1,34 @@ +#ifndef BOARD_CONFIG_H +#define BOARD_CONFIG_H + +// +// WARNING!!! PSRAM IC required for UXGA resolution and high JPEG quality +// Ensure ESP32 Wrover Module or other board with PSRAM is selected +// Partial images will be transmitted if image exceeds buffer size +// +// You must select partition scheme from the board menu that has at least 3MB APP space. + +// =================== +// Select camera model +// =================== +//#define CAMERA_MODEL_WROVER_KIT // Has PSRAM +#define CAMERA_MODEL_ESP_EYE // Has PSRAM +//#define CAMERA_MODEL_ESP32S3_EYE // Has PSRAM +//#define CAMERA_MODEL_M5STACK_PSRAM // Has PSRAM +//#define CAMERA_MODEL_M5STACK_V2_PSRAM // M5Camera version B Has PSRAM +//#define CAMERA_MODEL_M5STACK_WIDE // Has PSRAM +//#define CAMERA_MODEL_M5STACK_ESP32CAM // No PSRAM +//#define CAMERA_MODEL_M5STACK_UNITCAM // No PSRAM +//#define CAMERA_MODEL_M5STACK_CAMS3_UNIT // Has PSRAM +//#define CAMERA_MODEL_AI_THINKER // Has PSRAM +//#define CAMERA_MODEL_TTGO_T_JOURNAL // No PSRAM +//#define CAMERA_MODEL_XIAO_ESP32S3 // Has PSRAM +// ** Espressif Internal Boards ** +//#define CAMERA_MODEL_ESP32_CAM_BOARD +//#define CAMERA_MODEL_ESP32S2_CAM_BOARD +//#define CAMERA_MODEL_ESP32S3_CAM_LCD +//#define CAMERA_MODEL_DFRobot_FireBeetle2_ESP32S3 // Has PSRAM +//#define CAMERA_MODEL_DFRobot_Romeo_ESP32S3 // Has PSRAM +#include "camera_pins.h" + +#endif // BOARD_CONFIG_H diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h b/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h new file mode 100644 index 0000000..b38e277 --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h @@ -0,0 +1,949 @@ + +//File: index_ov2640.html.gz, Size: 6687 +#define index_ov2640_html_gz_len 6687 +const unsigned char index_ov2640_html_gz[] = { + 0x1F, 0x8B, 0x08, 0x08, 0xA5, 0xF6, 0xDA, 0x67, 0x00, 0xFF, 0x69, 0x6E, 0x64, 0x65, 0x78, 0x5F, 0x6F, 0x76, 0x32, 0x36, 0x34, 0x30, 0x2E, 0x68, 0x74, 0x6D, + 0x6C, 0x2E, 0x67, 0x7A, 0x00, 0xED, 0x7D, 0x7B, 0x73, 0xDB, 0x36, 0xD6, 0xF7, 0xFF, 0xFD, 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0xE2, 0xB3, 0xF2, 0x8A, 0x78, 0xFC, + 0x51, 0x47, 0xCD, 0xD2, 0x95, 0xA9, 0xA3, 0x2D, 0x08, 0x7E, 0xD9, 0x3E, 0x20, 0x36, 0xB8, 0x92, 0x45, 0x73, 0xD0, 0x88, 0x0D, 0x10, 0xC1, 0xA9, 0x14, 0xD9, + 0x41, 0xEB, 0xD0, 0x8C, 0x43, 0x04, 0x6C, 0xBE, 0x30, 0x52, 0x06, 0xC9, 0xB9, 0x2E, 0x1B, 0xF7, 0x75, 0x4A, 0x7D, 0x62, 0x74, 0x8F, 0x36, 0x70, 0xC8, 0xC4, + 0x9E, 0x59, 0x80, 0x29, 0xD6, 0x86, 0x99, 0x2A, 0x1B, 0xFC, 0xD9, 0xEF, 0xEC, 0xD0, 0x7F, 0x3C, 0x86, 0x9D, 0x61, 0x51, 0x70, 0xF4, 0xE8, 0xEC, 0x70, 0xEE, + 0x2D, 0xCC, 0xD1, 0xA3, 0xFF, 0x05, 0xDF, 0x19, 0xEB, 0xA3, 0xC1, 0x08, 0x01, 0x00 + +}; diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h b/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h new file mode 100644 index 0000000..3408508 --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h @@ -0,0 +1,338 @@ + +#if defined(CAMERA_MODEL_WROVER_KIT) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 21 +#define SIOD_GPIO_NUM 26 +#define SIOC_GPIO_NUM 27 + +#define Y9_GPIO_NUM 35 +#define Y8_GPIO_NUM 34 +#define Y7_GPIO_NUM 39 +#define Y6_GPIO_NUM 36 +#define Y5_GPIO_NUM 19 +#define Y4_GPIO_NUM 18 +#define Y3_GPIO_NUM 5 +#define Y2_GPIO_NUM 4 +#define VSYNC_GPIO_NUM 25 +#define HREF_GPIO_NUM 23 +#define PCLK_GPIO_NUM 22 + +#elif defined(CAMERA_MODEL_ESP_EYE) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 4 +#define SIOD_GPIO_NUM 18 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 36 +#define Y8_GPIO_NUM 37 +#define Y7_GPIO_NUM 38 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 35 +#define Y4_GPIO_NUM 14 +#define Y3_GPIO_NUM 13 +#define Y2_GPIO_NUM 34 +#define VSYNC_GPIO_NUM 5 +#define HREF_GPIO_NUM 27 +#define PCLK_GPIO_NUM 25 + +#define LED_GPIO_NUM 22 + +#elif defined(CAMERA_MODEL_M5STACK_PSRAM) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 25 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 32 +#define VSYNC_GPIO_NUM 22 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#elif defined(CAMERA_MODEL_M5STACK_V2_PSRAM) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 22 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 32 +#define VSYNC_GPIO_NUM 25 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#elif defined(CAMERA_MODEL_M5STACK_WIDE) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 22 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 32 +#define VSYNC_GPIO_NUM 25 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#define LED_GPIO_NUM 2 + +#elif defined(CAMERA_MODEL_M5STACK_ESP32CAM) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 25 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 17 +#define VSYNC_GPIO_NUM 22 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#elif defined(CAMERA_MODEL_M5STACK_UNITCAM) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 25 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 32 +#define VSYNC_GPIO_NUM 22 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#elif defined(CAMERA_MODEL_M5STACK_CAMS3_UNIT) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM 21 +#define XCLK_GPIO_NUM 11 +#define SIOD_GPIO_NUM 17 +#define SIOC_GPIO_NUM 41 + +#define Y9_GPIO_NUM 13 +#define Y8_GPIO_NUM 4 +#define Y7_GPIO_NUM 10 +#define Y6_GPIO_NUM 5 +#define Y5_GPIO_NUM 7 +#define Y4_GPIO_NUM 16 +#define Y3_GPIO_NUM 15 +#define Y2_GPIO_NUM 6 +#define VSYNC_GPIO_NUM 42 +#define HREF_GPIO_NUM 18 +#define PCLK_GPIO_NUM 12 + +#define LED_GPIO_NUM 14 + +#elif defined(CAMERA_MODEL_AI_THINKER) +#define PWDN_GPIO_NUM 32 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 0 +#define SIOD_GPIO_NUM 26 +#define SIOC_GPIO_NUM 27 + +#define Y9_GPIO_NUM 35 +#define Y8_GPIO_NUM 34 +#define Y7_GPIO_NUM 39 +#define Y6_GPIO_NUM 36 +#define Y5_GPIO_NUM 21 +#define Y4_GPIO_NUM 19 +#define Y3_GPIO_NUM 18 +#define Y2_GPIO_NUM 5 +#define VSYNC_GPIO_NUM 25 +#define HREF_GPIO_NUM 23 +#define PCLK_GPIO_NUM 22 + +// 4 for flash led or 33 for normal led +#define LED_GPIO_NUM 4 + +#elif defined(CAMERA_MODEL_TTGO_T_JOURNAL) +#define PWDN_GPIO_NUM 0 +#define RESET_GPIO_NUM 15 +#define XCLK_GPIO_NUM 27 +#define SIOD_GPIO_NUM 25 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 19 +#define Y8_GPIO_NUM 36 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 5 +#define Y4_GPIO_NUM 34 +#define Y3_GPIO_NUM 35 +#define Y2_GPIO_NUM 17 +#define VSYNC_GPIO_NUM 22 +#define HREF_GPIO_NUM 26 +#define PCLK_GPIO_NUM 21 + +#elif defined(CAMERA_MODEL_XIAO_ESP32S3) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 10 +#define SIOD_GPIO_NUM 40 +#define SIOC_GPIO_NUM 39 + +#define Y9_GPIO_NUM 48 +#define Y8_GPIO_NUM 11 +#define Y7_GPIO_NUM 12 +#define Y6_GPIO_NUM 14 +#define Y5_GPIO_NUM 16 +#define Y4_GPIO_NUM 18 +#define Y3_GPIO_NUM 17 +#define Y2_GPIO_NUM 15 +#define VSYNC_GPIO_NUM 38 +#define HREF_GPIO_NUM 47 +#define PCLK_GPIO_NUM 13 + +#elif defined(CAMERA_MODEL_ESP32_CAM_BOARD) +// The 18 pin header on the board has Y5 and Y3 swapped +#define USE_BOARD_HEADER 0 +#define PWDN_GPIO_NUM 32 +#define RESET_GPIO_NUM 33 +#define XCLK_GPIO_NUM 4 +#define SIOD_GPIO_NUM 18 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 36 +#define Y8_GPIO_NUM 19 +#define Y7_GPIO_NUM 21 +#define Y6_GPIO_NUM 39 +#if USE_BOARD_HEADER +#define Y5_GPIO_NUM 13 +#else +#define Y5_GPIO_NUM 35 +#endif +#define Y4_GPIO_NUM 14 +#if USE_BOARD_HEADER +#define Y3_GPIO_NUM 35 +#else +#define Y3_GPIO_NUM 13 +#endif +#define Y2_GPIO_NUM 34 +#define VSYNC_GPIO_NUM 5 +#define HREF_GPIO_NUM 27 +#define PCLK_GPIO_NUM 25 + +#elif defined(CAMERA_MODEL_ESP32S3_CAM_LCD) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 40 +#define SIOD_GPIO_NUM 17 +#define SIOC_GPIO_NUM 18 + +#define Y9_GPIO_NUM 39 +#define Y8_GPIO_NUM 41 +#define Y7_GPIO_NUM 42 +#define Y6_GPIO_NUM 12 +#define Y5_GPIO_NUM 3 +#define Y4_GPIO_NUM 14 +#define Y3_GPIO_NUM 47 +#define Y2_GPIO_NUM 13 +#define VSYNC_GPIO_NUM 21 +#define HREF_GPIO_NUM 38 +#define PCLK_GPIO_NUM 11 + +#elif defined(CAMERA_MODEL_ESP32S2_CAM_BOARD) +// The 18 pin header on the board has Y5 and Y3 swapped +#define USE_BOARD_HEADER 0 +#define PWDN_GPIO_NUM 1 +#define RESET_GPIO_NUM 2 +#define XCLK_GPIO_NUM 42 +#define SIOD_GPIO_NUM 41 +#define SIOC_GPIO_NUM 18 + +#define Y9_GPIO_NUM 16 +#define Y8_GPIO_NUM 39 +#define Y7_GPIO_NUM 40 +#define Y6_GPIO_NUM 15 +#if USE_BOARD_HEADER +#define Y5_GPIO_NUM 12 +#else +#define Y5_GPIO_NUM 13 +#endif +#define Y4_GPIO_NUM 5 +#if USE_BOARD_HEADER +#define Y3_GPIO_NUM 13 +#else +#define Y3_GPIO_NUM 12 +#endif +#define Y2_GPIO_NUM 14 +#define VSYNC_GPIO_NUM 38 +#define HREF_GPIO_NUM 4 +#define PCLK_GPIO_NUM 3 + +#elif defined(CAMERA_MODEL_ESP32S3_EYE) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 15 +#define SIOD_GPIO_NUM 4 +#define SIOC_GPIO_NUM 5 + +#define Y2_GPIO_NUM 11 +#define Y3_GPIO_NUM 9 +#define Y4_GPIO_NUM 8 +#define Y5_GPIO_NUM 10 +#define Y6_GPIO_NUM 12 +#define Y7_GPIO_NUM 18 +#define Y8_GPIO_NUM 17 +#define Y9_GPIO_NUM 16 + +#define VSYNC_GPIO_NUM 6 +#define HREF_GPIO_NUM 7 +#define PCLK_GPIO_NUM 13 + +#elif defined(CAMERA_MODEL_DFRobot_FireBeetle2_ESP32S3) || defined(CAMERA_MODEL_DFRobot_Romeo_ESP32S3) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 45 +#define SIOD_GPIO_NUM 1 +#define SIOC_GPIO_NUM 2 + +#define Y9_GPIO_NUM 48 +#define Y8_GPIO_NUM 46 +#define Y7_GPIO_NUM 8 +#define Y6_GPIO_NUM 7 +#define Y5_GPIO_NUM 4 +#define Y4_GPIO_NUM 41 +#define Y3_GPIO_NUM 40 +#define Y2_GPIO_NUM 39 +#define VSYNC_GPIO_NUM 6 +#define HREF_GPIO_NUM 42 +#define PCLK_GPIO_NUM 5 + +#else +#error "Camera model not selected" +#endif diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/ci.yml b/libraries/ESP32/examples/Camera/CameraWebServer/ci.yml new file mode 100644 index 0000000..aea91ac --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/ci.yml @@ -0,0 +1,14 @@ +fqbn: + esp32: + - espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=custom,FlashMode=dio + - espressif:esp32:esp32:PSRAM=disabled,PartitionScheme=custom,FlashMode=dio + esp32s2: + - espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=custom,FlashMode=dio + - espressif:esp32:esp32s2:PSRAM=disabled,PartitionScheme=custom,FlashMode=dio + esp32s3: + - espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=custom,FlashMode=qio + - espressif:esp32:esp32s3:PSRAM=enabled,USBMode=default,PartitionScheme=custom,FlashMode=qio + - espressif:esp32:esp32s3:PSRAM=disabled,USBMode=default,PartitionScheme=custom,FlashMode=qio + +requires: + - CONFIG_CAMERA_TASK_STACK_SIZE=[0-9]+ diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv b/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv new file mode 100644 index 0000000..b9f18c4 --- /dev/null +++ b/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x3c0000, +fr, data, , 0x3d0000, 0x20000, +coredump, data, coredump,0x3f0000, 0x10000, diff --git a/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino b/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino new file mode 100644 index 0000000..89a195b --- /dev/null +++ b/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino @@ -0,0 +1,30 @@ +/* The true ESP32 chip ID is essentially its MAC address. +This sketch provides an alternate chip ID that matches +the output of the ESP.getChipId() function on ESP8266 +(i.e. a 32-bit integer matching the last 3 bytes of +the MAC address. This is less unique than the +MAC address chip ID, but is helpful when you need +an identifier that can be no more than a 32-bit integer +(like for switch...case). + +created 2020-06-07 by cweinhofer +with help from Cicicok */ + +uint32_t chipId = 0; + +void setup() { + Serial.begin(115200); +} + +void loop() { + for (int i = 0; i < 17; i = i + 8) { + chipId |= ((ESP.getEfuseMac() >> (40 - i)) & 0xff) << i; + } + + Serial.printf("ESP32 Chip model = %s Rev %d\n", ESP.getChipModel(), ESP.getChipRevision()); + Serial.printf("This chip has %d cores\n", ESP.getChipCores()); + Serial.print("Chip ID: "); + Serial.println(chipId); + + delay(3000); +} diff --git a/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino new file mode 100644 index 0000000..aed57c4 --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino @@ -0,0 +1,98 @@ +/* + Deep Sleep with External Wake Up + ===================================== + This code displays how to use deep sleep with + an external trigger as a wake up source and how + to store data in RTC memory to use it over reboots + + This code is under Public Domain License. + + Hardware Connections + ====================== + Push Button to GPIO 33 pulled down with a 10K Ohm + resistor + + NOTE: + ====== + Only RTC IO can be used as a source for external wake + source. They are pins: 0,2,4,12-15,25-27,32-39. + + Author: + Pranav Cherukupalli +*/ +#include "driver/rtc_io.h" + +#define BUTTON_PIN_BITMASK(GPIO) (1ULL << GPIO) // 2 ^ GPIO_NUMBER in hex +#define USE_EXT0_WAKEUP 1 // 1 = EXT0 wakeup, 0 = EXT1 wakeup +#define WAKEUP_GPIO GPIO_NUM_33 // Only RTC IO are allowed - ESP32 Pin example +RTC_DATA_ATTR int bootCount = 0; + +/* + Method to print the reason by which ESP32 + has been awaken from sleep +*/ +void print_wakeup_reason() { + esp_sleep_wakeup_cause_t wakeup_reason; + + wakeup_reason = esp_sleep_get_wakeup_cause(); + + switch (wakeup_reason) { + case ESP_SLEEP_WAKEUP_EXT0: Serial.println("Wakeup caused by external signal using RTC_IO"); break; + case ESP_SLEEP_WAKEUP_EXT1: Serial.println("Wakeup caused by external signal using RTC_CNTL"); break; + case ESP_SLEEP_WAKEUP_TIMER: Serial.println("Wakeup caused by timer"); break; + case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break; + case ESP_SLEEP_WAKEUP_ULP: Serial.println("Wakeup caused by ULP program"); break; + default: Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break; + } +} + +void setup() { + Serial.begin(115200); + delay(1000); //Take some time to open up the Serial Monitor + + //Increment boot number and print it every reboot + ++bootCount; + Serial.println("Boot number: " + String(bootCount)); + + //Print the wakeup reason for ESP32 + print_wakeup_reason(); + + /* + First we configure the wake up source + We set our ESP32 to wake up for an external trigger. + There are two types for ESP32, ext0 and ext1 . + ext0 uses RTC_IO to wakeup thus requires RTC peripherals + to be on while ext1 uses RTC Controller so does not need + peripherals to be powered on. + Note that using internal pullups/pulldowns also requires + RTC peripherals to be turned on. + */ +#if USE_EXT0_WAKEUP + esp_sleep_enable_ext0_wakeup(WAKEUP_GPIO, 1); //1 = High, 0 = Low + // Configure pullup/downs via RTCIO to tie wakeup pins to inactive level during deepsleep. + // EXT0 resides in the same power domain (RTC_PERIPH) as the RTC IO pullup/downs. + // No need to keep that power domain explicitly, unlike EXT1. + rtc_gpio_pullup_dis(WAKEUP_GPIO); + rtc_gpio_pulldown_en(WAKEUP_GPIO); + +#else // EXT1 WAKEUP + //If you were to use ext1, you would use it like + esp_sleep_enable_ext1_wakeup_io(BUTTON_PIN_BITMASK(WAKEUP_GPIO), ESP_EXT1_WAKEUP_ANY_HIGH); + /* + If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO + during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will + increase some power consumption. However, if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH + domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep. + */ + rtc_gpio_pulldown_en(WAKEUP_GPIO); // GPIO33 is tie to GND in order to wake up in HIGH + rtc_gpio_pullup_dis(WAKEUP_GPIO); // Disable PULL_UP in order to allow it to wakeup on HIGH +#endif + //Go to sleep now + Serial.println("Going to sleep now"); + esp_deep_sleep_start(); + Serial.println("This will never be printed"); +} + +void loop() { + //This is not going to be called +} diff --git a/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.yml b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.yml new file mode 100644 index 0000000..f0c2d6e --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.yml @@ -0,0 +1,6 @@ +targets: + esp32c3: false + esp32c6: false + esp32h2: false + esp32p4: false + esp32c5: false diff --git a/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino new file mode 100644 index 0000000..73415ca --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino @@ -0,0 +1,161 @@ +/* + This example smothly blinks GPIO_2 using different frequencies changed after Deep Sleep Time + The PWM and control of blink frequency is done by ULP exclusively + This is an example about how to program the ULP using Arduino + It also demonstrates use of RTM MEMORY to persist data and states +*/ + +#include +#include "esp32/ulp.h" +#include "driver/rtc_io.h" +#include "soc/rtc_io_reg.h" + +// RTC Memory used for ULP internal variable and Sketch interfacing +#define RTC_dutyMeter 0 +#define RTC_dir 4 +#define RTC_fadeDelay 12 +// *fadeCycleDelay is used to pass values to ULP and change its behavior +uint32_t *fadeCycleDelay = &RTC_SLOW_MEM[RTC_fadeDelay]; +#define ULP_START_OFFSET 32 + +// For ESP32 Arduino, it is usually at offeset 512, defined in sdkconfig +RTC_DATA_ATTR uint32_t ULP_Started = 0; // 0 or 1 + +//Time-to-Sleep +#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */ +#define TIME_TO_SLEEP 5 /* Time ESP32 will go to sleep (in microseconds); multiplied by above conversion to achieve seconds*/ + +void ulp_setup() { + if (ULP_Started) { + return; + } + *fadeCycleDelay = 5; // 5..200 works fine for a full Fade In + Out cycle + ULP_Started = 1; + + // GPIO2 initialization (set to output and initial value is 0) + const gpio_num_t MeterPWMPin = GPIO_NUM_2; + rtc_gpio_init(MeterPWMPin); + rtc_gpio_set_direction(MeterPWMPin, RTC_GPIO_MODE_OUTPUT_ONLY); + rtc_gpio_set_level(MeterPWMPin, 0); + + // if LED is connected to GPIO2 (specify by +RTC_GPIO_OUT_DATA_S : ESP32 is 14, S2/S3 is 10) + const uint32_t MeterPWMBit = rtc_io_number_get(MeterPWMPin) + RTC_GPIO_OUT_DATA_S; + + enum labels { + INIFINITE_LOOP, + RUN_PWM, + NEXT_PWM_CYCLE, + PWM_ON, + PWM_OFF, + END_PWM_CYCLE, + POSITIVE_DIR, + DEC_DUTY, + INC_DUTY, + }; + + // Define ULP program + const ulp_insn_t ulp_prog[] = { + // Initial Value setup + I_MOVI(R0, 0), // R0 = 0 + I_ST(R0, R0, RTC_dutyMeter), // RTC_SLOW_MEM[RTC_dutyMeter] = 0 + I_MOVI(R1, 1), // R1 = 1 + I_ST(R1, R0, RTC_dir), // RTC_SLOW_MEM[RTC_dir] = 1 + + M_LABEL(INIFINITE_LOOP), // while(1) { + + // run certain PWM Duty for about (RTC_fadeDelay x 100) microseconds + I_MOVI(R3, 0), // R3 = 0 + I_LD(R3, R3, RTC_fadeDelay), // R3 = RTC_SLOW_MEM[RTC_fadeDelay] + M_LABEL(RUN_PWM), // do { // repeat RTC_fadeDelay times: + + // execute about 10KHz PWM on GPIO2 using as duty cycle = RTC_SLOW_MEM[RTC_dutyMeter] + I_MOVI(R0, 0), // R0 = 0 + I_LD(R0, R0, RTC_dutyMeter), // R0 = RTC_SLOW_MEM[RTC_dutyMeter] + M_BL(NEXT_PWM_CYCLE, 1), // if (R0 > 0) turn on LED + I_WR_REG(RTC_GPIO_OUT_W1TS_REG, MeterPWMBit, MeterPWMBit, 1), // W1TS set bit to clear GPIO - GPIO2 on + M_LABEL(PWM_ON), // while (R0 > 0) // repeat RTC_dutyMeter times: + M_BL(NEXT_PWM_CYCLE, 1), // { + //I_DELAY(8), // // 8 is about 1 microsecond based on 8MHz + I_SUBI(R0, R0, 1), // R0 = R0 - 1 + M_BX(PWM_ON), // } + M_LABEL(NEXT_PWM_CYCLE), // // toggle GPIO_2 + I_MOVI(R0, 0), // R0 = 0 + I_LD(R0, R0, RTC_dutyMeter), // R0 = RTC_SLOW_MEM[RTC_dutyMeter] + I_MOVI(R1, 100), // R1 = 100 + I_SUBR(R0, R1, R0), // R0 = 100 - dutyMeter + M_BL(END_PWM_CYCLE, 1), // if (R0 > 0) turn off LED + I_WR_REG(RTC_GPIO_OUT_W1TC_REG, MeterPWMBit, MeterPWMBit, 1), // W1TC set bit to clear GPIO - GPIO2 off + M_LABEL(PWM_OFF), // while (R0 > 0) // repeat (100 - RTC_dutyMeter) times: + M_BL(END_PWM_CYCLE, 1), // { + //I_DELAY(8), // // 8 is about 1us: ULP fetch+execution time + I_SUBI(R0, R0, 1), // R0 = R0 - 1 + M_BX(PWM_OFF), // } + M_LABEL(END_PWM_CYCLE), // + + I_SUBI(R3, R3, 1), // R3 = R3 - 1 // RTC_fadeDelay + I_MOVR(R0, R3), // R0 = R3 // only R0 can be used to compare and branch + M_BGE(RUN_PWM, 1), // } while (R3 > 0) // ESP32 repeatinf RTC_fadeDelay times + + // increase/decrease DutyMeter to apply Fade In/Out loop + I_MOVI(R1, 0), // R1 = 0 + I_LD(R1, R1, RTC_dutyMeter), // R1 = RTC_SLOW_MEM[RTC_dutyMeter] + I_MOVI(R0, 0), // R0 = 0 + I_LD(R0, R0, RTC_dir), // R0 = RTC_SLOW_MEM[RTC_dir] + + M_BGE(POSITIVE_DIR, 1), // if(dir == 0) { // decrease duty by 2 + // Dir is 0, means decrease Duty by 2 + I_MOVR(R0, R1), // R0 = Duty + M_BGE(DEC_DUTY, 1), // if (duty == 0) { // change direction and increase duty + I_MOVI(R3, 0), // R3 = 0 + I_MOVI(R2, 1), // R2 = 1 + I_ST(R2, R3, RTC_dir), // RTC_SLOW_MEM[RTC_dir] = 1 // increasing direction + M_BX(INC_DUTY), // goto "increase Duty" + M_LABEL(DEC_DUTY), // } "decrease Duty": + I_SUBI(R0, R0, 2), // Duty -= 2 + I_MOVI(R2, 0), // R2 = 0 + I_ST(R0, R2, RTC_dutyMeter), // RTC_SLOW_MEM[RTC_dutyMeter] += 2 + M_BX(INIFINITE_LOOP), // } + + M_LABEL(POSITIVE_DIR), // else { // dir == 1 // increase duty by 2 + // Dir is 1, means increase Duty by 2 + I_MOVR(R0, R1), // R0 = Duty + M_BL(INC_DUTY, 100), // if (duty == 100) { // change direction and decrease duty + I_MOVI(R2, 0), // R2 = 0 + I_ST(R2, R2, RTC_dir), // RTC_SLOW_MEM[RTC_dir] = 0 // decreasing direction + M_BX(DEC_DUTY), // goto "decrease Duty" + M_LABEL(INC_DUTY), // } "increase Duty": + I_ADDI(R0, R0, 2), // Duty += 2 + I_MOVI(R2, 0), // R2 = 0 + I_ST(R0, R2, RTC_dutyMeter), // RTC_SLOW_MEM[RTC_dutyMeter] -= 2 + // } // if (dir == 0) + M_BX(INIFINITE_LOOP), // } // while(1) + }; + // Run ULP program + size_t size = sizeof(ulp_prog) / sizeof(ulp_insn_t); + ulp_process_macros_and_load(ULP_START_OFFSET, ulp_prog, &size); + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + ulp_run(ULP_START_OFFSET); +} + +void setup() { + Serial.begin(115200); + + ulp_setup(); // it really only runs on the first ESP32 boot + Serial.printf("\nStarted smooth blink with delay %lu\n", *fadeCycleDelay); + + // *fadeCycleDelay resides in RTC_SLOW_MEM and persists along deep sleep waking up + // it is used as a delay time parameter for smooth blinking, in the ULP processing code + if (*fadeCycleDelay < 195) { + *fadeCycleDelay += 10; + } else { + *fadeCycleDelay = 5; // 5..200 works fine for a full Fade In + Out cycle + } + Serial.println("Entering in Deep Sleep"); + esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR /*/ 4*/); // time set with variable above + esp_deep_sleep_start(); + // From this point on, no code is executed in DEEP SLEEP mode +} + +void loop() { + // It never reaches this code because it enters in Deep Sleep mode at the end of setup() +} diff --git a/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.yml b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.yml new file mode 100644 index 0000000..556ac03 --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.yml @@ -0,0 +1,8 @@ +targets: + esp32c3: false + esp32c6: false + esp32h2: false + esp32p4: false + esp32s2: false + esp32s3: false + esp32c5: false diff --git a/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino new file mode 100644 index 0000000..a6e8855 --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino @@ -0,0 +1,92 @@ +/* +Simple Deep Sleep with Timer Wake Up +===================================== +ESP32 offers a deep sleep mode for effective power +saving as power is an important factor for IoT +applications. In this mode CPUs, most of the RAM, +and all the digital peripherals which are clocked +from APB_CLK are powered off. The only parts of +the chip which can still be powered on are: +RTC controller, RTC peripherals ,and RTC memories + +This code displays the most basic deep sleep with +a timer to wake it up and how to store data in +RTC memory to use it over reboots + +This code is under Public Domain License. + +Author: +Pranav Cherukupalli +*/ + +#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */ +#define TIME_TO_SLEEP 5 /* Time ESP32 will go to sleep (in seconds) */ + +RTC_DATA_ATTR int bootCount = 0; + +/* +Method to print the reason by which ESP32 +has been awaken from sleep +*/ +void print_wakeup_reason() { + esp_sleep_wakeup_cause_t wakeup_reason; + + wakeup_reason = esp_sleep_get_wakeup_cause(); + + switch (wakeup_reason) { + case ESP_SLEEP_WAKEUP_EXT0: Serial.println("Wakeup caused by external signal using RTC_IO"); break; + case ESP_SLEEP_WAKEUP_EXT1: Serial.println("Wakeup caused by external signal using RTC_CNTL"); break; + case ESP_SLEEP_WAKEUP_TIMER: Serial.println("Wakeup caused by timer"); break; + case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break; + case ESP_SLEEP_WAKEUP_ULP: Serial.println("Wakeup caused by ULP program"); break; + default: Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break; + } +} + +void setup() { + Serial.begin(115200); + delay(1000); //Take some time to open up the Serial Monitor + + //Increment boot number and print it every reboot + ++bootCount; + Serial.println("Boot number: " + String(bootCount)); + + //Print the wakeup reason for ESP32 + print_wakeup_reason(); + + /* + First we configure the wake up source + We set our ESP32 to wake up every 5 seconds + */ + esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR); + Serial.println("Setup ESP32 to sleep for every " + String(TIME_TO_SLEEP) + " Seconds"); + + /* + Next we decide what all peripherals to shut down/keep on + By default, ESP32 will automatically power down the peripherals + not needed by the wakeup source, but if you want to be a poweruser + this is for you. Read in detail at the API docs + http://esp-idf.readthedocs.io/en/latest/api-reference/system/deep_sleep.html + Left the line commented as an example of how to configure peripherals. + The line below turns off all RTC peripherals in deep sleep. + */ + //esp_deep_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF); + //Serial.println("Configured all RTC Peripherals to be powered down in sleep"); + + /* + Now that we have setup a wake cause and if needed setup the + peripherals state in deep sleep, we can now start going to + deep sleep. + In the case that no wake up sources were provided but deep + sleep was started, it will sleep forever unless hardware + reset occurs. + */ + Serial.println("Going to sleep now"); + Serial.flush(); + esp_deep_sleep_start(); + Serial.println("This will never be printed"); +} + +void loop() { + //This is not going to be called +} diff --git a/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.yml b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.yml new file mode 100644 index 0000000..f2c7072 --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.yml @@ -0,0 +1,2 @@ +targets: + esp32h2: false diff --git a/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino new file mode 100644 index 0000000..5b1e0e9 --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino @@ -0,0 +1,107 @@ +/* +Deep Sleep with Touch Wake Up +===================================== +This code displays how to use deep sleep with +a touch as a wake up source and how to store data in +RTC memory to use it over reboots + +ESP32 can have multiple touch pads enabled as wakeup source +ESP32-S2 and ESP32-S3 supports only 1 touch pad as wakeup source enabled + +This code is under Public Domain License. + +Author: +Pranav Cherukupalli +*/ + +#if CONFIG_IDF_TARGET_ESP32 +#define THRESHOLD 40 /* Greater the value, more the sensitivity */ +#elif (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3) +#define THRESHOLD 5000 /* Lower the value, more the sensitivity */ +#else // ESP32-P4 + default for other chips (to be adjusted) */ +#define THRESHOLD 500 /* Lower the value, more the sensitivity */ +#endif + +RTC_DATA_ATTR int bootCount = 0; +touch_pad_t touchPin; +/* +Method to print the reason by which ESP32 +has been awaken from sleep +*/ +void print_wakeup_reason() { + esp_sleep_wakeup_cause_t wakeup_reason; + + wakeup_reason = esp_sleep_get_wakeup_cause(); + + switch (wakeup_reason) { + case ESP_SLEEP_WAKEUP_EXT0: Serial.println("Wakeup caused by external signal using RTC_IO"); break; + case ESP_SLEEP_WAKEUP_EXT1: Serial.println("Wakeup caused by external signal using RTC_CNTL"); break; + case ESP_SLEEP_WAKEUP_TIMER: Serial.println("Wakeup caused by timer"); break; + case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break; + case ESP_SLEEP_WAKEUP_ULP: Serial.println("Wakeup caused by ULP program"); break; + default: Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break; + } +} + +/* +Method to print the touchpad by which ESP32 +has been awaken from sleep +*/ +void print_wakeup_touchpad() { + touchPin = (touch_pad_t)esp_sleep_get_touchpad_wakeup_status(); + +#if CONFIG_IDF_TARGET_ESP32 + switch (touchPin) { + case 0: Serial.println("Touch detected on GPIO 4"); break; + case 1: Serial.println("Touch detected on GPIO 0"); break; + case 2: Serial.println("Touch detected on GPIO 2"); break; + case 3: Serial.println("Touch detected on GPIO 15"); break; + case 4: Serial.println("Touch detected on GPIO 13"); break; + case 5: Serial.println("Touch detected on GPIO 12"); break; + case 6: Serial.println("Touch detected on GPIO 14"); break; + case 7: Serial.println("Touch detected on GPIO 27"); break; + case 8: Serial.println("Touch detected on GPIO 33"); break; + case 9: Serial.println("Touch detected on GPIO 32"); break; + default: Serial.println("Wakeup not by touchpad"); break; + } +#else + if (touchPin < TOUCH_PAD_MAX) { + Serial.printf("Touch detected on GPIO %d\n", touchPin); + } else { + Serial.println("Wakeup not by touchpad"); + } +#endif +} + +void setup() { + Serial.begin(115200); + delay(1000); //Take some time to open up the Serial Monitor + + //Increment boot number and print it every reboot + ++bootCount; + Serial.println("Boot number: " + String(bootCount)); + + //Print the wakeup reason for ESP32 and touchpad too + print_wakeup_reason(); + print_wakeup_touchpad(); + +#if CONFIG_IDF_TARGET_ESP32 + //Setup sleep wakeup on Touch Pad 3 + 7 (GPIO15 + GPIO 27) + touchSleepWakeUpEnable(T3, THRESHOLD); + touchSleepWakeUpEnable(T7, THRESHOLD); + +#else //ESP32-S2 + ESP32-S3 + ESP32-P4 + //Setup sleep wakeup on Touch Pad 3 (GPIO3) + touchSleepWakeUpEnable(T3, THRESHOLD); + +#endif + + //Go to sleep now + Serial.println("Going to sleep now"); + esp_deep_sleep_start(); + Serial.println("This will never be printed"); +} + +void loop() { + //This will never be reached +} diff --git a/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.yml b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.yml new file mode 100644 index 0000000..dc765ea --- /dev/null +++ b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.yml @@ -0,0 +1,5 @@ +targets: + esp32c3: false + esp32c6: false + esp32h2: false + esp32c5: false diff --git a/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino new file mode 100644 index 0000000..8704568 --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino @@ -0,0 +1,122 @@ +/* Basic Multi Threading Arduino Example + This example code is in the Public Domain (or CC0 licensed, at your option.) + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +// Please read file README.md in the folder containing this example. + +#if CONFIG_FREERTOS_UNICORE +#define TASK_RUNNING_CORE 0 +#else +#define TASK_RUNNING_CORE 1 +#endif + +#define ANALOG_INPUT_PIN A0 + +#ifndef LED_BUILTIN +#define LED_BUILTIN 13 // Specify the on which is your LED +#endif + +// Define two tasks for Blink & AnalogRead. +void TaskBlink(void *pvParameters); +void TaskAnalogRead(void *pvParameters); +TaskHandle_t analog_read_task_handle; // You can (don't have to) use this to be able to manipulate a task from somewhere else. + +// The setup function runs once when you press reset or power on the board. +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + // Set up two tasks to run independently. + uint32_t blink_delay = 1000; // Delay between changing state on LED pin + xTaskCreate( + TaskBlink, "Task Blink" // A name just for humans + , + 2048 // The stack size can be checked by calling `uxHighWaterMark = uxTaskGetStackHighWaterMark(NULL);` + , + (void *)&blink_delay // Task parameter which can modify the task behavior. This must be passed as pointer to void. + , + 2 // Priority + , + NULL // Task handle is not used here - simply pass NULL + ); + + // This variant of task creation can also specify on which core it will be run (only relevant for multi-core ESPs) + xTaskCreatePinnedToCore( + TaskAnalogRead, "Analog Read", 2048 // Stack size + , + NULL // When no parameter is used, simply pass NULL + , + 1 // Priority + , + &analog_read_task_handle // With task handle we will be able to manipulate with this task. + , + TASK_RUNNING_CORE // Core on which the task will run + ); + + Serial.printf("Basic Multi Threading Arduino Example\n"); + // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started. +} + +void loop() { + if (analog_read_task_handle != NULL) { // Make sure that the task actually exists + delay(10000); + vTaskDelete(analog_read_task_handle); // Delete task + analog_read_task_handle = NULL; // prevent calling vTaskDelete on non-existing task + } +} + +/*--------------------------------------------------*/ +/*---------------------- Tasks ---------------------*/ +/*--------------------------------------------------*/ + +void TaskBlink(void *pvParameters) { // This is a task. + uint32_t blink_delay = *((uint32_t *)pvParameters); + + /* + Blink + Turns on an LED on for one second, then off for one second, repeatedly. + + If you want to know what pin the on-board LED is connected to on your ESP32 model, check + the Technical Specs of your board. +*/ + + // initialize digital LED_BUILTIN on pin 13 as an output. + pinMode(LED_BUILTIN, OUTPUT); + + for (;;) { // A Task shall never return or exit. + digitalWrite(LED_BUILTIN, HIGH); // turn the LED on (HIGH is the voltage level) + // arduino-esp32 has FreeRTOS configured to have a tick-rate of 1000Hz and portTICK_PERIOD_MS + // refers to how many milliseconds the period between each ticks is, ie. 1ms. + delay(blink_delay); + digitalWrite(LED_BUILTIN, LOW); // turn the LED off by making the voltage LOW + delay(blink_delay); + } +} + +void TaskAnalogRead(void *pvParameters) { // This is a task. + (void)pvParameters; + // Check if the given analog pin is usable - if not - delete this task + if (digitalPinToAnalogChannel(ANALOG_INPUT_PIN) == -1) { + Serial.printf("TaskAnalogRead cannot work because the given pin %d cannot be used for ADC - the task will delete itself.\n", ANALOG_INPUT_PIN); + analog_read_task_handle = NULL; // Prevent calling vTaskDelete on non-existing task + vTaskDelete(NULL); // Delete this task + } + + /* + AnalogReadSerial + Reads an analog input on pin A3, prints the result to the serial monitor. + Graphical representation is available using serial plotter (Tools > Serial Plotter menu) + Attach the center pin of a potentiometer to pin A3, and the outside pins to +5V and ground. + + This example code is in the public domain. +*/ + + for (;;) { + // read the input on analog pin: + int sensorValue = analogRead(ANALOG_INPUT_PIN); + // print out the value you read: + Serial.println(sensorValue); + delay(100); // 100ms delay + } +} diff --git a/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md new file mode 100644 index 0000000..f48e352 --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md @@ -0,0 +1,85 @@ +# Basic Multi Threading Example + +This example demonstrates the basic usage of FreeRTOS Tasks for multi threading. + +Please refer to other examples in this folder to better utilize their full potential and safeguard potential problems. +It is also advised to read the documentation on FreeRTOS web pages: +[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html) + +This example will blink the built-in LED and read analog data. +Additionally, this example demonstrates the usage of the task handle, simply by deleting the analog +read task after 10 seconds from the main loop by calling the function `vTaskDelete`. + +### Theory: +A task is simply a function that runs when the operating system (FreeeRTOS) sees fit. +This task can have an infinite loop inside if you want to do some work periodically for the entirety of the program run. +This, however, can create a problem - no other task will ever run and also the Watch Dog will trigger and your program will restart. +A nice behaving tasks know when it is useless to keep the processor for itself and give it away for other tasks to be used. +This can be achieved in many ways, but the simplest is called `delay(`milliseconds)`. +During that delay, any other task may run and do its job. +When the delay runs out the Operating System gives the processor the task which can continue. +For other ways to yield the CPU in a task please see other examples in this folder. +It is also worth mentioning that two or more tasks running the same function will run them with separate stacks, so if you want to run the same code (which could be differentiated by the argument) there is no need to have multiple copies of the same function. + +**Task creation has a few parameters you should understand:** +``` + xTaskCreate(TaskFunction_t pxTaskCode, + const char * const pcName, + const uint16_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) +``` + - **pxTaskCode** is the name of your function which will run as a task + - **pcName** is a string of human-readable descriptions for your task + - **usStackDepth** is the number of words (word = 4 B) available to the task. If you see an error similar to this "Debug exception reason: Stack canary watchpoint triggered (Task Blink)" you should increase it + - **pvParameters** is a parameter that will be passed to the task function - it must be explicitly converted to (void*) and in your function explicitly converted back to the intended data type. + - **uxPriority** is a number from 0 to configMAX_PRIORITIES which determines how the FreeRTOS will allow the tasks to run. 0 is the lowest priority. + - **pxCreatedTask** task handle is a pointer to the task which allows you to manipulate the task - delete it, suspend and resume. + If you don't need to do anything special with your task, simply pass NULL for this parameter. + You can read more about task control here: https://www.freertos.org/a00112.html + +# Supported Targets + +This example supports all SoCs. + +### Hardware Connection + +If your board does not have a built-in LED, please connect one to the pin specified by the `LED_BUILTIN` in the code (you can also change the number and connect it to the pin you desire). + +Optionally you can connect the analog element to the pin. such as a variable resistor, analog input such as an audio signal, or any signal generator. However, if the pin is left unconnected it will receive background noise and you will also see a change in the signal when the pin is touched by a finger. +Please refer to the ESP-IDF ADC documentation for specific SoC for info on which pins are available: +[ESP32](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32/api-reference/peripherals/adc.html), + [ESP32-S2](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32s2/api-reference/peripherals/adc.html), + [ESP32-S3](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32s3/api-reference/peripherals/adc.html), + [ESP32-C3](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32c3/api-reference/peripherals/adc.html) + + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino b/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino new file mode 100644 index 0000000..9c90571 --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino @@ -0,0 +1,102 @@ +/* Basic Multi Threading Arduino Example + This example code is in the Public Domain (or CC0 licensed, at your option.) + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +// Please read file README.md in the folder containing this example. + +#define USE_MUTEX +int shared_variable = 0; +SemaphoreHandle_t shared_var_mutex = NULL; + +// Define a task function +void Task(void *pvParameters); + +// The setup function runs once when you press reset or power on the board. +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + Serial.printf(" Task 0 | Task 1\n"); + +#ifdef USE_MUTEX + shared_var_mutex = xSemaphoreCreateMutex(); // Create the mutex +#endif + + // Set up two tasks to run the same function independently. + static int task_number0 = 0; + xTaskCreate( + Task, "Task 0" // A name just for humans + , + 2048 // The stack size + , + (void *)&task_number0 // Pass reference to a variable describing the task number + //, 5 // High priority + , + 1 // priority + , + NULL // Task handle is not used here - simply pass NULL + ); + + static int task_number1 = 1; + xTaskCreate( + Task, "Task 1", 2048 // Stack size + , + (void *)&task_number1 // Pass reference to a variable describing the task number + , + 1 // Low priority + , + NULL // Task handle is not used here - simply pass NULL + ); + + // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started. +} + +void loop() {} + +/*--------------------------------------------------*/ +/*---------------------- Tasks ---------------------*/ +/*--------------------------------------------------*/ + +void Task(void *pvParameters) { // This is a task. + int task_num = *((int *)pvParameters); + Serial.printf("%s\n", task_num ? " Starting |" : " | Starting"); + for (;;) { // A Task shall never return or exit. +#ifdef USE_MUTEX + if (shared_var_mutex != NULL) { // Sanity check if the mutex exists + // Try to take the mutex and wait indefinitely if needed + if (xSemaphoreTake(shared_var_mutex, portMAX_DELAY) == pdTRUE) { + // Mutex successfully taken +#endif + int new_value = random(1000); + + char str0[35]; // Maximum possible length of the string + snprintf(str0, sizeof(str0), " %d <- %d |", shared_variable, new_value); + char str1[46]; // Maximum possible length of the string + snprintf(str1, sizeof(str1), " | %d <- %d", shared_variable, new_value); + Serial.printf("%s\n", task_num ? str0 : str1); + + shared_variable = new_value; + delay(random(100)); // wait random time of max 100 ms - simulating some computation + + snprintf(str0, sizeof(str0), " R: %d |", shared_variable); + snprintf(str1, sizeof(str1), " | R: %d", shared_variable); + Serial.printf("%s\n", task_num ? str0 : str1); + //Serial.printf("Task %d after write: reading %d\n", task_num, shared_variable); + + if (shared_variable != new_value) { + Serial.printf("%s\n", task_num ? " Mismatch! |" : " | Mismatch!"); + //Serial.printf("Task %d: detected race condition - the value changed!\n", task_num); + } + +#ifdef USE_MUTEX + xSemaphoreGive(shared_var_mutex); // After accessing the shared resource give the mutex and allow other processes to access it + } else { + // We could not obtain the semaphore and can therefore not access the shared resource safely. + } // mutex take + } // sanity check +#endif + delay(10); // Allow other task to be scheduled + } // Infinite loop +} diff --git a/libraries/ESP32/examples/FreeRTOS/Mutex/README.md b/libraries/ESP32/examples/FreeRTOS/Mutex/README.md new file mode 100644 index 0000000..435528b --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Mutex/README.md @@ -0,0 +1,117 @@ +# Mutex Example + +This example demonstrates the basic usage of FreeRTOS Mutually Exclusive Locks (Mutex) for securing access to shared resources in multi-threading. +Please refer to other examples in this folder to better understand the usage of tasks. +It is also advised to read the documentation on FreeRTOS web pages: +https://www.freertos.org/a00106.html + +This example creates 2 tasks with the same implementation - they write into a shared variable and then read it and check if it is the same as what they have written. +In single-thread programming like on Arduino this is of no concern and will be always ok, however when multi-threading is used the execution of the task is switched by the FreeRTOS and the value can be rewritten from another task before reading again. +The tasks print write and read operation - each in their column for better reading. Task 0 is on the left and Task 1 is on the right. +Watch the writes and read in secure mode when using the mutex (default) as the results are as you would expect them. +Then try to comment the USE_MUTEX and watch again - there will be a lot of mismatches! + +### Theory: +Mutex is a specialized version of Semaphore (please see the Semaphore example for more info). +In essence, the mutex is a variable whose value determines if the mute is taken (locked) or given (unlocked). +When two or more processes access the same resource (variable, peripheral, etc) it might happen, for example, that when one task starts to read a variable and the operating system (FreeRTOS) will schedule the execution of another task +which will write to this variable and when the previous task runs again it will read something different. + +Mutexes and binary semaphores are very similar but have some subtle differences: +Mutexes include a priority inheritance mechanism, whereas binary semaphores do not. +This makes binary semaphores the better choice for implementing synchronization (between tasks or between tasks and an interrupt), and mutexes the better +choice for implementing simple mutual exclusion. +What is priority inheritance? +If a low-priority task holds the Mutex but gets interrupted by a Higher priority task, which +then tries to take the Mutex, the low-priority task will temporarily ‘inherit’ the high priority so a middle-priority task can't block the low-priority task, and thus also block the high priority task. +Semaphores don't have the logic to handle this, in part because Semaphores aren't 'owned' by the task that takes them. + +A mutex can also be recursive - if a task that holds the mutex takes it again, it will succeed, and the mutex will be released +for other tasks only when it is given the same number of times that it was taken. + +You can check the danger by commenting on the definition of USE_MUTEX which will disable the mutex and present the danger of concurrent access. + + +# Supported Targets + +This example supports all ESP32 SoCs. + +## How to Use Example + +Flash and observe the serial output. + +Comment the `USE_MUTEX` definition, save and flash again and observe the behavior of unprotected access to the shared variable. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example Log Output + +The expected output of shared variables protected by mutex demonstrates mutually exclusive access from tasks - they do not interrupt each other and do not rewrite the value before the other task has read it back. + +``` + Task 0 | Task 1 + | Starting + | 0 <- 227 + Starting | + | R: 227 + 227 <- 737 | + R: 737 | + | 737 <- 282 + | R: 282 + 282 <- 267 | +``` + +The output of unprotected access to shared variable - it happens often that a task is interrupted after writing and before reading the other task write a different value - a corruption occurred! + +``` + Task 0 | Task 1 + | Starting + | 0 <- 333 + Starting | + 333 <- 620 | + R: 620 | + 620 <- 244 | + | R: 244 + | Mismatch! + | 244 <- 131 + R: 131 | + Mismatch! | + 131 <- 584 | + | R: 584 + | Mismatch! + | 584 <- 134 + | R: 134 + | 134 <- 554 + R: 554 | + Mismatch! | + 554 <- 313 | +``` + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino b/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino new file mode 100644 index 0000000..1ddecea --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino @@ -0,0 +1,129 @@ +/* Basic Multi Threading Arduino Example + This example code is in the Public Domain (or CC0 licensed, at your option.) + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +// Please read file README.md in the folder containing this example./* + +#define MAX_LINE_LENGTH (64) + +// Define two tasks for reading and writing from and to the serial port. +void TaskWriteToSerial(void *pvParameters); +void TaskReadFromSerial(void *pvParameters); + +// Define Queue handle +QueueHandle_t QueueHandle; +const int QueueElementSize = 10; +typedef struct { + char line[MAX_LINE_LENGTH]; + uint8_t line_length; +} message_t; + +// The setup function runs once when you press reset or power on the board. +void setup() { + // Initialize serial communication at 115200 bits per second: + Serial.begin(115200); + + // Create the queue which will have number of elements, each of size `message_t` and pass the address to . + QueueHandle = xQueueCreate(QueueElementSize, sizeof(message_t)); + + // Check if the queue was successfully created + if (QueueHandle == NULL) { + Serial.println("Queue could not be created. Halt."); + while (1) { + delay(1000); // Halt at this point as is not possible to continue + } + } + + // Set up two tasks to run independently. + xTaskCreate( + TaskWriteToSerial, "Task Write To Serial" // A name just for humans + , + 2048 // The stack size can be checked by calling `uxHighWaterMark = uxTaskGetStackHighWaterMark(NULL);` + , + NULL // No parameter is used + , + 2 // Priority, with 3 (configMAX_PRIORITIES - 1) being the highest, and 0 being the lowest. + , + NULL // Task handle is not used here + ); + + xTaskCreate( + TaskReadFromSerial, "Task Read From Serial", 2048 // Stack size + , + NULL // No parameter is used + , + 1 // Priority + , + NULL // Task handle is not used here + ); + + // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started. + Serial.printf( + "\nAnything you write will return as echo.\nMaximum line length is %d characters (+ terminating '0').\nAnything longer will be sent as a separate " + "line.\n\n", + MAX_LINE_LENGTH - 1 + ); +} + +void loop() { + // Loop is free to do any other work + + delay(1000); // While not being used yield the CPU to other tasks +} + +/*--------------------------------------------------*/ +/*---------------------- Tasks ---------------------*/ +/*--------------------------------------------------*/ + +void TaskWriteToSerial(void *pvParameters) { // This is a task. + message_t message; + for (;;) { // A Task shall never return or exit. + // One approach would be to poll the function (uxQueueMessagesWaiting(QueueHandle) and call delay if nothing is waiting. + // The other approach is to use infinite time to wait defined by constant `portMAX_DELAY`: + if (QueueHandle != NULL) { // Sanity check just to make sure the queue actually exists + int ret = xQueueReceive(QueueHandle, &message, portMAX_DELAY); + if (ret == pdPASS) { + // The message was successfully received - send it back to Serial port and "Echo: " + Serial.printf("Echo line of size %d: \"%s\"\n", message.line_length, message.line); + // The item is queued by copy, not by reference, so lets free the buffer after use. + } else if (ret == pdFALSE) { + Serial.println("The `TaskWriteToSerial` was unable to receive data from the Queue"); + } + } // Sanity check + } // Infinite loop +} + +void TaskReadFromSerial(void *pvParameters) { // This is a task. + message_t message; + for (;;) { + // Check if any data are waiting in the Serial buffer + message.line_length = Serial.available(); + if (message.line_length > 0) { + // Check if the queue exists AND if there is any free space in the queue + if (QueueHandle != NULL && uxQueueSpacesAvailable(QueueHandle) > 0) { + int max_length = message.line_length < MAX_LINE_LENGTH ? message.line_length : MAX_LINE_LENGTH - 1; + for (int i = 0; i < max_length; ++i) { + message.line[i] = Serial.read(); + } + message.line_length = max_length; + message.line[message.line_length] = 0; // Add the terminating nul char + + // The line needs to be passed as pointer to void. + // The last parameter states how many milliseconds should wait (keep trying to send) if is not possible to send right away. + // When the wait parameter is 0 it will not wait and if the send is not possible the function will return errQUEUE_FULL + int ret = xQueueSend(QueueHandle, (void *)&message, 0); + if (ret == pdTRUE) { + // The message was successfully sent. + } else if (ret == errQUEUE_FULL) { + // Since we are checking uxQueueSpacesAvailable this should not occur, however if more than one task should + // write into the same queue it can fill-up between the test and actual send attempt + Serial.println("The `TaskReadFromSerial` was unable to send data into the Queue"); + } // Queue send check + } // Queue sanity check + } else { + delay(100); // Allow other tasks to run when there is nothing to read + } // Serial buffer check + } // Infinite loop +} diff --git a/libraries/ESP32/examples/FreeRTOS/Queue/README.md b/libraries/ESP32/examples/FreeRTOS/Queue/README.md new file mode 100644 index 0000000..e81d674 --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Queue/README.md @@ -0,0 +1,71 @@ +# Queue Example + +This example demonstrates the basic usage of FreeRTOS Queues which enables tasks to pass data between each other in a secure asynchronous way. +Please refer to other examples in this folder to better understand the usage of tasks. +It is also advised to read the documentation on FreeRTOS web pages: +[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html) + +This example reads data received on the serial port (sent by the user) pass it via queue to another task which will send it back on Serial Output. + +### Theory: +A queue is a simple-to-use data structure (in the most basic way) controlled by `xQueueSend` and `xQueueReceive` functions. +Usually, one task writes into the queue and the other task reads from it. +Usage of queues enables the reading task to yield the CPU until there are data in the queue and therefore not waste precious computation time. + +# Supported Targets + +This example supports all ESP32 SoCs. + +## How to Use Example + +Flash and write anything to serial input. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example Log Output + +``` +Anything you write will return as echo. +Maximum line length is 63 characters (+ terminating '0'). +Anything longer will be sent as a separate line. + +``` +< Input text "Short input" + +``Echo line of size 11: "Short input"`` + +< Input text "An example of very long input which is longer than default 63 characters will be split." + +``` +Echo line of size 63: "An example of very long input which is longer than default 63 c" +Echo line of size 24: "haracters will be split." +``` + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md b/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md new file mode 100644 index 0000000..fcb38ee --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md @@ -0,0 +1,77 @@ +# Semaphore Example + +This example demonstrates the basic usage of FreeRTOS Semaphores and queue sets for coordination between tasks for multi-threading. +Please refer to other examples in this folder to better understand the usage of tasks. +It is also advised to read the documentation on FreeRTOS web pages: +[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html) + +### Theory: +Semaphore is in essence a variable. Tasks can set the value, wait until one or more +semaphores are set and thus communicate between each other their state. +A binary semaphore is a semaphore that has a maximum count of 1, hence the 'binary' name. +A task can only 'take' the semaphore if it is available, and the semaphore is only available if its count is 1. + +Semaphores can be controlled by any number of tasks. If you use semaphore as a one-way +signalization with only one task giving and only one task taking there is a much faster option +called Task Notifications - please see FreeRTOS documentation and read more about them: [https://www.freertos.org/RTOS-task-notifications.html](https://www.freertos.org/RTOS-task-notifications.html) + +This example uses a semaphore to signal when a package is delivered to a warehouse by multiple +delivery trucks, and multiple workers are waiting to receive the package. + +# Supported Targets + +This example supports all ESP32 SoCs. + +## How to Use Example + +Read the code and try to understand it, then flash and observe the Serial output. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example Log Output + +``` +Anything you write will return as echo. +Maximum line length is 63 characters (+ terminating '0'). +Anything longer will be sent as a separate line. + +``` +< Input text "Short input" + +``Echo line of size 11: "Short input"`` + +< Input text "An example of very long input which is longer than default 63 characters will be split." + +``` +Echo line of size 63: "An example of very long input which is longer than default 63 c" +Echo line of size 24: "haracters will be split." +``` + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino b/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino new file mode 100644 index 0000000..077d203 --- /dev/null +++ b/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino @@ -0,0 +1,56 @@ +/* Basic Multi Threading Arduino Example + This example code is in the Public Domain (or CC0 licensed, at your option.) + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +// Please read file README.md in the folder containing this example. + +#include + +SemaphoreHandle_t package_delivered_semaphore; + +void delivery_truck_task(void *pvParameters) { + int truck_number = (int)pvParameters; + while (1) { + // Wait for a package to be delivered + // ... + // Notify the warehouse that a package has been delivered + xSemaphoreGive(package_delivered_semaphore); + Serial.printf("Package delivered by truck: %d\n", truck_number); + //wait for some time + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +} + +void warehouse_worker_task(void *pvParameters) { + int worker_number = (int)pvParameters; + while (1) { + // Wait for a package to be delivered + xSemaphoreTake(package_delivered_semaphore, portMAX_DELAY); + Serial.printf("Package received by worker: %d\n", worker_number); + // Receive the package + // ... + } +} + +void setup() { + Serial.begin(115200); + + // Create the semaphore + package_delivered_semaphore = xSemaphoreCreateCounting(10, 0); + + // Create multiple delivery truck tasks + for (int i = 0; i < 5; i++) { + xTaskCreate(delivery_truck_task, "Delivery Truck", 2048, (void *)i, tskIDLE_PRIORITY, NULL); + } + + // Create multiple warehouse worker tasks + for (int i = 0; i < 3; i++) { + xTaskCreate(warehouse_worker_task, "Warehouse Worker", 2048, (void *)i, tskIDLE_PRIORITY, NULL); + } +} + +void loop() { + // Empty loop +} diff --git a/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino b/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino new file mode 100644 index 0000000..9544ce7 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino @@ -0,0 +1,39 @@ +/* + BlinkRGB + + Demonstrates usage of onboard RGB LED on some ESP dev boards. + + Calling digitalWrite(RGB_BUILTIN, HIGH) will use hidden RGB driver. + + RGBLedWrite demonstrates control of each channel: + void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val) + + WARNING: After using digitalWrite to drive RGB LED it will be impossible to drive the same pin + with normal HIGH/LOW level +*/ +//#define RGB_BRIGHTNESS 64 // Change white brightness (max 255) + +// the setup function runs once when you press reset or power the board + +void setup() { + // No need to initialize the RGB LED +} + +// the loop function runs over and over again forever +void loop() { +#ifdef RGB_BUILTIN + digitalWrite(RGB_BUILTIN, HIGH); // Turn the RGB LED white + delay(1000); + digitalWrite(RGB_BUILTIN, LOW); // Turn the RGB LED off + delay(1000); + + rgbLedWrite(RGB_BUILTIN, RGB_BRIGHTNESS, 0, 0); // Red + delay(1000); + rgbLedWrite(RGB_BUILTIN, 0, RGB_BRIGHTNESS, 0); // Green + delay(1000); + rgbLedWrite(RGB_BUILTIN, 0, 0, RGB_BRIGHTNESS); // Blue + delay(1000); + rgbLedWrite(RGB_BUILTIN, 0, 0, 0); // Off / black + delay(1000); +#endif +} diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino b/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino new file mode 100644 index 0000000..a38c6e6 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino @@ -0,0 +1,69 @@ +/* + * This example demonstrates usage of interrupt by detecting a button press. + * + * Setup: Connect first button between pin defined in BUTTON1 and GND + * Similarly connect second button between pin defined in BUTTON2 and GND. + * If you do not have a button simply connect a wire to those buttons + * - touching GND pin with other end of the wire will behave same as pressing the connected button. + * Wen using the bare wire be careful not to touch any other pin by accident. + * + * Note: There is no de-bounce implemented and the physical connection will normally + * trigger many more button presses than actually happened. + * This is completely normal and is not to be considered a fault. + */ + +#include +#include + +#define BUTTON1 16 +#define BUTTON2 17 + +class Button { +public: + Button(uint8_t reqPin) : PIN(reqPin) { + pinMode(PIN, INPUT_PULLUP); + }; + + void begin() { + attachInterrupt(PIN, std::bind(&Button::isr, this), FALLING); + Serial.printf("Started button interrupt on pin %d\n", PIN); + } + + ~Button() { + detachInterrupt(PIN); + } + + void ARDUINO_ISR_ATTR isr() { + numberKeyPresses = numberKeyPresses + 1; + pressed = true; + } + + void checkPressed() { + if (pressed) { + Serial.printf("Button on pin %u has been pressed %lu times\n", PIN, numberKeyPresses); + pressed = false; + } + } + +private: + const uint8_t PIN; + volatile uint32_t numberKeyPresses; + volatile bool pressed; +}; + +Button button1(BUTTON1); +Button button2(BUTTON2); + +void setup() { + Serial.begin(115200); + + Serial.println("Starting Functional Interrupt example."); + button1.begin(); + button2.begin(); + Serial.println("Setup done."); +} + +void loop() { + button1.checkPressed(); + button2.checkPressed(); +} diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/FunctionalInterruptLambda.ino b/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/FunctionalInterruptLambda.ino new file mode 100644 index 0000000..57d3538 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/FunctionalInterruptLambda.ino @@ -0,0 +1,157 @@ +/* + SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + ESP32 Lambda FunctionalInterrupt Example + ======================================== + + This example demonstrates how to use lambda functions with FunctionalInterrupt + for GPIO pin interrupt callbacks on ESP32. It shows CHANGE mode detection + with LED toggle functionality and proper debouncing. + + Hardware Setup: + - Use BOOT Button or connect a button between BUTTON_PIN and GND (with internal pullup) + - Use Builtin Board LED or connect an LED with resistor to GPIO 2 (LED_PIN) + + Features Demonstrated: + 1. CHANGE mode lambda to detect both RISING and FALLING edges + 2. LED toggle on button press (FALLING edge) + 3. Edge type detection using digitalRead() within ISR + 4. Hardware debouncing with configurable timeout + + IMPORTANT NOTE ABOUT ESP32 INTERRUPT BEHAVIOR: + - Only ONE interrupt handler can be attached per GPIO pin at a time + - Calling attachInterrupt() on a pin that already has an interrupt will override the previous one + - This applies regardless of edge type (RISING, FALLING, CHANGE) + - If you need both RISING and FALLING detection on the same pin, use CHANGE mode + and determine the edge type within your handler by reading the pin state +*/ + +#include +#include + +// Pin definitions +#define BUTTON_PIN BOOT_PIN // BOOT BUTTON - change as needed +#ifdef LED_BUILTIN +#define LED_PIN LED_BUILTIN +#else +#warning Using LED_PIN = GPIO 2 as default - change as needed +#define LED_PIN 2 // change as needed +#endif + +// Global variables for interrupt handling (volatile for ISR safety) +volatile uint32_t buttonPressCount = 0; +volatile uint32_t buttonReleaseCount = 0; +volatile bool buttonPressed = false; +volatile bool buttonReleased = false; +volatile bool ledState = false; +volatile bool ledStateChanged = false; // Flag to indicate LED needs updating + +// Debouncing variables (volatile for ISR safety) +volatile unsigned long lastButtonInterruptTime = 0; +const unsigned long DEBOUNCE_DELAY_MS = 50; // 50ms debounce delay + +// State-based debouncing to prevent hysteresis issues +volatile bool lastButtonState = HIGH; // Track last stable state (HIGH = released) + +// Global lambda function (declared at file scope) - ISR in IRAM +IRAM_ATTR std::function changeModeLambda = []() { + // Simple debouncing: check if enough time has passed since last interrupt + unsigned long currentTime = millis(); + if (currentTime - lastButtonInterruptTime < DEBOUNCE_DELAY_MS) { + return; // Ignore this interrupt due to bouncing + } + + // Read current pin state to determine edge type + bool currentState = digitalRead(BUTTON_PIN); + + // State-based debouncing: only process if state actually changed + if (currentState == lastButtonState) { + return; // No real state change, ignore (hysteresis/noise) + } + + // Update timing and state + lastButtonInterruptTime = currentTime; + lastButtonState = currentState; + + if (currentState == LOW) { + // FALLING edge detected (button pressed) - set flag for main loop + // volatile variables require use of temporary value transfer + uint32_t temp = buttonPressCount + 1; + buttonPressCount = temp; + buttonPressed = true; + ledStateChanged = true; // Signal main loop to toggle LED + } else { + // RISING edge detected (button released) - set flag for main loop + // volatile variables require use of temporary value transfer + uint32_t temp = buttonReleaseCount + 1; + buttonReleaseCount = temp; + buttonReleased = true; + } +}; + +void setup() { + Serial.begin(115200); + delay(1000); // Allow serial monitor to connect + + Serial.println("ESP32 Lambda FunctionalInterrupt Example"); + Serial.println("========================================"); + + // Configure pins + pinMode(BUTTON_PIN, INPUT_PULLUP); + pinMode(LED_PIN, OUTPUT); + digitalWrite(LED_PIN, LOW); + + // CHANGE mode lambda to handle both RISING and FALLING edges + // This toggles the LED on button press (FALLING edge) + Serial.println("Setting up CHANGE mode lambda for LED toggle"); + + // Use the global lambda function + attachInterrupt(BUTTON_PIN, changeModeLambda, CHANGE); + + Serial.println(); + Serial.printf("Lambda interrupt configured on Pin %d (CHANGE mode)\r\n", BUTTON_PIN); + Serial.printf("Debounce delay: %lu ms\r\n", DEBOUNCE_DELAY_MS); + Serial.println(); + Serial.println("Press the button to toggle the LED!"); + Serial.println("Button press (FALLING edge) will toggle the LED."); + Serial.println("Button release (RISING edge) will be detected and reported."); + Serial.println("Button includes debouncing to prevent mechanical bounce issues."); + Serial.println(); +} + +void loop() { + // Handle LED state changes (ISR-safe approach) + if (ledStateChanged) { + ledStateChanged = false; + ledState = !ledState; // Toggle LED state in main loop + digitalWrite(LED_PIN, ledState); + } + + // Check for button presses + if (buttonPressed) { + buttonPressed = false; + Serial.printf("==> Button PRESSED! Count: %lu, LED: %s (FALLING edge)\r\n", buttonPressCount, ledState ? "ON" : "OFF"); + } + + // Check for button releases + if (buttonReleased) { + buttonReleased = false; + Serial.printf("==> Button RELEASED! Count: %lu (RISING edge)\r\n", buttonReleaseCount); + } + + delay(10); +} diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/README.md b/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/README.md new file mode 100644 index 0000000..9488c31 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/FunctionalInterruptLambda/README.md @@ -0,0 +1,147 @@ +# ESP32 Lambda FunctionalInterrupt Example + +This example demonstrates how to use lambda functions with FunctionalInterrupt for GPIO pin interrupt callbacks on ESP32. It shows CHANGE mode detection with LED toggle functionality and proper debouncing. + +## Features Demonstrated + +1. **CHANGE mode lambda** to detect both RISING and FALLING edges +2. **LED toggle on button press** (FALLING edge) +3. **Edge type detection** using digitalRead() within ISR +4. **Hardware debouncing** with configurable timeout +5. **IRAM_ATTR lambda declaration** for optimal ISR performance in RAM + +## Hardware Setup + +- Use BOOT Button or connect a button between BUTTON_PIN and GND (with internal pullup) +- Use Builtin Board LED (no special hardware setup) or connect an LED with resistor to GPIO assigned as LED_PIN.\ + Some boards have an RGB LED that needs no special hardware setup to work as a simple white on/off LED. + +``` +ESP32 Board Button/LED +----------- --------- +BOOT_PIN ------------ [BUTTON] ---- GND +LED_PIN --------------- [LED] ----- GND + ¦ + [330O] (*) Only needed when using an external LED attached to the GPIO. + ¦ + 3V3 +``` + +## Important ESP32 Interrupt Behavior + +**CRITICAL:** Only ONE interrupt handler can be attached per GPIO pin at a time on ESP32. + +- Calling `attachInterrupt()` on a pin that already has an interrupt will **override** the previous one +- This applies regardless of edge type (RISING, FALLING, CHANGE) +- If you need both RISING and FALLING detection on the same pin, use **CHANGE mode** and determine the edge type within your handler by reading the pin state + +## Code Overview + +This example demonstrates a simple CHANGE mode lambda interrupt that: + +- **Detects both button press and release** using a single interrupt handler +- **Toggles LED only on button press** (FALLING edge) +- **Reports both press and release events** to Serial output +- **Uses proper debouncing** to prevent switch bounce issues +- **Implements minimal lambda captures** for simplicity + +## Lambda Function Pattern + +### CHANGE Mode Lambda with IRAM Declaration +```cpp +// Global lambda declared with IRAM_ATTR for optimal ISR performance +IRAM_ATTR std::function changeModeLambda = []() { + // Debouncing check + unsigned long currentTime = millis(); + if (currentTime - lastButtonInterruptTime < DEBOUNCE_DELAY_MS) { + return; // Ignore bouncing + } + + // Determine edge type + bool currentState = digitalRead(BUTTON_PIN); + if (currentState == lastButtonState) { + return; // No real state change + } + + // Update state and handle edges + lastButtonInterruptTime = currentTime; + lastButtonState = currentState; + + if (currentState == LOW) { + // Button pressed (FALLING edge) + buttonPressCount++; + buttonPressed = true; + ledStateChanged = true; // Signal LED toggle + } else { + // Button released (RISING edge) + buttonReleaseCount++; + buttonReleased = true; + } +}; + +attachInterrupt(BUTTON_PIN, changeModeLambda, CHANGE); +``` + +## Key Concepts + +### Edge Detection in CHANGE Mode +```cpp +if (digitalRead(pin) == LOW) { + // FALLING edge detected (button pressed) +} else { + // RISING edge detected (button released) +} +``` + +### Debouncing Strategy +This example implements dual-layer debouncing: +1. **Time-based**: Ignores interrupts within 50 ms of previous one +2. **State-based**: Only processes actual state changes + +### Main Loop Processing +```cpp +void loop() { + // Handle LED changes safely outside ISR + if (ledStateChanged) { + ledStateChanged = false; + ledState = !ledState; + digitalWrite(LED_PIN, ledState); + } + + // Report button events + if (buttonPressed) { + // Handle press event + } + if (buttonReleased) { + // Handle release event + } +} +``` + +## Expected Output + +``` +ESP32 Lambda FunctionalInterrupt Example +======================================== +Setting up CHANGE mode lambda for LED toggle + +Lambda interrupt configured on Pin 0 (CHANGE mode) +Debounce delay: 50 ms + +Press the button to toggle the LED! +Button press (FALLING edge) will toggle the LED. +Button release (RISING edge) will be detected and reported. +Button includes debouncing to prevent mechanical bounce issues. + +==> Button PRESSED! Count: 1, LED: ON (FALLING edge) +==> Button RELEASED! Count: 1 (RISING edge) +==> Button PRESSED! Count: 2, LED: OFF (FALLING edge) +==> Button RELEASED! Count: 2 (RISING edge) +``` + +## Pin Configuration + +The example uses these default pins: + +- `BUTTON_PIN`: BOOT_PIN (automatically assigned by the Arduino Core) +- `LED_PIN`: LED_BUILTIN (may not be available for your board - please verify it) diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino b/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino new file mode 100644 index 0000000..1b4d549 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino @@ -0,0 +1,39 @@ +#include + +#define BUTTON1 16 +#define BUTTON2 17 + +struct Button { + uint8_t PIN; + volatile uint32_t numberKeyPresses; + volatile int pressed; +}; + +void isr(void *param) { + struct Button *button = (struct Button *)param; + button->numberKeyPresses = button->numberKeyPresses + 1; + button->pressed = 1; +} + +void checkPressed(struct Button *button) { + if (button->pressed) { + Serial.printf("Button on pin %u has been pressed %lu times\n", button->PIN, button->numberKeyPresses); + button->pressed = 0; + } +} + +struct Button button1 = {BUTTON1, 0, 0}; +struct Button button2 = {BUTTON2, 0, 0}; + +void setup() { + Serial.begin(115200); + pinMode(button1.PIN, INPUT_PULLUP); + pinMode(button2.PIN, INPUT_PULLUP); + attachInterruptArg(button1.PIN, isr, (void *)&button1, FALLING); + attachInterruptArg(button2.PIN, isr, (void *)&button2, FALLING); +} + +void loop() { + checkPressed(&button1); + checkPressed(&button2); +} diff --git a/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino b/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino new file mode 100644 index 0000000..2e94176 --- /dev/null +++ b/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino @@ -0,0 +1,45 @@ +#include + +struct Button { + const uint8_t PIN; + uint32_t numberKeyPresses; + bool pressed; +}; + +Button button1 = {23, 0, false}; +Button button2 = {18, 0, false}; + +void ARDUINO_ISR_ATTR isr(void *arg) { + Button *s = static_cast +


+ +
+

+
+ + + diff --git a/libraries/USB/keywords.txt b/libraries/USB/keywords.txt new file mode 100644 index 0000000..e7ebc8f --- /dev/null +++ b/libraries/USB/keywords.txt @@ -0,0 +1,32 @@ +####################################### +# Syntax Coloring Map +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +USB KEYWORD1 +USBCDC KEYWORD1 +USBMSC KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +onEvent KEYWORD2 +enableReset KEYWORD2 + +vendorID KEYWORD2 +productID KEYWORD2 +productRevision KEYWORD2 +mediaPresent KEYWORD2 +onStartStop KEYWORD2 +onRead KEYWORD2 +onWrite KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/USB/library.properties b/libraries/USB/library.properties new file mode 100644 index 0000000..827ecc2 --- /dev/null +++ b/libraries/USB/library.properties @@ -0,0 +1,9 @@ +name=USB +version=3.3.7 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=ESP32S2 USB Library +paragraph= +category=Communication +url= +architectures=esp32 diff --git a/libraries/USB/src/USBHID.cpp b/libraries/USB/src/USBHID.cpp new file mode 100644 index 0000000..1d5d86f --- /dev/null +++ b/libraries/USB/src/USBHID.cpp @@ -0,0 +1,390 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "esp32-hal-tinyusb.h" +#include "USB.h" +#include "esp_hid_common.h" + +#define USB_HID_DEVICES_MAX 10 + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +typedef struct { + USBHIDDevice *device; + uint8_t reports_num; + uint8_t *report_ids; +} tinyusb_hid_device_t; + +static tinyusb_hid_device_t tinyusb_hid_devices[USB_HID_DEVICES_MAX]; + +static uint8_t tinyusb_hid_devices_num = 0; +static bool tinyusb_hid_devices_is_initialized = false; +static SemaphoreHandle_t tinyusb_hid_device_input_sem = NULL; +static SemaphoreHandle_t tinyusb_hid_device_input_mutex = NULL; + +static bool tinyusb_hid_is_initialized = false; +static hid_interface_protocol_enum_t tinyusb_interface_protocol = HID_ITF_PROTOCOL_NONE; +static uint8_t tinyusb_loaded_hid_devices_num = 0; +static uint16_t tinyusb_hid_device_descriptor_len = 0; +static uint8_t *tinyusb_hid_device_descriptor = NULL; +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG +static const char *tinyusb_hid_device_report_types[4] = {"INVALID", "INPUT", "OUTPUT", "FEATURE"}; +#endif + +static bool tinyusb_enable_hid_device(uint16_t descriptor_len, USBHIDDevice *device) { + if (tinyusb_hid_is_initialized) { + log_e("TinyUSB HID has already started! Device not enabled"); + return false; + } + if (tinyusb_loaded_hid_devices_num >= USB_HID_DEVICES_MAX) { + log_e("Maximum devices already enabled! Device not enabled"); + return false; + } + tinyusb_hid_device_descriptor_len += descriptor_len; + tinyusb_hid_devices[tinyusb_loaded_hid_devices_num++].device = device; + + log_d("Device[%u] len: %u", tinyusb_loaded_hid_devices_num - 1, descriptor_len); + return true; +} + +USBHIDDevice *tinyusb_get_device_by_report_id(uint8_t report_id) { + for (uint8_t i = 0; i < tinyusb_loaded_hid_devices_num; i++) { + tinyusb_hid_device_t *device = &tinyusb_hid_devices[i]; + if (device->device && device->reports_num) { + for (uint8_t r = 0; r < device->reports_num; r++) { + if (report_id == device->report_ids[r]) { + return device->device; + } + } + } + } + return NULL; +} + +static uint16_t tinyusb_on_get_feature(uint8_t report_id, uint8_t *buffer, uint16_t reqlen) { + USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id); + if (device) { + return device->_onGetFeature(report_id, buffer, reqlen); + } + return 0; +} + +static bool tinyusb_on_set_feature(uint8_t report_id, const uint8_t *buffer, uint16_t reqlen) { + USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id); + if (device) { + device->_onSetFeature(report_id, buffer, reqlen); + return true; + } + return false; +} + +static bool tinyusb_on_set_output(uint8_t report_id, const uint8_t *buffer, uint16_t reqlen) { + USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id); + if (device) { + device->_onOutput(report_id, buffer, reqlen); + return true; + } + return false; +} + +static uint16_t tinyusb_on_add_descriptor(uint8_t device_index, uint8_t *dst) { + uint16_t res = 0; + uint8_t report_id = 0, reports_num = 0; + tinyusb_hid_device_t *device = &tinyusb_hid_devices[device_index]; + if (device->device) { + res = device->device->_onGetDescriptor(dst); + if (res) { + + esp_hid_report_map_t *hid_report_map = esp_hid_parse_report_map(dst, res); + if (hid_report_map) { + if (device->report_ids) { + free(device->report_ids); + } + device->reports_num = hid_report_map->reports_len; + device->report_ids = (uint8_t *)malloc(device->reports_num); + memset(device->report_ids, 0, device->reports_num); + reports_num = device->reports_num; + + for (uint8_t i = 0; i < device->reports_num; i++) { + if (hid_report_map->reports[i].protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) { + report_id = hid_report_map->reports[i].report_id; + for (uint8_t r = 0; r < device->reports_num; r++) { + if (!report_id) { + //todo: handle better when device has no report ID set + break; + } else if (report_id == device->report_ids[r]) { + //already added + reports_num--; + break; + } else if (!device->report_ids[r]) { + //empty slot + device->report_ids[r] = report_id; + break; + } + } + } else { + reports_num--; + } + } + device->reports_num = reports_num; + esp_hid_free_report_map(hid_report_map); + } + } + } + return res; +} + +static bool tinyusb_load_enabled_hid_devices() { + if (tinyusb_hid_device_descriptor != NULL) { + return true; + } + tinyusb_hid_device_descriptor = (uint8_t *)malloc(tinyusb_hid_device_descriptor_len); + if (tinyusb_hid_device_descriptor == NULL) { + log_e("HID Descriptor Malloc Failed"); + return false; + } + uint8_t *dst = tinyusb_hid_device_descriptor; + + for (uint8_t i = 0; i < tinyusb_loaded_hid_devices_num; i++) { + uint16_t len = tinyusb_on_add_descriptor(i, dst); + if (!len) { + break; + } else { + dst += len; + } + } + + esp_hid_report_map_t *hid_report_map = esp_hid_parse_report_map(tinyusb_hid_device_descriptor, tinyusb_hid_device_descriptor_len); + if (hid_report_map) { + log_d("Loaded HID Descriptor with the following reports:"); + for (uint8_t i = 0; i < hid_report_map->reports_len; i++) { + if (hid_report_map->reports[i].protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) { + log_d( + " ID: %3u, Type: %7s, Size: %2u, Usage: %8s", hid_report_map->reports[i].report_id, esp_hid_report_type_str(hid_report_map->reports[i].report_type), + hid_report_map->reports[i].value_len, esp_hid_usage_str(hid_report_map->reports[i].usage) + ); + } + } + esp_hid_free_report_map(hid_report_map); + } else { + log_e("Failed to parse the hid report descriptor!"); + return false; + } + + return true; +} + +extern "C" uint16_t tusb_hid_load_descriptor(uint8_t *dst, uint8_t *itf) { + if (tinyusb_hid_is_initialized) { + return 0; + } + tinyusb_hid_is_initialized = true; + + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB HID"); + // For keyboard boot protocol, we've already called tinyusb_enable_interface2(reserve_endpoints=true) + uint8_t ep_in = tinyusb_interface_protocol == HID_ITF_PROTOCOL_KEYBOARD ? 1 : tinyusb_get_free_in_endpoint(); + TU_VERIFY(ep_in != 0); + uint8_t ep_out = tinyusb_interface_protocol == HID_ITF_PROTOCOL_KEYBOARD ? 1 : tinyusb_get_free_out_endpoint(); + TU_VERIFY(ep_out != 0); + uint8_t descriptor[TUD_HID_INOUT_DESC_LEN] = { + // HID Input & Output descriptor + // Interface number, string index, protocol, report descriptor len, EP OUT & IN address, size & polling interval + TUD_HID_INOUT_DESCRIPTOR( + *itf, str_index, tinyusb_interface_protocol, tinyusb_hid_device_descriptor_len, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE, 1 + ) + }; + *itf += 1; + memcpy(dst, descriptor, TUD_HID_INOUT_DESC_LEN); + return TUD_HID_INOUT_DESC_LEN; +} + +// Invoked when received GET HID REPORT DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint8_t const *tud_hid_descriptor_report_cb(uint8_t instance) { + log_v("instance: %u", instance); + if (!tinyusb_load_enabled_hid_devices()) { + return NULL; + } + return tinyusb_hid_device_descriptor; +} + +// Invoked when received SET_PROTOCOL request +// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1) +void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) { + log_v("instance: %u, protocol:%u", instance, protocol); + arduino_usb_hid_event_data_t p; + p.instance = instance; + p.set_protocol.protocol = protocol; + arduino_usb_event_post(ARDUINO_USB_HID_EVENTS, ARDUINO_USB_HID_SET_PROTOCOL_EVENT, &p, sizeof(arduino_usb_hid_event_data_t), portMAX_DELAY); +} + +// Invoked when received SET_IDLE request. return false will stall the request +// - Idle Rate = 0 : only send report if there is changes, i.e skip duplication +// - Idle Rate > 0 : skip duplication, but send at least 1 report every idle rate (in unit of 4 ms). +bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate) { + log_v("instance: %u, idle_rate:%u", instance, idle_rate); + arduino_usb_hid_event_data_t p; + p.instance = instance; + p.set_idle.idle_rate = idle_rate; + arduino_usb_event_post(ARDUINO_USB_HID_EVENTS, ARDUINO_USB_HID_SET_IDLE_EVENT, &p, sizeof(arduino_usb_hid_event_data_t), portMAX_DELAY); + return true; +} + +// Invoked when received GET_REPORT control request +// Application must fill buffer report's content and return its length. +// Return zero will cause the stack to STALL request +uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) { + uint16_t res = tinyusb_on_get_feature(report_id, buffer, reqlen); + if (!res) { + log_d("instance: %u, report_id: %u, report_type: %s, reqlen: %u", instance, report_id, tinyusb_hid_device_report_types[report_type], reqlen); + } + return res; +} + +// Invoked when received SET_REPORT control request or +// received data on OUT endpoint ( Report ID = 0, Type = 0 ) +void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const *buffer, uint16_t bufsize) { + if (!report_id && (!report_type || report_type == HID_REPORT_TYPE_OUTPUT)) { + if (!tinyusb_on_set_output(0, buffer, bufsize) && !tinyusb_on_set_output(buffer[0], buffer + 1, bufsize - 1)) { + log_d( + "instance: %u, report_id: %u, report_type: %s, bufsize: %u", instance, buffer[0], tinyusb_hid_device_report_types[HID_REPORT_TYPE_OUTPUT], bufsize - 1 + ); + } + } else { + if (!tinyusb_on_set_feature(report_id, buffer, bufsize)) { + log_d("instance: %u, report_id: %u, report_type: %s, bufsize: %u", instance, report_id, tinyusb_hid_device_report_types[report_type], bufsize); + } + } +} + +USBHID::USBHID(hid_interface_protocol_enum_t itf_protocol) { + if (!tinyusb_hid_devices_is_initialized) { + tinyusb_hid_devices_is_initialized = true; + for (uint8_t i = 0; i < USB_HID_DEVICES_MAX; i++) { + memset(&tinyusb_hid_devices[i], 0, sizeof(tinyusb_hid_device_t)); + } + tinyusb_hid_devices_num = 0; + tinyusb_interface_protocol = itf_protocol; + tinyusb_enable_interface2(USB_INTERFACE_HID, TUD_HID_INOUT_DESC_LEN, tusb_hid_load_descriptor, itf_protocol == HID_ITF_PROTOCOL_KEYBOARD); + } +} + +void USBHID::begin() { + if (tinyusb_hid_device_input_sem == NULL) { + tinyusb_hid_device_input_sem = xSemaphoreCreateBinary(); + } + if (tinyusb_hid_device_input_mutex == NULL) { + tinyusb_hid_device_input_mutex = xSemaphoreCreateMutex(); + } +} + +void USBHID::end() { + if (tinyusb_hid_device_input_sem != NULL) { + vSemaphoreDelete(tinyusb_hid_device_input_sem); + tinyusb_hid_device_input_sem = NULL; + } + if (tinyusb_hid_device_input_mutex != NULL) { + vSemaphoreDelete(tinyusb_hid_device_input_mutex); + tinyusb_hid_device_input_mutex = NULL; + } +} + +bool USBHID::ready(void) { + return tud_hid_n_ready(0); +} + +// TinyUSB is in the process of changing the type of the last argument to +// tud_hid_report_complete_cb(), so extract the type from the version of TinyUSB that we're +// compiled with. +template struct ArgType; + +template struct ArgType { + typedef T1 type1; + typedef T2 type2; + typedef T3 type3; +}; + +typedef ArgType::type3 tud_hid_report_complete_cb_len_t; + +void tud_hid_report_complete_cb(uint8_t instance, uint8_t const *report, tud_hid_report_complete_cb_len_t len) { + if (tinyusb_hid_device_input_sem) { + xSemaphoreGive(tinyusb_hid_device_input_sem); + } +} + +bool USBHID::SendReport(uint8_t id, const void *data, size_t len, uint32_t timeout_ms) { + if (!tinyusb_hid_device_input_sem || !tinyusb_hid_device_input_mutex) { + log_e("TX Semaphore is NULL. You must call USBHID::begin() before you can send reports"); + return false; + } + + if (xSemaphoreTake(tinyusb_hid_device_input_mutex, timeout_ms / portTICK_PERIOD_MS) != pdTRUE) { + log_e("report %u mutex failed", id); + return false; + } + + // If we're configured to support boot protocol, and the host has requested boot protocol, prevent + // sending of report ID, by passing report ID of 0 to tud_hid_n_report(). + uint8_t effective_id = ((tinyusb_interface_protocol != HID_ITF_PROTOCOL_NONE) && (tud_hid_n_get_protocol(0) == HID_PROTOCOL_BOOT)) ? 0 : id; + + bool res = ready(); + if (!res) { + log_e("not ready"); + } else { + // The semaphore may be given if the last SendReport() timed out waiting for the report to + // be sent. Or, tud_hid_report_complete_cb() may be called an extra time, causing the + // semaphore to be given. In these cases, take the semaphore to clear its state so that + // we can wait for it to be given after calling tud_hid_n_report(). + xSemaphoreTake(tinyusb_hid_device_input_sem, 0); + + res = tud_hid_n_report(0, effective_id, data, len); + if (!res) { + log_e("report %u failed", id); + } else { + if (xSemaphoreTake(tinyusb_hid_device_input_sem, timeout_ms / portTICK_PERIOD_MS) != pdTRUE) { + log_e("report %u wait failed", id); + res = false; + } + } + } + + xSemaphoreGive(tinyusb_hid_device_input_mutex); + return res; +} + +bool USBHID::addDevice(USBHIDDevice *device, uint16_t descriptor_len) { + if (device && tinyusb_loaded_hid_devices_num < USB_HID_DEVICES_MAX) { + if (!tinyusb_enable_hid_device(descriptor_len, device)) { + return false; + } + return true; + } + return false; +} + +void USBHID::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_HID_ANY_EVENT, callback); +} +void USBHID::onEvent(arduino_usb_hid_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_HID_EVENTS, event, callback, this); +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHID.h b/libraries/USB/src/USBHID.h new file mode 100644 index 0000000..3b9f811 --- /dev/null +++ b/libraries/USB/src/USBHID.h @@ -0,0 +1,86 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include +#include +#include "sdkconfig.h" + +#if CONFIG_TINYUSB_HID_ENABLED +#include "esp_event.h" +#include "class/hid/hid.h" +#include "class/hid/hid_device.h" + +// Used by the included TinyUSB drivers +enum { + HID_REPORT_ID_NONE, + HID_REPORT_ID_KEYBOARD, + HID_REPORT_ID_MOUSE, + HID_REPORT_ID_GAMEPAD, + HID_REPORT_ID_CONSUMER_CONTROL, + HID_REPORT_ID_SYSTEM_CONTROL, + HID_REPORT_ID_VENDOR +}; + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_EVENTS); + +typedef enum { + ARDUINO_USB_HID_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_HID_SET_PROTOCOL_EVENT = 0, + ARDUINO_USB_HID_SET_IDLE_EVENT, + ARDUINO_USB_HID_MAX_EVENT, +} arduino_usb_hid_event_t; + +typedef struct { + uint8_t instance; + union { + struct { + uint8_t protocol; + } set_protocol; + struct { + uint8_t idle_rate; + } set_idle; + }; +} arduino_usb_hid_event_data_t; + +class USBHIDDevice { +public: + virtual uint16_t _onGetDescriptor(uint8_t *buffer) { + return 0; + } + virtual uint16_t _onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len) { + return 0; + } + virtual void _onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len) {} + virtual void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) {} +}; + +class USBHID { +public: + USBHID(hid_interface_protocol_enum_t itf_protocol = HID_ITF_PROTOCOL_NONE); + void begin(void); + void end(void); + bool ready(void); + bool SendReport(uint8_t report_id, const void *data, size_t len, uint32_t timeout_ms = 100); + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_hid_event_t event, esp_event_handler_t callback); + static bool addDevice(USBHIDDevice *device, uint16_t descriptor_len); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDConsumerControl.cpp b/libraries/USB/src/USBHIDConsumerControl.cpp new file mode 100644 index 0000000..136cfb5 --- /dev/null +++ b/libraries/USB/src/USBHIDConsumerControl.cpp @@ -0,0 +1,55 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "USBHIDConsumerControl.h" + +static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_CONSUMER(HID_REPORT_ID(HID_REPORT_ID_CONSUMER_CONTROL))}; + +USBHIDConsumerControl::USBHIDConsumerControl() : hid() { + static bool initialized = false; + if (!initialized) { + initialized = true; + hid.addDevice(this, sizeof(report_descriptor)); + } +} + +uint16_t USBHIDConsumerControl::_onGetDescriptor(uint8_t *dst) { + memcpy(dst, report_descriptor, sizeof(report_descriptor)); + return sizeof(report_descriptor); +} + +void USBHIDConsumerControl::begin() { + hid.begin(); +} + +void USBHIDConsumerControl::end() {} + +bool USBHIDConsumerControl::send(uint16_t value) { + return hid.SendReport(HID_REPORT_ID_CONSUMER_CONTROL, &value, 2); +} + +size_t USBHIDConsumerControl::press(uint16_t k) { + return send(k); +} + +size_t USBHIDConsumerControl::release() { + return send(0); +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDConsumerControl.h b/libraries/USB/src/USBHIDConsumerControl.h new file mode 100644 index 0000000..7a59c70 --- /dev/null +++ b/libraries/USB/src/USBHIDConsumerControl.h @@ -0,0 +1,95 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +// Power Control +#define CONSUMER_CONTROL_POWER 0x0030 +#define CONSUMER_CONTROL_RESET 0x0031 +#define CONSUMER_CONTROL_SLEEP 0x0032 + +// Screen Brightness +#define CONSUMER_CONTROL_BRIGHTNESS_INCREMENT 0x006F +#define CONSUMER_CONTROL_BRIGHTNESS_DECREMENT 0x0070 + +// These HID usages operate only on mobile systems (battery powered) and +// require Windows 8 (build 8302 or greater). +#define CONSUMER_CONTROL_WIRELESS_RADIO_CONTROLS 0x000C +#define CONSUMER_CONTROL_WIRELESS_RADIO_BUTTONS 0x00C6 +#define CONSUMER_CONTROL_WIRELESS_RADIO_LED 0x00C7 +#define CONSUMER_CONTROL_WIRELESS_RADIO_SLIDER_SWITCH 0x00C8 + +// Media Control +#define CONSUMER_CONTROL_RECORD 0x00B2 +#define CONSUMER_CONTROL_FAST_FORWARD 0x00B3 +#define CONSUMER_CONTROL_REWIND 0x00B4 +#define CONSUMER_CONTROL_SCAN_NEXT 0x00B5 +#define CONSUMER_CONTROL_SCAN_PREVIOUS 0x00B6 +#define CONSUMER_CONTROL_STOP 0x00B7 +#define CONSUMER_CONTROL_EJECT 0x00B8 +#define CONSUMER_CONTROL_PLAY_PAUSE 0x00CD +#define CONSUMER_CONTROL_VOLUME 0x00E0 +#define CONSUMER_CONTROL_MUTE 0x00E2 +#define CONSUMER_CONTROL_BASS 0x00E3 +#define CONSUMER_CONTROL_TREBLE 0x00E4 +#define CONSUMER_CONTROL_BASS_BOOST 0x00E5 +#define CONSUMER_CONTROL_VOLUME_INCREMENT 0x00E9 +#define CONSUMER_CONTROL_VOLUME_DECREMENT 0x00EA +#define CONSUMER_CONTROL_BASS_INCREMENT 0x0152 +#define CONSUMER_CONTROL_BASS_DECREMENT 0x0153 +#define CONSUMER_CONTROL_TREBLE_INCREMENT 0x0154 +#define CONSUMER_CONTROL_TREBLE_DECREMENT 0x0155 + +// Application Launcher +#define CONSUMER_CONTROL_CONFIGURATION 0x0183 +#define CONSUMER_CONTROL_EMAIL_READER 0x018A +#define CONSUMER_CONTROL_CALCULATOR 0x0192 +#define CONSUMER_CONTROL_LOCAL_BROWSER 0x0194 + +// Browser/Explorer Specific +#define CONSUMER_CONTROL_SEARCH 0x0221 +#define CONSUMER_CONTROL_HOME 0x0223 +#define CONSUMER_CONTROL_BACK 0x0224 +#define CONSUMER_CONTROL_FORWARD 0x0225 +#define CONSUMER_CONTROL_BR_STOP 0x0226 +#define CONSUMER_CONTROL_REFRESH 0x0227 +#define CONSUMER_CONTROL_BOOKMARKS 0x022A + +// Mouse Horizontal scroll +#define CONSUMER_CONTROL_PAN 0x0238 + +class USBHIDConsumerControl : public USBHIDDevice { +private: + USBHID hid; + bool send(uint16_t value); + +public: + USBHIDConsumerControl(void); + void begin(void); + void end(void); + size_t press(uint16_t k); + size_t release(); + + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDGamepad.cpp b/libraries/USB/src/USBHIDGamepad.cpp new file mode 100644 index 0000000..a82e162 --- /dev/null +++ b/libraries/USB/src/USBHIDGamepad.cpp @@ -0,0 +1,109 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "USBHIDGamepad.h" + +static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_GAMEPAD(HID_REPORT_ID(HID_REPORT_ID_GAMEPAD))}; + +USBHIDGamepad::USBHIDGamepad() : hid(), _x(0), _y(0), _z(0), _rz(0), _rx(0), _ry(0), _hat(0), _buttons(0) { + static bool initialized = false; + if (!initialized) { + initialized = true; + hid.addDevice(this, sizeof(report_descriptor)); + } +} + +uint16_t USBHIDGamepad::_onGetDescriptor(uint8_t *dst) { + memcpy(dst, report_descriptor, sizeof(report_descriptor)); + return sizeof(report_descriptor); +} + +void USBHIDGamepad::begin() { + hid.begin(); +} + +void USBHIDGamepad::end() {} + +bool USBHIDGamepad::write() { + hid_gamepad_report_t report = {.x = _x, .y = _y, .z = _z, .rz = _rz, .rx = _rx, .ry = _ry, .hat = _hat, .buttons = _buttons}; + return hid.SendReport(HID_REPORT_ID_GAMEPAD, &report, sizeof(report)); +} + +bool USBHIDGamepad::leftStick(int8_t x, int8_t y) { + _x = x; + _y = y; + return write(); +} + +bool USBHIDGamepad::rightStick(int8_t z, int8_t rz) { + _z = z; + _rz = rz; + return write(); +} + +bool USBHIDGamepad::leftTrigger(int8_t rx) { + _rx = rx; + return write(); +} + +bool USBHIDGamepad::rightTrigger(int8_t ry) { + _ry = ry; + return write(); +} + +bool USBHIDGamepad::hat(uint8_t hat) { + if (hat > 9) { + return false; + } + _hat = hat; + return write(); +} + +bool USBHIDGamepad::pressButton(uint8_t button) { + if (button > 31) { + return false; + } + _buttons |= (1 << button); + return write(); +} + +bool USBHIDGamepad::releaseButton(uint8_t button) { + if (button > 31) { + return false; + } + _buttons &= ~(1 << button); + return write(); +} + +bool USBHIDGamepad::send(int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) { + if (hat > 9) { + return false; + } + _x = x; + _y = y; + _z = z; + _rz = rz; + _rx = rx; + _ry = ry; + _hat = hat; + _buttons = buttons; + return write(); +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDGamepad.h b/libraries/USB/src/USBHIDGamepad.h new file mode 100644 index 0000000..7e1ff2c --- /dev/null +++ b/libraries/USB/src/USBHIDGamepad.h @@ -0,0 +1,93 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +/// Standard Gamepad Buttons Naming from Linux input event codes +/// https://github.com/torvalds/linux/blob/master/include/uapi/linux/input-event-codes.h +#define BUTTON_A 0 +#define BUTTON_B 1 +#define BUTTON_C 2 +#define BUTTON_X 3 +#define BUTTON_Y 4 +#define BUTTON_Z 5 +#define BUTTON_TL 6 +#define BUTTON_TR 7 +#define BUTTON_TL2 8 +#define BUTTON_TR2 9 +#define BUTTON_SELECT 10 +#define BUTTON_START 11 +#define BUTTON_MODE 12 +#define BUTTON_THUMBL 13 +#define BUTTON_THUMBR 14 + +#define BUTTON_SOUTH BUTTON_A +#define BUTTON_EAST BUTTON_B +#define BUTTON_NORTH BUTTON_X +#define BUTTON_WEST BUTTON_Y + +/// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes) +#define HAT_CENTER 0 +#define HAT_UP 1 +#define HAT_UP_RIGHT 2 +#define HAT_RIGHT 3 +#define HAT_DOWN_RIGHT 4 +#define HAT_DOWN 5 +#define HAT_DOWN_LEFT 6 +#define HAT_LEFT 7 +#define HAT_UP_LEFT 8 + +class USBHIDGamepad : public USBHIDDevice { +private: + USBHID hid; + int8_t _x; ///< Delta x movement of left analog-stick + int8_t _y; ///< Delta y movement of left analog-stick + int8_t _z; ///< Delta z movement of right analog-joystick + int8_t _rz; ///< Delta Rz movement of right analog-joystick + int8_t _rx; ///< Delta Rx movement of analog left trigger + int8_t _ry; ///< Delta Ry movement of analog right trigger + uint8_t _hat; ///< Buttons mask for currently pressed buttons in the DPad/hat + uint32_t _buttons; ///< Buttons mask for currently pressed buttons + bool write(); + +public: + USBHIDGamepad(void); + void begin(void); + void end(void); + + bool leftStick(int8_t x, int8_t y); + bool rightStick(int8_t z, int8_t rz); + + bool leftTrigger(int8_t rx); + bool rightTrigger(int8_t ry); + + bool hat(uint8_t hat); + + bool pressButton(uint8_t button); + bool releaseButton(uint8_t button); + + bool send(int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons); + + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDKeyboard.cpp b/libraries/USB/src/USBHIDKeyboard.cpp new file mode 100644 index 0000000..9f371b2 --- /dev/null +++ b/libraries/USB/src/USBHIDKeyboard.cpp @@ -0,0 +1,235 @@ +/* + Keyboard.cpp + + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "USBHIDKeyboard.h" +#include "keyboardLayout/KeyboardLayout.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_KEYBOARD_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_KEYBOARD(HID_REPORT_ID(HID_REPORT_ID_KEYBOARD))}; + +USBHIDKeyboard::USBHIDKeyboard() : hid(HID_ITF_PROTOCOL_KEYBOARD), _asciimap(KeyboardLayout_en_US), shiftKeyReports(false) { + static bool initialized = false; + if (!initialized) { + initialized = true; + memset(&_keyReport, 0, sizeof(KeyReport)); + hid.addDevice(this, sizeof(report_descriptor)); + } +} + +uint16_t USBHIDKeyboard::_onGetDescriptor(uint8_t *dst) { + memcpy(dst, report_descriptor, sizeof(report_descriptor)); + return sizeof(report_descriptor); +} + +void USBHIDKeyboard::begin(const uint8_t *layout) { + _asciimap = layout; + hid.begin(); +} + +void USBHIDKeyboard::end() {} + +void USBHIDKeyboard::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_HID_KEYBOARD_ANY_EVENT, callback); +} +void USBHIDKeyboard::onEvent(arduino_usb_hid_keyboard_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_HID_KEYBOARD_EVENTS, event, callback, this); +} + +void USBHIDKeyboard::_onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) { + if (report_id == HID_REPORT_ID_KEYBOARD) { + arduino_usb_hid_keyboard_event_data_t p; + p.leds = buffer[0]; + arduino_usb_event_post( + ARDUINO_USB_HID_KEYBOARD_EVENTS, ARDUINO_USB_HID_KEYBOARD_LED_EVENT, &p, sizeof(arduino_usb_hid_keyboard_event_data_t), portMAX_DELAY + ); + } +} + +void USBHIDKeyboard::sendReport(KeyReport *keys) { + hid_keyboard_report_t report; + report.reserved = 0; + report.modifier = keys->modifiers; + memcpy(report.keycode, keys->keys, 6); + hid.SendReport(HID_REPORT_ID_KEYBOARD, &report, sizeof(report)); +} + +void USBHIDKeyboard::setShiftKeyReports(bool set) { + shiftKeyReports = set; +} + +size_t USBHIDKeyboard::pressRaw(uint8_t k) { + uint8_t i; + if (k >= 0xE0 && k < 0xE8) { + // it's a modifier key + _keyReport.modifiers |= (1 << (k - 0xE0)); + } else if (k && k < 0xA5) { + // Add k to the key report only if it's not already present + // and if there is an empty slot. + if (_keyReport.keys[0] != k && _keyReport.keys[1] != k && _keyReport.keys[2] != k && _keyReport.keys[3] != k && _keyReport.keys[4] != k + && _keyReport.keys[5] != k) { + + for (i = 0; i < 6; i++) { + if (_keyReport.keys[i] == 0x00) { + _keyReport.keys[i] = k; + break; + } + } + if (i == 6) { + return 0; + } + } + } else if (_keyReport.modifiers == 0) { + //not a modifier and not a key + return 0; + } + sendReport(&_keyReport); + return 1; +} + +size_t USBHIDKeyboard::releaseRaw(uint8_t k) { + uint8_t i; + if (k >= 0xE0 && k < 0xE8) { + // it's a modifier key + _keyReport.modifiers &= ~(1 << (k - 0xE0)); + } else if (k && k < 0xA5) { + // Test the key report to see if k is present. Clear it if it exists. + // Check all positions in case the key is present more than once (which it shouldn't be) + for (i = 0; i < 6; i++) { + if (0 != k && _keyReport.keys[i] == k) { + _keyReport.keys[i] = 0x00; + } + } + } + // Allowing for the release of a modifier key without a corresponding press + sendReport(&_keyReport); + return 1; +} + +// press() adds the specified key (printing, non-printing, or modifier) +// to the persistent key report and sends the report. Because of the way +// USB HID works, the host acts like the key remains pressed until we +// call release(), releaseAll(), or otherwise clear the report and resend. +size_t USBHIDKeyboard::press(uint8_t k) { + if (k >= 0x88) { // it's a non-printing key (not a modifier) + k = k - 0x88; + } else if (k >= 0x80) { // it's a modifier key + _keyReport.modifiers |= (1 << (k - 0x80)); + k = 0; + } else { // it's a printing key (k is a ASCII 0..127) + k = _asciimap[k]; + if (!k) { + return 0; + } + if ((k & SHIFT) == SHIFT) { // it's a capital letter or other character reached with shift + // At boot, some PCs need a separate report with the shift key down like a real keyboard. + if (shiftKeyReports) { + pressRaw(HID_KEY_SHIFT_LEFT); + } else { + _keyReport.modifiers |= 0x02; // the left shift modifier + } + k &= ~SHIFT; + } + if ((k & ALT_GR) == ALT_GR) { + _keyReport.modifiers |= 0x40; // AltGr = right Alt + k &= ~ALT_GR; + } + if (k == ISO_REPLACEMENT) { + k = ISO_KEY; + } + } + return pressRaw(k); +} + +// release() takes the specified key out of the persistent key report and +// sends the report. This tells the OS the key is no longer pressed and that +// it shouldn't be repeated any more. +size_t USBHIDKeyboard::release(uint8_t k) { + if (k >= 0x88) { // it's a non-printing key (not a modifier) + k = k - 0x88; + } else if (k >= 0x80) { // it's a modifier key + _keyReport.modifiers &= ~(1 << (k - 0x80)); + k = 0; + } else { // it's a printing key + k = _asciimap[k]; + if (!k) { + return 0; + } + if ((k & SHIFT) == SHIFT) { // it's a capital letter or other character reached with shift + if (shiftKeyReports) { + releaseRaw(k & 0x7F); // Release key without shift modifier + k = HID_KEY_SHIFT_LEFT; // Below, release shift modifier + } else { + _keyReport.modifiers &= ~(0x02); // the left shift modifier + k &= ~SHIFT; + } + } + if ((k & ALT_GR) == ALT_GR) { + _keyReport.modifiers &= ~(0x40); // AltGr = right Alt + k &= ~ALT_GR; + } + if (k == ISO_REPLACEMENT) { + k = ISO_KEY; + } + } + return releaseRaw(k); +} + +void USBHIDKeyboard::releaseAll(void) { + _keyReport.keys[0] = 0; + _keyReport.keys[1] = 0; + _keyReport.keys[2] = 0; + _keyReport.keys[3] = 0; + _keyReport.keys[4] = 0; + _keyReport.keys[5] = 0; + _keyReport.modifiers = 0; + sendReport(&_keyReport); +} + +size_t USBHIDKeyboard::write(uint8_t c) { + uint8_t p = press(c); // Keydown + release(c); // Keyup + return p; // just return the result of press() since release() almost always returns 1 +} + +size_t USBHIDKeyboard::write(const uint8_t *buffer, size_t size) { + size_t n = 0; + while (size--) { + if (*buffer != '\r') { + if (write(*buffer)) { + n++; + } else { + break; + } + } + buffer++; + } + return n; +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDKeyboard.h b/libraries/USB/src/USBHIDKeyboard.h new file mode 100644 index 0000000..d78b7fc --- /dev/null +++ b/libraries/USB/src/USBHIDKeyboard.h @@ -0,0 +1,183 @@ +/* + Keyboard.h + + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "Print.h" +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +#include "esp_event.h" + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_KEYBOARD_EVENTS); + +typedef enum { + ARDUINO_USB_HID_KEYBOARD_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_HID_KEYBOARD_LED_EVENT = 0, + ARDUINO_USB_HID_KEYBOARD_MAX_EVENT, +} arduino_usb_hid_keyboard_event_t; + +typedef union { + struct { + uint8_t numlock : 1; + uint8_t capslock : 1; + uint8_t scrolllock : 1; + uint8_t compose : 1; + uint8_t kana : 1; + uint8_t reserved : 3; + }; + uint8_t leds; +} arduino_usb_hid_keyboard_event_data_t; + +// Supported keyboard layouts +extern const uint8_t KeyboardLayout_de_DE[]; +extern const uint8_t KeyboardLayout_en_US[]; +extern const uint8_t KeyboardLayout_es_ES[]; +extern const uint8_t KeyboardLayout_fr_FR[]; +extern const uint8_t KeyboardLayout_it_IT[]; +extern const uint8_t KeyboardLayout_pt_PT[]; +extern const uint8_t KeyboardLayout_sv_SE[]; +extern const uint8_t KeyboardLayout_da_DK[]; +extern const uint8_t KeyboardLayout_hu_HU[]; +extern const uint8_t KeyboardLayout_pt_BR[]; + +#define KEY_LEFT_CTRL 0x80 +#define KEY_LEFT_SHIFT 0x81 +#define KEY_LEFT_ALT 0x82 +#define KEY_LEFT_GUI 0x83 +#define KEY_RIGHT_CTRL 0x84 +#define KEY_RIGHT_SHIFT 0x85 +#define KEY_RIGHT_ALT 0x86 // AltGr (Right Alt) Key +#define KEY_RIGHT_GUI 0x87 + +#define KEY_UP_ARROW 0xDA +#define KEY_DOWN_ARROW 0xD9 +#define KEY_LEFT_ARROW 0xD8 +#define KEY_RIGHT_ARROW 0xD7 +#define KEY_MENU 0xED // "Keyboard Application" in USB standard +#define KEY_SPACE 0x20 +#define KEY_BACKSPACE 0xB2 +#define KEY_TAB 0xB3 +#define KEY_RETURN 0xB0 +#define KEY_ESC 0xB1 +#define KEY_INSERT 0xD1 +#define KEY_DELETE 0xD4 +#define KEY_PAGE_UP 0xD3 +#define KEY_PAGE_DOWN 0xD6 +#define KEY_HOME 0xD2 +#define KEY_END 0xD5 +#define KEY_NUM_LOCK 0xDB +#define KEY_CAPS_LOCK 0xC1 +#define KEY_F1 0xC2 +#define KEY_F2 0xC3 +#define KEY_F3 0xC4 +#define KEY_F4 0xC5 +#define KEY_F5 0xC6 +#define KEY_F6 0xC7 +#define KEY_F7 0xC8 +#define KEY_F8 0xC9 +#define KEY_F9 0xCA +#define KEY_F10 0xCB +#define KEY_F11 0xCC +#define KEY_F12 0xCD +#define KEY_F13 0xF0 +#define KEY_F14 0xF1 +#define KEY_F15 0xF2 +#define KEY_F16 0xF3 +#define KEY_F17 0xF4 +#define KEY_F18 0xF5 +#define KEY_F19 0xF6 +#define KEY_F20 0xF7 +#define KEY_F21 0xF8 +#define KEY_F22 0xF9 +#define KEY_F23 0xFA +#define KEY_F24 0xFB +#define KEY_PRINT_SCREEN 0xCE +#define KEY_SCROLL_LOCK 0xCF +#define KEY_PAUSE 0xD0 + +#define LED_NUMLOCK 0x01 +#define LED_CAPSLOCK 0x02 +#define LED_SCROLLLOCK 0x04 +#define LED_COMPOSE 0x08 +#define LED_KANA 0x10 + +// Numeric keypad +#define KEY_KP_SLASH 0xDC +#define KEY_KP_ASTERISK 0xDD +#define KEY_KP_MINUS 0xDE +#define KEY_KP_PLUS 0xDF +#define KEY_KP_ENTER 0xE0 +#define KEY_KP_1 0xE1 +#define KEY_KP_2 0xE2 +#define KEY_KP_3 0xE3 +#define KEY_KP_4 0xE4 +#define KEY_KP_5 0xE5 +#define KEY_KP_6 0xE6 +#define KEY_KP_7 0xE7 +#define KEY_KP_8 0xE8 +#define KEY_KP_9 0xE9 +#define KEY_KP_0 0xEA +#define KEY_KP_DOT 0xEB + +// Low level key report: up to 6 keys and shift, ctrl etc at once +typedef struct { + uint8_t modifiers; + uint8_t reserved; + uint8_t keys[6]; +} KeyReport; + +class USBHIDKeyboard : public USBHIDDevice, public Print { +private: + USBHID hid; + KeyReport _keyReport; + const uint8_t *_asciimap; + bool shiftKeyReports; + +public: + USBHIDKeyboard(void); + void begin(const uint8_t *layout = KeyboardLayout_en_US); + void end(void); + size_t write(uint8_t k); + size_t write(const uint8_t *buffer, size_t size); + size_t press(uint8_t k); + size_t release(uint8_t k); + void releaseAll(void); + void sendReport(KeyReport *keys); + void setShiftKeyReports(bool set); + + //raw functions work with TinyUSB's HID_KEY_* macros + size_t pressRaw(uint8_t k); + size_t releaseRaw(uint8_t k); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_hid_keyboard_event_t event, esp_event_handler_t callback); + + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); + void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDMouse.cpp b/libraries/USB/src/USBHIDMouse.cpp new file mode 100644 index 0000000..885075c --- /dev/null +++ b/libraries/USB/src/USBHIDMouse.cpp @@ -0,0 +1,120 @@ +/* + Mouse.cpp + + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "USBHIDMouse.h" + +USBHIDMouseBase::USBHIDMouseBase(HIDMouseType_t *type) : hid(), _buttons(0), _type(type) { + static bool initialized = false; + if (!initialized) { + initialized = true; + hid.addDevice(this, _type->descriptor_size); + } +}; + +uint16_t USBHIDMouseBase::_onGetDescriptor(uint8_t *dst) { + memcpy(dst, _type->report_descriptor, _type->descriptor_size); + return _type->descriptor_size; +} + +void USBHIDMouseBase::buttons(uint8_t b) { + if (b != _buttons) { + _buttons = b; + } +} + +void USBHIDMouseBase::begin() { + hid.begin(); +} + +void USBHIDMouseBase::end() {} + +void USBHIDMouseBase::press(uint8_t b) { + this->buttons(_buttons | b); +} + +void USBHIDMouseBase::release(uint8_t b) { + this->buttons(_buttons & ~b); +} + +bool USBHIDMouseBase::isPressed(uint8_t b) { + if ((b & _buttons) > 0) { + return true; + } + return false; +} + +static const uint8_t abs_mouse_report_descriptor[] = {TUD_HID_REPORT_DESC_ABSMOUSE(HID_REPORT_ID(HID_REPORT_ID_MOUSE))}; + +HIDMouseType_t HIDMouseAbs = {HID_MOUSE_ABSOLUTE, abs_mouse_report_descriptor, sizeof(abs_mouse_report_descriptor), sizeof(hid_abs_mouse_report_t)}; + +void USBHIDAbsoluteMouse::move(int16_t x, int16_t y, int8_t wheel, int8_t pan) { + hid_abs_mouse_report_t report; + report.buttons = _buttons; + report.x = _lastx = x; + report.y = _lasty = y; + report.wheel = wheel; + report.pan = pan; + sendReport(report); +} + +void USBHIDAbsoluteMouse::click(uint8_t b) { + _buttons = b; + move(_lastx, _lasty); + _buttons = 0; + move(_lastx, _lasty); +} + +void USBHIDAbsoluteMouse::buttons(uint8_t b) { + if (b != _buttons) { + _buttons = b; + move(_lastx, _lasty); + } +} + +static const uint8_t rel_mouse_report_descriptor[] = {TUD_HID_REPORT_DESC_MOUSE(HID_REPORT_ID(HID_REPORT_ID_MOUSE))}; + +HIDMouseType_t HIDMouseRel = {HID_MOUSE_RELATIVE, rel_mouse_report_descriptor, sizeof(rel_mouse_report_descriptor), sizeof(hid_mouse_report_t)}; + +void USBHIDRelativeMouse::move(int8_t x, int8_t y, int8_t wheel, int8_t pan) { + hid_mouse_report_t report = {.buttons = _buttons, .x = x, .y = y, .wheel = wheel, .pan = pan}; + sendReport(report); +} + +void USBHIDRelativeMouse::click(uint8_t b) { + _buttons = b; + move(0, 0); + _buttons = 0; + move(0, 0); +} + +void USBHIDRelativeMouse::buttons(uint8_t b) { + if (b != _buttons) { + _buttons = b; + move(0, 0); + } +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDMouse.h b/libraries/USB/src/USBHIDMouse.h new file mode 100644 index 0000000..9b9e348 --- /dev/null +++ b/libraries/USB/src/USBHIDMouse.h @@ -0,0 +1,98 @@ +/* + Mouse.h + + Copyright (c) 2015, Arduino LLC + Original code (pre-library): Copyright (c) 2011, Peter Barrett + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +#define MOUSE_LEFT 0x01 +#define MOUSE_RIGHT 0x02 +#define MOUSE_MIDDLE 0x04 +#define MOUSE_BACKWARD 0x08 +#define MOUSE_FORWARD 0x10 +#define MOUSE_ALL 0x1F + +enum MousePositioning_t { + HID_MOUSE_RELATIVE, + HID_MOUSE_ABSOLUTE +}; + +struct HIDMouseType_t { + MousePositioning_t positioning; + const uint8_t *report_descriptor; + size_t descriptor_size; + size_t report_size; +}; + +extern HIDMouseType_t HIDMouseRel; +extern HIDMouseType_t HIDMouseAbs; + +class USBHIDMouseBase : public USBHIDDevice { +public: + USBHIDMouseBase(HIDMouseType_t *type); + void begin(void); + void end(void); + void press(uint8_t b = MOUSE_LEFT); // press LEFT by default + void release(uint8_t b = MOUSE_LEFT); // release LEFT by default + bool isPressed(uint8_t b = MOUSE_LEFT); // check LEFT by default + template bool sendReport(T report) { + return hid.SendReport(HID_REPORT_ID_MOUSE, &report, _type->report_size); + }; + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); + virtual void click(uint8_t b) = 0; + virtual void buttons(uint8_t b) = 0; + +protected: + USBHID hid; + uint8_t _buttons; + HIDMouseType_t *_type; +}; + +class USBHIDRelativeMouse : public USBHIDMouseBase { +public: + USBHIDRelativeMouse(void) : USBHIDMouseBase(&HIDMouseRel) {} + void move(int8_t x, int8_t y, int8_t wheel = 0, int8_t pan = 0); + void click(uint8_t b = MOUSE_LEFT) override; + void buttons(uint8_t b) override; +}; + +class USBHIDAbsoluteMouse : public USBHIDMouseBase { +public: + USBHIDAbsoluteMouse(void) : USBHIDMouseBase(&HIDMouseAbs) {} + void move(int16_t x, int16_t y, int8_t wheel = 0, int8_t pan = 0); + void click(uint8_t b = MOUSE_LEFT) override; + void buttons(uint8_t b) override; + +private: + int16_t _lastx = 0; + int16_t _lasty = 0; +}; + +// don't break examples and old sketches +typedef USBHIDRelativeMouse USBHIDMouse; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDSystemControl.cpp b/libraries/USB/src/USBHIDSystemControl.cpp new file mode 100644 index 0000000..97442bc --- /dev/null +++ b/libraries/USB/src/USBHIDSystemControl.cpp @@ -0,0 +1,58 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "USBHIDSystemControl.h" + +static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_SYSTEM_CONTROL(HID_REPORT_ID(HID_REPORT_ID_SYSTEM_CONTROL))}; + +USBHIDSystemControl::USBHIDSystemControl() : hid() { + static bool initialized = false; + if (!initialized) { + initialized = true; + hid.addDevice(this, sizeof(report_descriptor)); + } +} + +uint16_t USBHIDSystemControl::_onGetDescriptor(uint8_t *dst) { + memcpy(dst, report_descriptor, sizeof(report_descriptor)); + return sizeof(report_descriptor); +} + +void USBHIDSystemControl::begin() { + hid.begin(); +} + +void USBHIDSystemControl::end() {} + +bool USBHIDSystemControl::send(uint8_t value) { + return hid.SendReport(HID_REPORT_ID_SYSTEM_CONTROL, &value, 1); +} + +size_t USBHIDSystemControl::press(uint8_t k) { + if (k > 3) { + return 0; + } + return send(k); +} + +size_t USBHIDSystemControl::release() { + return send(0); +} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDSystemControl.h b/libraries/USB/src/USBHIDSystemControl.h new file mode 100644 index 0000000..c88f29b --- /dev/null +++ b/libraries/USB/src/USBHIDSystemControl.h @@ -0,0 +1,45 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +#define SYSTEM_CONTROL_NONE 0 +#define SYSTEM_CONTROL_POWER_OFF 1 +#define SYSTEM_CONTROL_STANDBY 2 +#define SYSTEM_CONTROL_WAKE_HOST 3 + +class USBHIDSystemControl : public USBHIDDevice { +private: + USBHID hid; + bool send(uint8_t value); + +public: + USBHIDSystemControl(void); + void begin(void); + void end(void); + size_t press(uint8_t k); + size_t release(); + + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDVendor.cpp b/libraries/USB/src/USBHIDVendor.cpp new file mode 100644 index 0000000..20a46e7 --- /dev/null +++ b/libraries/USB/src/USBHIDVendor.cpp @@ -0,0 +1,221 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBHID.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_HID_ENABLED + +#include "esp32-hal-log.h" +#include "USBHIDVendor.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_VENDOR_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +// HID Generic Input, Output & Feature +// - 1st parameter is report size (mandatory) +// - 2nd parameter is report id HID_REPORT_ID(n) (optional) +#define TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE(report_size, ...) \ + HID_USAGE_PAGE_N(HID_USAGE_PAGE_VENDOR, 2), HID_USAGE(0x01), HID_COLLECTION(HID_COLLECTION_APPLICATION), /* Report ID if any */ \ + __VA_ARGS__ /* Input */ \ + HID_USAGE(0x02), \ + HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size), \ + HID_INPUT(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), /* Output */ \ + HID_USAGE(0x03), HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size), \ + HID_OUTPUT(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), /* Feature */ \ + HID_USAGE(0x04), HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size), \ + HID_FEATURE(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), HID_COLLECTION_END + +#define TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE_LEN 46 + +// max size is 64 and we need one byte for the report ID +static uint8_t HID_VENDOR_REPORT_SIZE = 63; +static uint8_t feature[64]; +static QueueHandle_t rx_queue = NULL; +static bool prepend_size = false; + +USBHIDVendor::USBHIDVendor(uint8_t report_size, bool prepend) : hid() { + static bool initialized = false; + if (!initialized) { + initialized = true; + hid.addDevice(this, TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE_LEN); + memset(feature, 0, 64); + if (report_size < 64) { + HID_VENDOR_REPORT_SIZE = report_size; + } + prepend_size = prepend; + } +} + +uint16_t USBHIDVendor::_onGetDescriptor(uint8_t *dst) { + uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE(HID_VENDOR_REPORT_SIZE, HID_REPORT_ID(HID_REPORT_ID_VENDOR))}; + memcpy(dst, report_descriptor, sizeof(report_descriptor)); + return sizeof(report_descriptor); +} + +void USBHIDVendor::prependInputPacketsWithSize(bool enable) { + prepend_size = enable; +} + +size_t USBHIDVendor::setRxBufferSize(size_t rx_queue_len) { + if (rx_queue) { + if (!rx_queue_len) { + vQueueDelete(rx_queue); + rx_queue = NULL; + } + return 0; + } + rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t)); + if (!rx_queue) { + return 0; + } + return rx_queue_len; +} + +void USBHIDVendor::begin() { + hid.begin(); + setRxBufferSize(256); //default if not preset +} + +void USBHIDVendor::end() { + setRxBufferSize(0); +} + +void USBHIDVendor::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_HID_VENDOR_ANY_EVENT, callback); +} + +void USBHIDVendor::onEvent(arduino_usb_hid_vendor_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_HID_VENDOR_EVENTS, event, callback, this); +} + +uint16_t USBHIDVendor::_onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len) { + if (report_id != HID_REPORT_ID_VENDOR) { + return 0; + } + memcpy(buffer, feature, len); + arduino_usb_hid_vendor_event_data_t p; + p.buffer = feature; + p.len = len; + arduino_usb_event_post( + ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY + ); + return len; +} + +void USBHIDVendor::_onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len) { + if (report_id != HID_REPORT_ID_VENDOR) { + return; + } + memcpy(feature, buffer, len); + arduino_usb_hid_vendor_event_data_t p; + p.buffer = feature; + p.len = len; + arduino_usb_event_post( + ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY + ); +} + +void USBHIDVendor::_onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) { + if (report_id != HID_REPORT_ID_VENDOR) { + return; + } + for (uint32_t i = 0; i < len; i++) { + if (rx_queue == NULL || !xQueueSend(rx_queue, buffer + i, 0)) { + len = i + 1; + log_e("RX Queue Overflow"); + break; + } + } + arduino_usb_hid_vendor_event_data_t p; + p.buffer = buffer; + p.len = len; + arduino_usb_event_post(ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY); +} + +size_t USBHIDVendor::write(const uint8_t *buffer, size_t len) { + uint8_t hid_in[HID_VENDOR_REPORT_SIZE]; + const uint8_t *data = (const uint8_t *)buffer; + uint8_t size_offset = prepend_size ? 1 : 0; + size_t to_send = len, max_send = HID_VENDOR_REPORT_SIZE - size_offset, will_send = 0; + while (to_send) { + will_send = to_send; + if (will_send > max_send) { + will_send = max_send; + } + if (prepend_size) { + hid_in[0] = will_send; + } + // We can get INPUT only when data length equals the input report size + memcpy(hid_in + size_offset, data, will_send); + // pad with zeroes + memset(hid_in + size_offset + will_send, 0, max_send - will_send); + if (!hid.SendReport(HID_REPORT_ID_VENDOR, hid_in, HID_VENDOR_REPORT_SIZE)) { + return len - to_send; + } + to_send -= will_send; + data += will_send; + } + return len; +} + +size_t USBHIDVendor::write(uint8_t c) { + return write(&c, 1); +} + +int USBHIDVendor::available(void) { + if (rx_queue == NULL) { + return -1; + } + return uxQueueMessagesWaiting(rx_queue); +} + +int USBHIDVendor::peek(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c; + if (xQueuePeek(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +int USBHIDVendor::read(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + if (xQueueReceive(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +size_t USBHIDVendor::read(uint8_t *buffer, size_t size) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + size_t count = 0; + while (count < size && xQueueReceive(rx_queue, &c, 0)) { + buffer[count++] = c; + } + return count; +} + +void USBHIDVendor::flush(void) {} + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBHIDVendor.h b/libraries/USB/src/USBHIDVendor.h new file mode 100644 index 0000000..404f0fb --- /dev/null +++ b/libraries/USB/src/USBHIDVendor.h @@ -0,0 +1,73 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "Stream.h" +#include "USBHID.h" +#if CONFIG_TINYUSB_HID_ENABLED + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_VENDOR_EVENTS); + +typedef enum { + ARDUINO_USB_HID_VENDOR_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT = 0, + ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT, + ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT, + ARDUINO_USB_HID_VENDOR_MAX_EVENT, +} arduino_usb_hid_vendor_event_t; + +typedef struct { + const uint8_t *buffer; + uint16_t len; +} arduino_usb_hid_vendor_event_data_t; + +class USBHIDVendor : public USBHIDDevice, public Stream { +private: + USBHID hid; + +public: + // Max report size is 64, but we need one byte for report ID, so in reality max is 63. + // Because input packets are always with length equal to the report size + // it will not be known how many bytes actually matter. Setting 'prepend_size' to 'true' will + // make the first byte of each packet to be the length of data in that packet. + // This comes with penalty of one byte, but is very useful when using Vendor for streaming + USBHIDVendor(uint8_t report_size = 63, bool prepend_size = false); + void begin(void); + void end(void); + void prependInputPacketsWithSize(bool enable); + size_t setRxBufferSize(size_t); + size_t write(const uint8_t *buffer, size_t len); + size_t write(uint8_t); + int available(void); + int peek(void); + int read(void); + size_t read(uint8_t *buffer, size_t size); + void flush(void); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_hid_vendor_event_t event, esp_event_handler_t callback); + + // internal use + uint16_t _onGetDescriptor(uint8_t *buffer); + uint16_t _onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len); + void _onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len); + void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len); +}; + +#endif /* CONFIG_TINYUSB_HID_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBMIDI.cpp b/libraries/USB/src/USBMIDI.cpp new file mode 100644 index 0000000..61b75f0 --- /dev/null +++ b/libraries/USB/src/USBMIDI.cpp @@ -0,0 +1,200 @@ +#include "USBMIDI.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_MIDI_ENABLED + +#include "Arduino.h" +#include "esp32-hal-tinyusb.h" + +// Initialize static members +char *USBMIDI::midiUserDeviceName = nullptr; +// Weak definition of getUSBMIDIDefaultDeviceName to provide a default name +__attribute__((weak)) const char *getUSBMIDIDefaultDeviceName() { + return ESP32_USB_MIDI_DEFAULT_NAME; +} + +// Default Cable Number (for simplified APIs that do not expose this) +#define DEFAULT_CN 0 + +static bool tinyusb_midi_descriptor_loaded = false; +static bool tinyusb_midi_interface_enabled = false; + +extern "C" uint16_t tusb_midi_load_descriptor(uint8_t *dst, uint8_t *itf) { + if (tinyusb_midi_descriptor_loaded) { + return 0; + } + tinyusb_midi_descriptor_loaded = true; + + uint8_t str_index = tinyusb_add_string_descriptor(USBMIDI::getCurrentDeviceName()); + uint8_t ep_in = tinyusb_get_free_in_endpoint(); + TU_VERIFY(ep_in != 0); + uint8_t ep_out = tinyusb_get_free_out_endpoint(); + TU_VERIFY(ep_out != 0); + uint8_t descriptor[TUD_MIDI_DESC_LEN] = { + TUD_MIDI_DESCRIPTOR(*itf, str_index, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE), + }; + *itf += 2; + memcpy(dst, descriptor, TUD_MIDI_DESC_LEN); + + return TUD_MIDI_DESC_LEN; +} + +USBMIDI::USBMIDI() { + if (!tinyusb_midi_interface_enabled) { + tinyusb_midi_interface_enabled = true; + tinyusb_enable_interface(USB_INTERFACE_MIDI, TUD_MIDI_DESC_LEN, tusb_midi_load_descriptor); + } else { + log_e("USBMIDI: Multiple instances of USBMIDI not supported!"); + } +} + +// private function for setting a not null/empty MIDI device name limited to 32 characters +void USBMIDI::setDeviceName(const char *name) { + const uint8_t maxNameLength = 32; // tinyUSB Descriptor limit + if (name != nullptr && strlen(name) > 0) { + if (strlen(name) > maxNameLength) { + log_w("USBMIDI: Device name too long, truncating to %d characters.", maxNameLength); + } + if (!midiUserDeviceName) { + midiUserDeviceName = new char[maxNameLength + 1]; // +1 for null-terminator + } + if (midiUserDeviceName) { + strncpy(midiUserDeviceName, name, maxNameLength); + // Ensure null-termination when overflowing + midiUserDeviceName[maxNameLength] = '\0'; + } else { + log_e("USBMIDI: Failed to allocate memory for device name, using default name."); + } + } else { + log_w("USBMIDI: No device name provided, using default name [%s].", getUSBMIDIDefaultDeviceName()); + } +} + +/** +* @brief Constructor for setting the current device name +* 1. Name set via constructor (if any) +* 2. Name set via SET_USB_MIDI_DEVICE_NAME() macro (if defined) +* 3. Default name "TinyUSB MIDI" +* If device name is set as "", it will be ignored +*/ +USBMIDI::USBMIDI(const char *name) { + if (!tinyusb_midi_interface_enabled) { + setDeviceName(name); + tinyusb_midi_interface_enabled = true; + tinyusb_enable_interface(USB_INTERFACE_MIDI, TUD_MIDI_DESC_LEN, tusb_midi_load_descriptor); + } else { + log_e("USBMIDI: Multiple instances of USBMIDI not supported!"); + } +} + +USBMIDI::~USBMIDI() { + if (midiUserDeviceName) { + delete[] midiUserDeviceName; + midiUserDeviceName = nullptr; + } +} + +void USBMIDI::begin() {} +void USBMIDI::end() {} + +const char *USBMIDI::getCurrentDeviceName(void) { + if (midiUserDeviceName) { + return midiUserDeviceName; + } + // If no user name set, use the compile-time default name limited to 32 characters + setDeviceName(getUSBMIDIDefaultDeviceName()); + if (midiUserDeviceName && strlen(midiUserDeviceName)) { + return midiUserDeviceName; + } else { + return "TinyUSB MIDI"; + } +} + +// uint compatible version of constrain +#define uconstrain(amt, low, high) ((amt) <= (low) ? (low) : ((amt) > (high) ? (high) : (amt))) + +#define STATUS(CIN, CHANNEL) static_cast(((CIN & 0x7F) << 4) | (uconstrain(CHANNEL - 1, 0, 15) & 0x7F)) + +// Note: All the user-level API calls do extensive input constraining to prevent easy to make mistakes. +// (You can thank me later.) +#define _(x) static_cast(uconstrain(x, 0, 127)) + +// Note On +void USBMIDI::noteOn(uint8_t note, uint8_t velocity, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_NOTE_ON, STATUS(MIDI_CIN_NOTE_ON, channel), _(note), _(velocity)}; + writePacket(&event); +} + +// Note Off +void USBMIDI::noteOff(uint8_t note, uint8_t velocity, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_NOTE_OFF, STATUS(MIDI_CIN_NOTE_OFF, channel), _(note), _(velocity)}; + writePacket(&event); +} + +// Program Change +void USBMIDI::programChange(uint8_t program, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_PROGRAM_CHANGE, STATUS(MIDI_CIN_PROGRAM_CHANGE, channel), _(program), 0x0}; + writePacket(&event); +} + +// Control Change (Continuous Controller) +void USBMIDI::controlChange(uint8_t control, uint8_t value, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_CONTROL_CHANGE, STATUS(MIDI_CIN_CONTROL_CHANGE, channel), _(control), _(value)}; + writePacket(&event); +} + +// Polyphonic Key Pressure (Aftertouch) +void USBMIDI::polyPressure(uint8_t note, uint8_t pressure, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_POLY_KEYPRESS, STATUS(MIDI_CIN_POLY_KEYPRESS, channel), _(note), _(pressure)}; + writePacket(&event); +} + +// Channel Pressure (Aftertouch) +void USBMIDI::channelPressure(uint8_t pressure, uint8_t channel) { + midiEventPacket_t event = {MIDI_CIN_CHANNEL_PRESSURE, STATUS(MIDI_CIN_CHANNEL_PRESSURE, channel), _(pressure), 0x0}; + writePacket(&event); +} + +// Pitch Bend Change [-8192,0,8191] +void USBMIDI::pitchBend(int16_t value, uint8_t channel) { + uint16_t pitchBendValue = constrain(value, -8192, 8191) + 8192; + pitchBend(pitchBendValue, channel); +} + +// Pitch Bend Change [0,8192,16383] +void USBMIDI::pitchBend(uint16_t value, uint8_t channel) { + uint16_t pitchBendValue = static_cast(uconstrain(value, 0, 16383)); + // Split the 14-bit integer into two 7-bit values + uint8_t lsb = pitchBendValue & 0x7F; // Lower 7 bits + uint8_t msb = (pitchBendValue >> 7) & 0x7F; // Upper 7 bits + + midiEventPacket_t event = {MIDI_CIN_PITCH_BEND_CHANGE, STATUS(MIDI_CIN_PITCH_BEND_CHANGE, channel), lsb, msb}; + writePacket(&event); +} + +// Pitch Bend Change [-1.0,0,1.0] +void USBMIDI::pitchBend(double value, uint8_t channel) { + // Multiply by 8191 and round to nearest integer + int16_t pitchBendValue = static_cast(round(constrain(value, -1.0, 1.0) * 8191.0)); + + pitchBend(pitchBendValue, channel); +} + +bool USBMIDI::readPacket(midiEventPacket_t *packet) { + return tud_midi_packet_read((uint8_t *)packet); +} + +bool USBMIDI::writePacket(midiEventPacket_t *packet) { + return tud_midi_packet_write((uint8_t *)packet); +} + +size_t USBMIDI::write(uint8_t c) { + // MIDI_CIN_1BYTE_DATA => Verbatim MIDI byte-stream copy + // (See also Table 4-1 of USB MIDI spec 1.0) + midiEventPacket_t packet = {DEFAULT_CN | MIDI_CIN_1BYTE_DATA, c, 0, 0}; + + return tud_midi_packet_write((uint8_t *)&packet); +} + +#endif /* CONFIG_TINYUSB_MIDI_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBMIDI.h b/libraries/USB/src/USBMIDI.h new file mode 100644 index 0000000..8f111db --- /dev/null +++ b/libraries/USB/src/USBMIDI.h @@ -0,0 +1,91 @@ +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED +#include "esp32-hal-tinyusb.h" +#include "sdkconfig.h" + +#if CONFIG_TINYUSB_MIDI_ENABLED + +#pragma once + +#define MIDI_EP_HEADER_CN_GET(x) (x >> 4) +#define MIDI_EP_HEADER_CIN_GET(x) ((midi_code_index_number_t)((x) & 0xF)) + +typedef struct { + uint8_t header; + uint8_t byte1; + uint8_t byte2; + uint8_t byte3; +} midiEventPacket_t; + +class USBMIDI { +private: + static char *midiUserDeviceName; // user device name + static void setDeviceName(const char *name); // set user device name limited to 32 characters + +public: + /** + * @brief Default constructor + * Will use the compile-time name if set via SET_USB_MIDI_DEVICE_NAME(), + * otherwise uses "TinyUSB MIDI" + */ + USBMIDI(void); + + /** + * @brief Set the current device name + * 1. Name set via constructor (if any) + * 2. Name set via SET_USB_MIDI_DEVICE_NAME() macro (if defined) + * 3. Default name "TinyUSB MIDI" + * It has no effect if name is set as NULL or "" + */ + USBMIDI(const char *name); + + ~USBMIDI(); + + void begin(void); + void end(void); + + /** + * @brief Get the current device name + * @return The device name in order of precedence: + * 1. Name set via constructor (if any) + * 2. Name set via SET_USB_MIDI_DEVICE_NAME() macro (if defined) + * 3. Default name "TinyUSB MIDI" + */ + static const char *getCurrentDeviceName(void); + + /* User-level API */ + + // Note On + void noteOn(uint8_t note, uint8_t velocity = 0, uint8_t channel = 1); + // Note Off + void noteOff(uint8_t note, uint8_t velocity = 0, uint8_t channel = 1); + // Program Change + void programChange(uint8_t inProgramNumber, uint8_t channel = 1); + // Control Change (Continuous Controller) + void controlChange(uint8_t inControlNumber, uint8_t inControlValue = 0, uint8_t channel = 1); + // Polyphonic Key Pressure (Aftertouch) + void polyPressure(uint8_t note, uint8_t pressure, uint8_t channel = 1); + // Channel Pressure (Aftertouch) + void channelPressure(uint8_t pressure, uint8_t channel = 1); + // Pitch Bend Change [-8192,0,8191] + void pitchBend(int16_t pitchBendValue, uint8_t channel = 1); + // Pitch Bend Change [0,8192,16383] + void pitchBend(uint16_t pitchBendValue, uint8_t channel = 1); + // Pitch Bend Change [-1.0,0,1.0] + void pitchBend(double pitchBendValue, uint8_t channel = 1); + + /* USB MIDI 1.0 interface */ + + // Attempt to read a USB MIDI packet from the USB Bus + bool readPacket(midiEventPacket_t *packet); + // Attempt to write a USB MIDI packet to the USB Bus + bool writePacket(midiEventPacket_t *packet); + + /* Serial MIDI 1.0 interface */ + + // Write a Serial MIDI byte (status or data) to the USB Bus + size_t write(uint8_t c); +}; + +#endif /* CONFIG_TINYUSB_MIDI_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBVendor.cpp b/libraries/USB/src/USBVendor.cpp new file mode 100644 index 0000000..70fac57 --- /dev/null +++ b/libraries/USB/src/USBVendor.cpp @@ -0,0 +1,222 @@ +// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "USBVendor.h" +#if SOC_USB_OTG_SUPPORTED + +#if CONFIG_TINYUSB_VENDOR_ENABLED + +#include "esp32-hal-tinyusb.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_USB_VENDOR_EVENTS); +esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait); +esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg); + +static USBVendor *_Vendor = NULL; +static QueueHandle_t rx_queue = NULL; +static uint16_t USB_VENDOR_ENDPOINT_SIZE = CFG_TUD_ENDOINT_SIZE; + +uint16_t tusb_vendor_load_descriptor(uint8_t *dst, uint8_t *itf) { + uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB Vendor"); + uint8_t ep_num = tinyusb_get_free_duplex_endpoint(); + TU_VERIFY(ep_num != 0); + uint8_t descriptor[TUD_VENDOR_DESC_LEN] = {// Interface number, string index, EP Out & IN address, EP size + TUD_VENDOR_DESCRIPTOR(*itf, str_index, ep_num, (uint8_t)(0x80 | ep_num), USB_VENDOR_ENDPOINT_SIZE) + }; + *itf += 1; + memcpy(dst, descriptor, TUD_VENDOR_DESC_LEN); + return TUD_VENDOR_DESC_LEN; +} + +void tud_vendor_rx_cb(uint8_t itf) { + size_t len = tud_vendor_n_available(itf); + log_v("%u", len); + if (len) { + uint8_t buffer[len]; + len = tud_vendor_n_read(itf, buffer, len); + log_buf_v(buffer, len); + if (_Vendor) { + _Vendor->_onRX(buffer, len); + } + } else { + if (_Vendor) { + _Vendor->_onRX(NULL, len); + } + } +} + +extern "C" bool tinyusb_vendor_control_request_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + log_v( + "Port: %u, Stage: %u, Direction: %u, Type: %u, Recipient: %u, bRequest: 0x%x, wValue: %u, wIndex: %u, wLength: %u", rhport, stage, + request->bmRequestType_bit.direction, request->bmRequestType_bit.type, request->bmRequestType_bit.recipient, request->bRequest, request->wValue, + request->wIndex, request->wLength + ); + + if (_Vendor) { + return _Vendor->_onRequest(rhport, stage, (arduino_usb_control_request_t const *)request); + } + return false; +} + +USBVendor::USBVendor(uint16_t endpoint_size) : itf(0), cb(NULL) { + if (!_Vendor) { + _Vendor = this; + if (endpoint_size == 0) { + endpoint_size = CFG_TUD_ENDOINT_SIZE; + } + if (endpoint_size <= CFG_TUD_ENDOINT_SIZE) { + USB_VENDOR_ENDPOINT_SIZE = endpoint_size; + } + tinyusb_enable_interface(USB_INTERFACE_VENDOR, TUD_VENDOR_DESC_LEN, tusb_vendor_load_descriptor); + } else { + itf = _Vendor->itf; + cb = _Vendor->cb; + } +} + +size_t USBVendor::setRxBufferSize(size_t rx_queue_len) { + if (rx_queue) { + if (!rx_queue_len) { + vQueueDelete(rx_queue); + rx_queue = NULL; + } + return 0; + } + rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t)); + if (!rx_queue) { + return 0; + } + return rx_queue_len; +} + +void USBVendor::begin() { + setRxBufferSize(512); //default if not preset +} + +void USBVendor::end() { + setRxBufferSize(0); +} + +void USBVendor::onEvent(esp_event_handler_t callback) { + onEvent(ARDUINO_USB_VENDOR_ANY_EVENT, callback); +} + +void USBVendor::onEvent(arduino_usb_vendor_event_t event, esp_event_handler_t callback) { + arduino_usb_event_handler_register_with(ARDUINO_USB_VENDOR_EVENTS, event, callback, this); +} + +bool USBVendor::mounted() { + return tud_vendor_n_mounted(itf); +} + +bool USBVendor::sendResponse(uint8_t rhport, arduino_usb_control_request_t const *request, void *data, size_t len) { + if (!request) { + return false; + } + if (!data || !len) { + return tud_control_status(rhport, (tusb_control_request_t const *)request); + } else { + return tud_control_xfer(rhport, (tusb_control_request_t const *)request, data, len); + } +} + +void USBVendor::onRequest(arduino_usb_vendor_control_request_handler_t handler) { + cb = handler; +} + +bool USBVendor::_onRequest(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request) { + if (cb) { + return cb(rhport, stage, request); + } + return false; +} + +void USBVendor::_onRX(const uint8_t *buffer, size_t len) { + for (uint32_t i = 0; i < len; i++) { + if (rx_queue == NULL || !xQueueSend(rx_queue, buffer + i, 0)) { + len = i + 1; + log_e("RX Queue Overflow"); + break; + } + } + arduino_usb_vendor_event_data_t p; + p.data.len = len; + arduino_usb_event_post(ARDUINO_USB_VENDOR_EVENTS, ARDUINO_USB_VENDOR_DATA_EVENT, &p, sizeof(arduino_usb_vendor_event_data_t), portMAX_DELAY); +} + +size_t USBVendor::write(const uint8_t *buffer, size_t len) { + if (!mounted()) { + log_e("not mounted"); + return 0; + } + size_t max_len = tud_vendor_n_write_available(itf); + if (len > max_len) { + len = max_len; + } + if (len) { + return tud_vendor_n_write(itf, buffer, len); + } + return len; +} + +size_t USBVendor::write(uint8_t c) { + return write(&c, 1); +} + +int USBVendor::available(void) { + if (rx_queue == NULL) { + return -1; + } + return uxQueueMessagesWaiting(rx_queue); +} + +int USBVendor::peek(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c; + if (xQueuePeek(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +int USBVendor::read(void) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + if (xQueueReceive(rx_queue, &c, 0)) { + return c; + } + return -1; +} + +size_t USBVendor::read(uint8_t *buffer, size_t size) { + if (rx_queue == NULL) { + return -1; + } + uint8_t c = 0; + size_t count = 0; + while (count < size && xQueueReceive(rx_queue, &c, 0)) { + buffer[count++] = c; + } + return count; +} + +void USBVendor::flush(void) { + tud_vendor_n_write_flush(itf); +} + +#endif /* CONFIG_TINYUSB_VENDOR_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/USBVendor.h b/libraries/USB/src/USBVendor.h new file mode 100644 index 0000000..4990e46 --- /dev/null +++ b/libraries/USB/src/USBVendor.h @@ -0,0 +1,100 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#if SOC_USB_OTG_SUPPORTED + +#include "Stream.h" +#include "sdkconfig.h" + +#if CONFIG_TINYUSB_VENDOR_ENABLED +#include "esp_event.h" + +ESP_EVENT_DECLARE_BASE(ARDUINO_USB_VENDOR_EVENTS); + +#define REQUEST_STAGE_SETUP 0 +#define REQUEST_STAGE_DATA 1 +#define REQUEST_STAGE_ACK 2 + +#define REQUEST_TYPE_STANDARD 0 +#define REQUEST_TYPE_CLASS 1 +#define REQUEST_TYPE_VENDOR 2 +#define REQUEST_TYPE_INVALID 3 + +#define REQUEST_RECIPIENT_DEVICE 0 +#define REQUEST_RECIPIENT_INTERFACE 1 +#define REQUEST_RECIPIENT_ENDPOINT 2 +#define REQUEST_RECIPIENT_OTHER 3 + +#define REQUEST_DIRECTION_OUT 0 +#define REQUEST_DIRECTION_IN 1 + +typedef struct __attribute__((packed)) { + struct __attribute__((packed)) { + uint8_t bmRequestRecipient : 5; + uint8_t bmRequestType : 2; + uint8_t bmRequestDirection : 1; + }; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} arduino_usb_control_request_t; + +typedef enum { + ARDUINO_USB_VENDOR_ANY_EVENT = ESP_EVENT_ANY_ID, + ARDUINO_USB_VENDOR_DATA_EVENT, + ARDUINO_USB_VENDOR_MAX_EVENT, +} arduino_usb_vendor_event_t; + +typedef union { + struct { + uint16_t len; + } data; +} arduino_usb_vendor_event_data_t; + +typedef bool (*arduino_usb_vendor_control_request_handler_t)(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request); + +class USBVendor : public Stream { +private: + uint8_t itf; + arduino_usb_vendor_control_request_handler_t cb; + +public: + USBVendor(uint16_t endpoint_size = 0); + void begin(void); + void end(void); + size_t setRxBufferSize(size_t); + bool mounted(void); + size_t write(const uint8_t *buffer, size_t len); + size_t write(uint8_t); + int available(void); + int peek(void); + int read(void); + size_t read(uint8_t *buffer, size_t size); + void flush(void); + + void onEvent(esp_event_handler_t callback); + void onEvent(arduino_usb_vendor_event_t event, esp_event_handler_t callback); + void onRequest(arduino_usb_vendor_control_request_handler_t handler); + bool sendResponse(uint8_t rhport, arduino_usb_control_request_t const *request, void *data = NULL, size_t len = 0); + + bool _onRequest(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request); + void _onRX(const uint8_t *buffer, size_t len); +}; + +#endif /* CONFIG_TINYUSB_VENDOR_ENABLED */ +#endif /* SOC_USB_OTG_SUPPORTED */ diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout.h b/libraries/USB/src/keyboardLayout/KeyboardLayout.h new file mode 100644 index 0000000..ee6b6b4 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout.h @@ -0,0 +1,68 @@ +/* + KeyboardLayout.h + + This file is not part of the public API. It is meant to be included + only in Keyboard.cpp and the keyboard layout files. Layout files map + ASCII character codes to keyboard scan codes (technically, to USB HID + Usage codes), possibly altered by the SHIFT or ALT_GR modifiers. + Non-ASCII characters (anything outside the 7-bit range NUL..DEL) are + not supported. + + == Creating your own layout == + + In order to create your own layout file, copy an existing layout that + is similar to yours, then modify it to use the correct keys. The + layout is an array in ASCII order. Each entry contains a scan code, + possibly modified by "|SHIFT" or "|ALT_GR", as in this excerpt from + the Italian layout: + + 0x35, // bslash + 0x30|ALT_GR, // ] + 0x2e|SHIFT, // ^ + + Do not change the control characters (those before scan code 0x2c, + corresponding to space). Do not attempt to grow the table past DEL. Do + not use both SHIFT and ALT_GR on the same character: this is not + supported. Unsupported characters should have 0x00 as scan code. + + For a keyboard with an ISO physical layout, use the scan codes below: + + +---+---+---+---+---+---+---+---+---+---+---+---+---+-------+ + |35 |1e |1f |20 |21 |22 |23 |24 |25 |26 |27 |2d |2e |BackSp | + +---+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-----+ + | Tab |14 |1a |08 |15 |17 |1c |18 |0c |12 |13 |2f |30 | Ret | + +-----++--++--++--++--++--++--++--++--++--++--++--++--++ | + |CapsL |04 |16 |07 |09 |0a |0b |0d |0e |0f |33 |34 |31 | | + +----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+----+ + |Shi.|32 |1d |1b |06 |19 |05 |11 |10 |36 |37 |38 | Shift | + +----+---++--+-+-+---+---+---+---+---+--++---+---++----+----+ + |Ctrl|Win |Alt | |AlGr|Win |Menu|Ctrl| + +----+----+----+------------------------+----+----+----+----+ + + The ANSI layout is identical except that key 0x31 is above (rather + than next to) Return, and there is not key 0x32. + + Give a unique name to the layout array, then declare it in Keyboard.h + with a line of the form: + + extern const uint8_t KeyboardLayout_xx_YY[]; + + == Encoding details == + + All scan codes are less than 0x80, which makes bit 7 available to + signal that a modifier (Shift or AltGr) is needed to generate the + character. With only one exception, keys that are used with modifiers + have scan codes that are less than 0x40. This makes bit 6 available + to signal whether the modifier is Shift or AltGr. The exception is + 0x64, the key next next to Left Shift on the ISO layout (and absent + from the ANSI layout). We handle it by replacing its value by 0x32 in + the layout arrays. +*/ + +#include + +// Modifier keys for _asciimap[] table (not to be used directly) +#define SHIFT 0x80 +#define ALT_GR 0x40 +#define ISO_KEY 0x64 +#define ISO_REPLACEMENT 0x32 diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp new file mode 100644 index 0000000..7de2e1f --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp @@ -0,0 +1,137 @@ +/* + * Danish keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_da_DK[128] = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x20 | SHIFT, // # + 0x21 | ALT_GR, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x31, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x31 | SHIFT, // * + 0x2d, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x1f | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x25 | ALT_GR, // [ + 0x32 | ALT_GR, // bslash + 0x26 | ALT_GR, // ] + 0x00, // ^ not supported (requires dead key + space) + 0x38 | SHIFT, // _ + 0x00, // ` not supported (requires dead key + space) + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x24 | ALT_GR, // { + 0x2e | ALT_GR, // | + 0x27 | ALT_GR, // } + 0x00, // ~ not supported (requires dead key + space) + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp new file mode 100644 index 0000000..0e43016 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp @@ -0,0 +1,137 @@ +/* + * German keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_de_DE[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x31, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x31 | SHIFT, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x30 | SHIFT, // * + 0x30, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x14 | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1d | SHIFT, // Y + 0x1c | SHIFT, // Z + 0x25 | ALT_GR, // [ + 0x2d | ALT_GR, // bslash + 0x26 | ALT_GR, // ] + 0x00, // ^ not supported (requires dead key + space) + 0x38 | SHIFT, // _ + 0x00, // ` not supported (requires dead key + space) + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1d, // y + 0x1c, // z + 0x24 | ALT_GR, // { + 0x32 | ALT_GR, // | + 0x27 | ALT_GR, // } + 0x30 | ALT_GR, // ~ + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp new file mode 100644 index 0000000..36a961e --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp @@ -0,0 +1,137 @@ +/* + * Standard US keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_en_US[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x34 | SHIFT, // " + 0x20 | SHIFT, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x24 | SHIFT, // & + 0x34, // ' + 0x26 | SHIFT, // ( + 0x27 | SHIFT, // ) + 0x25 | SHIFT, // * + 0x2e | SHIFT, // + + 0x36, // , + 0x2d, // - + 0x37, // . + 0x38, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x33 | SHIFT, // : + 0x33, // ; + 0x36 | SHIFT, // < + 0x2e, // = + 0x37 | SHIFT, // > + 0x38 | SHIFT, // ? + 0x1f | SHIFT, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x2f, // [ + 0x31, // bslash + 0x30, // ] + 0x23 | SHIFT, // ^ + 0x2d | SHIFT, // _ + 0x35, // ` + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x2f | SHIFT, // { + 0x31 | SHIFT, // | + 0x30 | SHIFT, // } + 0x35 | SHIFT, // ~ + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp new file mode 100644 index 0000000..dac69cb --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp @@ -0,0 +1,137 @@ +/* + * Spanish keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_es_ES[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x20 | ALT_GR, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x2d, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x30 | SHIFT, // * + 0x30, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x1f | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x2f | ALT_GR, // [ + 0x35 | ALT_GR, // bslash + 0x30 | ALT_GR, // ] + 0x00, // ^ not supported (requires dead key + space) + 0x38 | SHIFT, // _ + 0x00, // ` not supported (requires dead key + space) + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x34 | ALT_GR, // { + 0x1e | ALT_GR, // | + 0x31 | ALT_GR, // } + 0x00, // ~ not supported (requires dead key + space) + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp new file mode 100644 index 0000000..8728417 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp @@ -0,0 +1,137 @@ +/* + * Traditional (not AFNOR) French keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_fr_FR[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x38, // ! + 0x20, // " + 0x20 | ALT_GR, // # + 0x30, // $ + 0x34 | SHIFT, // % + 0x1E, // & + 0x21, // ' + 0x22, // ( + 0x2d, // ) + 0x31, // * + 0x2e | SHIFT, // + + 0x10, // , + 0x23, // - + 0x36 | SHIFT, // . + 0x37 | SHIFT, // / + 0x27 | SHIFT, // 0 + 0x1e | SHIFT, // 1 + 0x1f | SHIFT, // 2 + 0x20 | SHIFT, // 3 + 0x21 | SHIFT, // 4 + 0x22 | SHIFT, // 5 + 0x23 | SHIFT, // 6 + 0x24 | SHIFT, // 7 + 0x25 | SHIFT, // 8 + 0x26 | SHIFT, // 9 + 0x37, // : + 0x36, // ; + 0x32, // < + 0x2e, // = + 0x32 | SHIFT, // > + 0x10 | SHIFT, // ? + 0x27 | ALT_GR, // @ + 0x14 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x33 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x04 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1d | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1a | SHIFT, // Z + 0x22 | ALT_GR, // [ + 0x25 | ALT_GR, // bslash + 0x2d | ALT_GR, // ] + 0x26 | ALT_GR, // ^ + 0x25, // _ + 0x24 | ALT_GR, // ` + 0x14, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x33, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x04, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1d, // w + 0x1b, // x + 0x1c, // y + 0x1a, // z + 0x21 | ALT_GR, // { + 0x23 | ALT_GR, // | + 0x2e | ALT_GR, // } + 0x1f | ALT_GR, // ~ + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp new file mode 100644 index 0000000..ff4344a --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp @@ -0,0 +1,143 @@ +/* + * Standard HU keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_hu_HU[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x21 | SHIFT, // ! + 0x1f | SHIFT, // " + 0x1b | ALT_GR, // # + 0x33 | ALT_GR, // $ + 0x22 | SHIFT, // % + 0x06 | ALT_GR, // & + 0x1e | SHIFT, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x38 | ALT_GR, // * + 0x20 | SHIFT, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x23 | SHIFT, // / + + 0x35, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + + 0x37 | SHIFT, // : + 0x36 | ALT_GR, // ; + 0x32 | ALT_GR, // < + 0x24 | SHIFT, // = + 0x1d | ALT_GR, // > + 0x36 | SHIFT, // ? + 0x19 | ALT_GR, // @ + + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1d | SHIFT, // Y + 0x1c | SHIFT, // Z + + 0x09 | ALT_GR, // [ + 0x14 | ALT_GR, // bslash + 0x0a | ALT_GR, // ] + 0x20 | ALT_GR, // ^ + 0x38 | SHIFT, // _ + 0x24 | ALT_GR, // ` + + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1d, // y + 0x1c, // z + + 0x05 | ALT_GR, // { + 0x1a | ALT_GR, // | + 0x11 | ALT_GR, // } + 0x1e | ALT_GR, // ~ + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp new file mode 100644 index 0000000..60a46bc --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp @@ -0,0 +1,137 @@ +/* + * Italian keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_it_IT[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x34 | ALT_GR, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x2d, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x30 | SHIFT, // * + 0x30, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x33 | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x2f | ALT_GR, // [ + 0x35, // bslash + 0x30 | ALT_GR, // ] + 0x2e | SHIFT, // ^ + 0x38 | SHIFT, // _ + 0x00, // ` not in this layout + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x00, // { not supported (requires AltGr+Shift) + 0x35 | SHIFT, // | + 0x00, // } not supported (requires AltGr+Shift) + 0x00, // ~ not in this layout + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp new file mode 100644 index 0000000..09014a7 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: Apache-2.0 + * + * Keyboard_pt_BR.h + * Portuguese Brazilian keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_pt_BR[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x35 | SHIFT, // " + 0x20 | SHIFT, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x24 | SHIFT, // & + 0x35, // ' + 0x26 | SHIFT, // ( + 0x27 | SHIFT, // ) + 0x25 | SHIFT, // * + 0x2e | SHIFT, // + + 0x36, // , + 0x2d, // - + 0x37, // . + 0x14 | ALT_GR, // / R_ALT + q + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x38 | SHIFT, // : + 0x38, // ; + 0x36 | SHIFT, // < + 0x2e, // = + 0x37 | SHIFT, // > + 0x1a | ALT_GR, // ? R_ALT + w + 0x1f | SHIFT, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x30, // [ + 0x32, // bslash -->ISO Key + 0x31, // ] + 0x34 | SHIFT, // ^ + 0x2d | SHIFT, // _ + 0x2f | SHIFT, // ` + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x30 | SHIFT, // { + 0x32 | SHIFT, // | -->ISO Key + 0x31 | SHIFT, // } + 0x34, // ~ + 0x4c // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp new file mode 100644 index 0000000..4f0c53d --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp @@ -0,0 +1,137 @@ +/* + * Portuguese keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_pt_PT[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x20 | SHIFT, // # + 0x21 | SHIFT, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x2d, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x2f | SHIFT, // * + 0x2f, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x1f | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x25 | ALT_GR, // [ + 0x35, // bslash + 0x26 | ALT_GR, // ] + 0x00, // ^ not supported (requires dead key + space) + 0x38 | SHIFT, // _ + 0x00, // ` not supported (requires dead key + space) + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x24 | ALT_GR, // { + 0x35 | SHIFT, // | + 0x27 | ALT_GR, // } + 0x00, // ~ not supported (requires dead key + space) + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp new file mode 100644 index 0000000..8ef92c1 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp @@ -0,0 +1,137 @@ +/* + * Swedish keyboard layout. + */ + +#include "KeyboardLayout.h" + +extern const uint8_t KeyboardLayout_sv_SE[128] PROGMEM = { + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e | SHIFT, // ! + 0x1f | SHIFT, // " + 0x20 | SHIFT, // # + 0x21 | ALT_GR, // $ + 0x22 | SHIFT, // % + 0x23 | SHIFT, // & + 0x31, // ' + 0x25 | SHIFT, // ( + 0x26 | SHIFT, // ) + 0x31 | SHIFT, // * + 0x2d, // + + 0x36, // , + 0x38, // - + 0x37, // . + 0x24 | SHIFT, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x37 | SHIFT, // : + 0x36 | SHIFT, // ; + 0x32, // < + 0x27 | SHIFT, // = + 0x32 | SHIFT, // > + 0x2d | SHIFT, // ? + 0x1f | ALT_GR, // @ + 0x04 | SHIFT, // A + 0x05 | SHIFT, // B + 0x06 | SHIFT, // C + 0x07 | SHIFT, // D + 0x08 | SHIFT, // E + 0x09 | SHIFT, // F + 0x0a | SHIFT, // G + 0x0b | SHIFT, // H + 0x0c | SHIFT, // I + 0x0d | SHIFT, // J + 0x0e | SHIFT, // K + 0x0f | SHIFT, // L + 0x10 | SHIFT, // M + 0x11 | SHIFT, // N + 0x12 | SHIFT, // O + 0x13 | SHIFT, // P + 0x14 | SHIFT, // Q + 0x15 | SHIFT, // R + 0x16 | SHIFT, // S + 0x17 | SHIFT, // T + 0x18 | SHIFT, // U + 0x19 | SHIFT, // V + 0x1a | SHIFT, // W + 0x1b | SHIFT, // X + 0x1c | SHIFT, // Y + 0x1d | SHIFT, // Z + 0x25 | ALT_GR, // [ + 0x2d | ALT_GR, // bslash + 0x26 | ALT_GR, // ] + 0x00, // ^ not supported (requires dead key + space) + 0x38 | SHIFT, // _ + 0x00, // ` not supported (requires dead key + space) + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x24 | ALT_GR, // { + 0x32 | ALT_GR, // | + 0x27 | ALT_GR, // } + 0x00, // ~ not supported (requires dead key + space) + 0x00 // DEL +}; diff --git a/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h b/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h new file mode 100644 index 0000000..8ad1540 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h @@ -0,0 +1,35 @@ +/* + Keyboard_da_DK.h + + Copyright (c) 2021, Peter John + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_DA_DK_h +#define KEYBOARD_DA_DK_h + +//================================================================================ +//================================================================================ +// Keyboard + +// DA_DK keys +#define KEY_A_RING (0x88 + 0x2f) +#define KEY_SLASHED_O (0x88 + 0x34) +#define KEY_ASH (0x88 + 0x33) +#define KEY_UMLAUT (0x88 + 0x30) +#define KEY_ACUTE_ACC (0x88 + 0x2e) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h b/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h new file mode 100644 index 0000000..8fec4e1 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h @@ -0,0 +1,36 @@ +/* + Keyboard_de_DE.h + + Copyright (c) 2022, Edgar Bonet + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_DE_DE_h +#define KEYBOARD_DE_DE_h + +//================================================================================ +//================================================================================ +// Keyboard + +// de_DE keys +#define KEY_CIRCUMFLEX (0x88 + 0x35) +#define KEY_ESZETT (0x88 + 0x2d) +#define KEY_ACUTE (0x88 + 0x2e) +#define KEY_U_UMLAUT (0x88 + 0x2f) +#define KEY_O_UMLAUT (0x88 + 0x33) +#define KEY_A_UMLAUT (0x88 + 0x34) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h b/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h new file mode 100644 index 0000000..25f7c01 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h @@ -0,0 +1,37 @@ +/* + Keyboard_es_ES.h + + Copyright (c) 2022, Edgar Bonet + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_ES_ES_h +#define KEYBOARD_ES_ES_h + +#include "class/hid/hid.h" +//================================================================================ +//================================================================================ +// Keyboard + +// es_ES keys +#define KEY_MASCULINE_ORDINAL (0x88 + 0x35) +#define KEY_INVERTED_EXCLAMATION (0x88 + 0x2e) +#define KEY_GRAVE (0x88 + 0x2f) +#define KEY_N_TILDE (0x88 + 0x33) +#define KEY_ACUTE (0x88 + 0x34) +#define KEY_C_CEDILLA (0x88 + 0x31) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h b/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h new file mode 100644 index 0000000..d5d9fa8 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h @@ -0,0 +1,37 @@ +/* + Keyboard_fr_FR.h + + Copyright (c) 2022, Edgar Bonet + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_FR_FR_h +#define KEYBOARD_FR_FR_h + +//================================================================================ +//================================================================================ +// Keyboard + +// fr_FR keys +#define KEY_SUPERSCRIPT_TWO (0x88 + 0x35) +#define KEY_E_ACUTE (0x88 + 0x1f) +#define KEY_E_GRAVE (0x88 + 0x24) +#define KEY_C_CEDILLA (0x88 + 0x26) +#define KEY_A_GRAVE (0x88 + 0x27) +#define KEY_CIRCUMFLEX (0x88 + 0x2f) +#define KEY_U_GRAVE (0x88 + 0x34) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h b/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h new file mode 100644 index 0000000..b021431 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h @@ -0,0 +1,43 @@ +/* + Keyboard_hu_HU.h + + Copyright (c) 2023, Barab(0x34)si Rich(0x34)rd + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_HU_HU_h +#define KEYBOARD_HU_HU_h + +//================================================================================ +//================================================================================ +// Keyboard + +// hu_HU keys +#define KEY_O_ACUTE (0x88 + 0x2e) +#define KEY_O_UMLAUT (0x88 + 0x27) +#define KEY_O_DOUBLE_ACUTE (0x88 + 0x2f) + +#define KEY_U_ACUTE (0x88 + 0x30) +#define KEY_U_UMLAUT (0x88 + 0x2d) +#define KEY_U_DOUBLE_ACUTE (0x88 + 0x31) + +#define KEY_A_ACUTE (0x88 + 0x34) + +#define KEY_E_ACUTE (0x88 + 0x33) + +#define KEY_I_ACUTE (0x88 + 0x32) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h b/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h new file mode 100644 index 0000000..41b52c8 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h @@ -0,0 +1,35 @@ +/* + Keyboard_it_IT.h + + Copyright (c) 2022, Edgar Bonet + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_IT_IT_h +#define KEYBOARD_IT_IT_h + +//================================================================================ +//================================================================================ +// Keyboard + +// it_IT keys +#define KEY_I_GRAVE (0x88 + 0x2e) +#define KEY_E_GRAVE (0x88 + 0x2f) +#define KEY_O_GRAVE (0x88 + 0x33) +#define KEY_A_GRAVE (0x88 + 0x34) +#define KEY_U_GRAVE (0x88 + 0x31) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h b/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h new file mode 100644 index 0000000..6b597e5 --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-License-Identifier: Apache-2.0 + * + * Keyboard_pt_BR.h + * Portuguese Brazilian keyboard layout. +*/ + +#ifndef KEYBOARD_PT_BR_h +#define KEYBOARD_PT_BR_h + +//================================================================================ +//================================================================================ +// Keyboard + +// pt_BR keys +#define KEY_C_CEDILLA (0x88 + 0x33) +#define KEY_ACUTE (0x88 + 0x2f) +// use the pressRaw() to press the modification key and then press the key you want to modify +#define KEY_MASCULINE_ORDINAL (0x88 + 0x32) // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_MASCULINE_ORDINAL) +#define KEY_FEMININE_ORDINAL (0x88 + 0x30) // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_FEMININE_ORDINAL) +#define KEY_PARAGRAPH (0x88 + 0x2e) // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_PARAGRAPH) +#define KEY_UMLAUT (0x88 + 0x23) // first pressRaw(HID_KEY_SHIFT_RIGHT), then press(KEY_UMLAUT) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h b/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h new file mode 100644 index 0000000..c1a2dbf --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h @@ -0,0 +1,35 @@ +/* + Keyboard_pt_PT.h + + Copyright (c) 2022, Edgar Bonet + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_PT_PT_h +#define KEYBOARD_PT_PT_h + +//================================================================================ +//================================================================================ +// Keyboard + +// pt_PT keys +#define KEY_LEFT_GUILLEMET (0x88 + 0x2e) +#define KEY_ACUTE (0x88 + 0x30) +#define KEY_C_CEDILLA (0x88 + 0x33) +#define KEY_MASCULINE_ORDINAL (0x88 + 0x34) +#define KEY_TILDE (0x88 + 0x31) + +#endif diff --git a/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h b/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h new file mode 100644 index 0000000..1a3e3bc --- /dev/null +++ b/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h @@ -0,0 +1,35 @@ +/* + Keyboard_sv_SE.h + + Copyright (c) 2021, Peter John + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef KEYBOARD_SV_SE_h +#define KEYBOARD_SV_SE_h + +//================================================================================ +//================================================================================ +// Keyboard + +// SV_SE keys +#define KEY_A_RING (0x88 + 0x2f) +#define KEY_A_UMLAUT (0x88 + 0x34) +#define KEY_O_UMLAUT (0x88 + 0x33) +#define KEY_UMLAUT (0x88 + 0x30) +#define KEY_ACUTE_ACC (0x88 + 0x2e) + +#endif diff --git a/libraries/Update/README.md b/libraries/Update/README.md new file mode 100644 index 0000000..7483cb3 --- /dev/null +++ b/libraries/Update/README.md @@ -0,0 +1,431 @@ +# ESP32 Arduino Update Library + +The Update library provides functionality for Over-The-Air (OTA) firmware updates on ESP32 devices. It supports secure updates with signature verification, encrypted updates, and various update sources. + +## Features + +- **OTA Updates**: Update firmware over Wi-Fi +- **Signature Verification**: RSA and ECDSA signature verification for secure updates (optional, must be enabled with `UPDATE_SIGN`) +- **Image Encryption**: Support for encrypted firmware updates (optional, can be disabled with `UPDATE_NOCRYPT`) +- **Multiple Sources**: HTTP, HTTPS, SD card, and custom sources +- **Progress Callbacks**: Monitor update progress +- **MD5 Verification**: Optional MD5 checksum verification + +## Quick Start + +### Basic OTA Update + +```cpp +#include + +WiFiClient client; +size_t updateSize = client.available(); + +if (Update.begin(updateSize)) { + Update.writeStream(client); + if (Update.end()) { + Serial.println("Update successful!"); + ESP.restart(); + } else { + Serial.println("Update failed!"); + } +} +``` + +### Signed OTA Update (Recommended) + +To enable signature verification, add `-DUPDATE_SIGN` to your build flags (e.g., in `build_opt.h`): +``` +-DUPDATE_SIGN +``` + +Then in your sketch: +```cpp +#include + +// Include your public key (generated with bin_signing.py) +#include "public_key.h" + +// Create verifier object (defaults to SHA-256) +UpdaterRSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN); + +// Install signature verification BEFORE Update.begin() +Update.installSignature(&sign); + +// Now perform the update as usual +if (Update.begin(updateSize)) { + Update.writeStream(client); + if (Update.end()) { + // Signature was verified successfully! + Serial.println("Signed update successful!"); + ESP.restart(); + } else { + if (Update.getError() == UPDATE_ERROR_SIGN) { + Serial.println("Signature verification failed!"); + } + } +} +``` + +## Signature Verification + +### Overview + +Code signing ensures that only firmware signed with your private key will be accepted by your devices. This protects against: + +- Unauthorized firmware updates +- Man-in-the-middle attacks +- Compromised update servers +- Supply chain attacks + +### Supported Algorithms + +**Signature Schemes:** +- RSA-2048, RSA-3072, RSA-4096 +- ECDSA-P256, ECDSA-P384 + +**Hash Algorithms:** +- SHA-256, SHA-384, SHA-512 + +### Setup + +1. **Generate Key Pair:** + +```bash +# RSA-2048 (recommended) +python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem +python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem + +# ECDSA-P256 (smaller, faster) +python /tools/bin_signing.py --generate-key ecdsa-p256 --out private_key.pem +python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +``` + +2. **Include Public Key in Sketch:** + +```cpp +#include "public_key.h" // Generated by bin_signing.py +``` + +3. **Install Signature Verification:** + +Enable the feature by adding to `build_opt.h`: +``` +-DUPDATE_SIGN +``` + +Then in your sketch: +```cpp +// For RSA with SHA-256 +UpdaterRSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, HASH_SHA256); +Update.installSignature(&sign); + +// For ECDSA with SHA-384 +UpdaterECDSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, HASH_SHA384); +Update.installSignature(&sign); +``` + +4. **Sign Your Firmware:** + +```bash +python /tools/bin_signing.py --bin --key private_key.pem --out firmware_signed.bin --hash +``` + +5. **Upload Signed Application Firmware:** + +The signed firmware includes the signature appended to the binary. Upload the newly created signed firmware instead of the original application binary. + +### Security Best Practices + +1. **Protect Your Private Key:** + - Never commit it to version control + - Store it in secure, encrypted storage + - Limit access to authorized personnel only + - Consider using HSM for production + +2. **Use HTTPS:** + - While signature verification protects integrity, HTTPS protects confidentiality + +## API Reference + +### UpdateClass Methods + +#### begin() +```cpp +bool begin(size_t size = UPDATE_SIZE_UNKNOWN, + int command = U_FLASH, + int ledPin = -1, + uint8_t ledOn = LOW, + const char *label = NULL) +``` +Starts an update operation. + +**Parameters:** +- `size`: Size of the update in bytes (including signature if using signed updates) +- `command`: Update type (U_FLASH, U_SPIFFS, U_FATFS, U_LITTLEFS) +- `ledPin`: Optional LED pin to indicate progress +- `ledOn`: LED on state (LOW or HIGH) +- `label`: Optional partition label + +**Returns:** `true` on success, `false` on failure + +#### installSignature() +```cpp +bool installSignature(UpdaterVerifyClass *sign) +``` +Installs signature verification. Must be called before `begin()`. + +**Parameters:** +- `sign`: Signature verifier (UpdaterRSAVerifier or UpdaterECDSAVerifier) + +**Returns:** `true` on success, `false` on failure + +#### write() +```cpp +size_t write(uint8_t *data, size_t len) +``` +Writes data to the update. + +**Parameters:** +- `data`: Data buffer +- `len`: Length of data + +**Returns:** Number of bytes written + +#### writeStream() +```cpp +size_t writeStream(Stream &data) +``` +Writes data from a stream. + +**Parameters:** +- `data`: Input stream + +**Returns:** Number of bytes written + +#### end() +```cpp +bool end(bool evenIfRemaining = false) +``` +Completes the update and verifies signature if enabled. + +**Parameters:** +- `evenIfRemaining`: Complete even if not all data was written + +**Returns:** `true` if update succeeded and signature is valid, `false` otherwise + +#### abort() +```cpp +void abort() +``` +Aborts the current update. + +#### setMD5() +```cpp +bool setMD5(const char *expected_md5) +``` +Sets expected MD5 hash for verification. + +**Parameters:** +- `expected_md5`: MD5 hash as hex string (32 characters) + +**Returns:** `true` on success, `false` on failure + +#### getError() +```cpp +uint8_t getError() +``` +Returns the last error code. + +**Returns:** Error code (see Error Codes below) + +#### errorString() +```cpp +const char *errorString() +``` +Returns a human-readable error message. + +**Returns:** Error message string + +### Hash Classes (from Hash Library) + +The Update library uses the Hash library for hashing. Simply use the builders from that library: + +```cpp +#include + +SHA256Builder hash256; // SHA-256 +SHA384Builder hash384; // SHA-384 +SHA512Builder hash512; // SHA-512 +``` + +See the [Hash library documentation](../Hash/README.md) for more details. + +### Signature Verifier Classes + +#### UpdaterRSAVerifier +RSA signature verifier. + +```cpp +UpdaterRSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType = HASH_SHA256) +``` + +**Parameters:** +- `pubkey`: Public key in PEM format +- `pubkeyLen`: Length of public key +- `hashType`: Hash algorithm (`HASH_SHA256`, `HASH_SHA384`, or `HASH_SHA512`). Defaults to `HASH_SHA256`. + +#### UpdaterECDSAVerifier +ECDSA signature verifier. + +```cpp +UpdaterECDSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType = HASH_SHA256) +``` + +**Parameters:** +- `pubkey`: Public key in PEM format +- `pubkeyLen`: Length of public key +- `hashType`: Hash algorithm (`HASH_SHA256`, `HASH_SHA384`, or `HASH_SHA512`). Defaults to `HASH_SHA256`. + +### Error Codes + +| Code | Name | Description | +|------|------|-------------| +| 0 | UPDATE_ERROR_OK | No error | +| 1 | UPDATE_ERROR_WRITE | Flash write failed | +| 2 | UPDATE_ERROR_ERASE | Flash erase failed | +| 3 | UPDATE_ERROR_READ | Flash read failed | +| 4 | UPDATE_ERROR_SPACE | Not enough space | +| 5 | UPDATE_ERROR_SIZE | Bad size given | +| 6 | UPDATE_ERROR_STREAM | Stream read timeout | +| 7 | UPDATE_ERROR_MD5 | MD5 check failed | +| 8 | UPDATE_ERROR_MAGIC_BYTE | Wrong magic byte | +| 9 | UPDATE_ERROR_ACTIVATE | Could not activate firmware | +| 10 | UPDATE_ERROR_NO_PARTITION | Partition not found | +| 11 | UPDATE_ERROR_BAD_ARGUMENT | Bad argument | +| 12 | UPDATE_ERROR_ABORT | Aborted | +| 13 | UPDATE_ERROR_DECRYPT | Decryption error | +| 14 | UPDATE_ERROR_SIGN | Signature verification failed | + +## Examples + +- **Signed_OTA_Update**: Demonstrates signed OTA updates with RSA/ECDSA +- **HTTPS_OTA_Update**: HTTPS OTA update +- **HTTP_Client_AES_OTA_Update**: Encrypted OTA update +- **SD_Update**: Update from SD card + +See the `examples/` directory for complete examples. + +## Tools + +### bin_signing.py + +Python script for key generation and firmware signing. Located in `/tools/bin_signing.py`. + +**Requirements:** +```bash +pip install cryptography +``` + +**Usage:** +```bash +# Generate keys +python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem +python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem + +# Sign firmware (defaults to SHA-256) +python /tools/bin_signing.py --bin firmware.bin --key private_key.pem --out firmware_signed.bin + +# Sign firmware with SHA-384 +python /tools/bin_signing.py --bin firmware.bin --key private_key.pem --out firmware_signed.bin --hash sha384 + +# Verify signature +python /tools/bin_signing.py --verify firmware_signed.bin --pubkey public_key.pem +``` + +See `/tools/bin_signing.py --help` for more options. + +## Troubleshooting + +### "Signature verification failed" + +- Ensure firmware was signed with correct private key +- Verify public key in sketch matches private key +- Check signature scheme and hash algorithm match +- Verify signed binary wasn't corrupted + +### "Failed to install signature verification" + +- Call `installSignature()` before `Update.begin()` +- Ensure hash and sign objects are properly initialized + +### "Update failed" with no specific error + +- Check firmware size is correct (including signature) +- Ensure enough space in target partition +- Verify magic byte (0xE9) at start of firmware + +### Memory Issues + +- Signature verification requires ~2KB of heap +- RSA-4096 uses more memory than ECDSA-P256 +- Ensure sufficient free heap before starting update + +## Compile-Time Options + +The Update library supports compile-time configuration to reduce code size if certain features are not needed: + +### UPDATE_SIGN + +Enable signature verification support (disabled by default). + +Add to your project's `build_opt.h`: +``` +-DUPDATE_SIGN +``` + +Or add to your build flags in `platformio.ini`: +```ini +build_flags = -DUPDATE_SIGN +``` + +**Effects:** +- Enables signature verification classes and methods +- Adds RSA and ECDSA signature verification support +- `installSignature()` method becomes available +- Increases code size due to mbedtls cryptographic functions + +### UPDATE_NOCRYPT + +Disable encryption/decryption support: + +```cpp +#define UPDATE_NOCRYPT +#include +``` + +**Effects:** +- Removes AES encryption support +- Reduces code size +- `setupCrypt()` and related methods will not be available + +**Note:** To enable signature verification while disabling encryption, add to `build_opt.h`: +``` +-DUPDATE_SIGN +-DUPDATE_NOCRYPT +``` + +## License + +This library is part of the Arduino-ESP32 project and is licensed under the Apache License 2.0. + +## Contributing + +Contributions are welcome! Please submit issues and pull requests on GitHub: +https://github.com/espressif/arduino-esp32 + +## Support + +- Documentation: https://docs.espressif.com/ +- Forum: https://esp32.com/ +- GitHub Issues: https://github.com/espressif/arduino-esp32/issues diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino b/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino new file mode 100644 index 0000000..08c0a5a --- /dev/null +++ b/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino @@ -0,0 +1,280 @@ +/** + AWS S3 OTA Update + Date: 14th June 2017 + Author: Arvind Ravulavaru + Purpose: Perform an OTA update from a bin located in Amazon S3 (HTTP Only) + + Upload: + Step 1 : Download the sample bin file from the examples folder + Step 2 : Upload it to your Amazon S3 account, in a bucket of your choice + Step 3 : Once uploaded, inside S3, select the bin file >> More (button on top of the file list) >> Make Public + Step 4 : You S3 URL => http://bucket-name.s3.ap-south-1.amazonaws.com/sketch-name.ino.bin + Step 5 : Build the above URL and fire it either in your browser or curl it `curl -I -v http://bucket-name.ap-south-1.amazonaws.com/sketch-name.ino.bin` to validate the same + Step 6: Plug in your SSID, Password, S3 Host and Bin file below + + Build & upload + Step 1 : Menu > Sketch > Export Compiled Library. The bin file will be saved in the sketch folder (Menu > Sketch > Show Sketch folder) + Step 2 : Upload bin to S3 and continue the above process + + // Check the bottom of this sketch for sample serial monitor log, during and after successful OTA Update +*/ + +#include +#include + +NetworkClient client; + +// Variables to validate +// response from S3 +long contentLength = 0; +bool isValidContentType = false; + +// Your SSID and PSWD that the chip needs +// to connect to +const char *SSID = "YOUR-SSID"; +const char *PSWD = "YOUR-SSID-PSWD"; + +// S3 Bucket Config +String host = "bucket-name.s3.ap-south-1.amazonaws.com"; // Host => bucket-name.s3.region.amazonaws.com +int port = 80; // Non https. For HTTPS 443. As of today, HTTPS doesn't work. +String bin = "/sketch-name.ino.bin"; // bin file name with a slash in front. + +// Utility to extract header value from headers +String getHeaderValue(String header, String headerName) { + return header.substring(strlen(headerName.c_str())); +} + +// OTA Logic +void execOTA() { + Serial.println("Connecting to: " + String(host)); + // Connect to S3 + if (client.connect(host.c_str(), port)) { + // Connection Succeed. + // Fetching the bin + Serial.println("Fetching Bin: " + String(bin)); + + // Get the contents of the bin file + client.print(String("GET ") + bin + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "Cache-Control: no-cache\r\n" + "Connection: close\r\n\r\n"); + + // Check what is being sent + // Serial.print(String("GET ") + bin + " HTTP/1.1\r\n" + + // "Host: " + host + "\r\n" + + // "Cache-Control: no-cache\r\n" + + // "Connection: close\r\n\r\n"); + + unsigned long timeout = millis(); + while (client.available() == 0) { + if (millis() - timeout > 5000) { + Serial.println("Client Timeout !"); + client.stop(); + return; + } + } + // Once the response is available, + // check stuff + + /* + Response Structure + HTTP/1.1 200 OK + x-amz-id-2: NVKxnU1aIQMmpGKhSwpCBh8y2JPbak18QLIfE+OiUDOos+7UftZKjtCFqrwsGOZRN5Zee0jpTd0= + x-amz-request-id: 2D56B47560B764EC + Date: Wed, 14 Jun 2017 03:33:59 GMT + Last-Modified: Fri, 02 Jun 2017 14:50:11 GMT + ETag: "d2afebbaaebc38cd669ce36727152af9" + Accept-Ranges: bytes + Content-Type: application/octet-stream + Content-Length: 357280 + Server: AmazonS3 + + {{BIN FILE CONTENTS}} + + */ + while (client.available()) { + // read line till /n + String line = client.readStringUntil('\n'); + // remove space, to check if the line is end of headers + line.trim(); + + // if the the line is empty, + // this is end of headers + // break the while and feed the + // remaining `client` to the + // Update.writeStream(); + if (!line.length()) { + //headers ended + break; // and get the OTA started + } + + // Check if the HTTP Response is 200 + // else break and Exit Update + if (line.startsWith("HTTP/1.1")) { + if (line.indexOf("200") < 0) { + Serial.println("Got a non 200 status code from server. Exiting OTA Update."); + break; + } + } + + // extract headers here + // Start with content length + if (line.startsWith("Content-Length: ")) { + contentLength = atol((getHeaderValue(line, "Content-Length: ")).c_str()); + Serial.println("Got " + String(contentLength) + " bytes from server"); + } + + // Next, the content type + if (line.startsWith("Content-Type: ")) { + String contentType = getHeaderValue(line, "Content-Type: "); + Serial.println("Got " + contentType + " payload."); + if (contentType == "application/octet-stream") { + isValidContentType = true; + } + } + } + } else { + // Connect to S3 failed + // May be try? + // Probably a choppy network? + Serial.println("Connection to " + String(host) + " failed. Please check your setup"); + // retry?? + // execOTA(); + } + + // Check what is the contentLength and if content type is `application/octet-stream` + Serial.println("contentLength : " + String(contentLength) + ", isValidContentType : " + String(isValidContentType)); + + // check contentLength and content type + if (contentLength && isValidContentType) { + // Check if there is enough to OTA Update + bool canBegin = Update.begin(contentLength); + + // If yes, begin + if (canBegin) { + Serial.println("Begin OTA. This may take 2 - 5 mins to complete. Things might be quite for a while.. Patience!"); + // No activity would appear on the Serial monitor + // So be patient. This may take 2 - 5mins to complete + size_t written = Update.writeStream(client); + + if (written == contentLength) { + Serial.println("Written : " + String(written) + " successfully"); + } else { + Serial.println("Written only : " + String(written) + "/" + String(contentLength) + ". Retry?"); + // retry?? + // execOTA(); + } + + if (Update.end()) { + Serial.println("OTA done!"); + if (Update.isFinished()) { + Serial.println("Update successfully completed. Rebooting."); + ESP.restart(); + } else { + Serial.println("Update not finished? Something went wrong!"); + } + } else { + Serial.println("Error Occurred. Error #: " + String(Update.getError())); + } + } else { + // not enough space to begin OTA + // Understand the partitions and + // space availability + Serial.println("Not enough space to begin OTA"); + client.clear(); + } + } else { + Serial.println("There was no content in the response"); + client.clear(); + } +} + +void setup() { + //Begin Serial + Serial.begin(115200); + delay(10); + + Serial.println("Connecting to " + String(SSID)); + + // Connect to provided SSID and PSWD + WiFi.begin(SSID, PSWD); + + // Wait for connection to establish + while (WiFi.status() != WL_CONNECTED) { + Serial.print("."); // Keep the serial monitor lit! + delay(500); + } + + // Connection Succeed + Serial.println(""); + Serial.println("Connected to " + String(SSID)); + + // Execute OTA Update + execOTA(); +} + +void loop() { + // chill +} + +/* + * Serial Monitor log for this sketch + * + * If the OTA succeeded, it would load the preference sketch, with a small modification. i.e. + * Print `OTA Update succeeded!! This is an example sketch : Preferences > StartCounter` + * And then keeps on restarting every 10 seconds, updating the preferences + * + * + rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) + configsip: 0, SPIWP:0x00 + clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 + mode:DIO, clock div:1 + load:0x3fff0008,len:8 + load:0x3fff0010,len:160 + load:0x40078000,len:10632 + load:0x40080000,len:252 + entry 0x40080034 + Connecting to SSID + ...... + Connected to SSID + Connecting to: bucket-name.s3.ap-south-1.amazonaws.com + Fetching Bin: /StartCounter.ino.bin + Got application/octet-stream payload. + Got 357280 bytes from server + contentLength : 357280, isValidContentType : 1 + Begin OTA. This may take 2 - 5 mins to complete. Things might be quite for a while.. Patience! + Written : 357280 successfully + OTA done! + Update successfully completed. Rebooting. + ets Jun 8 2016 00:22:57 + + rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) + configsip: 0, SPIWP:0x00 + clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 + mode:DIO, clock div:1 + load:0x3fff0008,len:8 + load:0x3fff0010,len:160 + load:0x40078000,len:10632 + load:0x40080000,len:252 + entry 0x40080034 + + OTA Update succeeded!! This is an example sketch : Preferences > StartCounter + Current counter value: 1 + Restarting in 10 seconds... + E (102534) wifi: esp_wifi_stop 802 wifi is not init + ets Jun 8 2016 00:22:57 + + rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) + configsip: 0, SPIWP:0x00 + clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 + mode:DIO, clock div:1 + load:0x3fff0008,len:8 + load:0x3fff0010,len:160 + load:0x40078000,len:10632 + load:0x40080000,len:252 + entry 0x40080034 + + OTA Update succeeded!! This is an example sketch : Preferences > StartCounter + Current counter value: 2 + Restarting in 10 seconds... + + .... + * + */ diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin b/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin new file mode 100644 index 0000000..4892698 Binary files /dev/null and b/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin differ diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/ci.yml b/libraries/Update/examples/AWS_S3_OTA_Update/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/AWS_S3_OTA_Update/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino b/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino new file mode 100644 index 0000000..af30bf7 --- /dev/null +++ b/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino @@ -0,0 +1,85 @@ +// This sketch provide the functionality of OTA Firmware Upgrade +#include "WiFi.h" +#include "HttpsOTAUpdate.h" +// This sketch shows how to implement HTTPS firmware update Over The Air. +// Please provide your WiFi credentials, https URL to the firmware image and the server certificate. + +static const char *ssid = "your-ssid"; // your network SSID (name of wifi network) +static const char *password = "your-password"; // your network password + +static const char *url = "https://example.com/firmware.bin"; //state url of your firmware image + +static const char *server_certificate = "-----BEGIN CERTIFICATE-----\n" + "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" + "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" + "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" + "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" + "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" + "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" + "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" + "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" + "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" + "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" + "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" + "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" + "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" + "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" + "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" + "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" + "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" + "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" + "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" + "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" + "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" + "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" + "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" + "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" + "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" + "-----END CERTIFICATE-----"; + +static HttpsOTAStatus_t otastatus; + +void HttpEvent(HttpEvent_t *event) { + switch (event->event_id) { + case HTTP_EVENT_ERROR: Serial.println("Http Event Error"); break; + case HTTP_EVENT_ON_CONNECTED: Serial.println("Http Event On Connected"); break; + case HTTP_EVENT_HEADER_SENT: Serial.println("Http Event Header Sent"); break; + case HTTP_EVENT_ON_HEADER: Serial.printf("Http Event On Header, key=%s, value=%s\n", event->header_key, event->header_value); break; + case HTTP_EVENT_ON_DATA: break; + case HTTP_EVENT_ON_FINISH: Serial.println("Http Event On Finish"); break; + case HTTP_EVENT_DISCONNECTED: Serial.println("Http Event Disconnected"); break; + case HTTP_EVENT_REDIRECT: Serial.println("Http Event Redirect"); break; + } +} + +void setup() { + + Serial.begin(115200); + Serial.print("Attempting to connect to SSID: "); + WiFi.begin(ssid, password); + + // attempt to connect to Wifi network: + while (WiFi.status() != WL_CONNECTED) { + Serial.print("."); + delay(1000); + } + + Serial.print("Connected to "); + Serial.println(ssid); + + HttpsOTA.onHttpEvent(HttpEvent); + Serial.println("Starting OTA"); + HttpsOTA.begin(url, server_certificate); + + Serial.println("Please Wait it takes some time ..."); +} + +void loop() { + otastatus = HttpsOTA.status(); + if (otastatus == HTTPS_OTA_SUCCESS) { + Serial.println("Firmware written successfully. To reboot device, call API ESP.restart() or PUSH restart button on device"); + } else if (otastatus == HTTPS_OTA_FAIL) { + Serial.println("Firmware Upgrade Fail"); + } + delay(1000); +} diff --git a/libraries/Update/examples/HTTPS_OTA_Update/Readme.md b/libraries/Update/examples/HTTPS_OTA_Update/Readme.md new file mode 100644 index 0000000..8a0a158 --- /dev/null +++ b/libraries/Update/examples/HTTPS_OTA_Update/Readme.md @@ -0,0 +1,32 @@ +# OTA Firmware Upgrade for Arduino +This sketch allows Arduino user to perform Over The Air (OTA) firmware upgrade. It uses HTTPS. + +# API introduced for OTA + +## HttpsOTA.begin(const char * url, const char * server_certificate, bool skip_cert_common_name_check) + +Main API which starts firmware upgrade + +### Parameters +* url : URL for the uploaded firmware image +* server_certificate : Provide the ota server certificate for authentication via HTTPS +* skip_cert_common_name_check : Skip any validation of server certificate CN field + +The default value provided to skip_cert_common_name_check is true + +## HttpsOTA.onHttpEvent(function) + +This API exposes HTTP Events to the user + +### Parameter +Function passed has following signature +void HttpEvent (HttpEvent_t * event); + +# HttpsOTA.otaStatus() + +It tracks the progress of OTA firmware upgrade. +* HTTPS_OTA_IDLE : OTA upgrade have not started yet. +* HTTPS_OTA_UPDATNG : OTA upgrade is in progress. +* HTTPS_OTA_SUCCESS : OTA upgrade is successful. +* HTTPS_OTA_FAIL : OTA upgrade failed. +* HTTPS_OTA_ERR : Error occurred while creating xEventGroup(). diff --git a/libraries/Update/examples/HTTPS_OTA_Update/ci.yml b/libraries/Update/examples/HTTPS_OTA_Update/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/HTTPS_OTA_Update/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino new file mode 100644 index 0000000..bd5070c --- /dev/null +++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino @@ -0,0 +1,330 @@ +/* +An example of how to use HTTPClient to download an encrypted and plain image files OTA from a web server. +This example uses Wifi & HTTPClient to connect to webserver and two functions for obtaining firmware image from webserver. +One uses the example 'updater.php' code on server to check and/or send relevant download firmware image file, +the other directly downloads the firmware file from web server. + +To use:- +Make a folder/directory on your webserver where your firmware images will be uploaded to. ie. /firmware +The 'updater.php' file can also be uploaded to the same folder. Edit and change definitions in 'update.php' to suit your needs. +In sketch: + set HTTPUPDATE_HOST to domain name or IP address if on LAN of your web server + set HTTPUPDATE_UPDATER_URI to path and file to call 'updater.php' +or set HTTPUPDATE_DIRECT_URI to path and firmware file to download + edit other HTTPUPDATE_ as needed + +Encrypted image will help protect your app image file from being copied and used on blank devices, encrypt your image file by using espressif IDF. +First install an app on device that has Update setup with the OTA decrypt mode on, same key, address and flash_crypt_conf as used in IDF to encrypt image file or vice versa. + +For easier development use the default U_AES_DECRYPT_AUTO decrypt mode. This mode allows both plain and encrypted app images to be uploaded. + +Note:- App image can also encrypted on device, by using espressif IDF to configure & enabled FLASH encryption, suggest the use of a different 'OTA_KEY' key for update from the eFuses 'flash_encryption' key used by device. + + ie. "Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG);" + +defaults:- {if not set ie. "Update.setupCrypt();" } + OTA_KEY = 0 ( 0 = no key, disables decryption ) + OTA_ADDRESS = 0 ( suggest dont set address to app0=0x10000 usually or app1=varies ) + OTA_CFG = 0xf + OTA_MODE = U_AES_DECRYPT_AUTO + +OTA_MODE options:- + U_AES_DECRYPT_NONE decryption disabled, loads OTA image files as sent(plain) + U_AES_DECRYPT_AUTO auto loads both plain & encrypted OTA FLASH image files, and plain OTA SPIFFS image files + U_AES_DECRYPT_ON decrypts OTA image files + +https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/ + +Example: + espsecure.py encrypt_flash_data -k ota_key.bin --flash_crypt_conf 0xf -a 0x4320 -o output_filename.bin source_filename.bin + +espsecure.py encrypt_flash_data = runs the idf encryption function to make a encrypted output file from a source file + -k text = path/filename to the AES 256bit(32byte) encryption key file + --flash_crypt_conf 0xn = 0x0 to 0xf, the more bits set the higher the security of encryption(address salting, 0x0 would use ota_key with no address salting) + -a 0xnnnnnn00 = 0x00 to 0x00fffff0 address offset(must be a multiple of 16, but better to use multiple of 32), used to offset the salting (has no effect when = --flash_crypt_conf 0x0) + -o text = path/filename to save encrypted output file to + text = path/filename to open source file from +*/ + +#include +#include +#include +#include +#include + +//========================================================================== +//========================================================================== +const char *WIFI_SSID = "wifi-ssid"; +const char *WIFI_PASSWORD = "wifi-password"; + +const uint8_t OTA_KEY[32] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, + 0x61, 0x20, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x74, 0x65, 0x73, 0x74, 0x20, 0x6b, 0x65, 0x79}; + +/* +const uint8_t OTA_KEY[32] = {'0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', ' ', 't', 'h', 'i', 's', ' ', + 'a', ' ', 's', 'i', 'm', 'p', 'l', 'e', + 't', 'e', 's', 't', ' ', 'k', 'e', 'y' }; +*/ + +//const uint8_t OTA_KEY[33] = "0123456789 this a simpletest key"; + +const uint32_t OTA_ADDRESS = 0x4320; +const uint32_t OTA_CFG = 0x0f; +const uint32_t OTA_MODE = U_AES_DECRYPT_AUTO; + +const char *HTTPUPDATE_USERAGRENT = "ESP32-Updater"; +//const char* HTTPUPDATE_HOST = "www.yourdomain.com"; +const char *HTTPUPDATE_HOST = "192.168.1.2"; +const uint16_t HTTPUPDATE_PORT = 80; +const char *HTTPUPDATE_UPDATER_URI = "/firmware/updater.php"; //uri to 'updater.php' +const char *HTTPUPDATE_DIRECT_URI = "/firmware/HTTP_Client_AES_OTA_Update-v1.1.xbin"; //uri to image file + +const char *HTTPUPDATE_USER = NULL; //use NULL if no authentication needed +//const char* HTTPUPDATE_USER = "user"; +const char *HTTPUPDATE_PASSWORD = "password"; + +const char *HTTPUPDATE_BRAND = "21"; /* Brand ID */ +const char *HTTPUPDATE_MODEL = "HTTP_Client_AES_OTA_Update"; /* Project name */ +const char *HTTPUPDATE_FIRMWARE = "0.9"; /* Firmware version */ + +//========================================================================== +//========================================================================== +String urlEncode(const String &url, const char *safeChars = "-_.~") { + String encoded = ""; + char temp[4]; + + for (int i = 0; i < url.length(); i++) { + temp[0] = url.charAt(i); + if (temp[0] == 32) { //space + encoded.concat('+'); + } else if ((temp[0] >= 48 && temp[0] <= 57) /*0-9*/ + || (temp[0] >= 65 && temp[0] <= 90) /*A-Z*/ + || (temp[0] >= 97 && temp[0] <= 122) /*a-z*/ + || (strchr(safeChars, temp[0]) != NULL) /* "=&-_.~" */ + ) { + encoded.concat(temp[0]); + } else { //character needs encoding + snprintf(temp, 4, "%%%02X", temp[0]); + encoded.concat(temp); + } + } + return encoded; +} + +//========================================================================== +bool addQuery(String *query, const String name, const String value) { + if (name.length() && value.length()) { + if (query->length() < 3) { + *query = "?"; + } else { + query->concat('&'); + } + query->concat(urlEncode(name)); + query->concat('='); + query->concat(urlEncode(value)); + return true; + } + return false; +} + +//========================================================================== +//========================================================================== +void printProgress(size_t progress, const size_t &size) { + static int last_progress = -1; + if (size > 0) { + progress = (progress * 100) / size; + progress = (progress > 100 ? 100 : progress); //0-100 + if (progress != last_progress) { + Serial.printf("Progress: %zu%%\n", progress); + last_progress = progress; + } + } +} + +//========================================================================== +bool http_downloadUpdate(HTTPClient &http, uint32_t size = 0) { + size = (size == 0 ? http.getSize() : size); + if (size == 0) { + return false; + } + NetworkClient *client = http.getStreamPtr(); + + if (!Update.begin(size, U_FLASH)) { + Serial.printf("Update.begin failed! (%s)\n", Update.errorString()); + return false; + } + + if (!Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG, OTA_MODE)) { + Serial.println("Update.setupCrypt failed!"); + } + + if (Update.writeStream(*client) != size) { + Serial.printf("Update.writeStream failed! (%s)\n", Update.errorString()); + return false; + } + + if (!Update.end()) { + Serial.printf("Update.end failed! (%s)\n", Update.errorString()); + return false; + } + return true; +} + +//========================================================================== +int http_sendRequest(HTTPClient &http) { + + //set request Headers to be sent to server + http.useHTTP10(true); // use HTTP/1.0 for update since the update handler not support any transfer Encoding + http.setTimeout(8000); + http.addHeader("Cache-Control", "no-cache"); + + //set own name for HTTPclient user-agent + http.setUserAgent(HTTPUPDATE_USERAGRENT); + + int code = http.GET(); //send the GET request to HTTP server + int len = http.getSize(); + + if (code == HTTP_CODE_OK) { + return (len > 0 ? len : 0); //return 0 or length of image to download + } else if (code < 0) { + Serial.printf("Error: %s\n", http.errorToString(code).c_str()); + return code; //error code should be minus between -1 to -11 + } else { + Serial.printf("Error: HTTP Server response code %i\n", code); + return -code; //return code should be minus between -100 to -511 + } +} + +//========================================================================== +/* http_updater sends a GET request to 'update.php' on web server */ +bool http_updater(const String &host, const uint16_t &port, String uri, const bool &download, const char *user = NULL, const char *password = NULL) { + //add GET query params to be sent to server (are used by server 'updater.php' code to determine what action to take) + String query = ""; + addQuery(&query, "cmd", (download ? "download" : "check")); //action command + + //setup HTTPclient to be ready to connect & send a request to HTTP server + HTTPClient http; + NetworkClient client; + uri.concat(query); //GET query added to end of uri path + if (!http.begin(client, host, port, uri)) { + return false; //httpclient setup error + } + Serial.printf("Sending HTTP request 'http://%s:%i%s'\n", host.c_str(), port, uri.c_str()); + + //set basic authorization, if needed for webpage access + if (user != NULL && password != NULL) { + http.setAuthorization(user, password); //set basic Authorization to server, if needed be gain access + } + + //add unique Headers to be sent to server used by server 'update.php' code to determine there a suitable firmware update image available + http.addHeader("Brand-Code", HTTPUPDATE_BRAND); + http.addHeader("Model", HTTPUPDATE_MODEL); + http.addHeader("Firmware", HTTPUPDATE_FIRMWARE); + + //set headers to look for to get returned values in servers http response to our http request + const char *headerkeys[] = {"update", "version"}; //server returns update 0=no update found, 1=update found, version=version of update found + size_t headerkeyssize = sizeof(headerkeys) / sizeof(char *); + http.collectHeaders(headerkeys, headerkeyssize); + + //connect & send HTTP request to server + int size = http_sendRequest(http); + + //is there an image to download + if (size > 0 || (!download && size == 0)) { + if (!http.header("update") || http.header("update").toInt() == 0) { + Serial.println("No Firmware available"); + } else if (!http.header("version") || http.header("version").toFloat() <= String(HTTPUPDATE_FIRMWARE).toFloat()) { + Serial.println("Firmware is upto Date"); + } else { + //image avaliabe to download & update + if (!download) { + Serial.printf("Found V%s Firmware\n", http.header("version").c_str()); + } else { + Serial.printf("Downloading & Installing V%s Firmware\n", http.header("version").c_str()); + } + if (!download || http_downloadUpdate(http)) { + http.end(); //end connection + return true; + } + } + } + + http.end(); //end connection + return false; +} + +//========================================================================== +/* this downloads Firmware image file directly from web server */ +bool http_direct(const String &host, const uint16_t &port, const String &uri, const char *user = NULL, const char *password = NULL) { + //setup HTTPclient to be ready to connect & send a request to HTTP server + HTTPClient http; + NetworkClient client; + if (!http.begin(client, host, port, uri)) { + return false; //httpclient setup error + } + Serial.printf("Sending HTTP request 'http://%s:%i%s'\n", host.c_str(), port, uri.c_str()); + + //set basic authorization, if needed for webpage access + if (user != NULL && password != NULL) { + http.setAuthorization(user, password); //set basic Authorization to server, if needed be gain access + } + + //connect & send HTTP request to server + int size = http_sendRequest(http); + + //is there an image to download + if (size > 0) { + if (http_downloadUpdate(http)) { + http.end(); + return true; //end connection + } + } else { + Serial.println("Image File not found"); + } + + http.end(); //end connection + return false; +} + +//========================================================================== +//========================================================================== + +void setup() { + Serial.begin(115200); + Serial.println(); + Serial.printf("Booting %s V%s\n", HTTPUPDATE_MODEL, HTTPUPDATE_FIRMWARE); + + WiFi.mode(WIFI_AP_STA); + WiFi.begin(WIFI_SSID, WIFI_PASSWORD); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi failed, retrying."); + } + int i = 0; + while (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.print("."); + if ((++i % 100) == 0) { + Serial.println(); + } + delay(100); + } + Serial.printf("Connected to Wifi\nLocal IP: %s\n", WiFi.localIP().toString().c_str()); + + Update.onProgress(printProgress); + + Serial.println("Checking with Server, if New Firmware available"); + if (http_updater(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_UPDATER_URI, 0, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) { //check for new firmware + if (http_updater(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_UPDATER_URI, 1, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) { //update to new firmware + Serial.println("Firmware Update Successful, rebooting"); + ESP.restart(); + } + } + + Serial.println("Checking Server for Firmware Image File to Download & Install"); + if (http_direct(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_DIRECT_URI, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) { + Serial.println("Firmware Update Successful, rebooting"); + ESP.restart(); + } +} + +void loop() {} diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.yml b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php new file mode 100644 index 0000000..056a741 --- /dev/null +++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php @@ -0,0 +1,64 @@ + $value) { + $headers += [$name => $value]; + } + verify( in_array($headers['Brand-Code'], $brand_codes) ); + + $GetArgs = filter_input_array(INPUT_GET); + verify( in_array($GetArgs['cmd'], $commands) ); + + if($GetArgs['cmd'] == "check" || $GetArgs['cmd'] == "download"){ +/*********************************************************************************/ +/* $firmware version & filename definitions for different Brands, Models & Firmware versions */ + if($headers['Brand-Code'] == "21"){ + if($headers['Model'] == "HTTP_Client_AES_OTA_Update"){ + + if($headers['Firmware'] < "0.9"){//ie. update to latest of this major version + $firmware = array('version'=>"0.9", 'filename'=>"HTTP_Client_AES_OTA_Update-v0.9.xbin"); + } + elseif($headers['Firmware'] == "0.9"){//ie. update between major versions + $firmware = array('version'=>"1.0", 'filename'=>"HTTP_Client_AES_OTA_Update-v1.0.xbin"); + } + elseif($headers['Firmware'] <= "1.4"){//ie. update to latest version + $firmware = array('version'=>"1.4", 'filename'=>"HTTP_Client_AES_OTA_Update-v1.4.xbin"); + } + + } + } +/* end of $firmware definitions for firmware update images on server */ +/*********************************************************************************/ + + if( !$firmware['filename'] || !file_exists($firmware['filename']) ){ + header('update: 0' );//no update available + exit; + }else{ + header('update: 1' );//update available + header('version: ' . $firmware['version'] ); + if($GetArgs['cmd'] == "download"){ +//Get file type and set it as Content Type + $finfo = finfo_open(FILEINFO_MIME_TYPE); + header('Content-Type: ' . finfo_file($finfo, $firmware['filename']));//application/octet-stream for binary file + finfo_close($finfo); +//Define file size + header('Content-Length: ' . filesize($firmware['filename'])); + readfile($firmware['filename']); //send file + } + exit; + } + } + + verify(false); +?> diff --git a/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino new file mode 100644 index 0000000..9d1d9f8 --- /dev/null +++ b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino @@ -0,0 +1,236 @@ +/* +An example of how to use Update to upload encrypted and plain image files OTA. This example uses a simple webserver & Wifi connection via AP or STA with mDNS and DNS for simple host URI. + +Encrypted image will help protect your app image file from being copied and used on blank devices, encrypt your image file by using espressif IDF. +First install an app on device that has Update setup with the OTA decrypt mode on, same key, address and flash_crypt_conf as used in IDF to encrypt image file or vice versa. + +For easier development use the default U_AES_DECRYPT_AUTO decrypt mode. This mode allows both plain and encrypted app images to be uploaded. + +Note:- App image can also encrypted on device, by using espressif IDF to configure & enabled FLASH encryption, suggest the use of a different 'OTA_KEY' key for update from the eFuses 'flash_encryption' key used by device. + + ie. "Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG);" + +defaults:- {if not set ie. "Update.setupCrypt();" } + OTA_KEY = 0 ( 0 = no key, disables decryption ) + OTA_ADDRESS = 0 ( suggest dont set address to app0=0x10000 usually or app1=varies ) + OTA_CFG = 0xf + OTA_MODE = U_AES_DECRYPT_AUTO + +OTA_MODE options:- + U_AES_DECRYPT_NONE decryption disabled, loads OTA image files as sent(plain) + U_AES_DECRYPT_AUTO auto loads both plain & encrypted OTA FLASH image files, and plain OTA File System image files + U_AES_DECRYPT_ON decrypts OTA image files + +https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/ + +Example: + espsecure.py encrypt_flash_data -k ota_key.bin --flash_crypt_conf 0xf -a 0x4320 -o output_filename.bin source_filename.bin + +espsecure.py encrypt_flash_data = runs the idf encryption function to make a encrypted output file from a source file + -k text = path/filename to the AES 256bit(32byte) encryption key file + --flash_crypt_conf 0xn = 0x0 to 0xf, the more bits set the higher the security of encryption(address salting, 0x0 would use ota_key with no address salting) + -a 0xnnnnnn00 = 0x00 to 0x00fffff0 address offset(must be a multiple of 16, but better to use multiple of 32), used to offset the salting (has no effect when = --flash_crypt_conf 0x0) + -o text = path/filename to save encrypted output file to + text = path/filename to open source file from +*/ + +#include +#include +#include +#include +#include + +WebServer httpServer(80); + +//with WIFI_MODE_AP defined the ESP32 is a wifi AP, with it undefined ESP32 tries to connect to wifi STA +#define WIFI_MODE_AP + +#ifdef WIFI_MODE_AP +#include +DNSServer dnsServer; +#endif + +const char *host = "esp32-web"; +const char *ssid = "wifi-ssid"; +const char *password = "wifi-password"; + +const uint8_t OTA_KEY[32] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, + 0x61, 0x20, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x74, 0x65, 0x73, 0x74, 0x20, 0x6b, 0x65, 0x79}; + +/* +const uint8_t OTA_KEY[32] = {'0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', ' ', 't', 'h', 'i', 's', ' ', + 'a', ' ', 's', 'i', 'm', 'p', 'l', 'e', + 't', 'e', 's', 't', ' ', 'k', 'e', 'y' }; +*/ + +//const uint8_t OTA_KEY[33] = "0123456789 this a simpletest key"; + +const uint32_t OTA_ADDRESS = 0x4320; //OTA_ADDRESS value has no effect when OTA_CFG = 0x00 +const uint32_t OTA_CFG = 0x0f; +const uint32_t OTA_MODE = U_AES_DECRYPT_AUTO; + +/*=================================================================*/ +const char *update_path = "update"; + +static const char UpdatePage_HTML[] PROGMEM = + R"( + + + Image Upload + + + + +
+ Firmware:

+

+ +
+


+
+ FileSystem:

+

+ +
+ + )"; + +/*=================================================================*/ + +void printProgress(size_t progress, size_t size) { + static int last_progress = -1; + if (size > 0) { + progress = (progress * 100) / size; + progress = (progress > 100 ? 100 : progress); //0-100 + if (progress != last_progress) { + Serial.printf("\nProgress: %zu%%", progress); + last_progress = progress; + } + } +} + +void setupHttpUpdateServer() { + //redirecting not found web pages back to update page + httpServer.onNotFound([&]() { //webpage not found + httpServer.sendHeader("Location", String("../") + String(update_path)); + httpServer.send(302, F("text/html"), ""); + }); + + // handler for the update web page + httpServer.on(String("/") + String(update_path), HTTP_GET, [&]() { + httpServer.send_P(200, PSTR("text/html"), UpdatePage_HTML); + }); + + // handler for the update page form POST + httpServer.on( + String("/") + String(update_path), HTTP_POST, + [&]() { + // handler when file upload finishes + if (Update.hasError()) { + httpServer.send(200, F("text/html"), String(F("Update error: ")) + String(Update.errorString())); + } else { + httpServer.client().setNoDelay(true); + httpServer.send(200, PSTR("text/html"), String(F("Update Success! Rebooting..."))); + delay(100); + httpServer.client().stop(); + ESP.restart(); + } + }, + [&]() { + // handler for the file upload, gets the sketch bytes, and writes + // them through the Update object + HTTPUpload &upload = httpServer.upload(); + if (upload.status == UPLOAD_FILE_START) { + Serial.printf("Update: %s\n", upload.filename.c_str()); + if (upload.name == "filesystem") { + if (!Update.begin(UPDATE_SIZE_UNKNOWN, U_FLASHFS)) { //start with max available size + Update.printError(Serial); + } + } else { + uint32_t maxSketchSpace = (ESP.getFreeSketchSpace() - 0x1000) & 0xFFFFF000; + if (!Update.begin(maxSketchSpace, U_FLASH)) { //start with max available size + Update.printError(Serial); + } + } + } else if (upload.status == UPLOAD_FILE_ABORTED || Update.hasError()) { + if (upload.status == UPLOAD_FILE_ABORTED) { + if (!Update.end(false)) { + Update.printError(Serial); + } + Serial.println("Update was aborted"); + } + } else if (upload.status == UPLOAD_FILE_WRITE) { + Serial.printf("."); + if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) { + Update.printError(Serial); + } + } else if (upload.status == UPLOAD_FILE_END) { + if (Update.end(true)) { //true to set the size to the current progress + Serial.printf("Update Success: %zu\nRebooting...\n", upload.totalSize); + } else { + Update.printError(Serial); + } + } + delay(0); + } + ); + + Update.onProgress(printProgress); +} + +/*=================================================================*/ + +void setup(void) { + Serial.begin(115200); + Serial.println(); + Serial.println("Booting Sketch..."); + WiFi.mode(WIFI_AP_STA); +#ifdef WIFI_MODE_AP + WiFi.softAP(ssid, password); + dnsServer.setErrorReplyCode(DNSReplyCode::NoError); + dnsServer.start(53, "*", WiFi.softAPIP()); //if DNS started with "*" for domain name, it will reply with provided IP to all DNS request + Serial.printf("Wifi AP started, IP address: %s\n", WiFi.softAPIP().toString().c_str()); + Serial.printf("You can connect to ESP32 AP use:-\n ssid: %s\npassword: %s\n\n", ssid, password); +#else + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi failed, retrying."); + } + int i = 0; + while (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.print("."); + if ((++i % 100) == 0) { + Serial.println(); + } + delay(100); + } + Serial.printf("Connected to Wifi\nLocal IP: %s\n", WiFi.localIP().toString().c_str()); +#endif + + if (MDNS.begin(host)) { + Serial.println("mDNS responder started"); + } + + setupHttpUpdateServer(); + + if (Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG, OTA_MODE)) { + Serial.println("Upload Decryption Ready"); + } + + httpServer.begin(); + + MDNS.addService("http", "tcp", 80); +#ifdef WIFI_MODE_AP + Serial.printf("HTTPUpdateServer ready with Captive DNS!\nOpen http://anyname.xyz/%s in your browser\n", update_path); +#else + Serial.printf("HTTPUpdateServer ready!\nOpen http://%s.local/%s in your browser\n", host, update_path); +#endif +} + +void loop(void) { + httpServer.handleClient(); +#ifdef WIFI_MODE_AP + dnsServer.processNextRequest(); //DNS captive portal for easy access to this device webserver +#endif +} diff --git a/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.yml b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino b/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino new file mode 100644 index 0000000..5756ccc --- /dev/null +++ b/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino @@ -0,0 +1,148 @@ +#include +#include +#include +#include +#include +#include "html.h" + +#define SSID_FORMAT "ESP32-%06lX" // 12 chars total +//#define PASSWORD "test123456" // generate if remarked + +// Set the username and password for firmware upload +const char *authUser = "........"; +const char *authPass = "........"; + +WebServer server(80); +Ticker tkSecond; +uint8_t otaDone = 0; + +const char *csrfHeaders[2] = {"Origin", "Host"}; +static bool authenticated = false; + +const char *alphanum = "0123456789!@#$%^&*abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"; +String generatePass(uint8_t str_len) { + String buff; + for (int i = 0; i < str_len; i++) { + buff += alphanum[random(strlen(alphanum) - 1)]; + } + return buff; +} + +void apMode() { + char ssid[13]; + char passwd[11]; + long unsigned int espmac = ESP.getEfuseMac() >> 24; + snprintf(ssid, 13, SSID_FORMAT, espmac); +#ifdef PASSWORD + snprintf(passwd, 11, PASSWORD); +#else + snprintf(passwd, 11, generatePass(10).c_str()); +#endif + WiFi.mode(WIFI_AP); + WiFi.softAP(ssid, passwd); // Set up the SoftAP + MDNS.begin("esp32"); + Serial.printf("AP: %s, PASS: %s\n", ssid, passwd); +} + +void handleUpdateEnd() { + if (!authenticated) { + return server.requestAuthentication(); + } + server.sendHeader("Connection", "close"); + if (Update.hasError()) { + server.send(502, "text/plain", Update.errorString()); + } else { + server.sendHeader("Refresh", "10"); + server.sendHeader("Location", "/"); + server.send(307); + delay(500); + ESP.restart(); + } +} + +void handleUpdate() { + size_t fsize = UPDATE_SIZE_UNKNOWN; + if (server.hasArg("size")) { + fsize = server.arg("size").toInt(); + } + HTTPUpload &upload = server.upload(); + if (upload.status == UPLOAD_FILE_START) { + authenticated = server.authenticate(authUser, authPass); + if (!authenticated) { + Serial.println("Authentication fail!"); + otaDone = 0; + return; + } + String origin = server.header(String(csrfHeaders[0])); + String host = server.header(String(csrfHeaders[1])); + String expectedOrigin = String("http://") + host; + if (origin != expectedOrigin) { + Serial.printf("Wrong origin received! Expected: %s, Received: %s\n", expectedOrigin.c_str(), origin.c_str()); + authenticated = false; + otaDone = 0; + return; + } + + Serial.printf("Receiving Update: %s, Size: %zu\n", upload.filename.c_str(), fsize); + if (!Update.begin(fsize)) { + otaDone = 0; + Update.printError(Serial); + } + } else if (authenticated && upload.status == UPLOAD_FILE_WRITE) { + if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) { + Update.printError(Serial); + } else { + otaDone = 100 * Update.progress() / Update.size(); + } + } else if (authenticated && upload.status == UPLOAD_FILE_END) { + if (Update.end(true)) { + Serial.printf("Update Success: %zu bytes\nRebooting...\n", upload.totalSize); + } else { + Serial.printf("%s\n", Update.errorString()); + otaDone = 0; + } + } +} + +void webServerInit() { + server.collectHeaders(csrfHeaders, 2); + server.on( + "/update", HTTP_POST, + []() { + handleUpdateEnd(); + }, + []() { + handleUpdate(); + } + ); + server.on("/favicon.ico", HTTP_GET, []() { + server.sendHeader("Content-Encoding", "gzip"); + server.send_P(200, "image/x-icon", favicon_ico_gz, favicon_ico_gz_len); + }); + server.onNotFound([]() { + if (!server.authenticate(authUser, authPass)) { + return server.requestAuthentication(); + } + server.send(200, "text/html", indexHtml); + }); + server.begin(); + Serial.printf("Web Server ready at http://esp32.local or http://%s\n", WiFi.softAPIP().toString().c_str()); +} + +void everySecond() { + if (otaDone > 1) { + Serial.printf("ota: %d%%\n", otaDone); + } +} + +void setup() { + Serial.begin(115200); + apMode(); + webServerInit(); + tkSecond.attach(1, everySecond); +} + +void loop() { + delay(150); + server.handleClient(); +} diff --git a/libraries/Update/examples/OTAWebUpdater/ci.yml b/libraries/Update/examples/OTAWebUpdater/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/OTAWebUpdater/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/OTAWebUpdater/html.h b/libraries/Update/examples/OTAWebUpdater/html.h new file mode 100644 index 0000000..b4c488b --- /dev/null +++ b/libraries/Update/examples/OTAWebUpdater/html.h @@ -0,0 +1,73 @@ +// Literal string +const char *indexHtml = R"literal( + + + +

ESP Firmware Update

+
+ + +
+
+
0%
+ + +)literal"; + +// Compressed gzip in C include file style +// listing was created using `xxd -i favicon.ico.gz` +const char favicon_ico_gz[] = { + 0x1f, 0x8b, 0x08, 0x08, 0x13, 0xb6, 0xa5, 0x62, 0x00, 0x03, 0x66, 0x61, 0x76, 0x69, 0x63, 0x6f, 0x6e, 0x2e, 0x69, 0x63, 0x6f, 0x00, 0xa5, 0x53, 0x69, 0x48, + 0x54, 0x51, 0x14, 0x7e, 0x41, 0x99, 0x4b, 0xa0, 0x15, 0x24, 0xb4, 0x99, 0x8e, 0x1b, 0x25, 0xa8, 0x54, 0xb4, 0x19, 0x56, 0x62, 0x41, 0xab, 0x14, 0x45, 0x61, + 0x51, 0x62, 0x86, 0x69, 0x1a, 0xd4, 0x60, 0xda, 0xa2, 0x99, 0x4b, 0x69, 0x1b, 0x42, 0x26, 0x5a, 0x09, 0x59, 0xd8, 0xfe, 0xab, 0x88, 0xa0, 0x82, 0xe8, 0x4f, + 0x90, 0xa5, 0x14, 0x68, 0x0b, 0xe6, 0x2c, 0x6f, 0x9c, 0xed, 0xcd, 0x9b, 0xcd, 0x19, 0x9d, 0x99, 0x3b, 0xe3, 0xd7, 0x79, 0x6f, 0x34, 0xac, 0xe8, 0x57, 0xf7, + 0x72, 0x1e, 0x87, 0xb3, 0xbe, 0xf3, 0x9d, 0xef, 0x72, 0xdc, 0x24, 0xba, 0x51, 0x51, 0x1c, 0x7d, 0x17, 0x70, 0x85, 0x93, 0x39, 0x6e, 0x16, 0xc7, 0x71, 0xc9, + 0x24, 0x64, 0x22, 0x4b, 0xd0, 0x2e, 0x1f, 0xf2, 0xcd, 0x8c, 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0x11, 0x16, 0x1f, 0xcc, 0x0f, 0xa5, 0xb9, 0x16, + 0xae, 0xe6, 0x51, 0x7b, 0xc9, 0x8a, 0x17, 0xaf, 0xdd, 0x18, 0xf1, 0x04, 0xb0, 0x65, 0x97, 0x01, 0x1d, 0xf7, 0x9c, 0xf0, 0xfb, 0x03, 0x28, 0x2a, 0x13, 0xd0, + 0xfb, 0xcd, 0x8b, 0xfe, 0x1f, 0x5e, 0x1c, 0x38, 0x6c, 0xc2, 0xe3, 0xa7, 0x2e, 0x2c, 0xcd, 0x1e, 0x44, 0x98, 0x62, 0x2c, 0x9f, 0x30, 0x39, 0x52, 0x6e, 0x41, + 0xe6, 0x56, 0x3d, 0x16, 0x65, 0xf0, 0xd8, 0xb9, 0xd7, 0x88, 0x0d, 0x39, 0x7a, 0x0c, 0xa8, 0x7d, 0x30, 0x99, 0x19, 0x0e, 0x95, 0x9a, 0x60, 0xb6, 0x30, 0x74, + 0xf5, 0x8c, 0xa0, 0xbc, 0x52, 0xc0, 0x28, 0xdd, 0xcb, 0xd7, 0xed, 0x20, 0x2c, 0xe5, 0xfc, 0xd9, 0xa9, 0x1a, 0x56, 0xdd, 0x68, 0x45, 0x5c, 0xba, 0x16, 0xf9, + 0xa5, 0x66, 0xb4, 0xdd, 0x72, 0xa0, 0x7f, 0xc0, 0x0b, 0x50, 0x5c, 0x6b, 0xbb, 0x1d, 0xf5, 0x97, 0xad, 0xb2, 0x7e, 0xb3, 0xc3, 0x81, 0x96, 0x5b, 0x76, 0x59, + 0x3f, 0x5e, 0x69, 0xc1, 0xe4, 0x98, 0x60, 0x7e, 0x0a, 0xed, 0xe7, 0xd4, 0x39, 0x11, 0xe7, 0x29, 0x8e, 0xb1, 0x00, 0x46, 0x47, 0x47, 0x21, 0x50, 0xbf, 0x36, + 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0x25, 0x0e, 0x84, 0x25, 0x04, 0x39, 0xb9, 0x25, 0xd7, 0x88, 0xfc, 0x12, 0x33, 0xa2, 0x93, 0xd5, 0xc8, 0x2b, + 0x32, 0xe1, 0xc4, 0x69, 0x01, 0xcd, 0xad, 0x76, 0xf4, 0xf6, 0x79, 0xe4, 0xff, 0xe0, 0xa9, 0xaf, 0xb2, 0x42, 0x40, 0x53, 0xb3, 0x0d, 0x43, 0x2e, 0xe2, 0x04, + 0xed, 0x34, 0x74, 0x0c, 0x7f, 0xe2, 0x11, 0x9b, 0x4e, 0x79, 0xe5, 0xd5, 0x22, 0xb2, 0x88, 0x1b, 0xcf, 0x5f, 0xba, 0xe5, 0x39, 0x25, 0x11, 0x09, 0xab, 0x07, + 0x34, 0xef, 0x41, 0xda, 0xfb, 0x3d, 0xea, 0xeb, 0x72, 0x07, 0x70, 0xf5, 0xba, 0x0d, 0x33, 0x92, 0xd5, 0xbf, 0xf3, 0x8f, 0xb8, 0x34, 0x7f, 0xb1, 0x16, 0x89, + 0x2b, 0x79, 0x64, 0x6c, 0x1a, 0x44, 0x53, 0x9b, 0x1d, 0x65, 0x55, 0x22, 0x76, 0x12, 0xce, 0x35, 0x0d, 0x22, 0x3e, 0xf4, 0x78, 0xd0, 0xfd, 0xd9, 0x43, 0x5c, + 0x14, 0x30, 0x23, 0xe9, 0x1f, 0xfc, 0x27, 0x9b, 0x54, 0x87, 0xf8, 0x28, 0xff, 0xdb, 0x94, 0xf9, 0x2a, 0x24, 0x10, 0x4f, 0xf3, 0x68, 0xae, 0x8d, 0xf4, 0x1e, + 0xe6, 0x11, 0x3f, 0x24, 0x7b, 0x78, 0xe2, 0xaf, 0x5c, 0xfc, 0xf1, 0x06, 0xff, 0x12, 0x69, 0xbf, 0x53, 0x68, 0x47, 0x21, 0x84, 0x91, 0xa4, 0x4f, 0xf4, 0x8d, + 0xbd, 0x63, 0x2f, 0xf7, 0x9f, 0xe7, 0x27, 0x40, 0xbb, 0x5a, 0x53, 0x7e, 0x04, 0x00, 0x00 +}; +const int favicon_ico_gz_len = 821; diff --git a/libraries/Update/examples/SD_Update/SD_Update.ino b/libraries/Update/examples/SD_Update/SD_Update.ino new file mode 100644 index 0000000..8b2451a --- /dev/null +++ b/libraries/Update/examples/SD_Update/SD_Update.ino @@ -0,0 +1,103 @@ +/* + Name: SD_Update.ino + Created: 12.09.2017 15:07:17 + Author: Frederik Merz + Purpose: Update firmware from SD card + + Steps: + 1. Flash this image to the ESP32 an run it + 2. Copy update.bin to a SD-Card, you can basically + compile this or any other example + then copy and rename the app binary to the sd card root + 3. Connect SD-Card as shown in SD example, + this can also be adapted for SPI + 3. After successful update and reboot, ESP32 shall start the new app +*/ + +#include +#include +#include + +// perform the actual update from a given stream +void performUpdate(Stream &updateSource, size_t updateSize) { + if (Update.begin(updateSize)) { + size_t written = Update.writeStream(updateSource); + if (written == updateSize) { + Serial.println("Written : " + String(written) + " successfully"); + } else { + Serial.println("Written only : " + String(written) + "/" + String(updateSize) + ". Retry?"); + } + if (Update.end()) { + Serial.println("OTA done!"); + if (Update.isFinished()) { + Serial.println("Update successfully completed. Rebooting."); + } else { + Serial.println("Update not finished? Something went wrong!"); + } + } else { + Serial.println("Error Occurred. Error #: " + String(Update.getError())); + } + + } else { + Serial.println("Not enough space to begin OTA"); + } +} + +// check given FS for valid update.bin and perform update if available +void updateFromFS(fs::FS &fs) { + File updateBin = fs.open("/update.bin"); + if (updateBin) { + if (updateBin.isDirectory()) { + Serial.println("Error, update.bin is not a file"); + updateBin.close(); + return; + } + + size_t updateSize = updateBin.size(); + + if (updateSize > 0) { + Serial.println("Try to start update"); + performUpdate(updateBin, updateSize); + } else { + Serial.println("Error, file is empty"); + } + + updateBin.close(); + + // when finished remove the binary from sd card to indicate end of the process + fs.remove("/update.bin"); + } else { + Serial.println("Could not load update.bin from sd root"); + } +} + +void setup() { + uint8_t cardType; + Serial.begin(115200); + Serial.println("Welcome to the SD-Update example!"); + + // You can uncomment this and build again + // Serial.println("Update successful"); + + //first init and check SD card + if (!SD.begin()) { + rebootEspWithReason("Card Mount Failed"); + } + + cardType = SD.cardType(); + + if (cardType == CARD_NONE) { + rebootEspWithReason("No SD_MMC card attached"); + } else { + updateFromFS(SD); + } +} + +void rebootEspWithReason(String reason) { + Serial.println(reason); + delay(1000); + ESP.restart(); +} + +//will not be reached +void loop() {} diff --git a/libraries/Update/examples/Signed_OTA_Update/README.md b/libraries/Update/examples/Signed_OTA_Update/README.md new file mode 100644 index 0000000..be449f4 --- /dev/null +++ b/libraries/Update/examples/Signed_OTA_Update/README.md @@ -0,0 +1,202 @@ +# Signed OTA Update Example + +This example demonstrates how to perform secure OTA (Over-The-Air) updates with signature verification on ESP32 devices using Arduino. + +## Overview + +Code signing ensures that only firmware signed with your private key will be accepted by your devices. This protects against unauthorized firmware updates, even if an attacker gains access to your update server. + +## Features + +- **RSA Signature Verification**: Supports RSA-2048, RSA-3072, and RSA-4096 +- **ECDSA Signature Verification**: Supports ECDSA-P256 and ECDSA-P384 +- **Multiple Hash Algorithms**: SHA-256, SHA-384, and SHA-512 +- **Automatic Signature Verification**: Signatures are verified automatically during OTA update +- **Secure by Default**: Update fails if signature verification fails + +## Prerequisites + +1. **Python 3** with the `cryptography` package: + ```bash + pip install cryptography + ``` + +2. **ESP32 Arduino Core** with Update library + +## Quick Start Guide + +### Step 1: Generate Key Pair + +Generate an RSA-2048 key pair (recommended): +```bash +python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem +python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +``` + +Or generate an ECDSA-P256 key pair (smaller, faster): +```bash +python /tools/bin_signing.py --generate-key ecdsa-p256 --out private_key.pem +python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +``` + +Where `` is your ESP32 Arduino installation path (e.g., `~/Arduino/hardware/espressif/esp32/`). + +**IMPORTANT**: Keep `private_key.pem` secure! Anyone with access to it can sign firmware for your devices. + +### Step 2: Update the Example Sketch + +1. Copy the generated `public_key.h` to the example directory +2. Open `Signed_OTA_Update.ino` +3. Update Wi-Fi credentials: + ```cpp + const char *ssid = "YOUR_SSID"; + const char *password = "YOUR_PASSWORD"; + ``` +4. Update firmware URL: + ```cpp + const char *firmwareUrl = "http://your-server.com/firmware_signed.bin"; + ``` +5. Uncomment the appropriate key type (RSA or ECDSA) +6. Uncomment the appropriate hash algorithm (SHA-256, SHA-384, or SHA-512) + +### Step 3: Build and Upload Initial Firmware + +1. Compile and upload the sketch to your ESP32 +2. Open Serial Monitor to verify it's running + +### Step 4: Build and Sign New Firmware + +1. Make changes to your sketch (e.g., add a version number) +2. Build the sketch and export the binary: + - Arduino IDE: `Sketch` → `Export Compiled Binary` + - Find the application `.bin` file in the `build` folder of your sketch folder. For example `build/espressif.esp32.esp32c6/Signed_OTA_Update.ino.bin`. + +3. Sign the binary: + ```bash + python /tools/bin_signing.py --bin --key private_key.pem --out firmware_signed.bin + ``` + + For other hash algorithms (for example SHA-384): + ```bash + python /tools/bin_signing.py --bin --key private_key.pem --out firmware_signed.bin --hash sha384 + ``` + +### Step 5: Host the Signed Firmware + +Upload `firmware_signed.bin` to your web server and make it accessible at the URL you configured. + +### Step 6: Perform OTA Update + +Reset your ESP32. It will: +1. Connect to Wi-Fi +2. Download the signed firmware +3. Verify the signature +4. Apply the update if signature is valid +5. Reboot with the new firmware + +## Security Considerations + +### Private Key Management + +- **NEVER** commit your private key to version control +- Store it securely (encrypted storage, HSM, etc.) +- Limit access to authorized personnel only +- Consider using separate keys for development and production + +### Recommended Practices + +1. **Use HTTPS**: While signature verification protects firmware integrity, HTTPS protects against MitM attacks +2. **Key Rotation**: Periodically rotate keys (requires firmware update to include new public key) + +## Signature Schemes Comparison + +| Scheme | Key Size | Signature Size | Verification Speed | Security | +|--------|----------|----------------|-------------------|----------| +| RSA-2048 | 2048 bits | 256 bytes | Medium | High | +| RSA-3072 | 3072 bits | 384 bytes | Slower | Very High | +| RSA-4096 | 4096 bits | 512 bytes | Slowest | Maximum | +| ECDSA-P256 | 256 bits | 64 bytes | Fast | High | +| ECDSA-P384 | 384 bits | 96 bytes | Fast | Very High | + +**Recommendation**: RSA-2048 or ECDSA-P256 provide good security with reasonable performance. + +## Hash Algorithms Comparison + +| Algorithm | Output Size | Speed | Security | +|-----------|-------------|-------|----------| +| SHA-256 | 32 bytes | Fast | High | +| SHA-384 | 48 bytes | Medium | Very High | +| SHA-512 | 64 bytes | Medium | Very High | + +**Recommendation**: SHA-256 is sufficient for most applications. + +## Troubleshooting + +### "Signature verification failed" + +- Ensure the firmware was signed with the correct private key +- Verify that the public key in the sketch matches the private key used for signing +- Check that the signature scheme (RSA/ECDSA) and hash algorithm match between signing and verification +- Ensure the signed binary wasn't corrupted during transfer + +### "Failed to install signature verification" + +- Check that `installSignature()` is called before `Update.begin()` +- Ensure hash and sign objects are properly initialized + +### "Public key parsing failed" + +- Verify the public key PEM format is correct +- Ensure PUBLIC_KEY_LEN matches the actual key length + +## Advanced Usage + +### Verifying a Signed Binary + +You can verify a signed binary without flashing it: + +```bash +python bin_signing.py --verify firmware_signed.bin --pubkey public_key.pem +``` + +### Using Different Hash Algorithms + +Match the hash algorithm between signing and verification: + +**Signing with SHA-384:** +```bash +python bin_signing.py --bin firmware.bin --key private_key.pem --out firmware_signed.bin --hash sha384 +``` + +**Sketch configuration:** +```cpp +#define USE_SHA384 +``` + +## API Reference + +### Classes + +- **UpdaterRSAVerifier**: RSA signature verifier +- **UpdaterECDSAVerifier**: ECDSA signature verifier + +### Methods + +```cpp +// Install signature verification (call before Update.begin()) +bool Update.installSignature(UpdaterVerifyClass *sign); +``` + +### Error Codes + +- `UPDATE_ERROR_SIGN (14)`: Signature verification failed + +## License + +This example is part of the Arduino-ESP32 project and is licensed under the Apache License 2.0. + +## Support + +For issues and questions: +- GitHub: https://github.com/espressif/arduino-esp32/issues +- Documentation: https://docs.espressif.com/ diff --git a/libraries/Update/examples/Signed_OTA_Update/Signed_OTA_Update.ino b/libraries/Update/examples/Signed_OTA_Update/Signed_OTA_Update.ino new file mode 100644 index 0000000..ded41a8 --- /dev/null +++ b/libraries/Update/examples/Signed_OTA_Update/Signed_OTA_Update.ino @@ -0,0 +1,231 @@ +/* + Signed OTA Update Example + + This example demonstrates how to perform a secure OTA update with signature verification. + Only firmware signed with the correct private key will be accepted. + + NOTE: This example requires signature verification support to be enabled. + This is done automatically via the build_opt.h file in this directory. + + Steps to use this example: + 1. Generate a key pair (see instructions below) + 2. Include the public key in this sketch (see public_key.h) + 3. Build and upload this sketch to your ESP32 + 4. Build your new firmware binary + 5. Sign the binary with the private key (see instructions below) + 6. Upload the signed firmware via OTA (HTTP/HTTPS server) + + Generating keys: + ------------------ + RSA (recommended for maximum compatibility): + python bin_signing.py --generate-key rsa-2048 --out private_key.pem + python bin_signing.py --extract-pubkey private_key.pem --out public_key.pem + + ECDSA (smaller keys, faster verification): + python bin_signing.py --generate-key ecdsa-p256 --out private_key.pem + python bin_signing.py --extract-pubkey private_key.pem --out public_key.pem + + Signing firmware: + ----------------- + python bin_signing.py --bin firmware.bin --key private_key.pem --out firmware_signed.bin + + IMPORTANT: Keep your private_key.pem secure! Anyone with access to it can + sign firmware that will be accepted by your devices. + + Created by lucasssvaz +*/ + +#include +#include +#include +#include + +// WiFi credentials +const char *ssid = "YOUR_SSID"; +const char *password = "YOUR_PASSWORD"; + +// URL to the signed firmware binary +const char *firmwareUrl = "http://your-server.com/firmware_signed.bin"; + +// Public key for signature verification +// Generated with: python bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +// This will create a public_key.h file that you should include below +#include "public_key.h" + +// Uncomment the key type you're using: +#define USE_RSA // RSA signature verification +//#define USE_ECDSA // ECDSA signature verification + +// Uncomment the hash algorithm you're using (must match the one used for signing): +#define USE_SHA256 // SHA-256 (recommended and default) +//#define USE_SHA384 // SHA-384 +//#define USE_SHA512 // SHA-512 + +void performOTAUpdate() { + HTTPClient http; + + Serial.println("Starting OTA update..."); + Serial.print("Firmware URL: "); + Serial.println(firmwareUrl); + + http.begin(firmwareUrl); + int httpCode = http.GET(); + + if (httpCode != HTTP_CODE_OK) { + Serial.printf("HTTP GET failed, error: %s\n", http.errorToString(httpCode).c_str()); + http.end(); + return; + } + + int contentLength = http.getSize(); + Serial.printf("Firmware size: %d bytes\n", contentLength); + + if (contentLength <= 0) { + Serial.println("Invalid content length"); + http.end(); + return; + } + + // The signed firmware includes the signature (512 bytes padding) + // The actual firmware size is contentLength - 512 + const size_t signatureSize = 512; + size_t firmwareSize = contentLength - signatureSize; + + Serial.printf("Actual firmware size: %zu bytes\n", firmwareSize); + Serial.printf("Signature size: %zu bytes\n", signatureSize); + + // Select hash algorithm +#ifdef USE_SHA256 + int hashType = HASH_SHA256; + Serial.println("Using SHA-256 hash"); +#elif defined(USE_SHA384) + int hashType = HASH_SHA384; + Serial.println("Using SHA-384 hash"); +#elif defined(USE_SHA512) + int hashType = HASH_SHA512; + Serial.println("Using SHA-512 hash"); +#else +#error "Please define a hash algorithm (USE_SHA256, USE_SHA384, or USE_SHA512)" +#endif + + // Create verifier object +#ifdef USE_RSA + UpdaterRSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, hashType); + Serial.println("Using RSA signature verification"); +#elif defined(USE_ECDSA) + UpdaterECDSAVerifier sign(PUBLIC_KEY, PUBLIC_KEY_LEN, hashType); + Serial.println("Using ECDSA signature verification"); +#else +#error "Please define a signature scheme (USE_RSA or USE_ECDSA)" +#endif + + // Install signature verification BEFORE calling Update.begin() + if (!Update.installSignature(&sign)) { + Serial.println("Failed to install signature verification"); + http.end(); + return; + } + Serial.println("Signature verification installed"); + + // Begin update with the TOTAL size (firmware + signature) + if (!Update.begin(contentLength)) { + Serial.printf("Update.begin failed: %s\n", Update.errorString()); + http.end(); + return; + } + + // Get the stream + WiFiClient *stream = http.getStreamPtr(); + + // Write firmware data + Serial.println("Writing firmware..."); + size_t written = 0; + uint8_t buff[1024]; + int progress = 0; + + while (http.connected() && (written < contentLength)) { + size_t available = stream->available(); + + if (available) { + int bytesRead = stream->readBytes(buff, min(available, sizeof(buff))); + + if (bytesRead > 0) { + size_t bytesWritten = Update.write(buff, bytesRead); + + if (bytesWritten > 0) { + written += bytesWritten; + + // Print progress + int newProgress = (written * 100) / contentLength; + if (newProgress != progress && newProgress % 10 == 0) { + progress = newProgress; + Serial.printf("Progress: %d%%\n", progress); + } + } else { + Serial.printf("Update.write failed: %s\n", Update.errorString()); + break; + } + } + } + delay(1); + } + + Serial.printf("Written: %zu bytes\n", written); + + // End the update - this will verify the signature + if (Update.end()) { + Serial.println("OTA update completed successfully!"); + Serial.println("Signature verified!"); + + if (Update.isFinished()) { + Serial.println("Update successfully completed. Rebooting..."); + delay(1000); + ESP.restart(); + } else { + Serial.println("Update not finished? Something went wrong!"); + } + } else { + Serial.printf("Update.end failed: %s\n", Update.errorString()); + + // Check if it was a signature verification failure + if (Update.getError() == UPDATE_ERROR_SIGN) { + Serial.println("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"); + Serial.println("SIGNATURE VERIFICATION FAILED!"); + Serial.println("The firmware was not signed with the"); + Serial.println("correct private key or is corrupted."); + Serial.println("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"); + } + } + + http.end(); +} + +void setup() { + Serial.begin(115200); + Serial.println("\n\nSigned OTA Update Example"); + Serial.println("=========================\n"); + + // Connect to WiFi + Serial.printf("Connecting to WiFi: %s\n", ssid); + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println("\nWiFi connected!"); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + // Wait a bit before starting OTA + delay(2000); + + // Perform OTA update + performOTAUpdate(); +} + +void loop() { + // Nothing to do here + delay(1000); +} diff --git a/libraries/Update/examples/Signed_OTA_Update/build_opt.h b/libraries/Update/examples/Signed_OTA_Update/build_opt.h new file mode 100644 index 0000000..1b328fa --- /dev/null +++ b/libraries/Update/examples/Signed_OTA_Update/build_opt.h @@ -0,0 +1 @@ +-DUPDATE_SIGN diff --git a/libraries/Update/examples/Signed_OTA_Update/ci.yml b/libraries/Update/examples/Signed_OTA_Update/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/Update/examples/Signed_OTA_Update/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/Update/examples/Signed_OTA_Update/public_key.h b/libraries/Update/examples/Signed_OTA_Update/public_key.h new file mode 100644 index 0000000..90ff650 --- /dev/null +++ b/libraries/Update/examples/Signed_OTA_Update/public_key.h @@ -0,0 +1,32 @@ +// Public key for OTA signature verification +// Include this in your Arduino sketch + +// ⚠️ THIS IS A TEST KEY - DO NOT USE IN PRODUCTION! +// Generate your own keys using: +// python /tools/bin_signing.py --generate-key rsa-2048 --out private_key.pem +// python /tools/bin_signing.py --extract-pubkey private_key.pem --out public_key.pem +// +// Then replace this file with the generated public_key.h + +// Test RSA-2048 Public Key (PEM format) +const uint8_t PUBLIC_KEY[] PROGMEM = { + 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x42, 0x45, 0x47, 0x49, 0x4e, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, 0x43, 0x20, 0x4b, 0x45, 0x59, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, + 0x0a, 0x4d, 0x49, 0x49, 0x42, 0x49, 0x6a, 0x41, 0x4e, 0x42, 0x67, 0x6b, 0x71, 0x68, 0x6b, 0x69, 0x47, 0x39, 0x77, 0x30, 0x42, 0x41, 0x51, 0x45, 0x46, 0x41, + 0x41, 0x4f, 0x43, 0x41, 0x51, 0x38, 0x41, 0x4d, 0x49, 0x49, 0x42, 0x43, 0x67, 0x4b, 0x43, 0x41, 0x51, 0x45, 0x41, 0x36, 0x42, 0x33, 0x52, 0x67, 0x34, 0x39, + 0x6b, 0x4e, 0x47, 0x72, 0x44, 0x2b, 0x50, 0x46, 0x6e, 0x39, 0x64, 0x69, 0x4b, 0x0a, 0x57, 0x50, 0x34, 0x65, 0x42, 0x59, 0x4d, 0x2f, 0x49, 0x79, 0x6b, 0x55, + 0x4b, 0x4d, 0x34, 0x39, 0x63, 0x6a, 0x65, 0x56, 0x56, 0x4f, 0x39, 0x42, 0x4f, 0x30, 0x66, 0x6c, 0x47, 0x47, 0x6e, 0x47, 0x71, 0x79, 0x34, 0x50, 0x72, 0x69, + 0x4e, 0x71, 0x32, 0x62, 0x4a, 0x4a, 0x6a, 0x7a, 0x68, 0x38, 0x46, 0x32, 0x42, 0x53, 0x4f, 0x75, 0x74, 0x48, 0x77, 0x75, 0x7a, 0x6d, 0x62, 0x45, 0x52, 0x6f, + 0x0a, 0x30, 0x38, 0x51, 0x72, 0x32, 0x30, 0x4e, 0x61, 0x52, 0x72, 0x7a, 0x6e, 0x71, 0x6e, 0x59, 0x4e, 0x57, 0x4e, 0x69, 0x6e, 0x43, 0x67, 0x7a, 0x34, 0x34, + 0x49, 0x4e, 0x50, 0x50, 0x78, 0x70, 0x45, 0x55, 0x65, 0x68, 0x61, 0x32, 0x66, 0x6d, 0x6d, 0x39, 0x77, 0x5a, 0x67, 0x57, 0x31, 0x69, 0x31, 0x67, 0x31, 0x77, + 0x70, 0x68, 0x56, 0x51, 0x6c, 0x5a, 0x30, 0x49, 0x63, 0x72, 0x6d, 0x5a, 0x5a, 0x0a, 0x42, 0x61, 0x33, 0x49, 0x64, 0x6a, 0x78, 0x63, 0x52, 0x67, 0x51, 0x6c, + 0x69, 0x32, 0x4b, 0x74, 0x78, 0x72, 0x41, 0x4a, 0x67, 0x33, 0x4a, 0x47, 0x43, 0x54, 0x2f, 0x39, 0x6d, 0x7a, 0x52, 0x31, 0x70, 0x37, 0x59, 0x34, 0x50, 0x34, + 0x65, 0x71, 0x30, 0x6b, 0x2b, 0x78, 0x2b, 0x45, 0x72, 0x6f, 0x35, 0x73, 0x47, 0x69, 0x49, 0x7a, 0x33, 0x44, 0x67, 0x61, 0x50, 0x43, 0x54, 0x41, 0x37, 0x52, + 0x0a, 0x4b, 0x69, 0x75, 0x6e, 0x2f, 0x67, 0x64, 0x56, 0x71, 0x34, 0x35, 0x2f, 0x75, 0x62, 0x64, 0x53, 0x58, 0x65, 0x62, 0x50, 0x46, 0x43, 0x73, 0x36, 0x66, + 0x46, 0x73, 0x52, 0x39, 0x6d, 0x43, 0x6f, 0x37, 0x70, 0x43, 0x4b, 0x74, 0x45, 0x55, 0x51, 0x78, 0x34, 0x4d, 0x68, 0x55, 0x4e, 0x5a, 0x48, 0x48, 0x31, 0x49, + 0x33, 0x62, 0x79, 0x57, 0x35, 0x7a, 0x39, 0x36, 0x49, 0x6a, 0x46, 0x44, 0x68, 0x0a, 0x54, 0x2f, 0x64, 0x5a, 0x71, 0x32, 0x6d, 0x44, 0x54, 0x64, 0x76, 0x59, + 0x2b, 0x6d, 0x5a, 0x75, 0x51, 0x4d, 0x37, 0x6c, 0x72, 0x31, 0x4d, 0x4e, 0x6a, 0x35, 0x36, 0x79, 0x74, 0x41, 0x56, 0x4a, 0x39, 0x56, 0x7a, 0x74, 0x44, 0x75, + 0x35, 0x4f, 0x6a, 0x48, 0x32, 0x76, 0x6f, 0x32, 0x6b, 0x59, 0x46, 0x4f, 0x72, 0x52, 0x49, 0x57, 0x70, 0x5a, 0x4c, 0x56, 0x35, 0x6c, 0x47, 0x79, 0x7a, 0x45, + 0x0a, 0x33, 0x77, 0x49, 0x44, 0x41, 0x51, 0x41, 0x42, 0x0a, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x45, 0x4e, 0x44, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, 0x43, 0x20, + 0x4b, 0x45, 0x59, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x0a, 0x00, +}; +const size_t PUBLIC_KEY_LEN = 452; diff --git a/libraries/Update/keywords.txt b/libraries/Update/keywords.txt new file mode 100644 index 0000000..5ddd5d4 --- /dev/null +++ b/libraries/Update/keywords.txt @@ -0,0 +1,63 @@ +####################################### +# Syntax Coloring Map For Update +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +Update KEYWORD1 +UpdaterVerifyClass KEYWORD1 +UpdaterRSAVerifier KEYWORD1 +UpdaterECDSAVerifier KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +write KEYWORD2 +writeStream KEYWORD2 +printError KEYWORD2 +installSignature KEYWORD2 +setMD5 KEYWORD2 +md5String KEYWORD2 +canRollBack KEYWORD2 +rollBack KEYWORD2 +onProgress KEYWORD2 +abort KEYWORD2 +setupCrypt KEYWORD2 +setCryptKey KEYWORD2 +setCryptMode KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +UPDATE_ERROR_OK LITERAL1 +UPDATE_ERROR_WRITE LITERAL1 +UPDATE_ERROR_ERASE LITERAL1 +UPDATE_ERROR_READ LITERAL1 +UPDATE_ERROR_SPACE LITERAL1 +UPDATE_ERROR_SIZE LITERAL1 +UPDATE_ERROR_STREAM LITERAL1 +UPDATE_ERROR_MD5 LITERAL1 +UPDATE_ERROR_MAGIC_BYTE LITERAL1 +UPDATE_ERROR_ACTIVATE LITERAL1 +UPDATE_ERROR_NO_PARTITION LITERAL1 +UPDATE_ERROR_BAD_ARGUMENT LITERAL1 +UPDATE_ERROR_ABORT LITERAL1 +UPDATE_ERROR_DECRYPT LITERAL1 +UPDATE_ERROR_SIGN LITERAL1 +U_FLASH LITERAL1 +U_FLASHFS LITERAL1 +U_SPIFFS LITERAL1 +U_FATFS LITERAL1 +U_LITTLEFS LITERAL1 +SIGN_NONE LITERAL1 +SIGN_RSA LITERAL1 +SIGN_ECDSA LITERAL1 +HASH_SHA256 LITERAL1 +HASH_SHA384 LITERAL1 +HASH_SHA512 LITERAL1 diff --git a/libraries/Update/library.properties b/libraries/Update/library.properties new file mode 100644 index 0000000..8a2a6d9 --- /dev/null +++ b/libraries/Update/library.properties @@ -0,0 +1,9 @@ +name=Update +version=3.3.7 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=ESP32 Sketch Update Library +paragraph= +category=Other +url= +architectures=esp32 diff --git a/libraries/Update/src/HttpsOTAUpdate.cpp b/libraries/Update/src/HttpsOTAUpdate.cpp new file mode 100644 index 0000000..9cc700a --- /dev/null +++ b/libraries/Update/src/HttpsOTAUpdate.cpp @@ -0,0 +1,109 @@ +/* OTA task + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#include +#include + +#include +#include +#include + +#include "esp32-hal-log.h" +#include "esp_http_client.h" +#include "esp_https_ota.h" + +#include "HttpsOTAUpdate.h" +#define OTA_TASK_STACK_SIZE 9216 + +typedef void (*HttpEventCb)(HttpEvent_t *); + +static esp_http_client_config_t config; +static HttpEventCb cb; +static EventGroupHandle_t ota_status = NULL; //check for ota status +static EventBits_t set_bit; + +const int OTA_IDLE_BIT = BIT0; +const int OTA_UPDATING_BIT = BIT1; +const int OTA_SUCCESS_BIT = BIT2; +const int OTA_FAIL_BIT = BIT3; + +esp_err_t http_event_handler(esp_http_client_event_t *event) { + cb(event); + return ESP_OK; +} + +void https_ota_task(void *param) { + if (ota_status) { + xEventGroupSetBits(ota_status, OTA_UPDATING_BIT); + xEventGroupClearBits(ota_status, OTA_IDLE_BIT); + } + esp_https_ota_config_t cfg; + cfg.http_config = (const esp_http_client_config_t *)param; + cfg.http_client_init_cb = NULL; + cfg.bulk_flash_erase = false; //Erase entire flash partition during initialization + cfg.partial_http_download = false; //Enable Firmware image to be downloaded over multiple HTTP requests + cfg.max_http_request_size = 0; //Maximum request size for partial HTTP download + + esp_err_t ret = esp_https_ota((const esp_https_ota_config_t *)&cfg); + if (ret == ESP_OK) { + if (ota_status) { + xEventGroupClearBits(ota_status, OTA_UPDATING_BIT); + xEventGroupSetBits(ota_status, OTA_SUCCESS_BIT); + } + } else { + if (ota_status) { + xEventGroupClearBits(ota_status, OTA_UPDATING_BIT); + xEventGroupSetBits(ota_status, OTA_FAIL_BIT); + } + } + vTaskDelete(NULL); +} + +HttpsOTAStatus_t HttpsOTAUpdateClass::status() { + if (ota_status) { + set_bit = xEventGroupGetBits(ota_status); + if (set_bit == OTA_IDLE_BIT) { + return HTTPS_OTA_IDLE; + } + if (set_bit == OTA_UPDATING_BIT) { + return HTTPS_OTA_UPDATING; + } + if (set_bit == OTA_SUCCESS_BIT) { + return HTTPS_OTA_SUCCESS; + } + if (set_bit == OTA_FAIL_BIT) { + return HTTPS_OTA_FAIL; + } + } + return HTTPS_OTA_ERR; +} + +void HttpsOTAUpdateClass::onHttpEvent(HttpEventCb cbEvent) { + cb = cbEvent; +} + +void HttpsOTAUpdateClass::begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check) { + config.url = url; + config.cert_pem = cert_pem; + config.skip_cert_common_name_check = skip_cert_common_name_check; + config.event_handler = http_event_handler; + + if (!ota_status) { + ota_status = xEventGroupCreate(); + if (!ota_status) { + log_e("OTA Event Group Create Failed"); + } + xEventGroupSetBits(ota_status, OTA_IDLE_BIT); + } + + if (xTaskCreate(&https_ota_task, "https_ota_task", OTA_TASK_STACK_SIZE, &config, 5, NULL) != pdPASS) { + log_e("Couldn't create ota task\n"); + } +} + +HttpsOTAUpdateClass HttpsOTA; diff --git a/libraries/Update/src/HttpsOTAUpdate.h b/libraries/Update/src/HttpsOTAUpdate.h new file mode 100644 index 0000000..8eadc79 --- /dev/null +++ b/libraries/Update/src/HttpsOTAUpdate.h @@ -0,0 +1,34 @@ +/* OTA task + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#ifndef HTTPSOTAUPDATE_H +#define HTTPSOTAUPDATE_H +#include "esp_http_client.h" +#define HttpEvent_t esp_http_client_event_t + +typedef enum { + HTTPS_OTA_IDLE, + HTTPS_OTA_UPDATING, + HTTPS_OTA_SUCCESS, + HTTPS_OTA_FAIL, + HTTPS_OTA_ERR +} HttpsOTAStatus_t; + +class HttpsOTAUpdateClass { + +public: + void begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check = true); + void onHttpEvent(void (*http_event_cb_t)(HttpEvent_t *)); + HttpsOTAStatus_t status(); +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_HTTPSOTAUPDATE) +extern HttpsOTAUpdateClass HttpsOTA; +#endif + +#endif diff --git a/libraries/Update/src/Update.h b/libraries/Update/src/Update.h new file mode 100644 index 0000000..3579237 --- /dev/null +++ b/libraries/Update/src/Update.h @@ -0,0 +1,377 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ESP32UPDATER_H +#define ESP32UPDATER_H + +#include +#include +#include +#include "esp_partition.h" +#ifdef UPDATE_SIGN +#include "Updater_Signing.h" +#endif /* UPDATE_SIGN */ + +#define UPDATE_ERROR_OK (0) ///< Update completed without error +#define UPDATE_ERROR_WRITE (1) ///< Write operation failed +#define UPDATE_ERROR_ERASE (2) ///< Erase operation failed +#define UPDATE_ERROR_READ (3) ///< Read operation failed +#define UPDATE_ERROR_SPACE (4) ///< Not enough space for update +#define UPDATE_ERROR_SIZE (5) ///< Provided size is invalid +#define UPDATE_ERROR_STREAM (6) ///< Stream read timeout or error +#define UPDATE_ERROR_MD5 (7) ///< MD5 checksum mismatch +#define UPDATE_ERROR_MAGIC_BYTE (8) ///< Magic byte/header mismatch +#define UPDATE_ERROR_ACTIVATE (9) ///< Activation failed +#define UPDATE_ERROR_NO_PARTITION (10) ///< No suitable partition found +#define UPDATE_ERROR_BAD_ARGUMENT (11) ///< Bad argument provided to API +#define UPDATE_ERROR_ABORT (12) ///< Update was aborted +#define UPDATE_ERROR_DECRYPT (13) ///< Decryption failed +#define UPDATE_ERROR_SIGN (14) ///< Signature verification failed + +#define UPDATE_SIZE_UNKNOWN 0xFFFFFFFF ///< Constant indicating update size is unknown + +#define U_FLASH 0 ///< Update target: Flash (OTA) +#define U_FLASHFS 100 ///< Update target: Flash filesystem (legacy) +#define U_SPIFFS 101 ///< Update target: SPIFFS filesystem +#define U_FATFS 102 ///< Update target: FAT filesystem +#define U_LITTLEFS 103 ///< Update target: LittleFS filesystem +#define U_AUTH 200 ///< Update target: Authentication/secure update + +#define ENCRYPTED_BLOCK_SIZE 16 ///< Encrypted block size in bytes +#define ENCRYPTED_TWEAK_BLOCK_SIZE 32 ///< Tweak block size used in encrypted images +#define ENCRYPTED_KEY_SIZE 32 ///< Encryption key size in bytes + +#define U_AES_DECRYPT_NONE 0 ///< No AES decryption: image is not encrypted +#define U_AES_DECRYPT_AUTO 1 ///< Auto-detect decryption needs +#define U_AES_DECRYPT_ON 2 ///< Force AES decryption on image +#define U_AES_DECRYPT_MODE_MASK 3 ///< Mask for decryption mode bits +#define U_AES_IMAGE_DECRYPTING_BIT 4 ///< Bit flag indicating image is being decrypted + +#define SPI_SECTORS_PER_BLOCK 16 // usually large erase block is 32k/64k ///< Number of SPI sectors per erase block (platform dependent) +#define SPI_FLASH_BLOCK_SIZE (SPI_SECTORS_PER_BLOCK * SPI_FLASH_SEC_SIZE) ///< Calculated SPI flash block size in bytes + +class UpdateClass { +public: + typedef std::function THandlerFunction_Progress; + + /** + * @brief Construct a new UpdateClass object + */ + UpdateClass(); + + /** + * @brief Register a progress callback + * + * The callback will be called with two arguments: number of bytes + * processed and total number of bytes expected. + * + * @param fn Callback function to receive progress updates + * @return Reference to this UpdateClass for chaining + */ + UpdateClass &onProgress(THandlerFunction_Progress fn); + + /** + * @brief Prepare the updater and reserve space + * + * @param size Size of incoming update in bytes or UPDATE_SIZE_UNKNOWN + * @param command Target command/partition type (e.g., `U_FLASH`) + * @param ledPin Optional LED pin to toggle during update + * @param ledOn LED active state (HIGH/LOW) + * @param label Optional partition label for selection + * @return true if preparation succeeded and there is enough space + * @return false on failure + */ + bool begin(size_t size = UPDATE_SIZE_UNKNOWN, int command = U_FLASH, int ledPin = -1, uint8_t ledOn = LOW, const char *label = NULL); + +#ifndef UPDATE_NOCRYPT + /** + * @brief Configure decryption parameters for encrypted images + * + * @param cryptKey Pointer to 32-byte AES key (or NULL to leave unchanged) + * @param cryptAddress Address/offset used for tweak calculation + * @param cryptConfig Lower nibble configuration bits for decryption + * @param cryptMode Decryption mode (`U_AES_DECRYPT_AUTO`, `U_AES_DECRYPT_ON`, etc.) + * @return true on success + * @return false on failure + */ + bool setupCrypt(const uint8_t *cryptKey = 0, size_t cryptAddress = 0, uint8_t cryptConfig = 0xf, int cryptMode = U_AES_DECRYPT_AUTO); +#endif /* UPDATE_NOCRYPT */ + + /** + * @brief Write a buffer to the update target + * + * Writes `len` bytes from `data` into the current update partition and + * advances the internal write pointer. + * + * @param data Pointer to data buffer + * @param len Number of bytes to write + * @return Number of bytes actually written + */ + size_t write(uint8_t *data, size_t len); + + /** + * @brief Write remaining bytes from a `Stream` to the update target + * + * Uses `readBytes()` and will set `UPDATE_ERROR_STREAM` on timeout. + * Suitable for slow sources such as `Serial`. + * + * @param data Stream to read from + * @return Number of bytes written + */ + size_t writeStream(Stream &data); + + /** + * @brief Finalize the update + * + * If all bytes have been written, this writes update configuration + * (e.g., eboot) and returns true. On error or if incomplete (and + * `evenIfRemaining` is false) it aborts and returns false. + * + * @param evenIfRemaining If true, accept incomplete updates and finalize + * @return true on successful finalization + * @return false on failure + */ + bool end(bool evenIfRemaining = false); + +#ifndef UPDATE_NOCRYPT + /** + * @brief Set AES256 decryption key + * + * @param cryptKey Pointer to 32-byte key + * @return true on success + */ + bool setCryptKey(const uint8_t *cryptKey); + + /** + * @brief Set crypt mode used for image decryption + * + * @param cryptMode One of `U_AES_DECRYPT_*` values + * @return true on success + */ + bool setCryptMode(const int cryptMode); + + /** + * @brief Set decryption address/offset + * + * The address is used when deriving tweaks for per-block decryption. + * Only the aligned part of the address is used (low bits cleared). + * + * @param cryptAddress Address/offset value + */ + void setCryptAddress(const size_t cryptAddress) { + _cryptAddress = cryptAddress & 0x00fffff0; + } + + /** + * @brief Set decryption configuration bits + * + * @param cryptConfig Configuration nibble used by the decryptor + */ + void setCryptConfig(const uint8_t cryptConfig) { + _cryptCfg = cryptConfig & 0x0f; + } +#endif /* UPDATE_NOCRYPT */ + + /** + * @brief Abort the running update and clear state + */ + void abort(); + + /** + * @brief Print the last error code and message to a `Print` stream + * + * @param out Output stream (e.g., `Serial`) + */ + void printError(Print &out); + + /** + * @brief Return a human-readable string for the last error + * + * @return const char* Pointer to a static error description + */ + const char *errorString(); + + /** + * @brief Set expected MD5 checksum for the incoming firmware image + * + * @param expected_md5 Hex string containing expected MD5 digest + * @param calc_post_decryption If true, calculate MD5 after decryption + * @return true if MD5 was accepted + */ + bool setMD5( + const char *expected_md5 +#ifndef UPDATE_NOCRYPT + , + bool calc_post_decryption = true +#endif /* #ifdef UPDATE_NOCRYPT */ + ); + + /** + * @brief Get MD5 digest string of the successfully completed firmware + * + * @return String Hex representation of MD5 digest + */ + String md5String(void) { + return _md5.toString(); + } + + /** + * @brief Retrieve the raw MD5 bytes of the completed firmware + * + * @param result Pointer to a 16-byte buffer to receive MD5 bytes + */ + void md5(uint8_t *result) { + return _md5.getBytes(result); + } + +#ifdef UPDATE_SIGN + /** + * @brief Install signature verification for update images + * + * Call before `begin()` to enable signature verification. The verifier + * determines hash type and signature format. + * + * @param sign Pointer to a verifier instance + * @return true if verifier was installed successfully + */ + bool installSignature(UpdaterVerifyClass *sign); +#endif /* UPDATE_SIGN */ + + //Helpers + uint8_t getError() { + return _error; + } + void clearError() { + _error = UPDATE_ERROR_OK; + } + bool hasError() { + return _error != UPDATE_ERROR_OK; + } + + bool isRunning() { + return _size > 0; + } + bool isFinished() { + return _progress == _size; + } + size_t size() { + return _size; + } + size_t progress() { + return _progress; + } + size_t remaining() { + return _size - _progress; + } + + /* + Template to write from objects that expose + available() and read(uint8_t*, size_t) methods + faster than the writeStream method + writes only what is available + */ + template size_t write(T &data) { + size_t written = 0; + if (hasError() || !isRunning()) { + return 0; + } + + size_t available = data.available(); + while (available) { + if (_bufferLen + available > remaining()) { + available = remaining() - _bufferLen; + } + if (_bufferLen + available > 4096) { + size_t toBuff = 4096 - _bufferLen; + data.read(_buffer + _bufferLen, toBuff); + _bufferLen += toBuff; + if (!_writeBuffer()) { + return written; + } + written += toBuff; + } else { + data.read(_buffer + _bufferLen, available); + _bufferLen += available; + written += available; + if (_bufferLen == remaining()) { + if (!_writeBuffer()) { + return written; + } + } + } + if (remaining() == 0) { + return written; + } + available = data.available(); + } + return written; + } + + /* + check if there is a firmware on the other OTA partition that you can bootinto + */ + bool canRollBack(); + /* + set the other OTA partition as bootable (reboot to enable) + */ + bool rollBack(); + +private: + void _reset(); + void _abort(uint8_t err); +#ifndef UPDATE_NOCRYPT + void _cryptKeyTweak(size_t cryptAddress, uint8_t *tweaked_key); + bool _decryptBuffer(); +#endif /* UPDATE_NOCRYPT */ + bool _writeBuffer(); + bool _verifyHeader(uint8_t data); + bool _verifyEnd(); + bool _enablePartition(const esp_partition_t *partition); + bool _chkDataInBlock(const uint8_t *data, size_t len) const; // check if block contains any data or is empty + + uint8_t _error; +#ifndef UPDATE_NOCRYPT + uint8_t *_cryptKey; + uint8_t *_cryptBuffer; +#endif /* UPDATE_NOCRYPT */ + uint8_t *_buffer; + uint8_t *_skipBuffer; + size_t _bufferLen; + size_t _size; + THandlerFunction_Progress _progress_callback; + uint32_t _progress; + uint32_t _command; + const esp_partition_t *_partition; + + String _target_md5; +#ifndef UPDATE_NOCRYPT + bool _target_md5_decrypted = true; +#endif /* UPDATE_NOCRYPT */ + MD5Builder _md5; + + int _ledPin; + uint8_t _ledOn; + +#ifndef UPDATE_NOCRYPT + uint8_t _cryptMode; + size_t _cryptAddress; + uint8_t _cryptCfg; +#endif /* UPDATE_NOCRYPT */ + +#ifdef UPDATE_SIGN + SHA2Builder *_hash; + UpdaterVerifyClass *_sign; + uint8_t *_signatureBuffer; + size_t _signatureSize; + int _hashType; +#endif /* UPDATE_SIGN */ +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_UPDATE) +extern UpdateClass Update; +#endif + +#endif diff --git a/libraries/Update/src/Updater.cpp b/libraries/Update/src/Updater.cpp new file mode 100644 index 0000000..c5ad1f4 --- /dev/null +++ b/libraries/Update/src/Updater.cpp @@ -0,0 +1,895 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "Update.h" +#include "Arduino.h" +#include "spi_flash_mmap.h" +#include "esp_ota_ops.h" +#include "esp_image_format.h" +#ifndef UPDATE_NOCRYPT +#include "mbedtls/aes.h" +#endif /* UPDATE_NOCRYPT */ + +static const char *_err2str(uint8_t _error) { + if (_error == UPDATE_ERROR_OK) { + return ("No Error"); + } else if (_error == UPDATE_ERROR_WRITE) { + return ("Flash Write Failed"); + } else if (_error == UPDATE_ERROR_ERASE) { + return ("Flash Erase Failed"); + } else if (_error == UPDATE_ERROR_READ) { + return ("Flash Read Failed"); + } else if (_error == UPDATE_ERROR_SPACE) { + return ("Not Enough Space"); + } else if (_error == UPDATE_ERROR_SIZE) { + return ("Bad Size Given"); + } else if (_error == UPDATE_ERROR_STREAM) { + return ("Stream Read Timeout"); + } else if (_error == UPDATE_ERROR_MD5) { + return ("MD5 Check Failed"); + } else if (_error == UPDATE_ERROR_MAGIC_BYTE) { + return ("Wrong Magic Byte"); + } else if (_error == UPDATE_ERROR_ACTIVATE) { + return ("Could Not Activate The Firmware"); + } else if (_error == UPDATE_ERROR_NO_PARTITION) { + return ("Partition Could Not be Found"); + } else if (_error == UPDATE_ERROR_BAD_ARGUMENT) { + return ("Bad Argument"); + } else if (_error == UPDATE_ERROR_ABORT) { + return ("Aborted"); +#ifndef UPDATE_NOCRYPT + } else if (_error == UPDATE_ERROR_DECRYPT) { + return ("Decryption error"); +#endif /* UPDATE_NOCRYPT */ +#ifdef UPDATE_SIGN + } else if (_error == UPDATE_ERROR_SIGN) { + return ("Signature Verification Failed"); +#endif /* UPDATE_SIGN */ + } + return ("UNKNOWN"); +} + +static bool _partitionIsBootable(const esp_partition_t *partition) { + uint8_t buf[ENCRYPTED_BLOCK_SIZE]; + if (!partition) { + return false; + } + if (!ESP.partitionRead(partition, 0, (uint32_t *)buf, ENCRYPTED_BLOCK_SIZE)) { + return false; + } + + if (buf[0] != ESP_IMAGE_HEADER_MAGIC) { + return false; + } + return true; +} + +bool UpdateClass::_enablePartition(const esp_partition_t *partition) { + if (!partition) { + return false; + } + return ESP.partitionWrite(partition, 0, (uint32_t *)_skipBuffer, ENCRYPTED_BLOCK_SIZE); +} + +UpdateClass::UpdateClass() + : _error(0), +#ifndef UPDATE_NOCRYPT + _cryptKey(0), _cryptBuffer(0), +#endif /* UPDATE_NOCRYPT */ + _buffer(0), _skipBuffer(0), _bufferLen(0), _size(0), _progress_callback(NULL), _progress(0), _command(U_FLASH), _partition(NULL) +#ifndef UPDATE_NOCRYPT + , + _cryptMode(U_AES_DECRYPT_AUTO), _cryptAddress(0), _cryptCfg(0xf) +#endif /* UPDATE_NOCRYPT */ +#ifdef UPDATE_SIGN + , + _hash(NULL), _sign(NULL), _signatureBuffer(NULL), _signatureSize(0), _hashType(-1) +#endif /* UPDATE_SIGN */ +{ +} + +UpdateClass &UpdateClass::onProgress(THandlerFunction_Progress fn) { + _progress_callback = fn; + return *this; +} + +void UpdateClass::_reset() { + if (_buffer) { + delete[] _buffer; + } + if (_skipBuffer) { + delete[] _skipBuffer; + } +#ifdef UPDATE_SIGN + if (_signatureBuffer) { + delete[] _signatureBuffer; + _signatureBuffer = nullptr; + } + if (_hash && _hashType >= 0) { + // Clean up internally-created hash object + delete _hash; + _hash = nullptr; + } +#endif /* UPDATE_SIGN */ + +#ifndef UPDATE_NOCRYPT + _cryptBuffer = nullptr; +#endif /* UPDATE_NOCRYPT */ + _buffer = nullptr; + _skipBuffer = nullptr; + _bufferLen = 0; + _progress = 0; + _size = 0; + _command = U_FLASH; +#ifdef UPDATE_SIGN + _signatureSize = 0; +#endif /* UPDATE_SIGN */ + + if (_ledPin != -1) { + digitalWrite(_ledPin, !_ledOn); // off + } +} + +bool UpdateClass::canRollBack() { + if (_buffer) { //Update is running + return false; + } + const esp_partition_t *partition = esp_ota_get_next_update_partition(NULL); + return _partitionIsBootable(partition); +} + +bool UpdateClass::rollBack() { + if (_buffer) { //Update is running + return false; + } + const esp_partition_t *partition = esp_ota_get_next_update_partition(NULL); + return _partitionIsBootable(partition) && !esp_ota_set_boot_partition(partition); +} + +#ifdef UPDATE_SIGN +bool UpdateClass::installSignature(UpdaterVerifyClass *sign) { + if (_size > 0) { + log_w("Update already running"); + return false; + } + if (!sign) { + log_e("Invalid verifier"); + return false; + } + + int hashType = sign->getHashType(); + if (hashType != HASH_SHA256 && hashType != HASH_SHA384 && hashType != HASH_SHA512) { + log_e("Invalid hash type: %d", hashType); + return false; + } + + _sign = sign; + _hashType = hashType; + _signatureSize = 512; // Fixed signature size (padded to 512 bytes) + + [[maybe_unused]] + const char *hashName = (hashType == HASH_SHA256) ? "SHA-256" + : (hashType == HASH_SHA384) ? "SHA-384" + : "SHA-512"; + log_i("Signature verification installed (hash: %s, signature size: %u bytes)", hashName, _signatureSize); + return true; +} +#endif /* UPDATE_SIGN */ + +bool UpdateClass::begin(size_t size, int command, int ledPin, uint8_t ledOn, const char *label) { + (void)label; + + if (_size > 0) { + log_w("already running"); + return false; + } + + _ledPin = ledPin; + _ledOn = !!ledOn; // 0(LOW) or 1(HIGH) + + _reset(); + _error = 0; + _target_md5 = emptyString; + _md5 = MD5Builder(); + +#ifdef UPDATE_SIGN + // Create and initialize signature hash if signature verification is enabled + if (_sign && _hashType >= 0) { + // Create the appropriate hash builder based on hashType + switch (_hashType) { + case HASH_SHA256: _hash = new SHA256Builder(); break; + case HASH_SHA384: _hash = new SHA384Builder(); break; + case HASH_SHA512: _hash = new SHA512Builder(); break; + default: log_e("Invalid hash type"); return false; + } + + if (_hash) { + _hash->begin(); + log_i("Signature hash initialized"); + } else { + log_e("Failed to create hash builder"); + return false; + } + } +#endif /* UPDATE_SIGN */ + + if (size == 0) { + _error = UPDATE_ERROR_SIZE; + return false; + } + +#ifdef UPDATE_SIGN + // Validate size is large enough to contain firmware + signature + if (_signatureSize > 0 && size < _signatureSize) { + _error = UPDATE_ERROR_SIZE; + log_e("Size too small for signature: %u < %u", size, _signatureSize); + return false; + } +#endif /* UPDATE_SIGN */ + + if (command == U_FLASH) { + _partition = esp_ota_get_next_update_partition(NULL); + if (!_partition || _partition == esp_ota_get_running_partition()) { + _error = UPDATE_ERROR_NO_PARTITION; + return false; + } + log_d("OTA Partition: %s", _partition->label); + } else if (command == U_SPIFFS) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, NULL); + if (!_partition) { + _error = UPDATE_ERROR_NO_PARTITION; + return false; + } + log_d("SPIFFS Partition: %s", _partition->label); + } else if (command == U_FATFS) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, NULL); + if (!_partition) { + _error = UPDATE_ERROR_NO_PARTITION; + return false; + } + log_d("FATFS Partition: %s", _partition->label); + } else if (command == U_LITTLEFS) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_LITTLEFS, NULL); + if (!_partition) { + _error = UPDATE_ERROR_NO_PARTITION; + return false; + } + log_d("LittleFS Partition: %s", _partition->label); + } else if (command == U_FLASHFS) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, NULL); + if (!_partition) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, NULL); + } + if (!_partition) { + _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_LITTLEFS, NULL); + } + if (!_partition) { + _error = UPDATE_ERROR_NO_PARTITION; + return false; + } + log_d("FS Partition: %s", _partition->label); + } else { + _error = UPDATE_ERROR_BAD_ARGUMENT; + log_e("bad command %u", command); + return false; + } + + if (size == UPDATE_SIZE_UNKNOWN) { + size = _partition->size; + } else if (size > _partition->size) { + _error = UPDATE_ERROR_SIZE; + log_e("too large %u > %u", size, _partition->size); + return false; + } + + //initialize + _buffer = new (std::nothrow) uint8_t[SPI_FLASH_SEC_SIZE]; + if (!_buffer) { + log_e("_buffer allocation failed"); + return false; + } + _size = size; + _command = command; + _md5.begin(); + return true; +} + +#ifndef UPDATE_NOCRYPT +bool UpdateClass::setupCrypt(const uint8_t *cryptKey, size_t cryptAddress, uint8_t cryptConfig, int cryptMode) { + if (setCryptKey(cryptKey)) { + if (setCryptMode(cryptMode)) { + setCryptAddress(cryptAddress); + setCryptConfig(cryptConfig); + return true; + } + } + return false; +} + +bool UpdateClass::setCryptKey(const uint8_t *cryptKey) { + if (!cryptKey) { + if (_cryptKey) { + delete[] _cryptKey; + _cryptKey = 0; + log_d("AES key unset"); + } + return false; //key cleared, no key to decrypt with + } + //initialize + if (!_cryptKey) { + _cryptKey = new (std::nothrow) uint8_t[ENCRYPTED_KEY_SIZE]; + } + if (!_cryptKey) { + log_e("new failed"); + return false; + } + memcpy(_cryptKey, cryptKey, ENCRYPTED_KEY_SIZE); + return true; +} + +bool UpdateClass::setCryptMode(const int cryptMode) { + if (cryptMode >= U_AES_DECRYPT_NONE && cryptMode <= U_AES_DECRYPT_ON) { + _cryptMode = cryptMode; + } else { + log_e("bad crypt mode argument %i", cryptMode); + return false; + } + return true; +} +#endif /* UPDATE_NOCRYPT */ + +void UpdateClass::_abort(uint8_t err) { + _reset(); + _error = err; +} + +void UpdateClass::abort() { + _abort(UPDATE_ERROR_ABORT); +} + +#ifndef UPDATE_NOCRYPT +/* + * Generates an address-tweaked encryption key for ESP32 flash encryption. + * + * Key Tweaking Overview: + * ---------------------- + * ESP32 flash encryption uses "key tweaking" to derive a unique effective key + * for each 32-byte region of flash. This prevents attackers from: + * - Swapping encrypted blocks between different flash addresses + * - Using known-plaintext from one region to attack another + * + * The tweak is computed by XORing address bits into the base key according + * to a specific pattern that matches ESP32's hardware flash encryption. + * + * Parameters: + * cryptAddress - Flash address used to derive the tweak (aligned to 32 bytes) + * tweaked_key - Output buffer for the 32-byte tweaked key + * + * Configuration (_cryptCfg): + * -------------------------- + * The _cryptCfg value (0x0 to 0xF) controls how much address information + * is mixed into the key: + * - 0x0: No tweaking, use base key as-is (lowest security) + * - 0xF: Full tweaking, maximum address mixing (highest security, default) + * - Other values: Partial tweaking for compatibility + * + * This matches the --flash_crypt_conf parameter in espsecure.py + */ +void UpdateClass::_cryptKeyTweak(size_t cryptAddress, uint8_t *tweaked_key) { + memcpy(tweaked_key, _cryptKey, ENCRYPTED_KEY_SIZE); + if (_cryptCfg == 0) { + return; // No tweaking needed, use base key as-is + } + + // Pattern defines which address bits to mix into each key region + // Values represent bit positions (23, 14, 12, 10, 8) used for tweaking + const uint8_t pattern[] = {23, 23, 23, 14, 23, 23, 23, 12, 23, 23, 23, 10, 23, 23, 23, 8}; + int pattern_idx = 0; + int key_idx = 0; + int bit_len = 0; + uint32_t tweak = 0; + + // Extract address bits 23-5 (aligned to 32-byte boundary) + cryptAddress &= 0x00ffffe0; + cryptAddress <<= 8; // Shift bit 23 to MSB position for easier manipulation + + // XOR address-derived bits into the key + while (pattern_idx < sizeof(pattern)) { + tweak = cryptAddress << (23 - pattern[pattern_idx]); + // Rotate to align with previous tweak bits + tweak = (tweak << (8 - bit_len)) | (tweak >> (24 + bit_len)); + bit_len += pattern[pattern_idx++] - 4; + + // XOR full bytes + while (bit_len > 7) { + tweaked_key[key_idx++] ^= tweak; + tweak = (tweak << 8) | (tweak >> 24); // Rotate left 8 bits + bit_len -= 8; + } + tweaked_key[key_idx] ^= tweak; // XOR remaining bits + } + + if (_cryptCfg == 0xf) { + return; // Full tweaking complete + } + + // Partial tweaking: restore some key bits based on _cryptCfg + // Each bit in _cryptCfg controls whether a key region stays tweaked or reverts + const uint8_t cfg_bits[] = {67, 65, 63, 61}; + key_idx = 0; + pattern_idx = 0; + while (key_idx < ENCRYPTED_KEY_SIZE) { + bit_len += cfg_bits[pattern_idx]; + if ((_cryptCfg & (1 << pattern_idx)) == 0) { + // Restore original key bits for this region + while (bit_len > 0) { + if (bit_len > 7 || ((_cryptCfg & (2 << pattern_idx)) == 0)) { + tweaked_key[key_idx] = _cryptKey[key_idx]; + } else { + // Partial byte: MSBits from original, LSBits stay tweaked + tweaked_key[key_idx] &= (0xff >> bit_len); + tweaked_key[key_idx] |= (_cryptKey[key_idx] & (~(0xff >> bit_len))); + } + key_idx++; + bit_len -= 8; + } + } else { + // Keep tweaked bits for this region + while (bit_len > 0) { + if (bit_len < 8 && ((_cryptCfg & (2 << pattern_idx)) == 0)) { + // Partial byte: MSBits stay tweaked, LSBits from original + tweaked_key[key_idx] &= (~(0xff >> bit_len)); + tweaked_key[key_idx] |= (_cryptKey[key_idx] & (0xff >> bit_len)); + } + key_idx++; + bit_len -= 8; + } + } + pattern_idx++; + } +} + +/* + * Decrypts the OTA update buffer using ESP32 flash encryption compatible algorithm. + * + * ESP32 Flash Encryption Scheme: + * ------------------------------ + * This function implements a decryption algorithm compatible with ESP32's flash + * encryption, which uses a symmetric (involutory) construction: + * + * Transform(data) = ByteReverse(AES_Encrypt(ByteReverse(data))) + * + * This transform is its own inverse: Transform(Transform(data)) = data + * Therefore, the SAME operation is used for both encryption and decryption. + * + * Algorithm steps for each 16-byte block: + * 1. Reverse the byte order of the block + * 2. Apply AES-256 encryption (NOT decryption!) with address-tweaked key + * 3. Reverse the byte order of the result + * + * Why AES_ENCRYPT for decryption? + * ------------------------------- + * The byte reversal combined with the key tweaking creates a mathematical + * structure where AES encryption serves as its own inverse. This design: + * - Matches ESP32 hardware flash encryption controller behavior + * - Simplifies bootloader (only needs encrypt logic) + * - Allows same code path for encrypt/decrypt operations + * + * Key Tweaking: + * ------------- + * The encryption key is "tweaked" based on the flash address every 32 bytes + * (ENCRYPTED_TWEAK_BLOCK_SIZE). This provides: + * - Different effective keys for different flash regions + * - Protection against block-swapping attacks + * + * Note: Since we use MBEDTLS_AES_ENCRYPT mode, we must call mbedtls_aes_setkey_enc() + * to set up the correct round keys. The encryption key schedule is required even + * though this function performs decryption. + * + * Reference: ESP-IDF flash encryption documentation + * https://docs.espressif.com/projects/esp-idf/en/latest/esp32/security/flash-encryption.html + */ +bool UpdateClass::_decryptBuffer() { + if (!_cryptKey) { + log_w("AES key not set"); + return false; + } + if (_bufferLen % ENCRYPTED_BLOCK_SIZE != 0) { + log_e("buffer size error"); + return false; + } + if (!_cryptBuffer) { + _cryptBuffer = new (std::nothrow) uint8_t[ENCRYPTED_BLOCK_SIZE]; + } + if (!_cryptBuffer) { + log_e("new failed"); + return false; + } + + uint8_t tweaked_key[ENCRYPTED_KEY_SIZE]; + int done = 0; + + mbedtls_aes_context ctx; + mbedtls_aes_init(&ctx); + + while ((_bufferLen - done) >= ENCRYPTED_BLOCK_SIZE) { + // Step 1: Reverse byte order of the 16-byte block + for (int i = 0; i < ENCRYPTED_BLOCK_SIZE; i++) { + _cryptBuffer[(ENCRYPTED_BLOCK_SIZE - 1) - i] = _buffer[i + done]; + } + + // Update tweaked key every ENCRYPTED_TWEAK_BLOCK_SIZE (32) bytes or at start + if (((_cryptAddress + _progress + done) % ENCRYPTED_TWEAK_BLOCK_SIZE) == 0 || done == 0) { + _cryptKeyTweak(_cryptAddress + _progress + done, tweaked_key); + // Use setkey_enc because we perform AES_ENCRYPT operation below + if (mbedtls_aes_setkey_enc(&ctx, tweaked_key, 256)) { + return false; + } + } + + // Step 2: Apply AES encryption (this decrypts due to the involutory scheme) + if (mbedtls_aes_crypt_ecb(&ctx, MBEDTLS_AES_ENCRYPT, _cryptBuffer, _cryptBuffer)) { + return false; + } + + // Step 3: Reverse byte order back to get the decrypted plaintext + for (int i = 0; i < ENCRYPTED_BLOCK_SIZE; i++) { + _buffer[i + done] = _cryptBuffer[(ENCRYPTED_BLOCK_SIZE - 1) - i]; + } + + done += ENCRYPTED_BLOCK_SIZE; + } + + return true; +} +#endif /* UPDATE_NOCRYPT */ + +bool UpdateClass::_writeBuffer() { +#ifndef UPDATE_NOCRYPT + //first bytes of loading image, check to see if loading image needs decrypting + if (!_progress) { + _cryptMode &= U_AES_DECRYPT_MODE_MASK; + if ((_cryptMode == U_AES_DECRYPT_ON) || ((_command == U_FLASH) && (_cryptMode & U_AES_DECRYPT_AUTO) && (_buffer[0] != ESP_IMAGE_HEADER_MAGIC))) { + _cryptMode |= U_AES_IMAGE_DECRYPTING_BIT; //set to decrypt the loading image + log_d("Decrypting OTA Image"); + } + } + + if (!_target_md5_decrypted) { + _md5.add(_buffer, _bufferLen); + } + + //check if data in buffer needs decrypting + if (_cryptMode & U_AES_IMAGE_DECRYPTING_BIT) { + if (!_decryptBuffer()) { + _abort(UPDATE_ERROR_DECRYPT); + return false; + } + } +#endif /* UPDATE_NOCRYPT */ + //first bytes of new firmware + uint8_t skip = 0; + if (!_progress && _command == U_FLASH) { + //check magic + if (_buffer[0] != ESP_IMAGE_HEADER_MAGIC) { + _abort(UPDATE_ERROR_MAGIC_BYTE); + return false; + } + + //Stash the first 16 bytes of data and set the offset so they are + //not written at this point so that partially written firmware + //will not be bootable + skip = ENCRYPTED_BLOCK_SIZE; + _skipBuffer = new (std::nothrow) uint8_t[skip]; + if (!_skipBuffer) { + log_e("_skipBuffer allocation failed"); + return false; + } + memcpy(_skipBuffer, _buffer, skip); + } + if (!_progress && _progress_callback) { + _progress_callback(0, _size); + } + size_t offset = _partition->address + _progress; + bool block_erase = + (_size - _progress >= SPI_FLASH_BLOCK_SIZE) && (offset % SPI_FLASH_BLOCK_SIZE == 0); // if it's the block boundary, than erase the whole block from here + bool part_head_sectors = + _partition->address % SPI_FLASH_BLOCK_SIZE + && offset < (_partition->address / SPI_FLASH_BLOCK_SIZE + 1) * SPI_FLASH_BLOCK_SIZE; // sector belong to unaligned partition heading block + bool part_tail_sectors = + offset >= (_partition->address + _size) / SPI_FLASH_BLOCK_SIZE * SPI_FLASH_BLOCK_SIZE; // sector belong to unaligned partition tailing block + if (block_erase || part_head_sectors || part_tail_sectors) { + if (!ESP.partitionEraseRange(_partition, _progress, block_erase ? SPI_FLASH_BLOCK_SIZE : SPI_FLASH_SEC_SIZE)) { + _abort(UPDATE_ERROR_ERASE); + return false; + } + } + + // try to skip empty blocks on unencrypted partitions + if ((_partition->encrypted || _chkDataInBlock(_buffer + skip / sizeof(uint32_t), _bufferLen - skip)) + && !ESP.partitionWrite(_partition, _progress + skip, (uint32_t *)_buffer + skip / sizeof(uint32_t), _bufferLen - skip)) { + _abort(UPDATE_ERROR_WRITE); + return false; + } + + //restore magic or md5 will fail + if (!_progress && _command == U_FLASH) { + _buffer[0] = ESP_IMAGE_HEADER_MAGIC; + } +#ifndef UPDATE_NOCRYPT + if (_target_md5_decrypted) { +#endif /* UPDATE_NOCRYPT */ + _md5.add(_buffer, _bufferLen); +#ifndef UPDATE_NOCRYPT + } +#endif /* UPDATE_NOCRYPT */ + +#ifdef UPDATE_SIGN + // Add data to signature hash if signature verification is enabled + // Only hash firmware bytes, not the signature bytes at the end + if (_hash && _signatureSize > 0) { + size_t firmwareSize = _size - _signatureSize; + if (_progress < firmwareSize) { + // Calculate how many bytes of this buffer are firmware (not signature) + size_t bytesToHash = _bufferLen; + if (_progress + _bufferLen > firmwareSize) { + bytesToHash = firmwareSize - _progress; + } + _hash->add(_buffer, bytesToHash); + } + } +#endif /* UPDATE_SIGN */ + + _progress += _bufferLen; + _bufferLen = 0; + if (_progress_callback) { + _progress_callback(_progress, _size); + } + return true; +} + +bool UpdateClass::_verifyHeader(uint8_t data) { + if (_command == U_FLASH) { + if (data != ESP_IMAGE_HEADER_MAGIC) { + _abort(UPDATE_ERROR_MAGIC_BYTE); + return false; + } + return true; + } else { + return true; + } + return false; +} + +bool UpdateClass::_verifyEnd() { + if (_command == U_FLASH) { + if (!_enablePartition(_partition) || !_partitionIsBootable(_partition)) { + _abort(UPDATE_ERROR_READ); + return false; + } + + if (esp_ota_set_boot_partition(_partition)) { + _abort(UPDATE_ERROR_ACTIVATE); + return false; + } + _reset(); + return true; + } else { + _reset(); + return true; + } + return false; +} + +bool UpdateClass::setMD5( + const char *expected_md5 +#ifndef UPDATE_NOCRYPT + , + bool calc_post_decryption +#endif /* UPDATE_NOCRYPT */ +) { + if (strlen(expected_md5) != 32) { + return false; + } + _target_md5 = expected_md5; + _target_md5.toLowerCase(); +#ifndef UPDATE_NOCRYPT + _target_md5_decrypted = calc_post_decryption; +#endif /* UPDATE_NOCRYPT */ + return true; +} + +bool UpdateClass::end(bool evenIfRemaining) { + if (hasError() || _size == 0) { + return false; + } + + if (!isFinished() && !evenIfRemaining) { + log_e("premature end: res:%u, pos:%u/%u\n", getError(), progress(), _size); + _abort(UPDATE_ERROR_ABORT); + return false; + } + + if (evenIfRemaining) { + if (_bufferLen > 0) { + _writeBuffer(); + } + _size = progress(); + } + + _md5.calculate(); + if (_target_md5.length()) { + if (_target_md5 != _md5.toString()) { + _abort(UPDATE_ERROR_MD5); + return false; + } + } + +#ifdef UPDATE_SIGN + // Verify signature if signature verification is enabled + if (_hash && _sign && _signatureSize > 0) { + log_i("Verifying signature..."); + _hash->calculate(); + + // Allocate buffer for signature (max 512 bytes for RSA-4096) + const size_t maxSigSize = 512; + _signatureBuffer = new (std::nothrow) uint8_t[maxSigSize]; + if (!_signatureBuffer) { + log_e("Failed to allocate signature buffer"); + _abort(UPDATE_ERROR_SIGN); + return false; + } + + // Read signature from partition (last 512 bytes of what was written) + size_t firmwareSize = _size - _signatureSize; + log_d("Reading signature from offset %u (firmware size: %u, total size: %u)", firmwareSize, firmwareSize, _size); + if (!ESP.partitionRead(_partition, firmwareSize, (uint32_t *)_signatureBuffer, maxSigSize)) { + log_e("Failed to read signature from partition"); + _abort(UPDATE_ERROR_SIGN); + return false; + } + + // Verify the signature + if (!_sign->verify(_hash, _signatureBuffer, maxSigSize)) { + log_e("Signature verification failed"); + _abort(UPDATE_ERROR_SIGN); + return false; + } + + log_i("Signature verified successfully"); + } +#endif /* UPDATE_SIGN */ + + return _verifyEnd(); +} + +size_t UpdateClass::write(uint8_t *data, size_t len) { + if (hasError() || !isRunning()) { + return 0; + } + + if (len > remaining()) { + _abort(UPDATE_ERROR_SPACE); + return 0; + } + + size_t left = len; + + while ((_bufferLen + left) > SPI_FLASH_SEC_SIZE) { + size_t toBuff = SPI_FLASH_SEC_SIZE - _bufferLen; + memcpy(_buffer + _bufferLen, data + (len - left), toBuff); + _bufferLen += toBuff; + if (!_writeBuffer()) { + return len - left; + } + left -= toBuff; + } + memcpy(_buffer + _bufferLen, data + (len - left), left); + _bufferLen += left; + if (_bufferLen == remaining()) { + if (!_writeBuffer()) { + return len - left; + } + } + return len; +} + +size_t UpdateClass::writeStream(Stream &data) { + size_t written = 0; + size_t toRead = 0; + int timeout_failures = 0; + + if (hasError() || !isRunning()) { + return 0; + } + +#ifndef UPDATE_NOCRYPT + if (_command == U_FLASH && !_cryptMode) { +#endif /* UPDATE_NOCRYPT */ + if (!_verifyHeader(data.peek())) { + _reset(); + return 0; + } +#ifndef UPDATE_NOCRYPT + } +#endif /* UPDATE_NOCRYPT */ + + if (_ledPin != -1) { + pinMode(_ledPin, OUTPUT); + } + + while (remaining()) { + if (_ledPin != -1) { + digitalWrite(_ledPin, _ledOn); // Switch LED on + } + size_t bytesToRead = SPI_FLASH_SEC_SIZE - _bufferLen; + if (bytesToRead > remaining()) { + bytesToRead = remaining(); + } + + /* + Init read&timeout counters and try to read, if read failed, increase counter, + wait 100ms and try to read again. If counter > 300 (30 sec), give up/abort + */ + toRead = 0; + timeout_failures = 0; + while (!toRead) { + toRead = data.readBytes(_buffer + _bufferLen, bytesToRead); + if (toRead == 0) { + timeout_failures++; + if (timeout_failures >= 300) { + _abort(UPDATE_ERROR_STREAM); + return written; + } + delay(100); + } + } + + if (_ledPin != -1) { + digitalWrite(_ledPin, !_ledOn); // Switch LED off + } + _bufferLen += toRead; + if ((_bufferLen == remaining() || _bufferLen == SPI_FLASH_SEC_SIZE) && !_writeBuffer()) { + return written; + } + written += toRead; + +#if CONFIG_FREERTOS_UNICORE + delay(1); // Fix solo WDT +#endif + } + return written; +} + +void UpdateClass::printError(Print &out) { + out.println(_err2str(_error)); +} + +const char *UpdateClass::errorString() { + return _err2str(_error); +} + +bool UpdateClass::_chkDataInBlock(const uint8_t *data, size_t len) const { + // check 32-bit aligned blocks only + if (!len || len % sizeof(uint32_t)) { + return true; + } + + size_t dwl = len / sizeof(uint32_t); + + do { + if (*(uint32_t *)data ^ 0xffffffff) { // for SPI NOR flash empty blocks are all one's, i.e. filled with 0xff byte + return true; + } + + data += sizeof(uint32_t); + } while (--dwl); + return false; +} + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_UPDATE) +UpdateClass Update; +#endif diff --git a/libraries/Update/src/Updater_Signing.cpp b/libraries/Update/src/Updater_Signing.cpp new file mode 100644 index 0000000..3332fe1 --- /dev/null +++ b/libraries/Update/src/Updater_Signing.cpp @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef UPDATE_SIGN + +#include "Updater_Signing.h" +#include "mbedtls/pk.h" +#include "mbedtls/rsa.h" +#include "mbedtls/ecdsa.h" +#include "mbedtls/ecp.h" +#include "mbedtls/md.h" +#include "esp32-hal-log.h" + +// ==================== UpdaterRSAVerifier (using mbedtls) ==================== + +UpdaterRSAVerifier::UpdaterRSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType) : _hashType(hashType), _valid(false) { + _ctx = new mbedtls_pk_context; + mbedtls_pk_init((mbedtls_pk_context *)_ctx); + + // Try to parse the public key + int ret = mbedtls_pk_parse_public_key((mbedtls_pk_context *)_ctx, pubkey, pubkeyLen); + if (ret != 0) { + log_e("Failed to parse RSA public key: -0x%04X", -ret); + return; + } + + // Verify it's an RSA key + if (mbedtls_pk_get_type((mbedtls_pk_context *)_ctx) != MBEDTLS_PK_RSA) { + log_e("Public key is not RSA"); + return; + } + + _valid = true; + log_i("RSA public key loaded successfully"); +} + +UpdaterRSAVerifier::~UpdaterRSAVerifier() { + if (_ctx) { + mbedtls_pk_free((mbedtls_pk_context *)_ctx); + delete (mbedtls_pk_context *)_ctx; + _ctx = nullptr; + } +} + +bool UpdaterRSAVerifier::verify(SHA2Builder *hash, const void *signature, size_t signatureLen) { + if (!_valid || !hash) { + log_e("Invalid RSA verifier or hash"); + return false; + } + + mbedtls_md_type_t md_type; + switch (_hashType) { + case HASH_SHA256: md_type = MBEDTLS_MD_SHA256; break; + case HASH_SHA384: md_type = MBEDTLS_MD_SHA384; break; + case HASH_SHA512: md_type = MBEDTLS_MD_SHA512; break; + default: log_e("Invalid hash type"); return false; + } + + // Get hash bytes from the builder + uint8_t hashBytes[64]; // Max hash size (SHA-512) + hash->getBytes(hashBytes); + + int ret = mbedtls_pk_verify((mbedtls_pk_context *)_ctx, md_type, hashBytes, hash->getHashSize(), (const unsigned char *)signature, signatureLen); + + if (ret == 0) { + log_i("RSA signature verified successfully"); + return true; + } else { + log_e("RSA signature verification failed: -0x%04X", -ret); + return false; + } +} + +// ==================== UpdaterECDSAVerifier (using mbedtls) ==================== + +UpdaterECDSAVerifier::UpdaterECDSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType) : _hashType(hashType), _valid(false) { + _ctx = new mbedtls_pk_context; + mbedtls_pk_init((mbedtls_pk_context *)_ctx); + + // Try to parse the public key + int ret = mbedtls_pk_parse_public_key((mbedtls_pk_context *)_ctx, pubkey, pubkeyLen); + if (ret != 0) { + log_e("Failed to parse ECDSA public key: -0x%04X", -ret); + return; + } + + // Verify it's an ECDSA key + mbedtls_pk_type_t type = mbedtls_pk_get_type((mbedtls_pk_context *)_ctx); + if (type != MBEDTLS_PK_ECKEY && type != MBEDTLS_PK_ECDSA) { + log_e("Public key is not ECDSA"); + return; + } + + _valid = true; + log_i("ECDSA public key loaded successfully"); +} + +UpdaterECDSAVerifier::~UpdaterECDSAVerifier() { + if (_ctx) { + mbedtls_pk_free((mbedtls_pk_context *)_ctx); + delete (mbedtls_pk_context *)_ctx; + _ctx = nullptr; + } +} + +bool UpdaterECDSAVerifier::verify(SHA2Builder *hash, const void *signature, size_t signatureLen) { + if (!_valid || !hash) { + log_e("Invalid ECDSA verifier or hash"); + return false; + } + + mbedtls_md_type_t md_type; + switch (_hashType) { + case HASH_SHA256: md_type = MBEDTLS_MD_SHA256; break; + case HASH_SHA384: md_type = MBEDTLS_MD_SHA384; break; + case HASH_SHA512: md_type = MBEDTLS_MD_SHA512; break; + default: log_e("Invalid hash type"); return false; + } + + // Get hash bytes from the builder + uint8_t hashBytes[64]; // Max hash size (SHA-512) + hash->getBytes(hashBytes); + + int ret = mbedtls_pk_verify((mbedtls_pk_context *)_ctx, md_type, hashBytes, hash->getHashSize(), (const unsigned char *)signature, signatureLen); + + if (ret == 0) { + log_i("ECDSA signature verified successfully"); + return true; + } else { + log_e("ECDSA signature verification failed: -0x%04X", -ret); + return false; + } +} + +#endif // UPDATE_SIGN diff --git a/libraries/Update/src/Updater_Signing.h b/libraries/Update/src/Updater_Signing.h new file mode 100644 index 0000000..1134a17 --- /dev/null +++ b/libraries/Update/src/Updater_Signing.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#ifdef UPDATE_SIGN + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Signature schemes +#define SIGN_NONE 0 +#define SIGN_RSA 1 +#define SIGN_ECDSA 2 + +// Hash algorithms for signature verification +#define HASH_SHA256 0 +#define HASH_SHA384 1 +#define HASH_SHA512 2 + +// Signature sizes (in bytes) +#define RSA_2048_SIGNATURE_SIZE 256 +#define RSA_3072_SIGNATURE_SIZE 384 +#define RSA_4096_SIGNATURE_SIZE 512 +#define ECDSA_P256_SIGNATURE_SIZE 64 +#define ECDSA_P384_SIGNATURE_SIZE 96 + +// Hash sizes (in bytes) +#define SHA256_SIZE 32 +#define SHA384_SIZE 48 +#define SHA512_SIZE 64 + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus + +class UpdaterVerifyClass { +public: + virtual bool verify(SHA2Builder *hash, const void *signature, size_t signatureLen) = 0; + virtual int getHashType() const = 0; + virtual ~UpdaterVerifyClass() {} +}; + +// Signature verifiers using mbedtls (required for public key cryptography) +class UpdaterRSAVerifier : public UpdaterVerifyClass { +public: + UpdaterRSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType = HASH_SHA256); + ~UpdaterRSAVerifier(); + bool verify(SHA2Builder *hash, const void *signature, size_t signatureLen) override; + int getHashType() const override { + return _hashType; + } + +private: + void *_ctx; + int _hashType; + bool _valid; +}; + +class UpdaterECDSAVerifier : public UpdaterVerifyClass { +public: + UpdaterECDSAVerifier(const uint8_t *pubkey, size_t pubkeyLen, int hashType = HASH_SHA256); + ~UpdaterECDSAVerifier(); + bool verify(SHA2Builder *hash, const void *signature, size_t signatureLen) override; + int getHashType() const override { + return _hashType; + } + +private: + void *_ctx; + int _hashType; + bool _valid; +}; + +#endif // __cplusplus + +#endif // UPDATE_SIGN diff --git a/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino b/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino new file mode 100644 index 0000000..eb805d2 --- /dev/null +++ b/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino @@ -0,0 +1,149 @@ +/* + Copyright (c) 2015, Majenko Technologies + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + * * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + + * * Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + + * * Neither the name of Majenko Technologies nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include + +const char *ssid = "YourSSIDHere"; +const char *password = "YourPSKHere"; + +WebServer server(80); + +const int led = 13; + +void handleRoot() { + digitalWrite(led, 1); + char temp[400]; + int sec = millis() / 1000; + int hr = sec / 3600; + int min = (sec / 60) % 60; + sec = sec % 60; + + snprintf( + temp, 400, + + "\ + \ + \ + ESP32 Demo\ + \ + \ + \ +

Hello from ESP32!

\ +

Uptime: %02d:%02d:%02d

\ + \ + \ +", + + hr, min, sec + ); + server.send(200, "text/html", temp); + digitalWrite(led, 0); +} + +void handleNotFound() { + digitalWrite(led, 1); + String message = "File Not Found\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + + for (uint8_t i = 0; i < server.args(); i++) { + message += " " + server.argName(i) + ": " + server.arg(i) + "\n"; + } + + server.send(404, "text/plain", message); + digitalWrite(led, 0); +} + +void setup(void) { + pinMode(led, OUTPUT); + digitalWrite(led, 0); + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + if (MDNS.begin("esp32")) { + Serial.println("MDNS responder started"); + } + + server.on("/", handleRoot); + server.on("/test.svg", drawGraph); + server.on("/inline", []() { + server.send(200, "text/plain", "this works as well"); + }); + server.onNotFound(handleNotFound); + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} + +void drawGraph() { + String out = ""; + char temp[100]; + out += "\n"; + out += "\n"; + out += "\n"; + int y = rand() % 130; + for (int x = 10; x < 390; x += 10) { + int y2 = rand() % 130; + sprintf(temp, "\n", x, 140 - y, x + 10, 140 - y2); + out += temp; + y = y2; + } + out += "\n\n"; + + server.send(200, "image/svg+xml", out); +} diff --git a/libraries/WebServer/examples/AdvancedWebServer/ci.yml b/libraries/WebServer/examples/AdvancedWebServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/AdvancedWebServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/ChunkWriting/ChunkWriting.ino b/libraries/WebServer/examples/ChunkWriting/ChunkWriting.ino new file mode 100644 index 0000000..50c2932 --- /dev/null +++ b/libraries/WebServer/examples/ChunkWriting/ChunkWriting.ino @@ -0,0 +1,75 @@ +/* + * This example demonstrates how to send an HTTP response using chunks + * It will create an HTTP Server (port 80) associated with an a MDNS service + * Access the HTTP server using a Web Browser: + * URL can be composed using the MDNS name "esp32_chunk_resp.local" + * http://esp32_chunk_resp.local/ + * or the IP Address that will be printed out, such as for instance 192.168.1.10 + * http://192.168.1.10/ + * + * ESP32 Server response can also be viewed using the curl command: + * curl -i esp32_chunk_resp.local:80 + * curl -i --raw esp32_chunk_resp.local:80 + */ + +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +void handleChunks() { + uint8_t countDown = 10; + server.chunkResponseBegin(); + char countContent[8]; + while (countDown) { + sprintf(countContent, "%d...\r\n", countDown--); + server.chunkWrite(countContent, strlen(countContent)); + // count down shall show up in the browser only after about 5 seconds when finishing the whole transmission + // using "curl -i esp32_chunk_resp.local:80", it will show the count down as it sends each chunk + delay(500); + } + server.chunkWrite("DONE!", 5); + server.chunkResponseEnd(); +} + +void setup(void) { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + // Use the URL: http://esp32_chunk_resp.local/ + if (MDNS.begin("esp32_chunk_resp")) { + Serial.println("MDNS responder started"); + } + + server.on("/", handleChunks); + + server.onNotFound([]() { + server.send(404, "text/plain", "Page not found"); + }); + + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/ChunkWriting/ci.yml b/libraries/WebServer/examples/ChunkWriting/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/ChunkWriting/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/FSBrowser/FSBrowser.ino b/libraries/WebServer/examples/FSBrowser/FSBrowser.ino new file mode 100644 index 0000000..4c6f895 --- /dev/null +++ b/libraries/WebServer/examples/FSBrowser/FSBrowser.ino @@ -0,0 +1,308 @@ +/* + FSWebServer - Example WebServer with FS backend for esp8266/esp32 + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the WebServer library for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + upload the contents of the data folder with MkSPIFFS Tool ("ESP32 Sketch Data Upload" in Tools menu in Arduino IDE) + or you can upload the contents of a folder if you CD in that folder and run the following command: + for file in `ls -A1`; do curl -F "file=@$PWD/$file" esp32fs.local/edit; done + + access the sample web page at http://esp32fs.local + edit the page by going to http://esp32fs.local/edit +*/ +#include +#include +#include +#include + +#define FILESYSTEM SPIFFS +// You only need to format the filesystem once +#define FORMAT_FILESYSTEM false +#define DBG_OUTPUT_PORT Serial + +#if FILESYSTEM == FFat +#include +#endif +#if FILESYSTEM == SPIFFS +#include +#endif + +const char *ssid = "wifi-ssid"; +const char *password = "wifi-password"; +const char *host = "esp32fs"; +WebServer server(80); +//holds the current upload +File fsUploadFile; + +//format bytes +String formatBytes(size_t bytes) { + if (bytes < 1024) { + return String(bytes) + "B"; + } else if (bytes < (1024 * 1024)) { + return String(bytes / 1024.0) + "KB"; + } else if (bytes < (1024 * 1024 * 1024)) { + return String(bytes / 1024.0 / 1024.0) + "MB"; + } else { + return String(bytes / 1024.0 / 1024.0 / 1024.0) + "GB"; + } +} + +String getContentType(String filename) { + if (server.hasArg("download")) { + return "application/octet-stream"; + } else if (filename.endsWith(".htm")) { + return "text/html"; + } else if (filename.endsWith(".html")) { + return "text/html"; + } else if (filename.endsWith(".css")) { + return "text/css"; + } else if (filename.endsWith(".js")) { + return "application/javascript"; + } else if (filename.endsWith(".png")) { + return "image/png"; + } else if (filename.endsWith(".gif")) { + return "image/gif"; + } else if (filename.endsWith(".jpg")) { + return "image/jpeg"; + } else if (filename.endsWith(".ico")) { + return "image/x-icon"; + } else if (filename.endsWith(".xml")) { + return "text/xml"; + } else if (filename.endsWith(".pdf")) { + return "application/x-pdf"; + } else if (filename.endsWith(".zip")) { + return "application/x-zip"; + } else if (filename.endsWith(".gz")) { + return "application/x-gzip"; + } + return "text/plain"; +} + +bool exists(String path) { + bool yes = false; + File file = FILESYSTEM.open(path, "r"); + if (!file.isDirectory()) { + yes = true; + } + file.close(); + return yes; +} + +bool handleFileRead(String path) { + DBG_OUTPUT_PORT.println("handleFileRead: " + path); + if (path.endsWith("/")) { + path += "index.htm"; + } + String contentType = getContentType(path); + String pathWithGz = path + ".gz"; + if (exists(pathWithGz) || exists(path)) { + if (exists(pathWithGz)) { + path += ".gz"; + } + File file = FILESYSTEM.open(path, "r"); + server.streamFile(file, contentType); + file.close(); + return true; + } + return false; +} + +void handleFileUpload() { + if (server.uri() != "/edit") { + return; + } + HTTPUpload &upload = server.upload(); + if (upload.status == UPLOAD_FILE_START) { + String filename = upload.filename; + if (!filename.startsWith("/")) { + filename = "/" + filename; + } + DBG_OUTPUT_PORT.print("handleFileUpload Name: "); + DBG_OUTPUT_PORT.println(filename); + fsUploadFile = FILESYSTEM.open(filename, "w"); + filename = String(); + } else if (upload.status == UPLOAD_FILE_WRITE) { + //DBG_OUTPUT_PORT.print("handleFileUpload Data: "); DBG_OUTPUT_PORT.println(upload.currentSize); + if (fsUploadFile) { + fsUploadFile.write(upload.buf, upload.currentSize); + } + } else if (upload.status == UPLOAD_FILE_END) { + if (fsUploadFile) { + fsUploadFile.close(); + } + DBG_OUTPUT_PORT.print("handleFileUpload Size: "); + DBG_OUTPUT_PORT.println(upload.totalSize); + } +} + +void handleFileDelete() { + if (server.args() == 0) { + return server.send(500, "text/plain", "BAD ARGS"); + } + String path = server.arg(0); + DBG_OUTPUT_PORT.println("handleFileDelete: " + path); + if (path == "/") { + return server.send(500, "text/plain", "BAD PATH"); + } + if (!exists(path)) { + return server.send(404, "text/plain", "FileNotFound"); + } + FILESYSTEM.remove(path); + server.send(200, "text/plain", ""); + path = String(); +} + +void handleFileCreate() { + if (server.args() == 0) { + return server.send(500, "text/plain", "BAD ARGS"); + } + String path = server.arg(0); + DBG_OUTPUT_PORT.println("handleFileCreate: " + path); + if (path == "/") { + return server.send(500, "text/plain", "BAD PATH"); + } + if (exists(path)) { + return server.send(500, "text/plain", "FILE EXISTS"); + } + File file = FILESYSTEM.open(path, "w"); + if (file) { + file.close(); + } else { + return server.send(500, "text/plain", "CREATE FAILED"); + } + server.send(200, "text/plain", ""); + path = String(); +} + +void handleFileList() { + if (!server.hasArg("dir")) { + server.send(500, "text/plain", "BAD ARGS"); + return; + } + + String path = server.arg("dir"); + DBG_OUTPUT_PORT.println("handleFileList: " + path); + + File root = FILESYSTEM.open(path); + path = String(); + + String output = "["; + if (root.isDirectory()) { + File file = root.openNextFile(); + while (file) { + if (output != "[") { + output += ','; + } + output += "{\"type\":\""; + output += (file.isDirectory()) ? "dir" : "file"; + output += "\",\"name\":\""; + output += String(file.path()).substring(1); + output += "\"}"; + file = root.openNextFile(); + } + } + output += "]"; + server.send(200, "text/json", output); +} + +void setup(void) { + DBG_OUTPUT_PORT.begin(115200); + DBG_OUTPUT_PORT.print("\n"); + DBG_OUTPUT_PORT.setDebugOutput(true); + if (FORMAT_FILESYSTEM) { + FILESYSTEM.format(); + } + FILESYSTEM.begin(); + { + File root = FILESYSTEM.open("/"); + File file = root.openNextFile(); + while (file) { + String fileName = file.name(); + size_t fileSize = file.size(); + DBG_OUTPUT_PORT.printf("FS File: %s, size: %s\n", fileName.c_str(), formatBytes(fileSize).c_str()); + file = root.openNextFile(); + } + DBG_OUTPUT_PORT.printf("\n"); + } + + //WIFI INIT + DBG_OUTPUT_PORT.printf("Connecting to %s\n", ssid); + if (String(WiFi.SSID()) != String(ssid)) { + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + } + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + DBG_OUTPUT_PORT.print("."); + } + DBG_OUTPUT_PORT.println(""); + DBG_OUTPUT_PORT.print("Connected! IP address: "); + DBG_OUTPUT_PORT.println(WiFi.localIP()); + + MDNS.begin(host); + DBG_OUTPUT_PORT.print("Open http://"); + DBG_OUTPUT_PORT.print(host); + DBG_OUTPUT_PORT.println(".local/edit to see the file browser"); + + //SERVER INIT + //list directory + server.on("/list", HTTP_GET, handleFileList); + //load editor + server.on("/edit", HTTP_GET, []() { + if (!handleFileRead("/edit.htm")) { + server.send(404, "text/plain", "FileNotFound"); + } + }); + //create file + server.on("/edit", HTTP_PUT, handleFileCreate); + //delete file + server.on("/edit", HTTP_DELETE, handleFileDelete); + //first callback is called after the request has ended with all parsed arguments + //second callback handles file uploads at that location + server.on( + "/edit", HTTP_POST, + []() { + server.send(200, "text/plain", ""); + }, + handleFileUpload + ); + + //called when the url is not defined here + //use it to load content from FILESYSTEM + server.onNotFound([]() { + if (!handleFileRead(server.uri())) { + server.send(404, "text/plain", "FileNotFound"); + } + }); + + //get heap status, analog input value and all GPIO statuses in one json call + server.on("/all", HTTP_GET, []() { + String json = "{"; + json += "\"heap\":" + String(ESP.getFreeHeap()); + json += ", \"analog\":" + String(analogRead(A0)); + json += ", \"gpio\":" + String((uint32_t)(0)); + json += "}"; + server.send(200, "text/json", json); + json = String(); + }); + server.begin(); + DBG_OUTPUT_PORT.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/FSBrowser/ci.yml b/libraries/WebServer/examples/FSBrowser/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/FSBrowser/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/FSBrowser/data/edit.htm.gz b/libraries/WebServer/examples/FSBrowser/data/edit.htm.gz new file mode 100644 index 0000000..69ce414 Binary files /dev/null and b/libraries/WebServer/examples/FSBrowser/data/edit.htm.gz differ diff --git a/libraries/WebServer/examples/FSBrowser/data/favicon.ico b/libraries/WebServer/examples/FSBrowser/data/favicon.ico new file mode 100644 index 0000000..71b25fe Binary files /dev/null and b/libraries/WebServer/examples/FSBrowser/data/favicon.ico differ diff --git a/libraries/WebServer/examples/FSBrowser/data/graphs.js.gz b/libraries/WebServer/examples/FSBrowser/data/graphs.js.gz new file mode 100644 index 0000000..7243544 Binary files /dev/null and b/libraries/WebServer/examples/FSBrowser/data/graphs.js.gz differ diff --git a/libraries/WebServer/examples/FSBrowser/data/index.htm b/libraries/WebServer/examples/FSBrowser/data/index.htm new file mode 100644 index 0000000..36858db --- /dev/null +++ b/libraries/WebServer/examples/FSBrowser/data/index.htm @@ -0,0 +1,97 @@ + + + + + + ESP Monitor + + + + +
+ + + + +
+
+
+
+ + diff --git a/libraries/WebServer/examples/Filters/Filters.ino b/libraries/WebServer/examples/Filters/Filters.ino new file mode 100644 index 0000000..8974e55 --- /dev/null +++ b/libraries/WebServer/examples/Filters/Filters.ino @@ -0,0 +1,110 @@ +#include +#include +#include +#include + +// Your STA WiFi Credentials +// ( This is the AP your ESP will connect to ) +const char *ssid = "........"; +const char *password = "........"; + +// Your AP WiFi Credentials +// ( This is the AP your ESP will broadcast ) +const char *ap_ssid = "ESP32_Demo"; +const char *ap_password = ""; + +WebServer server(80); + +const int led = 13; + +// ON_STA_FILTER - Only accept requests coming from STA interface +bool ON_STA_FILTER(WebServer &server) { + return WiFi.STA.hasIP() && WiFi.STA.localIP() == server.client().localIP(); +} + +// ON_AP_FILTER - Only accept requests coming from AP interface +bool ON_AP_FILTER(WebServer &server) { + return WiFi.AP.hasIP() && WiFi.AP.localIP() == server.client().localIP(); +} + +void handleNotFound() { + digitalWrite(led, 1); + String message = "File Not Found\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + for (uint8_t i = 0; i < server.args(); i++) { + message += " " + server.argName(i) + ": " + server.arg(i) + "\n"; + } + server.send(404, "text/plain", message); + digitalWrite(led, 0); +} + +void setup(void) { + pinMode(led, OUTPUT); + digitalWrite(led, 0); + Serial.begin(115200); + WiFi.mode(WIFI_AP_STA); + // Connect to STA + WiFi.begin(ssid, password); + // Start AP + WiFi.softAP(ap_ssid, ap_password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + if (MDNS.begin("esp32")) { + Serial.println("MDNS responder started"); + } + + // This route will be accessible by STA clients only + server + .on( + "/", + [&]() { + digitalWrite(led, 1); + server.send(200, "text/plain", "Hi!, This route is accessible for STA clients only"); + digitalWrite(led, 0); + } + ) + .setFilter(ON_STA_FILTER); + + // This route will be accessible by AP clients only + server + .on( + "/", + [&]() { + digitalWrite(led, 1); + server.send(200, "text/plain", "Hi!, This route is accessible for AP clients only"); + digitalWrite(led, 0); + } + ) + .setFilter(ON_AP_FILTER); + + server.on("/inline", []() { + server.send(200, "text/plain", "this works as well"); + }); + + server.onNotFound(handleNotFound); + + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/Filters/ci.yml b/libraries/WebServer/examples/Filters/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/Filters/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HelloServer/HelloServer.ino b/libraries/WebServer/examples/HelloServer/HelloServer.ino new file mode 100644 index 0000000..3cf8a73 --- /dev/null +++ b/libraries/WebServer/examples/HelloServer/HelloServer.ino @@ -0,0 +1,74 @@ +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +const int led = 13; + +void handleRoot() { + digitalWrite(led, 1); + server.send(200, "text/plain", "hello from esp32!"); + digitalWrite(led, 0); +} + +void handleNotFound() { + digitalWrite(led, 1); + String message = "File Not Found\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + for (uint8_t i = 0; i < server.args(); i++) { + message += " " + server.argName(i) + ": " + server.arg(i) + "\n"; + } + server.send(404, "text/plain", message); + digitalWrite(led, 0); +} + +void setup(void) { + pinMode(led, OUTPUT); + digitalWrite(led, 0); + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + if (MDNS.begin("esp32")) { + Serial.println("MDNS responder started"); + } + + server.on("/", handleRoot); + + server.on("/inline", []() { + server.send(200, "text/plain", "this works as well"); + }); + + server.onNotFound(handleNotFound); + + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HelloServer/ci.yml b/libraries/WebServer/examples/HelloServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HelloServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino b/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino new file mode 100644 index 0000000..7d984d9 --- /dev/null +++ b/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino @@ -0,0 +1,60 @@ +/* + HTTP Advanced Authentication example + Created Mar 16, 2017 by Ahmed El-Sharnoby. + This example code is in the public domain. +*/ + +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +const char *www_username = "admin"; +const char *www_password = "esp32"; +// allows you to set the realm of authentication Default:"Login Required" +const char *www_realm = "Custom Auth Realm"; +// the Content of the HTML response in case of Unautherized Access Default:empty +String authFailResponse = "Authentication Failed"; + +void setup() { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + server.on("/", []() { + if (!server.authenticate(www_username, www_password)) + //Basic Auth Method with Custom realm and Failure Response + //return server.requestAuthentication(BASIC_AUTH, www_realm, authFailResponse); + //Digest Auth Method with realm="Login Required" and empty Failure Response + //return server.requestAuthentication(DIGEST_AUTH); + //Digest Auth Method with Custom realm and empty Failure Response + //return server.requestAuthentication(DIGEST_AUTH, www_realm); + //Digest Auth Method with Custom realm and Failure Response + { + return server.requestAuthentication(DIGEST_AUTH, www_realm, authFailResponse); + } + server.send(200, "text/plain", "Login OK"); + }); + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpAdvancedAuth/ci.yml b/libraries/WebServer/examples/HttpAdvancedAuth/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpAdvancedAuth/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino b/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino new file mode 100644 index 0000000..0d3bca1 --- /dev/null +++ b/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino @@ -0,0 +1,60 @@ +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +typedef struct credentials_t { + String username; + String password; +} credentials_t; + +credentials_t passwdfile[] = { + {"admin", "esp32"}, {"fred", "41234123"}, {"charlie", "sdfsd"}, {"alice", "vambdnkuhj"}, {"bob", "svcdbjhws12"}, +}; +const size_t N_CREDENTIALS = sizeof(passwdfile) / sizeof(credentials_t); + +String *credentialsHandler(HTTPAuthMethod mode, String username, String params[]) { + for (int i = 0; i < N_CREDENTIALS; i++) { + if (username == passwdfile[i].username) { + return new String(passwdfile[i].password); + } + } + return NULL; +} + +void setup() { + Serial.begin(115200); + + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + server.on("/", []() { + if (!server.authenticate(&credentialsHandler)) { + server.requestAuthentication(); + return; + } + server.send(200, "text/plain", "Login OK"); + }); + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpAuthCallback/ci.yml b/libraries/WebServer/examples/HttpAuthCallback/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpAuthCallback/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino b/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino new file mode 100644 index 0000000..bcf78a9 --- /dev/null +++ b/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino @@ -0,0 +1,59 @@ +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +typedef struct credentials_t { + const char *username; + const char *password; +} credentials_t; + +credentials_t passwdfile[] = {{"admin", "esp32"}, {"fred", "41234123"}, {"charlie", "sdfsd"}, {"alice", "vambdnkuhj"}, {"bob", "svcdbjhws12"}, {NULL, NULL}}; + +void setup() { + Serial.begin(115200); + + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + server.on("/", []() { + if (!server.authenticate([](HTTPAuthMethod mode, String username, String params[]) -> String * { + // Scan the password list for the username and return the password if + // we find the username. + // + for (credentials_t *entry = passwdfile; entry->username; entry++) { + if (username == entry->username) { + return new String(entry->password); + }; + }; + // we've not found the user in the list. + return NULL; + })) { + server.requestAuthentication(); + return; + } + server.send(200, "text/plain", "Login OK"); + }); + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpAuthCallbackInline/ci.yml b/libraries/WebServer/examples/HttpAuthCallbackInline/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpAuthCallbackInline/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino b/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino new file mode 100644 index 0000000..f4d71f1 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino @@ -0,0 +1,42 @@ +#include +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +const char *www_username = "admin"; +const char *www_password = "esp32"; + +void setup() { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + server.on("/", []() { + if (!server.authenticate(www_username, www_password)) { + return server.requestAuthentication(); + } + server.send(200, "text/plain", "Login OK"); + }); + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpBasicAuth/ci.yml b/libraries/WebServer/examples/HttpBasicAuth/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuth/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino b/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino new file mode 100644 index 0000000..643a053 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino @@ -0,0 +1,72 @@ +#include +#include +#include +#include + +// Rather than specify the password as plaintext; we +// provide it as an (unsalted!) SHA1 hash. This is not +// much more secure (SHA1 is past its retirement age, +// and long obsolete/insecure) - but it helps a little. + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +// Passwords as plaintext - human readable and easily visible in +// the sourcecode and in the firmware/binary. +const char *www_username = "admin"; +const char *www_password = "esp32"; + +// The sha1 of 'esp32' (without the trailing \0) expressed as 20 +// bytes of hex. Created by for example 'echo -n esp32 | openssl sha1' +// or http://www.sha1-online.com. +const char *www_username_hex = "hexadmin"; +const char *www_password_hex = "8cb124f8c277c16ec0b2ee00569fd151a08e342b"; + +// The same; but now expressed as a base64 string (e.g. as commonly used +// by webservers). Created by ` echo -n esp32 | openssl sha1 -binary | openssl base64` +const char *www_username_base64 = "base64admin"; +const char *www_password_base64 = "jLEk+MJ3wW7Asu4AVp/RUaCONCs="; + +void setup() { + Serial.begin(115200); + + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + server.on("/", []() { + if (server.authenticate(www_username, www_password)) { + server.send(200, "text/plain", "Login against cleartext password OK"); + return; + } + if (server.authenticateBasicSHA1(www_username_hex, www_password_hex)) { + server.send(200, "text/plain", "Login against HEX of the SHA1 of the password OK"); + return; + } + if (server.authenticateBasicSHA1(www_username_base64, www_password_base64)) { + server.send(200, "text/plain", "Login against Base64 of the SHA1 of the password OK"); + return; + } + Serial.println("No/failed authentication"); + return server.requestAuthentication(); + }); + + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.yml b/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino new file mode 100644 index 0000000..89933a4 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino @@ -0,0 +1,118 @@ +#include +#include +#include +#include +#include + +// We have two options - we either come in with a bearer +// token - i.e. a special header or API token; or we +// get a normal HTTP style basic auth prompt. +// +// To do a bearer fetch - use something like Swagger or with curl: +// +// curl https://myesp.com/ -H "Authorization: Bearer SecritToken" +// +// We avoid hardcoding this "SecritToken" into the code by +// using a SHA1 instead (which is not particularly secure). + +// Create the secret token SHA1 with: +// echo -n SecritToken | openssl sha1 + +String secret_token_hex = "d2cce6b472959484a21c3194080c609b8a2c910b"; + +// Wifi credentials + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +// Rather than specify the admin password as plaintext; we +// provide it as an (unsalted!) SHA1 hash. This is not +// much more secure (SHA1 is past its retirement age, +// and long obsolete/insecure) - but it helps a little. + +// The sha1 of 'esp32' (without the trailing \0) expressed as 20 +// bytes of hex. Created by for example 'echo -n esp32 | openssl sha1' +// or http://www.sha1-online.com. +const char *www_username_hex = "admin"; +const char *www_password_hex = "8cb124f8c277c16ec0b2ee00569fd151a08e342b"; + +static unsigned char _bearer[20]; + +String *check_bearer_or_auth(HTTPAuthMethod mode, String authReq, String params[]) { + // we expect authReq to be "bearer some-secret" + String lcAuthReq = authReq; + lcAuthReq.toLowerCase(); + if (mode == OTHER_AUTH && (lcAuthReq.startsWith("bearer "))) { + String secret = authReq.substring(7); + secret.trim(); + + uint8_t sha1[20]; + SHA1Builder sha_builder; + + sha_builder.begin(); + sha_builder.add((uint8_t *)secret.c_str(), secret.length()); + sha_builder.calculate(); + sha_builder.getBytes(sha1); + + if (memcmp(_bearer, sha1, sizeof(_bearer)) == 0) { + Serial.println("Bearer token matches"); + return new String("anything non null"); + } else { + Serial.println("Bearer token does not match"); + } + } else if (mode == BASIC_AUTH) { + bool ret = server.authenticateBasicSHA1(www_username_hex, www_password_hex); + if (ret) { + Serial.println("Basic auth succeeded"); + return new String(params[0]); + } else { + Serial.println("Basic auth failed"); + } + } + + // No auth found + return NULL; +}; + +void setup() { + Serial.begin(115200); + + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() != WL_CONNECTED) { + Serial.println("WiFi Connect Failed! Rebooting..."); + delay(1000); + ESP.restart(); + } + ArduinoOTA.begin(); + + // Convert token to a convenient binary representation. + size_t len = HEXBuilder::hex2bytes(_bearer, sizeof(_bearer), secret_token_hex); + if (len != 20) { + Serial.println("Bearer token does not look like a valid SHA1 hex string ?!"); + } + + server.on("/", []() { + if (!server.authenticate(&check_bearer_or_auth)) { + Serial.println("No/failed authentication"); + return server.requestAuthentication(); + } + Serial.println("Authentication succeeded"); + server.send(200, "text/plain", "Login OK"); + return; + }); + + server.begin(); + + Serial.print("Open http://"); + Serial.print(WiFi.localIP()); + Serial.println("/ in your browser to see it working"); +} + +void loop() { + ArduinoOTA.handle(); + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.yml b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/Middleware/Middleware.ino b/libraries/WebServer/examples/Middleware/Middleware.ino new file mode 100644 index 0000000..9d95734 --- /dev/null +++ b/libraries/WebServer/examples/Middleware/Middleware.ino @@ -0,0 +1,186 @@ +/** + * Basic example of using Middlewares with WebServer + * + * Middleware are common request/response processing functions that can be applied globally to all incoming requests or to specific handlers. + * They allow for a common processing thus saving memory and space to avoid duplicating code or states on multiple handlers. + * + * Once the example is flashed (with the correct WiFi credentials), you can test the following scenarios with the listed curl commands: + * - CORS Middleware: answers to OPTIONS requests with the specified CORS headers and also add CORS headers to the response when the request has the Origin header + * - Logging Middleware: logs the request and response to an output in a curl-like format + * - Authentication Middleware: test the authentication with Digest Auth + * + * You can also add your own Middleware by extending the Middleware class and implementing the run method. + * When implementing a Middleware, you can decide when to call the next Middleware in the chain by calling next(). + * + * Middleware are execute in order of addition, the ones attached to the server will be executed first. + */ +#include +#include +#include + +// Your AP WiFi Credentials +// ( This is the AP your ESP will broadcast ) +const char *ap_ssid = "ESP32_Demo"; +const char *ap_password = ""; + +WebServer server(80); + +LoggingMiddleware logger; +CorsMiddleware cors; +AuthenticationMiddleware auth; + +void setup(void) { + Serial.begin(115200); + WiFi.softAP(ap_ssid, ap_password); + + Serial.print("IP address: "); + Serial.println(WiFi.AP.localIP()); + + // curl-like output example: + // + // > curl -v -X OPTIONS -H "origin: http://192.168.4.1" http://192.168.4.1/ + // + // Connection from 192.168.4.2:51683 + // > OPTIONS / HTTP/1.1 + // > Host: 192.168.4.1 + // > User-Agent: curl/8.10.0 + // > Accept: */* + // > origin: http://192.168.4.1 + // > + // * Processed in 5 ms + // < HTTP/1.HTTP/1.1 200 OK + // < Content-Type: text/html + // < Access-Control-Allow-Origin: http://192.168.4.1 + // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE + // < Access-Control-Allow-Headers: X-Custom-Header + // < Access-Control-Allow-Credentials: false + // < Access-Control-Max-Age: 600 + // < Content-Length: 0 + // < Connection: close + // < + logger.setOutput(Serial); + + cors.setOrigin("http://192.168.4.1"); + cors.setMethods("POST,GET,OPTIONS,DELETE"); + cors.setHeaders("X-Custom-Header"); + cors.setAllowCredentials(false); + cors.setMaxAge(600); + + auth.setUsername("admin"); + auth.setPassword("admin"); + auth.setRealm("My Super App"); + auth.setAuthMethod(DIGEST_AUTH); + auth.setAuthFailureMessage("Authentication Failed"); + + server.addMiddleware(&logger); + server.addMiddleware(&cors); + + // Not authenticated + // + // Test CORS preflight request with: + // > curl -v -X OPTIONS -H "origin: http://192.168.4.1" http://192.168.4.1/ + // + // Test cross-domain request with: + // > curl -v -X GET -H "origin: http://192.168.4.1" http://192.168.4.1/ + // + server.on("/", []() { + server.send(200, "text/plain", "Home"); + }); + + // Authenticated + // + // > curl -v -X GET -H "origin: http://192.168.4.1" http://192.168.4.1/protected + // + // Outputs: + // + // * Connection from 192.168.4.2:51750 + // > GET /protected HTTP/1.1 + // > Host: 192.168.4.1 + // > User-Agent: curl/8.10.0 + // > Accept: */* + // > origin: http://192.168.4.1 + // > + // * Processed in 7 ms + // < HTTP/1.HTTP/1.1 401 Unauthorized + // < Content-Type: text/html + // < Access-Control-Allow-Origin: http://192.168.4.1 + // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE + // < Access-Control-Allow-Headers: X-Custom-Header + // < Access-Control-Allow-Credentials: false + // < Access-Control-Max-Age: 600 + // < WWW-Authenticate: Digest realm="My Super App", qop="auth", nonce="ac388a64184e3e102aae6fff1c9e8d76", opaque="e7d158f2b54d25328142d118ff0f932d" + // < Content-Length: 21 + // < Connection: close + // < + // + // > curl -v -X GET -H "origin: http://192.168.4.1" --digest -u admin:admin http://192.168.4.1/protected + // + // Outputs: + // + // * Connection from 192.168.4.2:53662 + // > GET /protected HTTP/1.1 + // > Authorization: Digest username="admin", realm="My Super App", nonce="db9e6824eb2a13bc7b2bf8f3c43db896", uri="/protected", cnonce="NTliZDZiNTcwODM2MzAyY2JjMDBmZGJmNzFiY2ZmNzk=", nc=00000001, qop=auth, response="6ebd145ba0d3496a4a73f5ae79ff5264", opaque="23d739c22810282ff820538cba98bda4" + // > Host: 192.168.4.1 + // > User-Agent: curl/8.10.0 + // > Accept: */* + // > origin: http://192.168.4.1 + // > + // Request handling... + // * Processed in 7 ms + // < HTTP/1.HTTP/1.1 200 OK + // < Content-Type: text/plain + // < Access-Control-Allow-Origin: http://192.168.4.1 + // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE + // < Access-Control-Allow-Headers: X-Custom-Header + // < Access-Control-Allow-Credentials: false + // < Access-Control-Max-Age: 600 + // < Content-Length: 9 + // < Connection: close + // < + server + .on( + "/protected", + []() { + Serial.println("Request handling..."); + server.send(200, "text/plain", "Protected"); + } + ) + .addMiddleware(&auth); + + // Not found is also handled by global middleware + // + // curl -v -X GET -H "origin: http://192.168.4.1" http://192.168.4.1/inexsting + // + // Outputs: + // + // * Connection from 192.168.4.2:53683 + // > GET /inexsting HTTP/1.1 + // > Host: 192.168.4.1 + // > User-Agent: curl/8.10.0 + // > Accept: */* + // > origin: http://192.168.4.1 + // > + // * Processed in 16 ms + // < HTTP/1.HTTP/1.1 404 Not Found + // < Content-Type: text/plain + // < Access-Control-Allow-Origin: http://192.168.4.1 + // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE + // < Access-Control-Allow-Headers: X-Custom-Header + // < Access-Control-Allow-Credentials: false + // < Access-Control-Max-Age: 600 + // < Content-Length: 14 + // < Connection: close + // < + server.onNotFound([]() { + server.send(404, "text/plain", "Page not found"); + }); + + server.collectAllHeaders(); + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/Middleware/ci.yml b/libraries/WebServer/examples/Middleware/ci.yml new file mode 100644 index 0000000..86e194b --- /dev/null +++ b/libraries/WebServer/examples/Middleware/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_WIFI_SUPPORTED=y diff --git a/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino b/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino new file mode 100644 index 0000000..300a651 --- /dev/null +++ b/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino @@ -0,0 +1,141 @@ +#include +#include +#include +#include + +const char *ssid = "WiFi_SSID"; +const char *password = "WiFi_Password"; +const char *apssid = "ESP32"; + +WebServer *server0, *server1, *server2; + +#ifdef LED_BUILTIN +const int led = LED_BUILTIN; +#else +const int led = 13; +#endif + +void handleRoot(WebServer *server, const char *content) { + digitalWrite(led, 1); + server->send(200, "text/plain", content); + digitalWrite(led, 0); +} + +void handleRoot0() { + handleRoot(server0, "Hello from server0 who listens on both WLAN and own Soft AP"); +} + +void handleRoot1() { + handleRoot(server1, "Hello from server1 who listens only on WLAN"); +} + +void handleRoot2() { + handleRoot(server2, "Hello from server2 who listens only on own Soft AP"); +} + +void handleNotFound(WebServer *server) { + digitalWrite(led, 1); + String message = "File Not Found\n\n"; + message += "URI: "; + message += server->uri(); + message += "\nMethod: "; + message += (server->method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server->args(); + message += "\n"; + for (uint8_t i = 0; i < server->args(); i++) { + message += " " + server->argName(i) + ": " + server->arg(i) + "\n"; + } + server->send(404, "text/plain", message); + digitalWrite(led, 0); +} + +void handleNotFound0() { + handleNotFound(server0); +} + +void handleNotFound1() { + handleNotFound(server1); +} + +void handleNotFound2() { + handleNotFound(server2); +} + +void setup(void) { + pinMode(led, OUTPUT); + digitalWrite(led, 0); + Serial.begin(115200); + + Serial.println("Multi-homed Servers example starting"); + delay(1000); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.print("Connecting "); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to \""); + Serial.print(ssid); + Serial.print("\", IP address: \""); + Serial.println(WiFi.localIP()); + if (!WiFi.softAP(apssid)) { + Serial.println("failed to start softAP"); + for (;;) { + digitalWrite(led, 1); + delay(100); + digitalWrite(led, 0); + delay(100); + } + } + Serial.print("Soft AP SSID: \""); + Serial.print(apssid); + Serial.print("\", IP address: "); + Serial.println(WiFi.softAPIP()); + + if (MDNS.begin("esp32")) { + Serial.println("MDNS responder started"); + } + + server0 = new WebServer(8080); + server1 = new WebServer(WiFi.localIP(), 8081); + server2 = new WebServer(WiFi.softAPIP(), 8081); + + server0->on("/", handleRoot0); + server1->on("/", handleRoot1); + server2->on("/", handleRoot2); + + server0->onNotFound(handleNotFound0); + server1->onNotFound(handleNotFound1); + server2->onNotFound(handleNotFound2); + + server0->begin(); + Serial.println("HTTP server0 started"); + server1->begin(); + Serial.println("HTTP server1 started"); + server2->begin(); + Serial.println("HTTP server2 started"); + + Serial.printf("SSID: %s\n\thttp://", ssid); + Serial.print(WiFi.localIP()); + Serial.print(":8080\n\thttp://"); + Serial.print(WiFi.localIP()); + Serial.println(":8081"); + Serial.printf("SSID: %s\n\thttp://", apssid); + Serial.print(WiFi.softAPIP()); + Serial.print(":8080\n\thttp://"); + Serial.print(WiFi.softAPIP()); + Serial.println(":8081"); + Serial.printf("Any of the above SSIDs\n\thttp://esp32.local:8080\n\thttp://esp32.local:8081\n"); +} + +void loop(void) { + server0->handleClient(); + server1->handleClient(); + server2->handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/MultiHomedServers/README.md b/libraries/WebServer/examples/MultiHomedServers/README.md new file mode 100644 index 0000000..04b96df --- /dev/null +++ b/libraries/WebServer/examples/MultiHomedServers/README.md @@ -0,0 +1,115 @@ +# Multi Homed Servers + +This example tests support for multi-homed servers, i.e. a distinct web servers on distinct IP interface. + +It only tests the case n=2 because on a basic ESP32 device, we only have two IP interfaces, namely the Wi-Fi station interfaces and the Wi-Fi soft AP interface. +For this to work, the WebServer and the NetworkServer classes must correctly handle the case where an IP address is passed to their relevant constructor. +It also requires WebServer to work with multiple, simultaneous instances. + +Testing the WebServer and the NetworkServer constructors was the primary purpose of this script. +The part of WebServer used by this sketch does seem to work with multiple, simultaneous instances. +However there is much functionality in WebServer that is not tested here. It may all be well, but that is not proven here. + +This sketch starts the mDNS server, as did HelloServer, and it resolves esp32.local on both interfaces, but was not otherwise tested. +This script also tests that a server not bound to a specific IP address still works. + +We create three, simultaneous web servers, one specific to each interface and one that listens on both: + +| name | IP Address | Port | +| ---- | ---------- | ---- | +| server0 | INADDR_ANY | 8080 | +| server1 | station address | 8081 | +| server2 | soft AP address | 8081 | + +The expected responses to a browser's requests are as follows: + +#### 1. The Client connected to the same WLAN as the station: + +| Request URL | Response | +| ----------- | -------- | +| [http://stationaddress:8080](http://stationaddress:8080) | Hello from server0 who listens on both WLAN and own Soft AP | +| [http://stationaddress:8081](http://stationaddress:8081) | Hello from server1 who listens only on WLAN | + +#### 2. The Client is connected to the soft AP: + +| Request URL | Response | +| ----------- | -------- | +| [http://softAPaddress:8080](http://softAPaddress:8080) | Hello from server0 who listens on both WLAN and own Soft AP | +| [http://softAPaddress:8081](http://softAPaddress:8081) | Hello from server2 who listens only on own Soft AP | + +#### 3. The Client is connect to either WLAN or SoftAP: + +| Request URL | Response | +| ----------- | -------- | +| [http://esp32.local:8080](http://esp32.local:8080) | Hello from server0 who listens on both WLAN and own Soft AP | +| [http://esp32.local:8081](http://esp32.local:8081) | Hello from server1 who listens only on WLAN | + +MultiHomedServers was originally based on HelloServer. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | + +## How to Use Example + +Change the SSID and password in the example to your Wi-Fi and flash the example. +Open a serial terminal and the example will write the exact addresses with used IP addresses you can use to test the servers. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example Log Output + +``` +Multi-homed Servers example starting +Connecting ... +Connected to "WiFi_SSID", IP address: "192.168.42.24 +Soft AP SSID: "ESP32", IP address: 192.168.4.1 +MDNS responder started +SSID: WiFi_SSID + http://192.168.42.24:8080 + http://192.168.42.24:8081 +SSID: ESP32 + http://192.168.4.1:8080 + http://192.168.4.1:8081 +Any of the above SSIDs + http://esp32.local:8080 + http://esp32.local:8081 +HTTP server0 started +HTTP server1 started +HTTP server2 started +``` + +## Known issues + +`http://esp32.local` Does not work on some Android phones + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WebServer/examples/MultiHomedServers/ci.yml b/libraries/WebServer/examples/MultiHomedServers/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/MultiHomedServers/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/PathArgServer/PathArgServer.ino b/libraries/WebServer/examples/PathArgServer/PathArgServer.ino new file mode 100644 index 0000000..1debb18 --- /dev/null +++ b/libraries/WebServer/examples/PathArgServer/PathArgServer.ino @@ -0,0 +1,57 @@ +#include +#include +#include +#include + +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +void setup(void) { + Serial.begin(9600); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + if (MDNS.begin("esp32")) { + Serial.println("MDNS responder started"); + } + + server.on(F("/"), []() { + server.send(200, "text/plain", "hello from esp32!"); + }); + + server.on(UriBraces("/users/{}"), []() { + String user = server.pathArg(0); + server.send(200, "text/plain", "User: '" + user + "'"); + }); + + server.on(UriRegex("^\\/users\\/([0-9]+)\\/devices\\/([0-9]+)$"), []() { + String user = server.pathArg(0); + String device = server.pathArg(1); + server.send(200, "text/plain", "User: '" + user + "' and Device: '" + device + "'"); + }); + + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/PathArgServer/ci.yml b/libraries/WebServer/examples/PathArgServer/ci.yml new file mode 100644 index 0000000..9f15b34 --- /dev/null +++ b/libraries/WebServer/examples/PathArgServer/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/SDWebServer/SDWebServer.ino b/libraries/WebServer/examples/SDWebServer/SDWebServer.ino new file mode 100644 index 0000000..23fcc3f --- /dev/null +++ b/libraries/WebServer/examples/SDWebServer/SDWebServer.ino @@ -0,0 +1,320 @@ +/* + SDWebServer - Example WebServer with SD Card backend for esp8266 + + Copyright (c) 2015 Hristo Gochkov. All rights reserved. + This file is part of the WebServer library for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Have a FAT Formatted SD Card connected to the SPI port of the ESP8266 + The web root is the SD Card root folder + File extensions with more than 3 characters are not supported by the SD Library + File Names longer than 8 characters will be truncated by the SD library, so keep filenames shorter + index.htm is the default index (works on subfolders as well) + + upload the contents of SdRoot to the root of the SDcard and access the editor by going to http://esp8266sd.local/edit + To retrieve the contents of SDcard, visit http://esp32sd.local/list?dir=/ + dir is the argument that needs to be passed to the function PrintDirectory via HTTP Get request. + +*/ +#include +#include +#include +#include +#include +#include + +#define DBG_OUTPUT_PORT Serial + +const char *ssid = "**********"; +const char *password = "**********"; +const char *host = "esp32sd"; + +WebServer server(80); + +static bool hasSD = false; +File uploadFile; + +void returnOK() { + server.send(200, "text/plain", ""); +} + +void returnFail(String msg) { + server.send(500, "text/plain", msg + "\r\n"); +} + +bool loadFromSdCard(String path) { + String dataType = "text/plain"; + if (path.endsWith("/")) { + path += "index.htm"; + } + + if (path.endsWith(".src")) { + path = path.substring(0, path.lastIndexOf(".")); + } else if (path.endsWith(".htm")) { + dataType = "text/html"; + } else if (path.endsWith(".css")) { + dataType = "text/css"; + } else if (path.endsWith(".js")) { + dataType = "application/javascript"; + } else if (path.endsWith(".png")) { + dataType = "image/png"; + } else if (path.endsWith(".gif")) { + dataType = "image/gif"; + } else if (path.endsWith(".jpg")) { + dataType = "image/jpeg"; + } else if (path.endsWith(".ico")) { + dataType = "image/x-icon"; + } else if (path.endsWith(".xml")) { + dataType = "text/xml"; + } else if (path.endsWith(".pdf")) { + dataType = "application/pdf"; + } else if (path.endsWith(".zip")) { + dataType = "application/zip"; + } + + File dataFile = SD.open(path.c_str()); + if (dataFile.isDirectory()) { + path += "/index.htm"; + dataType = "text/html"; + dataFile = SD.open(path.c_str()); + } + + if (!dataFile) { + return false; + } + + if (server.hasArg("download")) { + dataType = "application/octet-stream"; + } + + if (server.streamFile(dataFile, dataType) != dataFile.size()) { + DBG_OUTPUT_PORT.println("Sent less data than expected!"); + } + + dataFile.close(); + return true; +} + +void handleFileUpload() { + if (server.uri() != "/edit") { + return; + } + HTTPUpload &upload = server.upload(); + if (upload.status == UPLOAD_FILE_START) { + if (SD.exists((char *)upload.filename.c_str())) { + SD.remove((char *)upload.filename.c_str()); + } + uploadFile = SD.open(upload.filename.c_str(), FILE_WRITE); + DBG_OUTPUT_PORT.print("Upload: START, filename: "); + DBG_OUTPUT_PORT.println(upload.filename); + } else if (upload.status == UPLOAD_FILE_WRITE) { + if (uploadFile) { + uploadFile.write(upload.buf, upload.currentSize); + } + DBG_OUTPUT_PORT.print("Upload: WRITE, Bytes: "); + DBG_OUTPUT_PORT.println(upload.currentSize); + } else if (upload.status == UPLOAD_FILE_END) { + if (uploadFile) { + uploadFile.close(); + } + DBG_OUTPUT_PORT.print("Upload: END, Size: "); + DBG_OUTPUT_PORT.println(upload.totalSize); + } +} + +void deleteRecursive(String path) { + File file = SD.open((char *)path.c_str()); + if (!file.isDirectory()) { + file.close(); + SD.remove((char *)path.c_str()); + return; + } + + file.rewindDirectory(); + while (true) { + File entry = file.openNextFile(); + if (!entry) { + break; + } + String entryPath = path + "/" + entry.name(); + if (entry.isDirectory()) { + entry.close(); + deleteRecursive(entryPath); + } else { + entry.close(); + SD.remove((char *)entryPath.c_str()); + } + yield(); + } + + SD.rmdir((char *)path.c_str()); + file.close(); +} + +void handleDelete() { + if (server.args() == 0) { + return returnFail("BAD ARGS"); + } + String path = server.arg(0); + if (path == "/" || !SD.exists((char *)path.c_str())) { + returnFail("BAD PATH"); + return; + } + deleteRecursive(path); + returnOK(); +} + +void handleCreate() { + if (server.args() == 0) { + return returnFail("BAD ARGS"); + } + String path = server.arg(0); + if (path == "/" || SD.exists((char *)path.c_str())) { + returnFail("BAD PATH"); + return; + } + + if (path.indexOf('.') > 0) { + File file = SD.open((char *)path.c_str(), FILE_WRITE); + if (file) { + file.write(0); + file.close(); + } + } else { + SD.mkdir((char *)path.c_str()); + } + returnOK(); +} + +void printDirectory() { + if (!server.hasArg("dir")) { + return returnFail("BAD ARGS"); + } + String path = server.arg("dir"); + if (path != "/" && !SD.exists((char *)path.c_str())) { + return returnFail("BAD PATH"); + } + File dir = SD.open((char *)path.c_str()); + path = String(); + if (!dir.isDirectory()) { + dir.close(); + return returnFail("NOT DIR"); + } + dir.rewindDirectory(); + server.setContentLength(CONTENT_LENGTH_UNKNOWN); + server.send(200, "text/json", ""); + + server.sendContent("["); + for (int cnt = 0; true; ++cnt) { + File entry = dir.openNextFile(); + if (!entry) { + break; + } + + String output; + if (cnt > 0) { + output = ','; + } + + output += "{\"type\":\""; + output += (entry.isDirectory()) ? "dir" : "file"; + output += "\",\"name\":\""; + output += entry.path(); + output += "\""; + output += "}"; + server.sendContent(output); + entry.close(); + } + server.sendContent("]"); + dir.close(); +} + +void handleNotFound() { + if (hasSD && loadFromSdCard(server.uri())) { + return; + } + String message = "SDCARD Not Detected\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + for (uint8_t i = 0; i < server.args(); i++) { + message += " NAME:" + server.argName(i) + "\n VALUE:" + server.arg(i) + "\n"; + } + server.send(404, "text/plain", message); + DBG_OUTPUT_PORT.print(message); +} + +void setup(void) { + DBG_OUTPUT_PORT.begin(115200); + DBG_OUTPUT_PORT.setDebugOutput(true); + DBG_OUTPUT_PORT.print("\n"); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + DBG_OUTPUT_PORT.print("Connecting to "); + DBG_OUTPUT_PORT.println(ssid); + + // Wait for connection + uint8_t i = 0; + while (WiFi.status() != WL_CONNECTED && i++ < 20) { //wait 10 seconds + delay(500); + } + if (i == 21) { + DBG_OUTPUT_PORT.print("Could not connect to"); + DBG_OUTPUT_PORT.println(ssid); + while (1) { + delay(500); + } + } + DBG_OUTPUT_PORT.print("Connected! IP address: "); + DBG_OUTPUT_PORT.println(WiFi.localIP()); + + if (MDNS.begin(host)) { + MDNS.addService("http", "tcp", 80); + DBG_OUTPUT_PORT.println("MDNS responder started"); + DBG_OUTPUT_PORT.print("You can now connect to http://"); + DBG_OUTPUT_PORT.print(host); + DBG_OUTPUT_PORT.println(".local"); + } + + server.on("/list", HTTP_GET, printDirectory); + server.on("/edit", HTTP_DELETE, handleDelete); + server.on("/edit", HTTP_PUT, handleCreate); + server.on( + "/edit", HTTP_POST, + []() { + returnOK(); + }, + handleFileUpload + ); + server.onNotFound(handleNotFound); + + server.begin(); + DBG_OUTPUT_PORT.println("HTTP server started"); + + if (SD.begin(SS)) { + DBG_OUTPUT_PORT.println("SD Card initialized."); + hasSD = true; + } +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm b/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm new file mode 100644 index 0000000..054846f --- /dev/null +++ b/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm @@ -0,0 +1,674 @@ + + + + SD Editor + + + + + +
+
+
+ + + + diff --git a/libraries/WebServer/examples/SDWebServer/SdRoot/index.htm b/libraries/WebServer/examples/SDWebServer/SdRoot/index.htm new file mode 100644 index 0000000..55fe5a6 --- /dev/null +++ b/libraries/WebServer/examples/SDWebServer/SdRoot/index.htm @@ -0,0 +1,22 @@ + + + + + ESP Index + + + + +

ESP8266 Pin Functions

+ + + diff --git a/libraries/WebServer/examples/SDWebServer/SdRoot/pins.png b/libraries/WebServer/examples/SDWebServer/SdRoot/pins.png new file mode 100644 index 0000000..ac7fc0f Binary files /dev/null and b/libraries/WebServer/examples/SDWebServer/SdRoot/pins.png differ diff --git a/libraries/WebServer/examples/SDWebServer/ci.yml b/libraries/WebServer/examples/SDWebServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/SDWebServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino b/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino new file mode 100644 index 0000000..2104292 --- /dev/null +++ b/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino @@ -0,0 +1,132 @@ +#include +#include +#include + +const char *ssid = "........"; +const char *password = "........"; + +WebServer server(80); + +//Check if header is present and correct +bool is_authentified() { + Serial.println("Enter is_authentified"); + if (server.hasHeader("Cookie")) { + Serial.print("Found cookie: "); + String cookie = server.header("Cookie"); + Serial.println(cookie); + if (cookie.indexOf("ESPSESSIONID=1") != -1) { + Serial.println("Authentication Successful"); + return true; + } + } + Serial.println("Authentication Failed"); + return false; +} + +//login page, also called for disconnect +void handleLogin() { + String msg; + if (server.hasHeader("Cookie")) { + Serial.print("Found cookie: "); + String cookie = server.header("Cookie"); + Serial.println(cookie); + } + if (server.hasArg("DISCONNECT")) { + Serial.println("Disconnection"); + server.sendHeader("Location", "/login"); + server.sendHeader("Cache-Control", "no-cache"); + server.sendHeader("Set-Cookie", "ESPSESSIONID=0"); + server.send(301); + return; + } + if (server.hasArg("USERNAME") && server.hasArg("PASSWORD")) { + if (server.arg("USERNAME") == "admin" && server.arg("PASSWORD") == "admin") { + server.sendHeader("Location", "/"); + server.sendHeader("Cache-Control", "no-cache"); + server.sendHeader("Set-Cookie", "ESPSESSIONID=1"); + server.send(301); + Serial.println("Log in Successful"); + return; + } + msg = "Wrong username/password! try again."; + Serial.println("Log in Failed"); + } + String content = "
To log in, please use : admin/admin
"; + content += "User:
"; + content += "Password:
"; + content += "
" + msg + "
"; + content += "You also can go here"; + server.send(200, "text/html", content); +} + +//root page can be accessed only if authentication is ok +void handleRoot() { + Serial.println("Enter handleRoot"); + String header; + if (!is_authentified()) { + server.sendHeader("Location", "/login"); + server.sendHeader("Cache-Control", "no-cache"); + server.send(301); + return; + } + String content = "

hello, you successfully connected to esp8266!


"; + if (server.hasHeader("User-Agent")) { + content += "the user agent used is : " + server.header("User-Agent") + "

"; + } + content += "You can access this page until you disconnect"; + server.send(200, "text/html", content); +} + +//no need authentication +void handleNotFound() { + String message = "File Not Found\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + for (uint8_t i = 0; i < server.args(); i++) { + message += " " + server.argName(i) + ": " + server.arg(i) + "\n"; + } + server.send(404, "text/plain", message); +} + +void setup(void) { + Serial.begin(115200); + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + Serial.println(""); + + // Wait for connection + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + server.on("/", handleRoot); + server.on("/login", handleLogin); + server.on("/inline", []() { + server.send(200, "text/plain", "this works without need of authentication"); + }); + + server.onNotFound(handleNotFound); + //here the list of headers to be recorded + const char *headerkeys[] = {"User-Agent", "Cookie"}; + size_t headerkeyssize = sizeof(headerkeys) / sizeof(char *); + //ask server to track these headers + server.collectHeaders(headerkeys, headerkeyssize); + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/SimpleAuthentification/ci.yml b/libraries/WebServer/examples/SimpleAuthentification/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/SimpleAuthentification/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/UploadHugeFile/README.md b/libraries/WebServer/examples/UploadHugeFile/README.md new file mode 100644 index 0000000..607dc9d --- /dev/null +++ b/libraries/WebServer/examples/UploadHugeFile/README.md @@ -0,0 +1,13 @@ +# Upload Huge File To SD Over Http + +This project is an example of an HTTP server designed to facilitate the transfer of large files using the PUT method, in accordance with RFC specifications. + +### Example cURL Command + +```bash +curl -X PUT -T ./my-file.mp3 http://esp-ip/upload/my-file.mp3 +``` + +## Resources + +- RFC HTTP/1.0 - Additional Request Methods - PUT : [Link](https://datatracker.ietf.org/doc/html/rfc1945#appendix-D.1.1) diff --git a/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino b/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino new file mode 100644 index 0000000..54c94ed --- /dev/null +++ b/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino @@ -0,0 +1,88 @@ +#include +#include +#include +#include + +const char *ssid = "**********"; +const char *password = "**********"; + +WebServer server(80); + +File rawFile; +void handleCreate() { + server.send(200, "text/plain", ""); +} +void handleCreateProcess() { + String path = "/" + server.pathArg(0); + HTTPRaw &raw = server.raw(); + if (raw.status == RAW_START) { + if (SD.exists((char *)path.c_str())) { + SD.remove((char *)path.c_str()); + } + rawFile = SD.open(path.c_str(), FILE_WRITE); + Serial.print("Upload: START, filename: "); + Serial.println(path); + } else if (raw.status == RAW_WRITE) { + if (rawFile) { + rawFile.write(raw.buf, raw.currentSize); + } + Serial.print("Upload: WRITE, Bytes: "); + Serial.println(raw.currentSize); + } else if (raw.status == RAW_END) { + if (rawFile) { + rawFile.close(); + } + Serial.print("Upload: END, Size: "); + Serial.println(raw.totalSize); + } +} + +void returnFail(String msg) { + server.send(500, "text/plain", msg + "\r\n"); +} + +void handleNotFound() { + String message = "File Not Found\n\n"; + message += "URI: "; + message += server.uri(); + message += "\nMethod: "; + message += (server.method() == HTTP_GET) ? "GET" : "POST"; + message += "\nArguments: "; + message += server.args(); + message += "\n"; + for (uint8_t i = 0; i < server.args(); i++) { + message += " " + server.argName(i) + ": " + server.arg(i) + "\n"; + } + server.send(404, "text/plain", message); +} + +void setup(void) { + Serial.begin(115200); + + while (!SD.begin()) { + delay(1); + } + Serial.println("SD Card initialized."); + + WiFi.mode(WIFI_STA); + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.print("Connected to "); + Serial.println(ssid); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + + server.on(UriRegex("/upload/(.*)"), HTTP_PUT, handleCreate, handleCreateProcess); + server.onNotFound(handleNotFound); + server.begin(); + Serial.println("HTTP server started"); +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/UploadHugeFile/ci.yml b/libraries/WebServer/examples/UploadHugeFile/ci.yml new file mode 100644 index 0000000..9f15b34 --- /dev/null +++ b/libraries/WebServer/examples/UploadHugeFile/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=huge_app + +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/WebServer/README.md b/libraries/WebServer/examples/WebServer/README.md new file mode 100644 index 0000000..b316682 --- /dev/null +++ b/libraries/WebServer/examples/WebServer/README.md @@ -0,0 +1,297 @@ +# Arduino-ESP32 WebServer Example for WebServer Library + +This example shows different techniques on how to use and extend the WebServer for specific purposes + +It is a small project in it's own and has some files to use on the web server to show how to use simple REST based services. + +This example requires some space for a filesystem and runs fine on supported SoCs with 4 MByte or more flash by selecting the proper partition table: + +* For using SPIFFS(LittleFS): `Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)` +* For using FATFS: `Default 4MB with ffat (1.2MB APP/1.5MB FATFS)` + + +It features + +* Setup a web server +* redirect when accessing the url with servername only +* get real time by using builtin NTP functionality +* send HTML responses from Sketch (see builtinfiles.h) +* use a LittleFS file system on the data partition for static files +* use http ETag Header for client side caching of static files +* use custom ETag calculation for static files +* extended FileServerHandler for uploading and deleting static files +* uploading files using drag & drop +* serve APIs using REST services (/api/list, /api/sysinfo) +* define HTML response when no file/api/handler was found + +## Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 | ESP32-C6 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | +| | yes | yes | yes | yes | yes | + +## Use the Example + +How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +* In the file `secrets.h` you can add the home Wi-Fi network name ans password. +* Compile and upload to the device. +* Have a look into the monitoring output. +* Open or using a browser. +* You will be redirected to as there are no files yet in the file system. +* Drag the files from the data folder onto the drop area shown in the browser. +* See below for more details + +## Implementing a web server + +The WebServer library offers a simple path to implement a web server on a ESP32 based board. + +The advantage on using the WebServer instead of the plain simple NetworkServer is that the WebServer +takes much care about the http protocol conventions and features and allows easily access to parameters. +It offers plug-in capabilities by registering specific functionalities that will be outlined below. + +### Initialization + +In the setup() function in the webserver.ino sketch file the following steps are implemented to make the webserver available on the local network. + +* Create a webserver listening to port 80 for HTTP requests. +* Initialize the access to the filesystem in the free flash memory. +* Connect to the local Wi-Fi network. Here is only a straight-forward implementation hard-coding network name and passphrase. You may consider to use something like the WiFiManager library in real applications. +* Register the device in DNS using a known hostname. +* Registering several plug-ins (see below). +* Starting the web server. + +### Running + +In the loop() function the web server will be given time to receive and send network packages by calling +`server.handleClient();`. + +## Registering simple functions to implement RESTful services + +Registering function is the simplest integration mechanism available to add functionality. The server offers the `on(path, function)` methods that take the URL and the function as parameters. + +There are 2 functions implemented that get registered to handle incoming GET requests for given URLs. + +The JSON data format is used often for such services as it is the "natural" data format of the browser using javascript. + +When the **handleSysInfo()** function is registered and a browser requests for the function will be called and can collect the requested information. + +> ```CPP +> server.on("/api/sysinfo", handleSysInfo); +> ``` + +The result in this case is a JSON object that is assembled in the result String variable and the returned as a response to the client also giving the information about the data format. + +You can try this request in a browser by opening in the address bar. + +> ```CPP +> server.on("/api/sysinfo", handleList); +> ``` + +The function **handleList()** is registered the same way to return the list of files in the file system also returning a JSON object including name, size and the last modification timestamp. + +You can try this request in a browser by opening in the address bar. + +## Registering a function to send out some static content from a String + +This is an example of registering a inline function in the web server. +The 2. parameter of the on() method is a so called CPP lambda function (without a name) +that actually has only one line of functionality by sending a string as result to the client. + +> ``` cpp +> server.on("/$upload.htm", []() { +> server.send(200, "text/html", FPSTR(uploadContent)); +> }); +> ``` + +Here the text from a static String with html code is returned instead of a file from the filesystem. +The content of this string can be found in the file `builtinfiles.h`. It contains a small html+javascript implementation +that allows uploading new files into the empty filesystem. + +Just open and drag some files from the data folder on the drop area. + +## Registering a function to handle requests to the server without a path + +Often servers are addressed by using the base URL like where no further path details is given. +Of course we like the user to be redirected to something usable. Therefore the `handleRoot()` function is registered: + +> ``` cpp +> server.on("/$upload.htm", handleRoot); +> ``` + +The `handleRoot()` function checks the filesystem for the file named **/index.htm** and creates a redirect to this file when the file exists. +Otherwise the redirection goes to the built-in **/$upload.htm** web page. + +## Using the serveStatic plug-in + +The **serveStatic** plug in is part of the library and handles delivering files from the filesystem to the client. It can be customized in some ways. + +> ``` cpp +> server.enableCORS(true); +> server.enableETag(true); +> server.serveStatic("/", LittleFS, "/"); +> ``` + +### Cross-Origin Resource Sharing (CORS) + +The `enableCORS(true)` function adds a `Access-Control-Allow-Origin: *` http-header to all responses to the client +to inform that it is allowed to call URLs and services on this server from other web sites. + +The feature is disabled by default (in the current version) and when you like to disable this then you should call `enableCORS(false)` during setup. + +* Web sites providing high sensitive information like online banking this is disabled most of the times. +* Web sites providing advertising information or reusable scripts / images this is enabled. + +### enabling ETag support + +To enable this in the embedded web server the `enableETag()` can be used. +(next to enableCORS) + +In the simplest version just call `enableETag(true)` to enable the internal ETag generation that calcs the hint using a md5 checksum in base64 encoded form. This is an simple approach that adds some time for calculation on every request but avoids network traffic. + +The headers will look like: + +``` txt +If-None-Match: "GhZka3HevoaEBbtQOgOqlA==" +ETag: "GhZka3HevoaEBbtQOgOqlA==" +``` + + +### ETag support customization + +The enableETag() function has an optional second optional parameter to provide a function for ETag calculation of files. + +The function enables eTags for all files by using calculating a value from the last write timestamp: + +``` cpp +server.enableETag(true, [](FS &fs, const String &path) -> String { + File f = fs.open(path, "r"); + String eTag = String(f.getLastWrite(), 16); // use file modification timestamp to create ETag + f.close(); + return (eTag); +}); +``` + +The headers will look like: + +``` txt +ETag: "63bbaeb5" +If-None-Match: "63bbaeb5" +``` + + +## Registering a full-featured handler as plug-in + +The example also implements the class `FileServerHandler` derived from the class `RequestHandler` to plug in functionality +that can handle more complex requests without giving a fixed URL. +It implements uploading and deleting files in the file system that is not implemented by the standard server.serveStatic functionality. + +This class has to implements several functions and works in a more detailed way: + +* The `canHandle()` method can inspect the given http method and url to decide weather the RequestFileHandler can handle the incoming request or not. + + In this case the RequestFileHandler will return true when the request method is an POST for upload or a DELETE for deleting files. + + The regular GET requests will be ignored and therefore handled by the also registered server.serveStatic handler. + +* The function `handle()` then implements the real deletion of the file. + +* The `canUpload()`and `upload()` methods work similar while the `upload()` method is called multiple times to create, append data and close the new file. + + +## File upload + +By opening you can easily upload files by dragging them over the drop area. + +Just take the files from the data folder to create some files that can explore the server functionality. + +Files will be uploaded to the root folder of the file system. and you will see it next time using . + +The filesize that is uploaded is not known when the upload mechanism in function +FileServerHandler::upload gets started. + +Uploading a file that fits into the available filesystem space +can be found in the Serial output: + +``` txt +starting upload file /file.txt... +finished. +1652 bytes uploaded. +``` + +Uploading a file that doesn't fit can be detected while uploading when writing to the filesystem fails. +However upload cannot be aborted by the current handler implementation. + +The solution implemented here is to delete the partially uploaded file and wait for the upload ending. +The following can be found in the Serial output: + +``` txt +starting upload file /huge.jpg... +./components/esp_littlefs/src/littlefs/lfs.c:584:error: No more free space 531 + write error! +finished. +``` + +You can see on the Serial output that one filesystem write error is reported. + +Please be patient and wait for the upload ending even when writing to the filesystem is disabled +it maybe take more than a minute. + + +## Registering a special handler for "file not found" + +Any other incoming request that was not handled by the registered plug-ins above can be detected by registering + +> ``` cpp +> // handle cases when file is not found +> server.onNotFound([]() { +> // standard not found in browser. +> server.send(404, "text/html", FPSTR(notFoundContent)); +> }); +> ``` + +This allows sending back an "friendly" result for the browser. Here a simple html page is created from a static string. +You can easily change the html code in the file `builtinfiles.h`. + + +## customizations + +You may like to change the hostname and the timezone in the lines: + +> ``` cpp +> #define HOSTNAME "webserver" +> #define TIMEZONE "CET-1CEST,M3.5.0,M10.5.0/3" +> ``` + + +## Troubleshooting + +Have a look in the Serial output for some additional runtime information. + + +## Changes + +* 2024-08-02 -- Fixing for board implementation 3.0.4 ff. +* 2024-08-02 -- Support for FAT + + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WebServer/examples/WebServer/WebServer.ino b/libraries/WebServer/examples/WebServer/WebServer.ino new file mode 100644 index 0000000..809a95c --- /dev/null +++ b/libraries/WebServer/examples/WebServer/WebServer.ino @@ -0,0 +1,376 @@ +// @file WebServer.ino +// @brief Example WebServer implementation using the ESP32 WebServer +// and most common use cases related to web servers. +// +// * Setup a web server +// * redirect when accessing the url with servername only +// * get real time by using builtin NTP functionality +// * send HTML responses from Sketch (see builtinfiles.h) +// * use a LittleFS file system on the data partition for static files +// * use http ETag Header for client side caching of static files +// * use custom ETag calculation for static files +// * extended FileServerHandler for uploading and deleting static files +// * extended FileServerHandler for uploading and deleting static files +// * serve APIs using REST services (/api/list, /api/sysinfo) +// * define HTML response when no file/api/handler was found +// +// See also README.md for instructions and hints. +// +// Please use the following Arduino IDE configuration +// +// * Board: "ESP32 Dev Module" or other board with ESP32 +// * Partition Scheme: "Default 4MB with spiffs" or any other scheme with spiffs or FAT +// but LittleFS will be used in the partition (not SPIFFS) +// * other setting as applicable +// +// Changelog: +// 21.07.2021 creation, first version +// 08.01.2023 ESP32 version with ETag +// 02.08.2024 support LitteFS and FAT file systems (on large Flash chips) + +#include +#include +#include + +#include "secrets.h" // add WLAN Credentials in here. + +#include "esp_partition.h" // to check existing data partitions in Flash memory + +#include // File System for Web Server Files +#include // Use LittleFSThis file system is used. +#include // or.. FAT + +// mark parameters not used in example +#define UNUSED __attribute__((unused)) + +// TRACE output simplified, can be deactivated here +#define TRACE(...) Serial.printf(__VA_ARGS__) + +// name of the server. You reach it using http://webserver +#define HOSTNAME "webserver" + +// local time zone definition (Berlin) +#define TIMEZONE "CET-1CEST,M3.5.0,M10.5.0/3" + +// need a WebServer for http access on port 80. +WebServer server(80); + +// The file system in use... +fs::FS *fsys = nullptr; + +// The text of builtin files are in this header file +#include "builtinfiles.h" + +// enable the CUSTOM_ETAG_CALC to enable calculation of ETags by a custom function +#define CUSTOM_ETAG_CALC + +// ===== Simple functions used to answer simple GET requests ===== + +// This function is called when the WebServer was requested without giving a filename. +// This will redirect to the file index.htm when it is existing otherwise to the built-in $upload.htm page +void handleRedirect() { + TRACE("Redirect...\n"); + String url = "/index.htm"; + + if (!fsys->exists(url)) { + url = "/$upload.htm"; + } + + server.sendHeader("Location", url, true); + server.send(302); +} // handleRedirect() + +// This function is called when the WebServer was requested to list all existing files in the filesystem. +// a JSON array with file information is returned. +void handleListFiles() { + File dir = fsys->open("/", "r"); + String result; + + result += "[\n"; + while (File entry = dir.openNextFile()) { + if (result.length() > 4) { + result += ",\n"; + } + result += " {"; + result += "\"type\": \"file\", "; + result += "\"name\": \"" + String(entry.name()) + "\", "; + result += "\"size\": " + String(entry.size()) + ", "; + result += "\"time\": " + String(entry.getLastWrite()); + result += "}"; + } // while + + result += "\n]"; + server.sendHeader("Cache-Control", "no-cache"); + server.send(200, "text/javascript; charset=utf-8", result); +} // handleListFiles() + +// This function is called when the sysInfo service was requested. +void handleSysInfo() { + String result; + + result += "{\n"; + result += " \"Chip Model\": " + String(ESP.getChipModel()) + ",\n"; + result += " \"Chip Cores\": " + String(ESP.getChipCores()) + ",\n"; + result += " \"Chip Revision\": " + String(ESP.getChipRevision()) + ",\n"; + result += " \"flashSize\": " + String(ESP.getFlashChipSize()) + ",\n"; + result += " \"freeHeap\": " + String(ESP.getFreeHeap()) + ",\n"; + + if (fsys == (fs::FS *)&FFat) { + result += " \"fsTotalBytes\": " + String(FFat.totalBytes()) + ",\n"; + result += " \"fsUsedBytes\": " + String(FFat.usedBytes()) + ",\n"; + } else { + result += " \"fsTotalBytes\": " + String(LittleFS.totalBytes()) + ",\n"; + result += " \"fsUsedBytes\": " + String(LittleFS.usedBytes()) + ",\n"; + } + + result += "}"; + + server.sendHeader("Cache-Control", "no-cache"); + server.send(200, "text/javascript; charset=utf-8", result); +} // handleSysInfo() + +// ===== Request Handler class used to answer more complex requests ===== + +// The FileServerHandler is registered to the web server to support DELETE and UPLOAD of files into the filesystem. +class FileServerHandler : public RequestHandler { +public: + // @brief Construct a new File Server Handler object + // @param fs The file system to be used. + // @param path Path to the root folder in the file system that is used for serving static data down and upload. + // @param cache_header Cache Header to be used in replies. + FileServerHandler() { + TRACE("FileServerHandler is registered\n"); + } + + // @brief check incoming request. Can handle POST for uploads and DELETE. + // @param requestMethod method of the http request line. + // @param requestUri request resource from the http request line. + // @return true when method can be handled. + bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &uri) override { + return ((requestMethod == HTTP_POST) || (requestMethod == HTTP_DELETE)); + } // canHandle() + + bool canUpload(WebServer &server, const String &uri) override { + // only allow upload on root fs level. + return (uri == "/"); + } // canUpload() + + bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override { + // ensure that filename starts with '/' + String fName = requestUri; + if (!fName.startsWith("/")) { + fName = "/" + fName; + } + + if (requestMethod == HTTP_POST) { + // all done in upload. no other forms. + + } else if (requestMethod == HTTP_DELETE) { + if (fsys->exists(fName)) { + TRACE("DELETE %s\n", fName.c_str()); + fsys->remove(fName); + } + } // if + + server.send(200); // all done. + return (true); + } // handle() + + // uploading process + void upload(WebServer UNUSED &server, const String &requestUri, HTTPUpload &upload) override { + // ensure that filename starts with '/' + static size_t uploadSize; + + if (upload.status == UPLOAD_FILE_START) { + String fName = upload.filename; + + // Open the file for writing + if (!fName.startsWith("/")) { + fName = "/" + fName; + } + TRACE("start uploading file %s...\n", fName.c_str()); + + if (fsys->exists(fName)) { + fsys->remove(fName); + } // if + _fsUploadFile = fsys->open(fName, "w"); + uploadSize = 0; + + } else if (upload.status == UPLOAD_FILE_WRITE) { + // Write received bytes + if (_fsUploadFile) { + size_t written = _fsUploadFile.write(upload.buf, upload.currentSize); + if (written < upload.currentSize) { + // upload failed + TRACE(" write error!\n"); + _fsUploadFile.close(); + + // delete file to free up space in filesystem + String fName = upload.filename; + if (!fName.startsWith("/")) { + fName = "/" + fName; + } + fsys->remove(fName); + } + uploadSize += upload.currentSize; + // TRACE("free:: %d of %d\n", LittleFS.usedBytes(), LittleFS.totalBytes()); + // TRACE("written:: %d of %d\n", written, upload.currentSize); + // TRACE("totalSize: %d\n", upload.currentSize + upload.totalSize); + } // if + + } else if (upload.status == UPLOAD_FILE_END) { + TRACE("upload done.\n"); + // Close the file + if (_fsUploadFile) { + _fsUploadFile.close(); + TRACE(" %d bytes uploaded.\n", upload.totalSize); + } + } // if + + } // upload() + +protected: + File _fsUploadFile; +}; + +// Setup everything to make the webserver work. +void setup(void) { + delay(3000); // wait for serial monitor to start completely. + + // Use Serial port for some trace information from the example + Serial.begin(115200); + Serial.setDebugOutput(false); + + TRACE("Starting WebServer example...\n"); + + // ----- check partitions for finding the filesystem type ----- + esp_partition_iterator_t i; + + i = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, nullptr); + if (i) { + TRACE("FAT partition found."); + fsys = &FFat; + + } else { + i = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, nullptr); + if (i) { + TRACE("SPIFFS partition found."); + fsys = &LittleFS; + + } else { + TRACE("no partition found."); + } + } + esp_partition_iterator_release(i); + + // mount and format as needed + TRACE("Mounting the filesystem...\n"); + if (!fsys) { + TRACE("need to change the board configuration to include a partition for files.\n"); + delay(30000); + + } else if ((fsys == (fs::FS *)&FFat) && (!FFat.begin())) { + TRACE("could not mount the filesystem...\n"); + delay(2000); + TRACE("formatting FAT...\n"); + FFat.format(); + delay(2000); + TRACE("restarting...\n"); + delay(2000); + ESP.restart(); + + } else if ((fsys == (fs::FS *)&LittleFS) && (!LittleFS.begin())) { + TRACE("could not mount the filesystem...\n"); + delay(2000); + TRACE("formatting LittleFS...\n"); + LittleFS.format(); + delay(2000); + TRACE("restarting...\n"); + delay(2000); + ESP.restart(); + } + + // allow to address the device by the given name e.g. http://webserver + WiFi.setHostname(HOSTNAME); + + // start WiFI + WiFi.mode(WIFI_STA); + if (strlen(ssid) == 0) { + WiFi.begin(); + } else { + WiFi.begin(ssid, passPhrase); + } + + TRACE("Connect to WiFi...\n"); + while (WiFi.status() != WL_CONNECTED) { + delay(500); + TRACE("."); + } + TRACE("connected.\n"); + + // Ask for the current time using NTP request builtin into ESP firmware. + TRACE("Setup ntp...\n"); + configTzTime(TIMEZONE, "pool.ntp.org"); + + TRACE("Register redirect...\n"); + + // register a redirect handler when only domain name is given. + server.on("/", HTTP_GET, handleRedirect); + + TRACE("Register service handlers...\n"); + + // serve a built-in htm page + server.on("/$upload.htm", []() { + server.send(200, "text/html", FPSTR(uploadContent)); + }); + + // register some REST services + server.on("/api/list", HTTP_GET, handleListFiles); + server.on("/api/sysinfo", HTTP_GET, handleSysInfo); + + TRACE("Register file system handlers...\n"); + + // UPLOAD and DELETE of files in the file system using a request handler. + server.addHandler(new FileServerHandler()); + + // enable CORS header in webserver results + server.enableCORS(true); + + // enable ETAG header in webserver results (used by serveStatic handler) +#if defined(CUSTOM_ETAG_CALC) + // This is a fast custom eTag generator. It returns a value based on the time the file was updated like + // ETag: 63bbceb5 + server.enableETag(true, [](FS &fs, const String &path) -> String { + File f = fs.open(path, "r"); + String eTag = String(f.getLastWrite(), 16); // use file modification timestamp to create ETag + f.close(); + return (eTag); + }); + +#else + // enable standard ETAG calculation using md5 checksum of file content. + server.enableETag(true); +#endif + + // serve all static files + server.serveStatic("/", *fsys, "/"); + + TRACE("Register default (not found) answer...\n"); + + // handle cases when file is not found + server.onNotFound([]() { + // standard not found in browser. + server.send(404, "text/html", FPSTR(notFoundContent)); + }); + + server.begin(); + + TRACE("open or \n", WiFi.getHostname(), WiFi.localIP().toString().c_str()); +} // setup + +// run the server... +void loop(void) { + server.handleClient(); +} // loop() + +// end. diff --git a/libraries/WebServer/examples/WebServer/builtinfiles.h b/libraries/WebServer/examples/WebServer/builtinfiles.h new file mode 100644 index 0000000..c7fa57f --- /dev/null +++ b/libraries/WebServer/examples/WebServer/builtinfiles.h @@ -0,0 +1,63 @@ +/** + * @file builtinfiles.h + * @brief This file is part of the WebServer example for the ESP8266WebServer. + * + * This file contains long, multiline text variables for all builtin resources. + */ + +// used for $upload.htm +static const char uploadContent[] PROGMEM = + R"==( + + + + + + + Upload + + + +

Upload

+ +
+
Drop files here...
+ + + +)=="; + +// used for $upload.htm +static const char notFoundContent[] PROGMEM = R"==( + + + Resource not found + + +

The resource was not found.

+

Start again

+ +)=="; diff --git a/libraries/WebServer/examples/WebServer/ci.yml b/libraries/WebServer/examples/WebServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/WebServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/examples/WebServer/data/files.htm b/libraries/WebServer/examples/WebServer/data/files.htm new file mode 100644 index 0000000..90fb8fa --- /dev/null +++ b/libraries/WebServer/examples/WebServer/data/files.htm @@ -0,0 +1,65 @@ + + + + Files + + + + +

Files on Server

+ +

These files are available on the server to be opened or delete:

+
+
+ + + + + diff --git a/libraries/WebServer/examples/WebServer/data/index.htm b/libraries/WebServer/examples/WebServer/data/index.htm new file mode 100644 index 0000000..312dd7b --- /dev/null +++ b/libraries/WebServer/examples/WebServer/data/index.htm @@ -0,0 +1,25 @@ + + + + HomePage + + + + +

Homepage of the WebServer Example

+ +

The following pages are available:

+ + +

The following REST services are available:

+ + + diff --git a/libraries/WebServer/examples/WebServer/data/style.css b/libraries/WebServer/examples/WebServer/data/style.css new file mode 100644 index 0000000..e2af558 --- /dev/null +++ b/libraries/WebServer/examples/WebServer/data/style.css @@ -0,0 +1,9 @@ +html, body { + color: #111111; font-family: Arial, ui-sans-serif, sans-serif; font-size: 1em; background-color: #f0f0f0; +} + +#list > div { + margin: 0 0 0.5rem 0; +} + +a { color: inherit; cursor: pointer; } diff --git a/libraries/WebServer/examples/WebServer/secrets.h b/libraries/WebServer/examples/WebServer/secrets.h new file mode 100644 index 0000000..0c5d368 --- /dev/null +++ b/libraries/WebServer/examples/WebServer/secrets.h @@ -0,0 +1,13 @@ +// Secrets for your local home network + +// This is a "hard way" to configure your local WiFi network name and passphrase +// into the source code and the uploaded sketch. +// +// Using the WiFi Manager is preferred and avoids reprogramming when your network changes. +// See https://homeding.github.io/#page=/wifimanager.md + +// ssid and passPhrase can be used when compiling for a specific environment as a 2. option. + +// add you wifi network name and PassPhrase or use WiFi Manager +const char *ssid = ""; +const char *passPhrase = ""; diff --git a/libraries/WebServer/examples/WebUpdate/WebUpdate.ino b/libraries/WebServer/examples/WebUpdate/WebUpdate.ino new file mode 100644 index 0000000..59def0a --- /dev/null +++ b/libraries/WebServer/examples/WebUpdate/WebUpdate.ino @@ -0,0 +1,107 @@ +/* + To upload through terminal you can use: curl -F "image=@firmware.bin" esp8266-webupdate.local/update +*/ + +#include +#include +#include +#include +#include + +const char *host = "esp32-webupdate"; +const char *ssid = "........"; +const char *password = "........"; + +// Set the username and password for firmware upload +const char *authUser = "........"; +const char *authPass = "........"; + +WebServer server(80); +const char *serverIndex = + "
"; + +const char *csrfHeaders[2] = {"Origin", "Host"}; +static bool authenticated = false; + +void setup(void) { + Serial.begin(115200); + Serial.println(); + Serial.println("Booting Sketch..."); + WiFi.mode(WIFI_AP_STA); + WiFi.begin(ssid, password); + if (WiFi.waitForConnectResult() == WL_CONNECTED) { + MDNS.begin(host); + server.collectHeaders(csrfHeaders, 2); + server.on("/", HTTP_GET, []() { + if (!server.authenticate(authUser, authPass)) { + return server.requestAuthentication(); + } + server.sendHeader("Connection", "close"); + server.send(200, "text/html", serverIndex); + }); + server.on( + "/update", HTTP_POST, + []() { + if (!authenticated) { + return server.requestAuthentication(); + } + server.sendHeader("Connection", "close"); + if (Update.hasError()) { + server.send(200, "text/plain", "FAIL"); + } else { + server.send(200, "text/plain", "Success! Rebooting..."); + delay(500); + ESP.restart(); + } + }, + []() { + HTTPUpload &upload = server.upload(); + if (upload.status == UPLOAD_FILE_START) { + Serial.setDebugOutput(true); + authenticated = server.authenticate(authUser, authPass); + if (!authenticated) { + Serial.println("Authentication fail!"); + return; + } + String origin = server.header(String(csrfHeaders[0])); + String host = server.header(String(csrfHeaders[1])); + String expectedOrigin = String("http://") + host; + if (origin != expectedOrigin) { + Serial.printf("Wrong origin received! Expected: %s, Received: %s\n", expectedOrigin.c_str(), origin.c_str()); + authenticated = false; + return; + } + + Serial.printf("Update: %s\n", upload.filename.c_str()); + if (!Update.begin()) { //start with max available size + Update.printError(Serial); + } + } else if (authenticated && upload.status == UPLOAD_FILE_WRITE) { + if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) { + Update.printError(Serial); + } + } else if (authenticated && upload.status == UPLOAD_FILE_END) { + if (Update.end(true)) { //true to set the size to the current progress + Serial.printf("Update Success: %zu\nRebooting...\n", upload.totalSize); + } else { + Update.printError(Serial); + } + Serial.setDebugOutput(false); + } else if (authenticated) { + Serial.printf("Update Failed Unexpectedly (likely broken connection): status=%d\n", upload.status); + } + } + ); + server.begin(); + MDNS.addService("http", "tcp", 80); + + Serial.printf("Ready! Open http://%s.local in your browser\n", host); + } else { + Serial.println("WiFi Failed"); + } +} + +void loop(void) { + server.handleClient(); + delay(2); //allow the cpu to switch to other tasks +} diff --git a/libraries/WebServer/examples/WebUpdate/ci.yml b/libraries/WebServer/examples/WebUpdate/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WebServer/examples/WebUpdate/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WebServer/keywords.txt b/libraries/WebServer/keywords.txt new file mode 100644 index 0000000..df20ff7 --- /dev/null +++ b/libraries/WebServer/keywords.txt @@ -0,0 +1,38 @@ +####################################### +# Syntax Coloring Map For Ultrasound +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +WebServer KEYWORD1 +WebServerSecure KEYWORD1 +HTTPMethod KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +handleClient KEYWORD2 +on KEYWORD2 +addHandler KEYWORD2 +uri KEYWORD2 +method KEYWORD2 +client KEYWORD2 +send KEYWORD2 +arg KEYWORD2 +argName KEYWORD2 +args KEYWORD2 +hasArg KEYWORD2 +onNotFound KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +HTTP_GET LITERAL1 +HTTP_POST LITERAL1 +HTTP_ANY LITERAL1 +CONTENT_LENGTH_UNKNOWN LITERAL1 diff --git a/libraries/WebServer/library.properties b/libraries/WebServer/library.properties new file mode 100644 index 0000000..25d4e06 --- /dev/null +++ b/libraries/WebServer/library.properties @@ -0,0 +1,9 @@ +name=WebServer +version=3.3.7 +author=Ivan Grokhotkov +maintainer=Ivan Grokhtkov +sentence=Simple web server library +paragraph=The library supports HTTP GET and POST requests, provides argument parsing, handles one client at a time. +category=Communication +url= +architectures=esp32 diff --git a/libraries/WebServer/src/HTTP_Method.h b/libraries/WebServer/src/HTTP_Method.h new file mode 100644 index 0000000..66d53bf --- /dev/null +++ b/libraries/WebServer/src/HTTP_Method.h @@ -0,0 +1,9 @@ +#ifndef _HTTP_Method_H_ +#define _HTTP_Method_H_ + +#include "http_parser.h" + +typedef enum http_method HTTPMethod; +#define HTTP_ANY (HTTPMethod)(255) + +#endif /* _HTTP_Method_H_ */ diff --git a/libraries/WebServer/src/Middlewares.h b/libraries/WebServer/src/Middlewares.h new file mode 100644 index 0000000..04fab52 --- /dev/null +++ b/libraries/WebServer/src/Middlewares.h @@ -0,0 +1,66 @@ +#ifndef MIDDLEWARES_H +#define MIDDLEWARES_H + +#include +#include + +#include + +// curl-like logging middleware +class LoggingMiddleware : public Middleware { +public: + void setOutput(Print &output); + + bool run(WebServer &server, Middleware::Callback next) override; + +private: + Print *_out = nullptr; +}; + +class CorsMiddleware : public Middleware { +public: + CorsMiddleware &setOrigin(const char *origin); + CorsMiddleware &setMethods(const char *methods); + CorsMiddleware &setHeaders(const char *headers); + CorsMiddleware &setAllowCredentials(bool credentials); + CorsMiddleware &setMaxAge(uint32_t seconds); + + void addCORSHeaders(WebServer &server); + + bool run(WebServer &server, Middleware::Callback next) override; + +private: + String _origin = F("*"); + String _methods = F("*"); + String _headers = F("*"); + bool _credentials = true; + uint32_t _maxAge = 86400; +}; + +class AuthenticationMiddleware : public Middleware { +public: + AuthenticationMiddleware &setUsername(const char *username); + AuthenticationMiddleware &setPassword(const char *password); + AuthenticationMiddleware &setPasswordHash(const char *sha1AsBase64orHex); + AuthenticationMiddleware &setCallback(WebServer::THandlerFunctionAuthCheck fn); + + AuthenticationMiddleware &setRealm(const char *realm); + AuthenticationMiddleware &setAuthMethod(HTTPAuthMethod method); + AuthenticationMiddleware &setAuthFailureMessage(const char *message); + + bool isAllowed(WebServer &server) const; + + bool run(WebServer &server, Middleware::Callback next) override; + +private: + String _username; + String _password; + bool _hash = false; + WebServer::THandlerFunctionAuthCheck _callback; + + const char *_realm = nullptr; + HTTPAuthMethod _method = BASIC_AUTH; + String _authFailMsg; +}; + +#endif diff --git a/libraries/WebServer/src/Parsing.cpp b/libraries/WebServer/src/Parsing.cpp new file mode 100644 index 0000000..df80510 --- /dev/null +++ b/libraries/WebServer/src/Parsing.cpp @@ -0,0 +1,622 @@ +/* + Parsing.cpp - HTTP request parsing. + + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Modified 8 May 2015 by Hristo Gochkov (proper post and file upload handling) +*/ + +#include +#include +#include "NetworkServer.h" +#include "NetworkClient.h" +#include "WebServer.h" +#include "detail/mimetable.h" + +#ifndef WEBSERVER_MAX_POST_ARGS +#define WEBSERVER_MAX_POST_ARGS 32 +#endif + +#define __STR(a) #a +#define _STR(a) __STR(a) +static const char *_http_method_str[] = { +#define XX(num, name, string) _STR(name), + HTTP_METHOD_MAP(XX) +#undef XX +}; + +static const char Content_Type[] PROGMEM = "Content-Type"; +static const char filename[] PROGMEM = "filename"; + +static char *readBytesWithTimeout(NetworkClient &client, size_t maxLength, size_t &dataLength, int timeout_ms) { + char *buf = nullptr; + dataLength = 0; + while (dataLength < maxLength) { + int tries = timeout_ms; + size_t newLength; + while (!(newLength = client.available()) && tries--) { + delay(1); + } + if (!newLength) { + break; + } + if (!buf) { + buf = (char *)malloc(newLength + 1); + if (!buf) { + return nullptr; + } + } else { + char *newBuf = (char *)realloc(buf, dataLength + newLength + 1); + if (!newBuf) { + free(buf); + return nullptr; + } + buf = newBuf; + } + client.readBytes(buf + dataLength, newLength); + dataLength += newLength; + buf[dataLength] = '\0'; + } + return buf; +} + +bool WebServer::_parseRequest(NetworkClient &client) { + // Read the first line of HTTP request + String req = client.readStringUntil('\r'); + client.readStringUntil('\n'); + //reset header value + if (_collectAllHeaders) { + // clear previous headers + collectAllHeaders(); + } else { + // clear previous headers + for (RequestArgument *header = _currentHeaders; header; header = header->next) { + header->value = String(); + } + } + + // First line of HTTP request looks like "GET /path HTTP/1.1" + // Retrieve the "/path" part by finding the spaces + int addr_start = req.indexOf(' '); + int addr_end = req.indexOf(' ', addr_start + 1); + if (addr_start == -1 || addr_end == -1) { + log_e("Invalid request: %s", req.c_str()); + return false; + } + + String methodStr = req.substring(0, addr_start); + String url = req.substring(addr_start + 1, addr_end); + String versionEnd = req.substring(addr_end + 8); + _currentVersion = atoi(versionEnd.c_str()); + String searchStr = ""; + int hasSearch = url.indexOf('?'); + if (hasSearch != -1) { + searchStr = url.substring(hasSearch + 1); + url = url.substring(0, hasSearch); + } + _currentUri = url; + _chunked = false; + _clientContentLength = 0; // not known yet, or invalid + + HTTPMethod method = HTTP_ANY; + size_t num_methods = sizeof(_http_method_str) / sizeof(const char *); + for (size_t i = 0; i < num_methods; i++) { + if (methodStr == _http_method_str[i]) { + method = (HTTPMethod)i; + break; + } + } + if (method == HTTP_ANY) { + log_e("Unknown HTTP Method: %s", methodStr.c_str()); + return false; + } + _currentMethod = method; + + log_v("method: %s url: %s search: %s", methodStr.c_str(), url.c_str(), searchStr.c_str()); + + //attach handler + RequestHandler *handler; + for (handler = _firstHandler; handler; handler = handler->next()) { + if (handler->canHandle(*this, _currentMethod, _currentUri)) { + break; + } + } + _currentHandler = handler; + + String formData; + // below is needed only when POST type request + if (method == HTTP_POST || method == HTTP_PUT || method == HTTP_PATCH || method == HTTP_DELETE) { + String boundaryStr; + String headerName; + String headerValue; + bool isForm = false; + bool isEncoded = false; + //parse headers + while (1) { + req = client.readStringUntil('\r'); + client.readStringUntil('\n'); + if (req == "") { + break; //no moar headers + } + int headerDiv = req.indexOf(':'); + if (headerDiv == -1) { + break; + } + headerName = req.substring(0, headerDiv); + headerValue = req.substring(headerDiv + 1); + headerValue.trim(); + _collectHeader(headerName.c_str(), headerValue.c_str()); + + if (headerName.equalsIgnoreCase(FPSTR(Content_Type))) { + using namespace mime; + if (headerValue.startsWith(FPSTR(mimeTable[txt].mimeType))) { + isForm = false; + } else if (headerValue.startsWith(F("application/x-www-form-urlencoded"))) { + isForm = false; + isEncoded = true; + } else if (headerValue.startsWith(F("multipart/"))) { + boundaryStr = headerValue.substring(headerValue.indexOf('=') + 1); + boundaryStr.replace("\"", ""); + isForm = true; + } + } else if (headerName.equalsIgnoreCase(F("Content-Length"))) { + _clientContentLength = headerValue.toInt(); + } else if (headerName.equalsIgnoreCase(F("Host"))) { + _hostHeader = headerValue; + } + } + + if (!isForm && _currentHandler && _currentHandler->canRaw(*this, _currentUri)) { + log_v("Parse raw"); + _currentRaw.reset(new HTTPRaw()); + _currentRaw->status = RAW_START; + _currentRaw->totalSize = 0; + _currentRaw->currentSize = 0; + log_v("Start Raw"); + _currentHandler->raw(*this, _currentUri, *_currentRaw); + _currentRaw->status = RAW_WRITE; + + while (_currentRaw->totalSize < (size_t)_clientContentLength) { + size_t read_len = std::min((size_t)_clientContentLength - _currentRaw->totalSize, (size_t)HTTP_RAW_BUFLEN); + _currentRaw->currentSize = client.readBytes(_currentRaw->buf, read_len); + _currentRaw->totalSize += _currentRaw->currentSize; + if (_currentRaw->currentSize == 0) { + _currentRaw->status = RAW_ABORTED; + _currentHandler->raw(*this, _currentUri, *_currentRaw); + return false; + } + _currentHandler->raw(*this, _currentUri, *_currentRaw); + } + _currentRaw->status = RAW_END; + _currentHandler->raw(*this, _currentUri, *_currentRaw); + log_v("Finish Raw"); + } else if (!isForm) { + size_t plainLength; + char *plainBuf = readBytesWithTimeout(client, _clientContentLength, plainLength, HTTP_MAX_POST_WAIT); + if (plainLength < (size_t)_clientContentLength) { + free(plainBuf); + return false; + } + if (_clientContentLength > 0) { + if (isEncoded) { + //url encoded form + if (searchStr != "") { + searchStr += '&'; + } + searchStr += plainBuf; + } + _parseArguments(searchStr); + if (!isEncoded) { + //plain post json or other data + RequestArgument &arg = _currentArgs[_currentArgCount++]; + arg.key = F("plain"); + arg.value = String(plainBuf); + } + + log_v("Plain: %s", plainBuf); + free(plainBuf); + } else { + // No content - but we can still have arguments in the URL. + _parseArguments(searchStr); + } + } else { + // it IS a form + _parseArguments(searchStr); + if (!_parseForm(client, boundaryStr, _clientContentLength)) { + return false; + } + } + } else { + String headerName; + String headerValue; + //parse headers + while (1) { + req = client.readStringUntil('\r'); + client.readStringUntil('\n'); + if (req == "") { + break; //no moar headers + } + int headerDiv = req.indexOf(':'); + if (headerDiv == -1) { + break; + } + headerName = req.substring(0, headerDiv); + headerValue = req.substring(headerDiv + 2); + _collectHeader(headerName.c_str(), headerValue.c_str()); + + if (headerName.equalsIgnoreCase("Host")) { + _hostHeader = headerValue; + } + } + _parseArguments(searchStr); + } + client.clear(); + + log_v("Request: %s", url.c_str()); + log_v(" Arguments: %s", searchStr.c_str()); + + return true; +} + +bool WebServer::_collectHeader(const char *headerName, const char *headerValue) { + RequestArgument *last = nullptr; + for (RequestArgument *header = _currentHeaders; header; header = header->next) { + if (header->next == nullptr) { + last = header; + } + if (header->key.equalsIgnoreCase(headerName)) { + header->value = headerValue; + log_v("header collected: %s: %s", headerName, headerValue); + return true; + } + } + assert(last); + if (_collectAllHeaders) { + last->next = new RequestArgument(); + last->next->key = headerName; + last->next->value = headerValue; + _headerKeysCount++; + log_v("header collected: %s: %s", headerName, headerValue); + return true; + } + + log_v("header skipped: %s: %s", headerName, headerValue); + + return false; +} + +void WebServer::_parseArguments(const String &data) { + log_v("args: %s", data.c_str()); + if (_currentArgs) { + delete[] _currentArgs; + } + _currentArgs = 0; + if (data.length() == 0) { + _currentArgCount = 0; + _currentArgs = new RequestArgument[1]; + return; + } + _currentArgCount = 1; + + for (int i = 0; i < (int)data.length();) { + i = data.indexOf('&', i); + if (i == -1) { + break; + } + ++i; + ++_currentArgCount; + } + log_v("args count: %d", _currentArgCount); + + _currentArgs = new RequestArgument[_currentArgCount + 1]; + int pos = 0; + int iarg; + for (iarg = 0; iarg < _currentArgCount;) { + int equal_sign_index = data.indexOf('=', pos); + int next_arg_index = data.indexOf('&', pos); + log_v("pos %d =@%d &@%d", pos, equal_sign_index, next_arg_index); + if ((equal_sign_index == -1) || ((equal_sign_index > next_arg_index) && (next_arg_index != -1))) { + log_e("arg missing value: %d", iarg); + if (next_arg_index == -1) { + break; + } + pos = next_arg_index + 1; + continue; + } + RequestArgument &arg = _currentArgs[iarg]; + arg.key = urlDecode(data.substring(pos, equal_sign_index)); + arg.value = urlDecode(data.substring(equal_sign_index + 1, next_arg_index)); + log_v("arg %d key: %s value: %s", iarg, arg.key.c_str(), arg.value.c_str()); + ++iarg; + if (next_arg_index == -1) { + break; + } + pos = next_arg_index + 1; + } + _currentArgCount = iarg; + log_v("args count: %d", _currentArgCount); +} + +void WebServer::_uploadWriteByte(uint8_t b) { + if (_currentUpload->currentSize == HTTP_UPLOAD_BUFLEN) { + if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) { + _currentHandler->upload(*this, _currentUri, *_currentUpload); + } + _currentUpload->totalSize += _currentUpload->currentSize; + _currentUpload->currentSize = 0; + } + _currentUpload->buf[_currentUpload->currentSize++] = b; +} + +int WebServer::_uploadReadByte(NetworkClient &client) { + int res = client.read(); + + if (res < 0) { + // keep trying until you either read a valid byte or timeout + const unsigned long startMillis = millis(); + const long timeoutIntervalMillis = client.getTimeout(); + bool timedOut = false; + for (;;) { + if (!client.connected()) { + return -1; + } + // loosely modeled after blinkWithoutDelay pattern + while (!timedOut && !client.available() && client.connected()) { + delay(2); + timedOut = (millis() - startMillis) >= timeoutIntervalMillis; + } + + res = client.read(); + if (res >= 0) { + return res; // exit on a valid read + } + // NOTE: it is possible to get here and have all of the following + // assertions hold true + // + // -- client.available() > 0 + // -- client.connected == true + // -- res == -1 + // + // a simple retry strategy overcomes this which is to say the + // assertion is not permanent, but the reason that this works + // is elusive, and possibly indicative of a more subtle underlying + // issue + + timedOut = (millis() - startMillis) >= timeoutIntervalMillis; + if (timedOut) { + return res; // exit on a timeout + } + } + } + + return res; +} + +bool WebServer::_parseForm(NetworkClient &client, const String &boundary, uint32_t len) { + (void)len; + log_v("Parse Form: Boundary: %s Length: %u", boundary.c_str(), len); + String line; + int retry = 0; + do { + line = client.readStringUntil('\r'); + ++retry; + } while (line.length() == 0 && retry < 3); + + client.readStringUntil('\n'); + //start reading the form + if (line == ("--" + boundary)) { + if (_postArgs) { + delete[] _postArgs; + } + _postArgs = new RequestArgument[WEBSERVER_MAX_POST_ARGS]; + _postArgsLen = 0; + while (1) { + String argName; + String argValue; + String argType; + String argFilename; + bool argIsFile = false; + + line = client.readStringUntil('\r'); + client.readStringUntil('\n'); + if (line.length() > (size_t)19 && line.substring(0, 19).equalsIgnoreCase(F("Content-Disposition"))) { + int nameStart = line.indexOf('='); + if (nameStart != -1) { + argName = line.substring(nameStart + 2); + nameStart = argName.indexOf('='); + if (nameStart == -1) { + argName = argName.substring(0, argName.length() - 1); + } else { + argFilename = argName.substring(nameStart + 2, argName.length() - 1); + argName = argName.substring(0, argName.indexOf('"')); + argIsFile = true; + log_v("PostArg FileName: %s", argFilename.c_str()); + //use GET to set the filename if uploading using blob + if (argFilename == F("blob") && hasArg(FPSTR(filename))) { + argFilename = arg(FPSTR(filename)); + } + } + log_v("PostArg Name: %s", argName.c_str()); + using namespace mime; + argType = FPSTR(mimeTable[txt].mimeType); + line = client.readStringUntil('\r'); + client.readStringUntil('\n'); + while (line.length() > 0) { + if (line.length() > (size_t)12 && line.substring(0, 12).equalsIgnoreCase(FPSTR(Content_Type))) { + argType = line.substring(line.indexOf(':') + 2); + } + //skip over any other headers + line = client.readStringUntil('\r'); + client.readStringUntil('\n'); + } + log_v("PostArg Type: %s", argType.c_str()); + if (!argIsFile) { + while (1) { + line = client.readStringUntil('\r'); + client.readStringUntil('\n'); + if (line.startsWith("--" + boundary)) { + break; + } + if (argValue.length() > (size_t)0) { + argValue += "\n"; + } + argValue += line; + } + log_v("PostArg Value: %s", argValue.c_str()); + + RequestArgument &arg = _postArgs[_postArgsLen++]; + arg.key = argName; + arg.value = argValue; + + if (line == ("--" + boundary + "--")) { + log_v("Done Parsing POST"); + break; + } else if (_postArgsLen >= WEBSERVER_MAX_POST_ARGS) { + log_e("Too many PostArgs (max: %d) in request.", WEBSERVER_MAX_POST_ARGS); + return false; + } + } else { + _currentUpload.reset(new HTTPUpload()); + _currentUpload->status = UPLOAD_FILE_START; + _currentUpload->name = argName; + _currentUpload->filename = argFilename; + _currentUpload->type = argType; + _currentUpload->totalSize = 0; + _currentUpload->currentSize = 0; + log_v("Start File: %s Type: %s", _currentUpload->filename.c_str(), _currentUpload->type.c_str()); + if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) { + _currentHandler->upload(*this, _currentUri, *_currentUpload); + } + _currentUpload->status = UPLOAD_FILE_WRITE; + + int fastBoundaryLen = 4 /* \r\n-- */ + boundary.length() + 1 /* \0 */; + char fastBoundary[fastBoundaryLen]; + snprintf(fastBoundary, fastBoundaryLen, "\r\n--%s", boundary.c_str()); + int boundaryPtr = 0; + while (true) { + int ret = _uploadReadByte(client); + if (ret < 0) { + // Unexpected, we should have had data available per above + return _parseFormUploadAborted(); + } + char in = (char)ret; + if (in == fastBoundary[boundaryPtr]) { + // The input matched the current expected character, advance and possibly exit this file + boundaryPtr++; + if (boundaryPtr == fastBoundaryLen - 1) { + // We read the whole boundary line, we're done here! + break; + } + } else { + // The char doesn't match what we want, so dump whatever matches we had, the read in char, and reset ptr to start + for (int i = 0; i < boundaryPtr; i++) { + _uploadWriteByte(fastBoundary[i]); + } + if (in == fastBoundary[0]) { + // This could be the start of the real end, mark it so and don't emit/skip it + boundaryPtr = 1; + } else { + // Not the 1st char of our pattern, so emit and ignore + _uploadWriteByte(in); + boundaryPtr = 0; + } + } + } + // Found the boundary string, finish processing this file upload + if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) { + _currentHandler->upload(*this, _currentUri, *_currentUpload); + } + _currentUpload->totalSize += _currentUpload->currentSize; + _currentUpload->status = UPLOAD_FILE_END; + if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) { + _currentHandler->upload(*this, _currentUri, *_currentUpload); + } + log_v("End File: %s Type: %s Size: %d", _currentUpload->filename.c_str(), _currentUpload->type.c_str(), (int)_currentUpload->totalSize); + if (!client.connected()) { + return _parseFormUploadAborted(); + } + line = client.readStringUntil('\r'); + client.readStringUntil('\n'); + if (line == "--") { // extra two dashes mean we reached the end of all form fields + log_v("Done Parsing POST"); + break; + } + continue; + } + } + } + } + + int iarg; + int totalArgs = ((WEBSERVER_MAX_POST_ARGS - _postArgsLen) < _currentArgCount) ? (WEBSERVER_MAX_POST_ARGS - _postArgsLen) : _currentArgCount; + for (iarg = 0; iarg < totalArgs; iarg++) { + RequestArgument &arg = _postArgs[_postArgsLen++]; + arg.key = _currentArgs[iarg].key; + arg.value = _currentArgs[iarg].value; + } + if (_currentArgs) { + delete[] _currentArgs; + } + _currentArgs = new RequestArgument[_postArgsLen]; + for (iarg = 0; iarg < _postArgsLen; iarg++) { + RequestArgument &arg = _currentArgs[iarg]; + arg.key = _postArgs[iarg].key; + arg.value = _postArgs[iarg].value; + } + _currentArgCount = iarg; + if (_postArgs) { + delete[] _postArgs; + _postArgs = nullptr; + _postArgsLen = 0; + } + return true; + } + log_e("Error: line: %s", line.c_str()); + return false; +} + +String WebServer::urlDecode(const String &text) { + String decoded = ""; + char temp[] = "0x00"; + unsigned int len = text.length(); + unsigned int i = 0; + while (i < len) { + char decodedChar; + char encodedChar = text.charAt(i++); + if ((encodedChar == '%') && (i + 1 < len)) { + temp[2] = text.charAt(i++); + temp[3] = text.charAt(i++); + + decodedChar = strtol(temp, NULL, 16); + } else { + if (encodedChar == '+') { + decodedChar = ' '; + } else { + decodedChar = encodedChar; // normal ascii char + } + } + decoded += decodedChar; + } + return decoded; +} + +bool WebServer::_parseFormUploadAborted() { + _currentUpload->status = UPLOAD_FILE_ABORTED; + if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) { + _currentHandler->upload(*this, _currentUri, *_currentUpload); + } + return false; +} diff --git a/libraries/WebServer/src/Uri.h b/libraries/WebServer/src/Uri.h new file mode 100644 index 0000000..34ec756 --- /dev/null +++ b/libraries/WebServer/src/Uri.h @@ -0,0 +1,29 @@ +#ifndef URI_H +#define URI_H + +#include +#include + +class Uri { + +protected: + const String _uri; + +public: + Uri(const char *uri) : _uri(uri) {} + Uri(const String &uri) : _uri(uri) {} + Uri(const __FlashStringHelper *uri) : _uri((const char *)uri) {} + virtual ~Uri() {} + + virtual Uri *clone() const { + return new Uri(_uri); + }; + + virtual void initPathArgs(__attribute__((unused)) std::vector &pathArgs) {} + + virtual bool canHandle(const String &requestUri, __attribute__((unused)) std::vector &pathArgs) { + return _uri == requestUri; + } +}; + +#endif diff --git a/libraries/WebServer/src/WebServer.cpp b/libraries/WebServer/src/WebServer.cpp new file mode 100644 index 0000000..98ec929 --- /dev/null +++ b/libraries/WebServer/src/WebServer.cpp @@ -0,0 +1,1072 @@ +/* + WebServer.cpp - Dead simple web-server. + Supports only one simultaneous client, knows how to handle GET and POST. + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Modified 8 May 2015 by Hristo Gochkov (proper post and file upload handling) +*/ + +#include +#include +#include +#include +#include "esp_random.h" +#include "NetworkServer.h" +#include "NetworkClient.h" +#include "WebServer.h" +#include "FS.h" +#include "detail/RequestHandlersImpl.h" +#include "MD5Builder.h" +#include "SHA1Builder.h" +#include "base64.h" + +static const char AUTHORIZATION_HEADER[] = "Authorization"; +static const char qop_auth[] PROGMEM = "qop=auth"; +static const char qop_auth_quoted[] PROGMEM = "qop=\"auth\""; +static const char WWW_Authenticate[] = "WWW-Authenticate"; +static const char Content_Length[] = "Content-Length"; +static const char ETAG_HEADER[] = "If-None-Match"; + +WebServer::WebServer(IPAddress addr, int port) : _server(addr, port) { + log_v("WebServer::Webserver(addr=%s, port=%d)", addr.toString().c_str(), port); +} + +WebServer::WebServer(int port) : _server(port) { + log_v("WebServer::Webserver(port=%d)", port); +} + +WebServer::~WebServer() { + _server.close(); + + _clearRequestHeaders(); + _clearResponseHeaders(); + delete _chain; + + RequestHandler *handler = _firstHandler; + while (handler) { + RequestHandler *next = handler->next(); + delete handler; + handler = next; + } + _firstHandler = nullptr; +} + +void WebServer::begin() { + close(); + _server.begin(); + _server.setNoDelay(true); +} + +void WebServer::begin(uint16_t port) { + close(); + _server.begin(port); + _server.setNoDelay(true); +} + +String WebServer::_extractParam(String &authReq, const String ¶m, const char delimit) { + int _begin = authReq.indexOf(param); + if (_begin == -1) { + return ""; + } + return authReq.substring(_begin + param.length(), authReq.indexOf(delimit, _begin + param.length())); +} + +static String md5str(String &in) { + MD5Builder md5 = MD5Builder(); + md5.begin(); + md5.add(in); + md5.calculate(); + return md5.toString(); +} + +bool WebServer::authenticateBasicSHA1(const char *_username, const char *_sha1Base64orHex) { + return WebServer::authenticate([_username, _sha1Base64orHex](HTTPAuthMethod mode, String username, String params[]) -> String * { + // rather than work on a password to compare with; we take the sha1 of the + // password received over the wire and compare that to the base64 encoded + // sha1 passed as _sha1base64. That way there is no need to have a + // plaintext password in the code/binary (though note that SHA1 is well + // past its retirement age). When that matches - we `cheat' by returning + // the password we got in the first place; so the normal BasicAuth + // can be completed. Note that this cannot work for a digest auth - + // as there the password in the clear is part of the calculation. + + if (params == nullptr) { + log_e("Something went wrong. params is NULL"); + return NULL; + } + + uint8_t sha1[20]; + char sha1calc[48]; // large enough for base64 and Hex representation + String ret; + SHA1Builder sha_builder; + base64 b64; + + log_v("Trying to authenticate user %s using SHA1.", username.c_str()); + sha_builder.begin(); + sha_builder.add((uint8_t *)params[0].c_str(), params[0].length()); + sha_builder.calculate(); + sha_builder.getBytes(sha1); + + // we can either decode _sha1base64orHex and then compare the 20 bytes; + // or encode the sha we calculated. We pick the latter as encoding of a + // fixed array of 20 bytes is safer than operating on something external. + if (strlen(_sha1Base64orHex) == 20 * 2) { // 2 chars per byte + sha_builder.bytes2hex(sha1calc, sizeof(sha1calc), sha1, sizeof(sha1)); + log_v("Calculated SHA1 in hex: %s", sha1calc); + } else { + ret = b64.encode(sha1, sizeof(sha1)); + ret.toCharArray(sha1calc, sizeof(sha1calc)); + log_v("Calculated SHA1 in base64: %s", sha1calc); + } + + return ((username.equalsConstantTime(_username)) && (String((char *)sha1calc).equalsConstantTime(_sha1Base64orHex)) + && (mode == BASIC_AUTH) /* to keep things somewhat time constant. */ + ) + ? new String(params[0]) + : NULL; + }); +} + +bool WebServer::authenticate(const char *_username, const char *_password) { + return WebServer::authenticate([_username, _password](HTTPAuthMethod mode, String username, String params[]) -> String * { + (void)mode; + (void)params; + return username.equalsConstantTime(_username) ? new String(_password) : NULL; + }); +} + +bool WebServer::authenticate(THandlerFunctionAuthCheck fn) { + if (!hasHeader(FPSTR(AUTHORIZATION_HEADER))) { + return false; + } + + String authReq = header(FPSTR(AUTHORIZATION_HEADER)); + if (authReq.startsWith(AuthTypeBasic)) { + log_v("Trying to authenticate using Basic Auth"); + bool ret = false; + + authReq = authReq.substring(6); // length of AuthTypeBasic including the space at the end. + authReq.trim(); + + /* base64 encoded string is always shorter (or equal) in length */ + char *decoded = (authReq.length() < HTTP_MAX_BASIC_AUTH_LEN) ? new char[authReq.length()] : NULL; + if (decoded) { + char *p; + if (base64_decode_chars(authReq.c_str(), authReq.length(), decoded) && (p = index(decoded, ':')) && p) { + authReq = ""; + /* Note: rfc7617 guarantees that there will not be an escaped colon in the username itself. + * Note: base64_decode_chars() guarantees a terminating \0 + */ + *p = '\0'; + char *_username = decoded, *_password = p + 1; + String params[] = {_password, _srealm}; + String *password = fn(BASIC_AUTH, _username, params); + + if (password) { + ret = password->equalsConstantTime(_password); + // we're more concerned about the password; as the attacker already + // knows the _pasword. Arduino's string handling is simple; it reallocs + // even when smaller; so a memset is enough (no capacity/size). + memset((void *)password->c_str(), 0, password->length()); + delete password; + } + } + delete[] decoded; + } + authReq = ""; + log_v("Authentication %s", ret ? "Success" : "Failed"); + return ret; + } else if (authReq.startsWith(AuthTypeDigest)) { + log_v("Trying to authenticate using Digest Auth"); + authReq = authReq.substring(7); + log_v("%s", authReq.c_str()); + + // extracting required parameters for RFC 2069 simpler Digest + String _username = _extractParam(authReq, F("username=\""), '\"'); + String _realm = _extractParam(authReq, F("realm=\""), '\"'); + String _uri = _extractParam(authReq, F("uri=\""), '\"'); + if (!_username.length()) { + goto exf; + } + + String params[] = {_realm, _uri}; + String *password = fn(DIGEST_AUTH, _username, params); + if (!password) { + goto exf; + } + + String _H1 = md5str(String(_username) + ':' + _realm + ':' + *password); + // we're extra concerned; as digest request us to know the password + // in the clear. + memset((void *)password->c_str(), 0, password->length()); + delete password; + _username = ""; + + String _nonce = _extractParam(authReq, F("nonce=\""), '\"'); + String _response = _extractParam(authReq, F("response=\""), '\"'); + String _opaque = _extractParam(authReq, F("opaque=\""), '\"'); + + if ((!_realm.length()) || (!_nonce.length()) || (!_uri.length()) || (!_response.length()) || (!_opaque.length())) { + goto exf; + } + + if ((_opaque != _sopaque) || (_nonce != _snonce) || (_realm != _srealm)) { + goto exf; + } + + // parameters for the RFC 2617 newer Digest + String _nc, _cnonce; + if (authReq.indexOf(FPSTR(qop_auth)) != -1 || authReq.indexOf(FPSTR(qop_auth_quoted)) != -1) { + _nc = _extractParam(authReq, F("nc="), ','); + _cnonce = _extractParam(authReq, F("cnonce=\""), '\"'); + } + + log_v("Hash of user:realm:pass=%s", _H1.c_str()); + String _H2 = ""; + if (_currentMethod == HTTP_GET) { + _H2 = md5str(String(F("GET:")) + _uri); + } else if (_currentMethod == HTTP_POST) { + _H2 = md5str(String(F("POST:")) + _uri); + } else if (_currentMethod == HTTP_PUT) { + _H2 = md5str(String(F("PUT:")) + _uri); + } else if (_currentMethod == HTTP_DELETE) { + _H2 = md5str(String(F("DELETE:")) + _uri); + } else { + _H2 = md5str(String(F("GET:")) + _uri); + } + log_v("Hash of GET:uri=%s", _H2.c_str()); + String _responsecheck = ""; + if (authReq.indexOf(FPSTR(qop_auth)) != -1 || authReq.indexOf(FPSTR(qop_auth_quoted)) != -1) { + _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _nc + ':' + _cnonce + F(":auth:") + _H2); + } else { + _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _H2); + } + authReq = ""; + + log_v("The Proper response=%s", _responsecheck.c_str()); + bool ret = _response == _responsecheck; + log_v("Authentication %s", ret ? "Success" : "Failed"); + return ret; + } else if (authReq.length()) { + // OTHER_AUTH + log_v("Trying to authenticate using Other Auth, authReq=%s", authReq.c_str()); + String *ret = fn(OTHER_AUTH, authReq, {}); + if (ret) { + log_v("Authentication Success"); + delete ret; + return true; + } + } +exf: + authReq = ""; + log_v("Authentication Failed"); + return false; +} + +String WebServer::_getRandomHexString() { + char buffer[33]; // buffer to hold 32 Hex Digit + /0 + int i; + for (i = 0; i < 4; i++) { + sprintf(buffer + (i * 8), "%08lx", esp_random()); + } + return String(buffer); +} + +void WebServer::requestAuthentication(HTTPAuthMethod mode, const char *realm, const String &authFailMsg) { + if (realm == NULL) { + _srealm = String(F("Login Required")); + } else { + _srealm = String(realm); + } + if (mode == BASIC_AUTH) { + sendHeader(String(FPSTR(WWW_Authenticate)), AuthTypeBasic + String(F(" realm=\"")) + _srealm + String(F("\""))); + } else { + _snonce = _getRandomHexString(); + _sopaque = _getRandomHexString(); + sendHeader( + String(FPSTR(WWW_Authenticate)), AuthTypeDigest + String(F(" realm=\"")) + _srealm + String(F("\", qop=\"auth\", nonce=\"")) + _snonce + + String(F("\", opaque=\"")) + _sopaque + String(F("\"")) + ); + } + using namespace mime; + send(401, String(FPSTR(mimeTable[html].mimeType)), authFailMsg); +} + +RequestHandler &WebServer::on(const Uri &uri, WebServer::THandlerFunction handler) { + return on(uri, HTTP_ANY, handler); +} + +RequestHandler &WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn) { + return on(uri, method, fn, _fileUploadHandler); +} + +RequestHandler &WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn) { + FunctionRequestHandler *handler = new FunctionRequestHandler(fn, ufn, uri, method); + _addRequestHandler(handler); + return *handler; +} + +bool WebServer::removeRoute(const char *uri) { + return removeRoute(String(uri), HTTP_ANY); +} + +bool WebServer::removeRoute(const char *uri, HTTPMethod method) { + return removeRoute(String(uri), method); +} + +bool WebServer::removeRoute(const String &uri) { + return removeRoute(uri, HTTP_ANY); +} + +bool WebServer::removeRoute(const String &uri, HTTPMethod method) { + bool anyHandlerRemoved = false; + RequestHandler *handler = _firstHandler; + RequestHandler *previousHandler = nullptr; + + while (handler) { + if (handler->canHandle(method, uri)) { + if (_removeRequestHandler(handler)) { + anyHandlerRemoved = true; + // Move to the next handler + if (previousHandler) { + handler = previousHandler->next(); + } else { + handler = _firstHandler; + } + continue; + } + } + previousHandler = handler; + handler = handler->next(); + } + + return anyHandlerRemoved; +} + +void WebServer::addHandler(RequestHandler *handler) { + _addRequestHandler(handler); +} + +bool WebServer::removeHandler(RequestHandler *handler) { + return _removeRequestHandler(handler); +} + +void WebServer::_addRequestHandler(RequestHandler *handler) { + if (!_lastHandler) { + _firstHandler = handler; + _lastHandler = handler; + } else { + _lastHandler->next(handler); + _lastHandler = handler; + } +} + +bool WebServer::_removeRequestHandler(RequestHandler *handler) { + RequestHandler *current = _firstHandler; + RequestHandler *previous = nullptr; + + while (current != nullptr) { + if (current == handler) { + if (previous == nullptr) { + _firstHandler = current->next(); + } else { + previous->next(current->next()); + } + + if (current == _lastHandler) { + _lastHandler = previous; + } + + // Delete 'matching' handler + delete current; + return true; + } + previous = current; + current = current->next(); + } + return false; +} + +void WebServer::serveStatic(const char *uri, FS &fs, const char *path, const char *cache_header) { + _addRequestHandler(new StaticRequestHandler(fs, path, uri, cache_header)); +} + +void WebServer::handleClient() { + if (_currentStatus == HC_NONE) { + _currentClient = _server.accept(); + if (!_currentClient) { + if (_nullDelay) { + delay(1); + } + return; + } + + log_v("New client: client.localIP()=%s", _currentClient.localIP().toString().c_str()); + + _currentStatus = HC_WAIT_READ; + _statusChange = millis(); + } + + bool keepCurrentClient = false; + bool callYield = false; + + if (_currentClient.connected()) { + switch (_currentStatus) { + case HC_NONE: + // No-op to avoid C++ compiler warning + break; + case HC_WAIT_READ: + // Wait for data from client to become available + if (_currentClient.available()) { + _currentClient.setTimeout(HTTP_MAX_SEND_WAIT); /* / 1000 removed, WifiClient setTimeout changed to ms */ + if (_parseRequest(_currentClient)) { + _contentLength = CONTENT_LENGTH_NOT_SET; + _responseCode = 0; + _clearResponseHeaders(); + + // Run server-level middlewares + if (_chain) { + _chain->runChain(*this, [this]() { + return _handleRequest(); + }); + } else { + _handleRequest(); + } + + if (_currentClient.isSSE()) { + _currentStatus = HC_WAIT_CLOSE; + _statusChange = millis(); + keepCurrentClient = true; + } + // Fix for issue with Chrome based browsers: https://github.com/espressif/arduino-esp32/issues/3652 + // if (_currentClient.connected()) { + // _currentStatus = HC_WAIT_CLOSE; + // _statusChange = millis(); + // keepCurrentClient = true; + // } + } + } else { // !_currentClient.available() + if (millis() - _statusChange <= HTTP_MAX_DATA_WAIT) { + keepCurrentClient = true; + } + callYield = true; + } + break; + case HC_WAIT_CLOSE: + if (_currentClient.isSSE()) { + // Never close connection + _statusChange = millis(); + } + // Wait for client to close the connection + if (millis() - _statusChange <= HTTP_MAX_CLOSE_WAIT) { + keepCurrentClient = true; + callYield = true; + } + } + } + + if (!keepCurrentClient) { + _currentClient = NetworkClient(); + _currentStatus = HC_NONE; + _currentUpload.reset(); + _currentRaw.reset(); + } + + if (callYield) { + yield(); + } +} + +void WebServer::close() { + _server.close(); + _currentStatus = HC_NONE; + if (!_headerKeysCount) { + collectHeaders(0, 0); + } +} + +void WebServer::stop() { + close(); +} + +void WebServer::sendHeader(const String &name, const String &value, bool first) { + if (name.indexOf('\r') != -1 || name.indexOf('\n') != -1) { + log_e("Invalid character in HTTP header name"); + return; + } + + if (value.indexOf('\r') != -1 || value.indexOf('\n') != -1) { + log_e("Invalid character in HTTP header value"); + return; + } + + RequestArgument *header = new RequestArgument(); + header->key = name; + header->value = value; + + if (!_responseHeaders || first) { + header->next = _responseHeaders; + _responseHeaders = header; + } else { + RequestArgument *last = _responseHeaders; + while (last->next) { + last = last->next; + } + last->next = header; + } + + _responseHeaderCount++; +} + +void WebServer::setContentLength(const size_t contentLength) { + _contentLength = contentLength; +} + +void WebServer::enableDelay(boolean value) { + _nullDelay = value; +} + +void WebServer::enableCORS(boolean value) { + _corsEnabled = value; +} + +void WebServer::enableCrossOrigin(boolean value) { + enableCORS(value); +} + +void WebServer::enableETag(bool enable, ETagFunction fn) { + _eTagEnabled = enable; + _eTagFunction = fn; +} + +void WebServer::chunkResponseBegin(const char *contentType) { + if (_chunkedResponseActive) { + log_e("Already in chunked response mode"); + return; + } + + if (strchr(contentType, '\r') || strchr(contentType, '\n')) { + log_e("Invalid character in content type"); + return; + } + + _chunkedResponseActive = true; + _chunkedClient = _currentClient; + + _contentLength = CONTENT_LENGTH_UNKNOWN; + + String header; + _prepareHeader(header, 200, contentType, 0); + _currentClientWrite(header.c_str(), header.length()); + + _chunkedResponseActive = true; + _chunkedClient = _currentClient; +} + +void WebServer::chunkWrite(const char *data, size_t length) { + if (!_chunkedResponseActive) { + log_e("Chunked response has not been started"); + return; + } + + char chunkSize[11]; + snprintf(chunkSize, sizeof(chunkSize), "%zx\r\n", length); + + if (_chunkedClient.write(chunkSize) != strlen(chunkSize)) { + log_e("Failed to write chunk size"); + _chunkedResponseActive = false; + return; + } + + if (_chunkedClient.write((const uint8_t *)data, length) != length) { + log_e("Failed to write chunk data"); + _chunkedResponseActive = false; + return; + } + + if (_chunkedClient.write("\r\n") != 2) { + log_e("Failed to write chunk terminator"); + _chunkedResponseActive = false; + return; + } +} + +void WebServer::chunkResponseEnd() { + if (!_chunkedResponseActive) { + log_e("Chunked response has not been started"); + return; + } + + if (_chunkedClient.write("0\r\n\r\n", 5) != 5) { + log_e("Failed to write terminating chunk"); + } + + _chunkedClient.clear(); + _chunkedResponseActive = false; + _chunked = false; + _chunkedClient = NetworkClient(); + + _clearResponseHeaders(); +} + +void WebServer::_prepareHeader(String &response, int code, const char *content_type, size_t contentLength) { + _responseCode = code; + + response.concat(version()); + response.concat(' '); + response.concat(String(code)); + response.concat(' '); + response.concat(responseCodeToString(code)); + response.concat(F("\r\n")); + + using namespace mime; + if (!content_type) { + content_type = mimeTable[html].mimeType; + } + + sendHeader(String(F("Content-Type")), String(FPSTR(content_type)), true); + if (_contentLength == CONTENT_LENGTH_NOT_SET) { + sendHeader(String(FPSTR(Content_Length)), String(contentLength)); + } else if (_contentLength != CONTENT_LENGTH_UNKNOWN) { + sendHeader(String(FPSTR(Content_Length)), String(_contentLength)); + } else if (_contentLength == CONTENT_LENGTH_UNKNOWN && _currentVersion) { //HTTP/1.1 or above client + //let's do chunked + _chunked = true; + sendHeader(String(F("Accept-Ranges")), String(F("none"))); + sendHeader(String(F("Transfer-Encoding")), String(F("chunked"))); + } + if (_corsEnabled) { + sendHeader(String(FPSTR("Access-Control-Allow-Origin")), String("*")); + sendHeader(String(FPSTR("Access-Control-Allow-Methods")), String("*")); + sendHeader(String(FPSTR("Access-Control-Allow-Headers")), String("*")); + } + sendHeader(String(F("Connection")), String(F("close"))); + + for (RequestArgument *header = _responseHeaders; header; header = header->next) { + response.concat(header->key); + response.concat(F(": ")); + response.concat(header->value); + response.concat(F("\r\n")); + } + + response.concat(F("\r\n")); +} + +void WebServer::send(int code, const char *content_type, const String &content) { + String header; + // Can we assume the following? + //if(code == 200 && content.length() == 0 && _contentLength == CONTENT_LENGTH_NOT_SET) + // _contentLength = CONTENT_LENGTH_UNKNOWN; + _prepareHeader(header, code, content_type, content.length()); + _currentClientWrite(header.c_str(), header.length()); + if (content.length()) { + sendContent(content); + } +} + +void WebServer::send(int code, char *content_type, const String &content) { + send(code, (const char *)content_type, content); +} + +void WebServer::send(int code, const String &content_type, const String &content) { + send(code, (const char *)content_type.c_str(), content); +} + +void WebServer::send(int code, const char *content_type, const char *content) { + const String passStr = (String)content; + if (strlen(content) != passStr.length()) { + log_e("String cast failed. Use send_P for long arrays"); + } + send(code, content_type, passStr); +} + +void WebServer::send_P(int code, PGM_P content_type, PGM_P content) { + size_t contentLength = 0; + + if (content != NULL) { + contentLength = strlen_P(content); + } + + String header; + char type[64]; + memccpy_P((void *)type, (PGM_VOID_P)content_type, 0, sizeof(type)); + _prepareHeader(header, code, (const char *)type, contentLength); + _currentClientWrite(header.c_str(), header.length()); + sendContent_P(content); +} + +void WebServer::send_P(int code, PGM_P content_type, PGM_P content, size_t contentLength) { + String header; + char type[64]; + memccpy_P((void *)type, (PGM_VOID_P)content_type, 0, sizeof(type)); + _prepareHeader(header, code, (const char *)type, contentLength); + sendContent(header); + sendContent_P(content, contentLength); +} + +void WebServer::sendContent(const String &content) { + sendContent(content.c_str(), content.length()); +} + +void WebServer::sendContent(const char *content, size_t contentLength) { + const char *footer = "\r\n"; + if (_chunked) { + char *chunkSize = (char *)malloc(11); + if (chunkSize) { + sprintf(chunkSize, "%x%s", contentLength, footer); + _currentClientWrite(chunkSize, strlen(chunkSize)); + free(chunkSize); + } + } + _currentClientWrite(content, contentLength); + if (_chunked) { + _currentClient.write(footer, 2); + if (contentLength == 0) { + _chunked = false; + } + } +} + +void WebServer::sendContent_P(PGM_P content) { + sendContent_P(content, strlen_P(content)); +} + +void WebServer::sendContent_P(PGM_P content, size_t size) { + const char *footer = "\r\n"; + if (_chunked) { + char *chunkSize = (char *)malloc(11); + if (chunkSize) { + sprintf(chunkSize, "%x%s", size, footer); + _currentClientWrite(chunkSize, strlen(chunkSize)); + free(chunkSize); + } + } + _currentClientWrite_P(content, size); + if (_chunked) { + _currentClient.write(footer, 2); + if (size == 0) { + _chunked = false; + } + } +} + +void WebServer::_streamFileCore(const size_t fileSize, const String &fileName, const String &contentType, const int code) { + using namespace mime; + setContentLength(fileSize); + if (fileName.endsWith(String(FPSTR(mimeTable[gz].endsWith))) && contentType != String(FPSTR(mimeTable[gz].mimeType)) + && contentType != String(FPSTR(mimeTable[none].mimeType))) { + sendHeader(F("Content-Encoding"), F("gzip")); + } + send(code, contentType, ""); +} + +String WebServer::pathArg(unsigned int i) const { + if (_currentHandler != nullptr) { + return _currentHandler->pathArg(i); + } + return ""; +} + +String WebServer::arg(const String &name) const { + for (int j = 0; j < _postArgsLen; ++j) { + if (_postArgs[j].key == name) { + return _postArgs[j].value; + } + } + for (int i = 0; i < _currentArgCount; ++i) { + if (_currentArgs[i].key == name) { + return _currentArgs[i].value; + } + } + return ""; +} + +String WebServer::arg(int i) const { + if (i < _currentArgCount) { + return _currentArgs[i].value; + } + return ""; +} + +String WebServer::argName(int i) const { + if (i < _currentArgCount) { + return _currentArgs[i].key; + } + return ""; +} + +int WebServer::args() const { + return _currentArgCount; +} + +bool WebServer::hasArg(const String &name) const { + for (int j = 0; j < _postArgsLen; ++j) { + if (_postArgs[j].key == name) { + return true; + } + } + for (int i = 0; i < _currentArgCount; ++i) { + if (_currentArgs[i].key == name) { + return true; + } + } + return false; +} + +String WebServer::header(const String &name) const { + for (RequestArgument *current = _currentHeaders; current; current = current->next) { + if (current->key.equalsIgnoreCase(name)) { + return current->value; + } + } + return ""; +} + +void WebServer::collectHeaders(const char *headerKeys[], const size_t headerKeysCount) { + collectAllHeaders(); + _collectAllHeaders = false; + + _headerKeysCount += headerKeysCount; + + RequestArgument *last = _currentHeaders->next; + + for (int i = 2; i < _headerKeysCount; i++) { + last->next = new RequestArgument(); + last->next->key = headerKeys[i - 2]; + last = last->next; + } +} + +String WebServer::header(int i) const { + RequestArgument *current = _currentHeaders; + while (current && i--) { + current = current->next; + } + return current ? current->value : emptyString; +} + +String WebServer::headerName(int i) const { + RequestArgument *current = _currentHeaders; + while (current && i--) { + current = current->next; + } + return current ? current->key : emptyString; +} + +int WebServer::headers() const { + return _headerKeysCount; +} + +bool WebServer::hasHeader(const String &name) const { + return header(name).length() > 0; +} + +String WebServer::hostHeader() const { + return _hostHeader; +} + +void WebServer::onFileUpload(THandlerFunction fn) { + _fileUploadHandler = fn; +} + +void WebServer::onNotFound(THandlerFunction fn) { + _notFoundHandler = fn; +} + +bool WebServer::_handleRequest() { + bool handled = false; + if (_currentHandler) { + handled = _currentHandler->process(*this, _currentMethod, _currentUri); + if (!handled) { + log_e("request handler failed to handle request"); + } + } + // DO NOT LOG if _currentHandler == null !! + // This is is valid use case to handle any other requests + // Also, this is just causing log flooding + if (!handled && _notFoundHandler) { + _notFoundHandler(); + handled = true; + } + if (!handled) { + using namespace mime; + send(404, String(FPSTR(mimeTable[html].mimeType)), String(F("Not found: ")) + _currentUri); + handled = true; + } + if (handled) { + _finalizeResponse(); + } + _currentUri = ""; + return handled; +} + +void WebServer::_finalizeResponse() { + if (_chunked) { + sendContent(""); + } +} + +String WebServer::responseCodeToString(int code) { + switch (code) { + case 100: return F("Continue"); + case 101: return F("Switching Protocols"); + case 200: return F("OK"); + case 201: return F("Created"); + case 202: return F("Accepted"); + case 203: return F("Non-Authoritative Information"); + case 204: return F("No Content"); + case 205: return F("Reset Content"); + case 206: return F("Partial Content"); + case 300: return F("Multiple Choices"); + case 301: return F("Moved Permanently"); + case 302: return F("Found"); + case 303: return F("See Other"); + case 304: return F("Not Modified"); + case 305: return F("Use Proxy"); + case 307: return F("Temporary Redirect"); + case 400: return F("Bad Request"); + case 401: return F("Unauthorized"); + case 402: return F("Payment Required"); + case 403: return F("Forbidden"); + case 404: return F("Not Found"); + case 405: return F("Method Not Allowed"); + case 406: return F("Not Acceptable"); + case 407: return F("Proxy Authentication Required"); + case 408: return F("Request Time-out"); + case 409: return F("Conflict"); + case 410: return F("Gone"); + case 411: return F("Length Required"); + case 412: return F("Precondition Failed"); + case 413: return F("Request Entity Too Large"); + case 414: return F("Request-URI Too Large"); + case 415: return F("Unsupported Media Type"); + case 416: return F("Requested range not satisfiable"); + case 417: return F("Expectation Failed"); + case 500: return F("Internal Server Error"); + case 501: return F("Not Implemented"); + case 502: return F("Bad Gateway"); + case 503: return F("Service Unavailable"); + case 504: return F("Gateway Time-out"); + case 505: return F("HTTP Version not supported"); + default: return F(""); + } +} + +void WebServer::_clearResponseHeaders() { + _responseHeaderCount = 0; + RequestArgument *current = _responseHeaders; + while (current) { + RequestArgument *next = current->next; + delete current; + current = next; + } + _responseHeaders = nullptr; +} + +void WebServer::_clearRequestHeaders() { + _headerKeysCount = 0; + RequestArgument *current = _currentHeaders; + while (current) { + RequestArgument *next = current->next; + delete current; + current = next; + } + _currentHeaders = nullptr; +} + +void WebServer::collectAllHeaders() { + _clearRequestHeaders(); + + _currentHeaders = new RequestArgument(); + _currentHeaders->key = FPSTR(AUTHORIZATION_HEADER); + + _currentHeaders->next = new RequestArgument(); + _currentHeaders->next->key = FPSTR(ETAG_HEADER); + + _headerKeysCount = 2; + _collectAllHeaders = true; +} + +const String &WebServer::responseHeader(String name) const { + for (RequestArgument *current = _responseHeaders; current; current = current->next) { + if (current->key.equalsIgnoreCase(name)) { + return current->value; + } + } + return emptyString; +} + +const String &WebServer::responseHeader(int i) const { + RequestArgument *current = _responseHeaders; + while (current && i--) { + current = current->next; + } + return current ? current->value : emptyString; +} + +const String &WebServer::responseHeaderName(int i) const { + RequestArgument *current = _responseHeaders; + while (current && i--) { + current = current->next; + } + return current ? current->key : emptyString; +} + +bool WebServer::hasResponseHeader(const String &name) const { + return header(name).length() > 0; +} + +int WebServer::clientContentLength() const { + return _clientContentLength; +} + +const String WebServer::version() const { + String v; + v.reserve(8); + v.concat(F("HTTP/1.")); + v.concat(_currentVersion); + return v; +} +int WebServer::responseCode() const { + return _responseCode; +} +int WebServer::responseHeaders() const { + return _responseHeaderCount; +} + +WebServer &WebServer::addMiddleware(Middleware *middleware) { + if (!_chain) { + _chain = new MiddlewareChain(); + } + _chain->addMiddleware(middleware); + return *this; +} + +WebServer &WebServer::addMiddleware(Middleware::Function fn) { + if (!_chain) { + _chain = new MiddlewareChain(); + } + _chain->addMiddleware(fn); + return *this; +} + +WebServer &WebServer::removeMiddleware(Middleware *middleware) { + if (_chain) { + _chain->removeMiddleware(middleware); + } + return *this; +} diff --git a/libraries/WebServer/src/WebServer.h b/libraries/WebServer/src/WebServer.h new file mode 100644 index 0000000..498bcb5 --- /dev/null +++ b/libraries/WebServer/src/WebServer.h @@ -0,0 +1,331 @@ +/* + WebServer.h - Dead simple web-server. + Supports only one simultaneous client, knows how to handle GET and POST. + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + Modified 8 May 2015 by Hristo Gochkov (proper post and file upload handling) +*/ + +#ifndef WEBSERVER_H +#define WEBSERVER_H + +#include +#include +#include "FS.h" +#include "Network.h" +#include "HTTP_Method.h" +#include "Uri.h" + +enum HTTPUploadStatus { + UPLOAD_FILE_START, + UPLOAD_FILE_WRITE, + UPLOAD_FILE_END, + UPLOAD_FILE_ABORTED +}; +enum HTTPRawStatus { + RAW_START, + RAW_WRITE, + RAW_END, + RAW_ABORTED +}; +enum HTTPClientStatus { + HC_NONE, + HC_WAIT_READ, + HC_WAIT_CLOSE +}; +enum HTTPAuthMethod { + BASIC_AUTH, + DIGEST_AUTH, + OTHER_AUTH +}; + +#define HTTP_DOWNLOAD_UNIT_SIZE 1436 + +#ifndef HTTP_UPLOAD_BUFLEN +#define HTTP_UPLOAD_BUFLEN 1436 +#endif + +#ifndef HTTP_RAW_BUFLEN +#define HTTP_RAW_BUFLEN 1436 +#endif + +#define HTTP_MAX_DATA_WAIT 5000 //ms to wait for the client to send the request +#define HTTP_MAX_POST_WAIT 5000 //ms to wait for POST data to arrive +#define HTTP_MAX_SEND_WAIT 5000 //ms to wait for data chunk to be ACKed +#define HTTP_MAX_CLOSE_WAIT 5000 //ms to wait for the client to close the connection +#define HTTP_MAX_BASIC_AUTH_LEN 256 // maximum length of a basic Auth base64 encoded username:password string + +#define CONTENT_LENGTH_UNKNOWN ((size_t) - 1) +#define CONTENT_LENGTH_NOT_SET ((size_t) - 2) + +class WebServer; + +typedef struct { + HTTPUploadStatus status; + String filename; + String name; + String type; + size_t totalSize; // file size + size_t currentSize; // size of data currently in buf + uint8_t buf[HTTP_UPLOAD_BUFLEN]; +} HTTPUpload; + +typedef struct { + HTTPRawStatus status; + size_t totalSize; // content size + size_t currentSize; // size of data currently in buf + uint8_t buf[HTTP_RAW_BUFLEN]; + void *data; // additional data +} HTTPRaw; + +#include "middleware/Middleware.h" +#include "detail/RequestHandler.h" + +namespace fs { +class FS; +} + +class WebServer { +public: + WebServer(IPAddress addr, int port = 80); + WebServer(int port = 80); + virtual ~WebServer(); + + virtual void begin(); + virtual void begin(uint16_t port); + virtual void handleClient(); + + virtual void close(); + void stop(); + + const String AuthTypeDigest = F("Digest"); + const String AuthTypeBasic = F("Basic"); + + void chunkResponseBegin(const char *contentType = "text/plain"); + void chunkWrite(const char *data, size_t length); + void chunkResponseEnd(); + + /* Callbackhandler for authentication. The extra parameters depend on the + * HTTPAuthMethod mode: + * + * BASIC_AUTH enteredUsernameOrReq contains the username entered by the user + * param[0] password entered (in the clear) + * param[1] authentication realm. + * + * To return - the password the user entered password is compared to. Or Null on fail. + * + * DIGEST_AUTH enteredUsernameOrReq contains the username entered by the user + * param[0] autenticaiton realm + * param[1] authentication URI + * + * To return - the password of which the digest will be based on for comparison. Or NULL + * to fail. + * + * OTHER_AUTH enteredUsernameOrReq rest of the auth line. + * params empty array + * + * To return - NULL to fail; or any string. + */ + typedef std::function THandlerFunctionAuthCheck; + + bool authenticate(THandlerFunctionAuthCheck fn); + bool authenticate(const char *username, const char *password); + bool authenticateBasicSHA1(const char *_username, const char *_sha1AsBase64orHex); + + void requestAuthentication(HTTPAuthMethod mode = BASIC_AUTH, const char *realm = NULL, const String &authFailMsg = String("")); + + typedef std::function THandlerFunction; + typedef std::function FilterFunction; + RequestHandler &on(const Uri &uri, THandlerFunction fn); + RequestHandler &on(const Uri &uri, HTTPMethod method, THandlerFunction fn); + RequestHandler &on(const Uri &uri, HTTPMethod method, THandlerFunction fn, THandlerFunction ufn); //ufn handles file uploads + bool removeRoute(const char *uri); + bool removeRoute(const char *uri, HTTPMethod method); + bool removeRoute(const String &uri); + bool removeRoute(const String &uri, HTTPMethod method); + void addHandler(RequestHandler *handler); + bool removeHandler(RequestHandler *handler); + void serveStatic(const char *uri, fs::FS &fs, const char *path, const char *cache_header = NULL); + void onNotFound(THandlerFunction fn); //called when handler is not assigned + void onFileUpload(THandlerFunction ufn); //handle file uploads + + WebServer &addMiddleware(Middleware *middleware); + WebServer &addMiddleware(Middleware::Function fn); + WebServer &removeMiddleware(Middleware *middleware); + + String uri() const { + return _currentUri; + } + HTTPMethod method() const { + return _currentMethod; + } + virtual NetworkClient &client() { + return _currentClient; + } + HTTPUpload &upload() { + return *_currentUpload; + } + HTTPRaw &raw() { + return *_currentRaw; + } + + String pathArg(unsigned int i) const; // get request path argument by number + String arg(const String &name) const; // get request argument value by name + String arg(int i) const; // get request argument value by number + String argName(int i) const; // get request argument name by number + int args() const; // get arguments count + bool hasArg(const String &name) const; // check if argument exists + void collectHeaders(const char *headerKeys[], const size_t headerKeysCount); // set the request headers to collect + void collectAllHeaders(); // collect all request headers + String header(const String &name) const; // get request header value by name + String header(int i) const; // get request header value by number + String headerName(int i) const; // get request header name by number + int headers() const; // get header count + bool hasHeader(const String &name) const; // check if header exists + + int clientContentLength() const; // return "content-length" of incoming HTTP header from "_currentClient" + const String version() const; // get the HTTP version string + String hostHeader() const; // get request host header if available or empty String if not + + int responseCode() const; // get the HTTP response code set + int responseHeaders() const; // get the HTTP response headers count + const String &responseHeader(String name) const; // get the HTTP response header value by name + const String &responseHeader(int i) const; // get the HTTP response header value by number + const String &responseHeaderName(int i) const; // get the HTTP response header name by number + bool hasResponseHeader(const String &name) const; // check if response header exists + + // send response to the client + // code - HTTP response code, can be 200 or 404 + // content_type - HTTP content type, like "text/plain" or "image/png" + // content - actual content body + void send(int code, const char *content_type = NULL, const String &content = String("")); + void send(int code, char *content_type, const String &content); + void send(int code, const String &content_type, const String &content); + void send(int code, const char *content_type, const char *content); + + void send_P(int code, PGM_P content_type, PGM_P content); + void send_P(int code, PGM_P content_type, PGM_P content, size_t contentLength); + + void enableDelay(boolean value); + void enableCORS(boolean value = true); + void enableCrossOrigin(boolean value = true); + typedef std::function ETagFunction; + void enableETag(bool enable, ETagFunction fn = nullptr); + + void setContentLength(const size_t contentLength); + void sendHeader(const String &name, const String &value, bool first = false); + void sendContent(const String &content); + void sendContent(const char *content, size_t contentLength); + void sendContent_P(PGM_P content); + void sendContent_P(PGM_P content, size_t size); + + static String urlDecode(const String &text); + + template size_t streamFile(T &file, const String &contentType, const int code = 200) { + _streamFileCore(file.size(), file.name(), contentType, code); + return _currentClient.write(file); + } + + bool _eTagEnabled = false; + ETagFunction _eTagFunction = nullptr; + + static String responseCodeToString(int code); + +private: + bool _chunkedResponseActive = false; + NetworkClient _chunkedClient; // Store by value, no dangling pointer + +protected: + virtual size_t _currentClientWrite(const char *b, size_t l) { + return _currentClient.write(b, l); + } + virtual size_t _currentClientWrite_P(PGM_P b, size_t l) { + return _currentClient.write_P(b, l); + } + void _addRequestHandler(RequestHandler *handler); + bool _removeRequestHandler(RequestHandler *handler); + bool _handleRequest(); + void _finalizeResponse(); + bool _parseRequest(NetworkClient &client); + void _parseArguments(const String &data); + bool _parseForm(NetworkClient &client, const String &boundary, uint32_t len); + bool _parseFormUploadAborted(); + void _uploadWriteByte(uint8_t b); + int _uploadReadByte(NetworkClient &client); + void _prepareHeader(String &response, int code, const char *content_type, size_t contentLength); + bool _collectHeader(const char *headerName, const char *headerValue); + + void _streamFileCore(const size_t fileSize, const String &fileName, const String &contentType, const int code = 200); + + String _getRandomHexString(); + // for extracting Auth parameters + String _extractParam(String &authReq, const String ¶m, const char delimit = '"'); + + void _clearResponseHeaders(); + void _clearRequestHeaders(); + + struct RequestArgument { + String key; + String value; + RequestArgument *next; + }; + + boolean _corsEnabled = false; + NetworkServer _server; + + NetworkClient _currentClient; + HTTPMethod _currentMethod = HTTP_ANY; + String _currentUri; + uint8_t _currentVersion = 0; + HTTPClientStatus _currentStatus = HC_NONE; + unsigned long _statusChange = 0; + boolean _nullDelay = true; + + RequestHandler *_currentHandler = nullptr; + RequestHandler *_firstHandler = nullptr; + RequestHandler *_lastHandler = nullptr; + THandlerFunction _notFoundHandler = nullptr; + THandlerFunction _fileUploadHandler = nullptr; + + int _currentArgCount = 0; + RequestArgument *_currentArgs = nullptr; + int _postArgsLen = 0; + RequestArgument *_postArgs = nullptr; + + std::unique_ptr _currentUpload; + std::unique_ptr _currentRaw; + + int _headerKeysCount = 0; + RequestArgument *_currentHeaders = nullptr; + size_t _contentLength = 0; + int _clientContentLength = 0; // "Content-Length" from header of incoming POST or GET request + RequestArgument *_responseHeaders = nullptr; + + String _hostHeader; + bool _chunked = false; + + String _snonce; // Store noance and opaque for future comparison + String _sopaque; + String _srealm; // Store the Auth realm between Calls + + int _responseHeaderCount = 0; + int _responseCode = 0; + bool _collectAllHeaders = false; + MiddlewareChain *_chain = nullptr; +}; + +#endif //ESP8266WEBSERVER_H diff --git a/libraries/WebServer/src/detail/RequestHandler.h b/libraries/WebServer/src/detail/RequestHandler.h new file mode 100644 index 0000000..75e11c9 --- /dev/null +++ b/libraries/WebServer/src/detail/RequestHandler.h @@ -0,0 +1,99 @@ +#ifndef REQUESTHANDLER_H +#define REQUESTHANDLER_H + +#include +#include + +class RequestHandler { +public: + virtual ~RequestHandler() { + delete _chain; + } + + /* + note: old handler API for backward compatibility + */ + + virtual bool canHandle(HTTPMethod method, const String &uri) { + (void)method; + (void)uri; + return false; + } + virtual bool canUpload(const String &uri) { + (void)uri; + return false; + } + virtual bool canRaw(const String &uri) { + (void)uri; + return false; + } + + /* + note: new handler API with support for filters etc. + */ + + virtual bool canHandle(WebServer &server, HTTPMethod method, const String &uri) { + (void)server; + (void)method; + (void)uri; + return false; + } + virtual bool canUpload(WebServer &server, const String &uri) { + (void)server; + (void)uri; + return false; + } + virtual bool canRaw(WebServer &server, const String &uri) { + (void)server; + (void)uri; + return false; + } + virtual bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) { + (void)server; + (void)requestMethod; + (void)requestUri; + return false; + } + virtual void upload(WebServer &server, const String &requestUri, HTTPUpload &upload) { + (void)server; + (void)requestUri; + (void)upload; + } + virtual void raw(WebServer &server, const String &requestUri, HTTPRaw &raw) { + (void)server; + (void)requestUri; + (void)raw; + } + + virtual RequestHandler &setFilter(std::function filter) { + (void)filter; + return *this; + } + + RequestHandler *next() { + return _next; + } + void next(RequestHandler *r) { + _next = r; + } + + RequestHandler &addMiddleware(Middleware *middleware); + RequestHandler &addMiddleware(Middleware::Function fn); + RequestHandler &removeMiddleware(Middleware *middleware); + bool process(WebServer &server, HTTPMethod requestMethod, String requestUri); + +private: + RequestHandler *_next = nullptr; + MiddlewareChain *_chain = nullptr; + +protected: + std::vector pathArgs; + +public: + const String &pathArg(unsigned int i) { + assert(i < pathArgs.size()); + return pathArgs[i]; + } +}; + +#endif //REQUESTHANDLER_H diff --git a/libraries/WebServer/src/detail/RequestHandlersImpl.h b/libraries/WebServer/src/detail/RequestHandlersImpl.h new file mode 100644 index 0000000..b77ebd0 --- /dev/null +++ b/libraries/WebServer/src/detail/RequestHandlersImpl.h @@ -0,0 +1,300 @@ +#ifndef REQUESTHANDLERSIMPL_H +#define REQUESTHANDLERSIMPL_H + +#include "RequestHandler.h" +#include "mimetable.h" +#include "WString.h" +#include "Uri.h" +#include +#include + +using namespace mime; + +RequestHandler &RequestHandler::addMiddleware(Middleware *middleware) { + if (!_chain) { + _chain = new MiddlewareChain(); + } + _chain->addMiddleware(middleware); + return *this; +} + +RequestHandler &RequestHandler::addMiddleware(Middleware::Function fn) { + if (!_chain) { + _chain = new MiddlewareChain(); + } + _chain->addMiddleware(fn); + return *this; +} + +RequestHandler &RequestHandler::removeMiddleware(Middleware *middleware) { + if (_chain) { + _chain->removeMiddleware(middleware); + } + return *this; +} + +bool RequestHandler::process(WebServer &server, HTTPMethod requestMethod, String requestUri) { + if (_chain) { + return _chain->runChain(server, [this, &server, &requestMethod, &requestUri]() { + (void)requestUri; + return handle(server, requestMethod, requestUri); + }); + } else { + return handle(server, requestMethod, requestUri); + } +} + +class FunctionRequestHandler : public RequestHandler { +public: + FunctionRequestHandler(WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn, const Uri &uri, HTTPMethod method) + : _fn(fn), _ufn(ufn), _uri(uri.clone()), _method(method) { + _uri->initPathArgs(pathArgs); + } + + ~FunctionRequestHandler() { + delete _uri; + } + + bool canHandle(HTTPMethod requestMethod, const String &requestUri) override { + if (_method != HTTP_ANY && _method != requestMethod) { + return false; + } + + return _uri->canHandle(requestUri, pathArgs); + } + + bool canUpload(const String &requestUri) override { + if (!_ufn || !canHandle(HTTP_POST, requestUri)) { + return false; + } + + return true; + } + + bool canRaw(const String &requestUri) override { + (void)requestUri; + if (!_ufn || _method == HTTP_GET) { + return false; + } + + return true; + } + + bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override { + if (_method != HTTP_ANY && _method != requestMethod) { + return false; + } + + return _uri->canHandle(requestUri, pathArgs) && (_filter != NULL ? _filter(server) : true); + } + + bool canUpload(WebServer &server, const String &requestUri) override { + if (!_ufn || !canHandle(server, HTTP_POST, requestUri)) { + return false; + } + + return true; + } + + bool canRaw(WebServer &server, const String &requestUri) override { + (void)requestUri; + if (!_ufn || _method == HTTP_GET || (_filter != NULL ? _filter(server) == false : false)) { + return false; + } + + return true; + } + + bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override { + if (!canHandle(server, requestMethod, requestUri)) { + return false; + } + + _fn(); + return true; + } + + void upload(WebServer &server, const String &requestUri, HTTPUpload &upload) override { + (void)upload; + if (canUpload(server, requestUri)) { + _ufn(); + } + } + + void raw(WebServer &server, const String &requestUri, HTTPRaw &raw) override { + (void)raw; + if (canRaw(server, requestUri)) { + _ufn(); + } + } + + FunctionRequestHandler &setFilter(WebServer::FilterFunction filter) { + _filter = filter; + return *this; + } + +protected: + WebServer::THandlerFunction _fn; + WebServer::THandlerFunction _ufn; + // _filter should return 'true' when the request should be handled + // and 'false' when the request should be ignored + WebServer::FilterFunction _filter; + Uri *_uri; + HTTPMethod _method; +}; + +class StaticRequestHandler : public RequestHandler { +public: + StaticRequestHandler(FS &fs, const char *path, const char *uri, const char *cache_header) : _fs(fs), _uri(uri), _path(path), _cache_header(cache_header) { + File f = fs.open(path); + _isFile = (f && (!f.isDirectory())); + log_v( + "StaticRequestHandler: path=%s uri=%s isFile=%d, cache_header=%s\r\n", path, uri, _isFile, cache_header ? cache_header : "" + ); // issue 5506 - cache_header can be nullptr + _baseUriLength = _uri.length(); + } + + bool canHandle(HTTPMethod requestMethod, const String &requestUri) override { + if (requestMethod != HTTP_GET) { + return false; + } + + if ((_isFile && requestUri != _uri) || !requestUri.startsWith(_uri)) { + return false; + } + + return true; + } + + bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override { + if (requestMethod != HTTP_GET) { + return false; + } + + if ((_isFile && requestUri != _uri) || !requestUri.startsWith(_uri)) { + return false; + } + + if (_filter != NULL ? _filter(server) == false : false) { + return false; + } + + return true; + } + + bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override { + if (!canHandle(server, requestMethod, requestUri)) { + return false; + } + + log_v("StaticRequestHandler::handle: request=%s _uri=%s\r\n", requestUri.c_str(), _uri.c_str()); + + String path(_path); + + if (!_isFile) { + // Base URI doesn't point to a file. + // If a directory is requested, look for index file. + if (requestUri.endsWith("/")) { + return handle(server, requestMethod, String(requestUri + "index.htm")); + } + + // Append whatever follows this URI in request to get the file path. + path += requestUri.substring(_baseUriLength); + } + log_v("StaticRequestHandler::handle: path=%s, isFile=%d\r\n", path.c_str(), _isFile); + + String contentType = getContentType(path); + + // look for gz file, only if the original specified path is not a gz. So part only works to send gzip via content encoding when a non compressed is asked for + // if you point the the path to gzip you will serve the gzip as content type "application/x-gzip", not text or javascript etc... + if (!path.endsWith(FPSTR(mimeTable[gz].endsWith)) && !_fs.exists(path)) { + String pathWithGz = path + FPSTR(mimeTable[gz].endsWith); + if (_fs.exists(pathWithGz)) { + path += FPSTR(mimeTable[gz].endsWith); + } + } + + File f = _fs.open(path, "r"); + if (!f || !f.available()) { + return false; + } + + String eTagCode; + + if (server._eTagEnabled) { + if (server._eTagFunction) { + eTagCode = (server._eTagFunction)(_fs, path); + } else { + eTagCode = calcETag(_fs, path); + } + + if (server.header("If-None-Match") == eTagCode) { + server.send(304); + return true; + } + } + + if (_cache_header.length() != 0) { + server.sendHeader("Cache-Control", _cache_header); + } + + if ((server._eTagEnabled) && (eTagCode.length() > 0)) { + server.sendHeader("ETag", eTagCode); + } + + server.streamFile(f, contentType); + return true; + } + + static String getContentType(const String &path) { + char buff[sizeof(mimeTable[0].mimeType)]; + // Check all entries but last one for match, return if found + for (size_t i = 0; i < sizeof(mimeTable) / sizeof(mimeTable[0]) - 1; i++) { + strcpy_P(buff, mimeTable[i].endsWith); + if (path.endsWith(buff)) { + strcpy_P(buff, mimeTable[i].mimeType); + return String(buff); + } + } + // Fall-through and just return default type + strcpy_P(buff, mimeTable[sizeof(mimeTable) / sizeof(mimeTable[0]) - 1].mimeType); + return String(buff); + } + + // calculate an ETag for a file in filesystem based on md5 checksum + // that can be used in the http headers - include quotes. + static String calcETag(FS &fs, const String &path) { + String result; + + // calculate eTag using md5 checksum + uint8_t md5_buf[16]; + File f = fs.open(path, "r"); + MD5Builder calcMD5; + calcMD5.begin(); + calcMD5.addStream(f, f.size()); + calcMD5.calculate(); + calcMD5.getBytes(md5_buf); + f.close(); + // create a minimal-length eTag using base64 byte[]->text encoding. + result = "\"" + base64::encode(md5_buf, 16) + "\""; + return (result); + } // calcETag + + StaticRequestHandler &setFilter(WebServer::FilterFunction filter) { + _filter = filter; + return *this; + } + +protected: + // _filter should return 'true' when the request should be handled + // and 'false' when the request should be ignored + WebServer::FilterFunction _filter; + FS _fs; + String _uri; + String _path; + String _cache_header; + bool _isFile; + size_t _baseUriLength; +}; + +#endif //REQUESTHANDLERSIMPL_H diff --git a/libraries/WebServer/src/detail/mimetable.cpp b/libraries/WebServer/src/detail/mimetable.cpp new file mode 100644 index 0000000..036de07 --- /dev/null +++ b/libraries/WebServer/src/detail/mimetable.cpp @@ -0,0 +1,34 @@ +#include "mimetable.h" +#include "pgmspace.h" + +namespace mime { + +// Table of extension->MIME strings stored in PROGMEM, needs to be global due to GCC section typing rules +const Entry mimeTable[maxType] = { + {".html", "text/html"}, + {".htm", "text/html"}, + {".css", "text/css"}, + {".txt", "text/plain"}, + {".js", "application/javascript"}, + {".mjs", "text/javascript"}, + {".json", "application/json"}, + {".png", "image/png"}, + {".gif", "image/gif"}, + {".jpg", "image/jpeg"}, + {".ico", "image/x-icon"}, + {".svg", "image/svg+xml"}, + {".ttf", "application/x-font-ttf"}, + {".otf", "application/x-font-opentype"}, + {".woff", "application/font-woff"}, + {".woff2", "application/font-woff2"}, + {".eot", "application/vnd.ms-fontobject"}, + {".sfnt", "application/font-sfnt"}, + {".xml", "text/xml"}, + {".pdf", "application/pdf"}, + {".zip", "application/zip"}, + {".gz", "application/x-gzip"}, + {".appcache", "text/cache-manifest"}, + {"", "application/octet-stream"} +}; + +} // namespace mime diff --git a/libraries/WebServer/src/detail/mimetable.h b/libraries/WebServer/src/detail/mimetable.h new file mode 100644 index 0000000..869b28e --- /dev/null +++ b/libraries/WebServer/src/detail/mimetable.h @@ -0,0 +1,42 @@ +#ifndef __MIMETABLE_H__ +#define __MIMETABLE_H__ + +namespace mime { + +enum type { + html, + htm, + css, + txt, + js, + mjs, + json, + png, + gif, + jpg, + ico, + svg, + ttf, + otf, + woff, + woff2, + eot, + sfnt, + xml, + pdf, + zip, + gz, + appcache, + none, + maxType +}; + +struct Entry { + const char endsWith[16]; + const char mimeType[32]; +}; + +extern const Entry mimeTable[maxType]; +} // namespace mime + +#endif diff --git a/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp b/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp new file mode 100644 index 0000000..cab25ba --- /dev/null +++ b/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp @@ -0,0 +1,82 @@ +#include "Middlewares.h" + +AuthenticationMiddleware &AuthenticationMiddleware::setUsername(const char *username) { + _username = username; + _callback = nullptr; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setPassword(const char *password) { + _password = password; + _hash = false; + _callback = nullptr; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setPasswordHash(const char *sha1AsBase64orHex) { + _password = sha1AsBase64orHex; + _hash = true; + _callback = nullptr; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setCallback(WebServer::THandlerFunctionAuthCheck fn) { + assert(fn); + _callback = fn; + _hash = false; + _username = emptyString; + _password = emptyString; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setRealm(const char *realm) { + _realm = realm; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setAuthMethod(HTTPAuthMethod method) { + _method = method; + return *this; +} + +AuthenticationMiddleware &AuthenticationMiddleware::setAuthFailureMessage(const char *message) { + _authFailMsg = message; + return *this; +} + +bool AuthenticationMiddleware::isAllowed(WebServer &server) const { + if (_callback) { + return server.authenticate(_callback); + } + + if (!_username.isEmpty() && !_password.isEmpty()) { + if (_hash) { + return server.authenticateBasicSHA1(_username.c_str(), _password.c_str()); + } else { + return server.authenticate(_username.c_str(), _password.c_str()); + } + } + + return true; +} + +bool AuthenticationMiddleware::run(WebServer &server, Middleware::Callback next) { + bool authenticationRequired = false; + + if (_callback) { + authenticationRequired = !server.authenticate(_callback); + } else if (!_username.isEmpty() && !_password.isEmpty()) { + if (_hash) { + authenticationRequired = !server.authenticateBasicSHA1(_username.c_str(), _password.c_str()); + } else { + authenticationRequired = !server.authenticate(_username.c_str(), _password.c_str()); + } + } + + if (authenticationRequired) { + server.requestAuthentication(_method, _realm, _authFailMsg); + return true; + } else { + return next(); + } +} diff --git a/libraries/WebServer/src/middleware/CorsMiddleware.cpp b/libraries/WebServer/src/middleware/CorsMiddleware.cpp new file mode 100644 index 0000000..a52ccd5 --- /dev/null +++ b/libraries/WebServer/src/middleware/CorsMiddleware.cpp @@ -0,0 +1,47 @@ +#include "Middlewares.h" + +CorsMiddleware &CorsMiddleware::setOrigin(const char *origin) { + _origin = origin; + return *this; +} + +CorsMiddleware &CorsMiddleware::setMethods(const char *methods) { + _methods = methods; + return *this; +} + +CorsMiddleware &CorsMiddleware::setHeaders(const char *headers) { + _headers = headers; + return *this; +} + +CorsMiddleware &CorsMiddleware::setAllowCredentials(bool credentials) { + _credentials = credentials; + return *this; +} + +CorsMiddleware &CorsMiddleware::setMaxAge(uint32_t seconds) { + _maxAge = seconds; + return *this; +} + +void CorsMiddleware::addCORSHeaders(WebServer &server) { + server.sendHeader(F("Access-Control-Allow-Origin"), _origin.c_str()); + server.sendHeader(F("Access-Control-Allow-Methods"), _methods.c_str()); + server.sendHeader(F("Access-Control-Allow-Headers"), _headers.c_str()); + server.sendHeader(F("Access-Control-Allow-Credentials"), _credentials ? F("true") : F("false")); + server.sendHeader(F("Access-Control-Max-Age"), String(_maxAge).c_str()); +} + +bool CorsMiddleware::run(WebServer &server, Middleware::Callback next) { + // Origin header ? => CORS handling + if (server.hasHeader(F("Origin"))) { + addCORSHeaders(server); + // check if this is a preflight request => handle it and return + if (server.method() == HTTP_OPTIONS) { + server.send(200); + return true; + } + } + return next(); +} diff --git a/libraries/WebServer/src/middleware/LoggingMiddleware.cpp b/libraries/WebServer/src/middleware/LoggingMiddleware.cpp new file mode 100644 index 0000000..e1f6d70 --- /dev/null +++ b/libraries/WebServer/src/middleware/LoggingMiddleware.cpp @@ -0,0 +1,74 @@ +#include "Middlewares.h" + +void LoggingMiddleware::setOutput(Print &output) { + _out = &output; +} + +bool LoggingMiddleware::run(WebServer &server, Middleware::Callback next) { + if (_out == nullptr) { + return next(); + } + + _out->print(F("* Connection from ")); + _out->print(server.client().remoteIP().toString()); + _out->print(F(":")); + _out->println(server.client().remotePort()); + + _out->print(F("> ")); + const HTTPMethod method = server.method(); + if (method == HTTP_ANY) { + _out->print(F("HTTP_ANY")); + } else { + _out->print(http_method_str(method)); + } + _out->print(F(" ")); + _out->print(server.uri()); + _out->print(F(" ")); + _out->println(server.version()); + + int n = server.headers(); + for (int i = 0; i < n; i++) { + String v = server.header(i); + if (!v.isEmpty()) { + // because these 2 are always there, eventually empty: "Authorization", "If-None-Match" + _out->print(F("> ")); + _out->print(server.headerName(i)); + _out->print(F(": ")); + _out->println(server.header(i)); + } + } + + _out->println(F(">")); + + uint32_t elapsed = millis(); + const bool ret = next(); + elapsed = millis() - elapsed; + + if (ret) { + _out->print(F("* Processed in ")); + _out->print(elapsed); + _out->println(F(" ms")); + _out->print(F("< ")); + _out->print(F("HTTP/1.")); + _out->print(server.version()); + _out->print(F(" ")); + _out->print(server.responseCode()); + _out->print(F(" ")); + _out->println(WebServer::responseCodeToString(server.responseCode())); + + n = server.responseHeaders(); + for (int i = 0; i < n; i++) { + _out->print(F("< ")); + _out->print(server.responseHeaderName(i)); + _out->print(F(": ")); + _out->println(server.responseHeader(i)); + } + + _out->println(F("<")); + + } else { + _out->println(F("* Not processed!")); + } + + return ret; +} diff --git a/libraries/WebServer/src/middleware/Middleware.h b/libraries/WebServer/src/middleware/Middleware.h new file mode 100644 index 0000000..01d84a0 --- /dev/null +++ b/libraries/WebServer/src/middleware/Middleware.h @@ -0,0 +1,55 @@ +#ifndef MIDDLEWARE_H +#define MIDDLEWARE_H + +#include +#include + +class MiddlewareChain; +class WebServer; + +class Middleware { +public: + typedef std::function Callback; + typedef std::function Function; + + virtual ~Middleware() {} + + virtual bool run(WebServer &server, Callback next) { + (void)server; + return next(); + }; + +private: + friend MiddlewareChain; + Middleware *_next = nullptr; + bool _freeOnRemoval = false; +}; + +class MiddlewareFunction : public Middleware { +public: + MiddlewareFunction(Middleware::Function fn) : _fn(fn) {} + + bool run(WebServer &server, Middleware::Callback next) override { + return _fn(server, next); + } + +private: + Middleware::Function _fn; +}; + +class MiddlewareChain { +public: + ~MiddlewareChain(); + + void addMiddleware(Middleware::Function fn); + void addMiddleware(Middleware *middleware); + bool removeMiddleware(Middleware *middleware); + + bool runChain(WebServer &server, Middleware::Callback finalizer); + +private: + Middleware *_root = nullptr; + Middleware *_current = nullptr; +}; + +#endif diff --git a/libraries/WebServer/src/middleware/MiddlewareChain.cpp b/libraries/WebServer/src/middleware/MiddlewareChain.cpp new file mode 100644 index 0000000..56b3066 --- /dev/null +++ b/libraries/WebServer/src/middleware/MiddlewareChain.cpp @@ -0,0 +1,73 @@ +#include "Middleware.h" + +MiddlewareChain::~MiddlewareChain() { + Middleware *current = _root; + while (current) { + Middleware *next = current->_next; + if (current->_freeOnRemoval) { + delete current; + } + current = next; + } + _root = nullptr; +} + +void MiddlewareChain::addMiddleware(Middleware::Function fn) { + MiddlewareFunction *middleware = new MiddlewareFunction(fn); + middleware->_freeOnRemoval = true; + addMiddleware(middleware); +} + +void MiddlewareChain::addMiddleware(Middleware *middleware) { + if (!_root) { + _root = middleware; + return; + } + Middleware *current = _root; + while (current->_next) { + current = current->_next; + } + current->_next = middleware; +} + +bool MiddlewareChain::removeMiddleware(Middleware *middleware) { + if (!_root) { + return false; + } + if (_root == middleware) { + _root = _root->_next; + if (middleware->_freeOnRemoval) { + delete middleware; + } + return true; + } + Middleware *current = _root; + while (current->_next) { + if (current->_next == middleware) { + current->_next = current->_next->_next; + if (middleware->_freeOnRemoval) { + delete middleware; + } + return true; + } + current = current->_next; + } + return false; +} + +bool MiddlewareChain::runChain(WebServer &server, Middleware::Callback finalizer) { + if (!_root) { + return finalizer(); + } + _current = _root; + Middleware::Callback next; + next = [this, &server, &next, finalizer]() { + if (!_current) { + return finalizer(); + } + Middleware *that = _current; + _current = _current->_next; + return that->run(server, next); + }; + return next(); +} diff --git a/libraries/WebServer/src/uri/UriBraces.h b/libraries/WebServer/src/uri/UriBraces.h new file mode 100644 index 0000000..aa8fe60 --- /dev/null +++ b/libraries/WebServer/src/uri/UriBraces.h @@ -0,0 +1,68 @@ +#ifndef URI_BRACES_H +#define URI_BRACES_H + +#include "Uri.h" + +class UriBraces : public Uri { + +public: + explicit UriBraces(const char *uri) : Uri(uri){}; + explicit UriBraces(const String &uri) : Uri(uri){}; + + Uri *clone() const override final { + return new UriBraces(_uri); + }; + + void initPathArgs(std::vector &pathArgs) override final { + int numParams = 0, start = 0; + do { + start = _uri.indexOf("{}", start); + if (start > 0) { + numParams++; + start += 2; + } + } while (start > 0); + pathArgs.resize(numParams); + } + + bool canHandle(const String &requestUri, std::vector &pathArgs) override final { + if (Uri::canHandle(requestUri, pathArgs)) { + return true; + } + + size_t uriLength = _uri.length(); + unsigned int pathArgIndex = 0; + unsigned int requestUriIndex = 0; + for (unsigned int i = 0; i < uriLength; i++, requestUriIndex++) { + char uriChar = _uri[i]; + char requestUriChar = requestUri[requestUriIndex]; + + if (uriChar == requestUriChar) { + continue; + } + if (uriChar != '{') { + return false; + } + + i += 2; // index of char after '}' + if (i >= uriLength) { + // there is no char after '}' + pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex); + return pathArgs[pathArgIndex].indexOf("/") == -1; // path argument may not contain a '/' + } else { + char charEnd = _uri[i]; + int uriIndex = requestUri.indexOf(charEnd, requestUriIndex); + if (uriIndex < 0) { + return false; + } + pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex, uriIndex); + requestUriIndex = (unsigned int)uriIndex; + } + pathArgIndex++; + } + + return requestUriIndex >= requestUri.length(); + } +}; + +#endif diff --git a/libraries/WebServer/src/uri/UriGlob.h b/libraries/WebServer/src/uri/UriGlob.h new file mode 100644 index 0000000..5e69954 --- /dev/null +++ b/libraries/WebServer/src/uri/UriGlob.h @@ -0,0 +1,22 @@ +#ifndef URI_GLOB_H +#define URI_GLOB_H + +#include "Uri.h" +#include + +class UriGlob : public Uri { + +public: + explicit UriGlob(const char *uri) : Uri(uri){}; + explicit UriGlob(const String &uri) : Uri(uri){}; + + Uri *clone() const override final { + return new UriGlob(_uri); + }; + + bool canHandle(const String &requestUri, __attribute__((unused)) std::vector &pathArgs) override final { + return fnmatch(_uri.c_str(), requestUri.c_str(), 0) == 0; + } +}; + +#endif diff --git a/libraries/WebServer/src/uri/UriRegex.h b/libraries/WebServer/src/uri/UriRegex.h new file mode 100644 index 0000000..6412e7e --- /dev/null +++ b/libraries/WebServer/src/uri/UriRegex.h @@ -0,0 +1,45 @@ +#ifndef URI_REGEX_H +#define URI_REGEX_H + +#include "Uri.h" +#include + +class UriRegex : public Uri { + +public: + explicit UriRegex(const char *uri) : Uri(uri){}; + explicit UriRegex(const String &uri) : Uri(uri){}; + + Uri *clone() const override final { + return new UriRegex(_uri); + }; + + void initPathArgs(std::vector &pathArgs) override final { + std::regex rgx((_uri + "|").c_str()); + std::smatch matches; + std::string s{""}; + std::regex_search(s, matches, rgx); + pathArgs.resize(matches.size() - 1); + } + + bool canHandle(const String &requestUri, std::vector &pathArgs) override final { + if (Uri::canHandle(requestUri, pathArgs)) { + return true; + } + + unsigned int pathArgIndex = 0; + std::regex rgx(_uri.c_str()); + std::smatch matches; + std::string s(requestUri.c_str()); + if (std::regex_search(s, matches, rgx)) { + for (size_t i = 1; i < matches.size(); ++i) { // skip first + pathArgs[pathArgIndex] = String(matches[i].str().c_str()); + pathArgIndex++; + } + return true; + } + return false; + } +}; + +#endif diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino b/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino new file mode 100644 index 0000000..39322c0 --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino @@ -0,0 +1,91 @@ +/* Wi-Fi FTM Initiator Arduino Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#include "WiFi.h" + +/* + THIS FEATURE IS SUPPORTED ONLY BY ESP32-S2 AND ESP32-C3 +*/ + +// Change the SSID and PASSWORD here if needed +const char *WIFI_FTM_SSID = "WiFi_FTM_Responder"; // SSID of AP that has FTM Enabled +const char *WIFI_FTM_PASS = "ftm_responder"; // STA Password + +// FTM settings +// Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0 (No pref), 16, 24, 32, 64) +const uint8_t FTM_FRAME_COUNT = 16; +// Requested time period between consecutive FTM bursts in 100’s of milliseconds (allowed values - 0 (No pref) or 2-255) +const uint16_t FTM_BURST_PERIOD = 2; + +// Semaphore to signal when FTM Report has been received +SemaphoreHandle_t ftmSemaphore; +// Status of the received FTM Report +bool ftmSuccess = true; + +// FTM report handler with the calculated data from the round trip +// WARNING: This function is called from a separate FreeRTOS task (thread)! +void onFtmReport(arduino_event_t *event) { + const char *status_str[5] = {"SUCCESS", "UNSUPPORTED", "CONF_REJECTED", "NO_RESPONSE", "FAIL"}; + wifi_event_ftm_report_t *report = &event->event_info.wifi_ftm_report; + // Set the global report status + ftmSuccess = report->status == FTM_STATUS_SUCCESS; + if (ftmSuccess) { + // The estimated distance in meters may vary depending on some factors (see README file) + Serial.printf("FTM Estimate: Distance: %.2f m, Return Time: %lu ns\n", (float)report->dist_est / 100.0, report->rtt_est); + // Pointer to FTM Report with multiple entries, should be freed after use + free(report->ftm_report_data); + } else { + Serial.print("FTM Error: "); + Serial.println(status_str[report->status]); + } + // Signal that report is received + xSemaphoreGive(ftmSemaphore); +} + +// Initiate FTM Session and wait for FTM Report +bool getFtmReport() { + if (!WiFi.initiateFTM(FTM_FRAME_COUNT, FTM_BURST_PERIOD)) { + Serial.println("FTM Error: Initiate Session Failed"); + return false; + } + // Wait for signal that report is received and return true if status was success + return xSemaphoreTake(ftmSemaphore, portMAX_DELAY) == pdPASS && ftmSuccess; +} + +void setup() { + Serial.begin(115200); + + // Create binary semaphore (initialized taken and can be taken/given from any thread/ISR) + ftmSemaphore = xSemaphoreCreateBinary(); + + // Will call onFtmReport() from another thread with FTM Report events. + WiFi.onEvent(onFtmReport, ARDUINO_EVENT_WIFI_FTM_REPORT); + + // Connect to AP that has FTM Enabled + Serial.println("Connecting to FTM Responder"); + WiFi.begin(WIFI_FTM_SSID, WIFI_FTM_PASS); + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println(""); + Serial.println("WiFi Connected"); + + Serial.print("Initiating FTM session with Frame Count "); + Serial.print(FTM_FRAME_COUNT); + Serial.print(" and Burst Period "); + Serial.print(FTM_BURST_PERIOD * 100); + Serial.println(" ms"); + + // Request FTM reports until one fails + while (getFtmReport()); +} + +void loop() { + delay(1000); +} diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/README.md b/libraries/WiFi/examples/FTM/FTM_Initiator/README.md new file mode 100644 index 0000000..b9c7f8d --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Initiator/README.md @@ -0,0 +1,106 @@ +# Wi-Fi FTM Initiator Arduino Example + +This example demonstrates how to use the Fine Timing Measurement (FTM) to calculate the distance from the Access Point and the device. This is calculated by the Wi-Fi Round Trip Time (Wi-Fi RTT) introduced on the [IEEE Std 802.11-2016](https://en.wikipedia.org/wiki/IEEE_802.11mc) standard. + +This example was based on the [ESP-IDF FTM](https://github.com/espressif/esp-idf/tree/master/examples/wifi/ftm). See the README file for more details about on how to use this feature. + +Some usages for this feature includes: + +* Indoor positioning systems. +* Navigation. +* Device Location. +* Smart Devices. +* Alarms. + +# Supported Targets + +Currently, this example supports the following targets: + +| Supported Targets | ESP32-S2 | ESP32-C3 | +| ----------------- | -------- | -------- | + +## How to Use Example + +In order to use the FTM, you will need a Responder or Wi-Fi router with FTM capabilities. If you don't own one, you can use a second ESP32-S2 or ESP32-C3 to simulate one. +See the **Responder** example to prepare the environment. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +### Configure the Project + +To configure this project, you can change the following configuration related to FTM feature: + +```c +// Change the SSID and PASSWORD here if needed +const char * WIFI_FTM_SSID = "WiFi_FTM_Responder"; // SSID of AP that has FTM Enabled +const char * WIFI_FTM_PASS = "ftm_responder"; // STA Password + +// FTM settings +// Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0 (No pref), 16, 24, 32, 64) +const uint8_t FTM_FRAME_COUNT = 16; +// Requested time period between consecutive FTM bursts in 100’s of milliseconds (allowed values - 0 (No pref) or 2-255) +const uint16_t FTM_BURST_PERIOD = 2; +``` + +* Change the Wi-Fi `SSID` and `PASSWORD` as the same as the Responder/Router. +* Change `FTM_FRAME_COUNT` with the number of frames requested to the Responder. +* Change `FTM_BURST_PERIOD` with the time between each FTM burst. + +To see more details about FTM, please see the [ESP-IDF docs](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/network/esp_wifi.html). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Log Output + +Expected log output: + +``` +ESP-ROM:esp32s2-rc4-20191025 +Build:Oct 25 2019 +rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT) +SPIWP:0xee +mode:DIO, clock div:1 +load:0x3ffe6100,len:0x4b0 +load:0x4004c000,len:0xa6c +load:0x40050000,len:0x25c4 +entry 0x4004c198 +Connecting to FTM Responder +..... +WiFi Connected +Initiating FTM session with Frame Count 16 and Burst Period 200 ms +FTM Estimate: Distance: 0.13 m, Return Time: 0 ns +FTM Estimate: Distance: 0.13 m, Return Time: 0 ns +FTM Estimate: Distance: 0.13 m, Return Time: 0 ns +FTM Estimate: Distance: 0.00 m, Return Time: 0 ns +... +``` + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source.*** + +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persist, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/ci.yml b/libraries/WiFi/examples/FTM/FTM_Initiator/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Initiator/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino b/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino new file mode 100644 index 0000000..fd6bf2f --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino @@ -0,0 +1,23 @@ +/* Wi-Fi FTM Responder Arduino Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. +*/ +#include "WiFi.h" +// Change the SSID and PASSWORD here if needed +const char *WIFI_FTM_SSID = "WiFi_FTM_Responder"; +const char *WIFI_FTM_PASS = "ftm_responder"; + +void setup() { + Serial.begin(115200); + Serial.println("Starting SoftAP with FTM Responder support"); + // Enable AP with FTM support (last argument is 'true') + WiFi.softAP(WIFI_FTM_SSID, WIFI_FTM_PASS, 1, 0, 4, true); +} + +void loop() { + delay(1000); +} diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/README.md b/libraries/WiFi/examples/FTM/FTM_Responder/README.md new file mode 100644 index 0000000..fdcf1ab --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Responder/README.md @@ -0,0 +1,90 @@ +# Wi-Fi FTM Responder Arduino Example + +This example demonstrates how to use the Fine Timing Measurement (FTM) to calculate the distance from the Access Point and the device. This is calculated by the Wi-Fi Round Trip Time (Wi-Fi RTT) introduced on the [IEEE Std 802.11-2016](https://en.wikipedia.org/wiki/IEEE_802.11mc) standard. + +This example will simulate the Router with FTM capability. + +This example was based on the [ESP-IDF FTM](https://github.com/espressif/esp-idf/tree/master/examples/wifi/ftm). See the README file for more details about on how to use this feature. + +Some usages for this feature includes: + +* Indoor positioning systems. +* Navigation. +* Device Location. +* Smart Devices. +* Alarms. + +# Supported Targets + +Currently, this example supports the following targets: + +| Supported Targets | ESP32-S2 | ESP32-C3 | +| ----------------- | -------- | -------- | + +## How to Use Example + +See the **Initiator** example to prepare the environment. + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +### Configure the Project + +To configure this project, you can change the following configuration related to STA: + +```c +// Change the SSID and PASSWORD here if needed +const char * WIFI_FTM_SSID = "WiFi_FTM_Responder"; +const char * WIFI_FTM_PASS = "ftm_responder"; +``` + +* Change the Wi-Fi `SSID` and `PASSWORD` as the same as the Initiator. + +To see more details about FTM, please see the [ESP-IDF docs](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/network/esp_wifi.html). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Log Output + +Expected log output: + +``` +Build:Oct 25 2019 +rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT) +SPIWP:0xee +mode:DIO, clock div:1 +load:0x3ffe6100,len:0x4b0 +load:0x4004c000,len:0xa6c +load:0x40050000,len:0x25c4 +entry 0x4004c198 +Starting SoftAP with FTM Responder support +``` + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source.*** + +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persist, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/ci.yml b/libraries/WiFi/examples/FTM/FTM_Responder/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/FTM/FTM_Responder/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino b/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino new file mode 100644 index 0000000..ad5bdee --- /dev/null +++ b/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino @@ -0,0 +1,112 @@ +/* + WiFi Web Server LED Blink + + A simple web server that lets you blink an LED via the web. + This sketch will print the IP address of your WiFi Shield (once connected) + to the Serial monitor. From there, you can open that address in a web browser + to turn on and off the LED on pin 5. + + If the IP address of your shield is yourAddress: + http://yourAddress/H turns the LED on + http://yourAddress/L turns it off + + This example is written for a network using WPA2 encryption. For insecure + WEP or WPA, change the Wifi.begin() call and use Wifi.setMinSecurity() accordingly. + + Circuit: + * WiFi shield attached + * LED attached to pin 5 + + created for arduino 25 Nov 2012 + by Tom Igoe + +ported for sparkfun esp32 +31.01.2017 by Jan Hendrik Berlin + + */ + +#include + +const char *ssid = "yourssid"; +const char *password = "yourpasswd"; + +NetworkServer server(80); + +void setup() { + Serial.begin(115200); + pinMode(5, OUTPUT); // set the LED pin mode + + delay(10); + + // We start by connecting to a WiFi network + + Serial.println(); + Serial.println(); + Serial.print("Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.println("WiFi connected."); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + + server.begin(); +} + +void loop() { + NetworkClient client = server.accept(); // listen for incoming clients + + if (client) { // if you get a client, + Serial.println("New Client."); // print a message out the serial port + String currentLine = ""; // make a String to hold incoming data from the client + while (client.connected()) { // loop while the client's connected + if (client.available()) { // if there's bytes to read from the client, + char c = client.read(); // read a byte, then + Serial.write(c); // print it out the serial monitor + if (c == '\n') { // if the byte is a newline character + + // if the current line is blank, you got two newline characters in a row. + // that's the end of the client HTTP request, so send a response: + if (currentLine.length() == 0) { + // HTTP headers always start with a response code (e.g. HTTP/1.1 200 OK) + // and a content-type so the client knows what's coming, then a blank line: + client.println("HTTP/1.1 200 OK"); + client.println("Content-type:text/html"); + client.println(); + + // the content of the HTTP response follows the header: + client.print("Click here to turn the LED on pin 5 on.
"); + client.print("Click here to turn the LED on pin 5 off.
"); + + // The HTTP response ends with another blank line: + client.println(); + // break out of the while loop: + break; + } else { // if you got a newline, then clear currentLine: + currentLine = ""; + } + } else if (c != '\r') { // if you got anything else but a carriage return character, + currentLine += c; // add it to the end of the currentLine + } + + // Check to see if the client request was "GET /H" or "GET /L": + if (currentLine.endsWith("GET /H")) { + digitalWrite(5, HIGH); // GET /H turns the LED on + } + if (currentLine.endsWith("GET /L")) { + digitalWrite(5, LOW); // GET /L turns the LED off + } + } + } + // close the connection: + client.stop(); + Serial.println("Client Disconnected."); + } +} diff --git a/libraries/WiFi/examples/SimpleWiFiServer/ci.yml b/libraries/WiFi/examples/SimpleWiFiServer/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/SimpleWiFiServer/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WPS/README.md b/libraries/WiFi/examples/WPS/README.md new file mode 100644 index 0000000..6c53535 --- /dev/null +++ b/libraries/WiFi/examples/WPS/README.md @@ -0,0 +1,104 @@ +Example Serial Logs For Various Cases +====================================== + +For WPS Push Button method,after the ESP32 boots up and prints that WPS has started, press the button that looks something like [this](https://www.verizon.com/supportresources/images/fqgrouter-frontview-wps-button.png) on your router. In case you dont find anything similar, check your router specs if it does really support WPS Push functionality. + +As for WPS Pin Mode, it will output a 8 digit Pin on the Serial Monitor that will change every 2 minutes if it hasn't connected. You need to log in to your router (generally reaching 192.168.0.1) and enter the pin shown in Serial Monitor in the WPS Settings of your router. + +#### WPS Push Button Failure + +``` +ets Jun 8 2016 00:22:57 + +rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +configsip: 0, SPIWP:0xee +clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 +mode:DIO, clock div:1 +load:0x3fff0010,len:4 +load:0x3fff0014,len:732 +load:0x40078000,len:0 +load:0x40078000,len:11572 +entry 0x40078a14 + +Starting WPS +Station Mode Started +WPS Timedout, retrying +WPS Timedout, retrying +``` + +#### WPS Push Button Successful + +``` +ets Jun 8 2016 00:22:57 + +rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +ets Jun 8 2016 00:22:57 + +rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +configsip: 0, SPIWP:0xee +clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 +mode:DIO, clock div:1 +load:0x3fff0010,len:4 +load:0x3fff0014,len:732 +load:0x40078000,len:0 +load:0x40078000,len:11572 +entry 0x40078a14 + +Starting WPS +Station Mode Started +WPS Successful, stopping WPS and connecting to: < Your Router SSID > +Disconnected from station, attempting reconnection +Connected to : < Your Router SSID > +Got IP: 192.168.1.100 +``` + +#### WPS PIN Failure + +``` +ets Jun 8 2016 00:22:57 + +rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +ets Jun 8 2016 00:22:57 + +rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +configsip: 0, SPIWP:0xee +clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 +mode:DIO, clock div:1 +load:0x3fff0010,len:4 +load:0x3fff0014,len:732 +load:0x40078000,len:0 +load:0x40078000,len:11572 +entry 0x40078a14 + +Starting WPS +Station Mode Started +WPS_PIN = 94842104 +WPS Timedout, retrying +WPS_PIN = 55814171 +WPS Timedout, retrying +WPS_PIN = 71321622 +``` + +#### WPS PIN Successful + +``` +ets Jun 8 2016 00:22:57 + +rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +configsip: 0, SPIWP:0xee +clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 +mode:DIO, clock div:1 +load:0x3fff0010,len:4 +load:0x3fff0014,len:732 +load:0x40078000,len:0 +load:0x40078000,len:11572 +entry 0x40078a14 + +Starting WPS +Station Mode Started +WPS_PIN = 36807581 +WPS Successful, stopping WPS and connecting to: +Disconnected from station, attempting reconnection +Connected to : +Got IP: 192.168.1.100 +``` diff --git a/libraries/WiFi/examples/WPS/WPS.ino b/libraries/WiFi/examples/WPS/WPS.ino new file mode 100644 index 0000000..aacdd14 --- /dev/null +++ b/libraries/WiFi/examples/WPS/WPS.ino @@ -0,0 +1,116 @@ +/* +Example Code To Get ESP32 To Connect To A Router Using WPS +=========================================================== +This example code provides both Push Button method and Pin +based WPS entry to get your ESP connected to your WiFi router. + +Hardware Requirements +======================== +ESP32 and a Router having WPS functionality + +This code is under Public Domain License. + +Author: +Pranav Cherukupalli +*/ + +#include "sdkconfig.h" +#if CONFIG_ESP_WIFI_REMOTE_ENABLED +#error "WPS is only supported in SoCs with native Wi-Fi support" +#endif + +#include "WiFi.h" +#include "esp_wps.h" +/* +Change the definition of the WPS mode +from WPS_TYPE_PBC to WPS_TYPE_PIN in +the case that you are using pin type +WPS (pin is 00000000) +*/ +#define ESP_WPS_MODE WPS_TYPE_PBC + +void wpsStart() { + esp_wps_config_t config; + memset(&config, 0, sizeof(esp_wps_config_t)); + //Same as config = WPS_CONFIG_INIT_DEFAULT(ESP_WPS_MODE); + config.wps_type = ESP_WPS_MODE; + strcpy(config.factory_info.manufacturer, "ESPRESSIF"); + strcpy(config.factory_info.model_number, CONFIG_IDF_TARGET); + strcpy(config.factory_info.model_name, "ESPRESSIF IOT"); + strcpy(config.factory_info.device_name, "ESP DEVICE"); + strcpy(config.pin, "00000000"); + esp_err_t err = esp_wifi_wps_enable(&config); + if (err != ESP_OK) { + Serial.printf("WPS Enable Failed: 0x%x: %s\n", err, esp_err_to_name(err)); + return; + } + + err = esp_wifi_wps_start(0); + if (err != ESP_OK) { + Serial.printf("WPS Start Failed: 0x%x: %s\n", err, esp_err_to_name(err)); + } +} + +void wpsStop() { + esp_err_t err = esp_wifi_wps_disable(); + if (err != ESP_OK) { + Serial.printf("WPS Disable Failed: 0x%x: %s\n", err, esp_err_to_name(err)); + } +} + +String wpspin2string(uint8_t a[]) { + char wps_pin[9]; + for (int i = 0; i < 8; i++) { + wps_pin[i] = a[i]; + } + wps_pin[8] = '\0'; + return (String)wps_pin; +} + +// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)! +void WiFiEvent(WiFiEvent_t event, arduino_event_info_t info) { + switch (event) { + case ARDUINO_EVENT_WIFI_STA_START: Serial.println("Station Mode Started"); break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + Serial.println("Connected to :" + String(WiFi.SSID())); + Serial.print("Got IP: "); + Serial.println(WiFi.localIP()); + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: + Serial.println("Disconnected from station, attempting reconnection"); + WiFi.reconnect(); + break; + case ARDUINO_EVENT_WPS_ER_SUCCESS: + Serial.println("WPS Successful, stopping WPS and connecting to: " + String(WiFi.SSID())); + wpsStop(); + delay(10); + WiFi.begin(); + break; + case ARDUINO_EVENT_WPS_ER_FAILED: + Serial.println("WPS Failed, retrying"); + wpsStop(); + wpsStart(); + break; + case ARDUINO_EVENT_WPS_ER_TIMEOUT: + Serial.println("WPS Timedout, retrying"); + wpsStop(); + wpsStart(); + break; + case ARDUINO_EVENT_WPS_ER_PIN: Serial.println("WPS_PIN = " + wpspin2string(info.wps_er_pin.pin_code)); break; + default: break; + } +} + +void setup() { + Serial.begin(115200); + delay(10); + Serial.println(); + WiFi.onEvent(WiFiEvent); // Will call WiFiEvent() from another thread. + WiFi.mode(WIFI_MODE_STA); + Serial.println("Starting WPS"); + wpsStart(); +} + +void loop() { + //nothing to do here +} diff --git a/libraries/WiFi/examples/WPS/ci.yml b/libraries/WiFi/examples/WPS/ci.yml new file mode 100644 index 0000000..86e194b --- /dev/null +++ b/libraries/WiFi/examples/WPS/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_WIFI_SUPPORTED=y diff --git a/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino new file mode 100644 index 0000000..19fd105 --- /dev/null +++ b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino @@ -0,0 +1,98 @@ +/* + WiFiAccessPoint.ino creates a WiFi access point and provides a web server on it. + + Steps: + 1. Connect to the access point "yourAp" + 2. Point your web browser to http://192.168.4.1/H to turn the LED on or http://192.168.4.1/L to turn it off + OR + Run raw TCP "GET /H" and "GET /L" on PuTTY terminal with 192.168.4.1 as IP address and 80 as port + + Created for arduino-esp32 on 04 July, 2018 + by Elochukwu Ifediora (fedy0) +*/ + +#include +#include +#include + +#ifndef LED_BUILTIN +#define LED_BUILTIN 2 // Set the GPIO pin where you connected your test LED or comment this line out if your dev board has a built-in LED +#endif + +// Set these to your desired credentials. +const char *ssid = "yourAP"; +const char *password = "yourPassword"; + +NetworkServer server(80); + +void setup() { + pinMode(LED_BUILTIN, OUTPUT); + + Serial.begin(115200); + Serial.println(); + Serial.println("Configuring access point..."); + + // You can remove the password parameter if you want the AP to be open. + // a valid password must have more than 7 characters + if (!WiFi.softAP(ssid, password)) { + log_e("Soft AP creation failed."); + while (1); + } + IPAddress myIP = WiFi.softAPIP(); + Serial.print("AP IP address: "); + Serial.println(myIP); + server.begin(); + + Serial.println("Server started"); +} + +void loop() { + NetworkClient client = server.accept(); // listen for incoming clients + + if (client) { // if you get a client, + Serial.println("New Client."); // print a message out the serial port + String currentLine = ""; // make a String to hold incoming data from the client + while (client.connected()) { // loop while the client's connected + if (client.available()) { // if there's bytes to read from the client, + char c = client.read(); // read a byte, then + Serial.write(c); // print it out the serial monitor + if (c == '\n') { // if the byte is a newline character + + // if the current line is blank, you got two newline characters in a row. + // that's the end of the client HTTP request, so send a response: + if (currentLine.length() == 0) { + // HTTP headers always start with a response code (e.g. HTTP/1.1 200 OK) + // and a content-type so the client knows what's coming, then a blank line: + client.println("HTTP/1.1 200 OK"); + client.println("Content-type:text/html"); + client.println(); + + // the content of the HTTP response follows the header: + client.print("Click here to turn ON the LED.
"); + client.print("Click here to turn OFF the LED.
"); + + // The HTTP response ends with another blank line: + client.println(); + // break out of the while loop: + break; + } else { // if you got a newline, then clear currentLine: + currentLine = ""; + } + } else if (c != '\r') { // if you got anything else but a carriage return character, + currentLine += c; // add it to the end of the currentLine + } + + // Check to see if the client request was "GET /H" or "GET /L": + if (currentLine.endsWith("GET /H")) { + digitalWrite(LED_BUILTIN, HIGH); // GET /H turns the LED on + } + if (currentLine.endsWith("GET /L")) { + digitalWrite(LED_BUILTIN, LOW); // GET /L turns the LED off + } + } + } + // close the connection: + client.stop(); + Serial.println("Client Disconnected."); + } +} diff --git a/libraries/WiFi/examples/WiFiAccessPoint/ci.yml b/libraries/WiFi/examples/WiFiAccessPoint/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiAccessPoint/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino b/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino new file mode 100644 index 0000000..942846f --- /dev/null +++ b/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino @@ -0,0 +1,133 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Sketch shows how to switch between WiFi and BlueTooth or use both +// Button is attached between GPIO 0 and GND and modes are switched with each press + +#include "soc/soc_caps.h" +#if !CONFIG_SOC_BT_SUPPORTED +#error "This example requires native Bluetooth support" +#endif + +#include "WiFi.h" +#define STA_SSID "your-ssid" +#define STA_PASS "your-pass" +#define AP_SSID "esp32" + +enum { + STEP_BTON, + STEP_BTOFF, + STEP_STA, + STEP_AP, + STEP_AP_STA, + STEP_OFF, + STEP_BT_STA, + STEP_END +}; + +void onButton() { + static uint32_t step = STEP_BTON; + switch (step) { + case STEP_BTON: //BT Only + Serial.println("** Starting BT"); + btStart(); + break; + case STEP_BTOFF: //All Off + Serial.println("** Stopping BT"); + btStop(); + break; + case STEP_STA: //STA Only + Serial.println("** Starting STA"); + WiFi.begin(STA_SSID, STA_PASS); + break; + case STEP_AP: //AP Only + Serial.println("** Stopping STA"); + WiFi.mode(WIFI_AP); + Serial.println("** Starting AP"); + WiFi.softAP(AP_SSID); + break; + case STEP_AP_STA: //AP+STA + Serial.println("** Starting STA"); + WiFi.begin(STA_SSID, STA_PASS); + break; + case STEP_OFF: //All Off + Serial.println("** Stopping WiFi"); + WiFi.mode(WIFI_OFF); + break; + case STEP_BT_STA: //BT+STA + Serial.println("** Starting STA+BT"); + WiFi.begin(STA_SSID, STA_PASS); + btStart(); + break; + case STEP_END: //All Off + Serial.println("** Stopping WiFi+BT"); + WiFi.mode(WIFI_OFF); + btStop(); + break; + default: break; + } + if (step == STEP_END) { + step = STEP_BTON; + } else { + step++; + } + //little debounce + delay(100); +} + +// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)! +void WiFiEvent(WiFiEvent_t event) { + switch (event) { + case ARDUINO_EVENT_WIFI_AP_START: + Serial.println("AP Started"); + WiFi.softAPsetHostname(AP_SSID); + break; + case ARDUINO_EVENT_WIFI_AP_STOP: Serial.println("AP Stopped"); break; + case ARDUINO_EVENT_WIFI_STA_START: + Serial.println("STA Started"); + WiFi.setHostname(AP_SSID); + break; + case ARDUINO_EVENT_WIFI_STA_CONNECTED: Serial.println("STA Connected"); break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP6: + Serial.print("STA IPv6: "); + Serial.println(WiFi.linkLocalIPv6()); + break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + Serial.print("STA IPv4: "); + Serial.println(WiFi.localIP()); + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: Serial.println("STA Disconnected"); break; + case ARDUINO_EVENT_WIFI_STA_STOP: Serial.println("STA Stopped"); break; + default: break; + } +} + +void setup() { + Serial.begin(115200); + pinMode(0, INPUT_PULLUP); + WiFi.onEvent(WiFiEvent); // Will call WiFiEvent() from another thread. + WiFi.enableIPv6(); + Serial.print("ESP32 SDK: "); + Serial.println(ESP.getSdkVersion()); + Serial.println("Press the button to select the next mode"); +} + +void loop() { + static uint8_t lastPinState = 1; + uint8_t pinState = digitalRead(0); + if (!pinState && lastPinState) { + onButton(); + } + lastPinState = pinState; +} diff --git a/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.yml b/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.yml new file mode 100644 index 0000000..62aa0cb --- /dev/null +++ b/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.yml @@ -0,0 +1,6 @@ +requires: + - CONFIG_SOC_BT_SUPPORTED=y + +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiClient/README.md b/libraries/WiFi/examples/WiFiClient/README.md new file mode 100644 index 0000000..9d3698a --- /dev/null +++ b/libraries/WiFi/examples/WiFiClient/README.md @@ -0,0 +1,161 @@ +# NetworkClient + +This example demonstrates reading and writing data from and to a web service which can be used for logging data, creating insights and taking actions based on those data. + +# Supported Targets + +Currently, this example supports all SoC with Wi-Fi. + + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | + + +## How to Use Example + +Flash this example and observe the serial output. You can also take a look at the values at [https://thingspeak.com/channels/2005329](https://thingspeak.com/channels/2005329) + +Please note that this public channel can be accessed by anyone and it is possible that more people will write their values. + +### Configure the Project + +Change `SSID` and `password` to connect to your Wi-Fi. +Default values will allow you to use this example without any changes. If you want to use your own channel and you don't have one already follow these steps: + +* Create an account on [thingspeak.com](https://www.thingspeak.com). +* After logging in, click on the "New Channel" button to create a new channel for your data. This is where your data will be stored and displayed. +* Fill in the Name, Description, and other fields for your channel as desired, then click the "Save Channel" button. +* Take note of the "Write API Key" located in the "API keys" tab, this is the key you will use to send data to your channel. +* Replace the channelID from tab "Channel Settings" and privateKey with "Read API Keys" from "API Keys" tab. +* Replace the host variable with the thingspeak server hostname "api.thingspeak.com" +* Upload the sketch to your ESP32 board and make sure that the board is connected to the internet. The ESP32 should now send data to your Thingspeak channel at the intervals specified by the loop function. +* Go to the channel view page on thingspeak and check the "Field1" for the new incoming data. +* You can use the data visualization and analysis tools provided by Thingspeak to display and process your data in various ways. +* Please note, that Thingspeak accepts only integer values. + +#### Config example: + +You can find the data to be changed at the top of the file: + +```cpp +const char* ssid = "your-ssid"; // Change this to your WiFi SSID +const char* password = "your-password"; // Change this to your WiFi password + +const char* host = "api.thingspeak.com"; // This should not be changed +const int httpPort = 80; // This should not be changed +const String channelID = "2005329"; // Change this to your channel ID +const String writeApiKey = "V6YOTILH9I7D51F9"; // Change this to your Write API key +const String readApiKey = "34W6LGLIFXD56MPM"; // Change this to your Read API key + +// The default example accepts one data filed named "field1" +// For your own server you can ofcourse create more of them. +int field1 = 0; + +int numberOfResults = 3; // Number of results to be read +int fieldNumber = 1; // Field number which will be read out +``` + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example Log Output + +The initial output which is common for all examples can be ignored: +``` +SP-ROM:esp32c3-api1-20210207 +Build:Feb 7 2021 +rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT) +SPIWP:0xee +mode:DIO, clock div:1 +load:0x3fcd5810,len:0x438 +load:0x403cc710,len:0x918 +load:0x403ce710,len:0x24e4 +entry 0x403cc710 +``` +Follows the setup output where connection to your Wi-Fi happens: +``` +****************************************************** +Connecting to your-ssid +. +WiFi connected +IP address: +192.168.1.2 +``` +Then you can see the write log: +``` +HTTP/1.1 200 OK +Date: Fri, 13 Jan 2023 13:12:31 GMT +Content-Type: text/plain; charset=utf-8 +Content-Length: 1 +Connection: close +Status: 200 OK +Cache-Control: max-age=0, private, must-revalidate +Access-Control-Allow-Origin: * +Access-Control-Max-Age: 1800 +X-Request-Id: 188e3464-f155-44b0-96f6-0f3614170bb0 +Access-Control-Allow-Headers: origin, content-type, X-Requested-With +Access-Control-Allow-Methods: GET, POST, PUT, OPTIONS, DELETE, PATCH +ETag: W/"5feceb66ffc86f38d952786c6d696c79" +X-Frame-Options: SAMEORIGIN + +0 +Closing connection +``` +Last portion is the read log: +``` +HTTP/1.1 200 OK +Date: Fri, 13 Jan 2023 13:12:32 GMT +Content-Type: application/json; charset=utf-8 +Transfer-Encoding: chunked +Connection: close +Status: 200 OK +Cache-Control: max-age=7, private +Access-Control-Allow-Origin: * +Access-Control-Max-Age: 1800 +X-Request-Id: 91b97016-7625-44f6-9797-1b2973aa57b7 +Access-Control-Allow-Headers: origin, content-type, X-Requested-With +Access-Control-Allow-Methods: GET, POST, PUT, OPTIONS, DELETE, PATCH +ETag: W/"8e9c308fe2c50309f991586be1aff28d" +X-Frame-Options: SAMEORIGIN + +1e3 +{"channel":{"id":2005329,"name":"WiFiCLient example","description":"Default setup for Arduino ESP32 NetworkClient example","latitude":"0.0","longitude":"0.0","field1":"data0","created_at":"2023-01-11T15:56:08Z","updated_at":"2023-01-13T08:13:58Z","last_entry_id":2871},"feeds":[{"created_at":"2023-01-13T13:11:30Z","entry_id":2869,"field1":"359"},{"created_at":"2023-01-13T13:11:57Z","entry_id":2870,"field1":"361"},{"created_at":"2023-01-13T13:12:23Z","entry_id":2871,"field1":"363"}]} +0 + + +Closing connection +``` +After this the write+read log repeat every 10 seconds. + + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **Wi-Fi not connected:** Check the SSID and password and also that the signal has sufficient strength. +* **400 Bad Request:** Check the writeApiKey. +* **404 Not Found:** Check the channel ID. +* **No data on chart / reading NULL:** Data must be sent as an integer, without commas. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/WiFiClient/WiFiClient.ino b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino new file mode 100644 index 0000000..b4c8824 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino @@ -0,0 +1,105 @@ +/* + Go to thingspeak.com and create an account if you don't have one already. + After logging in, click on the "New Channel" button to create a new channel for your data. This is where your data will be stored and displayed. + Fill in the Name, Description, and other fields for your channel as desired, then click the "Save Channel" button. + Take note of the "Write API Key" located in the "API keys" tab, this is the key you will use to send data to your channel. + Replace the channelID from tab "Channel Settings" and privateKey with "Read API Keys" from "API Keys" tab. + Replace the host variable with the thingspeak server hostname "api.thingspeak.com" + Upload the sketch to your ESP32 board and make sure that the board is connected to the internet. The ESP32 should now send data to your Thingspeak channel at the intervals specified by the loop function. + Go to the channel view page on thingspeak and check the "Field1" for the new incoming data. + You can use the data visualization and analysis tools provided by Thingspeak to display and process your data in various ways. + Please note, that Thingspeak accepts only integer values. + + You can later check the values at https://thingspeak.com/channels/2005329 + Please note that this public channel can be accessed by anyone and it is possible that more people will write their values. + */ + +#include + +const char *ssid = "your-ssid"; // Change this to your WiFi SSID +const char *password = "your-password"; // Change this to your WiFi password + +const char *host = "api.thingspeak.com"; // This should not be changed +const int httpPort = 80; // This should not be changed +const String channelID = "2005329"; // Change this to your channel ID +const String writeApiKey = "V6YOTILH9I7D51F9"; // Change this to your Write API key +const String readApiKey = "34W6LGLIFXD56MPM"; // Change this to your Read API key + +// The default example accepts one data filed named "field1" +// For your own server you can ofcourse create more of them. +int field1 = 0; + +int numberOfResults = 3; // Number of results to be read +int fieldNumber = 1; // Field number which will be read out + +void setup() { + Serial.begin(115200); + + // We start by connecting to a WiFi network + + Serial.println(); + Serial.println("******************************************************"); + Serial.print("Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); +} + +void readResponse(NetworkClient *client) { + unsigned long timeout = millis(); + while (client->available() == 0) { + if (millis() - timeout > 5000) { + Serial.println(">>> Client Timeout !"); + client->stop(); + return; + } + } + + // Read all the lines of the reply from server and print them to Serial + while (client->available()) { + String line = client->readStringUntil('\r'); + Serial.print(line); + } + + Serial.printf("\nClosing connection\n\n"); +} + +void loop() { + NetworkClient client; + String footer = String(" HTTP/1.1\r\n") + "Host: " + String(host) + "\r\n" + "Connection: close\r\n\r\n"; + + // WRITE -------------------------------------------------------------------------------------------- + if (!client.connect(host, httpPort)) { + return; + } + + client.print("GET /update?api_key=" + writeApiKey + "&field1=" + field1 + footer); + readResponse(&client); + + // READ -------------------------------------------------------------------------------------------- + + String readRequest = "GET /channels/" + channelID + "/fields/" + fieldNumber + ".json?results=" + numberOfResults + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + + "Connection: close\r\n\r\n"; + + if (!client.connect(host, httpPort)) { + return; + } + + client.print(readRequest); + readResponse(&client); + + // ------------------------------------------------------------------------------------------------- + + ++field1; + delay(10000); +} diff --git a/libraries/WiFi/examples/WiFiClient/ci.yml b/libraries/WiFi/examples/WiFiClient/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClient/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino new file mode 100644 index 0000000..3cbfb4a --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino @@ -0,0 +1,80 @@ +/* + * This sketch sends a message to a TCP server + * + */ + +#include +#include + +WiFiMulti WiFiMulti; + +void setup() { + Serial.begin(115200); + delay(10); + + // We start by connecting to a WiFi network + WiFiMulti.addAP("SSID", "passpasspass"); + + Serial.println(); + Serial.println(); + Serial.print("Waiting for WiFi... "); + + while (WiFiMulti.run() != WL_CONNECTED) { + Serial.print("."); + delay(500); + } + + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + + delay(500); +} + +void loop() { + // const uint16_t port = 80; + // const char * host = "192.168.1.1"; // ip or dns + const uint16_t port = 1337; + const char *host = "192.168.1.10"; // ip or dns + + Serial.print("Connecting to "); + Serial.println(host); + + // Use NetworkClient class to create TCP connections + NetworkClient client; + + if (!client.connect(host, port)) { + Serial.println("Connection failed."); + Serial.println("Waiting 5 seconds before retrying..."); + delay(5000); + return; + } + + // This will send a request to the server + //uncomment this line to send an arbitrary string to the server + //client.print("Send this data to the server"); + //uncomment this line to send a basic document request to the server + client.print("GET /index.html HTTP/1.1\n\n"); + + int maxloops = 0; + + //wait for the server's reply to become available + while (!client.available() && maxloops < 1000) { + maxloops++; + delay(1); //delay 1 msec + } + if (client.available() > 0) { + //read back one line from the server + String line = client.readStringUntil('\r'); + Serial.println(line); + } else { + Serial.println("client.available() timed out "); + } + + Serial.println("Closing connection."); + client.stop(); + + Serial.println("Waiting 5 seconds before restarting..."); + delay(5000); +} diff --git a/libraries/WiFi/examples/WiFiClientBasic/ci.yml b/libraries/WiFi/examples/WiFiClientBasic/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientBasic/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiClientConnect/README.md b/libraries/WiFi/examples/WiFiClientConnect/README.md new file mode 100644 index 0000000..939d44c --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientConnect/README.md @@ -0,0 +1,71 @@ +# NetworkClientConnect Example + +This example demonstrates how to connect to the Wi-Fi and manage the status and disconnection from STA. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | +| ----------------- | ----- | -------- | -------- | + +## How to Use Example + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example/Log Output + +``` +[WiFi] Connecting to MyWiFiNetwork +[ 66][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 0 - WIFI_READY +[ 150][V][WiFiGeneric.cpp:338] _arduino_event_cb(): STA Started +[ 151][V][WiFiGeneric.cpp:97] set_esp_interface_ip(): Configuring Station static IP: 0.0.0.0, MASK: 0.0.0.0, GW: 0.0.0.0 +[ 151][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 2 - STA_START +[WiFi] WiFi is disconnected +[ 234][V][WiFiGeneric.cpp:353] _arduino_event_cb(): STA Connected: SSID: MyWiFiNetwork, BSSID: xx:xx:xx:xx:xx:xx, Channel: 8, Auth: WPA2_PSK +[ 235][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 4 - STA_CONNECTED +[ 560][V][WiFiGeneric.cpp:367] _arduino_event_cb(): STA Got New IP:192.168.68.114 +[ 561][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 7 - STA_GOT_IP +[ 564][D][WiFiGeneric.cpp:1004] _eventCallback(): STA IP: 192.168.68.114, MASK: 255.255.255.0, GW: 192.168.68.1 +[WiFi] WiFi is connected! +[WiFi] IP address: 192.168.68.114 +[WiFi] Disconnecting from WiFi! +[ 2633][V][WiFiGeneric.cpp:360] _arduino_event_cb(): STA Disconnected: SSID: MyWiFiNetwork, BSSID: xx:xx:xx:xx:xx:xx, Reason: 8 +[ 2634][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 5 - STA_DISCONNECTED +[ 2635][V][WiFiGeneric.cpp:341] _arduino_event_cb(): STA Stopped +[ 2641][W][WiFiGeneric.cpp:953] _eventCallback(): Reason: 8 - ASSOC_LEAVE +[ 2654][D][WiFiGeneric.cpp:975] _eventCallback(): WiFi the station is disconnected +[ 2661][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 3 - STA_STOP +[WiFi] Disconnected from WiFi! +... +``` + +## Troubleshooting + +***Important: Be sure you're using a good quality USB cable that has enough power for your project.*** + +* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed. +* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino b/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino new file mode 100644 index 0000000..b2fdec6 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino @@ -0,0 +1,90 @@ +/* Wi-Fi STA Connect and Disconnect Example + + This example code is in the Public Domain (or CC0 licensed, at your option.) + + Unless required by applicable law or agreed to in writing, this + software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + CONDITIONS OF ANY KIND, either express or implied. + +*/ +#include + +const char *ssid = "your-ssid"; +const char *password = "your-password"; + +int btnGPIO = 0; +int btnState = false; + +void setup() { + Serial.begin(115200); + delay(10); + + // Set GPIO0 Boot button as input + pinMode(btnGPIO, INPUT); + + // We start by connecting to a WiFi network + // To debug, please enable Core Debug Level to Verbose + + Serial.println(); + Serial.print("[WiFi] Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + // Auto reconnect is set true as default + // To set auto connect off, use the following function + // WiFi.setAutoReconnect(false); + + // Will try for about 10 seconds (20x 500ms) + int tryDelay = 500; + int numberOfTries = 20; + + // Wait for the WiFi event + while (true) { + + switch (WiFi.status()) { + case WL_NO_SSID_AVAIL: Serial.println("[WiFi] SSID not found"); break; + case WL_CONNECT_FAILED: + Serial.print("[WiFi] Failed - WiFi not connected! Reason: "); + return; + break; + case WL_CONNECTION_LOST: Serial.println("[WiFi] Connection was lost"); break; + case WL_SCAN_COMPLETED: Serial.println("[WiFi] Scan is completed"); break; + case WL_DISCONNECTED: Serial.println("[WiFi] WiFi is disconnected"); break; + case WL_CONNECTED: + Serial.println("[WiFi] WiFi is connected!"); + Serial.print("[WiFi] IP address: "); + Serial.println(WiFi.localIP()); + return; + break; + default: + Serial.print("[WiFi] WiFi Status: "); + Serial.println(WiFi.status()); + break; + } + delay(tryDelay); + + if (numberOfTries <= 0) { + Serial.print("[WiFi] Failed to connect to WiFi!"); + // Use disconnect function to force stop trying to connect + WiFi.disconnect(); + return; + } else { + numberOfTries--; + } + } +} + +void loop() { + // Read the button state + btnState = digitalRead(btnGPIO); + + if (btnState == LOW) { + // Disconnect from WiFi + Serial.println("[WiFi] Disconnecting from WiFi!"); + // This function will disconnect and turn off the WiFi (NVS WiFi data is kept) + if (WiFi.disconnect(true, false)) { + Serial.println("[WiFi] Disconnected from WiFi!"); + } + delay(1000); + } +} diff --git a/libraries/WiFi/examples/WiFiClientConnect/ci.yml b/libraries/WiFi/examples/WiFiClientConnect/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientConnect/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/README.md b/libraries/WiFi/examples/WiFiClientEnterprise/README.md new file mode 100644 index 0000000..20d38b8 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEnterprise/README.md @@ -0,0 +1,45 @@ +# ESP32-Eduroam +* Eduroam Wi-Fi connection with university login identity +* Working under Eduroam networks worldwide +* Methods: PEAP + MsCHAPv2 + +# Format +* IDENTITY = youridentity --> if connecting from different university, use youridentity@youruniversity.domain format +* PASSWORD = yourpassword + +# Usage +* Change IDENTITY +* Change password +* Upload sketch and enjoy! +* After successful assign of IP address, board will connect to HTTP page on internet to verify your authentication +* Board will auto reconnect to Eduroam if it lost connection + +# Tested locations + +|University|Board|Method|Result| +|-------------|-------------| -----|------| +|Technical University in Košice (Slovakia)|ESP32 Devkit v1|PEAP + MsCHAPv2|Working| +|Technical University in Košice (Slovakia)|ESP32 Devmodule v4|PEAP + MsCHAPv2|Working on 6th attempt in loop| +|Slovak Technical University in Bratislava (Slovakia)|ESP32 Devkit v1|PEAP + MsCHAPv2|Working| +|University of Antwerp (Belgium)|Lolin32|PEAP + MsCHAPv2|Working| +|UPV Universitat Politècnica de València (Spain)|ESP32 Devmodule v4|PEAP + MsCHAPv2|Working| +|Local Zeroshell powered network|ESP32 Devkit v1|PEAP + MsCHAPv2|*Not working*| +|Hasselt University (Belgium)|xxx|PEAP + MsCHAPv2|Working with fix sketch| +|Universidad de Granada (Spain)|Lolin D32 Pro|PEAP + MsCHAPv2|Working| +|Universidad de Granada (Spain)|Lolin D32|PEAP + MsCHAPv2|Working| +|Universidade Federal de Santa Catarina (Brazil)|xxx|EAP-TTLS + MsCHAPv2|Working| +|University of Central Florida (Orlando, Florida)|ESP32 Built-in OLED – Heltec WiFi Kit 32|PEAP + MsCHAPv2|Working| +|Université de Montpellier (France)|NodeMCU-32S|PEAP + MsCHAPv2|Working| + + +# Common errors - Switch to Debug mode for Serial monitor prints +|Error|Appearance|Solution| +|-------------|-------------|-------------| +|Wi-Fi: Set status to INIT|Frequent|Hold EN button for few seconds| +|HANDSHAKE_TIMEOUT|Rare|Bug was found under Zeroshell RADIUS authentization - Unsuccessful connection| +|AUTH_EXPIRE|Common|In the case of weak Wi-Fi network signal, this error is quite common, bring your device closer to AP| +|ASSOC_EXPIRE|Rare|-| +# Successful connection example + ![alt text](https://i.nahraj.to/f/24Kc.png) +# Unsuccessful connection example + ![alt text](https://camo.githubusercontent.com/87e47d1b27f4e8ace87423e40e8edbce7983bafa/68747470733a2f2f692e6e616872616a2e746f2f662f323435572e504e47) diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino b/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino new file mode 100644 index 0000000..198f97e --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino @@ -0,0 +1,89 @@ +#include "sdkconfig.h" +#if CONFIG_ESP_WIFI_REMOTE_ENABLED +#error "WPA-Enterprise is only supported in SoCs with native Wi-Fi support" +#endif + +#include //Wifi library +#define EAP_IDENTITY "login" //if connecting from another corporation, use identity@organization.domain in Eduroam +#define EAP_USERNAME "login" //oftentimes just a repeat of the identity +#define EAP_PASSWORD "password" //your Eduroam password +const char *ssid = "eduroam"; // Eduroam SSID +const char *host = "arduino.php5.sk"; //external server domain for HTTP connection after authentication +int counter = 0; + +// NOTE: For some systems, various certification keys are required to connect to the wifi system. +// Usually you are provided these by the IT department of your organization when certs are required +// and you can't connect with just an identity and password. +// Most eduroam setups we have seen do not require this level of authentication, but you should contact +// your IT department to verify. +// You should uncomment these and populate with the contents of the files if this is required for your scenario (See Example 2 and Example 3 below). +//const char *ca_pem = "insert your CA cert from your .pem file here"; +//const char *client_cert = "insert your client cert from your .crt file here"; +//const char *client_key = "insert your client key from your .key file here"; + +void setup() { + Serial.begin(115200); + delay(10); + Serial.println(); + Serial.print("Connecting to network: "); + Serial.println(ssid); + WiFi.disconnect(true); //disconnect form wifi to set new wifi connection + WiFi.mode(WIFI_STA); //init wifi mode + + // Example1 (most common): a cert-file-free eduroam with PEAP (or TTLS) + WiFi.begin(ssid, WPA2_AUTH_PEAP, EAP_IDENTITY, EAP_USERNAME, EAP_PASSWORD); + + // Example 2: a cert-file WPA2 Enterprise with PEAP + //WiFi.begin(ssid, WPA2_AUTH_PEAP, EAP_IDENTITY, EAP_USERNAME, EAP_PASSWORD, ca_pem, client_cert, client_key); + + // Example 3: TLS with cert-files and no password + //WiFi.begin(ssid, WPA2_AUTH_TLS, EAP_IDENTITY, NULL, NULL, ca_pem, client_cert, client_key); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + counter++; + if (counter >= 60) { //after 30 seconds timeout - reset board + ESP.restart(); + } + } + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address set: "); + Serial.println(WiFi.localIP()); //print LAN IP +} +void loop() { + if (WiFi.status() == WL_CONNECTED) { //if we are connected to Eduroam network + counter = 0; //reset counter + Serial.println("Wifi is still connected with IP: "); + Serial.println(WiFi.localIP()); //inform user about his IP address + } else if (WiFi.status() != WL_CONNECTED) { //if we lost connection, retry + WiFi.begin(ssid); + } + while (WiFi.status() != WL_CONNECTED) { //during lost connection, print dots + delay(500); + Serial.print("."); + counter++; + if (counter >= 60) { //30 seconds timeout - reset board + ESP.restart(); + } + } + Serial.print("Connecting to website: "); + Serial.println(host); + NetworkClient client; + if (client.connect(host, 80)) { + String url = "/rele/rele1.txt"; + client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "User-Agent: ESP32\r\n" + "Connection: close\r\n\r\n"); + + while (client.connected()) { + String line = client.readStringUntil('\n'); + if (line == "\r") { + break; + } + } + String line = client.readStringUntil('\n'); + Serial.println(line); + } else { + Serial.println("Connection unsuccessful"); + } +} diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/ci.yml b/libraries/WiFi/examples/WiFiClientEnterprise/ci.yml new file mode 100644 index 0000000..86e194b --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEnterprise/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_WIFI_SUPPORTED=y diff --git a/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino new file mode 100644 index 0000000..41b2fd0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino @@ -0,0 +1,124 @@ +/* + * This sketch shows the WiFi event usage + * +*/ + +/* +* WiFi Events + +0 ARDUINO_EVENT_WIFI_READY < ESP32 WiFi ready +1 ARDUINO_EVENT_WIFI_SCAN_DONE < ESP32 finish scanning AP +2 ARDUINO_EVENT_WIFI_STA_START < ESP32 station start +3 ARDUINO_EVENT_WIFI_STA_STOP < ESP32 station stop +4 ARDUINO_EVENT_WIFI_STA_CONNECTED < ESP32 station connected to AP +5 ARDUINO_EVENT_WIFI_STA_DISCONNECTED < ESP32 station disconnected from AP +6 ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE < the auth mode of AP connected by ESP32 station changed +7 ARDUINO_EVENT_WIFI_STA_GOT_IP < ESP32 station got IP from connected AP +8 ARDUINO_EVENT_WIFI_STA_LOST_IP < ESP32 station lost IP and the IP is reset to 0 +9 ARDUINO_EVENT_WPS_ER_SUCCESS < ESP32 station wps succeeds in enrollee mode +10 ARDUINO_EVENT_WPS_ER_FAILED < ESP32 station wps fails in enrollee mode +11 ARDUINO_EVENT_WPS_ER_TIMEOUT < ESP32 station wps timeout in enrollee mode +12 ARDUINO_EVENT_WPS_ER_PIN < ESP32 station wps pin code in enrollee mode +13 ARDUINO_EVENT_WIFI_AP_START < ESP32 soft-AP start +14 ARDUINO_EVENT_WIFI_AP_STOP < ESP32 soft-AP stop +15 ARDUINO_EVENT_WIFI_AP_STACONNECTED < a station connected to ESP32 soft-AP +16 ARDUINO_EVENT_WIFI_AP_STADISCONNECTED < a station disconnected from ESP32 soft-AP +17 ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED < ESP32 soft-AP assign an IP to a connected station +18 ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED < Receive probe request packet in soft-AP interface +19 ARDUINO_EVENT_WIFI_AP_GOT_IP6 < ESP32 ap interface v6IP addr is preferred +19 ARDUINO_EVENT_WIFI_STA_GOT_IP6 < ESP32 station interface v6IP addr is preferred +20 ARDUINO_EVENT_ETH_START < ESP32 ethernet start +21 ARDUINO_EVENT_ETH_STOP < ESP32 ethernet stop +22 ARDUINO_EVENT_ETH_CONNECTED < ESP32 ethernet phy link up +23 ARDUINO_EVENT_ETH_DISCONNECTED < ESP32 ethernet phy link down +24 ARDUINO_EVENT_ETH_GOT_IP < ESP32 ethernet got IP from connected AP +19 ARDUINO_EVENT_ETH_GOT_IP6 < ESP32 ethernet interface v6IP addr is preferred +25 ARDUINO_EVENT_MAX +*/ + +#include + +const char *ssid = "your-ssid"; +const char *password = "your-password"; + +// WARNING: This function is called from a separate FreeRTOS task (thread)! +void WiFiEvent(WiFiEvent_t event) { + Serial.printf("[WiFi-event] event: %d\n", event); + + switch (event) { + case ARDUINO_EVENT_WIFI_READY: Serial.println("WiFi interface ready"); break; + case ARDUINO_EVENT_WIFI_SCAN_DONE: Serial.println("Completed scan for access points"); break; + case ARDUINO_EVENT_WIFI_STA_START: Serial.println("WiFi client started"); break; + case ARDUINO_EVENT_WIFI_STA_STOP: Serial.println("WiFi clients stopped"); break; + case ARDUINO_EVENT_WIFI_STA_CONNECTED: Serial.println("Connected to access point"); break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: Serial.println("Disconnected from WiFi access point"); break; + case ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE: Serial.println("Authentication mode of access point has changed"); break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + Serial.print("Obtained IP address: "); + Serial.println(WiFi.localIP()); + break; + case ARDUINO_EVENT_WIFI_STA_LOST_IP: Serial.println("Lost IP address and IP address is reset to 0"); break; + case ARDUINO_EVENT_WPS_ER_SUCCESS: Serial.println("WiFi Protected Setup (WPS): succeeded in enrollee mode"); break; + case ARDUINO_EVENT_WPS_ER_FAILED: Serial.println("WiFi Protected Setup (WPS): failed in enrollee mode"); break; + case ARDUINO_EVENT_WPS_ER_TIMEOUT: Serial.println("WiFi Protected Setup (WPS): timeout in enrollee mode"); break; + case ARDUINO_EVENT_WPS_ER_PIN: Serial.println("WiFi Protected Setup (WPS): pin code in enrollee mode"); break; + case ARDUINO_EVENT_WIFI_AP_START: Serial.println("WiFi access point started"); break; + case ARDUINO_EVENT_WIFI_AP_STOP: Serial.println("WiFi access point stopped"); break; + case ARDUINO_EVENT_WIFI_AP_STACONNECTED: Serial.println("Client connected"); break; + case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("Client disconnected"); break; + case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED: Serial.println("Assigned IP address to client"); break; + case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED: Serial.println("Received probe request"); break; + case ARDUINO_EVENT_WIFI_AP_GOT_IP6: Serial.println("AP IPv6 is preferred"); break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP6: Serial.println("STA IPv6 is preferred"); break; + case ARDUINO_EVENT_ETH_GOT_IP6: Serial.println("Ethernet IPv6 is preferred"); break; + case ARDUINO_EVENT_ETH_START: Serial.println("Ethernet started"); break; + case ARDUINO_EVENT_ETH_STOP: Serial.println("Ethernet stopped"); break; + case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("Ethernet connected"); break; + case ARDUINO_EVENT_ETH_DISCONNECTED: Serial.println("Ethernet disconnected"); break; + case ARDUINO_EVENT_ETH_GOT_IP: Serial.println("Obtained IP address"); break; + default: break; + } +} + +// WARNING: This function is called from a separate FreeRTOS task (thread)! +void WiFiGotIP(WiFiEvent_t event, WiFiEventInfo_t info) { + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(IPAddress(info.got_ip.ip_info.ip.addr)); +} + +void setup() { + Serial.begin(115200); + + // delete old config + WiFi.disconnect(true); + + delay(1000); + + // Examples of different ways to register wifi events; + // these handlers will be called from another thread. + WiFi.onEvent(WiFiEvent); + WiFi.onEvent(WiFiGotIP, WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_GOT_IP); + WiFiEventId_t eventID = WiFi.onEvent( + [](WiFiEvent_t event, WiFiEventInfo_t info) { + Serial.print("WiFi lost connection. Reason: "); + Serial.println(info.wifi_sta_disconnected.reason); + }, + WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_DISCONNECTED + ); + + // Remove WiFi event + Serial.print("WiFi Event ID: "); + Serial.println(eventID); + // WiFi.removeEvent(eventID); + + WiFi.begin(ssid, password); + + Serial.println(); + Serial.println(); + Serial.println("Wait for WiFi... "); +} + +void loop() { + delay(1000); +} diff --git a/libraries/WiFi/examples/WiFiClientEvents/ci.yml b/libraries/WiFi/examples/WiFiClientEvents/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientEvents/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino b/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino new file mode 100644 index 0000000..4d93d00 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino @@ -0,0 +1,87 @@ +/* + Example of connection using Static IP + by Evandro Luis Copercini + Public domain - 2017 +*/ + +#include + +const char *ssid = "your_network_name"; +const char *password = "your_network_password"; +const char *host = "example.com"; +const char *url = "/index.html"; + +IPAddress local_IP(192, 168, 31, 115); +IPAddress gateway(192, 168, 31, 1); +IPAddress subnet(255, 255, 0, 0); +IPAddress primaryDNS(8, 8, 8, 8); //optional +IPAddress secondaryDNS(8, 8, 4, 4); //optional + +void setup() { + Serial.begin(115200); + + if (!WiFi.config(local_IP, gateway, subnet, primaryDNS, secondaryDNS)) { + Serial.println("STA Failed to configure"); + } + + Serial.print("Connecting to "); + Serial.println(ssid); + + WiFi.begin(ssid, password); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.println("WiFi connected!"); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + Serial.print("ESP Mac Address: "); + Serial.println(WiFi.macAddress()); + Serial.print("Subnet Mask: "); + Serial.println(WiFi.subnetMask()); + Serial.print("Gateway IP: "); + Serial.println(WiFi.gatewayIP()); + Serial.print("DNS: "); + Serial.println(WiFi.dnsIP()); +} + +void loop() { + delay(5000); + + Serial.print("connecting to "); + Serial.println(host); + + // Use NetworkClient class to create TCP connections + NetworkClient client; + const int httpPort = 80; + if (!client.connect(host, httpPort)) { + Serial.println("connection failed"); + return; + } + + Serial.print("Requesting URL: "); + Serial.println(url); + + // This will send the request to the server + client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "Connection: close\r\n\r\n"); + unsigned long timeout = millis(); + while (client.available() == 0) { + if (millis() - timeout > 5000) { + Serial.println(">>> Client Timeout !"); + client.stop(); + return; + } + } + + // Read all the lines of the reply from server and print them to Serial + while (client.available()) { + String line = client.readStringUntil('\r'); + Serial.print(line); + } + + Serial.println(); + Serial.println("closing connection"); +} diff --git a/libraries/WiFi/examples/WiFiClientStaticIP/ci.yml b/libraries/WiFi/examples/WiFiClientStaticIP/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiClientStaticIP/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino b/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino new file mode 100644 index 0000000..c7f95c1 --- /dev/null +++ b/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino @@ -0,0 +1,68 @@ +#include + +#define STA_SSID "YOUR-SSID" +#define STA_PASS "YOUR-PASS" + +#define AP_SSID "ESP32-WIFI-EXTENDER" +#define AP_PASS "password" + +IPAddress ap_ip(192, 168, 4, 1); +IPAddress ap_mask(255, 255, 255, 0); +IPAddress ap_leaseStart(192, 168, 4, 2); +IPAddress ap_dns(8, 8, 4, 4); + +void setup() { + Serial.begin(115200); + Serial.setDebugOutput(true); + Network.onEvent(onEvent); + + WiFi.AP.begin(); + WiFi.AP.config(ap_ip, ap_ip, ap_mask, ap_leaseStart, ap_dns); + WiFi.AP.create(AP_SSID, AP_PASS); + if (!WiFi.AP.waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) { + Serial.println("Failed to start AP!"); + return; + } + + WiFi.begin(STA_SSID, STA_PASS); +} + +void loop() { + delay(20000); +} + +void onEvent(arduino_event_id_t event, arduino_event_info_t info) { + switch (event) { + case ARDUINO_EVENT_WIFI_STA_START: Serial.println("STA Started"); break; + case ARDUINO_EVENT_WIFI_STA_CONNECTED: Serial.println("STA Connected"); break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + Serial.println("STA Got IP"); + Serial.println(WiFi.STA); + WiFi.AP.enableNAPT(true); + break; + case ARDUINO_EVENT_WIFI_STA_LOST_IP: + Serial.println("STA Lost IP"); + WiFi.AP.enableNAPT(false); + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: + Serial.println("STA Disconnected"); + WiFi.AP.enableNAPT(false); + break; + case ARDUINO_EVENT_WIFI_STA_STOP: Serial.println("STA Stopped"); break; + + case ARDUINO_EVENT_WIFI_AP_START: + Serial.println("AP Started"); + Serial.println(WiFi.AP); + break; + case ARDUINO_EVENT_WIFI_AP_STACONNECTED: Serial.println("AP STA Connected"); break; + case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("AP STA Disconnected"); break; + case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED: + Serial.print("AP STA IP Assigned: "); + Serial.println(IPAddress(info.wifi_ap_staipassigned.ip.addr)); + break; + case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED: Serial.println("AP Probe Request Received"); break; + case ARDUINO_EVENT_WIFI_AP_STOP: Serial.println("AP Stopped"); break; + + default: break; + } +} diff --git a/libraries/WiFi/examples/WiFiExtender/ci.yml b/libraries/WiFi/examples/WiFiExtender/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiExtender/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino b/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino new file mode 100644 index 0000000..d7241a2 --- /dev/null +++ b/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino @@ -0,0 +1,120 @@ +#include "WiFi.h" + +#define STA_SSID "**********" +#define STA_PASS "**********" +#define AP_SSID "esp32-v6" + +static volatile bool wifi_connected = false; + +NetworkUDP ntpClient; + +void wifiOnConnect() { + Serial.println("STA Connected"); + Serial.print("STA IPv4: "); + Serial.println(WiFi.localIP()); + + ntpClient.begin(2390); +} + +void wifiOnDisconnect() { + Serial.println("STA Disconnected"); + delay(1000); + WiFi.begin(STA_SSID, STA_PASS); +} + +void wifiConnectedLoop() { + //lets check the time + const int NTP_PACKET_SIZE = 48; + byte ntpPacketBuffer[NTP_PACKET_SIZE]; + + IPAddress address; + WiFi.hostByName("time.nist.gov", address); + memset(ntpPacketBuffer, 0, NTP_PACKET_SIZE); + ntpPacketBuffer[0] = 0b11100011; // LI, Version, Mode + ntpPacketBuffer[1] = 0; // Stratum, or type of clock + ntpPacketBuffer[2] = 6; // Polling Interval + ntpPacketBuffer[3] = 0xEC; // Peer Clock Precision + // 8 bytes of zero for Root Delay & Root Dispersion + ntpPacketBuffer[12] = 49; + ntpPacketBuffer[13] = 0x4E; + ntpPacketBuffer[14] = 49; + ntpPacketBuffer[15] = 52; + ntpClient.beginPacket(address, 123); //NTP requests are to port 123 + ntpClient.write(ntpPacketBuffer, NTP_PACKET_SIZE); + ntpClient.endPacket(); + + delay(1000); + + int packetLength = ntpClient.parsePacket(); + if (packetLength) { + if (packetLength >= NTP_PACKET_SIZE) { + ntpClient.read(ntpPacketBuffer, NTP_PACKET_SIZE); + } + ntpClient.clear(); + uint32_t secsSince1900 = + (uint32_t)ntpPacketBuffer[40] << 24 | (uint32_t)ntpPacketBuffer[41] << 16 | (uint32_t)ntpPacketBuffer[42] << 8 | ntpPacketBuffer[43]; + //Serial.printf("Seconds since Jan 1 1900: %u\n", secsSince1900); + uint32_t epoch = secsSince1900 - 2208988800UL; + //Serial.printf("EPOCH: %u\n", epoch); + uint8_t h = (epoch % 86400L) / 3600; + uint8_t m = (epoch % 3600) / 60; + uint8_t s = (epoch % 60); + Serial.printf("UTC: %02u:%02u:%02u (GMT)\n", h, m, s); + } + + delay(9000); +} + +// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)! +void WiFiEvent(WiFiEvent_t event) { + switch (event) { + case ARDUINO_EVENT_WIFI_AP_START: + //can set ap hostname here + WiFi.softAPsetHostname(AP_SSID); + break; + case ARDUINO_EVENT_WIFI_STA_START: + //set sta hostname here + WiFi.setHostname(AP_SSID); + break; + case ARDUINO_EVENT_WIFI_STA_CONNECTED: break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP6: + Serial.print("STA IPv6: "); + Serial.println(WiFi.linkLocalIPv6()); + break; + case ARDUINO_EVENT_WIFI_AP_GOT_IP6: + Serial.print("AP IPv6: "); + Serial.println(WiFi.softAPlinkLocalIPv6()); + break; + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + wifiOnConnect(); + wifi_connected = true; + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: + wifi_connected = false; + wifiOnDisconnect(); + break; + default: break; + } +} + +void setup() { + Serial.begin(115200); + WiFi.disconnect(true); + WiFi.onEvent(WiFiEvent); // Will call WiFiEvent() from another thread. + WiFi.mode(WIFI_MODE_APSTA); + //enable ap ipv6 here + WiFi.softAPenableIPv6(); + WiFi.softAP(AP_SSID); + //enable sta ipv6 here + WiFi.enableIPv6(); + WiFi.begin(STA_SSID, STA_PASS); +} + +void loop() { + if (wifi_connected) { + wifiConnectedLoop(); + } + while (Serial.available()) { + Serial.write(Serial.read()); + } +} diff --git a/libraries/WiFi/examples/WiFiIPv6/ci.yml b/libraries/WiFi/examples/WiFiIPv6/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiIPv6/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino new file mode 100644 index 0000000..00a2456 --- /dev/null +++ b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino @@ -0,0 +1,33 @@ +/* + * This sketch tries to Connect to the best AP based on a given list + * + */ + +#include +#include + +WiFiMulti wifiMulti; + +void setup() { + Serial.begin(115200); + delay(10); + + wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1"); + wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2"); + wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3"); + + Serial.println("Connecting Wifi..."); + if (wifiMulti.run() == WL_CONNECTED) { + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + } +} + +void loop() { + if (wifiMulti.run() != WL_CONNECTED) { + Serial.println("WiFi not connected!"); + delay(1000); + } +} diff --git a/libraries/WiFi/examples/WiFiMulti/ci.yml b/libraries/WiFi/examples/WiFiMulti/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiMulti/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino b/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino new file mode 100644 index 0000000..8086161 --- /dev/null +++ b/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino @@ -0,0 +1,64 @@ +/* + * This sketch tries to connect to the best AP available + * and tests for captive portals on open networks + * + */ + +#include +#include +#include + +WiFiMulti wifiMulti; + +// callback used to check Internet connectivity +bool testConnection() { + HTTPClient http; + http.begin("http://www.espressif.com"); + int httpCode = http.GET(); + // we expect to get a 301 because it will ask to use HTTPS instead of HTTP + if (httpCode == HTTP_CODE_MOVED_PERMANENTLY) { + return true; + } + return false; +} + +void setup() { + Serial.begin(115200); + delay(10); + + wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1"); + wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2"); + wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3"); + + // These options can help when you need ANY kind of wifi connection to get a config file, report errors, etc. + wifiMulti.setStrictMode(false); // Default is true. Library will disconnect and forget currently connected AP if it's not in the AP list. + wifiMulti.setAllowOpenAP(true); // Default is false. True adds open APs to the AP list. + wifiMulti.setConnectionTestCallbackFunc(testConnection); // Attempts to connect to a remote webserver in case of captive portals. + + Serial.println("Connecting Wifi..."); + if (wifiMulti.run() == WL_CONNECTED) { + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + } +} + +void loop() { + static bool isConnected = false; + uint8_t WiFiStatus = wifiMulti.run(); + + if (WiFiStatus == WL_CONNECTED) { + if (!isConnected) { + Serial.println(""); + Serial.println("WiFi connected"); + Serial.println("IP address: "); + Serial.println(WiFi.localIP()); + } + isConnected = true; + } else { + Serial.println("WiFi not connected!"); + isConnected = false; + delay(5000); + } +} diff --git a/libraries/WiFi/examples/WiFiMultiAdvanced/ci.yml b/libraries/WiFi/examples/WiFiMultiAdvanced/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiMultiAdvanced/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiScan/README.md b/libraries/WiFi/examples/WiFiScan/README.md new file mode 100644 index 0000000..f1268f2 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScan/README.md @@ -0,0 +1,61 @@ +# WiFiScan Example + +This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks and print the results. + +## Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +## How to Use Example + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example/Log Output + +``` +Setup done +Scan start +Scan done +17 networks found +Nr | SSID | RSSI | CH | Encryption + 1 | IoTNetwork | -62 | 1 | WPA2 + 2 | WiFiSSID | -62 | 1 | WPA2-EAP + 3 | B3A7992 | -63 | 6 | WPA+WPA2 + 4 | WiFi | -63 | 6 | WPA3 + 5 | IoTNetwork2 | -64 | 11 | WPA2+WPA3 +... +``` + +## Troubleshooting + +***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.*** + +* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed. +* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/WiFiScan/WiFiScan.ino b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino new file mode 100644 index 0000000..d840959 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino @@ -0,0 +1,83 @@ +/* + * This sketch demonstrates how to scan WiFi networks. For chips that support 5GHz band, separate scans are done for all bands. + * The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported. + * E.g. the return value of `encryptionType()` different because more modern encryption is supported. + */ +#include "WiFi.h" + +void setup() { + Serial.begin(115200); + // Enable Station Interface + WiFi.STA.begin(); + Serial.println("Setup done"); +} + +void ScanWiFi() { + Serial.println("Scan start"); + // WiFi.scanNetworks will return the number of networks found. + int n = WiFi.scanNetworks(); + Serial.println("Scan done"); + if (n == 0) { + Serial.println("no networks found"); + } else { + Serial.print(n); + Serial.println(" networks found"); + Serial.println("Nr | SSID | RSSI | CH | Encryption"); + for (int i = 0; i < n; ++i) { + // Print SSID and RSSI for each network found + Serial.printf("%2d", i + 1); + Serial.print(" | "); + Serial.printf("%-32.32s", WiFi.SSID(i).c_str()); + Serial.print(" | "); + Serial.printf("%4ld", WiFi.RSSI(i)); + Serial.print(" | "); + Serial.printf("%2ld", WiFi.channel(i)); + Serial.print(" | "); + switch (WiFi.encryptionType(i)) { + case WIFI_AUTH_OPEN: Serial.print("open"); break; + case WIFI_AUTH_WEP: Serial.print("WEP"); break; + case WIFI_AUTH_WPA_PSK: Serial.print("WPA"); break; + case WIFI_AUTH_WPA2_PSK: Serial.print("WPA2"); break; + case WIFI_AUTH_WPA_WPA2_PSK: Serial.print("WPA+WPA2"); break; + case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break; + case WIFI_AUTH_WPA3_PSK: Serial.print("WPA3"); break; + case WIFI_AUTH_WPA2_WPA3_PSK: Serial.print("WPA2+WPA3"); break; + case WIFI_AUTH_WAPI_PSK: Serial.print("WAPI"); break; + default: Serial.print("unknown"); + } + Serial.println(); + delay(10); + } + } + + // Delete the scan result to free memory for code below. + WiFi.scanDelete(); + Serial.println("-------------------------------------"); +} +void loop() { + Serial.println("-------------------------------------"); + Serial.println("Default wifi band mode scan:"); + Serial.println("-------------------------------------"); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) + WiFi.setBandMode(WIFI_BAND_MODE_AUTO); +#endif + ScanWiFi(); +#if CONFIG_SOC_WIFI_SUPPORT_5G + // Wait a bit before scanning again. + delay(1000); + Serial.println("-------------------------------------"); + Serial.println("2.4 Ghz wifi band mode scan:"); + Serial.println("-------------------------------------"); + WiFi.setBandMode(WIFI_BAND_MODE_2G_ONLY); + ScanWiFi(); + // Wait a bit before scanning again. + delay(1000); + Serial.println("-------------------------------------"); + Serial.println("5 Ghz wifi band mode scan:"); + Serial.println("-------------------------------------"); + WiFi.setBandMode(WIFI_BAND_MODE_5G_ONLY); + ScanWiFi(); +#endif + // Wait a bit before scanning again. + delay(10000); +} diff --git a/libraries/WiFi/examples/WiFiScan/ci.yml b/libraries/WiFi/examples/WiFiScan/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScan/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiScanAsync/README.md b/libraries/WiFi/examples/WiFiScanAsync/README.md new file mode 100644 index 0000000..26120aa --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanAsync/README.md @@ -0,0 +1,71 @@ +# WiFiScanAsync Example + +This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks in asynchronous mode and print the results. + +## Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +## How to Use Example + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example/Log Output + +``` +Setup done +Scan start +Loop running... +Loop running... +Loop running... +Loop running... +Loop running... +Loop running... +Loop running... +Loop running... +Loop running... + +Scan done +17 networks found +Nr | SSID | RSSI | CH | Encryption + 1 | IoTNetwork | -62 | 1 | WPA2 + 2 | WiFiSSID | -62 | 1 | WPA2-EAP + 3 | B3A7992 | -63 | 6 | WPA+WPA2 + 4 | WiFi | -63 | 6 | WPA3 + 5 | IoTNetwork2 | -64 | 11 | WPA2+WPA3 +... +``` + +## Troubleshooting + +***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.*** + +* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed. +* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino b/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino new file mode 100644 index 0000000..b5f4a0a --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino @@ -0,0 +1,82 @@ +/* + This sketch demonstrates how to scan WiFi networks in Async Mode. + The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported. + E.g. the return value of `encryptionType()` different because more modern encryption is supported. +*/ +#include "WiFi.h" + +void startWiFiScan() { + Serial.println("Scan start"); + // WiFi.scanNetworks will return immediately in Async Mode. + WiFi.scanNetworks(true); // 'true' turns Async Mode ON +} + +void printScannedNetworks(uint16_t networksFound) { + if (networksFound == 0) { + Serial.println("no networks found"); + } else { + Serial.println("\nScan done"); + Serial.print(networksFound); + Serial.println(" networks found"); + Serial.println("Nr | SSID | RSSI | CH | Encryption"); + for (int i = 0; i < networksFound; ++i) { + // Print SSID and RSSI for each network found + Serial.printf("%2d", i + 1); + Serial.print(" | "); + Serial.printf("%-32.32s", WiFi.SSID(i).c_str()); + Serial.print(" | "); + Serial.printf("%4ld", WiFi.RSSI(i)); + Serial.print(" | "); + Serial.printf("%2ld", WiFi.channel(i)); + Serial.print(" | "); + switch (WiFi.encryptionType(i)) { + case WIFI_AUTH_OPEN: Serial.print("open"); break; + case WIFI_AUTH_WEP: Serial.print("WEP"); break; + case WIFI_AUTH_WPA_PSK: Serial.print("WPA"); break; + case WIFI_AUTH_WPA2_PSK: Serial.print("WPA2"); break; + case WIFI_AUTH_WPA_WPA2_PSK: Serial.print("WPA+WPA2"); break; + case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break; + case WIFI_AUTH_WPA3_PSK: Serial.print("WPA3"); break; + case WIFI_AUTH_WPA2_WPA3_PSK: Serial.print("WPA2+WPA3"); break; + case WIFI_AUTH_WAPI_PSK: Serial.print("WAPI"); break; + default: Serial.print("unknown"); + } + Serial.println(); + delay(10); + } + Serial.println(""); + // Delete the scan result to free memory for code below. + WiFi.scanDelete(); + } +} + +void setup() { + Serial.begin(115200); + + // Set WiFi to station mode and disconnect from an AP if it was previously connected. + WiFi.mode(WIFI_STA); + WiFi.disconnect(); + delay(100); + + Serial.println("Setup done"); + startWiFiScan(); +} + +void loop() { + // check WiFi Scan Async process + int16_t WiFiScanStatus = WiFi.scanComplete(); + if (WiFiScanStatus < 0) { // it is busy scanning or got an error + if (WiFiScanStatus == WIFI_SCAN_FAILED) { + Serial.println("WiFi Scan has failed. Starting again."); + startWiFiScan(); + } + // other option is status WIFI_SCAN_RUNNING - just wait. + } else { // Found Zero or more Wireless Networks + printScannedNetworks(WiFiScanStatus); + startWiFiScan(); // start over... + } + + // Loop can do something else... + delay(250); + Serial.println("Loop running..."); +} diff --git a/libraries/WiFi/examples/WiFiScanAsync/ci.yml b/libraries/WiFi/examples/WiFiScanAsync/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanAsync/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/README.md b/libraries/WiFi/examples/WiFiScanDualAntenna/README.md new file mode 100644 index 0000000..9a66111 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanDualAntenna/README.md @@ -0,0 +1,66 @@ +# WiFiScan Example + +This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks and print the results. + +This example shows the basic functionality of the dual antenna capability. + +# Supported Targets + +This example is compatible with the ESP32-WROOM-DA. + +## How to Use Example + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example/Log Output + +``` +ets Jul 29 2019 12:21:46 + +rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) +configsip: 0, SPIWP:0xee +clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 +mode:DIO, clock div:1 +load:0x3fff0030,len:1412 +load:0x40078000,len:13400 +load:0x40080400,len:3672 +entry 0x400805f8 +Setup done +scan start +scan done +17 networks found +1: IoTNetwork (-62)* +2: WiFiSSID (-62)* +3: B3A7992 (-63)* +4: WiFi (-63) +5: IoTNetwork2 (-64)* +... +``` + +## Troubleshooting + +***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.*** + +* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed. +* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-WROOM-DA Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-wroom-da_datasheet_en.pdf) diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino b/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino new file mode 100644 index 0000000..4db68d8 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino @@ -0,0 +1,77 @@ +/* + * This sketch demonstrates how to scan WiFi networks. + * The API is almost the same as with the WiFi Shield library, + * the most obvious difference being the different file you need to include: + */ +#include "WiFi.h" + +/* These are the GPIOs connected to the antenna switch on the ESP32-WROOM-DA. + * Both GPIOs are not exposed to the module pins and cannot be used except to + * control the antnnas switch. + * + * For more details, see the datashhet at: + * https://www.espressif.com/sites/default/files/documentation/esp32-wroom-da_datasheet_en.pdf + */ + +#define GPIO_ANT1 2 // GPIO for antenna 1 +#define GPIO_ANT2 25 // GPIO for antenna 2 (default) + +void setup() { + bool err = false; + Serial.begin(115200); + + // Set WiFi to station mode and disconnect from an AP if it was previously connected + WiFi.mode(WIFI_STA); + + /* Attention: This is the manual procedure for the dual antenna configuration. + * If you choose the ESP32-WROOM-DA module from the Tools -> Board, this configuration + * is not necessary! + * + * Set WiFi dual antenna configuration by passing the GPIO and antenna mode for RX ant TX + */ + err = WiFi.setDualAntennaConfig(GPIO_ANT1, GPIO_ANT2, WIFI_RX_ANT_AUTO, WIFI_TX_ANT_AUTO); + + /* For more details on how to use this feature, see our docs: + * https://docs.espressif.com/projects/arduino-esp32/en/latest/api/wifi.html + */ + + if (err == false) { + Serial.println("Dual Antenna configuration failed!"); + } else { + Serial.println("Dual Antenna configuration successfully done!"); + } + + WiFi.disconnect(); + delay(100); + + Serial.println("Setup done"); +} + +void loop() { + Serial.println("scan start"); + + // WiFi.scanNetworks will return the number of networks found + int n = WiFi.scanNetworks(); + Serial.println("scan done"); + if (n == 0) { + Serial.println("no networks found"); + } else { + Serial.print(n); + Serial.println(" networks found"); + for (int i = 0; i < n; ++i) { + // Print SSID and RSSI for each network found + Serial.print(i + 1); + Serial.print(": "); + Serial.print(WiFi.SSID(i)); + Serial.print(" ("); + Serial.print(WiFi.RSSI(i)); + Serial.print(")"); + Serial.println((WiFi.encryptionType(i) == WIFI_AUTH_OPEN) ? " " : "*"); + delay(10); + } + } + Serial.println(""); + + // Wait a bit before scanning again + delay(5000); +} diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/ci.yml b/libraries/WiFi/examples/WiFiScanDualAntenna/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanDualAntenna/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiScanTime/README.md b/libraries/WiFi/examples/WiFiScanTime/README.md new file mode 100644 index 0000000..7be0e05 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanTime/README.md @@ -0,0 +1,61 @@ +# WiFiScanTime Example + +This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks with custom scan timing and print the results. + +## Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | + +## How to Use Example + +* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide). + +#### Using Arduino IDE + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. + +## Example/Log Output + +``` +Setup done +Scan start +Scan done, elapsed time: 4960 ms +17 networks found +Nr | SSID | RSSI | CH | Encryption + 1 | IoTNetwork | -62 | 1 | WPA2 + 2 | WiFiSSID | -62 | 1 | WPA2-EAP + 3 | B3A7992 | -63 | 6 | WPA+WPA2 + 4 | WiFi | -63 | 6 | WPA3 + 5 | IoTNetwork2 | -64 | 11 | WPA2+WPA3 +... +``` + +## Troubleshooting + +***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.*** + +* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed. +* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else. + +## Resources + +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf) +* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) +* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino b/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino new file mode 100644 index 0000000..93dba79 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino @@ -0,0 +1,92 @@ +/* + * This sketch demonstrates how to scan WiFi networks with custom scanning time. + * The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported. + * E.g. the return value of `encryptionType()` different because more modern encryption is supported. + */ + +/* + * WiFi scan timing parameters explained: + * + * min=0, max=0: scan dwells on each channel for 120 ms. + * min>0, max=0: scan dwells on each channel for 120 ms. + * min=0, max>0: scan dwells on each channel for max ms. + * min>0, max>0: the minimum time the scan dwells on each channel is min ms. If no AP is found during this time frame, the scan switches to the next channel. Otherwise, the scan dwells on the channel for max ms. + */ + +#include "WiFi.h" + +void wifiScan(uint16_t min_time, uint16_t max_time) { + Serial.println("Scan start"); + + // Set the minimum time per channel for active scanning. + WiFi.setScanActiveMinTime(min_time); + + // Capture the start time of the scan. + uint32_t start = millis(); + + // WiFi.scanNetworks will return the number of networks found. + // Scan networks with those options: Synchrone mode, show hidden networks, active scan, max scan time per channel. + int n = WiFi.scanNetworks(false, true, false, max_time); + Serial.printf("Scan done, elapsed time: %lu ms\n", millis() - start); + if (n == 0) { + Serial.println("no networks found"); + } else { + Serial.print(n); + Serial.println(" networks found"); + Serial.println("Nr | SSID | RSSI | CH | Encryption"); + for (int i = 0; i < n; ++i) { + // Print SSID and RSSI for each network found + Serial.printf("%2d", i + 1); + Serial.print(" | "); + Serial.printf("%-32.32s", WiFi.SSID(i).c_str()); + Serial.print(" | "); + Serial.printf("%4ld", WiFi.RSSI(i)); + Serial.print(" | "); + Serial.printf("%2ld", WiFi.channel(i)); + Serial.print(" | "); + switch (WiFi.encryptionType(i)) { + case WIFI_AUTH_OPEN: Serial.print("open"); break; + case WIFI_AUTH_WEP: Serial.print("WEP"); break; + case WIFI_AUTH_WPA_PSK: Serial.print("WPA"); break; + case WIFI_AUTH_WPA2_PSK: Serial.print("WPA2"); break; + case WIFI_AUTH_WPA_WPA2_PSK: Serial.print("WPA+WPA2"); break; + case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break; + case WIFI_AUTH_WPA3_PSK: Serial.print("WPA3"); break; + case WIFI_AUTH_WPA2_WPA3_PSK: Serial.print("WPA2+WPA3"); break; + case WIFI_AUTH_WAPI_PSK: Serial.print("WAPI"); break; + default: Serial.print("unknown"); + } + Serial.println(); + delay(10); + } + } + Serial.println(""); + + // Delete the scan result to free memory for code below. + WiFi.scanDelete(); + + // Wait a bit before scanning again + delay(2000); +} + +void setup() { + Serial.begin(115200); + + // Set WiFi to station mode and disconnect from an AP if it was previously connected. + WiFi.mode(WIFI_STA); + WiFi.disconnect(); + delay(100); + + // Scan WiFi networks with a minimum time of 100 ms per channel and a maximum time of 300 ms per channel (default values). + wifiScan(100, 300); + + // Scan WiFi networks with a minimum time of 100 ms per channel and a maximum time of 1500 ms per channel. + wifiScan(100, 1500); + + // Scan WiFi networks with a minimum time of 0 ms per channel and a maximum time of 1500 ms per channel. + wifiScan(0, 1500); +} + +void loop() { + // Nothing to do here +} diff --git a/libraries/WiFi/examples/WiFiScanTime/ci.yml b/libraries/WiFi/examples/WiFiScanTime/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiScanTime/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino b/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino new file mode 100644 index 0000000..724355c --- /dev/null +++ b/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino @@ -0,0 +1,40 @@ +#include "sdkconfig.h" +#if CONFIG_ESP_WIFI_REMOTE_ENABLED +#error "SmartConfig is only supported in SoCs with native Wi-Fi support" +#endif + +#include "WiFi.h" + +void setup() { + Serial.begin(115200); + + //Init WiFi as Station, start SmartConfig + WiFi.mode(WIFI_AP_STA); + WiFi.beginSmartConfig(); + + //Wait for SmartConfig packet from mobile + Serial.println("Waiting for SmartConfig."); + while (!WiFi.smartConfigDone()) { + delay(500); + Serial.print("."); + } + + Serial.println(""); + Serial.println("SmartConfig received."); + + //Wait for WiFi to connect to AP + Serial.println("Waiting for WiFi"); + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + + Serial.println("WiFi Connected."); + + Serial.print("IP Address: "); + Serial.println(WiFi.localIP()); +} + +void loop() { + // put your main code here, to run repeatedly: +} diff --git a/libraries/WiFi/examples/WiFiSmartConfig/ci.yml b/libraries/WiFi/examples/WiFiSmartConfig/ci.yml new file mode 100644 index 0000000..86e194b --- /dev/null +++ b/libraries/WiFi/examples/WiFiSmartConfig/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_WIFI_SUPPORTED=y diff --git a/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino new file mode 100644 index 0000000..c227da0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino @@ -0,0 +1,135 @@ +/* + WiFiTelnetToSerial - Example Transparent UART to Telnet Server for ESP32 + + Copyright (c) 2017 Hristo Gochkov. All rights reserved. + This file is part of the ESP32 WiFi library for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +#include +#include + +WiFiMulti wifiMulti; + +//how many clients should be able to telnet to this ESP32 +#define MAX_SRV_CLIENTS 1 +const char *ssid = "**********"; +const char *password = "**********"; + +NetworkServer server(23); +NetworkClient serverClients[MAX_SRV_CLIENTS]; + +void setup() { + Serial.begin(115200); + Serial.println("\nConnecting"); + + wifiMulti.addAP(ssid, password); + wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2"); + wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3"); + + Serial.println("Connecting Wifi "); + for (int loops = 10; loops > 0; loops--) { + if (wifiMulti.run() == WL_CONNECTED) { + Serial.println(""); + Serial.print("WiFi connected "); + Serial.print("IP address: "); + Serial.println(WiFi.localIP()); + break; + } else { + Serial.println(loops); + delay(1000); + } + } + if (wifiMulti.run() != WL_CONNECTED) { + Serial.println("WiFi connect failed"); + delay(1000); + ESP.restart(); + } + + //start UART and the server + Serial1.begin(9600); + server.begin(); + server.setNoDelay(true); + + Serial.print("Ready! Use 'telnet "); + Serial.print(WiFi.localIP()); + Serial.println(" 23' to connect"); +} + +void loop() { + uint8_t i; + if (wifiMulti.run() == WL_CONNECTED) { + //check if there are any new clients + if (server.hasClient()) { + for (i = 0; i < MAX_SRV_CLIENTS; i++) { + //find free/disconnected spot + if (!serverClients[i] || !serverClients[i].connected()) { + if (serverClients[i]) { + serverClients[i].stop(); + } + serverClients[i] = server.accept(); + if (!serverClients[i]) { + Serial.println("available broken"); + } + Serial.print("New client: "); + Serial.print(i); + Serial.print(' '); + Serial.println(serverClients[i].remoteIP()); + break; + } + } + if (i >= MAX_SRV_CLIENTS) { + //no free/disconnected spot so reject + server.accept().stop(); + } + } + //check clients for data + for (i = 0; i < MAX_SRV_CLIENTS; i++) { + if (serverClients[i] && serverClients[i].connected()) { + if (serverClients[i].available()) { + //get data from the telnet client and push it to the UART + while (serverClients[i].available()) { + Serial1.write(serverClients[i].read()); + } + } + } else { + if (serverClients[i]) { + serverClients[i].stop(); + } + } + } + //check UART for data + if (Serial1.available()) { + size_t len = Serial1.available(); + uint8_t sbuf[len]; + Serial1.readBytes(sbuf, len); + //push UART data to all connected telnet clients + for (i = 0; i < MAX_SRV_CLIENTS; i++) { + if (serverClients[i] && serverClients[i].connected()) { + serverClients[i].write(sbuf, len); + delay(1); + } + } + } + } else { + Serial.println("WiFi not connected!"); + for (i = 0; i < MAX_SRV_CLIENTS; i++) { + if (serverClients[i]) { + serverClients[i].stop(); + } + } + delay(1000); + } +} diff --git a/libraries/WiFi/examples/WiFiTelnetToSerial/ci.yml b/libraries/WiFi/examples/WiFiTelnetToSerial/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiTelnetToSerial/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino b/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino new file mode 100644 index 0000000..f828ca2 --- /dev/null +++ b/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino @@ -0,0 +1,76 @@ +/* + * This sketch sends random data over UDP on a ESP32 device + * + */ +#include +#include + +// WiFi network name and password: +const char *networkName = "your-ssid"; +const char *networkPswd = "your-password"; + +//IP address to send UDP data to: +// either use the ip address of the server or +// a network broadcast address +const char *udpAddress = "192.168.0.255"; +const int udpPort = 3333; + +//Are we currently connected? +boolean connected = false; + +//The udp library class +NetworkUDP udp; + +void setup() { + // Initialize hardware serial: + Serial.begin(115200); + + //Connect to the WiFi network + connectToWiFi(networkName, networkPswd); +} + +void loop() { + //only send data when connected + if (connected) { + //Send a packet + udp.beginPacket(udpAddress, udpPort); + udp.printf("Seconds since boot: %lu", millis() / 1000); + udp.endPacket(); + } + //Wait for 1 second + delay(1000); +} + +void connectToWiFi(const char *ssid, const char *pwd) { + Serial.println("Connecting to WiFi network: " + String(ssid)); + + // delete old config + WiFi.disconnect(true); + //register event handler + WiFi.onEvent(WiFiEvent); // Will call WiFiEvent() from another thread. + + //Initiate connection + WiFi.begin(ssid, pwd); + + Serial.println("Waiting for WIFI connection..."); +} + +// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)! +void WiFiEvent(WiFiEvent_t event) { + switch (event) { + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + //When connected set + Serial.print("WiFi connected! IP address: "); + Serial.println(WiFi.localIP()); + //initializes the UDP state + //This initializes the transfer buffer + udp.begin(WiFi.localIP(), udpPort); + connected = true; + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: + Serial.println("WiFi lost connection"); + connected = false; + break; + default: break; + } +} diff --git a/libraries/WiFi/examples/WiFiUDPClient/ci.yml b/libraries/WiFi/examples/WiFiUDPClient/ci.yml new file mode 100644 index 0000000..006e6e0 --- /dev/null +++ b/libraries/WiFi/examples/WiFiUDPClient/ci.yml @@ -0,0 +1,3 @@ +requires_any: + - CONFIG_SOC_WIFI_SUPPORTED=y + - CONFIG_ESP_WIFI_REMOTE_ENABLED=y diff --git a/libraries/WiFi/examples/WiFiUDPClient/udp_server.py b/libraries/WiFi/examples/WiFiUDPClient/udp_server.py new file mode 100644 index 0000000..48ab8f7 --- /dev/null +++ b/libraries/WiFi/examples/WiFiUDPClient/udp_server.py @@ -0,0 +1,124 @@ +# This python script listens on UDP port 3333 +# for messages from the ESP32 board and prints them +import socket +import sys +import subprocess +import platform + + +def get_interface_ips(): + """Get all available interface IP addresses""" + interface_ips = [] + + # Try using system commands to get interface IPs + system = platform.system().lower() + + try: + if system == "darwin" or system == "linux": + # Use 'ifconfig' on macOS/Linux + result = subprocess.run(["ifconfig"], capture_output=True, text=True, timeout=5) + if result.returncode == 0: + lines = result.stdout.split("\n") + for line in lines: + if "inet " in line and "127.0.0.1" not in line: + # Extract IP address from ifconfig output + parts = line.strip().split() + for i, part in enumerate(parts): + if part == "inet": + if i + 1 < len(parts): + ip = parts[i + 1] + if ip not in interface_ips and ip != "127.0.0.1": + interface_ips.append(ip) + break + elif system == "windows": + # Use 'ipconfig' on Windows + result = subprocess.run(["ipconfig"], capture_output=True, text=True, timeout=5) + if result.returncode == 0: + lines = result.stdout.split("\n") + for line in lines: + if "IPv4 Address" in line and "127.0.0.1" not in line: + # Extract IP address from ipconfig output + if ":" in line: + ip = line.split(":")[1].strip() + if ip not in interface_ips and ip != "127.0.0.1": + interface_ips.append(ip) + except (subprocess.TimeoutExpired, subprocess.SubprocessError, FileNotFoundError): + print("Error: Failed to get interface IPs using system commands") + print("Trying fallback methods...") + + # Fallback: try to get IPs using socket methods + if not interface_ips: + try: + # Get all IP addresses associated with the hostname + hostname = socket.gethostname() + ip_list = socket.gethostbyname_ex(hostname)[2] + for ip in ip_list: + if ip not in interface_ips and ip != "127.0.0.1": + interface_ips.append(ip) + except socket.gaierror: + print("Error: Failed to get interface IPs using sockets") + + # Fail if no interfaces found + if not interface_ips: + print("Error: No network interfaces found. Please check your network configuration.") + sys.exit(1) + + return interface_ips + + +def select_interface(interface_ips): + """Ask user to select which interface to bind to""" + if len(interface_ips) == 1: + print(f"Using interface: {interface_ips[0]}") + return interface_ips[0] + + print("Multiple network interfaces detected:") + for i, ip in enumerate(interface_ips, 1): + print(f" {i}. {ip}") + + while True: + try: + choice = input(f"Select interface (1-{len(interface_ips)}): ").strip() + choice_idx = int(choice) - 1 + if 0 <= choice_idx < len(interface_ips): + selected_ip = interface_ips[choice_idx] + print(f"Selected interface: {selected_ip}") + return selected_ip + else: + print(f"Please enter a number between 1 and {len(interface_ips)}") + except ValueError: + print("Please enter a valid number") + except KeyboardInterrupt: + print("\nExiting...") + sys.exit(1) + + +try: + s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + s.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1) +except socket.error as msg: + print("Failed to create socket. Error Code : " + str(msg[0]) + " Message " + msg[1]) + sys.exit() + +# Get available interfaces and let user choose +interface_ips = get_interface_ips() +selected_ip = select_interface(interface_ips) + +try: + s.bind((selected_ip, 3333)) +except socket.error as msg: + print("Bind failed. Error: " + str(msg[0]) + ": " + msg[1]) + sys.exit() + +print(f"Server listening on {selected_ip}:3333") + +while 1: + d = s.recvfrom(1024) + data = d[0] + + if not data: + break + + print(data.strip()) + +s.close() diff --git a/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb b/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb new file mode 100644 index 0000000..abcfcca --- /dev/null +++ b/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb @@ -0,0 +1,16 @@ +# This ruby script listens on UDP port 3333 +# for messages from the ESP32 board and prints them + +require 'socket' +include Socket::Constants + +udp_socket = UDPSocket.new(AF_INET) + +#bind +udp_socket.bind("", 3333) +puts 'Server listening' + +while true do + message, sender = udp_socket.recvfrom(1024) + puts message +end diff --git a/libraries/WiFi/keywords.txt b/libraries/WiFi/keywords.txt new file mode 100644 index 0000000..08b970b --- /dev/null +++ b/libraries/WiFi/keywords.txt @@ -0,0 +1,68 @@ +####################################### +# Syntax Coloring Map For WiFi +####################################### + +####################################### +# Library (KEYWORD3) +####################################### + +WiFi KEYWORD3 + +####################################### +# Datatypes (KEYWORD1) +####################################### + +WiFi KEYWORD1 +NetworkClient KEYWORD1 +NetworkServer KEYWORD1 +NetworkUDP KEYWORD1 +NetworkClientSecure KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +status KEYWORD2 +mode KEYWORD2 +connect KEYWORD2 +write KEYWORD2 +available KEYWORD2 +config KEYWORD2 +setDNS KEYWORD2 +read KEYWORD2 +flush KEYWORD2 +stop KEYWORD2 +connected KEYWORD2 +begin KEYWORD2 +beginMulticast KEYWORD2 +disconnect KEYWORD2 +macAddress KEYWORD2 +localIP KEYWORD2 +subnetMask KEYWORD2 +gatewayIP KEYWORD2 +SSID KEYWORD2 +psk KEYWORD2 +BSSID KEYWORD2 +RSSI KEYWORD2 +encryptionType KEYWORD2 +beginPacket KEYWORD2 +beginPacketMulticast KEYWORD2 +endPacket KEYWORD2 +parsePacket KEYWORD2 +destinationIP KEYWORD2 +remoteIP KEYWORD2 +remotePort KEYWORD2 +softAP KEYWORD2 +softAPIP KEYWORD2 +softAPmacAddress KEYWORD2 +softAPConfig KEYWORD2 +printDiag KEYWORD2 +hostByName KEYWORD2 +scanNetworks KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### +WIFI_AP LITERAL1 +WIFI_STA LITERAL1 +WIFI_AP_STA LITERAL1 diff --git a/libraries/WiFi/library.properties b/libraries/WiFi/library.properties new file mode 100644 index 0000000..3b03232 --- /dev/null +++ b/libraries/WiFi/library.properties @@ -0,0 +1,9 @@ +name=WiFi +version=3.3.7 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Enables network connection (local and Internet) using the ESP32 built-in WiFi. +paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through WiFi. The shield can connect either to open or encrypted networks. The IP address can be assigned statically or through a DHCP. The library can also manage DNS. +category=Communication +url= +architectures=esp32 diff --git a/libraries/WiFi/src/AP.cpp b/libraries/WiFi/src/AP.cpp new file mode 100644 index 0000000..51229cf --- /dev/null +++ b/libraries/WiFi/src/AP.cpp @@ -0,0 +1,418 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiAP.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dhcpserver/dhcpserver_options.h" +#include "esp_netif.h" + +esp_netif_t *get_esp_interface_netif(esp_interface_t interface); + +static size_t _wifi_strncpy(char *dst, const char *src, size_t dst_len) { + if (!dst || !src || !dst_len) { + return 0; + } + size_t src_len = strlen(src); + if (src_len >= dst_len) { + src_len = dst_len; + } else { + src_len += 1; + } + memcpy(dst, src, src_len); + return src_len; +} + +/** + * compare two AP configurations + * @param lhs softap_config + * @param rhs softap_config + * @return equal + */ +static bool softap_config_equal(const wifi_config_t &lhs, const wifi_config_t &rhs) { + if (strncmp(reinterpret_cast(lhs.ap.ssid), reinterpret_cast(rhs.ap.ssid), 32) != 0) { + return false; + } + if (strncmp(reinterpret_cast(lhs.ap.password), reinterpret_cast(rhs.ap.password), 64) != 0) { + return false; + } + if (lhs.ap.channel != rhs.ap.channel) { + return false; + } + if (lhs.ap.authmode != rhs.ap.authmode) { + return false; + } + if (lhs.ap.ssid_hidden != rhs.ap.ssid_hidden) { + return false; + } + if (lhs.ap.max_connection != rhs.ap.max_connection) { + return false; + } + if (lhs.ap.pairwise_cipher != rhs.ap.pairwise_cipher) { + return false; + } + if (lhs.ap.ftm_responder != rhs.ap.ftm_responder) { + return false; + } + return true; +} + +static APClass *_ap_network_if = NULL; + +static esp_event_handler_instance_t _ap_ev_instance = NULL; +static void _ap_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) { + if (event_base == WIFI_EVENT) { + ((APClass *)arg)->_onApEvent(event_id, event_data); + } +} + +static void _onApArduinoEvent(arduino_event_t *ev) { + if (_ap_network_if == NULL || ev->event_id < ARDUINO_EVENT_WIFI_AP_START || ev->event_id > ARDUINO_EVENT_WIFI_AP_GOT_IP6) { + return; + } + log_v("Arduino AP Event: %d - %s", ev->event_id, Network.eventName(ev->event_id)); + if (ev->event_id == ARDUINO_EVENT_WIFI_AP_START) { +#if CONFIG_LWIP_IPV6 + if (_ap_network_if->getStatusBits() & ESP_NETIF_WANT_IP6_BIT) { + esp_err_t err = esp_netif_create_ip6_linklocal(_ap_network_if->netif()); + if (err != ESP_OK) { + log_e("Failed to enable IPv6 Link Local on AP: 0x%x: %s", err, esp_err_to_name(err)); + } else { + log_v("Enabled IPv6 Link Local on %s", _ap_network_if->desc()); + } + } +#endif + } +} + +void APClass::_onApEvent(int32_t event_id, void *event_data) { + arduino_event_t arduino_event; + arduino_event.event_id = ARDUINO_EVENT_MAX; + + if (event_id == WIFI_EVENT_AP_START) { + log_v("AP Started"); + arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_START; + setStatusBits(ESP_NETIF_STARTED_BIT); + } else if (event_id == WIFI_EVENT_AP_STOP) { + log_v("AP Stopped"); + arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STOP; + clearStatusBits(ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT); + } else if (event_id == WIFI_EVENT_AP_PROBEREQRECVED) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_ap_probe_req_rx_t *event = (wifi_event_ap_probe_req_rx_t *)event_data; + log_v("AP Probe Request: RSSI: %d, MAC: " MACSTR, event->rssi, MAC2STR(event->mac)); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED; + memcpy(&arduino_event.event_info.wifi_ap_probereqrecved, event_data, sizeof(wifi_event_ap_probe_req_rx_t)); + } else if (event_id == WIFI_EVENT_AP_STACONNECTED) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_ap_staconnected_t *event = (wifi_event_ap_staconnected_t *)event_data; + log_v("AP Station Connected: MAC: " MACSTR ", AID: %d", MAC2STR(event->mac), event->aid); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STACONNECTED; + memcpy(&arduino_event.event_info.wifi_ap_staconnected, event_data, sizeof(wifi_event_ap_staconnected_t)); + setStatusBits(ESP_NETIF_CONNECTED_BIT); + } else if (event_id == WIFI_EVENT_AP_STADISCONNECTED) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_ap_stadisconnected_t *event = (wifi_event_ap_stadisconnected_t *)event_data; + log_v("AP Station Disconnected: MAC: " MACSTR ", AID: %d", MAC2STR(event->mac), event->aid); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STADISCONNECTED; + memcpy(&arduino_event.event_info.wifi_ap_stadisconnected, event_data, sizeof(wifi_event_ap_stadisconnected_t)); + // If no more clients are left + wifi_sta_list_t clients; + if (esp_wifi_ap_get_sta_list(&clients) != ESP_OK || clients.num == 0) { + clearStatusBits(ESP_NETIF_CONNECTED_BIT); + } + } else { + return; + } + + if (arduino_event.event_id < ARDUINO_EVENT_MAX) { + Network.postEvent(&arduino_event); + } +} + +APClass::APClass() : _wifi_ap_event_handle(0) { + _ap_network_if = this; +} + +APClass::~APClass() { + end(); + _ap_network_if = NULL; +} + +bool APClass::onEnable() { + if (_ap_ev_instance == NULL && esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_ap_event_cb, this, &_ap_ev_instance)) { + log_e("event_handler_instance_register for WIFI_EVENT Failed!"); + return false; + } + if (_esp_netif == NULL) { + _wifi_ap_event_handle = Network.onSysEvent(_onApArduinoEvent); + _esp_netif = get_esp_interface_netif(ESP_IF_WIFI_AP); + /* attach to receive events */ + initNetif(ESP_NETIF_ID_AP); + } + return true; +} + +bool APClass::onDisable() { + Network.removeEvent(_wifi_ap_event_handle); + _wifi_ap_event_handle = 0; + // we just set _esp_netif to NULL here, so destroyNetif() does not try to destroy it. + // That would be done by WiFi.enableAP(false) if STA is not enabled, or when it gets disabled + _esp_netif = NULL; + destroyNetif(); + if (_ap_ev_instance != NULL) { + esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_ap_event_cb); + _ap_ev_instance = NULL; + } + return true; +} + +bool APClass::begin() { + if (!WiFi.enableAP(true)) { + log_e("AP enable failed!"); + return false; + } + if (!waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) { + log_e("Failed to start AP!"); + return false; + } + return true; +} + +bool APClass::end() { + if (!WiFi.enableAP(false)) { + log_e("AP disable failed!"); + return false; + } + return true; +} + +bool APClass::create( + const char *ssid, const char *passphrase, int channel, int ssid_hidden, int max_connection, bool ftm_responder, wifi_auth_mode_t auth_mode, + wifi_cipher_type_t cipher +) { + if (!ssid || *ssid == 0) { + log_e("SSID missing!"); + return false; + } + + if (passphrase && (strlen(passphrase) > 0 && strlen(passphrase) < 8)) { + log_e("passphrase too short!"); + return false; + } + + if (!begin()) { + return false; + } + + wifi_config_t conf; + memset(&conf, 0, sizeof(wifi_config_t)); + conf.ap.channel = channel; + conf.ap.max_connection = max_connection; + conf.ap.beacon_interval = 100; + conf.ap.ssid_hidden = ssid_hidden; + conf.ap.ftm_responder = ftm_responder; + if (ssid != NULL && ssid[0] != 0) { + _wifi_strncpy((char *)conf.ap.ssid, ssid, 32); + conf.ap.ssid_len = strlen(ssid); + if (passphrase != NULL && passphrase[0] != 0) { + conf.ap.authmode = auth_mode; + conf.ap.pairwise_cipher = cipher; + _wifi_strncpy((char *)conf.ap.password, passphrase, 64); + } + } + + wifi_config_t conf_current; + esp_err_t err = esp_wifi_get_config(WIFI_IF_AP, &conf_current); + if (err) { + log_e("Get AP config failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + if (!softap_config_equal(conf, conf_current)) { + err = esp_wifi_set_config(WIFI_IF_AP, &conf); + if (err) { + log_e("Set AP config failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + } + + return true; +} + +bool APClass::clear() { + if (!begin()) { + return false; + } + wifi_config_t conf; + memset(&conf, 0, sizeof(wifi_config_t)); + conf.ap.channel = 1; + conf.ap.max_connection = 4; + conf.ap.beacon_interval = 100; + esp_err_t err = esp_wifi_set_config(WIFI_IF_AP, &conf); + if (err) { + log_e("Set AP config failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; +} + +bool APClass::bandwidth(wifi_bandwidth_t bandwidth) { + if (!begin()) { + return false; + } + esp_err_t err = esp_wifi_set_bandwidth(WIFI_IF_AP, bandwidth); + if (err) { + log_e("Could not set AP bandwidth! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + return true; +} + +bool APClass::enableNAPT(bool enable) { + if (!started()) { + log_e("AP must be first started to enable/disable NAPT"); + return false; + } + esp_err_t err = ESP_OK; + if (enable) { + err = esp_netif_napt_enable(_esp_netif); + } else { + err = esp_netif_napt_disable(_esp_netif); + } + if (err) { + log_e("Could not set enable/disable NAPT! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; +} + +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) +bool APClass::enableDhcpCaptivePortal() { + esp_err_t err = ESP_OK; + static char captiveportal_uri[32] = { + 0, + }; + + if (!started()) { + log_e("AP must be first started to enable DHCP Captive Portal"); + return false; + } + + // Create Captive Portal URL: http://192.168.0.4 + strcpy(captiveportal_uri, "http://"); + strcat(captiveportal_uri, localIP().toString().c_str()); + log_i("DHCP Captive Portal URL: %s", captiveportal_uri); + + // Stop DHCPS + err = esp_netif_dhcps_stop(_esp_netif); + if (err && err != ESP_ERR_ESP_NETIF_DHCP_ALREADY_STOPPED) { + log_e("DHCPS Stop Failed! 0x%04x: %s", err, esp_err_to_name(err)); + return false; + } + + // Enable DHCP Captive Portal + err = esp_netif_dhcps_option(_esp_netif, ESP_NETIF_OP_SET, ESP_NETIF_CAPTIVEPORTAL_URI, captiveportal_uri, strlen(captiveportal_uri)); + if (err) { + log_e("Could not set enable DHCP Captive Portal! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + // Start DHCPS + err = esp_netif_dhcps_start(_esp_netif); + if (err) { + log_e("DHCPS Start Failed! 0x%04x: %s", err, esp_err_to_name(err)); + return false; + } + + return true; +} +#endif + +String APClass::SSID(void) const { + if (!started()) { + return String(); + } + wifi_config_t info; + if (!esp_wifi_get_config(WIFI_IF_AP, &info)) { + return String(reinterpret_cast(info.ap.ssid)); + } + return String(); +} + +uint8_t APClass::stationCount() { + wifi_sta_list_t clients; + if (!started()) { + return 0; + } + if (esp_wifi_ap_get_sta_list(&clients) == ESP_OK) { + return clients.num; + } + return 0; +} + +size_t APClass::printDriverInfo(Print &out) const { + size_t bytes = 0; + wifi_config_t info; + wifi_sta_list_t clients; + if (!started()) { + return bytes; + } + if (esp_wifi_get_config(WIFI_IF_AP, &info) != ESP_OK) { + return bytes; + } + bytes += out.print(","); + bytes += out.print((const char *)info.ap.ssid); + bytes += out.print(",CH:"); + bytes += out.print(info.ap.channel); + + if (info.ap.authmode == WIFI_AUTH_OPEN) { + bytes += out.print(",OPEN"); + } else if (info.ap.authmode == WIFI_AUTH_WEP) { + bytes += out.print(",WEP"); + } else if (info.ap.authmode == WIFI_AUTH_WPA_PSK) { + bytes += out.print(",WPA_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_WPA2_PSK) { + bytes += out.print(",WPA2_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_WPA_WPA2_PSK) { + bytes += out.print(",WPA_WPA2_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_ENTERPRISE) { + bytes += out.print(",WEAP"); + } else if (info.ap.authmode == WIFI_AUTH_WPA3_PSK) { + bytes += out.print(",WPA3_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_WPA2_WPA3_PSK) { + bytes += out.print(",WPA2_WPA3_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_WAPI_PSK) { + bytes += out.print(",WAPI_PSK"); + } else if (info.ap.authmode == WIFI_AUTH_OWE) { + bytes += out.print(",OWE"); + } else if (info.ap.authmode == WIFI_AUTH_WPA3_ENT_192) { + bytes += out.print(",WPA3_ENT_SUITE_B_192_BIT"); + } + + if (esp_wifi_ap_get_sta_list(&clients) == ESP_OK) { + bytes += out.print(",STA:"); + bytes += out.print(clients.num); + } + return bytes; +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/STA.cpp b/libraries/WiFi/src/STA.cpp new file mode 100644 index 0000000..7676d90 --- /dev/null +++ b/libraries/WiFi/src/STA.cpp @@ -0,0 +1,800 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiSTA.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/err.h" +#include "lwip/dns.h" +#include +#include +#include "esp_mac.h" + +#if __has_include("esp_eap_client.h") +#include "esp_eap_client.h" +#else +#include "esp_wpa2.h" +#endif + +esp_netif_t *get_esp_interface_netif(esp_interface_t interface); + +static size_t _wifi_strncpy(char *dst, const char *src, size_t dst_len) { + if (!dst || !src || !dst_len) { + return 0; + } + size_t src_len = strlen(src); + if (src_len >= dst_len) { + src_len = dst_len; + } else { + src_len += 1; + } + memcpy(dst, src, src_len); + return src_len; +} + +static STAClass *_sta_network_if = NULL; + +static esp_event_handler_instance_t _sta_ev_instance = NULL; +static void _sta_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) { + if (event_base == WIFI_EVENT) { + ((STAClass *)arg)->_onStaEvent(event_id, event_data); + } +} + +static bool _is_staReconnectableReason(uint8_t reason) { + switch (reason) { + case WIFI_REASON_UNSPECIFIED: + //Timeouts (retry) + case WIFI_REASON_AUTH_EXPIRE: + case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT: + case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT: + case WIFI_REASON_802_1X_AUTH_FAILED: + case WIFI_REASON_HANDSHAKE_TIMEOUT: + //Transient error (reconnect) + case WIFI_REASON_AUTH_LEAVE: + case WIFI_REASON_ASSOC_EXPIRE: + case WIFI_REASON_ASSOC_TOOMANY: + case WIFI_REASON_NOT_AUTHED: + case WIFI_REASON_NOT_ASSOCED: + case WIFI_REASON_ASSOC_NOT_AUTHED: + case WIFI_REASON_MIC_FAILURE: + case WIFI_REASON_IE_IN_4WAY_DIFFERS: + case WIFI_REASON_INVALID_PMKID: + case WIFI_REASON_BEACON_TIMEOUT: + case WIFI_REASON_NO_AP_FOUND: + case WIFI_REASON_ASSOC_FAIL: + case WIFI_REASON_CONNECTION_FAIL: + case WIFI_REASON_AP_TSF_RESET: + case WIFI_REASON_ROAMING: return true; + default: return false; + } +} + +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE +static const char *auth_mode_str(int authmode) { + switch (authmode) { + case WIFI_AUTH_OPEN: return ("OPEN"); break; + case WIFI_AUTH_WEP: return ("WEP"); break; + case WIFI_AUTH_WPA_PSK: return ("WPA_PSK"); break; + case WIFI_AUTH_WPA2_PSK: return ("WPA2_PSK"); break; + case WIFI_AUTH_WPA_WPA2_PSK: return ("WPA_WPA2_PSK"); break; + case WIFI_AUTH_WPA2_ENTERPRISE: return ("WPA2_ENTERPRISE"); break; + case WIFI_AUTH_WPA3_PSK: return ("WPA3_PSK"); break; + case WIFI_AUTH_WPA2_WPA3_PSK: return ("WPA2_WPA3_PSK"); break; + case WIFI_AUTH_WAPI_PSK: return ("WPAPI_PSK"); break; + default: break; + } + return ("UNKNOWN"); +} +#endif + +static void _onStaArduinoEvent(arduino_event_t *ev) { + if (_sta_network_if == NULL || ev->event_id < ARDUINO_EVENT_WIFI_STA_START || ev->event_id > ARDUINO_EVENT_WIFI_STA_LOST_IP) { + return; + } + static bool first_connect = true; + log_v("Arduino STA Event: %d - %s", ev->event_id, Network.eventName(ev->event_id)); + + if (ev->event_id == ARDUINO_EVENT_WIFI_STA_START) { + _sta_network_if->_setStatus(WL_DISCONNECTED); + if (esp_wifi_set_ps(WiFi.getSleep()) != ESP_OK) { + log_e("esp_wifi_set_ps failed"); + } + } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_STOP) { + _sta_network_if->_setStatus(WL_STOPPED); + } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_CONNECTED) { + _sta_network_if->_setStatus(WL_IDLE_STATUS); +#if CONFIG_LWIP_IPV6 + if (_sta_network_if->getStatusBits() & ESP_NETIF_WANT_IP6_BIT) { + esp_err_t err = esp_netif_create_ip6_linklocal(_sta_network_if->netif()); + if (err != ESP_OK) { + log_e("Failed to enable IPv6 Link Local on STA: 0x%x: %s", err, esp_err_to_name(err)); + } else { + log_v("Enabled IPv6 Link Local on %s", _sta_network_if->desc()); + } + } +#endif + } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_DISCONNECTED) { + uint8_t reason = ev->event_info.wifi_sta_disconnected.reason; + // Reason 0 causes crash, use reason 1 (UNSPECIFIED) instead + if (!reason) { + reason = WIFI_REASON_UNSPECIFIED; + } + log_w("Reason: %u - %s", reason, WiFi.STA.disconnectReasonName((wifi_err_reason_t)reason)); + if (reason == WIFI_REASON_NO_AP_FOUND) { + _sta_network_if->_setStatus(WL_NO_SSID_AVAIL); + } else if ((reason == WIFI_REASON_AUTH_FAIL) && !first_connect) { + _sta_network_if->_setStatus(WL_CONNECT_FAILED); + } else if (reason == WIFI_REASON_BEACON_TIMEOUT || reason == WIFI_REASON_HANDSHAKE_TIMEOUT) { + _sta_network_if->_setStatus(WL_CONNECTION_LOST); + } else if (reason == WIFI_REASON_AUTH_EXPIRE) { + + } else { + _sta_network_if->_setStatus(WL_DISCONNECTED); + } + + bool DoReconnect = false; + if (reason == WIFI_REASON_ASSOC_LEAVE) { //Voluntarily disconnected. Don't reconnect! + } else if (first_connect) { //Retry once for all failure reasons + first_connect = false; + DoReconnect = true; + log_d("WiFi Reconnect Running"); + } else if (_sta_network_if->getAutoReconnect() && _is_staReconnectableReason(reason)) { + DoReconnect = true; + log_d("WiFi AutoReconnect Running"); + } else if (reason == WIFI_REASON_ASSOC_FAIL) { + _sta_network_if->_setStatus(WL_CONNECT_FAILED); + } + if (DoReconnect) { + _sta_network_if->disconnect(); + _sta_network_if->connect(); + } + } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_GOT_IP) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + uint8_t *ip = (uint8_t *)&(ev->event_info.got_ip.ip_info.ip.addr); + uint8_t *mask = (uint8_t *)&(ev->event_info.got_ip.ip_info.netmask.addr); + uint8_t *gw = (uint8_t *)&(ev->event_info.got_ip.ip_info.gw.addr); + log_v( + "STA IP: %u.%u.%u.%u, MASK: %u.%u.%u.%u, GW: %u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3], mask[0], mask[1], mask[2], mask[3], gw[0], gw[1], gw[2], gw[3] + ); +#endif + _sta_network_if->_setStatus(WL_CONNECTED); + } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_LOST_IP) { + _sta_network_if->_setStatus(WL_IDLE_STATUS); + } +} + +void STAClass::_onStaEvent(int32_t event_id, void *event_data) { + arduino_event_t arduino_event; + arduino_event.event_id = ARDUINO_EVENT_MAX; + + if (event_id == WIFI_EVENT_STA_START) { + log_v("STA Started"); + arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_START; + setStatusBits(ESP_NETIF_STARTED_BIT); + } else if (event_id == WIFI_EVENT_STA_STOP) { + log_v("STA Stopped"); + arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_STOP; + clearStatusBits( + ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT + | ESP_NETIF_HAS_STATIC_IP_BIT + ); + } else if (event_id == WIFI_EVENT_STA_AUTHMODE_CHANGE) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_sta_authmode_change_t *event = (wifi_event_sta_authmode_change_t *)event_data; + log_v("STA Auth Mode Changed: From: %s, To: %s", auth_mode_str(event->old_mode), auth_mode_str(event->new_mode)); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE; + memcpy(&arduino_event.event_info.wifi_sta_authmode_change, event_data, sizeof(wifi_event_sta_authmode_change_t)); + } else if (event_id == WIFI_EVENT_STA_CONNECTED) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_sta_connected_t *event = (wifi_event_sta_connected_t *)event_data; + log_v( + "STA Connected: SSID: %s, BSSID: " MACSTR ", Channel: %u, Auth: %s", event->ssid, MAC2STR(event->bssid), event->channel, auth_mode_str(event->authmode) + ); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_CONNECTED; + memcpy(&arduino_event.event_info.wifi_sta_connected, event_data, sizeof(wifi_event_sta_connected_t)); + setStatusBits(ESP_NETIF_CONNECTED_BIT); + } else if (event_id == WIFI_EVENT_STA_DISCONNECTED) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_sta_disconnected_t *event = (wifi_event_sta_disconnected_t *)event_data; + log_v("STA Disconnected: SSID: %s, BSSID: " MACSTR ", Reason: %u", event->ssid, MAC2STR(event->bssid), event->reason); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_DISCONNECTED; + memcpy(&arduino_event.event_info.wifi_sta_disconnected, event_data, sizeof(wifi_event_sta_disconnected_t)); + clearStatusBits(ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT); + } else { + return; + } + + if (arduino_event.event_id < ARDUINO_EVENT_MAX) { + Network.postEvent(&arduino_event); + } +} + +STAClass::STAClass() + : _minSecurity(WIFI_AUTH_WPA2_PSK), _scanMethod(WIFI_FAST_SCAN), _sortMethod(WIFI_CONNECT_AP_BY_SIGNAL), _autoReconnect(true), _status(WL_STOPPED), + _wifi_sta_event_handle(0) { + _sta_network_if = this; +} + +STAClass::~STAClass() { + end(); + _sta_network_if = NULL; +} + +wl_status_t STAClass::status() { + return _status; +} + +void STAClass::_setStatus(wl_status_t status) { + _status = status; +} + +/** + * Sets the working bandwidth of the STA mode + * @param m wifi_bandwidth_t + */ +bool STAClass::bandwidth(wifi_bandwidth_t bandwidth) { + if (!begin()) { + return false; + } + + esp_err_t err; + err = esp_wifi_set_bandwidth(WIFI_IF_STA, bandwidth); + if (err) { + log_e("Could not set STA bandwidth! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + return true; +} + +bool STAClass::onEnable() { + if (_sta_ev_instance == NULL && esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_sta_event_cb, this, &_sta_ev_instance)) { + log_e("event_handler_instance_register for WIFI_EVENT Failed!"); + return false; + } + if (_esp_netif == NULL) { + _esp_netif = get_esp_interface_netif(ESP_IF_WIFI_STA); + if (_esp_netif == NULL) { + log_e("STA was enabled, but netif is NULL???"); + return false; + } + /* attach to receive events */ + _wifi_sta_event_handle = Network.onSysEvent(_onStaArduinoEvent); + initNetif(ESP_NETIF_ID_STA); + } + return true; +} + +bool STAClass::onDisable() { + Network.removeEvent(_wifi_sta_event_handle); + _wifi_sta_event_handle = 0; + // we just set _esp_netif to NULL here, so destroyNetif() does not try to destroy it. + // That would be done by WiFi.enableSTA(false) if AP is not enabled, or when it gets disabled + _esp_netif = NULL; + destroyNetif(); + if (_sta_ev_instance != NULL) { + esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_sta_event_cb); + _sta_ev_instance = NULL; + } + return true; +} + +bool STAClass::begin(bool tryConnect) { + if (!WiFi.enableSTA(true)) { + log_e("STA enable failed!"); + return false; + } + if (!waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) { + log_e("Failed to start STA!"); + return false; + } + if (tryConnect) { + return connect(); + } + return true; +} + +bool STAClass::end() { + if (!WiFi.enableSTA(false)) { + log_e("STA disable failed!"); + return false; + } + return true; +} + +bool STAClass::connect() { + if (_esp_netif == NULL) { + log_e("STA not started! You must call begin() first."); + return false; + } + + if (connected()) { + log_w("STA already connected."); + return true; + } + + wifi_config_t current_conf; + if (esp_wifi_get_config(WIFI_IF_STA, ¤t_conf) != ESP_OK || esp_wifi_set_config(WIFI_IF_STA, ¤t_conf) != ESP_OK) { + log_e("STA config failed"); + return false; + } + + if ((getStatusBits() & ESP_NETIF_HAS_STATIC_IP_BIT) == 0 && !config()) { + log_e("STA failed to configure dynamic IP!"); + return false; + } + + esp_err_t err = esp_wifi_connect(); + if (err) { + log_e("STA connect failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; +} + +/** + * Start Wifi connection + * if passphrase is set the most secure supported mode will be automatically selected + * @param ssid const char* Pointer to the SSID string. + * @param passphrase const char * Optional. Passphrase. Valid characters in a passphrase must be between ASCII 32-126 (decimal). + * @param bssid uint8_t[6] Optional. BSSID / MAC of AP + * @param channel Optional. Channel of AP + * @param tryConnect Optional. call connect + * @return + */ +bool STAClass::connect(const char *ssid, const char *passphrase, int32_t channel, const uint8_t *bssid, bool tryConnect) { + if (_esp_netif == NULL) { + log_e("STA not started! You must call begin() first."); + return false; + } + + if (connected()) { + log_w("STA currently connected. Disconnecting..."); + if (!disconnect(true, 1000)) { + return false; + } + } + + if (!ssid || *ssid == 0x00 || strlen(ssid) > 32) { + log_e("SSID too long or missing!"); + return false; + } + + if (passphrase && strlen(passphrase) > 64) { + log_e("passphrase too long!"); + return false; + } + + wifi_config_t conf; + memset(&conf, 0, sizeof(wifi_config_t)); + conf.sta.channel = channel; + conf.sta.scan_method = _scanMethod; + conf.sta.sort_method = _sortMethod; + conf.sta.threshold.rssi = -127; + conf.sta.pmf_cfg.capable = true; + if (ssid != NULL && ssid[0] != 0) { + _wifi_strncpy((char *)conf.sta.ssid, ssid, 32); + if (passphrase != NULL && passphrase[0] != 0) { + conf.sta.threshold.authmode = _minSecurity; + _wifi_strncpy((char *)conf.sta.password, passphrase, 64); + } + if (bssid != NULL) { + conf.sta.bssid_set = 1; + memcpy(conf.sta.bssid, bssid, 6); + } + } + + esp_err_t err = esp_wifi_set_config(WIFI_IF_STA, &conf); + if (err != ESP_OK) { + log_e("STA clear config failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + if ((getStatusBits() & ESP_NETIF_HAS_STATIC_IP_BIT) == 0 && !config()) { + log_e("STA failed to configure dynamic IP!"); + return false; + } + + if (tryConnect) { + esp_err_t err = esp_wifi_connect(); + if (err) { + log_e("STA connect failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + } + return true; +} + +#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT +/** + * Start Wifi connection with a WPA2 Enterprise AP + * if passphrase is set the most secure supported mode will be automatically selected + * @param ssid const char* Pointer to the SSID string. + * @param method wpa2_method_t The authentication method of WPA2 (WPA2_AUTH_TLS, WPA2_AUTH_PEAP, WPA2_AUTH_TTLS) + * @param wpa2_identity const char* Pointer to the entity + * @param wpa2_username const char* Pointer to the username + * @param password const char * Pointer to the password. + * @param ca_pem const char* Pointer to a string with the contents of a .pem file with CA cert + * @param client_crt const char* Pointer to a string with the contents of a .crt file with client cert + * @param client_key const char* Pointer to a string with the contents of a .key file with client key + * @param bssid uint8_t[6] Optional. BSSID / MAC of AP + * @param channel Optional. Channel of AP + * @param tryConnect Optional. call connect + * @return + */ +bool STAClass::connect( + const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity, const char *wpa2_username, const char *wpa2_password, const char *ca_pem, + const char *client_crt, const char *client_key, int ttls_phase2_type, int32_t channel, const uint8_t *bssid, bool tryConnect +) { + if (_esp_netif == NULL) { + log_e("STA not started! You must call begin() first."); + return false; + } + + if (connected()) { + log_w("STA currently connected. Disconnecting..."); + if (!disconnect(true, 1000)) { + return false; + } + } + + if (!wpa2_ssid || *wpa2_ssid == 0x00 || strlen(wpa2_ssid) > 32) { + log_e("SSID too long or missing!"); + return false; + } + + if (wpa2_identity && strlen(wpa2_identity) > 64) { + log_e("identity too long!"); + return false; + } + + if (wpa2_username && strlen(wpa2_username) > 64) { + log_e("username too long!"); + return false; + } + + if (wpa2_password && strlen(wpa2_password) > 64) { + log_e("password too long!"); + return false; + } + + if (ttls_phase2_type >= 0) { +#if __has_include("esp_eap_client.h") + esp_eap_client_set_ttls_phase2_method((esp_eap_ttls_phase2_types)ttls_phase2_type); +#else + esp_wifi_sta_wpa2_ent_set_ttls_phase2_method((esp_eap_ttls_phase2_types)ttls_phase2_type); +#endif + } + + if (ca_pem) { +#if __has_include("esp_eap_client.h") + esp_eap_client_set_ca_cert((uint8_t *)ca_pem, strlen(ca_pem)); +#else + esp_wifi_sta_wpa2_ent_set_ca_cert((uint8_t *)ca_pem, strlen(ca_pem)); +#endif + } + + if (client_crt) { +#if __has_include("esp_eap_client.h") + esp_eap_client_set_certificate_and_key((uint8_t *)client_crt, strlen(client_crt), (uint8_t *)client_key, strlen(client_key), NULL, 0); +#else + esp_wifi_sta_wpa2_ent_set_cert_key((uint8_t *)client_crt, strlen(client_crt), (uint8_t *)client_key, strlen(client_key), NULL, 0); +#endif + } + +#if __has_include("esp_eap_client.h") + esp_eap_client_set_identity((uint8_t *)wpa2_identity, strlen(wpa2_identity)); +#else + esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)wpa2_identity, strlen(wpa2_identity)); +#endif + if (method == WPA2_AUTH_PEAP || method == WPA2_AUTH_TTLS) { +#if __has_include("esp_eap_client.h") + esp_eap_client_set_username((uint8_t *)wpa2_username, strlen(wpa2_username)); + esp_eap_client_set_password((uint8_t *)wpa2_password, strlen(wpa2_password)); +#else + esp_wifi_sta_wpa2_ent_set_username((uint8_t *)wpa2_username, strlen(wpa2_username)); + esp_wifi_sta_wpa2_ent_set_password((uint8_t *)wpa2_password, strlen(wpa2_password)); +#endif + } +#if __has_include("esp_eap_client.h") + esp_wifi_sta_enterprise_enable(); //set config settings to enable function +#else + esp_wifi_sta_wpa2_ent_enable(); //set config settings to enable function +#endif + + return connect(wpa2_ssid, NULL, channel, bssid, tryConnect); //connect to wifi +} +#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */ + +bool STAClass::disconnect(bool eraseap, unsigned long timeout) { + esp_err_t err = esp_wifi_disconnect(); + if (err != ESP_OK) { + log_e("STA disconnect failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + if (timeout) { + const unsigned long start = millis(); + while (connected() && ((millis() - start) < timeout)) { + delay(5); + } + if (connected()) { + return false; + } + } + + if (eraseap) { + if (!started()) { + log_e("STA not started! You must call begin first."); + return false; + } + wifi_config_t conf; + memset(&conf, 0, sizeof(wifi_config_t)); + esp_err_t err = esp_wifi_set_config(WIFI_IF_STA, &conf); + if (err != ESP_OK) { + log_e("STA clear config failed! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + } + + return true; +} + +bool STAClass::reconnect() { + if (connected()) { + if (esp_wifi_disconnect() != ESP_OK) { + return false; + } + } + return esp_wifi_connect() == ESP_OK; +} + +bool STAClass::erase() { + if (!started()) { + log_e("STA not started! You must call begin first."); + return false; + } + return esp_wifi_restore() == ESP_OK; +} + +uint8_t STAClass::waitForConnectResult(unsigned long timeoutLength) { + //1 and 3 have STA enabled + if ((WiFiGenericClass::getMode() & WIFI_MODE_STA) == 0) { + return WL_DISCONNECTED; + } + unsigned long start = millis(); + while ((!status() || status() >= WL_DISCONNECTED) && (millis() - start) < timeoutLength) { + delay(100); + } + return status(); +} + +bool STAClass::setAutoReconnect(bool autoReconnect) { + _autoReconnect = autoReconnect; + return true; +} + +bool STAClass::getAutoReconnect() { + return _autoReconnect; +} + +void STAClass::setMinSecurity(wifi_auth_mode_t minSecurity) { + _minSecurity = minSecurity; +} + +void STAClass::setScanMethod(wifi_scan_method_t scanMethod) { + _scanMethod = scanMethod; +} + +void STAClass::setSortMethod(wifi_sort_method_t sortMethod) { + _sortMethod = sortMethod; +} + +String STAClass::SSID() const { + if (!started()) { + return String(); + } + wifi_ap_record_t info; + if (!esp_wifi_sta_get_ap_info(&info)) { + return String(reinterpret_cast(info.ssid)); + } + return String(); +} + +String STAClass::psk() const { + if (!started()) { + return String(); + } + wifi_config_t conf; + esp_wifi_get_config((wifi_interface_t)ESP_IF_WIFI_STA, &conf); + return String(reinterpret_cast(conf.sta.password)); +} + +uint8_t *STAClass::BSSID(uint8_t *buff) { + static uint8_t bssid[6]; + wifi_ap_record_t info; + if (!started()) { + return NULL; + } + esp_err_t err = esp_wifi_sta_get_ap_info(&info); + if (buff != NULL) { + if (err) { + memset(buff, 0, 6); + } else { + memcpy(buff, info.bssid, 6); + } + return buff; + } + if (!err) { + memcpy(bssid, info.bssid, 6); + return reinterpret_cast(bssid); + } + return NULL; +} + +String STAClass::BSSIDstr() { + uint8_t *bssid = BSSID(); + if (!bssid) { + return String(); + } + char mac[18] = {0}; + sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + return String(mac); +} + +int8_t STAClass::RSSI() { + if (!started()) { + return 0; + } + wifi_ap_record_t info; + if (!esp_wifi_sta_get_ap_info(&info)) { + return info.rssi; + } + return 0; +} + +size_t STAClass::printDriverInfo(Print &out) const { + size_t bytes = 0; + wifi_ap_record_t info; + if (!started()) { + return bytes; + } + if (esp_wifi_sta_get_ap_info(&info) != ESP_OK) { + return bytes; + } + bytes += out.print(","); + bytes += out.print((const char *)info.ssid); + bytes += out.print(",CH:"); + bytes += out.print(info.primary); + bytes += out.print(",RSSI:"); + bytes += out.print(info.rssi); + bytes += out.print(","); + if (info.phy_11ax) { + bytes += out.print("AX"); + } else if (info.phy_11n) { + bytes += out.print("N"); + } else if (info.phy_11g) { + bytes += out.print("G"); + } else if (info.phy_11b) { + bytes += out.print("B"); + } + if (info.phy_lr) { + bytes += out.print(","); + bytes += out.print("LR"); + } + + if (info.authmode == WIFI_AUTH_OPEN) { + bytes += out.print(",OPEN"); + } else if (info.authmode == WIFI_AUTH_WEP) { + bytes += out.print(",WEP"); + } else if (info.authmode == WIFI_AUTH_WPA_PSK) { + bytes += out.print(",WPA_PSK"); + } else if (info.authmode == WIFI_AUTH_WPA2_PSK) { + bytes += out.print(",WPA2_PSK"); + } else if (info.authmode == WIFI_AUTH_WPA_WPA2_PSK) { + bytes += out.print(",WPA_WPA2_PSK"); + } else if (info.authmode == WIFI_AUTH_ENTERPRISE) { + bytes += out.print(",EAP"); + } else if (info.authmode == WIFI_AUTH_WPA3_PSK) { + bytes += out.print(",WPA3_PSK"); + } else if (info.authmode == WIFI_AUTH_WPA2_WPA3_PSK) { + bytes += out.print(",WPA2_WPA3_PSK"); + } else if (info.authmode == WIFI_AUTH_WAPI_PSK) { + bytes += out.print(",WAPI_PSK"); + } else if (info.authmode == WIFI_AUTH_OWE) { + bytes += out.print(",OWE"); + } else if (info.authmode == WIFI_AUTH_WPA3_ENT_192) { + bytes += out.print(",WPA3_ENT_SUITE_B_192_BIT"); + } + + return bytes; +} + +/** + * @brief Convert wifi_err_reason_t to a string. + * @param [in] reason The reason to be converted. + * @return A string representation of the error code. + * @note: wifi_err_reason_t values as of Mar 2023 (arduino-esp32 r2.0.7) are: (1-39, 46-51, 67-68, 200-208) and are defined in /tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h. + */ +const char *STAClass::disconnectReasonName(wifi_err_reason_t reason) { + switch (reason) { + //ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2,0,7) + case WIFI_REASON_UNSPECIFIED: return "UNSPECIFIED"; + case WIFI_REASON_AUTH_EXPIRE: return "AUTH_EXPIRE"; + case WIFI_REASON_AUTH_LEAVE: return "AUTH_LEAVE"; + case WIFI_REASON_ASSOC_EXPIRE: return "ASSOC_EXPIRE"; + case WIFI_REASON_ASSOC_TOOMANY: return "ASSOC_TOOMANY"; + case WIFI_REASON_NOT_AUTHED: return "NOT_AUTHED"; + case WIFI_REASON_NOT_ASSOCED: return "NOT_ASSOCED"; + case WIFI_REASON_ASSOC_LEAVE: return "ASSOC_LEAVE"; + case WIFI_REASON_ASSOC_NOT_AUTHED: return "ASSOC_NOT_AUTHED"; + case WIFI_REASON_DISASSOC_PWRCAP_BAD: return "DISASSOC_PWRCAP_BAD"; + case WIFI_REASON_DISASSOC_SUPCHAN_BAD: return "DISASSOC_SUPCHAN_BAD"; + case WIFI_REASON_BSS_TRANSITION_DISASSOC: return "BSS_TRANSITION_DISASSOC"; + case WIFI_REASON_IE_INVALID: return "IE_INVALID"; + case WIFI_REASON_MIC_FAILURE: return "MIC_FAILURE"; + case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT: return "4WAY_HANDSHAKE_TIMEOUT"; + case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT: return "GROUP_KEY_UPDATE_TIMEOUT"; + case WIFI_REASON_IE_IN_4WAY_DIFFERS: return "IE_IN_4WAY_DIFFERS"; + case WIFI_REASON_GROUP_CIPHER_INVALID: return "GROUP_CIPHER_INVALID"; + case WIFI_REASON_PAIRWISE_CIPHER_INVALID: return "PAIRWISE_CIPHER_INVALID"; + case WIFI_REASON_AKMP_INVALID: return "AKMP_INVALID"; + case WIFI_REASON_UNSUPP_RSN_IE_VERSION: return "UNSUPP_RSN_IE_VERSION"; + case WIFI_REASON_INVALID_RSN_IE_CAP: return "INVALID_RSN_IE_CAP"; + case WIFI_REASON_802_1X_AUTH_FAILED: return "802_1X_AUTH_FAILED"; + case WIFI_REASON_CIPHER_SUITE_REJECTED: return "CIPHER_SUITE_REJECTED"; + case WIFI_REASON_TDLS_PEER_UNREACHABLE: return "TDLS_PEER_UNREACHABLE"; + case WIFI_REASON_TDLS_UNSPECIFIED: return "TDLS_UNSPECIFIED"; + case WIFI_REASON_SSP_REQUESTED_DISASSOC: return "SSP_REQUESTED_DISASSOC"; + case WIFI_REASON_NO_SSP_ROAMING_AGREEMENT: return "NO_SSP_ROAMING_AGREEMENT"; + case WIFI_REASON_BAD_CIPHER_OR_AKM: return "BAD_CIPHER_OR_AKM"; + case WIFI_REASON_NOT_AUTHORIZED_THIS_LOCATION: return "NOT_AUTHORIZED_THIS_LOCATION"; + case WIFI_REASON_SERVICE_CHANGE_PERCLUDES_TS: return "SERVICE_CHANGE_PERCLUDES_TS"; + case WIFI_REASON_UNSPECIFIED_QOS: return "UNSPECIFIED_QOS"; + case WIFI_REASON_NOT_ENOUGH_BANDWIDTH: return "NOT_ENOUGH_BANDWIDTH"; + case WIFI_REASON_MISSING_ACKS: return "MISSING_ACKS"; + case WIFI_REASON_EXCEEDED_TXOP: return "EXCEEDED_TXOP"; + case WIFI_REASON_STA_LEAVING: return "STA_LEAVING"; + case WIFI_REASON_END_BA: return "END_BA"; + case WIFI_REASON_UNKNOWN_BA: return "UNKNOWN_BA"; + case WIFI_REASON_TIMEOUT: return "TIMEOUT"; + case WIFI_REASON_PEER_INITIATED: return "PEER_INITIATED"; + case WIFI_REASON_AP_INITIATED: return "AP_INITIATED"; + case WIFI_REASON_INVALID_FT_ACTION_FRAME_COUNT: return "INVALID_FT_ACTION_FRAME_COUNT"; + case WIFI_REASON_INVALID_PMKID: return "INVALID_PMKID"; + case WIFI_REASON_INVALID_MDE: return "INVALID_MDE"; + case WIFI_REASON_INVALID_FTE: return "INVALID_FTE"; + case WIFI_REASON_TRANSMISSION_LINK_ESTABLISH_FAILED: return "TRANSMISSION_LINK_ESTABLISH_FAILED"; + case WIFI_REASON_ALTERATIVE_CHANNEL_OCCUPIED: return "ALTERATIVE_CHANNEL_OCCUPIED"; + case WIFI_REASON_BEACON_TIMEOUT: return "BEACON_TIMEOUT"; + case WIFI_REASON_NO_AP_FOUND: return "NO_AP_FOUND"; + case WIFI_REASON_AUTH_FAIL: return "AUTH_FAIL"; + case WIFI_REASON_ASSOC_FAIL: return "ASSOC_FAIL"; + case WIFI_REASON_HANDSHAKE_TIMEOUT: return "HANDSHAKE_TIMEOUT"; + case WIFI_REASON_CONNECTION_FAIL: return "CONNECTION_FAIL"; + case WIFI_REASON_AP_TSF_RESET: return "AP_TSF_RESET"; + case WIFI_REASON_ROAMING: return "ROAMING"; + case WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG: return "ASSOC_COMEBACK_TIME_TOO_LONG"; + default: return ""; + } +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFi.cpp b/libraries/WiFi/src/WiFi.cpp new file mode 100644 index 0000000..2db8dba --- /dev/null +++ b/libraries/WiFi/src/WiFi.cpp @@ -0,0 +1,99 @@ +/* + ESP8266WiFi.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ +#include "WiFi.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +} + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------------- Debug ------------------------------------------------------ +// ----------------------------------------------------------------------------------------------------------------------- + +/** + * Output WiFi settings to an object derived from Print interface (like Serial). + * @param p Print interface + */ +void WiFiClass::printDiag(Print &p) { + const char *modes[] = {"NULL", "STA", "AP", "STA+AP", "NAN"}; + + wifi_mode_t mode = WIFI_MODE_NULL; + esp_wifi_get_mode(&mode); + + uint8_t primaryChan = 0; + wifi_second_chan_t secondChan = WIFI_SECOND_CHAN_NONE; + esp_wifi_get_channel(&primaryChan, &secondChan); + + p.print("Mode: "); + p.println(modes[mode]); + + p.print("Channel: "); + p.println(primaryChan); + /* + p.print("AP id: "); + p.println(wifi_station_get_current_ap_id()); + + p.print("Status: "); + p.println(wifi_station_get_connect_status()); + */ + + wifi_config_t conf = {0}; + esp_wifi_get_config((wifi_interface_t)WIFI_IF_STA, &conf); + + const char *ssid = reinterpret_cast(conf.sta.ssid); + p.print("SSID ("); + p.print(strlen(ssid)); + p.print("): "); + p.println(ssid); + + const char *passphrase = reinterpret_cast(conf.sta.password); + p.print("Passphrase ("); + p.print(strlen(passphrase)); + p.print("): "); + p.println(passphrase); + + p.print("BSSID set: "); + p.println(conf.sta.bssid_set); +} + +void WiFiClass::enableProv(bool status) { + prov_enable = status; +} + +bool WiFiClass::isProvEnabled() { + return prov_enable; +} + +WiFiClass WiFi; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFi.h b/libraries/WiFi/src/WiFi.h new file mode 100644 index 0000000..ea2efd9 --- /dev/null +++ b/libraries/WiFi/src/WiFi.h @@ -0,0 +1,77 @@ +/* + WiFi.h - esp32 Wifi support. + Based on WiFi.h from Arduino WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include + +#include "Print.h" +#include "IPAddress.h" + +#include "WiFiType.h" +#include "WiFiSTA.h" +#include "WiFiAP.h" +#include "WiFiScan.h" +#include "WiFiGeneric.h" + +#include "WiFiClient.h" +#include "WiFiServer.h" +#include "WiFiUdp.h" + +class WiFiClass : public WiFiGenericClass, public WiFiSTAClass, public WiFiScanClass, public WiFiAPClass { +private: + bool prov_enable; + +public: + WiFiClass() { + prov_enable = false; + } + + using WiFiGenericClass::channel; + + using WiFiSTAClass::BSSID; + using WiFiSTAClass::BSSIDstr; + using WiFiSTAClass::RSSI; + using WiFiSTAClass::SSID; + + using WiFiScanClass::BSSID; + using WiFiScanClass::BSSIDstr; + using WiFiScanClass::channel; + using WiFiScanClass::encryptionType; + using WiFiScanClass::RSSI; + using WiFiScanClass::SSID; + +public: + void printDiag(Print &dest); + friend class NetworkClient; + friend class NetworkServer; + friend class NetworkUDP; + void enableProv(bool status); + bool isProvEnabled(); +}; + +extern WiFiClass WiFi; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiAP.cpp b/libraries/WiFi/src/WiFiAP.cpp new file mode 100644 index 0000000..bb15ff4 --- /dev/null +++ b/libraries/WiFi/src/WiFiAP.cpp @@ -0,0 +1,198 @@ +/* + ESP8266WiFiSTA.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiAP.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dhcpserver/dhcpserver_options.h" + +/** + * Set up an access point + * @param ssid Pointer to the SSID (max 63 char). + * @param passphrase (for WPA2 min 8 char, for open use NULL) + * @param channel WiFi channel number, 1 - 13. + * @param ssid_hidden Network cloaking (0 = broadcast SSID, 1 = hide SSID) + * @param max_connection Max simultaneous connected clients, 1 - 4. +*/ +bool WiFiAPClass::softAP( + const char *ssid, const char *passphrase, int channel, int ssid_hidden, int max_connection, bool ftm_responder, wifi_auth_mode_t auth_mode, + wifi_cipher_type_t cipher +) { + return AP.begin() && AP.create(ssid, passphrase, channel, ssid_hidden, max_connection, ftm_responder, auth_mode, cipher); +} + +/** + * Return the current SSID associated with the network + * @return SSID + */ +String WiFiAPClass::softAPSSID() const { + return AP.SSID(); +} + +/** + * Configure access point + * @param local_ip access point IP + * @param gateway gateway IP + * @param subnet subnet mask + */ +bool WiFiAPClass::softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dhcp_lease_start, IPAddress dns) { + return AP.begin() && AP.config(local_ip, gateway, subnet, dhcp_lease_start, dns); +} + +/** + * Disconnect from the network (close AP) + * @param wifioff disable mode? + * @return one value of wl_status_t enum + */ +bool WiFiAPClass::softAPdisconnect(bool wifioff) { + if (!AP.clear()) { + return false; + } + if (wifioff) { + return AP.end(); + } + return true; +} + +/** + * Sets the working bandwidth of the AP mode + * @param m wifi_bandwidth_t + */ +bool WiFiAPClass::softAPbandwidth(wifi_bandwidth_t bandwidth) { + return AP.bandwidth(bandwidth); +} + +/** + * Get the count of the Station / client that are connected to the softAP interface + * @return Stations count + */ +uint8_t WiFiAPClass::softAPgetStationNum() { + return AP.stationCount(); +} + +/** + * Get the softAP interface IP address. + * @return IPAddress softAP IP + */ +IPAddress WiFiAPClass::softAPIP() { + return AP.localIP(); +} + +/** + * Get the softAP broadcast IP address. + * @return IPAddress softAP broadcastIP + */ +IPAddress WiFiAPClass::softAPBroadcastIP() { + return AP.broadcastIP(); +} + +/** + * Get the softAP network ID. + * @return IPAddress softAP networkID + */ +IPAddress WiFiAPClass::softAPNetworkID() { + return AP.networkID(); +} + +/** + * Get the softAP subnet mask. + * @return IPAddress subnetMask + */ +IPAddress WiFiAPClass::softAPSubnetMask() { + return AP.subnetMask(); +} + +/** + * Get the softAP subnet CIDR. + * @return uint8_t softAP subnetCIDR + */ +uint8_t WiFiAPClass::softAPSubnetCIDR() { + return AP.subnetCIDR(); +} + +/** + * Get the softAP interface MAC address. + * @param mac pointer to uint8_t array with length WL_MAC_ADDR_LENGTH + * @return pointer to uint8_t* + */ +uint8_t *WiFiAPClass::softAPmacAddress(uint8_t *mac) { + return AP.macAddress(mac); +} + +/** + * Get the softAP interface MAC address. + * @return String mac + */ +String WiFiAPClass::softAPmacAddress(void) { + return AP.macAddress(); +} + +/** + * Get the softAP interface Host name. + * @return char array hostname + */ +const char *WiFiAPClass::softAPgetHostname() { + return AP.getHostname(); +} + +/** + * Set the softAP interface Host name. + * @param hostname pointer to const string + * @return true on success + */ +bool WiFiAPClass::softAPsetHostname(const char *hostname) { + return AP.setHostname(hostname); +} + +#if CONFIG_LWIP_IPV6 +/** + * Enable IPv6 on the softAP interface. + * @return true on success + */ +bool WiFiAPClass::softAPenableIPv6(bool enable) { + return AP.enableIPv6(enable); +} + +/** + * Get the softAP interface IPv6 address. + * @return IPAddress softAP IPv6 + */ + +IPAddress WiFiAPClass::softAPlinkLocalIPv6() { + return AP.linkLocalIPv6(); +} +#endif +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiAP.h b/libraries/WiFi/src/WiFiAP.h new file mode 100644 index 0000000..064a6f6 --- /dev/null +++ b/libraries/WiFi/src/WiFiAP.h @@ -0,0 +1,131 @@ +/* + ESP8266WiFiAP.h - esp8266 Wifi support. + Based on WiFi.h from Arduino WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "esp_wifi_types.h" +#include "WiFiType.h" +#include "WiFiGeneric.h" + +#define WIFI_AP_DEFAULT_AUTH_MODE WIFI_AUTH_WPA2_PSK +#define WIFI_AP_DEFAULT_CIPHER WIFI_CIPHER_TYPE_CCMP // Disable by default enabled insecure TKIP and use just CCMP. + +// ---------------------------------------------------------------------------------------------- +// ------------------------------------ NEW AP Implementation ---------------------------------- +// ---------------------------------------------------------------------------------------------- + +class APClass : public NetworkInterface { +public: + APClass(); + ~APClass(); + + bool begin(); + bool end(); + + bool create( + const char *ssid, const char *passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false, + wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER + ); + + bool create( + const String &ssid, const String &passphrase = emptyString, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false, + wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER + ) { + return create(ssid.c_str(), passphrase.c_str(), channel, ssid_hidden, max_connection, ftm_responder, auth_mode, cipher); + } + + bool clear(); + + bool bandwidth(wifi_bandwidth_t bandwidth); + bool enableNAPT(bool enable = true); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) + bool enableDhcpCaptivePortal(); +#endif + + String SSID(void) const; + uint8_t stationCount(); + + void _onApEvent(int32_t event_id, void *event_data); + +protected: + network_event_handle_t _wifi_ap_event_handle; + + size_t printDriverInfo(Print &out) const; + + friend class WiFiGenericClass; + bool onEnable(); + bool onDisable(); +}; + +// ---------------------------------------------------------------------------------------------- +// ------------------------------- OLD AP API (compatibility) ---------------------------------- +// ---------------------------------------------------------------------------------------------- + +class WiFiAPClass { + +public: + APClass AP; + + bool softAP( + const char *ssid, const char *passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false, + wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER + ); + bool softAP( + const String &ssid, const String &passphrase = emptyString, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false, + wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER + ) { + return softAP(ssid.c_str(), passphrase.c_str(), channel, ssid_hidden, max_connection, ftm_responder, auth_mode, cipher); + } + + bool softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dhcp_lease_start = (uint32_t)0, IPAddress dns = (uint32_t)0); + bool softAPdisconnect(bool wifioff = false); + + bool softAPbandwidth(wifi_bandwidth_t bandwidth); + + uint8_t softAPgetStationNum(); + String softAPSSID(void) const; + + IPAddress softAPIP(); + IPAddress softAPBroadcastIP(); + IPAddress softAPNetworkID(); + IPAddress softAPSubnetMask(); + uint8_t softAPSubnetCIDR(); + +#if CONFIG_LWIP_IPV6 + bool softAPenableIPv6(bool enable = true); + IPAddress softAPlinkLocalIPv6(); +#endif + + const char *softAPgetHostname(); + bool softAPsetHostname(const char *hostname); + + uint8_t *softAPmacAddress(uint8_t *mac); + String softAPmacAddress(void); + +protected: +}; + +#endif /* SOC_WIFI_SUPPORTED*/ diff --git a/libraries/WiFi/src/WiFiClient.h b/libraries/WiFi/src/WiFiClient.h new file mode 100644 index 0000000..4add805 --- /dev/null +++ b/libraries/WiFi/src/WiFiClient.h @@ -0,0 +1,3 @@ +#pragma once +#include "NetworkClient.h" +typedef NetworkClient WiFiClient; diff --git a/libraries/WiFi/src/WiFiGeneric.cpp b/libraries/WiFi/src/WiFiGeneric.cpp new file mode 100644 index 0000000..0a53020 --- /dev/null +++ b/libraries/WiFi/src/WiFiGeneric.cpp @@ -0,0 +1,1121 @@ +/* + ESP8266WiFiGeneric.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +extern "C" { +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#if SOC_WIFI_SUPPORTED +#include +#endif +#include "lwip/ip_addr.h" +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/dns.h" +#include "lwip/netif.h" +#include "dhcpserver/dhcpserver.h" +#include "dhcpserver/dhcpserver_options.h" + +} //extern "C" + +#include "esp32-hal.h" +#include +#include "sdkconfig.h" + +ESP_EVENT_DEFINE_BASE(ARDUINO_EVENTS); + +static esp_netif_t *esp_netifs[ESP_IF_MAX] = {NULL, NULL, NULL}; + +esp_netif_t *get_esp_interface_netif(esp_interface_t interface) { + if (interface < ESP_IF_MAX) { + return esp_netifs[interface]; + } + return NULL; +} + +static void _arduino_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) { + (void)arg; + arduino_event_t arduino_event; + arduino_event.event_id = ARDUINO_EVENT_MAX; + + /* + * SCAN + * */ + if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_SCAN_DONE) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_event_sta_scan_done_t *event = (wifi_event_sta_scan_done_t *)event_data; + log_v("SCAN Done: ID: %u, Status: %u, Results: %u", event->scan_id, event->status, event->number); +#endif + arduino_event.event_id = ARDUINO_EVENT_WIFI_SCAN_DONE; + memcpy(&arduino_event.event_info.wifi_scan_done, event_data, sizeof(wifi_event_sta_scan_done_t)); + + /* + * WPS + * */ + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_SUCCESS) { + arduino_event.event_id = ARDUINO_EVENT_WPS_ER_SUCCESS; + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_FAILED) { + arduino_event.event_id = ARDUINO_EVENT_WPS_ER_FAILED; + memcpy(&arduino_event.event_info.wps_fail_reason, event_data, sizeof(wifi_event_sta_wps_fail_reason_t)); + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_TIMEOUT) { + arduino_event.event_id = ARDUINO_EVENT_WPS_ER_TIMEOUT; + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_PIN) { + arduino_event.event_id = ARDUINO_EVENT_WPS_ER_PIN; + memcpy(&arduino_event.event_info.wps_er_pin, event_data, sizeof(wifi_event_sta_wps_er_pin_t)); + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP) { + arduino_event.event_id = ARDUINO_EVENT_WPS_ER_PBC_OVERLAP; + + /* + * FTM + * */ + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_FTM_REPORT) { + arduino_event.event_id = ARDUINO_EVENT_WIFI_FTM_REPORT; + memcpy(&arduino_event.event_info.wifi_ftm_report, event_data, sizeof(wifi_event_ftm_report_t)); + +#if !CONFIG_ESP_WIFI_REMOTE_ENABLED + /* + * SMART CONFIG + * */ + } else if (event_base == SC_EVENT && event_id == SC_EVENT_SCAN_DONE) { + log_v("SC Scan Done"); + arduino_event.event_id = ARDUINO_EVENT_SC_SCAN_DONE; + } else if (event_base == SC_EVENT && event_id == SC_EVENT_FOUND_CHANNEL) { + log_v("SC Found Channel"); + arduino_event.event_id = ARDUINO_EVENT_SC_FOUND_CHANNEL; + } else if (event_base == SC_EVENT && event_id == SC_EVENT_GOT_SSID_PSWD) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + smartconfig_event_got_ssid_pswd_t *event = (smartconfig_event_got_ssid_pswd_t *)event_data; + log_v("SC: SSID: %s, Password: %s", (const char *)event->ssid, (const char *)event->password); +#endif + arduino_event.event_id = ARDUINO_EVENT_SC_GOT_SSID_PSWD; + memcpy(&arduino_event.event_info.sc_got_ssid_pswd, event_data, sizeof(smartconfig_event_got_ssid_pswd_t)); + + } else if (event_base == SC_EVENT && event_id == SC_EVENT_SEND_ACK_DONE) { + log_v("SC Send Ack Done"); + arduino_event.event_id = ARDUINO_EVENT_SC_SEND_ACK_DONE; + +#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI + /* + * Provisioning + * */ + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_INIT) { + log_v("Provisioning Initialized!"); + arduino_event.event_id = ARDUINO_EVENT_PROV_INIT; + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_DEINIT) { + log_v("Provisioning Uninitialized!"); + arduino_event.event_id = ARDUINO_EVENT_PROV_DEINIT; + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_START) { + log_v("Provisioning Start!"); + arduino_event.event_id = ARDUINO_EVENT_PROV_START; + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_END) { + log_v("Provisioning End!"); + network_prov_mgr_deinit(); + arduino_event.event_id = ARDUINO_EVENT_PROV_END; + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_RECV) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE + wifi_sta_config_t *event = (wifi_sta_config_t *)event_data; + log_v("Provisioned Credentials: SSID: %s, Password: %s", (const char *)event->ssid, (const char *)event->password); +#endif + arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_RECV; + memcpy(&arduino_event.event_info.prov_cred_recv, event_data, sizeof(wifi_sta_config_t)); + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_FAIL) { +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + network_prov_wifi_sta_fail_reason_t *reason = (network_prov_wifi_sta_fail_reason_t *)event_data; + log_e("Provisioning Failed: Reason : %s", (*reason == NETWORK_PROV_WIFI_STA_AUTH_ERROR) ? "Authentication Failed" : "AP Not Found"); +#endif + arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_FAIL; + memcpy(&arduino_event.event_info.prov_fail_reason, event_data, sizeof(network_prov_wifi_sta_fail_reason_t)); + } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_SUCCESS) { + log_v("Provisioning Success!"); + arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_SUCCESS; +#endif +#endif + } + + if (arduino_event.event_id < ARDUINO_EVENT_MAX) { + Network.postEvent(&arduino_event); + } +} + +static bool initWiFiEvents() { + if (esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) { + log_e("event_handler_instance_register for WIFI_EVENT Failed!"); + return false; + } + +#if !CONFIG_ESP_WIFI_REMOTE_ENABLED + if (esp_event_handler_instance_register(SC_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) { + log_e("event_handler_instance_register for SC_EVENT Failed!"); + return false; + } + +#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI + if (esp_event_handler_instance_register(NETWORK_PROV_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) { + log_e("event_handler_instance_register for NETWORK_PROV_EVENT Failed!"); + return false; + } +#endif +#endif + + return true; +} + +static bool deinitWiFiEvents() { + if (esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) { + log_e("esp_event_handler_unregister for WIFI_EVENT Failed!"); + return false; + } + +#if !CONFIG_ESP_WIFI_REMOTE_ENABLED + if (esp_event_handler_unregister(SC_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) { + log_e("esp_event_handler_unregister for SC_EVENT Failed!"); + return false; + } + +#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI + if (esp_event_handler_unregister(NETWORK_PROV_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) { + log_e("esp_event_handler_unregister for NETWORK_PROV_EVENT Failed!"); + return false; + } +#endif +#endif + + return true; +} + +/* + * WiFi INIT + * */ + +static bool lowLevelInitDone = false; +bool WiFiGenericClass::_wifiUseStaticBuffers = false; + +bool WiFiGenericClass::useStaticBuffers() { + return _wifiUseStaticBuffers; +} + +void WiFiGenericClass::useStaticBuffers(bool bufferMode) { + if (lowLevelInitDone) { + log_w("WiFi already started. Call WiFi.mode(WIFI_MODE_NULL) before setting Static Buffer Mode."); + } + _wifiUseStaticBuffers = bufferMode; +} + +// Temporary fix to ensure that CDC+JTAG stay on on ESP32-C3 +#if CONFIG_IDF_TARGET_ESP32C3 +extern "C" void phy_bbpll_en_usb(bool en); +#endif + +#if CONFIG_ESP_WIFI_REMOTE_ENABLED + +bool WiFiGenericClass::setPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst) { + return hostedSetPins(clk, cmd, d0, d1, d2, d3, rst); +} + +#endif + +bool wifiLowLevelInit(bool persistent) { + if (!lowLevelInitDone) { + lowLevelInitDone = true; +#if CONFIG_ESP_WIFI_REMOTE_ENABLED + if (!hostedInitWiFi()) { + lowLevelInitDone = false; + return lowLevelInitDone; + } +#endif + if (!Network.begin()) { + lowLevelInitDone = false; + return lowLevelInitDone; + } + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + +#if CONFIG_ESP_WIFI_REMOTE_ENABLED + // required for proper work when esp-hosted is used. + cfg.nvs_enable = false; + persistent = false; +#endif + + if (!WiFiGenericClass::useStaticBuffers()) { + cfg.static_tx_buf_num = 0; + cfg.dynamic_tx_buf_num = 32; + cfg.tx_buf_type = 1; + cfg.cache_tx_buf_num = 4; // can't be zero! + cfg.static_rx_buf_num = 4; + cfg.dynamic_rx_buf_num = 32; + } + + esp_err_t err = esp_wifi_init(&cfg); + if (err) { + log_e("esp_wifi_init 0x%x: %s", err, esp_err_to_name(err)); + lowLevelInitDone = false; + return lowLevelInitDone; + } +// Temporary fix to ensure that CDC+JTAG stay on on ESP32-C3 +#if CONFIG_IDF_TARGET_ESP32C3 + phy_bbpll_en_usb(true); +#endif + if (!persistent) { + lowLevelInitDone = esp_wifi_set_storage(WIFI_STORAGE_RAM) == ESP_OK; + } + if (lowLevelInitDone) { + initWiFiEvents(); + if (esp_netifs[ESP_IF_WIFI_AP] == NULL) { + esp_netifs[ESP_IF_WIFI_AP] = esp_netif_create_default_wifi_ap(); + } + if (esp_netifs[ESP_IF_WIFI_STA] == NULL) { + esp_netifs[ESP_IF_WIFI_STA] = esp_netif_create_default_wifi_sta(); + } + + arduino_event_t arduino_event; + arduino_event.event_id = ARDUINO_EVENT_WIFI_READY; + Network.postEvent(&arduino_event); + } + } + return lowLevelInitDone; +} + +static bool wifiLowLevelDeinit() { + if (lowLevelInitDone) { + lowLevelInitDone = false; + deinitWiFiEvents(); + if (esp_netifs[ESP_IF_WIFI_AP] != NULL) { + esp_netif_destroy_default_wifi(esp_netifs[ESP_IF_WIFI_AP]); + esp_netifs[ESP_IF_WIFI_AP] = NULL; + } + if (esp_netifs[ESP_IF_WIFI_STA] != NULL) { + esp_netif_destroy_default_wifi(esp_netifs[ESP_IF_WIFI_STA]); + esp_netifs[ESP_IF_WIFI_STA] = NULL; + } + lowLevelInitDone = !(esp_wifi_deinit() == ESP_OK); + if (!lowLevelInitDone) { + arduino_event_t arduino_event; + arduino_event.event_id = ARDUINO_EVENT_WIFI_OFF; + Network.postEvent(&arduino_event); +#if CONFIG_ESP_WIFI_REMOTE_ENABLED + hostedDeinitWiFi(); +#endif + } + } + return !lowLevelInitDone; +} + +static bool _esp_wifi_started = false; + +static bool espWiFiStart() { + if (_esp_wifi_started) { + return true; + } + _esp_wifi_started = true; + esp_err_t err = esp_wifi_start(); + if (err != ESP_OK) { + _esp_wifi_started = false; + log_e("esp_wifi_start 0x%x: %s", err, esp_err_to_name(err)); + return _esp_wifi_started; + } +#if SOC_WIFI_SUPPORT_5G + log_v("Setting Band Mode to AUTO"); + esp_wifi_set_band_mode(WIFI_BAND_MODE_AUTO); +#endif + return _esp_wifi_started; +} + +static bool espWiFiStop() { + esp_err_t err; + if (!_esp_wifi_started) { + return true; + } + _esp_wifi_started = false; + err = esp_wifi_stop(); + if (err) { + log_e("Could not stop WiFi! 0x%x: %s", err, esp_err_to_name(err)); + _esp_wifi_started = true; + return false; + } + return wifiLowLevelDeinit(); +} + +// ----------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------------- Generic WiFi function ----------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +bool WiFiGenericClass::_persistent = true; +bool WiFiGenericClass::_long_range = false; +#if CONFIG_IDF_TARGET_ESP32S2 +wifi_ps_type_t WiFiGenericClass::_sleepEnabled = WIFI_PS_NONE; +#else +wifi_ps_type_t WiFiGenericClass::_sleepEnabled = WIFI_PS_MIN_MODEM; +#endif + +WiFiGenericClass::WiFiGenericClass() {} + +const char *WiFiGenericClass::disconnectReasonName(wifi_err_reason_t reason) { + return WiFi.STA.disconnectReasonName(reason); +} + +const char *WiFiGenericClass::eventName(arduino_event_id_t id) { + return Network.eventName(id); +} + +const char *WiFiGenericClass::getHostname() { + return NetworkManager::getHostname(); +} + +bool WiFiGenericClass::setHostname(const char *hostname) { + return NetworkManager::setHostname(hostname); +} + +/** + * callback for WiFi events + * @param arg + */ +void WiFiGenericClass::_eventCallback(arduino_event_t *event) { + if (!event) { + return; //Null would crash this function + } + + // log_d("Arduino Event: %d - %s", event->event_id, WiFi.eventName(event->event_id)); + if (event->event_id == ARDUINO_EVENT_WIFI_SCAN_DONE) { + WiFiScanClass::_scanDone(); +#if !CONFIG_ESP_WIFI_REMOTE_ENABLED + } else if (event->event_id == ARDUINO_EVENT_SC_GOT_SSID_PSWD) { + WiFi.begin( + (const char *)event->event_info.sc_got_ssid_pswd.ssid, (const char *)event->event_info.sc_got_ssid_pswd.password, 0, + ((event->event_info.sc_got_ssid_pswd.bssid_set == true) ? event->event_info.sc_got_ssid_pswd.bssid : NULL) + ); + } else if (event->event_id == ARDUINO_EVENT_SC_SEND_ACK_DONE) { + esp_smartconfig_stop(); + WiFiSTAClass::_smartConfigDone = true; +#endif + } +} + +/** + * Return the current channel associated with the network + * @return channel (1-13) + */ +int32_t WiFiGenericClass::channel(void) { + uint8_t primaryChan = 0; + wifi_second_chan_t secondChan = WIFI_SECOND_CHAN_NONE; + if (!lowLevelInitDone) { + return primaryChan; + } + esp_wifi_get_channel(&primaryChan, &secondChan); + return primaryChan; +} + +/** + * Set the WiFi channel configuration + * @param primary primary channel. Depending on the region, not all channels may be available. + * @param secondary secondary channel (WIFI_SECOND_CHAN_NONE, WIFI_SECOND_CHAN_ABOVE, WIFI_SECOND_CHAN_BELOW) + * @return 0 on success, otherwise error + */ +int WiFiGenericClass::setChannel(uint8_t primary, wifi_second_chan_t secondary) { + wifi_country_t country; + esp_err_t ret; + + ret = esp_wifi_get_country(&country); + if (ret != ESP_OK) { + log_e("Failed to get country info 0x%x: %s", ret, esp_err_to_name(ret)); + return ret; + } + + uint8_t min_chan = country.schan; + uint8_t max_chan = min_chan + country.nchan - 1; + + if (primary < min_chan || primary > max_chan) { + log_e("Invalid primary channel: %d. Valid range is %d-%d for country %s", primary, min_chan, max_chan, country.cc); + return ESP_ERR_INVALID_ARG; + } + + ret = esp_wifi_set_channel(primary, secondary); + if (ret != ESP_OK) { + log_e("Failed to set channel 0x%x: %s", ret, esp_err_to_name(ret)); + return ret; + } + + return ESP_OK; +} + +/** + * store WiFi config in SDK flash area + * @param persistent + */ +void WiFiGenericClass::persistent(bool persistent) { + _persistent = persistent; +} + +/** + * enable WiFi long range mode + * @param enable + */ +void WiFiGenericClass::enableLongRange(bool enable) { + _long_range = enable; +} + +#if CONFIG_SOC_WIFI_HE_SUPPORT +#define WIFI_PROTOCOL_DEFAULT (WIFI_PROTOCOL_11B | WIFI_PROTOCOL_11G | WIFI_PROTOCOL_11N | WIFI_PROTOCOL_11AX) +#else +#define WIFI_PROTOCOL_DEFAULT (WIFI_PROTOCOL_11B | WIFI_PROTOCOL_11G | WIFI_PROTOCOL_11N) +#endif + +#if SOC_WIFI_SUPPORT_5G +#if CONFIG_SOC_WIFI_HE_SUPPORT +#define WIFI_PROTOCOL_DEFAULT_5G (WIFI_PROTOCOL_11A | WIFI_PROTOCOL_11N | WIFI_PROTOCOL_11AC | WIFI_PROTOCOL_11AX) +#else +#define WIFI_PROTOCOL_DEFAULT_5G (WIFI_PROTOCOL_11A | WIFI_PROTOCOL_11N | WIFI_PROTOCOL_11AC) +#endif +#endif + +static bool _wifi_is_lr_enabled(wifi_interface_t ifx) { +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) && SOC_WIFI_SUPPORT_5G + wifi_band_mode_t band_mode = WIFI_BAND_MODE_AUTO; + esp_err_t err = esp_wifi_get_band_mode(&band_mode); + if (err != ESP_OK) { + log_e("Failed to get Current Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + if (band_mode == WIFI_BAND_MODE_AUTO) { + wifi_protocols_t protocols = {.ghz_2g = 0, .ghz_5g = 0}; + err = esp_wifi_get_protocols(ifx, &protocols); + if (err != ESP_OK) { + log_e("Failed to get Current Protocols: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return protocols.ghz_2g == WIFI_PROTOCOL_LR; + } else if (band_mode == WIFI_BAND_MODE_5G_ONLY) { + return false; + } +#endif + uint16_t protocol_bitmap = 0; + esp_err_t err2 = esp_wifi_get_protocol(ifx, (uint8_t *)&protocol_bitmap); + if (err2 != ESP_OK) { + log_e("Failed to get Current Protocols: 0x%x: %s", err2, esp_err_to_name(err2)); + return false; + } + return protocol_bitmap == WIFI_PROTOCOL_LR; +} + +static bool _wifi_enable_lr(wifi_interface_t ifx) { +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) && SOC_WIFI_SUPPORT_5G + wifi_band_mode_t band_mode = WIFI_BAND_MODE_AUTO; + esp_err_t err = esp_wifi_get_band_mode(&band_mode); + if (err != ESP_OK) { + log_e("Failed to get Current Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + if (band_mode == WIFI_BAND_MODE_AUTO) { + wifi_protocols_t protocols = {.ghz_2g = WIFI_PROTOCOL_LR, .ghz_5g = WIFI_PROTOCOL_DEFAULT_5G}; + err = esp_wifi_set_protocols(ifx, &protocols); + if (err != ESP_OK) { + log_e("Failed to set LR Protocol: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; + } else if (band_mode == WIFI_BAND_MODE_5G_ONLY) { + log_e("LR Protocol can only be enabled on 2.4GHz WiFi"); + return false; + } +#endif + esp_err_t err2 = esp_wifi_set_protocol(ifx, WIFI_PROTOCOL_LR); + if (err2 != ESP_OK) { + log_e("Failed to set LR Protocol: 0x%x: %s", err2, esp_err_to_name(err2)); + return false; + } + return true; +} + +static bool _wifi_disable_lr(wifi_interface_t ifx) { +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) && SOC_WIFI_SUPPORT_5G + wifi_band_mode_t band_mode = WIFI_BAND_MODE_AUTO; + esp_err_t err = esp_wifi_get_band_mode(&band_mode); + if (err != ESP_OK) { + log_e("Failed to get Current Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + if (band_mode == WIFI_BAND_MODE_AUTO) { + wifi_protocols_t protocols = {.ghz_2g = WIFI_PROTOCOL_DEFAULT, .ghz_5g = WIFI_PROTOCOL_DEFAULT_5G}; + err = esp_wifi_set_protocols(ifx, &protocols); + if (err != ESP_OK) { + log_e("Failed to set Default Protocol: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; + } else if (band_mode == WIFI_BAND_MODE_5G_ONLY) { + log_e("LR Protocol can only be disabled on 2.4GHz WiFi"); + return false; + } +#endif + esp_err_t err2 = esp_wifi_set_protocol(ifx, WIFI_PROTOCOL_DEFAULT); + if (err2 != ESP_OK) { + log_e("Failed to set Default Protocol: 0x%x: %s", err2, esp_err_to_name(err2)); + return false; + } + return true; +} + +/** + * set new mode + * @param m WiFiMode_t + */ +bool WiFiGenericClass::mode(wifi_mode_t m) { + wifi_mode_t cm = getMode(); + if (cm == m) { + return true; + } + if (!cm && m) { + // Turn ON WiFi + if (!wifiLowLevelInit(_persistent)) { + return false; + } + Network.onSysEvent(_eventCallback); + } + + if (((m & WIFI_MODE_STA) != 0) && ((cm & WIFI_MODE_STA) == 0)) { + // we are enabling STA interface + WiFi.STA.onEnable(); + } + if (((m & WIFI_MODE_AP) != 0) && ((cm & WIFI_MODE_AP) == 0)) { + // we are enabling AP interface + WiFi.AP.onEnable(); + } + + if (cm && !m) { + // Turn OFF WiFi + if (!espWiFiStop()) { + return false; + } + if ((cm & WIFI_MODE_STA) != 0) { + // we are disabling STA interface + WiFi.STA.onDisable(); + } + if ((cm & WIFI_MODE_AP) != 0) { + // we are disabling AP interface + WiFi.AP.onDisable(); + } + Network.removeEvent(_eventCallback); + return true; + } + + esp_err_t err; + if (((m & WIFI_MODE_STA) != 0) && ((cm & WIFI_MODE_STA) == 0)) { + err = esp_netif_set_hostname(esp_netifs[ESP_IF_WIFI_STA], NetworkManager::getHostname()); + if (err) { + log_e("Could not set hostname! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + } + err = esp_wifi_set_mode(m); + if (err) { + log_e("Could not set mode! 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + if (((m & WIFI_MODE_STA) == 0) && ((cm & WIFI_MODE_STA) != 0)) { + // we are disabling STA interface (but AP is ON) + WiFi.STA.onDisable(); + } + if (((m & WIFI_MODE_AP) == 0) && ((cm & WIFI_MODE_AP) != 0)) { + // we are disabling AP interface (but STA is ON) + WiFi.AP.onDisable(); + } + + if (_long_range) { + if (m & WIFI_MODE_STA) { + if (!_wifi_enable_lr(WIFI_IF_STA)) { + log_e("Could not enable long range on STA!"); + return false; + } + } + if (m & WIFI_MODE_AP) { + if (!_wifi_enable_lr(WIFI_IF_AP)) { + log_e("Could not enable long range on AP!"); + return false; + } + } + } else { + if (m & WIFI_MODE_STA) { + if (_wifi_is_lr_enabled(WIFI_IF_STA)) { + log_v("Disabling long range on STA"); + if (!_wifi_disable_lr(WIFI_IF_STA)) { + log_e("Could not disable long range on STA!"); + return false; + } + } + } + if (m & WIFI_MODE_AP) { + if (_wifi_is_lr_enabled(WIFI_IF_AP)) { + log_v("Disabling long range on AP"); + if (!_wifi_disable_lr(WIFI_IF_AP)) { + log_e("Could not disable long range on AP!"); + return false; + } + } + } + } + if (!espWiFiStart()) { + return false; + } + +#ifdef BOARD_HAS_DUAL_ANTENNA + if (!setDualAntennaConfig(ANT1, ANT2, WIFI_RX_ANT_AUTO, WIFI_TX_ANT_AUTO)) { + log_e("Dual Antenna Config failed!"); + return false; + } +#endif + + return true; +} + +/** + * get WiFi mode + * @return WiFiMode + */ +wifi_mode_t WiFiGenericClass::getMode() { + if (!lowLevelInitDone || !_esp_wifi_started) { + return WIFI_MODE_NULL; + } + wifi_mode_t mode; + if (esp_wifi_get_mode(&mode) != ESP_OK) { + log_w("WiFi not started"); + return WIFI_MODE_NULL; + } + return mode; +} + +/** + * control STA mode + * @param enable bool + * @return ok + */ +bool WiFiGenericClass::enableSTA(bool enable) { + + wifi_mode_t currentMode = getMode(); + bool isEnabled = ((currentMode & WIFI_MODE_STA) != 0); + + if (isEnabled != enable) { + if (enable) { + return mode((wifi_mode_t)(currentMode | WIFI_MODE_STA)); + } + return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_STA))); + } + return true; +} + +/** + * control AP mode + * @param enable bool + * @return ok + */ +bool WiFiGenericClass::enableAP(bool enable) { + + wifi_mode_t currentMode = getMode(); + bool isEnabled = ((currentMode & WIFI_MODE_AP) != 0); + + if (isEnabled != enable) { + if (enable) { + return mode((wifi_mode_t)(currentMode | WIFI_MODE_AP)); + } + return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_AP))); + } + return true; +} + +/** + * Enable or disable WiFi modem power save mode + * @param enable bool + * @return ok + */ +bool WiFiGenericClass::setSleep(bool enabled) { + return setSleep(enabled ? WIFI_PS_MIN_MODEM : WIFI_PS_NONE); +} + +/** + * Set WiFi modem power save mode + * @param mode wifi_ps_type_t + * @return ok + */ +bool WiFiGenericClass::setSleep(wifi_ps_type_t sleepType) { + if (sleepType > WIFI_PS_MAX_MODEM) { + return false; + } + + if (!WiFi.STA.started()) { + _sleepEnabled = sleepType; + return true; + } + + esp_err_t err = esp_wifi_set_ps(sleepType); + if (err != ESP_OK) { + log_e("esp_wifi_set_ps failed!: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + _sleepEnabled = sleepType; + return true; +} + +/** + * Get WiFi modem power save mode + * @return wifi_ps_type_t + */ +wifi_ps_type_t WiFiGenericClass::getSleep() { + return _sleepEnabled; +} + +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) +/** + * control wifi band mode + * @param band_mode enum possible band modes + * @return ok + */ +bool WiFiGenericClass::setBandMode(wifi_band_mode_t band_mode) { +#if SOC_WIFI_SUPPORT_5G + if (!WiFi.STA.started() && !WiFi.AP.started()) { + log_e("You need to start WiFi first"); + return false; + } + wifi_band_mode_t bm = WIFI_BAND_MODE_AUTO; + esp_err_t err = esp_wifi_get_band_mode(&bm); + if (err != ESP_OK) { + log_e("Failed to get Current Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } else if (bm == band_mode) { + log_d("No change in Band Mode"); + return true; + } else { + log_d("Switching Band Mode from %d to %d", bm, band_mode); + } +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR + if (WiFi.STA.connected() || WiFi.AP.connected()) { + log_e("Your network will get disconnected!"); + } +#endif + err = esp_wifi_set_band_mode(band_mode); + if (err != ESP_OK) { + log_e("Failed to set Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + delay(100); + return true; +#else + if (band_mode == WIFI_BAND_MODE_5G_ONLY) { + log_e("This chip supports only 2.4GHz WiFi"); + } + return band_mode != WIFI_BAND_MODE_5G_ONLY; +#endif +} + +/** + * get the current enabled wifi band mode + * @return enum band mode + */ +wifi_band_mode_t WiFiGenericClass::getBandMode() { +#if SOC_WIFI_SUPPORT_5G + wifi_band_mode_t band_mode = WIFI_BAND_MODE_AUTO; + if (!WiFi.STA.started() && !WiFi.AP.started()) { + log_e("You need to start WiFi first"); + return band_mode; + } + esp_err_t err = esp_wifi_get_band_mode(&band_mode); + if (err != ESP_OK) { + log_e("Failed to get Band Mode: 0x%x: %s", err, esp_err_to_name(err)); + } + return band_mode; +#else + return WIFI_BAND_MODE_2G_ONLY; +#endif +} +#endif + +/** + * get the current active wifi band + * @return enum band + */ +wifi_band_t WiFiGenericClass::getBand() { +#if SOC_WIFI_SUPPORT_5G + wifi_band_t band = WIFI_BAND_2G; + if (!WiFi.STA.started() && !WiFi.AP.started()) { + log_e("You need to start WiFi first"); + return band; + } + esp_err_t err = esp_wifi_get_band(&band); + if (err != ESP_OK) { + log_e("Failed to get Band: 0x%x: %s", err, esp_err_to_name(err)); + } + return band; +#else + return WIFI_BAND_2G; +#endif +} + +/** + * control wifi tx power + * @param power enum maximum wifi tx power + * @return ok + */ +bool WiFiGenericClass::setTxPower(wifi_power_t power) { + if (!WiFi.STA.started() && !WiFi.AP.started()) { + log_w("Neither AP or STA has been started"); + return false; + } + esp_err_t err = esp_wifi_set_max_tx_power(power); + if (err != ESP_OK) { + log_e("Failed to set TX Power: 0x%x: %s", err, esp_err_to_name(err)); + } + return err == ESP_OK; +} + +wifi_power_t WiFiGenericClass::getTxPower() { + int8_t power; + if (!WiFi.STA.started() && !WiFi.AP.started()) { + log_w("Neither AP or STA has been started"); + return WIFI_POWER_19_5dBm; + } + esp_err_t err = esp_wifi_get_max_tx_power(&power); + if (err != ESP_OK) { + log_e("Failed to get TX Power: 0x%x: %s", err, esp_err_to_name(err)); + return WIFI_POWER_19_5dBm; + } + return (wifi_power_t)power; +} + +/** + * Initiate FTM Session. + * @param frm_count Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0(No pref), 16, 24, 32, 64) + * @param burst_period Requested time period between consecutive FTM bursts in 100's of milliseconds (allowed values - 0(No pref), 2 - 255) + * @param channel Primary channel of the FTM Responder + * @param mac MAC address of the FTM Responder + * @return true on success + */ +bool WiFiGenericClass::initiateFTM(uint8_t frm_count, uint16_t burst_period, uint8_t channel, const uint8_t *mac) { + wifi_ftm_initiator_cfg_t ftmi_cfg = { + .resp_mac = {0, 0, 0, 0, 0, 0}, .channel = channel, .frm_count = frm_count, .burst_period = burst_period, .use_get_report_api = true + }; + if (mac != NULL) { + memcpy(ftmi_cfg.resp_mac, mac, 6); + } + // Request FTM session with the Responder + esp_err_t err = esp_wifi_ftm_initiate_session(&ftmi_cfg); + if (ESP_OK != err) { + log_e("Failed to initiate FTM session: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + return true; +} + +/** + * Configure Dual antenna. + * @param gpio_ant1 Configure the GPIO number for the antenna 1 connected to the RF switch (default GPIO2 on ESP32-WROOM-DA) + * @param gpio_ant2 Configure the GPIO number for the antenna 2 connected to the RF switch (default GPIO25 on ESP32-WROOM-DA) + * @param rx_mode Set the RX antenna mode. See wifi_rx_ant_t for the options. + * @param tx_mode Set the TX antenna mode. See wifi_tx_ant_t for the options. + * @return true on success + */ +bool WiFiGenericClass::setDualAntennaConfig(uint8_t gpio_ant1, uint8_t gpio_ant2, wifi_rx_ant_t rx_mode, wifi_tx_ant_t tx_mode) { +#if !CONFIG_ESP_WIFI_REMOTE_ENABLED + + esp_phy_ant_gpio_config_t wifi_ant_io; + + esp_err_t err = esp_phy_get_ant_gpio(&wifi_ant_io); + if (ESP_OK != err) { + log_e("Failed to get antenna configuration: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + wifi_ant_io.gpio_cfg[0].gpio_num = gpio_ant1; + wifi_ant_io.gpio_cfg[0].gpio_select = 1; + wifi_ant_io.gpio_cfg[1].gpio_num = gpio_ant2; + wifi_ant_io.gpio_cfg[1].gpio_select = 1; + + err = esp_phy_set_ant_gpio(&wifi_ant_io); + if (ESP_OK != err) { + log_e("Failed to set antenna GPIO configuration: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } + + // Set antenna default configuration + esp_phy_ant_config_t ant_config = { + .rx_ant_mode = ESP_PHY_ANT_MODE_AUTO, + .rx_ant_default = ESP_PHY_ANT_MAX, // Ignored in AUTO mode + .tx_ant_mode = ESP_PHY_ANT_MODE_AUTO, + .enabled_ant0 = 1, + .enabled_ant1 = 2, + }; + + switch (rx_mode) { + case WIFI_RX_ANT0: ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_ANT0; break; + case WIFI_RX_ANT1: ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_ANT1; break; + case WIFI_RX_ANT_AUTO: + log_i("TX Antenna will be automatically selected"); + ant_config.rx_ant_default = ESP_PHY_ANT_ANT0; + ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + // Force TX for AUTO if RX is AUTO + ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + goto set_ant; + break; + default: + log_e("Invalid default antenna! Falling back to AUTO"); + ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + break; + } + + switch (tx_mode) { + case WIFI_TX_ANT0: ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_ANT0; break; + case WIFI_TX_ANT1: ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_ANT1; break; + case WIFI_TX_ANT_AUTO: + log_i("RX Antenna will be automatically selected"); + ant_config.rx_ant_default = ESP_PHY_ANT_ANT0; + ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + // Force RX for AUTO if RX is AUTO + ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + break; + default: + log_e("Invalid default antenna! Falling back to AUTO"); + ant_config.rx_ant_default = ESP_PHY_ANT_ANT0; + ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO; + break; + } + +set_ant: + err = esp_phy_set_ant(&ant_config); + if (ESP_OK != err) { + log_e("Failed to set antenna configuration: 0x%x: %s", err, esp_err_to_name(err)); + return false; + } +#endif + return true; +} + +// ----------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------------ Generic Network function --------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +/* + * Deprecated Methods +*/ +int WiFiGenericClass::hostByName(const char *aHostname, IPAddress &aResult) { + return Network.hostByName(aHostname, aResult); +} + +IPAddress WiFiGenericClass::calculateNetworkID(IPAddress ip, IPAddress subnet) { + IPAddress networkID; + + for (size_t i = 0; i < 4; i++) { + networkID[i] = subnet[i] & ip[i]; + } + + return networkID; +} + +IPAddress WiFiGenericClass::calculateBroadcast(IPAddress ip, IPAddress subnet) { + IPAddress broadcastIp; + + for (int i = 0; i < 4; i++) { + broadcastIp[i] = ~subnet[i] | ip[i]; + } + + return broadcastIp; +} + +uint8_t WiFiGenericClass::calculateSubnetCIDR(IPAddress subnetMask) { + uint8_t CIDR = 0; + + for (uint8_t i = 0; i < 4; i++) { + if (subnetMask[i] == 0x80) { // 128 + CIDR += 1; + } else if (subnetMask[i] == 0xC0) { // 192 + CIDR += 2; + } else if (subnetMask[i] == 0xE0) { // 224 + CIDR += 3; + } else if (subnetMask[i] == 0xF0) { // 242 + CIDR += 4; + } else if (subnetMask[i] == 0xF8) { // 248 + CIDR += 5; + } else if (subnetMask[i] == 0xFC) { // 252 + CIDR += 6; + } else if (subnetMask[i] == 0xFE) { // 254 + CIDR += 7; + } else if (subnetMask[i] == 0xFF) { // 255 + CIDR += 8; + } + } + + return CIDR; +} + +wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventCb cbEvent, arduino_event_id_t event) { + return Network.onEvent(cbEvent, event); +} + +wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventFuncCb cbEvent, arduino_event_id_t event) { + return Network.onEvent(cbEvent, event); +} + +wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event) { + return Network.onEvent(cbEvent, event); +} + +void WiFiGenericClass::removeEvent(WiFiEventCb cbEvent, arduino_event_id_t event) { + Network.removeEvent(cbEvent, event); +} + +void WiFiGenericClass::removeEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event) { + Network.removeEvent(cbEvent, event); +} + +void WiFiGenericClass::removeEvent(wifi_event_id_t id) { + Network.removeEvent(id); +} + +int WiFiGenericClass::setStatusBits(int bits) { + return Network.setStatusBits(bits); +} + +int WiFiGenericClass::clearStatusBits(int bits) { + return Network.clearStatusBits(bits); +} + +int WiFiGenericClass::getStatusBits() { + return Network.getStatusBits(); +} + +int WiFiGenericClass::waitStatusBits(int bits, uint32_t timeout_ms) { + return Network.waitStatusBits(bits, timeout_ms); +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiGeneric.h b/libraries/WiFi/src/WiFiGeneric.h new file mode 100644 index 0000000..4270e4d --- /dev/null +++ b/libraries/WiFi/src/WiFiGeneric.h @@ -0,0 +1,164 @@ +/* + ESP8266WiFiGeneric.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "esp_err.h" +#include "esp_event.h" +#include +#include "WiFiType.h" +#include "IPAddress.h" +#include "esp_smartconfig.h" +#include "esp_netif_types.h" +#if CONFIG_ETH_ENABLED +#include "esp_eth_driver.h" +#endif +#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI +#include "network_provisioning/manager.h" +#endif +#include "lwip/ip_addr.h" + +#include "Network.h" + +#define WiFiEventCb NetworkEventCb +#define WiFiEventFuncCb NetworkEventFuncCb +#define WiFiEventSysCb NetworkEventSysCb +#define wifi_event_id_t network_event_handle_t + +typedef enum { + WIFI_POWER_21dBm = 84, // 21dBm + WIFI_POWER_20_5dBm = 82, // 20.5dBm + WIFI_POWER_20dBm = 80, // 20dBm + WIFI_POWER_19_5dBm = 78, // 19.5dBm + WIFI_POWER_19dBm = 76, // 19dBm + WIFI_POWER_18_5dBm = 74, // 18.5dBm + WIFI_POWER_17dBm = 68, // 17dBm + WIFI_POWER_15dBm = 60, // 15dBm + WIFI_POWER_13dBm = 52, // 13dBm + WIFI_POWER_11dBm = 44, // 11dBm + WIFI_POWER_8_5dBm = 34, // 8.5dBm + WIFI_POWER_7dBm = 28, // 7dBm + WIFI_POWER_5dBm = 20, // 5dBm + WIFI_POWER_2dBm = 8, // 2dBm + WIFI_POWER_MINUS_1dBm = -4 // -1dBm +} wifi_power_t; + +typedef enum { + WIFI_RX_ANT0 = 0, + WIFI_RX_ANT1, + WIFI_RX_ANT_AUTO +} wifi_rx_ant_t; + +typedef enum { + WIFI_TX_ANT0 = 0, + WIFI_TX_ANT1, + WIFI_TX_ANT_AUTO +} wifi_tx_ant_t; + +class WiFiGenericClass { +public: + WiFiGenericClass(); + +#if CONFIG_ESP_WIFI_REMOTE_ENABLED + // Set SDIO pins for connection to external ESP MCU + static bool setPins(int8_t clk, int8_t cmd, int8_t d0, int8_t d1, int8_t d2, int8_t d3, int8_t rst); +#endif + + wifi_event_id_t onEvent(WiFiEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX); + wifi_event_id_t onEvent(WiFiEventFuncCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX); + wifi_event_id_t onEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX); + void removeEvent(WiFiEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX); + void removeEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX); + void removeEvent(wifi_event_id_t id); + + static int getStatusBits(); + static int waitStatusBits(int bits, uint32_t timeout_ms); + + int32_t channel(void); + int setChannel(uint8_t primary, wifi_second_chan_t secondary = WIFI_SECOND_CHAN_NONE); + + void persistent(bool persistent); + void enableLongRange(bool enable); + + static bool mode(wifi_mode_t); + static wifi_mode_t getMode(); + + bool enableSTA(bool enable); + bool enableAP(bool enable); + + bool setSleep(bool enabled); + bool setSleep(wifi_ps_type_t sleepType); + wifi_ps_type_t getSleep(); + + bool setTxPower(wifi_power_t power); + wifi_power_t getTxPower(); + +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 2) + bool setBandMode(wifi_band_mode_t band_mode); + wifi_band_mode_t getBandMode(); +#endif + wifi_band_t getBand(); + + bool initiateFTM(uint8_t frm_count = 16, uint16_t burst_period = 2, uint8_t channel = 1, const uint8_t *mac = NULL); + + static bool setDualAntennaConfig(uint8_t gpio_ant1, uint8_t gpio_ant2, wifi_rx_ant_t rx_mode, wifi_tx_ant_t tx_mode); + + static const char *getHostname(); + static bool setHostname(const char *hostname); + static bool hostname(const String &aHostname) { + return setHostname(aHostname.c_str()); + } + + static void useStaticBuffers(bool bufferMode); + static bool useStaticBuffers(); + + static int hostByName(const char *aHostname, IPAddress &aResult); + + static IPAddress calculateNetworkID(IPAddress ip, IPAddress subnet); + static IPAddress calculateBroadcast(IPAddress ip, IPAddress subnet); + static uint8_t calculateSubnetCIDR(IPAddress subnetMask); + + const char *disconnectReasonName(wifi_err_reason_t reason); + const char *eventName(arduino_event_id_t id); + + static void _eventCallback(arduino_event_t *event); + +protected: + static bool _persistent; + static bool _long_range; + static wifi_ps_type_t _sleepEnabled; + static bool _wifiUseStaticBuffers; + + static int setStatusBits(int bits); + static int clearStatusBits(int bits); + + friend class WiFiSTAClass; + friend class WiFiScanClass; + friend class WiFiAPClass; + friend class ETHClass; +}; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiMulti.cpp b/libraries/WiFi/src/WiFiMulti.cpp new file mode 100644 index 0000000..c99bef5 --- /dev/null +++ b/libraries/WiFi/src/WiFiMulti.cpp @@ -0,0 +1,353 @@ +/** + * + * @file WiFiMulti.cpp + * @date 16.05.2015 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the esp8266 core for Arduino environment. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include "WiFiMulti.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED +#include +#include +#include + +WiFiMulti::WiFiMulti() { + ipv6_support = false; +} + +void WiFiMulti::APlistClean(void) { + for (auto entry : APlist) { + if (entry.ssid) { + free(entry.ssid); + } + if (entry.passphrase) { + free(entry.passphrase); + } + } + APlist.clear(); +} + +WiFiMulti::~WiFiMulti() { + APlistClean(); +} + +bool WiFiMulti::addAP(const char *ssid, const char *passphrase) { + WifiAPlist_t newAP; + + if (!ssid || *ssid == '\0' || strlen(ssid) > 31) { + // fail SSID too long or missing! + log_e("[WIFI][APlistAdd] no ssid or ssid too long"); + return false; + } + + if (passphrase && strlen(passphrase) > 63) { + // fail passphrase too long! + log_e("[WIFI][APlistAdd] passphrase too long"); + return false; + } + + newAP.ssid = strdup(ssid); + + if (!newAP.ssid) { + log_e("[WIFI][APlistAdd] fail newAP.ssid == 0"); + return false; + } + + if (passphrase && *passphrase != '\0') { + newAP.passphrase = strdup(passphrase); + if (!newAP.passphrase) { + log_e("[WIFI][APlistAdd] fail newAP.passphrase == 0"); + free(newAP.ssid); + return false; + } + } else { + newAP.passphrase = NULL; + } + newAP.hasFailed = false; + APlist.push_back(newAP); + log_i("[WIFI][APlistAdd] add SSID: %s", newAP.ssid); + return true; +} + +uint8_t WiFiMulti::run(uint32_t connectTimeout, bool scanHidden) { + int8_t scanResult; + unsigned long startTime; + uint8_t status = WiFi.status(); + if (status == WL_CONNECTED) { + if (!_bWFMInit && _connectionTestCBFunc != NULL) { + if (_connectionTestCBFunc() == true) { + _bWFMInit = true; + return status; + } + } else { + if (!_bStrict) { + return status; + } else { + for (auto ap : APlist) { + if (WiFi.SSID() == ap.ssid) { + return status; + } + } + } + } + WiFi.disconnect(false, false); + delay(10); + status = WiFi.status(); + } + + scanResult = WiFi.scanNetworks(false, scanHidden); + if (scanResult == WIFI_SCAN_RUNNING) { + // scan is running + return WL_NO_SSID_AVAIL; + } else if (scanResult >= 0) { + // scan done analyze + int32_t bestIndex = -1; + WifiAPlist_t bestNetwork{NULL, NULL, false}; + int bestNetworkDb = INT_MIN; + int bestNetworkSec = WIFI_AUTH_MAX; + uint8_t bestBSSID[6]; + int32_t bestChannel = 0; + + log_i("[WIFI] scan done"); + + if (scanResult == 0) { + log_e("[WIFI] no networks found"); + } else { + log_i("[WIFI] %d networks found", scanResult); + + int8_t failCount = 0; + int8_t foundCount = 0; + for (int8_t i = 0; i < scanResult; ++i) { + + String ssid_scan; + int32_t rssi_scan; + uint8_t sec_scan; + uint8_t *BSSID_scan; + int32_t chan_scan; + bool hidden_scan; + + WiFi.getNetworkInfo(i, ssid_scan, sec_scan, rssi_scan, BSSID_scan, chan_scan); + hidden_scan = (ssid_scan.length() == 0) && scanHidden; + // add any Open WiFi AP to the list, if allowed with setAllowOpenAP(true) + if (_bAllowOpenAP && sec_scan == WIFI_AUTH_OPEN) { + bool found = false; + for (auto check : APlist) { + if (ssid_scan == check.ssid) { + found = true; + break; + } + } + // If we didn't find it, add this Open WiFi AP to the list + if (!found) { + log_i("[WIFI][APlistAdd] adding Open WiFi SSID: %s", ssid_scan.c_str()); + addAP(ssid_scan.c_str()); + } + } + + if (hidden_scan) { + log_v("hidden ssid on channel %d found, trying to connect with known credentials...", chan_scan); + } + + bool known = false; + for (uint32_t x = 0; x < APlist.size(); x++) { + WifiAPlist_t entry = APlist[x]; + + if (ssid_scan == entry.ssid || hidden_scan) { // SSID match or hidden network found + if (!hidden_scan) { + log_v("known ssid: %s, has failed: %s", entry.ssid, entry.hasFailed ? "yes" : "no"); + foundCount++; + } + if (!entry.hasFailed) { + if (hidden_scan) { + WiFi.begin(entry.ssid, entry.passphrase, chan_scan, BSSID_scan); + + // If the ssid returned from the scan is empty, it is a hidden SSID + // it appears that the WiFi.begin() function is asynchronous and takes + // additional time to connect to a hidden SSID. Therefore a delay of 1000ms + // is added for hidden SSIDs before calling WiFi.status() + delay(1000); + + status = WiFi.status(); + startTime = millis(); + + while (status != WL_CONNECTED && (millis() - startTime) <= connectTimeout) { + delay(10); + status = WiFi.status(); + } + + WiFi.disconnect(); + delay(10); + + if (status == WL_CONNECTED) { + log_v("hidden ssid %s found", entry.ssid); + ssid_scan = entry.ssid; + foundCount++; + } else { + continue; + } + } + known = true; + log_v("rssi_scan: %d, bestNetworkDb: %d", rssi_scan, bestNetworkDb); + if (rssi_scan > bestNetworkDb) { // best network + if (_bAllowOpenAP || (sec_scan == WIFI_AUTH_OPEN || entry.passphrase)) { // check for passphrase if not open wlan + log_v("best network is now: %s", ssid_scan); + bestIndex = x; + bestNetworkSec = sec_scan; + bestNetworkDb = rssi_scan; + bestChannel = chan_scan; + memcpy((void *)&bestNetwork, (void *)&entry, sizeof(bestNetwork)); + memcpy((void *)&bestBSSID, (void *)BSSID_scan, sizeof(bestBSSID)); + } + } + break; + } else { + failCount++; + } + } + } + + if (known) { + log_d( + " ---> %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) (%c) (%s)", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3], + BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*', (hidden_scan) ? "hidden" : "visible" + ); + } else { + log_d( + " %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) (%c) (%s)", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3], + BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*', (hidden_scan) ? "hidden" : "visible" + ); + } + } + log_v("foundCount = %d, failCount = %d", foundCount, failCount); + // if all the APs in the list have failed, reset the failure flags + if (foundCount == failCount) { + resetFails(); // keeps trying the APs in the list + } + } + // clean up ram + WiFi.scanDelete(); + + if (bestIndex >= 0) { + log_i( + "[WIFI] Connecting BSSID: %02X:%02X:%02X:%02X:%02X:%02X SSID: %s Channel: %d (%d)", bestBSSID[0], bestBSSID[1], bestBSSID[2], bestBSSID[3], + bestBSSID[4], bestBSSID[5], bestNetwork.ssid, bestChannel, bestNetworkDb + ); + +#if CONFIG_LWIP_IPV6 + if (ipv6_support == true) { + WiFi.enableIPv6(); + } +#endif + WiFi.disconnect(); + delay(10); + WiFi.begin(bestNetwork.ssid, (_bAllowOpenAP && bestNetworkSec == WIFI_AUTH_OPEN) ? NULL : bestNetwork.passphrase, bestChannel, bestBSSID); + status = WiFi.status(); + _bWFMInit = true; + + startTime = millis(); + // wait for connection, fail, or timeout + while (status != WL_CONNECTED && (millis() - startTime) <= connectTimeout) { // && status != WL_NO_SSID_AVAIL && status != WL_CONNECT_FAILED + delay(10); + status = WiFi.status(); + } + + switch (status) { + case WL_CONNECTED: + log_i("[WIFI] Connecting done."); + log_d("[WIFI] SSID: %s", WiFi.SSID().c_str()); + log_d("[WIFI] IP: %s", WiFi.localIP().toString().c_str()); + log_d("[WIFI] MAC: %s", WiFi.BSSIDstr().c_str()); + log_d("[WIFI] Channel: %d", WiFi.channel()); + + if (_connectionTestCBFunc != NULL) { + // We connected to an AP but if it's a captive portal we're not going anywhere. Test it. + if (_connectionTestCBFunc()) { + resetFails(); + } else { + markAsFailed(bestIndex); + WiFi.disconnect(); + delay(10); + status = WiFi.status(); + } + } else { + resetFails(); + } + break; + case WL_NO_SSID_AVAIL: + log_e("[WIFI] Connecting Failed AP not found."); + markAsFailed(bestIndex); + break; + case WL_CONNECT_FAILED: + log_e("[WIFI] Connecting Failed."); + markAsFailed(bestIndex); + break; + default: + log_e("[WIFI] Connecting Failed (%d).", status); + markAsFailed(bestIndex); + break; + } + } else { + log_e("[WIFI] no matching wifi found!"); + } + } else { + // start scan + log_d("[WIFI] delete old wifi config..."); + WiFi.disconnect(); + + log_d("[WIFI] start scan"); + // scan wifi async mode + WiFi.scanNetworks(true); + } + + return status; +} + +#if CONFIG_LWIP_IPV6 +void WiFiMulti::enableIPv6(bool state) { + ipv6_support = state; +} +#endif + +void WiFiMulti::markAsFailed(int32_t i) { + APlist[i].hasFailed = true; + log_d("[WIFI] Marked SSID %s as failed", APlist[i].ssid); +} + +void WiFiMulti::resetFails() { + for (uint32_t i = 0; i < APlist.size(); i++) { + APlist[i].hasFailed = false; + } + log_d("[WIFI] Resetting failure flags"); +} + +void WiFiMulti::setStrictMode(bool bStrict) { + _bStrict = bStrict; +} + +void WiFiMulti::setAllowOpenAP(bool bAllowOpenAP) { + _bAllowOpenAP = bAllowOpenAP; +} + +void WiFiMulti::setConnectionTestCallbackFunc(ConnectionTestCB_t cbFunc) { + _connectionTestCBFunc = cbFunc; +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiMulti.h b/libraries/WiFi/src/WiFiMulti.h new file mode 100644 index 0000000..d818f77 --- /dev/null +++ b/libraries/WiFi/src/WiFiMulti.h @@ -0,0 +1,83 @@ +/** + * + * @file ESP8266WiFiMulti.h + * @date 16.05.2015 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the esp8266 core for Arduino environment. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "WiFi.h" +#include + +typedef struct { + char *ssid; + char *passphrase; + bool hasFailed; +} WifiAPlist_t; + +typedef std::function ConnectionTestCB_t; + +class WiFiMulti { +public: + WiFiMulti(); + ~WiFiMulti(); + + bool addAP(const char *ssid, const char *passphrase = NULL); + uint8_t run(uint32_t connectTimeout = 5000, bool scanHidden = false); +#if CONFIG_LWIP_IPV6 + void enableIPv6(bool state); +#endif + + // Force (default: true) to only keep connected or to connect to an AP from the provided WiFiMulti list. + // When bStrict is false, it will keep the last/current connected AP even if not in the WiFiMulti List. + void setStrictMode(bool bStrict = true); + + // allows (true) to connect to ANY open AP, even if not in the user list + // default false (do not connect to an open AP that has not been explicitaly added by the user to list) + void setAllowOpenAP(bool bAllowOpenAP = false); + + // clears the current list of Multi APs and frees the memory + void APlistClean(void); + + // allow the user to define a callback function that will validate the connection to the Internet. + // if the callback returns true, the connection is considered valid and the AP will added to the validated AP list. + // set the callback to NULL to disable the feature and validate any SSID that is in the list. + void setConnectionTestCallbackFunc(ConnectionTestCB_t cbFunc); + +private: + std::vector APlist; + bool ipv6_support; + + bool _bStrict = true; + bool _bAllowOpenAP = false; + ConnectionTestCB_t _connectionTestCBFunc = NULL; + bool _bWFMInit = false; + + void markAsFailed(int32_t i); + void resetFails(); +}; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiSTA.cpp b/libraries/WiFi/src/WiFiSTA.cpp new file mode 100644 index 0000000..3e4260b --- /dev/null +++ b/libraries/WiFi/src/WiFiSTA.cpp @@ -0,0 +1,486 @@ +/* + WiFiSTA.cpp - WiFi library for esp32 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiSTA.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/err.h" +#include "lwip/dns.h" +#include +#include +#include "esp_mac.h" + +#if __has_include("esp_eap_client.h") +#include "esp_eap_client.h" +#else +#include "esp_wpa2.h" +#endif + +// ----------------------------------------------------------------------------------------------------------------------- +// ---------------------------------------------------- STA function ----------------------------------------------------- +// ----------------------------------------------------------------------------------------------------------------------- + +/** + * Return Connection status. + * @return one of the value defined in wl_status_t + * + */ +wl_status_t WiFiSTAClass::status() { + return STA.status(); +} + +#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT +wl_status_t WiFiSTAClass::begin( + const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity, const char *wpa2_username, const char *wpa2_password, const char *ca_pem, + const char *client_crt, const char *client_key, int ttls_phase2_type, int32_t channel, const uint8_t *bssid, bool tryConnect +) { + if (!STA.begin()) { + return WL_CONNECT_FAILED; + } + + if (!STA.connect( + wpa2_ssid, method, wpa2_identity, wpa2_username, wpa2_password, ca_pem, client_crt, client_key, ttls_phase2_type, channel, bssid, tryConnect + )) { + return WL_CONNECT_FAILED; + } + + return STA.status(); +} +#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */ + +wl_status_t WiFiSTAClass::begin(const char *ssid, const char *passphrase, int32_t channel, const uint8_t *bssid, bool tryConnect) { + if (!STA.begin()) { + return WL_CONNECT_FAILED; + } + + if (!STA.connect(ssid, passphrase, channel, bssid, tryConnect)) { + return WL_CONNECT_FAILED; + } + + return STA.status(); +} + +/** + * Use to connect to SDK config. + * @return wl_status_t + */ +wl_status_t WiFiSTAClass::begin() { + if (!STA.begin(true)) { + return WL_CONNECT_FAILED; + } + + return STA.status(); +} + +/** + * will force a disconnect and then start reconnecting to AP + * @return true when successful + */ +bool WiFiSTAClass::reconnect() { + return STA.reconnect(); +} + +/** + * Disconnect from the network. + * @param wifioff `true` to turn the Wi-Fi radio off. + * @param eraseap `true` to erase the AP configuration from the NVS memory. + * @return `true` when successful. + */ +bool WiFiSTAClass::disconnectAsync(bool wifioff, bool eraseap) { + return disconnect(wifioff, eraseap, 0); +} + +/** + * Disconnect from the network. + * @param wifioff `true` to turn the Wi-Fi radio off. + * @param eraseap `true` to erase the AP configuration from the NVS memory. + * @param timeoutLength timeout to wait for status change + * @return `true` when successful. + */ +bool WiFiSTAClass::disconnect(bool wifioff, bool eraseap, unsigned long timeoutLength) { + if (!STA.disconnect(eraseap, timeoutLength)) { + return false; + } + if (wifioff) { + return STA.end(); + } + return true; +} + +/** + * @brief Reset WiFi settings in NVS to default values. + * + * This function will reset settings made using the following APIs: + * - esp_wifi_set_bandwidth, + * - esp_wifi_set_protocol, + * - esp_wifi_set_config related + * - esp_wifi_set_mode + * + * @return true if erase succeeded + * @note: Resets SSID, password, protocol, mode, etc. + * These settings are maintained by WiFi driver in IDF. + * WiFi driver must be initialized. + */ +bool WiFiSTAClass::eraseAP(void) { + return STA.erase(); +} + +/** + * Change IP configuration settings disabling the dhcp client + * @param local_ip Static ip configuration + * @param gateway Static gateway configuration + * @param subnet Static Subnet mask + * @param dns1 Static DNS server 1 + * @param dns2 Static DNS server 2 + */ +bool WiFiSTAClass::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2) { + // handle Arduino ordering of parameters: ip, dns, gw, subnet + if (local_ip.type() == IPv4 && local_ip != INADDR_NONE && subnet[0] != 255) { + IPAddress tmp = dns1; + dns1 = gateway; + gateway = subnet; + subnet = (tmp != INADDR_NONE) ? tmp : IPAddress(255, 255, 255, 0); + } + + return STA.begin() && STA.config(local_ip, gateway, subnet, dns1, dns2); +} + +bool WiFiSTAClass::config(IPAddress local_ip, IPAddress dns) { + + if (local_ip == INADDR_NONE) { + return config(INADDR_NONE, INADDR_NONE, INADDR_NONE); + } + + if (local_ip.type() != IPv4) { + return false; + } + + IPAddress gw(local_ip); + gw[3] = 1; + if (dns == INADDR_NONE) { + dns = gw; + } + return config(local_ip, gw, IPAddress(255, 255, 255, 0), dns); +} + +/** + * Change DNS server for static IP configuration + * @param dns1 Static DNS server 1 + * @param dns2 Static DNS server 2 (optional) + */ +bool WiFiSTAClass::setDNS(IPAddress dns1, IPAddress dns2) { + return STA.begin() && STA.dnsIP(0, dns1) && STA.dnsIP(1, dns2); +} + +/** + * Sets the working bandwidth of the STA mode + * @param m wifi_bandwidth_t + */ +bool WiFiSTAClass::bandwidth(wifi_bandwidth_t bandwidth) { + return STA.bandwidth(bandwidth); +} + +/** + * is STA interface connected? + * @return true if STA is connected to an AP + */ +bool WiFiSTAClass::isConnected() { + return STA.connected() && STA.hasIP(); +} + +/** + * Set the minimum security for AP to be considered connectable. + * Must be called before WiFi.begin(). + * @param minSecurity wifi_auth_mode_t + */ +void WiFiSTAClass::setMinSecurity(wifi_auth_mode_t minSecurity) { + return STA.setMinSecurity(minSecurity); +} + +/** + * Set the way that AP is chosen. + * First SSID match[WIFI_FAST_SCAN] or Sorted[WIFI_ALL_CHANNEL_SCAN] (RSSI or Security) + * Must be called before WiFi.begin() + * @param scanMethod wifi_scan_method_t + */ +void WiFiSTAClass::setScanMethod(wifi_scan_method_t scanMethod) { + return STA.setScanMethod(scanMethod); +} + +/** + * Set the way that AP is sorted. (requires scanMethod WIFI_ALL_CHANNEL_SCAN) + * By SSID[WIFI_CONNECT_AP_BY_SIGNAL] or Security[WIFI_CONNECT_AP_BY_SECURITY] + * Must be called before WiFi.begin() + * @param sortMethod wifi_sort_method_t + */ +void WiFiSTAClass::setSortMethod(wifi_sort_method_t sortMethod) { + return STA.setSortMethod(sortMethod); +} + +/** + * Function used to set the automatic reconnection if the connection is lost. + * @param autoReconnect `true` to enable this option. + * @return true + */ +bool WiFiSTAClass::setAutoReconnect(bool autoReconnect) { + return STA.setAutoReconnect(autoReconnect); +} +/** + * Function used to get the automatic reconnection if the connection is lost. + * @return The function will return `true` if this setting is enabled. + */ +bool WiFiSTAClass::getAutoReconnect() { + return STA.getAutoReconnect(); +} + +/** + * Wait for WiFi connection to reach a result + * returns the status reached or disconnect if STA is off + * @return wl_status_t + */ +uint8_t WiFiSTAClass::waitForConnectResult(unsigned long timeoutLength) { + return STA.waitForConnectResult(timeoutLength); +} + +/** + * Get the station interface IP address. + * @return IPAddress station IP + */ +IPAddress WiFiSTAClass::localIP() { + return STA.localIP(); +} + +/** + * Get the station interface MAC address. + * @param mac pointer to uint8_t array with length WL_MAC_ADDR_LENGTH + * @return pointer to uint8_t * + */ +uint8_t *WiFiSTAClass::macAddress(uint8_t *mac) { + return STA.macAddress(mac); +} + +/** + * Get the station interface MAC address. + * @return String mac + */ +String WiFiSTAClass::macAddress(void) { + return STA.macAddress(); +} + +/** + * Get the interface subnet mask address. + * @return IPAddress subnetMask + */ +IPAddress WiFiSTAClass::subnetMask() { + return STA.subnetMask(); +} + +/** + * Get the gateway ip address. + * @return IPAddress gatewayIP + */ +IPAddress WiFiSTAClass::gatewayIP() { + return STA.gatewayIP(); +} + +/** + * Get the DNS ip address. + * @param dns_no + * @return IPAddress DNS Server IP + */ +IPAddress WiFiSTAClass::dnsIP(uint8_t dns_no) { + return STA.dnsIP(dns_no); +} + +/** + * Get the broadcast ip address. + * @return IPAddress broadcastIP + */ +IPAddress WiFiSTAClass::broadcastIP() { + return STA.broadcastIP(); +} + +/** + * Get the network id. + * @return IPAddress networkID + */ +IPAddress WiFiSTAClass::networkID() { + return STA.networkID(); +} + +/** + * Get the subnet CIDR. + * @return uint8_t subnetCIDR + */ +uint8_t WiFiSTAClass::subnetCIDR() { + return STA.subnetCIDR(); +} + +/** + * Return the current SSID associated with the network + * @return SSID + */ +String WiFiSTAClass::SSID() const { + return STA.SSID(); +} + +/** + * Return the current pre shared key associated with the network + * @return psk string + */ +String WiFiSTAClass::psk() const { + return STA.psk(); +} + +/** + * Return the current bssid / mac associated with the network if configured + * @return bssid uint8_t * + */ +uint8_t *WiFiSTAClass::BSSID(uint8_t *buff) { + return STA.BSSID(buff); +} + +/** + * Return the current bssid / mac associated with the network if configured + * @return String bssid mac + */ +String WiFiSTAClass::BSSIDstr(void) { + return STA.BSSIDstr(); +} + +/** + * Return the current network RSSI. + * @return RSSI value + */ +int8_t WiFiSTAClass::RSSI(void) { + return STA.RSSI(); +} + +#if CONFIG_LWIP_IPV6 +/** + * Enable IPv6 on the station interface. + * Should be called before WiFi.begin() + * + * @return true on success + */ +bool WiFiSTAClass::enableIPv6(bool en) { + return STA.enableIPv6(en); +} + +/** + * Get the station interface link-local IPv6 address. + * @return IPAddress + */ +IPAddress WiFiSTAClass::linkLocalIPv6() { + return STA.linkLocalIPv6(); +} + +/** + * Get the station interface global IPv6 address. + * @return IPAddress + */ +IPAddress WiFiSTAClass::globalIPv6() { + return STA.globalIPv6(); +} +#endif + +bool WiFiSTAClass::_smartConfigStarted = false; +bool WiFiSTAClass::_smartConfigDone = false; + +/** + * @brief + * + * @param type Select type of SmartConfig. Default type is SC_TYPE_ESPTOUCH + * @param crypt_key When using type SC_TYPE_ESPTOUTCH_V2 crypt key needed, else ignored. Length should be 16 chars. + * @return true if configuration is successful. + * @return false if configuration fails. + */ +bool WiFiSTAClass::beginSmartConfig(smartconfig_type_t type, char *crypt_key) { + esp_err_t err; + if (_smartConfigStarted) { + return false; + } + + if (!WiFi.mode(WIFI_STA)) { + return false; + } + esp_wifi_disconnect(); + + smartconfig_start_config_t conf = SMARTCONFIG_START_CONFIG_DEFAULT(); + + if (type == SC_TYPE_ESPTOUCH_V2) { + conf.esp_touch_v2_enable_crypt = true; + conf.esp_touch_v2_key = crypt_key; + } + + err = esp_smartconfig_set_type(type); + if (err != ESP_OK) { + log_e("SmartConfig Set Type Failed!"); + return false; + } + err = esp_smartconfig_start(&conf); + if (err != ESP_OK) { + log_e("SmartConfig Start Failed!"); + return false; + } + _smartConfigStarted = true; + _smartConfigDone = false; + return true; +} + +bool WiFiSTAClass::stopSmartConfig() { + if (!_smartConfigStarted) { + return true; + } + + if (esp_smartconfig_stop() == ESP_OK) { + _smartConfigStarted = false; + return true; + } + + return false; +} + +bool WiFiSTAClass::smartConfigDone() { + if (!_smartConfigStarted) { + return false; + } + + return _smartConfigDone; +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiSTA.h b/libraries/WiFi/src/WiFiSTA.h new file mode 100644 index 0000000..22c3a1d --- /dev/null +++ b/libraries/WiFi/src/WiFiSTA.h @@ -0,0 +1,224 @@ +/* + ESP8266WiFiSTA.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "WiFiType.h" +#include "WiFiGeneric.h" +#ifdef ESP_IDF_VERSION_MAJOR +#include "esp_event.h" +#endif + +typedef enum { + WPA2_AUTH_TLS = 0, + WPA2_AUTH_PEAP = 1, + WPA2_AUTH_TTLS = 2 +} wpa2_auth_method_t; + +// ---------------------------------------------------------------------------------------------- +// ------------------------------------ NEW STA Implementation ---------------------------------- +// ---------------------------------------------------------------------------------------------- + +class STAClass : public NetworkInterface { +public: + STAClass(); + ~STAClass(); + + bool begin(bool tryConnect = false); + bool end(); + + bool bandwidth(wifi_bandwidth_t bandwidth); + + bool connect(); + bool connect(const char *ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool tryConnect = true); + bool connect(const String &ssid, const String &passphrase = emptyString, int32_t channel = 0, const uint8_t *bssid = NULL, bool tryConnect = true) { + return connect(ssid.c_str(), passphrase.c_str(), channel, bssid, tryConnect); + } + +#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT + bool connect( + const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity = NULL, const char *wpa2_username = NULL, const char *wpa2_password = NULL, + const char *ca_pem = NULL, const char *client_crt = NULL, const char *client_key = NULL, int ttls_phase2_type = -1, int32_t channel = 0, + const uint8_t *bssid = 0, bool tryConnect = true + ); + bool connect( + const String &wpa2_ssid, wpa2_auth_method_t method, const String &wpa2_identity = emptyString, const String &wpa2_username = emptyString, + const String &wpa2_password = emptyString, const String &ca_pem = emptyString, const String &client_crt = emptyString, + const String &client_key = emptyString, int ttls_phase2_type = -1, int32_t channel = 0, const uint8_t *bssid = 0, bool tryConnect = true + ) { + return connect( + wpa2_ssid.c_str(), method, wpa2_identity.c_str(), wpa2_username.c_str(), wpa2_password.c_str(), ca_pem.c_str(), client_crt.c_str(), client_key.c_str(), + ttls_phase2_type, channel, bssid, tryConnect + ); + } +#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */ + bool disconnect(bool eraseap = false, unsigned long timeout = 0); + bool reconnect(); + bool erase(); + + uint8_t waitForConnectResult(unsigned long timeoutLength = 60000); + + bool setAutoReconnect(bool autoReconnect); + bool getAutoReconnect(); + + // Next group functions must be called before WiFi.begin() + void setMinSecurity(wifi_auth_mode_t minSecurity); // Default is WIFI_AUTH_WPA2_PSK + void setScanMethod(wifi_scan_method_t scanMethod); // Default is WIFI_FAST_SCAN + void setSortMethod(wifi_sort_method_t sortMethod); // Default is WIFI_CONNECT_AP_BY_SIGNAL + + wl_status_t status(); + + String SSID() const; + String psk() const; + uint8_t *BSSID(uint8_t *bssid = NULL); + String BSSIDstr(); + int8_t RSSI(); + + const char *disconnectReasonName(wifi_err_reason_t reason); + + // Private Use + void _setStatus(wl_status_t status); + void _onStaEvent(int32_t event_id, void *event_data); + +protected: + wifi_auth_mode_t _minSecurity; + wifi_scan_method_t _scanMethod; + wifi_sort_method_t _sortMethod; + bool _autoReconnect; + wl_status_t _status; + network_event_handle_t _wifi_sta_event_handle; + + size_t printDriverInfo(Print &out) const; + + friend class WiFiGenericClass; + bool onEnable(); + bool onDisable(); +}; + +// ---------------------------------------------------------------------------------------------- +// ------------------------------- OLD STA API (compatibility) ---------------------------------- +// ---------------------------------------------------------------------------------------------- + +class WiFiSTAClass { +public: + STAClass STA; + +#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT + wl_status_t begin( + const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity = NULL, const char *wpa2_username = NULL, const char *wpa2_password = NULL, + const char *ca_pem = NULL, const char *client_crt = NULL, const char *client_key = NULL, int ttls_phase2_type = -1, int32_t channel = 0, + const uint8_t *bssid = 0, bool tryConnect = true + ); + wl_status_t begin( + const String &wpa2_ssid, wpa2_auth_method_t method, const String &wpa2_identity = (const char *)NULL, const String &wpa2_username = (const char *)NULL, + const String &wpa2_password = (const char *)NULL, const String &ca_pem = (const char *)NULL, const String &client_crt = (const char *)NULL, + const String &client_key = (const char *)NULL, int ttls_phase2_type = -1, int32_t channel = 0, const uint8_t *bssid = 0, bool tryConnect = true + ) { + return begin( + wpa2_ssid.c_str(), method, wpa2_identity.c_str(), wpa2_username.c_str(), wpa2_password.c_str(), ca_pem.c_str(), client_crt.c_str(), client_key.c_str(), + ttls_phase2_type, channel, bssid, tryConnect + ); + } +#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */ + + wl_status_t begin(const char *ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool tryConnect = true); + wl_status_t + begin(const String &ssid, const String &passphrase = (const char *)NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool tryConnect = true) { + return begin(ssid.c_str(), passphrase.c_str(), channel, bssid, tryConnect); + } + wl_status_t begin(); + + // also accepts Arduino ordering of parameters: ip, dns, gw, mask + bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000); + + // two and one parameter version. 2nd parameter is DNS like in Arduino + bool config(IPAddress local_ip, IPAddress dns = (uint32_t)0x00000000); + + bool setDNS(IPAddress dns1, IPAddress dns2 = (uint32_t)0x00000000); // sets DNS IP for all network interfaces + + bool bandwidth(wifi_bandwidth_t bandwidth); + + bool reconnect(); + bool disconnectAsync(bool wifioff = false, bool eraseap = false); + bool disconnect(bool wifioff = false, bool eraseap = false, unsigned long timeoutLength = 100); + bool eraseAP(void); + + bool isConnected(); + + bool setAutoReconnect(bool autoReconnect); + bool getAutoReconnect(); + + uint8_t waitForConnectResult(unsigned long timeoutLength = 60000); + + // Next group functions must be called before WiFi.begin() + void setMinSecurity(wifi_auth_mode_t minSecurity); // Default is WIFI_AUTH_WPA2_PSK + void setScanMethod(wifi_scan_method_t scanMethod); // Default is WIFI_FAST_SCAN + void setSortMethod(wifi_sort_method_t sortMethod); // Default is WIFI_CONNECT_AP_BY_SIGNAL + + // STA WiFi info + wl_status_t status(); + String SSID() const; + String psk() const; + + uint8_t *BSSID(uint8_t *bssid = NULL); + String BSSIDstr(); + + int8_t RSSI(); + + IPAddress localIP(); + + uint8_t *macAddress(uint8_t *mac); + String macAddress(); + + IPAddress subnetMask(); + IPAddress gatewayIP(); + IPAddress dnsIP(uint8_t dns_no = 0); + + IPAddress broadcastIP(); + IPAddress networkID(); + uint8_t subnetCIDR(); + +#if CONFIG_LWIP_IPV6 + bool enableIPv6(bool en = true); + IPAddress linkLocalIPv6(); + IPAddress globalIPv6(); +#endif + + // ---------------------------------------------------------------------------------------------- + // ---------------------------------------- Smart Config ---------------------------------------- + // ---------------------------------------------------------------------------------------------- +protected: + static bool _smartConfigStarted; + +public: + bool beginSmartConfig(smartconfig_type_t type = SC_TYPE_ESPTOUCH, char *crypt_key = NULL); + bool stopSmartConfig(); + bool smartConfigDone(); + + static bool _smartConfigDone; +}; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiScan.cpp b/libraries/WiFi/src/WiFiScan.cpp new file mode 100644 index 0000000..b9978d8 --- /dev/null +++ b/libraries/WiFi/src/WiFiScan.cpp @@ -0,0 +1,294 @@ +/* + ESP8266WiFiScan.cpp - WiFi library for esp8266 + + Copyright (c) 2014 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Reworked on 28 Dec 2015 by Markus Sattler + + */ + +#include "WiFi.h" +#include "WiFiGeneric.h" +#include "WiFiScan.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +extern "C" { +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lwip/err.h" +} + +bool WiFiScanClass::_scanAsync = false; +uint32_t WiFiScanClass::_scanStarted = 0; +uint32_t WiFiScanClass::_scanTimeout = 60000; +uint16_t WiFiScanClass::_scanCount = 0; +uint32_t WiFiScanClass::_scanActiveMinTime = 100; + +void *WiFiScanClass::_scanResult = nullptr; + +void WiFiScanClass::setScanTimeout(uint32_t ms) { + WiFiScanClass::_scanTimeout = ms; +} + +void WiFiScanClass::setScanActiveMinTime(uint32_t ms) { + WiFiScanClass::_scanActiveMinTime = ms; +} + +/** + * Start scan WiFi networks available + * @param async run in async mode + * @param show_hidden show hidden networks + * @return Number of discovered networks + */ +int16_t + WiFiScanClass::scanNetworks(bool async, bool show_hidden, bool passive, uint32_t max_ms_per_chan, uint8_t channel, const char *ssid, const uint8_t *bssid) { + if (WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) { + return WIFI_SCAN_RUNNING; + } + + WiFiScanClass::_scanAsync = async; + + WiFi.enableSTA(true); + + scanDelete(); + + wifi_scan_config_t config; + memset(&config, 0, sizeof(wifi_scan_config_t)); + config.ssid = (uint8_t *)ssid; + config.bssid = (uint8_t *)bssid; + config.channel = channel; + config.show_hidden = show_hidden; + if (passive) { + config.scan_type = WIFI_SCAN_TYPE_PASSIVE; + config.scan_time.passive = max_ms_per_chan; + } else { + config.scan_type = WIFI_SCAN_TYPE_ACTIVE; + config.scan_time.active.min = _scanActiveMinTime; + config.scan_time.active.max = max_ms_per_chan; + } + if (esp_wifi_scan_start(&config, false) == ESP_OK) { + _scanStarted = millis(); + + WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT); + WiFiGenericClass::setStatusBits(WIFI_SCANNING_BIT); + + if (WiFiScanClass::_scanAsync) { + return WIFI_SCAN_RUNNING; + } + if (WiFiGenericClass::waitStatusBits(WIFI_SCAN_DONE_BIT, _scanTimeout)) { + return (int16_t)WiFiScanClass::_scanCount; + } + } + return WIFI_SCAN_FAILED; +} + +/** + * private + * scan callback + * @param result void *arg + * @param status STATUS + */ +void WiFiScanClass::_scanDone() { + if (!(WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT)) { + return; //Ignore if not scanning, scan was started by other + } + esp_wifi_scan_get_ap_num(&(WiFiScanClass::_scanCount)); + if (WiFiScanClass::_scanResult) { + free(WiFiScanClass::_scanResult); + WiFiScanClass::_scanResult = NULL; + } + + if (WiFiScanClass::_scanCount) { + WiFiScanClass::_scanResult = calloc(WiFiScanClass::_scanCount, sizeof(wifi_ap_record_t)); + if (!WiFiScanClass::_scanResult) { + WiFiScanClass::_scanCount = 0; + } else if (esp_wifi_scan_get_ap_records(&(WiFiScanClass::_scanCount), (wifi_ap_record_t *)_scanResult) != ESP_OK) { + free(WiFiScanClass::_scanResult); + WiFiScanClass::_scanResult = NULL; + WiFiScanClass::_scanCount = 0; + } + } + WiFiGenericClass::setStatusBits(WIFI_SCAN_DONE_BIT); + WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT); +} + +/** + * + * @param i specify from which network item want to get the information + * @return bss_info * + */ +void *WiFiScanClass::_getScanInfoByIndex(int i) { + if (!WiFiScanClass::_scanResult || (size_t)i >= WiFiScanClass::_scanCount) { + return 0; + } + return reinterpret_cast(WiFiScanClass::_scanResult) + i; +} + +/** + * called to get the scan state in Async mode + * @return scan result or status + * -1 if scan not fin + * -2 if scan not triggered + */ +int16_t WiFiScanClass::scanComplete() { + if (WiFiGenericClass::getStatusBits() & WIFI_SCAN_DONE_BIT) { + return WiFiScanClass::_scanCount; + } + + if (WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) { + // Check if the delay expired, return WIFI_SCAN_FAILED in this case + if ((millis() - WiFiScanClass::_scanStarted) > WiFiScanClass::_scanTimeout) { + WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT); + return WIFI_SCAN_FAILED; + } + return WIFI_SCAN_RUNNING; + } + + return WIFI_SCAN_FAILED; +} + +/** + * delete last scan result from RAM + */ +void WiFiScanClass::scanDelete() { + WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT); + WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT); + if (WiFiScanClass::_scanResult) { + free(WiFiScanClass::_scanResult); + WiFiScanClass::_scanResult = NULL; + } + WiFiScanClass::_scanCount = 0; +} + +/** + * loads all infos from a scanned wifi in to the ptr parameters + * @param networkItem uint8_t + * @param ssid const char** + * @param encryptionType uint8_t * + * @param RSSI int32_t * + * @param BSSID uint8_t ** + * @param channel int32_t * + * @return (true if ok) + */ +bool WiFiScanClass::getNetworkInfo(uint8_t i, String &ssid, uint8_t &encType, int32_t &rssi, uint8_t *&bssid, int32_t &channel) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return false; + } + ssid = (const char *)it->ssid; + encType = it->authmode; + rssi = it->rssi; + bssid = it->bssid; + channel = it->primary; + return true; +} + +/** + * Return the SSID discovered during the network scan. + * @param i specify from which network item want to get the information + * @return ssid string of the specified item on the networks scanned list + */ +String WiFiScanClass::SSID(uint8_t i) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return String(); + } + return String(reinterpret_cast(it->ssid)); +} + +/** + * Return the encryption type of the networks discovered during the scanNetworks + * @param i specify from which network item want to get the information + * @return encryption type (enum wl_enc_type) of the specified item on the networks scanned list + */ +wifi_auth_mode_t WiFiScanClass::encryptionType(uint8_t i) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return WIFI_AUTH_OPEN; + } + return it->authmode; +} + +/** + * Return the RSSI of the networks discovered during the scanNetworks + * @param i specify from which network item want to get the information + * @return signed value of RSSI of the specified item on the networks scanned list + */ +int32_t WiFiScanClass::RSSI(uint8_t i) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return 0; + } + return it->rssi; +} + +/** + * return MAC / BSSID of scanned wifi + * @param i specify from which network item want to get the information + * @param buff optional buffer for the result uint8_t array with length 6 + * @return uint8_t * MAC / BSSID of scanned wifi + */ +uint8_t *WiFiScanClass::BSSID(uint8_t i, uint8_t *buff) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (buff != NULL) { + if (!it) { + memset(buff, 0, 6); + } else { + memcpy(buff, it->bssid, 6); + } + return buff; + } + if (!it) { + return 0; + } + return it->bssid; +} + +/** + * return MAC / BSSID of scanned wifi + * @param i specify from which network item want to get the information + * @return String MAC / BSSID of scanned wifi + */ +String WiFiScanClass::BSSIDstr(uint8_t i) { + char mac[18] = {0}; + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return String(); + } + sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", it->bssid[0], it->bssid[1], it->bssid[2], it->bssid[3], it->bssid[4], it->bssid[5]); + return String(mac); +} + +int32_t WiFiScanClass::channel(uint8_t i) { + wifi_ap_record_t *it = reinterpret_cast(_getScanInfoByIndex(i)); + if (!it) { + return 0; + } + return it->primary; +} + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiScan.h b/libraries/WiFi/src/WiFiScan.h new file mode 100644 index 0000000..7afd26b --- /dev/null +++ b/libraries/WiFi/src/WiFiScan.h @@ -0,0 +1,74 @@ +/* + ESP8266WiFiScan.h - esp8266 Wifi support. + Based on WiFi.h from Ardiono WiFi shield library. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "WiFiType.h" +#include "WiFiGeneric.h" + +class WiFiScanClass { + +public: + void setScanTimeout(uint32_t ms); + void setScanActiveMinTime(uint32_t ms); + + int16_t scanNetworks( + bool async = false, bool show_hidden = false, bool passive = false, uint32_t max_ms_per_chan = 300, uint8_t channel = 0, const char *ssid = nullptr, + const uint8_t *bssid = nullptr + ); + + int16_t scanComplete(); + void scanDelete(); + + // scan result + bool getNetworkInfo(uint8_t networkItem, String &ssid, uint8_t &encryptionType, int32_t &RSSI, uint8_t *&BSSID, int32_t &channel); + + String SSID(uint8_t networkItem); + wifi_auth_mode_t encryptionType(uint8_t networkItem); + int32_t RSSI(uint8_t networkItem); + uint8_t *BSSID(uint8_t networkItem, uint8_t *bssid = NULL); + String BSSIDstr(uint8_t networkItem); + int32_t channel(uint8_t networkItem); + static void *getScanInfoByIndex(int i) { + return _getScanInfoByIndex(i); + }; + + static void _scanDone(); + +protected: + static bool _scanAsync; + + static uint32_t _scanStarted; + static uint32_t _scanTimeout; + static uint16_t _scanCount; + static uint32_t _scanActiveMinTime; + + static void *_scanResult; + + static void *_getScanInfoByIndex(int i); +}; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiServer.h b/libraries/WiFi/src/WiFiServer.h new file mode 100644 index 0000000..850bd98 --- /dev/null +++ b/libraries/WiFi/src/WiFiServer.h @@ -0,0 +1,3 @@ +#pragma once +#include "NetworkServer.h" +typedef NetworkServer WiFiServer; diff --git a/libraries/WiFi/src/WiFiType.h b/libraries/WiFi/src/WiFiType.h new file mode 100644 index 0000000..29af9ce --- /dev/null +++ b/libraries/WiFi/src/WiFiType.h @@ -0,0 +1,55 @@ +/* + ESP8266WiFiType.h - esp8266 Wifi support. + Copyright (c) 2011-2014 Arduino. All right reserved. + Modified by Ivan Grokhotkov, December 2014 + Reworked by Markus Sattler, December 2015 + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED + +#include "esp_wifi_types.h" + +#define WIFI_SCAN_RUNNING (-1) +#define WIFI_SCAN_FAILED (-2) + +#define WiFiMode_t wifi_mode_t +#define WIFI_OFF WIFI_MODE_NULL +#define WIFI_STA WIFI_MODE_STA +#define WIFI_AP WIFI_MODE_AP +#define WIFI_AP_STA WIFI_MODE_APSTA + +#define WiFiEvent_t arduino_event_id_t +#define WiFiEventInfo_t arduino_event_info_t +#define WiFiEventId_t wifi_event_id_t + +typedef enum { + WL_NO_SHIELD = 255, // for compatibility with WiFi Shield library + WL_STOPPED = 254, + WL_IDLE_STATUS = 0, + WL_NO_SSID_AVAIL = 1, + WL_SCAN_COMPLETED = 2, + WL_CONNECTED = 3, + WL_CONNECT_FAILED = 4, + WL_CONNECTION_LOST = 5, + WL_DISCONNECTED = 6 +} wl_status_t; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFi/src/WiFiUdp.h b/libraries/WiFi/src/WiFiUdp.h new file mode 100644 index 0000000..420d29b --- /dev/null +++ b/libraries/WiFi/src/WiFiUdp.h @@ -0,0 +1,3 @@ +#pragma once +#include "NetworkUdp.h" +typedef NetworkUDP WiFiUDP; diff --git a/libraries/WiFiProv/examples/WiFiProv/README.md b/libraries/WiFiProv/examples/WiFiProv/README.md new file mode 100644 index 0000000..690c276 --- /dev/null +++ b/libraries/WiFiProv/examples/WiFiProv/README.md @@ -0,0 +1,125 @@ +# Provisioning for Arduino + +This sketch implements provisioning using various IDF components. + +## Description + +This example allows Arduino users to choose either BLE or SOFTAP as the mode of transport for provisioning-related communication between the device (to be provisioned) and the client (owner of the device). + +## APIs introduced for provisioning + + +### WiFi.onEvent() + + +This API can be used to register a function to be called from another +thread for Wi-Fi Events and Provisioning Events. + + +### WiFi.beginProvision() + + +``` +WiFi.beginProvision(void (*scheme_cb)(), wifi_prov_scheme_event_handler_t scheme_event_handler, wifi_prov_security_t security, char *pop, char *service_name, char *service_key, uint8_t *uuid); +``` + +#### Parameters passed + +- Function pointer: Choose the mode of transfer + - `provSchemeBLE` - Using BLE + - `provSchemeSoftAP` - Using SoftAP + +- `security`: Choose the security type + - `WIFI_PROV_SECURITY_1` - Enables secure communication with a secure handshake using key exchange and proof of possession (pop), and encryption/decryption of messages. + - `WIFI_PROV_SECURITY_0` - Does not provide application-level security, allowing plain text communication. + +- `scheme_event_handler`: Specify the handlers according to the chosen mode + - BLE: + - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM` - Used when the application doesn't need BT and BLE after provisioning is finished. + - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE` - Used when the application doesn't need BLE to be active after provisioning is finished. + - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT` - Used when the application doesn't need BT to be active after provisioning is finished. + + - SoftAP: + - `WIFI_PROV_EVENT_HANDLER_NONE` + +- `pop`: String used for authentication. + +- `service_name`: Specify the service name for the device. If not specified, the default chosen name is `PROV_XXX`, where XXX represents the last 3 bytes of the MAC address. + +- `service_key`: Specify the service key. If the chosen mode of provisioning is BLE, the `service_key` is always NULL. + +- `uuid`: Users can specify their own 128-bit UUID while provisioning using BLE. If not specified, the default value is: + +``` +{ 0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02 } +``` + +- `reset_provisioned`: Resets previously provisioned data before initializing. Using this prevents problem when the device automatically connects to previously connected Wi-Fi and therefore cannot be found. + +**NOTE:** If none of the parameters are specified in `beginProvision`, default provisioning takes place using SoftAP with the following settings: +- `scheme = WIFI_PROV_SCHEME_SOFTAP` +- `scheme_event_handler = WIFI_PROV_EVENT_HANDLER_NONE` +- `security = WIFI_PROV_SECURITY_1` +- `pop = "abcd1234"` +- `service_name = "PROV_XXX"` +- `service_key = NULL` +- `uuid = NULL` +- `reset_provisioned = false` + +## Flashing +This sketch takes up a lot of space for the app and may not be able to flash with default setting on some chips. +If you see Error like this: "Sketch too big" +In Arduino IDE go to: Tools > Partition scheme > chose anything that has more than 1.4 MB APP for example `No OTA (2MB APP/2MB SPIFFS)` + +## Log Output +- To enable debugging: Go to Tools -> Core Debug Level -> Info. + +## Provisioning Tools +[Provisioning Tools](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/provisioning/wifi_provisioning.html#provisioning-tools) + +## Example Output + +### Provisioning using SoftAP +``` +[I][WiFiProv.cpp:117] beginProvision(): Starting AP using SOFTAP + service_name: PROV_XXX + password: 123456789 + pop: abcd1234 + +Provisioning started +Give Credentials of your access point using "Android app" + +Received Wi-Fi credentials + SSID: GIONEE M2 + Password: 123456789 + +Connected IP address: 192.168.43.120 +Provisioning Successful +Provisioning Ends +``` + +### Provisioning using BLE +``` +[I][WiFiProv.cpp:115] beginProvision(): Starting AP using BLE + service_name: PROV_XXX + pop: abcd1234 + +Provisioning started +Give Credentials of your access point using "Android app" + +Received Wi-Fi credentials + SSID: GIONEE M2 + Password: 123456789 + +Connected IP address: 192.168.43.120 +Provisioning Successful +Provisioning Ends +``` + +### Credentials are available on the device +``` +[I][WiFiProv.cpp:146] beginProvision(): Already Provisioned, starting Wi-Fi STA +[I][WiFiProv.cpp:150] beginProvision(): SSID: Wce***** +[I][WiFiProv.cpp:152] beginProvision(): CONNECTING TO THE ACCESS POINT: +Connected IP address: 192.168.43.120 +``` diff --git a/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino b/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino new file mode 100644 index 0000000..2f7d8c5 --- /dev/null +++ b/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino @@ -0,0 +1,82 @@ +/* +Please read README.md file in this folder, or on the web: +https://github.com/espressif/arduino-esp32/tree/master/libraries/WiFiProv/examples/WiFiProv + +Note: This sketch takes up a lot of space for the app and may not be able to flash with default setting on some chips. + If you see Error like this: "Sketch too big" + In Arduino IDE go to: Tools > Partition scheme > chose anything that has more than 1.4MB APP + - for example "No OTA (2MB APP/2MB SPIFFS)" +*/ + +#include "sdkconfig.h" +#if CONFIG_ESP_WIFI_REMOTE_ENABLED +#error "WiFiProv is only supported in SoCs with native Wi-Fi support" +#endif + +#include "WiFiProv.h" +#include "WiFi.h" + +// #define USE_SOFT_AP // Uncomment if you want to enforce using the Soft AP method instead of BLE +const char *pop = "abcd1234"; // Proof of possession - otherwise called a PIN - string provided by the device, entered by the user in the phone app +const char *service_name = "PROV_123"; // Name of your device (the Espressif apps expects by default device name starting with "Prov_") +const char *service_key = NULL; // Password used for SofAP method (NULL = no password needed) +bool reset_provisioned = true; // When true the library will automatically delete previously provisioned data. + +// WARNING: SysProvEvent is called from a separate FreeRTOS task (thread)! +void SysProvEvent(arduino_event_t *sys_event) { + switch (sys_event->event_id) { + case ARDUINO_EVENT_WIFI_STA_GOT_IP: + Serial.print("\nConnected IP address : "); + Serial.println(IPAddress(sys_event->event_info.got_ip.ip_info.ip.addr)); + break; + case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: Serial.println("\nDisconnected. Connecting to the AP again... "); break; + case ARDUINO_EVENT_PROV_START: Serial.println("\nProvisioning started\nGive Credentials of your access point using smartphone app"); break; + case ARDUINO_EVENT_PROV_CRED_RECV: + { + Serial.println("\nReceived Wi-Fi credentials"); + Serial.print("\tSSID : "); + Serial.println((const char *)sys_event->event_info.prov_cred_recv.ssid); + Serial.print("\tPassword : "); + Serial.println((char const *)sys_event->event_info.prov_cred_recv.password); + break; + } + case ARDUINO_EVENT_PROV_CRED_FAIL: + { + Serial.println("\nProvisioning failed!\nPlease reset to factory and retry provisioning\n"); + if (sys_event->event_info.prov_fail_reason == NETWORK_PROV_WIFI_STA_AUTH_ERROR) { + Serial.println("\nWi-Fi AP password incorrect"); + } else { + Serial.println("\nWi-Fi AP not found....Add API \" nvs_flash_erase() \" before beginProvision()"); + } + break; + } + case ARDUINO_EVENT_PROV_CRED_SUCCESS: Serial.println("\nProvisioning Successful"); break; + case ARDUINO_EVENT_PROV_END: Serial.println("\nProvisioning Ends"); break; + default: break; + } +} + +void setup() { + Serial.begin(115200); + WiFi.begin(); // no SSID/PWD - get it from the Provisioning APP or from NVS (last successful connection) + WiFi.onEvent(SysProvEvent); + +// BLE Provisioning using the ESP SoftAP Prov works fine for any BLE SoC, including ESP32, ESP32S3 and ESP32C3. +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") && !defined(USE_SOFT_AP) + Serial.println("Begin Provisioning using BLE"); + // Sample uuid that user can pass during provisioning using BLE + uint8_t uuid[16] = {0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02}; + WiFiProv.beginProvision( + NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BLE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key, uuid, reset_provisioned + ); + log_d("ble qr"); + WiFiProv.printQR(service_name, pop, "ble"); +#else + Serial.println("Begin Provisioning using Soft AP"); + WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key); + log_d("wifi qr"); + WiFiProv.printQR(service_name, pop, "softap"); +#endif +} + +void loop() {} diff --git a/libraries/WiFiProv/examples/WiFiProv/ci.yml b/libraries/WiFiProv/examples/WiFiProv/ci.yml new file mode 100644 index 0000000..e412162 --- /dev/null +++ b/libraries/WiFiProv/examples/WiFiProv/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=huge_app + +requires: + - CONFIG_SOC_WIFI_SUPPORTED=y diff --git a/libraries/WiFiProv/library.properties b/libraries/WiFiProv/library.properties new file mode 100644 index 0000000..4baaf42 --- /dev/null +++ b/libraries/WiFiProv/library.properties @@ -0,0 +1,8 @@ +name=WiFiProv +version=3.3.7 +author=Switi Mhaiske +maintainer=Hristo Gochkov +sentence=Enables provisioning. +paragraph=With this library you can perform provisioning on esp32 via SoftAP or BLE. +url= +architectures=esp32 diff --git a/libraries/WiFiProv/src/WiFiProv.cpp b/libraries/WiFiProv/src/WiFiProv.cpp new file mode 100644 index 0000000..f372caf --- /dev/null +++ b/libraries/WiFiProv/src/WiFiProv.cpp @@ -0,0 +1,285 @@ +/* + WiFiProv.cpp - WiFiProv class for provisioning + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED && CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI + +#include +#include +#include +#include +#include +#include +#include +#include +#if __has_include("qrcode.h") +#include "qrcode.h" +#endif + +#include +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") +#include "network_provisioning/scheme_ble.h" +#endif +#include +#include +#undef IPADDR_NONE +#include "WiFiProv.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "SimpleBLE.h" +#endif + +bool wifiLowLevelInit(bool persistent); + +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") +static const uint8_t custom_service_uuid[16] = { + 0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02, +}; +#endif + +#define SERV_NAME_PREFIX_PROV "PROV_" + +static void get_device_service_name(prov_scheme_t prov_scheme, char *service_name, size_t max) { + uint8_t eth_mac[6] = {0, 0, 0, 0, 0, 0}; + if (esp_wifi_get_mac((wifi_interface_t)WIFI_IF_STA, eth_mac) != ESP_OK) { + log_e("esp_wifi_get_mac failed!"); + return; + } +#if CONFIG_IDF_TARGET_ESP32 && (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + if (prov_scheme == NETWORK_PROV_SCHEME_BLE) { + snprintf(service_name, max, "%s%02X%02X%02X", SERV_NAME_PREFIX_PROV, eth_mac[3], eth_mac[4], eth_mac[5]); + } else { +#endif + snprintf(service_name, max, "%s%02X%02X%02X", SERV_NAME_PREFIX_PROV, eth_mac[3], eth_mac[4], eth_mac[5]); +#if CONFIG_IDF_TARGET_ESP32 && (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + } +#endif +} + +void WiFiProvClass ::initProvision(prov_scheme_t prov_scheme, scheme_handler_t scheme_handler, bool reset_provisioned) { + if (this->provInitDone) { + log_i("provInit was already done!"); + return; + } + network_prov_mgr_config_t config; +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + if (prov_scheme == NETWORK_PROV_SCHEME_BLE) { + config.scheme = network_prov_scheme_ble; + } else { +#endif + config.scheme = network_prov_scheme_softap; +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + } + + if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_NONE) { +#endif + network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_EVENT_HANDLER_NONE; + memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t)); +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM) { + network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM; + memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t)); + } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BT) { + network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT; + memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t)); + } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BLE) { + network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE; + memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t)); + } else { + log_e("Unknown scheme handler!"); + return; + } +#endif + config.app_event_handler.event_cb = NULL; + config.app_event_handler.user_data = NULL; + WiFi.STA.begin(false); + if (network_prov_mgr_init(config) != ESP_OK) { + log_e("network_prov_mgr_init failed!"); + return; + } + if (reset_provisioned) { + log_i("Resetting provisioned data."); + network_prov_mgr_reset_wifi_provisioning(); + } else if (network_prov_mgr_is_wifi_provisioned(&(this->provisioned)) != ESP_OK) { + log_e("network_prov_mgr_is_wifi_provisioned failed!"); + network_prov_mgr_deinit(); + return; + } + this->provInitDone = true; +} + +void WiFiProvClass ::beginProvision( + prov_scheme_t prov_scheme, scheme_handler_t scheme_handler, network_prov_security_t security, const char *pop, const char *service_name, + const char *service_key, uint8_t *uuid, bool reset_provisioned +) { + if (!this->provInitDone) { + WiFiProvClass ::initProvision(prov_scheme, scheme_handler, reset_provisioned); + } + static char service_name_temp[32]; + if (provisioned == false) { +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + if (prov_scheme == NETWORK_PROV_SCHEME_BLE) { + service_key = NULL; + if (uuid == NULL) { + uuid = (uint8_t *)custom_service_uuid; + } + network_prov_scheme_ble_set_service_uuid(uuid); + } +#endif + + if (service_name == NULL) { + get_device_service_name(prov_scheme, service_name_temp, 32); + service_name = (const char *)service_name_temp; + } + +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + if (prov_scheme == NETWORK_PROV_SCHEME_BLE) { + log_i("Starting AP using BLE. service_name : %s, pop : %s", service_name, pop); + } else { +#endif + if (service_key == NULL) { + log_i("Starting provisioning AP using SOFTAP. service_name : %s, pop : %s", service_name, pop); + } else { + log_i("Starting provisioning AP using SOFTAP. service_name : %s, password : %s, pop : %s", service_name, service_key, pop); + } +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + } +#endif + if (network_prov_mgr_start_provisioning(security, pop, service_name, service_key) != ESP_OK) { + log_e("network_prov_mgr_start_provisioning failed!"); + return; + } + } else { + log_i("Already Provisioned"); +#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO + static wifi_config_t conf; + esp_wifi_get_config((wifi_interface_t)WIFI_IF_STA, &conf); + log_i("Attempting connect to AP: %s\n", conf.sta.ssid); +#endif + esp_wifi_start(); + network_prov_mgr_deinit(); + WiFi.begin(); + } +} + +void WiFiProvClass::endProvision() { + network_prov_mgr_stop_provisioning(); +} + +bool WiFiProvClass::disableAutoStop(uint32_t cleanup_delay) { + esp_err_t err = network_prov_mgr_disable_auto_stop(cleanup_delay); + if (err != ESP_OK) { + log_e("disable_auto_stop failed!"); + } + return err == ESP_OK; +} + +// Copied from IDF example + +#if __has_include("qrcode.h") +static const char *lt[] = { + /* 0 */ " ", + /* 1 */ "\u2580 ", + /* 2 */ " \u2580", + /* 3 */ "\u2580\u2580", + /* 4 */ "\u2584 ", + /* 5 */ "\u2588 ", + /* 6 */ "\u2584\u2580", + /* 7 */ "\u2588\u2580", + /* 8 */ " \u2584", + /* 9 */ "\u2580\u2584", + /* 10 */ " \u2588", + /* 11 */ "\u2580\u2588", + /* 12 */ "\u2584\u2584", + /* 13 */ "\u2588\u2584", + /* 14 */ "\u2584\u2588", + /* 15 */ "\u2588\u2588", +}; + +static Print *qr_out = NULL; + +static void _qrcode_print_console(esp_qrcode_handle_t qrcode) { + int size = esp_qrcode_get_size(qrcode); + int border = 2; + unsigned char num = 0; + + if (qr_out == NULL) { + return; + } + + for (int y = -border; y < size + border; y += 2) { + for (int x = -border; x < size + border; x += 2) { + num = 0; + if (esp_qrcode_get_module(qrcode, x, y)) { + num |= 1 << 0; + } + if ((x < size + border) && esp_qrcode_get_module(qrcode, x + 1, y)) { + num |= 1 << 1; + } + if ((y < size + border) && esp_qrcode_get_module(qrcode, x, y + 1)) { + num |= 1 << 2; + } + if ((x < size + border) && (y < size + border) && esp_qrcode_get_module(qrcode, x + 1, y + 1)) { + num |= 1 << 3; + } + qr_out->print(lt[num]); + } + qr_out->print("\n"); + } + qr_out->print("\n"); +} +#endif + +void WiFiProvClass::printQR(const char *name, const char *pop, const char *transport, Print &out) { + if (!name || !transport) { + log_w("Cannot generate QR code payload. Data missing."); + return; + } + char payload[150] = {0}; + if (pop) { + snprintf( + payload, sizeof(payload), + "{\"ver\":\"%s\",\"name\":\"%s\"" + ",\"pop\":\"%s\",\"transport\":\"%s\"}", + "v1", name, pop, transport + ); + } else { + snprintf( + payload, sizeof(payload), + "{\"ver\":\"%s\",\"name\":\"%s\"" + ",\"transport\":\"%s\"}", + "v1", name, transport + ); + } +#if __has_include("qrcode.h") + esp_qrcode_config_t cfg = ESP_QRCODE_CONFIG_DEFAULT(); + cfg.display_func = _qrcode_print_console; + out.printf("Scan this QR code from the provisioning application for Provisioning.\n"); + qr_out = &out; + esp_qrcode_generate(&cfg, payload); + qr_out = NULL; + out.printf("If QR code is not visible, copy paste the below URL in a browser.\nhttps://rainmaker.espressif.com/qrcode.html?data=%s\n", payload); +#else + out.println("If you are using Arduino as IDF component, install ESP Rainmaker:\nhttps://github.com/espressif/esp-rainmaker"); +#endif +} + +WiFiProvClass WiFiProv; + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/WiFiProv/src/WiFiProv.h b/libraries/WiFiProv/src/WiFiProv.h new file mode 100644 index 0000000..0ebc595 --- /dev/null +++ b/libraries/WiFiProv/src/WiFiProv.h @@ -0,0 +1,72 @@ +/* + WiFiProv.h - Base class for provisioning support + All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if SOC_WIFI_SUPPORTED && CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI + +#include "WiFi.h" +#include "HardwareSerial.h" +#include "network_provisioning/manager.h" +//Select the scheme using which you want to provision +typedef enum { + NETWORK_PROV_SCHEME_SOFTAP, +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + NETWORK_PROV_SCHEME_BLE, +#endif + NETWORK_PROV_SCHEME_MAX +} prov_scheme_t; + +typedef enum { + NETWORK_PROV_SCHEME_HANDLER_NONE, +#if (defined(CONFIG_BLUEDROID_ENABLED) || defined(CONFIG_NIMBLE_ENABLED)) && __has_include("esp_bt.h") + NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM, + NETWORK_PROV_SCHEME_HANDLER_FREE_BLE, + NETWORK_PROV_SCHEME_HANDLER_FREE_BT, +#endif + NETWORK_PROV_SCHEME_HANDLER_MAX +} scheme_handler_t; + +//Provisioning class +class WiFiProvClass { +private: + bool provInitDone = false; + bool provisioned = false; + +public: + void initProvision( + prov_scheme_t prov_scheme = NETWORK_PROV_SCHEME_SOFTAP, scheme_handler_t scheme_handler = NETWORK_PROV_SCHEME_HANDLER_NONE, bool reset_provisioned = false + ); + void beginProvision( + prov_scheme_t prov_scheme = NETWORK_PROV_SCHEME_SOFTAP, scheme_handler_t scheme_handler = NETWORK_PROV_SCHEME_HANDLER_NONE, + network_prov_security_t security = NETWORK_PROV_SECURITY_1, const char *pop = "abcd1234", const char *service_name = NULL, const char *service_key = NULL, + uint8_t *uuid = NULL, bool reset_provisioned = false + ); + void endProvision(); + bool disableAutoStop(uint32_t cleanup_delay); + void printQR(const char *name, const char *pop, const char *transport, Print &out = Serial); +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_WIFIPROV) +extern WiFiProvClass WiFiProv; +#endif + +#endif /* SOC_WIFI_SUPPORTED */ diff --git a/libraries/Wire/examples/WireMaster/WireMaster.ino b/libraries/Wire/examples/WireMaster/WireMaster.ino new file mode 100644 index 0000000..ea603e3 --- /dev/null +++ b/libraries/Wire/examples/WireMaster/WireMaster.ino @@ -0,0 +1,30 @@ +#include "Wire.h" + +#define I2C_DEV_ADDR 0x55 + +uint32_t i = 0; + +void setup() { + Serial.begin(115200); + Serial.setDebugOutput(true); + Wire.begin(); +} + +void loop() { + delay(5000); + + //Write message to the slave + Wire.beginTransmission(I2C_DEV_ADDR); + Wire.printf("Hello World! %lu", i++); + uint8_t error = Wire.endTransmission(true); + Serial.printf("endTransmission: %u\n", error); + + //Read 16 bytes from the slave + uint8_t bytesReceived = Wire.requestFrom(I2C_DEV_ADDR, 16); + Serial.printf("requestFrom: %u\n", bytesReceived); + if ((bool)bytesReceived) { //If received more than zero bytes + uint8_t temp[bytesReceived]; + Wire.readBytes(temp, bytesReceived); + log_print_buf(temp, bytesReceived); + } +} diff --git a/libraries/Wire/examples/WireMaster/ci.yml b/libraries/Wire/examples/WireMaster/ci.yml new file mode 100644 index 0000000..f992877 --- /dev/null +++ b/libraries/Wire/examples/WireMaster/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_I2C_SUPPORTED=y diff --git a/libraries/Wire/examples/WireScan/WireScan.ino b/libraries/Wire/examples/WireScan/WireScan.ino new file mode 100644 index 0000000..59f17af --- /dev/null +++ b/libraries/Wire/examples/WireScan/WireScan.ino @@ -0,0 +1,28 @@ +#include "Wire.h" + +void setup() { + Serial.begin(115200); + Wire.begin(); +} + +void loop() { + byte error, address; + int nDevices = 0; + + delay(5000); + + Serial.println("Scanning for I2C devices ..."); + for (address = 0x01; address < 0x7f; address++) { + Wire.beginTransmission(address); + error = Wire.endTransmission(); + if (error == 0) { + Serial.printf("I2C device found at address 0x%02X\n", address); + nDevices++; + } else if (error != 2) { + Serial.printf("Error %d at address 0x%02X\n", error, address); + } + } + if (nDevices == 0) { + Serial.println("No I2C devices found"); + } +} diff --git a/libraries/Wire/examples/WireScan/ci.yml b/libraries/Wire/examples/WireScan/ci.yml new file mode 100644 index 0000000..f992877 --- /dev/null +++ b/libraries/Wire/examples/WireScan/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_I2C_SUPPORTED=y diff --git a/libraries/Wire/examples/WireSlave/WireSlave.ino b/libraries/Wire/examples/WireSlave/WireSlave.ino new file mode 100644 index 0000000..9e86549 --- /dev/null +++ b/libraries/Wire/examples/WireSlave/WireSlave.ino @@ -0,0 +1,35 @@ +#include "Wire.h" + +#define I2C_DEV_ADDR 0x55 + +uint32_t i = 0; + +void onRequest() { + Wire.print(i++); + Wire.print(" Packets."); + Serial.println("onRequest"); +} + +void onReceive(int len) { + Serial.printf("onReceive[%d]: ", len); + while (Wire.available()) { + Serial.write(Wire.read()); + } + Serial.println(); +} + +void setup() { + Serial.begin(115200); + Serial.setDebugOutput(true); + Wire.onReceive(onReceive); + Wire.onRequest(onRequest); + Wire.begin((uint8_t)I2C_DEV_ADDR); + +#if CONFIG_IDF_TARGET_ESP32 + char message[64]; + snprintf(message, 64, "%lu Packets.", i++); + Wire.slaveWrite((uint8_t *)message, strlen(message)); +#endif +} + +void loop() {} diff --git a/libraries/Wire/examples/WireSlave/ci.yml b/libraries/Wire/examples/WireSlave/ci.yml new file mode 100644 index 0000000..40e259f --- /dev/null +++ b/libraries/Wire/examples/WireSlave/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_I2C_SUPPORT_SLAVE=y diff --git a/libraries/Wire/examples/WireSlaveFunctionalCallback/WireSlaveFunctionalCallback.ino b/libraries/Wire/examples/WireSlaveFunctionalCallback/WireSlaveFunctionalCallback.ino new file mode 100644 index 0000000..a18fd2f --- /dev/null +++ b/libraries/Wire/examples/WireSlaveFunctionalCallback/WireSlaveFunctionalCallback.ino @@ -0,0 +1,37 @@ +// This example demonstrates the use of functional callbacks with the Wire library +// for I2C slave communication. It shows how to handle requests and data reception + +#include "Wire.h" + +#define I2C_DEV_ADDR 0x55 + +uint32_t i = 0; + +void setup() { + Serial.begin(115200); + Serial.setDebugOutput(true); + + Wire.onRequest([]() { + Wire.print(i++); + Wire.print(" Packets."); + Serial.println("onRequest"); + }); + + Wire.onReceive([](int len) { + Serial.printf("onReceive[%d]: ", len); + while (Wire.available()) { + Serial.write(Wire.read()); + } + Serial.println(); + }); + + Wire.begin((uint8_t)I2C_DEV_ADDR); + +#if CONFIG_IDF_TARGET_ESP32 + char message[64]; + snprintf(message, 64, "%lu Packets.", i++); + Wire.slaveWrite((uint8_t *)message, strlen(message)); +#endif +} + +void loop() {} diff --git a/libraries/Wire/examples/WireSlaveFunctionalCallback/ci.yml b/libraries/Wire/examples/WireSlaveFunctionalCallback/ci.yml new file mode 100644 index 0000000..40e259f --- /dev/null +++ b/libraries/Wire/examples/WireSlaveFunctionalCallback/ci.yml @@ -0,0 +1,2 @@ +requires: + - CONFIG_SOC_I2C_SUPPORT_SLAVE=y diff --git a/libraries/Wire/keywords.txt b/libraries/Wire/keywords.txt new file mode 100644 index 0000000..80d5f0d --- /dev/null +++ b/libraries/Wire/keywords.txt @@ -0,0 +1,34 @@ +####################################### +# Syntax Coloring Map For Wire +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +setClock KEYWORD2 +getClock KEYWORD2 +setTimeOut KEYWORD2 +getTimeOut KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +onReceive KEYWORD2 +onRequest KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +Wire KEYWORD2 +TwoWire KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/libraries/Wire/library.properties b/libraries/Wire/library.properties new file mode 100644 index 0000000..23955df --- /dev/null +++ b/libraries/Wire/library.properties @@ -0,0 +1,9 @@ +name=Wire +version=3.3.7 +author=Hristo Gochkov +maintainer=Hristo Gochkov +sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. For esp8266 boards. +paragraph= +category=Signal Input/Output +url=http://arduino.cc/en/Reference/Wire +architectures=esp32 diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp new file mode 100644 index 0000000..cda098d --- /dev/null +++ b/libraries/Wire/src/Wire.cpp @@ -0,0 +1,666 @@ +/* + TwoWire.cpp - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified Nov 2017 by Chuck Todd (ctodd@cableone.net) - ESP32 ISR Support + Modified Nov 2021 by Hristo Gochkov to support ESP-IDF API + */ +#include "soc/soc_caps.h" +#if SOC_I2C_SUPPORTED + +extern "C" { +#include +#include +#include +} + +#include "esp32-hal-i2c.h" +#if SOC_I2C_SUPPORT_SLAVE +#include "esp32-hal-i2c-slave.h" +#endif /* SOC_I2C_SUPPORT_SLAVE */ +#include "Wire.h" +#include "Arduino.h" + +TwoWire::TwoWire(uint8_t bus_num) + : num(bus_num), sda(-1), scl(-1), bufferSize(I2C_BUFFER_LENGTH) // default Wire Buffer Size + , + rxBuffer(NULL), rxIndex(0), rxLength(0), txBuffer(NULL), txLength(0), txAddress(0), _timeOutMillis(50), nonStop(false) +#if !CONFIG_DISABLE_HAL_LOCKS + , + currentTaskHandle(NULL), lock(NULL) +#endif +#if SOC_I2C_SUPPORT_SLAVE + , + is_slave(false), user_onRequest(nullptr), user_onReceive(nullptr) +#endif /* SOC_I2C_SUPPORT_SLAVE */ +{ +} + +TwoWire::~TwoWire() { + end(); +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock != NULL) { + vSemaphoreDelete(lock); + } +#endif +} + +uint8_t TwoWire::getBusNum() { + return num; +} + +bool TwoWire::initPins(int sdaPin, int sclPin) { + if (sdaPin < 0) { // default param passed + if (num == 0) { + if (sda == -1) { + sdaPin = SDA; //use Default Pin + } else { + sdaPin = sda; // reuse prior pin + } + } else { + if (sda == -1) { +#ifdef WIRE1_PIN_DEFINED + sdaPin = SDA1; +#else + log_e("no Default SDA Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral +#endif + } else { + sdaPin = sda; // reuse prior pin + } + } + } + + if (sclPin < 0) { // default param passed + if (num == 0) { + if (scl == -1) { + sclPin = SCL; // use Default pin + } else { + sclPin = scl; // reuse prior pin + } + } else { + if (scl == -1) { +#ifdef WIRE1_PIN_DEFINED + sclPin = SCL1; +#else + log_e("no Default SCL Pin for Second Peripheral"); + return false; //no Default pin for Second Peripheral +#endif + } else { + sclPin = scl; // reuse prior pin + } + } + } + + sda = sdaPin; + scl = sclPin; + return true; +} + +bool TwoWire::setPins(int sdaPin, int sclPin) { +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock == NULL) { + lock = xSemaphoreCreateMutex(); + if (lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return false; + } + } + //acquire lock + if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return false; + } +#endif + if (!i2cIsInit(num)) { + initPins(sdaPin, sclPin); + } else { + log_e("bus already initialized. change pins only when not."); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); +#endif + return !i2cIsInit(num); +} + +bool TwoWire::allocateWireBuffer() { + // or both buffer can be allocated or none will be + if (rxBuffer == NULL) { + rxBuffer = (uint8_t *)malloc(bufferSize); + if (rxBuffer == NULL) { + log_e("Can't allocate memory for I2C_%d rxBuffer", num); + return false; + } + } + if (txBuffer == NULL) { + txBuffer = (uint8_t *)malloc(bufferSize); + if (txBuffer == NULL) { + log_e("Can't allocate memory for I2C_%d txBuffer", num); + freeWireBuffer(); // free rxBuffer for safety! + return false; + } + } + // in case both were allocated before, they must have the same size. All good. + return true; +} + +void TwoWire::freeWireBuffer() { + if (rxBuffer != NULL) { + free(rxBuffer); + rxBuffer = NULL; + } + if (txBuffer != NULL) { + free(txBuffer); + txBuffer = NULL; + } +} + +size_t TwoWire::setBufferSize(size_t bSize) { + // Maximum size .... HEAP limited ;-) + if (bSize < 32) { // 32 bytes is the I2C FIFO Len for ESP32/S2/S3/C3 + log_e("Minimum Wire Buffer size is 32 bytes"); + return 0; + } + +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock == NULL) { + lock = xSemaphoreCreateMutex(); + if (lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return 0; + } + } + //acquire lock + if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return 0; + } +#endif + // allocateWireBuffer allocates memory for both pointers or just free them + if (rxBuffer != NULL || txBuffer != NULL) { + // if begin() has been already executed, memory size changes... data may be lost. We don't care! :^) + if (bSize != bufferSize) { + // we want a new buffer size ... just reset buffer pointers and allocate new ones + freeWireBuffer(); + bufferSize = bSize; + if (!allocateWireBuffer()) { + // failed! Error message already issued + bSize = 0; // returns error + log_e("Buffer allocation failed"); + } + } // else nothing changes, all set! + } else { + // no memory allocated yet, just change the size value - allocation in begin() + bufferSize = bSize; + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); + +#endif + return bSize; +} + +#if SOC_I2C_SUPPORT_SLAVE +// Slave Begin +bool TwoWire::begin(uint8_t addr, int sdaPin, int sclPin, uint32_t frequency) { + bool started = false; +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock == NULL) { + lock = xSemaphoreCreateMutex(); + if (lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return false; + } + } + //acquire lock + if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return false; + } +#endif + if (is_slave) { + log_w("Bus already started in Slave Mode."); + started = true; + goto end; + } + if (i2cIsInit(num)) { + log_e("Bus already started in Master Mode."); + goto end; + } + if (!allocateWireBuffer()) { + // failed! Error Message already issued + goto end; + } + if (!initPins(sdaPin, sclPin)) { + goto end; + } + i2cSlaveAttachCallbacks(num, onRequestService, onReceiveService, this); + if (i2cSlaveInit(num, sda, scl, addr, frequency, bufferSize, bufferSize) != ESP_OK) { + log_e("Slave Init ERROR"); + goto end; + } + is_slave = true; + started = true; +end: + if (!started) { + freeWireBuffer(); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); +#endif + return started; +} +#endif /* SOC_I2C_SUPPORT_SLAVE */ + +// Master Begin +bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) { + bool started = false; + esp_err_t err = ESP_OK; +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock == NULL) { + lock = xSemaphoreCreateMutex(); + if (lock == NULL) { + log_e("xSemaphoreCreateMutex failed"); + return false; + } + } + //acquire lock + if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return false; + } +#endif +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus already started in Slave Mode."); + goto end; + } +#endif /* SOC_I2C_SUPPORT_SLAVE */ + if (i2cIsInit(num)) { + log_w("Bus already started in Master Mode."); + started = true; + goto end; + } + if (!allocateWireBuffer()) { + // failed! Error Message already issued + goto end; + } + if (!initPins(sdaPin, sclPin)) { + goto end; + } + err = i2cInit(num, sda, scl, frequency); + started = (err == ESP_OK); + +end: + if (!started) { + freeWireBuffer(); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); +#endif + return started; +} + +bool TwoWire::end() { + esp_err_t err = ESP_OK; +#if !CONFIG_DISABLE_HAL_LOCKS + if (lock != NULL) { + //acquire lock + if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return false; + } +#endif +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + err = i2cSlaveDeinit(num); + if (err == ESP_OK) { + is_slave = false; + } + } else +#endif /* SOC_I2C_SUPPORT_SLAVE */ + if (i2cIsInit(num)) { + err = i2cDeinit(num); + } + freeWireBuffer(); +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); + } +#endif + return (err == ESP_OK); +} + +uint32_t TwoWire::getClock() { + uint32_t frequency = 0; +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + } else { +#endif +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus is in Slave Mode"); + } else +#endif /* SOC_I2C_SUPPORT_SLAVE */ + { + i2cGetClock(num, &frequency); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); + } +#endif + return frequency; +} + +bool TwoWire::setClock(uint32_t frequency) { + esp_err_t err = ESP_OK; +#if !CONFIG_DISABLE_HAL_LOCKS + //acquire lock + if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return false; + } +#endif +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus is in Slave Mode"); + err = ESP_FAIL; + } else +#endif /* SOC_I2C_SUPPORT_SLAVE */ + { + err = i2cSetClock(num, frequency); + } +#if !CONFIG_DISABLE_HAL_LOCKS + //release lock + xSemaphoreGive(lock); +#endif + return (err == ESP_OK); +} + +void TwoWire::setTimeOut(uint16_t timeOutMillis) { + _timeOutMillis = timeOutMillis; +} + +uint16_t TwoWire::getTimeOut() { + return _timeOutMillis; +} + +void TwoWire::beginTransmission(uint8_t address) { +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus is in Slave Mode"); + return; + } +#endif /* SOC_I2C_SUPPORT_SLAVE */ +#if !CONFIG_DISABLE_HAL_LOCKS + TaskHandle_t task = xTaskGetCurrentTaskHandle(); + if (currentTaskHandle != task) { + //acquire lock + if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return; + } + currentTaskHandle = task; + } +#endif + nonStop = false; + txAddress = address; + txLength = 0; +} + +/* +https://www.arduino.cc/reference/en/language/functions/communication/wire/endtransmission/ +endTransmission() returns: +0: success. +1: data too long to fit in transmit buffer. +2: received NACK on transmit of address. +3: received NACK on transmit of data. +4: other error. +5: timeout +*/ +uint8_t TwoWire::endTransmission(bool sendStop) { +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus is in Slave Mode"); + return 4; + } +#endif /* SOC_I2C_SUPPORT_SLAVE */ + if (txBuffer == NULL) { + log_e("NULL TX buffer pointer"); + return 4; + } + esp_err_t err = ESP_OK; + if (sendStop) { + err = i2cWrite(num, txAddress, txBuffer, txLength, _timeOutMillis); +#if !CONFIG_DISABLE_HAL_LOCKS + currentTaskHandle = NULL; + //release lock + xSemaphoreGive(lock); +#endif + } else { + //mark as non-stop + nonStop = true; + } + switch (err) { + case ESP_OK: return 0; + case ESP_FAIL: return 2; + case ESP_ERR_NOT_FOUND: return 2; + case ESP_ERR_TIMEOUT: return 5; + default: break; + } + return 4; +} + +uint8_t TwoWire::endTransmission() { + return endTransmission(true); +} + +size_t TwoWire::requestFrom(uint8_t address, size_t size, bool sendStop) { +#if SOC_I2C_SUPPORT_SLAVE + if (is_slave) { + log_e("Bus is in Slave Mode"); + return 0; + } +#endif /* SOC_I2C_SUPPORT_SLAVE */ + if (rxBuffer == NULL || txBuffer == NULL) { + log_e("NULL buffer pointer"); + return 0; + } + esp_err_t err = ESP_OK; +#if !CONFIG_DISABLE_HAL_LOCKS + TaskHandle_t task = xTaskGetCurrentTaskHandle(); + if (currentTaskHandle != task) { + //acquire lock + if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) { + log_e("could not acquire lock"); + return 0; + } + currentTaskHandle = task; + } +#endif + if (nonStop) { + if (address != txAddress) { + log_e("Unfinished Repeated Start transaction! Expected address do not match! %u != %u", address, txAddress); +#if !CONFIG_DISABLE_HAL_LOCKS + currentTaskHandle = NULL; + //release lock + xSemaphoreGive(lock); +#endif + return 0; + } + nonStop = false; + rxIndex = 0; + rxLength = 0; + err = i2cWriteReadNonStop(num, address, txBuffer, txLength, rxBuffer, size, _timeOutMillis, &rxLength); + if (err) { + log_e("i2cWriteReadNonStop returned Error %d", err); + } + } else { + rxIndex = 0; + rxLength = 0; + err = i2cRead(num, address, rxBuffer, size, _timeOutMillis, &rxLength); + if (err) { + log_e("i2cRead returned Error %d", err); + } + } +#if !CONFIG_DISABLE_HAL_LOCKS + currentTaskHandle = NULL; + //release lock + xSemaphoreGive(lock); +#endif + return rxLength; +} + +size_t TwoWire::requestFrom(uint8_t address, size_t size) { + return requestFrom(address, size, true); +} + +size_t TwoWire::write(uint8_t data) { + if (txBuffer == NULL) { + log_e("NULL TX buffer pointer"); + return 0; + } + if (txLength >= bufferSize) { + return 0; + } + txBuffer[txLength++] = data; + return 1; +} + +size_t TwoWire::write(const uint8_t *data, size_t quantity) { + for (size_t i = 0; i < quantity; ++i) { + if (!write(data[i])) { + return i; + } + } + return quantity; +} + +int TwoWire::available() { + int result = rxLength - rxIndex; + return result; +} + +int TwoWire::read() { + int value = -1; + if (rxBuffer == NULL) { + log_e("NULL RX buffer pointer"); + return value; + } + if (rxIndex < rxLength) { + value = rxBuffer[rxIndex++]; + } + return value; +} + +int TwoWire::peek() { + int value = -1; + if (rxBuffer == NULL) { + log_e("NULL RX buffer pointer"); + return value; + } + if (rxIndex < rxLength) { + value = rxBuffer[rxIndex]; + } + return value; +} + +void TwoWire::flush() { + rxIndex = 0; + rxLength = 0; + txLength = 0; + //i2cFlush(num); // cleanup +} + +void TwoWire::onReceive(const std::function &function) { +#if SOC_I2C_SUPPORT_SLAVE + user_onReceive = function; +#endif +} + +// sets function called on slave read +void TwoWire::onRequest(const std::function &function) { +#if SOC_I2C_SUPPORT_SLAVE + user_onRequest = function; +#endif +} + +#if SOC_I2C_SUPPORT_SLAVE + +size_t TwoWire::slaveWrite(const uint8_t *buffer, size_t len) { + return i2cSlaveWrite(num, buffer, len, _timeOutMillis); +} + +void TwoWire::onReceiveService(uint8_t num, uint8_t *inBytes, size_t numBytes, bool stop, void *arg) { + TwoWire *wire = (TwoWire *)arg; + if (!wire->user_onReceive) { + return; + } + if (wire->rxBuffer == NULL) { + log_e("NULL RX buffer pointer"); + return; + } + for (uint8_t i = 0; i < numBytes; ++i) { + wire->rxBuffer[i] = inBytes[i]; + } + wire->rxIndex = 0; + wire->rxLength = numBytes; + wire->user_onReceive(numBytes); +} + +void TwoWire::onRequestService(uint8_t num, void *arg) { + TwoWire *wire = (TwoWire *)arg; + if (!wire->user_onRequest) { + return; + } + if (wire->txBuffer == NULL) { + log_e("NULL TX buffer pointer"); + return; + } + wire->txLength = 0; + wire->user_onRequest(); + if (wire->txLength) { + wire->slaveWrite((uint8_t *)wire->txBuffer, wire->txLength); + } +} + +#endif /* SOC_I2C_SUPPORT_SLAVE */ + +TwoWire Wire = TwoWire(0); +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) +#if SOC_I2C_NUM > 1 +TwoWire Wire1 = TwoWire(1); +#elif SOC_I2C_NUM > 2 +TwoWire Wire2 = TwoWire(2); +#endif /* SOC_I2C_NUM */ +#else +#if SOC_HP_I2C_NUM > 1 +TwoWire Wire1 = TwoWire(1); +#endif /* SOC_HP_I2C_NUM */ +#endif + +#endif /* SOC_I2C_SUPPORTED */ diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h new file mode 100644 index 0000000..91a9ddc --- /dev/null +++ b/libraries/Wire/src/Wire.h @@ -0,0 +1,161 @@ +/* + TwoWire.h - TWI/I2C library for Arduino & Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts + Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support + Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support + Modified November 2017 by Chuck Todd to use ISR and increase stability. + Modified Nov 2021 by Hristo Gochkov to support ESP-IDF API +*/ + +#ifndef TwoWire_h +#define TwoWire_h + +#include "soc/soc_caps.h" +#if SOC_I2C_SUPPORTED +#include "esp_idf_version.h" + +#include +#include +#if !CONFIG_DISABLE_HAL_LOCKS +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#endif +#include "HardwareI2C.h" +#include "Stream.h" + +// WIRE_HAS_BUFFER_SIZE means Wire has setBufferSize() +#define WIRE_HAS_BUFFER_SIZE 1 +// WIRE_HAS_END means Wire has end() +#define WIRE_HAS_END 1 + +#ifndef I2C_BUFFER_LENGTH +#define I2C_BUFFER_LENGTH 128 // Default size, if none is set using Wire::setBuffersize(size_t) +#endif + +class TwoWire : public HardwareI2C { +protected: + uint8_t num; + int8_t sda; + int8_t scl; + + size_t bufferSize; + uint8_t *rxBuffer; + size_t rxIndex; + size_t rxLength; + + uint8_t *txBuffer; + size_t txLength; + uint16_t txAddress; + + uint32_t _timeOutMillis; + bool nonStop; +#if !CONFIG_DISABLE_HAL_LOCKS + TaskHandle_t currentTaskHandle; + SemaphoreHandle_t lock; +#endif +private: +#if SOC_I2C_SUPPORT_SLAVE + bool is_slave; + std::function user_onRequest; + std::function user_onReceive; + static void onRequestService(uint8_t, void *); + static void onReceiveService(uint8_t, uint8_t *, size_t, bool, void *); +#endif /* SOC_I2C_SUPPORT_SLAVE */ + bool initPins(int sdaPin, int sclPin); + bool allocateWireBuffer(); + void freeWireBuffer(); + +public: + TwoWire(uint8_t bus_num); + ~TwoWire(); + + bool begin() override final { + return begin(-1, -1); + } + + bool begin(uint8_t address) override final { +#if SOC_I2C_SUPPORT_SLAVE + return begin(address, -1, -1, 0); +#else + log_e("I2C slave is not supported on " CONFIG_IDF_TARGET); + return false; +#endif + } + + bool end() override; + + uint8_t getBusNum(); + + bool setClock(uint32_t freq) override; + + void beginTransmission(uint8_t address) override; + uint8_t endTransmission(bool stopBit) override; + uint8_t endTransmission() override; + + size_t requestFrom(uint8_t address, size_t len, bool stopBit) override; + size_t requestFrom(uint8_t address, size_t len) override; + + void onReceive(const std::function &) override; + void onRequest(const std::function &) override; + + //call setPins() first, so that begin() can be called without arguments from libraries + bool setPins(int sda, int scl); + + bool begin(int sda, int scl, uint32_t frequency = 0); // returns true, if successful init of i2c bus +#if SOC_I2C_SUPPORT_SLAVE + bool begin(uint8_t slaveAddr, int sda, int scl, uint32_t frequency); +#endif /* SOC_I2C_SUPPORT_SLAVE */ + + size_t setBufferSize(size_t bSize); + + void setTimeOut(uint16_t timeOutMillis); // default timeout of i2c transactions is 50ms + uint16_t getTimeOut(); + + uint32_t getClock(); + + size_t write(uint8_t) override; + size_t write(const uint8_t *, size_t) override; + int available() override; + int read() override; + int peek() override; + void flush() override; + +#if SOC_I2C_SUPPORT_SLAVE + size_t slaveWrite(const uint8_t *, size_t); +#endif /* SOC_I2C_SUPPORT_SLAVE */ +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_WIRE) +extern TwoWire Wire; +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) +#if SOC_I2C_NUM > 1 +extern TwoWire Wire1; +#elif SOC_I2C_NUM > 2 +extern TwoWire Wire2; +#endif /* SOC_I2C_NUM */ +#else +#if SOC_HP_I2C_NUM > 1 +extern TwoWire Wire1; +#endif /* SOC_HP_I2C_NUM */ +#endif +#endif + +#endif /* SOC_I2C_SUPPORTED */ +#endif /* TwoWire_h */ diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md new file mode 100644 index 0000000..d629417 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md @@ -0,0 +1,72 @@ +# Arduino-ESP32 Zigbee Analog Input Output Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) analog input/output device. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Analog Sensor Functions + + * After this board first starts up, it would be configured locally to report an analog input on change or every 30 seconds. + * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured value to the network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the ADC GPIO by changing the `analogPin` variable. By default, it's the pin `A0`. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino new file mode 100644 index 0000000..f1cc54b --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino @@ -0,0 +1,163 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee analog input / output device. + * + * The example demonstrates how to use Zigbee library to create a end device analog device. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + * Modified by Pat Clay + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator/router device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee analog device configuration */ +#define ANALOG_DEVICE_ENDPOINT_NUMBER 1 + +uint8_t analogPin = A0; +uint8_t button = BOOT_PIN; + +ZigbeeAnalog zbAnalogDevice = ZigbeeAnalog(ANALOG_DEVICE_ENDPOINT_NUMBER); +ZigbeeAnalog zbAnalogTemp = ZigbeeAnalog(ANALOG_DEVICE_ENDPOINT_NUMBER + 1); +ZigbeeAnalog zbAnalogFan = ZigbeeAnalog(ANALOG_DEVICE_ENDPOINT_NUMBER + 2); +ZigbeeAnalog zbAnalogPercent = ZigbeeAnalog(ANALOG_DEVICE_ENDPOINT_NUMBER + 3); + +void onAnalogOutputChange(float analog_output) { + Serial.printf("Received analog output change: %.1f\r\n", analog_output); +} + +void setup() { + Serial.begin(115200); + Serial.println("Starting..."); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set analog resolution to 10 bits + analogReadResolution(10); + + // Optional: set Zigbee device name and model + zbAnalogDevice.setManufacturerAndModel("Espressif", "ZigbeeAnalogDevice"); + + // Set up analog input + zbAnalogDevice.addAnalogInput(); + zbAnalogDevice.setAnalogInputApplication(ESP_ZB_ZCL_AI_POWER_IN_WATTS_CONSUMPTION); + zbAnalogDevice.setAnalogInputDescription("Power Consumption (Watts)"); + zbAnalogDevice.setAnalogInputResolution(0.01); + + // Set up analog output + zbAnalogDevice.addAnalogOutput(); + zbAnalogDevice.setAnalogOutputApplication(ESP_ZB_ZCL_AI_RPM_OTHER); + zbAnalogDevice.setAnalogOutputDescription("Fan Speed (RPM)"); + zbAnalogDevice.setAnalogOutputResolution(1); + + // Set the min and max values for the analog output which is used by HA to limit the range of the analog output + zbAnalogDevice.setAnalogOutputMinMax(-10000, 10000); //-10000 to 10000 RPM + + // If analog output cluster is added, set callback function for analog output change + zbAnalogDevice.onAnalogOutputChange(onAnalogOutputChange); + + // Set up analog input + zbAnalogTemp.addAnalogInput(); + zbAnalogTemp.setAnalogInputApplication(ESP_ZB_ZCL_AI_TEMPERATURE_OTHER); + zbAnalogTemp.setAnalogInputDescription("Temperature"); + zbAnalogTemp.setAnalogInputResolution(0.1); + + // Set up analog input + zbAnalogFan.addAnalogInput(); + zbAnalogFan.setAnalogInputApplication(ESP_ZB_ZCL_AI_RPM_OTHER); + zbAnalogFan.setAnalogInputDescription("RPM"); + zbAnalogFan.setAnalogInputResolution(1); + + // Set up analog input + zbAnalogPercent.addAnalogInput(); + zbAnalogPercent.setAnalogInputApplication(ESP_ZB_ZCL_AI_PERCENTAGE_OTHER); + zbAnalogPercent.setAnalogInputDescription("Percentage"); + zbAnalogPercent.setAnalogInputResolution(0.01); + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbAnalogDevice); + Zigbee.addEndpoint(&zbAnalogTemp); + Zigbee.addEndpoint(&zbAnalogFan); + Zigbee.addEndpoint(&zbAnalogPercent); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in Router Device mode + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); + + // Optional: Add reporting for analog input + zbAnalogDevice.setAnalogInputReporting(0, 30, 10); // report every 30 seconds if value changes by 10 +} + +void loop() { + static uint32_t timeCounter = 0; + + // Read ADC value and update the analog value every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + float analog = (float)analogRead(analogPin); + Serial.printf("Updating analog input to %.1f\r\n", analog); + zbAnalogDevice.setAnalogInput(analog); + zbAnalogTemp.setAnalogInput(analog / 100); + zbAnalogFan.setAnalogInput(analog); + zbAnalogPercent.setAnalogInput(analog / 10); + + // Analog input supports reporting + zbAnalogDevice.reportAnalogInput(); + zbAnalogTemp.reportAnalogInput(); + zbAnalogFan.reportAnalogInput(); + zbAnalogPercent.reportAnalogInput(); + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // For demonstration purposes, increment the analog output value by 100 + zbAnalogDevice.setAnalogOutput(zbAnalogDevice.getAnalogOutput() + 100); + zbAnalogDevice.reportAnalogOutput(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.yml b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/README.md b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/README.md new file mode 100644 index 0000000..18b8694 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/README.md @@ -0,0 +1,80 @@ +# Arduino-ESP32 Zigbee Binary Input Output Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) binary input/output device with multiple applications: HVAC fan status/control, security zone armed status, and HVAC humidifier control. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Binary Input/Output Functions + + * The example implements three binary devices: + - **Binary Fan Device (Endpoint 1)**: + - Binary Input: HVAC Fan Status - Reports the current state of a fan + - Binary Output: HVAC Fan - Controls the fan switch with callback function + - **Binary Zone Device (Endpoint 2)**: + - Binary Input: Security Zone Armed - Reports the armed state of a security zone + - **Binary Humidifier Device (Endpoint 3)**: + - Binary Output: HVAC Humidifier - Controls the humidifier switch with callback function + * By clicking the button (BOOT) on this board, it will toggle all binary inputs/outputs and immediately send a report of their states to the network. + * Holding the button for more than 3 seconds will trigger a factory reset of the Zigbee device. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +The example uses the following default pins: +* Button: `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2) + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/Zigbee_Binary_Input_Output.ino b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/Zigbee_Binary_Input_Output.ino new file mode 100644 index 0000000..60ae273 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/Zigbee_Binary_Input_Output.ino @@ -0,0 +1,144 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee binary input/output device. + * + * The example demonstrates how to use Zigbee library to create an end device binary sensor/switch device. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee binary sensor device configuration */ +#define BINARY_DEVICE_ENDPOINT_NUMBER 1 + +uint8_t button = BOOT_PIN; + +ZigbeeBinary zbBinaryFan = ZigbeeBinary(BINARY_DEVICE_ENDPOINT_NUMBER); +ZigbeeBinary zbBinaryZone = ZigbeeBinary(BINARY_DEVICE_ENDPOINT_NUMBER + 1); +ZigbeeBinary zbBinaryHumidifier = ZigbeeBinary(BINARY_DEVICE_ENDPOINT_NUMBER + 2); + +bool zoneStatus = false; + +void fanSwitch(bool state) { + Serial.println("Fan switch changed to: " + String(state)); + // Switch Fan status input signaling the fan status has changed + zbBinaryFan.setBinaryInput(state); + zbBinaryFan.reportBinaryInput(); +} + +void humidifierSwitch(bool state) { + Serial.println("Humidifier switch changed to: " + String(state)); +} + +void setup() { + Serial.begin(115200); + Serial.println("Starting..."); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set analog resolution to 10 bits + analogReadResolution(10); + + // Optional: set Zigbee device name and model + zbBinaryFan.setManufacturerAndModel("Espressif", "ZigbeeBinarySensor"); + + // Set up binary fan status input + switch output (HVAC) + zbBinaryFan.addBinaryInput(); + zbBinaryFan.setBinaryInputApplication(BINARY_INPUT_APPLICATION_TYPE_HVAC_FAN_STATUS); + zbBinaryFan.setBinaryInputDescription("Fan Status"); + + zbBinaryFan.addBinaryOutput(); + zbBinaryFan.setBinaryOutputApplication(BINARY_OUTPUT_APPLICATION_TYPE_HVAC_FAN); + zbBinaryFan.setBinaryOutputDescription("Fan Switch"); + + zbBinaryFan.onBinaryOutputChange(fanSwitch); + + // Set up binary zone armed input (Security) + zbBinaryZone.addBinaryInput(); + zbBinaryZone.setBinaryInputApplication(BINARY_INPUT_APPLICATION_TYPE_SECURITY_ZONE_ARMED); + zbBinaryZone.setBinaryInputDescription("Zone Armed"); + + // Set up binary humidifier output (HVAC) + zbBinaryHumidifier.addBinaryOutput(); + zbBinaryHumidifier.setBinaryOutputApplication(BINARY_OUTPUT_APPLICATION_TYPE_HVAC_HUMIDIFIER); + zbBinaryHumidifier.setBinaryOutputDescription("Humidifier Switch"); + + zbBinaryHumidifier.onBinaryOutputChange(humidifierSwitch); + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbBinaryFan); + Zigbee.addEndpoint(&zbBinaryZone); + Zigbee.addEndpoint(&zbBinaryHumidifier); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); +} + +void loop() { + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + + // Toggle fan + zbBinaryFan.setBinaryOutput(!zbBinaryFan.getBinaryOutput()); + zbBinaryFan.reportBinaryOutput(); + + // Toggle zone + zoneStatus = !zoneStatus; + zbBinaryZone.setBinaryInput(zoneStatus); + zbBinaryZone.reportBinaryInput(); + + // Toggle humidifier + zbBinaryHumidifier.setBinaryOutput(!zbBinaryHumidifier.getBinaryOutput()); + zbBinaryHumidifier.reportBinaryOutput(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/ci.yml b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Binary_Input_Output/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md new file mode 100644 index 0000000..88c8bf0 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md @@ -0,0 +1,72 @@ +# Arduino-ESP32 Carbon dioxide (CO2) Sensor Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with carbon dioxide measuring. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Pressure + Flow Sensor Functions + + * After this board first starts up, it would be configured locally to report the carbon dioxide on every 30 seconds. + * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured carbon dioxide to the network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +In this example, the internal temperature sensor is used to demonstrate reading of the carbon dioxide sensors. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino new file mode 100644 index 0000000..47b9a05 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino @@ -0,0 +1,106 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee carbon dioxide sensor. + * + * The example demonstrates how to use Zigbee library to create a end device carbon dioxide sensor. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee carbon dioxide sensor configuration */ +#define CARBON_DIOXIDE_SENSOR_ENDPOINT_NUMBER 10 +uint8_t button = BOOT_PIN; + +ZigbeeCarbonDioxideSensor zbCarbonDioxideSensor = ZigbeeCarbonDioxideSensor(CARBON_DIOXIDE_SENSOR_ENDPOINT_NUMBER); + +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbCarbonDioxideSensor.setManufacturerAndModel("Espressif", "ZigbeeCarbonDioxideSensor"); + + // Set minimum and maximum carbon dioxide measurement value in ppm + zbCarbonDioxideSensor.setMinMaxValue(0, 1500); + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbCarbonDioxideSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Set reporting interval for carbon dioxide measurement to be done every 30 seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta (carbon dioxide change in ppm) + // if min = 1 and max = 0, reporting is sent only when carbon dioxide changes by delta + // if min = 0 and max = 10, reporting is sent every 10 seconds or when carbon dioxide changes by delta + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change + zbCarbonDioxideSensor.setReporting(0, 30, 0); +} + +void loop() { + static uint32_t timeCounter = 0; + // Read carbon dioxide sensor every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + // Read sensor value - here is chip temperature used + 300 as a dummy value for demonstration + uint16_t carbon_dioxide_value = 300 + (uint16_t)temperatureRead(); + Serial.printf("Updating carbon dioxide sensor value to %d ppm\r\n", carbon_dioxide_value); + zbCarbonDioxideSensor.setCarbonDioxide(carbon_dioxide_value); + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + zbCarbonDioxideSensor.report(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md new file mode 100644 index 0000000..4da23c8 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee Color Dimmable Light Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) color dimmable light. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with Zigbee_Color_Dimmer_Switch example) +* A USB cable for power supply and programming +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Color_Dimmable_Light example + +### Configure the Project + +Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino new file mode 100644 index 0000000..5549fcc --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino @@ -0,0 +1,153 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee Color Dimmable light bulb with RGB and Temperature support. + * + * The example demonstrates how to use Zigbee library to create an end device with + * color dimmable light end point supporting both RGB (X/Y) and Color Temperature modes. + * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee color dimmable light configuration */ +#define ZIGBEE_RGB_LIGHT_ENDPOINT 10 +uint8_t led = RGB_BUILTIN; +uint8_t button = BOOT_PIN; + +ZigbeeColorDimmableLight zbColorLight = ZigbeeColorDimmableLight(ZIGBEE_RGB_LIGHT_ENDPOINT); + +/********************* Temperature conversion functions **************************/ +uint16_t kelvinToMireds(uint16_t kelvin) { + return 1000000 / kelvin; +} + +uint16_t miredsToKelvin(uint16_t mireds) { + return 1000000 / mireds; +} + +/********************* RGB LED functions **************************/ +void setRGBLight(bool state, uint8_t red, uint8_t green, uint8_t blue, uint8_t level) { + if (!state) { + rgbLedWrite(led, 0, 0, 0); + return; + } + float brightness = (float)level / 255; + rgbLedWrite(led, red * brightness, green * brightness, blue * brightness); +} + +/********************* Temperature LED functions **************************/ +void setTempLight(bool state, uint8_t level, uint16_t mireds) { + if (!state) { + rgbLedWrite(led, 0, 0, 0); + return; + } + float brightness = (float)level / 255; + // Convert mireds to color temperature (K) and map to white/yellow + uint16_t kelvin = miredsToKelvin(mireds); + uint8_t warm = constrain(map(kelvin, 2000, 6500, 255, 0), 0, 255); + uint8_t cold = constrain(map(kelvin, 2000, 6500, 0, 255), 0, 255); + rgbLedWrite(led, warm * brightness, warm * brightness, cold * brightness); +} + +// Create a task on identify call to handle the identify function +void identify(uint16_t time) { + static uint8_t blink = 1; + log_d("Identify called for %d seconds", time); + if (time == 0) { + // If identify time is 0, stop blinking and restore light as it was used for identify + zbColorLight.restoreLight(); + return; + } + rgbLedWrite(led, 255 * blink, 255 * blink, 255 * blink); + blink = !blink; +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init RMT and leave light OFF + rgbLedWrite(led, 0, 0, 0); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + // Enable both XY (RGB) and Temperature color capabilities + uint16_t capabilities = ZIGBEE_COLOR_CAPABILITY_X_Y | ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP; + zbColorLight.setLightColorCapabilities(capabilities); + + // Set callback functions for RGB and Temperature modes + zbColorLight.onLightChangeRgb(setRGBLight); + zbColorLight.onLightChangeTemp(setTempLight); + + // Optional: Set callback function for device identify + zbColorLight.onIdentify(identify); + + // Optional: Set Zigbee device name and model + zbColorLight.setManufacturerAndModel("Espressif", "ZBColorLightBulb"); + + // Set min/max temperature range (High Kelvin -> Low Mireds: Min and Max is switched) + zbColorLight.setLightColorTemperatureRange(kelvinToMireds(6500), kelvinToMireds(2000)); + + // Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeLight endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbColorLight); + + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // Increase blightness by 50 every time the button is pressed + zbColorLight.setLightLevel(zbColorLight.getLightLevel() + 50); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.yml b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md new file mode 100644 index 0000000..8dd63a7 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee Color Dimmer Switch Example + +This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) color dimmer light switch. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_Color_Dimmable_Light example). +* A USB cable for power supply and programming. +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator and upload the Zigbee_Color_Dimmable_Light example. + +### Configure the Project + +Set the Button Switch GPIO by changing the `GPIO_SWITCH` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`. +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`. +* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with the example `Zigbee_Color_Dimmable_Light` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino new file mode 100644 index 0000000..bc57300 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino @@ -0,0 +1,165 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee color dimmer switch. + * + * The example demonstrates how to use Zigbee library to control a RGB light bulb. + * The RGB light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator (Switch). + * To turn on/off the light, push the button on the switch. + * To change the color, level, or step the level of the light, send serial commands to the switch. + * + * By setting the switch to allow multiple binding, so it can bind to multiple lights. + * Also every 30 seconds, all bound lights are printed to the serial console. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee color dimmer switch configuration */ +#define SWITCH_ENDPOINT_NUMBER 5 +uint8_t button = BOOT_PIN; + +/* Zigbee switch */ +ZigbeeColorDimmerSwitch zbSwitch = ZigbeeColorDimmerSwitch(SWITCH_ENDPOINT_NUMBER); + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + //Init button switch + pinMode(button, INPUT_PULLUP); + + //Optional: set Zigbee device name and model + zbSwitch.setManufacturerAndModel("Espressif", "ZigbeeSwitch"); + + //Optional to allow multiple light to bind to the switch + zbSwitch.allowMultipleBinding(true); + + //Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbSwitch); + + //Open network for 180 seconds after boot + Zigbee.setRebootOpenNetwork(180); + + //When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode + if (!Zigbee.begin(ZIGBEE_COORDINATOR)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + Serial.println("Waiting for Light to bound to the switch"); + //Wait for switch to bound to a light: + while (!zbSwitch.bound()) { + Serial.printf("."); + delay(500); + } + Serial.println(); +} + +void loop() { + // Handle button switch in loop() + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + while (digitalRead(button) == LOW) { + delay(50); + } + // Toggle light + zbSwitch.lightToggle(); + } + // Handle serial input to control color and level of the light + if (Serial.available()) { + String command = Serial.readString(); + + if (command == "on") { + zbSwitch.lightOn(); + } else if (command == "off") { + zbSwitch.lightOff(); + } else if (command == "toggle") { + zbSwitch.lightToggle(); + } else if (command == "red") { + zbSwitch.setLightColor(255, 0, 0); + } else if (command == "green") { + zbSwitch.setLightColor(0, 255, 0); + } else if (command == "blue") { + zbSwitch.setLightColor(0, 0, 255); + } else if (command == "white") { + zbSwitch.setLightColor(255, 255, 255); + } else if (command == "color") { + //wait for color value + Serial.println("Enter red value (0-255):"); + while (!Serial.available()) { + delay(100); + } + int red = Serial.parseInt(); + Serial.println("Enter green value (0-255):"); + while (!Serial.available()) { + delay(100); + } + int green = Serial.parseInt(); + Serial.println("Enter blue value (0-255):"); + while (!Serial.available()) { + delay(100); + } + int blue = Serial.parseInt(); + zbSwitch.setLightColor(red, green, blue); + } else if (command == "level") { + //wait for level value + Serial.println("Enter level value (0-255):"); + while (!Serial.available()) { + delay(100); + } + int level = Serial.parseInt(); + zbSwitch.setLightLevel(level); + } else if (command == "stepup") { + // Step level up by 20 units over 1 second + zbSwitch.setLightLevelStep(ZIGBEE_LEVEL_STEP_UP, 20, 10); + Serial.println("Step level up"); + } else if (command == "stepdown") { + // Step level down by 20 units over 1 second + zbSwitch.setLightLevelStep(ZIGBEE_LEVEL_STEP_DOWN, 20, 10); + Serial.println("Step level down"); + } else if (command == "stepupfast") { + // Step level up by 10 units as fast as possible (transition_time 0xFFFF) + zbSwitch.setLightLevelStep(ZIGBEE_LEVEL_STEP_UP, 10, 0xFFFF); + Serial.println("Step level up (fast)"); + } else if (command == "stepdownfast") { + // Step level down by 10 units as fast as possible + zbSwitch.setLightLevelStep(ZIGBEE_LEVEL_STEP_DOWN, 10, 0xFFFF); + Serial.println("Step level down (fast)"); + } else if (command == "help") { + Serial.println("Commands: on, off, toggle, red, green, blue, white, color, level, stepup, stepdown, stepupfast, stepdownfast"); + } else { + Serial.println("Unknown command (type 'help' for list)"); + } + } + + // print the bound devices (lights) every 30 seconds + static uint32_t last_print = 0; + if (millis() - last_print > 30000) { + last_print = millis(); + zbSwitch.printBoundDevices(Serial); + } +} diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.yml b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md b/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md new file mode 100644 index 0000000..a5a3235 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md @@ -0,0 +1,58 @@ +# Arduino-ESP32 Zigbee Contact Switch Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) contact switch (IAS Zone), +that can be used for example as window/door sensor having 2 states - closed/open. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). +Set the Sensor GPIO by changing the `sensor_pin` variable. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino b/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino new file mode 100644 index 0000000..1a84c4d --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino @@ -0,0 +1,138 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee contact switch (IAS Zone). + * + * The example demonstrates how to use Zigbee library to create a end device contact switch. + * The contact switch is a Zigbee end device, which is reporting data to the Zigbee network. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" +#include + +/* Zigbee contact sensor configuration */ +#define CONTACT_SWITCH_ENDPOINT_NUMBER 1 +uint8_t button = BOOT_PIN; +uint8_t sensor_pin = 4; + +ZigbeeContactSwitch zbContactSwitch = ZigbeeContactSwitch(CONTACT_SWITCH_ENDPOINT_NUMBER); + +/* Preferences for storing ENROLLED flag to persist across reboots */ +Preferences preferences; + +void setup() { + Serial.begin(115200); + + preferences.begin("Zigbee", false); // Save ENROLLED flag in flash so it persists across reboots + bool enrolled = preferences.getBool("ENROLLED"); // Get ENROLLED flag from preferences + preferences.end(); + + // Init button + switch + pinMode(button, INPUT_PULLUP); + pinMode(sensor_pin, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbContactSwitch.setManufacturerAndModel("Espressif", "ZigbeeContactSwitch"); + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbContactSwitch); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Check if device has been enrolled before restarting - if so, restore IAS Zone enroll, otherwise request new IAS Zone enroll + if (enrolled) { + Serial.println("Device has been enrolled before - restoring IAS Zone enrollment"); + zbContactSwitch.restoreIASZoneEnroll(); + } else { + Serial.println("Device is factory new - first time joining network - requesting new IAS Zone enrollment"); + zbContactSwitch.requestIASZoneEnroll(); + } + + while (!zbContactSwitch.enrolled()) { + Serial.print("."); + delay(100); + } + Serial.println(); + Serial.println("Zigbee enrolled successfully!"); + + // Store ENROLLED flag only if this was a new enrollment (previous flag was false) + // Skip writing if we just restored enrollment (flag was already true) + if (!enrolled) { + preferences.begin("Zigbee", false); + preferences.putBool("ENROLLED", true); // set ENROLLED flag to true + preferences.end(); + Serial.println("ENROLLED flag saved to preferences"); + } +} + +void loop() { + // Checking pin for contact change + static bool contact = false; + if (digitalRead(sensor_pin) == HIGH && !contact) { + // Update contact sensor value + zbContactSwitch.setOpen(); + contact = true; + } else if (digitalRead(sensor_pin) == LOW && contact) { + zbContactSwitch.setClosed(); + contact = false; + } + + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + // Clear the ENROLLED flag from preferences + preferences.begin("Zigbee", false); + preferences.putBool("ENROLLED", false); // set ENROLLED flag to false + preferences.end(); + Serial.println("ENROLLED flag cleared from preferences"); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.yml b/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md new file mode 100644 index 0000000..e5bf51b --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee Dimmable Light Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) dimmable light. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming +* Board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Dimmable_Light example +* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application) + +### Configure the Project + +Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino new file mode 100644 index 0000000..c77a7e7 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino @@ -0,0 +1,121 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee Dimmable light bulb. + * + * The example demonstrates how to use Zigbee library to create an end device with + * dimmable light end point. + * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by [FaBjE](https://github.com/FaBjE) based on examples by [Jan Procházka](https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee dimmable light configuration */ +#define ZIGBEE_LIGHT_ENDPOINT 10 +uint8_t led = RGB_BUILTIN; +uint8_t button = BOOT_PIN; + +ZigbeeDimmableLight zbDimmableLight = ZigbeeDimmableLight(ZIGBEE_LIGHT_ENDPOINT); + +/********************* RGB LED functions **************************/ +void setLight(bool state, uint8_t level) { + if (!state) { + rgbLedWrite(led, 0, 0, 0); + return; + } + rgbLedWrite(led, level, level, level); +} + +// Create a task on identify call to handle the identify function +void identify(uint16_t time) { + static uint8_t blink = 1; + log_d("Identify called for %d seconds", time); + if (time == 0) { + // If identify time is 0, stop blinking and restore light as it was used for identify + zbDimmableLight.restoreLight(); + return; + } + rgbLedWrite(led, 255 * blink, 255 * blink, 255 * blink); + blink = !blink; +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init RMT and leave light OFF + rgbLedWrite(led, 0, 0, 0); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + // Set callback function for light change + zbDimmableLight.onLightChange(setLight); + + // Optional: Set callback function for device identify + zbDimmableLight.onIdentify(identify); + + // Optional: Set Zigbee device name and model + zbDimmableLight.setManufacturerAndModel("Espressif", "ZBLightBulb"); + + // Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeLight endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbDimmableLight); + + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // Increase blightness by 50 every time the button is pressed + zbDimmableLight.setLightLevel(zbDimmableLight.getLightLevel() + 50); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.yml b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/README.md new file mode 100644 index 0000000..fe03204 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/README.md @@ -0,0 +1,87 @@ +# Arduino-ESP32 Zigbee AC Electrical Measurement Example + +This example shows how to configure the Zigbee router device and use it as a Home Automation (HA) AC electrical measurement device that reports voltage, current, power, and frequency measurements. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## AC Electrical Measurement Functions + + * After this board first starts up, it would be configured locally to report AC electrical measurements: + - AC voltage in volts (0-300.00 V) + - AC current in amps (0-10.000 A) + - AC power in watts (0-3200.0 W) + - AC frequency in hertz (0-65.000 Hz) + * Holding the button (BOOT) for more than 3 seconds will trigger a factory reset of the device. + * The device reports measurements every 2 seconds with simulated values. + +## Measurement Precision + +The example demonstrates how to set up proper measurement precision using multiplier and divisor values: + * Voltage: 1/100 = 0.01 V (1 unit = 10 mV) + * Current: 1/1000 = 0.001 A (1 unit = 1 mA) + * Power: 1/10 = 0.1 W (1 unit = 100 mW) + * Frequency: 1/1000 = 0.001 Hz (1 unit = 1 mHz) + +These settings ensure accurate reporting of measurements with proper decimal precision in the Zigbee network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the ADC GPIO by changing the `analogPin` variable. By default, it's the pin `A0`. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Router Zigbee mode: `Tools -> Zigbee mode: Zigbee Router` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the Router device flashed with this example is not connecting to the coordinator, erase the flash of the Router device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/Zigbee_Electrical_AC_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/Zigbee_Electrical_AC_Sensor.ino new file mode 100644 index 0000000..9e86561 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/Zigbee_Electrical_AC_Sensor.ino @@ -0,0 +1,162 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee electrical AC measurement device. + * + * The example demonstrates how to use Zigbee library to create a router device that measures + * AC electrical parameters like voltage, current, power, power factor and frequency. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +// Recommended to use Router mode, as this type of device is expected to be mains powered. +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator/router mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee AC measurement device configuration */ +#define AC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER 1 + +uint8_t analogPin = A0; +uint8_t button = BOOT_PIN; + +ZigbeeElectricalMeasurement zbElectricalMeasurement = ZigbeeElectricalMeasurement(AC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER); + +void onAnalogOutputChange(float analog_output) { + Serial.printf("Received analog output change: %.1f\r\n", analog_output); +} + +void setup() { + Serial.begin(115200); + Serial.println("Starting..."); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set analog resolution to 10 bits + analogReadResolution(10); + + // Optional: set Zigbee device name and model + zbElectricalMeasurement.setManufacturerAndModel("Espressif", "ZigbeeElectricalMeasurementAC"); + + // Add analog clusters to Zigbee Analog according your needs + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement( + ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC + ); // frequency is not phase specific (shared) + + // Optional: set Multiplier/Divisor for the measurements + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, 1, 100); // 1/100 = 0.01V (1 unit of measurement = 0.01V = 10mV) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, 1, 1000); // 1/1000 = 0.001A (1 unit of measurement = 0.001A = 1mA) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, 1, 10); // 1/10 = 0.1W (1 unit of measurement = 0.1W = 100mW) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, 1, 1000); // 1/1000 = 0.001Hz (1 unit of measurement = 0.001Hz = 1mHz) + + // Optional: set Min/max values for the measurements + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A, 0, 30000); // 0-300.00V + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A, 0, 10000); // 0-10.000A + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A, 0, 32000); // 0-3200.0W + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC, 0, 65000); // 0-65.000Hz + + // Optional: set power factor for the measurements + zbElectricalMeasurement.setACPowerFactor(ZIGBEE_AC_PHASE_TYPE_A, 98); // 100 = 1.00, 0 = 0.00, -100 = -1.00 + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbElectricalMeasurement); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in Router mode + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); + + // Optional: Add reporting for AC measurements (this is overridden by HomeAssistant ZHA if used as a Zigbee coordinator) + zbElectricalMeasurement.setACReporting( + ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A, 0, 30, 10 + ); // report every 30 seconds if value changes by 10 (0.1V) + zbElectricalMeasurement.setACReporting( + ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A, 0, 30, 100 + ); // report every 30 seconds if value changes by 10 (0.1A) + zbElectricalMeasurement.setACReporting( + ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A, 0, 30, 10 + ); // report every 30 seconds if value changes by 10 (1W) + zbElectricalMeasurement.setACReporting( + ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC, 0, 30, 100 + ); // report every 30 seconds if value changes by 100 (0.1Hz) +} + +void loop() { + static uint32_t timeCounter = 0; + + static uint8_t randomizer = 0; + // Read ADC value as current to demonstrate the measurements and update the electrical measurement values every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + uint16_t voltage = 23000 + randomizer; // 230.00 V + uint16_t current = analogReadMilliVolts(analogPin); // demonstrates 0-3.3A + int16_t power = ((voltage / 100) * (current / 1000) * 10); //calculate power in W + uint16_t frequency = 50135; // 50.000 Hz + Serial.printf("Updating AC voltage to %d (0.01V), current to %d (mA), power to %d (0.1W), frequency to %d (mHz)\r\n", voltage, current, power, frequency); + + // Update the measurements + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A, voltage); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A, current); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A, power); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC, frequency); + + // Report the measurements + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC); + + randomizer += 10; + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/README.md b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/README.md new file mode 100644 index 0000000..3714a05 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/README.md @@ -0,0 +1,87 @@ +# Arduino-ESP32 Zigbee AC Electrical MultiPhase Measurement Example + +This example shows how to configure the Zigbee router device and use it as a Home Automation (HA) AC electrical measurement device that reports voltage, current, power, and frequency measurements across three phases. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## AC Electrical Measurement Functions + + * After this board first starts up, it would be configured locally to report AC electrical measurements: + - AC voltage in volts (0-300.00 V) for each phase (A, B, C) + - AC current in amps (0-10.000 A) for each phase (A, B, C) + - AC power in watts (0-3200.0 W) for each phase (A, B, C) + - AC frequency in hertz (0-65.000 Hz) shared across all phases + * Holding the button (BOOT) for more than 3 seconds will trigger a factory reset of the device. + * The device reports measurements every 2 seconds with simulated values. + +## Measurement Precision + +The example demonstrates how to set up proper measurement precision using multiplier and divisor values: + * Voltage: 1/100 = 0.01 V (1 unit = 10 mV) + * Current: 1/1000 = 0.001 A (1 unit = 1 mA) + * Power: 1/10 = 0.1 W (1 unit = 100 mW) + * Frequency: 1/1000 = 0.001 Hz (1 unit = 1 mHz) + +These settings ensure accurate reporting of measurements with proper decimal precision in the Zigbee network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the ADC GPIO by changing the `analogPin` variable. By default, it's the pin `A0`. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Router Zigbee mode: `Tools -> Zigbee mode: Zigbee Router` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the Router device flashed with this example is not connecting to the coordinator, erase the flash of the Router device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/Zigbee_Electrical_AC_Sensor_MultiPhase.ino b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/Zigbee_Electrical_AC_Sensor_MultiPhase.ino new file mode 100644 index 0000000..e219113 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/Zigbee_Electrical_AC_Sensor_MultiPhase.ino @@ -0,0 +1,192 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee electrical AC measurement device with multi-phase support. + * + * The example demonstrates how to use Zigbee library to create a router device that measures + * AC electrical parameters like voltage, current, power, power factor and frequency across + * three phases (A, B, C). This allows monitoring of three-phase power systems commonly used + * in industrial and commercial applications. + * + * The device measures: + * - Per phase: voltage, current, power, power factor + * - Shared: frequency (common across all phases) + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +// Recommended to use Router mode, as this type of device is expected to be mains powered. +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator/router mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee AC measurement device configuration */ +#define AC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER 1 + +uint8_t analogPin = A0; +uint8_t button = BOOT_PIN; + +ZigbeeElectricalMeasurement zbElectricalMeasurement = ZigbeeElectricalMeasurement(AC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER); + +void onAnalogOutputChange(float analog_output) { + Serial.printf("Received analog output change: %.1f\r\n", analog_output); +} + +void setup() { + Serial.begin(115200); + Serial.println("Starting..."); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set analog resolution to 10 bits + analogReadResolution(10); + + // Optional: set Zigbee device name and model + zbElectricalMeasurement.setManufacturerAndModel("Espressif", "ZigbeeElectricalMeasurementAC"); + + // Add analog clusters to Zigbee Analog according your needs + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A); + + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_B); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_B); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_B); + + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_C); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_C); + zbElectricalMeasurement.addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_C); + + zbElectricalMeasurement.addACMeasurement( + ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC + ); // frequency is not phase specific (shared) + + // Recommended: set Multiplier/Divisor for the measurements (common for all phases) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, 1, 100); // 1/100 = 0.01V (1 unit of measurement = 0.01V = 10mV) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, 1, 1000); // 1/1000 = 0.001A (1 unit of measurement = 0.001A = 1mA) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, 1, 10); // 1/10 = 0.1W (1 unit of measurement = 0.1W = 100mW) + zbElectricalMeasurement.setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, 1, 1000); // 1/1000 = 0.001Hz (1 unit of measurement = 0.001Hz = 1mHz) + + // Optional: set Min/max values for the measurements + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A, 0, 30000); // 0-300.00V + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A, 0, 10000); // 0-10.000A + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A, 0, 32000); // 0-3200.0W + + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_B, 0, 30000); // 0-300.00V + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_B, 0, 10000); // 0-10.000A + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_B, 0, 32000); // 0-3200.0W + + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_C, 0, 30000); // 0-300.00V + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_C, 0, 10000); // 0-10.000A + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_C, 0, 32000); // 0-3200.0W + + zbElectricalMeasurement.setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC, 0, 65000); // 0-65.000Hz + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbElectricalMeasurement); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in Router mode + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); +} + +void loop() { + static uint32_t timeCounter = 0; + static uint8_t randomizer = 0; + // Read ADC value and update the analog value every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + uint16_t voltage = 23000 + randomizer; // 230.00 V + uint16_t current = analogReadMilliVolts(analogPin); // demonstrates approx 0-3.3A + int16_t power = ((voltage / 100) * (current / 1000) * 10); //calculate power in W + uint16_t frequency = 50135; // 50.000 Hz + Serial.printf("Updating AC voltage to %d (0.01V), current to %d (mA), power to %d (0.1W), frequency to %d (mHz)\r\n", voltage, current, power, frequency); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A, voltage); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A, current); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A, power); + + // Phase B demonstrates phase shift + current += 500; + voltage += 500; + power = ((voltage / 100) * (current / 1000) * 10); //calculate power in W + + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_B, voltage); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_B, current); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_B, power); + + // Phase C demonstrates phase shift + current += 500; + voltage += 500; + power = ((voltage / 100) * (current / 1000) * 10); //calculate power in W + + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_C, voltage); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_C, current); + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_C, power); + + zbElectricalMeasurement.setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC, frequency); + + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_A); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_A); + + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_B); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_B); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_B); + + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE, ZIGBEE_AC_PHASE_TYPE_C); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT, ZIGBEE_AC_PHASE_TYPE_C); + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_POWER, ZIGBEE_AC_PHASE_TYPE_C); + + zbElectricalMeasurement.reportAC(ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY, ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC); + + randomizer += 10; + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/ci.yml b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_AC_Sensor_MultiPhase/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/README.md new file mode 100644 index 0000000..e8922fc --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/README.md @@ -0,0 +1,85 @@ +# Arduino-ESP32 Zigbee DC Electrical Measurement Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) DC electrical measurement device that reports voltage, current, and power measurements. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## DC Electrical Measurement Functions + + * After this board first starts up, it would be configured locally to report DC electrical measurements: + - DC voltage in millivolts (0-5000 mV) + - DC current in milliamps (0-1000 mA) + - DC power in milliwatts (0-5000 mW) + * Holding the button (BOOT) for more than 3 seconds will trigger a factory reset of the device. + * The device reports measurements every 30 seconds if the value changes by more than the configured delta. + +## Measurement Precision + +The example demonstrates how to set up proper measurement precision using multiplier and divisor values: + * Voltage: 1/1000 = 0.001 V (1 unit = 1 mV) + * Current: 1/1000 = 0.001 A (1 unit = 1 mA) + * Power: 1/1000 = 0.001 W (1 unit = 1 mW) + +These settings ensure accurate reporting of measurements with proper decimal precision in the Zigbee network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the ADC GPIO by changing the `analogPin` variable. By default, it's the pin `A0`. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/Zigbee_Electrical_DC_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/Zigbee_Electrical_DC_Sensor.ino new file mode 100644 index 0000000..4324a7b --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/Zigbee_Electrical_DC_Sensor.ino @@ -0,0 +1,137 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates a Zigbee DC electrical measurement sensor. + * + * The example shows how to use the Zigbee library to create an end device that measures + * DC voltage, current and power using the Electrical Measurement cluster. + * + * The device reports: + * - DC voltage in millivolts (0-5000mV) + * - DC current in milliamps (0-1000mA) + * - DC power in milliwatts (0-5000mW) + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee DC measurement device configuration */ +#define DC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER 1 + +uint8_t analogPin = A0; +uint8_t button = BOOT_PIN; + +ZigbeeElectricalMeasurement zbElectricalMeasurement = ZigbeeElectricalMeasurement(DC_ELECTRICAL_MEASUREMENT_ENDPOINT_NUMBER); + +void setup() { + Serial.begin(115200); + Serial.println("Starting..."); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set analog resolution to 10 bits + analogReadResolution(10); + + // Optional: set Zigbee device name and model + zbElectricalMeasurement.setManufacturerAndModel("Espressif", "ZigbeeElectricalMeasurementDC"); + + // Add analog clusters to Zigbee Analog according your needs + zbElectricalMeasurement.addDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE); + zbElectricalMeasurement.addDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT); + zbElectricalMeasurement.addDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_POWER); + + // // Optional: set Min/max values for the measurements + zbElectricalMeasurement.setDCMinMaxValue(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE, 0, 5000); // 0-5.000V + zbElectricalMeasurement.setDCMinMaxValue(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT, 0, 1000); // 0-1.000A + zbElectricalMeasurement.setDCMinMaxValue(ZIGBEE_DC_MEASUREMENT_TYPE_POWER, 0, 5000); // 0-5.000W + + // // Optional: set Multiplier/Divisor for the measurements + zbElectricalMeasurement.setDCMultiplierDivisor(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE, 1, 1000); // 1/1000 = 0.001V (1 unit of measurement = 0.001V = 1mV) + zbElectricalMeasurement.setDCMultiplierDivisor(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT, 1, 1000); // 1/1000 = 0.001A (1 unit of measurement = 0.001A = 1mA) + zbElectricalMeasurement.setDCMultiplierDivisor(ZIGBEE_DC_MEASUREMENT_TYPE_POWER, 1, 1000); // 1/1000 = 0.001W (1 unit of measurement = 0.001W = 1mW) + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbElectricalMeasurement); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); + + // Optional: Add reporting for DC measurements (this is overridden by HomeAssistant ZHA if connected to its network) + zbElectricalMeasurement.setDCReporting(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE, 0, 30, 10); // report every 30 seconds if value changes by 10 (0.1V) + zbElectricalMeasurement.setDCReporting(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT, 0, 30, 10); // report every 30 seconds if value changes by 10 (0.1A) + zbElectricalMeasurement.setDCReporting(ZIGBEE_DC_MEASUREMENT_TYPE_POWER, 0, 30, 10); // report every 30 seconds if value changes by 10 (0.1W) +} + +void loop() { + static uint32_t timeCounter = 0; + static uint8_t randomizer = 0; + // Read ADC value and update the analog value every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + int16_t voltage_mv = (int16_t)(analogReadMilliVolts(analogPin)); + int16_t current_ma = randomizer; //0-255mA + int16_t power_mw = voltage_mv * current_ma / 1000; //calculate power in mW + Serial.printf("Updating DC voltage to %d mV, current to %d mA, power to %d mW\r\n", voltage_mv, current_ma, power_mw); + zbElectricalMeasurement.setDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE, voltage_mv); + zbElectricalMeasurement.setDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT, current_ma); + zbElectricalMeasurement.setDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE_POWER, power_mw); + // Analog input supports reporting + zbElectricalMeasurement.reportDC(ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE); + zbElectricalMeasurement.reportDC(ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT); + zbElectricalMeasurement.reportDC(ZIGBEE_DC_MEASUREMENT_TYPE_POWER); + + randomizer += 10; + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Electrical_DC_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Fan_Control/README.md b/libraries/Zigbee/examples/Zigbee_Fan_Control/README.md new file mode 100644 index 0000000..91700b6 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Fan_Control/README.md @@ -0,0 +1,83 @@ +# Arduino-ESP32 Zigbee Fan Control Example + +This example demonstrates how to use the Zigbee library to create a router device fan control and use it as a Home Automation (HA) fan control device. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Fan Control Functions + +1. Initialize a Zigbee fan control device. +2. Control fan modes (OFF, LOW, MEDIUM, HIGH, ON). +3. Respond to fan control commands from the Zigbee network. + +## Hardware Required + +* ESP32-H2 or ESP32-C6 development board +* A USB cable for power supply and programming +* RGB LED for visual feedback (built-in on most development boards) + +### Configure the Project + +In this example the RGB LED is used to indicate the current fan control mode. +The LED colors represent different fan modes: +- OFF: No light +- LOW: Blue +- MEDIUM: Yellow +- HIGH: Red +- ON: White + +Set the button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee ZCZR 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Fan_Control/Zigbee_Fan_Control.ino b/libraries/Zigbee/examples/Zigbee_Fan_Control/Zigbee_Fan_Control.ino new file mode 100644 index 0000000..4c0d15a --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Fan_Control/Zigbee_Fan_Control.ino @@ -0,0 +1,129 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee fan control. + * + * The example demonstrates how to use Zigbee library to create a router device fan control. + * The fan control is a Zigbee router device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee light bulb configuration */ +#define ZIGBEE_FAN_CONTROL_ENDPOINT 1 + +#ifdef RGB_BUILTIN +uint8_t led = RGB_BUILTIN; // To demonstrate the current fan control mode +#else +uint8_t led = 2; +#endif + +uint8_t button = BOOT_PIN; + +ZigbeeFanControl zbFanControl = ZigbeeFanControl(ZIGBEE_FAN_CONTROL_ENDPOINT); + +/********************* fan control callback function **************************/ +void setFan(ZigbeeFanMode mode) { + switch (mode) { + case FAN_MODE_OFF: + rgbLedWrite(led, 0, 0, 0); // Off + Serial.println("Fan mode: OFF"); + break; + case FAN_MODE_LOW: + rgbLedWrite(led, 0, 0, 255); // Blue + Serial.println("Fan mode: LOW"); + break; + case FAN_MODE_MEDIUM: + rgbLedWrite(led, 255, 255, 0); // Yellow + Serial.println("Fan mode: MEDIUM"); + break; + case FAN_MODE_HIGH: + rgbLedWrite(led, 255, 0, 0); // Red + Serial.println("Fan mode: HIGH"); + break; + case FAN_MODE_ON: + rgbLedWrite(led, 255, 255, 255); // White + Serial.println("Fan mode: ON"); + break; + default: log_e("Unhandled fan mode: %d", mode); break; + } +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init LED that will be used to indicate the current fan control mode + rgbLedWrite(led, 0, 0, 0); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + //Optional: set Zigbee device name and model + zbFanControl.setManufacturerAndModel("Espressif", "ZBFanControl"); + + // Set the fan mode sequence to LOW_MED_HIGH + zbFanControl.setFanModeSequence(FAN_MODE_SEQUENCE_LOW_MED_HIGH); + + // Set callback function for fan mode change + zbFanControl.onFanModeChange(setFan); + + //Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeFanControl endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbFanControl); + + // When all EPs are registered, start Zigbee in ROUTER mode + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Fan_Control/ci.yml b/libraries/Zigbee/examples/Zigbee_Fan_Control/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Fan_Control/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/README.md b/libraries/Zigbee/examples/Zigbee_Gateway/README.md new file mode 100644 index 0000000..4156538 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Gateway/README.md @@ -0,0 +1,64 @@ +# Arduino-ESP32 Zigbee Gateway Example + +This example shows how to configure Zigbee Gateway device, running on SoCs without native IEEE 802.15.4. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 | +| ----------------- | ----- | -------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee Radio Co-processor loaded with [ot_rcp example](https://github.com/espressif/esp-idf/tree/master/examples/openthread/ot_rcp). +* A USB cable for power supply and programming. +* Choose another board from supported targets as Zigbee coordinator/router and upload the Zigbee_Gateway example. + +### Configure the Project + +Set the RCP connection (UART) by changing the `GATEWAY_RCP_UART_PORT`, `GATEWAY_RCP_RX_PIN` and `GATEWAY_RCP_TX_PIN` definition. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`. +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`. +* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino b/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino new file mode 100644 index 0000000..402227b --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino @@ -0,0 +1,130 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee Gateway functionality. + * + * The example demonstrates how to use Zigbee library on ESP32s to create a Zigbee Gateway, updating the time from NTP server. + * The Gateway is able to communicate with Zigbee end devices and send/receive data to/from them. + * The Gateway is also able to communicate with the cloud or other devices over Wi-Fi / BLE. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode->Zigbee ZCZR (coordinator/router) + * and also the correct partition scheme must be selected in Tools->Partition Scheme->Zigbee ZCZR + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" +#include +#include "time.h" +#include "esp_sntp.h" + +/* Zigbee gateway configuration */ +#define GATEWAY_ENDPOINT_NUMBER 1 +#define GATEWAY_RCP_UART_PORT UART_NUM_1 // UART 0 is used for Serial communication +#define GATEWAY_RCP_RX_PIN 4 +#define GATEWAY_RCP_TX_PIN 5 + +ZigbeeGateway zbGateway = ZigbeeGateway(GATEWAY_ENDPOINT_NUMBER); + +/* Wi-Fi credentials */ +const char *ssid = "your-ssid"; +const char *password = "your-password"; + +/* NTP server configuration */ +const char *ntpServer1 = "pool.ntp.org"; +const char *ntpServer2 = "time.nist.gov"; +const long gmtOffset_sec = 3600; +const int daylightOffset_sec = 3600; +const char *time_zone = "CET-1CEST,M3.5.0,M10.5.0/3"; // TimeZone rule for Europe/Rome including daylight adjustment rules (optional) + +/* Time structure */ +struct tm timeinfo; + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Initialize Wi-Fi and connect to AP + WiFi.begin(ssid, password); + esp_sntp_servermode_dhcp(1); // (optional) + + Serial.print("Connecting to WiFi"); + + while (WiFi.status() != WL_CONNECTED) { + delay(500); + Serial.print("."); + } + Serial.println("WiFi connected"); + + // Initialize Zigbee and Begin Zigbee stack + // Optional: set Zigbee device name and model + zbGateway.setManufacturerAndModel("Espressif", "ZigbeeGateway"); + zbGateway.addTimeCluster(timeinfo, gmtOffset_sec); + + // Add endpoint to Zigbee Core + Serial.println("Adding Zigbee Gateway endpoint"); + Zigbee.addEndpoint(&zbGateway); + + // Optional: Open network for 180 seconds after boot + Zigbee.setRebootOpenNetwork(180); + + // Set custom radio configuration for RCP communication + esp_zb_radio_config_t radio_config = ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG(); + radio_config.radio_uart_config.port = GATEWAY_RCP_UART_PORT; + radio_config.radio_uart_config.rx_pin = (gpio_num_t)GATEWAY_RCP_RX_PIN; + radio_config.radio_uart_config.tx_pin = (gpio_num_t)GATEWAY_RCP_TX_PIN; + + Zigbee.setRadioConfig(radio_config); + + // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR or ZIGBEE_ROUTER mode + if (!Zigbee.begin(ZIGBEE_COORDINATOR)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + // set notification call-back function + sntp_set_time_sync_notification_cb(timeavailable); + sntp_set_sync_interval(30000); // sync every 30 seconds + + // config time zone and NTP servers + configTime(gmtOffset_sec, daylightOffset_sec, ntpServer1, ntpServer2); +} + +void loop() { + // Nothing to do here in this example +} + +void printLocalTime() { + if (!getLocalTime(&timeinfo)) { + Serial.println("No time available (yet)"); + return; + } + Serial.println(&timeinfo, "%A, %B %d %Y %H:%M:%S"); + zbGateway.setTime(timeinfo); + Serial.println("Time updated in Zigbee Gateway"); +} + +// Callback function (gets called when time adjusts via NTP) +void timeavailable(struct timeval *t) { + Serial.println("Got time adjustment from NTP!"); + printLocalTime(); +} diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/ci.yml b/libraries/Zigbee/examples/Zigbee_Gateway/ci.yml new file mode 100644 index 0000000..ab3b507 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Gateway/ci.yml @@ -0,0 +1,8 @@ +fqbn_append: PartitionScheme=zigbee_zczr_8MB,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y + +targets: + esp32c6: false + esp32h2: false diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md new file mode 100644 index 0000000..fe72369 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md @@ -0,0 +1,78 @@ +# Arduino-ESP32 Zigbee Illuminance Sensor Example + +This example demonstrates how to use the Zigbee library to create an end device illuminance sensor and use it as a Home Automation (HA) extended illuminance sensor. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Illuminance Sensor Functions + +1. Initialize a Zigbee illuminance sensor. +2. Measure illuminance value. +3. Report the measured value to the Zigbee network. + +## Hardware Required + +* ESP32-H2 or ESP32-C6 development board +* A USB cable for power supply and programming +* Some kind of light sensor, such as a photoresistor + +### Configure the Project + +In this example the raw analog value of a light sensor is used to calculate illuminance. +Alter the calculation according to your use case and calibrate it to receive correct lux values. +Set the illuminance sensor GPIO by changing the `illuminance_sensor_pin` variable to the pin to the pin to which your sensor is connected. +Set the button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Enable USB CDC to be able to use the serial monitor: `Tools -> USB CDC On Boot: Enabled` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure that you are using a good quality USB cable with data lines and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino new file mode 100644 index 0000000..bbb2cba --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino @@ -0,0 +1,141 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee illuminance sensor. + * + * The example demonstrates how to use Zigbee library to create a end device illuminance sensor. + * The illuminance sensor is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by MikaFromTheRoof (https://github.com/MikaFromTheRoof) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +#define ZIGBEE_ILLUMINANCE_SENSOR_ENDPOINT 9 +uint8_t button = BOOT_PIN; +uint8_t illuminance_sensor_pin = 6; // Insert the analog pin to which the sensor (e.g. photoresistor) is connected + +ZigbeeIlluminanceSensor zbIlluminanceSensor = ZigbeeIlluminanceSensor(ZIGBEE_ILLUMINANCE_SENSOR_ENDPOINT); + +/********************* Illuminance sensor **************************/ +static void illuminance_sensor_value_update(void *arg) { + for (;;) { + // read the raw analog value from the sensor + int lsens_analog_raw = analogRead(illuminance_sensor_pin); + Serial.printf("[Illuminance Sensor] raw analog value: %d\r\n", lsens_analog_raw); + + // conversion into zigbee raw illuminance value (typically between 0 in darkness and 50000 in direct sunlight) + // depends on the value range of the raw analog sensor values and will need calibration for correct lux values + // for demonstration purpose map the 12-bit ADC value (0-4095) to Zigbee illuminance range (0-50000) + int lsens_illuminance_raw = map(lsens_analog_raw, 0, 4095, 0, 50000); + Serial.printf("[Illuminance Sensor] raw illuminance value: %d\r\n", lsens_illuminance_raw); + + // according to zigbee documentation the formular 10^(lsens_illuminance_raw/10000)-1 can be used to calculate lux value from raw illuminance value + // Note: Zigbee2MQTT seems to be using the formular 10^(lsens_illuminance_raw/10000) instead (without -1) + int lsens_illuminance_lux = round(pow(10, (lsens_illuminance_raw / 10000.0)) - 1); + Serial.printf("[Illuminance Sensor] lux value: %d lux\r\n", lsens_illuminance_lux); + + // Update illuminance in illuminance sensor EP + zbIlluminanceSensor.setIlluminance(lsens_illuminance_raw); // use raw illuminance here! + + delay(1000); // reduce delay (in ms), if you want your device to react more quickly to changes in illuminance + } +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Optional: configure analog input + analogSetAttenuation(ADC_11db); // set analog to digital converter (ADC) attenuation to 11 dB (up to ~3.3V input) + analogReadResolution(12); // set analog read resolution to 12 bits (value range from 0 to 4095), 12 is default + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + // Optional: Set Zigbee device name and model + zbIlluminanceSensor.setManufacturerAndModel("Espressif", "ZigbeeIlluminanceSensor"); + + // Optional: Set power source (choose between ZB_POWER_SOURCE_MAINS and ZB_POWER_SOURCE_BATTERY), defaults to unknown + zbIlluminanceSensor.setPowerSource(ZB_POWER_SOURCE_MAINS); + + // Set minimum and maximum for raw illuminance value (0 min and 50000 max equals to 0 lux - 100,000 lux) + zbIlluminanceSensor.setMinMaxValue(0, 50000); + + // Optional: Set tolerance for raw illuminance value + zbIlluminanceSensor.setTolerance(1); + + // Add endpoint to Zigbee Core + Serial.println("Adding Zigbee illuminance sensor endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbIlluminanceSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Start illuminance sensor reading task + xTaskCreate(illuminance_sensor_value_update, "illuminance_sensor_update", 2048, NULL, 10, NULL); + + // Set reporting schedule for illuminance value measurement in seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta + // if min = 1 and max = 0, delta = 1000, reporting is sent when raw illuminance value changes by 1000, but at most once per second + // if min = 0 and max = 10, delta = 1000, reporting is sent every 10 seconds or if raw illuminance value changes by 1000 + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of illuminance change + // Note: On pairing with Zigbee Home Automation or Zigbee2MQTT the reporting schedule will most likely be overwritten with their default settings + zbIlluminanceSensor.setReporting(1, 0, 1000); +} + +/********************* Main loop **************************/ +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3 secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s"); + delay(1000); + Zigbee.factoryReset(); + } + } + // force report of illuminance when button is pressed + zbIlluminanceSensor.report(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/README.md b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/README.md new file mode 100644 index 0000000..662ebe7 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/README.md @@ -0,0 +1,90 @@ +# Arduino-ESP32 Zigbee Multistate Input Output Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) multistate input/output device. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Multistate Device Functions + +This example demonstrates two different multistate devices: + +1. **Standard Multistate Device** (`zbMultistateDevice`): Uses predefined application states from the Zigbee specification + - Application Type 0: Fan states (Off, On, Auto) + - Application Type 7: Light states (High, Normal, Low) + +2. **Custom Multistate Device** (`zbMultistateDeviceCustom`): Uses user-defined custom states + - Custom fan states: Off, On, UltraSlow, Slow, Fast, SuperFast + +* After this board first starts up, it will be configured as two multistate devices with different state configurations. +* By clicking the button (BOOT) on this board, the devices will cycle through their respective states and report the changes to the network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +The example creates two multistate devices: +- **Endpoint 1**: Standard multistate device using predefined Zigbee application types +- **Endpoint 2**: Custom multistate device using user-defined states + +You can modify the state names and configurations by changing the following variables: +- `multistate_custom_state_names[]`: Array of custom state names +- Application type and length macros: `ZB_MULTISTATE_APPLICATION_TYPE_X_STATE_NAMES`, +`ZB_MULTISTATE_APPLICATION_TYPE_X_NUM_STATES`, `ZB_MULTISTATE_APPLICATION_TYPE_X_INDEX` +- Device descriptions and application types in the setup() function + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator/Router Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee ZCZR 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/Zigbee_Multistate_Input_Output.ino b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/Zigbee_Multistate_Input_Output.ino new file mode 100644 index 0000000..d0f944e --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/Zigbee_Multistate_Input_Output.ino @@ -0,0 +1,189 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee multistate input / output device. + * + * The example demonstrates how to use Zigbee library to create a router multistate device. + * In the example, we have two multistate devices: + * - zbMultistateDevice: uses defined application states from Zigbee specification + * - zbMultistateDeviceCustom: uses custom application states (user defined) + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * NOTE: HomeAssistant ZHA does not support multistate input and output clusters yet. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator/router device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee multistate device configuration */ +#define MULTISTATE_DEVICE_ENDPOINT_NUMBER 1 + +uint8_t button = BOOT_PIN; + +// zbMultistateDevice will use defined application states +ZigbeeMultistate zbMultistateDevice = ZigbeeMultistate(MULTISTATE_DEVICE_ENDPOINT_NUMBER); + +// zbMultistateDeviceCustom will use custom application states (user defined) +ZigbeeMultistate zbMultistateDeviceCustom = ZigbeeMultistate(MULTISTATE_DEVICE_ENDPOINT_NUMBER + 1); + +const char *multistate_custom_state_names[6] = {"Off", "On", "UltraSlow", "Slow", "Fast", "SuperFast"}; + +void onStateChange(uint16_t state) { + // print the state + Serial.printf("Received state change: %d\r\n", state); + // print the state name using the stored state names + const char *const *state_names = ZB_MULTISTATE_APPLICATION_TYPE_7_STATE_NAMES; + if (state_names && state < zbMultistateDevice.getMultistateOutputStateNamesLength()) { + Serial.printf("State name: %s\r\n", state_names[state]); + } + // print state index of possible options + Serial.printf("State index: %d / %d\r\n", state, zbMultistateDevice.getMultistateOutputStateNamesLength() - 1); +} + +void onStateChangeCustom(uint16_t state) { + // print the state + Serial.printf("Received state change: %d\r\n", state); + // print the state name using the stored state names + if (state < zbMultistateDeviceCustom.getMultistateOutputStateNamesLength()) { + Serial.printf("State name: %s\r\n", multistate_custom_state_names[state]); + } + // print state index of possible options + Serial.printf("State index: %d / %d\r\n", state, zbMultistateDeviceCustom.getMultistateOutputStateNamesLength() - 1); + + Serial.print("Changing to fan mode to: "); + switch (state) { + case 0: Serial.println("Off"); break; + case 1: Serial.println("On"); break; + case 2: Serial.println("UltraSlow"); break; + case 3: Serial.println("Slow"); break; + case 4: Serial.println("Fast"); break; + case 5: Serial.println("SuperFast"); break; + default: Serial.println("Invalid state"); break; + } +} + +void setup() { + log_d("Starting serial"); + Serial.begin(115200); + + // Init button switch + log_d("Init button switch"); + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + log_d("Set Zigbee device name and model"); + zbMultistateDevice.setManufacturerAndModel("Espressif", "ZigbeeMultistateDevice"); + + // Set up analog input + log_d("Add Multistate Input"); + zbMultistateDevice.addMultistateInput(); + log_d("Set Multistate Input Application"); + zbMultistateDevice.setMultistateInputApplication(ZB_MULTISTATE_APPLICATION_TYPE_0_INDEX); + log_d("Set Multistate Input Description"); + zbMultistateDevice.setMultistateInputDescription("Fan (on/off/auto)"); + zbMultistateDevice.setMultistateInputStates(ZB_MULTISTATE_APPLICATION_TYPE_0_NUM_STATES); + + // Set up analog output + log_d("Add Multistate Output"); + zbMultistateDevice.addMultistateOutput(); + log_d("Set Multistate Output Application"); + zbMultistateDevice.setMultistateOutputApplication(ZB_MULTISTATE_APPLICATION_TYPE_7_INDEX); + log_d("Set Multistate Output Description"); + zbMultistateDevice.setMultistateOutputDescription("Light (high/normal/low)"); + zbMultistateDevice.setMultistateOutputStates(ZB_MULTISTATE_APPLICATION_TYPE_7_NUM_STATES); + + // Set up custom output + log_d("Add Multistate Output"); + zbMultistateDeviceCustom.addMultistateOutput(); + log_d("Set Multistate Output Application"); + zbMultistateDeviceCustom.setMultistateOutputApplication(ZB_MULTISTATE_APPLICATION_TYPE_OTHER_INDEX); + log_d("Set Multistate Output Description"); + zbMultistateDeviceCustom.setMultistateOutputDescription("Fan (on/off/slow/medium/fast)"); + zbMultistateDeviceCustom.setMultistateOutputStates(5); + + // Set callback function for multistate output change + log_d("Set callback function for multistate output change"); + zbMultistateDevice.onMultistateOutputChange(onStateChange); + zbMultistateDeviceCustom.onMultistateOutputChange(onStateChangeCustom); + + // Add endpoints to Zigbee Core + log_d("Add endpoints to Zigbee Core"); + Zigbee.addEndpoint(&zbMultistateDevice); + Zigbee.addEndpoint(&zbMultistateDeviceCustom); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in Router Device mode + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println("Connected"); +} + +void loop() { + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // For demonstration purposes, increment the multistate output/input value by 1 + if (zbMultistateDevice.getMultistateOutput() < zbMultistateDevice.getMultistateOutputStateNamesLength() - 1) { + zbMultistateDevice.setMultistateOutput(zbMultistateDevice.getMultistateOutput() + 1); + zbMultistateDevice.reportMultistateOutput(); + zbMultistateDevice.setMultistateInput(zbMultistateDevice.getMultistateOutput()); + zbMultistateDevice.reportMultistateInput(); + } else { + zbMultistateDevice.setMultistateOutput(0); + zbMultistateDevice.reportMultistateOutput(); + zbMultistateDevice.setMultistateInput(zbMultistateDevice.getMultistateOutput()); + zbMultistateDevice.reportMultistateInput(); + } + + if (zbMultistateDeviceCustom.getMultistateOutput() < zbMultistateDeviceCustom.getMultistateOutputStateNamesLength() - 1) { + zbMultistateDeviceCustom.setMultistateOutput(zbMultistateDeviceCustom.getMultistateOutput() + 1); + zbMultistateDeviceCustom.reportMultistateOutput(); + } else { + zbMultistateDeviceCustom.setMultistateOutput(0); + zbMultistateDeviceCustom.reportMultistateOutput(); + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/ci.yml b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Multistate_Input_Output/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md b/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md new file mode 100644 index 0000000..143ff94 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee OTA Client + on/off light Example + +This example shows how to configure the Zigbee end device with OTA Client and use it as a Home Automation (HA) on/off light. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`. +By default, the `rgbLedWrite` function is used to control the LED. You can change it to digitalWrite to control a simple LED. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino b/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino new file mode 100644 index 0000000..6ea2329 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino @@ -0,0 +1,131 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates OTA support on light bulb. + * + * The example demonstrates how to use Zigbee library to create a end device light bulb with OTA support. + * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee light bulb configuration */ +#define ZIGBEE_LIGHT_ENDPOINT 1 +uint8_t led = RGB_BUILTIN; +uint8_t button = BOOT_PIN; + +/* Zigbee OTA configuration */ +#define OTA_UPGRADE_RUNNING_FILE_VERSION 0x01010100 // Increment this value when the running image is updated +#define OTA_UPGRADE_DOWNLOADED_FILE_VERSION 0x01010101 // Increment this value when the downloaded image is updated +#define OTA_UPGRADE_HW_VERSION 0x0101 // The hardware version, this can be used to differentiate between different hardware versions + +ZigbeeLight zbLight = ZigbeeLight(ZIGBEE_LIGHT_ENDPOINT); + +volatile bool otaRunning = false; + +/********************* Callbacks *************************/ +void otaActiveCallback(bool otaActive) { + otaRunning = otaActive; + if (otaActive) { + Serial.println("OTA started"); + } else { + Serial.println("OTA finished"); + } +} + +/********************* RGB LED functions **************************/ +void setLED(bool value) { + digitalWrite(led, value); +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood) + pinMode(led, OUTPUT); + digitalWrite(led, LOW); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbLight.setManufacturerAndModel("Espressif", "ZBLightBulb"); + + // Set callback function for light change + zbLight.onLightChange(setLED); + + // Add OTA client to the light bulb + zbLight.addOTAClient(OTA_UPGRADE_RUNNING_FILE_VERSION, OTA_UPGRADE_DOWNLOADED_FILE_VERSION, OTA_UPGRADE_HW_VERSION); + + // Optional: Register callback for OTA state change + zbLight.onOTAStateChange(otaActiveCallback); + + // Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeLight endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbLight); + + // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Start Zigbee OTA client query, first request is within a minute and the next requests are sent every hour automatically + zbLight.requestOTAUpdate(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + if (otaRunning) { + Serial.println("OTA in progress, cannot reset now"); + break; + } + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // Toggle light by pressing the button + zbLight.setLight(!zbLight.getLightState()); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.yml b/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md new file mode 100644 index 0000000..0c5dcd0 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md @@ -0,0 +1,57 @@ +# Arduino-ESP32 Zigbee Occupancy Sensor Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) occupancy sensor (PIR). + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). +Set the Sensor GPIO by changing the `sensor_pin` variable. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino new file mode 100644 index 0000000..46afdf3 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino @@ -0,0 +1,103 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee occupancy sensor. + * + * The example demonstrates how to use Zigbee library to create a end device occupancy sensor. + * The occupancy sensor is a Zigbee end device, which is reporting data to the Zigbee network. + * Tested with PIR sensor HC-SR501 connected to GPIO4. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee occupancy sensor configuration */ +#define OCCUPANCY_SENSOR_ENDPOINT_NUMBER 10 +uint8_t button = BOOT_PIN; +uint8_t sensor_pin = 4; + +ZigbeeOccupancySensor zbOccupancySensor = ZigbeeOccupancySensor(OCCUPANCY_SENSOR_ENDPOINT_NUMBER); + +void setup() { + Serial.begin(115200); + + // Init button + PIR sensor + pinMode(button, INPUT_PULLUP); + pinMode(sensor_pin, INPUT); + + // Optional: set Zigbee device name and model + zbOccupancySensor.setManufacturerAndModel("Espressif", "ZigbeeOccupancyPIRSensor"); + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbOccupancySensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking PIR sensor for occupancy change + static bool occupancy = false; + if (digitalRead(sensor_pin) == HIGH && !occupancy) { + // Update occupancy sensor value + zbOccupancySensor.setOccupancy(true); + zbOccupancySensor.report(); + occupancy = true; + } else if (digitalRead(sensor_pin) == LOW && occupancy) { + zbOccupancySensor.setOccupancy(false); + zbOccupancySensor.report(); + occupancy = false; + } + + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md b/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md new file mode 100644 index 0000000..e74c750 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md @@ -0,0 +1,70 @@ +# Arduino-ESP32 Zigbee On/Off Light Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) on/off light. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with Zigbee_On_Off_switch example) +* A USB cable for power supply and programming +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_On_Off_Light example + +### Configure the Project + +Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`. +By default, the `rgbLedWrite` function is used to control the LED. You can change it to digitalWrite to control a simple LED. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino b/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino new file mode 100644 index 0000000..6db8bd7 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino @@ -0,0 +1,101 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee light bulb. + * + * The example demonstrates how to use Zigbee library to create a end device light bulb. + * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee light bulb configuration */ +#define ZIGBEE_LIGHT_ENDPOINT 10 +uint8_t led = RGB_BUILTIN; +uint8_t button = BOOT_PIN; + +ZigbeeLight zbLight = ZigbeeLight(ZIGBEE_LIGHT_ENDPOINT); + +/********************* RGB LED functions **************************/ +void setLED(bool value) { + digitalWrite(led, value); +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood) + pinMode(led, OUTPUT); + digitalWrite(led, LOW); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + //Optional: set Zigbee device name and model + zbLight.setManufacturerAndModel("Espressif", "ZBLightBulb"); + + // Set callback function for light change + zbLight.onLightChange(setLED); + + //Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeLight endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbLight); + + // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // Toggle light by pressing the button + zbLight.setLight(!zbLight.getLightState()); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.yml b/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/README.md b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/README.md new file mode 100644 index 0000000..7ec806a --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/README.md @@ -0,0 +1,110 @@ +# Arduino-ESP32 Zigbee Multi-Switch Example + +This example demonstrates how to configure a Zigbee device as a multi-switch controller that can control up to three different Zigbee lights independently. The switch can operate in either coordinator or router mode, making it compatible with Home Assistant integration. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee multi-switch controller +* One or more Zigbee light devices (loaded with Zigbee_On_Off_Light example) +* A USB cable for power supply and programming + +### Configure the Project + +The example uses the BOOT button (pin 9) on ESP32-C6 and ESP32-H2 as the physical switch input. The switch can be configured to operate in two modes: + +1. **Coordinator Mode**: For running your own Zigbee network +2. **Router Mode**: For Home Assistant integration + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board` +* Select the Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose` + +## Features + +The multi-switch example provides the following functionality: + +1. **Light Configuration** + - Configure up to 3 different lights using their endpoint and IEEE address + - Configuration is stored in NVS (Non-Volatile Storage) and persists after power loss + - Remove configured lights when needed + +2. **Control Commands** + - Control all bound lights simultaneously: + - Turn all bound lights ON + - Turn all bound lights OFF + - Toggle all bound lights + - Control individual lights (1-3): + - Turn light ON + - Turn light OFF + - Toggle light + +3. **Network Management** + - Factory reset capability + - Open network for device joining + - View bound devices and current light configurations + +## Serial Commands + +The example accepts the following commands through the serial interface: + +* `config` - Configure a new light (requires light number, endpoint, and IEEE address) +* `remove` - Remove a configured light +* `on` - Turn all bound lights ON +* `off` - Turn all bound lights OFF +* `toggle` - Toggle all bound lights +* `1on`, `2on`, `3on` - Turn individual light ON +* `1off`, `2off`, `3off` - Turn individual light OFF +* `1toggle`, `2toggle`, `3toggle` - Toggle individual light +* `freset` - Perform factory reset +* `open_network` - Open network for device joining (only for coordinator role) + +## Troubleshooting + +If the End device flashed with the example `Zigbee_On_Off_Light` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled` +* In the `Zigbee_On_Off_Light` example sketch call `Zigbee.factoryReset()` + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time)` before calling `Zigbee.begin()` +* In application you can anytime call `Zigbee.openNetwork(time)` to open the network for devices to join + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/Zigbee_On_Off_MultiSwitch.ino b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/Zigbee_On_Off_MultiSwitch.ino new file mode 100644 index 0000000..63e342b --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/Zigbee_On_Off_MultiSwitch.ino @@ -0,0 +1,274 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee multi-light switch. + * + * The example demonstrates how to use Zigbee library to control multiple light bulbs. + * The light bulbs are Zigbee devices, which are controlled by a Zigbee coordinator/router (Multi-Switch). + * Settings are stored in NVS to not be lost after power loss. + * Configuring and controlling the lights is done via serial input. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" +#include + +#define ZIGBEE_ROLE ZIGBEE_ROUTER // ZIGBEE_ROUTER for HomeAssistant integration, ZIGBEE_COORDINATOR for running own network + +/* Zigbee switch configuration */ +#define SWITCH_ENDPOINT_NUMBER 1 + +uint8_t button = BOOT_PIN; + +ZigbeeSwitch zbSwitch = ZigbeeSwitch(SWITCH_ENDPOINT_NUMBER); + +int buttonState; +int lastButtonState = LOW; +unsigned long lastDebounceTime = 0; // the last time the output pin was toggled +unsigned long debounceDelay = 50; // the debounce time; increase if the output flickers + +// To be stored in NVS to not be lost after power loss +Preferences prefs; + +zb_device_params_t light_1; +zb_device_params_t light_2; +zb_device_params_t light_3; + +void storeLightParams(zb_device_params_t *light, int light_number) { + char key[10]; + snprintf(key, sizeof(key), "light_%d", light_number); + prefs.putBytes(key, light, sizeof(zb_device_params_t)); +} + +void loadLightParams(zb_device_params_t *light, int light_number) { + char key[10]; + snprintf(key, sizeof(key), "light_%d", light_number); + prefs.getBytes(key, light, sizeof(zb_device_params_t)); +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Initialize Preferences + prefs.begin("lights", false); // false means read/write mode + + // Load saved light parameters + loadLightParams(&light_1, 1); + loadLightParams(&light_2, 2); + loadLightParams(&light_3, 3); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Set Zigbee device name and model + zbSwitch.setManufacturerAndModel("Espressif", "ZBMultiSwitch"); + + // Set binding settings depending on the role + if (ZIGBEE_ROLE == ZIGBEE_COORDINATOR) { + zbSwitch.allowMultipleBinding(true); // To allow binding multiple lights to the switch + } else { + zbSwitch.setManualBinding(true); //Set manual binding to true, so binding is done on Home Assistant side + } + + // Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeSwitch endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbSwitch); + + // When all EPs are registered, start Zigbee with given role + if (!Zigbee.begin(ZIGBEE_ROLE)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Handle button switch in loop() + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + while (digitalRead(button) == LOW) { + delay(50); + } + // Print bound devices + Serial.println("Bound devices:"); + zbSwitch.printBoundDevices(Serial); + Serial.println("Lights configured:"); + Serial.printf("Light 1: %d %s\n", light_1.endpoint, Zigbee.formatIEEEAddress(light_1.ieee_addr)); + Serial.printf("Light 2: %d %s\n", light_2.endpoint, Zigbee.formatIEEEAddress(light_2.ieee_addr)); + Serial.printf("Light 3: %d %s\n", light_3.endpoint, Zigbee.formatIEEEAddress(light_3.ieee_addr)); + } + // Handle serial input to configure and control the lights + if (Serial.available()) { + String command = Serial.readString(); + Serial.println("Command: " + command); + + if (command == "config") { + //wait for light number, endpoint and ieee address + Serial.println("Enter light number (1-3):"); + while (!Serial.available()) { + delay(100); + } + int light_number = Serial.parseInt(); + Serial.println("Enter endpoint:"); + while (!Serial.available()) { + delay(100); + } + int endpoint = Serial.parseInt(); + Serial.println("Enter ieee address:"); + while (!Serial.available()) { + delay(100); + } + String ieee_address = Serial.readStringUntil('\n'); + ieee_address.trim(); + //convert ieee address to uint8_t array (format in string is 00:00:00:00:00:00:00:00) + uint8_t ieee_address_array[8]; + int index = 0; + bool valid = true; + + // Check if the string has the correct format (8 hex pairs with colons) + if (ieee_address.length() != 23) { // 8 pairs * 2 + 7 colons + Serial.println("Invalid IEEE address format. Expected format: 00:00:00:00:00:00:00:00"); + valid = false; + } else { + for (int i = 0; i < ieee_address.length() && index < 8 && valid; i += 3) { + // Check for colon at expected positions + if (i > 0 && ieee_address.charAt(i - 1) != ':') { + valid = false; + break; + } + // Convert two hex characters to a byte + char hex[3] = {ieee_address.charAt(i), ieee_address.charAt(i + 1), '\0'}; + char *endptr; + long value = strtol(hex, &endptr, 16); + if (*endptr != '\0' || value < 0 || value > 255) { + valid = false; + break; + } + // Store bytes in reverse order to match Zigbee standard + ieee_address_array[7 - index++] = (uint8_t)value; + } + } + + if (!valid || index != 8) { + Serial.println("Invalid IEEE address. Please enter a valid address in format: 00:00:00:00:00:00:00:00"); + return; + } + //set the light parameters + if (light_number == 1) { + light_1.endpoint = endpoint; + memcpy(light_1.ieee_addr, ieee_address_array, 8); + storeLightParams(&light_1, 1); + } else if (light_number == 2) { + light_2.endpoint = endpoint; + memcpy(light_2.ieee_addr, ieee_address_array, 8); + storeLightParams(&light_2, 2); + } else if (light_number == 3) { + light_3.endpoint = endpoint; + memcpy(light_3.ieee_addr, ieee_address_array, 8); + storeLightParams(&light_3, 3); + } + Serial.printf("Light %d configured\n", light_number); + } else if (command == "remove") { + //wait for light number + Serial.println("Enter light number (1-3):"); + while (!Serial.available()) { + delay(100); + } + int light_number = Serial.parseInt(); + uint8_t ieee_address_empty[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + if (light_number == 1) { + light_1.endpoint = 0; + memcpy(light_1.ieee_addr, ieee_address_empty, 8); + storeLightParams(&light_1, 1); + } else if (light_number == 2) { + light_2.endpoint = 0; + memcpy(light_2.ieee_addr, ieee_address_empty, 8); + storeLightParams(&light_2, 2); + } else if (light_number == 3) { + light_3.endpoint = 0; + memcpy(light_3.ieee_addr, ieee_address_empty, 8); + storeLightParams(&light_3, 3); + } + Serial.printf("Light %d removed\n", light_number); + } else if (command == "on") { + Serial.println(" --> SIG Input : All Lights ON"); + zbSwitch.lightOn(); + } else if (command == "off") { + Serial.println(" --> SIG Input : All Lights OFF"); + zbSwitch.lightOff(); + } else if (command == "toggle") { + Serial.println(" --> SIG Input : All Lights Toggle"); + zbSwitch.lightToggle(); + } else if (command == "1on") { + Serial.println(" --> SIG Input : Light 1 ON"); + zbSwitch.lightOn(light_1.endpoint, light_1.ieee_addr); + } else if (command == "1off") { + Serial.println(" --> SIG Input : Light 1 OFF"); + zbSwitch.lightOff(light_1.endpoint, light_1.ieee_addr); + } else if (command == "1toggle") { + Serial.println(" --> SIG Input : Light 1 Toggle"); + zbSwitch.lightToggle(light_1.endpoint, light_1.ieee_addr); + } else if (command == "2on") { + Serial.println(" --> SIG Input : Light 2 ON"); + zbSwitch.lightOn(light_2.endpoint, light_2.ieee_addr); + } else if (command == "2off") { + Serial.println(" --> SIG Input : Light 2 OFF"); + zbSwitch.lightOff(light_2.endpoint, light_2.ieee_addr); + } else if (command == "2toggle") { + Serial.println(" --> SIG Input : Light 2 Toggle"); + zbSwitch.lightToggle(light_2.endpoint, light_2.ieee_addr); + } else if (command == "3on") { + Serial.println(" --> SIG Input : Light 3 ON"); + zbSwitch.lightOn(light_3.endpoint, light_3.ieee_addr); + } else if (command == "3off") { + Serial.println(" --> SIG Input : Light 3 OFF"); + zbSwitch.lightOff(light_3.endpoint, light_3.ieee_addr); + } else if (command == "3toggle") { + Serial.println(" --> SIG Input : Light 3 Toggle"); + zbSwitch.lightToggle(light_3.endpoint, light_3.ieee_addr); + } else if (command == "freset") { + Serial.println(" --> SIG Input : Factory Reset!"); + delay(1500); + Zigbee.factoryReset(); + } else if (command == "open_network") { + Serial.println(" --> SIG Input : Open Network"); + if (ZIGBEE_ROLE == ZIGBEE_COORDINATOR) { + Zigbee.openNetwork(180); + } else { + Serial.println("Open network is only available for coordinator role"); + } + } else { + Serial.println("Unknown command"); + } + } +} diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/ci.yml b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_MultiSwitch/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md new file mode 100644 index 0000000..b70f57d --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee On/Off Light Switch Example + +This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) on/off light switch. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_On_Off_Light example). +* A USB cable for power supply and programming. +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator and upload the Zigbee_On_Off_Switch example. + +### Configure the Project + +Set the Button Switch GPIO by changing the `GPIO_INPUT_IO_TOGGLE_SWITCH` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`. +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`. +* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with the example `Zigbee_On_Off_Light` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* In the `Zigbee_On_Off_Light` example sketch call `Zigbee.factoryReset();`. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino new file mode 100644 index 0000000..d4a71bb --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino @@ -0,0 +1,224 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee light switch. + * + * The example demonstrates how to use Zigbee library to control a light bulb. + * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator (Switch). + * Button switch and Zigbee runs in separate tasks. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee switch configuration */ +#define SWITCH_ENDPOINT_NUMBER 5 + +#define GPIO_INPUT_IO_TOGGLE_SWITCH BOOT_PIN +#define PAIR_SIZE(TYPE_STR_PAIR) (sizeof(TYPE_STR_PAIR) / sizeof(TYPE_STR_PAIR[0])) + +typedef enum { + SWITCH_ON_CONTROL, + SWITCH_OFF_CONTROL, + SWITCH_ONOFF_TOGGLE_CONTROL, + SWITCH_LEVEL_UP_CONTROL, + SWITCH_LEVEL_DOWN_CONTROL, + SWITCH_LEVEL_CYCLE_CONTROL, + SWITCH_COLOR_CONTROL, +} SwitchFunction; + +typedef struct { + uint8_t pin; + SwitchFunction func; +} SwitchData; + +typedef enum { + SWITCH_IDLE, + SWITCH_PRESS_ARMED, + SWITCH_PRESS_DETECTED, + SWITCH_PRESSED, + SWITCH_RELEASE_DETECTED, +} SwitchState; + +static SwitchData buttonFunctionPair[] = {{GPIO_INPUT_IO_TOGGLE_SWITCH, SWITCH_ONOFF_TOGGLE_CONTROL}}; + +ZigbeeSwitch zbSwitch = ZigbeeSwitch(SWITCH_ENDPOINT_NUMBER); + +static bool light_state = false; + +/********************* Zigbee functions **************************/ +static void onZbButton(SwitchData *button_func_pair) { + if (button_func_pair->func == SWITCH_ONOFF_TOGGLE_CONTROL) { + // Send toggle command to the light + Serial.println("Toggling light"); + zbSwitch.lightToggle(); + } +} + +static void onLightStateChange(bool state) { + if (state != light_state) { + light_state = state; + Serial.printf("Light state changed to %d\r\n", state); + } +} + +/********************* Periodic task ***************************/ +void periodicTask(void *arg) { + while (true) { + // print the bound lights every 10 seconds + static uint32_t lastPrint = 0; + if (millis() - lastPrint > 10000) { + lastPrint = millis(); + zbSwitch.printBoundDevices(Serial); + } + + // Poll light state every second + static uint32_t lastPoll = 0; + if (millis() - lastPoll > 1000) { + lastPoll = millis(); + zbSwitch.getLightState(); + } + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +} + +/********************* GPIO functions **************************/ +static QueueHandle_t gpio_evt_queue = NULL; + +static void IRAM_ATTR onGpioInterrupt(void *arg) { + xQueueSendFromISR(gpio_evt_queue, (SwitchData *)arg, NULL); +} + +static void enableGpioInterrupt(bool enabled) { + for (int i = 0; i < PAIR_SIZE(buttonFunctionPair); ++i) { + if (enabled) { + enableInterrupt((buttonFunctionPair[i]).pin); + } else { + disableInterrupt((buttonFunctionPair[i]).pin); + } + } +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + //Optional: set Zigbee device name and model + zbSwitch.setManufacturerAndModel("Espressif", "ZigbeeSwitch"); + + //Optional to allow multiple light to bind to the switch + zbSwitch.allowMultipleBinding(true); + + zbSwitch.onLightStateChange(onLightStateChange); + + //Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeSwitch endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbSwitch); + + //Open network for 180 seconds after boot + Zigbee.setRebootOpenNetwork(180); + + // Init button switch + for (int i = 0; i < PAIR_SIZE(buttonFunctionPair); i++) { + pinMode(buttonFunctionPair[i].pin, INPUT_PULLUP); + /* create a queue to handle gpio event from isr */ + gpio_evt_queue = xQueueCreate(10, sizeof(SwitchData)); + if (gpio_evt_queue == 0) { + Serial.println("Queue creating failed, rebooting..."); + ESP.restart(); + } + attachInterruptArg(buttonFunctionPair[i].pin, onGpioInterrupt, (void *)(buttonFunctionPair + i), FALLING); + } + + // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode + if (!Zigbee.begin(ZIGBEE_COORDINATOR)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + Serial.println("Waiting for Light to bound to the switch"); + //Wait for switch to bound to a light: + while (!zbSwitch.bound()) { + Serial.printf("."); + delay(500); + } + + // Optional: List all bound devices and read manufacturer and model name + std::list boundLights = zbSwitch.getBoundDevices(); + for (const auto &device : boundLights) { + Serial.printf("Device on endpoint %d, short address: 0x%x\r\n", device->endpoint, device->short_addr); + Serial.printf( + "IEEE Address: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\r\n", device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], + device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1], device->ieee_addr[0] + ); + char *manufacturer = zbSwitch.readManufacturer(device->endpoint, device->short_addr, device->ieee_addr); + char *model = zbSwitch.readModel(device->endpoint, device->short_addr, device->ieee_addr); + if (manufacturer != nullptr) { + Serial.printf("Light manufacturer: %s\r\n", manufacturer); + } + if (model != nullptr) { + Serial.printf("Light model: %s\r\n", model); + } + } + + Serial.println(); + + xTaskCreate(periodicTask, "periodicTask", 1024 * 4, NULL, 10, NULL); +} + +void loop() { + // Handle button switch in loop() + uint8_t pin = 0; + SwitchData buttonSwitch; + static SwitchState buttonState = SWITCH_IDLE; + bool eventFlag = false; + + /* check if there is any queue received, if yes read out the buttonSwitch */ + if (xQueueReceive(gpio_evt_queue, &buttonSwitch, portMAX_DELAY)) { + pin = buttonSwitch.pin; + enableGpioInterrupt(false); + eventFlag = true; + } + while (eventFlag) { + bool value = digitalRead(pin); + switch (buttonState) { + case SWITCH_IDLE: buttonState = (value == LOW) ? SWITCH_PRESS_DETECTED : SWITCH_IDLE; break; + case SWITCH_PRESS_DETECTED: buttonState = (value == LOW) ? SWITCH_PRESS_DETECTED : SWITCH_RELEASE_DETECTED; break; + case SWITCH_RELEASE_DETECTED: + buttonState = SWITCH_IDLE; + /* callback to button_handler */ + (*onZbButton)(&buttonSwitch); + break; + default: break; + } + if (buttonState == SWITCH_IDLE) { + enableGpioInterrupt(true); + eventFlag = false; + break; + } + vTaskDelay(10 / portTICK_PERIOD_MS); + } +} diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.yml b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md new file mode 100644 index 0000000..51bf114 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md @@ -0,0 +1,72 @@ +# Arduino-ESP32 PM2.5 Sensor + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with particulate matter (PM2.5) measuring + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Pressure + Flow Sensor Functions + + * After this board first starts up, it would be configured locally to report the PM2.5 on every 30 seconds. + * By clicking the button (BOOT) on this board, this board will immediately send a report of the current PM2.5 to the network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +In this example, the internal temperature sensor is used to demonstrate reading of the PM2.5 sensors. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino new file mode 100644 index 0000000..a98d697 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino @@ -0,0 +1,109 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee PM2.5 sensor. + * + * The example demonstrates how to use Zigbee library to create a end device PM2.5 sensor. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee PM2.5 sensor configuration */ +#define PM2_5_SENSOR_ENDPOINT_NUMBER 1 +uint8_t button = BOOT_PIN; + +ZigbeePM25Sensor zbPM25Sensor = ZigbeePM25Sensor(PM2_5_SENSOR_ENDPOINT_NUMBER); + +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbPM25Sensor.setManufacturerAndModel("Espressif", "ZigbeePM25Sensor"); + + // Set minimum and maximum PM2.5 measurement value in µg/m³ + zbPM25Sensor.setMinMaxValue(0, 350); + + // Set tolerance for PM2.5 measurement in µg/m³ + zbPM25Sensor.setTolerance(0.1); + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbPM25Sensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Set reporting interval for PM2.5 measurement to be done every 30 seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta (PM2.5 change in µg/m³) + // if min = 1 and max = 0, reporting is sent only when PM2.5 changes by delta + // if min = 0 and max = 10, reporting is sent every 10 seconds or when PM2.5 changes by delta + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change + zbPM25Sensor.setReporting(0, 30, 0); +} + +void loop() { + static uint32_t timeCounter = 0; + // Read PM2.5 sensor every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + // Read sensor value - here is chip temperature used + 50 as a dummy value for demonstration + float pm25_value = 50.5 + temperatureRead(); + Serial.printf("Updating PM2.5 sensor value to %0.1f µg/m³\r\n", pm25_value); + zbPM25Sensor.setPM25(pm25_value); + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + zbPM25Sensor.report(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Power_Outlet/README.md b/libraries/Zigbee/examples/Zigbee_Power_Outlet/README.md new file mode 100644 index 0000000..996aa36 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Power_Outlet/README.md @@ -0,0 +1,61 @@ +@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee On/Off Power Outlet Example + +This example shows how to configure Zigbee Router device and use it as a Home Automation (HA) on/off power outlet. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming. + +### Configure the Project + +Set the Button GPIO by changing the `button` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`. +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee ZCZR 4MB with spiffs`. +* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the device flashed with the example `Zigbee_Power_Outlet` is not connecting to the coordinator, erase the flash of the device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator or do some big changes in the application code. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* In the `Zigbee_Power_Outlet` example sketch call `Zigbee.factoryReset();`. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Power_Outlet/Zigbee_Power_Outlet.ino b/libraries/Zigbee/examples/Zigbee_Power_Outlet/Zigbee_Power_Outlet.ino new file mode 100644 index 0000000..ba1474d --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Power_Outlet/Zigbee_Power_Outlet.ino @@ -0,0 +1,107 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee power outlet. + * + * The example demonstrates how to use Zigbee library to create a end device power outlet. + * The power outlet is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Ludovic Boué (https://github.com/lboue) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee router mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee power outlet configuration */ +#define ZIGBEE_OUTLET_ENDPOINT 1 + +#ifdef LED_BUILTIN // Use built-in LED if defined for the board +uint8_t led = LED_BUILTIN; +#else +uint8_t led = 2; // Use custom LED pin +#endif + +uint8_t button = BOOT_PIN; + +ZigbeePowerOutlet zbOutlet = ZigbeePowerOutlet(ZIGBEE_OUTLET_ENDPOINT); + +/********************* RGB LED functions **************************/ +void setLED(bool value) { + digitalWrite(led, value); +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood) + pinMode(led, OUTPUT); + digitalWrite(led, LOW); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + //Optional: set Zigbee device name and model + zbOutlet.setManufacturerAndModel("Espressif", "ZBPowerOutlet"); + + // Set callback function for power outlet change + zbOutlet.onPowerOutletChange(setLED); + + //Add endpoint to Zigbee Core + Serial.println("Adding ZigbeePowerOutlet endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbOutlet); + + // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE + if (!Zigbee.begin(ZIGBEE_ROUTER)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + // Toggle state by pressing the button + zbOutlet.setState(!zbOutlet.getPowerOutletState()); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Power_Outlet/ci.yml b/libraries/Zigbee/examples/Zigbee_Power_Outlet/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Power_Outlet/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md new file mode 100644 index 0000000..964c750 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md @@ -0,0 +1,72 @@ +# Arduino-ESP32 Zigbee Pressure + Flow Sensor Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with pressure and flow measuring. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Pressure + Flow Sensor Functions + + * After this board first starts up, it would be configured locally to report the pressure and flow on change or every 30 seconds. + * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured flow and pressure to the network. + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +In this example, the internal temperature sensor is used to demonstrate reading of the flow and pressure sensors. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino new file mode 100644 index 0000000..a652a22 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino @@ -0,0 +1,128 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee temperature sensor. + * + * The example demonstrates how to use Zigbee library to create a end device temperature sensor. + * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee flow + pressure sensor configuration */ +#define FLOW_SENSOR_ENDPOINT_NUMBER 10 +#define PRESSURE_SENSOR_ENDPOINT_NUMBER 11 + +uint8_t button = BOOT_PIN; + +ZigbeeFlowSensor zbFlowSensor = ZigbeeFlowSensor(FLOW_SENSOR_ENDPOINT_NUMBER); +ZigbeePressureSensor zbPressureSensor = ZigbeePressureSensor(PRESSURE_SENSOR_ENDPOINT_NUMBER); + +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbFlowSensor.setManufacturerAndModel("Espressif", "ZigbeeFlowSensor"); + + // Set minimum and maximum flow measurement value in 0,1 m3/h + zbFlowSensor.setMinMaxValue(0.0, 100.0); + + // Optional: Set tolerance for flow measurement in 0,1 m3/h + zbFlowSensor.setTolerance(1.0); + + // Optional: set Zigbee device name and model + zbPressureSensor.setManufacturerAndModel("Espressif", "ZigbeePressureSensor"); + + // Set minimum and maximum pressure measurement value in hPa + zbPressureSensor.setMinMaxValue(0, 10000); + + // Optional: Set tolerance for pressure measurement in hPa + zbPressureSensor.setTolerance(1); + + // Add endpoints to Zigbee Core + Zigbee.addEndpoint(&zbFlowSensor); + Zigbee.addEndpoint(&zbPressureSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Set reporting interval for flow and pressure measurement in seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta (pressure change in hPa, flow change in 0,1 m3/h) + // if min = 1 and max = 0, reporting is sent only when temperature changes by delta + // if min = 0 and max = 10, reporting is sent every 10 seconds or temperature changes by delta + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change + zbFlowSensor.setReporting(0, 30, 1.0); + zbPressureSensor.setReporting(0, 30, 1); +} + +void loop() { + static uint32_t timeCounter = 0; + + // Read flow and pressure sensors every 2s + if (!(timeCounter++ % 20)) { // delaying for 100ms x 20 = 2s + float flow_value = temperatureRead(); + uint16_t pressure_value = (uint16_t)temperatureRead() * 100; //*100 for demonstration so the value is in 1000-3000hPa + Serial.printf("Updating flow sensor value to %.2f m3/h\r\n", flow_value); + zbFlowSensor.setFlow(flow_value); + Serial.printf("Updating pressure sensor value to %d hPa\r\n", pressure_value); + zbPressureSensor.setPressure(pressure_value); + } + + // Checking button for factory reset and reporting + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + zbFlowSensor.report(); + zbPressureSensor.report(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md b/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md new file mode 100644 index 0000000..198dd85 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md @@ -0,0 +1,68 @@ +# Arduino-ESP32 Zigbee Range Extender (Router) Example + +This example shows how to configure the Zigbee Router device and use it as a Home Automation (HA) network range extender. + +To see if the communication with your Zigbee network works, use the Serial monitor and watch for output there. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming +* Board (ESP32-H2 or ESP32-C6) as Zigbee router device and upload the Zigbee_Range_Extender example +* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application) + +### Configure the Project + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator/Router device Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` (select correct size) +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the Router device flashed with this example is not connecting to the coordinator, erase the flash of the Router device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino b/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino new file mode 100644 index 0000000..a1ba90f --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino @@ -0,0 +1,120 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee Range Extender (router). + * + * The example demonstrates how to use Zigbee library to create a Zigbee network ragbe extender (router). + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator/router mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee light bulb configuration */ +#define USE_CUSTOM_ZIGBEE_CONFIG 1 +#define ZIGBEE_EXTENDER_ENDPOINT 1 + +#ifndef LED_BUILTIN +#define LED_BUILTIN 4 +#endif + +uint8_t led = LED_BUILTIN; +uint8_t button = BOOT_PIN; + +ZigbeeRangeExtender zbExtender = ZigbeeRangeExtender(ZIGBEE_EXTENDER_ENDPOINT); + +/************************** Identify ******************************/ +// Create a task on identify call to handle the identify function +void identify(uint16_t time) { + static uint8_t blink = 1; + log_d("Identify called for %d seconds", time); + if (time == 0) { + digitalWrite(led, LOW); + return; + } + digitalWrite(led, blink); + blink = !blink; +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood) + pinMode(led, OUTPUT); + digitalWrite(led, LOW); + + // Init button for factory reset + pinMode(button, INPUT_PULLUP); + + // Optional: Set callback function for device identify + zbExtender.onIdentify(identify); + + // Optional: Set Zigbee device name and model + zbExtender.setManufacturerAndModel("Espressif", "ZigbeeRangeExtender"); + + // Add endpoint to Zigbee Core + Serial.println("Adding Zigbee Extender endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbExtender); + +#if USE_CUSTOM_ZIGBEE_CONFIG + // Optional: Create a custom Zigbee configuration for Zigbee Extender + esp_zb_cfg_t zigbeeConfig = ZIGBEE_DEFAULT_ROUTER_CONFIG(); + zigbeeConfig.nwk_cfg.zczr_cfg.max_children = 20; // 10 is default + + // When all EPs are registered, start Zigbee with custom config + if (!Zigbee.begin(&zigbeeConfig)) { +#else + // When all EPs are registered, start Zigbee as ROUTER device + if (!Zigbee.begin(ZIGBEE_ROUTER)) { +#endif + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + } +} diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.yml b/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md b/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md new file mode 100644 index 0000000..0b2b2f9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md @@ -0,0 +1,71 @@ +# Arduino-ESP32 Zigbee Networks Scan Example + +This example shows how to scan Zigbee Networks. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Example Output + + Setup done + Loop running... + Loop running... + Loop running... + Loop running... + + Scan done + 2 networks found: + Nr | PAN ID | CH | Permit Joining | Router Capacity | End Device Capacity | Extended PAN ID + 1 | 0xe6f0 | 14 | Yes | Yes | Yes | f0:f5:bd:ff:fe:02:3f:24 + 2 | 0xa9bb | 24 | No | Yes | Yes | 60:55:f9:00:00:f7:52:d0 + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with `Zigbee_Thermostat` example) +* A USB cable for power supply and programming +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device (loaded with `Zigbee_Temperature_Sensor` example) + +### Configure the Project + +In this example, the internal temperature sensor task is reading the chip temperature. +Set the Button Switch GPIO by changing the `GPIO_INPUT_IO_TOGGLE_SWITCH` definition. By default, it's the `GPIO_NUM_9` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino b/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino new file mode 100644 index 0000000..eab6ecf --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino @@ -0,0 +1,109 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee Network Scanning. + * + * The example demonstrates how to use ESP Zigbee stack to scan for Zigbee networks. + * + * Any Zigbee mode can be selected in Tools->Zigbee mode + * with proper Zigbee partition scheme in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#if !defined(ZIGBEE_MODE_ED) && !defined(ZIGBEE_MODE_ZCZR) +#error "Zigbee device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +#ifdef ZIGBEE_MODE_ZCZR +zigbee_role_t role = ZIGBEE_ROUTER; // or can be ZIGBEE_COORDINATOR, but it won't scan itself +#else +zigbee_role_t role = ZIGBEE_END_DEVICE; +#endif + +void printScannedNetworks(uint16_t networksFound) { + if (networksFound == 0) { + Serial.println("No networks found"); + } else { + zigbee_scan_result_t *scan_result = Zigbee.getScanResult(); + Serial.println("\nScan done"); + Serial.print(networksFound); + Serial.println(" networks found:"); + Serial.println("Nr | PAN ID | CH | Permit Joining | Router Capacity | End Device Capacity | Extended PAN ID"); + for (int i = 0; i < networksFound; ++i) { + // Print all available info for each network found + Serial.printf("%2d", i + 1); + Serial.print(" | "); + Serial.printf("0x%04hx", scan_result[i].short_pan_id); + Serial.print(" | "); + Serial.printf("%2d", scan_result[i].logic_channel); + Serial.print(" | "); + Serial.printf("%-14.14s", scan_result[i].permit_joining ? "Yes" : "No"); + Serial.print(" | "); + Serial.printf("%-15.15s", scan_result[i].router_capacity ? "Yes" : "No"); + Serial.print(" | "); + Serial.printf("%-19.19s", scan_result[i].end_device_capacity ? "Yes" : "No"); + Serial.print(" | "); + Serial.printf( + "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", scan_result[i].extended_pan_id[7], scan_result[i].extended_pan_id[6], scan_result[i].extended_pan_id[5], + scan_result[i].extended_pan_id[4], scan_result[i].extended_pan_id[3], scan_result[i].extended_pan_id[2], scan_result[i].extended_pan_id[1], + scan_result[i].extended_pan_id[0] + ); + Serial.println(); + delay(10); + } + Serial.println(""); + // Delete the scan result to free memory for code below. + Zigbee.scanDelete(); + } +} + +void setup() { + Serial.begin(115200); + + // Initialize Zigbee stack without any EPs just for scanning + if (!Zigbee.begin(role)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + Serial.println("Setup done, starting Zigbee network scan..."); + // Start Zigbee Network Scan with default parameters (all channels, scan time 5) + Zigbee.scanNetworks(); +} + +void loop() { + // check Zigbee Network Scan process + int16_t ZigbeeScanStatus = Zigbee.scanComplete(); + if (ZigbeeScanStatus < 0) { // it is busy scanning or got an error + if (ZigbeeScanStatus == ZB_SCAN_FAILED) { + Serial.println("Zigbee scan has failed. Starting again."); + Zigbee.scanNetworks(); + } + // other option is status ZB_SCAN_RUNNING - just wait. + } else { // Found Zero or more Wireless Networks + printScannedNetworks(ZigbeeScanStatus); + Zigbee.scanNetworks(); // start over... + } + + // Loop can do something else... + delay(500); + Serial.println("Loop running..."); +} diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.yml b/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md new file mode 100644 index 0000000..afaa12c --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md @@ -0,0 +1,75 @@ +# Arduino-ESP32 Zigbee Temperature and Humidity Sensor Sleepy Device Example + +This example demonstrates how to use the Zigbee library to create an end device temperature/humidity sensor and use it as a Home Automation (HA) extended temperature sensor. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Temperature Sensor Functions + +1. Initialize a Zigbee temperature and humidity sensor. +2. Measure temperature and humidity values. +3. Report the measured values to the Zigbee network. +4. Put the device to sleep to save power. + +## Hardware Required + +* ESP32-H2 or ESP32-C6 development board +* A USB cable for power supply and programming + +### Configure the Project + +In this example, to demonstrate the functionality the chip temperature is used and reported as temperature and humidity. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino new file mode 100644 index 0000000..401c4ab --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino @@ -0,0 +1,211 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee temperature and humidity sensor Sleepy device. + * + * The example demonstrates how to use Zigbee library to create an end device temperature and humidity sensor. + * The sensor is a Zigbee end device, which is reporting data to the Zigbee network. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +#define USE_GLOBAL_ON_RESPONSE_CALLBACK 1 // Set to 0 to use local callback specified directly for the endpoint. + +/* Zigbee temperature + humidity sensor configuration */ +#define TEMP_SENSOR_ENDPOINT_NUMBER 10 + +#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */ +#define TIME_TO_SLEEP 55 /* Sleep for 55s will + 5s delay for establishing connection => data reported every 1 minute */ +#define REPORT_TIMEOUT 1000 /* Timeout for response from coordinator in ms */ + +uint8_t button = BOOT_PIN; + +ZigbeeTempSensor zbTempSensor = ZigbeeTempSensor(TEMP_SENSOR_ENDPOINT_NUMBER); + +uint8_t dataToSend = 2; // Temperature and humidity values are reported in same endpoint, so 2 values are reported +bool resend = false; + +/************************ Callbacks *****************************/ +#if USE_GLOBAL_ON_RESPONSE_CALLBACK +void onGlobalResponse(zb_cmd_type_t command, esp_zb_zcl_status_t status, uint8_t endpoint, uint16_t cluster) { + Serial.printf("Global response command: %d, status: %s, endpoint: %d, cluster: 0x%04x\r\n", command, esp_zb_zcl_status_to_name(status), endpoint, cluster); + if ((command == ZB_CMD_REPORT_ATTRIBUTE) && (endpoint == TEMP_SENSOR_ENDPOINT_NUMBER)) { + switch (status) { + case ESP_ZB_ZCL_STATUS_SUCCESS: dataToSend--; break; + case ESP_ZB_ZCL_STATUS_FAIL: resend = true; break; + default: break; // add more statuses like ESP_ZB_ZCL_STATUS_INVALID_VALUE, ESP_ZB_ZCL_STATUS_TIMEOUT etc. + } + } +} +#else +void onResponse(zb_cmd_type_t command, esp_zb_zcl_status_t status) { + Serial.printf("Response command: %d, status: %s\r\n", command, esp_zb_zcl_status_to_name(status)); + if (command == ZB_CMD_REPORT_ATTRIBUTE) { + switch (status) { + case ESP_ZB_ZCL_STATUS_SUCCESS: dataToSend--; break; + case ESP_ZB_ZCL_STATUS_FAIL: resend = true; break; + default: break; // add more statuses like ESP_ZB_ZCL_STATUS_INVALID_VALUE, ESP_ZB_ZCL_STATUS_TIMEOUT etc. + } + } +} +#endif + +/************************ Temp sensor *****************************/ +static void meausureAndSleep(void *arg) { + // Measure temperature sensor value + float temperature = temperatureRead(); + + // Use temperature value as humidity value to demonstrate both temperature and humidity + float humidity = temperature; + + // Update temperature and humidity values in Temperature sensor EP + zbTempSensor.setTemperature(temperature); + zbTempSensor.setHumidity(humidity); + + // Report temperature and humidity values + zbTempSensor.report(); // reports temperature and humidity values (if humidity sensor is not added, only temperature is reported) + Serial.printf("Reported temperature: %.2f°C, Humidity: %.2f%%\r\n", temperature, humidity); + + unsigned long startTime = millis(); + const unsigned long timeout = REPORT_TIMEOUT; + + Serial.printf("Waiting for data report to be confirmed \r\n"); + // Wait until data was successfully sent + int tries = 0; + const int maxTries = 3; + while (dataToSend != 0 && tries < maxTries) { + if (resend) { + Serial.println("Resending data on failure!"); + resend = false; + dataToSend = 2; + zbTempSensor.report(); // report again + } + if (millis() - startTime >= timeout) { + Serial.println("\nReport timeout! Report Again"); + dataToSend = 2; + zbTempSensor.report(); // report again + startTime = millis(); + tries++; + } + Serial.printf("."); + delay(50); // 50ms delay to avoid busy-waiting + } + + // Put device to deep sleep after data was sent successfully or timeout + Serial.println("Going to sleep now"); + esp_deep_sleep_start(); +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Configure the wake up source and set to wake up every 5 seconds + esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR); + + // Optional: set Zigbee device name and model + zbTempSensor.setManufacturerAndModel("Espressif", "SleepyZigbeeTempSensor"); + + // Set minimum and maximum temperature measurement value (10-50°C is default range for chip temperature measurement) + zbTempSensor.setMinMaxValue(10, 50); + + // Set default (initial) value for the temperature sensor to 10.0°C to match the minimum temperature measurement value (default value is 0.0°C) + zbTempSensor.setDefaultValue(10.0); + + // Set tolerance for temperature measurement in °C (lowest possible value is 0.01°C) + zbTempSensor.setTolerance(1); + + // Set power source to battery, battery percentage and battery voltage (now 100% and 3.5V for demonstration) + // The value can be also updated by calling zbTempSensor.setBatteryPercentage(percentage) or zbTempSensor.setBatteryVoltage(voltage) anytime after Zigbee.begin() + zbTempSensor.setPowerSource(ZB_POWER_SOURCE_BATTERY, 100, 35); + + // Add humidity cluster to the temperature sensor device with min, max, tolerance and default values + zbTempSensor.addHumiditySensor(0, 100, 1, 0.0); + + // Set callback for default response to handle status of reported data, there are 2 options. + +#if USE_GLOBAL_ON_RESPONSE_CALLBACK + // Global callback for all endpoints with more params to determine the endpoint and cluster in the callback function. + Zigbee.onGlobalDefaultResponse(onGlobalResponse); +#else + // Callback specified for endpoint + zbTempSensor.onDefaultResponse(onResponse); +#endif + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbTempSensor); + + // Create a custom Zigbee configuration for End Device with keep alive 10s to avoid interference with reporting data + esp_zb_cfg_t zigbeeConfig = ZIGBEE_DEFAULT_ED_CONFIG(); + zigbeeConfig.nwk_cfg.zed_cfg.keep_alive = 10000; + + // For battery powered devices, it can be better to set timeout for Zigbee Begin to lower value to save battery + // If the timeout has been reached, the network channel mask will be reset and the device will try to connect again after reset (scanning all channels) + Zigbee.setTimeout(10000); // Set timeout for Zigbee Begin to 10s (default is 30s) + + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin(&zigbeeConfig, false)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); // If Zigbee failed to start, reboot the device and try again + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + Serial.println("Successfully connected to Zigbee network"); + + // Start Temperature sensor reading task + xTaskCreate(meausureAndSleep, "temp_sensor_update", 2048, NULL, 10, NULL); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 10000) { + // If key pressed for more than 10secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + // Optional set reset in factoryReset to false, to not restart device after erasing nvram, but set it to endless sleep manually instead + Zigbee.factoryReset(false); + Serial.println("Going to endless sleep, press RESET button or power off/on the device to wake up"); + esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER); + esp_deep_sleep_start(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.yml b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md new file mode 100644 index 0000000..577bd7c --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md @@ -0,0 +1,79 @@ +# Arduino-ESP32 Zigbee Temperature Sensor Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) temperature sensor. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Temperature Sensor Functions + +Note: + * This board means the board (e.g. ESP32-H2 / C6) loaded with `Zigbee_Temperature_Sensor` example. + * The remote board means the board (e.g. ESP32-H2 / C6) loaded with `Zigbee_Thermostat` example. + +Functions: + * After this board first starts up, it would be configured locally to report the temperature on 1 degree change and no periodic reporting to the remote board. + * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured temperature to the remote board. + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with `Zigbee_Thermostat` example) +* A USB cable for power supply and programming +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the `Zigbee_Temperature_Sensor` example + +### Configure the Project + +In this example, the internal temperature sensor task is reading the chip temperature. +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino new file mode 100644 index 0000000..e7f4721 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino @@ -0,0 +1,141 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee temperature sensor. + * + * The example demonstrates how to use Zigbee library to create a end device temperature sensor. + * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee temperature sensor configuration */ +#define TEMP_SENSOR_ENDPOINT_NUMBER 10 +uint8_t button = BOOT_PIN; + +// Optional Time cluster variables +struct tm timeinfo; +struct tm *localTime; +int32_t timezone; + +ZigbeeTempSensor zbTempSensor = ZigbeeTempSensor(TEMP_SENSOR_ENDPOINT_NUMBER); + +/************************ Temp sensor *****************************/ +static void temp_sensor_value_update(void *arg) { + for (;;) { + // Read temperature sensor value + float tsens_value = temperatureRead(); + Serial.printf("Updated temperature sensor value to %.2f°C\r\n", tsens_value); + // Update temperature value in Temperature sensor EP + zbTempSensor.setTemperature(tsens_value); + delay(1000); + } +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbTempSensor.setManufacturerAndModel("Espressif", "ZigbeeTempSensor"); + + // Set minimum and maximum temperature measurement value (10-50°C is default range for chip temperature measurement) + zbTempSensor.setMinMaxValue(10, 50); + + // Optional: Set default (initial) value for the temperature sensor to 10.0°C to match the minimum temperature measurement value + zbTempSensor.setDefaultValue(10.0); + + // Optional: Set tolerance for temperature measurement in °C (lowest possible value is 0.01°C) + zbTempSensor.setTolerance(1); + + // Optional: Time cluster configuration (default params, as this device will revieve time from coordinator) + zbTempSensor.addTimeCluster(); + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbTempSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Optional: If time cluster is added, time can be read from the coordinator + timeinfo = zbTempSensor.getTime(); + timezone = zbTempSensor.getTimezone(); + + Serial.println("UTC time:"); + Serial.println(&timeinfo, "%A, %B %d %Y %H:%M:%S"); + + time_t local = mktime(&timeinfo) + timezone; + localTime = localtime(&local); + + Serial.println("Local time with timezone:"); + Serial.println(localTime, "%A, %B %d %Y %H:%M:%S"); + + // Start Temperature sensor reading task + xTaskCreate(temp_sensor_value_update, "temp_sensor_update", 2048, NULL, 10, NULL); + + // Set reporting interval for temperature measurement in seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta (temp change in 0,1 °C) + // if min = 1 and max = 0, reporting is sent only when temperature changes by delta + // if min = 0 and max = 10, reporting is sent every 10 seconds or temperature changes by delta + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of temperature change + zbTempSensor.setReporting(1, 0, 1); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + zbTempSensor.reportTemperature(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/README.md b/libraries/Zigbee/examples/Zigbee_Thermostat/README.md new file mode 100644 index 0000000..e61173f --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Thermostat/README.md @@ -0,0 +1,79 @@ +# Arduino-ESP32 Zigbee Thermostat Example + +This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) thermostat. + +**This example is based on ESP-Zigbee-SDK example esp_zigbee_HA_sample/HA_thermostat.** + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Thermostat Functions + +Note: + * This board means the board (e.g. ESP32-H2) loaded with `Zigbee_Thermostat` example. + * The remote board means the board (e.g. ESP32-H2) loaded with `Zigbee_Temperature_Sensor` example. + +Functions: + * By clicking the button (BOOT) on this board, this board will read temperature value, temperature measurement range and temperature tolerance from the remote board. Also, this board will configure the remote board to report the measured temperature value every 10 seconds or every 2 degree changes. + +## Hardware Required + +* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_Temperature_Sensor example). +* A USB cable for power supply and programming. +* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator (loaded with Zigbee_Thermostat example). + +### Configure the Project + +Set the Button GPIO by changing the `BUTTON_PIN` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2). + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`. +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`. +* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with the example `Zigbee_Temperature_Sensor` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* In the `Zigbee_Temperature_Sensor` example sketch call `Zigbee.factoryReset();`. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino b/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino new file mode 100644 index 0000000..73125cb --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino @@ -0,0 +1,168 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates simple Zigbee thermostat. + * + * The example demonstrates how to use Zigbee library to get data from temperature + * sensor end device and act as an thermostat. + * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator (thermostat). + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ZCZR +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +/* Zigbee thermostat configuration */ +#define THERMOSTAT_ENDPOINT_NUMBER 1 +#define USE_RECEIVE_TEMP_WITH_SOURCE 1 +uint8_t button = BOOT_PIN; + +ZigbeeThermostat zbThermostat = ZigbeeThermostat(THERMOSTAT_ENDPOINT_NUMBER); + +// Save temperature sensor data +float sensor_temp; +float sensor_max_temp; +float sensor_min_temp; +float sensor_tolerance; + +struct tm timeinfo = {}; // Time structure for Time cluster + +/****************** Temperature sensor handling *******************/ +#if USE_RECEIVE_TEMP_WITH_SOURCE == 0 +void receiveSensorTemp(float temperature) { + Serial.printf("Temperature sensor value: %.2f°C\n", temperature); + sensor_temp = temperature; +} +#else +void receiveSensorTempWithSource(float temperature, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) { + if (src_address.addr_type == ESP_ZB_ZCL_ADDR_TYPE_SHORT) { + Serial.printf("Temperature sensor value: %.2f°C from endpoint %d, address 0x%04x\n", temperature, src_endpoint, src_address.u.short_addr); + } else { + Serial.printf( + "Temperature sensor value: %.2f°C from endpoint %d, address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", temperature, src_endpoint, + src_address.u.ieee_addr[7], src_address.u.ieee_addr[6], src_address.u.ieee_addr[5], src_address.u.ieee_addr[4], src_address.u.ieee_addr[3], + src_address.u.ieee_addr[2], src_address.u.ieee_addr[1], src_address.u.ieee_addr[0] + ); + } + sensor_temp = temperature; +} +#endif + +void receiveSensorConfig(float min_temp, float max_temp, float tolerance) { + Serial.printf("Temperature sensor config: min %.2f°C, max %.2f°C, tolerance %.2f°C\n", min_temp, max_temp, tolerance); + sensor_min_temp = min_temp; + sensor_max_temp = max_temp; + sensor_tolerance = tolerance; +} +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + + // Init button switch + pinMode(button, INPUT_PULLUP); + +// Set callback function for receiving temperature from sensor - Use only one option +#if USE_RECEIVE_TEMP_WITH_SOURCE == 0 + zbThermostat.onTempReceive(receiveSensorTemp); // If you bound only one sensor or you don't need to know the source of the temperature +#else + zbThermostat.onTempReceiveWithSource(receiveSensorTempWithSource); +#endif + + // Set callback function for receiving sensor configuration + zbThermostat.onTempConfigReceive(receiveSensorConfig); + + //Optional: set Zigbee device name and model + zbThermostat.setManufacturerAndModel("Espressif", "ZigbeeThermostat"); + + //Optional Time cluster configuration + //example time January 13, 2025 13:30:30 CET + timeinfo.tm_year = 2025 - 1900; // = 2025 + timeinfo.tm_mon = 0; // January + timeinfo.tm_mday = 13; // 13th + timeinfo.tm_hour = 12; // 12 hours - 1 hour (CET) + timeinfo.tm_min = 30; // 30 minutes + timeinfo.tm_sec = 30; // 30 seconds + timeinfo.tm_isdst = -1; + + // Set time and gmt offset (timezone in seconds -> CET = +3600 seconds) + zbThermostat.addTimeCluster(timeinfo, 3600); + + //Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbThermostat); + + //Open network for 180 seconds after boot + Zigbee.setRebootOpenNetwork(180); + + // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode + if (!Zigbee.begin(ZIGBEE_COORDINATOR)) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + + Serial.println("Waiting for Temperature sensor to bound to the thermostat"); + while (!zbThermostat.bound()) { + Serial.printf("."); + delay(500); + } + + Serial.println(); + + // Get temperature sensor configuration for all bound sensors by endpoint number and address + std::list boundSensors = zbThermostat.getBoundDevices(); + for (const auto &device : boundSensors) { + Serial.println("--------------------------------"); + if (device->short_addr == 0x0000 || device->short_addr == 0xFFFF) { //End devices never have 0x0000 short address or 0xFFFF group address + Serial.printf( + "Device on endpoint %d, IEEE Address: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\r\n", device->endpoint, device->ieee_addr[7], device->ieee_addr[6], + device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1], device->ieee_addr[0] + ); + zbThermostat.getTemperatureSettings(device->endpoint, device->ieee_addr); + } else { + Serial.printf("Device on endpoint %d, short address: 0x%x\r\n", device->endpoint, device->short_addr); + zbThermostat.getTemperatureSettings(device->endpoint, device->short_addr); + } + } +} + +void loop() { + // Handle button switch in loop() + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + while (digitalRead(button) == LOW) { + delay(50); + } + // Set reporting interval for temperature sensor + zbThermostat.setTemperatureReporting(0, 10, 2); + } + + // Print temperature sensor data each 10 seconds + static uint32_t last_print = 0; + if (millis() - last_print > 10000) { + last_print = millis(); + int temp_percent = (int)((sensor_temp - sensor_min_temp) / (sensor_max_temp - sensor_min_temp) * 100); + Serial.printf("Loop temperature info: %.2f°C (%d %%)\n", sensor_temp, temp_percent); + zbThermostat.printBoundDevices(Serial); + } +} diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/ci.yml b/libraries/Zigbee/examples/Zigbee_Thermostat/ci.yml new file mode 100644 index 0000000..2f21922 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Thermostat/ci.yml @@ -0,0 +1,4 @@ +fqbn_append: PartitionScheme=zigbee_zczr,ZigbeeMode=zczr + +requires: + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md new file mode 100644 index 0000000..b0e5b5f --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md @@ -0,0 +1,58 @@ +# Arduino-ESP32 Zigbee Vibration Sensor Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) vibration sensor (IAS Zone), +that can be used for example as a security device which is sensing a vibrations. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming + +### Configure the Project + +Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2). +Set the Sensor GPIO by changing the `sensor_pin` variable. + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino new file mode 100644 index 0000000..b3fc6b9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino @@ -0,0 +1,142 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee vibration sensor (IAS Zone). + * + * The example demonstrates how to use Zigbee library to create a end device vibration sensor. + * The vibration sensor is a Zigbee end device, which is reporting data to the Zigbee network. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" +#include + +/* Zigbee vibration sensor configuration */ +#define VIBRATION_SENSOR_ENDPOINT_NUMBER 1 +uint8_t button = BOOT_PIN; +uint8_t sensor_pin = 4; + +ZigbeeVibrationSensor zbVibrationSensor = ZigbeeVibrationSensor(VIBRATION_SENSOR_ENDPOINT_NUMBER); + +/* Preferences for storing ENROLLED flag to persist across reboots */ +Preferences preferences; + +void setup() { + Serial.begin(115200); + + preferences.begin("Zigbee", false); // Save ENROLLED flag in flash so it persists across reboots + bool enrolled = preferences.getBool("ENROLLED"); // Get ENROLLED flag from preferences + preferences.end(); + + // Init button + sensor + pinMode(button, INPUT_PULLUP); + pinMode(sensor_pin, INPUT); + + // Optional: set Zigbee device name and model + zbVibrationSensor.setManufacturerAndModel("Espressif", "ZigbeeVibrationSensor"); + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbVibrationSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Check if device has been enrolled before restarting - if so, restore IAS Zone enroll, otherwise request new IAS Zone enroll + if (enrolled) { + Serial.println("Device has been enrolled before - restoring IAS Zone enrollment"); + zbVibrationSensor.restoreIASZoneEnroll(); + } else { + Serial.println("Device is factory new - first time joining network - requesting new IAS Zone enrollment"); + zbVibrationSensor.requestIASZoneEnroll(); + } + + while (!zbVibrationSensor.enrolled()) { + Serial.print("."); + delay(100); + } + Serial.println(); + Serial.println("Zigbee enrolled successfully!"); + + // Store ENROLLED flag only if this was a new enrollment (previous flag was false) + // Skip writing if we just restored enrollment (flag was already true) + if (!enrolled) { + preferences.begin("Zigbee", false); + preferences.putBool("ENROLLED", true); // set ENROLLED flag to true + preferences.end(); + Serial.println("ENROLLED flag saved to preferences"); + } +} + +void loop() { + // Checking pin for contact change + static bool sensed = false; + if (digitalRead(sensor_pin) == HIGH && !sensed) { + // Update contact sensor value + zbVibrationSensor.setVibration(true); + sensed = true; + //if sensed, wait 2 seconds before next sensing + delay(2000); + } else if (digitalRead(sensor_pin) == LOW && sensed) { + zbVibrationSensor.setVibration(false); + sensed = false; + //if not sensed, wait 0,5 seconds before next sensing + delay(500); + } + + // Checking button for factory reset + if (digitalRead(button) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(button) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + // Clear the ENROLLED flag from preferences + preferences.begin("Zigbee", false); + preferences.putBool("ENROLLED", false); // set ENROLLED flag to false + preferences.end(); + Serial.println("ENROLLED flag cleared from preferences"); + delay(1000); + Zigbee.factoryReset(); + } + } + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md new file mode 100644 index 0000000..826c766 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md @@ -0,0 +1,60 @@ +# Zigbee Wind Speed Sensor Integration with HomeAssistant ZHA + +This guide provides a workaround for integrating a Zigbee Wind Speed Sensor with HomeAssistant using the ZHA integration. Since the wind speed cluster is not natively supported, we will use the ZHA Toolkit from HACS to read the wind speed attribute and store it in a helper variable. +## Alternative Option: Creating a Custom Quirk + +For advanced users, a more robust solution is to create a custom quirk for your Zigbee Wind Speed Sensor. This approach involves writing a custom device handler that directly supports the wind speed cluster, providing a more seamless integration with HomeAssistant. + +Creating a custom quirk can be complex and requires familiarity with Python and the Zigbee protocol. However, it offers greater flexibility and control over your device's behavior. + +For more information and guidance on creating custom quirks, visit the [ZHA Device Handlers repository](https://github.com/zigpy/zha-device-handlers/). + +## Prerequisites + +- HomeAssistant installed and running +- Zigbee Wind Speed Sensor paired with HomeAssistant ZHA +- HACS (Home Assistant Community Store) installed. For more information, visit [HACS](https://hacs.xyz) + +## Steps + +### 1. Install ZHA Toolkit + +1. Open HomeAssistant. +2. Navigate to HACS > Integrations. +3. Search for "ZHA Toolkit - Service for advanced Zigbee Usage" and install it. For more information, visit the [ZHA Toolkit repository](https://github.com/mdeweerd/zha-toolkit). +4. Restart HomeAssistant to apply changes. + +### 2. Create a Helper Variable + +1. Go to Configuration -> Devices & Services -> Helpers. +2. Click on "Add Helper" and select "Number". +3. Name the helper (e.g., `wind_speed`), set the minimum and maximum values, and save it. + +### 3. Create an Automation + +1. Go to Configuration > Automations & Scenes. +2. Click on "Add Automation" and choose "Start with an empty automation". +3. Set a name for the automation (e.g., `Read Wind Speed`). +4. Add a trigger: + - Trigger Type: Time Pattern + - Every: 30 seconds +5. Add an action (Then do): + - Action Type: ZHA Toolkit: Read Attribute + - Setup the action: + ```yaml + action: zha_toolkit.attr_read + metadata: {} + data: + ieee: f0:f5:bd:ff:fe:0e:61:30 #set device IEEE address + endpoint: 10 #set windspeed device endpoint + cluster: 1035 #use this windspeed cluster + attribute: 0 #read measurement value + state_id: input_number.wind_speed #save to created helper variable + state_value_template: value/100 #use correct value format (convert u16 to float) + ``` +6. Save the automation. + +## Conclusion + +By following these steps, you can successfully integrate your Zigbee Wind Speed Sensor with HomeAssistant using the ZHA integration and ZHA Toolkit. The wind speed readings will be updated every 30 seconds and stored in the helper variable for use in your HomeAssistant setup. +The helper variable `wind_speed` is now an entity in HomeAssistant. You can use this entity to display the wind speed on your dashboard or in other automations. diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino new file mode 100644 index 0000000..1c24df9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino @@ -0,0 +1,119 @@ +// Copyright 2024 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee windspeed sensor. + * + * The example demonstrates how to use Zigbee library to create a end device wind speed sensor. + * The wind speed sensor is a Zigbee end device, which is controlled by a Zigbee coordinator. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode" +#endif + +#include "Zigbee.h" + +#define BUTTON_PIN 9 //Boot button for C6/H2 +#define WIND_SPEED_SENSOR_ENDPOINT_NUMBER 10 + +ZigbeeWindSpeedSensor zbWindSpeedSensor = ZigbeeWindSpeedSensor(WIND_SPEED_SENSOR_ENDPOINT_NUMBER); + +/************************ WindSpeed sensor *****************************/ +static void windspeed_sensor_value_update(void *arg) { + for (;;) { + // Read wind speed sensor value (simulated now by temperature sensor) + float windspeed = temperatureRead(); + log_v("Wind speed sensor value: %.2fm/s", windspeed); + // Update windspeed value in Windspeed sensor EP + zbWindSpeedSensor.setWindSpeed(windspeed); + delay(1000); + } +} + +/********************* Arduino functions **************************/ +void setup() { + Serial.begin(115200); + while (!Serial) { + delay(10); + } + + // Init button switch + pinMode(BUTTON_PIN, INPUT); + + // Optional: set Zigbee device name and model + zbWindSpeedSensor.setManufacturerAndModel("Espressif", "ZigbeeWindSpeedSensor"); + + // Set minimum and maximum windspeed measurement value in m/s + zbWindSpeedSensor.setMinMaxValue(0, 50); + + // Set tolerance for windspeed measurement in m/s (lowest possible value is 0.01 m/s) + zbWindSpeedSensor.setTolerance(1); + + // Add endpoint to Zigbee Core + Zigbee.addEndpoint(&zbWindSpeedSensor); + + Serial.println("Starting Zigbee..."); + // When all EPs are registered, start Zigbee in End Device mode + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } else { + Serial.println("Zigbee started successfully!"); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Start Wind speed sensor reading task + xTaskCreate(windspeed_sensor_value_update, "wind_speed_sensor_update", 2048, NULL, 10, NULL); + + // Set reporting interval for windspeed measurement in seconds, must be called after Zigbee.begin() + // min_interval and max_interval in seconds, delta (WindSpeed change in m/s) + // if min = 1 and max = 0, reporting is sent only when windspeed changes by delta + // if min = 0 and max = 10, reporting is sent every 10 seconds or windspeed changes by delta + // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of windspeed change + zbWindSpeedSensor.setReporting(1, 0, 1); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(BUTTON_PIN) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(BUTTON_PIN) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.println("Resetting Zigbee to factory and rebooting in 1s."); + delay(1000); + Zigbee.factoryReset(); + } + } + zbWindSpeedSensor.reportWindSpeed(); + } + delay(100); +} diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.yml b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md b/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md new file mode 100644 index 0000000..469560a --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md @@ -0,0 +1,69 @@ +# Arduino-ESP32 Window Covering Example + +This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) window covering device. + +To see if the communication with your Zigbee network works, use the Serial monitor and watch for output there. + +# Supported Targets + +Currently, this example supports the following targets. + +| Supported Targets | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | + +## Hardware Required + +* A USB cable for power supply and programming +* Board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Window_Covering example +* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application) + +### Configure the Project + +#### Using Arduino IDE + +To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits). + +* Before Compile/Verify, select the correct board: `Tools -> Board`. +* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)` +* Select Tools / USB CDC On Boot: "Enabled" +* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` +* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port. +* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`. + +## Troubleshooting + +If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator. +You can do the following: + +* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`. +* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack. + +By default, the coordinator network is closed after rebooting or flashing new firmware. +To open the network you have 2 options: + +* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`. +* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join. + +***Important: Make sure you are using a good quality USB cable and that you have a reliable power source*** + +* **LED not blinking:** Check the wiring connection and the IO selection. +* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed. +* **COM port not detected:** Check the USB cable and the USB to Serial driver installation. + +If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute). + +## Contribute + +To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst) + +If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome! + +Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else. + +## Resources + +* Official ESP32 Forum: [Link](https://esp32.com) +* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32) +* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) +* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) +* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com) diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino b/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino new file mode 100644 index 0000000..c7f9cf8 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino @@ -0,0 +1,198 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @brief This example demonstrates Zigbee Window Covering. + * + * The example demonstrates how to use Zigbee library to create a end device window covering device. + * The window covering is a Zigbee end device, which is moving the blinds (lift+tilt) and reporting + * its current position to the Zigbee network. + * + * Use setCoveringType() to set the type of covering (blind, shade, etc.). + * + * The example also demonstrates how to use the button to manually control the lift position. + * + * Proper Zigbee mode must be selected in Tools->Zigbee mode + * and also the correct partition scheme must be selected in Tools->Partition Scheme. + * + * Please check the README.md for instructions and more detailed description. + * + * Created by hennikul and Jan Procházka (https://github.com/P-R-O-C-H-Y/) + */ + +#ifndef ZIGBEE_MODE_ED +#error "Zigbee end device mode is not selected in Tools->Zigbee mode" +#endif + +#include "ZigbeeCore.h" +#include "ep/ZigbeeWindowCovering.h" + +#define ZIGBEE_COVERING_ENDPOINT 10 +#define BUTTON_PIN 9 // ESP32-C6/H2 Boot button + +#define MAX_LIFT 200 // centimeters from open position (0-900) +#define MIN_LIFT 0 + +#define MAX_TILT 40 // centimeters from open position (0-900) +#define MIN_TILT 0 + +uint16_t currentLift = MAX_LIFT; +uint8_t currentLiftPercentage = 100; + +uint16_t currentTilt = MAX_TILT; +uint8_t currentTiltPercentage = 100; + +ZigbeeWindowCovering zbCovering = ZigbeeWindowCovering(ZIGBEE_COVERING_ENDPOINT); + +void setup() { + Serial.begin(115200); + + // Init button for factory reset + pinMode(BUTTON_PIN, INPUT_PULLUP); + + // Optional: set Zigbee device name and model + zbCovering.setManufacturerAndModel("Espressif", "WindowBlinds"); + + // Set proper covering type, it defines which attributes are available + zbCovering.setCoveringType(BLIND_LIFT_AND_TILT); + + // Set configuration: operational, online, not commands_reversed, lift / tilt closed_loop, lift / tilt encoder_controlled + zbCovering.setConfigStatus(true, true, false, true, true, true, true); + + // Set mode: not motor_reversed, calibration_mode, not maintenance_mode, not leds_on + zbCovering.setMode(false, true, false, false); + + // Set limits of motion + zbCovering.setLimits(MIN_LIFT, MAX_LIFT, MIN_TILT, MAX_TILT); + + // Set callback function for open, close, filt and tilt change, stop + zbCovering.onOpen(fullOpen); + zbCovering.onClose(fullClose); + zbCovering.onGoToLiftPercentage(goToLiftPercentage); + zbCovering.onGoToTiltPercentage(goToTiltPercentage); + zbCovering.onStop(stopMotor); + + // Add endpoint to Zigbee Core + Serial.println("Adding ZigbeeWindowCovering endpoint to Zigbee Core"); + Zigbee.addEndpoint(&zbCovering); + + // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE + Serial.println("Calling Zigbee.begin()"); + if (!Zigbee.begin()) { + Serial.println("Zigbee failed to start!"); + Serial.println("Rebooting..."); + ESP.restart(); + } + Serial.println("Connecting to network"); + while (!Zigbee.connected()) { + Serial.print("."); + delay(100); + } + Serial.println(); + + // Set initial position + zbCovering.setLiftPercentage(currentLiftPercentage); + zbCovering.setTiltPercentage(currentTiltPercentage); +} + +void loop() { + // Checking button for factory reset + if (digitalRead(BUTTON_PIN) == LOW) { // Push button pressed + // Key debounce handling + delay(100); + int startTime = millis(); + while (digitalRead(BUTTON_PIN) == LOW) { + delay(50); + if ((millis() - startTime) > 3000) { + // If key pressed for more than 3secs, factory reset Zigbee and reboot + Serial.printf("Resetting Zigbee to factory settings, reboot.\n"); + Zigbee.factoryReset(); + delay(30000); + } + } + // Manual lift control simulation by pressing button + manualControl(); + } + delay(500); +} + +void fullOpen() { + /* This is where you would trigger your motor to go to full open state, currentLift should + be updated until full open has been reached in order to provide feedback to controller of actual position + The stop can be always called, so the movement can be stopped at any time */ + + // Our cover updates instantly! + currentLift = MAX_LIFT; + currentLiftPercentage = 100; + Serial.println("Opening cover"); + // Update the current position + zbCovering.setLiftPercentage(currentLiftPercentage); +} + +void fullClose() { + /* This is where you would trigger your motor to go to full close state, currentLift should + be updated until full close has been reached in order to provide feedback to controller of actual position + The stop can be always called, so the movement can be stopped at any time */ + + // Our cover updates instantly! + currentLift = MIN_LIFT; + currentLiftPercentage = 0; + Serial.println("Closing cover"); + // Update the current position + zbCovering.setLiftPercentage(currentLiftPercentage); +} + +void goToLiftPercentage(uint8_t liftPercentage) { + /* This is where you would trigger your motor to go towards liftPercentage, currentLift should + be updated until liftPercentage has been reached in order to provide feedback to controller */ + + // Our simulated cover updates instantly! + currentLift = (liftPercentage * MAX_LIFT) / 100; + currentLiftPercentage = liftPercentage; + Serial.printf("New requested lift from Zigbee: %d (%d)\n", currentLift, liftPercentage); + + // Update the current position + zbCovering.setLiftPercentage(currentLiftPercentage); //or setLiftPosition() +} + +void goToTiltPercentage(uint8_t tiltPercentage) { + /* This is where you would trigger your motor to go towards tiltPercentage, currentTilt should + be updated until tiltPercentage has been reached in order to provide feedback to controller */ + + // Our simulated cover updates instantly! + currentTilt = (tiltPercentage * MAX_TILT) / 100; + currentTiltPercentage = tiltPercentage; + Serial.printf("New requested tilt from Zigbee: %d (%d)\n", currentTilt, tiltPercentage); + + // Update the current position + zbCovering.setTiltPercentage(currentTiltPercentage); //or setTiltPosition() +} + +void stopMotor() { + // Motor can be stopped while moving cover toward current target, when stopped the actual position should be updated + Serial.println("Stopping motor"); + // Update the current position of both lift and tilt + zbCovering.setLiftPercentage(currentLiftPercentage); + zbCovering.setTiltPercentage(currentTiltPercentage); +} + +void manualControl() { + // Simulate lift percentage move by increasing it by 20% each time + currentLiftPercentage += 20; + if (currentLiftPercentage > 100) { + currentLiftPercentage = 0; + } + zbCovering.setLiftPercentage(currentLiftPercentage); + // Also setLiftPosition() can be used to set the exact position instead of percentage +} diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.yml b/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.yml new file mode 100644 index 0000000..22315a9 --- /dev/null +++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.yml @@ -0,0 +1,5 @@ +fqbn_append: PartitionScheme=zigbee,ZigbeeMode=ed + +requires: + - CONFIG_SOC_IEEE802154_SUPPORTED=y + - CONFIG_ZB_ENABLED=y diff --git a/libraries/Zigbee/keywords.txt b/libraries/Zigbee/keywords.txt new file mode 100644 index 0000000..48b4f3d --- /dev/null +++ b/libraries/Zigbee/keywords.txt @@ -0,0 +1,355 @@ +####################################### +# Syntax Coloring Map For Zigbee +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +# Base Classes +ZigbeeCore KEYWORD1 +Zigbee KEYWORD1 +ZigbeeEP KEYWORD1 + +# Endpoint Classes +ZigbeeAnalog KEYWORD1 +ZigbeeBinary KEYWORD1 +ZigbeeCarbonDioxideSensor KEYWORD1 +ZigbeeColorDimmableLight KEYWORD1 +ZigbeeColorDimmerSwitch KEYWORD1 +ZigbeeContactSwitch KEYWORD1 +ZigbeeDimableLight KEYWORD1 +ZigbeeDoorWindowHandle KEYWORD1 +ZigbeeElectricalMeasurement KEYWORD1 +ZigbeeFanControl KEYWORD1 +ZigbeeFlowSensor KEYWORD1 +ZigbeeGateway KEYWORD1 +ZigbeeIlluminanceSensor KEYWORD1 +ZigbeeLight KEYWORD1 +ZigbeeMultistate KEYWORD1 +ZigbeeOccupancySensor KEYWORD1 +ZigbeePM25Sensor KEYWORD1 +ZigbeePowerOutlet KEYWORD1 +ZigbeePressureSensor KEYWORD1 +ZigbeeRangeExtender KEYWORD1 +ZigbeeSwitch KEYWORD1 +ZigbeeTempSensor KEYWORD1 +ZigbeeThermostat KEYWORD1 +ZigbeeVibrationSensor KEYWORD1 +ZigbeeWindowCovering KEYWORD1 +ZigbeeWindSpeedSensor KEYWORD1 + +# Other +zigbee_role_t KEYWORD1 +zbstring_t KEYWORD1 +zb_device_params_t KEYWORD1 +zigbee_scan_result_t KEYWORD1 +zb_power_source_t KEYWORD1 +ZigbeeWindowCoveringType KEYWORD1 +ZigbeeLevelStepDirection KEYWORD1 +ZigbeeFanMode KEYWORD1 +ZigbeeFanModeSequence KEYWORD1 +zb_cmd_type_t KEYWORD1 +ZigbeeColorMode KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +# ZigbeeCore +begin KEYWORD2 +start KEYWORD2 +stop KEYWORD2 +started KEYWORD2 +connected KEYWORD2 +getRole KEYWORD2 +addEndpoint KEYWORD2 +setRadioConfig KEYWORD2 +getRadioConfig KEYWORD2 +setHostConfig KEYWORD2 +getHostConfig KEYWORD2 +setPrimaryChannelMask KEYWORD2 +setScanDuration KEYWORD2 +getScanDuration KEYWORD2 +setRebootOpenNetwork KEYWORD2 +openNetwork KEYWORD2 +scanNetworks KEYWORD2 +scanComplete KEYWORD2 +getScanResult KEYWORD2 +scanDelete KEYWORD2 +factoryReset KEYWORD2 +allowMultiEndpointBinding KEYWORD2 + +# Common ZigbeeEP +setEpConfig KEYWORD2 +setVersion KEYWORD2 +getEndpoint KEYWORD2 +printBoundDevices KEYWORD2 +getBoundDevices KEYWORD2 +bound KEYWORD2 +allowMultipleBinding KEYWORD2 +setManualBinding KEYWORD2 +setManufacturerAndModel KEYWORD2 +setPowerSource KEYWORD2 +setBatteryPercentage KEYWORD2 +reportBatteryPercentage KEYWORD2 +readManufacturer KEYWORD2 +readModel KEYWORD2 +onIdentify KEYWORD2 +addTimeCluster KEYWORD2 +setTime KEYWORD2 +setTimezone KEYWORD2 +getTime KEYWORD2 +getTimezone KEYWORD2 +addOTAClient KEYWORD2 +clearBoundDevices KEYWORD2 +onDefaultResponse KEYWORD2 + +# ZigbeeLight + ZigbeeColorDimmableLight +restoreLight KEYWORD2 +setLight KEYWORD2 +setLightState KEYWORD2 +setLightLevel KEYWORD2 +setLightColor KEYWORD2 +setLightColorTemperature KEYWORD2 +setLightColorCapabilities KEYWORD2 +setLightColorTemperatureRange KEYWORD2 +getLightState KEYWORD2 +getLightLevel KEYWORD2 +getLightRed KEYWORD2 +getLightGreen KEYWORD2 +getLightBlue KEYWORD2 +getLightColorTemperature KEYWORD2 +getLightColorMode KEYWORD2 +getLightColorHue KEYWORD2 +getLightColorSaturation KEYWORD2 +getLightColorCapabilities KEYWORD2 +onLightChange KEYWORD2 +onLightChangeRgb KEYWORD2 +onLightChangeHsv KEYWORD2 +onLightChangeTemp KEYWORD2 +onLightColorChangeWithSource KEYWORD2 +onLightLevelChange KEYWORD2 +onLightLevelChangeWithSource KEYWORD2 +onLightStateChange KEYWORD2 +onLightStateChangeWithSource KEYWORD2 + +# ZigbeeSwitch + ZigbeeColorDimmerSwitch +lightToggle KEYWORD2 +lightOn KEYWORD2 +lightOff KEYWORD2 +lightOffWithEffect KEYWORD2 +lightOnWithTimedOff KEYWORD2 +lightOnWithSceneRecall KEYWORD2 +setLightLevel KEYWORD2 +setLightLevelStep KEYWORD2 +setLightColor KEYWORD2 +getLightState KEYWORD2 +getLightLevel KEYWORD2 +getLightColor KEYWORD2 +onLightStateChange KEYWORD2 +onLightStateChangeWithSource KEYWORD2 +onLightLevelChange KEYWORD2 +onLightLevelChangeWithSource KEYWORD2 +onLightColorChange KEYWORD2 +onLightColorChangeWithSource KEYWORD2 + +# ZigbeeThermostat +onTempRecieve KEYWORD2 +onTempReceiveWithSource KEYWORD2 +onTempConfigReceive KEYWORD2 +getTemperature KEYWORD2 +getTemperatureSettings KEYWORD2 +setTemperatureReporting KEYWORD2 +onHumidityReceive KEYWORD2 +onHumidityReceiveWithSource KEYWORD2 +onHumidityConfigReceive KEYWORD2 +getHumidity KEYWORD2 +getHumiditySettings KEYWORD2 +setHumidityReporting KEYWORD2 + +# Common Zigbee Sensor +setMinMaxValue KEYWORD2 +setTolerance KEYWORD2 +setReporting KEYWORD2 +report KEYWORD2 + +# ZigbeeTempSensor + humidity +setTemperature KEYWORD2 +reportTemperature KEYWORD2 +addHumiditySensor KEYWORD2 +setHumidity KEYWORD2 +setHumidityReporting KEYWORD2 +reportHumidity KEYWORD2 + +# ZigbeeIlluminanceSensor +setIlluminance KEYWORD2 + +# ZigbeeFlowSensor +setFlow KEYWORD2 + +# ZigbeePressureSensor +setPressure KEYWORD2 + +# ZigbeeOccupancySensor +setOccupancy KEYWORD2 +setSensorType KEYWORD2 + +# ZigbeeCarbonDioxideSensor +setCarbonDioxide KEYWORD2 + +# ZigbeeAnalog +addAnalogInput KEYWORD2 +addAnalogOutput KEYWORD2 +onAnalogOutputChange KEYWORD2 +setAnalogInput KEYWORD2 +setAnalogOutput KEYWORD2 +getAnalogOutput KEYWORD2 +reportAnalogInput KEYWORD2 +reportAnalogOutput KEYWORD2 +setAnalogInputReporting KEYWORD2 +setAnalogInputApplication KEYWORD2 +setAnalogInputDescription KEYWORD2 +setAnalogInputResolution KEYWORD2 +setAnalogOutputApplication KEYWORD2 +setAnalogOutputDescription KEYWORD2 +setAnalogOutputResolution KEYWORD2 + +# ZigbeeCarbonDioxideSensor +setCarbonDioxide KEYWORD2 + +# ZigbeeContactSwitch + ZigbeeDoorWindowHandle +setIASClientEndpoint KEYWORD2 +setClosed KEYWORD2 +setOpen KEYWORD2 +setTilted KEYWORD2 +requestIASZoneEnroll KEYWORD2 +restoreIASZoneEnroll KEYWORD2 +enrolled KEYWORD2 + +# ZigbeeVibrationSensor +setVibration KEYWORD2 + +# ZigbeeWindowCovering +onOpen KEYWORD2 +onClose KEYWORD2 +onGoToLiftPercentage KEYWORD2 +onGoToTiltPercentage KEYWORD2 +onStop KEYWORD2 +setLiftPosition KEYWORD2 +setLiftPercentage KEYWORD2 +setTiltPosition KEYWORD2 +setTiltPercentage KEYWORD2 +setCoveringType KEYWORD2 +setConfigStatus KEYWORD2 +setMode KEYWORD2 +setLimits KEYWORD2 + +# ZigbeeBinary +addBinaryInput KEYWORD2 +addBinaryOutput KEYWORD2 +onBinaryOutputChange KEYWORD2 +setBinaryInput KEYWORD2 +setBinaryOutput KEYWORD2 +getBinaryOutput KEYWORD2 +reportBinaryInput KEYWORD2 +reportBinaryOutput KEYWORD2 +setBinaryInputApplication KEYWORD2 +setBinaryInputDescription KEYWORD2 +setBinaryOutputApplication KEYWORD2 +setBinaryOutputDescription KEYWORD2 + +# ZigbeeFanControl +setFanModeSequence KEYWORD2 +getFanMode KEYWORD2 +getFanModeSequence KEYWORD2 +onFanModeChange KEYWORD2 + +# ZigbeeMultistate +addMultistateInput KEYWORD2 +addMultistateOutput KEYWORD2 +onMultistateOutputChange KEYWORD2 +setMultistateInput KEYWORD2 +getMultistateInput KEYWORD2 +setMultistateOutput KEYWORD2 +getMultistateOutput KEYWORD2 +reportMultistateInput KEYWORD2 +reportMultistateOutput KEYWORD2 +setMultistateInputApplication KEYWORD2 +setMultistateInputDescription KEYWORD2 +setMultistateInputStates KEYWORD2 +setMultistateOutputApplication KEYWORD2 +setMultistateOutputDescription KEYWORD2 +setMultistateOutputStates KEYWORD2 +#getMultistateInputStateNames KEYWORD2 +getMultistateInputStateNamesLength KEYWORD2 +#getMultistateOutputStateNames KEYWORD2 +getMultistateOutputStateNamesLength KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + +ZIGBEE_COORDINATOR LITERAL1 +ZIGBEE_ROUTER LITERAL1 +ZIGBEE_END_DEVICE LITERAL1 +ZIGBEE_DEFAULT_ED_CONFIG LITERAL1 +ZIGBEE_DEFAULT_ROUTER_CONFIG LITERAL1 +ZIGBEE_DEFAULT_COORDINATOR_CONFIG LITERAL1 +ZIGBEE_DEFAULT_RADIO_CONFIG LITERAL1 +ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG LITERAL1 +ZIGBEE_DEFAULT_HOST_CONFIG LITERAL1 +ZB_ARRAY_LENGHT LITERAL1 + +# ZigbeeMultistate +ZB_MULTISTATE_APPLICATION_TYPE_0_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_0_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_0_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_1_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_1_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_1_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_2_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_2_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_2_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_3_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_3_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_3_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_4_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_4_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_4_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_5_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_5_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_5_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_6_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_6_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_6_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_7_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_7_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_7_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_8_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_8_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_8_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_9_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_9_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_9_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_10_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_10_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_10_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_11_INDEX LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_11_NUM_STATES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_11_STATE_NAMES LITERAL1 +ZB_MULTISTATE_APPLICATION_TYPE_OTHER_INDEX LITERAL1 + +# ZigbeeColorDimmerSwitch level step +ZIGBEE_LEVEL_STEP_UP LITERAL1 +ZIGBEE_LEVEL_STEP_DOWN LITERAL1 + +#ZigbeeColorDimmableLight +ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION LITERAL1 +ZIGBEE_COLOR_CAPABILITY_ENHANCED_HUE LITERAL1 +ZIGBEE_COLOR_CAPABILITY_COLOR_LOOP LITERAL1 +ZIGBEE_COLOR_CAPABILITY_X_Y LITERAL1 +ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP LITERAL1 +ZIGBEE_COLOR_MODE_HUE_SATURATION LITERAL1 +ZIGBEE_COLOR_MODE_CURRENT_X_Y LITERAL1 +ZIGBEE_COLOR_MODE_TEMPERATURE LITERAL1 diff --git a/libraries/Zigbee/library.properties b/libraries/Zigbee/library.properties new file mode 100644 index 0000000..5c56493 --- /dev/null +++ b/libraries/Zigbee/library.properties @@ -0,0 +1,9 @@ +name=Zigbee +version=3.3.7 +author=P-R-O-C-H-Y +maintainer=Jan Procházka +sentence=Enables zigbee connection with the ESP32 +paragraph=With this library you can create zigbee end devices, routers, coordinators and connect them to the zigbee network. +category=Communication +url= +architectures=esp32 diff --git a/libraries/Zigbee/src/Zigbee.h b/libraries/Zigbee/src/Zigbee.h new file mode 100644 index 0000000..837c19f --- /dev/null +++ b/libraries/Zigbee/src/Zigbee.h @@ -0,0 +1,58 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Zigbee library header file for includes of all Zigbee library headers. + +#pragma once + +// Common types and functions +#include "ZigbeeTypes.h" + +// Core +#include "ZigbeeCore.h" +#include "ZigbeeEP.h" + +// Endpoints +//// Switches +#include "ep/ZigbeeColorDimmerSwitch.h" +#include "ep/ZigbeeSwitch.h" +//// Lights +#include "ep/ZigbeeColorDimmableLight.h" +#include "ep/ZigbeeDimmableLight.h" +#include "ep/ZigbeeLight.h" +//// Controllers +#include "ep/ZigbeeThermostat.h" +#include "ep/ZigbeeFanControl.h" +////Outlets +#include "ep/ZigbeePowerOutlet.h" +//// Sensors +#include "ep/ZigbeeAnalog.h" +#include "ep/ZigbeeBinary.h" +#include "ep/ZigbeeCarbonDioxideSensor.h" +#include "ep/ZigbeeContactSwitch.h" +#include "ep/ZigbeeDoorWindowHandle.h" +#include "ep/ZigbeeElectricalMeasurement.h" +#include "ep/ZigbeeFlowSensor.h" +#include "ep/ZigbeeIlluminanceSensor.h" +#include "ep/ZigbeeMultistate.h" +#include "ep/ZigbeeOccupancySensor.h" +#include "ep/ZigbeePM25Sensor.h" +#include "ep/ZigbeePressureSensor.h" +#include "ep/ZigbeeTempSensor.h" +#include "ep/ZigbeeVibrationSensor.h" +#include "ep/ZigbeeWindSpeedSensor.h" +#include "ep/ZigbeeWindowCovering.h" +//// Other +#include "ep/ZigbeeGateway.h" +#include "ep/ZigbeeRangeExtender.h" diff --git a/libraries/Zigbee/src/ZigbeeCore.cpp b/libraries/Zigbee/src/ZigbeeCore.cpp new file mode 100644 index 0000000..9706d73 --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeCore.cpp @@ -0,0 +1,849 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Zigbee Core Functions */ + +#include "ZigbeeCore.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeHandlers.cpp" +#include "Arduino.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif +#include "zboss_api.h" +extern zb_ret_t zb_nvram_write_dataset(zb_nvram_dataset_types_t t); // rejoin scanning workaround +extern void zb_set_ed_node_descriptor(bool power_src, bool rx_on_when_idle, bool alloc_addr); // sleepy device power mode workaround +#ifdef __cplusplus +} +#endif + +static bool edBatteryPowered = false; + +ZigbeeCore::ZigbeeCore() { + _radio_config.radio_mode = ZB_RADIO_MODE_NATIVE; // Use the native 15.4 radio + _host_config.host_connection_mode = ZB_HOST_CONNECTION_MODE_NONE; // Disable host connection + _zb_ep_list = esp_zb_ep_list_create(); + _primary_channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK; + _open_network = 0; + _scan_status = ZB_SCAN_FAILED; + _begin_timeout = ZB_BEGIN_TIMEOUT_DEFAULT; + _started = false; + _connected = false; + _scan_duration = 3; // default scan duration + _rx_on_when_idle = true; + _debug = false; + _allow_multi_endpoint_binding = false; + _global_default_response_cb = nullptr; // Initialize global callback to nullptr + if (!lock) { + lock = xSemaphoreCreateBinary(); + if (lock == NULL) { + log_e("Semaphore creation failed"); + } + } +} + +//forward declaration +static esp_err_t zb_action_handler(esp_zb_core_action_callback_id_t callback_id, const void *message); +bool zb_apsde_data_indication_handler(esp_zb_apsde_data_ind_t ind); + +bool ZigbeeCore::begin(esp_zb_cfg_t *role_cfg, bool erase_nvs) { + if (!zigbeeInit(role_cfg, erase_nvs)) { + log_e("ZigbeeCore begin failed"); + return false; + } + _role = (zigbee_role_t)role_cfg->esp_zb_role; + if (xSemaphoreTake(lock, _begin_timeout) != pdTRUE) { + log_e("ZigbeeCore begin failed or timeout"); + if (_role != ZIGBEE_COORDINATOR) { // Only End Device and Router can rejoin + resetNVRAMChannelMask(); + } + } + return started(); +} + +bool ZigbeeCore::begin(zigbee_role_t role, bool erase_nvs) { + bool status = true; + switch (role) { + case ZIGBEE_COORDINATOR: + { + _role = ZIGBEE_COORDINATOR; + esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_COORDINATOR_CONFIG(); + status = zigbeeInit(&zb_nwk_cfg, erase_nvs); + break; + } + case ZIGBEE_ROUTER: + { + _role = ZIGBEE_ROUTER; + esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_ROUTER_CONFIG(); + status = zigbeeInit(&zb_nwk_cfg, erase_nvs); + break; + } + case ZIGBEE_END_DEVICE: + { + _role = ZIGBEE_END_DEVICE; + esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_ED_CONFIG(); + status = zigbeeInit(&zb_nwk_cfg, erase_nvs); + break; + } + default: log_e("Invalid Zigbee Role"); return false; + } + if (!status || xSemaphoreTake(lock, _begin_timeout) != pdTRUE) { + log_e("ZigbeeCore begin failed or timeout"); + if (_role != ZIGBEE_COORDINATOR) { // Only End Device and Router can rejoin + resetNVRAMChannelMask(); + } + } + return started(); +} + +bool ZigbeeCore::addEndpoint(ZigbeeEP *ep) { + ep_objects.push_back(ep); + + log_d("Endpoint: %d, Device ID: 0x%04x", ep->_endpoint, ep->_device_id); + //Register clusters and ep_list to the ZigbeeCore class's ep_list + if (ep->_ep_config.endpoint == 0 || ep->_cluster_list == nullptr) { + log_e("Endpoint config or Cluster list is not initialized, EP not added to ZigbeeCore's EP list"); + return false; + } + esp_err_t ret = ESP_OK; + if (ep->_device_id == ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID) { + ret = esp_zb_ep_list_add_gateway_ep(_zb_ep_list, ep->_cluster_list, ep->_ep_config); + } else { + ret = esp_zb_ep_list_add_ep(_zb_ep_list, ep->_cluster_list, ep->_ep_config); + } + if (ret != ESP_OK) { + log_e("Failed to add endpoint: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +static void esp_zb_task(void *pvParameters) { + esp_zb_bdb_set_scan_duration(Zigbee.getScanDuration()); + + /* initialize Zigbee stack */ + ESP_ERROR_CHECK(esp_zb_start(false)); + + //NOTE: This is a workaround to make battery powered devices to be discovered as battery powered + if (((zigbee_role_t)Zigbee.getRole() == ZIGBEE_END_DEVICE) && edBatteryPowered) { + zb_set_ed_node_descriptor(0, Zigbee.getRxOnWhenIdle(), 1); + } + + esp_zb_stack_main_loop(); +} + +// Zigbee core init function +bool ZigbeeCore::zigbeeInit(esp_zb_cfg_t *zb_cfg, bool erase_nvs) { + // Zigbee platform configuration + esp_zb_platform_config_t platform_config = { + .radio_config = _radio_config, + .host_config = _host_config, + }; + + esp_err_t err = esp_zb_platform_config(&platform_config); + if (err != ESP_OK) { + log_e("Failed to configure Zigbee platform"); + return false; + } + + // Initialize Zigbee stack + log_d("Initialize Zigbee stack"); + esp_zb_init(zb_cfg); + + // Register all Zigbee EPs in list + if (ep_objects.empty()) { + log_w("No Zigbee EPs to register"); + } else { + log_d("Register all Zigbee EPs in list"); + err = esp_zb_device_register(_zb_ep_list); + if (err != ESP_OK) { + log_e("Failed to register Zigbee EPs"); + return false; + } + + //print the list of Zigbee EPs from ep_objects + log_i("List of registered Zigbee EPs:"); + for (std::list::iterator it = ep_objects.begin(); it != ep_objects.end(); ++it) { + log_i("Device type: %s, Endpoint: %d, Device ID: 0x%04x", getDeviceTypeString((*it)->_device_id), (*it)->_endpoint, (*it)->_device_id); + if ((*it)->_power_source == ZB_POWER_SOURCE_BATTERY) { + edBatteryPowered = true; + } + } + } + // Register Zigbee action handler + esp_zb_core_action_handler_register(zb_action_handler); + err = esp_zb_set_primary_network_channel_set(_primary_channel_mask); + if (err != ESP_OK) { + log_e("Failed to set primary network channel mask"); + return false; + } + + // Register APSDATA INDICATION handler to catch bind/unbind requests + esp_zb_aps_data_indication_handler_register(zb_apsde_data_indication_handler); + + //Erase NVRAM before creating connection to new Coordinator + if (erase_nvs) { + esp_zb_nvram_erase_at_start(true); + } + + // Create Zigbee task and start Zigbee stack + xTaskCreate(esp_zb_task, "Zigbee_main", 8192, NULL, 5, NULL); + + return true; +} + +void ZigbeeCore::setRadioConfig(esp_zb_radio_config_t config) { + _radio_config = config; +} + +esp_zb_radio_config_t ZigbeeCore::getRadioConfig() { + return _radio_config; +} + +void ZigbeeCore::setHostConfig(esp_zb_host_config_t config) { + _host_config = config; +} + +esp_zb_host_config_t ZigbeeCore::getHostConfig() { + return _host_config; +} + +void ZigbeeCore::setPrimaryChannelMask(uint32_t mask) { + _primary_channel_mask = mask; +} + +void ZigbeeCore::setScanDuration(uint8_t duration) { + if (duration < 1 || duration > 4) { + log_e("Invalid scan duration, must be between 1 and 4"); + return; + } + _scan_duration = duration; +} + +void ZigbeeCore::setRebootOpenNetwork(uint8_t time) { + _open_network = time; +} + +void ZigbeeCore::openNetwork(uint8_t time) { + if (started()) { + log_v("Opening network for joining for %d seconds", time); + esp_zb_bdb_open_network(time); + } +} + +void ZigbeeCore::closeNetwork() { + if (started()) { + log_v("Closing network"); + esp_zb_bdb_close_network(); + } +} + +static void bdb_start_top_level_commissioning_cb(uint8_t mode_mask) { + if (esp_zb_bdb_start_top_level_commissioning(mode_mask) != ESP_OK) { + log_e("Failed to start Zigbee commissioning"); + } +} + +void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct) { + //common variables + uint32_t *p_sg_p = signal_struct->p_app_signal; + esp_err_t err_status = signal_struct->esp_err_status; + esp_zb_app_signal_type_t sig_type = (esp_zb_app_signal_type_t)*p_sg_p; + //coordinator variables + esp_zb_zdo_signal_device_annce_params_t *dev_annce_params = NULL; + esp_zb_zdo_signal_leave_params_t *leave_params = NULL; + //router variables + esp_zb_zdo_signal_device_update_params_t *dev_update_params = NULL; + + //main switch + switch (sig_type) { + case ESP_ZB_ZDO_SIGNAL_SKIP_STARTUP: // Common + log_i("Zigbee stack initialized"); + log_d("Zigbee channel mask: 0x%08x", esp_zb_get_channel_mask()); + esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_INITIALIZATION); + break; + case ESP_ZB_BDB_SIGNAL_DEVICE_FIRST_START: // Common + case ESP_ZB_BDB_SIGNAL_DEVICE_REBOOT: // Common + if (err_status == ESP_OK) { + log_i("Device started up in %s factory-reset mode", esp_zb_bdb_is_factory_new() ? "" : "non"); + if (esp_zb_bdb_is_factory_new()) { + // Role specific code + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) { + log_i("Start network formation"); + esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_FORMATION); + } else { + log_i("Start network steering"); + esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_STEERING); + Zigbee._started = true; + xSemaphoreGive(Zigbee.lock); + } + } else { + log_i("Device rebooted"); + Zigbee._started = true; + xSemaphoreGive(Zigbee.lock); + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR && Zigbee._open_network > 0) { + log_i("Opening network for joining for %d seconds", Zigbee._open_network); + esp_zb_bdb_open_network(Zigbee._open_network); + } else { + // Save the channel mask to NVRAM in case of reboot which may be on a different channel after a change in the network + Zigbee.setNVRAMChannelMask(1 << esp_zb_get_current_channel()); + Zigbee._connected = true; // Coordinator is always connected + } + Zigbee.searchBindings(); + } + } else { + /* commissioning failed */ + log_w("Commissioning failed, trying again...", esp_err_to_name(err_status)); + esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_INITIALIZATION, 500); + } + break; + case ESP_ZB_BDB_SIGNAL_FORMATION: // Coordinator + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) { + if (err_status == ESP_OK) { + esp_zb_ieee_addr_t extended_pan_id; + esp_zb_get_extended_pan_id(extended_pan_id); + log_i( + "Formed network successfully (Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, PAN ID: 0x%04hx, Channel:%d, Short Address: 0x%04hx)", + extended_pan_id[7], extended_pan_id[6], extended_pan_id[5], extended_pan_id[4], extended_pan_id[3], extended_pan_id[2], extended_pan_id[1], + extended_pan_id[0], esp_zb_get_pan_id(), esp_zb_get_current_channel(), esp_zb_get_short_address() + ); + Zigbee._connected = true; + esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_STEERING); + } else { + log_i("Restart network formation (status: %s)", esp_err_to_name(err_status)); + esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_NETWORK_FORMATION, 1000); + } + } + break; + case ESP_ZB_BDB_SIGNAL_STEERING: // Router and End Device + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) { + if (err_status == ESP_OK) { + log_i("Network steering started"); + } + Zigbee._started = true; + xSemaphoreGive(Zigbee.lock); + } else { + if (err_status == ESP_OK) { + esp_zb_ieee_addr_t extended_pan_id; + esp_zb_get_extended_pan_id(extended_pan_id); + log_i( + "Joined network successfully (Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, PAN ID: 0x%04hx, Channel:%d, Short Address: 0x%04hx)", + extended_pan_id[7], extended_pan_id[6], extended_pan_id[5], extended_pan_id[4], extended_pan_id[3], extended_pan_id[2], extended_pan_id[1], + extended_pan_id[0], esp_zb_get_pan_id(), esp_zb_get_current_channel(), esp_zb_get_short_address() + ); + Zigbee._connected = true; + // Set channel mask and write to NVRAM, so that the device will re-join the network faster after reboot (scan only on the current channel) + Zigbee.setNVRAMChannelMask(1 << esp_zb_get_current_channel()); + } else { + log_i("Network steering was not successful (status: %s)", esp_err_to_name(err_status)); + esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_NETWORK_STEERING, 1000); + } + } + break; + case ESP_ZB_ZDO_SIGNAL_DEVICE_ANNCE: // Coordinator + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) { + dev_annce_params = (esp_zb_zdo_signal_device_annce_params_t *)esp_zb_app_signal_get_params(p_sg_p); + log_i("New device commissioned or rejoined (short: 0x%04hx)", dev_annce_params->device_short_addr); + esp_zb_zdo_match_desc_req_param_t cmd_req; + cmd_req.dst_nwk_addr = dev_annce_params->device_short_addr; + cmd_req.addr_of_interest = dev_annce_params->device_short_addr; + log_v("Device capabilities: 0x%02x", dev_annce_params->capability); + /* + capability: + Bit 0 – Alternate PAN Coordinator + Bit 1 – Device type: 1- ZigBee Router; 0 – End Device + Bit 2 – Power Source: 1 Main powered + Bit 3 – Receiver on when Idle + Bit 4 – Reserved + Bit 5 – Reserved + Bit 6 – Security capability + Bit 7 – Reserved + */ + // for each endpoint in the list call the findEndpoint function if not bounded or allowed to bind multiple devices + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + log_d("Checking endpoint %d", (*it)->getEndpoint()); + if (!(*it)->epUseManualBinding()) { + if (!(*it)->bound() || (*it)->epAllowMultipleBinding()) { + // Check if the device is already bound + bool found = false; + // Get the list of devices bound to the EP + std::list bound_devices = (*it)->getBoundDevices(); + for (std::list::iterator device = bound_devices.begin(); device != bound_devices.end(); ++device) { + if (((*device)->short_addr == dev_annce_params->device_short_addr) || (memcmp((*device)->ieee_addr, dev_annce_params->ieee_addr, 8) == 0)) { + found = true; + log_d("Device already bound to endpoint %d", (*it)->getEndpoint()); + break; + } + } + if (!found) { + log_d("Device not bound to endpoint %d and it is free to bound!", (*it)->getEndpoint()); + (*it)->findEndpoint(&cmd_req); + log_d("Endpoint %d is searching for device", (*it)->getEndpoint()); + if (!Zigbee.allowMultiEndpointBinding()) { // If multi endpoint binding is not allowed, break the loop to keep backwards compatibility + break; + } + } + } + } + } + } + break; + case ESP_ZB_ZDO_SIGNAL_DEVICE_UPDATE: // Router + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_ROUTER) { + dev_update_params = (esp_zb_zdo_signal_device_update_params_t *)esp_zb_app_signal_get_params(p_sg_p); + log_i("New device commissioned or rejoined (short: 0x%04hx)", dev_update_params->short_addr); + esp_zb_zdo_match_desc_req_param_t cmd_req; + cmd_req.dst_nwk_addr = dev_update_params->short_addr; + cmd_req.addr_of_interest = dev_update_params->short_addr; + // for each endpoint in the list call the findEndpoint function if not bounded or allowed to bind multiple devices + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + log_d("Checking endpoint %d", (*it)->getEndpoint()); + if (!(*it)->epUseManualBinding()) { + if (!(*it)->bound() || (*it)->epAllowMultipleBinding()) { + // Check if the device is already bound + bool found = false; + // Get the list of devices bound to the EP + std::list bound_devices = (*it)->getBoundDevices(); + for (std::list::iterator device = bound_devices.begin(); device != bound_devices.end(); ++device) { + if (((*device)->short_addr == dev_update_params->short_addr) || (memcmp((*device)->ieee_addr, dev_update_params->long_addr, 8) == 0)) { + found = true; + log_d("Device already bound to endpoint %d", (*it)->getEndpoint()); + break; + } + } + if (!found) { + log_d("Device not bound to endpoint %d and it is free to bound!", (*it)->getEndpoint()); + (*it)->findEndpoint(&cmd_req); + log_d("Endpoint %d is searching for device", (*it)->getEndpoint()); + if (!Zigbee.allowMultiEndpointBinding()) { // If multi endpoint binding is not allowed, break the loop to keep backwards compatibility + break; + } + } + } + } + } + } + break; + case ESP_ZB_NWK_SIGNAL_PERMIT_JOIN_STATUS: // Coordinator + if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) { + if (err_status == ESP_OK) { + if (*(uint8_t *)esp_zb_app_signal_get_params(p_sg_p)) { + log_i("Network(0x%04hx) is open for %d seconds", esp_zb_get_pan_id(), *(uint8_t *)esp_zb_app_signal_get_params(p_sg_p)); + } else { + log_i("Network(0x%04hx) closed, devices joining not allowed.", esp_zb_get_pan_id()); + } + } + } + break; + case ESP_ZB_ZDO_SIGNAL_LEAVE: // End Device + Router + // Received signal to leave the network + if ((zigbee_role_t)Zigbee.getRole() != ZIGBEE_COORDINATOR) { + leave_params = (esp_zb_zdo_signal_leave_params_t *)esp_zb_app_signal_get_params(p_sg_p); + log_v("Signal to leave the network, leave type: %d", leave_params->leave_type); + if (leave_params->leave_type == ESP_ZB_NWK_LEAVE_TYPE_RESET) { // Leave without rejoin -> Factory reset + log_i("Leave without rejoin, factory reset the device"); + Zigbee.factoryReset(true); + } else { // Leave with rejoin -> Rejoin the network, only reboot the device + log_i("Leave with rejoin, only reboot the device"); + ESP.restart(); + } + } + break; + default: log_v("ZDO signal: %s (0x%x), status: %s", esp_zb_zdo_signal_to_string(sig_type), sig_type, esp_err_to_name(err_status)); break; + } +} + +// APS DATA INDICATION HANDLER to catch bind/unbind requests +bool zb_apsde_data_indication_handler(esp_zb_apsde_data_ind_t ind) { + if (Zigbee.getDebugMode()) { + log_d("APSDE INDICATION - Received APSDE-DATA indication, status: %d", ind.status); + log_d( + "APSDE INDICATION - dst_endpoint: %d, src_endpoint: %d, dst_addr_mode: %d, src_addr_mode: %d, cluster_id: 0x%04x, asdu_length: %d", ind.dst_endpoint, + ind.src_endpoint, ind.dst_addr_mode, ind.src_addr_mode, ind.cluster_id, ind.asdu_length + ); + log_d( + "APSDE INDICATION - dst_short_addr: 0x%04x, src_short_addr: 0x%04x, profile_id: 0x%04x, security_status: %d, lqi: %d, rx_time: %d", ind.dst_short_addr, + ind.src_short_addr, ind.profile_id, ind.security_status, ind.lqi, ind.rx_time + ); + } + if (ind.status == 0x00) { + // Catch bind/unbind requests to update the bound devices list + if (ind.cluster_id == 0x21 || ind.cluster_id == 0x22) { + Zigbee.searchBindings(); + } + } else { + log_e("APSDE INDICATION - Invalid status of APSDE-DATA indication, error code: %d", ind.status); + } + return false; //False to let the stack process the message as usual +} + +void ZigbeeCore::factoryReset(bool restart) { + if (restart) { + log_v("Factory resetting Zigbee stack, device will reboot"); + esp_zb_factory_reset(); + } else { + log_v("Factory resetting Zigbee NVRAM to factory default"); + log_w("The device will not reboot, to take effect please reboot the device manually"); + esp_zb_zcl_reset_nvram_to_factory_default(); + } +} + +void ZigbeeCore::scanCompleteCallback(esp_zb_zdp_status_t zdo_status, uint8_t count, esp_zb_network_descriptor_t *nwk_descriptor) { + log_v("Zigbee network scan complete"); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_v("Found %d networks", count); + //print Zigbee networks + for (int i = 0; i < count; i++) { + log_v( + "Network %d: PAN ID: 0x%04hx, Permit Joining: %s, Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, Channel: %d, Router Capacity: %s, End " + "Device Capacity: %s", + i, nwk_descriptor[i].short_pan_id, nwk_descriptor[i].permit_joining ? "Yes" : "No", nwk_descriptor[i].extended_pan_id[7], + nwk_descriptor[i].extended_pan_id[6], nwk_descriptor[i].extended_pan_id[5], nwk_descriptor[i].extended_pan_id[4], nwk_descriptor[i].extended_pan_id[3], + nwk_descriptor[i].extended_pan_id[2], nwk_descriptor[i].extended_pan_id[1], nwk_descriptor[i].extended_pan_id[0], nwk_descriptor[i].logic_channel, + nwk_descriptor[i].router_capacity ? "Yes" : "No", nwk_descriptor[i].end_device_capacity ? "Yes" : "No" + ); + } + //save scan result and update scan status + //copy network descriptor to _scan_result to keep the data after the callback + Zigbee._scan_result = (esp_zb_network_descriptor_t *)malloc(count * sizeof(esp_zb_network_descriptor_t)); + memcpy(Zigbee._scan_result, nwk_descriptor, count * sizeof(esp_zb_network_descriptor_t)); + Zigbee._scan_status = count; + } else { + log_e("Failed to scan Zigbee network (status: 0x%x)", zdo_status); + Zigbee._scan_status = ZB_SCAN_FAILED; + Zigbee._scan_result = nullptr; + } +} + +void ZigbeeCore::scanNetworks(u_int32_t channel_mask, u_int8_t scan_duration) { + if (!started()) { + log_e("Zigbee stack is not started, cannot scan networks"); + return; + } + if (_scan_status == ZB_SCAN_RUNNING) { + log_w("Scan already in progress, ignoring new scan request"); + return; + } + log_v("Scanning Zigbee networks"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zdo_active_scan_request(channel_mask, scan_duration, scanCompleteCallback); + esp_zb_lock_release(); + _scan_status = ZB_SCAN_RUNNING; +} + +int16_t ZigbeeCore::scanComplete() { + return _scan_status; +} + +zigbee_scan_result_t *ZigbeeCore::getScanResult() { + return _scan_result; +} + +void ZigbeeCore::scanDelete() { + if (_scan_result != nullptr) { + free(_scan_result); + _scan_result = nullptr; + } + _scan_status = ZB_SCAN_FAILED; +} + +// Recall bounded devices from the binding table after reboot or when requested +void ZigbeeCore::bindingTableCb(const esp_zb_zdo_binding_table_info_t *table_info, void *user_ctx) { + esp_zb_zdo_mgmt_bind_param_t *req = (esp_zb_zdo_mgmt_bind_param_t *)user_ctx; + esp_zb_zdp_status_t zdo_status = (esp_zb_zdp_status_t)table_info->status; + log_d("Binding table callback for address 0x%04x with status %d", req->dst_addr, zdo_status); + + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + // Print binding table log simple + log_d("Binding table info: total %d, index %d, count %d", table_info->total, table_info->index, table_info->count); + + if (table_info->total == 0) { + log_d("No binding table entries found"); + // Clear all bound devices since there are no entries + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + log_d("Clearing bound devices for EP %d", (*it)->getEndpoint()); + (*it)->clearBoundDevices(); + } + free(req); + return; + } + + // Create a set to track found devices using both short and IEEE addresses + struct DeviceIdentifier { + uint8_t endpoint; + uint16_t short_addr; + esp_zb_ieee_addr_t ieee_addr; + bool is_ieee; + + bool operator<(const DeviceIdentifier &other) const { + if (endpoint != other.endpoint) { + return endpoint < other.endpoint; + } + if (is_ieee != other.is_ieee) { + return is_ieee < other.is_ieee; + } + if (is_ieee) { + return memcmp(ieee_addr, other.ieee_addr, sizeof(esp_zb_ieee_addr_t)) < 0; + } + return short_addr < other.short_addr; + } + }; + static std::set found_devices; + static std::vector all_records; + + // If this is the first chunk (index 0), clear the previous data + if (table_info->index == 0) { + found_devices.clear(); + all_records.clear(); + } + + // Add current records to our collection + esp_zb_zdo_binding_table_record_t *record = table_info->record; + for (int i = 0; i < table_info->count; i++) { + log_d( + "Processing record %d: src_endp %d, dst_endp %d, cluster_id 0x%04x, dst_addr_mode %d", i, record->src_endp, record->dst_endp, record->cluster_id, + record->dst_addr_mode + ); + all_records.push_back(*record); + record = record->next; + } + + // If this is not the last chunk, request the next one + if (table_info->index + table_info->count < table_info->total) { + log_d("Requesting next chunk of binding table (current index: %d, count: %d, total: %d)", table_info->index, table_info->count, table_info->total); + req->start_index = table_info->index + table_info->count; + esp_zb_zdo_binding_table_req(req, bindingTableCb, req); + } else { + // This is the last chunk, process all records + log_d("Processing final chunk of binding table, total records: %d", all_records.size()); + for (const auto &record : all_records) { + + DeviceIdentifier dev_id; + dev_id.endpoint = record.src_endp; + dev_id.is_ieee = (record.dst_addr_mode == ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT); + + if (dev_id.is_ieee) { + memcpy(dev_id.ieee_addr, record.dst_address.addr_long, sizeof(esp_zb_ieee_addr_t)); + dev_id.short_addr = 0xFFFF; // Invalid short address + } else { + dev_id.short_addr = record.dst_address.addr_short; + memset(dev_id.ieee_addr, 0, sizeof(esp_zb_ieee_addr_t)); + } + + // Track this device as found + found_devices.insert(dev_id); + } + + // Now process each endpoint and update its bound devices + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + log_d("Processing endpoint %d", (*it)->getEndpoint()); + std::list bound_devices = (*it)->getBoundDevices(); + std::list devices_to_remove; + + // First, identify devices that need to be removed + for (std::list::iterator dev_it = bound_devices.begin(); dev_it != bound_devices.end(); ++dev_it) { + DeviceIdentifier dev_id; + dev_id.endpoint = (*it)->getEndpoint(); + + // Create both short and IEEE address identifiers for the device + bool found = false; + + // Check if device exists with short address + if ((*dev_it)->short_addr != 0xFFFF) { + dev_id.is_ieee = false; + dev_id.short_addr = (*dev_it)->short_addr; + memset(dev_id.ieee_addr, 0, sizeof(esp_zb_ieee_addr_t)); + if (found_devices.find(dev_id) != found_devices.end()) { + found = true; + } + } + + // Check if device exists with IEEE address + if (!found) { + dev_id.is_ieee = true; + memcpy(dev_id.ieee_addr, (*dev_it)->ieee_addr, sizeof(esp_zb_ieee_addr_t)); + dev_id.short_addr = 0xFFFF; + if (found_devices.find(dev_id) != found_devices.end()) { + found = true; + } + } + + if (!found) { + devices_to_remove.push_back(*dev_it); + } + } + + // Remove devices that are no longer in the binding table + for (std::list::iterator dev_it = devices_to_remove.begin(); dev_it != devices_to_remove.end(); ++dev_it) { + (*it)->removeBoundDevice(*dev_it); + free(*dev_it); + } + + // Now add new devices from the binding table + for (const auto &record : all_records) { + if (record.src_endp == (*it)->getEndpoint()) { + log_d("Processing binding record for EP %d", record.src_endp); + zb_device_params_t *device = (zb_device_params_t *)calloc(1, sizeof(zb_device_params_t)); + if (!device) { + log_e("Failed to allocate memory for device params"); + continue; + } + device->endpoint = record.dst_endp; + + bool is_ieee = (record.dst_addr_mode == ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT); + if (is_ieee) { + memcpy(device->ieee_addr, record.dst_address.addr_long, sizeof(esp_zb_ieee_addr_t)); + device->short_addr = 0xFFFF; + } else { + device->short_addr = record.dst_address.addr_short; + memset(device->ieee_addr, 0, sizeof(esp_zb_ieee_addr_t)); + } + + // Check if device already exists + bool device_exists = false; + for (std::list::iterator dev_it = bound_devices.begin(); dev_it != bound_devices.end(); ++dev_it) { + if (is_ieee) { + if (memcmp((*dev_it)->ieee_addr, device->ieee_addr, sizeof(esp_zb_ieee_addr_t)) == 0) { + device_exists = true; + break; + } + } else { + if ((*dev_it)->short_addr == device->short_addr) { + device_exists = true; + break; + } + } + } + + if (!device_exists) { + (*it)->addBoundDevice(device); + log_d( + "Device bound to EP %d -> device endpoint: %d, %s: %s", record.src_endp, device->endpoint, is_ieee ? "ieee addr" : "short addr", + is_ieee ? formatIEEEAddress(device->ieee_addr) : formatShortAddress(device->short_addr) + ); + } else { + log_d("Device already exists, freeing allocated memory"); + free(device); // Free the device if it already exists + } + } + } + } + + // Print bound devices + log_d("Filling bounded devices finished"); + free(req); + } + } else { + log_e("Binding table request failed with status: %d", zdo_status); + free(req); + } +} + +void ZigbeeCore::searchBindings() { + esp_zb_zdo_mgmt_bind_param_t *mb_req = (esp_zb_zdo_mgmt_bind_param_t *)malloc(sizeof(esp_zb_zdo_mgmt_bind_param_t)); + mb_req->dst_addr = esp_zb_get_short_address(); + mb_req->start_index = 0; + log_d("Requesting binding table for address 0x%04x", mb_req->dst_addr); + esp_zb_zdo_binding_table_req(mb_req, bindingTableCb, (void *)mb_req); +} + +void ZigbeeCore::resetNVRAMChannelMask() { + _primary_channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK; + esp_zb_set_channel_mask(_primary_channel_mask); + zb_nvram_write_dataset(ZB_NVRAM_COMMON_DATA); + log_v("Channel mask reset to all channels"); +} + +void ZigbeeCore::setNVRAMChannelMask(uint32_t mask) { + _primary_channel_mask = mask; + esp_zb_set_channel_mask(_primary_channel_mask); + zb_nvram_write_dataset(ZB_NVRAM_COMMON_DATA); + log_v("Channel mask set to 0x%08x", mask); +} + +void ZigbeeCore::stop() { + if (started()) { + vTaskSuspend(xTaskGetHandle("Zigbee_main")); + log_v("Zigbee stack stopped"); + _started = false; + } + return; +} + +void ZigbeeCore::start() { + if (!started()) { + vTaskResume(xTaskGetHandle("Zigbee_main")); + log_v("Zigbee stack started"); + _started = true; + } + return; +} + +// Function to convert enum value to string +const char *ZigbeeCore::getDeviceTypeString(esp_zb_ha_standard_devices_t deviceId) { + switch (deviceId) { + case ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID: return "General On/Off switch"; + case ESP_ZB_HA_LEVEL_CONTROL_SWITCH_DEVICE_ID: return "Level Control Switch"; + case ESP_ZB_HA_ON_OFF_OUTPUT_DEVICE_ID: return "General On/Off output"; + case ESP_ZB_HA_LEVEL_CONTROLLABLE_OUTPUT_DEVICE_ID: return "Level Controllable Output"; + case ESP_ZB_HA_SCENE_SELECTOR_DEVICE_ID: return "Scene Selector"; + case ESP_ZB_HA_CONFIGURATION_TOOL_DEVICE_ID: return "Configuration Tool"; + case ESP_ZB_HA_REMOTE_CONTROL_DEVICE_ID: return "Remote Control"; + case ESP_ZB_HA_COMBINED_INTERFACE_DEVICE_ID: return "Combined Interface"; + case ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID: return "Range Extender"; + case ESP_ZB_HA_MAINS_POWER_OUTLET_DEVICE_ID: return "Mains Power Outlet"; + case ESP_ZB_HA_DOOR_LOCK_DEVICE_ID: return "Door lock client"; + case ESP_ZB_HA_DOOR_LOCK_CONTROLLER_DEVICE_ID: return "Door lock controller"; + case ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID: return "Simple Sensor device"; + case ESP_ZB_HA_CONSUMPTION_AWARENESS_DEVICE_ID: return "Consumption Awareness Device"; + case ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID: return "Home Gateway"; + case ESP_ZB_HA_SMART_PLUG_DEVICE_ID: return "Smart plug"; + case ESP_ZB_HA_WHITE_GOODS_DEVICE_ID: return "White Goods"; + case ESP_ZB_HA_METER_INTERFACE_DEVICE_ID: return "Meter Interface"; + case ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID: return "On/Off Light Device"; + case ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID: return "Dimmable Light Device"; + case ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID: return "Color Dimmable Light Device"; + case ESP_ZB_HA_DIMMER_SWITCH_DEVICE_ID: return "Dimmer Switch Device"; + case ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID: return "Color Dimmer Switch Device"; + case ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID: return "Light Sensor"; + case ESP_ZB_HA_SHADE_DEVICE_ID: return "Shade"; + case ESP_ZB_HA_SHADE_CONTROLLER_DEVICE_ID: return "Shade controller"; + case ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID: return "Window Covering client"; + case ESP_ZB_HA_WINDOW_COVERING_CONTROLLER_DEVICE_ID: return "Window Covering controller"; + case ESP_ZB_HA_HEATING_COOLING_UNIT_DEVICE_ID: return "Heating/Cooling Unit device"; + case ESP_ZB_HA_THERMOSTAT_DEVICE_ID: return "Thermostat Device"; + case ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID: return "Temperature Sensor"; + case ESP_ZB_HA_IAS_CONTROL_INDICATING_EQUIPMENT_ID: return "IAS Control and Indicating Equipment"; + case ESP_ZB_HA_IAS_ANCILLARY_CONTROL_EQUIPMENT_ID: return "IAS Ancillary Control Equipment"; + case ESP_ZB_HA_IAS_ZONE_ID: return "IAS Zone"; + case ESP_ZB_HA_IAS_WARNING_DEVICE_ID: return "IAS Warning Device"; + case ESP_ZB_HA_TEST_DEVICE_ID: return "Custom HA device for test"; + case ESP_ZB_HA_CUSTOM_TUNNEL_DEVICE_ID: return "Custom Tunnel device"; + case ESP_ZB_HA_CUSTOM_ATTR_DEVICE_ID: return "Custom Attributes Device"; + default: return "Unknown device type"; + } +} + +void ZigbeeCore::callDefaultResponseCallback(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status, uint8_t endpoint, uint16_t cluster) { + if (_global_default_response_cb) { + _global_default_response_cb(resp_to_cmd, status, endpoint, cluster); + } +} + +ZigbeeCore Zigbee = ZigbeeCore(); + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ZigbeeCore.h b/libraries/Zigbee/src/ZigbeeCore.h new file mode 100644 index 0000000..6295832 --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeCore.h @@ -0,0 +1,237 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Zigbee core class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "esp_zigbee_core.h" +#include "zdo/esp_zigbee_zdo_common.h" +#include "aps/esp_zigbee_aps.h" +#include +#include +#include "ZigbeeTypes.h" +#include "ZigbeeEP.h" +class ZigbeeEP; + +typedef void (*voidFuncPtr)(void); +typedef void (*voidFuncPtrArg)(void *); + +typedef esp_zb_network_descriptor_t zigbee_scan_result_t; + +// enum of Zigbee Roles +typedef enum { + ZIGBEE_COORDINATOR = 0, + ZIGBEE_ROUTER = 1, + ZIGBEE_END_DEVICE = 2 +} zigbee_role_t; + +#define ZB_SCAN_RUNNING (-1) +#define ZB_SCAN_FAILED (-2) + +#define ZB_BEGIN_TIMEOUT_DEFAULT 30000 // 30 seconds + +#define ZIGBEE_DEFAULT_ED_CONFIG() \ + { \ + .esp_zb_role = ESP_ZB_DEVICE_TYPE_ED, .install_code_policy = false, \ + .nwk_cfg = { \ + .zed_cfg = \ + { \ + .ed_timeout = ESP_ZB_ED_AGING_TIMEOUT_64MIN, \ + .keep_alive = 3000, \ + }, \ + }, \ + } + +#define ZIGBEE_DEFAULT_ROUTER_CONFIG() \ + { \ + .esp_zb_role = ESP_ZB_DEVICE_TYPE_ROUTER, .install_code_policy = false, .nwk_cfg = { \ + .zczr_cfg = \ + { \ + .max_children = 10, \ + }, \ + } \ + } + +#define ZIGBEE_DEFAULT_COORDINATOR_CONFIG() \ + { \ + .esp_zb_role = ESP_ZB_DEVICE_TYPE_COORDINATOR, .install_code_policy = false, .nwk_cfg = { \ + .zczr_cfg = \ + { \ + .max_children = 10, \ + }, \ + } \ + } + +#define ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG() \ + { \ + .radio_mode = ZB_RADIO_MODE_UART_RCP, \ + .radio_uart_config = { \ + .port = UART_NUM_1, \ + .rx_pin = GPIO_NUM_NC, \ + .tx_pin = GPIO_NUM_NC, \ + .uart_config = \ + { \ + .baud_rate = 460800, \ + .data_bits = UART_DATA_8_BITS, \ + .parity = UART_PARITY_DISABLE, \ + .stop_bits = UART_STOP_BITS_1, \ + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ + .rx_flow_ctrl_thresh = 0, \ + .source_clk = UART_SCLK_DEFAULT, \ + }, \ + }, \ + } + +class ZigbeeCore { +private: + esp_zb_radio_config_t _radio_config; + esp_zb_host_config_t _host_config; + uint32_t _primary_channel_mask; + uint32_t _begin_timeout; + int16_t _scan_status; + uint8_t _scan_duration; + bool _rx_on_when_idle; + + esp_zb_ep_list_t *_zb_ep_list; + zigbee_role_t _role; + bool _started; + bool _connected; + + uint8_t _open_network; + zigbee_scan_result_t *_scan_result; + SemaphoreHandle_t lock; + bool _debug; + bool _allow_multi_endpoint_binding; + + // Global default response callback + void (*_global_default_response_cb)(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status, uint8_t endpoint, uint16_t cluster); + + bool zigbeeInit(esp_zb_cfg_t *zb_cfg, bool erase_nvs); + static void scanCompleteCallback(esp_zb_zdp_status_t zdo_status, uint8_t count, esp_zb_network_descriptor_t *nwk_descriptor); + const char *getDeviceTypeString(esp_zb_ha_standard_devices_t deviceId); + void searchBindings(); + static void bindingTableCb(const esp_zb_zdo_binding_table_info_t *table_info, void *user_ctx); + void resetNVRAMChannelMask(); // Reset to default mask also in NVRAM + void setNVRAMChannelMask(uint32_t mask); // Set channel mask in NVRAM + +public: + ZigbeeCore(); + ~ZigbeeCore() {} + + std::list ep_objects; + + bool begin(zigbee_role_t role = ZIGBEE_END_DEVICE, bool erase_nvs = false); + bool begin(esp_zb_cfg_t *role_cfg, bool erase_nvs = false); + // bool end(); + void stop(); + void start(); + + bool started() { + return _started; + } + bool connected() { + return _connected; + } + zigbee_role_t getRole() { + return _role; + } + + bool addEndpoint(ZigbeeEP *ep); + //void removeEndpoint(ZigbeeEP *ep); + + void setRadioConfig(esp_zb_radio_config_t config); + esp_zb_radio_config_t getRadioConfig(); + + void setHostConfig(esp_zb_host_config_t config); + esp_zb_host_config_t getHostConfig(); + + void setPrimaryChannelMask(uint32_t mask); // By default all channels are scanned (11-26) -> mask 0x07FFF800 + + void setScanDuration(uint8_t duration); // Can be set from 1 - 4. 1 is fastest, 4 is slowest + uint8_t getScanDuration() { + return _scan_duration; + } + + void setRxOnWhenIdle(bool rx_on_when_idle) { + _rx_on_when_idle = rx_on_when_idle; + } + bool getRxOnWhenIdle() { + return _rx_on_when_idle; + } + void setTimeout(uint32_t timeout) { + _begin_timeout = timeout; + } + void setRebootOpenNetwork(uint8_t time); + void openNetwork(uint8_t time); + void closeNetwork(); + + //scan_duration Time spent scanning each channel, in units of ((1 << scan_duration) + 1) * a beacon time. (15.36 microseconds) + void scanNetworks(uint32_t channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK, uint8_t scan_duration = 5); + // Zigbee scan complete status check, -2: failed or not started, -1: running, 0: no networks found, >0: number of networks found + int16_t scanComplete(); + zigbee_scan_result_t *getScanResult(); + void scanDelete(); + + void factoryReset(bool restart = true); + + void setDebugMode(bool debug) { + _debug = debug; + } + bool getDebugMode() { + return _debug; + } + + void allowMultiEndpointBinding(bool allow) { + _allow_multi_endpoint_binding = allow; + } + bool allowMultiEndpointBinding() { + return _allow_multi_endpoint_binding; + } + + // Set global default response callback + void onGlobalDefaultResponse(void (*callback)(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status, uint8_t endpoint, uint16_t cluster)) { + _global_default_response_cb = callback; + } + + // Call global default response callback (for internal use) + void callDefaultResponseCallback(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status, uint8_t endpoint, uint16_t cluster); + + // Friend function declaration to allow access to private members + friend void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct); + friend bool zb_apsde_data_indication_handler(esp_zb_apsde_data_ind_t ind); + + // Helper functions for formatting addresses + static inline const char *formatIEEEAddress(const esp_zb_ieee_addr_t addr) { + static char buf[24]; + snprintf(buf, sizeof(buf), "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]); + return buf; + } + + static inline const char *formatShortAddress(uint16_t addr) { + static char buf[7]; + snprintf(buf, sizeof(buf), "0x%04X", addr); + return buf; + } +}; + +#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_ZIGBEE) +extern ZigbeeCore Zigbee; +#endif + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ZigbeeEP.cpp b/libraries/Zigbee/src/ZigbeeEP.cpp new file mode 100644 index 0000000..d43bcaf --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeEP.cpp @@ -0,0 +1,709 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Common Class for Zigbee End Point */ + +#include "ZigbeeEP.h" + +#if CONFIG_ZB_ENABLED + +#include "esp_zigbee_cluster.h" +#include "zcl/esp_zigbee_zcl_power_config.h" + +/* Zigbee End Device Class */ +ZigbeeEP::ZigbeeEP(uint8_t endpoint) { + _endpoint = endpoint; + log_v("Endpoint: %d", _endpoint); + _ep_config.endpoint = 0; + _cluster_list = nullptr; + _on_identify = nullptr; + _on_ota_state_change = nullptr; + _on_default_response = nullptr; + _read_model = NULL; + _read_manufacturer = NULL; + _time_status = 0; + _is_bound = false; + _use_manual_binding = false; + _allow_multiple_binding = false; + if (!lock) { + lock = xSemaphoreCreateBinary(); + if (lock == NULL) { + log_e("Semaphore creation failed"); + } + } +} + +void ZigbeeEP::setVersion(uint8_t version) { + _ep_config.app_device_version = version; + + esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (basic_cluster == nullptr) { + log_e("Failed to get basic cluster for application version"); + return; + } + esp_err_t ret = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_APPLICATION_VERSION_ID, (void *)&version); + if (ret != ESP_OK) { + log_e("Failed to add application version to basic cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + } +} + +void ZigbeeEP::setHardwareVersion(uint8_t version) { + esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (basic_cluster == nullptr) { + log_e("Failed to get basic cluster for hardware version"); + return; + } + esp_err_t ret = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_HW_VERSION_ID, (void *)&version); + if (ret != ESP_OK) { + log_e("Failed to add hardware version to basic cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + } +} + +bool ZigbeeEP::setManufacturerAndModel(const char *name, const char *model) { + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_name[ZB_MAX_NAME_LENGTH + 2]; + char zb_model[ZB_MAX_NAME_LENGTH + 2]; + + // Convert manufacturer to ZCL string + size_t name_length = strlen(name); + size_t model_length = strlen(model); + if (name_length > ZB_MAX_NAME_LENGTH || model_length > ZB_MAX_NAME_LENGTH) { + log_e("Manufacturer or model name is too long"); + return false; + } + // Get and check the basic cluster + esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (basic_cluster == nullptr) { + log_e("Failed to get basic cluster"); + return false; + } + // Store the length as the first element + zb_name[0] = static_cast(name_length); // Cast size_t to char + zb_model[0] = static_cast(model_length); + // Use memcpy to copy the characters to the result array + memcpy(zb_name + 1, name, name_length); + memcpy(zb_model + 1, model, model_length); + // Null-terminate the array + zb_name[name_length + 1] = '\0'; + zb_model[model_length + 1] = '\0'; + // Update the manufacturer and model attributes + esp_err_t ret_name = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID, (void *)zb_name); + if (ret_name != ESP_OK) { + log_e("Failed to set manufacturer: 0x%x: %s", ret_name, esp_err_to_name(ret_name)); + } + esp_err_t ret_model = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID, (void *)zb_model); + if (ret_model != ESP_OK) { + log_e("Failed to set model: 0x%x: %s", ret_model, esp_err_to_name(ret_model)); + } + return ret_name == ESP_OK && ret_model == ESP_OK; +} + +bool ZigbeeEP::setPowerSource(zb_power_source_t power_source, uint8_t battery_percentage, uint8_t battery_voltage) { + esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_POWER_SOURCE_ID, (void *)&power_source); + if (ret != ESP_OK) { + log_e("Failed to set power source: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + if (power_source == ZB_POWER_SOURCE_BATTERY) { + // Add power config cluster and battery percentage attribute + if (battery_percentage > 100) { + battery_percentage = 100; + } + battery_percentage = battery_percentage * 2; + esp_zb_attribute_list_t *power_config_cluster = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG); + ret = esp_zb_power_config_cluster_add_attr(power_config_cluster, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID, (void *)&battery_percentage); + if (ret != ESP_OK) { + log_e("Failed to add battery percentage attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_power_config_cluster_add_attr(power_config_cluster, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_VOLTAGE_ID, (void *)&battery_voltage); + if (ret != ESP_OK) { + log_e("Failed to add battery voltage attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_list_add_power_config_cluster(_cluster_list, power_config_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add power config cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } + _power_source = power_source; + return true; +} + +bool ZigbeeEP::setBatteryPercentage(uint8_t percentage) { + // 100% = 200 in decimal, 0% = 0 + // Convert percentage to 0-200 range + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + if (percentage > 100) { + percentage = 100; + } + percentage = percentage * 2; + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID, &percentage, + false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set battery percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + log_v("Battery percentage updated"); + return true; +} + +bool ZigbeeEP::setBatteryVoltage(uint8_t voltage) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_VOLTAGE_ID, &voltage, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set battery voltage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + log_v("Battery voltage updated"); + return true; +} + +bool ZigbeeEP::reportBatteryPercentage() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + memset(&report_attr_cmd, 0, sizeof(report_attr_cmd)); + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to report battery percentage: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Battery percentage reported"); + return true; +} + +char *ZigbeeEP::readManufacturer(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr) { + /* Read peer Manufacture Name & Model Identifier */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + + if (short_addr != 0) { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + } else { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + } + + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BASIC; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID, + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + if (_read_manufacturer != NULL) { + free(_read_manufacturer); + } + _read_manufacturer = NULL; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Wait for response or timeout + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading manufacturer"); + } + return _read_manufacturer; +} + +char *ZigbeeEP::readModel(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr) { + /* Read peer Manufacture Name & Model Identifier */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + + if (short_addr != 0) { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + } else { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + } + + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BASIC; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID, + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + if (_read_model != NULL) { + free(_read_model); + } + _read_model = NULL; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Wait for response or timeout + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading model"); + } + return _read_model; +} + +void ZigbeeEP::printBoundDevices() { + log_i("Bound devices:"); + for ([[maybe_unused]] + const auto &device : _bound_devices) { + log_i( + "Device on endpoint %d, short address: 0x%x, ieee address: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", device->endpoint, device->short_addr, + device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1], + device->ieee_addr[0] + ); + } +} + +void ZigbeeEP::printBoundDevices(Print &print) { + print.println("Bound devices:"); + for ([[maybe_unused]] + const auto &device : _bound_devices) { + print.printf( + "Device on endpoint %d, short address: 0x%x, ieee address: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\r\n", device->endpoint, device->short_addr, + device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1], + device->ieee_addr[0] + ); + } +} + +void ZigbeeEP::zbReadBasicCluster(const esp_zb_zcl_attribute_t *attribute) { + /* Basic cluster attributes */ + if (attribute->id == ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_CHAR_STRING && attribute->data.value) { + zbstring_t *zbstr = (zbstring_t *)attribute->data.value; + _read_manufacturer = (char *)malloc(zbstr->len + 1); + if (_read_manufacturer == NULL) { + log_e("Failed to allocate memory for manufacturer data"); + xSemaphoreGive(lock); + return; + } + memcpy(_read_manufacturer, zbstr->data, zbstr->len); + _read_manufacturer[zbstr->len] = '\0'; + log_i("Peer Manufacturer is \"%s\"", _read_manufacturer); + xSemaphoreGive(lock); + } + if (attribute->id == ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_CHAR_STRING && attribute->data.value) { + zbstring_t *zbstr = (zbstring_t *)attribute->data.value; + _read_model = (char *)malloc(zbstr->len + 1); + if (_read_model == NULL) { + log_e("Failed to allocate memory for model data"); + xSemaphoreGive(lock); + return; + } + memcpy(_read_model, zbstr->data, zbstr->len); + _read_model[zbstr->len] = '\0'; + log_i("Peer Model is \"%s\"", _read_model); + xSemaphoreGive(lock); + } +} + +void ZigbeeEP::zbIdentify(const esp_zb_zcl_set_attr_value_message_t *message) { + if (message->attribute.id == ESP_ZB_ZCL_CMD_IDENTIFY_IDENTIFY_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + if (_on_identify != NULL) { + _on_identify(*(uint16_t *)message->attribute.data.value); + } + } else { + log_w("Other identify commands are not implemented yet."); + } +} + +void ZigbeeEP::zbOTAState(bool otaActive) { + if (_on_ota_state_change != NULL) { + _on_ota_state_change(otaActive); + } +} + +bool ZigbeeEP::addTimeCluster(tm time, int32_t gmt_offset) { + time_t utc_time = 0; + // Check if time is set + if (time.tm_year > 0) { + // Convert time to UTC + utc_time = mktime(&time); + } + + // Create time cluster server attributes + esp_zb_attribute_list_t *time_cluster_server = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_TIME); + esp_err_t ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID, (void *)&gmt_offset); + if (ret != ESP_OK) { + log_e("Failed to add time zone attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_ID, (void *)&utc_time); + if (ret != ESP_OK) { + log_e("Failed to add time attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_STATUS_ID, (void *)&_time_status); + if (ret != ESP_OK) { + log_e("Failed to add time status attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + // Create time cluster client attributes + esp_zb_attribute_list_t *time_cluster_client = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_TIME); + // Add time clusters to cluster list + ret = esp_zb_cluster_list_add_time_cluster(_cluster_list, time_cluster_server, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add time cluster (server role): 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_list_add_time_cluster(_cluster_list, time_cluster_client, ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add time cluster (client role): 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeEP::setTime(tm time) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + time_t utc_time = mktime(&time); + log_d("Setting time to %lld", utc_time); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_ID, &utc_time, false); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set time: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeEP::setTimezone(int32_t gmt_offset) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_d("Setting timezone to %d", gmt_offset); + esp_zb_lock_acquire(portMAX_DELAY); + ret = + esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID, &gmt_offset, false); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set timezone: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +tm ZigbeeEP::getTime(uint8_t endpoint, int32_t short_addr, esp_zb_ieee_addr_t ieee_addr) { + /* Read peer time */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + + if (short_addr >= 0) { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = (uint16_t)short_addr; + } else { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + } + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TIME_TIME_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TIME; + + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + + // clear read time + _read_time = 0; + + log_v("Reading time from endpoint %d", endpoint); + esp_zb_zcl_read_attr_cmd_req(&read_req); + + //Wait for response or timeout + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading time"); + return tm(); + } + + struct tm *timeinfo = localtime(&_read_time); + if (timeinfo) { + // Update time + setTime(*timeinfo); + // Update time status to synced + _time_status |= 0x02; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_STATUS_ID, &_time_status, false + ); + esp_zb_lock_release(); + + return *timeinfo; + } else { + log_e("Error while converting time"); + return tm(); + } +} + +int32_t ZigbeeEP::getTimezone(uint8_t endpoint, int32_t short_addr, esp_zb_ieee_addr_t ieee_addr) { + /* Read peer timezone */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + + if (short_addr >= 0) { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = (uint16_t)short_addr; + } else { + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + } + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TIME; + + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + + // clear read timezone + _read_timezone = 0; + + log_v("Reading timezone from endpoint %d", endpoint); + esp_zb_zcl_read_attr_cmd_req(&read_req); + + //Wait for response or timeout + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading timezone"); + return 0; + } + setTimezone(_read_timezone); + return _read_timezone; +} + +void ZigbeeEP::zbReadTimeCluster(const esp_zb_zcl_attribute_t *attribute) { + /* Time cluster attributes */ + if (attribute->id == ESP_ZB_ZCL_ATTR_TIME_TIME_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_UTC_TIME) { + log_v("Time attribute received"); + log_v("Time: %lld", *(uint32_t *)attribute->data.value); + _read_time = *(uint32_t *)attribute->data.value; + xSemaphoreGive(lock); + } else if (attribute->id == ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S32) { + log_v("Timezone attribute received"); + log_v("Timezone: %d", *(int32_t *)attribute->data.value); + _read_timezone = *(int32_t *)attribute->data.value; + xSemaphoreGive(lock); + } +} + +// typedef struct esp_zb_ota_cluster_cfg_s { +// uint32_t ota_upgrade_file_version; /*!< The attribute indicates the file version of the running firmware image on the device */ +// uint16_t ota_upgrade_manufacturer; /*!< The attribute indicates the value for the manufacturer of the device */ +// uint16_t ota_upgrade_image_type; /*!< The attribute indicates the the image type of the file that the client is currently downloading */ +// uint32_t ota_upgrade_downloaded_file_ver; /*!< The attribute indicates the file version of the downloaded image on the device*/ +// esp_zb_ota_cluster_cfg_t; + +// typedef struct esp_zb_zcl_ota_upgrade_client_variable_s { +// uint16_t timer_query; /*!< The field indicates the time of querying OTA image for OTA upgrade client */ +// uint16_t hw_version; /*!< The hardware version */ +// uint8_t max_data_size; /*!< The maximum size of OTA data */ +// } esp_zb_zcl_ota_upgrade_client_variable_t; + +bool ZigbeeEP::addOTAClient( + uint32_t file_version, uint32_t downloaded_file_ver, uint16_t hw_version, uint16_t manufacturer, uint16_t image_type, uint8_t max_data_size +) { + + esp_zb_ota_cluster_cfg_t ota_cluster_cfg = {}; + ota_cluster_cfg.ota_upgrade_file_version = file_version; //OTA_UPGRADE_RUNNING_FILE_VERSION; + ota_cluster_cfg.ota_upgrade_downloaded_file_ver = downloaded_file_ver; //OTA_UPGRADE_DOWNLOADED_FILE_VERSION; + ota_cluster_cfg.ota_upgrade_manufacturer = manufacturer; //OTA_UPGRADE_MANUFACTURER; + ota_cluster_cfg.ota_upgrade_image_type = image_type; //OTA_UPGRADE_IMAGE_TYPE; + + esp_zb_attribute_list_t *ota_cluster = esp_zb_ota_cluster_create(&ota_cluster_cfg); + + esp_zb_zcl_ota_upgrade_client_variable_t variable_config = {}; + variable_config.timer_query = ESP_ZB_ZCL_OTA_UPGRADE_QUERY_TIMER_COUNT_DEF; + variable_config.hw_version = hw_version; //OTA_UPGRADE_HW_VERSION; + variable_config.max_data_size = max_data_size; //OTA_UPGRADE_MAX_DATA_SIZE; + + uint16_t ota_upgrade_server_addr = 0xffff; + uint8_t ota_upgrade_server_ep = 0xff; + + esp_err_t ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_CLIENT_DATA_ID, (void *)&variable_config); + if (ret != ESP_OK) { + log_e("Failed to add OTA client data: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_SERVER_ADDR_ID, (void *)&ota_upgrade_server_addr); + if (ret != ESP_OK) { + log_e("Failed to add OTA server address: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_SERVER_ENDPOINT_ID, (void *)&ota_upgrade_server_ep); + if (ret != ESP_OK) { + log_e("Failed to add OTA server endpoint: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_list_add_ota_cluster(_cluster_list, ota_cluster, ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add OTA cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +static void findOTAServer(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + esp_zb_ota_upgrade_client_query_interval_set(*((uint8_t *)user_ctx), OTA_UPGRADE_QUERY_INTERVAL); + esp_zb_ota_upgrade_client_query_image_req(addr, endpoint); + log_i("Query OTA upgrade from server endpoint: %d after %d seconds", endpoint, OTA_UPGRADE_QUERY_INTERVAL); + } else { + log_w("No OTA Server found"); + } +} + +void ZigbeeEP::requestOTAUpdate() { + esp_zb_zdo_match_desc_req_param_t req; + memset(&req, 0, sizeof(req)); + uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_OTA_UPGRADE}; + + /* Match the OTA server of coordinator */ + req.addr_of_interest = 0x0000; + req.dst_nwk_addr = 0x0000; + req.num_in_clusters = 1; + req.num_out_clusters = 0; + req.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + req.cluster_list = cluster_list; + esp_zb_lock_acquire(portMAX_DELAY); + if (esp_zb_bdb_dev_joined()) { + esp_zb_zdo_match_cluster(&req, findOTAServer, &_endpoint); + } + esp_zb_lock_release(); +} + +void ZigbeeEP::removeBoundDevice(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + log_d( + "Attempting to remove device with endpoint %d and IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + + for (std::list::iterator it = _bound_devices.begin(); it != _bound_devices.end(); ++it) { + if ((*it)->endpoint == endpoint && memcmp((*it)->ieee_addr, ieee_addr, sizeof(esp_zb_ieee_addr_t)) == 0) { + log_d("Found matching device, removing it"); + _bound_devices.erase(it); + if (_bound_devices.empty()) { + _is_bound = false; + } + return; + } + } + log_w("No matching device found for removal"); +} + +void ZigbeeEP::removeBoundDevice(zb_device_params_t *device) { + if (!device) { + log_e("Invalid device parameters provided"); + return; + } + + log_d( + "Attempting to remove device with endpoint %d, short address 0x%04x, IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", device->endpoint, + device->short_addr, device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], + device->ieee_addr[1], device->ieee_addr[0] + ); + + for (std::list::iterator it = _bound_devices.begin(); it != _bound_devices.end(); ++it) { + bool endpoint_matches = ((*it)->endpoint == device->endpoint); + bool short_addr_matches = (device->short_addr != 0xFFFF && (*it)->short_addr == device->short_addr); + bool ieee_addr_matches = (memcmp((*it)->ieee_addr, device->ieee_addr, sizeof(esp_zb_ieee_addr_t)) == 0); + + if (endpoint_matches && (short_addr_matches || ieee_addr_matches)) { + log_d("Found matching device by %s, removing it", short_addr_matches ? "short address" : "IEEE address"); + _bound_devices.erase(it); + if (_bound_devices.empty()) { + _is_bound = false; + } + return; + } + } + log_w("No matching device found for removal"); +} + +void ZigbeeEP::zbDefaultResponse(const esp_zb_zcl_cmd_default_resp_message_t *message) { + log_v("Default response received for endpoint %d", _endpoint); + log_v("Status code: %s", esp_zb_zcl_status_to_name(message->status_code)); + log_v("Response to command: %d", message->resp_to_cmd); + if (_on_default_response) { + _on_default_response((zb_cmd_type_t)message->resp_to_cmd, message->status_code); + } +} + +// Global function implementation +const char *esp_zb_zcl_status_to_name(esp_zb_zcl_status_t status) { + switch (status) { + case ESP_ZB_ZCL_STATUS_SUCCESS: return "Success"; + case ESP_ZB_ZCL_STATUS_FAIL: return "Fail"; + case ESP_ZB_ZCL_STATUS_NOT_AUTHORIZED: return "Not authorized"; + case ESP_ZB_ZCL_STATUS_MALFORMED_CMD: return "Malformed command"; + case ESP_ZB_ZCL_STATUS_UNSUP_CLUST_CMD: return "Unsupported cluster command"; + case ESP_ZB_ZCL_STATUS_UNSUP_GEN_CMD: return "Unsupported general command"; + case ESP_ZB_ZCL_STATUS_UNSUP_MANUF_CLUST_CMD: return "Unsupported manufacturer cluster command"; + case ESP_ZB_ZCL_STATUS_UNSUP_MANUF_GEN_CMD: return "Unsupported manufacturer general command"; + case ESP_ZB_ZCL_STATUS_INVALID_FIELD: return "Invalid field"; + case ESP_ZB_ZCL_STATUS_UNSUP_ATTRIB: return "Unsupported attribute"; + case ESP_ZB_ZCL_STATUS_INVALID_VALUE: return "Invalid value"; + case ESP_ZB_ZCL_STATUS_READ_ONLY: return "Read only"; + case ESP_ZB_ZCL_STATUS_INSUFF_SPACE: return "Insufficient space"; + case ESP_ZB_ZCL_STATUS_DUPE_EXISTS: return "Duplicate exists"; + case ESP_ZB_ZCL_STATUS_NOT_FOUND: return "Not found"; + case ESP_ZB_ZCL_STATUS_UNREPORTABLE_ATTRIB: return "Unreportable attribute"; + case ESP_ZB_ZCL_STATUS_INVALID_TYPE: return "Invalid type"; + case ESP_ZB_ZCL_STATUS_WRITE_ONLY: return "Write only"; + case ESP_ZB_ZCL_STATUS_INCONSISTENT: return "Inconsistent"; + case ESP_ZB_ZCL_STATUS_ACTION_DENIED: return "Action denied"; + case ESP_ZB_ZCL_STATUS_TIMEOUT: return "Timeout"; + case ESP_ZB_ZCL_STATUS_ABORT: return "Abort"; + case ESP_ZB_ZCL_STATUS_INVALID_IMAGE: return "Invalid OTA upgrade image"; + case ESP_ZB_ZCL_STATUS_WAIT_FOR_DATA: return "Server does not have data block available yet"; + case ESP_ZB_ZCL_STATUS_NO_IMAGE_AVAILABLE: return "No image available"; + case ESP_ZB_ZCL_STATUS_REQUIRE_MORE_IMAGE: return "Require more image"; + case ESP_ZB_ZCL_STATUS_NOTIFICATION_PENDING: return "Notification pending"; + case ESP_ZB_ZCL_STATUS_HW_FAIL: return "Hardware failure"; + case ESP_ZB_ZCL_STATUS_SW_FAIL: return "Software failure"; + case ESP_ZB_ZCL_STATUS_CALIB_ERR: return "Calibration error"; + case ESP_ZB_ZCL_STATUS_UNSUP_CLUST: return "Cluster is not found on the target endpoint"; + case ESP_ZB_ZCL_STATUS_LIMIT_REACHED: return "Limit reached"; + default: return "Unknown status"; + } +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ZigbeeEP.h b/libraries/Zigbee/src/ZigbeeEP.h new file mode 100644 index 0000000..b146433 --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeEP.h @@ -0,0 +1,219 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Common Class for Zigbee End point */ + +#pragma once + +#include "ZigbeeCore.h" +#if CONFIG_ZB_ENABLED + +#include +#include + +/* Useful defines */ +#define ZB_CMD_TIMEOUT 10000 // 10 seconds +#define OTA_UPGRADE_QUERY_INTERVAL (1 * 60) // 1 hour = 60 minutes + +#define ZB_ARRAY_LENGHT(arr) (sizeof(arr) / sizeof(arr[0])) + +#define RGB_TO_XYZ(r, g, b, X, Y, Z) \ + { \ + X = (float)(0.412453 * (r) + 0.357580 * (g) + 0.180423 * (b)); \ + Y = (float)(0.212671 * (r) + 0.715160 * (g) + 0.072169 * (b)); \ + Z = (float)(0.019334 * (r) + 0.119193 * (g) + 0.950227 * (b)); \ + } + +typedef struct zbstring_s { + uint8_t len; + char data[]; +} ESP_ZB_PACKED_STRUCT zbstring_t; + +typedef struct zb_device_params_s { + esp_zb_ieee_addr_t ieee_addr; + uint8_t endpoint; + uint16_t short_addr; +} zb_device_params_t; + +typedef enum { + ZB_POWER_SOURCE_UNKNOWN = 0x00, + ZB_POWER_SOURCE_MAINS = 0x01, + ZB_POWER_SOURCE_BATTERY = 0x03, +} zb_power_source_t; + +// Global function for converting ZCL status to name +const char *esp_zb_zcl_status_to_name(esp_zb_zcl_status_t status); + +/* Zigbee End Device Class */ +class ZigbeeEP { +public: + // constants and limits + static constexpr size_t ZB_MAX_NAME_LENGTH = 32; + + // constructors and destructor + ZigbeeEP(uint8_t endpoint = 10); + ~ZigbeeEP() {} + + // Set ep config and cluster list + void setEpConfig(esp_zb_endpoint_config_t ep_config, esp_zb_cluster_list_t *cluster_list) { + _ep_config = ep_config; + _cluster_list = cluster_list; + } + + // Set application version and hardware version + void setVersion(uint8_t version); + void setHardwareVersion(uint8_t version); + + uint8_t getEndpoint() { + return _endpoint; + } + + void printBoundDevices(); + void printBoundDevices(Print &print); + + std::list getBoundDevices() const { + return _bound_devices; + } + + bool bound() { + return _is_bound; + } + void allowMultipleBinding(bool bind) { + _allow_multiple_binding = bind; + } + void setManualBinding(bool bind) { + _use_manual_binding = bind; + } + + // Set Manufacturer name and model + bool setManufacturerAndModel(const char *name, const char *model); + + // Methods to read manufacturer and model name from selected endpoint and short address + char *readManufacturer(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr); + char *readModel(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr); + + // Set Power source and battery percentage for battery powered devices + bool setPowerSource(zb_power_source_t power_source, uint8_t percentage = 0xff, uint8_t voltage = 0xff); // voltage in 100mV + bool setBatteryPercentage(uint8_t percentage); // 0-100 % + bool setBatteryVoltage(uint8_t voltage); // voltage in 100mV (example value 35 for 3.5V) + bool reportBatteryPercentage(); // battery voltage is not reportable attribute + + // Set time + bool addTimeCluster(tm time = {}, int32_t gmt_offset = 0); // gmt offset in seconds + bool setTime(tm time); + bool setTimezone(int32_t gmt_offset); + + // Get time from Coordinator or specific endpoint (blocking until response) + struct tm getTime(uint8_t endpoint = 1, int32_t short_addr = 0x0000, esp_zb_ieee_addr_t ieee_addr = {0}); + int32_t getTimezone(uint8_t endpoint = 1, int32_t short_addr = 0x0000, esp_zb_ieee_addr_t ieee_addr = {0}); // gmt offset in seconds + + bool epAllowMultipleBinding() { + return _allow_multiple_binding; + } + bool epUseManualBinding() { + return _use_manual_binding; + } + + // OTA methods + /** + * @brief Add OTA client to the Zigbee endpoint. + * + * @param file_version The current file version of the OTA client. + * @param downloaded_file_ver The version of the downloaded file. + * @param hw_version The hardware version of the device. + * @param manufacturer The manufacturer code (default: 0x1001). + * @param image_type The image type code (default: 0x1011). + * @param max_data_size The maximum data size for OTA transfer (default and recommended: 223). + * @return true if the OTA client was added successfully, false otherwise. + */ + bool addOTAClient( + uint32_t file_version, uint32_t downloaded_file_ver, uint16_t hw_version, uint16_t manufacturer = 0x1001, uint16_t image_type = 0x1011, + uint8_t max_data_size = 223 + ); + /** + * @brief Request OTA update from the server, first request is within a minute and the next requests are sent every hour automatically. + */ + void requestOTAUpdate(); + + // findEndpoint may be implemented by EPs to find and bind devices + virtual void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) {}; + + // list of all handlers function calls, to be override by EPs implementation + virtual void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {}; + virtual void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) {}; + virtual void + zbWriteAttributeResponse(uint16_t cluster_id, uint16_t attribute_id, esp_zb_zcl_status_t status, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) {}; + virtual void zbReadBasicCluster(const esp_zb_zcl_attribute_t *attribute); //already implemented + virtual void zbIdentify(const esp_zb_zcl_set_attr_value_message_t *message); + virtual void zbOTAState(bool otaActive); + virtual void zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) {}; + virtual void zbReadTimeCluster(const esp_zb_zcl_attribute_t *attribute); //already implemented + virtual void zbIASZoneStatusChangeNotification(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message) {}; + virtual void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {}; + virtual void zbDefaultResponse(const esp_zb_zcl_cmd_default_resp_message_t *message); //already implemented + + virtual void addBoundDevice(zb_device_params_t *device) { + _bound_devices.push_back(device); + _is_bound = true; + } + + virtual void removeBoundDevice(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + virtual void removeBoundDevice(zb_device_params_t *device); + + virtual void clearBoundDevices() { + _bound_devices.clear(); + _is_bound = false; + } + + void onIdentify(void (*callback)(uint16_t)) { + _on_identify = callback; + } + + void onOTAStateChange(void (*callback)(bool state)) { + _on_ota_state_change = callback; + } + + void onDefaultResponse(void (*callback)(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status)) { + _on_default_response = callback; + } + + // Convert ZCL status to name + +private: + char *_read_manufacturer; + char *_read_model; + void (*_on_identify)(uint16_t time); + void (*_on_ota_state_change)(bool state); + void (*_on_default_response)(zb_cmd_type_t resp_to_cmd, esp_zb_zcl_status_t status); + time_t _read_time; + int32_t _read_timezone; + +protected: + uint8_t _endpoint; + esp_zb_ha_standard_devices_t _device_id; + esp_zb_endpoint_config_t _ep_config; + esp_zb_cluster_list_t *_cluster_list; + bool _is_bound; + bool _allow_multiple_binding; + bool _use_manual_binding; + std::list _bound_devices; + SemaphoreHandle_t lock; + zb_power_source_t _power_source; + uint8_t _time_status; + + // Friend class declaration to allow access to protected members + friend class ZigbeeCore; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ZigbeeHandlers.cpp b/libraries/Zigbee/src/ZigbeeHandlers.cpp new file mode 100644 index 0000000..9b574ea --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeHandlers.cpp @@ -0,0 +1,475 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Zigbee Common Functions */ +#include "ZigbeeCore.h" +#include "Arduino.h" + +#if CONFIG_ZB_ENABLED + +#include "esp_ota_ops.h" +#if CONFIG_ZB_DELTA_OTA // Delta OTA, code is prepared for this feature but not enabled by default +#include "esp_delta_ota_ops.h" +#endif + +//OTA Upgrade defines and variables +#define OTA_ELEMENT_HEADER_LEN 6 /* OTA element format header size include tag identifier and length field */ + +/** + * @name Enumeration for the tag identifier denotes the type and format of the data within the element + * @anchor esp_ota_element_tag_id_t + */ +typedef enum esp_ota_element_tag_id_e { + UPGRADE_IMAGE = 0x0000, /*!< Upgrade image */ +} esp_ota_element_tag_id_t; + +static const esp_partition_t *s_ota_partition = NULL; +static esp_ota_handle_t s_ota_handle = 0; +static bool s_tagid_received = false; + +// forward declaration of all implemented handlers +static esp_err_t zb_attribute_set_handler(const esp_zb_zcl_set_attr_value_message_t *message); +static esp_err_t zb_attribute_reporting_handler(const esp_zb_zcl_report_attr_message_t *message); +static esp_err_t zb_cmd_read_attr_resp_handler(const esp_zb_zcl_cmd_read_attr_resp_message_t *message); +static esp_err_t zb_cmd_write_attr_resp_handler(const esp_zb_zcl_cmd_write_attr_resp_message_t *message); +static esp_err_t zb_configure_report_resp_handler(const esp_zb_zcl_cmd_config_report_resp_message_t *message); +static esp_err_t zb_cmd_ias_zone_status_change_handler(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message); +static esp_err_t zb_cmd_ias_zone_enroll_response_handler(const esp_zb_zcl_ias_zone_enroll_response_message_t *message); +static esp_err_t zb_cmd_default_resp_handler(const esp_zb_zcl_cmd_default_resp_message_t *message); +static esp_err_t zb_window_covering_movement_resp_handler(const esp_zb_zcl_window_covering_movement_message_t *message); +static esp_err_t zb_ota_upgrade_status_handler(const esp_zb_zcl_ota_upgrade_value_message_t *message); +static esp_err_t zb_ota_upgrade_query_image_resp_handler(const esp_zb_zcl_ota_upgrade_query_image_resp_message_t *message); + +// Zigbee action handlers +[[maybe_unused]] +static esp_err_t zb_action_handler(esp_zb_core_action_callback_id_t callback_id, const void *message) { + esp_err_t ret = ESP_OK; + switch (callback_id) { + case ESP_ZB_CORE_SET_ATTR_VALUE_CB_ID: ret = zb_attribute_set_handler((esp_zb_zcl_set_attr_value_message_t *)message); break; + case ESP_ZB_CORE_REPORT_ATTR_CB_ID: ret = zb_attribute_reporting_handler((esp_zb_zcl_report_attr_message_t *)message); break; + case ESP_ZB_CORE_CMD_READ_ATTR_RESP_CB_ID: ret = zb_cmd_read_attr_resp_handler((esp_zb_zcl_cmd_read_attr_resp_message_t *)message); break; + case ESP_ZB_CORE_CMD_REPORT_CONFIG_RESP_CB_ID: ret = zb_configure_report_resp_handler((esp_zb_zcl_cmd_config_report_resp_message_t *)message); break; + case ESP_ZB_CORE_CMD_IAS_ZONE_ZONE_STATUS_CHANGE_NOT_ID: + ret = zb_cmd_ias_zone_status_change_handler((esp_zb_zcl_ias_zone_status_change_notification_message_t *)message); + break; + case ESP_ZB_CORE_IAS_ZONE_ENROLL_RESPONSE_VALUE_CB_ID: + ret = zb_cmd_ias_zone_enroll_response_handler((esp_zb_zcl_ias_zone_enroll_response_message_t *)message); + break; + case ESP_ZB_CORE_WINDOW_COVERING_MOVEMENT_CB_ID: + ret = zb_window_covering_movement_resp_handler((esp_zb_zcl_window_covering_movement_message_t *)message); + break; + case ESP_ZB_CORE_OTA_UPGRADE_VALUE_CB_ID: ret = zb_ota_upgrade_status_handler((esp_zb_zcl_ota_upgrade_value_message_t *)message); break; + case ESP_ZB_CORE_OTA_UPGRADE_QUERY_IMAGE_RESP_CB_ID: + ret = zb_ota_upgrade_query_image_resp_handler((esp_zb_zcl_ota_upgrade_query_image_resp_message_t *)message); + break; + case ESP_ZB_CORE_CMD_DEFAULT_RESP_CB_ID: ret = zb_cmd_default_resp_handler((esp_zb_zcl_cmd_default_resp_message_t *)message); break; + case ESP_ZB_CORE_CMD_WRITE_ATTR_RESP_CB_ID: ret = zb_cmd_write_attr_resp_handler((esp_zb_zcl_cmd_write_attr_resp_message_t *)message); break; + default: log_w("Receive unhandled Zigbee action(0x%x) callback", callback_id); break; + } + return ret; +} + +static esp_err_t zb_attribute_set_handler(const esp_zb_zcl_set_attr_value_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + + log_v( + "Received message: endpoint(%d), cluster(0x%x), attribute(0x%x), data size(%d)", message->info.dst_endpoint, message->info.cluster, message->attribute.id, + message->attribute.data.size + ); + + // List through all Zigbee EPs and call the callback function, with the message + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY) { + (*it)->zbIdentify(message); //method zbIdentify implemented in the common EP class + } else { + (*it)->zbAttributeSet(message); //method zbAttributeSet must be implemented in specific EP class + } + } + } + return ESP_OK; +} + +static esp_err_t zb_attribute_reporting_handler(const esp_zb_zcl_report_attr_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->status); + return ESP_ERR_INVALID_ARG; + } + log_v( + "Received report from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->src_address.u.short_addr, message->src_endpoint, + message->dst_endpoint, message->cluster + ); + // List through all Zigbee EPs and call the callback function, with the message + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->dst_endpoint == (*it)->getEndpoint()) { + (*it)->zbAttributeRead( + message->cluster, &message->attribute, message->src_endpoint, message->src_address + ); //method zbAttributeRead must be implemented in specific EP class + } + } + return ESP_OK; +} + +static esp_err_t zb_cmd_read_attr_resp_handler(const esp_zb_zcl_cmd_read_attr_resp_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + log_v( + "Read attribute response: from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->info.src_address.u.short_addr, + message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster + ); + + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + esp_zb_zcl_read_attr_resp_variable_t *variable = message->variables; + while (variable) { + log_v( + "Read attribute response: status(%d), cluster(0x%x), attribute(0x%x), type(0x%x), value(%d)", variable->status, message->info.cluster, + variable->attribute.id, variable->attribute.data.type, variable->attribute.data.value ? *(uint8_t *)variable->attribute.data.value : 0 + ); + if (variable->status == ESP_ZB_ZCL_STATUS_SUCCESS) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_BASIC) { + (*it)->zbReadBasicCluster(&variable->attribute); //method zbReadBasicCluster implemented in the common EP class + } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_TIME) { + (*it)->zbReadTimeCluster(&variable->attribute); //method zbReadTimeCluster implemented in the common EP class + } else { + (*it)->zbAttributeRead( + message->info.cluster, &variable->attribute, message->info.src_endpoint, message->info.src_address + ); //method zbAttributeRead must be implemented in specific EP class + } + } + variable = variable->next; + } + } + } + return ESP_OK; +} + +static esp_err_t zb_cmd_write_attr_resp_handler(const esp_zb_zcl_cmd_write_attr_resp_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + log_v( + "Write attribute response: from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->info.src_address.u.short_addr, + message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster + ); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + esp_zb_zcl_write_attr_resp_variable_t *variable = message->variables; + while (variable) { + log_v("Write attribute response: status(%d), cluster(0x%x), attribute(0x%x)", variable->status, message->info.cluster, variable->attribute_id); + if (variable->status == ESP_ZB_ZCL_STATUS_SUCCESS) { + (*it)->zbWriteAttributeResponse( + message->info.cluster, variable->attribute_id, variable->status, message->info.src_endpoint, message->info.src_address + ); + } + variable = variable->next; + } + } + } + return ESP_OK; +} + +static esp_err_t zb_configure_report_resp_handler(const esp_zb_zcl_cmd_config_report_resp_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + esp_zb_zcl_config_report_resp_variable_t *variable = message->variables; + while (variable) { + log_v( + "Configure report response: status(%d), cluster(0x%x), direction(0x%x), attribute(0x%x)", variable->status, message->info.cluster, variable->direction, + variable->attribute_id + ); + variable = variable->next; + } + return ESP_OK; +} + +static esp_err_t zb_cmd_ias_zone_status_change_handler(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + log_v( + "IAS Zone Status Notification: from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->info.src_address.u.short_addr, + message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster + ); + + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + (*it)->zbIASZoneStatusChangeNotification(message); + } + } + return ESP_OK; +} + +static esp_err_t zb_cmd_ias_zone_enroll_response_handler(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + log_v("IAS Zone Enroll Response received"); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + (*it)->zbIASZoneEnrollResponse(message); + } + } + return ESP_OK; +} + +static esp_err_t zb_window_covering_movement_resp_handler(const esp_zb_zcl_window_covering_movement_message_t *message) { + if (!message) { + log_e("Empty message"); + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + } + + log_v( + "Received message: endpoint(%d), cluster(0x%x), command(0x%x), payload(%d)", message->info.dst_endpoint, message->info.cluster, message->command, + message->payload + ); + + // List through all Zigbee EPs and call the callback function, with the message + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + (*it)->zbWindowCoveringMovementCmd(message); //method zbWindowCoveringMovementCmd must be implemented in specific EP class + } + } + return ESP_OK; +} + +static esp_err_t esp_element_ota_data(uint32_t total_size, const void *payload, uint16_t payload_size, void **outbuf, uint16_t *outlen) { + static uint16_t tagid = 0; + void *data_buf = NULL; + uint16_t data_len; + + if (!s_tagid_received) { + uint32_t length = 0; + if (!payload || payload_size <= OTA_ELEMENT_HEADER_LEN) { + log_e("Invalid element format"); + return ESP_ERR_INVALID_ARG; + } + + const uint8_t *payload_ptr = (const uint8_t *)payload; + tagid = *(const uint16_t *)payload_ptr; + length = *(const uint32_t *)(payload_ptr + sizeof(tagid)); + if ((length + OTA_ELEMENT_HEADER_LEN) != total_size) { + log_e("Invalid element length [%ld/%ld]", length, total_size); + return ESP_ERR_INVALID_ARG; + } + + s_tagid_received = true; + + data_buf = (void *)(payload_ptr + OTA_ELEMENT_HEADER_LEN); + data_len = payload_size - OTA_ELEMENT_HEADER_LEN; + } else { + data_buf = (void *)payload; + data_len = payload_size; + } + + switch (tagid) { + case UPGRADE_IMAGE: + *outbuf = data_buf; + *outlen = data_len; + break; + default: + log_e("Unsupported element tag identifier %d", tagid); + return ESP_ERR_INVALID_ARG; + break; + } + + return ESP_OK; +} + +static esp_err_t zb_ota_upgrade_status_handler(const esp_zb_zcl_ota_upgrade_value_message_t *message) { + static uint32_t total_size = 0; + static uint32_t offset = 0; + [[maybe_unused]] + static int64_t start_time = 0; + esp_err_t ret = ESP_OK; + + if (message->info.status == ESP_ZB_ZCL_STATUS_SUCCESS) { + switch (message->upgrade_status) { + case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_START: + log_i("Zigbee - OTA upgrade start"); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + (*it)->zbOTAState(true); // Notify that OTA is active + } + start_time = esp_timer_get_time(); + s_ota_partition = esp_ota_get_next_update_partition(NULL); + assert(s_ota_partition); +#if CONFIG_ZB_DELTA_OTA + ret = esp_delta_ota_begin(s_ota_partition, 0, &s_ota_handle); +#else + ret = esp_ota_begin(s_ota_partition, 0, &s_ota_handle); +#endif + if (ret != ESP_OK) { + log_e("Zigbee - Failed to begin OTA partition, status: %s", esp_err_to_name(ret)); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + (*it)->zbOTAState(false); // Notify that OTA is no longer active + } + return ret; + } + break; + case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_RECEIVE: + total_size = message->ota_header.image_size; + offset += message->payload_size; + log_i("Zigbee - OTA Client receives data: progress [%ld/%ld]", offset, total_size); + if (message->payload_size && message->payload) { + uint16_t payload_size = 0; + void *payload = NULL; + ret = esp_element_ota_data(total_size, message->payload, message->payload_size, &payload, &payload_size); + if (ret != ESP_OK) { + log_e("Zigbee - Failed to element OTA data, status: %s", esp_err_to_name(ret)); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + (*it)->zbOTAState(false); // Notify that OTA is no longer active + } + return ret; + } +#if CONFIG_ZB_DELTA_OTA + ret = esp_delta_ota_write(s_ota_handle, payload, payload_size); +#else + ret = esp_ota_write(s_ota_handle, (const void *)payload, payload_size); +#endif + if (ret != ESP_OK) { + log_e("Zigbee - Failed to write OTA data to partition, status: %s", esp_err_to_name(ret)); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + (*it)->zbOTAState(false); // Notify that OTA is no longer active + } + return ret; + } + } + break; + case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_APPLY: log_i("Zigbee - OTA upgrade apply"); break; + case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_CHECK: + ret = offset == total_size ? ESP_OK : ESP_FAIL; + offset = 0; + total_size = 0; + s_tagid_received = false; + log_i("Zigbee - OTA upgrade check status: %s", esp_err_to_name(ret)); + break; + case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_FINISH: + log_i("Zigbee - OTA Finish"); + log_i( + "Zigbee - OTA Information: version: 0x%lx, manufacturer code: 0x%x, image type: 0x%x, total size: %ld bytes, cost time: %lld ms,", + message->ota_header.file_version, message->ota_header.manufacturer_code, message->ota_header.image_type, message->ota_header.image_size, + (esp_timer_get_time() - start_time) / 1000 + ); + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + (*it)->zbOTAState(false); // Notify that OTA is no longer active + } +#if CONFIG_ZB_DELTA_OTA + ret = esp_delta_ota_end(s_ota_handle); +#else + ret = esp_ota_end(s_ota_handle); +#endif + if (ret != ESP_OK) { + log_e("Zigbee - Failed to end OTA partition, status: %s", esp_err_to_name(ret)); + return ret; + } + ret = esp_ota_set_boot_partition(s_ota_partition); + if (ret != ESP_OK) { + log_e("Zigbee - Failed to set OTA boot partition, status: %s", esp_err_to_name(ret)); + return ret; + } + log_w("Zigbee - Prepare to restart system"); + esp_restart(); + break; + default: log_i("Zigbee - OTA status: %d", message->upgrade_status); break; + } + } + return ret; +} + +static esp_err_t zb_ota_upgrade_query_image_resp_handler(const esp_zb_zcl_ota_upgrade_query_image_resp_message_t *message) { + if (message->info.status == ESP_ZB_ZCL_STATUS_SUCCESS) { + log_i("Zigbee - Queried OTA image from address: 0x%04hx, endpoint: %d", message->server_addr.u.short_addr, message->server_endpoint); + log_i("Zigbee - Image version: 0x%lx, manufacturer code: 0x%x, image size: %ld", message->file_version, message->manufacturer_code, message->image_size); + if (message->image_size == 0) { + log_i("Zigbee - Rejecting OTA image upgrade, image size is 0"); + return ESP_FAIL; + } + if (message->file_version == 0) { + log_i("Zigbee - Rejecting OTA image upgrade, file version is 0"); + return ESP_FAIL; + } + log_i("Zigbee - Approving OTA image upgrade"); + } else { + log_i("Zigbee - OTA image upgrade response status: 0x%x", message->info.status); + } + return ESP_OK; +} + +static esp_err_t zb_cmd_default_resp_handler(const esp_zb_zcl_cmd_default_resp_message_t *message) { + if (!message) { + log_e("Empty message"); + return ESP_FAIL; + } + if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Received message: error status(%d)", message->info.status); + return ESP_ERR_INVALID_ARG; + } + log_v( + "Received default response: from address(0x%x), src_endpoint(%d) to dst_endpoint(%d), cluster(0x%x) with status 0x%x", + message->info.src_address.u.short_addr, message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster, message->status_code + ); + + // Call global callback if set + Zigbee.callDefaultResponseCallback((zb_cmd_type_t)message->resp_to_cmd, message->status_code, message->info.dst_endpoint, message->info.cluster); + + // List through all Zigbee EPs and call the callback function, with the message + for (std::list::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) { + if (message->info.dst_endpoint == (*it)->getEndpoint()) { + (*it)->zbDefaultResponse(message); //method zbDefaultResponse is implemented in the common EP class + } + } + return ESP_OK; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ZigbeeTypes.h b/libraries/Zigbee/src/ZigbeeTypes.h new file mode 100644 index 0000000..5b5a34f --- /dev/null +++ b/libraries/Zigbee/src/ZigbeeTypes.h @@ -0,0 +1,44 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_zigbee_core.h" + +// Foundation Command Types +typedef enum { + ZB_CMD_READ_ATTRIBUTE = 0x00U, /*!< Read attributes command */ + ZB_CMD_READ_ATTRIBUTE_RESPONSE = 0x01U, /*!< Read attributes response command */ + ZB_CMD_WRITE_ATTRIBUTE = 0x02U, /*!< Write attributes foundation command */ + ZB_CMD_WRITE_ATTRIBUTE_UNDIVIDED = 0x03U, /*!< Write attributes undivided command */ + ZB_CMD_WRITE_ATTRIBUTE_RESPONSE = 0x04U, /*!< Write attributes response command */ + ZB_CMD_WRITE_ATTRIBUTE_NO_RESPONSE = 0x05U, /*!< Write attributes no response command */ + ZB_CMD_CONFIGURE_REPORTING = 0x06U, /*!< Configure reporting command */ + ZB_CMD_CONFIGURE_REPORTING_RESPONSE = 0x07U, /*!< Configure reporting response command */ + ZB_CMD_READ_REPORTING_CONFIG = 0x08U, /*!< Read reporting config command */ + ZB_CMD_READ_REPORTING_CONFIG_RESPONSE = 0x09U, /*!< Read reporting config response command */ + ZB_CMD_REPORT_ATTRIBUTE = 0x0aU, /*!< Report attribute command */ + ZB_CMD_DEFAULT_RESPONSE = 0x0bU, /*!< Default response command */ + ZB_CMD_DISCOVER_ATTRIBUTES = 0x0cU, /*!< Discover attributes command */ + ZB_CMD_DISCOVER_ATTRIBUTES_RESPONSE = 0x0dU, /*!< Discover attributes response command */ + ZB_CMD_READ_ATTRIBUTE_STRUCTURED = 0x0eU, /*!< Read attributes structured */ + ZB_CMD_WRITE_ATTRIBUTE_STRUCTURED = 0x0fU, /*!< Write attributes structured */ + ZB_CMD_WRITE_ATTRIBUTE_STRUCTURED_RESPONSE = 0x10U, /*!< Write attributes structured response */ + ZB_CMD_DISCOVER_COMMANDS_RECEIVED = 0x11U, /*!< Discover Commands Received command */ + ZB_CMD_DISCOVER_COMMANDS_RECEIVED_RESPONSE = 0x12U, /*!< Discover Commands Received response command */ + ZB_CMD_DISCOVER_COMMANDS_GENERATED = 0x13U, /*!< Discover Commands Generated command */ + ZB_CMD_DISCOVER_COMMANDS_GENERATED_RESPONSE = 0x14U, /*!< Discover Commands Generated response command */ + ZB_CMD_DISCOVER_ATTRIBUTES_EXTENDED = 0x15U, /*!< Discover attributes extended command */ + ZB_CMD_DISCOVER_ATTRIBUTES_EXTENDED_RESPONSE = 0x16U, /*!< Discover attributes extended response command */ +} zb_cmd_type_t; diff --git a/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp b/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp new file mode 100644 index 0000000..309942e --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp @@ -0,0 +1,480 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeAnalog.h" +#if CONFIG_ZB_ENABLED +#include + +ZigbeeAnalog::ZigbeeAnalog(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + _on_analog_output_change = nullptr; + + //Create basic analog sensor clusters without configuration + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeAnalog::addAnalogInput() { + esp_zb_attribute_list_t *esp_zb_analog_input_cluster = esp_zb_analog_input_cluster_create(NULL); + + // Create default description for Analog Input + char default_description[] = "\x0C" + "Analog Input"; + uint32_t application_type = 0x00000000 | (ESP_ZB_ZCL_AI_GROUP_ID << 24); + float resolution = 0.1; // Default resolution of 0.1 + float min = -FLT_MAX; // Default min value for float + float max = FLT_MAX; // Default max value for float + + esp_err_t ret = esp_zb_analog_input_cluster_add_attr(esp_zb_analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_input_cluster_add_attr(esp_zb_analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_input_cluster_add_attr(esp_zb_analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_RESOLUTION_ID, (void *)&resolution); + if (ret != ESP_OK) { + log_e("Failed to add resolution attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_input_cluster_add_attr(esp_zb_analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_MIN_PRESENT_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_input_cluster_add_attr(esp_zb_analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_MAX_PRESENT_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_list_add_analog_input_cluster(_cluster_list, esp_zb_analog_input_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Analog Input cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + _analog_clusters |= ANALOG_INPUT; + return true; +} + +// Check esp_zigbee_zcl_analog_input.h for application type values +bool ZigbeeAnalog::setAnalogInputApplication(uint32_t application_type) { + if (!(_analog_clusters & ANALOG_INPUT)) { + log_e("Analog Input cluster not added"); + return false; + } + + // Add the Analog Input group ID (0x00) to the application type + uint32_t application_type_value = (ESP_ZB_ZCL_AI_GROUP_ID << 24) | application_type; + + esp_zb_attribute_list_t *analog_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set AI application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::addAnalogOutput() { + esp_zb_attribute_list_t *esp_zb_analog_output_cluster = esp_zb_analog_output_cluster_create(NULL); + + // Create default description for Analog Output + char default_description[] = "\x0D" + "Analog Output"; + uint32_t application_type = 0x00000000 | (ESP_ZB_ZCL_AO_GROUP_ID << 24); + float resolution = 1; // Default resolution of 1 + float min = -FLT_MAX; // Default min value for float + float max = FLT_MAX; // Default max value for float + + esp_err_t ret = + esp_zb_analog_output_cluster_add_attr(esp_zb_analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_output_cluster_add_attr(esp_zb_analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_output_cluster_add_attr(esp_zb_analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_RESOLUTION_ID, (void *)&resolution); + if (ret != ESP_OK) { + log_e("Failed to add resolution attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_output_cluster_add_attr(esp_zb_analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_MIN_PRESENT_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_analog_output_cluster_add_attr(esp_zb_analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_MAX_PRESENT_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_list_add_analog_output_cluster(_cluster_list, esp_zb_analog_output_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Analog Output cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + _analog_clusters |= ANALOG_OUTPUT; + return true; +} + +// Check esp_zigbee_zcl_analog_output.h for application type values +bool ZigbeeAnalog::setAnalogOutputApplication(uint32_t application_type) { + if (!(_analog_clusters & ANALOG_OUTPUT)) { + log_e("Analog Output cluster not added"); + return false; + } + + // Add the Analog Output group ID (0x00) to the application type + uint32_t application_type_value = (ESP_ZB_ZCL_AO_GROUP_ID << 24) | application_type; + + esp_zb_attribute_list_t *analog_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set AO application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +//set attribute method -> method overridden in child class +void ZigbeeAnalog::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_PRESENT_VALUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_SINGLE) { + _output_state = *(float *)message->attribute.data.value; + analogOutputChanged(); + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Analog Output", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Analog endpoint", message->info.cluster); + } +} + +void ZigbeeAnalog::analogOutputChanged() { + if (_on_analog_output_change) { + _on_analog_output_change(_output_state); + } else { + log_w("No callback function set for analog output change"); + } +} + +bool ZigbeeAnalog::setAnalogInput(float analog) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + if (!(_analog_clusters & ANALOG_INPUT)) { + log_e("Analog Input cluster not added"); + return false; + } + log_d("Setting analog input to %.1f", analog); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID, &analog, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set analog input: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogOutput(float analog) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + _output_state = analog; + analogOutputChanged(); + + log_v("Updating analog output to %.2f", analog); + /* Update analog output */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_PRESENT_VALUE_ID, &_output_state, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set analog output: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::reportAnalogInput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Analog Input report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Analog Input report sent"); + return true; +} + +bool ZigbeeAnalog::reportAnalogOutput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Analog Output report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Analog Output report sent"); + return true; +} + +bool ZigbeeAnalog::setAnalogInputReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.s32 = delta; + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set Analog Input reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogInputDescription(const char *description) { + if (!(_analog_clusters & ANALOG_INPUT)) { + log_e("Analog Input cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the analog input cluster + esp_zb_attribute_list_t *analog_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_input_cluster == nullptr) { + log_e("Failed to get analog input cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogOutputDescription(const char *description) { + if (!(_analog_clusters & ANALOG_OUTPUT)) { + log_e("Analog Output cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the analog output cluster + esp_zb_attribute_list_t *analog_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_output_cluster == nullptr) { + log_e("Failed to get analog output cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogInputResolution(float resolution) { + if (!(_analog_clusters & ANALOG_INPUT)) { + log_e("Analog Input cluster not added"); + return false; + } + + esp_zb_attribute_list_t *analog_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_input_cluster == nullptr) { + log_e("Failed to get analog input cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_RESOLUTION_ID, (void *)&resolution); + if (ret != ESP_OK) { + log_e("Failed to set resolution: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogOutputResolution(float resolution) { + if (!(_analog_clusters & ANALOG_OUTPUT)) { + log_e("Analog Output cluster not added"); + return false; + } + + esp_zb_attribute_list_t *analog_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_output_cluster == nullptr) { + log_e("Failed to get analog output cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_RESOLUTION_ID, (void *)&resolution); + if (ret != ESP_OK) { + log_e("Failed to set resolution: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogOutputMinMax(float min, float max) { + if (!(_analog_clusters & ANALOG_OUTPUT)) { + log_e("Analog Output cluster not added"); + return false; + } + + esp_zb_attribute_list_t *analog_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_output_cluster == nullptr) { + log_e("Failed to get analog output cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_MIN_PRESENT_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_update_attr(analog_output_cluster, ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_MAX_PRESENT_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeAnalog::setAnalogInputMinMax(float min, float max) { + if (!(_analog_clusters & ANALOG_INPUT)) { + log_e("Analog Input cluster not added"); + return false; + } + + esp_zb_attribute_list_t *analog_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (analog_input_cluster == nullptr) { + log_e("Failed to get analog input cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_MIN_PRESENT_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_update_attr(analog_input_cluster, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_MAX_PRESENT_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeAnalog.h b/libraries/Zigbee/src/ep/ZigbeeAnalog.h new file mode 100644 index 0000000..38a267a --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeAnalog.h @@ -0,0 +1,93 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Analog sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +//enum for bits set to check what analog cluster were added +enum zigbee_analog_clusters { + ANALOG_INPUT = 1, + ANALOG_OUTPUT = 2 +}; + +typedef struct zigbee_analog_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_analog_output_cluster_cfg_t analog_output_cfg; + esp_zb_analog_input_cluster_cfg_t analog_input_cfg; +} zigbee_analog_cfg_t; + +class ZigbeeAnalog : public ZigbeeEP { +public: + ZigbeeAnalog(uint8_t endpoint); + ~ZigbeeAnalog() {} + + // Add analog clusters + bool addAnalogInput(); + bool addAnalogOutput(); + + // Set the application type and description for the analog input + bool setAnalogInputApplication(uint32_t application_type); // Check esp_zigbee_zcl_analog_input.h for application type values + bool setAnalogInputDescription(const char *description); + bool setAnalogInputResolution(float resolution); + + // Set the application type and description for the analog output + bool setAnalogOutputApplication(uint32_t application_type); // Check esp_zigbee_zcl_analog_output.h for application type values + bool setAnalogOutputDescription(const char *description); + bool setAnalogOutputResolution(float resolution); + + // Set the min and max values for the analog Input/Output + bool setAnalogOutputMinMax(float min, float max); + bool setAnalogInputMinMax(float min, float max); + + // Use to set a cb function to be called on analog output change + void onAnalogOutputChange(void (*callback)(float analog)) { + _on_analog_output_change = callback; + } + + // Set the Analog Input/Output value + bool setAnalogInput(float analog); + bool setAnalogOutput(float analog); + + // Get the Analog Output value + float getAnalogOutput() { + return _output_state; + } + + // Report Analog Input/Output + bool reportAnalogInput(); + bool reportAnalogOutput(); + + // Set reporting for Analog Input + bool setAnalogInputReporting(uint16_t min_interval, uint16_t max_interval, float delta); + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + + void (*_on_analog_output_change)(float); + void analogOutputChanged(); + + uint8_t _analog_clusters; + float _output_state; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeBinary.cpp b/libraries/Zigbee/src/ep/ZigbeeBinary.cpp new file mode 100644 index 0000000..38ba970 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeBinary.cpp @@ -0,0 +1,314 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeBinary.h" +#if CONFIG_ZB_ENABLED + +ZigbeeBinary::ZigbeeBinary(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + _on_binary_output_change = nullptr; + + //Create basic binary sensor clusters without configuration + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeBinary::addBinaryInput() { + esp_zb_attribute_list_t *esp_zb_binary_input_cluster = esp_zb_binary_input_cluster_create(NULL); + + // Create default description for Binary Input + char default_description[] = "\x0C" + "Binary Input"; + uint32_t application_type = 0x00000000 | (0x03 << 24); // Group ID 0x03 + + esp_err_t ret = esp_zb_binary_input_cluster_add_attr(esp_zb_binary_input_cluster, ESP_ZB_ZCL_ATTR_BINARY_INPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_binary_input_cluster_add_attr(esp_zb_binary_input_cluster, ESP_ZB_ZCL_ATTR_BINARY_INPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_list_add_binary_input_cluster(_cluster_list, esp_zb_binary_input_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Binary Input cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + _binary_clusters |= BINARY_INPUT; + return true; +} + +bool ZigbeeBinary::addBinaryOutput() { + esp_zb_attribute_list_t *esp_zb_binary_output_cluster = esp_zb_binary_output_cluster_create(NULL); + + // Create default description for Binary Output + char default_description[] = "\x0D" + "Binary Output"; + uint32_t application_type = 0x00000000 | (0x04 << 24); // Group ID 0x04 + + esp_err_t ret = + esp_zb_binary_output_cluster_add_attr(esp_zb_binary_output_cluster, ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_binary_output_cluster_add_attr(esp_zb_binary_output_cluster, ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_cluster_list_add_binary_output_cluster(_cluster_list, esp_zb_binary_output_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Binary Output cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + _binary_clusters |= BINARY_OUTPUT; + return true; +} + +// Check Zigbee Cluster Specification 3.14.11.19.4 Binary Inputs (BI) Types for application type values +bool ZigbeeBinary::setBinaryInputApplication(uint32_t application_type) { + if (!(_binary_clusters & BINARY_INPUT)) { + log_e("Binary Input cluster not added"); + return false; + } + + // Add the Binary Input group ID (0x03) to the application type + uint32_t application_type_value = (0x03 << 24) | application_type; + + esp_zb_attribute_list_t *binary_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BINARY_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(binary_input_cluster, ESP_ZB_ZCL_ATTR_BINARY_INPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set Binary Input application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +// Check Zigbee Cluster Specification 3.14.11.19.5 Binary Outputs (BO) Types for application type values +bool ZigbeeBinary::setBinaryOutputApplication(uint32_t application_type) { + if (!(_binary_clusters & BINARY_OUTPUT)) { + log_e("Binary Output cluster not added"); + return false; + } + + // Add the Binary Output group ID (0x04) to the application type + uint32_t application_type_value = (0x04 << 24) | application_type; + + esp_zb_attribute_list_t *binary_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BINARY_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(binary_output_cluster, ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set Binary Output application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeBinary::setBinaryInput(bool input) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + if (!(_binary_clusters & BINARY_INPUT)) { + log_e("Binary Input cluster not added"); + return false; + } + log_d("Setting binary input to %d", input); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_BINARY_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_BINARY_INPUT_PRESENT_VALUE_ID, &input, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set binary input: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeBinary::reportBinaryInput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_BINARY_INPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BINARY_INPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Binary Input report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Binary Input report sent"); + return true; +} + +bool ZigbeeBinary::setBinaryInputDescription(const char *description) { + if (!(_binary_clusters & BINARY_INPUT)) { + log_e("Binary Input cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the binary input cluster + esp_zb_attribute_list_t *binary_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BINARY_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (binary_input_cluster == nullptr) { + log_e("Failed to get binary input cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(binary_input_cluster, ESP_ZB_ZCL_ATTR_BINARY_INPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeBinary::setBinaryOutputDescription(const char *description) { + if (!(_binary_clusters & BINARY_OUTPUT)) { + log_e("Binary Output cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the binary output cluster + esp_zb_attribute_list_t *binary_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BINARY_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (binary_output_cluster == nullptr) { + log_e("Failed to get binary output cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(binary_output_cluster, ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +//set attribute method -> method overridden in child class +void ZigbeeBinary::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_BINARY_OUTPUT) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_PRESENT_VALUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + _output_state = *(bool *)message->attribute.data.value; + binaryOutputChanged(); + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Binary Output", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Binary endpoint", message->info.cluster); + } +} + +void ZigbeeBinary::binaryOutputChanged() { + if (_on_binary_output_change) { + _on_binary_output_change(_output_state); + } else { + log_w("No callback function set for binary output change"); + } +} + +bool ZigbeeBinary::setBinaryOutput(bool output) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + _output_state = output; + binaryOutputChanged(); + + log_v("Updating binary output to %d", output); + /* Update binary output */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_BINARY_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_PRESENT_VALUE_ID, &_output_state, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set binary output: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeBinary::reportBinaryOutput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_BINARY_OUTPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BINARY_OUTPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Binary Output report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Binary Output report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeBinary.h b/libraries/Zigbee/src/ep/ZigbeeBinary.h new file mode 100644 index 0000000..c0ca3c8 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeBinary.h @@ -0,0 +1,123 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Binary sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +//enum for bits set to check what analog cluster were added +enum zigbee_binary_clusters { + BINARY_INPUT = 1, + BINARY_OUTPUT = 2 +}; + +// HVAC application types for Binary Input (more can be found in Zigbee Cluster Specification 3.14.11.19.4 Binary Inputs (BI) Types) +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_BOILER_STATUS 0x00000003 // Type 0x00, Index 0x0003 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_CHILLER_STATUS 0x00000013 // Type 0x00, Index 0x0013 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_OCCUPANCY 0x00000031 // Type 0x00, Index 0x0031 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_FAN_STATUS 0x00000035 // Type 0x00, Index 0x0035 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_FILTER_STATUS 0x00000036 // Type 0x00, Index 0x0036 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_HEATING_ALARM 0x0000003E // Type 0x00, Index 0x003E +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_COOLING_ALARM 0x0000001D // Type 0x00, Index 0x001D +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_UNIT_ENABLE 0x00000090 // Type 0x00, Index 0x0090 +#define BINARY_INPUT_APPLICATION_TYPE_HVAC_OTHER 0x0000FFFF // Type 0x00, Index 0xFFFF + +// Security application types for Binary Input +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_GLASS_BREAKAGE_DETECTION_0 0x01000000 // Type 0x01, Index 0x0000 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_INTRUSION_DETECTION 0x01000001 // Type 0x01, Index 0x0001 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_MOTION_DETECTION 0x01000002 // Type 0x01, Index 0x0002 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_GLASS_BREAKAGE_DETECTION_1 0x01000003 // Type 0x01, Index 0x0003 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_ZONE_ARMED 0x01000004 // Type 0x01, Index 0x0004 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_GLASS_BREAKAGE_DETECTION_2 0x01000005 // Type 0x01, Index 0x0005 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_SMOKE_DETECTION 0x01000006 // Type 0x01, Index 0x0006 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_CARBON_DIOXIDE_DETECTION 0x01000007 // Type 0x01, Index 0x0007 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_HEAT_DETECTION 0x01000008 // Type 0x01, Index 0x0008 +#define BINARY_INPUT_APPLICATION_TYPE_SECURITY_OTHER 0x0100FFFF // Type 0x01, Index 0xFFFF + +// HVAC application types for Binary Output (more can be found in Zigbee Cluster Specification 3.14.11.19.5 Binary Outputs (BO) Types) +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_BOILER 0x00000003 // Type 0x00, Index 0x0003 +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_CHILLER 0x0000000D // Type 0x00, Index 0x000D +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_FAN 0x00000022 // Type 0x00, Index 0x0022 +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_HEATING_VALVE 0x0000002C // Type 0x00, Index 0x002C +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_HUMIDIFIER 0x00000033 // Type 0x00, Index 0x0033 +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_PREHEAT 0x00000034 // Type 0x00, Index 0x0034 +#define BINARY_OUTPUT_APPLICATION_TYPE_HVAC_OTHER 0x0000FFFF // Type 0x00, Index 0xFFFF + +// Security application types for Binary Output +#define BINARY_OUTPUT_APPLICATION_TYPE_SECURITY_ARM_DISARM_COMMAND 0x01000000 // Type 0x01, Index 0x0000 +#define BINARY_OUTPUT_APPLICATION_TYPE_SECURITY_OCCUPANCY_CONTROL 0x01000001 // Type 0x01, Index 0x0001 +#define BINARY_OUTPUT_APPLICATION_TYPE_SECURITY_ENABLE_CONTROL 0x01000002 // Type 0x01, Index 0x0002 +#define BINARY_OUTPUT_APPLICATION_TYPE_SECURITY_ACCESS_CONTROL 0x01000003 // Type 0x01, Index 0x0003 +#define BINARY_OUTPUT_APPLICATION_TYPE_SECURITY_OTHER 0x0100FFFF // Type 0x01, Index 0xFFFF + +typedef struct zigbee_binary_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_binary_output_cluster_cfg_t binary_output_cfg; + esp_zb_binary_input_cluster_cfg_t binary_input_cfg; +} zigbee_binary_cfg_t; + +class ZigbeeBinary : public ZigbeeEP { +public: + ZigbeeBinary(uint8_t endpoint); + ~ZigbeeBinary() {} + + // Add binary cluster + bool addBinaryInput(); + bool addBinaryOutput(); + + // Set the application type and description for the binary input + bool setBinaryInputApplication(uint32_t application_type); // Check esp_zigbee_zcl_binary_input.h for application type values + bool setBinaryInputDescription(const char *description); + + // Set the application type and description for the binary output + bool setBinaryOutputApplication(uint32_t application_type); // Check esp_zigbee_zcl_binary_output.h for application type values + bool setBinaryOutputDescription(const char *description); + + // Use to set a cb function to be called on binary output change + void onBinaryOutputChange(void (*callback)(bool binary_output)) { + _on_binary_output_change = callback; + } + + // Set the binary input/output value + bool setBinaryInput(bool input); + bool setBinaryOutput(bool output); + + // Get the Binary Output value + bool getBinaryOutput() { + return _output_state; + } + + // Report Binary Input/Output value + bool reportBinaryInput(); + bool reportBinaryOutput(); + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + + void (*_on_binary_output_change)(bool); + void binaryOutputChanged(); + + bool _output_state; + uint8_t _binary_clusters; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp new file mode 100644 index 0000000..20c715d --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp @@ -0,0 +1,154 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeCarbonDioxideSensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_carbon_dioxide_sensor_clusters_create(zigbee_carbon_dioxide_sensor_cfg_t *carbon_dioxide_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->identify_cfg) : NULL; + esp_zb_carbon_dioxide_measurement_cluster_cfg_t *carbon_dioxide_meas_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->carbon_dioxide_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_carbon_dioxide_measurement_cluster( + cluster_list, esp_zb_carbon_dioxide_measurement_cluster_create(carbon_dioxide_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE + ); + return cluster_list; +} + +ZigbeeCarbonDioxideSensor::ZigbeeCarbonDioxideSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom pressure sensor configuration + zigbee_carbon_dioxide_sensor_cfg_t carbon_dioxide_sensor_cfg = ZIGBEE_DEFAULT_CARBON_DIOXIDE_SENSOR_CONFIG(); + _cluster_list = zigbee_carbon_dioxide_sensor_clusters_create(&carbon_dioxide_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeCarbonDioxideSensor::setDefaultValue(float defaultValue) { + float zb_default_value = defaultValue / 1000000.0f; + esp_zb_attribute_list_t *carbon_dioxide_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = + esp_zb_cluster_update_attr(carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID, (void *)&zb_default_value); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeCarbonDioxideSensor::setMinMaxValue(float min, float max) { + float zb_min = min / 1000000.0f; + float zb_max = max / 1000000.0f; + esp_zb_attribute_list_t *carbon_dioxide_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&zb_min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&zb_max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeCarbonDioxideSensor::setTolerance(float tolerance) { + float zb_tolerance = tolerance / 1000000.0f; + esp_zb_attribute_list_t *carbon_dioxide_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_carbon_dioxide_measurement_cluster_add_attr( + carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance + ); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeCarbonDioxideSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + float delta_f = delta / 1000000.0f; + memcpy(&reporting_info.u.send_info.delta.s32, &delta_f, sizeof(float)); + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeCarbonDioxideSensor::setCarbonDioxide(float carbon_dioxide) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + float zb_carbon_dioxide = carbon_dioxide / 1000000.0f; + log_v("Updating carbon dioxide sensor value..."); + /* Update carbon dioxide sensor measured value */ + log_d("Setting carbon dioxide to %0.1f", carbon_dioxide); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID, + &zb_carbon_dioxide, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set carbon dioxide: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeCarbonDioxideSensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send carbon dioxide report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Carbon dioxide report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h new file mode 100644 index 0000000..2d6a87d --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h @@ -0,0 +1,79 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_CARBON_DIOXIDE_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .carbon_dioxide_meas_cfg = \ + { \ + .measured_value = 0.0, \ + .min_measured_value = 0.0, \ + .max_measured_value = 1.0, \ + }, \ + } +// clang-format on + +typedef struct zigbee_carbon_dioxide_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_carbon_dioxide_measurement_cluster_cfg_t carbon_dioxide_meas_cfg; +} zigbee_carbon_dioxide_sensor_cfg_t; + +class ZigbeeCarbonDioxideSensor : public ZigbeeEP { +public: + ZigbeeCarbonDioxideSensor(uint8_t endpoint); + ~ZigbeeCarbonDioxideSensor() {} + + // Set the carbon dioxide value in ppm + bool setCarbonDioxide(float carbon_dioxide); + + // Set the default (initial) value for the carbon dioxide sensor in ppm + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(float defaultValue); + + // Set the min and max value for the carbon dioxide sensor in ppm + bool setMinMaxValue(float min, float max); + + // Set the tolerance value for the carbon dioxide sensor in ppm + bool setTolerance(float tolerance); + + // Set the reporting interval for carbon dioxide measurement in seconds and delta (carbon dioxide change in ppm) + // NOTE: Delta reporting is currently not supported by the carbon dioxide sensor + bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta); + + // Report the carbon dioxide value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp new file mode 100644 index 0000000..a31cf17 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp @@ -0,0 +1,569 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "ZigbeeColorDimmableLight.h" +#if CONFIG_ZB_ENABLED + +ZigbeeColorDimmableLight::ZigbeeColorDimmableLight(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID; + + esp_zb_color_dimmable_light_cfg_t light_cfg = ZIGBEE_DEFAULT_COLOR_DIMMABLE_LIGHT_CONFIG(); + _cluster_list = esp_zb_color_dimmable_light_clusters_create(&light_cfg); + + //Add support for hue and saturation + uint8_t hue = 0; + uint8_t saturation = 0; + + // Add support for Color Temperature and Hue Saturation attributes + uint16_t color_temperature = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_TEMPERATURE_DEF_VALUE; + uint16_t min_temp = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MIN_MIREDS_DEFAULT_VALUE; + uint16_t max_temp = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MAX_MIREDS_DEFAULT_VALUE; + + esp_zb_attribute_list_t *color_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, &hue); + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID, &saturation); + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMPERATURE_ID, &color_temperature); + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MIN_MIREDS_ID, &min_temp); + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MAX_MIREDS_ID, &max_temp); + uint8_t color_mode = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_MODE_DEFAULT_VALUE; + esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_MODE_ID, &color_mode); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID, .app_device_version = 0 + }; + + //set default values + _current_state = false; + _current_level = 255; + _current_color = {255, 255, 255}; + _current_hsv = {0, 0, 255}; + _current_color_temperature = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_TEMPERATURE_DEF_VALUE; + _current_color_mode = ZIGBEE_COLOR_MODE_CURRENT_X_Y; //default XY color mode + _color_capabilities = ZIGBEE_COLOR_CAPABILITY_X_Y; //default XY color supported only + + // Initialize callbacks to nullptr + _on_light_change_rgb = nullptr; + _on_light_change_hsv = nullptr; + _on_light_change_temp = nullptr; +} + +uint16_t ZigbeeColorDimmableLight::getCurrentColorX() { + return (*(uint16_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID + ) + ->data_p); +} + +uint16_t ZigbeeColorDimmableLight::getCurrentColorY() { + return (*(uint16_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID + ) + ->data_p); +} + +uint8_t ZigbeeColorDimmableLight::getCurrentColorHue() { + return (*(uint8_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID + ) + ->data_p); +} + +uint8_t ZigbeeColorDimmableLight::getCurrentColorSaturation() { + return (*(uint8_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID + ) + ->data_p); +} + +uint16_t ZigbeeColorDimmableLight::getCurrentColorTemperature() { + return (*(uint16_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMPERATURE_ID + ) + ->data_p); +} + +//set attribute method -> method overridden in child class +void ZigbeeColorDimmableLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + //check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + if (_current_state != *(bool *)message->attribute.data.value) { + _current_state = *(bool *)message->attribute.data.value; + lightChangedByMode(); + } + return; + } else { + log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id); + } + } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + if (_current_level != *(uint8_t *)message->attribute.data.value) { + _current_level = *(uint8_t *)message->attribute.data.value; + // Update HSV value if in HSV mode + if (_current_color_mode == ZIGBEE_COLOR_MODE_HUE_SATURATION) { + _current_hsv.v = _current_level; + } + lightChangedByMode(); + } + return; + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Level Control", message->attribute.id); + } + } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_MODE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_8BIT_ENUM) { + uint8_t new_color_mode = (*(uint8_t *)message->attribute.data.value); + if (new_color_mode > ZIGBEE_COLOR_MODE_TEMPERATURE) { + log_w("Invalid color mode received: %d", new_color_mode); + return; + } + + // Validate that the requested color mode is supported by capabilities + if (!isColorModeSupported(new_color_mode)) { + log_w("Color mode %d not supported by current capabilities: 0x%04x", new_color_mode, _color_capabilities); + return; + } + + _current_color_mode = new_color_mode; + log_v("Color mode changed to: %d", _current_color_mode); + // Don't call setLightColorMode() here - the attribute was already set externally + // Just update our internal state + return; + } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + // Validate XY capability + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_X_Y)) { + log_w("XY color capability not enabled, but XY attribute received. Current capabilities: 0x%04x", _color_capabilities); + return; + } + uint16_t light_color_x = (*(uint16_t *)message->attribute.data.value); + uint16_t light_color_y = getCurrentColorY(); + // Update color mode to XY if not already + if (_current_color_mode != ZIGBEE_COLOR_MODE_CURRENT_X_Y) { + setLightColorMode(ZIGBEE_COLOR_MODE_CURRENT_X_Y); + } + //calculate RGB from XY and call RGB callback + _current_color = espXYToRgbColor(255, light_color_x, light_color_y, false); + lightChangedRgb(); + return; + + } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + // Validate XY capability + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_X_Y)) { + log_w("XY color capability not enabled, but XY attribute received. Current capabilities: 0x%04x", _color_capabilities); + return; + } + uint16_t light_color_x = getCurrentColorX(); + uint16_t light_color_y = (*(uint16_t *)message->attribute.data.value); + // Update color mode to XY if not already + if (_current_color_mode != ZIGBEE_COLOR_MODE_CURRENT_X_Y) { + setLightColorMode(ZIGBEE_COLOR_MODE_CURRENT_X_Y); + } + //calculate RGB from XY and call RGB callback + _current_color = espXYToRgbColor(255, light_color_x, light_color_y, false); + lightChangedRgb(); + return; + } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + // Validate Hue/Saturation capability + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION)) { + log_w("Hue/Saturation color capability not enabled, but Hue attribute received. Current capabilities: 0x%04x", _color_capabilities); + return; + } + uint8_t light_color_hue = (*(uint8_t *)message->attribute.data.value); + // Update color mode to HS if not already + if (_current_color_mode != ZIGBEE_COLOR_MODE_HUE_SATURATION) { + setLightColorMode(ZIGBEE_COLOR_MODE_HUE_SATURATION); + } + // Store HSV values and call HSV callback (don't convert to RGB) + _current_hsv.h = light_color_hue; + _current_hsv.s = getCurrentColorSaturation(); + _current_hsv.v = _current_level; // Use level as value + lightChangedHsv(); + return; + } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + // Validate Hue/Saturation capability + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION)) { + log_w("Hue/Saturation color capability not enabled, but Saturation attribute received. Current capabilities: 0x%04x", _color_capabilities); + return; + } + uint8_t light_color_saturation = (*(uint8_t *)message->attribute.data.value); + // Update color mode to HS if not already + if (_current_color_mode != ZIGBEE_COLOR_MODE_HUE_SATURATION) { + setLightColorMode(ZIGBEE_COLOR_MODE_HUE_SATURATION); + } + // Store HSV values and call HSV callback (don't convert to RGB) + _current_hsv.h = getCurrentColorHue(); + _current_hsv.s = light_color_saturation; + _current_hsv.v = _current_level; // Use level as value + lightChangedHsv(); + return; + } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMPERATURE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + // Validate Color Temperature capability + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP)) { + log_w("Color temperature capability not enabled, but Temperature attribute received. Current capabilities: 0x%04x", _color_capabilities); + return; + } + uint16_t light_color_temp = (*(uint16_t *)message->attribute.data.value); + // Update color mode to TEMP if not already + if (_current_color_mode != ZIGBEE_COLOR_MODE_TEMPERATURE) { + setLightColorMode(ZIGBEE_COLOR_MODE_TEMPERATURE); + } + if (_current_color_temperature != light_color_temp) { + _current_color_temperature = light_color_temp; + lightChangedTemp(); + } + return; + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Color Control", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Color dimmable Light", message->info.cluster); + } +} + +void ZigbeeColorDimmableLight::lightChangedRgb() { + if (_on_light_change_rgb) { + _on_light_change_rgb(_current_state, _current_color.r, _current_color.g, _current_color.b, _current_level); + } +} + +void ZigbeeColorDimmableLight::lightChangedHsv() { + if (_on_light_change_hsv) { + _on_light_change_hsv(_current_state, _current_hsv.h, _current_hsv.s, _current_hsv.v); + } +} + +void ZigbeeColorDimmableLight::lightChangedTemp() { + if (_on_light_change_temp) { + _on_light_change_temp(_current_state, _current_level, _current_color_temperature); + } +} + +void ZigbeeColorDimmableLight::lightChangedByMode() { + // Call the appropriate callback based on current color mode + switch (_current_color_mode) { + case ZIGBEE_COLOR_MODE_CURRENT_X_Y: lightChangedRgb(); break; + case ZIGBEE_COLOR_MODE_HUE_SATURATION: lightChangedHsv(); break; + case ZIGBEE_COLOR_MODE_TEMPERATURE: lightChangedTemp(); break; + default: log_e("Unknown color mode: %d", _current_color_mode); break; + } +} + +bool ZigbeeColorDimmableLight::setLight(bool state, uint8_t level, uint8_t red, uint8_t green, uint8_t blue) { + // Check if XY color capability is enabled + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_X_Y)) { + log_e("XY color capability not enabled. Current capabilities: 0x%04x", _color_capabilities); + return false; + } + if (!setLightColorMode(ZIGBEE_COLOR_MODE_CURRENT_X_Y)) { + log_e("Failed to set light color mode: %d", ZIGBEE_COLOR_MODE_CURRENT_X_Y); + return false; + } + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update all attributes + _current_state = state; + _current_level = level; + _current_color = {red, green, blue}; + lightChangedRgb(); + + espXyColor_t xy_color = espRgbColorToXYColor(_current_color); + espHsvColor_t hsv_color = espRgbColorToHsvColor(_current_color); + // Clamp hue and saturation to valid Zigbee range (0-254, where 254 = 0xFE is max per ZCL spec) + uint8_t hue = std::min(std::max((uint8_t)hsv_color.h, (uint8_t)0), (uint8_t)254); + uint8_t saturation = std::min(std::max((uint8_t)hsv_color.s, (uint8_t)0), (uint8_t)254); + // Update HSV state + _current_hsv = hsv_color; + + log_v("Updating light state: %d, level: %d, color: %d, %d, %d", state, level, red, green, blue); + /* Update light clusters */ + esp_zb_lock_acquire(portMAX_DELAY); + //set on/off state + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set level + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set x color + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, &xy_color.x, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light xy color: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set y color + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID, &xy_color.y, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light y color: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set hue (for compatibility) + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, &hue, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light hue: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set saturation (for compatibility) + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID, &saturation, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light saturation: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeColorDimmableLight::setLightState(bool state) { + if (_current_state == state) { + return true; // No change needed + } + + _current_state = state; + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false + ); + esp_zb_lock_release(); + + if (ret == ESP_ZB_ZCL_STATUS_SUCCESS) { + lightChangedByMode(); // Call appropriate callback based on current color mode + } else { + log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + } + + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeColorDimmableLight::setLightLevel(uint8_t level) { + if (_current_level == level) { + return true; // No change needed + } + + _current_level = level; + // Update HSV value if in HSV mode + if (_current_color_mode == ZIGBEE_COLOR_MODE_HUE_SATURATION) { + _current_hsv.v = level; + } + + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false + ); + esp_zb_lock_release(); + + if (ret == ESP_ZB_ZCL_STATUS_SUCCESS) { + lightChangedByMode(); // Call appropriate callback based on current color mode + } else { + log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + } + + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeColorDimmableLight::setLightColor(uint8_t red, uint8_t green, uint8_t blue) { + return setLight(_current_state, _current_level, red, green, blue); +} + +bool ZigbeeColorDimmableLight::setLightColor(espRgbColor_t rgb_color) { + return setLight(_current_state, _current_level, rgb_color.r, rgb_color.g, rgb_color.b); +} + +bool ZigbeeColorDimmableLight::setLightColor(espHsvColor_t hsv_color) { + // Check if Hue/Saturation color capability is enabled + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION)) { + log_e("Hue/Saturation color capability not enabled. Current capabilities: 0x%04x", _color_capabilities); + return false; + } + + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + if (!setLightColorMode(ZIGBEE_COLOR_MODE_HUE_SATURATION)) { + log_e("Failed to set light color mode: %d", ZIGBEE_COLOR_MODE_HUE_SATURATION); + return false; + } + // Update HSV state and level from value component + _current_hsv = hsv_color; + _current_level = hsv_color.v; // Use HSV value component to update brightness level + lightChangedHsv(); + + // Clamp hue and saturation to valid Zigbee range (0-254, where 254 = 0xFE is max per ZCL spec) + uint8_t hue = std::clamp((uint8_t)hsv_color.h, (uint8_t)0, (uint8_t)254); + uint8_t saturation = std::clamp((uint8_t)hsv_color.s, (uint8_t)0, (uint8_t)254); + + log_v("Updating light HSV: H=%d, S=%d, V=%d (level=%d)", hue, saturation, hsv_color.v, _current_level); + /* Update light clusters */ + esp_zb_lock_acquire(portMAX_DELAY); + //set level (brightness from HSV value component) + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set hue + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, &hue, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light hue: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + //set saturation + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID, &saturation, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light saturation: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeColorDimmableLight::setLightColorTemperature(uint16_t color_temperature) { + // Check if Color Temperature capability is enabled + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP)) { + log_e("Color temperature capability not enabled. Current capabilities: 0x%04x", _color_capabilities); + return false; + } + if (!setLightColorMode(ZIGBEE_COLOR_MODE_TEMPERATURE)) { + log_e("Failed to set light color mode: %d", ZIGBEE_COLOR_MODE_TEMPERATURE); + return false; + } + + _current_color_temperature = color_temperature; + lightChangedTemp(); + + log_v("Updating light color temperature: %d", color_temperature); + + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + /* Update light clusters */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMPERATURE_ID, + &_current_color_temperature, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light color temperature: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeColorDimmableLight::isColorModeSupported(uint8_t color_mode) { + switch (color_mode) { + case ZIGBEE_COLOR_MODE_CURRENT_X_Y: return (_color_capabilities & ZIGBEE_COLOR_CAPABILITY_X_Y) != 0; + case ZIGBEE_COLOR_MODE_HUE_SATURATION: return (_color_capabilities & ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION) != 0; + case ZIGBEE_COLOR_MODE_TEMPERATURE: return (_color_capabilities & ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP) != 0; + default: return false; + } +} + +bool ZigbeeColorDimmableLight::setLightColorMode(uint8_t color_mode) { + if (color_mode > ZIGBEE_COLOR_MODE_TEMPERATURE) { + log_e("Invalid color mode: %d", color_mode); + return false; + } + + // Check if the requested color mode is supported by capabilities + if (!isColorModeSupported(color_mode)) { + log_e("Color mode %d not supported by current capabilities: 0x%04x", color_mode, _color_capabilities); + return false; + } + + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting color mode: %d", color_mode); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_MODE_ID, &color_mode, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light color mode: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _current_color_mode = color_mode; + return true; +} + +bool ZigbeeColorDimmableLight::setLightColorCapabilities(uint16_t capabilities) { + esp_zb_attribute_list_t *color_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (!color_cluster) { + log_e("Color control cluster not found"); + return false; + } + + // Validate capabilities (max value is 0x001f per ZCL spec) + if (capabilities > 0x001f) { + log_e("Invalid color capabilities value: 0x%04x (max: 0x001f)", capabilities); + return false; + } + + _color_capabilities = capabilities; + + esp_err_t ret = esp_zb_cluster_update_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_CAPABILITIES_ID, &_color_capabilities); + if (ret != ESP_OK) { + log_e("Failed to set color capabilities: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + log_v("Color capabilities set to: 0x%04x", _color_capabilities); + return true; +} + +bool ZigbeeColorDimmableLight::setLightColorTemperatureRange(uint16_t min_temp, uint16_t max_temp) { + esp_zb_attribute_list_t *color_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (!color_cluster) { + log_e("Color control cluster not found"); + return false; + } + if (!(_color_capabilities & ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP)) { + log_e("Color temperature capability not enabled. Current capabilities: 0x%04x", _color_capabilities); + return false; + } + esp_err_t ret = esp_zb_cluster_update_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MIN_MIREDS_ID, &min_temp); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_COLOR_TEMP_PHYSICAL_MAX_MIREDS_ID, &max_temp); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h new file mode 100644 index 0000000..92fbb91 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h @@ -0,0 +1,190 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Light endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +#define ZIGBEE_DEFAULT_COLOR_DIMMABLE_LIGHT_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .groups_cfg = \ + { \ + .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .scenes_cfg = \ + { \ + .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE, \ + .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE, \ + .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE, \ + .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE, \ + .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .on_off_cfg = \ + { \ + .on_off = ESP_ZB_ZCL_ON_OFF_ON_OFF_DEFAULT_VALUE, \ + }, \ + .level_cfg = \ + { \ + .current_level = ESP_ZB_ZCL_LEVEL_CONTROL_CURRENT_LEVEL_DEFAULT_VALUE, \ + }, \ + .color_cfg = { \ + .current_x = ESP_ZB_ZCL_COLOR_CONTROL_CURRENT_X_DEF_VALUE, \ + .current_y = ESP_ZB_ZCL_COLOR_CONTROL_CURRENT_Y_DEF_VALUE, \ + .color_mode = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_MODE_DEFAULT_VALUE, \ + .options = ESP_ZB_ZCL_COLOR_CONTROL_OPTIONS_DEFAULT_VALUE, \ + .enhanced_color_mode = ESP_ZB_ZCL_COLOR_CONTROL_ENHANCED_COLOR_MODE_DEFAULT_VALUE, \ + .color_capabilities = 0x0009, \ + }, \ + } + +// Color capabilities bit flags (matching ZCL spec) - can be combined with bitwise OR +static constexpr uint16_t ZIGBEE_COLOR_CAPABILITY_HUE_SATURATION = (1 << 0); // Bit 0: Hue/saturation supported +static constexpr uint16_t ZIGBEE_COLOR_CAPABILITY_ENHANCED_HUE = (1 << 1); // Bit 1: Enhanced hue supported +static constexpr uint16_t ZIGBEE_COLOR_CAPABILITY_COLOR_LOOP = (1 << 2); // Bit 2: Color loop supported +static constexpr uint16_t ZIGBEE_COLOR_CAPABILITY_X_Y = (1 << 3); // Bit 3: X/Y supported +static constexpr uint16_t ZIGBEE_COLOR_CAPABILITY_COLOR_TEMP = (1 << 4); // Bit 4: Color temperature supported + +// Color mode enum values (matching ZCL spec) +enum ZigbeeColorMode { + ZIGBEE_COLOR_MODE_HUE_SATURATION = 0x00, // CurrentHue and CurrentSaturation + ZIGBEE_COLOR_MODE_CURRENT_X_Y = 0x01, // CurrentX and CurrentY // codespell:ignore currenty + ZIGBEE_COLOR_MODE_TEMPERATURE = 0x02, // ColorTemperature +}; + +// Callback function type definitions for better readability and type safety +// RGB callback: (state, red, green, blue, level) +typedef void (*ZigbeeColorLightRgbCallback)(bool state, uint8_t red, uint8_t green, uint8_t blue, uint8_t level); +// HSV callback: (state, hue, saturation, value) - value represents brightness (0-255) +typedef void (*ZigbeeColorLightHsvCallback)(bool state, uint8_t hue, uint8_t saturation, uint8_t value); +// Temperature callback: (state, level, color_temperature_in_mireds) +typedef void (*ZigbeeColorLightTempCallback)(bool state, uint8_t level, uint16_t color_temperature); + +class ZigbeeColorDimmableLight : public ZigbeeEP { +public: + ZigbeeColorDimmableLight(uint8_t endpoint); + ~ZigbeeColorDimmableLight() {} + + // Must be called before starting Zigbee, by default XY are selected as color mode + bool setLightColorCapabilities(uint16_t capabilities); + + [[deprecated("Use onLightChangeRgb() instead. This will be removed in a future major version.")]] + void onLightChange(ZigbeeColorLightRgbCallback callback) { + _on_light_change_rgb = callback; + } + void onLightChangeRgb(ZigbeeColorLightRgbCallback callback) { + _on_light_change_rgb = callback; + } + void onLightChangeHsv(ZigbeeColorLightHsvCallback callback) { + _on_light_change_hsv = callback; + } + void onLightChangeTemp(ZigbeeColorLightTempCallback callback) { + _on_light_change_temp = callback; + } + void restoreLight() { + lightChangedByMode(); + } + + bool setLightState(bool state); + bool setLightLevel(uint8_t level); + bool setLightColor(uint8_t red, uint8_t green, uint8_t blue); + bool setLightColor(espRgbColor_t rgb_color); + bool setLightColor(espHsvColor_t hsv_color); + bool setLightColorTemperature(uint16_t color_temperature); + bool setLight(bool state, uint8_t level, uint8_t red, uint8_t green, uint8_t blue); + bool setLightColorTemperatureRange(uint16_t min_temp, uint16_t max_temp); + + bool getLightState() { + return _current_state; + } + uint8_t getLightLevel() { + return _current_level; + } + espRgbColor_t getLightColor() { + return _current_color; + } + uint8_t getLightRed() { + return _current_color.r; + } + uint8_t getLightGreen() { + return _current_color.g; + } + uint8_t getLightBlue() { + return _current_color.b; + } + uint16_t getLightColorTemperature() { + return _current_color_temperature; + } + uint8_t getLightColorMode() { + return _current_color_mode; + } + uint8_t getLightColorHue() { + return _current_hsv.h; + } + uint8_t getLightColorSaturation() { + return _current_hsv.s; + } + uint16_t getLightColorCapabilities() { + return _color_capabilities; + } + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + bool setLightColorMode(uint8_t color_mode); + bool isColorModeSupported(uint8_t color_mode); + + uint16_t getCurrentColorX(); + uint16_t getCurrentColorY(); + uint8_t getCurrentColorHue(); + uint8_t getCurrentColorSaturation(); + uint16_t getCurrentColorTemperature(); + + void lightChangedRgb(); + void lightChangedHsv(); + void lightChangedTemp(); + void lightChangedByMode(); + + //callback function to be called on light change for RGB (State, R, G, B, Level) + ZigbeeColorLightRgbCallback _on_light_change_rgb; + //callback function to be called on light change for HSV (State, H, S, V, Level) + ZigbeeColorLightHsvCallback _on_light_change_hsv; + //callback function to be called on light change for TEMP (State, Level, Temperature) + ZigbeeColorLightTempCallback _on_light_change_temp; + + bool _current_state; + uint8_t _current_level; + espRgbColor_t _current_color; + espHsvColor_t _current_hsv; + uint16_t _current_color_temperature; + uint8_t _current_color_mode; + + uint16_t _color_capabilities; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp new file mode 100644 index 0000000..ea19de2 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp @@ -0,0 +1,974 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeColorDimmerSwitch.h" +#if CONFIG_ZB_ENABLED + +// Initialize the static instance pointer +ZigbeeColorDimmerSwitch *ZigbeeColorDimmerSwitch::_instance = nullptr; + +ZigbeeColorDimmerSwitch::ZigbeeColorDimmerSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID; + _instance = this; // Set the static pointer to this instance + _device = nullptr; // Initialize light pointer to null + + _light_color_rgb = {0, 0, 0}; + _light_color_hsv = {0, 0, 255}; + _light_color_xy = {0, 0}; + _on_light_state_change = nullptr; + _on_light_state_change_with_source = nullptr; + _on_light_level_change = nullptr; + _on_light_level_change_with_source = nullptr; + _on_light_color_change = nullptr; + _on_light_color_change_with_source = nullptr; + + esp_zb_color_dimmable_switch_cfg_t switch_cfg = ESP_ZB_DEFAULT_COLOR_DIMMABLE_SWITCH_CONFIG(); + _cluster_list = esp_zb_color_dimmable_switch_clusters_create(&switch_cfg); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID, .app_device_version = 0 + }; +} + +void ZigbeeColorDimmerSwitch::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeColorDimmerSwitch *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_i("Bound successfully!"); + if (instance->_device) { + zb_device_params_t *light = (zb_device_params_t *)instance->_device; + log_i("The light originating from address(0x%x) on endpoint(%d)", light->short_addr, light->endpoint); + log_d("Light bound to a switch on EP %d", instance->_endpoint); + instance->_bound_devices.push_back(light); + } + instance->_is_bound = true; + } else { + instance->_device = nullptr; + } +} + +void ZigbeeColorDimmerSwitch::bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeColorDimmerSwitch *instance = static_cast(user_ctx); + if (instance) { + log_d("bindCbWrapper on EP %d", instance->_endpoint); + instance->bindCb(zdo_status, user_ctx); + } +} + +void ZigbeeColorDimmerSwitch::findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeColorDimmerSwitch *instance = static_cast(user_ctx); + if (instance) { + log_d("findCbWrapper on EP %d", instance->_endpoint); + instance->findCb(zdo_status, addr, endpoint, user_ctx); + } +} + +void ZigbeeColorDimmerSwitch::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeColorDimmerSwitch *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_d("Found light endpoint"); + esp_zb_zdo_bind_req_param_t bind_req; + memset(&bind_req, 0, sizeof(bind_req)); + zb_device_params_t *light = (zb_device_params_t *)malloc(sizeof(zb_device_params_t)); + light->endpoint = endpoint; + light->short_addr = addr; + esp_zb_ieee_address_by_short(light->short_addr, light->ieee_addr); + esp_zb_get_long_address(bind_req.src_address); + bind_req.src_endp = instance->_endpoint; + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED; + memcpy(bind_req.dst_address_u.addr_long, light->ieee_addr, sizeof(esp_zb_ieee_addr_t)); + bind_req.dst_endp = endpoint; + bind_req.req_dst_addr = esp_zb_get_short_address(); + instance->_device = light; + log_v("Try to bind on/off control of dimmable light"); + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeColorDimmerSwitch::bindCbWrapper, NULL); + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL; + log_v("Try to bind level control of dimmable light"); + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeColorDimmerSwitch::bindCbWrapper, NULL); + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + log_v("Try to bind color control of dimmable light"); + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeColorDimmerSwitch::bindCbWrapper, this); + } else { + log_d("No color dimmable light endpoint found"); + } +} + +// find on_off light endpoint +void ZigbeeColorDimmerSwitch::findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) { + uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, + ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL}; + esp_zb_zdo_match_desc_req_param_t color_dimmable_light_req = { + .dst_nwk_addr = cmd_req->dst_nwk_addr, + .addr_of_interest = cmd_req->addr_of_interest, + .profile_id = ESP_ZB_AF_HA_PROFILE_ID, + .num_in_clusters = 3, + .num_out_clusters = 3, + .cluster_list = cluster_list, + }; + esp_zb_zdo_match_cluster(&color_dimmable_light_req, ZigbeeColorDimmerSwitch::findCbWrapper, this); +} + +// Methods to control the light +void ZigbeeColorDimmerSwitch::lightToggle() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightToggle(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightToggle(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light toggle' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOn() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOn(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOn(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light on' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOff() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOff(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOff(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light off' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant) { + if (_is_bound) { + esp_zb_zcl_on_off_off_with_effect_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.effect_id = effect_id; + cmd_req.effect_variant = effect_variant; + log_v("Sending 'light off with effect' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_off_with_effect_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOnWithSceneRecall() { + if (_is_bound) { + esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + log_v("Sending 'light on with scene recall' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off) { + if (_is_bound) { + esp_zb_zcl_on_off_on_with_timed_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_control = on_off_control; //TODO: Test how it works, then maybe change API + cmd_req.on_time = time_on; + cmd_req.off_wait_time = time_off; + log_v("Sending 'light on with time off' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_on_with_timed_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level) { + if (_is_bound) { + esp_zb_zcl_move_to_level_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.level = level; + cmd_req.transition_time = 0xffff; + log_v("Sending 'set light level' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_move_to_level_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.level = level; + cmd_req.transition_time = 0xffff; + log_v("Sending 'set light level' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_move_to_level_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.level = level; + cmd_req.transition_time = 0xffff; + log_v("Sending 'set light level' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_move_to_level_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + cmd_req.level = level; + cmd_req.transition_time = 0xffff; + log_v( + "Sending 'set light level' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue) { + if (_is_bound) { + espXyColor_t xy_color = espRgbToXYColor(red, green, blue); + + esp_zb_zcl_color_move_to_color_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.color_x = xy_color.x; + cmd_req.color_y = xy_color.y; + cmd_req.transition_time = 0; + log_v("Sending 'set light color' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint16_t group_addr) { + if (_is_bound) { + espXyColor_t xy_color = espRgbToXYColor(red, green, blue); + + esp_zb_zcl_color_move_to_color_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.color_x = xy_color.x; + cmd_req.color_y = xy_color.y; + cmd_req.transition_time = 0; + log_v("Sending 'set light color' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + espXyColor_t xy_color = espRgbToXYColor(red, green, blue); + + esp_zb_zcl_color_move_to_color_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.color_x = xy_color.x; + cmd_req.color_y = xy_color.y; + cmd_req.transition_time = 0; + log_v("Sending 'set light color' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + espXyColor_t xy_color = espRgbToXYColor(red, green, blue); + + esp_zb_zcl_color_move_to_color_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + cmd_req.color_x = xy_color.x; + cmd_req.color_y = xy_color.y; + cmd_req.transition_time = 0; + log_v( + "Sending 'set light color' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeColorDimmerSwitch::getLightState() { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightState(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightState(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightState(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightLevel() { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightLevel(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightLevel(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightLevel(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColor() { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColor(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColor(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColor(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColorHS() { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColorHS(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColorHS(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::getLightColorHS(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL; + read_req.attr_number = 2; + uint16_t attr_id[] = {ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID}; + read_req.attr_field = attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time) { + if (_is_bound) { + esp_zb_zcl_level_step_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.step_mode = (uint8_t)direction; + cmd_req.step_size = step_size; + cmd_req.transition_time = transition_time; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_step_cmd_req(&cmd_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_level_step_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.step_mode = (uint8_t)direction; + cmd_req.step_size = step_size; + cmd_req.transition_time = transition_time; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_step_cmd_req(&cmd_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevelStep( + ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint8_t endpoint, uint16_t short_addr +) { + if (_is_bound) { + esp_zb_zcl_level_step_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.step_mode = (uint8_t)direction; + cmd_req.step_size = step_size; + cmd_req.transition_time = transition_time; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_step_cmd_req(&cmd_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::setLightLevelStep( + ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr +) { + if (_is_bound) { + esp_zb_zcl_level_step_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + cmd_req.step_mode = (uint8_t)direction; + cmd_req.step_size = step_size; + cmd_req.transition_time = transition_time; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_level_step_cmd_req(&cmd_req); + esp_zb_lock_release(); + } +} + +void ZigbeeColorDimmerSwitch::zbAttributeRead( + uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address +) { + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (attribute->id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + bool light_state = attribute->data.value ? *(bool *)attribute->data.value : false; + if (_on_light_state_change) { + _on_light_state_change(light_state); + } + if (_on_light_state_change_with_source) { + _on_light_state_change_with_source(light_state, src_endpoint, src_address); + } + } + } + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL) { + if (attribute->id == ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + uint8_t light_level = attribute->data.value ? *(uint8_t *)attribute->data.value : 0; + if (_on_light_level_change) { + _on_light_level_change(light_level); + } + if (_on_light_level_change_with_source) { + _on_light_level_change_with_source(light_level, src_endpoint, src_address); + } + } + } + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL) { + static bool x_received = false; + static bool y_received = false; + static bool h_received = false; + static bool s_received = false; + + if (attribute->id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + _light_color_xy.x = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + x_received = true; + } + if (attribute->id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + _light_color_xy.y = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + y_received = true; + } + + if (attribute->id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + _light_color_hsv.h = attribute->data.value ? *(uint8_t *)attribute->data.value : 0; + h_received = true; + } + if (attribute->id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + _light_color_hsv.s = attribute->data.value ? *(uint8_t *)attribute->data.value : 0; + s_received = true; + } + + // Process XY color if both X and Y have been received + if (x_received && y_received) { + _light_color_rgb = espXYToRgbColor(255, _light_color_xy.x, _light_color_xy.y, false); + if (_on_light_color_change) { + _on_light_color_change(_light_color_rgb.r, _light_color_rgb.g, _light_color_rgb.b); + } + if (_on_light_color_change_with_source) { + _on_light_color_change_with_source(_light_color_rgb.r, _light_color_rgb.g, _light_color_rgb.b, src_endpoint, src_address); + } + x_received = false; // Reset flags after processing + y_received = false; + } + + // Process HS color if both H and S have been received + if (h_received && s_received) { + _light_color_rgb = espHsvColorToRgbColor(_light_color_hsv); + if (_on_light_color_change) { + _on_light_color_change(_light_color_rgb.r, _light_color_rgb.g, _light_color_rgb.b); + } + if (_on_light_color_change_with_source) { + _on_light_color_change_with_source(_light_color_rgb.r, _light_color_rgb.g, _light_color_rgb.b, src_endpoint, src_address); + } + h_received = false; // Reset flags after processing + s_received = false; + } + } +} +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h new file mode 100644 index 0000000..3ea5cf6 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h @@ -0,0 +1,136 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Switch endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +/** Level step direction for setLightLevelStep (ZCL Step command: 0 = Up, 1 = Down) */ +enum ZigbeeLevelStepDirection { + ZIGBEE_LEVEL_STEP_UP = 0, + ZIGBEE_LEVEL_STEP_DOWN = 1 +}; + +class ZigbeeColorDimmerSwitch : public ZigbeeEP { +public: + ZigbeeColorDimmerSwitch(uint8_t endpoint); + ~ZigbeeColorDimmerSwitch() {} + + // methods to control the color dimmable light + void lightToggle(); + void lightToggle(uint16_t group_addr); + void lightToggle(uint8_t endpoint, uint16_t short_addr); + void lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOn(); + void lightOn(uint16_t group_addr); + void lightOn(uint8_t endpoint, uint16_t short_addr); + void lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOff(); + void lightOff(uint16_t group_addr); + void lightOff(uint8_t endpoint, uint16_t short_addr); + void lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant); + void lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off); + void lightOnWithSceneRecall(); + + void setLightLevel(uint8_t level); + void setLightLevel(uint8_t level, uint16_t group_addr); + void setLightLevel(uint8_t level, uint8_t endpoint, uint16_t short_addr); + void setLightLevel(uint8_t level, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time); + void setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint16_t group_addr); + void setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint8_t endpoint, uint16_t short_addr); + void setLightLevelStep(ZigbeeLevelStepDirection direction, uint8_t step_size, uint16_t transition_time, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void setLightColor(uint8_t red, uint8_t green, uint8_t blue); + void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint16_t group_addr); + void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, uint16_t short_addr); + void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void getLightState(); + void getLightState(uint16_t group_addr); + void getLightState(uint8_t endpoint, uint16_t short_addr); + void getLightState(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void getLightLevel(); + void getLightLevel(uint16_t group_addr); + void getLightLevel(uint8_t endpoint, uint16_t short_addr); + void getLightLevel(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void getLightColor(); + void getLightColor(uint16_t group_addr); + void getLightColor(uint8_t endpoint, uint16_t short_addr); + void getLightColor(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void getLightColorHS(); + void getLightColorHS(uint16_t group_addr); + void getLightColorHS(uint8_t endpoint, uint16_t short_addr); + void getLightColorHS(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void onLightStateChange(void (*callback)(bool)) { + _on_light_state_change = callback; + } + void onLightStateChangeWithSource(void (*callback)(bool, uint8_t, esp_zb_zcl_addr_t)) { + _on_light_state_change_with_source = callback; + } + void onLightLevelChange(void (*callback)(uint8_t)) { + _on_light_level_change = callback; + } + void onLightLevelChangeWithSource(void (*callback)(uint8_t, uint8_t, esp_zb_zcl_addr_t)) { + _on_light_level_change_with_source = callback; + } + void onLightColorChange(void (*callback)(uint8_t, uint8_t, uint8_t)) { + _on_light_color_change = callback; + } + void onLightColorChangeWithSource(void (*callback)(uint8_t, uint8_t, uint8_t, uint8_t, esp_zb_zcl_addr_t)) { + _on_light_color_change_with_source = callback; + } + +private: + // save instance of the class in order to use it in static functions + static ZigbeeColorDimmerSwitch *_instance; + zb_device_params_t *_device; + + espHsvColor_t _light_color_hsv; + espXyColor_t _light_color_xy; + espRgbColor_t _light_color_rgb; + + void (*_on_light_state_change)(bool); + void (*_on_light_state_change_with_source)(bool, uint8_t, esp_zb_zcl_addr_t); + void (*_on_light_level_change)(uint8_t); + void (*_on_light_level_change_with_source)(uint8_t, uint8_t, esp_zb_zcl_addr_t); + void (*_on_light_color_change)(uint8_t, uint8_t, uint8_t); + void (*_on_light_color_change_with_source)(uint8_t, uint8_t, uint8_t, uint8_t, esp_zb_zcl_addr_t); + + void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req); + void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx); + void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + static void bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx); + static void findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + + void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) override; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp new file mode 100644 index 0000000..35e05af --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp @@ -0,0 +1,171 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeContactSwitch.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_contact_switch_clusters_create(zigbee_contact_switch_cfg_t *contact_switch) { + esp_zb_basic_cluster_cfg_t *basic_cfg = contact_switch ? &(contact_switch->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = contact_switch ? &(contact_switch->identify_cfg) : NULL; + esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = contact_switch ? &(contact_switch->ias_zone_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeeContactSwitch::ZigbeeContactSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_IAS_ZONE_ID; + _zone_status = 0; + _zone_id = 0xff; + _ias_cie_endpoint = 1; + _enrolled = false; + + //Create custom contact switch configuration + zigbee_contact_switch_cfg_t contact_switch_cfg = ZIGBEE_DEFAULT_CONTACT_SWITCH_CONFIG(); + _cluster_list = zigbee_contact_switch_clusters_create(&contact_switch_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0}; +} + +void ZigbeeContactSwitch::setIASClientEndpoint(uint8_t ep_number) { + _ias_cie_endpoint = ep_number; +} + +bool ZigbeeContactSwitch::setClosed() { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Contact switch to closed"); + uint8_t closed = 0; // ALARM1 = 0, ALARM2 = 0 + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &closed, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set contact switch to closed: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = closed; + return report(); +} + +bool ZigbeeContactSwitch::setOpen() { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Contact switch to open"); + uint8_t open = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1 | ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM2; // ALARM1 = 1, ALARM2 = 1 + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &open, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set contact switch to open: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = open; + return report(); +} + +bool ZigbeeContactSwitch::report() { + /* Send IAS Zone status changed notification command */ + + esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd; + status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint; //default is 1 + memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t)); + + status_change_notif_cmd.zone_status = _zone_status; + status_change_notif_cmd.extend_status = 0; + status_change_notif_cmd.zone_id = _zone_id; + status_change_notif_cmd.delay = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone status changed notification sent"); + return true; +} + +void ZigbeeContactSwitch::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) { + log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code); + if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) { + log_v("IAS Zone Enroll Response: success"); + esp_zb_lock_acquire(portMAX_DELAY); + memcpy( + _ias_cie_addr, + (*(esp_zb_ieee_addr_t *) + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID) + ->data_p), + sizeof(esp_zb_ieee_addr_t) + ); + esp_zb_lock_release(); + _zone_id = message->zone_id; + _enrolled = true; + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster); + } +} + +bool ZigbeeContactSwitch::requestIASZoneEnroll() { + esp_zb_zcl_ias_zone_enroll_request_cmd_t enroll_request; + enroll_request.zcl_basic_cmd.src_endpoint = _endpoint; + enroll_request.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + enroll_request.zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_CONTACT_SWITCH; + enroll_request.manuf_code = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_enroll_cmd_req(&enroll_request); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone enroll request sent"); + return true; +} + +bool ZigbeeContactSwitch::restoreIASZoneEnroll() { + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_attr_t *ias_cie_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID); + esp_zb_zcl_attr_t *zone_id_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONEID_ID); + esp_zb_lock_release(); + + if (ias_cie_attr == NULL || ias_cie_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: ias cie address attribute not found"); + return false; + } + if (zone_id_attr == NULL || zone_id_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: zone id attribute not found"); + return false; + } + + memcpy(_ias_cie_addr, (esp_zb_ieee_addr_t *)ias_cie_attr->data_p, sizeof(esp_zb_ieee_addr_t)); + _zone_id = (*(uint8_t *)zone_id_attr->data_p); + + log_d( + "Restored IAS Zone enroll: zone id(%d), ias cie address(%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X)", _zone_id, _ias_cie_addr[0], _ias_cie_addr[1], + _ias_cie_addr[2], _ias_cie_addr[3], _ias_cie_addr[4], _ias_cie_addr[5], _ias_cie_addr[6], _ias_cie_addr[7] + ); + + if (_zone_id == 0xFF) { + log_e("Failed to restore IAS Zone enroll: zone id not valid"); + return false; + } + _enrolled = true; + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h new file mode 100644 index 0000000..002ed72 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h @@ -0,0 +1,93 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee contact switch (IAS Zone) endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_CONTACT_SWITCH_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .ias_zone_cfg = \ + { \ + .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED, \ + .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_CONTACT_SWITCH, \ + .zone_status = 0, \ + .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT, \ + .zone_id = 0xff, \ + .zone_ctx = {0, 0, 0, 0}, \ + }, \ + } +// clang-format on + +typedef struct zigbee_contact_switch_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg; +} zigbee_contact_switch_cfg_t; + +class ZigbeeContactSwitch : public ZigbeeEP { +public: + ZigbeeContactSwitch(uint8_t endpoint); + ~ZigbeeContactSwitch() {} + + // Set the IAS Client endpoint number (default is 1) + void setIASClientEndpoint(uint8_t ep_number); + + // Set the contact switch value to closed + bool setClosed(); + + // Set the contact switch value to open + bool setOpen(); + + // Report the contact switch value, done automatically after setting the position + bool report(); + + // Request a new IAS zone enroll, can be called to enroll a new device or to re-enroll an already enrolled device + bool requestIASZoneEnroll(); + + // Restore IAS Zone enroll, needed to be called after rebooting already enrolled device - restored from flash memory (faster for sleepy devices) + bool restoreIASZoneEnroll(); + + // Check if the device is enrolled in the IAS Zone + bool enrolled() { + return _enrolled; + } + +private: + void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override; + uint8_t _zone_status; + uint8_t _zone_id; + esp_zb_ieee_addr_t _ias_cie_addr; + uint8_t _ias_cie_endpoint; + bool _enrolled; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp new file mode 100644 index 0000000..1318cba --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp @@ -0,0 +1,128 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeDimmableLight.h" +#if CONFIG_ZB_ENABLED + +#include "esp_zigbee_cluster.h" + +ZigbeeDimmableLight::ZigbeeDimmableLight(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID; + _on_light_change = nullptr; + + zigbee_dimmable_light_cfg_t light_cfg = ZIGBEE_DEFAULT_DIMMABLE_LIGHT_CONFIG(); + _cluster_list = zigbee_dimmable_light_clusters_create(&light_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID, .app_device_version = 0}; + + // set default values + _current_state = false; + _current_level = 255; +} + +// set attribute method -> method overridden in child class +void ZigbeeDimmableLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + // check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + if (_current_state != *(bool *)message->attribute.data.value) { + _current_state = *(bool *)message->attribute.data.value; + lightChanged(); + } + return; + } else { + log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id); + } + } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) { + if (_current_level != *(uint8_t *)message->attribute.data.value) { + _current_level = *(uint8_t *)message->attribute.data.value; + lightChanged(); + } + return; + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Level Control", message->attribute.id); + // TODO: implement more attributes -> includes/zcl/esp_zigbee_zcl_level.h + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for dimmable Light", message->info.cluster); + } +} + +void ZigbeeDimmableLight::lightChanged() { + if (_on_light_change) { + _on_light_change(_current_state, _current_level); + } +} + +bool ZigbeeDimmableLight::setLight(bool state, uint8_t level) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update all attributes + _current_state = state; + _current_level = level; + lightChanged(); + + log_v("Updating on/off light state to %d", state); + /* Update light clusters */ + esp_zb_lock_acquire(portMAX_DELAY); + // set on/off state + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + // set level + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeDimmableLight::setLightState(bool state) { + return setLight(state, _current_level); +} + +bool ZigbeeDimmableLight::setLightLevel(uint8_t level) { + return setLight(_current_state, level); +} + +esp_zb_cluster_list_t *ZigbeeDimmableLight::zigbee_dimmable_light_clusters_create(zigbee_dimmable_light_cfg_t *light_cfg) { + esp_zb_attribute_list_t *esp_zb_basic_cluster = esp_zb_basic_cluster_create(&light_cfg->basic_cfg); + esp_zb_attribute_list_t *esp_zb_identify_cluster = esp_zb_identify_cluster_create(&light_cfg->identify_cfg); + esp_zb_attribute_list_t *esp_zb_groups_cluster = esp_zb_groups_cluster_create(&light_cfg->groups_cfg); + esp_zb_attribute_list_t *esp_zb_scenes_cluster = esp_zb_scenes_cluster_create(&light_cfg->scenes_cfg); + esp_zb_attribute_list_t *esp_zb_on_off_cluster = esp_zb_on_off_cluster_create(&light_cfg->on_off_cfg); + esp_zb_attribute_list_t *esp_zb_level_cluster = esp_zb_level_cluster_create(&light_cfg->level_cfg); + + // ------------------------------ Create cluster list ------------------------------ + esp_zb_cluster_list_t *esp_zb_cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(esp_zb_cluster_list, esp_zb_basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(esp_zb_cluster_list, esp_zb_identify_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_groups_cluster(esp_zb_cluster_list, esp_zb_groups_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_scenes_cluster(esp_zb_cluster_list, esp_zb_scenes_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_on_off_cluster(esp_zb_cluster_list, esp_zb_on_off_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_level_cluster(esp_zb_cluster_list, esp_zb_level_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + return esp_zb_cluster_list; +} + +#endif // SOC_IEEE802154_SUPPORTED diff --git a/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h new file mode 100644 index 0000000..da1d106 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h @@ -0,0 +1,126 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Light endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +/** + * @brief Zigbee HA standard dimmable light device clusters. + * Added here as not supported by ESP Zigbee library. + * + * + */ +typedef struct zigbee_dimmable_light_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; /*!< Basic cluster configuration, @ref esp_zb_basic_cluster_cfg_s */ + esp_zb_identify_cluster_cfg_t identify_cfg; /*!< Identify cluster configuration, @ref esp_zb_identify_cluster_cfg_s */ + esp_zb_groups_cluster_cfg_t groups_cfg; /*!< Groups cluster configuration, @ref esp_zb_groups_cluster_cfg_s */ + esp_zb_scenes_cluster_cfg_t scenes_cfg; /*!< Scenes cluster configuration, @ref esp_zb_scenes_cluster_cfg_s */ + esp_zb_on_off_cluster_cfg_t on_off_cfg; /*!< On off cluster configuration, @ref esp_zb_on_off_cluster_cfg_s */ + esp_zb_level_cluster_cfg_t level_cfg; /*!< Level cluster configuration, @ref esp_zb_level_cluster_cfg_s */ +} zigbee_dimmable_light_cfg_t; + +/** + * @brief Zigbee HA standard dimmable light device default config value. + * Added here as not supported by ESP Zigbee library. + * + */ +// clang-format off +#define ZIGBEE_DEFAULT_DIMMABLE_LIGHT_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .groups_cfg = \ + { \ + .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .scenes_cfg = \ + { \ + .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE, \ + .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE, \ + .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE, \ + .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE, \ + .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .on_off_cfg = \ + { \ + .on_off = ESP_ZB_ZCL_ON_OFF_ON_OFF_DEFAULT_VALUE, \ + }, \ + .level_cfg = \ + { \ + .current_level = ESP_ZB_ZCL_LEVEL_CONTROL_CURRENT_LEVEL_DEFAULT_VALUE, \ + }, \ + } +// clang-format on + +class ZigbeeDimmableLight : public ZigbeeEP { +public: + ZigbeeDimmableLight(uint8_t endpoint); + ~ZigbeeDimmableLight() {} + + void onLightChange(void (*callback)(bool, uint8_t)) { + _on_light_change = callback; + } + void restoreLight() { + lightChanged(); + } + + bool setLightState(bool state); + bool setLightLevel(uint8_t level); + bool setLight(bool state, uint8_t level); + + bool getLightState() { + return _current_state; + } + uint8_t getLightLevel() { + return _current_level; + } + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + void lightChanged(); + // callback function to be called on light change (State, Level) + void (*_on_light_change)(bool, uint8_t); + + /** + * @brief Create a standard HA dimmable light cluster list. + * Added here as not supported by ESP Zigbee library. + * + * @note This contains basic, identify, groups, scenes, on-off, level, as server side. + * @param[in] light_cfg Configuration parameters for this cluster lists defined by @ref zigbee_dimmable_light_cfg_t + * + * @return Pointer to cluster list @ref esp_zb_cluster_list_s + * + */ + esp_zb_cluster_list_t *zigbee_dimmable_light_clusters_create(zigbee_dimmable_light_cfg_t *light_cfg); + + bool _current_state; + uint8_t _current_level; +}; + +#endif // SOC_IEEE802154_SUPPORTED diff --git a/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp new file mode 100644 index 0000000..2a3a5c8 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp @@ -0,0 +1,188 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeDoorWindowHandle.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_door_window_handle_clusters_create(zigbee_door_window_handle_cfg_t *door_window_handle) { + esp_zb_basic_cluster_cfg_t *basic_cfg = door_window_handle ? &(door_window_handle->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = door_window_handle ? &(door_window_handle->identify_cfg) : NULL; + esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = door_window_handle ? &(door_window_handle->ias_zone_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeeDoorWindowHandle::ZigbeeDoorWindowHandle(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_IAS_ZONE_ID; + _zone_status = 0; + _zone_id = 0xff; + _ias_cie_endpoint = 1; + _enrolled = false; + + //Create custom door window handle configuration + zigbee_door_window_handle_cfg_t door_window_handle_cfg = ZIGBEE_DEFAULT_DOOR_WINDOW_HANDLE_CONFIG(); + _cluster_list = zigbee_door_window_handle_clusters_create(&door_window_handle_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0}; +} + +void ZigbeeDoorWindowHandle::setIASClientEndpoint(uint8_t ep_number) { + _ias_cie_endpoint = ep_number; +} + +bool ZigbeeDoorWindowHandle::setClosed() { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Door/Window handle to closed"); + uint8_t closed = 0; // ALARM1 = 0, ALARM2 = 0 + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &closed, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set door/window handle to closed: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = closed; + return report(); +} + +bool ZigbeeDoorWindowHandle::setOpen() { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Door/Window handle to open"); + uint8_t open = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1 | ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM2; // ALARM1 = 1, ALARM2 = 1 + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &open, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set door/window handle to open: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = open; + return report(); +} + +bool ZigbeeDoorWindowHandle::setTilted() { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Door/Window handle to tilted"); + uint8_t tilted = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1; // ALARM1 = 1, ALARM2 = 0 + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &tilted, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set door/window handle to tilted: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = tilted; + return report(); +} + +bool ZigbeeDoorWindowHandle::report() { + /* Send IAS Zone status changed notification command */ + + esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd; + status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint; //default is 1 + memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t)); + + status_change_notif_cmd.zone_status = _zone_status; + status_change_notif_cmd.extend_status = 0; + status_change_notif_cmd.zone_id = _zone_id; + status_change_notif_cmd.delay = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone status changed notification sent"); + return true; +} + +void ZigbeeDoorWindowHandle::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) { + log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code); + if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) { + log_v("IAS Zone Enroll Response: success"); + esp_zb_lock_acquire(portMAX_DELAY); + memcpy( + _ias_cie_addr, + (*(esp_zb_ieee_addr_t *) + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID) + ->data_p), + sizeof(esp_zb_ieee_addr_t) + ); + esp_zb_lock_release(); + _zone_id = message->zone_id; + _enrolled = true; + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster); + } +} + +bool ZigbeeDoorWindowHandle::requestIASZoneEnroll() { + esp_zb_zcl_ias_zone_enroll_request_cmd_t enroll_request; + enroll_request.zcl_basic_cmd.src_endpoint = _endpoint; + enroll_request.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + enroll_request.zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_DOOR_WINDOW_HANDLE; + enroll_request.manuf_code = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_enroll_cmd_req(&enroll_request); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone enroll request sent"); + return true; +} + +bool ZigbeeDoorWindowHandle::restoreIASZoneEnroll() { + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_attr_t *ias_cie_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID); + esp_zb_zcl_attr_t *zone_id_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONEID_ID); + esp_zb_lock_release(); + + if (ias_cie_attr == NULL || ias_cie_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: ias cie address attribute not found"); + return false; + } + if (zone_id_attr == NULL || zone_id_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: zone id attribute not found"); + return false; + } + + memcpy(_ias_cie_addr, (esp_zb_ieee_addr_t *)ias_cie_attr->data_p, sizeof(esp_zb_ieee_addr_t)); + _zone_id = (*(uint8_t *)zone_id_attr->data_p); + + log_d( + "Restored IAS Zone enroll: zone id(%d), ias cie address(%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X)", _zone_id, _ias_cie_addr[0], _ias_cie_addr[1], + _ias_cie_addr[2], _ias_cie_addr[3], _ias_cie_addr[4], _ias_cie_addr[5], _ias_cie_addr[6], _ias_cie_addr[7] + ); + + if (_zone_id == 0xFF) { + log_e("Failed to restore IAS Zone enroll: zone id not valid"); + return false; + } + _enrolled = true; + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h new file mode 100644 index 0000000..cfaf7e7 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h @@ -0,0 +1,97 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee door window handle (IAS Zone) endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +#define ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_DOOR_WINDOW_HANDLE 0x0016 +// clang-format off +#define ZIGBEE_DEFAULT_DOOR_WINDOW_HANDLE_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .ias_zone_cfg = \ + { \ + .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED, \ + .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_DOOR_WINDOW_HANDLE, \ + .zone_status = 0, \ + .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT, \ + .zone_id = 0xff, \ + .zone_ctx = {0, 0, 0, 0}, \ + }, \ + } +// clang-format on + +typedef struct zigbee_door_window_handle_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg; +} zigbee_door_window_handle_cfg_t; + +class ZigbeeDoorWindowHandle : public ZigbeeEP { +public: + ZigbeeDoorWindowHandle(uint8_t endpoint); + ~ZigbeeDoorWindowHandle() {} + + // Set the IAS Client endpoint number (default is 1) + void setIASClientEndpoint(uint8_t ep_number); + + // Set the door/window handle value to closed + bool setClosed(); + + // Set the door/window handle value to open + bool setOpen(); + + // Set the door/window handle value to tilted + bool setTilted(); + + // Report the door/window handle value, done automatically after setting the position + bool report(); + + // Request a new IAS zone enroll, can be called to enroll a new device or to re-enroll an already enrolled device + bool requestIASZoneEnroll(); + + // Restore IAS Zone enroll, needed to be called after rebooting already enrolled device - restored from flash memory (faster for sleepy devices) + bool restoreIASZoneEnroll(); + + // Check if the device is enrolled in the IAS Zone + bool enrolled() { + return _enrolled; + } + +private: + void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override; + uint8_t _zone_status; + uint8_t _zone_id; + esp_zb_ieee_addr_t _ias_cie_addr; + uint8_t _ias_cie_endpoint; + bool _enrolled; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.cpp b/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.cpp new file mode 100644 index 0000000..cbcc3ea --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.cpp @@ -0,0 +1,1002 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeElectricalMeasurement.h" +#if CONFIG_ZB_ENABLED + +// Workaround for wrong name in ZCL header +#define ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_ID ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DCPOWER_ID + +esp_zb_cluster_list_t *zigbee_electrical_measurement_clusters_create(zigbee_electrical_measurement_cfg_t *electrical_measurement) { + esp_zb_basic_cluster_cfg_t *basic_cfg = electrical_measurement ? &(electrical_measurement->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = electrical_measurement ? &(electrical_measurement->identify_cfg) : NULL; + esp_zb_electrical_meas_cluster_cfg_t *electrical_measurement_cfg = electrical_measurement ? &(electrical_measurement->electrical_measurement_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_electrical_meas_cluster( + cluster_list, esp_zb_electrical_meas_cluster_create(electrical_measurement_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE + ); + return cluster_list; +} + +ZigbeeElectricalMeasurement::ZigbeeElectricalMeasurement(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom pressure sensor configuration + zigbee_electrical_measurement_cfg_t electrical_measurement_cfg = ZIGBEE_DEFAULT_ELECTRICAL_MEASUREMENT_CONFIG(); + _cluster_list = zigbee_electrical_measurement_clusters_create(&electrical_measurement_cfg); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_METER_INTERFACE_DEVICE_ID, .app_device_version = 0 + }; +} + +/* DC MEASUREMENT */ + +bool ZigbeeElectricalMeasurement::addDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type) { + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + // Set the DC measurement type bit in the measurement type attribute + measure_type |= ESP_ZB_ZCL_ELECTRICAL_MEASUREMENT_DC_MEASUREMENT; + esp_zb_cluster_update_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_MEASUREMENT_TYPE_ID, &measure_type); + + int16_t default_min = -32767; + int16_t default_max = 32767; + int16_t default_measurement = 0; + uint16_t default_multiplier = 1; + uint16_t default_divisor = 1; + + esp_err_t ret = ESP_OK; + // Add the DC Voltage attributes + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE) { + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_ID, (void *)&default_measurement + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MIN_ID, (void *)&default_min); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MAX_ID, (void *)&default_max); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MULTIPLIER_ID, (void *)&default_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_DIVISOR_ID, (void *)&default_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + // Add the DC Current attributes + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_ID, (void *)&default_measurement + ); + if (ret != ESP_OK) { + log_e("Failed to add DC current: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MIN_ID, (void *)&default_min); + if (ret != ESP_OK) { + log_e("Failed to add DC current min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MAX_ID, (void *)&default_max); + if (ret != ESP_OK) { + log_e("Failed to add DC current max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MULTIPLIER_ID, (void *)&default_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add DC current multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_DIVISOR_ID, (void *)&default_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add DC current divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } else { //(measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) + // Add the DC Power attributes + ret = + esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_ID, (void *)&default_measurement); + if (ret != ESP_OK) { + log_e("Failed to add DC power: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MIN_ID, (void *)&default_min); + if (ret != ESP_OK) { + log_e("Failed to add DC power min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MAX_ID, (void *)&default_max); + if (ret != ESP_OK) { + log_e("Failed to add DC power max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MULTIPLIER_ID, (void *)&default_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add DC power multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_DIVISOR_ID, (void *)&default_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add DC power divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } + return true; +} + +bool ZigbeeElectricalMeasurement::setDCMinMaxValue(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, int16_t min, int16_t max) { + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + esp_zb_zcl_electrical_measurement_attr_t attr_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MIN_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MAX_ID; + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + attr_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MIN_ID; + attr_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MAX_ID; + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) { + attr_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MIN_ID; + attr_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MAX_ID; + } + esp_err_t ret = ESP_OK; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_min, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_max, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::setDCMultiplierDivisor(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, uint16_t multiplier, uint16_t divisor) { + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + esp_zb_zcl_electrical_measurement_attr_t attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_MULTIPLIER_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_DIVISOR_ID; + + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_DIVISOR_ID; + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) { + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_DIVISOR_ID; + } + + esp_err_t ret = ESP_OK; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_multiplier, (void *)&multiplier); + if (ret != ESP_OK) { + log_e("Failed to set multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_divisor, (void *)&divisor); + if (ret != ESP_OK) { + log_e("Failed to set divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::setDCReporting(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, uint16_t min_interval, uint16_t max_interval, int16_t delta) { + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_ID; + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_ID; + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_ID; + } + + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = attr_id; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.s16 = delta; + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::setDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, int16_t measurement) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + + esp_zb_zcl_electrical_measurement_attr_t attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_ID; + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_ID; + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_ID; + } + + log_v("Updating DC measurement value..."); + /* Update DC sensor measured value */ + log_d("Setting DC measurement to %d", measurement); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &measurement, false); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set DC measurement: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::reportDC(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type) { + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_VOLTAGE_ID; + if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_CURRENT_ID; + } else if (measurement_type == ZIGBEE_DC_MEASUREMENT_TYPE_POWER) { + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_DC_POWER_ID; + } + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = attr_id; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send DC report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("DC report sent"); + return true; +} + +/* AC MEASUREMENT */ + +bool ZigbeeElectricalMeasurement::addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type) { + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + // Non phase specific dont need any bit set + break; + case ZIGBEE_AC_PHASE_TYPE_A: measure_type |= ESP_ZB_ZCL_ELECTRICAL_MEASUREMENT_PHASE_A_MEASUREMENT; break; + case ZIGBEE_AC_PHASE_TYPE_B: measure_type |= ESP_ZB_ZCL_ELECTRICAL_MEASUREMENT_PHASE_B_MEASUREMENT; break; + case ZIGBEE_AC_PHASE_TYPE_C: measure_type |= ESP_ZB_ZCL_ELECTRICAL_MEASUREMENT_PHASE_C_MEASUREMENT; break; + default: log_e("Invalid phase type"); break; + } + // Set Active measurement bit for active power and power factor, otherwise no bit needed for voltage, current + if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER || measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR) { + measure_type |= ESP_ZB_ZCL_ELECTRICAL_MEASUREMENT_ACTIVE_MEASUREMENT; // Active power is used + } + // Update the measurement type attribute + esp_zb_cluster_update_attr(electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_MEASUREMENT_TYPE_ID, &measure_type); + + // Default values for AC measurements + [[maybe_unused]] + int16_t default_ac_power_min = -32767; + [[maybe_unused]] + int16_t default_ac_power_max = 32767; + [[maybe_unused]] + int16_t default_ac_power_measurement = 0; + [[maybe_unused]] + uint16_t default_ac_min = 0x0000; + [[maybe_unused]] + uint16_t default_ac_max = 0xffff; + [[maybe_unused]] + uint16_t default_ac_measurement = 0x0000; + [[maybe_unused]] + uint16_t default_ac_multiplier = 1; + [[maybe_unused]] + uint16_t default_ac_divisor = 1; + [[maybe_unused]] + int8_t default_ac_power_factor = 100; + + esp_err_t ret = ESP_OK; + + // AC Frequency + if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY) { // No phase specific + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_ID, (void *)&default_ac_measurement + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_MIN_ID, (void *)&default_ac_min + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_MAX_ID, (void *)&default_ac_max + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_MULTIPLIER_ID, (void *)&default_ac_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_DIVISOR_ID, (void *)&default_ac_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add DC voltage divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; + } + // Add the AC Voltage attributes + else if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE) { + esp_zb_zcl_electrical_measurement_attr_t attr_voltage = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_voltage_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_voltage_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_ID; + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + // already set + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_voltage = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHB_ID; + attr_voltage_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_PH_B_ID; + attr_voltage_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_voltage = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHC_ID; + attr_voltage_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_PH_C_ID; + attr_voltage_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_voltage, (void *)&default_ac_measurement); + if (ret != ESP_OK) { + log_e("Failed to add AC voltage: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_voltage_min, (void *)&default_ac_min); + if (ret != ESP_OK) { + log_e("Failed to add AC voltage min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_voltage_max, (void *)&default_ac_max); + if (ret != ESP_OK) { + log_e("Failed to add AC voltage max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + if (!ac_volt_mult_div_set) { + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACVOLTAGE_MULTIPLIER_ID, (void *)&default_ac_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add AC voltage multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACVOLTAGE_DIVISOR_ID, (void *)&default_ac_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add AC voltage divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ac_volt_mult_div_set = true; // Set flag to true, so we dont add the attributes again + } + } + // Add the AC Current attributes + else if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT) { + esp_zb_zcl_electrical_measurement_attr_t attr_current = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_current_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_current_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_ID; + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + // already set + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_current = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHB_ID; + attr_current_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_PH_B_ID; + attr_current_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_current = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHC_ID; + attr_current_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_PH_C_ID; + attr_current_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_current, (void *)&default_ac_measurement); + if (ret != ESP_OK) { + log_e("Failed to add AC current: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_current_min, (void *)&default_ac_min); + if (ret != ESP_OK) { + log_e("Failed to add AC current min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_current_max, (void *)&default_ac_max); + if (ret != ESP_OK) { + log_e("Failed to add AC current max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + if (!ac_current_mult_div_set) { + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACCURRENT_MULTIPLIER_ID, (void *)&default_ac_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add AC current multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACCURRENT_DIVISOR_ID, (void *)&default_ac_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add AC current divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ac_current_mult_div_set = true; // Set flag to true, so we dont add the attributes again + } + } + // Add the AC Power attributes + else if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER) { + esp_zb_zcl_electrical_measurement_attr_t attr_power = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_power_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_ID; + esp_zb_zcl_electrical_measurement_attr_t attr_power_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_ID; + + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + // already set + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_power = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHB_ID; + attr_power_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_PH_B_ID; + attr_power_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_power = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHC_ID; + attr_power_min = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_PH_C_ID; + attr_power_max = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_power, (void *)&default_ac_measurement); + if (ret != ESP_OK) { + log_e("Failed to add AC power: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_power_min, (void *)&default_ac_min); + if (ret != ESP_OK) { + log_e("Failed to add AC power min: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_power_max, (void *)&default_ac_max); + if (ret != ESP_OK) { + log_e("Failed to add AC power max: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + if (!ac_power_mult_div_set) { + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACPOWER_MULTIPLIER_ID, (void *)&default_ac_multiplier + ); + if (ret != ESP_OK) { + log_e("Failed to add AC power multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr( + electrical_measurement_cluster, ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACPOWER_DIVISOR_ID, (void *)&default_ac_divisor + ); + if (ret != ESP_OK) { + log_e("Failed to add AC power divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ac_power_mult_div_set = true; // Set flag to true, so we dont add the attributes again + } + } else { //(measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR) + esp_zb_zcl_electrical_measurement_attr_t attr_power_factor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_ID; + + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + // already set + break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_power_factor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_B_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_power_factor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_C_ID; break; + default: log_e("Invalid phase type"); return false; + } + ret = esp_zb_electrical_meas_cluster_add_attr(electrical_measurement_cluster, attr_power_factor, (void *)&default_ac_power_factor); + if (ret != ESP_OK) { + log_e("Failed to add AC power factor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } + return true; +} + +bool ZigbeeElectricalMeasurement::setACMinMaxValue( + ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, int32_t min_value, int32_t max_value +) { + uint16_t attr_min_id = 0; + uint16_t attr_max_id = 0; + + // Check min/max values are valid for the measurement type + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: + if (min_value < 0 || min_value > UINT16_MAX || max_value < 0 || max_value > UINT16_MAX) { + log_e("AC measurement min/max values must be between 0 and %u (got min=%d, max=%d)", UINT16_MAX, min_value, max_value); + return false; + } + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + if (min_value < INT16_MIN || min_value > INT16_MAX || max_value < INT16_MIN || max_value > INT16_MAX) { + log_e("AC power min/max values must be between %d and %d (got min=%d, max=%d)", INT16_MIN, INT16_MAX, min_value, max_value); + return false; + } + break; + + default: log_e("Invalid measurement type"); return false; + } + + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_PH_B_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MIN_PH_C_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_VOLTAGE_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_PH_B_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MIN_PH_C_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMS_CURRENT_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_B: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_PH_B_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_PH_B_ID; + break; + case ZIGBEE_AC_PHASE_TYPE_C: + attr_min_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MIN_PH_C_ID; + attr_max_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_MAX_PH_C_ID; + break; + default: log_e("Invalid phase type"); return false; + } + break; + + default: log_e("Invalid measurement type"); return false; + } + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + esp_err_t ret = ESP_OK; + if (measure_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER) { + int16_t int16_min_value = (int16_t)min_value; + int16_t int16_max_value = (int16_t)max_value; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_min_id, (void *)&int16_min_value); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_max_id, (void *)&int16_max_value); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } else { + uint16_t uint16_min_value = (uint16_t)min_value; + uint16_t uint16_max_value = (uint16_t)max_value; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_min_id, (void *)&uint16_min_value); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_max_id, (void *)&uint16_max_value); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + } + return true; +} + +bool ZigbeeElectricalMeasurement::setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, uint16_t multiplier, uint16_t divisor) { + uint16_t attr_multiplier = 0; + uint16_t attr_divisor = 0; + + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACVOLTAGE_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACVOLTAGE_DIVISOR_ID; + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACCURRENT_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACCURRENT_DIVISOR_ID; + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACPOWER_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACPOWER_DIVISOR_ID; + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: + attr_multiplier = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_MULTIPLIER_ID; + attr_divisor = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_DIVISOR_ID; + break; + default: log_e("Invalid measurement type"); return false; + } + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + esp_err_t ret = ESP_OK; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_multiplier, (void *)&multiplier); + if (ret != ESP_OK) { + log_e("Failed to set multiplier: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_divisor, (void *)&divisor); + if (ret != ESP_OK) { + log_e("Failed to set divisor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::setACPowerFactor(ZIGBEE_AC_PHASE_TYPE phase_type, int8_t power_factor) { + uint16_t attr_id = 0; + + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_B_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_C_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + + esp_zb_attribute_list_t *electrical_measurement_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + esp_err_t ret = ESP_OK; + ret = esp_zb_cluster_update_attr(electrical_measurement_cluster, attr_id, (void *)&power_factor); + if (ret != ESP_OK) { + log_e("Failed to set power factor: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} +bool ZigbeeElectricalMeasurement::setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, int32_t value) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + uint16_t attr_id = 0; + + // Check value is valid for the measurement type + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: + if (value < 0 || value > UINT16_MAX) { + log_e("AC measurement value must be between 0 and %u (got %d)", UINT16_MAX, value); + return false; + } + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + if (value < INT16_MIN || value > INT16_MAX) { + log_e("AC power value must be between %d and %d (got %d)", INT16_MIN, INT16_MAX, value); + return false; + } + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR: + if (value < -100 || value > 100) { + log_e("AC power factor value must be between -100 and 100 (got %d)", value); + return false; + } + break; + + default: log_e("Invalid measurement type"); return false; + } + // Convert value to appropriate type based on measurement type + uint16_t uint16_value = (uint16_t)value; + int16_t int16_value = (int16_t)value; + int8_t int8_value = (int8_t)value; + + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + // Use uint16_t for voltage + log_v("Updating AC voltage measurement value..."); + log_d("Setting AC voltage to %u", uint16_value); + esp_zb_lock_acquire(portMAX_DELAY); + ret = + esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &uint16_value, false); + esp_zb_lock_release(); + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + // Use uint16_t for current + log_v("Updating AC current measurement value..."); + log_d("Setting AC current to %u", uint16_value); + esp_zb_lock_acquire(portMAX_DELAY); + ret = + esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &uint16_value, false); + esp_zb_lock_release(); + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + // Use int16_t for power + log_v("Updating AC power measurement value..."); + log_d("Setting AC power to %d", int16_value); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &int16_value, false); + esp_zb_lock_release(); + break; + + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: + attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_ID; + // Use uint16_t for frequency + log_v("Updating AC frequency measurement value..."); + log_d("Setting AC frequency to %u", uint16_value); + esp_zb_lock_acquire(portMAX_DELAY); + ret = + esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &uint16_value, false); + esp_zb_lock_release(); + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_B_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_POWER_FACTOR_PH_C_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + // Use int8_t for power factor + log_v("Updating AC power factor measurement value..."); + log_d("Setting AC power factor to %d", int8_value); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, attr_id, &int8_value, false); + esp_zb_lock_release(); + break; + default: log_e("Invalid measurement type"); return false; + } + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set AC measurement: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::setACReporting( + ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, uint16_t min_interval, uint16_t max_interval, int32_t delta +) { + uint16_t attr_id = 0; + + // Convert value to appropriate type based on measurement type + uint16_t uint16_delta = (uint16_t)delta; + int16_t int16_delta = (int16_t)delta; + + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_ID; break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR: log_e("Power factor attribute reporting not supported by zigbee specification"); return false; + default: log_e("Invalid measurement type"); return false; + } + + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = attr_id; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + if (measurement_type == ZIGBEE_AC_MEASUREMENT_TYPE_POWER) { + reporting_info.u.send_info.delta.s16 = int16_delta; + } else { + reporting_info.u.send_info.delta.u16 = uint16_delta; + } + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeElectricalMeasurement::reportAC(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type) { + uint16_t attr_id = 0; + + switch (measurement_type) { + case ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSVOLTAGE_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_RMSCURRENT_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER: + switch (phase_type) { + case ZIGBEE_AC_PHASE_TYPE_A: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_ID; break; + case ZIGBEE_AC_PHASE_TYPE_B: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHB_ID; break; + case ZIGBEE_AC_PHASE_TYPE_C: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_ACTIVE_POWER_PHC_ID; break; + case ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC: + default: log_e("Invalid phase type"); return false; + } + break; + case ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY: attr_id = ESP_ZB_ZCL_ATTR_ELECTRICAL_MEASUREMENT_AC_FREQUENCY_ID; break; + case ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR: log_e("Power factor attribute reporting not supported by zigbee specification"); return false; + default: log_e("Invalid measurement type"); return false; + } + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = attr_id; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ELECTRICAL_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send AC report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("AC report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.h b/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.h new file mode 100644 index 0000000..61879b3 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeElectricalMeasurement.h @@ -0,0 +1,119 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_ELECTRICAL_MEASUREMENT_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .electrical_measurement_cfg = \ + { \ + .measured_type = 0x00, \ + }, \ + } +// clang-format on + +enum ZIGBEE_DC_MEASUREMENT_TYPE { + ZIGBEE_DC_MEASUREMENT_TYPE_VOLTAGE = 0x0001, + ZIGBEE_DC_MEASUREMENT_TYPE_CURRENT = 0x0002, + ZIGBEE_DC_MEASUREMENT_TYPE_POWER = 0x0003, +}; + +enum ZIGBEE_AC_MEASUREMENT_TYPE { + ZIGBEE_AC_MEASUREMENT_TYPE_VOLTAGE = 0x0001, + ZIGBEE_AC_MEASUREMENT_TYPE_CURRENT = 0x0002, + ZIGBEE_AC_MEASUREMENT_TYPE_POWER = 0x0003, + ZIGBEE_AC_MEASUREMENT_TYPE_POWER_FACTOR = 0x0004, + ZIGBEE_AC_MEASUREMENT_TYPE_FREQUENCY = 0x0005, +}; + +enum ZIGBEE_AC_PHASE_TYPE { + ZIGBEE_AC_PHASE_TYPE_NON_SPECIFIC = 0x0000, + ZIGBEE_AC_PHASE_TYPE_A = 0x0001, + ZIGBEE_AC_PHASE_TYPE_B = 0x0002, + ZIGBEE_AC_PHASE_TYPE_C = 0x0003, +}; + +typedef struct zigbee_electrical_measurement_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_electrical_meas_cluster_cfg_t electrical_measurement_cfg; +} zigbee_electrical_measurement_cfg_t; + +class ZigbeeElectricalMeasurement : public ZigbeeEP { +public: + ZigbeeElectricalMeasurement(uint8_t endpoint); + ~ZigbeeElectricalMeasurement() {} + + /** + * @brief DC measurement methods + */ + // Add a DC measurement type + bool addDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type); + // Set the DC measurement value for the given measurement type + bool setDCMeasurement(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, int16_t value); + // Set the DC min and max value for the given measurement type + bool setDCMinMaxValue(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, int16_t min, int16_t max); + // Set the DC multiplier and divisor for the given measurement type + bool setDCMultiplierDivisor(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, uint16_t multiplier, uint16_t divisor); + // Set the DC reporting interval for the given measurement type in seconds and delta (measurement change) + bool setDCReporting(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type, uint16_t min_interval, uint16_t max_interval, int16_t delta); + // Report the DC measurement value for the given measurement type + bool reportDC(ZIGBEE_DC_MEASUREMENT_TYPE measurement_type); + + /** + * @brief AC measurement methods + */ + // Add an AC measurement type for selected phase type + bool addACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type); + // Set the AC measurement value for the given measurement type and phase type (uint16_t for voltage, current and frequency, int16_t for power) + bool setACMeasurement(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, int32_t value); + // Set the AC min and max value for the given measurement type and phase type (uint16_t for voltage, current and frequency, int16_t for power) + bool setACMinMaxValue(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, int32_t min, int32_t max); + // Set the AC multiplier and divisor for the given measurement type (common for all phases) + bool setACMultiplierDivisor(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, uint16_t multiplier, uint16_t divisor); + // Set the AC power factor for the given phase type (-100 to 100 %) + bool setACPowerFactor(ZIGBEE_AC_PHASE_TYPE phase_type, int8_t power_factor); + // Set the AC reporting interval for the given measurement type and phase type in seconds and delta (measurement change - uint16_t for voltage, current and frequency, int16_t for power) + bool + setACReporting(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type, uint16_t min_interval, uint16_t max_interval, int32_t delta); + // Report the AC measurement value for the given measurement type and phase type + bool reportAC(ZIGBEE_AC_MEASUREMENT_TYPE measurement_type, ZIGBEE_AC_PHASE_TYPE phase_type); + +private: + uint32_t measure_type = 0x0000; + bool ac_volt_mult_div_set = false; + bool ac_current_mult_div_set = false; + bool ac_power_mult_div_set = false; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeFanControl.cpp b/libraries/Zigbee/src/ep/ZigbeeFanControl.cpp new file mode 100644 index 0000000..623003b --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeFanControl.cpp @@ -0,0 +1,84 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeFanControl.h" +#if CONFIG_ZB_ENABLED + +ZigbeeFanControl::ZigbeeFanControl(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_THERMOSTAT_DEVICE_ID; //There is no FAN_CONTROL_DEVICE_ID in the Zigbee spec + _on_fan_mode_change = nullptr; + + //Create basic analog sensor clusters without configuration + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_fan_control_cluster(_cluster_list, esp_zb_fan_control_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_HEATING_COOLING_UNIT_DEVICE_ID, .app_device_version = 0 + }; +} + +bool ZigbeeFanControl::setFanModeSequence(ZigbeeFanModeSequence sequence) { + esp_zb_attribute_list_t *fan_control_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FAN_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(fan_control_cluster, ESP_ZB_ZCL_ATTR_FAN_CONTROL_FAN_MODE_SEQUENCE_ID, (void *)&sequence); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + _current_fan_mode_sequence = sequence; + _current_fan_mode = FAN_MODE_OFF; + // Set initial fan mode to OFF + ret = esp_zb_cluster_update_attr(fan_control_cluster, ESP_ZB_ZCL_ATTR_FAN_CONTROL_FAN_MODE_ID, (void *)&_current_fan_mode); + if (ret != ESP_OK) { + log_e("Failed to set fan mode: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +//set attribute method -> method overridden in child class +void ZigbeeFanControl::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + //check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_FAN_CONTROL) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_FAN_CONTROL_FAN_MODE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_8BIT_ENUM) { + if (message->attribute.data.value != nullptr && message->attribute.data.size >= 1) { + uint8_t raw_mode = *(const uint8_t *)message->attribute.data.value; + if (raw_mode <= FAN_MODE_SMART) { + _current_fan_mode = (ZigbeeFanMode)raw_mode; + fanModeChanged(); + } else { + log_w("Fan mode value out of range: %u, ignoring", raw_mode); + } + } else { + log_w("Invalid fan mode attribute: value=%p size=%u", message->attribute.data.value, message->attribute.data.size); + } + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Fan Control", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Fan Control", message->info.cluster); + } +} + +void ZigbeeFanControl::fanModeChanged() { + if (_on_fan_mode_change) { + _on_fan_mode_change(_current_fan_mode); + } else { + log_w("No callback function set for fan mode change"); + } +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeFanControl.h b/libraries/Zigbee/src/ep/ZigbeeFanControl.h new file mode 100644 index 0000000..75d614e --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeFanControl.h @@ -0,0 +1,79 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// Custom Arduino-friendly enums for fan mode values +enum ZigbeeFanMode { + FAN_MODE_OFF = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_OFF, + FAN_MODE_LOW = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_LOW, + FAN_MODE_MEDIUM = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_MEDIUM, + FAN_MODE_HIGH = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_HIGH, + FAN_MODE_ON = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_ON, + FAN_MODE_AUTO = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_AUTO, + FAN_MODE_SMART = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SMART, +}; + +// Custom Arduino-friendly enums for fan mode sequence +enum ZigbeeFanModeSequence { + FAN_MODE_SEQUENCE_LOW_MED_HIGH = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SEQUENCE_LOW_MED_HIGH, + FAN_MODE_SEQUENCE_LOW_HIGH = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SEQUENCE_LOW_HIGH, + FAN_MODE_SEQUENCE_LOW_MED_HIGH_AUTO = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SEQUENCE_LOW_MED_HIGH_AUTO, + FAN_MODE_SEQUENCE_LOW_HIGH_AUTO = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SEQUENCE_LOW_HIGH_AUTO, + FAN_MODE_SEQUENCE_ON_AUTO = ESP_ZB_ZCL_FAN_CONTROL_FAN_MODE_SEQUENCE_ON_AUTO, +}; + +class ZigbeeFanControl : public ZigbeeEP { +public: + ZigbeeFanControl(uint8_t endpoint); + ~ZigbeeFanControl() {} + + // Set the fan mode sequence value + bool setFanModeSequence(ZigbeeFanModeSequence sequence); + + // Use to get fan mode + ZigbeeFanMode getFanMode() { + return _current_fan_mode; + } + + // Use to get fan mode sequence + ZigbeeFanModeSequence getFanModeSequence() { + return _current_fan_mode_sequence; + } + + // On fan mode change callback + void onFanModeChange(void (*callback)(ZigbeeFanMode mode)) { + _on_fan_mode_change = callback; + } + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + //callback function to be called on fan mode change + void (*_on_fan_mode_change)(ZigbeeFanMode mode); + void fanModeChanged(); + + ZigbeeFanMode _current_fan_mode; + ZigbeeFanModeSequence _current_fan_mode_sequence; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp new file mode 100644 index 0000000..bd3c52a --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp @@ -0,0 +1,151 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeFlowSensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_flow_sensor_clusters_create(zigbee_flow_sensor_cfg_t *flow_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = flow_sensor ? &(flow_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = flow_sensor ? &(flow_sensor->identify_cfg) : NULL; + esp_zb_flow_meas_cluster_cfg_t *flow_meas_cfg = flow_sensor ? &(flow_sensor->flow_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_flow_meas_cluster(cluster_list, esp_zb_flow_meas_cluster_create(flow_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeeFlowSensor::ZigbeeFlowSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom pressure sensor configuration + zigbee_flow_sensor_cfg_t flow_sensor_cfg = ZIGBEE_DEFAULT_FLOW_SENSOR_CONFIG(); + _cluster_list = zigbee_flow_sensor_clusters_create(&flow_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeFlowSensor::setDefaultValue(float defaultValue) { + uint16_t zb_default_value = (uint16_t)(defaultValue * 10); + esp_zb_attribute_list_t *flow_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID, (void *)&zb_default_value); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeFlowSensor::setMinMaxValue(float min, float max) { + uint16_t zb_min = (uint16_t)(min * 10); + uint16_t zb_max = (uint16_t)(max * 10); + esp_zb_attribute_list_t *flow_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_MIN_VALUE_ID, (void *)&zb_min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_MAX_VALUE_ID, (void *)&zb_max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeFlowSensor::setTolerance(float tolerance) { + uint16_t zb_tolerance = (uint16_t)(tolerance * 10); + esp_zb_attribute_list_t *flow_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_flow_meas_cluster_add_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeFlowSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 10); // Convert delta to ZCL uint16_t + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeFlowSensor::setFlow(float flow) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + uint16_t zb_flow = (uint16_t)(flow * 10); + log_v("Updating flow sensor value..."); + /* Update temperature sensor measured value */ + log_d("Setting flow to %d", zb_flow); + + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID, &zb_flow, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set flow value: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeFlowSensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + + if (ret != ESP_OK) { + log_e("Failed to send flow report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Flow report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h new file mode 100644 index 0000000..0bc7b76 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h @@ -0,0 +1,78 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Flow sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_FLOW_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .flow_meas_cfg = \ + { \ + .measured_value = 0, \ + .min_value = 0, \ + .max_value = 0x7FFF, \ + }, \ + } +// clang-format on + +typedef struct zigbee_flow_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_flow_meas_cluster_cfg_t flow_meas_cfg; +} zigbee_flow_sensor_cfg_t; + +class ZigbeeFlowSensor : public ZigbeeEP { +public: + ZigbeeFlowSensor(uint8_t endpoint); + ~ZigbeeFlowSensor() {} + + // Set the flow value in 0,1 m3/h + bool setFlow(float value); + + // Set the default (initial) value for the flow sensor in 0,1 m3/h + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(float defaultValue); + + // Set the min and max value for the flow sensor in 0,1 m3/h + bool setMinMaxValue(float min, float max); + + // Set the tolerance value for the flow sensor in 0,01 m3/h + bool setTolerance(float tolerance); + + // Set the reporting interval for flow measurement in seconds and delta (temp change in 0,1 m3/h) + bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta); + + // Report the flow value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeGateway.cpp b/libraries/Zigbee/src/ep/ZigbeeGateway.cpp new file mode 100644 index 0000000..2640efc --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeGateway.cpp @@ -0,0 +1,29 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeGateway.h" +#if CONFIG_ZB_ENABLED + +ZigbeeGateway::ZigbeeGateway(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID; + + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID, .app_device_version = 0}; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeGateway.h b/libraries/Zigbee/src/ep/ZigbeeGateway.h new file mode 100644 index 0000000..e5ec3c0 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeGateway.h @@ -0,0 +1,32 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Gateway endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeeGateway : public ZigbeeEP { +public: + ZigbeeGateway(uint8_t endpoint); + ~ZigbeeGateway() {} +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp new file mode 100644 index 0000000..a904b68 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp @@ -0,0 +1,132 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeIlluminanceSensor.h" +#if CONFIG_ZB_ENABLED + +ZigbeeIlluminanceSensor::ZigbeeIlluminanceSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID; + + esp_zb_light_sensor_cfg_t light_sensor_cfg = ZIGBEE_DEFAULT_ILLUMINANCE_SENSOR_CONFIG(); + _cluster_list = esp_zb_light_sensor_clusters_create(&light_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeIlluminanceSensor::setDefaultValue(uint16_t defaultValue) { + esp_zb_attribute_list_t *light_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID, (void *)&defaultValue); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeIlluminanceSensor::setMinMaxValue(uint16_t min, uint16_t max) { + esp_zb_attribute_list_t *light_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeIlluminanceSensor::setTolerance(uint16_t tolerance) { + esp_zb_attribute_list_t *light_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_illuminance_meas_cluster_add_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeIlluminanceSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = delta; + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeIlluminanceSensor::setIlluminance(uint16_t illuminanceValue) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Updating Illuminance..."); + /* Update illuminance sensor measured illuminance */ + log_d("Setting Illuminance to %d", illuminanceValue); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID, + &illuminanceValue, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set illuminance: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeIlluminanceSensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send illuminance report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Illuminance report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h new file mode 100644 index 0000000..5ae36b0 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h @@ -0,0 +1,69 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Illuminance sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +#define ZIGBEE_DEFAULT_ILLUMINANCE_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .illuminance_cfg = { \ + .measured_value = ESP_ZB_ZCL_ILLUMINANCE_MEASUREMENT_LIGHT_SENSOR_TYPE_DEFAULT_VALUE, \ + .min_value = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MIN_MEASURED_VALUE_MIN_VALUE, \ + .max_value = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MAX_MEASURED_VALUE_MAX_VALUE, \ + }, \ + } + +class ZigbeeIlluminanceSensor : public ZigbeeEP { +public: + ZigbeeIlluminanceSensor(uint8_t endpoint); + ~ZigbeeIlluminanceSensor() {} + + // Set the illuminance value + bool setIlluminance(uint16_t value); + + // Set the default (initial) value for the illuminance sensor + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(uint16_t defaultValue); + + // Set the min and max value for the illuminance sensor + bool setMinMaxValue(uint16_t min, uint16_t max); + + // Set the tolerance value for the illuminance sensor + bool setTolerance(uint16_t tolerance); + + // Set the reporting interval for illuminance measurement in seconds and delta + bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta); + + // Report the illuminance value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeLight.cpp b/libraries/Zigbee/src/ep/ZigbeeLight.cpp new file mode 100644 index 0000000..579498c --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeLight.cpp @@ -0,0 +1,71 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeLight.h" +#if CONFIG_ZB_ENABLED + +ZigbeeLight::ZigbeeLight(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID; + _on_light_change = nullptr; + + esp_zb_on_off_light_cfg_t light_cfg = ESP_ZB_DEFAULT_ON_OFF_LIGHT_CONFIG(); + _cluster_list = esp_zb_on_off_light_clusters_create(&light_cfg); // use esp_zb_zcl_cluster_list_create() instead of esp_zb_on_off_light_clusters_create() + _ep_config = {.endpoint = endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID, .app_device_version = 0}; + log_v("Light endpoint created %d", _endpoint); +} + +//set attribute method -> method overridden in child class +void ZigbeeLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + //check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + _current_state = *(bool *)message->attribute.data.value; + lightChanged(); + } else { + log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster); + } +} + +void ZigbeeLight::lightChanged() { + if (_on_light_change) { + _on_light_change(_current_state); + } else { + log_w("No callback function set for light change"); + } +} + +bool ZigbeeLight::setLight(bool state) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + _current_state = state; + lightChanged(); + + log_v("Updating on/off light state to %d", state); + /* Update on/off light state */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeLight.h b/libraries/Zigbee/src/ep/ZigbeeLight.h new file mode 100644 index 0000000..ce88a7a --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeLight.h @@ -0,0 +1,55 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Light endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeeLight : public ZigbeeEP { +public: + ZigbeeLight(uint8_t endpoint); + ~ZigbeeLight() {} + + // Use to set a cb function to be called on light change + void onLightChange(void (*callback)(bool)) { + _on_light_change = callback; + } + // Use to restore light state + void restoreLight() { + lightChanged(); + } + // Use to control light state + bool setLight(bool state); + // Use to get light state + bool getLightState() { + return _current_state; + } + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + //callback function to be called on light change + void (*_on_light_change)(bool); + void lightChanged(); + + bool _current_state; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeMultistate.cpp b/libraries/Zigbee/src/ep/ZigbeeMultistate.cpp new file mode 100644 index 0000000..ddfffbf --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeMultistate.cpp @@ -0,0 +1,457 @@ +#include "ZigbeeMultistate.h" +#if CONFIG_ZB_ENABLED + +// Workaround for ESP-ZIGBEE-SDK 1.6.6 known issue +#ifdef __cplusplus +extern "C" { +#endif +extern void esp_zb_zcl_multi_input_init_server(void); +extern void esp_zb_zcl_multi_input_init_client(void); + +void esp_zb_zcl_multistate_input_init_server(void) { + esp_zb_zcl_multi_input_init_server(); +} +void esp_zb_zcl_multistate_input_init_client(void) { + esp_zb_zcl_multi_input_init_client(); +} +#ifdef __cplusplus +} +#endif + +ZigbeeMultistate::ZigbeeMultistate(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create basic multistate clusters without configuration + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; + + // Initialize member variables + _multistate_clusters = 0; + _input_state = 0; + _output_state = 0; + _input_state_names_length = 0; + _output_state_names_length = 0; + // _input_state_names = nullptr; + // _output_state_names = nullptr; + _on_multistate_output_change = nullptr; +} + +bool ZigbeeMultistate::addMultistateInput() { + esp_zb_multistate_input_cluster_cfg_t multistate_input_cfg = { + .number_of_states = 3, .out_of_service = false, .present_value = 0, .status_flags = ESP_ZB_ZCL_MULTI_VALUE_STATUS_FLAGS_NORMAL + }; + + esp_zb_attribute_list_t *multistate_input_cluster = esp_zb_multistate_input_cluster_create(&multistate_input_cfg); + + // Create default description for Multistate Input + char default_description[] = "\x10" // Size of the description text + "Multistate Input"; // Description text + uint32_t application_type = 0x00000000 | (0x0D << 24); // Application type + // const char* state_text[] = { "Off", "On", "Auto" }; // State text array + + esp_err_t ret = esp_zb_multistate_input_cluster_add_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_multistate_input_cluster_add_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + // ret = esp_zb_multistate_input_cluster_add_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_STATE_TEXT_ID, (void *)state_text); + // if (ret != ESP_OK) { + // log_e("Failed to add state text attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + // return false; + // } + + ret = esp_zb_cluster_list_add_multistate_input_cluster(_cluster_list, multistate_input_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Multistate Input cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + _multistate_clusters |= MULTISTATE_INPUT; + return true; +} + +bool ZigbeeMultistate::addMultistateOutput() { + esp_zb_multistate_output_cluster_cfg_t multistate_output_cfg = { + .number_of_states = 3, .out_of_service = false, .present_value = 0, .status_flags = ESP_ZB_ZCL_MULTI_VALUE_STATUS_FLAGS_NORMAL + }; + + esp_zb_attribute_list_t *multistate_output_cluster = esp_zb_multistate_output_cluster_create(&multistate_output_cfg); + + // Create default description for Multistate Output + char default_description[] = "\x11" // Size of the description text + "Multistate Output"; // Description text + uint32_t application_type = 0x00000000 | (0x0E << 24); + // const char* state_text[] = { "Off", "On", "Auto" }; // State text array + + esp_err_t ret = + esp_zb_multistate_output_cluster_add_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_DESCRIPTION_ID, (void *)default_description); + if (ret != ESP_OK) { + log_e("Failed to add description attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + ret = esp_zb_multistate_output_cluster_add_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type); + if (ret != ESP_OK) { + log_e("Failed to add application type attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + // ret = esp_zb_multistate_output_cluster_add_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_STATE_TEXT_ID, (void *)state_text); + // if (ret != ESP_OK) { + // log_e("Failed to add state text attribute: 0x%x: %s", ret, esp_err_to_name(ret)); + // return false; + // } + + ret = esp_zb_cluster_list_add_multistate_output_cluster(_cluster_list, multistate_output_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (ret != ESP_OK) { + log_e("Failed to add Multistate Output cluster: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + _multistate_clusters |= MULTISTATE_OUTPUT; + return true; +} + +bool ZigbeeMultistate::setMultistateInputApplication(uint32_t application_type) { + if (!(_multistate_clusters & MULTISTATE_INPUT)) { + log_e("Multistate Input cluster not added"); + return false; + } + + // Add the Multistate Input group ID (0x0D) to the application type + uint32_t application_type_value = (0x0D << 24) | application_type; + + esp_zb_attribute_list_t *multistate_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set Multistate Input application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::setMultistateOutputApplication(uint32_t application_type) { + if (!(_multistate_clusters & MULTISTATE_OUTPUT)) { + log_e("Multistate Output cluster not added"); + return false; + } + + // Add the Multistate Output group ID (0x0E) to the application type + uint32_t application_type_value = (0x0E << 24) | application_type; + + esp_zb_attribute_list_t *multistate_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_APPLICATION_TYPE_ID, (void *)&application_type_value); + if (ret != ESP_OK) { + log_e("Failed to set Multistate Output application type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::setMultistateInputDescription(const char *description) { + if (!(_multistate_clusters & MULTISTATE_INPUT)) { + log_e("Multistate Input cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the multistate input cluster + esp_zb_attribute_list_t *multistate_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_input_cluster == nullptr) { + log_e("Failed to get multistate input cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::setMultistateOutputDescription(const char *description) { + if (!(_multistate_clusters & MULTISTATE_OUTPUT)) { + log_e("Multistate Output cluster not added"); + return false; + } + + // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator) + char zb_description[ZB_MAX_NAME_LENGTH + 2]; + + // Convert description to ZCL string + size_t description_length = strlen(description); + if (description_length > ZB_MAX_NAME_LENGTH) { + log_e("Description is too long"); + return false; + } + + // Get and check the multistate output cluster + esp_zb_attribute_list_t *multistate_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_output_cluster == nullptr) { + log_e("Failed to get multistate output cluster"); + return false; + } + + // Store the length as the first element + zb_description[0] = static_cast(description_length); // Cast size_t to char + // Use memcpy to copy the characters to the result array + memcpy(zb_description + 1, description, description_length); + // Null-terminate the array + zb_description[description_length + 1] = '\0'; + + // Update the description attribute + esp_err_t ret = esp_zb_cluster_update_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_DESCRIPTION_ID, (void *)zb_description); + if (ret != ESP_OK) { + log_e("Failed to set description: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::setMultistateInputStates(uint16_t number_of_states) { + if (!(_multistate_clusters & MULTISTATE_INPUT)) { + log_e("Multistate Input cluster not added"); + return false; + } + + esp_zb_attribute_list_t *multistate_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_input_cluster == nullptr) { + log_e("Failed to get multistate input cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_NUMBER_OF_STATES_ID, (void *)&number_of_states); + if (ret != ESP_OK) { + log_e("Failed to set number of states: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + _input_state_names_length = number_of_states; + return true; +} + +bool ZigbeeMultistate::setMultistateOutputStates(uint16_t number_of_states) { + if (!(_multistate_clusters & MULTISTATE_OUTPUT)) { + log_e("Multistate Output cluster not added"); + return false; + } + + esp_zb_attribute_list_t *multistate_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_output_cluster == nullptr) { + log_e("Failed to get multistate output cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_NUMBER_OF_STATES_ID, (void *)&number_of_states); + if (ret != ESP_OK) { + log_e("Failed to set number of states: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + _output_state_names_length = number_of_states; + return true; +} + +/* TODO: revisit this after arrays are supported + +bool ZigbeeMultistate::setMultistateInputStates(const char * const states[], uint16_t states_length) { + if (!(_multistate_clusters & MULTISTATE_INPUT)) { + log_e("Multistate Input cluster not added"); + return false; + } + + esp_zb_attribute_list_t *multistate_input_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_input_cluster == nullptr) { + log_e("Failed to get multistate input cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_STATE_TEXT_ID, (void *)states); + if (ret != ESP_OK) { + log_e("Failed to set states text: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(multistate_input_cluster, ESP_ZB_ZCL_ATTR_MULTI_INPUT_NUMBER_OF_STATES_ID, (void *)&states_length); + if (ret != ESP_OK) { + log_e("Failed to set number of states: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + // Store state names locally for getter access + _input_state_names = states; + _input_state_names_length = states_length; + return true; +} + +bool ZigbeeMultistate::setMultistateOutputStates(const char * const states[], uint16_t states_length) { + if (!(_multistate_clusters & MULTISTATE_OUTPUT)) { + log_e("Multistate Output cluster not added"); + return false; + } + + esp_zb_attribute_list_t *multistate_output_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + if (multistate_output_cluster == nullptr) { + log_e("Failed to get multistate output cluster"); + return false; + } + + esp_err_t ret = esp_zb_cluster_update_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_STATE_TEXT_ID, (void *)states); + if (ret != ESP_OK) { + log_e("Failed to set states text: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(multistate_output_cluster, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_NUMBER_OF_STATES_ID, (void *)&states_length); + if (ret != ESP_OK) { + log_e("Failed to set number of states: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + + // Store state names locally for getter access + _output_state_names = states; + _output_state_names_length = states_length; + return true; +} +*/ + +//set attribute method -> method overridden in child class +void ZigbeeMultistate::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_PRESENT_VALUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + _output_state = *(uint16_t *)message->attribute.data.value; + multistateOutputChanged(); + } else { + log_w("Received message ignored. Attribute ID: %d not supported for Multistate Output", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Multistate endpoint", message->info.cluster); + } +} + +void ZigbeeMultistate::multistateOutputChanged() { + if (_on_multistate_output_change) { + _on_multistate_output_change(_output_state); + } else { + log_w("No callback function set for multistate output change"); + } +} + +bool ZigbeeMultistate::setMultistateInput(uint16_t state) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + if (!(_multistate_clusters & MULTISTATE_INPUT)) { + log_e("Multistate Input cluster not added"); + return false; + } + log_d("Setting multistate input to %d", state); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_MULTI_INPUT_PRESENT_VALUE_ID, &state, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set multistate input: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::setMultistateOutput(uint16_t state) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + _output_state = state; + multistateOutputChanged(); + + log_v("Updating multistate output to %d", state); + /* Update multistate output */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_PRESENT_VALUE_ID, &_output_state, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set multistate output: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeMultistate::reportMultistateInput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_MULTI_INPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_MULTI_INPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Multistate Input report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Multistate Input report sent"); + return true; +} + +bool ZigbeeMultistate::reportMultistateOutput() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_MULTI_OUTPUT_PRESENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_MULTI_OUTPUT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send Multistate Output report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Multistate Output report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeMultistate.h b/libraries/Zigbee/src/ep/ZigbeeMultistate.h new file mode 100644 index 0000000..e4eb0be --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeMultistate.h @@ -0,0 +1,188 @@ +/* Class of Zigbee Multistate sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// Types for Multistate Input/Output +// uint16_t for present value -> index to array of states +// uint16_t for number of states +// uint8_t chars for state names, with max of 16 chars ASCII + +// Multistate Input/Output Application Types Defines +#define ZB_MULTISTATE_APPLICATION_TYPE_0_INDEX 0x0000 +#define ZB_MULTISTATE_APPLICATION_TYPE_0_NUM_STATES 3 +#define ZB_MULTISTATE_APPLICATION_TYPE_0_STATE_NAMES \ + (const char *const[]) { \ + "Off", "On", "Auto" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_1_INDEX 0x0001 +#define ZB_MULTISTATE_APPLICATION_TYPE_1_NUM_STATES 4 +#define ZB_MULTISTATE_APPLICATION_TYPE_1_STATE_NAMES \ + (const char *const[]) { \ + "Off", "Low", "Medium", "High" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_2_INDEX 0x0002 +#define ZB_MULTISTATE_APPLICATION_TYPE_2_NUM_STATES 7 +#define ZB_MULTISTATE_APPLICATION_TYPE_2_STATE_NAMES \ + (const char *const[]) { \ + "Auto", "Heat", "Cool", "Off", "Emergency Heat", "Fan Only", "Max Heat" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_3_INDEX 0x0003 +#define ZB_MULTISTATE_APPLICATION_TYPE_3_NUM_STATES 4 +#define ZB_MULTISTATE_APPLICATION_TYPE_3_STATE_NAMES \ + (const char *const[]) { \ + "Occupied", "Unoccupied", "Standby", "Bypass" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_4_INDEX 0x0004 +#define ZB_MULTISTATE_APPLICATION_TYPE_4_NUM_STATES 3 +#define ZB_MULTISTATE_APPLICATION_TYPE_4_STATE_NAMES \ + (const char *const[]) { \ + "Inactive", "Active", "Hold" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_5_INDEX 0x0005 +#define ZB_MULTISTATE_APPLICATION_TYPE_5_NUM_STATES 8 +#define ZB_MULTISTATE_APPLICATION_TYPE_5_STATE_NAMES \ + (const char *const[]) { \ + "Auto", "Warm-up", "Water Flush", "Autocalibration", "Shutdown Open", "Shutdown Closed", "Low Limit", "Test and Balance" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_6_INDEX 0x0006 +#define ZB_MULTISTATE_APPLICATION_TYPE_6_NUM_STATES 6 +#define ZB_MULTISTATE_APPLICATION_TYPE_6_STATE_NAMES \ + (const char *const[]) { \ + "Off", "Auto", "Heat Cool", "Heat Only", "Cool Only", "Fan Only" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_7_INDEX 0x0007 +#define ZB_MULTISTATE_APPLICATION_TYPE_7_NUM_STATES 3 +#define ZB_MULTISTATE_APPLICATION_TYPE_7_STATE_NAMES \ + (const char *const[]) { \ + "High", "Normal", "Low" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_8_INDEX 0x0008 +#define ZB_MULTISTATE_APPLICATION_TYPE_8_NUM_STATES 4 +#define ZB_MULTISTATE_APPLICATION_TYPE_8_STATE_NAMES \ + (const char *const[]) { \ + "Occupied", "Unoccupied", "Startup", "Shutdown" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_9_INDEX 0x0009 +#define ZB_MULTISTATE_APPLICATION_TYPE_9_NUM_STATES 3 +#define ZB_MULTISTATE_APPLICATION_TYPE_9_STATE_NAMES \ + (const char *const[]) { \ + "Night", "Day", "Hold" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_10_INDEX 0x000A +#define ZB_MULTISTATE_APPLICATION_TYPE_10_NUM_STATES 5 +#define ZB_MULTISTATE_APPLICATION_TYPE_10_STATE_NAMES \ + (const char *const[]) { \ + "Off", "Cool", "Heat", "Auto", "Emergency Heat" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_11_INDEX 0x000B +#define ZB_MULTISTATE_APPLICATION_TYPE_11_NUM_STATES 7 +#define ZB_MULTISTATE_APPLICATION_TYPE_11_STATE_NAMES \ + (const char *const[]) { \ + "Shutdown Closed", "Shutdown Open", "Satisfied", "Mixing", "Cooling", "Heating", "Suppl Heat" \ + } + +#define ZB_MULTISTATE_APPLICATION_TYPE_OTHER_INDEX 0xFFFF + +//enum for bits set to check what multistate cluster were added +enum zigbee_multistate_clusters { + MULTISTATE_INPUT = 1, + MULTISTATE_OUTPUT = 2 +}; + +typedef struct zigbee_multistate_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; +} zigbee_multistate_cfg_t; + +class ZigbeeMultistate : public ZigbeeEP { +public: + ZigbeeMultistate(uint8_t endpoint); + ~ZigbeeMultistate() {} + + // Add multistate clusters + bool addMultistateInput(); + bool addMultistateOutput(); + + // Set the application type and description for the multistate input + bool setMultistateInputApplication(uint32_t application_type); // Check esp_zigbee_zcl_multistate_input.h for application type values + bool setMultistateInputDescription(const char *description); + bool setMultistateInputStates(uint16_t number_of_states); + // bool setMultistateInputStates(const char * const states[], uint16_t states_length); + + // Set the application type and description for the multistate output + bool setMultistateOutputApplication(uint32_t application_type); // Check esp_zigbee_zcl_multistate_output.h for application type values + bool setMultistateOutputDescription(const char *description); + bool setMultistateOutputStates(uint16_t number_of_states); + // bool setMultistateOutputStates(const char * const states[], uint16_t states_length); + + // Use to set a cb function to be called on multistate output change + void onMultistateOutputChange(void (*callback)(uint16_t state)) { + _on_multistate_output_change = callback; + } + + // Set the Multistate Input/Output value + bool setMultistateInput(uint16_t state); + bool setMultistateOutput(uint16_t state); + + // Get the Multistate Input/Output values + uint16_t getMultistateInput() { + return _input_state; + } + uint16_t getMultistateOutput() { + return _output_state; + } + + // Get state names and length + uint16_t getMultistateInputStateNamesLength() { + return _input_state_names_length; + } + uint16_t getMultistateOutputStateNamesLength() { + return _output_state_names_length; + } + // const char* const* getMultistateInputStateNames() { + // return _input_state_names; + // } + // const char* const* getMultistateOutputStateNames() { + // return _output_state_names; + // } + + // Report Multistate Input/Output + bool reportMultistateInput(); + bool reportMultistateOutput(); + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + + void (*_on_multistate_output_change)(uint16_t state); + void multistateOutputChanged(); + + uint8_t _multistate_clusters; + uint16_t _output_state; + uint16_t _input_state; + + // Local storage for state names + uint16_t _input_state_names_length; + uint16_t _output_state_names_length; + // const char* const* _input_state_names; + // const char* const* _output_state_names; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp new file mode 100644 index 0000000..eb85b12 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp @@ -0,0 +1,95 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeOccupancySensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_occupancy_sensor_clusters_create(zigbee_occupancy_sensor_cfg_t *occupancy_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = occupancy_sensor ? &(occupancy_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = occupancy_sensor ? &(occupancy_sensor->identify_cfg) : NULL; + esp_zb_occupancy_sensing_cluster_cfg_t *occupancy_meas_cfg = occupancy_sensor ? &(occupancy_sensor->occupancy_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_occupancy_sensing_cluster(cluster_list, esp_zb_occupancy_sensing_cluster_create(occupancy_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeeOccupancySensor::ZigbeeOccupancySensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom occupancy sensor configuration + zigbee_occupancy_sensor_cfg_t occupancy_sensor_cfg = ZIGBEE_DEFAULT_OCCUPANCY_SENSOR_CONFIG(); + _cluster_list = zigbee_occupancy_sensor_clusters_create(&occupancy_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeeOccupancySensor::setSensorType(uint8_t sensor_type) { + uint8_t sensor_type_bitmap = 1 << sensor_type; + esp_zb_attribute_list_t *occupancy_sens_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(occupancy_sens_cluster, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_ID, (void *)&sensor_type); + if (ret != ESP_OK) { + log_e("Failed to set sensor type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(occupancy_sens_cluster, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_BITMAP_ID, (void *)&sensor_type_bitmap); + if (ret != ESP_OK) { + log_e("Failed to set sensor type bitmap: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeOccupancySensor::setOccupancy(bool occupied) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Updating occupancy sensor value..."); + /* Update occupancy sensor value */ + log_d("Setting occupancy to %d", occupied); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_ID, &occupied, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set occupancy: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeOccupancySensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send occupancy report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Occupancy report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h new file mode 100644 index 0000000..9f1b190 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h @@ -0,0 +1,68 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_OCCUPANCY_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .occupancy_meas_cfg = \ + { \ + .occupancy = ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_UNOCCUPIED, \ + .sensor_type = ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_PIR, \ + .sensor_type_bitmap = (1 << ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_PIR), \ + }, \ + } +// clang-format on + +typedef struct zigbee_occupancy_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_occupancy_sensing_cluster_cfg_t occupancy_meas_cfg; +} zigbee_occupancy_sensor_cfg_t; + +class ZigbeeOccupancySensor : public ZigbeeEP { +public: + ZigbeeOccupancySensor(uint8_t endpoint); + ~ZigbeeOccupancySensor() {} + + // Set the occupancy value. True for occupied, false for unoccupied + bool setOccupancy(bool occupied); + + // Set the sensor type, see esp_zb_zcl_occupancy_sensing_occupancy_sensor_type_t + bool setSensorType(uint8_t sensor_type); + + // Report the occupancy value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp new file mode 100644 index 0000000..6a3b68f --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp @@ -0,0 +1,144 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeePM25Sensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_pm2_5_sensor_clusters_create(zigbee_pm2_5_sensor_cfg_t *pm2_5_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = pm2_5_sensor ? &(pm2_5_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = pm2_5_sensor ? &(pm2_5_sensor->identify_cfg) : NULL; + esp_zb_pm2_5_measurement_cluster_cfg_t *pm2_5_meas_cfg = pm2_5_sensor ? &(pm2_5_sensor->pm2_5_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_pm2_5_measurement_cluster(cluster_list, esp_zb_pm2_5_measurement_cluster_create(pm2_5_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeePM25Sensor::ZigbeePM25Sensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom PM2.5 sensor configuration + zigbee_pm2_5_sensor_cfg_t pm2_5_sensor_cfg = ZIGBEE_DEFAULT_PM2_5_SENSOR_CONFIG(); + _cluster_list = zigbee_pm2_5_sensor_clusters_create(&pm2_5_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeePM25Sensor::setDefaultValue(float defaultValue) { + esp_zb_attribute_list_t *pm2_5_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID, (void *)&defaultValue); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePM25Sensor::setMinMaxValue(float min, float max) { + esp_zb_attribute_list_t *pm2_5_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePM25Sensor::setTolerance(float tolerance) { + esp_zb_attribute_list_t *pm2_5_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_pm2_5_measurement_cluster_add_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePM25Sensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + // reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100); // Convert delta to ZCL uint16_t + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + float delta_f = delta; + memcpy(&reporting_info.u.send_info.delta.s32, &delta_f, sizeof(float)); + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePM25Sensor::setPM25(float pm25) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Updating PM2.5 sensor value..."); + /* Update PM2.5 sensor measured value */ + log_d("Setting PM2.5 to %0.1f", pm25); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID, &pm25, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set PM2.5: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePM25Sensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send PM2.5 report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("PM2.5 report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h new file mode 100644 index 0000000..967ccdc --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h @@ -0,0 +1,78 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee PM2.5 sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_PM2_5_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .pm2_5_meas_cfg = \ + { \ + .measured_value = 0.0, \ + .min_measured_value = 0.0, \ + .max_measured_value = 500.0, \ + }, \ + } +// clang-format on + +typedef struct zigbee_pm2_5_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_pm2_5_measurement_cluster_cfg_t pm2_5_meas_cfg; +} zigbee_pm2_5_sensor_cfg_t; + +class ZigbeePM25Sensor : public ZigbeeEP { +public: + ZigbeePM25Sensor(uint8_t endpoint); + ~ZigbeePM25Sensor() {} + + // Set the PM2.5 value in 0.1 µg/m³ + bool setPM25(float pm25); + + // Set the default (initial) value for the PM2.5 sensor in 0.1 µg/m³ + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(float defaultValue); + + // Set the min and max value for the PM2.5 sensor in 0.1 µg/m³ + bool setMinMaxValue(float min, float max); + + // Set the tolerance value for the PM2.5 sensor in 0.1 µg/m³ + bool setTolerance(float tolerance); + + // Set the reporting interval for PM2.5 measurement in seconds and delta (PM2.5 change in 0.1 µg/m³) + bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta); + + // Report the PM2.5 value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePowerOutlet.cpp b/libraries/Zigbee/src/ep/ZigbeePowerOutlet.cpp new file mode 100644 index 0000000..250bd65 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePowerOutlet.cpp @@ -0,0 +1,73 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeePowerOutlet.h" +#if CONFIG_ZB_ENABLED + +ZigbeePowerOutlet::ZigbeePowerOutlet(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_MAINS_POWER_OUTLET_DEVICE_ID; + _on_state_change = nullptr; + + esp_zb_mains_power_outlet_cfg_t outlet_cfg = ESP_ZB_DEFAULT_MAINS_POWER_OUTLET_CONFIG(); + _cluster_list = esp_zb_mains_power_outlet_clusters_create(&outlet_cfg); + _ep_config = { + .endpoint = endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_MAINS_POWER_OUTLET_DEVICE_ID, .app_device_version = 0 + }; + log_v("Outlet endpoint created %d", _endpoint); +} + +//set attribute method -> method overridden in child class +void ZigbeePowerOutlet::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + //check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + _current_state = *(bool *)message->attribute.data.value; + stateChanged(); + } else { + log_w("Received message ignored. Attribute ID: %d not supported for On/Off Outlet", message->attribute.id); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for On/Off Outlet", message->info.cluster); + } +} + +void ZigbeePowerOutlet::stateChanged() { + if (_on_state_change) { + _on_state_change(_current_state); + } else { + log_w("No callback function set for outlet change"); + } +} + +bool ZigbeePowerOutlet::setState(bool state) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + _current_state = state; + stateChanged(); + + log_v("Updating on/off outlet state to %d", state); + /* Update on/off outlet state */ + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false + ); + esp_zb_lock_release(); + + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set outlet state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePowerOutlet.h b/libraries/Zigbee/src/ep/ZigbeePowerOutlet.h new file mode 100644 index 0000000..231f7b6 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePowerOutlet.h @@ -0,0 +1,55 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Power outlet endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeePowerOutlet : public ZigbeeEP { +public: + ZigbeePowerOutlet(uint8_t endpoint); + ~ZigbeePowerOutlet() {} + + // Use to set a cb function to be called on outlet change + void onPowerOutletChange(void (*callback)(bool)) { + _on_state_change = callback; + } + // Use to restore outlet state + void restoreState() { + stateChanged(); + } + // Use to control outlet state + bool setState(bool state); + // Use to get outlet state + bool getPowerOutletState() { + return _current_state; + } + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + //callback function to be called on outlet change + void (*_on_state_change)(bool); + void stateChanged(); + + bool _current_state; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp b/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp new file mode 100644 index 0000000..0af331b --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp @@ -0,0 +1,140 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeePressureSensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_pressure_sensor_clusters_create(zigbee_pressure_sensor_cfg_t *pressure_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = pressure_sensor ? &(pressure_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = pressure_sensor ? &(pressure_sensor->identify_cfg) : NULL; + esp_zb_pressure_meas_cluster_cfg_t *pressure_meas_cfg = pressure_sensor ? &(pressure_sensor->pressure_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_pressure_meas_cluster(cluster_list, esp_zb_pressure_meas_cluster_create(pressure_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeePressureSensor::ZigbeePressureSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + //Create custom pressure sensor configuration + zigbee_pressure_sensor_cfg_t presssure_sensor_cfg = ZIGBEE_DEFAULT_PRESSURE_SENSOR_CONFIG(); + _cluster_list = zigbee_pressure_sensor_clusters_create(&presssure_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +bool ZigbeePressureSensor::setDefaultValue(int16_t defaultValue) { + esp_zb_attribute_list_t *pressure_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID, (void *)&defaultValue); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePressureSensor::setMinMaxValue(int16_t min, int16_t max) { + esp_zb_attribute_list_t *pressure_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MIN_VALUE_ID, (void *)&min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MAX_VALUE_ID, (void *)&max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePressureSensor::setTolerance(uint16_t tolerance) { + esp_zb_attribute_list_t *pressure_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_pressure_meas_cluster_add_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + } + return ret == ESP_OK; +} + +bool ZigbeePressureSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = delta; // x hPa + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePressureSensor::setPressure(int16_t pressure) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Updating pressure sensor value..."); + /* Update pressure sensor measured value */ + log_d("Setting pressure to %d hPa", pressure); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID, &pressure, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set pressure: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeePressureSensor::report() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send pressure report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Pressure report sent"); + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeePressureSensor.h b/libraries/Zigbee/src/ep/ZigbeePressureSensor.h new file mode 100644 index 0000000..930846c --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeePressureSensor.h @@ -0,0 +1,78 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_PRESSURE_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .pressure_meas_cfg = \ + { \ + .measured_value = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_DEFAULT_VALUE, \ + .min_value = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MIN_VALUE_DEFAULT_VALUE, \ + .max_value = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MAX_VALUE_DEFAULT_VALUE, \ + }, \ + } +// clang-format on + +typedef struct zigbee_pressure_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_pressure_meas_cluster_cfg_t pressure_meas_cfg; +} zigbee_pressure_sensor_cfg_t; + +class ZigbeePressureSensor : public ZigbeeEP { +public: + ZigbeePressureSensor(uint8_t endpoint); + ~ZigbeePressureSensor() {} + + // Set the pressure value in 1 hPa + bool setPressure(int16_t value); + + // Set the default (initial) value for the pressure sensor in 1 hPa + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(int16_t defaultValue); + + // Set the min and max value for the pressure sensor in 1 hPa + bool setMinMaxValue(int16_t min, int16_t max); + + // Set the tolerance value for the pressure sensor in 1 hPa + bool setTolerance(uint16_t tolerance); + + // Set the reporting interval for pressure measurement in seconds and delta (pressure change in 1 hPa) + bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta); + + // Report the pressure value + bool report(); +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp new file mode 100644 index 0000000..b12cde2 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp @@ -0,0 +1,29 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeRangeExtender.h" +#if CONFIG_ZB_ENABLED + +ZigbeeRangeExtender::ZigbeeRangeExtender(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID; + + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID, .app_device_version = 0}; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h new file mode 100644 index 0000000..8d4c156 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h @@ -0,0 +1,32 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Range Extender endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeeRangeExtender : public ZigbeeEP { +public: + ZigbeeRangeExtender(uint8_t endpoint); + ~ZigbeeRangeExtender() {} +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp new file mode 100644 index 0000000..2660dd7 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp @@ -0,0 +1,460 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeSwitch.h" +#if CONFIG_ZB_ENABLED + +// Initialize the static instance pointer +ZigbeeSwitch *ZigbeeSwitch::_instance = nullptr; + +ZigbeeSwitch::ZigbeeSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID; + _instance = this; // Set the static pointer to this instance + _device = nullptr; + _on_light_state_change = nullptr; + _on_light_state_change_with_source = nullptr; + + esp_zb_on_off_switch_cfg_t switch_cfg = ESP_ZB_DEFAULT_ON_OFF_SWITCH_CONFIG(); + _cluster_list = esp_zb_on_off_switch_clusters_create(&switch_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID, .app_device_version = 0}; +} + +void ZigbeeSwitch::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeSwitch *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_i("Bound successfully!"); + if (instance->_device) { + zb_device_params_t *light = (zb_device_params_t *)instance->_device; + log_i("The light originating from address(0x%x) on endpoint(%d)", light->short_addr, light->endpoint); + log_d("Light bound to a switch on EP %d", instance->_endpoint); + instance->_bound_devices.push_back(light); + } + instance->_is_bound = true; + } else { + instance->_device = nullptr; + } +} + +void ZigbeeSwitch::bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeSwitch *instance = static_cast(user_ctx); + if (instance) { + log_d("bindCbWrapper on EP %d", instance->_endpoint); + instance->bindCb(zdo_status, user_ctx); + } +} + +// Static wrapper for findCb +void ZigbeeSwitch::findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeSwitch *instance = static_cast(user_ctx); + if (instance) { + log_d("findCbWrapper on EP %d", instance->_endpoint); + instance->findCb(zdo_status, addr, endpoint, user_ctx); + } +} + +void ZigbeeSwitch::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeSwitch *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_d("Found light endpoint"); + esp_zb_zdo_bind_req_param_t bind_req; + memset(&bind_req, 0, sizeof(bind_req)); + zb_device_params_t *light = (zb_device_params_t *)malloc(sizeof(zb_device_params_t)); + light->endpoint = endpoint; + light->short_addr = addr; + esp_zb_ieee_address_by_short(light->short_addr, light->ieee_addr); + log_d("Light found: short address(0x%x), endpoint(%d)", light->short_addr, light->endpoint); + + esp_zb_get_long_address(bind_req.src_address); + bind_req.src_endp = instance->_endpoint; + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED; + memcpy(bind_req.dst_address_u.addr_long, light->ieee_addr, sizeof(esp_zb_ieee_addr_t)); + bind_req.dst_endp = endpoint; + bind_req.req_dst_addr = esp_zb_get_short_address(); + log_v("Try to bind On/Off"); + //save light params in the class + instance->_device = light; + + log_d("Find callback on EP %d", instance->_endpoint); + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeSwitch::bindCbWrapper, this); + } else { + log_d("No light endpoint found"); + } +} + +// find on_off light endpoint +void ZigbeeSwitch::findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) { + uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF}; + esp_zb_zdo_match_desc_req_param_t on_off_req = { + .dst_nwk_addr = cmd_req->dst_nwk_addr, + .addr_of_interest = cmd_req->addr_of_interest, + .profile_id = ESP_ZB_AF_HA_PROFILE_ID, + .num_in_clusters = 1, + .num_out_clusters = 1, + .cluster_list = cluster_list, + }; + esp_zb_zdo_match_cluster(&on_off_req, ZigbeeSwitch::findCbWrapper, this); +} + +// Methods to control the light +void ZigbeeSwitch::lightToggle() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightToggle(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightToggle(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + log_v("Sending 'light toggle' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light toggle' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOn() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOn(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOn(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + log_v("Sending 'light on' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light on' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOff() { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOff(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOff(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + log_v("Sending 'light off' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_on_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.zcl_basic_cmd.dst_endpoint = endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID; + memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + log_v( + "Sending 'light off' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant) { + if (_is_bound) { + esp_zb_zcl_on_off_off_with_effect_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.effect_id = effect_id; + cmd_req.effect_variant = effect_variant; + log_v("Sending 'light off with effect' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_off_with_effect_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOnWithSceneRecall() { + if (_is_bound) { + esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + log_v("Sending 'light on with scene recall' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off) { + if (_is_bound) { + esp_zb_zcl_on_off_on_with_timed_off_cmd_t cmd_req; + memset(&cmd_req, 0, sizeof(cmd_req)); + cmd_req.zcl_basic_cmd.src_endpoint = _endpoint; + cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + cmd_req.on_off_control = on_off_control; //TODO: Test how it works, then maybe change API + cmd_req.on_time = time_on; + cmd_req.off_wait_time = time_off; + log_v("Sending 'light on with time off' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_on_off_on_with_timed_off_cmd_req(&cmd_req); + esp_zb_lock_release(); + } else { + log_e("Light not bound"); + } +} + +void ZigbeeSwitch::getLightState() { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeSwitch::getLightState(uint16_t group_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeSwitch::getLightState(uint8_t endpoint, uint16_t short_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeSwitch::getLightState(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + if (_is_bound) { + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF; + read_req.attr_number = 1; + uint16_t attr_id = ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID; + read_req.attr_field = &attr_id; + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + } +} + +void ZigbeeSwitch::zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) { + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) { + if (attribute->id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) { + bool light_state = attribute->data.value ? *(bool *)attribute->data.value : false; + if (_on_light_state_change) { + _on_light_state_change(light_state); + } + if (_on_light_state_change_with_source) { + _on_light_state_change_with_source(light_state, src_endpoint, src_address); + } + } + } +} +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeSwitch.h b/libraries/Zigbee/src/ep/ZigbeeSwitch.h new file mode 100644 index 0000000..09c1735 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeSwitch.h @@ -0,0 +1,79 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee On/Off Switch endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeeSwitch : public ZigbeeEP { +public: + ZigbeeSwitch(uint8_t endpoint); + ~ZigbeeSwitch() {} + + // methods to control the on/off light + void lightToggle(); + void lightToggle(uint16_t group_addr); + void lightToggle(uint8_t endpoint, uint16_t short_addr); + void lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOn(); + void lightOn(uint16_t group_addr); + void lightOn(uint8_t endpoint, uint16_t short_addr); + void lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOff(); + void lightOff(uint16_t group_addr); + void lightOff(uint8_t endpoint, uint16_t short_addr); + void lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant); + void lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off); + void lightOnWithSceneRecall(); + + void getLightState(); + void getLightState(uint16_t group_addr); + void getLightState(uint8_t endpoint, uint16_t short_addr); + void getLightState(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void onLightStateChange(void (*callback)(bool)) { + _on_light_state_change = callback; + } + void onLightStateChangeWithSource(void (*callback)(bool, uint8_t, esp_zb_zcl_addr_t)) { + _on_light_state_change_with_source = callback; + } + +private: + // save instance of the class in order to use it in static functions + static ZigbeeSwitch *_instance; + zb_device_params_t *_device; + + void (*_on_light_state_change)(bool); + void (*_on_light_state_change_with_source)(bool, uint8_t, esp_zb_zcl_addr_t); + + void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req); + void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx); + void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + static void findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + static void bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx); + void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) override; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp new file mode 100644 index 0000000..4f1e9c8 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp @@ -0,0 +1,234 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeTempSensor.h" +#if CONFIG_ZB_ENABLED + +ZigbeeTempSensor::ZigbeeTempSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID; + _humidity_sensor = false; + + esp_zb_temperature_sensor_cfg_t temp_sensor_cfg = ESP_ZB_DEFAULT_TEMPERATURE_SENSOR_CONFIG(); + _cluster_list = esp_zb_temperature_sensor_clusters_create(&temp_sensor_cfg); + + // Set default (initial) value for the temperature sensor to 0.0°C + setDefaultValue(0.0); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID, .app_device_version = 0 + }; +} + +static int16_t zb_float_to_s16(float temp) { + return (int16_t)(temp * 100); +} + +bool ZigbeeTempSensor::setMinMaxValue(float min, float max) { + int16_t zb_min = zb_float_to_s16(min); + int16_t zb_max = zb_float_to_s16(max); + esp_zb_attribute_list_t *temp_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, (void *)&zb_min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, (void *)&zb_max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::setDefaultValue(float defaultValue) { + int16_t zb_default_value = zb_float_to_s16(defaultValue); + esp_zb_attribute_list_t *temp_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, (void *)&zb_default_value); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::setTolerance(float tolerance) { + // Convert tolerance to ZCL uint16_t + uint16_t zb_tolerance = (uint16_t)(tolerance * 100); + esp_zb_attribute_list_t *temp_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_temperature_meas_cluster_add_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100); // Convert delta to ZCL uint16_t + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::setTemperature(float temperature) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + int16_t zb_temperature = zb_float_to_s16(temperature); + log_v("Updating temperature sensor value..."); + /* Update temperature sensor measured value */ + log_d("Setting temperature to %d", zb_temperature); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, &zb_temperature, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set temperature: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::reportTemperature() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; //Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; //Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send temperature report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Temperature report sent"); + return true; +} + +void ZigbeeTempSensor::addHumiditySensor(float min, float max, float tolerance, float defaultValue) { + uint16_t zb_min = (uint16_t)(min * 100); + uint16_t zb_max = (uint16_t)(max * 100); + uint16_t zb_tolerance = (uint16_t)(tolerance * 100); + uint16_t default_hum = (uint16_t)(defaultValue * 100); + esp_zb_attribute_list_t *humidity_cluster = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT); + esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, &default_hum); + esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, &zb_min); + esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, &zb_max); + esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID, &zb_tolerance); + esp_zb_cluster_list_add_humidity_meas_cluster(_cluster_list, humidity_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + _humidity_sensor = true; +} + +bool ZigbeeTempSensor::setHumidity(float humidity) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + uint16_t zb_humidity = (uint16_t)(humidity * 100); + log_v("Updating humidity sensor value..."); + /* Update humidity sensor measured value */ + log_d("Setting humidity to %d", zb_humidity); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, &zb_humidity, + false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set humidity: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::reportHumidity() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send humidity report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Humidity report sent"); + return true; +} + +bool ZigbeeTempSensor::setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100); // Convert delta to ZCL uint16_t + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set humidity reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeTempSensor::report() { + bool temp_ret = reportTemperature(); + bool hum_ret = true; + if (_humidity_sensor) { + hum_ret = reportHumidity(); + } + return temp_ret && hum_ret; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeTempSensor.h b/libraries/Zigbee/src/ep/ZigbeeTempSensor.h new file mode 100644 index 0000000..edc8812 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeTempSensor.h @@ -0,0 +1,69 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Temperature + Humidity sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +class ZigbeeTempSensor : public ZigbeeEP { +public: + ZigbeeTempSensor(uint8_t endpoint); + ~ZigbeeTempSensor() {} + + // Set the temperature value in 0,01°C + bool setTemperature(float value); + + // Set the default (initial) value for the temperature sensor in 0,01°C + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(float defaultValue); + + // Set the min and max value for the temperature sensor in 0,01°C + bool setMinMaxValue(float min, float max); + + // Set the tolerance value for the temperature sensor in 0,01°C + bool setTolerance(float tolerance); + + // Set the reporting interval for temperature measurement in seconds and delta (temp change in 0,01 °C) + bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta); + + // Report the temperature value + bool reportTemperature(); + + // Add humidity cluster to the temperature sensor device + void addHumiditySensor(float min = 0.0, float max = 100.0, float tolerance = 0.1, float defaultValue = 0.0); + + // Set the humidity value in 0,01% + bool setHumidity(float value); + + // Set the reporting interval for humidity measurement in seconds and delta (humidity change in 0,01%) + bool setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta); + + // Report the humidity value + bool reportHumidity(); + + // Report the temperature and humidity values if humidity sensor is added + bool report(); + +private: + bool _humidity_sensor; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp b/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp new file mode 100644 index 0000000..bf69ce8 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp @@ -0,0 +1,871 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeThermostat.h" +#if CONFIG_ZB_ENABLED + +static float zb_s16_to_temperature(int16_t value) { + return 1.0 * value / 100; +} + +// Initialize the static instance of the class +ZigbeeThermostat *ZigbeeThermostat::_instance = nullptr; + +ZigbeeThermostat::ZigbeeThermostat(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_THERMOSTAT_DEVICE_ID; + _instance = this; // Set the static pointer to this instance + _device = nullptr; // Initialize sensor pointer to null + _on_temp_receive = nullptr; + _on_temp_receive_with_source = nullptr; + _on_temp_config_receive = nullptr; + _on_humidity_receive = nullptr; + _on_humidity_receive_with_source = nullptr; + _on_humidity_config_receive = nullptr; + + //use custom config to avoid narrowing error -> must be fixed in zigbee-sdk + esp_zb_thermostat_cfg_t thermostat_cfg = ZB_DEFAULT_THERMOSTAT_CONFIG(); + + //use custom cluster creating to accept reportings from temperature sensor + _cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_attribute_list_t *basic_cluster = esp_zb_basic_cluster_create(&(thermostat_cfg.basic_cfg)); + esp_zb_cluster_list_add_basic_cluster(_cluster_list, basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(&(thermostat_cfg.identify_cfg)), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + esp_zb_cluster_list_add_thermostat_cluster(_cluster_list, esp_zb_thermostat_cluster_create(&(thermostat_cfg.thermostat_cfg)), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + /* Add temperature measurement cluster for attribute reporting */ + esp_zb_cluster_list_add_temperature_meas_cluster(_cluster_list, esp_zb_temperature_meas_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + esp_zb_cluster_list_add_humidity_meas_cluster(_cluster_list, esp_zb_humidity_meas_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_THERMOSTAT_DEVICE_ID, .app_device_version = 0}; +} + +void ZigbeeThermostat::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeThermostat *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_i("Bound successfully!"); + if (instance->_device) { + zb_device_params_t *sensor = (zb_device_params_t *)instance->_device; + log_i("The sensor originating from address(0x%x) on endpoint(%d)", sensor->short_addr, sensor->endpoint); + log_d("Sensor bound to thermostat on EP %d", instance->_endpoint); + instance->_bound_devices.push_back(sensor); + } + instance->_is_bound = true; + } else { + instance->_device = nullptr; + } +} + +void ZigbeeThermostat::bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx) { + ZigbeeThermostat *instance = static_cast(user_ctx); + if (instance) { + log_d("bindCbWrapper on EP %d", instance->_endpoint); + instance->bindCb(zdo_status, user_ctx); + } +} + +void ZigbeeThermostat::findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeThermostat *instance = static_cast(user_ctx); + if (instance) { + log_d("findCbWrapper on EP %d", instance->_endpoint); + instance->findCb(zdo_status, addr, endpoint, user_ctx); + } +} + +void ZigbeeThermostat::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) { + ZigbeeThermostat *instance = static_cast(user_ctx); + if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) { + log_i("Found temperature sensor"); + esp_zb_zdo_bind_req_param_t bind_req; + memset(&bind_req, 0, sizeof(bind_req)); + /* Store the information of the remote device */ + zb_device_params_t *sensor = (zb_device_params_t *)malloc(sizeof(zb_device_params_t)); + sensor->endpoint = endpoint; + sensor->short_addr = addr; + esp_zb_ieee_address_by_short(sensor->short_addr, sensor->ieee_addr); + log_d("Temperature sensor found: short address(0x%x), endpoint(%d)", sensor->short_addr, sensor->endpoint); + + /* 1. Send binding request to the sensor */ + bind_req.req_dst_addr = addr; + memcpy(bind_req.src_address, sensor->ieee_addr, sizeof(esp_zb_ieee_addr_t)); + bind_req.src_endp = endpoint; + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED; + esp_zb_get_long_address(bind_req.dst_address_u.addr_long); + bind_req.dst_endp = instance->_endpoint; + + log_i("Request temperature sensor to bind us"); + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeThermostat::bindCbWrapper, NULL); + + log_i("Request humidity sensor to bind us"); + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeThermostat::bindCbWrapper, NULL); + + /* 2. Send binding request to self */ + bind_req.req_dst_addr = esp_zb_get_short_address(); + + /* populate the src information of the binding */ + esp_zb_get_long_address(bind_req.src_address); + bind_req.src_endp = instance->_endpoint; + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED; + memcpy(bind_req.dst_address_u.addr_long, sensor->ieee_addr, sizeof(esp_zb_ieee_addr_t)); + bind_req.dst_endp = endpoint; + log_i("Try to bind Humidity Measurement"); // Optional cluster to bind, if fails, continue to bind the temperature measurement cluster + // save sensor params in the class + instance->_device = sensor; + + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeThermostat::bindCbWrapper, NULL); + bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + log_i("Try to bind Temperature Measurement"); // Mandatory cluster to bind + esp_zb_zdo_device_bind_req(&bind_req, ZigbeeThermostat::bindCbWrapper, this); + } else { + log_d("No temperature sensor endpoint found"); + } +} + +void ZigbeeThermostat::findEndpoint(esp_zb_zdo_match_desc_req_param_t *param) { + uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT}; + param->profile_id = ESP_ZB_AF_HA_PROFILE_ID; + param->num_in_clusters = 2; + param->num_out_clusters = 0; + param->cluster_list = cluster_list; + esp_zb_zdo_match_cluster(param, ZigbeeThermostat::findCbWrapper, this); +} + +void ZigbeeThermostat::zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) { + static uint8_t read_config = 0; + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT) { + if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) { + int16_t value = attribute->data.value ? *(int16_t *)attribute->data.value : 0; + if (_on_temp_receive) { + _on_temp_receive(zb_s16_to_temperature(value)); + } + if (_on_temp_receive_with_source) { + _on_temp_receive_with_source(zb_s16_to_temperature(value), src_endpoint, src_address); + } + } + if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) { + int16_t min_value = attribute->data.value ? *(int16_t *)attribute->data.value : 0; + _min_temp = zb_s16_to_temperature(min_value); + read_config++; + log_d("Received min temperature: %.2f°C from endpoint %d", _min_temp, src_endpoint); + } + if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) { + int16_t max_value = attribute->data.value ? *(int16_t *)attribute->data.value : 0; + _max_temp = zb_s16_to_temperature(max_value); + read_config++; + log_d("Received max temperature: %.2f°C from endpoint %d", _max_temp, src_endpoint); + } + if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + uint16_t tolerance = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + _tolerance_temp = 1.0 * tolerance / 100; + read_config++; + log_d("Received tolerance: %.2f°C from endpoint %d", _tolerance_temp, src_endpoint); + } + if (read_config == 3) { + log_d("All temperature config attributes processed"); + read_config = 0; + xSemaphoreGive(lock); + } + } + static uint8_t read_humidity_config = 0; + if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT) { + if (attribute->id == ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + uint16_t value = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + float humidity = 1.0 * value / 100; + if (_on_humidity_receive) { + _on_humidity_receive(humidity); + } + if (_on_humidity_receive_with_source) { + _on_humidity_receive_with_source(humidity, src_endpoint, src_address); + } + } + if (attribute->id == ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + uint16_t min_value = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + _min_humidity = 1.0 * min_value / 100; + read_humidity_config++; + log_d("Received min humidity: %.2f%% from endpoint %d", _min_humidity, src_endpoint); + } + if (attribute->id == ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + uint16_t max_value = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + _max_humidity = 1.0 * max_value / 100; + read_humidity_config++; + log_d("Received max humidity: %.2f%% from endpoint %d", _max_humidity, src_endpoint); + } + if (attribute->id == ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) { + uint16_t tolerance = attribute->data.value ? *(uint16_t *)attribute->data.value : 0; + _tolerance_humidity = 1.0 * tolerance / 100; + read_humidity_config++; + log_d("Received tolerance: %.2f%% from endpoint %d", _tolerance_humidity, src_endpoint); + } + if (read_humidity_config == 3) { + log_d("All humidity config attributes processed"); + read_humidity_config = 0; + xSemaphoreGive(lock); + } + } +} + +// Temperature measuring methods + +void ZigbeeThermostat::getTemperature() { + /* Send "read attributes" command to all bound sensors */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read temperature' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getTemperature(uint16_t group_addr) { + /* Send "read attributes" command to the group */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read temperature' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getTemperature(uint8_t endpoint, uint16_t short_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read temperature' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getTemperature(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i( + "Sending 'read temperature' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getTemperatureSettings() { + /* Send "read attributes" command to all bound sensors */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read sensor settings' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_temp_config_receive(_min_temp, _max_temp, _tolerance_temp); + } +} + +void ZigbeeThermostat::getTemperatureSettings(uint16_t group_addr) { + /* Send "read attributes" command to the group */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read sensor settings' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_temp_config_receive(_min_temp, _max_temp, _tolerance_temp); + } +} + +void ZigbeeThermostat::getTemperatureSettings(uint8_t endpoint, uint16_t short_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read sensor settings' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_temp_config_receive(_min_temp, _max_temp, _tolerance_temp); + } +} + +void ZigbeeThermostat::getTemperatureSettings(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i( + "Sending 'read sensor settings' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_temp_config_receive(_min_temp, _max_temp, _tolerance_temp); + } +} + +void ZigbeeThermostat::setTemperatureReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to all bound sensors */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_S16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure temperature reporting' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setTemperatureReporting(uint16_t group_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to the group */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_S16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure temperature reporting' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setTemperatureReporting(uint8_t endpoint, uint16_t short_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to specific endpoint */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_endpoint = endpoint; + report_cmd.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_S16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure temperature reporting' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setTemperatureReporting(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to specific endpoint */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_endpoint = endpoint; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT; + memcpy(report_cmd.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_S16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i( + "Sending 'configure temperature reporting' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], + ieee_addr[6], ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +// Humidity measuring methods + +void ZigbeeThermostat::getHumidity() { + /* Send "read attributes" command to all bound sensors */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getHumidity(uint16_t group_addr) { + /* Send "read attributes" command to the group */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getHumidity(uint8_t endpoint, uint16_t short_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getHumidity(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID}; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i( + "Sending 'read humidity' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5], + ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::getHumiditySettings() { + /* Send "read attributes" command to all bound sensors */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity settings' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_humidity_config_receive(_min_humidity, _max_humidity, _tolerance_humidity); + } +} + +void ZigbeeThermostat::getHumiditySettings(uint16_t group_addr) { + /* Send "read attributes" command to the group */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity settings' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_humidity_config_receive(_min_humidity, _max_humidity, _tolerance_humidity); + } +} + +void ZigbeeThermostat::getHumiditySettings(uint8_t endpoint, uint16_t short_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i("Sending 'read humidity settings' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_humidity_config_receive(_min_humidity, _max_humidity, _tolerance_humidity); + } +} + +void ZigbeeThermostat::getHumiditySettings(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + /* Send "read attributes" command to specific endpoint */ + esp_zb_zcl_read_attr_cmd_t read_req; + memset(&read_req, 0, sizeof(read_req)); + read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + read_req.zcl_basic_cmd.src_endpoint = _endpoint; + read_req.zcl_basic_cmd.dst_endpoint = endpoint; + read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + uint16_t attributes[] = { + ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID + }; + read_req.attr_number = ZB_ARRAY_LENGHT(attributes); + read_req.attr_field = attributes; + + log_i( + "Sending 'read humidity settings' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_read_attr_cmd_req(&read_req); + esp_zb_lock_release(); + + //Take semaphore to wait for response of all attributes + if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) { + log_e("Error while reading attributes"); + return; + } else { + //Call the callback function when all attributes are read + _on_humidity_config_receive(_min_humidity, _max_humidity, _tolerance_humidity); + } +} + +void ZigbeeThermostat::setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to all bound sensors */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_U16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure humidity reporting' command"); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setHumidityReporting(uint16_t group_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to the group */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_addr_u.addr_short = group_addr; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_U16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure humidity reporting' command to group address 0x%x", group_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setHumidityReporting(uint8_t endpoint, uint16_t short_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to specific endpoint */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_endpoint = endpoint; + report_cmd.zcl_basic_cmd.dst_addr_u.addr_short = short_addr; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_U16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i("Sending 'configure humidity reporting' command to endpoint %d, address 0x%x", endpoint, short_addr); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} + +void ZigbeeThermostat::setHumidityReporting(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr, uint16_t min_interval, uint16_t max_interval, float delta) { + /* Send "configure report attribute" command to specific endpoint */ + esp_zb_zcl_config_report_cmd_t report_cmd; + memset(&report_cmd, 0, sizeof(report_cmd)); + report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + report_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_cmd.zcl_basic_cmd.dst_endpoint = endpoint; + report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT; + memcpy(report_cmd.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t)); + + int16_t report_change = (int16_t)delta * 100; + esp_zb_zcl_config_report_record_t records[] = { + { + .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND, + .attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, + .attrType = ESP_ZB_ZCL_ATTR_TYPE_U16, + .min_interval = min_interval, + .max_interval = max_interval, + .reportable_change = (void *)&report_change, + }, + }; + report_cmd.record_number = ZB_ARRAY_LENGHT(records); + report_cmd.record_field = records; + + log_i( + "Sending 'configure humidity reporting' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], + ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0] + ); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_config_report_cmd_req(&report_cmd); + esp_zb_lock_release(); +} +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeThermostat.h b/libraries/Zigbee/src/ep/ZigbeeThermostat.h new file mode 100644 index 0000000..57a4c93 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeThermostat.h @@ -0,0 +1,154 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Temperature sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +//define the thermostat configuration to avoid narrowing conversion issue in zigbee-sdk +#define ZB_DEFAULT_THERMOSTAT_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .thermostat_cfg = { \ + .local_temperature = (int16_t)ESP_ZB_ZCL_THERMOSTAT_LOCAL_TEMPERATURE_DEFAULT_VALUE, \ + .occupied_cooling_setpoint = ESP_ZB_ZCL_THERMOSTAT_OCCUPIED_COOLING_SETPOINT_DEFAULT_VALUE, \ + .occupied_heating_setpoint = ESP_ZB_ZCL_THERMOSTAT_OCCUPIED_HEATING_SETPOINT_DEFAULT_VALUE, \ + .control_sequence_of_operation = ESP_ZB_ZCL_THERMOSTAT_CONTROL_SEQ_OF_OPERATION_DEFAULT_VALUE, \ + .system_mode = ESP_ZB_ZCL_THERMOSTAT_CONTROL_SYSTEM_MODE_DEFAULT_VALUE, \ + }, \ + } +class ZigbeeThermostat : public ZigbeeEP { +public: + ZigbeeThermostat(uint8_t endpoint); + ~ZigbeeThermostat() {} + + // Temperature measuring methods + void onTempReceive(void (*callback)(float)) { + _on_temp_receive = callback; + } + void onTempReceiveWithSource(void (*callback)(float, uint8_t, esp_zb_zcl_addr_t)) { + _on_temp_receive_with_source = callback; + } + // For backward compatibility: keep onConfigReceive as an alias to onTempConfigReceive (deprecated). + [[deprecated("Use onTempConfigReceive instead.")]] + void onConfigReceive(void (*callback)(float, float, float)) { + onTempConfigReceive(callback); + } + void onTempConfigReceive(void (*callback)(float, float, float)) { + _on_temp_config_receive = callback; + } + + void getTemperature(); + void getTemperature(uint16_t group_addr); + void getTemperature(uint8_t endpoint, uint16_t short_addr); + void getTemperature(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + // For backward compatibility: keep getSensorSettings as an alias to getTemperatureSettings (deprecated). + [[deprecated("Use getTemperatureSettings instead.")]] + void getSensorSettings() { + getTemperatureSettings(); + } + [[deprecated("Use getTemperatureSettings instead.")]] + void getSensorSettings(uint16_t group_addr) { + getTemperatureSettings(group_addr); + } + [[deprecated("Use getTemperatureSettings instead.")]] + void getSensorSettings(uint8_t endpoint, uint16_t short_addr) { + getTemperatureSettings(endpoint, short_addr); + } + [[deprecated("Use getTemperatureSettings instead.")]] + void getSensorSettings(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) { + getTemperatureSettings(endpoint, ieee_addr); + } + + void getTemperatureSettings(); + void getTemperatureSettings(uint16_t group_addr); + void getTemperatureSettings(uint8_t endpoint, uint16_t short_addr); + void getTemperatureSettings(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void setTemperatureReporting(uint16_t min_interval, uint16_t max_interval, float delta); + void setTemperatureReporting(uint16_t group_addr, uint16_t min_interval, uint16_t max_interval, float delta); + void setTemperatureReporting(uint8_t endpoint, uint16_t short_addr, uint16_t min_interval, uint16_t max_interval, float delta); + void setTemperatureReporting(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr, uint16_t min_interval, uint16_t max_interval, float delta); + + // Humidity measuring methods + void onHumidityReceive(void (*callback)(float)) { + _on_humidity_receive = callback; + } + void onHumidityReceiveWithSource(void (*callback)(float, uint8_t, esp_zb_zcl_addr_t)) { + _on_humidity_receive_with_source = callback; + } + void onHumidityConfigReceive(void (*callback)(float, float, float)) { + _on_humidity_config_receive = callback; + } + + void getHumidity(); + void getHumidity(uint16_t group_addr); + void getHumidity(uint8_t endpoint, uint16_t short_addr); + void getHumidity(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void getHumiditySettings(); + void getHumiditySettings(uint16_t group_addr); + void getHumiditySettings(uint8_t endpoint, uint16_t short_addr); + void getHumiditySettings(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr); + + void setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta); + void setHumidityReporting(uint16_t group_addr, uint16_t min_interval, uint16_t max_interval, float delta); + void setHumidityReporting(uint8_t endpoint, uint16_t short_addr, uint16_t min_interval, uint16_t max_interval, float delta); + void setHumidityReporting(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr, uint16_t min_interval, uint16_t max_interval, float delta); + +private: + // save instance of the class in order to use it in static functions + static ZigbeeThermostat *_instance; + zb_device_params_t *_device; + + void (*_on_temp_receive)(float); + void (*_on_temp_receive_with_source)(float, uint8_t, esp_zb_zcl_addr_t); + void (*_on_temp_config_receive)(float, float, float); + float _min_temp; + float _max_temp; + float _tolerance_temp; + + void (*_on_humidity_receive)(float); + void (*_on_humidity_receive_with_source)(float, uint8_t, esp_zb_zcl_addr_t); + void (*_on_humidity_config_receive)(float, float, float); + float _min_humidity; + float _max_humidity; + float _tolerance_humidity; + + void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req); + void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx); + void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + static void bindCbWrapper(esp_zb_zdp_status_t zdo_status, void *user_ctx); + static void findCbWrapper(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx); + + void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute, uint8_t src_endpoint, esp_zb_zcl_addr_t src_address) override; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp new file mode 100644 index 0000000..a9fd437 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp @@ -0,0 +1,153 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeVibrationSensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_vibration_sensor_clusters_create(zigbee_vibration_sensor_cfg_t *vibration_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = vibration_sensor ? &(vibration_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = vibration_sensor ? &(vibration_sensor->identify_cfg) : NULL; + esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = vibration_sensor ? &(vibration_sensor->ias_zone_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + return cluster_list; +} + +ZigbeeVibrationSensor::ZigbeeVibrationSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_IAS_ZONE_ID; + _zone_status = 0; + _zone_id = 0xff; + _ias_cie_endpoint = 1; + _enrolled = false; + + //Create custom vibration sensor configuration + zigbee_vibration_sensor_cfg_t vibration_sensor_cfg = ZIGBEE_DEFAULT_VIBRATION_SENSOR_CONFIG(); + _cluster_list = zigbee_vibration_sensor_clusters_create(&vibration_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0}; +} + +void ZigbeeVibrationSensor::setIASClientEndpoint(uint8_t ep_number) { + _ias_cie_endpoint = ep_number; +} + +bool ZigbeeVibrationSensor::setVibration(bool sensed) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + log_v("Setting Vibration sensor to %s", sensed ? "sensed" : "not sensed"); + uint8_t vibration = (uint8_t)sensed; + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &vibration, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set vibration status: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + _zone_status = vibration; + return report(); +} + +bool ZigbeeVibrationSensor::report() { + /* Send IAS Zone status changed notification command */ + + esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd; + status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT; + status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint; //default is 1 + memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t)); + status_change_notif_cmd.zone_status = _zone_status; + status_change_notif_cmd.extend_status = 0; + status_change_notif_cmd.zone_id = _zone_id; + status_change_notif_cmd.delay = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone status changed notification sent"); + return true; +} + +void ZigbeeVibrationSensor::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) { + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) { + log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code); + if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) { + log_v("IAS Zone Enroll Response: success"); + esp_zb_lock_acquire(portMAX_DELAY); + memcpy( + _ias_cie_addr, + (*(esp_zb_ieee_addr_t *) + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID) + ->data_p), + sizeof(esp_zb_ieee_addr_t) + ); + esp_zb_lock_release(); + _zone_id = message->zone_id; + _enrolled = true; + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster); + } +} + +bool ZigbeeVibrationSensor::requestIASZoneEnroll() { + esp_zb_zcl_ias_zone_enroll_request_cmd_t enroll_request; + enroll_request.zcl_basic_cmd.src_endpoint = _endpoint; + enroll_request.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + enroll_request.zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_VIBRATION_MOVEMENT; + enroll_request.manuf_code = 0; + + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_ias_zone_enroll_cmd_req(&enroll_request); //return transaction sequence number, ignore it + esp_zb_lock_release(); + log_v("IAS Zone enroll request sent"); + return true; +} + +bool ZigbeeVibrationSensor::restoreIASZoneEnroll() { + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_attr_t *ias_cie_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID); + esp_zb_zcl_attr_t *zone_id_attr = + esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONEID_ID); + esp_zb_lock_release(); + + if (ias_cie_attr == NULL || ias_cie_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: ias cie address attribute not found"); + return false; + } + if (zone_id_attr == NULL || zone_id_attr->data_p == NULL) { + log_e("Failed to restore IAS Zone enroll: zone id attribute not found"); + return false; + } + + memcpy(_ias_cie_addr, (esp_zb_ieee_addr_t *)ias_cie_attr->data_p, sizeof(esp_zb_ieee_addr_t)); + _zone_id = (*(uint8_t *)zone_id_attr->data_p); + + log_d( + "Restored IAS Zone enroll: zone id(%d), ias cie address(%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X)", _zone_id, _ias_cie_addr[0], _ias_cie_addr[1], + _ias_cie_addr[2], _ias_cie_addr[3], _ias_cie_addr[4], _ias_cie_addr[5], _ias_cie_addr[6], _ias_cie_addr[7] + ); + + if (_zone_id == 0xFF) { + log_e("Failed to restore IAS Zone enroll: zone id not valid"); + return false; + } + _enrolled = true; + return true; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h new file mode 100644 index 0000000..a819be0 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h @@ -0,0 +1,90 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee contact switch (IAS Zone) endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// clang-format off +#define ZIGBEE_DEFAULT_VIBRATION_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .ias_zone_cfg = \ + { \ + .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED, \ + .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_VIBRATION_MOVEMENT, \ + .zone_status = 0, \ + .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT, \ + .zone_id = 0xff, \ + .zone_ctx = {0, 0, 0, 0}, \ + }, \ + } +// clang-format on + +typedef struct zigbee_vibration_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg; +} zigbee_vibration_sensor_cfg_t; + +class ZigbeeVibrationSensor : public ZigbeeEP { +public: + ZigbeeVibrationSensor(uint8_t endpoint); + ~ZigbeeVibrationSensor() {} + + // Set the IAS Client endpoint number (default is 1) + void setIASClientEndpoint(uint8_t ep_number); + + // Set the vibration sensor value (true = sensed, false = not sensed) + bool setVibration(bool sensed); + + // Report the vibration sensor value, done automatically after setting the sensed value + bool report(); + + // Request a new IAS zone enroll, can be called to enroll a new device or to re-enroll an already enrolled device + bool requestIASZoneEnroll(); + + // Restore IAS Zone enroll, needed to be called after rebooting already enrolled device - restored from flash memory (faster for sleepy devices) + bool restoreIASZoneEnroll(); + + // Check if the device is enrolled in the IAS Zone + bool enrolled() { + return _enrolled; + } + +private: + void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override; + uint8_t _zone_status; + uint8_t _zone_id; + esp_zb_ieee_addr_t _ias_cie_addr; + uint8_t _ias_cie_endpoint; + bool _enrolled; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp new file mode 100644 index 0000000..1f3f765 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp @@ -0,0 +1,155 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeWindSpeedSensor.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *zigbee_wind_speed_sensor_clusters_create(zigbee_wind_speed_sensor_cfg_t *wind_speed_sensor) { + esp_zb_basic_cluster_cfg_t *basic_cfg = wind_speed_sensor ? &(wind_speed_sensor->basic_cfg) : NULL; + esp_zb_identify_cluster_cfg_t *identify_cfg = wind_speed_sensor ? &(wind_speed_sensor->identify_cfg) : NULL; + esp_zb_wind_speed_measurement_cluster_cfg_t *wind_speed_cfg = wind_speed_sensor ? &(wind_speed_sensor->wind_speed_meas_cfg) : NULL; + esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_wind_speed_measurement_cluster( + cluster_list, esp_zb_wind_speed_measurement_cluster_create(wind_speed_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE + ); + return cluster_list; +} + +// There is no device_id for wind speed sensor, we use a generic one +ZigbeeWindSpeedSensor::ZigbeeWindSpeedSensor(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID; + + zigbee_wind_speed_sensor_cfg_t windspeed_sensor_cfg = ZIGBEE_DEFAULT_WIND_SPEED_SENSOR_CONFIG(); + _cluster_list = zigbee_wind_speed_sensor_clusters_create(&windspeed_sensor_cfg); + + _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0}; +} + +static uint16_t zb_windspeed_to_u16(float windspeed) { + return (uint16_t)(windspeed * 100); +} + +bool ZigbeeWindSpeedSensor::setDefaultValue(float defaultValue) { + uint16_t zb_default_value = zb_windspeed_to_u16(defaultValue); + esp_zb_attribute_list_t *windspeed_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID, (void *)&zb_default_value); + if (ret != ESP_OK) { + log_e("Failed to set default value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindSpeedSensor::setMinMaxValue(float min, float max) { + uint16_t zb_min = zb_windspeed_to_u16(min); + uint16_t zb_max = zb_windspeed_to_u16(max); + esp_zb_attribute_list_t *windspeed_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&zb_min); + if (ret != ESP_OK) { + log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&zb_max); + if (ret != ESP_OK) { + log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindSpeedSensor::setTolerance(float tolerance) { + // Convert tolerance to ZCL uint16_t + uint16_t zb_tolerance = zb_windspeed_to_u16(tolerance); + esp_zb_attribute_list_t *windspeed_measure_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = + esp_zb_wind_speed_measurement_cluster_add_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance); + if (ret != ESP_OK) { + log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindSpeedSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) { + esp_zb_zcl_reporting_info_t reporting_info; + memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t)); + reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV; + reporting_info.ep = _endpoint; + reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT; + reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE; + reporting_info.attr_id = ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID; + reporting_info.u.send_info.min_interval = min_interval; + reporting_info.u.send_info.max_interval = max_interval; + reporting_info.u.send_info.def_min_interval = min_interval; + reporting_info.u.send_info.def_max_interval = max_interval; + reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100); // Convert delta to ZCL uint16_t + reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID; + reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC; + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindSpeedSensor::setWindSpeed(float windspeed) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + uint16_t zb_windspeed = zb_windspeed_to_u16(windspeed); + log_v("Updating windspeed sensor value..."); + /* Update windspeed sensor measured value */ + log_d("Setting windspeed to %d", zb_windspeed); + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID, + &zb_windspeed, false + ); + esp_zb_lock_release(); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set wind speed: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindSpeedSensor::reportWindSpeed() { + /* Send report attributes command */ + esp_zb_zcl_report_attr_cmd_t report_attr_cmd; + report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT; + report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID; + report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI; + report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT; + report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint; + report_attr_cmd.manuf_specific = 0x00U; // Standard profile command. Manufacturer code field shall not be included into ZCL frame header. + report_attr_cmd.dis_default_resp = 0x00U; // Default response is enabled. + + esp_zb_lock_acquire(portMAX_DELAY); + esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd); + esp_zb_lock_release(); + if (ret != ESP_OK) { + log_e("Failed to send wind speed report: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + log_v("Wind speed measurement report sent"); + return true; +} + +#endif //CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h new file mode 100644 index 0000000..011cb5e --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h @@ -0,0 +1,74 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee WindSpeed sensor endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +#define ZIGBEE_DEFAULT_WIND_SPEED_SENSOR_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .wind_speed_meas_cfg = { \ + .measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_DEFAULT, \ + .min_measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MIN_MEASURED_VALUE_DEFAULT, \ + .max_measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MAX_MEASURED_VALUE_DEFAULT, \ + }, \ + } + +typedef struct zigbee_wind_speed_sensor_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; /*!< Basic cluster configuration, @ref esp_zb_basic_cluster_cfg_s */ + esp_zb_identify_cluster_cfg_t identify_cfg; /*!< Identify cluster configuration, @ref esp_zb_identify_cluster_cfg_s */ + esp_zb_wind_speed_measurement_cluster_cfg_t + wind_speed_meas_cfg; /*!< Wind speed measurement cluster configuration, @ref esp_zb_wind_speed_measurement_cluster_cfg_s */ +} zigbee_wind_speed_sensor_cfg_t; + +class ZigbeeWindSpeedSensor : public ZigbeeEP { +public: + ZigbeeWindSpeedSensor(uint8_t endpoint); + ~ZigbeeWindSpeedSensor() {} + + // Set the WindSpeed value in 0,01 m/s + bool setWindSpeed(float value); + + // Set the default (initial) value for the wind speed sensor in 0,01 m/s + // Must be called before adding the EP to Zigbee class. Only effective in factory reset mode (before commissioning) + bool setDefaultValue(float defaultValue); + + // Set the min and max value for the WindSpeed sensor + bool setMinMaxValue(float min, float max); + + // Set the tolerance value for the WindSpeed sensor + bool setTolerance(float tolerance); + + // Set the reporting interval for WindSpeed measurement in seconds and delta + bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta); + bool reportWindSpeed(); +}; + +#endif //CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp new file mode 100644 index 0000000..f4e3657 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp @@ -0,0 +1,413 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "ZigbeeWindowCovering.h" +#if CONFIG_ZB_ENABLED + +esp_zb_cluster_list_t *ZigbeeWindowCovering::zigbee_window_covering_clusters_create(zigbee_window_covering_cfg_t *window_covering_cfg) { + esp_zb_attribute_list_t *esp_zb_basic_cluster = esp_zb_basic_cluster_create(&window_covering_cfg->basic_cfg); + esp_zb_attribute_list_t *esp_zb_identify_cluster = esp_zb_identify_cluster_create(&window_covering_cfg->identify_cfg); + esp_zb_attribute_list_t *esp_zb_groups_cluster = esp_zb_groups_cluster_create(&window_covering_cfg->groups_cfg); + esp_zb_attribute_list_t *esp_zb_scenes_cluster = esp_zb_scenes_cluster_create(&window_covering_cfg->scenes_cfg); + esp_zb_attribute_list_t *esp_zb_window_covering_cluster = esp_zb_window_covering_cluster_create(&window_covering_cfg->window_covering_cfg); + + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID, &_current_lift_percentage + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID, &_current_tilt_percentage + ); + esp_zb_window_covering_cluster_add_attr(esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID, &_current_lift_position); + esp_zb_window_covering_cluster_add_attr(esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID, &_current_lift_position); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_ID, &_installed_open_limit_lift + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_ID, &_installed_open_limit_tilt + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_ID, &_installed_closed_limit_lift + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_ID, &_installed_closed_limit_tilt + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_ID, &_physical_closed_limit_lift + ); + esp_zb_window_covering_cluster_add_attr( + esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_ID, &_physical_closed_limit_lift + ); + + // ------------------------------ Create cluster list ------------------------------ + esp_zb_cluster_list_t *esp_zb_cluster_list = esp_zb_zcl_cluster_list_create(); + esp_zb_cluster_list_add_basic_cluster(esp_zb_cluster_list, esp_zb_basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_identify_cluster(esp_zb_cluster_list, esp_zb_identify_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_groups_cluster(esp_zb_cluster_list, esp_zb_groups_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_scenes_cluster(esp_zb_cluster_list, esp_zb_scenes_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_zb_cluster_list_add_window_covering_cluster(esp_zb_cluster_list, esp_zb_window_covering_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + + return esp_zb_cluster_list; +} + +ZigbeeWindowCovering::ZigbeeWindowCovering(uint8_t endpoint) : ZigbeeEP(endpoint) { + _device_id = ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID; + _on_open = nullptr; + _on_close = nullptr; + _on_go_to_lift_percentage = nullptr; + _on_go_to_tilt_percentage = nullptr; + _on_stop = nullptr; + + // set default values for window covering attributes + _current_lift_percentage = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_DEFAULT_VALUE; + _current_tilt_percentage = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_DEFAULT_VALUE; + _installed_open_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_DEFAULT_VALUE; + _installed_closed_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_DEFAULT_VALUE; + _installed_open_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_DEFAULT_VALUE; + _installed_closed_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_DEFAULT_VALUE; + _current_lift_position = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_LIFT_DEFAULT_VALUE; + _current_tilt_position = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_TILT_DEFAULT_VALUE; + _physical_closed_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_DEFAULT_VALUE; + _physical_closed_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_DEFAULT_VALUE; + + // Create custom window covering configuration + zigbee_window_covering_cfg_t window_covering_cfg = ZIGBEE_DEFAULT_WINDOW_COVERING_CONFIG(); + _cluster_list = zigbee_window_covering_clusters_create(&window_covering_cfg); + + _ep_config = { + .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID, .app_device_version = 0 + }; +} + +// Configuration methods for window covering +bool ZigbeeWindowCovering::setCoveringType(ZigbeeWindowCoveringType covering_type) { + esp_zb_attribute_list_t *window_covering_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_WINDOW_COVERING_TYPE_ID, (void *)&covering_type); + if (ret != ESP_OK) { + log_e("Failed to set covering type: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindowCovering::setConfigStatus( + bool operational, bool online, bool commands_reversed, bool lift_closed_loop, bool tilt_closed_loop, bool lift_encoder_controlled, + bool tilt_encoder_controlled +) { + uint8_t config_status = (operational ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_OPERATIONAL : 0) | (online ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_ONLINE : 0) + | (commands_reversed ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS : 0) + | (lift_closed_loop ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_LIFT_CONTROL_IS_CLOSED_LOOP : 0) + | (tilt_closed_loop ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_TILT_CONTROL_IS_CLOSED_LOOP : 0) + | (lift_encoder_controlled ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_LIFT_ENCODER_CONTROLLED : 0) + | (tilt_encoder_controlled ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_TILT_ENCODER_CONTROLLED : 0); + + log_v("Updating window covering config status to %d", config_status); + + esp_zb_attribute_list_t *window_covering_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID, (void *)&config_status); + if (ret != ESP_OK) { + log_e("Failed to set config status: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindowCovering::setMode(bool motor_reversed, bool calibration_mode, bool maintenance_mode, bool leds_on) { + uint8_t mode = (motor_reversed ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_REVERSED_MOTOR_DIRECTION : 0) + | (calibration_mode ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_RUN_IN_CALIBRATION_MODE : 0) + | (maintenance_mode ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_MOTOR_IS_RUNNING_IN_MAINTENANCE_MODE : 0) + | (leds_on ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_LEDS_WILL_DISPLAY_FEEDBACK : 0); + + log_v("Updating window covering mode to %d", mode); + + esp_zb_attribute_list_t *window_covering_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_MODE_ID, (void *)&mode); + if (ret != ESP_OK) { + log_e("Failed to set mode: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +bool ZigbeeWindowCovering::setLimits( + uint16_t installed_open_limit_lift, uint16_t installed_closed_limit_lift, uint16_t installed_open_limit_tilt, uint16_t installed_closed_limit_tilt +) { + _installed_open_limit_lift = installed_open_limit_lift; + _installed_closed_limit_lift = installed_closed_limit_lift; + _physical_closed_limit_lift = installed_closed_limit_lift; + _installed_open_limit_tilt = installed_open_limit_tilt; + _installed_closed_limit_tilt = installed_closed_limit_tilt; + _physical_closed_limit_tilt = installed_closed_limit_tilt; + + esp_zb_attribute_list_t *window_covering_cluster = + esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE); + esp_err_t ret = + esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_ID, (void *)&_installed_open_limit_lift); + if (ret != ESP_OK) { + log_e("Failed to set installed open limit lift: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_ID, (void *)&_installed_closed_limit_lift); + if (ret != ESP_OK) { + log_e("Failed to set installed closed limit lift: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_ID, (void *)&_installed_open_limit_tilt); + if (ret != ESP_OK) { + log_e("Failed to set installed open limit tilt: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_ID, (void *)&_installed_closed_limit_tilt); + if (ret != ESP_OK) { + log_e("Failed to set installed closed limit tilt: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = + esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_ID, (void *)&_physical_closed_limit_lift); + if (ret != ESP_OK) { + log_e("Failed to set physical closed limit lift: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_ID, (void *)&_physical_closed_limit_tilt); + if (ret != ESP_OK) { + log_e("Failed to set physical closed limit tilt: 0x%x: %s", ret, esp_err_to_name(ret)); + return false; + } + return true; +} + +// Callback for handling incoming messages and commands +void ZigbeeWindowCovering::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) { + //check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING) { + log_v("Received attribute id: 0x%x / data.type: 0x%x", message->attribute.id, message->attribute.data.type); + if (message->attribute.id == ESP_ZB_ZCL_ATTR_WINDOW_COVERING_MODE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_8BITMAP) { + uint8_t mode = *(uint8_t *)message->attribute.data.value; + bool motor_reversed = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_REVERSED_MOTOR_DIRECTION; + bool calibration_mode = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_RUN_IN_CALIBRATION_MODE; + bool maintenance_mode = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_MOTOR_IS_RUNNING_IN_MAINTENANCE_MODE; + bool leds_on = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_LEDS_WILL_DISPLAY_FEEDBACK; + log_v( + "Updating window covering mode to motor reversed: %d, calibration mode: %d, maintenance mode: %d, leds on: %d", motor_reversed, calibration_mode, + maintenance_mode, leds_on + ); + setMode(motor_reversed, calibration_mode, maintenance_mode, leds_on); + //Update Configuration status with motor reversed status + uint8_t config_status; + config_status = (*(uint8_t *)esp_zb_zcl_get_attribute( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID + ) + ->data_p); + config_status = motor_reversed ? config_status | ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS + : config_status & ~ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS; + log_v("Updating window covering config status to %d", config_status); + esp_zb_lock_acquire(portMAX_DELAY); + esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID, &config_status, + false + ); + esp_zb_lock_release(); + return; + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Window Covering", message->info.cluster); + } +} + +void ZigbeeWindowCovering::zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) { + // check the data and call right method + if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING) { + if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_UP_OPEN) { + open(); + return; + } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_DOWN_CLOSE) { + close(); + return; + } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_STOP) { + stop(); + return; + } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_GO_TO_LIFT_PERCENTAGE) { + if (_current_lift_percentage != message->payload.percentage_lift_value) { + _current_lift_percentage = message->payload.percentage_lift_value; + goToLiftPercentage(_current_lift_percentage); + return; + } + } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_GO_TO_TILT_PERCENTAGE) { + if (_current_tilt_percentage != message->payload.percentage_tilt_value) { + _current_tilt_percentage = message->payload.percentage_tilt_value; + goToTiltPercentage(_current_tilt_percentage); + return; + } + } else { + log_w("Received message ignored. Command: %d not supported for Window Covering", message->command); + } + } else { + log_w("Received message ignored. Cluster ID: %d not supported for Window Covering", message->info.cluster); + } +} + +void ZigbeeWindowCovering::open() { + if (_on_open) { + _on_open(); + } +} + +void ZigbeeWindowCovering::close() { + if (_on_close) { + _on_close(); + } +} + +void ZigbeeWindowCovering::goToLiftPercentage(uint8_t lift_percentage) { + if (_on_go_to_lift_percentage) { + _on_go_to_lift_percentage(lift_percentage); + } +} + +void ZigbeeWindowCovering::goToTiltPercentage(uint8_t tilt_percentage) { + if (_on_go_to_tilt_percentage) { + _on_go_to_tilt_percentage(tilt_percentage); + } +} + +void ZigbeeWindowCovering::stop() { + if (_on_stop) { + _on_stop(); + } +} + +// Methods to control window covering from user application +bool ZigbeeWindowCovering::setLiftPosition(uint16_t lift_position) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update both lift attributes + _current_lift_position = lift_position; + _current_lift_percentage = ((lift_position - _installed_open_limit_lift) * 100) / (_installed_closed_limit_lift - _installed_open_limit_lift); + log_v("Updating window covering lift position to %d (%d%)", _current_lift_position, _current_lift_percentage); + + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID, + &_current_lift_position, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set lift position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID, + &_current_lift_percentage, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set lift percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeWindowCovering::setLiftPercentage(uint8_t lift_percentage) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update both lift attributes + _current_lift_percentage = lift_percentage; + _current_lift_position = _installed_open_limit_lift + ((_installed_closed_limit_lift - _installed_open_limit_lift) * lift_percentage) / 100; + log_v("Updating window covering lift percentage to %d%% (%d)", _current_lift_percentage, _current_lift_position); + + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID, + &_current_lift_position, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set lift position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID, + &_current_lift_percentage, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set lift percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeWindowCovering::setTiltPosition(uint16_t tilt_position) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update both tilt attributes + _current_tilt_position = tilt_position; + _current_tilt_percentage = ((tilt_position - _installed_open_limit_tilt) * 100) / (_installed_closed_limit_tilt - _installed_open_limit_tilt); + + log_v("Updating window covering tilt position to %d (%d%)", _current_tilt_position, _current_tilt_percentage); + + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID, + &_current_tilt_position, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set tilt position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID, + &_current_tilt_percentage, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set tilt percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +bool ZigbeeWindowCovering::setTiltPercentage(uint8_t tilt_percentage) { + esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS; + // Update both tilt attributes + _current_tilt_percentage = tilt_percentage; + _current_tilt_position = _installed_open_limit_tilt + ((_installed_closed_limit_tilt - _installed_open_limit_tilt) * tilt_percentage) / 100; + + log_v("Updating window covering tilt percentage to %d%% (%d)", _current_tilt_percentage, _current_tilt_position); + + esp_zb_lock_acquire(portMAX_DELAY); + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID, + &_current_tilt_position, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set tilt position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } + ret = esp_zb_zcl_set_attribute_val( + _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID, + &_current_tilt_percentage, false + ); + if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) { + log_e("Failed to set tilt percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret)); + goto unlock_and_return; + } +unlock_and_return: + esp_zb_lock_release(); + return ret == ESP_ZB_ZCL_STATUS_SUCCESS; +} + +#endif // CONFIG_ZB_ENABLED diff --git a/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h new file mode 100644 index 0000000..f63e5f9 --- /dev/null +++ b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h @@ -0,0 +1,161 @@ +// Copyright 2025 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* Class of Zigbee Window Covering endpoint inherited from common EP class */ + +#pragma once + +#include "soc/soc_caps.h" +#include "sdkconfig.h" +#if CONFIG_ZB_ENABLED + +#include "ZigbeeEP.h" +#include "ha/esp_zigbee_ha_standard.h" + +// Window covering types supported by Zigbee Window Covering cluster +enum ZigbeeWindowCoveringType { + ROLLERSHADE = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE, // LIFT support + ROLLERSHADE_2_MOTOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_2_MOTOR, // LIFT support + ROLLERSHADE_EXTERIOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_EXTERIOR, // LIFT support + ROLLERSHADE_EXTERIOR_2_MOTOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_EXTERIOR_2_MOTOR, // LIFT support + DRAPERY = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_DRAPERY, // LIFT support + AWNING = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_AWNING, // LIFT support + SHUTTER = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_SHUTTER, // TILT support + BLIND_TILT_ONLY = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_TILT_BLIND_TILT_ONLY, // TILT support + BLIND_LIFT_AND_TILT = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_TILT_BLIND_LIFT_AND_TILT, // LIFT and TILT support + PROJECTOR_SCREEN = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_PROJECTOR_SCREEN, // LIFT support +}; + +// clang-format off +#define ZIGBEE_DEFAULT_WINDOW_COVERING_CONFIG() \ + { \ + .basic_cfg = \ + { \ + .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE, \ + .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE, \ + }, \ + .identify_cfg = \ + { \ + .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \ + }, \ + .groups_cfg = \ + { \ + .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .scenes_cfg = \ + { \ + .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE, \ + .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE, \ + .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE, \ + .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE, \ + .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE, \ + }, \ + .window_covering_cfg = \ + { \ + .covering_type = ESP_ZB_ZCL_WINDOW_COVERING_WINDOW_COVERING_TYPE_DEFAULT_VALUE, \ + .covering_status = ESP_ZB_ZCL_WINDOW_COVERING_CONFIG_STATUS_DEFAULT_VALUE, \ + .covering_mode = ESP_ZB_ZCL_WINDOW_COVERING_MODE_DEFAULT_VALUE, \ + }, \ + } +// clang-format on + +typedef struct zigbee_window_covering_cfg_s { + esp_zb_basic_cluster_cfg_t basic_cfg; + esp_zb_identify_cluster_cfg_t identify_cfg; + esp_zb_groups_cluster_cfg_t groups_cfg; + esp_zb_scenes_cluster_cfg_t scenes_cfg; + esp_zb_window_covering_cluster_cfg_t window_covering_cfg; +} zigbee_window_covering_cfg_t; + +class ZigbeeWindowCovering : public ZigbeeEP { +public: + ZigbeeWindowCovering(uint8_t endpoint); + ~ZigbeeWindowCovering() {} + + // Set the callback functions for the window covering commands + void onOpen(void (*callback)()) { + _on_open = callback; + } + void onClose(void (*callback)()) { + _on_close = callback; + } + void onGoToLiftPercentage(void (*callback)(uint8_t)) { + _on_go_to_lift_percentage = callback; + } + void onGoToTiltPercentage(void (*callback)(uint8_t)) { + _on_go_to_tilt_percentage = callback; + } + void onStop(void (*callback)()) { + _on_stop = callback; + } + + // Set the window covering position in centimeters or percentage (0-100) + bool setLiftPosition(uint16_t lift_position); + bool setLiftPercentage(uint8_t lift_percentage); + bool setTiltPosition(uint16_t tilt_position); + bool setTiltPercentage(uint8_t tilt_percentage); + + // Set the window covering type (see ZigbeeWindowCoveringType) + bool setCoveringType(ZigbeeWindowCoveringType covering_type); + + // Set window covering config/status, for more info see esp_zb_zcl_window_covering_config_status_t + bool setConfigStatus( + bool operational, bool online, bool commands_reversed, bool lift_closed_loop, bool tilt_closed_loop, bool lift_encoder_controlled, + bool tilt_encoder_controlled + ); + + // Set configuration mode of window covering, for more info see esp_zb_zcl_window_covering_mode_t + bool setMode(bool motor_reversed, bool calibration_mode, bool maintenance_mode, bool leds_on); + + // Set limits of motion, for more info see esp_zb_zcl_window_covering_info_attr_t + bool setLimits( + uint16_t installed_open_limit_lift, uint16_t installed_closed_limit_lift, uint16_t installed_open_limit_tilt, uint16_t installed_closed_limit_tilt + ); + +private: + void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override; + void zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) override; + + // Create window covering cluster list + esp_zb_cluster_list_t *zigbee_window_covering_clusters_create(zigbee_window_covering_cfg_t *window_covering_cfg); + + void open(); + void close(); + void goToLiftPercentage(uint8_t); + void goToTiltPercentage(uint8_t); + void stop(); + + // callback function to be called on lift percentage change (lift percentage) + void (*_on_open)(); + void (*_on_close)(); + void (*_on_go_to_lift_percentage)(uint8_t); + void (*_on_go_to_tilt_percentage)(uint8_t); + void (*_on_stop)(); + + // Widows covering lift attributes + uint8_t _current_lift_percentage; + uint16_t _current_lift_position; + uint16_t _installed_open_limit_lift; + uint16_t _installed_closed_limit_lift; + uint16_t _physical_closed_limit_lift; + + // Windows covering tilt attributes + uint8_t _current_tilt_percentage; + uint16_t _current_tilt_position; + uint16_t _installed_open_limit_tilt; + uint16_t _installed_closed_limit_tilt; + uint16_t _physical_closed_limit_tilt; +}; + +#endif // CONFIG_ZB_ENABLED diff --git a/package.json b/package.json new file mode 100644 index 0000000..dc58c88 --- /dev/null +++ b/package.json @@ -0,0 +1,16 @@ +{ + "name": "framework-arduinoespressif32", + "version": "3.3.7", + "description": "Arduino Wiring-based Framework for the Espressif ESP32, ESP32-P4, ESP32-S and ESP32-C series of SoCs", + "keywords": [ + "framework", + "arduino", + "espressif", + "esp32" + ], + "license": "LGPL-2.1-or-later", + "repository": { + "type": "git", + "url": "https://github.com/espressif/arduino-esp32" + } +} diff --git a/platform.txt b/platform.txt new file mode 100644 index 0000000..dc99bae --- /dev/null +++ b/platform.txt @@ -0,0 +1,398 @@ +name=ESP32 Arduino +version=3.3.7 + +tools.esp32-arduino-libs.path={runtime.tools.{build.chip_variant}-libs.path} +tools.esp32-arduino-libs.path.windows={runtime.tools.{build.chip_variant}-libs.path} +tools.xtensa-esp-elf-gcc.path={runtime.tools.esp-x32.path} +tools.xtensa-esp-elf-gdb.path={runtime.tools.xtensa-esp-elf-gdb.path} +tools.riscv32-esp-elf-gcc.path={runtime.tools.esp-rv32.path} +tools.riscv32-esp-elf-gdb.path={runtime.tools.riscv32-esp-elf-gdb.path} + +tools.esptool_py.path={runtime.tools.esptool_py.path} +tools.esptool_py.cmd=esptool +tools.esptool_py.cmd.windows=esptool.exe + +tools.esptool_py.network_cmd=python3 "{runtime.platform.path}/tools/espota.py" -r +tools.esptool_py.network_cmd.windows="{runtime.platform.path}\tools\espota.exe" -r + +tools.esp_ota.cmd=python3 "{runtime.platform.path}/tools/espota.py" -r +tools.esp_ota.cmd.windows="{runtime.platform.path}\tools\espota.exe" -r + +tools.gen_esp32part.cmd=python3 "{runtime.platform.path}/tools/gen_esp32part.py" +tools.gen_esp32part.cmd.windows="{runtime.platform.path}\tools\gen_esp32part.exe" + +tools.gen_insights_pkg.cmd=python3 "{runtime.platform.path}"/tools/gen_insights_package.py +tools.gen_insights_pkg.cmd.windows="{runtime.platform.path}\tools\gen_insights_package.exe" + +compiler.path={tools.{build.tarch}-esp-elf-gcc.path}/bin/ +compiler.prefix={build.tarch}-{build.target}-elf- + +compiler.sdk.path={tools.esp32-arduino-libs.path} + +# EXPERIMENTAL feature: optimization flags +# - this is alpha and may be subject to change without notice +compiler.optimization_flags=-Os +compiler.optimization_flags.release=-Os +compiler.optimization_flags.debug=-Og -g3 + +# Arduino Compile Warning Levels +compiler.warning_flags=-w +compiler.warning_flags.none=-w +compiler.warning_flags.default= +compiler.warning_flags.more=-Wall +compiler.warning_flags.all=-Wall -Wextra + +# Additional flags specific to Arduino (not based on IDF flags). +# Update tools/pioarduino-build.py when changing these flags. +compiler.common_werror_flags=-Werror=return-type + +# Compile Flags +compiler.cpreprocessor.flags="@{compiler.sdk.path}/flags/defines" "-I{build.source.path}" -iprefix "{compiler.sdk.path}/include/" "@{compiler.sdk.path}/flags/includes" "-I{compiler.sdk.path}/{build.memory_type}/include" +compiler.c.flags=-MMD -c "@{compiler.sdk.path}/flags/c_flags" {compiler.warning_flags} {compiler.optimization_flags} {compiler.common_werror_flags} +compiler.cpp.flags=-MMD -c "@{compiler.sdk.path}/flags/cpp_flags" {compiler.warning_flags} {compiler.optimization_flags} {compiler.common_werror_flags} +compiler.S.flags=-MMD -c -x assembler-with-cpp "@{compiler.sdk.path}/flags/S_flags" {compiler.warning_flags} {compiler.optimization_flags} +compiler.c.elf.flags="-Wl,--Map={build.path}/{build.project_name}.map" "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" "-L{compiler.sdk.path}/{build.memory_type}" "-Wl,--wrap=esp_panic_handler" "@{compiler.sdk.path}/flags/ld_flags" "@{compiler.sdk.path}/flags/ld_scripts" +compiler.c.elf.libs="@{compiler.sdk.path}/flags/ld_libs" +compiler.ar.flags=cr + +# Compilers +compiler.c.cmd={compiler.prefix}gcc +compiler.cpp.cmd={compiler.prefix}g++ +compiler.S.cmd={compiler.prefix}gcc +compiler.c.elf.cmd={compiler.prefix}g++ +compiler.as.cmd={compiler.prefix}as +compiler.ar.cmd={compiler.prefix}gcc-ar +compiler.size.cmd={compiler.prefix}size + +# These can be overridden in platform.local.txt +compiler.c.extra_flags= +compiler.cpp.extra_flags= +compiler.S.extra_flags= +compiler.c.elf.extra_flags= +compiler.ar.extra_flags= +compiler.objcopy.eep.extra_flags= +compiler.elf2hex.extra_flags= +compiler.libraries.ldflags= + +# Target dependent definitions +build.extra_flags.esp32=-DARDUINO_USB_CDC_ON_BOOT=0 +build.extra_flags.esp32s3=-DARDUINO_USB_MODE={build.usb_mode} -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot} +build.extra_flags.esp32s2=-DARDUINO_USB_MODE=0 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot} +build.extra_flags.esp32c2=-DARDUINO_USB_CDC_ON_BOOT=0 +build.extra_flags.esp32c3=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} +build.extra_flags.esp32c6=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} +build.extra_flags.esp32h2=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} +build.extra_flags.esp32p4=-DARDUINO_USB_MODE={build.usb_mode} -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot} +build.extra_flags.esp32c5=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} +build.extra_flags.esp32c61=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} + +# This can be overriden in boards.txt +build.zigbee_mode= +build.zigbee_libs= +build.flash_size=4MB +build.flash_mode=dio +build.flash_freq=80m +build.img_freq={build.flash_freq} +build.boot=qio +build.boot_freq={build.flash_freq} +build.bootloader_addr=0x1000 +build.custom_bootloader=bootloader +build.custom_partitions=partitions +build.code_debug=0 +build.defines= +build.loop_core= +build.event_core= +build.extra_flags=-DARDUINO_HOST_OS="{runtime.os}" -DARDUINO_FQBN="{build.fqbn}" -DESP32=ESP32 -DCORE_DEBUG_LEVEL={build.code_debug} {build.loop_core} {build.event_core} {build.defines} {build.extra_flags.{build.mcu}} {build.zigbee_mode} +build.extra_libs= +build.memory_type={build.boot}_qspi +build.chip_variant={build.mcu} + +# Custom build options +build.opt.name=build_opt.h +build.opt.path={build.path}/{build.opt.name} + +# Check if custom partitions exist: source > variant > build.partitions +recipe.hooks.prebuild.1.pattern=/usr/bin/env bash -c "[ ! -f "{build.source.path}"/partitions.csv ] || cp -f "{build.source.path}"/partitions.csv "{build.path}"/partitions.csv" +recipe.hooks.prebuild.2.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/partitions.csv ] || [ ! -f "{build.variant.path}"/{build.custom_partitions}.csv ] || cp "{build.variant.path}"/{build.custom_partitions}.csv "{build.path}"/partitions.csv" +recipe.hooks.prebuild.3.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/partitions.csv ] || cp "{runtime.platform.path}"/tools/partitions/{build.partitions}.csv "{build.path}"/partitions.csv" + +recipe.hooks.prebuild.1.pattern.windows=cmd /c if exist "{build.source.path}\partitions.csv" COPY /y "{build.source.path}\partitions.csv" "{build.path}\partitions.csv" +recipe.hooks.prebuild.2.pattern.windows=cmd /c if not exist "{build.path}\partitions.csv" if exist "{build.variant.path}\{build.custom_partitions}.csv" COPY "{build.variant.path}\{build.custom_partitions}.csv" "{build.path}\partitions.csv" +recipe.hooks.prebuild.3.pattern.windows=cmd /c if not exist "{build.path}\partitions.csv" COPY "{runtime.platform.path}\tools\partitions\{build.partitions}.csv" "{build.path}\partitions.csv" + +# Check if custom bootloader exist: source > variant > build.boot +recipe.hooks.prebuild.4.pattern_args=--chip {build.mcu} elf2image --flash-mode {build.flash_mode} --flash-freq {build.img_freq} --flash-size {build.flash_size} -o +recipe.hooks.prebuild.4.pattern=/usr/bin/env bash -c "[ -f "{build.source.path}"/bootloader.bin ] && cp -f "{build.source.path}"/bootloader.bin "{build.path}"/{build.project_name}.bootloader.bin || ( [ -f "{build.variant.path}"/{build.custom_bootloader}.bin ] && cp "{build.variant.path}"/{build.custom_bootloader}.bin "{build.path}"/{build.project_name}.bootloader.bin || "{tools.esptool_py.path}"/{tools.esptool_py.cmd} {recipe.hooks.prebuild.4.pattern_args} "{build.path}"/{build.project_name}.bootloader.bin "{compiler.sdk.path}"/bin/bootloader_{build.boot}_{build.boot_freq}.elf )" +recipe.hooks.prebuild.4.pattern.windows=cmd /c IF EXIST "{build.source.path}\bootloader.bin" ( COPY /y "{build.source.path}\bootloader.bin" "{build.path}\{build.project_name}.bootloader.bin" ) ELSE ( IF EXIST "{build.variant.path}\{build.custom_bootloader}.bin" ( COPY "{build.variant.path}\{build.custom_bootloader}.bin" "{build.path}\{build.project_name}.bootloader.bin" ) ELSE ( "{tools.esptool_py.path}\{tools.esptool_py.cmd}" {recipe.hooks.prebuild.4.pattern_args} "{build.path}\{build.project_name}.bootloader.bin" "{compiler.sdk.path}\bin\bootloader_{build.boot}_{build.boot_freq}.elf" ) ) + +# Check if custom build options exist in the sketch folder +recipe.hooks.prebuild.5.pattern=/usr/bin/env bash -c "[ ! -f "{build.source.path}"/build_opt.h ] || cp -f "{build.source.path}"/build_opt.h "{build.path}"/build_opt.h" +recipe.hooks.prebuild.6.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/build_opt.h ] || : > "{build.path}"/build_opt.h" + +recipe.hooks.prebuild.5.pattern.windows=cmd /c if exist "{build.source.path}\build_opt.h" COPY /y "{build.source.path}\build_opt.h" "{build.path}\build_opt.h" +recipe.hooks.prebuild.6.pattern.windows=cmd /c if not exist "{build.path}\build_opt.h" type nul > "{build.path}\build_opt.h" + +# Set -DARDUINO_CORE_BUILD only on core file compilation +file_opts.path={build.path}/file_opts +recipe.hooks.prebuild.7.pattern=/usr/bin/env bash -c ": > '{file_opts.path}'" +recipe.hooks.core.prebuild.1.pattern=/usr/bin/env bash -c "echo -DARDUINO_CORE_BUILD > '{file_opts.path}'" +recipe.hooks.core.postbuild.1.pattern=/usr/bin/env bash -c ": > '{file_opts.path}'" + +recipe.hooks.prebuild.7.pattern.windows=cmd /c type nul > "{file_opts.path}" +recipe.hooks.core.prebuild.1.pattern.windows=cmd /c echo "-DARDUINO_CORE_BUILD" > "{file_opts.path}" +recipe.hooks.core.postbuild.1.pattern.windows=cmd /c type nul > "{file_opts.path}" + +# Copy sdkconfig to build folder +recipe.hooks.prebuild.8.pattern=/usr/bin/env bash -c "cp -f "{compiler.sdk.path}"/sdkconfig "{build.path}"/sdkconfig" +recipe.hooks.prebuild.8.pattern.windows=cmd /c COPY /y "{compiler.sdk.path}\sdkconfig" "{build.path}\sdkconfig" + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.extra_flags} {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}" + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.extra_flags} {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}" + +## Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.extra_flags} {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}" + +## Create archives +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -Wl,--start-group {object_files} "{archive_file_path}" {build.extra_libs} {build.zigbee_libs} {compiler.c.elf.libs} {compiler.libraries.ldflags} -Wl,--end-group -Wl,-EL -o "{build.path}/{build.project_name}.elf" + +## Create partitions.bin +recipe.objcopy.partitions.bin.pattern={tools.gen_esp32part.cmd} -q "{build.path}/partitions.csv" "{build.path}/{build.project_name}.partitions.bin" + +## Create bin +recipe.objcopy.bin.pattern_args=--chip {build.mcu} elf2image --flash-mode "{build.flash_mode}" --flash-freq "{build.img_freq}" --flash-size "{build.flash_size}" --elf-sha256-offset 0xb0 -o "{build.path}/{build.project_name}.bin" "{build.path}/{build.project_name}.elf" +recipe.objcopy.bin.pattern="{tools.esptool_py.path}/{tools.esptool_py.cmd}" {recipe.objcopy.bin.pattern_args} + +## Create Insights Firmware Package +recipe.hooks.objcopy.postobjcopy.1.pattern_args={build.path} {build.project_name} "{build.source.path}" +recipe.hooks.objcopy.postobjcopy.1.pattern=/usr/bin/env bash -c "[ ! -d "{build.path}"/libraries/Insights ] || {tools.gen_insights_pkg.cmd} {recipe.hooks.objcopy.postobjcopy.1.pattern_args}" +recipe.hooks.objcopy.postobjcopy.1.pattern.windows=cmd /c if exist "{build.path}\libraries\Insights" {tools.gen_insights_pkg.cmd} {recipe.hooks.objcopy.postobjcopy.1.pattern_args} + +## Copy ESP_SR Model +recipe.hooks.objcopy.postobjcopy.2.pattern=/usr/bin/env bash -c "[ ! -d "{build.path}"/libraries/ESP_SR ] || [ ! -f "{compiler.sdk.path}"/esp_sr/srmodels.bin ] || cp -f "{compiler.sdk.path}"/esp_sr/srmodels.bin "{build.path}"/srmodels.bin" +recipe.hooks.objcopy.postobjcopy.2.pattern.windows=cmd /c if exist "{build.path}\libraries\ESP_SR" if exist "{compiler.sdk.path}\esp_sr\srmodels.bin" COPY /y "{compiler.sdk.path}\esp_sr\srmodels.bin" "{build.path}\srmodels.bin" + +# Create merged binary +recipe.hooks.objcopy.postobjcopy.3.pattern_args=--chip {build.mcu} merge-bin -o "{build.path}/{build.project_name}.merged.bin" --pad-to-size {build.flash_size} --flash-mode keep --flash-freq keep --flash-size keep {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x10000 "{build.path}/{build.project_name}.bin" +recipe.hooks.objcopy.postobjcopy.3.pattern="{tools.esptool_py.path}/{tools.esptool_py.cmd}" {recipe.hooks.objcopy.postobjcopy.3.pattern_args} + +# Generate flash_args file +# Do NOT change the spacing: specifically, do not insert whitespace between a closing quote (') and the following redirection/operator symbols (>, >>, &&). This avoids a bug in older arduino-builder versions shipped with IDE 1.x, which occurs if a quote (') character is directly followed by a whitespace. +recipe.hooks.objcopy.postobjcopy.4.pattern=/usr/bin/env bash -c "echo '--flash-mode {build.flash_mode} --flash-freq {build.img_freq} --flash-size {build.flash_size}'>'{build.path}/flash_args'&& echo '{build.bootloader_addr} {build.project_name}.bootloader.bin'>> '{build.path}/flash_args'&& echo '0x8000 {build.project_name}.partitions.bin'>> '{build.path}/flash_args'&& echo '0xe000 boot_app0.bin'>> '{build.path}/flash_args'&& echo '0x10000 {build.project_name}.bin'>> '{build.path}/flash_args'" +recipe.hooks.objcopy.postobjcopy.4.pattern.windows=cmd /c echo --flash-mode {build.flash_mode} --flash-freq {build.img_freq} --flash-size {build.flash_size} > "{build.path}\flash_args" && echo {build.bootloader_addr} {build.project_name}.bootloader.bin >> "{build.path}\flash_args" && echo 0x8000 {build.project_name}.partitions.bin >> "{build.path}\flash_args" && echo 0xe000 boot_app0.bin >> "{build.path}\flash_args" && echo 0x10000 {build.project_name}.bin >> "{build.path}\flash_args" + +## Save bin +recipe.output.tmp_file={build.project_name}.bin +recipe.output.save_file={build.project_name}.{build.variant}.bin + +## Compute size +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=^(?:\.iram0\.text|\.iram0\.vectors|\.dram0\.data|\.dram1\.data|\.flash\.text|\.flash\.rodata|\.flash\.appdesc|\.flash\.init_array|\.eh_frame|)\s+([0-9]+).* +recipe.size.regex.data=^(?:\.dram0\.data|\.dram0\.bss|\.dram1\.data|\.dram1\.bss|\.noinit)\s+([0-9]+).* + +## Export extra build artifacts when "Export compiled Binary" is selected + +## By default Arduino IDE exports everything that starts with the sketch name +## We need to export other files as well + +## Define FQBN transformation logic as reusable properties +## Converts FQBN to vendor.arch.board format matching Arduino IDE default export path +recipe.hooks.savehex.fqbn_to_dir=FQBN_DIR=$(echo '{build.fqbn}' | cut -d: -f1-3 | tr ':' '.') && mkdir -p '{sketch_path}/build/'$FQBN_DIR +recipe.hooks.savehex.fqbn_to_dir.windows=$env:FQBN_DIR=('{build.fqbn}' -split ':')[0..2] -join '.'; $dest='{sketch_path}\build\' + $env:FQBN_DIR; New-Item -ItemType Directory -Force -Path $dest | Out-Null + +## Export all files starting with sketch name (*.bin, *.elf, *.map, etc.) +## IDE v1 does not do this automatically like IDE v2 +recipe.hooks.savehex.postsavehex.0.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{build.path}/{build.project_name}.'* '{sketch_path}/build/'$FQBN_DIR'/' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.0.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue -Path '{build.path}\{build.project_name}.*' -Destination $dest" + +## Export partitions.csv (for reference) +recipe.hooks.savehex.postsavehex.1.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{build.path}/partitions.csv' '{sketch_path}/build/'$FQBN_DIR'/partitions.csv' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.1.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue '{build.path}\partitions.csv' ($dest + '\partitions.csv')" + +## Export sdkconfig (for reference) +recipe.hooks.savehex.postsavehex.2.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{build.path}/sdkconfig' '{sketch_path}/build/'$FQBN_DIR'/sdkconfig' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.2.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue '{build.path}\sdkconfig' ($dest + '\sdkconfig')" + +## Export flash_args +recipe.hooks.savehex.postsavehex.3.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{build.path}/flash_args' '{sketch_path}/build/'$FQBN_DIR'/flash_args' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.3.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue '{build.path}\flash_args' ($dest + '\flash_args')" + +## Export boot_app0.bin +recipe.hooks.savehex.postsavehex.4.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{runtime.platform.path}/tools/partitions/boot_app0.bin' '{sketch_path}/build/'$FQBN_DIR'/boot_app0.bin' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.4.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue '{runtime.platform.path}\tools\partitions\boot_app0.bin' ($dest + '\boot_app0.bin')" + +## Export build.options.json +recipe.hooks.savehex.postsavehex.5.pattern=/usr/bin/env bash -c "{recipe.hooks.savehex.fqbn_to_dir} && cp -f '{build.path}/build.options.json' '{sketch_path}/build/'$FQBN_DIR'/build.options.json' 2>/dev/null || true" +recipe.hooks.savehex.postsavehex.5.pattern.windows=powershell -Command "{recipe.hooks.savehex.fqbn_to_dir}; Copy-Item -Force -ErrorAction SilentlyContinue '{build.path}\build.options.json' ($dest + '\build.options.json')" + +## Required discoveries and monitors +## --------------------------------- +pluggable_discovery.required.0=builtin:serial-discovery +pluggable_discovery.required.1=builtin:mdns-discovery +pluggable_monitor.required.serial=builtin:serial-monitor + +## ------------------ +## Upload/Debug tools +## ------------------ + +# Debugger configuration +# ---------------------- + +# ESP32 debug configuration +debug_script.esp32=esp32-wrover-kit-3.3v.cfg +debug_config.esp32.cortex-debug.custom.name=Arduino on ESP32 +debug_config.esp32.cortex-debug.custom.postAttachCommands.0=set remote hardware-watchpoint-limit 2 +debug_config.esp32.cortex-debug.custom.postAttachCommands.1=monitor reset halt +debug_config.esp32.cortex-debug.custom.postAttachCommands.2=monitor gdb_sync +debug_config.esp32.cortex-debug.custom.postAttachCommands.3=thb setup +debug_config.esp32.cortex-debug.custom.postAttachCommands.4=c +debug_config.esp32.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt +debug_config.esp32.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync +debug_config.esp32.cortex-debug.custom.overrideRestartCommands.2=thb setup +debug_config.esp32.cortex-debug.custom.overrideRestartCommands.3=c + +# ESP32-S2 debug configuration +debug_script.esp32s2=esp32s2-kaluga-1.cfg +debug_config.esp32s2.cortex-debug.custom.name=Arduino on ESP32-S2 +debug_config.esp32s2.cortex-debug.custom.postAttachCommands.0=set remote hardware-watchpoint-limit 2 +debug_config.esp32s2.cortex-debug.custom.postAttachCommands.1=monitor reset halt +debug_config.esp32s2.cortex-debug.custom.postAttachCommands.2=monitor gdb_sync +debug_config.esp32s2.cortex-debug.custom.postAttachCommands.3=thb setup +debug_config.esp32s2.cortex-debug.custom.postAttachCommands.4=c +debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt +debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync +debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.2=thb setup +debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.3=c + +# ESP32-S3 debug configuration +debug_script.esp32s3=esp32s3-builtin.cfg +debug_config.esp32s3.cortex-debug.custom.name=Arduino on ESP32-S3 +debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 2 +debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.1=monitor reset halt +debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.2=monitor gdb_sync +debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.3=thb setup +debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.4=c +debug_config.esp32s3.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt +debug_config.esp32s3.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync + +# ESP32-C3 debug configuration +debug_script.esp32c3=esp32c3-builtin.cfg +debug_config.esp32c3.cortex-debug.custom.name=Arduino on ESP32-C3 +debug_config.esp32c3.cortex-debug.custom.serverArgs.0=-d3 +debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 8 +debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.1=monitor reset +debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.2=monitor halt +debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.3=monitor gdb_sync +debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.4=thb setup +debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.0=monitor reset +debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.1=monitor halt +debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.2=monitor gdb_sync +debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.3=thb setup + +# ESP32-C6 debug configuration (TBD) +debug_script.esp32c6=esp32c6-builtin.cfg +debug_config.esp32c6= + +# ESP32-H2 debug configuration (TBD) +debug_script.esp32h2=esp32h2-builtin.cfg +debug_config.esp32h2= + +# ESP32-P4 debug configuration (TBD) +debug_script.esp32p4=esp32p4-builtin.cfg +debug_config.esp32p4= + +# ESP32-C5 debug configuration (TBD) +debug_script.esp32c5=esp32c5-builtin.cfg +debug_config.esp32c5= + +# Debug API variable definitions +debug.executable={build.path}/{build.project_name}.elf +debug.toolchain=gcc +debug.toolchain.path={tools.{build.tarch}-esp-elf-gdb.path}/bin/ +debug.toolchain.prefix={build.tarch}-{build.target}-elf +debug.server=openocd +debug.server.openocd.path={runtime.tools.openocd-esp32.path}/bin/openocd +debug.server.openocd.scripts_dir={runtime.tools.openocd-esp32.path}/share/openocd/scripts/ +debug.server.openocd.scripts_dir.windows={runtime.tools.openocd-esp32.path}\share\openocd\scripts\ +debug.server.openocd.scripts.0=board/{debug_script.{build.mcu}} +debug.svd_file={runtime.platform.path}/tools/ide-debug/svd/{build.mcu}.svd + +debug.cortex-debug.custom.objdumpPath={compiler.path}{compiler.prefix}objdump +debug.cortex-debug.custom.request=attach +debug.additional_config=debug_config.{build.mcu} + +## +## ESPTool +## + +## Upload Sketch +## ------------- +tools.esptool_py.upload.protocol=serial +tools.esptool_py.upload.params.verbose= +tools.esptool_py.upload.params.quiet= +tools.esptool_py.upload.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default-reset --after hard-reset write-flash {upload.erase_cmd} -z --flash-mode keep --flash-freq keep --flash-size keep {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x10000 "{build.path}/{build.project_name}.bin" {upload.extra_flags} +tools.esptool_py.upload.pattern="{path}/{cmd}" {upload.pattern_args} + +## Program Application +## ------------------- +tools.esptool_py.program.params.verbose= +tools.esptool_py.program.params.quiet= +tools.esptool_py.program.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default-reset --after hard-reset write-flash -z --flash-mode keep --flash-freq keep --flash-size keep 0x10000 "{build.path}/{build.project_name}.bin" +tools.esptool_py.program.pattern="{path}/{cmd}" {program.pattern_args} + +## Erase Chip (before burning the bootloader) +## ------------------------------------------ +tools.esptool_py.erase.protocol=serial +tools.esptool_py.erase.params.verbose= +tools.esptool_py.erase.params.quiet= +tools.esptool_py.erase.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default-reset --after hard-reset erase-flash +tools.esptool_py.erase.pattern="{path}/{cmd}" {erase.pattern_args} + +## Burn Bootloader +## --------------- +tools.esptool_py.bootloader.protocol=serial +tools.esptool_py.bootloader.params.verbose= +tools.esptool_py.bootloader.params.quiet= +tools.esptool_py.bootloader.pattern= + +## Upload Sketch Through OTA (Arduino IDE 1.x) +## ------------------------------------------- +## The following rule is deprecated by pluggable discovery. +## We keep it to avoid breaking compatibility with the Arduino Java IDE. +tools.esptool_py.upload.network_pattern={network_cmd} -i "{serial.port}" -p "{network.port}" "--auth={network.password}" -f "{build.path}/{build.project_name}.bin" + +## Upload Sketch Through OTA (Arduino IDE 2.x) +## ------------------------------------------- +tools.esp_ota.upload.protocol=network +tools.esp_ota.upload.field.password=Password +tools.esp_ota.upload.field.password.secret=true +tools.esp_ota.upload.pattern={cmd} -i {upload.port.address} -p {upload.port.properties.port} "--auth={upload.field.password}" -f "{build.path}/{build.project_name}.bin" + +## Upload Sketch Through DFU OTA +## ------------------------------------------- +tools.dfu-util.path={runtime.tools.dfu-util-0.11.0-arduino5.path} +tools.dfu-util.cmd=dfu-util +tools.dfu-util.upload.params.verbose=-d +tools.dfu-util.upload.params.quiet= +tools.dfu-util.upload.pattern="{path}/{cmd}" --device {vid.0}:{pid.0} -D "{build.path}/{build.project_name}.bin" -Q + +## -------------------------------------------------------------------------- +## esptool_py_app_only is used to upload only the application image +## It won't upload the bootloader or any other binary except for the main application +## -------------------------------------------------------------------------- +tools.esptool_py_app_only.path={runtime.tools.esptool_py.path} +tools.esptool_py_app_only.cmd=esptool +tools.esptool_py_app_only.cmd.windows=esptool.exe + +tools.esptool_py_app_only.upload.protocol=serial +tools.esptool_py_app_only.upload.params.verbose= +tools.esptool_py_app_only.upload.params.quiet= + +tools.esptool_py_app_only.upload.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default-reset --after hard-reset write-flash --flash-mode {build.flash_mode} --flash-freq {build.flash_freq} --flash-size {build.flash_size} {build.flash_offset} "{build.path}/{build.project_name}.bin" {upload.extra_flags} + +tools.esptool_py_app_only.upload.pattern="{path}/{cmd}" {tools.esptool_py_app_only.upload.pattern_args} diff --git a/programmers.txt b/programmers.txt new file mode 100644 index 0000000..8148c18 --- /dev/null +++ b/programmers.txt @@ -0,0 +1,8 @@ +esptool.name=Esptool +esptool.communication=serial +esptool.protocol=serial +esptool.program.protocol=serial +esptool.program.tool=esptool_py +esptool.program.tool.default=esptool_py +esptool.program.extra_params= +esptool.extra_params= diff --git a/tools/espota.exe b/tools/espota.exe new file mode 100644 index 0000000..2f6e40d Binary files /dev/null and b/tools/espota.exe differ diff --git a/tools/espota.py b/tools/espota.py new file mode 100755 index 0000000..d3c4bc6 --- /dev/null +++ b/tools/espota.py @@ -0,0 +1,583 @@ +#!/usr/bin/env python +# +# Original espota.py by Ivan Grokhotkov: +# https://gist.github.com/igrr/d35ab8446922179dc58c +# +# Modified since 2015-09-18 from Pascal Gollor (https://github.com/pgollor) +# Modified since 2015-11-09 from Hristo Gochkov (https://github.com/me-no-dev) +# Modified since 2016-01-03 from Matthew O'Gorman (https://githumb.com/mogorman) +# Modified since 2025-09-04 from Lucas Saavedra Vaz (https://github.com/lucasssvaz) +# +# This script will push an OTA update to the ESP +# use it like: +# python espota.py -i -I -p -P [-a password] -f +# Or to upload SPIFFS image: +# python espota.py -i -I -p -P [-a password] -s -f +# +# Changes +# 2015-09-18: +# - Add option parser. +# - Add logging. +# - Send command to controller to differ between flashing and transmitting SPIFFS image. +# +# Changes +# 2015-11-09: +# - Added digest authentication +# - Enhanced error tracking and reporting +# +# Changes +# 2016-01-03: +# - Added more options to parser. +# +# Changes +# 2023-05-22: +# - Replaced the deprecated optparse module with argparse. +# - Adjusted the code style to conform to PEP 8 guidelines. +# - Used with statement for file handling to ensure proper resource cleanup. +# - Incorporated exception handling to catch and handle potential errors. +# - Made variable names more descriptive for better readability. +# - Introduced constants for better code maintainability. +# +# Changes +# 2025-09-04: +# - Changed authentication to use PBKDF2-HMAC-SHA256 for challenge/response +# +# Changes +# 2025-09-18: +# - Fixed authentication when using old images with MD5 passwords +# +# Changes +# 2025-10-07: +# - Fixed authentication when images might use old MD5 hashes stored in the firmware + + +from __future__ import print_function +import socket +import sys +import os +import argparse +import logging +import hashlib +import random + +# Commands +FLASH = 0 +SPIFFS = 100 +AUTH = 200 + +# Constants +PROGRESS_BAR_LENGTH = 60 + + +# update_progress(): Displays or updates a console progress bar +def update_progress(progress): + if PROGRESS: + status = "" + if isinstance(progress, int): + progress = float(progress) + if not isinstance(progress, float): + progress = 0 + status = "Error: progress var must be float\r\n" + if progress < 0: + progress = 0 + status = "Halt...\r\n" + if progress >= 1: + progress = 1 + status = "Done...\r\n" + block = int(round(PROGRESS_BAR_LENGTH * progress)) + text = "\rUploading: [{0}] {1}% {2}".format( + "=" * block + " " * (PROGRESS_BAR_LENGTH - block), int(progress * 100), status + ) + sys.stderr.write(text) + sys.stderr.flush() + else: + sys.stderr.write(".") + sys.stderr.flush() + + +def send_invitation_and_get_auth_challenge(remote_addr, remote_port, message): + """ + Send invitation to ESP device and get authentication challenge. + Returns (success, auth_data, error_message) tuple. + """ + remote_address = (remote_addr, int(remote_port)) + inv_tries = 0 + data = "" + + msg = "Sending invitation to %s " % remote_addr + sys.stderr.write(msg) + sys.stderr.flush() + + while inv_tries < 10: + inv_tries += 1 + sock2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + try: + sent = sock2.sendto(message.encode(), remote_address) # noqa: F841 + except: # noqa: E722 + sys.stderr.write("failed\n") + sys.stderr.flush() + sock2.close() + return False, None, "Host %s Not Found" % remote_addr + + sock2.settimeout(TIMEOUT) + try: + # Try to read up to 69 bytes for new protocol (SHA256) + # If device sends less (37 bytes), it's using old MD5 protocol + data = sock2.recv(69).decode() + sock2.close() + break + except: # noqa: E722 + sys.stderr.write(".") + sys.stderr.flush() + sock2.close() + + sys.stderr.write("\n") + sys.stderr.flush() + + if inv_tries == 10: + return False, None, "No response from the ESP" + + return True, data, None + + +def authenticate( + remote_addr, remote_port, password, use_md5_password, use_old_protocol, filename, content_size, file_md5, nonce +): + """ + Perform authentication with the ESP device. + + Args: + use_md5_password: If True, hash password with MD5 instead of SHA256 + use_old_protocol: If True, use old MD5 challenge/response protocol (pre-3.3.1) + + Returns (success, error_message) tuple. + """ + cnonce_text = "%s%u%s%s" % (filename, content_size, file_md5, remote_addr) + remote_address = (remote_addr, int(remote_port)) + + if use_old_protocol: + # Generate client nonce (cnonce) + cnonce = hashlib.md5(cnonce_text.encode()).hexdigest() + + # Old MD5 challenge/response protocol (pre-3.3.1) + # 1. Hash the password with MD5 + password_hash = hashlib.md5(password.encode()).hexdigest() + + # 2. Create challenge response + challenge = "%s:%s:%s" % (password_hash, nonce, cnonce) + response = hashlib.md5(challenge.encode()).hexdigest() + expected_response_length = 32 + else: + # Generate client nonce (cnonce) using SHA256 for new protocol + cnonce = hashlib.sha256(cnonce_text.encode()).hexdigest() + + # New PBKDF2-HMAC-SHA256 challenge/response protocol (3.3.1+) + # The password can be hashed with either MD5 or SHA256 + if use_md5_password: + # Use MD5 for password hash (for devices that stored MD5 hashes) + password_hash = hashlib.md5(password.encode()).hexdigest() + else: + # Use SHA256 for password hash (recommended) + password_hash = hashlib.sha256(password.encode()).hexdigest() + + # 2. Derive key using PBKDF2-HMAC-SHA256 with the password hash + salt = nonce + ":" + cnonce + derived_key = hashlib.pbkdf2_hmac("sha256", password_hash.encode(), salt.encode(), 10000) + derived_key_hex = derived_key.hex() + + # 3. Create challenge response + challenge = derived_key_hex + ":" + nonce + ":" + cnonce + response = hashlib.sha256(challenge.encode()).hexdigest() + expected_response_length = 64 + + # Send authentication response + sock2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) + try: + message = "%d %s %s\n" % (AUTH, cnonce, response) + sock2.sendto(message.encode(), remote_address) + sock2.settimeout(10) + try: + data = sock2.recv(expected_response_length).decode() + except: # noqa: E722 + sock2.close() + return False, "No Answer to our Authentication" + + if data != "OK": + sock2.close() + return False, data + + sock2.close() + return True, None + except Exception as e: + sock2.close() + return False, str(e) + + +def serve( # noqa: C901 + remote_addr, local_addr, remote_port, local_port, password, md5_target, filename, command=FLASH +): + # Create a TCP/IP socket + sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM) + server_address = (local_addr, local_port) + logging.info("Starting on %s:%s", str(server_address[0]), str(server_address[1])) + try: + sock.bind(server_address) + sock.listen(1) + except Exception as e: + logging.error("Listen Failed: %s", str(e)) + return 1 + + content_size = os.path.getsize(filename) + with open(filename, "rb") as f: + file_md5 = hashlib.md5(f.read()).hexdigest() + logging.info("Upload size: %d", content_size) + message = "%d %d %d %s\n" % (command, local_port, content_size, file_md5) + + # Send invitation and get authentication challenge + success, data, error = send_invitation_and_get_auth_challenge(remote_addr, remote_port, message) + if not success: + logging.error(error) + return 1 + + if data != "OK": + if data.startswith("AUTH"): + nonce = data.split()[1] + nonce_length = len(nonce) + + # Detect protocol version based on nonce length: + # - 32 chars = Old MD5 protocol (pre-3.3.1) + # - 64 chars = New SHA256 protocol (3.3.1+) + + if nonce_length == 32: + # Scenario 1: Old device (pre-3.3.1) using MD5 protocol + logging.info("Detected old MD5 protocol (pre-3.3.1)") + sys.stderr.write("Authenticating (MD5 protocol)...") + sys.stderr.flush() + auth_success, auth_error = authenticate( + remote_addr, + remote_port, + password, + use_md5_password=True, + use_old_protocol=True, + filename=filename, + content_size=content_size, + file_md5=file_md5, + nonce=nonce, + ) + + if not auth_success: + sys.stderr.write("FAIL\n") + logging.error("Authentication Failed: %s", auth_error) + logging.error("Please check your password and try again") + return 1 + + sys.stderr.write("OK\n") + logging.warning("====================================================================") + logging.warning("WARNING: Device is using old MD5 authentication protocol (pre-3.3.1)") + logging.warning("Please update to ESP32 Arduino Core 3.3.1+ for improved security.") + logging.warning("======================================================================") + + elif nonce_length == 64: + # New protocol (3.3.1+) - try SHA256 password first, then MD5 if it fails + + # Scenario 2: Try SHA256 password hash first (recommended for new devices) + if md5_target: + # User explicitly requested MD5 password hash + logging.info("Using MD5 password hash as requested") + sys.stderr.write("Authenticating (SHA256 protocol with MD5 password)...") + sys.stderr.flush() + auth_success, auth_error = authenticate( + remote_addr, + remote_port, + password, + use_md5_password=True, + use_old_protocol=False, + filename=filename, + content_size=content_size, + file_md5=file_md5, + nonce=nonce, + ) + + if auth_success: + logging.warning("Using insecure MD5 hash for password due to legacy device support") + logging.warning("Please upgrade devices to ESP32 Arduino Core 3.3.1+ for improved security") + else: + # Try SHA256 password hash first + sys.stderr.write("Authenticating (PBKDF2-HMAC-SHA256)...\n") + sys.stderr.flush() + auth_success, auth_error = authenticate( + remote_addr, + remote_port, + password, + use_md5_password=False, + use_old_protocol=False, + filename=filename, + content_size=content_size, + file_md5=file_md5, + nonce=nonce, + ) + + # Scenario 3: If SHA256 fails, try MD5 password hash (for devices with stored MD5 passwords) + if not auth_success: + sys.stderr.write("FAIL\n") + logging.info("SHA256 password failed, trying MD5 password hash") + sys.stderr.write("Retrying with MD5 password...\n") + sys.stderr.flush() + + # Device is back in OTA_IDLE after auth failure, need to send new invitation + success, data, error = send_invitation_and_get_auth_challenge(remote_addr, remote_port, message) + if not success: + sys.stderr.write("FAIL\n") + logging.error("Failed to get new challenge for MD5 retry: %s", error) + return 1 + + if not data.startswith("AUTH"): + sys.stderr.write("FAIL\n") + logging.error("Expected AUTH challenge for MD5 retry, got: %s", data) + return 1 + + # Get new nonce for second attempt + nonce = data.split()[1] + + sys.stderr.write("Authenticating (MD5)...\n") + sys.stderr.flush() + + auth_success, auth_error = authenticate( + remote_addr, + remote_port, + password, + use_md5_password=True, + use_old_protocol=False, + filename=filename, + content_size=content_size, + file_md5=file_md5, + nonce=nonce, + ) + + if auth_success: + logging.warning("====================================================================") + logging.warning("WARNING: Device authenticated with MD5 password hash (deprecated)") + logging.warning("MD5 is cryptographically broken and should not be used.") + logging.warning( + "Please update your sketch to use either setPassword() or setPasswordHash()" + ) + logging.warning( + "with SHA256, then upload again to migrate to the new secure SHA256 protocol." + ) + logging.warning("======================================================================") + + if not auth_success: + sys.stderr.write("FAIL\n") + logging.error("Authentication Failed: %s", auth_error) + logging.error("Please check your password and try again") + return 1 + + sys.stderr.write("OK\n") + else: + logging.error("Invalid nonce length: %d (expected 32 or 64)", nonce_length) + return 1 + else: + logging.error("Bad Answer: %s", data) + return 1 + + logging.info("Waiting for device...") + + try: + sock.settimeout(10) + connection, client_address = sock.accept() + sock.settimeout(None) + connection.settimeout(None) + except: # noqa: E722 + logging.error("No response from device") + sock.close() + return 1 + + try: + with open(filename, "rb") as f: + if PROGRESS: + update_progress(0) + else: + sys.stderr.write("Uploading") + sys.stderr.flush() + offset = 0 + while True: + chunk = f.read(1024) + if not chunk: + break + offset += len(chunk) + update_progress(offset / float(content_size)) + connection.settimeout(10) + try: + connection.sendall(chunk) + res = connection.recv(10) + response_text = res.decode().strip() + last_response_contained_ok = "OK" in response_text + logging.debug("Chunk response: '%s'", response_text) + except Exception as e: + sys.stderr.write("\n") + logging.error("Error Uploading: %s", str(e)) + connection.close() + return 1 + + if last_response_contained_ok: + logging.info("Success") + connection.close() + return 0 + + sys.stderr.write("\n") + logging.info("Waiting for result...") + count = 0 + received_any_response = False + while count < 10: # Increased from 5 to 10 attempts + count += 1 + connection.settimeout(30) # Reduced from 60s to 30s per attempt + try: + data = connection.recv(32).decode().strip() + received_any_response = True + logging.info("Result attempt %d: '%s'", count, data) + + if "OK" in data: + logging.info("Success") + connection.close() + return 0 + elif data: # Got some response but not OK + logging.warning("Unexpected response from device: '%s'", data) + + except socket.timeout: + logging.debug("Timeout waiting for result (attempt %d/10)", count) + continue + except Exception as e: + logging.debug("Error receiving result (attempt %d/10): %s", count, str(e)) + # Don't return error here, continue trying + continue + + # After all attempts, provide detailed error information + if received_any_response: + logging.warning( + "Upload completed but device sent unexpected response(s). This may still be successful." + ) + logging.warning("Device might be rebooting to apply firmware - this is normal.") + connection.close() + return 0 # Consider it successful if we got any response and upload completed + else: + logging.error("No response from device after upload completion") + logging.error("This could indicate device reboot (normal) or network issues") + connection.close() + return 1 + except Exception as e: # noqa: E722 + logging.error("Error: %s", str(e)) + finally: + connection.close() + + sock.close() + return 1 + + +def parse_args(unparsed_args): + parser = argparse.ArgumentParser(description="Transmit image over the air to the ESP32 module with OTA support.") + + # destination ip and port + parser.add_argument("-i", "--ip", dest="esp_ip", action="store", help="ESP32 IP Address.", default=False) + parser.add_argument("-I", "--host_ip", dest="host_ip", action="store", help="Host IP Address.", default="0.0.0.0") + parser.add_argument("-p", "--port", dest="esp_port", type=int, help="ESP32 OTA Port. Default: 3232", default=3232) + parser.add_argument( + "-P", + "--host_port", + dest="host_port", + type=int, + help="Host server OTA Port. Default: random 10000-60000", + default=random.randint(10000, 60000), + ) + + # authentication + parser.add_argument("-a", "--auth", dest="auth", help="Set authentication password.", action="store", default="") + parser.add_argument( + "-m", + "--md5-target", + dest="md5_target", + help=( + "Use MD5 for password hashing (for devices with stored MD5 passwords). " + "By default, SHA256 is tried first, then MD5 as fallback." + ), + action="store_true", + default=False, + ) + + # image + parser.add_argument("-f", "--file", dest="image", help="Image file.", metavar="FILE", default=None) + parser.add_argument( + "-s", + "--spiffs", + dest="spiffs", + action="store_true", + help="Transmit a SPIFFS image and do not flash the module.", + default=False, + ) + + # output + parser.add_argument( + "-d", + "--debug", + dest="debug", + action="store_true", + help="Show debug output. Overrides loglevel with debug.", + default=False, + ) + parser.add_argument( + "-r", + "--progress", + dest="progress", + action="store_true", + help="Show progress output. Does not work for Arduino IDE.", + default=False, + ) + parser.add_argument( + "-t", + "--timeout", + dest="timeout", + type=int, + help="Timeout to wait for the ESP32 to accept invitation.", + default=10, + ) + + return parser.parse_args(unparsed_args) + + +def main(args): + options = parse_args(args) + log_level = logging.WARNING + if options.debug: + log_level = logging.DEBUG + + logging.basicConfig(level=log_level, format="%(asctime)-8s [%(levelname)s]: %(message)s", datefmt="%H:%M:%S") + logging.debug("Options: %s", str(options)) + + # check options + global PROGRESS + PROGRESS = options.progress + + global TIMEOUT + TIMEOUT = options.timeout + + if not options.esp_ip or not options.image: + logging.critical("Not enough arguments.") + return 1 + + command = FLASH + if options.spiffs: + command = SPIFFS + + return serve( + options.esp_ip, + options.host_ip, + options.esp_port, + options.host_port, + options.auth, + options.md5_target, + options.image, + command, + ) + + +if __name__ == "__main__": + sys.exit(main(sys.argv[1:])) diff --git a/tools/gen_esp32part.exe b/tools/gen_esp32part.exe new file mode 100644 index 0000000..2e7b100 Binary files /dev/null and b/tools/gen_esp32part.exe differ diff --git a/tools/gen_esp32part.py b/tools/gen_esp32part.py new file mode 100755 index 0000000..959b318 --- /dev/null +++ b/tools/gen_esp32part.py @@ -0,0 +1,789 @@ +#!/usr/bin/env python +# +# ESP32 partition table generation tool +# +# Converts partition tables to/from CSV and binary formats. +# +# See https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/partition-tables.html +# for explanation of partition table structure and uses. +# +# SPDX-FileCopyrightText: 2016-2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Apache-2.0 +import argparse +import binascii +import errno +import hashlib +import os +import re +import struct +import sys + +MAX_PARTITION_LENGTH = 0xC00 # 3K for partition data (96 entries) leaves 1K in a 4K sector for signature +MD5_PARTITION_BEGIN = b"\xeb\xeb" + b"\xff" * 14 # The first 2 bytes are like magic numbers for MD5 sum +PARTITION_TABLE_SIZE = 0x1000 # Size of partition table + +MIN_PARTITION_SUBTYPE_APP_OTA = 0x10 +NUM_PARTITION_SUBTYPE_APP_OTA = 16 +MIN_PARTITION_SUBTYPE_APP_TEE = 0x30 +NUM_PARTITION_SUBTYPE_APP_TEE = 2 + +SECURE_NONE = None +SECURE_V1 = "v1" +SECURE_V2 = "v2" + +__version__ = "1.5" + +APP_TYPE = 0x00 +DATA_TYPE = 0x01 +BOOTLOADER_TYPE = 0x02 +PARTITION_TABLE_TYPE = 0x03 + +TYPES = { + "bootloader": BOOTLOADER_TYPE, + "partition_table": PARTITION_TABLE_TYPE, + "app": APP_TYPE, + "data": DATA_TYPE, +} + +NVS_RW_MIN_PARTITION_SIZE = 0x3000 + + +def get_ptype_as_int(ptype): + """Convert a string which might be numeric or the name of a partition type to an integer""" + try: + return TYPES[ptype] + except KeyError: + try: + return int(ptype, 0) + except TypeError: + return ptype + + +# Keep this map in sync with esp_partition_subtype_t enum in esp_partition.h +SUBTYPES = { + BOOTLOADER_TYPE: { + "primary": 0x00, + "ota": 0x01, + "recovery": 0x02, + }, + PARTITION_TABLE_TYPE: { + "primary": 0x00, + "ota": 0x01, + }, + APP_TYPE: { + "factory": 0x00, + "test": 0x20, + }, + DATA_TYPE: { + "ota": 0x00, + "phy": 0x01, + "nvs": 0x02, + "coredump": 0x03, + "nvs_keys": 0x04, + "efuse": 0x05, + "undefined": 0x06, + "esphttpd": 0x80, + "fat": 0x81, + "spiffs": 0x82, + "littlefs": 0x83, + "tee_ota": 0x90, + }, +} + + +def get_subtype_as_int(ptype, subtype): + """Convert a string which might be numeric or the name of a partition subtype to an integer""" + try: + return SUBTYPES[get_ptype_as_int(ptype)][subtype] + except KeyError: + try: + return int(subtype, 0) + except TypeError: + return subtype + + +ALIGNMENT = { + APP_TYPE: 0x10000, + DATA_TYPE: 0x1000, + BOOTLOADER_TYPE: 0x1000, + PARTITION_TABLE_TYPE: 0x1000, +} + + +def get_alignment_offset_for_type(ptype): + return ALIGNMENT.get(ptype, ALIGNMENT[DATA_TYPE]) + + +def get_alignment_size_for_type(ptype): + if ptype == APP_TYPE: + if secure == SECURE_V1: + # For secure boot v1 case, app partition must be 64K aligned + # signature block (68 bytes) lies at the very end of 64K block + return 0x10000 + elif secure == SECURE_V2: + # For secure boot v2 case, app partition must be 4K aligned + # signature block (4K) is kept after padding the unsigned image to 64K boundary + return 0x1000 + else: + # For no secure boot enabled case, app partition must be 4K aligned (min. flash erase size) + return 0x1000 + # No specific size alignment requirement as such + return 0x1 + + +def get_partition_type(ptype): + if ptype == "app": + return APP_TYPE + if ptype == "data": + return DATA_TYPE + if ptype == "bootloader": + return BOOTLOADER_TYPE + if ptype == "partition_table": + return PARTITION_TABLE_TYPE + raise InputError("Invalid partition type") + + +def add_extra_subtypes(csv): + for line_no in csv: + try: + fields = [line.strip() for line in line_no.split(",")] + for subtype, subtype_values in SUBTYPES.items(): + if int(fields[2], 16) in subtype_values.values() and subtype == get_partition_type(fields[0]): + raise ValueError("Found duplicate value in partition subtype") + SUBTYPES[TYPES[fields[0]]][fields[1]] = int(fields[2], 16) + except InputError as err: + raise InputError("Error parsing custom subtypes: %s" % err) + + +quiet = False +md5sum = True +secure = SECURE_NONE +offset_part_table = 0 +primary_bootloader_offset = None +recovery_bootloader_offset = None + + +def status(msg): + """Print status message to stderr""" + if not quiet: + critical(msg) + + +def critical(msg): + """Print critical message to stderr""" + sys.stderr.write(msg) + sys.stderr.write("\n") + + +class PartitionTable(list): + def __init__(self): + super(PartitionTable, self).__init__(self) + + @classmethod + def from_file(cls, f): + data = f.read() + data_is_binary = data[0:2] == PartitionDefinition.MAGIC_BYTES + if data_is_binary: + status("Parsing binary partition input...") + return cls.from_binary(data), True + + data = data.decode() + status("Parsing CSV input...") + return cls.from_csv(data), False + + @classmethod + def from_csv(cls, csv_contents): + res = PartitionTable() + lines = csv_contents.splitlines() + + def expand_vars(f): + f = os.path.expandvars(f) + m = re.match(r"(? 1} + + # print sorted duplicate partitions by name + if len(duplicates) != 0: + critical("A list of partitions that have the same name:") + for p in sorted(self, key=lambda x: x.name): + if len(duplicates.intersection([p.name])) != 0: + critical("%s" % (p.to_csv())) + raise InputError("Partition names must be unique") + + # check for overlaps + last = None + for p in sorted(self, key=lambda x: x.offset): + if p.offset < offset_part_table + PARTITION_TABLE_SIZE: + is_primary_bootloader = p.type == BOOTLOADER_TYPE and p.subtype == SUBTYPES[p.type]["primary"] + is_primary_partition_table = p.type == PARTITION_TABLE_TYPE and p.subtype == SUBTYPES[p.type]["primary"] + if not (is_primary_bootloader or is_primary_partition_table): + raise InputError( + "Partition offset 0x%x is below 0x%x" % (p.offset, offset_part_table + PARTITION_TABLE_SIZE) + ) + if last is not None and p.offset < last.offset + last.size: + raise InputError( + "Partition at 0x%x overlaps 0x%x-0x%x" % (p.offset, last.offset, last.offset + last.size - 1) + ) + last = p + + # check that otadata should be unique + otadata_duplicates = [p for p in self if p.type == TYPES["data"] and p.subtype == SUBTYPES[DATA_TYPE]["ota"]] + if len(otadata_duplicates) > 1: + for p in otadata_duplicates: + critical("%s" % (p.to_csv())) + raise InputError( + "Found multiple otadata partitions. Only one partition can be defined with " + 'type="data"(1) and subtype="ota"(0).' + ) + + if len(otadata_duplicates) == 1 and otadata_duplicates[0].size != 0x2000: + p = otadata_duplicates[0] + critical("%s" % (p.to_csv())) + raise InputError("otadata partition must have size = 0x2000") + + # Above checks but for TEE otadata + otadata_duplicates = [ + p for p in self if p.type == TYPES["data"] and p.subtype == SUBTYPES[DATA_TYPE]["tee_ota"] + ] + if len(otadata_duplicates) > 1: + for p in otadata_duplicates: + critical("%s" % (p.to_csv())) + raise InputError( + "Found multiple TEE otadata partitions. Only one partition can be defined with " + 'type="data"(1) and subtype="tee_ota"(0x90).' + ) + + if len(otadata_duplicates) == 1 and otadata_duplicates[0].size != 0x2000: + p = otadata_duplicates[0] + critical("%s" % (p.to_csv())) + raise InputError("TEE otadata partition must have size = 0x2000") + + def flash_size(self): + """Return the size that partitions will occupy in flash + (ie the offset the last partition ends at) + """ + try: + last = sorted(self, reverse=True)[0] + except IndexError: + return 0 # empty table! + return last.offset + last.size + + def verify_size_fits(self, flash_size_bytes: int) -> None: + """Check that partition table fits into the given flash size. + Raises InputError otherwise. + """ + table_size = self.flash_size() + if flash_size_bytes < table_size: + mb = 1024 * 1024 + raise InputError( + "Partitions tables occupies %.1fMB of flash (%d bytes) which does not fit in configured " + "flash size %dMB. Change the flash size in menuconfig under the 'Serial Flasher Config' menu." + % (table_size / mb, table_size, flash_size_bytes / mb) + ) + + @classmethod + def from_binary(cls, b): + md5 = hashlib.md5() + result = cls() + for o in range(0, len(b), 32): + data = b[o : o + 32] + if len(data) != 32: + raise InputError("Partition table length must be a multiple of 32 bytes") + if data == b"\xff" * 32: + return result # got end marker + if md5sum and data[:2] == MD5_PARTITION_BEGIN[:2]: # check only the magic number part + if data[16:] == md5.digest(): + continue # the next iteration will check for the end marker + else: + raise InputError( + "MD5 checksums don't match! (computed: 0x%s, parsed: 0x%s)" + % (md5.hexdigest(), binascii.hexlify(data[16:])) + ) + else: + md5.update(data) + result.append(PartitionDefinition.from_binary(data)) + raise InputError("Partition table is missing an end-of-table marker") + + def to_binary(self): + result = b"".join(e.to_binary() for e in self) + if md5sum: + result += MD5_PARTITION_BEGIN + hashlib.md5(result).digest() + if len(result) >= MAX_PARTITION_LENGTH: + raise InputError("Binary partition table length (%d) longer than max" % len(result)) + result += b"\xff" * (MAX_PARTITION_LENGTH - len(result)) # pad the sector, for signing + return result + + def to_csv(self, simple_formatting=False): + rows = ["# ESP-IDF Partition Table", "# Name, Type, SubType, Offset, Size, Flags"] + rows += [x.to_csv(simple_formatting) for x in self] + return "\n".join(rows) + "\n" + + +class PartitionDefinition(object): + MAGIC_BYTES = b"\xaa\x50" + + # dictionary maps flag name (as used in CSV flags list, property name) + # to bit set in flags words in binary format + FLAGS = {"encrypted": 0, "readonly": 1} + + # add subtypes for the 16 OTA slot values ("ota_XX, etc.") + for ota_slot in range(NUM_PARTITION_SUBTYPE_APP_OTA): + SUBTYPES[TYPES["app"]]["ota_%d" % ota_slot] = MIN_PARTITION_SUBTYPE_APP_OTA + ota_slot + + # add subtypes for the 2 TEE OTA slot values ("tee_XX, etc.") + for tee_slot in range(NUM_PARTITION_SUBTYPE_APP_TEE): + SUBTYPES[TYPES["app"]]["tee_%d" % tee_slot] = MIN_PARTITION_SUBTYPE_APP_TEE + tee_slot + + def __init__(self): + self.name = "" + self.type = None + self.subtype = None + self.offset = None + self.size = None + self.encrypted = False + self.readonly = False + + @classmethod + def from_csv(cls, line, line_no): + """Parse a line from the CSV""" + line_w_defaults = line + ",,,," # lazy way to support default fields + fields = [f.strip() for f in line_w_defaults.split(",")] + + res = PartitionDefinition() + res.line_no = line_no + res.name = fields[0] + res.type = res.parse_type(fields[1]) + res.subtype = res.parse_subtype(fields[2]) + res.offset = res.parse_address(fields[3], res.type, res.subtype) + res.size = res.parse_size(fields[4], res.type) + if res.size is None: + raise InputError("Size field can't be empty") + + flags = fields[5].split(":") + for flag in flags: + if flag in cls.FLAGS: + setattr(res, flag, True) + elif len(flag) > 0: + raise InputError("CSV flag column contains unknown flag '%s'" % (flag)) + + return res + + def __eq__(self, other): + return ( + self.name == other.name + and self.type == other.type + and self.subtype == other.subtype + and self.offset == other.offset + and self.size == other.size + ) + + def __repr__(self): + def maybe_hex(x): + return "0x%x" % x if x is not None else "None" + + return "PartitionDefinition('%s', 0x%x, 0x%x, %s, %s)" % ( + self.name, + self.type, + self.subtype or 0, + maybe_hex(self.offset), + maybe_hex(self.size), + ) + + def __str__(self): + return "Part '%s' %d/%d @ 0x%x size 0x%x" % ( + self.name, + self.type, + self.subtype, + self.offset or -1, + self.size or -1, + ) + + def __cmp__(self, other): + return self.offset - other.offset + + def __lt__(self, other): + return self.offset < other.offset + + def __gt__(self, other): + return self.offset > other.offset + + def __le__(self, other): + return self.offset <= other.offset + + def __ge__(self, other): + return self.offset >= other.offset + + def parse_type(self, strval): + if strval == "": + raise InputError("Field 'type' can't be left empty.") + return parse_int(strval, TYPES) + + def parse_subtype(self, strval): + if strval == "": + if self.type == TYPES["app"]: + raise InputError("App partition cannot have an empty subtype") + return SUBTYPES[DATA_TYPE]["undefined"] + return parse_int(strval, SUBTYPES.get(self.type, {})) + + def parse_size(self, strval, ptype): + if ptype == BOOTLOADER_TYPE: + if primary_bootloader_offset is None: + raise InputError("Primary bootloader offset is not defined. Please use --primary-bootloader-offset") + return offset_part_table - primary_bootloader_offset + if ptype == PARTITION_TABLE_TYPE: + return PARTITION_TABLE_SIZE + if strval == "": + return None # PartitionTable will fill in default + return parse_int(strval) + + def parse_address(self, strval, ptype, psubtype): + if ptype == BOOTLOADER_TYPE: + if psubtype == SUBTYPES[ptype]["primary"]: + if primary_bootloader_offset is None: + raise InputError("Primary bootloader offset is not defined. Please use --primary-bootloader-offset") + return primary_bootloader_offset + if psubtype == SUBTYPES[ptype]["recovery"]: + if recovery_bootloader_offset is None: + raise InputError( + "Recovery bootloader offset is not defined. Please use --recovery-bootloader-offset" + ) + return recovery_bootloader_offset + if ptype == PARTITION_TABLE_TYPE and psubtype == SUBTYPES[ptype]["primary"]: + return offset_part_table + if strval == "": + return None # PartitionTable will fill in default + return parse_int(strval) + + def verify(self): + if self.type is None: + raise ValidationError(self, "Type field is not set") + if self.subtype is None: + raise ValidationError(self, "Subtype field is not set") + if self.offset is None: + raise ValidationError(self, "Offset field is not set") + if self.size is None: + raise ValidationError(self, "Size field is not set") + offset_align = get_alignment_offset_for_type(self.type) + if self.offset % offset_align: + raise ValidationError(self, "Offset 0x%x is not aligned to 0x%x" % (self.offset, offset_align)) + if self.type == APP_TYPE: + size_align = get_alignment_size_for_type(self.type) + if self.size % size_align: + raise ValidationError(self, "Size 0x%x is not aligned to 0x%x" % (self.size, size_align)) + + if self.name in TYPES and TYPES.get(self.name, "") != self.type: + critical( + "WARNING: Partition has name '%s' which is a partition type, but does not match this partition's " + "type (0x%x). Mistake in partition table?" % (self.name, self.type) + ) + all_subtype_names = [] + for names in (t.keys() for t in SUBTYPES.values()): + all_subtype_names += names + if self.name in all_subtype_names and SUBTYPES.get(self.type, {}).get(self.name, "") != self.subtype: + critical( + "WARNING: Partition has name '%s' which is a partition subtype, but this partition has " + "non-matching type 0x%x and subtype 0x%x. Mistake in partition table?" + % (self.name, self.type, self.subtype) + ) + + always_rw_data_subtypes = [SUBTYPES[DATA_TYPE]["ota"], SUBTYPES[DATA_TYPE]["coredump"]] + if self.type == TYPES["data"] and self.subtype in always_rw_data_subtypes and self.readonly is True: + raise ValidationError( + self, + "'%s' partition of type %s and subtype %s is always read-write and cannot be read-only" + % (self.name, self.type, self.subtype), + ) + + if self.type == TYPES["data"] and self.subtype == SUBTYPES[DATA_TYPE]["nvs"]: + if self.size < NVS_RW_MIN_PARTITION_SIZE and self.readonly is False: + raise ValidationError( + self, + """'%s' partition of type %s and subtype %s of this size (0x%x) must be flagged as 'readonly' \ +(the size of read/write NVS has to be at least 0x%x)""" + % (self.name, self.type, self.subtype, self.size, NVS_RW_MIN_PARTITION_SIZE), + ) + + STRUCT_FORMAT = b"<2sBBLL16sL" + + @classmethod + def from_binary(cls, b): + if len(b) != 32: + raise InputError("Partition definition length must be exactly 32 bytes. Got %d bytes." % len(b)) + res = cls() + (magic, res.type, res.subtype, res.offset, res.size, res.name, flags) = struct.unpack(cls.STRUCT_FORMAT, b) + if b"\x00" in res.name: # strip null byte padding from name string + res.name = res.name[: res.name.index(b"\x00")] + res.name = res.name.decode() + if magic != cls.MAGIC_BYTES: + raise InputError("Invalid magic bytes (%r) for partition definition" % magic) + for flag, bit in cls.FLAGS.items(): + if flags & (1 << bit): + setattr(res, flag, True) + flags &= ~(1 << bit) + if flags != 0: + critical("WARNING: Partition definition had unknown flag(s) 0x%08x. Newer binary format?" % flags) + return res + + def get_flags_list(self): + return [flag for flag in self.FLAGS.keys() if getattr(self, flag)] + + def to_binary(self): + flags = sum((1 << self.FLAGS[flag]) for flag in self.get_flags_list()) + return struct.pack( + self.STRUCT_FORMAT, + self.MAGIC_BYTES, + self.type, + self.subtype, + self.offset, + self.size, + self.name.encode(), + flags, + ) + + def to_csv(self, simple_formatting=False): + def addr_format(a, include_sizes): + if not simple_formatting and include_sizes: + for val, suffix in [(0x100000, "M"), (0x400, "K")]: + if a % val == 0: + return "%d%s" % (a // val, suffix) + return "0x%x" % a + + def lookup_keyword(t, keywords): + for k, v in keywords.items(): + if simple_formatting is False and t == v: + return k + return "%d" % t + + def generate_text_flags(): + """colon-delimited list of flags""" + return ":".join(self.get_flags_list()) + + return ",".join( + [ + self.name, + lookup_keyword(self.type, TYPES), + lookup_keyword(self.subtype, SUBTYPES.get(self.type, {})), + addr_format(self.offset, False), + addr_format(self.size, True), + generate_text_flags(), + ] + ) + + +def parse_int(v, keywords={}): + """Generic parser for integer fields - int(x,0) with provision for + k/m/K/M suffixes and 'keyword' value lookup. + """ + try: + for letter, multiplier in [("k", 1024), ("m", 1024 * 1024)]: + if v.lower().endswith(letter): + return parse_int(v[:-1], keywords) * multiplier + return int(v, 0) + except ValueError: + if len(keywords) == 0: + raise InputError("Invalid field value %s" % v) + try: + return keywords[v.lower()] + except KeyError: + raise InputError("Value '%s' is not valid. Known keywords: %s" % (v, ", ".join(keywords))) + + +def main(): + global quiet + global md5sum + global offset_part_table + global secure + global primary_bootloader_offset + global recovery_bootloader_offset + parser = argparse.ArgumentParser(description="ESP32 partition table utility") + + parser.add_argument( + "--flash-size", + help="Optional flash size limit, checks partition table fits in flash", + nargs="?", + choices=["1MB", "2MB", "4MB", "8MB", "16MB", "32MB", "64MB", "128MB"], + ) + parser.add_argument( + "--disable-md5sum", help="Disable md5 checksum for the partition table", default=False, action="store_true" + ) + parser.add_argument("--no-verify", help="Don't verify partition table fields", action="store_true") + parser.add_argument( + "--verify", + "-v", + help="Verify partition table fields (deprecated, this behavior is " + "enabled by default and this flag does nothing.", + action="store_true", + ) + parser.add_argument("--quiet", "-q", help="Don't print non-critical status messages to stderr", action="store_true") + parser.add_argument("--offset", "-o", help="Set offset partition table", default="0x8000") + parser.add_argument("--primary-bootloader-offset", help="Set primary bootloader offset", default=None) + parser.add_argument("--recovery-bootloader-offset", help="Set recovery bootloader offset", default=None) + parser.add_argument( + "--secure", + help="Require app partitions to be suitable for secure boot", + nargs="?", + const=SECURE_V1, + choices=[SECURE_V1, SECURE_V2], + ) + parser.add_argument("--extra-partition-subtypes", help="Extra partition subtype entries", nargs="*") + parser.add_argument("input", help="Path to CSV or binary file to parse.", type=argparse.FileType("rb")) + parser.add_argument( + "output", + help="Path to output converted binary or CSV file. Will use stdout if omitted.", + nargs="?", + default="-", + ) + + args = parser.parse_args() + + quiet = args.quiet + md5sum = not args.disable_md5sum + secure = args.secure + offset_part_table = int(args.offset, 0) + if args.primary_bootloader_offset is not None: + primary_bootloader_offset = int(args.primary_bootloader_offset, 0) + if primary_bootloader_offset >= offset_part_table: + raise InputError( + f"Unsupported configuration. Primary bootloader must be below partition table. " + f"Check --primary-bootloader-offset={primary_bootloader_offset:#x} and --offset={offset_part_table:#x}" + ) + if args.recovery_bootloader_offset is not None: + recovery_bootloader_offset = int(args.recovery_bootloader_offset, 0) + if args.extra_partition_subtypes: + add_extra_subtypes(args.extra_partition_subtypes) + + table, input_is_binary = PartitionTable.from_file(args.input) + + if not args.no_verify: + status("Verifying table...") + table.verify() + + if args.flash_size: + size_mb = int(args.flash_size.replace("MB", "")) + table.verify_size_fits(size_mb * 1024 * 1024) + + # Make sure that the output directory is created + output_dir = os.path.abspath(os.path.dirname(args.output)) + + if not os.path.exists(output_dir): + try: + os.makedirs(output_dir) + except OSError as exc: + if exc.errno != errno.EEXIST: + raise + + if input_is_binary: + output = table.to_csv() + with sys.stdout if args.output == "-" else open(args.output, "w", encoding="utf-8") as f: + f.write(output) + else: + output = table.to_binary() + try: + stdout_binary = sys.stdout.buffer # Python 3 + except AttributeError: + stdout_binary = sys.stdout + with stdout_binary if args.output == "-" else open(args.output, "wb") as f: + f.write(output) + + +class InputError(RuntimeError): + def __init__(self, e): + super(InputError, self).__init__(e) + + +class ValidationError(InputError): + def __init__(self, partition, message): + super(ValidationError, self).__init__("Partition %s invalid: %s" % (partition.name, message)) + + +if __name__ == "__main__": + try: + main() + except InputError as e: + print(e, file=sys.stderr) + sys.exit(2) diff --git a/tools/gen_insights_package.exe b/tools/gen_insights_package.exe new file mode 100755 index 0000000..444f345 Binary files /dev/null and b/tools/gen_insights_package.exe differ diff --git a/tools/gen_insights_package.py b/tools/gen_insights_package.py new file mode 100644 index 0000000..c9e2765 --- /dev/null +++ b/tools/gen_insights_package.py @@ -0,0 +1,53 @@ +import os +import sys +import shutil +import json + +APP_HEADER_SIZE = 32 +VERSION_NAME_OFFSET = APP_HEADER_SIZE + 16 +VERSION_NAME_SIZE = 32 +PROJECT_NAME_OFFSET = VERSION_NAME_OFFSET + VERSION_NAME_SIZE +PROJECT_NAME_SIZE = 32 + +# Input path of temporary build directory created by Arduino +BUILD_DIR = sys.argv[1] +# Input project name +PROJ_NAME = sys.argv[2] +# Input path to create output package +TARGET_PATH = sys.argv[3] + + +def main(): + print("Creating ESP Insights Firmware Package.") + archive_path = os.path.join(BUILD_DIR, PROJ_NAME) + out_path = os.path.join(TARGET_PATH, PROJ_NAME) + + # Create target archive directories + os.makedirs(archive_path, exist_ok=True) + os.makedirs(os.path.join(archive_path, "partition_table"), exist_ok=True) + os.makedirs(os.path.join(archive_path, "bootloader"), exist_ok=True) + + # Copy files from build directory to archive directory + shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".bin"), archive_path) + shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".elf"), archive_path) + shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".map"), archive_path) + shutil.copy2(os.path.join(BUILD_DIR, "partitions.csv"), archive_path) + shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".bootloader.bin"), os.path.join(archive_path, "bootloader")) + shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".partitions.bin"), os.path.join(archive_path, "partition_table")) + + with open(os.path.join(BUILD_DIR, PROJ_NAME + ".bin"), "rb") as bin_file: + bin_file.seek(VERSION_NAME_OFFSET) + version_name = (bin_file.read(VERSION_NAME_SIZE).decode("utf-8")).split("\x00", 1)[0] + bin_file.seek(PROJECT_NAME_OFFSET) + project_name = (bin_file.read(PROJECT_NAME_SIZE).decode("utf-8")).split("\x00", 1)[0] + project_build_config_obj = {"project": {"name": project_name, "version": version_name}} + with open(os.path.join(archive_path, "project_build_config.json"), "w") as json_file: + json_file.write(json.dumps(project_build_config_obj)) + + shutil.make_archive(out_path, "zip", BUILD_DIR, PROJ_NAME) + print("Archive created at {}".format(out_path + ".zip")) + return + + +if __name__ == "__main__": + main() diff --git a/tools/ide-debug/svd/esp32.svd b/tools/ide-debug/svd/esp32.svd new file mode 100644 index 0000000..7e895e4 --- /dev/null +++ b/tools/ide-debug/svd/esp32.svd @@ -0,0 +1,46087 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32 + ESP32 + 8 + 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Xtensa LX6 + r0p0 + little + false + true + 3 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x3FF01000 + + 0x0 + 0x40 + registers + + + + START + 0x0 + 0x20 + + + START + Write 1 to start the AES operation. + 0 + 1 + write-only + + + + + IDLE + 0x4 + 0x20 + + + IDLE + AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’ otherwise. + 0 + 1 + read-only + + + + + MODE + 0x8 + 0x20 + + + MODE + Selects the AES accelerator mode of operation. See Table 22-1 for details. + 0 + 8 + read-write + + + + + 8 + 0x4 + KEY_%s + 0x10 + 0x20 + + + KEY + AES key material register. + 0 + 8 + read-write + + + + + 4 + 0x4 + TEXT_%s + 0x30 + 0x20 + + + TEXT + Plaintext and ciphertext register. + 0 + 8 + read-write + + + + + ENDIAN + 0x40 + 0x20 + + + ENDIAN + Endianness selection register. See Table 22-2 for details. + 0 + 2 + read-write + + + + + + + APB_CTRL + Advanced Peripheral Bus Controller + APB_CTRL + 0x3FF66000 + + 0x0 + 0x44 + registers + + + + SYSCLK_CONF + 0x0 + 0x20 + 0x00002000 + + + PRE_DIV_CNT + 0 + 10 + read-write + + + CLK_320M_EN + 10 + 1 + read-write + + + CLK_EN + 11 + 1 + read-write + + + RST_TICK_CNT + 12 + 1 + read-write + + + QUICK_CLK_CHNG + 13 + 1 + read-write + + + + + XTAL_TICK_CONF + 0x4 + 0x20 + 0x00000027 + + + XTAL_TICK_NUM + 0 + 8 + read-write + + + + + PLL_TICK_CONF + 0x8 + 0x20 + 0x0000004F + + + PLL_TICK_NUM + 0 + 8 + read-write + + + + + CK8M_TICK_CONF + 0xC + 0x20 + 0x0000000B + + + CK8M_TICK_NUM + 0 + 8 + read-write + + + + + APB_SARADC_CTRL + 0x10 + 0x20 + 0x007F8240 + + + SARADC_START_FORCE + 0 + 1 + read-write + + + SARADC_START + 1 + 1 + read-write + + + SARADC_SAR2_MUX + 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL + 2 + 1 + read-write + + + SARADC_WORK_MODE + 0: single mode 1: double mode 2: alternate mode + 3 + 2 + read-write + + + SARADC_SAR_SEL + 0: SAR1 1: SAR2 only work for single SAR mode + 5 + 1 + read-write + + + SARADC_SAR_CLK_GATED + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 4 + read-write + + + SARADC_SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 19 + 4 + read-write + + + SARADC_SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 24 + 1 + read-write + + + SARADC_DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits. + 25 + 1 + read-write + + + SARADC_DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix + 26 + 1 + read-write + + + + + APB_SARADC_CTRL2 + 0x14 + 0x20 + 0x000001FE + + + SARADC_MEAS_NUM_LIMIT + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted otherwise not + 10 + 1 + read-write + + + + + APB_SARADC_FSM + 0x18 + 0x20 + 0x0208FF08 + + + SARADC_RSTB_WAIT + 0 + 8 + read-write + + + SARADC_STANDBY_WAIT + 8 + 8 + read-write + + + SARADC_START_WAIT + 16 + 8 + read-write + + + SARADC_SAMPLE_CYCLE + sample cycles + 24 + 8 + read-write + + + + + APB_SARADC_SAR1_PATT_TAB1 + 0x1C + 0x20 + 0x0F0F0F0F + + + SARADC_SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR1_PATT_TAB2 + 0x20 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR1_PATT_TAB3 + 0x24 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR1_PATT_TAB4 + 0x28 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR2_PATT_TAB1 + 0x2C + 0x20 + 0x0F0F0F0F + + + SARADC_SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR2_PATT_TAB2 + 0x30 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR2_PATT_TAB3 + 0x34 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + APB_SARADC_SAR2_PATT_TAB4 + 0x38 + 0x20 + 0x0F0F0F0F + + + SARADC_SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + APLL_TICK_CONF + 0x3C + 0x20 + 0x00000063 + + + APLL_TICK_NUM + 0 + 8 + read-write + + + + + DATE + 0x7C + 0x20 + 0x16042000 + + + DATE + 0 + 32 + read-write + + + + + + + BB + Peripheral BB + BB + 0x3FF5D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + + + DPORT + Peripheral DPORT + DPORT + 0x3FF00000 + + 0x0 + 0x5C0 + registers + + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_BB + 2 + + + BT_MAC + 3 + + + BT_BB + 4 + + + BT_BB_NMI + 5 + + + RWBT + 6 + + + RWBLE + 7 + + + RWBT_NMI + 8 + + + RWBLE_NMI + 9 + + + + PRO_BOOT_REMAP_CTRL + 0x0 + 0x20 + + + PRO_BOOT_REMAP + 0 + 1 + read-write + + + + + APP_BOOT_REMAP_CTRL + 0x4 + 0x20 + + + APP_BOOT_REMAP + 0 + 1 + read-write + + + + + ACCESS_CHECK + 0x8 + 0x20 + + + PRO + 0 + 1 + read-only + + + APP + 8 + 1 + read-only + + + + + PRO_DPORT_APB_MASK0 + 0xC + 0x20 + + + PRODPORT_APB_MASK0 + 0 + 32 + read-write + + + + + PRO_DPORT_APB_MASK1 + 0x10 + 0x20 + + + PRODPORT_APB_MASK1 + 0 + 32 + read-write + + + + + APP_DPORT_APB_MASK0 + 0x14 + 0x20 + + + APPDPORT_APB_MASK0 + 0 + 32 + read-write + + + + + APP_DPORT_APB_MASK1 + 0x18 + 0x20 + + + APPDPORT_APB_MASK1 + 0 + 32 + read-write + + + + + PERI_CLK_EN + 0x1C + 0x20 + + + PERI_CLK_EN + 0 + 32 + read-write + + + + + PERI_RST_EN + 0x20 + 0x20 + + + PERI_RST_EN + 0 + 32 + read-write + + + + + WIFI_BB_CFG + 0x24 + 0x20 + + + WIFI_BB_CFG + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + 0x28 + 0x20 + + + WIFI_BB_CFG_2 + 0 + 32 + read-write + + + + + APPCPU_CTRL_A + 0x2C + 0x20 + 0x00000001 + + + APPCPU_RESETTING + 0 + 1 + read-write + + + + + APPCPU_CTRL_B + 0x30 + 0x20 + + + APPCPU_CLKGATE_EN + 0 + 1 + read-write + + + + + APPCPU_CTRL_C + 0x34 + 0x20 + + + APPCPU_RUNSTALL + 0 + 1 + read-write + + + + + APPCPU_CTRL_D + 0x38 + 0x20 + + + APPCPU_BOOT_ADDR + 0 + 32 + read-write + + + + + CPU_PER_CONF + 0x3C + 0x20 + + + CPUPERIOD_SEL + 0 + 2 + read-write + + + LOWSPEED_CLK_SEL + 2 + 1 + read-write + + + FAST_CLK_RTC_SEL + 3 + 1 + read-write + + + + + PRO_CACHE_CTRL + 0x40 + 0x20 + 0x00000010 + + + PRO_CACHE_MODE + 2 + 1 + read-write + + + PRO_CACHE_ENABLE + 3 + 1 + read-write + + + PRO_CACHE_FLUSH_ENA + 4 + 1 + read-write + + + PRO_CACHE_FLUSH_DONE + 5 + 1 + read-only + + + PRO_CACHE_LOCK_0_EN + 6 + 1 + read-write + + + PRO_CACHE_LOCK_1_EN + 7 + 1 + read-write + + + PRO_CACHE_LOCK_2_EN + 8 + 1 + read-write + + + PRO_CACHE_LOCK_3_EN + 9 + 1 + read-write + + + PRO_SINGLE_IRAM_ENA + 10 + 1 + read-write + + + PRO_DRAM_SPLIT + 11 + 1 + read-write + + + PRO_AHB_SPI_REQ + 12 + 1 + read-only + + + PRO_SLAVE_REQ + 13 + 1 + read-only + + + AHB_SPI_REQ + 14 + 1 + read-only + + + SLAVE_REQ + 15 + 1 + read-only + + + PRO_DRAM_HL + 16 + 1 + read-write + + + + + PRO_CACHE_CTRL1 + 0x44 + 0x20 + 0x000008FF + + + PRO_CACHE_MASK_IRAM0 + 0 + 1 + read-write + + + PRO_CACHE_MASK_IRAM1 + 1 + 1 + read-write + + + PRO_CACHE_MASK_IROM0 + 2 + 1 + read-write + + + PRO_CACHE_MASK_DRAM1 + 3 + 1 + read-write + + + PRO_CACHE_MASK_DROM0 + 4 + 1 + read-write + + + PRO_CACHE_MASK_OPSDRAM + 5 + 1 + read-write + + + PRO_CMMU_SRAM_PAGE_MODE + 6 + 3 + read-write + + + PRO_CMMU_FLASH_PAGE_MODE + 9 + 2 + read-write + + + PRO_CMMU_FORCE_ON + 11 + 1 + read-write + + + PRO_CMMU_PD + 12 + 1 + read-write + + + PRO_CACHE_MMU_IA_CLR + 13 + 1 + read-write + + + + + PRO_CACHE_LOCK_0_ADDR + 0x48 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + PRO_CACHE_LOCK_1_ADDR + 0x4C + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + PRO_CACHE_LOCK_2_ADDR + 0x50 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + PRO_CACHE_LOCK_3_ADDR + 0x54 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + APP_CACHE_CTRL + 0x58 + 0x20 + 0x00000010 + + + APP_CACHE_MODE + 2 + 1 + read-write + + + APP_CACHE_ENABLE + 3 + 1 + read-write + + + APP_CACHE_FLUSH_ENA + 4 + 1 + read-write + + + APP_CACHE_FLUSH_DONE + 5 + 1 + read-only + + + APP_CACHE_LOCK_0_EN + 6 + 1 + read-write + + + APP_CACHE_LOCK_1_EN + 7 + 1 + read-write + + + APP_CACHE_LOCK_2_EN + 8 + 1 + read-write + + + APP_CACHE_LOCK_3_EN + 9 + 1 + read-write + + + APP_SINGLE_IRAM_ENA + 10 + 1 + read-write + + + APP_DRAM_SPLIT + 11 + 1 + read-write + + + APP_AHB_SPI_REQ + 12 + 1 + read-only + + + APP_SLAVE_REQ + 13 + 1 + read-only + + + APP_DRAM_HL + 14 + 1 + read-write + + + + + APP_CACHE_CTRL1 + 0x5C + 0x20 + 0x000008FF + + + APP_CACHE_MASK_IRAM0 + 0 + 1 + read-write + + + APP_CACHE_MASK_IRAM1 + 1 + 1 + read-write + + + APP_CACHE_MASK_IROM0 + 2 + 1 + read-write + + + APP_CACHE_MASK_DRAM1 + 3 + 1 + read-write + + + APP_CACHE_MASK_DROM0 + 4 + 1 + read-write + + + APP_CACHE_MASK_OPSDRAM + 5 + 1 + read-write + + + APP_CMMU_SRAM_PAGE_MODE + 6 + 3 + read-write + + + APP_CMMU_FLASH_PAGE_MODE + 9 + 2 + read-write + + + APP_CMMU_FORCE_ON + 11 + 1 + read-write + + + APP_CMMU_PD + 12 + 1 + read-write + + + APP_CACHE_MMU_IA_CLR + 13 + 1 + read-write + + + + + APP_CACHE_LOCK_0_ADDR + 0x60 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + APP_CACHE_LOCK_1_ADDR + 0x64 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + APP_CACHE_LOCK_2_ADDR + 0x68 + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + APP_CACHE_LOCK_3_ADDR + 0x6C + 0x20 + + + PRE + 0 + 14 + read-write + + + MIN + 14 + 4 + read-write + + + MAX + 18 + 4 + read-write + + + + + TRACEMEM_MUX_MODE + 0x70 + 0x20 + + + TRACEMEM_MUX_MODE + 0 + 2 + read-write + + + + + PRO_TRACEMEM_ENA + 0x74 + 0x20 + + + PRO_TRACEMEM_ENA + 0 + 1 + read-write + + + + + APP_TRACEMEM_ENA + 0x78 + 0x20 + + + APP_TRACEMEM_ENA + 0 + 1 + read-write + + + + + CACHE_MUX_MODE + 0x7C + 0x20 + + + CACHE_MUX_MODE + 0 + 2 + read-write + + + + + IMMU_PAGE_MODE + 0x80 + 0x20 + + + INTERNAL_SRAM_IMMU_ENA + 0 + 1 + read-write + + + IMMU_PAGE_MODE + 1 + 2 + read-write + + + + + DMMU_PAGE_MODE + 0x84 + 0x20 + + + INTERNAL_SRAM_DMMU_ENA + 0 + 1 + read-write + + + DMMU_PAGE_MODE + 1 + 2 + read-write + + + + + ROM_MPU_ENA + 0x88 + 0x20 + + + SHARE_ROM_MPU_ENA + 0 + 1 + read-write + + + PRO_ROM_MPU_ENA + 1 + 1 + read-write + + + APP_ROM_MPU_ENA + 2 + 1 + read-write + + + + + MEM_PD_MASK + 0x8C + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + 0 + 1 + read-write + + + + + ROM_PD_CTRL + 0x90 + 0x20 + + + PRO_ROM_PD + 0 + 1 + read-write + + + APP_ROM_PD + 1 + 1 + read-write + + + SHARE_ROM_PD + 2 + 6 + read-write + + + + + ROM_FO_CTRL + 0x94 + 0x20 + 0x00000003 + + + PRO_ROM_FO + 0 + 1 + read-write + + + APP_ROM_FO + 1 + 1 + read-write + + + SHARE_ROM_FO + 2 + 6 + read-write + + + + + SRAM_PD_CTRL_0 + 0x98 + 0x20 + + + SRAM_PD_0 + 0 + 32 + read-write + + + + + SRAM_PD_CTRL_1 + 0x9C + 0x20 + + + SRAM_PD_1 + 0 + 1 + read-write + + + + + SRAM_FO_CTRL_0 + 0xA0 + 0x20 + 0xFFFFFFFF + + + SRAM_FO_0 + 0 + 32 + read-write + + + + + SRAM_FO_CTRL_1 + 0xA4 + 0x20 + 0x00000001 + + + SRAM_FO_1 + 0 + 1 + read-write + + + + + IRAM_DRAM_AHB_SEL + 0xA8 + 0x20 + + + MASK_PRO_IRAM + 0 + 1 + read-write + + + MASK_APP_IRAM + 1 + 1 + read-write + + + MASK_PRO_DRAM + 2 + 1 + read-write + + + MASK_APP_DRAM + 3 + 1 + read-write + + + MASK_AHB + 4 + 1 + read-write + + + MAC_DUMP_MODE + 5 + 2 + read-write + + + + + TAG_FO_CTRL + 0xAC + 0x20 + 0x00000101 + + + PRO_CACHE_TAG_FORCE_ON + 0 + 1 + read-write + + + PRO_CACHE_TAG_PD + 1 + 1 + read-write + + + APP_CACHE_TAG_FORCE_ON + 8 + 1 + read-write + + + APP_CACHE_TAG_PD + 9 + 1 + read-write + + + + + AHB_LITE_MASK + 0xB0 + 0x20 + + + PRO + 0 + 1 + read-write + + + APP + 4 + 1 + read-write + + + SDIO + 8 + 1 + read-write + + + PRODPORT + 9 + 1 + read-write + + + APPDPORT + 10 + 1 + read-write + + + AHB_LITE_SDHOST_PID + 11 + 3 + read-write + + + + + AHB_MPU_TABLE_0 + 0xB4 + 0x20 + 0xFFFFFFFF + + + AHB_ACCESS_GRANT_0 + 0 + 32 + read-write + + + + + AHB_MPU_TABLE_1 + 0xB8 + 0x20 + 0x000001FF + + + AHB_ACCESS_GRANT_1 + 0 + 9 + read-write + + + + + HOST_INF_SEL + 0xBC + 0x20 + + + PERI_IO_SWAP + 0 + 8 + read-write + + + LINK_DEVICE_SEL + 8 + 8 + read-write + + + + + PERIP_CLK_EN + 0xC0 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + 0 + 1 + read-write + + + SPI01_CLK_EN + 1 + 1 + read-write + + + UART_CLK_EN + 2 + 1 + read-write + + + WDG_CLK_EN + 3 + 1 + read-write + + + I2S0_CLK_EN + 4 + 1 + read-write + + + UART1_CLK_EN + 5 + 1 + read-write + + + SPI2_CLK_EN + 6 + 1 + read-write + + + I2C0_EXT0_CLK_EN + 7 + 1 + read-write + + + UHCI0_CLK_EN + 8 + 1 + read-write + + + RMT_CLK_EN + 9 + 1 + read-write + + + PCNT_CLK_EN + 10 + 1 + read-write + + + LEDC_CLK_EN + 11 + 1 + read-write + + + UHCI1_CLK_EN + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + 13 + 1 + read-write + + + EFUSE_CLK_EN + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + 15 + 1 + read-write + + + SPI3_CLK_EN + 16 + 1 + read-write + + + PWM0_CLK_EN + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + 18 + 1 + read-write + + + TWAI_CLK_EN + 19 + 1 + read-write + + + PWM1_CLK_EN + 20 + 1 + read-write + + + I2S1_CLK_EN + 21 + 1 + read-write + + + SPI_DMA_CLK_EN + 22 + 1 + read-write + + + UART2_CLK_EN + 23 + 1 + read-write + + + UART_MEM_CLK_EN + 24 + 1 + read-write + + + PWM2_CLK_EN + 25 + 1 + read-write + + + PWM3_CLK_EN + 26 + 1 + read-write + + + + + PERIP_RST_EN + 0xC4 + 0x20 + + + TIMERS_RST + 0 + 1 + read-write + + + SPI01_RST + 1 + 1 + read-write + + + UART_RST + 2 + 1 + read-write + + + WDG_RST + 3 + 1 + read-write + + + I2S0_RST + 4 + 1 + read-write + + + UART1_RST + 5 + 1 + read-write + + + SPI2_RST + 6 + 1 + read-write + + + I2C0_EXT0_RST + 7 + 1 + read-write + + + UHCI0_RST + 8 + 1 + read-write + + + RMT_RST + 9 + 1 + read-write + + + PCNT_RST + 10 + 1 + read-write + + + LEDC_RST + 11 + 1 + read-write + + + UHCI1_RST + 12 + 1 + read-write + + + TIMERGROUP_RST + 13 + 1 + read-write + + + EFUSE_RST + 14 + 1 + read-write + + + TIMERGROUP1_RST + 15 + 1 + read-write + + + SPI3_RST + 16 + 1 + read-write + + + PWM0_RST + 17 + 1 + read-write + + + I2C_EXT1_RST + 18 + 1 + read-write + + + TWAI_RST + 19 + 1 + read-write + + + PWM1_RST + 20 + 1 + read-write + + + I2S1_RST + 21 + 1 + read-write + + + SPI_DMA_RST + 22 + 1 + read-write + + + UART2_RST + 23 + 1 + read-write + + + UART_MEM_RST + 24 + 1 + read-write + + + PWM2_RST + 25 + 1 + read-write + + + PWM3_RST + 26 + 1 + read-write + + + + + SLAVE_SPI_CONFIG + 0xC8 + 0x20 + + + SLAVE_SPI_MASK_PRO + 0 + 1 + read-write + + + SLAVE_SPI_MASK_APP + 4 + 1 + read-write + + + SPI_ENCRYPT_ENABLE + 8 + 1 + read-write + + + SPI_DECRYPT_ENABLE + 12 + 1 + read-write + + + + + WIFI_CLK_EN + 0xCC + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + 0 + 32 + read-write + + + WIFI_CLK_WIFI_EN + 0 + 3 + read-write + + + WIFI_CLK_WIFI_BT_COMMON + 0 + 6 + read-write + + + WIFI_CLK_BT_EN + 11 + 3 + read-write + + + + + CORE_RST_EN + 0xD0 + 0x20 + + + CORE_RST + 0 + 8 + read-write + + + BB_RST + 0 + 1 + read-write + + + FE_RST + 1 + 1 + read-write + + + MAC_RST + 2 + 1 + read-write + + + BT_RST + 3 + 1 + read-write + + + BTMAC_RST + 4 + 1 + read-write + + + SDIO_RST + 5 + 1 + read-write + + + SDIO_HOST_RST + 6 + 1 + read-write + + + EMAC_RST + 7 + 1 + read-write + + + MACPWR_RST + 8 + 1 + read-write + + + RW_BTMAC_RST + 9 + 1 + read-write + + + RW_BTLP_RST + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + 0xD4 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + 0 + 12 + read-write + + + BTEXTWAKEUP_REQ + 12 + 1 + read-write + + + + + BT_LPCK_DIV_FRAC + 0xD8 + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + 0 + 12 + read-write + + + BT_LPCK_DIV_A + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + 24 + 1 + read-write + + + LPCLK_SEL_8M + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + 27 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + 0xDC + 0x20 + + + CPU_INTR_FROM_CPU_0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + 0xE0 + 0x20 + + + CPU_INTR_FROM_CPU_1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + 0xE4 + 0x20 + + + CPU_INTR_FROM_CPU_2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + 0xE8 + 0x20 + + + CPU_INTR_FROM_CPU_3 + 0 + 1 + read-write + + + + + PRO_INTR_STATUS_0 + 0xEC + 0x20 + + + PRO_INTR_STATUS_0 + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_1 + 0xF0 + 0x20 + + + PRO_INTR_STATUS_1 + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_2 + 0xF4 + 0x20 + + + PRO_INTR_STATUS_2 + 0 + 32 + read-only + + + + + APP_INTR_STATUS_0 + 0xF8 + 0x20 + + + APP_INTR_STATUS_0 + 0 + 32 + read-only + + + + + APP_INTR_STATUS_1 + 0xFC + 0x20 + + + APP_INTR_STATUS_1 + 0 + 32 + read-only + + + + + APP_INTR_STATUS_2 + 0x100 + 0x20 + + + APP_INTR_STATUS_2 + 0 + 32 + read-only + + + + + PRO_MAC_INTR_MAP + 0x104 + 0x20 + 0x00000010 + + + PRO_MAC_INTR_MAP + 0 + 5 + read-write + + + + + PRO_MAC_NMI_MAP + 0x108 + 0x20 + 0x00000010 + + + PRO_MAC_NMI_MAP + 0 + 5 + read-write + + + + + PRO_BB_INT_MAP + 0x10C + 0x20 + 0x00000010 + + + PRO_BB_INT_MAP + 0 + 5 + read-write + + + + + PRO_BT_MAC_INT_MAP + 0x110 + 0x20 + 0x00000010 + + + PRO_BT_MAC_INT_MAP + 0 + 5 + read-write + + + + + PRO_BT_BB_INT_MAP + 0x114 + 0x20 + 0x00000010 + + + PRO_BT_BB_INT_MAP + 0 + 5 + read-write + + + + + PRO_BT_BB_NMI_MAP + 0x118 + 0x20 + 0x00000010 + + + PRO_BT_BB_NMI_MAP + 0 + 5 + read-write + + + + + PRO_RWBT_IRQ_MAP + 0x11C + 0x20 + 0x00000010 + + + PRO_RWBT_IRQ_MAP + 0 + 5 + read-write + + + + + PRO_RWBLE_IRQ_MAP + 0x120 + 0x20 + 0x00000010 + + + PRO_RWBLE_IRQ_MAP + 0 + 5 + read-write + + + + + PRO_RWBT_NMI_MAP + 0x124 + 0x20 + 0x00000010 + + + PRO_RWBT_NMI_MAP + 0 + 5 + read-write + + + + + PRO_RWBLE_NMI_MAP + 0x128 + 0x20 + 0x00000010 + + + PRO_RWBLE_NMI_MAP + 0 + 5 + read-write + + + + + PRO_SLC0_INTR_MAP + 0x12C + 0x20 + 0x00000010 + + + PRO_SLC0_INTR_MAP + 0 + 5 + read-write + + + + + PRO_SLC1_INTR_MAP + 0x130 + 0x20 + 0x00000010 + + + PRO_SLC1_INTR_MAP + 0 + 5 + read-write + + + + + PRO_UHCI0_INTR_MAP + 0x134 + 0x20 + 0x00000010 + + + PRO_UHCI0_INTR_MAP + 0 + 5 + read-write + + + + + PRO_UHCI1_INTR_MAP + 0x138 + 0x20 + 0x00000010 + + + PRO_UHCI1_INTR_MAP + 0 + 5 + read-write + + + + + PRO_TG_T0_LEVEL_INT_MAP + 0x13C + 0x20 + 0x00000010 + + + PRO_TG_T0_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_T1_LEVEL_INT_MAP + 0x140 + 0x20 + 0x00000010 + + + PRO_TG_T1_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_WDT_LEVEL_INT_MAP + 0x144 + 0x20 + 0x00000010 + + + PRO_TG_WDT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_LACT_LEVEL_INT_MAP + 0x148 + 0x20 + 0x00000010 + + + PRO_TG_LACT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_T0_LEVEL_INT_MAP + 0x14C + 0x20 + 0x00000010 + + + PRO_TG1_T0_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_T1_LEVEL_INT_MAP + 0x150 + 0x20 + 0x00000010 + + + PRO_TG1_T1_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_WDT_LEVEL_INT_MAP + 0x154 + 0x20 + 0x00000010 + + + PRO_TG1_WDT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_LACT_LEVEL_INT_MAP + 0x158 + 0x20 + 0x00000010 + + + PRO_TG1_LACT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_MAP + 0x15C + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_PRO_MAP + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_NMI_MAP + 0x160 + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_PRO_NMI_MAP + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_0_MAP + 0x164 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_0_MAP + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_1_MAP + 0x168 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_1_MAP + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_2_MAP + 0x16C + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_2_MAP + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_3_MAP + 0x170 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_3_MAP + 0 + 5 + read-write + + + + + PRO_SPI_INTR_0_MAP + 0x174 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_0_MAP + 0 + 5 + read-write + + + + + PRO_SPI_INTR_1_MAP + 0x178 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_1_MAP + 0 + 5 + read-write + + + + + PRO_SPI_INTR_2_MAP + 0x17C + 0x20 + 0x00000010 + + + PRO_SPI_INTR_2_MAP + 0 + 5 + read-write + + + + + PRO_SPI_INTR_3_MAP + 0x180 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_3_MAP + 0 + 5 + read-write + + + + + PRO_I2S0_INT_MAP + 0x184 + 0x20 + 0x00000010 + + + PRO_I2S0_INT_MAP + 0 + 5 + read-write + + + + + PRO_I2S1_INT_MAP + 0x188 + 0x20 + 0x00000010 + + + PRO_I2S1_INT_MAP + 0 + 5 + read-write + + + + + PRO_UART_INTR_MAP + 0x18C + 0x20 + 0x00000010 + + + PRO_UART_INTR_MAP + 0 + 5 + read-write + + + + + PRO_UART1_INTR_MAP + 0x190 + 0x20 + 0x00000010 + + + PRO_UART1_INTR_MAP + 0 + 5 + read-write + + + + + PRO_UART2_INTR_MAP + 0x194 + 0x20 + 0x00000010 + + + PRO_UART2_INTR_MAP + 0 + 5 + read-write + + + + + PRO_SDIO_HOST_INTERRUPT_MAP + 0x198 + 0x20 + 0x00000010 + + + PRO_SDIO_HOST_INTERRUPT_MAP + 0 + 5 + read-write + + + + + PRO_EMAC_INT_MAP + 0x19C + 0x20 + 0x00000010 + + + PRO_EMAC_INT_MAP + 0 + 5 + read-write + + + + + PRO_PWM0_INTR_MAP + 0x1A0 + 0x20 + 0x00000010 + + + PRO_PWM0_INTR_MAP + 0 + 5 + read-write + + + + + PRO_PWM1_INTR_MAP + 0x1A4 + 0x20 + 0x00000010 + + + PRO_PWM1_INTR_MAP + 0 + 5 + read-write + + + + + PRO_PWM2_INTR_MAP + 0x1A8 + 0x20 + 0x00000010 + + + PRO_PWM2_INTR_MAP + 0 + 5 + read-write + + + + + PRO_PWM3_INTR_MAP + 0x1AC + 0x20 + 0x00000010 + + + PRO_PWM3_INTR_MAP + 0 + 5 + read-write + + + + + PRO_LEDC_INT_MAP + 0x1B0 + 0x20 + 0x00000010 + + + PRO_LEDC_INT_MAP + 0 + 5 + read-write + + + + + PRO_EFUSE_INT_MAP + 0x1B4 + 0x20 + 0x00000010 + + + PRO_EFUSE_INT_MAP + 0 + 5 + read-write + + + + + PRO_CAN_INT_MAP + 0x1B8 + 0x20 + 0x00000010 + + + PRO_CAN_INT_MAP + 0 + 5 + read-write + + + + + PRO_RTC_CORE_INTR_MAP + 0x1BC + 0x20 + 0x00000010 + + + PRO_RTC_CORE_INTR_MAP + 0 + 5 + read-write + + + + + PRO_RMT_INTR_MAP + 0x1C0 + 0x20 + 0x00000010 + + + PRO_RMT_INTR_MAP + 0 + 5 + read-write + + + + + PRO_PCNT_INTR_MAP + 0x1C4 + 0x20 + 0x00000010 + + + PRO_PCNT_INTR_MAP + 0 + 5 + read-write + + + + + PRO_I2C_EXT0_INTR_MAP + 0x1C8 + 0x20 + 0x00000010 + + + PRO_I2C_EXT0_INTR_MAP + 0 + 5 + read-write + + + + + PRO_I2C_EXT1_INTR_MAP + 0x1CC + 0x20 + 0x00000010 + + + PRO_I2C_EXT1_INTR_MAP + 0 + 5 + read-write + + + + + PRO_RSA_INTR_MAP + 0x1D0 + 0x20 + 0x00000010 + + + PRO_RSA_INTR_MAP + 0 + 5 + read-write + + + + + PRO_SPI1_DMA_INT_MAP + 0x1D4 + 0x20 + 0x00000010 + + + PRO_SPI1_DMA_INT_MAP + 0 + 5 + read-write + + + + + PRO_SPI2_DMA_INT_MAP + 0x1D8 + 0x20 + 0x00000010 + + + PRO_SPI2_DMA_INT_MAP + 0 + 5 + read-write + + + + + PRO_SPI3_DMA_INT_MAP + 0x1DC + 0x20 + 0x00000010 + + + PRO_SPI3_DMA_INT_MAP + 0 + 5 + read-write + + + + + PRO_WDG_INT_MAP + 0x1E0 + 0x20 + 0x00000010 + + + PRO_WDG_INT_MAP + 0 + 5 + read-write + + + + + PRO_TIMER_INT1_MAP + 0x1E4 + 0x20 + 0x00000010 + + + PRO_TIMER_INT1_MAP + 0 + 5 + read-write + + + + + PRO_TIMER_INT2_MAP + 0x1E8 + 0x20 + 0x00000010 + + + PRO_TIMER_INT2_MAP + 0 + 5 + read-write + + + + + PRO_TG_T0_EDGE_INT_MAP + 0x1EC + 0x20 + 0x00000010 + + + PRO_TG_T0_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_T1_EDGE_INT_MAP + 0x1F0 + 0x20 + 0x00000010 + + + PRO_TG_T1_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_WDT_EDGE_INT_MAP + 0x1F4 + 0x20 + 0x00000010 + + + PRO_TG_WDT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG_LACT_EDGE_INT_MAP + 0x1F8 + 0x20 + 0x00000010 + + + PRO_TG_LACT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_T0_EDGE_INT_MAP + 0x1FC + 0x20 + 0x00000010 + + + PRO_TG1_T0_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_T1_EDGE_INT_MAP + 0x200 + 0x20 + 0x00000010 + + + PRO_TG1_T1_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_WDT_EDGE_INT_MAP + 0x204 + 0x20 + 0x00000010 + + + PRO_TG1_WDT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_TG1_LACT_EDGE_INT_MAP + 0x208 + 0x20 + 0x00000010 + + + PRO_TG1_LACT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + PRO_MMU_IA_INT_MAP + 0x20C + 0x20 + 0x00000010 + + + PRO_MMU_IA_INT_MAP + 0 + 5 + read-write + + + + + PRO_MPU_IA_INT_MAP + 0x210 + 0x20 + 0x00000010 + + + PRO_MPU_IA_INT_MAP + 0 + 5 + read-write + + + + + PRO_CACHE_IA_INT_MAP + 0x214 + 0x20 + 0x00000010 + + + PRO_CACHE_IA_INT_MAP + 0 + 5 + read-write + + + + + APP_MAC_INTR_MAP + 0x218 + 0x20 + 0x00000010 + + + APP_MAC_INTR_MAP + 0 + 5 + read-write + + + + + APP_MAC_NMI_MAP + 0x21C + 0x20 + 0x00000010 + + + APP_MAC_NMI_MAP + 0 + 5 + read-write + + + + + APP_BB_INT_MAP + 0x220 + 0x20 + 0x00000010 + + + APP_BB_INT_MAP + 0 + 5 + read-write + + + + + APP_BT_MAC_INT_MAP + 0x224 + 0x20 + 0x00000010 + + + APP_BT_MAC_INT_MAP + 0 + 5 + read-write + + + + + APP_BT_BB_INT_MAP + 0x228 + 0x20 + 0x00000010 + + + APP_BT_BB_INT_MAP + 0 + 5 + read-write + + + + + APP_BT_BB_NMI_MAP + 0x22C + 0x20 + 0x00000010 + + + APP_BT_BB_NMI_MAP + 0 + 5 + read-write + + + + + APP_RWBT_IRQ_MAP + 0x230 + 0x20 + 0x00000010 + + + APP_RWBT_IRQ_MAP + 0 + 5 + read-write + + + + + APP_RWBLE_IRQ_MAP + 0x234 + 0x20 + 0x00000010 + + + APP_RWBLE_IRQ_MAP + 0 + 5 + read-write + + + + + APP_RWBT_NMI_MAP + 0x238 + 0x20 + 0x00000010 + + + APP_RWBT_NMI_MAP + 0 + 5 + read-write + + + + + APP_RWBLE_NMI_MAP + 0x23C + 0x20 + 0x00000010 + + + APP_RWBLE_NMI_MAP + 0 + 5 + read-write + + + + + APP_SLC0_INTR_MAP + 0x240 + 0x20 + 0x00000010 + + + APP_SLC0_INTR_MAP + 0 + 5 + read-write + + + + + APP_SLC1_INTR_MAP + 0x244 + 0x20 + 0x00000010 + + + APP_SLC1_INTR_MAP + 0 + 5 + read-write + + + + + APP_UHCI0_INTR_MAP + 0x248 + 0x20 + 0x00000010 + + + APP_UHCI0_INTR_MAP + 0 + 5 + read-write + + + + + APP_UHCI1_INTR_MAP + 0x24C + 0x20 + 0x00000010 + + + APP_UHCI1_INTR_MAP + 0 + 5 + read-write + + + + + APP_TG_T0_LEVEL_INT_MAP + 0x250 + 0x20 + 0x00000010 + + + APP_TG_T0_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_T1_LEVEL_INT_MAP + 0x254 + 0x20 + 0x00000010 + + + APP_TG_T1_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_WDT_LEVEL_INT_MAP + 0x258 + 0x20 + 0x00000010 + + + APP_TG_WDT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_LACT_LEVEL_INT_MAP + 0x25C + 0x20 + 0x00000010 + + + APP_TG_LACT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_T0_LEVEL_INT_MAP + 0x260 + 0x20 + 0x00000010 + + + APP_TG1_T0_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_T1_LEVEL_INT_MAP + 0x264 + 0x20 + 0x00000010 + + + APP_TG1_T1_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_WDT_LEVEL_INT_MAP + 0x268 + 0x20 + 0x00000010 + + + APP_TG1_WDT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_LACT_LEVEL_INT_MAP + 0x26C + 0x20 + 0x00000010 + + + APP_TG1_LACT_LEVEL_INT_MAP + 0 + 5 + read-write + + + + + APP_GPIO_INTERRUPT_MAP + 0x270 + 0x20 + 0x00000010 + + + APP_GPIO_INTERRUPT_APP_MAP + 0 + 5 + read-write + + + + + APP_GPIO_INTERRUPT_NMI_MAP + 0x274 + 0x20 + 0x00000010 + + + APP_GPIO_INTERRUPT_APP_NMI_MAP + 0 + 5 + read-write + + + + + APP_CPU_INTR_FROM_CPU_0_MAP + 0x278 + 0x20 + 0x00000010 + + + APP_CPU_INTR_FROM_CPU_0_MAP + 0 + 5 + read-write + + + + + APP_CPU_INTR_FROM_CPU_1_MAP + 0x27C + 0x20 + 0x00000010 + + + APP_CPU_INTR_FROM_CPU_1_MAP + 0 + 5 + read-write + + + + + APP_CPU_INTR_FROM_CPU_2_MAP + 0x280 + 0x20 + 0x00000010 + + + APP_CPU_INTR_FROM_CPU_2_MAP + 0 + 5 + read-write + + + + + APP_CPU_INTR_FROM_CPU_3_MAP + 0x284 + 0x20 + 0x00000010 + + + APP_CPU_INTR_FROM_CPU_3_MAP + 0 + 5 + read-write + + + + + APP_SPI_INTR_0_MAP + 0x288 + 0x20 + 0x00000010 + + + APP_SPI_INTR_0_MAP + 0 + 5 + read-write + + + + + APP_SPI_INTR_1_MAP + 0x28C + 0x20 + 0x00000010 + + + APP_SPI_INTR_1_MAP + 0 + 5 + read-write + + + + + APP_SPI_INTR_2_MAP + 0x290 + 0x20 + 0x00000010 + + + APP_SPI_INTR_2_MAP + 0 + 5 + read-write + + + + + APP_SPI_INTR_3_MAP + 0x294 + 0x20 + 0x00000010 + + + APP_SPI_INTR_3_MAP + 0 + 5 + read-write + + + + + APP_I2S0_INT_MAP + 0x298 + 0x20 + 0x00000010 + + + APP_I2S0_INT_MAP + 0 + 5 + read-write + + + + + APP_I2S1_INT_MAP + 0x29C + 0x20 + 0x00000010 + + + APP_I2S1_INT_MAP + 0 + 5 + read-write + + + + + APP_UART_INTR_MAP + 0x2A0 + 0x20 + 0x00000010 + + + APP_UART_INTR_MAP + 0 + 5 + read-write + + + + + APP_UART1_INTR_MAP + 0x2A4 + 0x20 + 0x00000010 + + + APP_UART1_INTR_MAP + 0 + 5 + read-write + + + + + APP_UART2_INTR_MAP + 0x2A8 + 0x20 + 0x00000010 + + + APP_UART2_INTR_MAP + 0 + 5 + read-write + + + + + APP_SDIO_HOST_INTERRUPT_MAP + 0x2AC + 0x20 + 0x00000010 + + + APP_SDIO_HOST_INTERRUPT_MAP + 0 + 5 + read-write + + + + + APP_EMAC_INT_MAP + 0x2B0 + 0x20 + 0x00000010 + + + APP_EMAC_INT_MAP + 0 + 5 + read-write + + + + + APP_PWM0_INTR_MAP + 0x2B4 + 0x20 + 0x00000010 + + + APP_PWM0_INTR_MAP + 0 + 5 + read-write + + + + + APP_PWM1_INTR_MAP + 0x2B8 + 0x20 + 0x00000010 + + + APP_PWM1_INTR_MAP + 0 + 5 + read-write + + + + + APP_PWM2_INTR_MAP + 0x2BC + 0x20 + 0x00000010 + + + APP_PWM2_INTR_MAP + 0 + 5 + read-write + + + + + APP_PWM3_INTR_MAP + 0x2C0 + 0x20 + 0x00000010 + + + APP_PWM3_INTR_MAP + 0 + 5 + read-write + + + + + APP_LEDC_INT_MAP + 0x2C4 + 0x20 + 0x00000010 + + + APP_LEDC_INT_MAP + 0 + 5 + read-write + + + + + APP_EFUSE_INT_MAP + 0x2C8 + 0x20 + 0x00000010 + + + APP_EFUSE_INT_MAP + 0 + 5 + read-write + + + + + APP_CAN_INT_MAP + 0x2CC + 0x20 + 0x00000010 + + + APP_CAN_INT_MAP + 0 + 5 + read-write + + + + + APP_RTC_CORE_INTR_MAP + 0x2D0 + 0x20 + 0x00000010 + + + APP_RTC_CORE_INTR_MAP + 0 + 5 + read-write + + + + + APP_RMT_INTR_MAP + 0x2D4 + 0x20 + 0x00000010 + + + APP_RMT_INTR_MAP + 0 + 5 + read-write + + + + + APP_PCNT_INTR_MAP + 0x2D8 + 0x20 + 0x00000010 + + + APP_PCNT_INTR_MAP + 0 + 5 + read-write + + + + + APP_I2C_EXT0_INTR_MAP + 0x2DC + 0x20 + 0x00000010 + + + APP_I2C_EXT0_INTR_MAP + 0 + 5 + read-write + + + + + APP_I2C_EXT1_INTR_MAP + 0x2E0 + 0x20 + 0x00000010 + + + APP_I2C_EXT1_INTR_MAP + 0 + 5 + read-write + + + + + APP_RSA_INTR_MAP + 0x2E4 + 0x20 + 0x00000010 + + + APP_RSA_INTR_MAP + 0 + 5 + read-write + + + + + APP_SPI1_DMA_INT_MAP + 0x2E8 + 0x20 + 0x00000010 + + + APP_SPI1_DMA_INT_MAP + 0 + 5 + read-write + + + + + APP_SPI2_DMA_INT_MAP + 0x2EC + 0x20 + 0x00000010 + + + APP_SPI2_DMA_INT_MAP + 0 + 5 + read-write + + + + + APP_SPI3_DMA_INT_MAP + 0x2F0 + 0x20 + 0x00000010 + + + APP_SPI3_DMA_INT_MAP + 0 + 5 + read-write + + + + + APP_WDG_INT_MAP + 0x2F4 + 0x20 + 0x00000010 + + + APP_WDG_INT_MAP + 0 + 5 + read-write + + + + + APP_TIMER_INT1_MAP + 0x2F8 + 0x20 + 0x00000010 + + + APP_TIMER_INT1_MAP + 0 + 5 + read-write + + + + + APP_TIMER_INT2_MAP + 0x2FC + 0x20 + 0x00000010 + + + APP_TIMER_INT2_MAP + 0 + 5 + read-write + + + + + APP_TG_T0_EDGE_INT_MAP + 0x300 + 0x20 + 0x00000010 + + + APP_TG_T0_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_T1_EDGE_INT_MAP + 0x304 + 0x20 + 0x00000010 + + + APP_TG_T1_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_WDT_EDGE_INT_MAP + 0x308 + 0x20 + 0x00000010 + + + APP_TG_WDT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG_LACT_EDGE_INT_MAP + 0x30C + 0x20 + 0x00000010 + + + APP_TG_LACT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_T0_EDGE_INT_MAP + 0x310 + 0x20 + 0x00000010 + + + APP_TG1_T0_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_T1_EDGE_INT_MAP + 0x314 + 0x20 + 0x00000010 + + + APP_TG1_T1_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_WDT_EDGE_INT_MAP + 0x318 + 0x20 + 0x00000010 + + + APP_TG1_WDT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_TG1_LACT_EDGE_INT_MAP + 0x31C + 0x20 + 0x00000010 + + + APP_TG1_LACT_EDGE_INT_MAP + 0 + 5 + read-write + + + + + APP_MMU_IA_INT_MAP + 0x320 + 0x20 + 0x00000010 + + + APP_MMU_IA_INT_MAP + 0 + 5 + read-write + + + + + APP_MPU_IA_INT_MAP + 0x324 + 0x20 + 0x00000010 + + + APP_MPU_IA_INT_MAP + 0 + 5 + read-write + + + + + APP_CACHE_IA_INT_MAP + 0x328 + 0x20 + 0x00000010 + + + APP_CACHE_IA_INT_MAP + 0 + 5 + read-write + + + + + AHBLITE_MPU_TABLE_UART + 0x32C + 0x20 + + + UART_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SPI1 + 0x330 + 0x20 + + + SPI1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SPI0 + 0x334 + 0x20 + + + SPI0_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_GPIO + 0x338 + 0x20 + + + GPIO_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_FE2 + 0x33C + 0x20 + + + FE2_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_FE + 0x340 + 0x20 + + + FE_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_TIMER + 0x344 + 0x20 + + + TIMER_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_RTC + 0x348 + 0x20 + + + RTC_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_IO_MUX + 0x34C + 0x20 + + + IOMUX_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_WDG + 0x350 + 0x20 + + + WDG_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_HINF + 0x354 + 0x20 + + + HINF_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_UHCI1 + 0x358 + 0x20 + + + UHCI1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_MISC + 0x35C + 0x20 + + + MISC_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_I2C + 0x360 + 0x20 + + + I2C_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_I2S0 + 0x364 + 0x20 + + + I2S0_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_UART1 + 0x368 + 0x20 + + + UART1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_BT + 0x36C + 0x20 + + + BT_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_BT_BUFFER + 0x370 + 0x20 + + + BTBUFFER_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_I2C_EXT0 + 0x374 + 0x20 + + + I2CEXT0_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_UHCI0 + 0x378 + 0x20 + + + UHCI0_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SLCHOST + 0x37C + 0x20 + + + SLCHOST_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_RMT + 0x380 + 0x20 + + + RMT_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_PCNT + 0x384 + 0x20 + + + PCNT_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SLC + 0x388 + 0x20 + + + SLC_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_LEDC + 0x38C + 0x20 + + + LEDC_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_EFUSE + 0x390 + 0x20 + + + EFUSE_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SPI_ENCRYPT + 0x394 + 0x20 + + + SPI_ENCRYPY_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_BB + 0x398 + 0x20 + + + BB_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_PWM0 + 0x39C + 0x20 + + + PWM0_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_TIMERGROUP + 0x3A0 + 0x20 + + + TIMERGROUP_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_TIMERGROUP1 + 0x3A4 + 0x20 + + + TIMERGROUP1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SPI2 + 0x3A8 + 0x20 + + + SPI2_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SPI3 + 0x3AC + 0x20 + + + SPI3_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_APB_CTRL + 0x3B0 + 0x20 + + + APBCTRL_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_I2C_EXT1 + 0x3B4 + 0x20 + + + I2CEXT1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_SDIO_HOST + 0x3B8 + 0x20 + + + SDIOHOST_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_EMAC + 0x3BC + 0x20 + + + EMAC_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_CAN + 0x3C0 + 0x20 + + + CAN_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_PWM1 + 0x3C4 + 0x20 + + + PWM1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_I2S1 + 0x3C8 + 0x20 + + + I2S1_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_UART2 + 0x3CC + 0x20 + + + UART2_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_PWM2 + 0x3D0 + 0x20 + + + PWM2_ACCESS_GRANT_CONFIG + 0 + 6 + read-write + + + + + AHBLITE_MPU_TABLE_PWM3 + 0x3D4 + 0x20 + + + PWM3_ACCESS_GRANT_CONFIG + 0 + 6 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read-only + + + AHB_ACCESS_DENY + 8 + 1 + read-only + + + AHBLITE_ACCESS_DENY + 9 + 1 + read-only + + + AHBLITE_IA + 10 + 1 + read-only + + + + + PRO_DCACHE_DBUG0 + 0x3F0 + 0x20 + + + PRO_SLAVE_WDATA + 0 + 1 + read-write + + + PRO_CACHE_MMU_IA + 0 + 1 + read-only + + + PRO_CACHE_IA + 1 + 6 + read-only + + + PRO_CACHE_STATE + 7 + 12 + read-only + + + PRO_WR_BAK_TO_READ + 19 + 1 + read-only + + + PRO_TX_END + 20 + 1 + read-only + + + PRO_SLAVE_WR + 21 + 1 + read-only + + + PRO_SLAVE_WDATA_V + 22 + 1 + read-only + + + PRO_RX_END + 23 + 1 + read-only + + + + + PRO_DCACHE_DBUG1 + 0x3F4 + 0x20 + + + PRO_CTAG_RAM_RDATA + 0 + 32 + read-only + + + + + PRO_DCACHE_DBUG2 + 0x3F8 + 0x20 + + + PRO_CACHE_VADDR + 0 + 27 + read-only + + + + + PRO_DCACHE_DBUG3 + 0x3FC + 0x20 + + + PRO_MMU_RDATA + 0 + 9 + read-only + + + PRO_CPU_DISABLED_CACHE_IA + 9 + 6 + read-only + + + PRO_CPU_DISABLED_CACHE_IA_OPPOSITE + 9 + 1 + read-write + + + PRO_CPU_DISABLED_CACHE_IA_DRAM1 + 10 + 1 + read-write + + + PRO_CPU_DISABLED_CACHE_IA_IROM0 + 11 + 1 + read-write + + + PRO_CPU_DISABLED_CACHE_IA_IRAM1 + 12 + 1 + read-write + + + PRO_CPU_DISABLED_CACHE_IA_IRAM0 + 13 + 1 + read-write + + + PRO_CPU_DISABLED_CACHE_IA_DROM0 + 14 + 1 + read-write + + + PRO_CACHE_IRAM0_PID_ERROR + 15 + 1 + read-only + + + + + PRO_DCACHE_DBUG4 + 0x400 + 0x20 + + + PRO_DRAM1ADDR0_IA + 0 + 20 + read-only + + + + + PRO_DCACHE_DBUG5 + 0x404 + 0x20 + + + PRO_DROM0ADDR0_IA + 0 + 20 + read-only + + + + + PRO_DCACHE_DBUG6 + 0x408 + 0x20 + + + PRO_IRAM0ADDR_IA + 0 + 20 + read-only + + + + + PRO_DCACHE_DBUG7 + 0x40C + 0x20 + + + PRO_IRAM1ADDR_IA + 0 + 20 + read-only + + + + + PRO_DCACHE_DBUG8 + 0x410 + 0x20 + + + PRO_IROM0ADDR_IA + 0 + 20 + read-only + + + + + PRO_DCACHE_DBUG9 + 0x414 + 0x20 + + + PRO_OPSDRAMADDR_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG0 + 0x418 + 0x20 + + + APP_SLAVE_WDATA + 0 + 1 + read-write + + + APP_CACHE_MMU_IA + 0 + 1 + read-only + + + APP_CACHE_IA + 1 + 6 + read-only + + + APP_CACHE_STATE + 7 + 12 + read-only + + + APP_WR_BAK_TO_READ + 19 + 1 + read-only + + + APP_TX_END + 20 + 1 + read-only + + + APP_SLAVE_WR + 21 + 1 + read-only + + + APP_SLAVE_WDATA_V + 22 + 1 + read-only + + + APP_RX_END + 23 + 1 + read-only + + + + + APP_DCACHE_DBUG1 + 0x41C + 0x20 + + + APP_CTAG_RAM_RDATA + 0 + 32 + read-only + + + + + APP_DCACHE_DBUG2 + 0x420 + 0x20 + + + APP_CACHE_VADDR + 0 + 27 + read-only + + + + + APP_DCACHE_DBUG3 + 0x424 + 0x20 + + + APP_MMU_RDATA + 0 + 9 + read-only + + + APP_CPU_DISABLED_CACHE_IA + 9 + 6 + read-only + + + APP_CPU_DISABLED_CACHE_IA_OPPOSITE + 9 + 1 + read-write + + + APP_CPU_DISABLED_CACHE_IA_DRAM1 + 10 + 1 + read-write + + + APP_CPU_DISABLED_CACHE_IA_IROM0 + 11 + 1 + read-write + + + APP_CPU_DISABLED_CACHE_IA_IRAM1 + 12 + 1 + read-write + + + APP_CPU_DISABLED_CACHE_IA_IRAM0 + 13 + 1 + read-write + + + APP_CPU_DISABLED_CACHE_IA_DROM0 + 14 + 1 + read-write + + + APP_CACHE_IRAM0_PID_ERROR + 15 + 1 + read-only + + + + + APP_DCACHE_DBUG4 + 0x428 + 0x20 + + + APP_DRAM1ADDR0_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG5 + 0x42C + 0x20 + + + APP_DROM0ADDR0_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG6 + 0x430 + 0x20 + + + APP_IRAM0ADDR_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG7 + 0x434 + 0x20 + + + APP_IRAM1ADDR_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG8 + 0x438 + 0x20 + + + APP_IROM0ADDR_IA + 0 + 20 + read-only + + + + + APP_DCACHE_DBUG9 + 0x43C + 0x20 + + + APP_OPSDRAMADDR_IA + 0 + 20 + read-only + + + + + PRO_CPU_RECORD_CTRL + 0x440 + 0x20 + 0x00000100 + + + PRO_CPU_RECORD_ENABLE + 0 + 1 + read-write + + + PRO_CPU_RECORD_DISABLE + 4 + 1 + read-write + + + PRO_CPU_PDEBUG_ENABLE + 8 + 1 + read-write + + + + + PRO_CPU_RECORD_STATUS + 0x444 + 0x20 + + + PRO_CPU_RECORDING + 0 + 1 + read-only + + + + + PRO_CPU_RECORD_PID + 0x448 + 0x20 + + + RECORD_PRO_PID + 0 + 3 + read-only + + + + + PRO_CPU_RECORD_PDEBUGINST + 0x44C + 0x20 + + + RECORD_PRO_PDEBUGINST + 0 + 32 + read-only + + + RECORD_PDEBUGINST_SZ + 0 + 8 + read-write + + + RECORD_PDEBUGINST_ISRC + 12 + 3 + read-write + + + RECORD_PDEBUGINST_LOOP_REP + 20 + 1 + read-write + + + RECORD_PDEBUGINST_LOOP + 21 + 1 + read-write + + + RECORD_PDEBUGINST_CINTL + 24 + 4 + read-write + + + + + PRO_CPU_RECORD_PDEBUGSTATUS + 0x450 + 0x20 + + + RECORD_PRO_PDEBUGSTATUS + 0 + 8 + read-only + + + RECORD_PDEBUGSTATUS_BBCAUSE + 0 + 6 + read-write + + + RECORD_PDEBUGSTATUS_INSNTYPE + 0 + 6 + read-write + + + + + PRO_CPU_RECORD_PDEBUGDATA + 0x454 + 0x20 + + + RECORD_PRO_PDEBUGDATA + 0 + 32 + read-only + + + RECORD_PDEBUGDATA_DEP_OTHER + 0 + 1 + read-write + + + RECORD_PDEBUGDATA_EXCVEC + 0 + 5 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_SR + 0 + 8 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_RER + 0 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BUFF + 1 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_WER + 1 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BUFFCONFL + 2 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_ER + 2 + 12 + read-write + + + RECORD_PDEBUGDATA_STALL_DCM + 3 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_LSU + 4 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ICM + 6 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_IRAMBUSY + 7 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_LSU + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_IPIF + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_RSR + 8 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_TIE + 9 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_WSR + 9 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_RUN + 10 + 1 + read-write + + + RECORD_PDEBUGDATA_INSNTYPE_XSR + 10 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_STR + 11 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP + 12 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BPIFETCH + 12 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_L32R + 13 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_LSPROC + 14 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_BPLOAD + 15 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_MEMW + 16 + 1 + read-write + + + RECORD_PDEBUGDATA_EXCCAUSE + 16 + 6 + read-write + + + RECORD_PDEBUGDATA_STALL_BANKCONFL + 16 + 1 + read-write + + + RECORD_PDEBUGDATA_DEP_HALT + 17 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ITERMUL + 18 + 1 + read-write + + + RECORD_PDEBUGDATA_STALL_ITERDIV + 19 + 1 + read-write + + + + + PRO_CPU_RECORD_PDEBUGPC + 0x458 + 0x20 + + + RECORD_PRO_PDEBUGPC + 0 + 32 + read-only + + + + + PRO_CPU_RECORD_PDEBUGLS0STAT + 0x45C + 0x20 + + + RECORD_PRO_PDEBUGLS0STAT + 0 + 32 + read-only + + + RECORD_PDEBUGLS0STAT_TYPE + 0 + 4 + read-write + + + RECORD_PDEBUGLS0STAT_SZ + 4 + 4 + read-write + + + RECORD_PDEBUGLS0STAT_DTLBM + 8 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_DCM + 9 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_DCH + 10 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_UC + 12 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_WB + 13 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_COH + 16 + 1 + read-write + + + RECORD_PDEBUGLS0STAT_STCOH + 17 + 2 + read-write + + + RECORD_PDEBUGLS0STAT_TGT + 20 + 4 + read-write + + + + + PRO_CPU_RECORD_PDEBUGLS0ADDR + 0x460 + 0x20 + + + RECORD_PRO_PDEBUGLS0ADDR + 0 + 32 + read-only + + + + + PRO_CPU_RECORD_PDEBUGLS0DATA + 0x464 + 0x20 + + + RECORD_PRO_PDEBUGLS0DATA + 0 + 32 + read-only + + + + + APP_CPU_RECORD_CTRL + 0x468 + 0x20 + 0x00000100 + + + APP_CPU_RECORD_ENABLE + 0 + 1 + read-write + + + APP_CPU_RECORD_DISABLE + 4 + 1 + read-write + + + APP_CPU_PDEBUG_ENABLE + 8 + 1 + read-write + + + + + APP_CPU_RECORD_STATUS + 0x46C + 0x20 + + + APP_CPU_RECORDING + 0 + 1 + read-only + + + + + APP_CPU_RECORD_PID + 0x470 + 0x20 + + + RECORD_APP_PID + 0 + 3 + read-only + + + + + APP_CPU_RECORD_PDEBUGINST + 0x474 + 0x20 + + + RECORD_APP_PDEBUGINST + 0 + 32 + read-only + + + + + APP_CPU_RECORD_PDEBUGSTATUS + 0x478 + 0x20 + + + RECORD_APP_PDEBUGSTATUS + 0 + 8 + read-only + + + + + APP_CPU_RECORD_PDEBUGDATA + 0x47C + 0x20 + + + RECORD_APP_PDEBUGDATA + 0 + 32 + read-only + + + + + APP_CPU_RECORD_PDEBUGPC + 0x480 + 0x20 + + + RECORD_APP_PDEBUGPC + 0 + 32 + read-only + + + + + APP_CPU_RECORD_PDEBUGLS0STAT + 0x484 + 0x20 + + + RECORD_APP_PDEBUGLS0STAT + 0 + 32 + read-only + + + + + APP_CPU_RECORD_PDEBUGLS0ADDR + 0x488 + 0x20 + + + RECORD_APP_PDEBUGLS0ADDR + 0 + 32 + read-only + + + + + APP_CPU_RECORD_PDEBUGLS0DATA + 0x48C + 0x20 + + + RECORD_APP_PDEBUGLS0DATA + 0 + 32 + read-only + + + + + RSA_PD_CTRL + 0x490 + 0x20 + + + RSA_PD + 0 + 1 + read-write + + + + + ROM_MPU_TABLE0 + 0x494 + 0x20 + 0x00000001 + + + ROM_MPU_TABLE0 + 0 + 2 + read-write + + + + + ROM_MPU_TABLE1 + 0x498 + 0x20 + 0x00000001 + + + ROM_MPU_TABLE1 + 0 + 2 + read-write + + + + + ROM_MPU_TABLE2 + 0x49C + 0x20 + 0x00000001 + + + ROM_MPU_TABLE2 + 0 + 2 + read-write + + + + + ROM_MPU_TABLE3 + 0x4A0 + 0x20 + 0x00000001 + + + ROM_MPU_TABLE3 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE0 + 0x4A4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE0 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE1 + 0x4A8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE1 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE2 + 0x4AC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE2 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE3 + 0x4B0 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE3 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE4 + 0x4B4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE4 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE5 + 0x4B8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE5 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE6 + 0x4BC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE6 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE7 + 0x4C0 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE7 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE8 + 0x4C4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE8 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE9 + 0x4C8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE9 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE10 + 0x4CC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE10 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE11 + 0x4D0 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE11 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE12 + 0x4D4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE12 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE13 + 0x4D8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE13 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE14 + 0x4DC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE14 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE15 + 0x4E0 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE15 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE16 + 0x4E4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE16 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE17 + 0x4E8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE17 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE18 + 0x4EC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE18 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE19 + 0x4F0 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE19 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE20 + 0x4F4 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE20 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE21 + 0x4F8 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE21 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE22 + 0x4FC + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE22 + 0 + 2 + read-write + + + + + SHROM_MPU_TABLE23 + 0x500 + 0x20 + 0x00000001 + + + SHROM_MPU_TABLE23 + 0 + 2 + read-write + + + + + IMMU_TABLE0 + 0x504 + 0x20 + + + IMMU_TABLE0 + 0 + 7 + read-write + + + + + IMMU_TABLE1 + 0x508 + 0x20 + 0x00000001 + + + IMMU_TABLE1 + 0 + 7 + read-write + + + + + IMMU_TABLE2 + 0x50C + 0x20 + 0x00000002 + + + IMMU_TABLE2 + 0 + 7 + read-write + + + + + IMMU_TABLE3 + 0x510 + 0x20 + 0x00000003 + + + IMMU_TABLE3 + 0 + 7 + read-write + + + + + IMMU_TABLE4 + 0x514 + 0x20 + 0x00000004 + + + IMMU_TABLE4 + 0 + 7 + read-write + + + + + IMMU_TABLE5 + 0x518 + 0x20 + 0x00000005 + + + IMMU_TABLE5 + 0 + 7 + read-write + + + + + IMMU_TABLE6 + 0x51C + 0x20 + 0x00000006 + + + IMMU_TABLE6 + 0 + 7 + read-write + + + + + IMMU_TABLE7 + 0x520 + 0x20 + 0x00000007 + + + IMMU_TABLE7 + 0 + 7 + read-write + + + + + IMMU_TABLE8 + 0x524 + 0x20 + 0x00000008 + + + IMMU_TABLE8 + 0 + 7 + read-write + + + + + IMMU_TABLE9 + 0x528 + 0x20 + 0x00000009 + + + IMMU_TABLE9 + 0 + 7 + read-write + + + + + IMMU_TABLE10 + 0x52C + 0x20 + 0x0000000A + + + IMMU_TABLE10 + 0 + 7 + read-write + + + + + IMMU_TABLE11 + 0x530 + 0x20 + 0x0000000B + + + IMMU_TABLE11 + 0 + 7 + read-write + + + + + IMMU_TABLE12 + 0x534 + 0x20 + 0x0000000C + + + IMMU_TABLE12 + 0 + 7 + read-write + + + + + IMMU_TABLE13 + 0x538 + 0x20 + 0x0000000D + + + IMMU_TABLE13 + 0 + 7 + read-write + + + + + IMMU_TABLE14 + 0x53C + 0x20 + 0x0000000E + + + IMMU_TABLE14 + 0 + 7 + read-write + + + + + IMMU_TABLE15 + 0x540 + 0x20 + 0x0000000F + + + IMMU_TABLE15 + 0 + 7 + read-write + + + + + DMMU_TABLE0 + 0x544 + 0x20 + + + DMMU_TABLE0 + 0 + 7 + read-write + + + + + DMMU_TABLE1 + 0x548 + 0x20 + 0x00000001 + + + DMMU_TABLE1 + 0 + 7 + read-write + + + + + DMMU_TABLE2 + 0x54C + 0x20 + 0x00000002 + + + DMMU_TABLE2 + 0 + 7 + read-write + + + + + DMMU_TABLE3 + 0x550 + 0x20 + 0x00000003 + + + DMMU_TABLE3 + 0 + 7 + read-write + + + + + DMMU_TABLE4 + 0x554 + 0x20 + 0x00000004 + + + DMMU_TABLE4 + 0 + 7 + read-write + + + + + DMMU_TABLE5 + 0x558 + 0x20 + 0x00000005 + + + DMMU_TABLE5 + 0 + 7 + read-write + + + + + DMMU_TABLE6 + 0x55C + 0x20 + 0x00000006 + + + DMMU_TABLE6 + 0 + 7 + read-write + + + + + DMMU_TABLE7 + 0x560 + 0x20 + 0x00000007 + + + DMMU_TABLE7 + 0 + 7 + read-write + + + + + DMMU_TABLE8 + 0x564 + 0x20 + 0x00000008 + + + DMMU_TABLE8 + 0 + 7 + read-write + + + + + DMMU_TABLE9 + 0x568 + 0x20 + 0x00000009 + + + DMMU_TABLE9 + 0 + 7 + read-write + + + + + DMMU_TABLE10 + 0x56C + 0x20 + 0x0000000A + + + DMMU_TABLE10 + 0 + 7 + read-write + + + + + DMMU_TABLE11 + 0x570 + 0x20 + 0x0000000B + + + DMMU_TABLE11 + 0 + 7 + read-write + + + + + DMMU_TABLE12 + 0x574 + 0x20 + 0x0000000C + + + DMMU_TABLE12 + 0 + 7 + read-write + + + + + DMMU_TABLE13 + 0x578 + 0x20 + 0x0000000D + + + DMMU_TABLE13 + 0 + 7 + read-write + + + + + DMMU_TABLE14 + 0x57C + 0x20 + 0x0000000E + + + DMMU_TABLE14 + 0 + 7 + read-write + + + + + DMMU_TABLE15 + 0x580 + 0x20 + 0x0000000F + + + DMMU_TABLE15 + 0 + 7 + read-write + + + + + PRO_INTRUSION_CTRL + 0x584 + 0x20 + 0x00000001 + + + PRO_INTRUSION_RECORD_RESET_N + 0 + 1 + read-write + + + + + PRO_INTRUSION_STATUS + 0x588 + 0x20 + + + PRO_INTRUSION_RECORD + 0 + 4 + read-only + + + + + APP_INTRUSION_CTRL + 0x58C + 0x20 + 0x00000001 + + + APP_INTRUSION_RECORD_RESET_N + 0 + 1 + read-write + + + + + APP_INTRUSION_STATUS + 0x590 + 0x20 + + + APP_INTRUSION_RECORD + 0 + 4 + read-only + + + + + FRONT_END_MEM_PD + 0x594 + 0x20 + 0x00000005 + + + AGC_MEM_FORCE_PU + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + 3 + 1 + read-write + + + + + MMU_IA_INT_EN + 0x598 + 0x20 + + + MMU_IA_INT_EN + 0 + 24 + read-write + + + + + MPU_IA_INT_EN + 0x59C + 0x20 + + + MPU_IA_INT_EN + 0 + 17 + read-write + + + + + CACHE_IA_INT_EN + 0x5A0 + 0x20 + + + CACHE_IA_INT_EN + Interrupt enable bits for various invalid cache access reasons + 0 + 28 + read-write + + + CACHE_IA_INT_APP_DROM0 + APP CPU invalid access to DROM0 when cache is disabled + 0 + 1 + read-write + + + CACHE_IA_INT_APP_IRAM0 + APP CPU invalid access to IRAM0 when cache is disabled + 1 + 1 + read-write + + + CACHE_IA_INT_APP_IRAM1 + APP CPU invalid access to IRAM1 when cache is disabled + 2 + 1 + read-write + + + CACHE_IA_INT_APP_IROM0 + APP CPU invalid access to IROM0 when cache is disabled + 3 + 1 + read-write + + + CACHE_IA_INT_APP_DRAM1 + APP CPU invalid access to DRAM1 when cache is disabled + 4 + 1 + read-write + + + CACHE_IA_INT_APP_OPPOSITE + APP CPU invalid access to APP CPU cache when cache disabled + 5 + 1 + read-write + + + CACHE_IA_INT_PRO_DROM0 + PRO CPU invalid access to DROM0 when cache is disabled + 14 + 1 + read-write + + + CACHE_IA_INT_PRO_IRAM0 + PRO CPU invalid access to IRAM0 when cache is disabled + 15 + 1 + read-write + + + CACHE_IA_INT_PRO_IRAM1 + PRO CPU invalid access to IRAM1 when cache is disabled + 16 + 1 + read-write + + + CACHE_IA_INT_PRO_IROM0 + PRO CPU invalid access to IROM0 when cache is disabled + 17 + 1 + read-write + + + CACHE_IA_INT_PRO_DRAM1 + PRO CPU invalid access to DRAM1 when cache is disabled + 18 + 1 + read-write + + + CACHE_IA_INT_PRO_OPPOSITE + PRO CPU invalid access to APP CPU cache when cache disabled + 19 + 1 + read-write + + + + + SECURE_BOOT_CTRL + 0x5A4 + 0x20 + + + SW_BOOTLOADER_SEL + 0 + 1 + read-write + + + + + SPI_DMA_CHAN_SEL + 0x5A8 + 0x20 + + + SPI1_DMA_CHAN_SEL + 0 + 2 + read-write + + + SPI2_DMA_CHAN_SEL + 2 + 2 + read-write + + + SPI3_DMA_CHAN_SEL + 4 + 2 + read-write + + + + + PRO_VECBASE_CTRL + 0x5AC + 0x20 + + + PRO_OUT_VECBASE_SEL + 0 + 2 + read-write + + + + + PRO_VECBASE_SET + 0x5B0 + 0x20 + + + PRO_OUT_VECBASE + 0 + 22 + read-write + + + + + APP_VECBASE_CTRL + 0x5B4 + 0x20 + + + APP_OUT_VECBASE_SEL + 0 + 2 + read-write + + + + + APP_VECBASE_SET + 0x5B8 + 0x20 + + + APP_OUT_VECBASE + 0 + 22 + read-write + + + + + DATE + 0xFFC + 0x20 + 0x01605190 + + + DATE + 0 + 28 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x3FF5A000 + + 0x0 + 0x124 + registers + + + EFUSE + 44 + + + + BLK0_RDATA0 + 0x0 + 0x20 + + + RD_EFUSE_WR_DIS + read for efuse_wr_disable + 0 + 16 + read-only + + + RD_EFUSE_RD_DIS + read for efuse_rd_disable + 16 + 4 + read-only + + + RD_FLASH_CRYPT_CNT + read for flash_crypt_cnt + 20 + 7 + read-only + + + + + BLK0_RDATA1 + 0x4 + 0x20 + + + RD_WIFI_MAC_CRC_LOW + read for low 32bit WIFI_MAC_Address + 0 + 32 + read-only + + + + + BLK0_RDATA2 + 0x8 + 0x20 + + + RD_WIFI_MAC_CRC_HIGH + read for high 24bit WIFI_MAC_Address + 0 + 24 + read-only + + + + + BLK0_RDATA3 + 0xC + 0x20 + + + RD_CHIP_VER_DIS_APP_CPU + 0 + 1 + read-only + + + RD_CHIP_VER_DIS_BT + 1 + 1 + read-only + + + RD_CHIP_VER_PKG_4BIT + most significant bit of chip package + 2 + 1 + read-only + + + RD_CHIP_VER_DIS_CACHE + 3 + 1 + read-only + + + RD_SPI_PAD_CONFIG_HD + read for SPI_pad_config_hd + 4 + 5 + read-only + + + RD_CHIP_VER_PKG + least significant bits of chip package + 9 + 3 + read-write + + + RD_CHIP_CPU_FREQ_LOW + If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise + 12 + 1 + read-write + + + RD_CHIP_CPU_FREQ_RATED + If set, the ESP32's maximum CPU frequency has been rated + 13 + 1 + read-write + + + RD_BLK3_PART_RESERVE + If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + 14 + 1 + read-write + + + RD_CHIP_VER_REV1 + bit is set to 1 for rev1 silicon + 15 + 1 + read-write + + + + + BLK0_RDATA4 + 0x10 + 0x20 + + + RD_CK8M_FREQ + 0 + 8 + read-only + + + RD_ADC_VREF + True ADC reference voltage + 8 + 5 + read-write + + + RD_SDIO_DREFH + 8 + 2 + read-only + + + RD_SDIO_DREFM + 10 + 2 + read-only + + + RD_SDIO_DREFL + 12 + 2 + read-only + + + RD_XPD_SDIO + read for XPD_SDIO_REG + 14 + 1 + read-only + + + RD_SDIO_TIEH + read for SDIO_TIEH + 15 + 1 + read-only + + + RD_SDIO_FORCE + read for sdio_force + 16 + 1 + read-only + + + + + BLK0_RDATA5 + 0x14 + 0x20 + + + RD_SPI_PAD_CONFIG_CLK + read for SPI_pad_config_clk + 0 + 5 + read-only + + + RD_SPI_PAD_CONFIG_Q + read for SPI_pad_config_q + 5 + 5 + read-only + + + RD_SPI_PAD_CONFIG_D + read for SPI_pad_config_d + 10 + 5 + read-only + + + RD_SPI_PAD_CONFIG_CS0 + read for SPI_pad_config_cs0 + 15 + 5 + read-only + + + RD_CHIP_VER_REV2 + 20 + 1 + read-only + + + RD_VOL_LEVEL_HP_INV + This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + 22 + 2 + read-only + + + RD_WAFER_VERSION_MINOR + 24 + 2 + read-only + + + RD_FLASH_CRYPT_CONFIG + read for flash_crypt_config + 28 + 4 + read-only + + + + + BLK0_RDATA6 + 0x18 + 0x20 + + + RD_CODING_SCHEME + read for coding_scheme + 0 + 2 + read-only + + + RD_CONSOLE_DEBUG_DISABLE + read for console_debug_disable + 2 + 1 + read-only + + + RD_DISABLE_SDIO_HOST + 3 + 1 + read-only + + + RD_ABS_DONE_0 + read for abstract_done_0 + 4 + 1 + read-only + + + RD_ABS_DONE_1 + read for abstract_done_1 + 5 + 1 + read-only + + + RD_DISABLE_JTAG + read for JTAG_disable + 6 + 1 + read-only + + + RD_DISABLE_DL_ENCRYPT + read for download_dis_encrypt + 7 + 1 + read-only + + + RD_DISABLE_DL_DECRYPT + read for download_dis_decrypt + 8 + 1 + read-only + + + RD_DISABLE_DL_CACHE + read for download_dis_cache + 9 + 1 + read-only + + + RD_KEY_STATUS + read for key_status + 10 + 1 + read-only + + + + + BLK0_WDATA0 + 0x1C + 0x20 + + + WR_DIS + program for efuse_wr_disable + 0 + 16 + read-write + + + RD_DIS + program for efuse_rd_disable + 16 + 4 + read-write + + + FLASH_CRYPT_CNT + program for flash_crypt_cnt + 20 + 7 + read-write + + + + + BLK0_WDATA1 + 0x20 + 0x20 + + + WIFI_MAC_CRC_LOW + program for low 32bit WIFI_MAC_Address + 0 + 32 + read-write + + + + + BLK0_WDATA2 + 0x24 + 0x20 + + + WIFI_MAC_CRC_HIGH + program for high 24bit WIFI_MAC_Address + 0 + 24 + read-write + + + + + BLK0_WDATA3 + 0x28 + 0x20 + + + CHIP_VER_DIS_APP_CPU + 0 + 1 + read-write + + + CHIP_VER_DIS_BT + 1 + 1 + read-write + + + CHIP_VER_PKG_4BIT + most significant bit of chip package + 2 + 1 + read-only + + + CHIP_VER_DIS_CACHE + 3 + 1 + read-write + + + SPI_PAD_CONFIG_HD + program for SPI_pad_config_hd + 4 + 5 + read-write + + + CHIP_VER_PKG + least significant bits of chip package + 9 + 3 + read-write + + + CHIP_CPU_FREQ_LOW + If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise + 12 + 1 + read-write + + + CHIP_CPU_FREQ_RATED + If set, the ESP32's maximum CPU frequency has been rated + 13 + 1 + read-write + + + BLK3_PART_RESERVE + If set, this bit indicates that BLOCK3[143:96] is reserved for internal use + 14 + 1 + read-write + + + CHIP_VER_REV1 + 15 + 1 + read-write + + + + + BLK0_WDATA4 + 0x2C + 0x20 + + + CK8M_FREQ + 0 + 8 + read-write + + + ADC_VREF + True ADC reference voltage + 8 + 5 + read-write + + + SDIO_DREFH + 8 + 2 + read-write + + + SDIO_DREFM + 10 + 2 + read-write + + + SDIO_DREFL + 12 + 2 + read-write + + + XPD_SDIO + program for XPD_SDIO_REG + 14 + 1 + read-write + + + SDIO_TIEH + program for SDIO_TIEH + 15 + 1 + read-write + + + SDIO_FORCE + program for sdio_force + 16 + 1 + read-write + + + + + BLK0_WDATA5 + 0x30 + 0x20 + + + SPI_PAD_CONFIG_CLK + program for SPI_pad_config_clk + 0 + 5 + read-write + + + SPI_PAD_CONFIG_Q + program for SPI_pad_config_q + 5 + 5 + read-write + + + SPI_PAD_CONFIG_D + program for SPI_pad_config_d + 10 + 5 + read-write + + + SPI_PAD_CONFIG_CS0 + program for SPI_pad_config_cs0 + 15 + 5 + read-write + + + INST_CONFIG + 20 + 8 + read-write + + + VOL_LEVEL_HP_INV + This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W) + 22 + 2 + read-write + + + DIG_VOL_L6 + 24 + 4 + read-write + + + FLASH_CRYPT_CONFIG + program for flash_crypt_config + 28 + 4 + read-write + + + + + BLK0_WDATA6 + 0x34 + 0x20 + + + CODING_SCHEME + program for coding_scheme + 0 + 2 + read-write + + + CONSOLE_DEBUG_DISABLE + program for console_debug_disable + 2 + 1 + read-write + + + DISABLE_SDIO_HOST + 3 + 1 + read-write + + + ABS_DONE_0 + program for abstract_done_0 + 4 + 1 + read-write + + + ABS_DONE_1 + program for abstract_done_1 + 5 + 1 + read-write + + + DISABLE_JTAG + program for JTAG_disable + 6 + 1 + read-write + + + DISABLE_DL_ENCRYPT + program for download_dis_encrypt + 7 + 1 + read-write + + + DISABLE_DL_DECRYPT + program for download_dis_decrypt + 8 + 1 + read-write + + + DISABLE_DL_CACHE + program for download_dis_cache + 9 + 1 + read-write + + + KEY_STATUS + program for key_status + 10 + 1 + read-write + + + + + BLK1_RDATA0 + 0x38 + 0x20 + + + BLK1_DOUT0 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA1 + 0x3C + 0x20 + + + BLK1_DOUT1 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA2 + 0x40 + 0x20 + + + BLK1_DOUT2 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA3 + 0x44 + 0x20 + + + BLK1_DOUT3 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA4 + 0x48 + 0x20 + + + BLK1_DOUT4 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA5 + 0x4C + 0x20 + + + BLK1_DOUT5 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA6 + 0x50 + 0x20 + + + BLK1_DOUT6 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK1_RDATA7 + 0x54 + 0x20 + + + BLK1_DOUT7 + read for BLOCK1 + 0 + 32 + read-only + + + + + BLK2_RDATA0 + 0x58 + 0x20 + + + BLK2_DOUT0 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA1 + 0x5C + 0x20 + + + BLK2_DOUT1 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA2 + 0x60 + 0x20 + + + BLK2_DOUT2 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA3 + 0x64 + 0x20 + + + BLK2_DOUT3 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA4 + 0x68 + 0x20 + + + BLK2_DOUT4 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA5 + 0x6C + 0x20 + + + BLK2_DOUT5 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA6 + 0x70 + 0x20 + + + BLK2_DOUT6 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK2_RDATA7 + 0x74 + 0x20 + + + BLK2_DOUT7 + read for BLOCK2 + 0 + 32 + read-only + + + + + BLK3_RDATA0 + 0x78 + 0x20 + + + BLK3_DOUT0 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK3_RDATA1 + 0x7C + 0x20 + + + BLK3_DOUT1 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK3_RDATA2 + 0x80 + 0x20 + + + BLK3_DOUT2 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK3_RDATA3 + 0x84 + 0x20 + + + BLK3_DOUT3 + read for BLOCK3 + 0 + 32 + read-only + + + RD_ADC1_TP_LOW + ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 0 + 7 + read-write + + + RD_ADC1_TP_HIGH + ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 7 + 9 + read-write + + + RD_ADC2_TP_LOW + ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 16 + 7 + read-write + + + RD_ADC2_TP_HIGH + ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 23 + 9 + read-write + + + + + BLK3_RDATA4 + 0x88 + 0x20 + + + BLK3_DOUT4 + read for BLOCK3 + 0 + 32 + read-only + + + RD_CAL_RESERVED + Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE + 0 + 16 + read-write + + + + + BLK3_RDATA5 + 0x8C + 0x20 + + + BLK3_DOUT5 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK3_RDATA6 + 0x90 + 0x20 + + + BLK3_DOUT6 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK3_RDATA7 + 0x94 + 0x20 + + + BLK3_DOUT7 + read for BLOCK3 + 0 + 32 + read-only + + + + + BLK1_WDATA0 + 0x98 + 0x20 + + + BLK1_DIN0 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA1 + 0x9C + 0x20 + + + BLK1_DIN1 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA2 + 0xA0 + 0x20 + + + BLK1_DIN2 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA3 + 0xA4 + 0x20 + + + BLK1_DIN3 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA4 + 0xA8 + 0x20 + + + BLK1_DIN4 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA5 + 0xAC + 0x20 + + + BLK1_DIN5 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA6 + 0xB0 + 0x20 + + + BLK1_DIN6 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK1_WDATA7 + 0xB4 + 0x20 + + + BLK1_DIN7 + program for BLOCK1 + 0 + 32 + read-write + + + + + BLK2_WDATA0 + 0xB8 + 0x20 + + + BLK2_DIN0 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA1 + 0xBC + 0x20 + + + BLK2_DIN1 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA2 + 0xC0 + 0x20 + + + BLK2_DIN2 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA3 + 0xC4 + 0x20 + + + BLK2_DIN3 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA4 + 0xC8 + 0x20 + + + BLK2_DIN4 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA5 + 0xCC + 0x20 + + + BLK2_DIN5 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA6 + 0xD0 + 0x20 + + + BLK2_DIN6 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK2_WDATA7 + 0xD4 + 0x20 + + + BLK2_DIN7 + program for BLOCK2 + 0 + 32 + read-write + + + + + BLK3_WDATA0 + 0xD8 + 0x20 + + + BLK3_DIN0 + program for BLOCK3 + 0 + 32 + read-write + + + + + BLK3_WDATA1 + 0xDC + 0x20 + + + BLK3_DIN1 + program for BLOCK3 + 0 + 32 + read-write + + + + + BLK3_WDATA2 + 0xE0 + 0x20 + + + BLK3_DIN2 + program for BLOCK3 + 0 + 32 + read-write + + + + + BLK3_WDATA3 + 0xE4 + 0x20 + + + BLK3_DIN3 + program for BLOCK3 + 0 + 32 + read-write + + + ADC1_TP_LOW + ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 0 + 7 + read-write + + + ADC1_TP_HIGH + ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 7 + 9 + read-write + + + ADC2_TP_LOW + ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 16 + 7 + read-write + + + ADC2_TP_HIGH + ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE + 23 + 9 + read-write + + + + + BLK3_WDATA4 + 0xE8 + 0x20 + + + BLK3_DIN4 + program for BLOCK3 + 0 + 32 + read-write + + + CAL_RESERVED + Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE + 0 + 16 + read-write + + + + + BLK3_WDATA5 + 0xEC + 0x20 + + + BLK3_DIN5 + program for BLOCK3 + 0 + 32 + read-write + + + + + BLK3_WDATA6 + 0xF0 + 0x20 + + + BLK3_DIN6 + program for BLOCK3 + 0 + 32 + read-write + + + + + BLK3_WDATA7 + 0xF4 + 0x20 + + + BLK3_DIN7 + program for BLOCK3 + 0 + 32 + read-write + + + + + CLK + 0xF8 + 0x20 + 0x00004052 + + + SEL0 + efuse timing configure + 0 + 8 + read-write + + + SEL1 + efuse timing configure + 8 + 8 + read-write + + + EN + 16 + 1 + read-write + + + + + CONF + 0xFC + 0x20 + 0x00010000 + + + OP_CODE + efuse operation code + 0 + 16 + read-write + + + FORCE_NO_WR_RD_DIS + 16 + 1 + read-write + + + + + STATUS + 0x100 + 0x20 + + + DEBUG + 0 + 32 + read-only + + + + + CMD + 0x104 + 0x20 + + + READ_CMD + command for read + 0 + 1 + read-write + + + PGM_CMD + command for program + 1 + 1 + read-write + + + + + INT_RAW + 0x108 + 0x20 + + + READ_DONE_INT_RAW + read done interrupt raw status + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + program done interrupt raw status + 1 + 1 + read-only + + + + + INT_ST + 0x10C + 0x20 + + + READ_DONE_INT_ST + read done interrupt status + 0 + 1 + read-only + + + PGM_DONE_INT_ST + program done interrupt status + 1 + 1 + read-only + + + + + INT_ENA + 0x110 + 0x20 + + + READ_DONE_INT_ENA + read done interrupt enable + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + program done interrupt enable + 1 + 1 + read-write + + + + + INT_CLR + 0x114 + 0x20 + + + READ_DONE_INT_CLR + read done interrupt clear + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + program done interrupt clear + 1 + 1 + write-only + + + + + DAC_CONF + 0x118 + 0x20 + 0x00000028 + + + DAC_CLK_DIV + efuse timing configure + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + 8 + 1 + read-write + + + + + DEC_STATUS + 0x11C + 0x20 + + + DEC_WARNINGS + the decode result of 3/4 coding scheme has warning + 0 + 12 + read-only + + + + + DATE + 0x1FC + 0x20 + 0x16042600 + + + DATE + 0 + 32 + read-write + + + + + + + FLASH_ENCRYPTION + Flash Encryption Peripheral + FLASH_ENCRYPTION + 0x3FF46000 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + BUFFER_%s + 0x0 + 0x20 + + + BUFFER + Data buffers for encryption. + 0 + 8 + write-only + + + + + START + 0x20 + 0x20 + + + FLASH_START + Set this bit to start encryption operation on data buffer. + 0 + 8 + write-only + + + + + ADDRESS + 0x24 + 0x20 + + + ADDRESS + The physical address on the off-chip flash must be 8-word boundary aligned. + 0 + 8 + write-only + + + + + DONE + 0x28 + 0x20 + + + FLASH_DONE + Set this bit when encryption operation is complete. + 0 + 1 + read-only + + + + + + + FRC_TIMER + Peripheral FRC_TIMER + FRC + 0x3FF47000 + + 0x0 + 0x14 + registers + + + + TIMER_LOAD + 0x0 + 0x20 + + + VALUE + 0 + 8 + read-write + + + + + TIMER_COUNT + 0x4 + 0x20 + + + TIMER_COUNT + 0 + 8 + read-write + + + + + TIMER_CTRL + 0x8 + 0x20 + + + TIMER_PRESCALER + 1 + 8 + read-write + + + + + TIMER_INT + 0xC + 0x20 + + + CLR + 0 + 1 + read-write + + + + + TIMER_ALARM + 0x10 + 0x20 + + + TIMER_ALARM + 0 + 8 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x3FF44000 + + 0x0 + 0x5CC + registers + + + GPIO + 22 + + + GPIO_NMI + 23 + + + + BT_SELECT + 0x0 + 0x20 + + + BT_SEL + NA + 0 + 32 + read-write + + + + + OUT + 0x4 + 0x20 + + + DATA + GPIO0~31 output value + 0 + 32 + read-write + + + + + OUT_W1TS + 0x8 + 0x20 + + + OUT_DATA_W1TS + GPIO0~31 output value write 1 to set + 0 + 32 + read-write + + + + + OUT_W1TC + 0xC + 0x20 + + + OUT_DATA_W1TC + GPIO0~31 output value write 1 to clear + 0 + 32 + read-write + + + + + OUT1 + 0x10 + 0x20 + + + DATA + GPIO32~39 output value + 0 + 8 + read-write + + + + + OUT1_W1TS + 0x14 + 0x20 + + + OUT1_DATA_W1TS + GPIO32~39 output value write 1 to set + 0 + 8 + read-write + + + + + OUT1_W1TC + 0x18 + 0x20 + + + OUT1_DATA_W1TC + GPIO32~39 output value write 1 to clear + 0 + 8 + read-write + + + + + SDIO_SELECT + 0x1C + 0x20 + + + SDIO_SEL + SDIO PADS on/off control from outside + 0 + 8 + read-write + + + + + ENABLE + 0x20 + 0x20 + + + DATA + GPIO0~31 output enable + 0 + 32 + read-write + + + + + ENABLE_W1TS + 0x24 + 0x20 + + + ENABLE_DATA_W1TS + GPIO0~31 output enable write 1 to set + 0 + 32 + read-write + + + + + ENABLE_W1TC + 0x28 + 0x20 + + + ENABLE_DATA_W1TC + GPIO0~31 output enable write 1 to clear + 0 + 32 + read-write + + + + + ENABLE1 + 0x2C + 0x20 + + + DATA + GPIO32~39 output enable + 0 + 8 + read-write + + + + + ENABLE1_W1TS + 0x30 + 0x20 + + + ENABLE1_DATA_W1TS + GPIO32~39 output enable write 1 to set + 0 + 8 + read-write + + + + + ENABLE1_W1TC + 0x34 + 0x20 + + + ENABLE1_DATA_W1TC + GPIO32~39 output enable write 1 to clear + 0 + 8 + read-write + + + + + STRAP + 0x38 + 0x20 + + + STRAPPING + {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} + 0 + 16 + read-only + + + + + IN + 0x3C + 0x20 + + + DATA_NEXT + GPIO0~31 input value + 0 + 32 + read-write + + + + + IN1 + 0x40 + 0x20 + + + DATA_NEXT + GPIO32~39 input value + 0 + 8 + read-write + + + + + STATUS + 0x44 + 0x20 + + + INT + GPIO0~31 interrupt status + 0 + 32 + read-write + + + + + STATUS_W1TS + 0x48 + 0x20 + + + STATUS_INT_W1TS + GPIO0~31 interrupt status write 1 to set + 0 + 32 + read-write + + + + + STATUS_W1TC + 0x4C + 0x20 + + + STATUS_INT_W1TC + GPIO0~31 interrupt status write 1 to clear + 0 + 32 + read-write + + + + + STATUS1 + 0x50 + 0x20 + + + INT + GPIO32~39 interrupt status + 0 + 8 + read-write + + + + + STATUS1_W1TS + 0x54 + 0x20 + + + STATUS1_INT_W1TS + GPIO32~39 interrupt status write 1 to set + 0 + 8 + read-write + + + + + STATUS1_W1TC + 0x58 + 0x20 + + + STATUS1_INT_W1TC + GPIO32~39 interrupt status write 1 to clear + 0 + 8 + read-write + + + + + ACPU_INT + 0x60 + 0x20 + + + APPCPU_INT + GPIO0~31 APP CPU interrupt status + 0 + 32 + read-only + + + + + ACPU_NMI_INT + 0x64 + 0x20 + + + APPCPU_NMI_INT + GPIO0~31 APP CPU non-maskable interrupt status + 0 + 32 + read-only + + + + + PCPU_INT + 0x68 + 0x20 + + + PROCPU_INT + GPIO0~31 PRO CPU interrupt status + 0 + 32 + read-only + + + + + PCPU_NMI_INT + 0x6C + 0x20 + + + PROCPU_NMI_INT + GPIO0~31 PRO CPU non-maskable interrupt status + 0 + 32 + read-only + + + + + CPUSDIO_INT + 0x70 + 0x20 + + + SDIO_INT + SDIO's extent GPIO0~31 interrupt + 0 + 32 + read-only + + + + + ACPU_INT1 + 0x74 + 0x20 + + + APPCPU_INT_H + GPIO32~39 APP CPU interrupt status + 0 + 8 + read-only + + + + + ACPU_NMI_INT1 + 0x78 + 0x20 + + + APPCPU_NMI_INT_H + GPIO32~39 APP CPU non-maskable interrupt status + 0 + 8 + read-only + + + + + PCPU_INT1 + 0x7C + 0x20 + + + PROCPU_INT_H + GPIO32~39 PRO CPU interrupt status + 0 + 8 + read-only + + + + + PCPU_NMI_INT1 + 0x80 + 0x20 + + + PROCPU_NMI_INT_H + GPIO32~39 PRO CPU non-maskable interrupt status + 0 + 8 + read-only + + + + + CPUSDIO_INT1 + 0x84 + 0x20 + + + SDIO_INT_H + SDIO's extent GPIO32~39 interrupt + 0 + 8 + read-only + + + PIN_PAD_DRIVER + 2 + 1 + read-write + + + PIN_INT_TYPE + 7 + 3 + read-write + + + PIN_WAKEUP_ENABLE + 10 + 1 + read-write + + + PIN_CONFIG + 11 + 2 + read-write + + + PIN_INT_ENA + 13 + 5 + read-write + + + + + 40 + 0x4 + 0-39 + PIN%s + 0x88 + 0x20 + + + PAD_DRIVER + if set to 0: normal output if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + GPIO wake up enable only available in light sleep + 10 + 1 + read-write + + + CONFIG + NA + 11 + 2 + read-write + + + INT_ENA + bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable + 13 + 5 + read-write + + + + + cali_conf + 0x128 + 0x20 + + + CALI_RTC_MAX + 0 + 10 + read-write + + + CALI_START + 31 + 1 + read-write + + + + + cali_data + 0x12C + 0x20 + + + CALI_VALUE_SYNC2 + 0 + 20 + read-only + + + CALI_RDY_REAL + 30 + 1 + read-only + + + CALI_RDY_SYNC2 + 31 + 1 + read-only + + + + + 256 + 0x4 + 0-255 + FUNC%s_IN_SEL_CFG + 0x130 + 0x20 + + + IN_SEL + select one of the 256 inputs + 0 + 6 + read-write + + + IN_INV_SEL + revert the value of the input if you want to revert please set the value to 1 + 6 + 1 + read-write + + + SEL + if the slow signal bypass the io matrix or not if you want setting the value to 1 + 7 + 1 + read-write + + + + + 40 + 0x4 + 0-39 + FUNC%s_OUT_SEL_CFG + 0x530 + 0x20 + + + OUT_SEL + select one of the 256 output to 40 GPIO + 0 + 9 + read-write + + + INV_SEL + invert the output value if you want to revert the output value setting the value to 1 + 9 + 1 + read-write + + + OEN_SEL + weather using the logical oen signal or not using the value setting by the register + 10 + 1 + read-write + + + OEN_INV_SEL + invert the output enable value if you want to revert the output enable value setting the value to 1 + 11 + 1 + read-write + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIO_SIGMADELTA + 0x3FF44F00 + + 0x0 + 0x2C + registers + + + + SIGMADELTA0 + 0x0 + 0x20 + 0x0000FF00 + + + SD0_IN + 0 + 8 + read-write + + + SD0_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA1 + 0x4 + 0x20 + 0x0000FF00 + + + SD1_IN + 0 + 8 + read-write + + + SD1_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA2 + 0x8 + 0x20 + 0x0000FF00 + + + SD2_IN + 0 + 8 + read-write + + + SD2_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA3 + 0xC + 0x20 + 0x0000FF00 + + + SD3_IN + 0 + 8 + read-write + + + SD3_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA4 + 0x10 + 0x20 + 0x0000FF00 + + + SD4_IN + 0 + 8 + read-write + + + SD4_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA5 + 0x14 + 0x20 + 0x0000FF00 + + + SD5_IN + 0 + 8 + read-write + + + SD5_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA6 + 0x18 + 0x20 + 0x0000FF00 + + + SD6_IN + 0 + 8 + read-write + + + SD6_PRESCALE + 8 + 8 + read-write + + + + + SIGMADELTA7 + 0x1C + 0x20 + 0x0000FF00 + + + SD7_IN + 0 + 8 + read-write + + + SD7_PRESCALE + 8 + 8 + read-write + + + + + CG + 0x20 + 0x20 + + + SD_CLK_EN + 31 + 1 + read-write + + + + + MISC + 0x24 + 0x20 + + + SPI_SWAP + 31 + 1 + read-write + + + + + VERSION + 0x28 + 0x20 + 0x01506190 + + + SD_DATE + 0 + 28 + read-write + + + + + + + HINF + Peripheral HINF + HINF + 0x3FF4B000 + + 0x0 + 0x34 + registers + + + + CFG_DATA0 + 0x0 + 0x20 + 0x22226666 + + + USER_ID_FN1 + 0 + 16 + read-write + + + DEVICE_ID_FN1 + 16 + 16 + read-write + + + + + CFG_DATA1 + 0x4 + 0x20 + 0x01110011 + + + SDIO_ENABLE + 0 + 1 + read-write + + + SDIO_IOREADY1 + 1 + 1 + read-write + + + HIGHSPEED_ENABLE + 2 + 1 + read-write + + + HIGHSPEED_MODE + 3 + 1 + read-only + + + SDIO_CD_ENABLE + 4 + 1 + read-write + + + SDIO_IOREADY2 + 5 + 1 + read-write + + + SDIO_INT_MASK + 6 + 1 + read-write + + + IOENABLE2 + 7 + 1 + read-only + + + CD_DISABLE + 8 + 1 + read-only + + + FUNC1_EPS + 9 + 1 + read-only + + + EMP + 10 + 1 + read-only + + + IOENABLE1 + 11 + 1 + read-only + + + SDIO20_CONF0 + 12 + 4 + read-write + + + SDIO_VER + 16 + 12 + read-write + + + FUNC2_EPS + 28 + 1 + read-only + + + SDIO20_CONF1 + 29 + 3 + read-write + + + + + CFG_DATA7 + 0x1C + 0x20 + 0x00020000 + + + PIN_STATE + 0 + 8 + read-write + + + CHIP_STATE + 8 + 8 + read-write + + + SDIO_RST + 16 + 1 + read-write + + + SDIO_IOREADY0 + 17 + 1 + read-write + + + + + CIS_CONF0 + 0x20 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W0 + 0 + 32 + read-write + + + + + CIS_CONF1 + 0x24 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W1 + 0 + 32 + read-write + + + + + CIS_CONF2 + 0x28 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W2 + 0 + 32 + read-write + + + + + CIS_CONF3 + 0x2C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W3 + 0 + 32 + read-write + + + + + CIS_CONF4 + 0x30 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W4 + 0 + 32 + read-write + + + + + CIS_CONF5 + 0x34 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W5 + 0 + 32 + read-write + + + + + CIS_CONF6 + 0x38 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W6 + 0 + 32 + read-write + + + + + CIS_CONF7 + 0x3C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W7 + 0 + 32 + read-write + + + + + CFG_DATA16 + 0x40 + 0x20 + 0x33336666 + + + USER_ID_FN2 + 0 + 16 + read-write + + + DEVICE_ID_FN2 + 16 + 16 + read-write + + + + + DATE + 0xFC + 0x20 + 0x15030200 + + + SDIO_DATE + 0 + 32 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x3FF53000 + + 0x0 + 0x9C + registers + + + I2C_EXT0 + 49 + + + + SCL_LOW_PERIOD + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure the low level width of SCL clock. + 0 + 14 + read-write + + + + + CTR + 0x4 + 0x20 + 0x00000003 + + + SDA_FORCE_OUT + 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal) + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal) + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. + 2 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending data in txfifo. + 5 + 1 + read-write + + + TX_LSB_FIRST + This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit + 7 + 1 + read-write + + + CLK_EN + This is the clock gating control bit for reading or writing registers. + 8 + 1 + read-write + + + + + SR + 0x8 + 0x20 + + + ACK_REC + This register stores the value of ACK bit. + 0 + 1 + read-only + + + SLAVE_RW + when in slave mode 1: master read slave 0: master write slave. + 1 + 1 + read-only + + + TIME_OUT + when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. + 2 + 1 + read-only + + + ARB_LOST + when I2C lost control of SDA line this register changes to high level. + 3 + 1 + read-only + + + BUS_BUSY + 1:I2C bus is busy transferring data. 0:I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level. + 5 + 1 + read-only + + + BYTE_TRANS + This register changes to high level when one byte is transferred. + 6 + 1 + read-only + + + RXFIFO_CNT + This register represent the amount of data need to send. + 8 + 6 + read-only + + + TXFIFO_CNT + This register stores the amount of received data in ram. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP + 28 + 3 + read-only + + + + + TO + 0xC + 0x20 + + + TIME_OUT + This register is used to configure the max clock number of receiving a data. + 0 + 20 + read-write + + + + + SLAVE_ADDR + 0x10 + 0x20 + + + SLAVE_ADDR + when configured as i2c slave this register is used to configure slave's address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This register is used to enable slave 10bit address mode. + 31 + 1 + read-write + + + + + RXFIFO_ST + 0x14 + 0x20 + + + RXFIFO_START_ADDR + This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. + 0 + 5 + read-only + + + RXFIFO_END_ADDR + This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. + 5 + 5 + read-only + + + TXFIFO_START_ADDR + This is the offset address of the first sending data as described in nonfifo_tx_thres register. + 10 + 5 + read-only + + + TXFIFO_END_ADDR + This is the offset address of the last sending data as described in nonfifo_tx_thres register. + 15 + 5 + read-only + + + + + FIFO_CONF + 0x18 + 0x20 + 0x0155408B + + + RXFIFO_FULL_THRHD + 0 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + Config txfifo empty threhd value when using apb fifo access + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enble apb nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx fifo when using apb fifo access. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx fifo when using apb fifo access. + 13 + 1 + read-write + + + NONFIFO_RX_THRES + when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. + 14 + 6 + read-write + + + NONFIFO_TX_THRES + when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. + 20 + 6 + read-write + + + + + DATA + 0x1C + 0x20 + + + FIFO_RDATA + The register represent the byte data read from rxfifo when use apb fifo access + 0 + 8 + read-only + + + + + INT_RAW + 0x20 + 0x20 + + + RXFIFO_FULL_INT_RAW + The raw interrupt status bit for rxfifo full when use apb fifo access. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + The raw interrupt status bit for txfifo empty when use apb fifo access. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status bit for receiving data overflow when use apb fifo access. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. + 3 + 1 + read-only + + + SLAVE_TRAN_COMP_INT_RAW + The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. + 5 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. + 9 + 1 + read-only + + + ACK_ERR_INT_RAW + The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. + 10 + 1 + read-only + + + RX_REC_FULL_INT_RAW + The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. + 11 + 1 + read-only + + + TX_SEND_EMPTY_INT_RAW + The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. + 12 + 1 + read-only + + + + + INT_CLR + 0x24 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear the txfifo_empty_int interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear the rxfifo_ovf_int interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the end_detect_int interrupt. + 3 + 1 + write-only + + + SLAVE_TRAN_COMP_INT_CLR + Set this bit to clear the slave_tran_comp_int interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the arbitration_lost_int interrupt. + 5 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + Set this bit to clear the master_tran_comp interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the trans_complete_int interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the time_out_int interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the trans_start_int interrupt. + 9 + 1 + write-only + + + ACK_ERR_INT_CLR + Set this bit to clear the ack_err_int interrupt. + 10 + 1 + write-only + + + RX_REC_FULL_INT_CLR + Set this bit to clear the rx_rec_full_int interrupt. + 11 + 1 + write-only + + + TX_SEND_EMPTY_INT_CLR + Set this bit to clear the tx_send_empty_int interrupt. + 12 + 1 + write-only + + + + + INT_ENA + 0x28 + 0x20 + + + RXFIFO_FULL_INT_ENA + The enable bit for rxfifo_full_int interrupt. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + The enable bit for txfifo_empty_int interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The enable bit for rxfifo_ovf_int interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The enable bit for end_detect_int interrupt. + 3 + 1 + read-write + + + SLAVE_TRAN_COMP_INT_ENA + The enable bit for slave_tran_comp_int interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The enable bit for arbitration_lost_int interrupt. + 5 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + The enable bit for master_tran_comp_int interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The enable bit for trans_complete_int interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The enable bit for time_out_int interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The enable bit for trans_start_int interrupt. + 9 + 1 + read-write + + + ACK_ERR_INT_ENA + The enable bit for ack_err_int interrupt. + 10 + 1 + read-write + + + RX_REC_FULL_INT_ENA + The enable bit for rx_rec_full_int interrupt. + 11 + 1 + read-write + + + TX_SEND_EMPTY_INT_ENA + The enable bit for tx_send_empty_int interrupt. + 12 + 1 + read-write + + + + + INT_STATUS + 0x2C + 0x20 + + + RXFIFO_FULL_INT_ST + The masked interrupt status for rxfifo_full_int interrupt. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + The masked interrupt status for txfifo_empty_int interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status for rxfifo_ovf_int interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status for end_detect_int interrupt. + 3 + 1 + read-only + + + SLAVE_TRAN_COMP_INT_ST + The masked interrupt status for slave_tran_comp_int interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status for arbitration_lost_int interrupt. + 5 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + The masked interrupt status for master_tran_comp_int interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status for trans_complete_int interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status for time_out_int interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status for trans_start_int interrupt. + 9 + 1 + read-only + + + ACK_ERR_INT_ST + The masked interrupt status for ack_err_int interrupt. + 10 + 1 + read-only + + + RX_REC_FULL_INT_ST + The masked interrupt status for rx_rec_full_int interrupt. + 11 + 1 + read-only + + + TX_SEND_EMPTY_INT_ST + The masked interrupt status for tx_send_empty_int interrupt. + 12 + 1 + read-only + + + + + SDA_HOLD + 0x30 + 0x20 + + + TIME + This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. + 0 + 10 + read-write + + + + + SDA_SAMPLE + 0x34 + 0x20 + + + TIME + This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL + 0 + 10 + read-write + + + + + SCL_HIGH_PERIOD + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure the clock num during SCL is low level. + 0 + 14 + read-write + + + + + SCL_START_HOLD + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. + 0 + 10 + read-write + + + + + SCL_RSTART_SETUP + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. + 0 + 10 + read-write + + + + + SCL_STOP_HOLD + 0x48 + 0x20 + + + TIME + This register is used to configure the clock num after the STOP bit's posedge. + 0 + 14 + read-write + + + + + SCL_STOP_SETUP + 0x4C + 0x20 + + + TIME + This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. + 0 + 10 + read-write + + + + + SCL_FILTER_CFG + 0x50 + 0x20 + 0x00000008 + + + SCL_FILTER_THRES + When input SCL's pulse width is smaller than this register value I2C ignores this pulse. + 0 + 3 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 3 + 1 + read-write + + + + + SDA_FILTER_CFG + 0x54 + 0x20 + 0x00000008 + + + SDA_FILTER_THRES + When input SCL's pulse width is smaller than this register value I2C ignores this pulse. + 0 + 3 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 3 + 1 + read-write + + + + + 16 + 0x4 + 0-15 + COMD%s + 0x58 + 0x20 + + + COMMAND + This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit. + 0 + 14 + read-write + + + COMMAND_DONE + When command0 is done in I2C Master mode this bit changes to high level. + 31 + 1 + read-write + + + + + DATE + 0xF8 + 0x20 + 0x16042000 + + + DATE + 0 + 32 + read-write + + + + + FIFO_START_ADDR + 0x100 + 0x20 + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller + 0x3FF67000 + + I2C_EXT1 + 50 + + + + I2S0 + I2S (Inter-IC Sound) Controller + I2S + 0x3FF4F000 + + 0x0 + 0xB4 + registers + + + I2S0 + 32 + + + + CONF + 0x8 + 0x20 + 0x00030300 + + + TX_RESET + 0 + 1 + read-write + + + RX_RESET + 1 + 1 + read-write + + + TX_FIFO_RESET + 2 + 1 + read-write + + + RX_FIFO_RESET + 3 + 1 + read-write + + + TX_START + 4 + 1 + read-write + + + RX_START + 5 + 1 + read-write + + + TX_SLAVE_MOD + 6 + 1 + read-write + + + RX_SLAVE_MOD + 7 + 1 + read-write + + + TX_RIGHT_FIRST + 8 + 1 + read-write + + + RX_RIGHT_FIRST + 9 + 1 + read-write + + + TX_MSB_SHIFT + 10 + 1 + read-write + + + RX_MSB_SHIFT + 11 + 1 + read-write + + + TX_SHORT_SYNC + 12 + 1 + read-write + + + RX_SHORT_SYNC + 13 + 1 + read-write + + + TX_MONO + 14 + 1 + read-write + + + RX_MONO + 15 + 1 + read-write + + + TX_MSB_RIGHT + 16 + 1 + read-write + + + RX_MSB_RIGHT + 17 + 1 + read-write + + + SIG_LOOPBACK + 18 + 1 + read-write + + + + + INT_RAW + 0xC + 0x20 + + + RX_TAKE_DATA_INT_RAW + 0 + 1 + read-only + + + TX_PUT_DATA_INT_RAW + 1 + 1 + read-only + + + RX_WFULL_INT_RAW + 2 + 1 + read-only + + + RX_REMPTY_INT_RAW + 3 + 1 + read-only + + + TX_WFULL_INT_RAW + 4 + 1 + read-only + + + TX_REMPTY_INT_RAW + 5 + 1 + read-only + + + RX_HUNG_INT_RAW + 6 + 1 + read-only + + + TX_HUNG_INT_RAW + 7 + 1 + read-only + + + IN_DONE_INT_RAW + 8 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + 9 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + 10 + 1 + read-only + + + OUT_DONE_INT_RAW + 11 + 1 + read-only + + + OUT_EOF_INT_RAW + 12 + 1 + read-only + + + IN_DSCR_ERR_INT_RAW + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_RAW + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_RAW + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + 16 + 1 + read-only + + + + + INT_ST + 0x10 + 0x20 + + + RX_TAKE_DATA_INT_ST + 0 + 1 + read-only + + + TX_PUT_DATA_INT_ST + 1 + 1 + read-only + + + RX_WFULL_INT_ST + 2 + 1 + read-only + + + RX_REMPTY_INT_ST + 3 + 1 + read-only + + + TX_WFULL_INT_ST + 4 + 1 + read-only + + + TX_REMPTY_INT_ST + 5 + 1 + read-only + + + RX_HUNG_INT_ST + 6 + 1 + read-only + + + TX_HUNG_INT_ST + 7 + 1 + read-only + + + IN_DONE_INT_ST + 8 + 1 + read-only + + + IN_SUC_EOF_INT_ST + 9 + 1 + read-only + + + IN_ERR_EOF_INT_ST + 10 + 1 + read-only + + + OUT_DONE_INT_ST + 11 + 1 + read-only + + + OUT_EOF_INT_ST + 12 + 1 + read-only + + + IN_DSCR_ERR_INT_ST + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_ST + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_ST + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + 16 + 1 + read-only + + + + + INT_ENA + 0x14 + 0x20 + + + RX_TAKE_DATA_INT_ENA + 0 + 1 + read-write + + + TX_PUT_DATA_INT_ENA + 1 + 1 + read-write + + + RX_WFULL_INT_ENA + 2 + 1 + read-write + + + RX_REMPTY_INT_ENA + 3 + 1 + read-write + + + TX_WFULL_INT_ENA + 4 + 1 + read-write + + + TX_REMPTY_INT_ENA + 5 + 1 + read-write + + + RX_HUNG_INT_ENA + 6 + 1 + read-write + + + TX_HUNG_INT_ENA + 7 + 1 + read-write + + + IN_DONE_INT_ENA + 8 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + 9 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + 10 + 1 + read-write + + + OUT_DONE_INT_ENA + 11 + 1 + read-write + + + OUT_EOF_INT_ENA + 12 + 1 + read-write + + + IN_DSCR_ERR_INT_ENA + 13 + 1 + read-write + + + OUT_DSCR_ERR_INT_ENA + 14 + 1 + read-write + + + IN_DSCR_EMPTY_INT_ENA + 15 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + 16 + 1 + read-write + + + + + INT_CLR + 0x18 + 0x20 + + + TAKE_DATA_INT_CLR + 0 + 1 + write-only + + + PUT_DATA_INT_CLR + 1 + 1 + write-only + + + RX_WFULL_INT_CLR + 2 + 1 + write-only + + + RX_REMPTY_INT_CLR + 3 + 1 + write-only + + + TX_WFULL_INT_CLR + 4 + 1 + write-only + + + TX_REMPTY_INT_CLR + 5 + 1 + write-only + + + RX_HUNG_INT_CLR + 6 + 1 + write-only + + + TX_HUNG_INT_CLR + 7 + 1 + write-only + + + IN_DONE_INT_CLR + 8 + 1 + write-only + + + IN_SUC_EOF_INT_CLR + 9 + 1 + write-only + + + IN_ERR_EOF_INT_CLR + 10 + 1 + write-only + + + OUT_DONE_INT_CLR + 11 + 1 + write-only + + + OUT_EOF_INT_CLR + 12 + 1 + write-only + + + IN_DSCR_ERR_INT_CLR + 13 + 1 + write-only + + + OUT_DSCR_ERR_INT_CLR + 14 + 1 + write-only + + + IN_DSCR_EMPTY_INT_CLR + 15 + 1 + write-only + + + OUT_TOTAL_EOF_INT_CLR + 16 + 1 + write-only + + + + + TIMING + 0x1C + 0x20 + + + TX_BCK_IN_DELAY + 0 + 2 + read-write + + + TX_WS_IN_DELAY + 2 + 2 + read-write + + + RX_BCK_IN_DELAY + 4 + 2 + read-write + + + RX_WS_IN_DELAY + 6 + 2 + read-write + + + RX_SD_IN_DELAY + 8 + 2 + read-write + + + TX_BCK_OUT_DELAY + 10 + 2 + read-write + + + TX_WS_OUT_DELAY + 12 + 2 + read-write + + + TX_SD_OUT_DELAY + 14 + 2 + read-write + + + RX_WS_OUT_DELAY + 16 + 2 + read-write + + + RX_BCK_OUT_DELAY + 18 + 2 + read-write + + + TX_DSYNC_SW + 20 + 1 + read-write + + + RX_DSYNC_SW + 21 + 1 + read-write + + + DATA_ENABLE_DELAY + 22 + 2 + read-write + + + TX_BCK_IN_INV + 24 + 1 + read-write + + + + + FIFO_CONF + 0x20 + 0x20 + 0x00001820 + + + RX_DATA_NUM + 0 + 6 + read-write + + + TX_DATA_NUM + 6 + 6 + read-write + + + DSCR_EN + 12 + 1 + read-write + + + TX_FIFO_MOD + 13 + 3 + read-write + + + RX_FIFO_MOD + 16 + 3 + read-write + + + TX_FIFO_MOD_FORCE_EN + 19 + 1 + read-write + + + RX_FIFO_MOD_FORCE_EN + 20 + 1 + read-write + + + + + RXEOF_NUM + 0x24 + 0x20 + 0x00000040 + + + RX_EOF_NUM + 0 + 32 + read-write + + + + + CONF_SIGLE_DATA + 0x28 + 0x20 + + + SIGLE_DATA + 0 + 32 + read-write + + + + + CONF_CHAN + 0x2C + 0x20 + + + TX_CHAN_MOD + 0 + 3 + read-write + + + RX_CHAN_MOD + 3 + 2 + read-write + + + + + OUT_LINK + 0x30 + 0x20 + + + OUTLINK_ADDR + 0 + 20 + read-write + + + OUTLINK_STOP + 28 + 1 + read-write + + + OUTLINK_START + 29 + 1 + read-write + + + OUTLINK_RESTART + 30 + 1 + read-write + + + OUTLINK_PARK + 31 + 1 + read-only + + + + + IN_LINK + 0x34 + 0x20 + + + INLINK_ADDR + 0 + 20 + read-write + + + INLINK_STOP + 28 + 1 + read-write + + + INLINK_START + 29 + 1 + read-write + + + INLINK_RESTART + 30 + 1 + read-write + + + INLINK_PARK + 31 + 1 + read-only + + + + + OUT_EOF_DES_ADDR + 0x38 + 0x20 + + + OUT_EOF_DES_ADDR + 0 + 32 + read-only + + + + + IN_EOF_DES_ADDR + 0x3C + 0x20 + + + IN_SUC_EOF_DES_ADDR + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR + 0x40 + 0x20 + + + OUT_EOF_BFR_DES_ADDR + 0 + 32 + read-only + + + + + AHB_TEST + 0x44 + 0x20 + + + AHB_TESTMODE + 0 + 3 + read-write + + + AHB_TESTADDR + 4 + 2 + read-write + + + + + INLINK_DSCR + 0x48 + 0x20 + + + INLINK_DSCR + 0 + 32 + read-only + + + + + INLINK_DSCR_BF0 + 0x4C + 0x20 + + + INLINK_DSCR_BF0 + 0 + 32 + read-only + + + + + INLINK_DSCR_BF1 + 0x50 + 0x20 + + + INLINK_DSCR_BF1 + 0 + 32 + read-only + + + + + OUTLINK_DSCR + 0x54 + 0x20 + + + OUTLINK_DSCR + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF0 + 0x58 + 0x20 + + + OUTLINK_DSCR_BF0 + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF1 + 0x5C + 0x20 + + + OUTLINK_DSCR_BF1 + 0 + 32 + read-only + + + + + LC_CONF + 0x60 + 0x20 + 0x00000100 + + + IN_RST + 0 + 1 + read-write + + + OUT_RST + 1 + 1 + read-write + + + AHBM_FIFO_RST + 2 + 1 + read-write + + + AHBM_RST + 3 + 1 + read-write + + + OUT_LOOP_TEST + 4 + 1 + read-write + + + IN_LOOP_TEST + 5 + 1 + read-write + + + OUT_AUTO_WRBACK + 6 + 1 + read-write + + + OUT_NO_RESTART_CLR + 7 + 1 + read-write + + + OUT_EOF_MODE + 8 + 1 + read-write + + + OUTDSCR_BURST_EN + 9 + 1 + read-write + + + INDSCR_BURST_EN + 10 + 1 + read-write + + + OUT_DATA_BURST_EN + 11 + 1 + read-write + + + CHECK_OWNER + 12 + 1 + read-write + + + MEM_TRANS_EN + 13 + 1 + read-write + + + + + OUTFIFO_PUSH + 0x64 + 0x20 + + + OUTFIFO_WDATA + 0 + 9 + read-write + + + OUTFIFO_PUSH + 16 + 1 + read-write + + + + + INFIFO_POP + 0x68 + 0x20 + + + INFIFO_RDATA + 0 + 12 + read-only + + + INFIFO_POP + 16 + 1 + read-write + + + + + LC_STATE0 + 0x6C + 0x20 + + + LC_STATE0 + 0 + 32 + read-only + + + + + LC_STATE1 + 0x70 + 0x20 + + + LC_STATE1 + 0 + 32 + read-only + + + + + LC_HUNG_CONF + 0x74 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + 11 + 1 + read-write + + + + + CVSD_CONF0 + 0x80 + 0x20 + 0x80007FFF + + + CVSD_Y_MAX + 0 + 16 + read-write + + + CVSD_Y_MIN + 16 + 16 + read-write + + + + + CVSD_CONF1 + 0x84 + 0x20 + 0x000A0500 + + + CVSD_SIGMA_MAX + 0 + 16 + read-write + + + CVSD_SIGMA_MIN + 16 + 16 + read-write + + + + + CVSD_CONF2 + 0x88 + 0x20 + 0x000502A4 + + + CVSD_K + 0 + 3 + read-write + + + CVSD_J + 3 + 3 + read-write + + + CVSD_BETA + 6 + 10 + read-write + + + CVSD_H + 16 + 3 + read-write + + + + + PLC_CONF0 + 0x8C + 0x20 + 0x08A80339 + + + GOOD_PACK_MAX + 0 + 6 + read-write + + + N_ERR_SEG + 6 + 3 + read-write + + + SHIFT_RATE + 9 + 3 + read-write + + + MAX_SLIDE_SAMPLE + 12 + 8 + read-write + + + PACK_LEN_8K + 20 + 5 + read-write + + + N_MIN_ERR + 25 + 3 + read-write + + + + + PLC_CONF1 + 0x90 + 0x20 + 0xA0178A05 + + + BAD_CEF_ATTEN_PARA + 0 + 8 + read-write + + + BAD_CEF_ATTEN_PARA_SHIFT + 8 + 4 + read-write + + + BAD_OLA_WIN2_PARA_SHIFT + 12 + 4 + read-write + + + BAD_OLA_WIN2_PARA + 16 + 8 + read-write + + + SLIDE_WIN_LEN + 24 + 8 + read-write + + + + + PLC_CONF2 + 0x94 + 0x20 + 0x00000028 + + + CVSD_SEG_MOD + 0 + 2 + read-write + + + MIN_PERIOD + 2 + 5 + read-write + + + + + ESCO_CONF0 + 0x98 + 0x20 + + + ESCO_EN + 0 + 1 + read-write + + + ESCO_CHAN_MOD + 1 + 1 + read-write + + + ESCO_CVSD_DEC_PACK_ERR + 2 + 1 + read-write + + + ESCO_CVSD_PACK_LEN_8K + 3 + 5 + read-write + + + ESCO_CVSD_INF_EN + 8 + 1 + read-write + + + CVSD_DEC_START + 9 + 1 + read-write + + + CVSD_DEC_RESET + 10 + 1 + read-write + + + PLC_EN + 11 + 1 + read-write + + + PLC2DMA_EN + 12 + 1 + read-write + + + + + SCO_CONF0 + 0x9C + 0x20 + + + SCO_WITH_I2S_EN + 0 + 1 + read-write + + + SCO_NO_I2S_EN + 1 + 1 + read-write + + + CVSD_ENC_START + 2 + 1 + read-write + + + CVSD_ENC_RESET + 3 + 1 + read-write + + + + + CONF1 + 0xA0 + 0x20 + 0x00000089 + + + TX_PCM_CONF + 0 + 3 + read-write + + + TX_PCM_BYPASS + 3 + 1 + read-write + + + RX_PCM_CONF + 4 + 3 + read-write + + + RX_PCM_BYPASS + 7 + 1 + read-write + + + TX_STOP_EN + 8 + 1 + read-write + + + TX_ZEROS_RM_EN + 9 + 1 + read-write + + + + + PD_CONF + 0xA4 + 0x20 + 0x0000000A + + + FIFO_FORCE_PD + 0 + 1 + read-write + + + FIFO_FORCE_PU + 1 + 1 + read-write + + + PLC_MEM_FORCE_PD + 2 + 1 + read-write + + + PLC_MEM_FORCE_PU + 3 + 1 + read-write + + + + + CONF2 + 0xA8 + 0x20 + + + CAMERA_EN + 0 + 1 + read-write + + + LCD_TX_WRX2_EN + 1 + 1 + read-write + + + LCD_TX_SDX2_EN + 2 + 1 + read-write + + + DATA_ENABLE_TEST_EN + 3 + 1 + read-write + + + DATA_ENABLE + 4 + 1 + read-write + + + LCD_EN + 5 + 1 + read-write + + + EXT_ADC_START_EN + 6 + 1 + read-write + + + INTER_VALID_EN + 7 + 1 + read-write + + + + + CLKM_CONF + 0xAC + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + 0 + 8 + read-write + + + CLKM_DIV_B + 8 + 6 + read-write + + + CLKM_DIV_A + 14 + 6 + read-write + + + CLK_EN + 20 + 1 + read-write + + + CLKA_ENA + 21 + 1 + read-write + + + + + SAMPLE_RATE_CONF + 0xB0 + 0x20 + 0x00410186 + + + TX_BCK_DIV_NUM + 0 + 6 + read-write + + + RX_BCK_DIV_NUM + 6 + 6 + read-write + + + TX_BITS_MOD + 12 + 6 + read-write + + + RX_BITS_MOD + 18 + 6 + read-write + + + + + PDM_CONF + 0xB4 + 0x20 + 0x01550020 + + + TX_PDM_EN + 0 + 1 + read-write + + + RX_PDM_EN + 1 + 1 + read-write + + + PCM2PDM_CONV_EN + 2 + 1 + read-write + + + PDM2PCM_CONV_EN + 3 + 1 + read-write + + + TX_PDM_SINC_OSR2 + 4 + 4 + read-write + + + TX_PDM_PRESCALE + 8 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + 16 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + 18 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + 20 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + 22 + 2 + read-write + + + RX_PDM_SINC_DSR_16_EN + 24 + 1 + read-write + + + TX_PDM_HP_BYPASS + 25 + 1 + read-write + + + + + PDM_FREQ_CONF + 0xB8 + 0x20 + 0x000F01E0 + + + TX_PDM_FS + 0 + 10 + read-write + + + TX_PDM_FP + 10 + 10 + read-write + + + + + STATE + 0xBC + 0x20 + 0x00000007 + + + TX_IDLE + 0 + 1 + read-only + + + TX_FIFO_RESET_BACK + 1 + 1 + read-only + + + RX_FIFO_RESET_BACK + 2 + 1 + read-only + + + + + DATE + 0xFC + 0x20 + 0x01604201 + + + I2SDATE + 0 + 32 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller + 0x3FF6D000 + + I2S1 + 33 + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x3FF49000 + + 0x0 + 0x94 + registers + + + + PIN_CTRL + 0x0 + 0x20 + + + CLK1 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. + 0 + 4 + read-write + + + CLK2 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. + 4 + 4 + read-write + + + CLK3 + If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. + 8 + 4 + read-write + + + + + GPIO36 + 0x4 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO37 + 0x8 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO38 + 0xC + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO39 + 0x10 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO34 + 0x14 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO35 + 0x18 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO32 + 0x1C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO33 + 0x20 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO25 + 0x24 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO26 + 0x28 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO27 + 0x2C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO14 + 0x30 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO12 + 0x34 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO13 + 0x38 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO15 + 0x3C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO2 + 0x40 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO0 + 0x44 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO4 + 0x48 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO16 + 0x4C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO17 + 0x50 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO9 + 0x54 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO10 + 0x58 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO11 + 0x5C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO6 + 0x60 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO7 + 0x64 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO8 + 0x68 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO5 + 0x6C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO18 + 0x70 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO19 + 0x74 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO20 + 0x78 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO21 + 0x7C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO22 + 0x80 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO3 + 0x84 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO1 + 0x88 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO23 + 0x8C + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + GPIO24 + 0x90 + 0x20 + + + MCU_OE + Output enable of the pad in sleep mode. 1: enable output; 0: disable output. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. + 10 + 2 + read-write + + + MCU_SEL + Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. + 12 + 3 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x3FF59000 + + 0x0 + 0x198 + registers + + + LEDC + 43 + + + TIMER1 + 56 + + + TIMER2 + 57 + + + + 8 + 0x14 + 0-7 + HSCH%s_CONF0 + 0x0 + 0x20 + + + TIMER_SEL + There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. + 0 + 2 + read-write + + + SIG_OUT_EN + This is the output enable control bit for high speed channel0 + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when high speed channel0 is off. + 3 + 1 + read-write + + + + + 8 + 0x14 + 0-7 + HSCH%s_HPOINT + 0x4 + 0x20 + + + HPOINT + The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0] + 0 + 20 + read-write + + + + + 8 + 0x14 + 0-7 + HSCH%s_DUTY + 0x8 + 0x20 + + + DUTY + This register represents the current duty of the output signal for high speed channel0. + 0 + 25 + read-write + + + + + 8 + 0x14 + 0-7 + HSCH%s_CONF1 + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register controls the increase or decrease step scale for high speed channel0. + 0 + 10 + read-write + + + DUTY_CYCLE + This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the num of increased or decreased times for high speed channel0. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. + 30 + 1 + read-write + + + DUTY_START + When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware. + 31 + 1 + read-write + + + + + 8 + 0x14 + 0-7 + HSCH%s_DUTY_R + 0x10 + 0x20 + + + DUTY_R + This register represents the current duty cycle of the output signal for high-speed channel %s + 0 + 25 + read-only + + + + + 8 + 0x14 + 0-7 + LSCH%s_CONF0 + 0xA0 + 0x20 + + + TIMER_SEL + There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. + 0 + 2 + read-write + + + SIG_OUT_EN + This is the output enable control bit for low speed channel0. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when low speed channel0 is off. + 3 + 1 + read-write + + + PARA_UP + This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. + 4 + 1 + read-write + + + + + 8 + 0x14 + 0-7 + LSCH%s_HPOINT + 0xA4 + 0x20 + + + HPOINT + The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0] + 0 + 20 + read-write + + + + + 8 + 0x14 + 0-7 + LSCH%s_DUTY + 0xA8 + 0x20 + read-write + + + DUTY + This register represents the current duty of the output signal for low speed channel0. + 0 + 25 + read-write + + + + + 8 + 0x14 + 0-7 + LSCH%s_CONF1 + 0xAC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register controls the increase or decrease step scale for low speed channel0. + 0 + 10 + read-write + + + DUTY_CYCLE + This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the num of increased or decreased times for low speed channel6. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. + 30 + 1 + read-write + + + DUTY_START + When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. + 31 + 1 + read-write + + + + + 8 + 0x14 + 0-7 + LSCH%s_DUTY_R + 0xB0 + 0x20 + + + DUTY_R + This register represents the current duty cycle of the output signal for low-speed channel %s + 0 + 25 + read-only + + + + + 4 + 0x8 + 0-3 + HSTIMER%s_CONF + 0x140 + 0x20 + 0x01000000 + + + DUTY_RES + This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20. + 0 + 5 + read-write + + + DIV_NUM + This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. + 5 + 18 + read-write + + + PAUSE + This bit is used to pause the counter in high speed timer0 + 23 + 1 + read-write + + + RST + This bit is used to reset high speed timer0 the counter will be 0 after reset. + 24 + 1 + read-write + + + TICK_SEL + This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick + 25 + 1 + read-write + + + LIM + 31 + 5 + read-write + + + + + 4 + 0x8 + 0-3 + HSTIMER%s_VALUE + 0x144 + 0x20 + + + CNT + software can read this register to get the current counter value in high speed timer0 + 0 + 20 + read-only + + + + + 4 + 0x8 + 0-3 + LSTIMER%s_CONF + 0x160 + 0x20 + 0x01000000 + + + DUTY_RES + This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20. + 0 + 5 + read-write + + + DIV_NUM + This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. + 5 + 18 + read-write + + + PAUSE + This bit is used to pause the counter in low speed timer0. + 23 + 1 + read-write + + + RST + This bit is used to reset low speed timer0 the counter will be 0 after reset. + 24 + 1 + read-write + + + TICK_SEL + This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick + 25 + 1 + read-write + + + PARA_UP + Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. + 26 + 1 + read-write + + + LIM + 31 + 5 + read-write + + + + + 4 + 0x8 + 0-3 + LSTIMER%s_VALUE + 0x164 + 0x20 + + + CNT + software can read this register to get the current counter value in low speed timer0. + 0 + 20 + read-only + + + + + INT_RAW + 0x180 + 0x20 + + + HSTIMER0_OVF_INT_RAW + The interrupt raw bit for high speed channel0 counter overflow. + 0 + 1 + read-only + + + HSTIMER1_OVF_INT_RAW + The interrupt raw bit for high speed channel1 counter overflow. + 1 + 1 + read-only + + + HSTIMER2_OVF_INT_RAW + The interrupt raw bit for high speed channel2 counter overflow. + 2 + 1 + read-only + + + HSTIMER3_OVF_INT_RAW + The interrupt raw bit for high speed channel3 counter overflow. + 3 + 1 + read-only + + + LSTIMER0_OVF_INT_RAW + The interrupt raw bit for low speed channel0 counter overflow. + 4 + 1 + read-only + + + LSTIMER1_OVF_INT_RAW + The interrupt raw bit for low speed channel1 counter overflow. + 5 + 1 + read-only + + + LSTIMER2_OVF_INT_RAW + The interrupt raw bit for low speed channel2 counter overflow. + 6 + 1 + read-only + + + LSTIMER3_OVF_INT_RAW + The interrupt raw bit for low speed channel3 counter overflow. + 7 + 1 + read-only + + + DUTY_CHNG_END_HSCH0_INT_RAW + The interrupt raw bit for high speed channel 0 duty change done. + 8 + 1 + read-only + + + DUTY_CHNG_END_HSCH1_INT_RAW + The interrupt raw bit for high speed channel 1 duty change done. + 9 + 1 + read-only + + + DUTY_CHNG_END_HSCH2_INT_RAW + The interrupt raw bit for high speed channel 2 duty change done. + 10 + 1 + read-only + + + DUTY_CHNG_END_HSCH3_INT_RAW + The interrupt raw bit for high speed channel 3 duty change done. + 11 + 1 + read-only + + + DUTY_CHNG_END_HSCH4_INT_RAW + The interrupt raw bit for high speed channel 4 duty change done. + 12 + 1 + read-only + + + DUTY_CHNG_END_HSCH5_INT_RAW + The interrupt raw bit for high speed channel 5 duty change done. + 13 + 1 + read-only + + + DUTY_CHNG_END_HSCH6_INT_RAW + The interrupt raw bit for high speed channel 6 duty change done. + 14 + 1 + read-only + + + DUTY_CHNG_END_HSCH7_INT_RAW + The interrupt raw bit for high speed channel 7 duty change done. + 15 + 1 + read-only + + + DUTY_CHNG_END_LSCH0_INT_RAW + The interrupt raw bit for low speed channel 0 duty change done. + 16 + 1 + read-only + + + DUTY_CHNG_END_LSCH1_INT_RAW + The interrupt raw bit for low speed channel 1 duty change done. + 17 + 1 + read-only + + + DUTY_CHNG_END_LSCH2_INT_RAW + The interrupt raw bit for low speed channel 2 duty change done. + 18 + 1 + read-only + + + DUTY_CHNG_END_LSCH3_INT_RAW + The interrupt raw bit for low speed channel 3 duty change done. + 19 + 1 + read-only + + + DUTY_CHNG_END_LSCH4_INT_RAW + The interrupt raw bit for low speed channel 4 duty change done. + 20 + 1 + read-only + + + DUTY_CHNG_END_LSCH5_INT_RAW + The interrupt raw bit for low speed channel 5 duty change done. + 21 + 1 + read-only + + + DUTY_CHNG_END_LSCH6_INT_RAW + The interrupt raw bit for low speed channel 6 duty change done. + 22 + 1 + read-only + + + DUTY_CHNG_END_LSCH7_INT_RAW + The interrupt raw bit for low speed channel 7 duty change done. + 23 + 1 + read-only + + + + + INT_ST + 0x184 + 0x20 + + + HSTIMER0_OVF_INT_ST + The interrupt status bit for high speed channel0 counter overflow event. + 0 + 1 + read-only + + + HSTIMER1_OVF_INT_ST + The interrupt status bit for high speed channel1 counter overflow event. + 1 + 1 + read-only + + + HSTIMER2_OVF_INT_ST + The interrupt status bit for high speed channel2 counter overflow event. + 2 + 1 + read-only + + + HSTIMER3_OVF_INT_ST + The interrupt status bit for high speed channel3 counter overflow event. + 3 + 1 + read-only + + + LSTIMER0_OVF_INT_ST + The interrupt status bit for low speed channel0 counter overflow event. + 4 + 1 + read-only + + + LSTIMER1_OVF_INT_ST + The interrupt status bit for low speed channel1 counter overflow event. + 5 + 1 + read-only + + + LSTIMER2_OVF_INT_ST + The interrupt status bit for low speed channel2 counter overflow event. + 6 + 1 + read-only + + + LSTIMER3_OVF_INT_ST + The interrupt status bit for low speed channel3 counter overflow event. + 7 + 1 + read-only + + + DUTY_CHNG_END_HSCH0_INT_ST + The interrupt status bit for high speed channel 0 duty change done event. + 8 + 1 + read-only + + + DUTY_CHNG_END_HSCH1_INT_ST + The interrupt status bit for high speed channel 1 duty change done event. + 9 + 1 + read-only + + + DUTY_CHNG_END_HSCH2_INT_ST + The interrupt status bit for high speed channel 2 duty change done event. + 10 + 1 + read-only + + + DUTY_CHNG_END_HSCH3_INT_ST + The interrupt status bit for high speed channel 3 duty change done event. + 11 + 1 + read-only + + + DUTY_CHNG_END_HSCH4_INT_ST + The interrupt status bit for high speed channel 4 duty change done event. + 12 + 1 + read-only + + + DUTY_CHNG_END_HSCH5_INT_ST + The interrupt status bit for high speed channel 5 duty change done event. + 13 + 1 + read-only + + + DUTY_CHNG_END_HSCH6_INT_ST + The interrupt status bit for high speed channel 6 duty change done event. + 14 + 1 + read-only + + + DUTY_CHNG_END_HSCH7_INT_ST + The interrupt status bit for high speed channel 7 duty change done event. + 15 + 1 + read-only + + + DUTY_CHNG_END_LSCH0_INT_ST + The interrupt status bit for low speed channel 0 duty change done event. + 16 + 1 + read-only + + + DUTY_CHNG_END_LSCH1_INT_ST + The interrupt status bit for low speed channel 1 duty change done event. + 17 + 1 + read-only + + + DUTY_CHNG_END_LSCH2_INT_ST + The interrupt status bit for low speed channel 2 duty change done event. + 18 + 1 + read-only + + + DUTY_CHNG_END_LSCH3_INT_ST + The interrupt status bit for low speed channel 3 duty change done event. + 19 + 1 + read-only + + + DUTY_CHNG_END_LSCH4_INT_ST + The interrupt status bit for low speed channel 4 duty change done event. + 20 + 1 + read-only + + + DUTY_CHNG_END_LSCH5_INT_ST + The interrupt status bit for low speed channel 5 duty change done event. + 21 + 1 + read-only + + + DUTY_CHNG_END_LSCH6_INT_ST + The interrupt status bit for low speed channel 6 duty change done event. + 22 + 1 + read-only + + + DUTY_CHNG_END_LSCH7_INT_ST + The interrupt status bit for low speed channel 7 duty change done event + 23 + 1 + read-only + + + + + INT_ENA + 0x188 + 0x20 + + + HSTIMER0_OVF_INT_ENA + The interrupt enable bit for high speed channel0 counter overflow interrupt. + 0 + 1 + read-write + + + HSTIMER1_OVF_INT_ENA + The interrupt enable bit for high speed channel1 counter overflow interrupt. + 1 + 1 + read-write + + + HSTIMER2_OVF_INT_ENA + The interrupt enable bit for high speed channel2 counter overflow interrupt. + 2 + 1 + read-write + + + HSTIMER3_OVF_INT_ENA + The interrupt enable bit for high speed channel3 counter overflow interrupt. + 3 + 1 + read-write + + + LSTIMER0_OVF_INT_ENA + The interrupt enable bit for low speed channel0 counter overflow interrupt. + 4 + 1 + read-write + + + LSTIMER1_OVF_INT_ENA + The interrupt enable bit for low speed channel1 counter overflow interrupt. + 5 + 1 + read-write + + + LSTIMER2_OVF_INT_ENA + The interrupt enable bit for low speed channel2 counter overflow interrupt. + 6 + 1 + read-write + + + LSTIMER3_OVF_INT_ENA + The interrupt enable bit for low speed channel3 counter overflow interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_HSCH0_INT_ENA + The interrupt enable bit for high speed channel 0 duty change done interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_HSCH1_INT_ENA + The interrupt enable bit for high speed channel 1 duty change done interrupt. + 9 + 1 + read-write + + + DUTY_CHNG_END_HSCH2_INT_ENA + The interrupt enable bit for high speed channel 2 duty change done interrupt. + 10 + 1 + read-write + + + DUTY_CHNG_END_HSCH3_INT_ENA + The interrupt enable bit for high speed channel 3 duty change done interrupt. + 11 + 1 + read-write + + + DUTY_CHNG_END_HSCH4_INT_ENA + The interrupt enable bit for high speed channel 4 duty change done interrupt. + 12 + 1 + read-write + + + DUTY_CHNG_END_HSCH5_INT_ENA + The interrupt enable bit for high speed channel 5 duty change done interrupt. + 13 + 1 + read-write + + + DUTY_CHNG_END_HSCH6_INT_ENA + The interrupt enable bit for high speed channel 6 duty change done interrupt. + 14 + 1 + read-write + + + DUTY_CHNG_END_HSCH7_INT_ENA + The interrupt enable bit for high speed channel 7 duty change done interrupt. + 15 + 1 + read-write + + + DUTY_CHNG_END_LSCH0_INT_ENA + The interrupt enable bit for low speed channel 0 duty change done interrupt. + 16 + 1 + read-write + + + DUTY_CHNG_END_LSCH1_INT_ENA + The interrupt enable bit for low speed channel 1 duty change done interrupt. + 17 + 1 + read-write + + + DUTY_CHNG_END_LSCH2_INT_ENA + The interrupt enable bit for low speed channel 2 duty change done interrupt. + 18 + 1 + read-write + + + DUTY_CHNG_END_LSCH3_INT_ENA + The interrupt enable bit for low speed channel 3 duty change done interrupt. + 19 + 1 + read-write + + + DUTY_CHNG_END_LSCH4_INT_ENA + The interrupt enable bit for low speed channel 4 duty change done interrupt. + 20 + 1 + read-write + + + DUTY_CHNG_END_LSCH5_INT_ENA + The interrupt enable bit for low speed channel 5 duty change done interrupt. + 21 + 1 + read-write + + + DUTY_CHNG_END_LSCH6_INT_ENA + The interrupt enable bit for low speed channel 6 duty change done interrupt. + 22 + 1 + read-write + + + DUTY_CHNG_END_LSCH7_INT_ENA + The interrupt enable bit for low speed channel 7 duty change done interrupt. + 23 + 1 + read-write + + + + + INT_CLR + 0x18C + 0x20 + + + HSTIMER0_OVF_INT_CLR + Set this bit to clear high speed channel0 counter overflow interrupt. + 0 + 1 + write-only + + + HSTIMER1_OVF_INT_CLR + Set this bit to clear high speed channel1 counter overflow interrupt. + 1 + 1 + write-only + + + HSTIMER2_OVF_INT_CLR + Set this bit to clear high speed channel2 counter overflow interrupt. + 2 + 1 + write-only + + + HSTIMER3_OVF_INT_CLR + Set this bit to clear high speed channel3 counter overflow interrupt. + 3 + 1 + write-only + + + LSTIMER0_OVF_INT_CLR + Set this bit to clear low speed channel0 counter overflow interrupt. + 4 + 1 + write-only + + + LSTIMER1_OVF_INT_CLR + Set this bit to clear low speed channel1 counter overflow interrupt. + 5 + 1 + write-only + + + LSTIMER2_OVF_INT_CLR + Set this bit to clear low speed channel2 counter overflow interrupt. + 6 + 1 + write-only + + + LSTIMER3_OVF_INT_CLR + Set this bit to clear low speed channel3 counter overflow interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_HSCH0_INT_CLR + Set this bit to clear high speed channel 0 duty change done interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_HSCH1_INT_CLR + Set this bit to clear high speed channel 1 duty change done interrupt. + 9 + 1 + write-only + + + DUTY_CHNG_END_HSCH2_INT_CLR + Set this bit to clear high speed channel 2 duty change done interrupt. + 10 + 1 + write-only + + + DUTY_CHNG_END_HSCH3_INT_CLR + Set this bit to clear high speed channel 3 duty change done interrupt. + 11 + 1 + write-only + + + DUTY_CHNG_END_HSCH4_INT_CLR + Set this bit to clear high speed channel 4 duty change done interrupt. + 12 + 1 + write-only + + + DUTY_CHNG_END_HSCH5_INT_CLR + Set this bit to clear high speed channel 5 duty change done interrupt. + 13 + 1 + write-only + + + DUTY_CHNG_END_HSCH6_INT_CLR + Set this bit to clear high speed channel 6 duty change done interrupt. + 14 + 1 + write-only + + + DUTY_CHNG_END_HSCH7_INT_CLR + Set this bit to clear high speed channel 7 duty change done interrupt. + 15 + 1 + write-only + + + DUTY_CHNG_END_LSCH0_INT_CLR + Set this bit to clear low speed channel 0 duty change done interrupt. + 16 + 1 + write-only + + + DUTY_CHNG_END_LSCH1_INT_CLR + Set this bit to clear low speed channel 1 duty change done interrupt. + 17 + 1 + write-only + + + DUTY_CHNG_END_LSCH2_INT_CLR + Set this bit to clear low speed channel 2 duty change done interrupt. + 18 + 1 + write-only + + + DUTY_CHNG_END_LSCH3_INT_CLR + Set this bit to clear low speed channel 3 duty change done interrupt. + 19 + 1 + write-only + + + DUTY_CHNG_END_LSCH4_INT_CLR + Set this bit to clear low speed channel 4 duty change done interrupt. + 20 + 1 + write-only + + + DUTY_CHNG_END_LSCH5_INT_CLR + Set this bit to clear low speed channel 5 duty change done interrupt. + 21 + 1 + write-only + + + DUTY_CHNG_END_LSCH6_INT_CLR + Set this bit to clear low speed channel 6 duty change done interrupt. + 22 + 1 + write-only + + + DUTY_CHNG_END_LSCH7_INT_CLR + Set this bit to clear low speed channel 7 duty change done interrupt. + 23 + 1 + write-only + + + + + CONF + 0x190 + 0x20 + + + APB_CLK_SEL + This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz + 0 + 1 + read-write + + + + + DATE + 0x1FC + 0x20 + 0x16031700 + + + DATE + This register represents the version . + 0 + 32 + read-write + + + + + + + PWM0 + Motor Control Pulse-Width Modulation + MCPWM + 0x3FF5E000 + + 0x0 + 0x128 + registers + + + PWM0 + 39 + + + + CLK_CFG + 0x0 + 0x20 + + + CLK_PRESCALE + 0 + 8 + read-write + + + + + TIMER0_CFG0 + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + 0 + 8 + read-write + + + TIMER0_PERIOD + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + 24 + 2 + read-write + + + + + TIMER0_CFG1 + 0x8 + 0x20 + + + TIMER0_START + 0 + 3 + read-write + + + TIMER0_MOD + 3 + 2 + read-write + + + + + TIMER0_SYNC + 0xC + 0x20 + + + TIMER0_SYNCI_EN + 0 + 1 + read-write + + + SW + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + 2 + 2 + read-write + + + TIMER0_PHASE + 4 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + 20 + 1 + read-write + + + + + TIMER0_STATUS + 0x10 + 0x20 + + + TIMER0_VALUE + 0 + 16 + read-only + + + TIMER0_DIRECTION + 16 + 1 + read-only + + + + + TIMER1_CFG0 + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + 0 + 8 + read-write + + + TIMER1_PERIOD + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + 24 + 2 + read-write + + + + + TIMER1_CFG1 + 0x18 + 0x20 + + + TIMER1_START + 0 + 3 + read-write + + + TIMER1_MOD + 3 + 2 + read-write + + + + + TIMER1_SYNC + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + 0 + 1 + read-write + + + SW + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + 2 + 2 + read-write + + + TIMER1_PHASE + 4 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + 20 + 1 + read-write + + + + + TIMER1_STATUS + 0x20 + 0x20 + + + TIMER1_VALUE + 0 + 16 + read-only + + + TIMER1_DIRECTION + 16 + 1 + read-only + + + + + TIMER2_CFG0 + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + 0 + 8 + read-write + + + TIMER2_PERIOD + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + 24 + 2 + read-write + + + + + TIMER2_CFG1 + 0x28 + 0x20 + + + TIMER2_START + 0 + 3 + read-write + + + TIMER2_MOD + 3 + 2 + read-write + + + + + TIMER2_SYNC + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + 0 + 1 + read-write + + + SW + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + 2 + 2 + read-write + + + TIMER2_PHASE + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + 20 + 1 + read-write + + + + + TIMER2_STATUS + 0x30 + 0x20 + + + TIMER2_VALUE + 0 + 16 + read-only + + + TIMER2_DIRECTION + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + 0x34 + 0x20 + + + TIMER0_SYNCISEL + 0 + 3 + read-write + + + TIMER1_SYNCISEL + 3 + 3 + read-write + + + TIMER2_SYNCISEL + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + 4 + 2 + read-write + + + + + GEN0_STMP_CFG + 0x3C + 0x20 + + + GEN0_A_UPMETHOD + 0 + 4 + read-write + + + GEN0_B_UPMETHOD + 4 + 4 + read-write + + + GEN0_A_SHDW_FULL + 8 + 1 + read-write + + + GEN0_B_SHDW_FULL + 9 + 1 + read-write + + + + + GEN0_TSTMP_A + 0x40 + 0x20 + + + GEN0_A + 0 + 16 + read-write + + + + + GEN0_TSTMP_B + 0x44 + 0x20 + + + GEN0_B + 0 + 16 + read-write + + + + + GEN0_CFG0 + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + 0 + 4 + read-write + + + GEN0_T0_SEL + 4 + 3 + read-write + + + GEN0_T1_SEL + 7 + 3 + read-write + + + + + GEN0_FORCE + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + 14 + 2 + read-write + + + + + GEN0_A + 0x50 + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + GEN0_B + 0x54 + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + DT0_CFG + 0x58 + 0x20 + 0x00018000 + + + DT0_FED_UPMETHOD + 0 + 4 + read-write + + + DT0_RED_UPMETHOD + 4 + 4 + read-write + + + DT0_DEB_MODE + 8 + 1 + read-write + + + DT0_A_OUTSWAP + 9 + 1 + read-write + + + DT0_B_OUTSWAP + 10 + 1 + read-write + + + DT0_RED_INSEL + 11 + 1 + read-write + + + DT0_FED_INSEL + 12 + 1 + read-write + + + DT0_RED_OUTINVERT + 13 + 1 + read-write + + + DT0_FED_OUTINVERT + 14 + 1 + read-write + + + DT0_A_OUTBYPASS + 15 + 1 + read-write + + + DT0_B_OUTBYPASS + 16 + 1 + read-write + + + DT0_CLK_SEL + 17 + 1 + read-write + + + + + DT0_FED_CFG + 0x5C + 0x20 + + + DT0_FED + 0 + 16 + read-write + + + + + DT0_RED_CFG + 0x60 + 0x20 + + + DT0_RED + 0 + 16 + read-write + + + + + CARRIER0_CFG + 0x64 + 0x20 + + + CARRIER0_EN + 0 + 1 + read-write + + + CARRIER0_PRESCALE + 1 + 4 + read-write + + + CARRIER0_DUTY + 5 + 3 + read-write + + + CARRIER0_OSHTWTH + 8 + 4 + read-write + + + CARRIER0_OUT_INVERT + 12 + 1 + read-write + + + CARRIER0_IN_INVERT + 13 + 1 + read-write + + + + + FH0_CFG0 + 0x68 + 0x20 + + + FH0_SW_CBC + 0 + 1 + read-write + + + FH0_F2_CBC + 1 + 1 + read-write + + + FH0_F1_CBC + 2 + 1 + read-write + + + FH0_F0_CBC + 3 + 1 + read-write + + + FH0_SW_OST + 4 + 1 + read-write + + + FH0_F2_OST + 5 + 1 + read-write + + + FH0_F1_OST + 6 + 1 + read-write + + + FH0_F0_OST + 7 + 1 + read-write + + + FH0_A_CBC_D + 8 + 2 + read-write + + + FH0_A_CBC_U + 10 + 2 + read-write + + + FH0_A_OST_D + 12 + 2 + read-write + + + FH0_A_OST_U + 14 + 2 + read-write + + + FH0_B_CBC_D + 16 + 2 + read-write + + + FH0_B_CBC_U + 18 + 2 + read-write + + + FH0_B_OST_D + 20 + 2 + read-write + + + FH0_B_OST_U + 22 + 2 + read-write + + + + + FH0_CFG1 + 0x6C + 0x20 + + + FH0_CLR_OST + 0 + 1 + read-write + + + FH0_CBCPULSE + 1 + 2 + read-write + + + FH0_FORCE_CBC + 3 + 1 + read-write + + + FH0_FORCE_OST + 4 + 1 + read-write + + + + + FH0_STATUS + 0x70 + 0x20 + + + FH0_CBC_ON + 0 + 1 + read-only + + + FH0_OST_ON + 1 + 1 + read-only + + + + + GEN1_STMP_CFG + 0x74 + 0x20 + + + GEN1_A_UPMETHOD + 0 + 4 + read-write + + + GEN1_B_UPMETHOD + 4 + 4 + read-write + + + GEN1_A_SHDW_FULL + 8 + 1 + read-write + + + GEN1_B_SHDW_FULL + 9 + 1 + read-write + + + + + GEN1_TSTMP_A + 0x78 + 0x20 + + + GEN1_A + 0 + 16 + read-write + + + + + GEN1_TSTMP_B + 0x7C + 0x20 + + + GEN1_B + 0 + 16 + read-write + + + + + GEN1_CFG0 + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + 0 + 4 + read-write + + + GEN1_T0_SEL + 4 + 3 + read-write + + + GEN1_T1_SEL + 7 + 3 + read-write + + + + + GEN1_FORCE + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + 14 + 2 + read-write + + + + + GEN1_A + 0x88 + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + GEN1_B + 0x8C + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + DT1_CFG + 0x90 + 0x20 + 0x00018000 + + + DT1_FED_UPMETHOD + 0 + 4 + read-write + + + DT1_RED_UPMETHOD + 4 + 4 + read-write + + + DT1_DEB_MODE + 8 + 1 + read-write + + + DT1_A_OUTSWAP + 9 + 1 + read-write + + + DT1_B_OUTSWAP + 10 + 1 + read-write + + + DT1_RED_INSEL + 11 + 1 + read-write + + + DT1_FED_INSEL + 12 + 1 + read-write + + + DT1_RED_OUTINVERT + 13 + 1 + read-write + + + DT1_FED_OUTINVERT + 14 + 1 + read-write + + + DT1_A_OUTBYPASS + 15 + 1 + read-write + + + DT1_B_OUTBYPASS + 16 + 1 + read-write + + + DT1_CLK_SEL + 17 + 1 + read-write + + + + + DT1_FED_CFG + 0x94 + 0x20 + + + DT1_FED + 0 + 16 + read-write + + + + + DT1_RED_CFG + 0x98 + 0x20 + + + DT1_RED + 0 + 16 + read-write + + + + + CARRIER1_CFG + 0x9C + 0x20 + + + CARRIER1_EN + 0 + 1 + read-write + + + CARRIER1_PRESCALE + 1 + 4 + read-write + + + CARRIER1_DUTY + 5 + 3 + read-write + + + CARRIER1_OSHTWTH + 8 + 4 + read-write + + + CARRIER1_OUT_INVERT + 12 + 1 + read-write + + + CARRIER1_IN_INVERT + 13 + 1 + read-write + + + + + FH1_CFG0 + 0xA0 + 0x20 + + + FH1_SW_CBC + 0 + 1 + read-write + + + FH1_F2_CBC + 1 + 1 + read-write + + + FH1_F1_CBC + 2 + 1 + read-write + + + FH1_F0_CBC + 3 + 1 + read-write + + + FH1_SW_OST + 4 + 1 + read-write + + + FH1_F2_OST + 5 + 1 + read-write + + + FH1_F1_OST + 6 + 1 + read-write + + + FH1_F0_OST + 7 + 1 + read-write + + + FH1_A_CBC_D + 8 + 2 + read-write + + + FH1_A_CBC_U + 10 + 2 + read-write + + + FH1_A_OST_D + 12 + 2 + read-write + + + FH1_A_OST_U + 14 + 2 + read-write + + + FH1_B_CBC_D + 16 + 2 + read-write + + + FH1_B_CBC_U + 18 + 2 + read-write + + + FH1_B_OST_D + 20 + 2 + read-write + + + FH1_B_OST_U + 22 + 2 + read-write + + + + + FH1_CFG1 + 0xA4 + 0x20 + + + FH1_CLR_OST + 0 + 1 + read-write + + + FH1_CBCPULSE + 1 + 2 + read-write + + + FH1_FORCE_CBC + 3 + 1 + read-write + + + FH1_FORCE_OST + 4 + 1 + read-write + + + + + FH1_STATUS + 0xA8 + 0x20 + + + FH1_CBC_ON + 0 + 1 + read-only + + + FH1_OST_ON + 1 + 1 + read-only + + + + + GEN2_STMP_CFG + 0xAC + 0x20 + + + GEN2_A_UPMETHOD + 0 + 4 + read-write + + + GEN2_B_UPMETHOD + 4 + 4 + read-write + + + GEN2_A_SHDW_FULL + 8 + 1 + read-write + + + GEN2_B_SHDW_FULL + 9 + 1 + read-write + + + + + GEN2_TSTMP_A + 0xB0 + 0x20 + + + GEN2_A + 0 + 16 + read-write + + + + + GEN2_TSTMP_B + 0xB4 + 0x20 + + + GEN2_B + 0 + 16 + read-write + + + + + GEN2_CFG0 + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + 0 + 4 + read-write + + + GEN2_T0_SEL + 4 + 3 + read-write + + + GEN2_T1_SEL + 7 + 3 + read-write + + + + + GEN2_FORCE + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + 14 + 2 + read-write + + + + + GEN2_A + 0xC0 + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + GEN2_B + 0xC4 + 0x20 + + + UTEZ + 0 + 2 + read-write + + + UTEP + 2 + 2 + read-write + + + UTEA + 4 + 2 + read-write + + + UTEB + 6 + 2 + read-write + + + UT0 + 8 + 2 + read-write + + + UT1 + 10 + 2 + read-write + + + DTEZ + 12 + 2 + read-write + + + DTEP + 14 + 2 + read-write + + + DTEA + 16 + 2 + read-write + + + DTEB + 18 + 2 + read-write + + + DT0 + 20 + 2 + read-write + + + DT1 + 22 + 2 + read-write + + + + + DT2_CFG + 0xC8 + 0x20 + 0x00018000 + + + DT2_FED_UPMETHOD + 0 + 4 + read-write + + + DT2_RED_UPMETHOD + 4 + 4 + read-write + + + DT2_DEB_MODE + 8 + 1 + read-write + + + DT2_A_OUTSWAP + 9 + 1 + read-write + + + DT2_B_OUTSWAP + 10 + 1 + read-write + + + DT2_RED_INSEL + 11 + 1 + read-write + + + DT2_FED_INSEL + 12 + 1 + read-write + + + DT2_RED_OUTINVERT + 13 + 1 + read-write + + + DT2_FED_OUTINVERT + 14 + 1 + read-write + + + DT2_A_OUTBYPASS + 15 + 1 + read-write + + + DT2_B_OUTBYPASS + 16 + 1 + read-write + + + DT2_CLK_SEL + 17 + 1 + read-write + + + + + DT2_FED_CFG + 0xCC + 0x20 + + + DT2_FED + 0 + 16 + read-write + + + + + DT2_RED_CFG + 0xD0 + 0x20 + + + DT2_RED + 0 + 16 + read-write + + + + + CARRIER2_CFG + 0xD4 + 0x20 + + + CARRIER2_EN + 0 + 1 + read-write + + + CARRIER2_PRESCALE + 1 + 4 + read-write + + + CARRIER2_DUTY + 5 + 3 + read-write + + + CARRIER2_OSHTWTH + 8 + 4 + read-write + + + CARRIER2_OUT_INVERT + 12 + 1 + read-write + + + CARRIER2_IN_INVERT + 13 + 1 + read-write + + + + + FH2_CFG0 + 0xD8 + 0x20 + + + FH2_SW_CBC + 0 + 1 + read-write + + + FH2_F2_CBC + 1 + 1 + read-write + + + FH2_F1_CBC + 2 + 1 + read-write + + + FH2_F0_CBC + 3 + 1 + read-write + + + FH2_SW_OST + 4 + 1 + read-write + + + FH2_F2_OST + 5 + 1 + read-write + + + FH2_F1_OST + 6 + 1 + read-write + + + FH2_F0_OST + 7 + 1 + read-write + + + FH2_A_CBC_D + 8 + 2 + read-write + + + FH2_A_CBC_U + 10 + 2 + read-write + + + FH2_A_OST_D + 12 + 2 + read-write + + + FH2_A_OST_U + 14 + 2 + read-write + + + FH2_B_CBC_D + 16 + 2 + read-write + + + FH2_B_CBC_U + 18 + 2 + read-write + + + FH2_B_OST_D + 20 + 2 + read-write + + + FH2_B_OST_U + 22 + 2 + read-write + + + + + FH2_CFG1 + 0xDC + 0x20 + + + FH2_CLR_OST + 0 + 1 + read-write + + + FH2_CBCPULSE + 1 + 2 + read-write + + + FH2_FORCE_CBC + 3 + 1 + read-write + + + FH2_FORCE_OST + 4 + 1 + read-write + + + + + FH2_STATUS + 0xE0 + 0x20 + + + FH2_CBC_ON + 0 + 1 + read-only + + + FH2_OST_ON + 1 + 1 + read-only + + + + + FAULT_DETECT + 0xE4 + 0x20 + + + F0_EN + 0 + 1 + read-write + + + F1_EN + 1 + 1 + read-write + + + F2_EN + 2 + 1 + read-write + + + F0_POLE + 3 + 1 + read-write + + + F1_POLE + 4 + 1 + read-write + + + F2_POLE + 5 + 1 + read-write + + + EVENT_F0 + 6 + 1 + read-only + + + EVENT_F1 + 7 + 1 + read-only + + + EVENT_F2 + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + 0xE8 + 0x20 + + + CAP_TIMER_EN + 0 + 1 + read-write + + + CAP_SYNCI_EN + 1 + 1 + read-write + + + CAP_SYNCI_SEL + 2 + 3 + read-write + + + CAP_SYNC_SW + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + 0xEC + 0x20 + + + CAP_TIMER_PHASE + 0 + 32 + read-write + + + + + CAP_CH0_CFG + 0xF0 + 0x20 + + + CAP0_EN + 0 + 1 + read-write + + + CAP0_MODE + 1 + 2 + read-write + + + CAP0_PRESCALE + 3 + 8 + read-write + + + CAP0_IN_INVERT + 11 + 1 + read-write + + + CAP0_SW + 12 + 1 + write-only + + + + + CAP_CH1_CFG + 0xF4 + 0x20 + + + CAP1_EN + 0 + 1 + read-write + + + CAP1_MODE + 1 + 2 + read-write + + + CAP1_PRESCALE + 3 + 8 + read-write + + + CAP1_IN_INVERT + 11 + 1 + read-write + + + CAP1_SW + 12 + 1 + write-only + + + + + CAP_CH2_CFG + 0xF8 + 0x20 + + + CAP2_EN + 0 + 1 + read-write + + + CAP2_MODE + 1 + 2 + read-write + + + CAP2_PRESCALE + 3 + 8 + read-write + + + CAP2_IN_INVERT + 11 + 1 + read-write + + + CAP2_SW + 12 + 1 + write-only + + + + + CAP_CH0 + 0xFC + 0x20 + + + CAP0_VALUE + 0 + 32 + read-only + + + + + CAP_CH1 + 0x100 + 0x20 + + + CAP1_VALUE + 0 + 32 + read-only + + + + + CAP_CH2 + 0x104 + 0x20 + + + CAP2_VALUE + 0 + 32 + read-only + + + + + CAP_STATUS + 0x108 + 0x20 + + + CAP0_EDGE + 0 + 1 + read-only + + + CAP1_EDGE + 1 + 1 + read-only + + + CAP2_EDGE + 2 + 1 + read-only + + + + + UPDATE_CFG + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + 1 + 1 + read-write + + + OP0_UP_EN + 2 + 1 + read-write + + + OP0_FORCE_UP + 3 + 1 + read-write + + + OP1_UP_EN + 4 + 1 + read-write + + + OP1_FORCE_UP + 5 + 1 + read-write + + + OP2_UP_EN + 6 + 1 + read-write + + + OP2_FORCE_UP + 7 + 1 + read-write + + + + + INT_ENA + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + 8 + 1 + read-write + + + FAULT0_INT_ENA + 9 + 1 + read-write + + + FAULT1_INT_ENA + 10 + 1 + read-write + + + FAULT2_INT_ENA + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + 14 + 1 + read-write + + + OP0_TEA_INT_ENA + 15 + 1 + read-write + + + OP1_TEA_INT_ENA + 16 + 1 + read-write + + + OP2_TEA_INT_ENA + 17 + 1 + read-write + + + OP0_TEB_INT_ENA + 18 + 1 + read-write + + + OP1_TEB_INT_ENA + 19 + 1 + read-write + + + OP2_TEB_INT_ENA + 20 + 1 + read-write + + + FH0_CBC_INT_ENA + 21 + 1 + read-write + + + FH1_CBC_INT_ENA + 22 + 1 + read-write + + + FH2_CBC_INT_ENA + 23 + 1 + read-write + + + FH0_OST_INT_ENA + 24 + 1 + read-write + + + FH1_OST_INT_ENA + 25 + 1 + read-write + + + FH2_OST_INT_ENA + 26 + 1 + read-write + + + CAP0_INT_ENA + 27 + 1 + read-write + + + CAP1_INT_ENA + 28 + 1 + read-write + + + CAP2_INT_ENA + 29 + 1 + read-write + + + + + INT_RAW + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + 0 + 1 + read-only + + + TIMER1_STOP_INT_RAW + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + 7 + 1 + read-only + + + TIMER2_TEP_INT_RAW + 8 + 1 + read-only + + + FAULT0_INT_RAW + 9 + 1 + read-only + + + FAULT1_INT_RAW + 10 + 1 + read-only + + + FAULT2_INT_RAW + 11 + 1 + read-only + + + FAULT0_CLR_INT_RAW + 12 + 1 + read-only + + + FAULT1_CLR_INT_RAW + 13 + 1 + read-only + + + FAULT2_CLR_INT_RAW + 14 + 1 + read-only + + + OP0_TEA_INT_RAW + 15 + 1 + read-only + + + OP1_TEA_INT_RAW + 16 + 1 + read-only + + + OP2_TEA_INT_RAW + 17 + 1 + read-only + + + OP0_TEB_INT_RAW + 18 + 1 + read-only + + + OP1_TEB_INT_RAW + 19 + 1 + read-only + + + OP2_TEB_INT_RAW + 20 + 1 + read-only + + + FH0_CBC_INT_RAW + 21 + 1 + read-only + + + FH1_CBC_INT_RAW + 22 + 1 + read-only + + + FH2_CBC_INT_RAW + 23 + 1 + read-only + + + FH0_OST_INT_RAW + 24 + 1 + read-only + + + FH1_OST_INT_RAW + 25 + 1 + read-only + + + FH2_OST_INT_RAW + 26 + 1 + read-only + + + CAP0_INT_RAW + 27 + 1 + read-only + + + CAP1_INT_RAW + 28 + 1 + read-only + + + CAP2_INT_RAW + 29 + 1 + read-only + + + + + INT_ST + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + 8 + 1 + read-only + + + FAULT0_INT_ST + 9 + 1 + read-only + + + FAULT1_INT_ST + 10 + 1 + read-only + + + FAULT2_INT_ST + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + 14 + 1 + read-only + + + OP0_TEA_INT_ST + 15 + 1 + read-only + + + OP1_TEA_INT_ST + 16 + 1 + read-only + + + OP2_TEA_INT_ST + 17 + 1 + read-only + + + OP0_TEB_INT_ST + 18 + 1 + read-only + + + OP1_TEB_INT_ST + 19 + 1 + read-only + + + OP2_TEB_INT_ST + 20 + 1 + read-only + + + FH0_CBC_INT_ST + 21 + 1 + read-only + + + FH1_CBC_INT_ST + 22 + 1 + read-only + + + FH2_CBC_INT_ST + 23 + 1 + read-only + + + FH0_OST_INT_ST + 24 + 1 + read-only + + + FH1_OST_INT_ST + 25 + 1 + read-only + + + FH2_OST_INT_ST + 26 + 1 + read-only + + + CAP0_INT_ST + 27 + 1 + read-only + + + CAP1_INT_ST + 28 + 1 + read-only + + + CAP2_INT_ST + 29 + 1 + read-only + + + + + INT_CLR + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + 8 + 1 + write-only + + + FAULT0_INT_CLR + 9 + 1 + write-only + + + FAULT1_INT_CLR + 10 + 1 + write-only + + + FAULT2_INT_CLR + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + 14 + 1 + write-only + + + OP0_TEA_INT_CLR + 15 + 1 + write-only + + + OP1_TEA_INT_CLR + 16 + 1 + write-only + + + OP2_TEA_INT_CLR + 17 + 1 + write-only + + + OP0_TEB_INT_CLR + 18 + 1 + write-only + + + OP1_TEB_INT_CLR + 19 + 1 + write-only + + + OP2_TEB_INT_CLR + 20 + 1 + write-only + + + FH0_CBC_INT_CLR + 21 + 1 + write-only + + + FH1_CBC_INT_CLR + 22 + 1 + write-only + + + FH2_CBC_INT_CLR + 23 + 1 + write-only + + + FH0_OST_INT_CLR + 24 + 1 + write-only + + + FH1_OST_INT_CLR + 25 + 1 + write-only + + + FH2_OST_INT_CLR + 26 + 1 + write-only + + + CAP0_INT_CLR + 27 + 1 + write-only + + + CAP1_INT_CLR + 28 + 1 + write-only + + + CAP2_INT_CLR + 29 + 1 + write-only + + + + + CLK + 0x120 + 0x20 + + + EN + 0 + 1 + read-write + + + + + VERSION + 0x124 + 0x20 + 0x02107230 + + + DATE + 0 + 28 + read-write + + + + + + + PWM1 + Motor Control Pulse-Width Modulation + 0x3FF6C000 + + PWM1 + 40 + + + + NRX + Peripheral NRX + NRX + 0x3FF5CC00 + + 0x0 + 0x4 + registers + + + + NRXPD_CTRL + WiFi RX control register + 0xD4 + 0x20 + + + DEMAP_FORCE_PD + 0 + 1 + read-write + + + DEMAP_FORCE_PU + 1 + 1 + read-write + + + VIT_FORCE_PD + 2 + 1 + read-write + + + VIT_FORCE_PU + 3 + 1 + read-write + + + RX_ROT_FORCE_PD + 4 + 1 + read-write + + + RX_ROT_FORCE_PU + 5 + 1 + read-write + + + CHAN_EST_FORCE_PD + 6 + 1 + read-write + + + CHAN_EST_FORCE_PU + 7 + 1 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x3FF57000 + + 0x0 + 0xB8 + registers + + + PCNT + 48 + + + + U0_CONF0 + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U0 + This register is used to filter pluse whose width is smaller than this value for unit0. + 0 + 10 + read-write + + + FILTER_EN_U0 + This is the enable bit for filtering input signals for unit0. + 10 + 1 + read-write + + + THR_ZERO_EN_U0 + This is the enable bit for comparing unit0's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U0 + This is the enable bit for comparing unit0's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U0 + This is the enable bit for comparing unit0's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U0 + This is the enable bit for comparing unit0's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U0 + This is the enable bit for comparing unit0's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U0 + This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U0 + This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U0 + This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U0 + This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U0 + This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U0 + This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U0 + This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U0 + This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U0_CONF1 + 0x4 + 0x20 + + + CNT_THRES0_U0 + This register is used to configure thres0 value for unit0. + 0 + 16 + read-write + + + CNT_THRES1_U0 + This register is used to configure thres1 value for unit0. + 16 + 16 + read-write + + + + + U0_CONF2 + 0x8 + 0x20 + + + CNT_H_LIM_U0 + This register is used to configure thr_h_lim value for unit0. + 0 + 16 + read-write + + + CNT_L_LIM_U0 + This register is used to confiugre thr_l_lim value for unit0. + 16 + 16 + read-write + + + + + U1_CONF0 + 0xC + 0x20 + 0x00003C10 + + + FILTER_THRES_U1 + This register is used to filter pluse whose width is smaller than this value for unit1. + 0 + 10 + read-write + + + FILTER_EN_U1 + This is the enable bit for filtering input signals for unit1. + 10 + 1 + read-write + + + THR_ZERO_EN_U1 + This is the enable bit for comparing unit1's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U1 + This is the enable bit for comparing unit1's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U1 + This is the enable bit for comparing unit1's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U1 + This is the enable bit for comparing unit1's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U1 + This is the enable bit for comparing unit1's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U1 + This register is used to control the mode of channel0's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U1 + This register is used to control the mode of channel0's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U1 + This register is used to control the mode of channel0's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U1 + This register is used to control the mode of channel0's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U1 + This register is used to control the mode of channel1's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U1 + This register is used to control the mode of channel1's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U1 + This register is used to control the mode of channel1's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U1 + This register is used to control the mode of channel1's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U1_CONF1 + 0x10 + 0x20 + + + CNT_THRES0_U1 + This register is used to configure thres0 value for unit1. + 0 + 16 + read-write + + + CNT_THRES1_U1 + This register is used to configure thres1 value for unit1. + 16 + 16 + read-write + + + + + U1_CONF2 + 0x14 + 0x20 + + + CNT_H_LIM_U1 + This register is used to configure thr_h_lim value for unit1. + 0 + 16 + read-write + + + CNT_L_LIM_U1 + This register is used to confiugre thr_l_lim value for unit1. + 16 + 16 + read-write + + + + + U2_CONF0 + 0x18 + 0x20 + 0x00003C10 + + + FILTER_THRES_U2 + This register is used to filter pluse whose width is smaller than this value for unit2. + 0 + 10 + read-write + + + FILTER_EN_U2 + This is the enable bit for filtering input signals for unit2. + 10 + 1 + read-write + + + THR_ZERO_EN_U2 + This is the enable bit for comparing unit2's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U2 + This is the enable bit for comparing unit2's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U2 + This is the enable bit for comparing unit2's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U2 + This is the enable bit for comparing unit2's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U2 + This is the enable bit for comparing unit2's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U2 + This register is used to control the mode of channel0's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U2 + This register is used to control the mode of channel0's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U2 + This register is used to control the mode of channel0's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U2 + This register is used to control the mode of channel0's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U2 + This register is used to control the mode of channel1's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U2 + This register is used to control the mode of channel1's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U2 + This register is used to control the mode of channel1's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U2 + This register is used to control the mode of channel1's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U2_CONF1 + 0x1C + 0x20 + + + CNT_THRES0_U2 + This register is used to configure thres0 value for unit2. + 0 + 16 + read-write + + + CNT_THRES1_U2 + This register is used to configure thres1 value for unit2. + 16 + 16 + read-write + + + + + U2_CONF2 + 0x20 + 0x20 + + + CNT_H_LIM_U2 + This register is used to configure thr_h_lim value for unit2. + 0 + 16 + read-write + + + CNT_L_LIM_U2 + This register is used to confiugre thr_l_lim value for unit2. + 16 + 16 + read-write + + + + + U3_CONF0 + 0x24 + 0x20 + 0x00003C10 + + + FILTER_THRES_U3 + This register is used to filter pluse whose width is smaller than this value for unit3. + 0 + 10 + read-write + + + FILTER_EN_U3 + This is the enable bit for filtering input signals for unit3. + 10 + 1 + read-write + + + THR_ZERO_EN_U3 + This is the enable bit for comparing unit3's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U3 + This is the enable bit for comparing unit3's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U3 + This is the enable bit for comparing unit3's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U3 + This is the enable bit for comparing unit3's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U3 + This is the enable bit for comparing unit3's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U3 + This register is used to control the mode of channel0's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U3 + This register is used to control the mode of channel0's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U3 + This register is used to control the mode of channel0's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U3 + This register is used to control the mode of channel0's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U3 + This register is used to control the mode of channel1's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U3 + This register is used to control the mode of channel1's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U3 + This register is used to control the mode of channel1's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U3 + This register is used to control the mode of channel1's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U3_CONF1 + 0x28 + 0x20 + + + CNT_THRES0_U3 + This register is used to configure thres0 value for unit3. + 0 + 16 + read-write + + + CNT_THRES1_U3 + This register is used to configure thres1 value for unit3. + 16 + 16 + read-write + + + + + U3_CONF2 + 0x2C + 0x20 + + + CNT_H_LIM_U3 + This register is used to configure thr_h_lim value for unit3. + 0 + 16 + read-write + + + CNT_L_LIM_U3 + This register is used to confiugre thr_l_lim value for unit3. + 16 + 16 + read-write + + + + + U4_CONF0 + 0x30 + 0x20 + 0x00003C10 + + + FILTER_THRES_U4 + This register is used to filter pluse whose width is smaller than this value for unit4. + 0 + 10 + read-write + + + FILTER_EN_U4 + This is the enable bit for filtering input signals for unit4. + 10 + 1 + read-write + + + THR_ZERO_EN_U4 + This is the enable bit for comparing unit4's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U4 + This is the enable bit for comparing unit4's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U4 + This is the enable bit for comparing unit4's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U4 + This is the enable bit for comparing unit4's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U4 + This is the enable bit for comparing unit4's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U4 + This register is used to control the mode of channel0's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U4 + This register is used to control the mode of channel0's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U4 + This register is used to control the mode of channel0's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U4 + This register is used to control the mode of channel0's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U4 + This register is used to control the mode of channel1's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U4 + This register is used to control the mode of channel1's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U4 + This register is used to control the mode of channel1's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U4 + This register is used to control the mode of channel1's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U4_CONF1 + 0x34 + 0x20 + + + CNT_THRES0_U4 + This register is used to configure thres0 value for unit4. + 0 + 16 + read-write + + + CNT_THRES1_U4 + This register is used to configure thres1 value for unit4. + 16 + 16 + read-write + + + + + U4_CONF2 + 0x38 + 0x20 + + + CNT_H_LIM_U4 + This register is used to configure thr_h_lim value for unit4. + 0 + 16 + read-write + + + CNT_L_LIM_U4 + This register is used to confiugre thr_l_lim value for unit4. + 16 + 16 + read-write + + + + + U5_CONF0 + 0x3C + 0x20 + 0x00003C10 + + + FILTER_THRES_U5 + This register is used to filter pluse whose width is smaller than this value for unit5. + 0 + 10 + read-write + + + FILTER_EN_U5 + This is the enable bit for filtering input signals for unit5. + 10 + 1 + read-write + + + THR_ZERO_EN_U5 + This is the enable bit for comparing unit5's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U5 + This is the enable bit for comparing unit5's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U5 + This is the enable bit for comparing unit5's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U5 + This is the enable bit for comparing unit5's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U5 + This is the enable bit for comparing unit5's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U5 + This register is used to control the mode of channel0's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U5 + This register is used to control the mode of channel0's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U5 + This register is used to control the mode of channel0's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U5 + This register is used to control the mode of channel0's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U5 + This register is used to control the mode of channel1's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U5 + This register is used to control the mode of channel1's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U5 + This register is used to control the mode of channel1's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U5 + This register is used to control the mode of channel1's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U5_CONF1 + 0x40 + 0x20 + + + CNT_THRES0_U5 + This register is used to configure thres0 value for unit5. + 0 + 16 + read-write + + + CNT_THRES1_U5 + This register is used to configure thres1 value for unit5. + 16 + 16 + read-write + + + + + U5_CONF2 + 0x44 + 0x20 + + + CNT_H_LIM_U5 + This register is used to configure thr_h_lim value for unit5. + 0 + 16 + read-write + + + CNT_L_LIM_U5 + This register is used to confiugre thr_l_lim value for unit5. + 16 + 16 + read-write + + + + + U6_CONF0 + 0x48 + 0x20 + 0x00003C10 + + + FILTER_THRES_U6 + This register is used to filter pluse whose width is smaller than this value for unit6. + 0 + 10 + read-write + + + FILTER_EN_U6 + This is the enable bit for filtering input signals for unit6. + 10 + 1 + read-write + + + THR_ZERO_EN_U6 + This is the enable bit for comparing unit6's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U6 + This is the enable bit for comparing unit6's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U6 + This is the enable bit for comparing unit6's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U6 + This is the enable bit for comparing unit6's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U6 + This is the enable bit for comparing unit6's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U6 + This register is used to control the mode of channel0's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U6 + This register is used to control the mode of channel0's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U6 + This register is used to control the mode of channel0's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U6 + This register is used to control the mode of channel0's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U6 + This register is used to control the mode of channel1's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U6 + This register is used to control the mode of channel1's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U6 + This register is used to control the mode of channel1's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U6 + This register is used to control the mode of channel1's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U6_CONF1 + 0x4C + 0x20 + + + CNT_THRES0_U6 + This register is used to configure thres0 value for unit6. + 0 + 16 + read-write + + + CNT_THRES1_U6 + This register is used to configure thres1 value for unit6. + 16 + 16 + read-write + + + + + U6_CONF2 + 0x50 + 0x20 + + + CNT_H_LIM_U6 + This register is used to configure thr_h_lim value for unit6. + 0 + 16 + read-write + + + CNT_L_LIM_U6 + This register is used to confiugre thr_l_lim value for unit6. + 16 + 16 + read-write + + + + + U7_CONF0 + 0x54 + 0x20 + 0x00003C10 + + + FILTER_THRES_U7 + This register is used to filter pluse whose width is smaller than this value for unit7. + 0 + 10 + read-write + + + FILTER_EN_U7 + This is the enable bit for filtering input signals for unit7. + 10 + 1 + read-write + + + THR_ZERO_EN_U7 + This is the enable bit for comparing unit7's count with 0 value. + 11 + 1 + read-write + + + THR_H_LIM_EN_U7 + This is the enable bit for comparing unit7's count with thr_h_lim value. + 12 + 1 + read-write + + + THR_L_LIM_EN_U7 + This is the enable bit for comparing unit7's count with thr_l_lim value. + 13 + 1 + read-write + + + THR_THRES0_EN_U7 + This is the enable bit for comparing unit7's count with thres0 value. + 14 + 1 + read-write + + + THR_THRES1_EN_U7 + This is the enable bit for comparing unit7's count with thres1 value . + 15 + 1 + read-write + + + CH0_NEG_MODE_U7 + This register is used to control the mode of channel0's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 16 + 2 + read-write + + + CH0_POS_MODE_U7 + This register is used to control the mode of channel0's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U7 + This register is used to control the mode of channel0's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U7 + This register is used to control the mode of channel0's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 22 + 2 + read-write + + + CH1_NEG_MODE_U7 + This register is used to control the mode of channel1's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden + 24 + 2 + read-write + + + CH1_POS_MODE_U7 + This register is used to control the mode of channel1's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U7 + This register is used to control the mode of channel1's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U7 + This register is used to control the mode of channel1's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden + 30 + 2 + read-write + + + + + U7_CONF1 + 0x58 + 0x20 + + + CNT_THRES0_U7 + This register is used to configure thres0 value for unit7. + 0 + 16 + read-write + + + CNT_THRES1_U7 + This register is used to configure thres1 value for unit7. + 16 + 16 + read-write + + + + + U7_CONF2 + 0x5C + 0x20 + + + CNT_H_LIM_U7 + This register is used to configure thr_h_lim value for unit7. + 0 + 16 + read-write + + + CNT_L_LIM_U7 + This register is used to confiugre thr_l_lim value for unit7. + 16 + 16 + read-write + + + + + U0_CNT + 0x60 + 0x20 + + + PLUS_CNT_U0 + This register stores the current pulse count value for unit0. + 0 + 16 + read-only + + + + + U1_CNT + 0x64 + 0x20 + + + PLUS_CNT_U1 + This register stores the current pulse count value for unit1. + 0 + 16 + read-only + + + + + U2_CNT + 0x68 + 0x20 + + + PLUS_CNT_U2 + This register stores the current pulse count value for unit2. + 0 + 16 + read-only + + + + + U3_CNT + 0x6C + 0x20 + + + PLUS_CNT_U3 + This register stores the current pulse count value for unit3. + 0 + 16 + read-only + + + + + U4_CNT + 0x70 + 0x20 + + + PLUS_CNT_U4 + This register stores the current pulse count value for unit4. + 0 + 16 + read-only + + + + + U5_CNT + 0x74 + 0x20 + + + PLUS_CNT_U5 + This register stores the current pulse count value for unit5. + 0 + 16 + read-only + + + + + U6_CNT + 0x78 + 0x20 + + + PLUS_CNT_U6 + This register stores the current pulse count value for unit6. + 0 + 16 + read-only + + + + + U7_CNT + 0x7C + 0x20 + + + PLUS_CNT_U7 + This register stores the current pulse count value for unit7. + 0 + 16 + read-only + + + + + INT_RAW + 0x80 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + This is the interrupt raw bit for channel0 event. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + This is the interrupt raw bit for channel1 event. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + This is the interrupt raw bit for channel2 event. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + This is the interrupt raw bit for channel3 event. + 3 + 1 + read-only + + + CNT_THR_EVENT_U4_INT_RAW + This is the interrupt raw bit for channel4 event. + 4 + 1 + read-only + + + CNT_THR_EVENT_U5_INT_RAW + This is the interrupt raw bit for channel5 event. + 5 + 1 + read-only + + + CNT_THR_EVENT_U6_INT_RAW + This is the interrupt raw bit for channel6 event. + 6 + 1 + read-only + + + CNT_THR_EVENT_U7_INT_RAW + This is the interrupt raw bit for channel7 event. + 7 + 1 + read-only + + + + + INT_ST + 0x84 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + This is the interrupt status bit for channel0 event. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + This is the interrupt status bit for channel1 event. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + This is the interrupt status bit for channel2 event. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + This is the interrupt status bit for channel3 event. + 3 + 1 + read-only + + + CNT_THR_EVENT_U4_INT_ST + This is the interrupt status bit for channel4 event. + 4 + 1 + read-only + + + CNT_THR_EVENT_U5_INT_ST + This is the interrupt status bit for channel5 event. + 5 + 1 + read-only + + + CNT_THR_EVENT_U6_INT_ST + This is the interrupt status bit for channel6 event. + 6 + 1 + read-only + + + CNT_THR_EVENT_U7_INT_ST + This is the interrupt status bit for channel7 event. + 7 + 1 + read-only + + + + + INT_ENA + 0x88 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + This is the interrupt enable bit for channel0 event. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + This is the interrupt enable bit for channel1 event. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + This is the interrupt enable bit for channel2 event. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + This is the interrupt enable bit for channel3 event. + 3 + 1 + read-write + + + CNT_THR_EVENT_U4_INT_ENA + This is the interrupt enable bit for channel4 event. + 4 + 1 + read-write + + + CNT_THR_EVENT_U5_INT_ENA + This is the interrupt enable bit for channel5 event. + 5 + 1 + read-write + + + CNT_THR_EVENT_U6_INT_ENA + This is the interrupt enable bit for channel6 event. + 6 + 1 + read-write + + + CNT_THR_EVENT_U7_INT_ENA + This is the interrupt enable bit for channel7 event. + 7 + 1 + read-write + + + + + INT_CLR + 0x8C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear channel0 event interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear channel1 event interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear channel2 event interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear channel3 event interrupt. + 3 + 1 + write-only + + + CNT_THR_EVENT_U4_INT_CLR + Set this bit to clear channel4 event interrupt. + 4 + 1 + write-only + + + CNT_THR_EVENT_U5_INT_CLR + Set this bit to clear channel5 event interrupt. + 5 + 1 + write-only + + + CNT_THR_EVENT_U6_INT_CLR + Set this bit to clear channel6 event interrupt. + 6 + 1 + write-only + + + CNT_THR_EVENT_U7_INT_CLR + Set this bit to clear channel7 event interrupt. + 7 + 1 + write-only + + + + + U0_STATUS + 0x90 + 0x20 + + + CORE_STATUS_U0 + 0 + 32 + read-only + + + STATUS_CNT_MODE + 0 + 2 + read-write + + + STATUS_THRES1 + 2 + 1 + read-write + + + STATUS_THRES0 + 3 + 1 + read-write + + + STATUS_L_LIM + 4 + 1 + read-write + + + STATUS_H_LIM + 5 + 1 + read-write + + + STATUS_ZERO + 6 + 1 + read-write + + + + + U1_STATUS + 0x94 + 0x20 + + + CORE_STATUS_U1 + 0 + 32 + read-only + + + + + U2_STATUS + 0x98 + 0x20 + + + CORE_STATUS_U2 + 0 + 32 + read-only + + + + + U3_STATUS + 0x9C + 0x20 + + + CORE_STATUS_U3 + 0 + 32 + read-only + + + + + U4_STATUS + 0xA0 + 0x20 + + + CORE_STATUS_U4 + 0 + 32 + read-only + + + + + U5_STATUS + 0xA4 + 0x20 + + + CORE_STATUS_U5 + 0 + 32 + read-only + + + + + U6_STATUS + 0xA8 + 0x20 + + + CORE_STATUS_U6 + 0 + 32 + read-only + + + + + U7_STATUS + 0xAC + 0x20 + + + CORE_STATUS_U7 + 0 + 32 + read-only + + + + + CTRL + 0xB0 + 0x20 + 0x00005555 + + + PLUS_CNT_RST_U0 + Set this bit to clear unit0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to pause unit0's counter. + 1 + 1 + read-write + + + PLUS_CNT_RST_U1 + Set this bit to clear unit1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to pause unit1's counter. + 3 + 1 + read-write + + + PLUS_CNT_RST_U2 + Set this bit to clear unit2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to pause unit2's counter. + 5 + 1 + read-write + + + PLUS_CNT_RST_U3 + Set this bit to clear unit3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to pause unit3's counter. + 7 + 1 + read-write + + + PLUS_CNT_RST_U4 + Set this bit to clear unit4's counter. + 8 + 1 + read-write + + + CNT_PAUSE_U4 + Set this bit to pause unit4's counter. + 9 + 1 + read-write + + + PLUS_CNT_RST_U5 + Set this bit to clear unit5's counter. + 10 + 1 + read-write + + + CNT_PAUSE_U5 + Set this bit to pause unit5's counter. + 11 + 1 + read-write + + + PLUS_CNT_RST_U6 + Set this bit to clear unit6's counter. + 12 + 1 + read-write + + + CNT_PAUSE_U6 + Set this bit to pause unit6's counter. + 13 + 1 + read-write + + + PLUS_CNT_RST_U7 + Set this bit to clear unit7's counter. + 14 + 1 + read-write + + + CNT_PAUSE_U7 + Set this bit to pause unit7's counter. + 15 + 1 + read-write + + + CLK_EN + 16 + 1 + read-write + + + + + DATE + 0xFC + 0x20 + 0x14122600 + + + DATE + 0 + 32 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x3FF56000 + + 0x0 + 0xF8 + registers + + + RMT + 47 + + + + CH0DATA + 0x0 + 0x20 + + + CH1DATA + 0x4 + 0x20 + + + CH2DATA + 0x8 + 0x20 + + + CH3DATA + 0xC + 0x20 + + + CH4DATA + 0x10 + 0x20 + + + CH5DATA + 0x14 + 0x20 + + + CH6DATA + 0x18 + 0x20 + + + CH7DATA + 0x1C + 0x20 + + + 8 + 0x8 + 0-7 + CH%sCONF0 + 0x20 + 0x20 + 0x31100002 + + + DIV_CNT + This register is used to configure the frequency divider's factor in channel0. + 0 + 8 + read-write + + + IDLE_THRES + In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done. + 8 + 16 + read-write + + + MEM_SIZE + This register is used to configure the the amount of memory blocks allocated to channel0. + 24 + 4 + read-write + + + CARRIER_EN + This is the carrier modulation enable control bit for channel0. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the way carrier wave is modulated for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level. + 29 + 1 + read-write + + + MEM_PD + This bit is used to reduce power consumed by mem. 1:mem is in low power state. + 30 + 1 + read-write + + + CLK_EN + This bit is used to control clock.when software config RMT internal registers it controls the register clock. + 31 + 1 + read-write + + + + + 8 + 0x8 + 0-7 + CH%sCONF1 + 0x24 + 0x20 + 0x00000F20 + + + TX_START + Set this bit to start sending data for channel0. + 0 + 1 + read-write + + + RX_EN + Set this bit to enbale receving data for channel0. + 1 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for channel0 by receiver access. + 2 + 1 + read-write + + + MEM_RD_RST + Set this bit to reset read ram address for channel0 by transmitter access. + 3 + 1 + read-write + + + APB_MEM_RST + Set this bit to reset W/R ram address for channel0 by apb fifo access + 4 + 1 + read-write + + + MEM_OWNER + This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram + 5 + 1 + read-write + + + TX_CONTI_MODE + Set this bit to continue sending from the first data to the last data in channel0 again and again. + 6 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter enable bit for channel0. + 7 + 1 + read-write + + + RX_FILTER_THRES + in receive mode channel0 ignore input pulse when the pulse width is smaller then this value. + 8 + 8 + read-write + + + REF_CNT_RST + This bit is used to reset divider in channel0. + 16 + 1 + read-write + + + REF_ALWAYS_ON + This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref + 17 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the output signal's level for channel0 in IDLE state. + 18 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable control bit for channel0 in IDLE state. + 19 + 1 + read-write + + + + + CH0STATUS + 0x60 + 0x20 + + + STATUS + The status for channel0 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel0. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel0. + 12 + 10 + read-only + + + STATE + The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH1STATUS + 0x64 + 0x20 + + + STATUS + The status for channel1 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel1. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel1. + 12 + 10 + read-only + + + STATE + The channel1 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel1 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel1 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel1. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel1 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel1 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH2STATUS + 0x68 + 0x20 + + + STATUS + The status for channel2 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel2. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel2. + 12 + 10 + read-only + + + STATE + The channel2 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel2 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel2 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel2. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel2 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel2 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH3STATUS + 0x6C + 0x20 + + + STATUS + The status for channel3 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel3. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel3. + 12 + 10 + read-only + + + STATE + The channel3 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel3 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel3 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel3. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel3 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel3 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH4STATUS + 0x70 + 0x20 + + + STATUS + The status for channel4 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel4. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel4. + 12 + 10 + read-only + + + STATE + The channel4 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel4 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel4 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel4. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel4 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel4 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH5STATUS + 0x74 + 0x20 + + + STATUS + The status for channel5 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel5. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel5. + 12 + 10 + read-only + + + STATE + The channel5 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel5 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel5 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel5. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel5 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel5 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH6STATUS + 0x78 + 0x20 + + + STATUS + The status for channel6 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel6. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel6. + 12 + 10 + read-only + + + STATE + The channel6 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel6 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel6 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel6. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel6 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel6 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH7STATUS + 0x7C + 0x20 + + + STATUS + The status for channel7 + 0 + 32 + read-only + + + MEM_WADDR_EX + The current memory read address of channel7. + 0 + 10 + read-only + + + MEM_RADDR_EX + The current memory write address of channel7. + 12 + 10 + read-only + + + STATE + The channel7 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. + 24 + 3 + read-only + + + MEM_OWNER_ERR + When channel7 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. + 27 + 1 + read-only + + + MEM_FULL + The memory full status bit for channel7 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + 28 + 1 + read-only + + + MEM_EMPTY + The memory empty status bit for channel7. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. + 29 + 1 + read-only + + + APB_MEM_WR_ERR + The apb write memory status bit for channel7 turns to high level when the apb write address exceeds the configuration range. + 30 + 1 + read-only + + + APB_MEM_RD_ERR + The apb read memory status bit for channel7 turns to high level when the apb read address exceeds the configuration range. + 31 + 1 + read-only + + + + + CH0ADDR + 0x80 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel0 by apb fifo access + 0 + 32 + read-only + + + + + CH1ADDR + 0x84 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel1 by apb fifo access + 0 + 32 + read-only + + + + + CH2ADDR + 0x88 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel2 by apb fifo access + 0 + 32 + read-only + + + + + CH3ADDR + 0x8C + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel3 by apb fifo access + 0 + 32 + read-only + + + + + CH4ADDR + 0x90 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel4 by apb fifo access + 0 + 32 + read-only + + + + + CH5ADDR + 0x94 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel5 by apb fifo access + 0 + 32 + read-only + + + + + CH6ADDR + 0x98 + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel6 by apb fifo access + 0 + 32 + read-only + + + + + CH7ADDR + 0x9C + 0x20 + + + APB_MEM_ADDR + The ram relative address in channel7 by apb fifo access + 0 + 32 + read-only + + + + + INT_RAW + 0xA0 + 0x20 + + + 8 + 0x3 + 0-7 + CH%s_TX_END_INT_RAW + The interrupt raw bit for channel %s turns to high level when the transmit process is done. + 0 + 1 + read-only + + + 8 + 0x3 + 0-7 + CH%s_RX_END_INT_RAW + The interrupt raw bit for channel %s turns to high level when the receive process is done. + 1 + 1 + read-only + + + 8 + 0x3 + 0-7 + CH%s_ERR_INT_RAW + The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + 2 + 1 + read-only + + + 8 + 0x1 + 0-7 + CH%s_TX_THR_EVENT_INT_RAW + The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + 24 + 1 + read-only + + + + + INT_ST + 0xA4 + 0x20 + + + 8 + 0x3 + 0-7 + CH%s_TX_END_INT_ST + The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + 0 + 1 + read-only + + + 8 + 0x3 + 0-7 + CH%s_RX_END_INT_ST + The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + 1 + 1 + read-only + + + 8 + 0x3 + 0-7 + CH%s_ERR_INT_ST + The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + 2 + 1 + read-only + + + 8 + 0x1 + 0-7 + CH%s_TX_THR_EVENT_INT_ST + The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + 24 + 1 + read-only + + + + + INT_ENA + 0xA8 + 0x20 + + + 8 + 0x3 + 0-7 + CH%s_TX_END_INT_ENA + Set this bit to enable rmt_ch%s_tx_end_int_st. + 0 + 1 + read-write + + + 8 + 0x3 + 0-7 + CH%s_RX_END_INT_ENA + Set this bit to enable rmt_ch%s_rx_end_int_st. + 1 + 1 + read-write + + + 8 + 0x3 + 0-7 + CH%s_ERR_INT_ENA + Set this bit to enable rmt_ch%s_err_int_st. + 2 + 1 + read-write + + + 8 + 0x1 + 0-7 + CH%s_TX_THR_EVENT_INT_ENA + Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + 24 + 1 + read-write + + + + + INT_CLR + 0xAC + 0x20 + + + 8 + 0x3 + 0-7 + CH%s_TX_END_INT_CLR + Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + 0 + 1 + write-only + + + 8 + 0x3 + 0-7 + CH%s_RX_END_INT_CLR + Set this bit to clear the rmt_ch%s_tx_end_int_raw. + 1 + 1 + write-only + + + 8 + 0x3 + 0-7 + CH%s_ERR_INT_CLR + Set this bit to clear the rmt_ch%s_err_int_raw. + 2 + 1 + write-only + + + 8 + 0x1 + 0-7 + CH%s_TX_THR_EVENT_INT_CLR + Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + 24 + 1 + write-only + + + + + CH0CARRIER_DUTY + 0xB0 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel0. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel0. + 16 + 16 + read-write + + + + + CH1CARRIER_DUTY + 0xB4 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel1. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel1. + 16 + 16 + read-write + + + + + CH2CARRIER_DUTY + 0xB8 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel2. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel2. + 16 + 16 + read-write + + + + + CH3CARRIER_DUTY + 0xBC + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel3. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel3. + 16 + 16 + read-write + + + + + CH4CARRIER_DUTY + 0xC0 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel4. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel4. + 16 + 16 + read-write + + + + + CH5CARRIER_DUTY + 0xC4 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel5. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel5. + 16 + 16 + read-write + + + + + CH6CARRIER_DUTY + 0xC8 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel6. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel6. + 16 + 16 + read-write + + + + + CH7CARRIER_DUTY + 0xCC + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave's low level value for channel7. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave's high level value for channel7. + 16 + 16 + read-write + + + + + 8 + 0x4 + 0-7 + CH%s_TX_LIM + 0xD0 + 0x20 + 0x00000080 + + + TX_LIM + When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt. + 0 + 9 + read-write + + + + + APB_CONF + 0xF0 + 0x20 + + + APB_FIFO_MASK + Set this bit to disable apb fifo access + 0 + 1 + read-write + + + MEM_TX_WRAP_EN + when datas need to be send is more than channel's mem can store then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn. + 1 + 1 + read-write + + + + + DATE + 0xFC + 0x20 + 0x16022600 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60035000 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x144 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x3FF02000 + + 0x0 + 0x1C + registers + + + RSA + 51 + + + + M_PRIME + 0x0 + 0x20 + + + M_PRIME + This register contains M’. + 0 + 8 + read-write + + + + + MODEXP_MODE + 0x4 + 0x20 + + + MODEXP_MODE + This register contains the mode of modular exponentiation. + 0 + 2 + read-write + + + + + MODEXP_START + 0x8 + 0x20 + + + MODEXP_START + Write 1 to start modular exponentiation. + 0 + 1 + write-only + + + + + MULT_MODE + 0xC + 0x20 + + + MULT_MODE + This register contains the mode of modular multiplication and multiplication. + 0 + 1 + read-write + + + + + MULT_START + 0x10 + 0x20 + + + MULT_START + Write 1 to start modular multiplication or multiplication. + 0 + 1 + write-only + + + + + INTERRUPT + 0x14 + 0x20 + + + INTERRUPT + RSA interrupt status register. Will read 1 once an operation has completed. + 0 + 1 + read-write + + + + + CLEAN + 0x18 + 0x20 + + + CLEAN + This bit will read 1 once the memory initialization is completed. + 0 + 1 + read-only + + + + + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x3FF48000 + + 0x0 + 0xDC + registers + + + RTC_CORE + 46 + + + + OPTIONS0 + 0x0 + 0x20 + 0x1C492000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset + 4 + 1 + write-only + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + BIAS_SLEEP_FOLW_8M + BIAS_SLEEP follow CK8M + 14 + 1 + read-write + + + BIAS_FORCE_SLEEP + BIAS_SLEEP force sleep + 15 + 1 + read-write + + + BIAS_FORCE_NOSLEEP + BIAS_SLEEP force no sleep + 16 + 1 + read-write + + + BIAS_I2C_FOLW_8M + BIAS_I2C follow CK8M + 17 + 1 + read-write + + + BIAS_I2C_FORCE_PD + BIAS_I2C force power down + 18 + 1 + read-write + + + BIAS_I2C_FORCE_PU + BIAS_I2C force power up + 19 + 1 + read-write + + + BIAS_CORE_FOLW_8M + BIAS_CORE follow CK8M + 20 + 1 + read-write + + + BIAS_CORE_FORCE_PD + BIAS_CORE force power down + 21 + 1 + read-write + + + BIAS_CORE_FORCE_PU + BIAS_CORE force power up + 22 + 1 + read-write + + + XTL_FORCE_ISO + 23 + 1 + read-write + + + PLL_FORCE_ISO + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + 25 + 1 + read-write + + + XTL_FORCE_NOISO + 26 + 1 + read-write + + + PLL_FORCE_NOISO + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + write-only + + + + + SLP_TIMER0 + 0x4 + 0x20 + + + SLP_VAL_LO + RTC sleep timer low 32 bits + 0 + 32 + read-write + + + + + SLP_TIMER1 + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + read-write + + + + + TIME_UPDATE + 0xC + 0x20 + + + TIME_VALID + To indicate the register is updated + 30 + 1 + read-only + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + write-only + + + + + TIME0 + 0x10 + 0x20 + + + TIME_LO + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME1 + 0x14 + 0x20 + + + TIME_HI + RTC timer high 16 bits + 0 + 16 + read-only + + + + + STATE0 + 0x18 + 0x20 + 0x00300000 + + + TOUCH_WAKEUP_FORCE_EN + touch controller force wake up + 20 + 1 + read-write + + + ULP_CP_WAKEUP_FORCE_EN + ULP-coprocessor force wake up + 21 + 1 + read-write + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge 0: APB to RTC using sync + 22 + 1 + read-write + + + TOUCH_SLP_TIMER_EN + touch timer enable bit + 23 + 1 + read-write + + + ULP_CP_SLP_TIMER_EN + ULP-coprocessor timer enable bit + 24 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-only + + + SLP_WAKEUP + sleep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + sleep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + 0x20 + 0x20 + 0x01080000 + + + ULPCP_TOUCH_START_WAIT + wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + 15 + 9 + read-write + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER3 + 0x24 + 0x20 + 0x14160A08 + + + WIFI_WAIT_TIMER + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + 9 + 7 + read-write + + + ROM_RAM_WAIT_TIMER + 16 + 9 + read-write + + + ROM_RAM_POWERUP_TIMER + 25 + 7 + read-write + + + + + TIMER4 + 0x28 + 0x20 + 0x10200A08 + + + WAIT_TIMER + 0 + 9 + read-write + + + POWERUP_TIMER + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + 25 + 7 + read-write + + + + + TIMER5 + 0x2C + 0x20 + 0x12148001 + + + ULP_CP_SUBTIMER_PREDIV + 0 + 8 + read-write + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + RTCMEM_WAIT_TIMER + 16 + 9 + read-write + + + RTCMEM_POWERUP_TIMER + 25 + 7 + read-write + + + + + ANA_CONF + 0x30 + 0x20 + 0x00800000 + + + PLLA_FORCE_PD + PLLA force power down + 23 + 1 + read-write + + + PLLA_FORCE_PU + PLLA force power up + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up otherwise power down + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up otherwise power down + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up otherwise power down + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up otherwise power down + 30 + 1 + read-write + + + PLL_I2C_PU + 1: PLL_I2C power up otherwise power down + 31 + 1 + read-write + + + + + RESET_STATE + 0x34 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + APPCPU_STAT_VECTOR_SEL + APP CPU state vector sel + 12 + 1 + read-write + + + PROCPU_STAT_VECTOR_SEL + PRO CPU state vector sel + 13 + 1 + read-write + + + + + WAKEUP_STATE + 0x38 + 0x20 + 0x00006000 + + + WAKEUP_CAUSE + wakeup cause + 0 + 11 + read-only + + + WAKEUP_ENA + wakeup enable bitmap + 11 + 11 + read-write + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 22 + 1 + read-write + + + + + INT_ENA + 0x3C + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + read-write + + + SDIO_IDLE_INT_ENA + enable SDIO idle interrupt + 2 + 1 + read-write + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + read-write + + + TIME_VALID_INT_ENA + enable RTC time valid interrupt + 4 + 1 + read-write + + + ULP_CP_INT_ENA + enable ULP-coprocessor interrupt + 5 + 1 + read-write + + + TOUCH_INT_ENA + enable touch interrupt + 6 + 1 + read-write + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 7 + 1 + read-write + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 8 + 1 + read-write + + + + + INT_RAW + 0x40 + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-only + + + SDIO_IDLE_INT_RAW + SDIO idle interrupt raw + 2 + 1 + read-only + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-only + + + TIME_VALID_INT_RAW + RTC time valid interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_RAW + ULP-coprocessor interrupt raw + 5 + 1 + read-only + + + TOUCH_INT_RAW + touch interrupt raw + 6 + 1 + read-only + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 7 + 1 + read-only + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 8 + 1 + read-only + + + + + INT_ST + 0x44 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-only + + + SDIO_IDLE_INT_ST + SDIO idle interrupt state + 2 + 1 + read-only + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-only + + + TIME_VALID_INT_ST + RTC time valid interrupt state + 4 + 1 + read-only + + + SAR_INT_ST + ULP-coprocessor interrupt state + 5 + 1 + read-only + + + TOUCH_INT_ST + touch interrupt state + 6 + 1 + read-only + + + BROWN_OUT_INT_ST + brown out interrupt state + 7 + 1 + read-only + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 8 + 1 + read-only + + + + + INT_CLR + 0x48 + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + write-only + + + SDIO_IDLE_INT_CLR + Clear SDIO idle interrupt state + 2 + 1 + write-only + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + write-only + + + TIME_VALID_INT_CLR + Clear RTC time valid interrupt state + 4 + 1 + write-only + + + SAR_INT_CLR + Clear ULP-coprocessor interrupt state + 5 + 1 + write-only + + + TOUCH_INT_CLR + Clear touch interrupt state + 6 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 7 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 8 + 1 + write-only + + + + + STORE0 + 0x4C + 0x20 + + + SCRATCH0 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE1 + 0x50 + 0x20 + + + SCRATCH1 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE2 + 0x54 + 0x20 + + + SCRATCH2 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE3 + 0x58 + 0x20 + + + SCRATCH3 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + EXT_XTL_CONF + 0x5C + 0x20 + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level 1: power down XTAL at low level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + enable control XTAL by external pads + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + 0x60 + 0x20 + + + EXT_WAKEUP0_LV + 0: external wakeup at low level 1: external wakeup at high level + 30 + 1 + read-write + + + EXT_WAKEUP1_LV + 0: external wakeup at low level 1: external wakeup at high level + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + 0x64 + 0x20 + + + GPIO_REJECT_EN + enable GPIO reject + 24 + 1 + read-write + + + SDIO_REJECT_EN + enable SDIO reject + 25 + 1 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 26 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 27 + 1 + read-write + + + REJECT_CAUSE + sleep reject cause + 28 + 4 + read-only + + + + + CPU_PERIOD_CONF + 0x68 + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + CPU period sel + 30 + 2 + read-write + + + + + SDIO_ACT_CONF + 0x6C + 0x20 + + + SDIO_ACT_DNUM + 22 + 10 + read-write + + + + + CLK_CONF + 0x70 + 0x20 + 0x00002210 + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024. + 4 + 2 + read-write + + CK8M_DIV + read-write + + DIV128 + DIV128 + 0 + + + DIV256 + DIV256 + 1 + + + DIV512 + DIV512 + 2 + + + DIV1024 + DIV1024 + 3 + + + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256 + 7 + 1 + read-write + + ENB_CK8M_DIV + read-write + + CK8M_DIV_256 + CK8M_DIV_256 + 0 + + + CK8M + CK8M + 1 + + + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DFREQ_FORCE + 11 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + SOC_CLK_SEL + SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL + 27 + 2 + read-write + + SOC_CLK_SEL + read-write + + XTAL + XTAL + 0 + + + PLL + PLL + 1 + + + CK8M + CK8M + 2 + + + APLL + APLL + 3 + + + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4 1: CK8M + 29 + 1 + read-write + + FAST_CLK_RTC_SEL + read-write + + XTAL_DIV_4 + XTAL_DIV_4 + 0 + + + CK8M + CK8M + 1 + + + + + ANA_CLK_RTC_SEL + slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT + 30 + 2 + read-write + + ANA_CLK_RTC_SEL + read-write + + SLOW_CK + SLOW_CK + 0 + + + CK_XTAL_32K + CK_XTAL_32K + 1 + + + CK8M_D256_OUT + CK8M_D256_OUT + 2 + + + + + + + SDIO_CONF + 0x74 + 0x20 + 0x02A00000 + + + SDIO_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG 0: use state machine + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + REG1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1 + 31 + 1 + read-write + + + + + BIAS_CONF + 0x78 + 0x20 + + + DBG_ATTEN + DBG_ATTEN + 24 + 2 + read-write + + + ENB_SCK_XTAL + ENB_SCK_XTAL + 26 + 1 + read-write + + + INC_HEARTBEAT_REFRESH + INC_HEARTBEAT_REFRESH + 27 + 1 + read-write + + + DEC_HEARTBEAT_PERIOD + DEC_HEARTBEAT_PERIOD + 28 + 1 + read-write + + + INC_HEARTBEAT_PERIOD + INC_HEARTBEAT_PERIOD + 29 + 1 + read-write + + + DEC_HEARTBEAT_WIDTH + DEC_HEARTBEAT_WIDTH + 30 + 1 + read-write + + + RST_BIAS_I2C + RST_BIAS_I2C + 31 + 1 + read-write + + + + + REG + 0x7C + 0x20 + 0x29002400 + + + SCK_DCAP_FORCE + N/A + 7 + 1 + read-write + + + DIG_DBIAS_SLP + DIG_REG_DBIAS during sleep + 8 + 3 + read-write + + + DIG_DBIAS_WAK + DIG_REG_DBIAS during wakeup + 11 + 3 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + DBIAS_SLP + RTC_DBIAS during sleep + 22 + 3 + read-write + + + DBIAS_WAK + RTC_DBIAS during wakeup + 25 + 3 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + FORCE_PU + RTC_REG force power up + 31 + 1 + read-write + + + + + PWC + 0x80 + 0x20 + 0x00012925 + + + FASTMEM_FORCE_NOISO + Fast RTC memory force no ISO + 0 + 1 + read-write + + + FASTMEM_FORCE_ISO + Fast RTC memory force ISO + 1 + 1 + read-write + + + SLOWMEM_FORCE_NOISO + RTC memory force no ISO + 2 + 1 + read-write + + + SLOWMEM_FORCE_ISO + RTC memory force ISO + 3 + 1 + read-write + + + FORCE_ISO + rtc_peri force ISO + 4 + 1 + read-write + + + FORCE_NOISO + rtc_peri force no ISO + 5 + 1 + read-write + + + FASTMEM_FOLW_CPU + 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine + 6 + 1 + read-write + + + FASTMEM_FORCE_LPD + Fast RTC memory force PD + 7 + 1 + read-write + + + FASTMEM_FORCE_LPU + Fast RTC memory force no PD + 8 + 1 + read-write + + + SLOWMEM_FOLW_CPU + 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine + 9 + 1 + read-write + + + SLOWMEM_FORCE_LPD + RTC memory force PD + 10 + 1 + read-write + + + SLOWMEM_FORCE_LPU + RTC memory force no PD + 11 + 1 + read-write + + + FASTMEM_FORCE_PD + Fast RTC memory force power down + 12 + 1 + read-write + + + FASTMEM_FORCE_PU + Fast RTC memory force power up + 13 + 1 + read-write + + + FASTMEM_PD_EN + enable power down fast RTC memory in sleep + 14 + 1 + read-write + + + SLOWMEM_FORCE_PD + RTC memory force power down + 15 + 1 + read-write + + + SLOWMEM_FORCE_PU + RTC memory force power up + 16 + 1 + read-write + + + SLOWMEM_PD_EN + enable power down RTC memory in sleep + 17 + 1 + read-write + + + FORCE_PD + rtc_peri force power down + 18 + 1 + read-write + + + FORCE_PU + rtc_peri force power up + 19 + 1 + read-write + + + PD_EN + enable power down rtc_peri in sleep + 20 + 1 + read-write + + + + + DIG_PWC + 0x84 + 0x20 + 0x00155550 + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force no PD in sleep + 4 + 1 + read-write + + + ROM0_FORCE_PD + ROM force power down + 5 + 1 + read-write + + + ROM0_FORCE_PU + ROM force power up + 6 + 1 + read-write + + + INTER_RAM0_FORCE_PD + internal SRAM 0 force power down + 7 + 1 + read-write + + + INTER_RAM0_FORCE_PU + internal SRAM 0 force power up + 8 + 1 + read-write + + + INTER_RAM1_FORCE_PD + internal SRAM 1 force power down + 9 + 1 + read-write + + + INTER_RAM1_FORCE_PU + internal SRAM 1 force power up + 10 + 1 + read-write + + + INTER_RAM2_FORCE_PD + internal SRAM 2 force power down + 11 + 1 + read-write + + + INTER_RAM2_FORCE_PU + internal SRAM 2 force power up + 12 + 1 + read-write + + + INTER_RAM3_FORCE_PD + internal SRAM 3 force power down + 13 + 1 + read-write + + + INTER_RAM3_FORCE_PU + internal SRAM 3 force power up + 14 + 1 + read-write + + + INTER_RAM4_FORCE_PD + internal SRAM 4 force power down + 15 + 1 + read-write + + + INTER_RAM4_FORCE_PU + internal SRAM 4 force power up + 16 + 1 + read-write + + + WIFI_FORCE_PD + wifi force power down + 17 + 1 + read-write + + + WIFI_FORCE_PU + wifi force power up + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + ROM0_PD_EN + enable power down ROM in sleep + 24 + 1 + read-write + + + INTER_RAM0_PD_EN + enable power down internal SRAM 0 in sleep + 25 + 1 + read-write + + + INTER_RAM1_PD_EN + enable power down internal SRAM 1 in sleep + 26 + 1 + read-write + + + INTER_RAM2_PD_EN + enable power down internal SRAM 2 in sleep + 27 + 1 + read-write + + + INTER_RAM3_PD_EN + enable power down internal SRAM 3 in sleep + 28 + 1 + read-write + + + INTER_RAM4_PD_EN + enable power down internal SRAM 4 in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + enable power down wifi in sleep + 30 + 1 + read-write + + + DG_WRAP_PD_EN + enable power down digital core in sleep + 31 + 1 + read-write + + + + + DIG_ISO + 0x88 + 0x20 + 0xAAAA5000 + + + FORCE_OFF + 7 + 1 + read-write + + + FORCE_ON + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + ROM0_FORCE_ISO + ROM force ISO + 16 + 1 + read-write + + + ROM0_FORCE_NOISO + ROM force no ISO + 17 + 1 + read-write + + + INTER_RAM0_FORCE_ISO + internal SRAM 0 force ISO + 18 + 1 + read-write + + + INTER_RAM0_FORCE_NOISO + internal SRAM 0 force no ISO + 19 + 1 + read-write + + + INTER_RAM1_FORCE_ISO + internal SRAM 1 force ISO + 20 + 1 + read-write + + + INTER_RAM1_FORCE_NOISO + internal SRAM 1 force no ISO + 21 + 1 + read-write + + + INTER_RAM2_FORCE_ISO + internal SRAM 2 force ISO + 22 + 1 + read-write + + + INTER_RAM2_FORCE_NOISO + internal SRAM 2 force no ISO + 23 + 1 + read-write + + + INTER_RAM3_FORCE_ISO + internal SRAM 3 force ISO + 24 + 1 + read-write + + + INTER_RAM3_FORCE_NOISO + internal SRAM 3 force no ISO + 25 + 1 + read-write + + + INTER_RAM4_FORCE_ISO + internal SRAM 4 force ISO + 26 + 1 + read-write + + + INTER_RAM4_FORCE_NOISO + internal SRAM 4 force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + wifi force ISO + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + wifi force no ISO + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + digital core force no ISO + 31 + 1 + read-write + + + + + WDTCONFIG0 + 0x8C + 0x20 + 0x00004C80 + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 7 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 8 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 9 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 10 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 11 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 14 + 3 + read-write + + + WDT_LEVEL_INT_EN + N/A + 17 + 1 + read-write + + + WDT_EDGE_INT_EN + N/A + 18 + 1 + read-write + + + WDT_STG3 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 28 + 3 + read-write + + + WDT_EN + enable RTC WDT + 31 + 1 + read-write + + + + + WDTCONFIG1 + 0x90 + 0x20 + 0x0001F400 + + + WDT_STG0_HOLD + 0 + 32 + read-write + + + + + WDTCONFIG2 + 0x94 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + 0 + 32 + read-write + + + + + WDTCONFIG3 + 0x98 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + 0 + 32 + read-write + + + + + WDTCONFIG4 + 0x9C + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + 0 + 32 + read-write + + + + + WDTFEED + 0xA0 + 0x20 + + + WDT_FEED + 31 + 1 + write-only + + + + + WDTWPROTECT + 0xA4 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + 0 + 32 + read-write + + + + + TEST_MUX + 0xA8 + 0x20 + + + ENT_RTC + ENT_RTC + 29 + 1 + read-write + + + DTEST_RTC + DTEST_RTC + 30 + 2 + read-write + + + + + SW_CPU_STALL + 0xAC + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 26 + 6 + read-write + + + + + STORE4 + 0xB0 + 0x20 + + + SCRATCH4 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE5 + 0xB4 + 0x20 + + + SCRATCH5 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE6 + 0xB8 + 0x20 + + + SCRATCH6 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + STORE7 + 0xBC + 0x20 + + + SCRATCH7 + 32-bit general purpose retention register + 0 + 32 + read-write + + + + + LOW_POWER_ST + 0xC0 + 0x20 + + + LOW_POWER_DIAG0 + 0 + 32 + read-only + + + RDY_FOR_WAKEUP + 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise + 19 + 1 + read-only + + + + + DIAG1 + 0xC4 + 0x20 + + + LOW_POWER_DIAG1 + 0 + 32 + read-only + + + + + HOLD_FORCE + 0xC8 + 0x20 + + + ADC1_HOLD_FORCE + 0 + 1 + read-write + + + ADC2_HOLD_FORCE + 1 + 1 + read-write + + + PDAC1_HOLD_FORCE + 2 + 1 + read-write + + + PDAC2_HOLD_FORCE + 3 + 1 + read-write + + + SENSE1_HOLD_FORCE + 4 + 1 + read-write + + + SENSE2_HOLD_FORCE + 5 + 1 + read-write + + + SENSE3_HOLD_FORCE + 6 + 1 + read-write + + + SENSE4_HOLD_FORCE + 7 + 1 + read-write + + + TOUCH_PAD0_HOLD_FORCE + 8 + 1 + read-write + + + TOUCH_PAD1_HOLD_FORCE + 9 + 1 + read-write + + + TOUCH_PAD2_HOLD_FORCE + 10 + 1 + read-write + + + TOUCH_PAD3_HOLD_FORCE + 11 + 1 + read-write + + + TOUCH_PAD4_HOLD_FORCE + 12 + 1 + read-write + + + TOUCH_PAD5_HOLD_FORCE + 13 + 1 + read-write + + + TOUCH_PAD6_HOLD_FORCE + 14 + 1 + read-write + + + TOUCH_PAD7_HOLD_FORCE + 15 + 1 + read-write + + + X32P_HOLD_FORCE + 16 + 1 + read-write + + + X32N_HOLD_FORCE + 17 + 1 + read-write + + + + + EXT_WAKEUP1 + 0xCC + 0x20 + + + SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 18 + read-write + + + STATUS_CLR + clear ext wakeup1 status + 18 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + 0xD0 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 18 + read-only + + + + + BROWN_OUT + 0xD4 + 0x20 + 0x13FF0000 + + + RTC_MEM_PID_CONF + 0 + 8 + read-write + + + RTC_MEM_CRC_START + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + 9 + 11 + read-write + + + CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + RTC_MEM_CRC_LEN + 20 + 11 + read-write + + + RST_ENA + enable brown out reset + 26 + 1 + read-write + + + DBROWN_OUT_THRES + brown out threshold + 27 + 3 + read-write + + + ENA + enable brown out + 30 + 1 + read-write + + + DET + brown out detect + 31 + 1 + read-only + + + RTC_MEM_CRC_FINISH + 31 + 1 + read-write + + + + + DATE + 0x13C + 0x20 + 0x01604280 + + + CNTL_DATE + 0 + 28 + read-write + + + + + + + RTCIO + Peripheral RTCIO + RTC_GPIO + 0x3FF48400 + + 0x0 + 0xCC + registers + + + + OUT + 0x0 + 0x20 + + + DATA + GPIO0~17 output value + 14 + 18 + read-write + + + + + OUT_W1TS + 0x4 + 0x20 + + + OUT_DATA_W1TS + GPIO0~17 output value write 1 to set + 14 + 18 + write-only + + + + + OUT_W1TC + 0x8 + 0x20 + + + OUT_DATA_W1TC + GPIO0~17 output value write 1 to clear + 14 + 18 + write-only + + + + + ENABLE + 0xC + 0x20 + + + ENABLE + GPIO0~17 output enable + 14 + 18 + read-write + + + + + ENABLE_W1TS + 0x10 + 0x20 + + + ENABLE_W1TS + GPIO0~17 output enable write 1 to set + 14 + 18 + write-only + + + + + ENABLE_W1TC + 0x14 + 0x20 + + + ENABLE_W1TC + GPIO0~17 output enable write 1 to clear + 14 + 18 + write-only + + + + + STATUS + 0x18 + 0x20 + + + INT + GPIO0~17 interrupt status + 14 + 18 + read-write + + + + + STATUS_W1TS + 0x1C + 0x20 + + + STATUS_INT_W1TS + GPIO0~17 interrupt status write 1 to set + 14 + 18 + write-only + + + + + STATUS_W1TC + 0x20 + 0x20 + + + STATUS_INT_W1TC + GPIO0~17 interrupt status write 1 to clear + 14 + 18 + write-only + + + + + IN + 0x24 + 0x20 + + + NEXT + GPIO0~17 input value + 14 + 18 + read-only + + + + + 18 + 0x4 + 0-17 + PIN%s + 0x28 + 0x20 + + + PAD_DRIVER + if set to 0: normal output if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + GPIO wake up enable only available in light sleep + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + 0x70 + 0x20 + + + DEBUG_SEL0 + 0 + 5 + read-write + + + DEBUG_SEL1 + 5 + 5 + read-write + + + DEBUG_SEL2 + 10 + 5 + read-write + + + DEBUG_SEL3 + 15 + 5 + read-write + + + DEBUG_SEL4 + 20 + 5 + read-write + + + DEBUG_12M_NO_GATING + 25 + 1 + read-write + + + + + DIG_PAD_HOLD + 0x74 + 0x20 + + + DIG_PAD_HOLD + select the digital pad hold value. + 0 + 32 + read-write + + + + + HALL_SENS + 0x78 + 0x20 + + + HALL_PHASE + Reverse phase of hall sensor + 30 + 1 + read-write + + + XPD_HALL + Power on hall sensor and connect to VP and VN + 31 + 1 + read-write + + + + + SENSOR_PADS + 0x7C + 0x20 + + + SENSE4_FUN_IE + the input enable of the pad + 4 + 1 + read-write + + + SENSE4_SLP_IE + the input enable of the pad in sleep status + 5 + 1 + read-write + + + SENSE4_SLP_SEL + the sleep status selection signal of the pad + 6 + 1 + read-write + + + SENSE4_FUN_SEL + the functional selection signal of the pad + 7 + 2 + read-write + + + SENSE3_FUN_IE + the input enable of the pad + 9 + 1 + read-write + + + SENSE3_SLP_IE + the input enable of the pad in sleep status + 10 + 1 + read-write + + + SENSE3_SLP_SEL + the sleep status selection signal of the pad + 11 + 1 + read-write + + + SENSE3_FUN_SEL + the functional selection signal of the pad + 12 + 2 + read-write + + + SENSE2_FUN_IE + the input enable of the pad + 14 + 1 + read-write + + + SENSE2_SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SENSE2_SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + SENSE2_FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + SENSE1_FUN_IE + the input enable of the pad + 19 + 1 + read-write + + + SENSE1_SLP_IE + the input enable of the pad in sleep status + 20 + 1 + read-write + + + SENSE1_SLP_SEL + the sleep status selection signal of the pad + 21 + 1 + read-write + + + SENSE1_FUN_SEL + the functional selection signal of the pad + 22 + 2 + read-write + + + SENSE4_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 24 + 1 + read-write + + + SENSE3_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 25 + 1 + read-write + + + SENSE2_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 26 + 1 + read-write + + + SENSE1_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 27 + 1 + read-write + + + SENSE4_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 28 + 1 + read-write + + + SENSE3_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 29 + 1 + read-write + + + SENSE2_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 30 + 1 + read-write + + + SENSE1_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + ADC_PAD + 0x80 + 0x20 + + + ADC2_FUN_IE + the input enable of the pad + 18 + 1 + read-write + + + ADC2_SLP_IE + the input enable of the pad in sleep status + 19 + 1 + read-write + + + ADC2_SLP_SEL + the sleep status selection signal of the pad + 20 + 1 + read-write + + + ADC2_FUN_SEL + the functional selection signal of the pad + 21 + 2 + read-write + + + ADC1_FUN_IE + the input enable of the pad + 23 + 1 + read-write + + + ADC1_SLP_IE + the input enable of the pad in sleep status + 24 + 1 + read-write + + + ADC1_SLP_SEL + the sleep status selection signal of the pad + 25 + 1 + read-write + + + ADC1_FUN_SEL + the functional selection signal of the pad + 26 + 2 + read-write + + + ADC2_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 28 + 1 + read-write + + + ADC1_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 29 + 1 + read-write + + + ADC2_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 30 + 1 + read-write + + + ADC1_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + PAD_DAC1 + 0x84 + 0x20 + 0x80000000 + + + PDAC1_DAC_XPD_FORCE + Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + 10 + 1 + read-write + + + PDAC1_FUN_IE + the input enable of the pad + 11 + 1 + read-write + + + PDAC1_SLP_OE + the output enable of the pad in sleep status + 12 + 1 + read-write + + + PDAC1_SLP_IE + the input enable of the pad in sleep status + 13 + 1 + read-write + + + PDAC1_SLP_SEL + the sleep status selection signal of the pad + 14 + 1 + read-write + + + PDAC1_FUN_SEL + the functional selection signal of the pad + 15 + 2 + read-write + + + PDAC1_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 17 + 1 + read-write + + + PDAC1_XPD_DAC + Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + 18 + 1 + read-write + + + PDAC1_DAC + PAD DAC1 control code. + 19 + 8 + read-write + + + PDAC1_RUE + the pull up enable of the pad + 27 + 1 + read-write + + + PDAC1_RDE + the pull down enable of the pad + 28 + 1 + read-write + + + PDAC1_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 29 + 1 + read-write + + + PDAC1_DRV + the driver strength of the pad + 30 + 2 + read-write + + + + + PAD_DAC2 + 0x88 + 0x20 + 0x80000000 + + + PDAC2_DAC_XPD_FORCE + Power on DAC2. Usually we need to tristate PDAC2 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + 10 + 1 + read-write + + + PDAC2_FUN_IE + the input enable of the pad + 11 + 1 + read-write + + + PDAC2_SLP_OE + the output enable of the pad in sleep status + 12 + 1 + read-write + + + PDAC2_SLP_IE + the input enable of the pad in sleep status + 13 + 1 + read-write + + + PDAC2_SLP_SEL + the sleep status selection signal of the pad + 14 + 1 + read-write + + + PDAC2_FUN_SEL + the functional selection signal of the pad + 15 + 2 + read-write + + + PDAC2_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 17 + 1 + read-write + + + PDAC2_XPD_DAC + Power on DAC2. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + 18 + 1 + read-write + + + PDAC2_DAC + PAD DAC2 control code. + 19 + 8 + read-write + + + PDAC2_RUE + the pull up enable of the pad + 27 + 1 + read-write + + + PDAC2_RDE + the pull down enable of the pad + 28 + 1 + read-write + + + PDAC2_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 29 + 1 + read-write + + + PDAC2_DRV + the driver strength of the pad + 30 + 2 + read-write + + + + + XTAL_32K_PAD + 0x8C + 0x20 + 0x84100010 + + + DBIAS_XTAL_32K + 32K XTAL self-bias reference control. + 1 + 2 + read-write + + + DRES_XTAL_32K + 32K XTAL resistor bias control. + 3 + 2 + read-write + + + X32P_FUN_IE + the input enable of the pad + 5 + 1 + read-write + + + X32P_SLP_OE + the output enable of the pad in sleep status + 6 + 1 + read-write + + + X32P_SLP_IE + the input enable of the pad in sleep status + 7 + 1 + read-write + + + X32P_SLP_SEL + the sleep status selection signal of the pad + 8 + 1 + read-write + + + X32P_FUN_SEL + the functional selection signal of the pad + 9 + 2 + read-write + + + X32N_FUN_IE + the input enable of the pad + 11 + 1 + read-write + + + X32N_SLP_OE + the output enable of the pad in sleep status + 12 + 1 + read-write + + + X32N_SLP_IE + the input enable of the pad in sleep status + 13 + 1 + read-write + + + X32N_SLP_SEL + the sleep status selection signal of the pad + 14 + 1 + read-write + + + X32N_FUN_SEL + the functional selection signal of the pad + 15 + 2 + read-write + + + X32P_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 17 + 1 + read-write + + + X32N_MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 18 + 1 + read-write + + + XPD_XTAL_32K + Power up 32kHz crystal oscillator + 19 + 1 + read-write + + + DAC_XTAL_32K + 32K XTAL bias current DAC. + 20 + 2 + read-write + + + X32P_RUE + the pull up enable of the pad + 22 + 1 + read-write + + + X32P_RDE + the pull down enable of the pad + 23 + 1 + read-write + + + X32P_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 24 + 1 + read-write + + + X32P_DRV + the driver strength of the pad + 25 + 2 + read-write + + + X32N_RUE + the pull up enable of the pad + 27 + 1 + read-write + + + X32N_RDE + the pull down enable of the pad + 28 + 1 + read-write + + + X32N_HOLD + hold the current value of the output when setting the hold to Ò1Ó + 29 + 1 + read-write + + + X32N_DRV + the driver strength of the pad + 30 + 2 + read-write + + + + + TOUCH_CFG + 0x90 + 0x20 + 0x66000000 + + + TOUCH_DCUR + touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available + 23 + 2 + read-write + + + TOUCH_DRANGE + touch sensor saw wave voltage range. + 25 + 2 + read-write + + + TOUCH_DREFL + touch sensor saw wave bottom voltage. + 27 + 2 + read-write + + + TOUCH_DREFH + touch sensor saw wave top voltage. + 29 + 2 + read-write + + + TOUCH_XPD_BIAS + touch sensor bias power on. + 31 + 1 + read-write + + + + + TOUCH_PAD0 + 0x94 + 0x20 + 0x52000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4 + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD1 + 0x98 + 0x20 + 0x4A000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0 + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + 31 + 1 + read-write + + + + + TOUCH_PAD2 + 0x9C + 0x20 + 0x52000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2 + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD3 + 0xA0 + 0x20 + 0x4A000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD4 + 0xA4 + 0x20 + 0x52000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD5 + 0xA8 + 0x20 + 0x52000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD6 + 0xAC + 0x20 + 0x4A000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD7 + 0xB0 + 0x20 + 0x42000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27 + 12 + 1 + read-write + + + FUN_IE + the input enable of the pad + 13 + 1 + read-write + + + SLP_OE + the output enable of the pad in sleep status + 14 + 1 + read-write + + + SLP_IE + the input enable of the pad in sleep status + 15 + 1 + read-write + + + SLP_SEL + the sleep status selection signal of the pad + 16 + 1 + read-write + + + FUN_SEL + the functional selection signal of the pad + 17 + 2 + read-write + + + MUX_SEL + Ò1Ó select the digital function Ó0Óslection the rtc function + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + RUE + the pull up enable of the pad + 27 + 1 + read-write + + + RDE + the pull down enable of the pad + 28 + 1 + read-write + + + DRV + the driver strength of the pad + 29 + 2 + read-write + + + HOLD + hold the current value of the output when setting the hold to Ò1Ó + 31 + 1 + read-write + + + + + TOUCH_PAD8 + 0xB4 + 0x20 + 0x02000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + + + TOUCH_PAD9 + 0xB8 + 0x20 + 0x02000000 + + + TO_GPIO + connect the rtc pad input to digital pad input Ó0Ó is availbale + 19 + 1 + read-write + + + XPD + touch sensor power on. + 20 + 1 + read-write + + + TIE_OPT + default touch sensor tie option. 0: tie low 1: tie high. + 21 + 1 + read-write + + + START + start touch sensor. + 22 + 1 + read-write + + + DAC + touch sensor slope control. 3-bit for each touch panel default 100. + 23 + 3 + read-write + + + + + EXT_WAKEUP0 + 0xBC + 0x20 + + + SEL + select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 + 27 + 5 + read-write + + + + + XTL_EXT_CTR + 0xC0 + 0x20 + + + SEL + select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 + 27 + 5 + read-write + + + + + SAR_I2C_IO + 0xC4 + 0x20 + + + SAR_DEBUG_BIT_SEL + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda + 30 + 2 + read-write + + + + + DATE + 0xC8 + 0x20 + 0x01603160 + + + IO_DATE + date + 0 + 28 + read-write + + + + + + + RTC_I2C + Peripheral RTC_I2C + RTC_I2C + 0x3FF48C00 + + 0x0 + 0x3C + registers + + + + SCL_LOW_PERIOD + 0x0 + 0x20 + + + SCL_LOW_PERIOD + number of cycles that scl == 0 + 0 + 25 + read-write + + + + + CTRL + 0x4 + 0x20 + + + SDA_FORCE_OUT + SDA is push-pull (1) or open-drain (0) + 0 + 1 + read-write + + + SCL_FORCE_OUT + SCL is push-pull (1) or open-drain (0) + 1 + 1 + read-write + + + MS_MODE + Master (1) or slave (0) + 4 + 1 + read-write + + + TRANS_START + Force to generate start condition + 5 + 1 + read-write + + + TX_LSB_FIRST + Send LSB first + 6 + 1 + read-write + + + RX_LSB_FIRST + Receive LSB first + 7 + 1 + read-write + + + + + DEBUG_STATUS + 0x8 + 0x20 + + + ACK_VAL + The value of an acknowledge signal on the bus + 0 + 1 + read-write + + + SLAVE_RW + When working as a slave, the value of R/W bit received + 1 + 1 + read-write + + + TIMED_OUT + Transfer has timed out + 2 + 1 + read-write + + + ARB_LOST + When working as a master, lost control of I2C bus + 3 + 1 + read-write + + + BUS_BUSY + operation is in progress + 4 + 1 + read-write + + + SLAVE_ADDR_MATCH + When working as a slave, whether address was matched + 5 + 1 + read-write + + + BYTE_TRANS + 8 bit transmit done + 6 + 1 + read-write + + + MAIN_STATE + state of the main state machine + 25 + 3 + read-write + + + SCL_STATE + state of SCL state machine + 28 + 3 + read-write + + + + + TIMEOUT + 0xC + 0x20 + + + TIMEOUT + Maximum number of FAST_CLK cycles that the transmission can take + 0 + 20 + read-write + + + + + SLAVE_ADDR + 0x10 + 0x20 + + + SLAVE_ADDR + local slave address + 0 + 15 + read-write + + + _10BIT + Set if local slave address is 10-bit + 31 + 1 + read-write + + + + + DATA + 0x1C + 0x20 + + + INT_RAW + 0x20 + 0x20 + + + SLAVE_TRANS_COMPLETE_INT_RAW + Slave accepted 1 byte and address matched + 3 + 1 + read-write + + + ARBITRATION_LOST_INT_RAW + Master lost arbitration + 4 + 1 + read-write + + + MASTER_TRANS_COMPLETE_INT_RAW + 5 + 1 + read-write + + + TRANS_COMPLETE_INT_RAW + Stop condition has been detected interrupt raw status + 6 + 1 + read-write + + + TIME_OUT_INT_RAW + time out interrupt raw status + 7 + 1 + read-only + + + + + INT_CLR + 0x24 + 0x20 + + + SLAVE_TRANS_COMPLETE_INT_CLR + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_CLR + 5 + 1 + read-write + + + MASTER_TRANS_COMPLETE_INT_CLR + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_CLR + 7 + 1 + read-write + + + TIME_OUT_INT_CLR + 8 + 1 + write-only + + + + + INT_EN + 0x28 + 0x20 + + + INT_ST + 0x2C + 0x20 + + + SDA_DUTY + 0x30 + 0x20 + + + SDA_DUTY + Number of FAST_CLK cycles SDA will switch after falling edge of SCL + 0 + 20 + read-write + + + + + SCL_HIGH_PERIOD + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Number of FAST_CLK cycles for SCL to be high + 0 + 20 + read-write + + + + + SCL_START_PERIOD + 0x40 + 0x20 + + + SCL_START_PERIOD + Number of FAST_CLK cycles to wait before generating start condition + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + 0x44 + 0x20 + + + SCL_STOP_PERIOD + Number of FAST_CLK cycles to wait before generating stop condition + 0 + 20 + read-write + + + + + CMD + 0x48 + 0x20 + + + VAL + Command content + 0 + 14 + read-write + + + DONE + Bit is set by HW when command is done + 31 + 1 + read-write + + + + + + + SDMMC + SD/MMC Host Controller + SDHOST + 0x3FF68000 + + 0x0 + 0xA4 + registers + + + + CTRL + Control register + 0x0 + 0x20 + + + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 + 1 + read-write + + + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 + 1 + read-write + + + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 + read-write + + + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 + 1 + read-write + + + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 + 1 + read-write + + + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 + 1 + read-write + + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + + + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 + read-write + + + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 + read-write + + + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 + read-write + + + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 + read-write + + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + + + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 + read-write + + + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 + 2 + read-write + + + + + TMOUT + Data and response timeout configuration register + 0x14 + 0x20 + 0xFFFFFF40 + + + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 + read-write + + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + + + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 + read-write + + + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. + 16 + 2 + read-write + + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + + + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 + read-write + + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + + + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 + 2 + read-write + + + + + CMDARG + Command argument data register + 0x28 + 0x20 + + + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 + read-write + + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + + + INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 + 1 + read-write + + + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 + read-write + + + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 + 1 + read-write + + + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 + 1 + read-write + + + TRANSFER_MODE + Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 + 1 + read-write + + + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. + 13 + 1 + read-write + + + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. + 14 + 1 + read-write + + + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. + 15 + 1 + read-write + + + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. + 16 + 5 + read-write + + + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 + 1 + read-write + + + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 + 1 + read-write + + + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 + 1 + read-write + + + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 + read-write + + + + + RESP0 + Response data register + 0x30 + 0x20 + + + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only + + + + + RESP1 + Long response data register + 0x34 + 0x20 + + + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only + + + + + RESP2 + Long response data register + 0x38 + 0x20 + + + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + + RESP3 + Long response data register + 0x3C + 0x20 + + + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 + 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 + 2 + read-write + + + + + STATUS + SD/MMC status register + 0x48 + 0x20 + 0x00000716 + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. + 0 + 1 + read-only + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. + 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 + 1 + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only + + + + + FIFOTH + FIFO configuration register + 0x4C + 0x20 + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 + read-write + + + + + CDETECT + Card detect register + 0x50 + 0x20 + + + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + WRTPRT + Card write protection (WP) status register + 0x54 + 0x20 + + + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + TCBCNT + Transferred byte count register + 0x5C + 0x20 + + + TCBCNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-only + + + + + TBBCNT + Transferred byte count register + 0x60 + 0x20 + + + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-only + + + + + DEBNCE + Debounce filter time configuration register + 0x64 + 0x20 + + + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. + 0 + 24 + read-write + + + + + USRID + User ID (scratchpad) register + 0x68 + 0x20 + + + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. + 0 + 32 + read-write + + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + + + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only + + + + + HCON + Hardware feature register + 0x70 + 0x20 + 0x03444CC3 + + + CARD_TYPE + Hardware support SDIO and MMC. + 0 + 1 + read-only + + + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. + 7 + 3 + read-only + + + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 + 2 + read-only + + + + + UHS + UHS-1 register + 0x74 + 0x20 + + + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. + 16 + 2 + read-write + + + + + RST_N + Card reset register + 0x78 + 0x20 + 0x00000001 + + + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + 0 + 2 + read-write + + + + + BMOD + Burst mode transfer configuration register + 0x80 + 0x20 + + + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. + 0 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 + read-write + + + + + PLDMND + Poll demand configuration register + 0x84 + 0x20 + + + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . + 0 + 32 + write-only + + + + + DBADDR + Descriptor base address register + 0x88 + 0x20 + + + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. + 0 + 32 + read-write + + + + + IDSTS + IDMAC status register + 0x8C + 0x20 + + + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + 0 + 1 + read-write + + + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 + 1 + read-write + + + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 + 1 + read-write + + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + + + + + IDINTEN + IDMAC interrupt enable register + 0x90 + 0x20 + + + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 + read-write + + + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. + 8 + 1 + read-write + + + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 + read-write + + + + + DSCADDR + Host descriptor address pointer + 0x94 + 0x20 + + + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. + 0 + 32 + read-only + + + + + BUFADDR + Host buffer address pointer register + 0x98 + 0x20 + + + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. + 0 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 + read-write + + + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. + 2 + 1 + read-write + + + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 + read-write + + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + + + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 + 2 + read-write + + + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 + read-write + + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + + + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 + read-write + + + + + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 + 0x20 + + + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + 0 + 32 + read-write + + + + + CLK_EDGE_SEL + SDIO control register. + 0x800 + 0x20 + 0x00820200 + + + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. + 0 + 3 + read-write + + + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 + read-write + + + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 + read-write + + + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 + read-write + + + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 + read-write + + + CCLLKIN_EDGE_N + The value should be equal to CCLKIN_EDGE_L. + 17 + 4 + read-write + + + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable + 23 + 1 + read-write + + + + + + + SENS + Peripheral SENS + SENS + 0x3FF48800 + + 0x0 + 0xA8 + registers + + + + SAR_READ_CTRL + 0x0 + 0x20 + 0x00070902 + + + SAR1_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR1_SAMPLE_CYCLE + sample cycles for SAR ADC1 + 8 + 8 + read-write + + + SAR1_SAMPLE_BIT + 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width + 16 + 2 + read-write + + + SAR1_CLK_GATED + 18 + 1 + read-write + + + SAR1_SAMPLE_NUM + 19 + 8 + read-write + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL + 27 + 1 + read-write + + + SAR1_DATA_INV + Invert SAR ADC1 data + 28 + 1 + read-write + + + + + SAR_READ_STATUS1 + 0x4 + 0x20 + + + SAR1_READER_STATUS + 0 + 32 + read-only + + + + + SAR_MEAS_WAIT1 + 0x8 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + 16 + 16 + read-write + + + + + SAR_MEAS_WAIT2 + 0xC + 0x20 + 0x0020000A + + + FORCE_XPD_SAR_SW + 0 + 1 + read-write + + + SAR_AMP_WAIT3 + 0 + 16 + read-write + + + FORCE_XPD_AMP + 16 + 2 + read-write + + + FORCE_XPD_SAR + 18 + 2 + read-write + + + SAR2_RSTB_WAIT + 20 + 8 + read-write + + + + + SAR_MEAS_CTRL + 0x10 + 0x20 + 0x0707338F + + + XPD_SAR_AMP_FSM + 0 + 4 + read-write + + + AMP_RST_FB_FSM + 4 + 4 + read-write + + + AMP_SHORT_REF_FSM + 8 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + 12 + 4 + read-write + + + XPD_SAR_FSM + 16 + 4 + read-write + + + SAR_RSTB_FSM + 20 + 4 + read-write + + + SAR2_XPD_WAIT + 24 + 8 + read-write + + + + + SAR_READ_STATUS2 + 0x14 + 0x20 + + + SAR2_READER_STATUS + 0 + 32 + read-only + + + + + ULP_CP_SLEEP_CYC0 + 0x18 + 0x20 + 0x000000C8 + + + SLEEP_CYCLES_S0 + sleep cycles for ULP-coprocessor timer + 0 + 32 + read-write + + + + + ULP_CP_SLEEP_CYC1 + 0x1C + 0x20 + 0x00000064 + + + SLEEP_CYCLES_S1 + 0 + 32 + read-write + + + + + ULP_CP_SLEEP_CYC2 + 0x20 + 0x20 + 0x00000032 + + + SLEEP_CYCLES_S2 + 0 + 32 + read-write + + + + + ULP_CP_SLEEP_CYC3 + 0x24 + 0x20 + 0x00000028 + + + SLEEP_CYCLES_S3 + 0 + 32 + read-write + + + + + ULP_CP_SLEEP_CYC4 + 0x28 + 0x20 + 0x00000014 + + + SLEEP_CYCLES_S4 + 0 + 32 + read-write + + + + + SAR_START_FORCE + 0x2C + 0x20 + 0x0000000F + + + SAR1_BIT_WIDTH + 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits + 0 + 2 + read-write + + + SAR2_BIT_WIDTH + 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits + 2 + 2 + read-write + + + SAR2_EN_TEST + SAR2_EN_TEST only active when reg_sar2_dig_force = 0 + 4 + 1 + read-write + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT PA power detector capacitance tuning. + 5 + 3 + read-write + + + ULP_CP_FORCE_START_TOP + 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer + 8 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1 + 9 + 1 + read-write + + + SARCLK_EN + 10 + 1 + read-write + + + PC_INIT + initialized PC for ULP-coprocessor + 11 + 11 + read-write + + + SAR2_STOP + stop SAR ADC2 conversion + 22 + 1 + read-write + + + SAR1_STOP + stop SAR ADC1 conversion + 23 + 1 + read-write + + + SAR2_PWDET_EN + N/A + 24 + 1 + read-write + + + + + SAR_MEM_WR_CTRL + 0x30 + 0x20 + 0x00100200 + + + MEM_WR_ADDR_INIT + 0 + 11 + read-write + + + MEM_WR_ADDR_SIZE + 11 + 11 + read-write + + + RTC_MEM_WR_OFFST_CLR + 22 + 1 + write-only + + + + + SAR_ATTEN1 + 0x34 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB + 0 + 32 + read-write + + + + + SAR_ATTEN2 + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB + 0 + 32 + read-write + + + + + SAR_SLAVE_ADDR1 + 0x3C + 0x20 + + + I2C_SLAVE_ADDR1 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR0 + 11 + 11 + read-write + + + MEAS_STATUS + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + 0x40 + 0x20 + + + I2C_SLAVE_ADDR3 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + 0x44 + 0x20 + + + I2C_SLAVE_ADDR5 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR4 + 11 + 11 + read-write + + + TSENS_OUT + temperature sensor data out + 22 + 8 + read-only + + + TSENS_RDY_OUT + indicate temperature sensor out ready + 30 + 1 + read-only + + + + + SAR_SLAVE_ADDR4 + 0x48 + 0x20 + + + I2C_SLAVE_ADDR7 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR6 + 11 + 11 + read-write + + + I2C_RDATA + I2C read data + 22 + 8 + read-only + + + I2C_DONE + indicate I2C done + 30 + 1 + read-only + + + + + SAR_TSENS_CTRL + 0x4C + 0x20 + 0x00066002 + + + TSENS_XPD_WAIT + 0 + 12 + read-write + + + TSENS_XPD_FORCE + 12 + 1 + read-write + + + TSENS_CLK_INV + 13 + 1 + read-write + + + TSENS_CLK_GATED + 14 + 1 + read-write + + + TSENS_IN_INV + invert temperature sensor data + 15 + 1 + read-write + + + TSENS_CLK_DIV + temperature sensor clock divider + 16 + 8 + read-write + + + TSENS_POWER_UP + temperature sensor power up + 24 + 1 + read-write + + + TSENS_POWER_UP_FORCE + 1: dump out & power up controlled by SW 0: by FSM + 25 + 1 + read-write + + + TSENS_DUMP_OUT + temperature sensor dump out only active when reg_tsens_power_up_force = 1 + 26 + 1 + read-write + + + + + SAR_I2C_CTRL + 0x50 + 0x20 + + + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 + 0 + 28 + read-write + + + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 + 1 + read-write + + + + + SAR_MEAS_START1 + 0x54 + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data + 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1 + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1 + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_TOUCH_CTRL1 + 0x58 + 0x20 + 0x02041000 + + + TOUCH_MEAS_DELAY + the meas length (in 8MHz) + 0 + 16 + read-write + + + TOUCH_XPD_WAIT + the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + 16 + 8 + read-write + + + TOUCH_OUT_SEL + 1: when the counter is greater then the threshold the touch pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched" + 24 + 1 + read-write + + + TOUCH_OUT_1EN + 1: wakeup interrupt is generated if SET1 is "touched" 0: wakeup interrupt is generated only if SET1 & SET2 is both "touched" + 25 + 1 + read-write + + + XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 26 + 1 + read-write + + + HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 27 + 1 + read-write + + + + + SAR_TOUCH_THRES1 + 0x5C + 0x20 + + + TOUCH_OUT_TH1 + the threshold for touch pad 1 + 0 + 16 + read-write + + + TOUCH_OUT_TH0 + the threshold for touch pad 0 + 16 + 16 + read-write + + + + + SAR_TOUCH_THRES2 + 0x60 + 0x20 + + + TOUCH_OUT_TH3 + the threshold for touch pad 3 + 0 + 16 + read-write + + + TOUCH_OUT_TH2 + the threshold for touch pad 2 + 16 + 16 + read-write + + + + + SAR_TOUCH_THRES3 + 0x64 + 0x20 + + + TOUCH_OUT_TH5 + the threshold for touch pad 5 + 0 + 16 + read-write + + + TOUCH_OUT_TH4 + the threshold for touch pad 4 + 16 + 16 + read-write + + + + + SAR_TOUCH_THRES4 + 0x68 + 0x20 + + + TOUCH_OUT_TH7 + the threshold for touch pad 7 + 0 + 16 + read-write + + + TOUCH_OUT_TH6 + the threshold for touch pad 6 + 16 + 16 + read-write + + + + + SAR_TOUCH_THRES5 + 0x6C + 0x20 + + + TOUCH_OUT_TH9 + the threshold for touch pad 9 + 0 + 16 + read-write + + + TOUCH_OUT_TH8 + the threshold for touch pad 8 + 16 + 16 + read-write + + + + + SAR_TOUCH_OUT1 + 0x70 + 0x20 + + + TOUCH_MEAS_OUT1 + the counter for touch pad 1 + 0 + 16 + read-only + + + TOUCH_MEAS_OUT0 + the counter for touch pad 0 + 16 + 16 + read-only + + + + + SAR_TOUCH_OUT2 + 0x74 + 0x20 + + + TOUCH_MEAS_OUT3 + the counter for touch pad 3 + 0 + 16 + read-only + + + TOUCH_MEAS_OUT2 + the counter for touch pad 2 + 16 + 16 + read-only + + + + + SAR_TOUCH_OUT3 + 0x78 + 0x20 + + + TOUCH_MEAS_OUT5 + the counter for touch pad 5 + 0 + 16 + read-only + + + TOUCH_MEAS_OUT4 + the counter for touch pad 4 + 16 + 16 + read-only + + + + + SAR_TOUCH_OUT4 + 0x7C + 0x20 + + + TOUCH_MEAS_OUT7 + the counter for touch pad 7 + 0 + 16 + read-only + + + TOUCH_MEAS_OUT6 + the counter for touch pad 6 + 16 + 16 + read-only + + + + + SAR_TOUCH_OUT5 + 0x80 + 0x20 + + + TOUCH_MEAS_OUT9 + the counter for touch pad 9 + 0 + 16 + read-only + + + TOUCH_MEAS_OUT8 + the counter for touch pad 8 + 16 + 16 + read-only + + + + + SAR_TOUCH_CTRL2 + 0x84 + 0x20 + 0x00400800 + + + TOUCH_MEAS_EN + 10-bit register to indicate which pads are "touched" + 0 + 10 + read-only + + + TOUCH_MEAS_DONE + fsm set 1 to indicate touch touch meas is done + 10 + 1 + read-only + + + TOUCH_START_FSM_EN + 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers + 11 + 1 + read-write + + + TOUCH_START_EN + 1: start touch fsm valid when reg_touch_start_force is set + 12 + 1 + read-write + + + TOUCH_START_FORCE + 1: to start touch fsm by SW 0: to start touch fsm by timer + 13 + 1 + read-write + + + TOUCH_SLEEP_CYCLES + sleep cycles for timer + 14 + 16 + read-write + + + TOUCH_MEAS_EN_CLR + to clear reg_touch_meas_en + 30 + 1 + write-only + + + + + SAR_TOUCH_ENABLE + 0x8C + 0x20 + 0x3FFFFFFF + + + TOUCH_PAD_WORKEN + Bitmap defining the working set during the measurement. + 0 + 10 + read-write + + + TOUCH_PAD_OUTEN2 + Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched" only if at least one of touch pad in SET2 is "touched". + 10 + 10 + read-write + + + TOUCH_PAD_OUTEN1 + Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched" only if at least one of touch pad in SET1 is "touched". + 20 + 10 + read-write + + + + + SAR_READ_CTRL2 + 0x90 + 0x20 + 0x00070902 + + + SAR2_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR2_SAMPLE_CYCLE + sample cycles for SAR ADC2 + 8 + 8 + read-write + + + SAR2_SAMPLE_BIT + 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width + 16 + 2 + read-write + + + SAR2_CLK_GATED + 18 + 1 + read-write + + + SAR2_SAMPLE_NUM + 19 + 8 + read-write + + + SAR2_PWDET_FORCE + 27 + 1 + read-write + + + SAR2_DIG_FORCE + 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL + 28 + 1 + read-write + + + SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 + read-write + + + + + SAR_MEAS_START2 + 0x94 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data + 0 + 16 + read-only + + + MEAS2_DONE_SAR + SAR ADC2 conversion done indication + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1 + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1 + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_DAC_CTRL1 + 0x98 + 0x20 + + + SW_FSTEP + frequency step for CW generator can be used to adjust the frequency + 0 + 16 + read-write + + + SW_TONE_EN + 1: enable CW generator 0: disable CW generator + 16 + 1 + read-write + + + DEBUG_BIT_SEL + 17 + 5 + read-write + + + DAC_DIG_FORCE + 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA + 22 + 1 + read-write + + + DAC_CLK_FORCE_LOW + 1: force PDAC_CLK to low + 23 + 1 + read-write + + + DAC_CLK_FORCE_HIGH + 1: force PDAC_CLK to high + 24 + 1 + read-write + + + DAC_CLK_INV + 1: invert PDAC_CLK + 25 + 1 + read-write + + + + + SAR_DAC_CTRL2 + 0x9C + 0x20 + 0x03000000 + + + DAC_DC1 + DC offset for DAC1 CW generator + 0 + 8 + read-write + + + DAC_DC2 + DC offset for DAC2 CW generator + 8 + 8 + read-write + + + DAC_SCALE1 + 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 + 16 + 2 + read-write + + + DAC_SCALE2 + 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 + 18 + 2 + read-write + + + DAC_INV1 + 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB + 20 + 2 + read-write + + + DAC_INV2 + 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB + 22 + 2 + read-write + + + DAC_CW_EN1 + 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0] + 24 + 1 + read-write + + + DAC_CW_EN2 + 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0] + 25 + 1 + read-write + + + + + SAR_MEAS_CTRL2 + 0xA0 + 0x20 + 0x00000003 + + + SAR1_DAC_XPD_FSM + 0 + 4 + read-write + + + SAR1_DAC_XPD_FSM_IDLE + 4 + 1 + read-write + + + XPD_SAR_AMP_FSM_IDLE + 5 + 1 + read-write + + + AMP_RST_FB_FSM_IDLE + 6 + 1 + read-write + + + AMP_SHORT_REF_FSM_IDLE + 7 + 1 + read-write + + + AMP_SHORT_REF_GND_FSM_IDLE + 8 + 1 + read-write + + + XPD_SAR_FSM_IDLE + 9 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + 10 + 1 + read-write + + + SAR2_RSTB_FORCE + 11 + 2 + read-write + + + AMP_RST_FB_FORCE + 13 + 2 + read-write + + + AMP_SHORT_REF_FORCE + 15 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + 17 + 2 + read-write + + + + + SAR_NOUSE + 0xF8 + 0x20 + + + SAR_NOUSE + 0 + 32 + read-write + + + + + SARDATE + 0xFC + 0x20 + 0x01605180 + + + SAR_DATE + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x3FF03000 + + 0x0 + 0xC0 + registers + + + + 32 + 0x4 + TEXT_%s + 0x0 + 0x20 + + + TEXT + SHA Message block and hash result register. + 0 + 8 + read-write + + + + + SHA1_START + 0x80 + 0x20 + + + SHA1_START + Write 1 to start an SHA-1 operation on the first message block. + 0 + 1 + write-only + + + + + SHA1_CONTINUE + 0x80 + 0x20 + + + SHA1_CONTINUE + Write 1 to continue the SHA-1 operation with subsequent blocks. + 0 + 1 + write-only + + + + + SHA1_LOAD + 0x88 + 0x20 + + + SHA1_LOAD + Write 1 to finish the SHA-1 operation to calculate the final message hash. + 0 + 1 + write-only + + + + + SHA1_BUSY + 0x8C + 0x20 + + + SHA1_BUSY + SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. + 0 + 1 + write-only + + + + + SHA256_START + 0x90 + 0x20 + + + SHA256_START + Write 1 to start an SHA-256 operation on the first message block. + 0 + 1 + write-only + + + + + SHA256_LOAD + 0x90 + 0x20 + + + SHA256_LOAD + Write 1 to finish the SHA-256 operation to calculate the final message hash. + 0 + 1 + write-only + + + + + SHA256_CONTINUE + 0x94 + 0x20 + + + SHA256_CONTINUE + Write 1 to continue the SHA-256 operation with subsequent blocks. + 0 + 1 + write-only + + + + + SHA256_BUSY + 0x9C + 0x20 + + + SHA256_BUSY + SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. + 0 + 1 + read-only + + + + + SHA384_START + 0xA0 + 0x20 + + + SHA384_START + Write 1 to start an SHA-384 operation on the first message block. + 0 + 1 + write-only + + + + + SHA384_CONTINUE + 0xA4 + 0x20 + + + SHA384_CONTINUE + Write 1 to continue the SHA-384 operation with subsequent blocks. + 0 + 1 + write-only + + + + + SHA384_LOAD + 0xA8 + 0x20 + + + SHA384_LOAD + Write 1 to finish the SHA-384 operation to calculate the final message hash. + 0 + 1 + write-only + + + + + SHA384_BUSY + 0xAC + 0x20 + + + SHA384_BUSY + SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. + 0 + 1 + read-only + + + + + SHA512_START + 0xB0 + 0x20 + + + SHA512_START + Write 1 to start an SHA-512 operation on the first message block. + 0 + 1 + write-only + + + + + SHA512_CONTINUE + 0xB4 + 0x20 + + + SHA512_CONTINUE + Write 1 to continue the SHA-512 operation with subsequent blocks. + 0 + 1 + write-only + + + + + SHA512_LOAD + 0xB8 + 0x20 + + + SHA512_LOAD + Write 1 to finish the SHA-512 operation to calculate the final message hash. + 0 + 1 + write-only + + + + + SHA512_BUSY + 0xBC + 0x20 + + + SHA512_BUSY + SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. + 0 + 1 + read-only + + + + + + + SLC + Peripheral SLC + SLC + 0x3FF58000 + + 0x0 + 0x14C + registers + + + + CONF0 + 0x0 + 0x20 + 0xFF3CFF30 + + + SLC0_TX_RST + 0 + 1 + read-write + + + SLC0_RX_RST + 1 + 1 + read-write + + + AHBM_FIFO_RST + 2 + 1 + read-write + + + AHBM_RST + 3 + 1 + read-write + + + SLC0_TX_LOOP_TEST + 4 + 1 + read-write + + + SLC0_RX_LOOP_TEST + 5 + 1 + read-write + + + SLC0_RX_AUTO_WRBACK + 6 + 1 + read-write + + + SLC0_RX_NO_RESTART_CLR + 7 + 1 + read-write + + + SLC0_RXDSCR_BURST_EN + 8 + 1 + read-write + + + SLC0_RXDATA_BURST_EN + 9 + 1 + read-write + + + SLC0_RXLINK_AUTO_RET + 10 + 1 + read-write + + + SLC0_TXLINK_AUTO_RET + 11 + 1 + read-write + + + SLC0_TXDSCR_BURST_EN + 12 + 1 + read-write + + + SLC0_TXDATA_BURST_EN + 13 + 1 + read-write + + + SLC0_TOKEN_AUTO_CLR + 14 + 1 + read-write + + + SLC0_TOKEN_SEL + 15 + 1 + read-write + + + SLC1_TX_RST + 16 + 1 + read-write + + + SLC1_RX_RST + 17 + 1 + read-write + + + SLC0_WR_RETRY_MASK_EN + 18 + 1 + read-write + + + SLC1_WR_RETRY_MASK_EN + 19 + 1 + read-write + + + SLC1_TX_LOOP_TEST + 20 + 1 + read-write + + + SLC1_RX_LOOP_TEST + 21 + 1 + read-write + + + SLC1_RX_AUTO_WRBACK + 22 + 1 + read-write + + + SLC1_RX_NO_RESTART_CLR + 23 + 1 + read-write + + + SLC1_RXDSCR_BURST_EN + 24 + 1 + read-write + + + SLC1_RXDATA_BURST_EN + 25 + 1 + read-write + + + SLC1_RXLINK_AUTO_RET + 26 + 1 + read-write + + + SLC1_TXLINK_AUTO_RET + 27 + 1 + read-write + + + SLC1_TXDSCR_BURST_EN + 28 + 1 + read-write + + + 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write-only + + + SLC0_RX_DONE_INT_CLR + 16 + 1 + write-only + + + SLC0_RX_EOF_INT_CLR + 17 + 1 + write-only + + + SLC0_TOHOST_INT_CLR + 18 + 1 + write-only + + + SLC0_TX_DSCR_ERR_INT_CLR + 19 + 1 + write-only + + + SLC0_RX_DSCR_ERR_INT_CLR + 20 + 1 + write-only + + + SLC0_TX_DSCR_EMPTY_INT_CLR + 21 + 1 + write-only + + + SLC0_HOST_RD_ACK_INT_CLR + 22 + 1 + write-only + + + SLC0_WR_RETRY_DONE_INT_CLR + 23 + 1 + write-only + + + SLC0_TX_ERR_EOF_INT_CLR + 24 + 1 + write-only + + + CMD_DTC_INT_CLR + 25 + 1 + write-only + + + SLC0_RX_QUICK_EOF_INT_CLR + 26 + 1 + write-only + + + + + _1INT_RAW + 0x14 + 0x20 + + + FRHOST_BIT8_INT_RAW + 0 + 1 + read-only + + + FRHOST_BIT9_INT_RAW + 1 + 1 + read-only + + + FRHOST_BIT10_INT_RAW + 2 + 1 + read-only + + + FRHOST_BIT11_INT_RAW + 3 + 1 + read-only + + + FRHOST_BIT12_INT_RAW + 4 + 1 + read-only + + + FRHOST_BIT13_INT_RAW + 5 + 1 + read-only + + + FRHOST_BIT14_INT_RAW + 6 + 1 + read-only + + + FRHOST_BIT15_INT_RAW + 7 + 1 + read-only + + + SLC1_RX_START_INT_RAW + 8 + 1 + read-only + + + SLC1_TX_START_INT_RAW + 9 + 1 + read-only + + + SLC1_RX_UDF_INT_RAW + 10 + 1 + read-only + + + SLC1_TX_OVF_INT_RAW + 11 + 1 + read-only + + + SLC1_TOKEN0_1TO0_INT_RAW + 12 + 1 + read-only + + + SLC1_TOKEN1_1TO0_INT_RAW + 13 + 1 + read-only + + + SLC1_TX_DONE_INT_RAW + 14 + 1 + read-only + + + SLC1_TX_SUC_EOF_INT_RAW + 15 + 1 + read-only + + + SLC1_RX_DONE_INT_RAW + 16 + 1 + read-only + + + SLC1_RX_EOF_INT_RAW + 17 + 1 + read-only + + + SLC1_TOHOST_INT_RAW + 18 + 1 + read-only + + + SLC1_TX_DSCR_ERR_INT_RAW + 19 + 1 + read-only + + + SLC1_RX_DSCR_ERR_INT_RAW + 20 + 1 + read-only + + + SLC1_TX_DSCR_EMPTY_INT_RAW + 21 + 1 + read-only + + + SLC1_HOST_RD_ACK_INT_RAW + 22 + 1 + read-only + + + SLC1_WR_RETRY_DONE_INT_RAW + 23 + 1 + read-only + + + SLC1_TX_ERR_EOF_INT_RAW + 24 + 1 + read-only + + + + + _1INT_ST + 0x18 + 0x20 + + + FRHOST_BIT8_INT_ST + 0 + 1 + read-only + + + FRHOST_BIT9_INT_ST + 1 + 1 + read-only + + + FRHOST_BIT10_INT_ST + 2 + 1 + read-only + + + FRHOST_BIT11_INT_ST + 3 + 1 + read-only + + + FRHOST_BIT12_INT_ST + 4 + 1 + read-only + + + FRHOST_BIT13_INT_ST + 5 + 1 + read-only + + + FRHOST_BIT14_INT_ST + 6 + 1 + read-only + + + FRHOST_BIT15_INT_ST + 7 + 1 + read-only + + + SLC1_RX_START_INT_ST + 8 + 1 + read-only + + + SLC1_TX_START_INT_ST + 9 + 1 + read-only + + + SLC1_RX_UDF_INT_ST + 10 + 1 + read-only + + + SLC1_TX_OVF_INT_ST + 11 + 1 + read-only + + + SLC1_TOKEN0_1TO0_INT_ST + 12 + 1 + read-only + + + SLC1_TOKEN1_1TO0_INT_ST + 13 + 1 + read-only + + + SLC1_TX_DONE_INT_ST + 14 + 1 + read-only + + + SLC1_TX_SUC_EOF_INT_ST + 15 + 1 + read-only + + + SLC1_RX_DONE_INT_ST + 16 + 1 + read-only + + + SLC1_RX_EOF_INT_ST + 17 + 1 + read-only + + + SLC1_TOHOST_INT_ST + 18 + 1 + read-only + + + SLC1_TX_DSCR_ERR_INT_ST + 19 + 1 + read-only + + + SLC1_RX_DSCR_ERR_INT_ST + 20 + 1 + read-only + + + SLC1_TX_DSCR_EMPTY_INT_ST + 21 + 1 + read-only + + + SLC1_HOST_RD_ACK_INT_ST + 22 + 1 + read-only + + + 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HOST_SLC0_TOHOST_BIT7_INT_ST + 7 + 1 + read-only + + + HOST_SLC0_TOKEN0_1TO0_INT_ST + 8 + 1 + read-only + + + HOST_SLC0_TOKEN1_1TO0_INT_ST + 9 + 1 + read-only + + + HOST_SLC0_TOKEN0_0TO1_INT_ST + 10 + 1 + read-only + + + HOST_SLC0_TOKEN1_0TO1_INT_ST + 11 + 1 + read-only + + + HOST_SLC0HOST_RX_SOF_INT_ST + 12 + 1 + read-only + + + HOST_SLC0HOST_RX_EOF_INT_ST + 13 + 1 + read-only + + + HOST_SLC0HOST_RX_START_INT_ST + 14 + 1 + read-only + + + HOST_SLC0HOST_TX_START_INT_ST + 15 + 1 + read-only + + + HOST_SLC0_RX_UDF_INT_ST + 16 + 1 + read-only + + + HOST_SLC0_TX_OVF_INT_ST + 17 + 1 + read-only + + + HOST_SLC0_RX_PF_VALID_INT_ST + 18 + 1 + read-only + + + HOST_SLC0_EXT_BIT0_INT_ST + 19 + 1 + read-only + + + HOST_SLC0_EXT_BIT1_INT_ST + 20 + 1 + read-only + + + HOST_SLC0_EXT_BIT2_INT_ST + 21 + 1 + read-only + + + HOST_SLC0_EXT_BIT3_INT_ST + 22 + 1 + read-only + + + HOST_SLC0_RX_NEW_PACKET_INT_ST + 23 + 1 + read-only + + + HOST_SLC0_HOST_RD_RETRY_INT_ST + 24 + 1 + read-only + + + HOST_GPIO_SDIO_INT_ST + 25 + 1 + read-only + + + + + HOST_SLC1HOST_INT_ST + 0x5C + 0x20 + + + HOST_SLC1_TOHOST_BIT0_INT_ST + 0 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT1_INT_ST + 1 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT2_INT_ST + 2 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT3_INT_ST + 3 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT4_INT_ST + 4 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT5_INT_ST + 5 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT6_INT_ST + 6 + 1 + read-only + + + HOST_SLC1_TOHOST_BIT7_INT_ST + 7 + 1 + read-only + + + HOST_SLC1_TOKEN0_1TO0_INT_ST + 8 + 1 + read-only + + + HOST_SLC1_TOKEN1_1TO0_INT_ST + 9 + 1 + read-only + + + HOST_SLC1_TOKEN0_0TO1_INT_ST + 10 + 1 + read-only + + + HOST_SLC1_TOKEN1_0TO1_INT_ST + 11 + 1 + read-only + + + HOST_SLC1HOST_RX_SOF_INT_ST + 12 + 1 + read-only + + + HOST_SLC1HOST_RX_EOF_INT_ST + 13 + 1 + read-only + + + HOST_SLC1HOST_RX_START_INT_ST + 14 + 1 + read-only + + + HOST_SLC1HOST_TX_START_INT_ST + 15 + 1 + read-only + + + HOST_SLC1_RX_UDF_INT_ST + 16 + 1 + read-only + + + HOST_SLC1_TX_OVF_INT_ST + 17 + 1 + read-only + + + HOST_SLC1_RX_PF_VALID_INT_ST + 18 + 1 + read-only + + + HOST_SLC1_EXT_BIT0_INT_ST + 19 + 1 + read-only + + + HOST_SLC1_EXT_BIT1_INT_ST + 20 + 1 + read-only + + + HOST_SLC1_EXT_BIT2_INT_ST + 21 + 1 + read-only + + + HOST_SLC1_EXT_BIT3_INT_ST + 22 + 1 + read-only + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST + 23 + 1 + read-only + + + HOST_SLC1_HOST_RD_RETRY_INT_ST + 24 + 1 + read-only + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_ST + 25 + 1 + read-only + + + + + HOST_SLCHOST_PKT_LEN + 0x60 + 0x20 + + + HOST_HOSTSLC0_LEN + 0 + 20 + read-only + + + HOST_HOSTSLC0_LEN_CHECK + 20 + 12 + read-only + + + + + HOST_SLCHOST_STATE_W0 + 0x64 + 0x20 + + + HOST_SLCHOST_STATE0 + 0 + 8 + read-only + + + HOST_SLCHOST_STATE1 + 8 + 8 + read-only + + + HOST_SLCHOST_STATE2 + 16 + 8 + read-only + + + HOST_SLCHOST_STATE3 + 24 + 8 + read-only + + + + + HOST_SLCHOST_STATE_W1 + 0x68 + 0x20 + + + HOST_SLCHOST_STATE4 + 0 + 8 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HOST_SLCHOST_CONF41 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF42 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF43 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CONF_W11 + 0xA8 + 0x20 + + + HOST_SLCHOST_CONF44 + 0 + 8 + read-write + + + HOST_SLCHOST_CONF45 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF46 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF47 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CONF_W12 + 0xAC + 0x20 + + + HOST_SLCHOST_CONF48 + 0 + 8 + read-write + + + HOST_SLCHOST_CONF49 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF50 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF51 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CONF_W13 + 0xB0 + 0x20 + + + HOST_SLCHOST_CONF52 + 0 + 8 + read-write + + + HOST_SLCHOST_CONF53 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF54 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF55 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CONF_W14 + 0xB4 + 0x20 + + + HOST_SLCHOST_CONF56 + 0 + 8 + read-write + + + HOST_SLCHOST_CONF57 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF58 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF59 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CONF_W15 + 0xB8 + 0x20 + + + HOST_SLCHOST_CONF60 + 0 + 8 + read-write + + + HOST_SLCHOST_CONF61 + 8 + 8 + read-write + + + HOST_SLCHOST_CONF62 + 16 + 8 + read-write + + + HOST_SLCHOST_CONF63 + 24 + 8 + read-write + + + + + HOST_SLCHOST_CHECK_SUM0 + 0xBC + 0x20 + + + HOST_SLCHOST_CHECK_SUM0 + 0 + 32 + read-only + + + + + HOST_SLCHOST_CHECK_SUM1 + 0xC0 + 0x20 + + + HOST_SLCHOST_CHECK_SUM1 + 0 + 32 + read-only + + + + + HOST_SLC1HOST_TOKEN_RDATA + 0xC4 + 0x20 + + + HOST_SLC1_TOKEN0 + 0 + 12 + read-only + + + HOST_SLC1_RX_PF_VALID + 12 + 1 + read-only + + + HOST_HOSTSLC1_TOKEN1 + 16 + 12 + read-only + + + HOST_SLC1_RX_PF_EOF + 28 + 4 + read-only + + + + + HOST_SLC0HOST_TOKEN_WDATA + 0xC8 + 0x20 + + + HOST_SLC0HOST_TOKEN0_WD + 0 + 12 + read-write + + + HOST_SLC0HOST_TOKEN1_WD + 16 + 12 + read-write + + + + + HOST_SLC1HOST_TOKEN_WDATA + 0xCC + 0x20 + + + HOST_SLC1HOST_TOKEN0_WD + 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HOST_SLC0_TOHOST_BIT6_INT_CLR + 6 + 1 + write-only + + + HOST_SLC0_TOHOST_BIT7_INT_CLR + 7 + 1 + write-only + + + HOST_SLC0_TOKEN0_1TO0_INT_CLR + 8 + 1 + write-only + + + HOST_SLC0_TOKEN1_1TO0_INT_CLR + 9 + 1 + write-only + + + HOST_SLC0_TOKEN0_0TO1_INT_CLR + 10 + 1 + write-only + + + HOST_SLC0_TOKEN1_0TO1_INT_CLR + 11 + 1 + write-only + + + HOST_SLC0HOST_RX_SOF_INT_CLR + 12 + 1 + write-only + + + HOST_SLC0HOST_RX_EOF_INT_CLR + 13 + 1 + write-only + + + HOST_SLC0HOST_RX_START_INT_CLR + 14 + 1 + write-only + + + HOST_SLC0HOST_TX_START_INT_CLR + 15 + 1 + write-only + + + HOST_SLC0_RX_UDF_INT_CLR + 16 + 1 + write-only + + + HOST_SLC0_TX_OVF_INT_CLR + 17 + 1 + write-only + + + HOST_SLC0_RX_PF_VALID_INT_CLR + 18 + 1 + write-only + + + HOST_SLC0_EXT_BIT0_INT_CLR + 19 + 1 + write-only + + + HOST_SLC0_EXT_BIT1_INT_CLR + 20 + 1 + write-only + + + HOST_SLC0_EXT_BIT2_INT_CLR + 21 + 1 + write-only + + + HOST_SLC0_EXT_BIT3_INT_CLR + 22 + 1 + write-only + + + HOST_SLC0_RX_NEW_PACKET_INT_CLR + 23 + 1 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HOST_SLC1HOST_RX_START_INT_CLR + 14 + 1 + write-only + + + HOST_SLC1HOST_TX_START_INT_CLR + 15 + 1 + write-only + + + HOST_SLC1_RX_UDF_INT_CLR + 16 + 1 + write-only + + + HOST_SLC1_TX_OVF_INT_CLR + 17 + 1 + write-only + + + HOST_SLC1_RX_PF_VALID_INT_CLR + 18 + 1 + write-only + + + HOST_SLC1_EXT_BIT0_INT_CLR + 19 + 1 + write-only + + + HOST_SLC1_EXT_BIT1_INT_CLR + 20 + 1 + write-only + + + HOST_SLC1_EXT_BIT2_INT_CLR + 21 + 1 + write-only + + + HOST_SLC1_EXT_BIT3_INT_CLR + 22 + 1 + write-only + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR + 23 + 1 + write-only + + + HOST_SLC1_HOST_RD_RETRY_INT_CLR + 24 + 1 + write-only + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR + 25 + 1 + write-only + + + + + HOST_SLC0HOST_FUNC1_INT_ENA + 0xDC + 0x20 + + + HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_FN1_SLC0HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_FN1_SLC0HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_FN1_SLC0HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_FN1_SLC0HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_FN1_SLC0_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_FN1_SLC0_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_FN1_SLC0_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_FN1_SLC0_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_FN1_SLC0_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_FN1_SLC0_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_FN1_SLC0_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_FN1_GPIO_SDIO_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC1HOST_FUNC1_INT_ENA + 0xE0 + 0x20 + + + HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_FN1_SLC1HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_FN1_SLC1HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_FN1_SLC1HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_FN1_SLC1HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_FN1_SLC1_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_FN1_SLC1_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_FN1_SLC1_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_FN1_SLC1_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_FN1_SLC1_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_FN1_SLC1_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_FN1_SLC1_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC0HOST_FUNC2_INT_ENA + 0xE4 + 0x20 + + + HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_FN2_SLC0HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_FN2_SLC0HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_FN2_SLC0HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_FN2_SLC0HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_FN2_SLC0_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_FN2_SLC0_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_FN2_SLC0_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_FN2_SLC0_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_FN2_SLC0_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_FN2_SLC0_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_FN2_SLC0_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_FN2_GPIO_SDIO_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC1HOST_FUNC2_INT_ENA + 0xE8 + 0x20 + + + HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_FN2_SLC1HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_FN2_SLC1HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_FN2_SLC1HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_FN2_SLC1HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_FN2_SLC1_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_FN2_SLC1_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_FN2_SLC1_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_FN2_SLC1_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_FN2_SLC1_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_FN2_SLC1_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_FN2_SLC1_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC0HOST_INT_ENA + 0xEC + 0x20 + + + HOST_SLC0_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_SLC0_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_SLC0_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_SLC0_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_SLC0_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_SLC0HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_SLC0HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_SLC0HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_SLC0HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_SLC0_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_SLC0_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_SLC0_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_SLC0_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_SLC0_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_SLC0_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_SLC0_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_SLC0_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_SLC0_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_GPIO_SDIO_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC1HOST_INT_ENA + 0xF0 + 0x20 + + + HOST_SLC1_TOHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + HOST_SLC1_TOKEN0_1TO0_INT_ENA + 8 + 1 + read-write + + + HOST_SLC1_TOKEN1_1TO0_INT_ENA + 9 + 1 + read-write + + + HOST_SLC1_TOKEN0_0TO1_INT_ENA + 10 + 1 + read-write + + + HOST_SLC1_TOKEN1_0TO1_INT_ENA + 11 + 1 + read-write + + + HOST_SLC1HOST_RX_SOF_INT_ENA + 12 + 1 + read-write + + + HOST_SLC1HOST_RX_EOF_INT_ENA + 13 + 1 + read-write + + + HOST_SLC1HOST_RX_START_INT_ENA + 14 + 1 + read-write + + + HOST_SLC1HOST_TX_START_INT_ENA + 15 + 1 + read-write + + + HOST_SLC1_RX_UDF_INT_ENA + 16 + 1 + read-write + + + HOST_SLC1_TX_OVF_INT_ENA + 17 + 1 + read-write + + + HOST_SLC1_RX_PF_VALID_INT_ENA + 18 + 1 + read-write + + + HOST_SLC1_EXT_BIT0_INT_ENA + 19 + 1 + read-write + + + HOST_SLC1_EXT_BIT1_INT_ENA + 20 + 1 + read-write + + + HOST_SLC1_EXT_BIT2_INT_ENA + 21 + 1 + read-write + + + HOST_SLC1_EXT_BIT3_INT_ENA + 22 + 1 + read-write + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + 23 + 1 + read-write + + + HOST_SLC1_HOST_RD_RETRY_INT_ENA + 24 + 1 + read-write + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA + 25 + 1 + read-write + + + + + HOST_SLC0HOST_RX_INFOR + 0xF4 + 0x20 + + + HOST_SLC0HOST_RX_INFOR + 0 + 20 + read-write + + + + + HOST_SLC1HOST_RX_INFOR + 0xF8 + 0x20 + + + HOST_SLC1HOST_RX_INFOR + 0 + 20 + read-write + + + + + HOST_SLC0HOST_LEN_WD + 0xFC + 0x20 + + + HOST_SLC0HOST_LEN_WD + 0 + 32 + read-write + + + + + HOST_SLC_APBWIN_WDATA + 0x100 + 0x20 + + + HOST_SLC_APBWIN_WDATA + 0 + 32 + read-write + + + + + HOST_SLC_APBWIN_CONF + 0x104 + 0x20 + + + HOST_SLC_APBWIN_ADDR + 0 + 28 + read-write + + + HOST_SLC_APBWIN_WR + 28 + 1 + read-write + + + HOST_SLC_APBWIN_START + 29 + 1 + read-write + + + + + HOST_SLC_APBWIN_RDATA + 0x108 + 0x20 + + + HOST_SLC_APBWIN_RDATA + 0 + 32 + read-only + + + + + HOST_SLCHOST_RDCLR0 + 0x10C + 0x20 + 0x0003C044 + + + HOST_SLCHOST_SLC0_BIT7_CLRADDR + 0 + 9 + read-write + + + HOST_SLCHOST_SLC0_BIT6_CLRADDR + 9 + 9 + read-write + + + + + HOST_SLCHOST_RDCLR1 + 0x110 + 0x20 + 0x0003C1E0 + + + HOST_SLCHOST_SLC1_BIT7_CLRADDR + 0 + 9 + read-write + + + HOST_SLCHOST_SLC1_BIT6_CLRADDR + 9 + 9 + read-write + + + + + HOST_SLC0HOST_INT_ENA1 + 0x114 + 0x20 + + + HOST_SLC0_TOHOST_BIT0_INT_ENA1 + 0 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT1_INT_ENA1 + 1 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT2_INT_ENA1 + 2 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT3_INT_ENA1 + 3 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT4_INT_ENA1 + 4 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT5_INT_ENA1 + 5 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT6_INT_ENA1 + 6 + 1 + read-write + + + HOST_SLC0_TOHOST_BIT7_INT_ENA1 + 7 + 1 + read-write + + + HOST_SLC0_TOKEN0_1TO0_INT_ENA1 + 8 + 1 + read-write + + + HOST_SLC0_TOKEN1_1TO0_INT_ENA1 + 9 + 1 + read-write + + + HOST_SLC0_TOKEN0_0TO1_INT_ENA1 + 10 + 1 + read-write + + + HOST_SLC0_TOKEN1_0TO1_INT_ENA1 + 11 + 1 + read-write + + + HOST_SLC0HOST_RX_SOF_INT_ENA1 + 12 + 1 + read-write + + + HOST_SLC0HOST_RX_EOF_INT_ENA1 + 13 + 1 + read-write + + + HOST_SLC0HOST_RX_START_INT_ENA1 + 14 + 1 + read-write + + + HOST_SLC0HOST_TX_START_INT_ENA1 + 15 + 1 + read-write + + + HOST_SLC0_RX_UDF_INT_ENA1 + 16 + 1 + read-write + + + HOST_SLC0_TX_OVF_INT_ENA1 + 17 + 1 + read-write + + + HOST_SLC0_RX_PF_VALID_INT_ENA1 + 18 + 1 + read-write + + + HOST_SLC0_EXT_BIT0_INT_ENA1 + 19 + 1 + read-write + + + HOST_SLC0_EXT_BIT1_INT_ENA1 + 20 + 1 + read-write + + + HOST_SLC0_EXT_BIT2_INT_ENA1 + 21 + 1 + read-write + + + HOST_SLC0_EXT_BIT3_INT_ENA1 + 22 + 1 + read-write + + + HOST_SLC0_RX_NEW_PACKET_INT_ENA1 + 23 + 1 + read-write + + + HOST_SLC0_HOST_RD_RETRY_INT_ENA1 + 24 + 1 + read-write + + + HOST_GPIO_SDIO_INT_ENA1 + 25 + 1 + read-write + + + + + HOST_SLC1HOST_INT_ENA1 + 0x118 + 0x20 + + + HOST_SLC1_TOHOST_BIT0_INT_ENA1 + 0 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT1_INT_ENA1 + 1 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT2_INT_ENA1 + 2 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT3_INT_ENA1 + 3 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT4_INT_ENA1 + 4 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT5_INT_ENA1 + 5 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT6_INT_ENA1 + 6 + 1 + read-write + + + HOST_SLC1_TOHOST_BIT7_INT_ENA1 + 7 + 1 + read-write + + + HOST_SLC1_TOKEN0_1TO0_INT_ENA1 + 8 + 1 + read-write + + + HOST_SLC1_TOKEN1_1TO0_INT_ENA1 + 9 + 1 + read-write + + + HOST_SLC1_TOKEN0_0TO1_INT_ENA1 + 10 + 1 + read-write + + + HOST_SLC1_TOKEN1_0TO1_INT_ENA1 + 11 + 1 + read-write + + + HOST_SLC1HOST_RX_SOF_INT_ENA1 + 12 + 1 + read-write + + + HOST_SLC1HOST_RX_EOF_INT_ENA1 + 13 + 1 + read-write + + + HOST_SLC1HOST_RX_START_INT_ENA1 + 14 + 1 + read-write + + + HOST_SLC1HOST_TX_START_INT_ENA1 + 15 + 1 + read-write + + + HOST_SLC1_RX_UDF_INT_ENA1 + 16 + 1 + read-write + + + HOST_SLC1_TX_OVF_INT_ENA1 + 17 + 1 + read-write + + + HOST_SLC1_RX_PF_VALID_INT_ENA1 + 18 + 1 + read-write + + + HOST_SLC1_EXT_BIT0_INT_ENA1 + 19 + 1 + read-write + + + HOST_SLC1_EXT_BIT1_INT_ENA1 + 20 + 1 + read-write + + + HOST_SLC1_EXT_BIT2_INT_ENA1 + 21 + 1 + read-write + + + HOST_SLC1_EXT_BIT3_INT_ENA1 + 22 + 1 + read-write + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 + 23 + 1 + read-write + + + HOST_SLC1_HOST_RD_RETRY_INT_ENA1 + 24 + 1 + read-write + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 + 25 + 1 + read-write + + + + + HOST_SLCHOSTDATE + 0x178 + 0x20 + 0x16022500 + + + HOST_SLCHOST_DATE + 0 + 32 + read-write + + + + + HOST_SLCHOSTID + 0x17C + 0x20 + 0x00000600 + + + HOST_SLCHOST_ID + 0 + 32 + read-write + + + + + HOST_SLCHOST_CONF + 0x1F0 + 0x20 + + + HOST_FRC_SDIO11 + 0 + 5 + read-write + + + HOST_FRC_SDIO20 + 5 + 5 + read-write + + + HOST_FRC_NEG_SAMP + 10 + 5 + read-write + + + HOST_FRC_POS_SAMP + 15 + 5 + read-write + + + HOST_FRC_QUICK_IN + 20 + 5 + read-write + + + HOST_SDIO20_INT_DELAY + 25 + 1 + read-write + + + HOST_SDIO_PAD_PULLUP + 26 + 1 + read-write + + + HOST_HSPEED_CON_EN + 27 + 1 + read-write + + + + + HOST_SLCHOST_INF_ST + 0x1F4 + 0x20 + + + HOST_SDIO20_MODE + 0 + 5 + read-only + + + HOST_SDIO_NEG_SAMP + 5 + 5 + read-only + + + HOST_SDIO_QUICK_IN + 10 + 5 + read-only + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI + 0x3FF43000 + + 0x0 + 0x110 + registers + + + SPI0 + 28 + + + + CMD + 0x0 + 0x20 + + + FLASH_PER + program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 16 + 1 + read-write + + + FLASH_PES + program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + 0x4 + 0x20 + + + CTRL + 0x8 + 0x20 + 0x0020A400 + + + FCS_CRC_EN + For SPI1 initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + WAIT_FLASH_IDLE_EN + wait flash idle when program flash or erase flash. 1: enable 0: disable. + 12 + 1 + read-write + + + FASTRD_MODE + This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + FREAD_DUAL + In the read operations read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high 0: output low. + 21 + 1 + read-write + + + WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first + 25 + 1 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first + 26 + 1 + read-write + + + + + CTRL1 + 0xC + 0x20 + 0x5FFF0000 + + + CS_HOLD_DELAY_RES + Delay cycles of resume Flash when resume Flash is enable by spi clock. + 16 + 12 + read-write + + + CS_HOLD_DELAY + SPI cs signal is delayed by spi clock cycles + 28 + 4 + read-write + + + + + RD_STATUS + 0x10 + 0x20 + + + STATUS + In the slave mode, it is the status for master to read out. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit. + 16 + 8 + read-write + + + STATUS_EXT + In the slave mode,it is the status for master to read out. + 24 + 8 + read-write + + + + + CTRL2 + 0x14 + 0x20 + 0x00000011 + + + SETUP_TIME + (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit. + 0 + 4 + read-write + + + HOLD_TIME + delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit. + 4 + 4 + read-write + + + CK_OUT_LOW_MODE + modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits. + 8 + 4 + read-write + + + CK_OUT_HIGH_MODE + modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits. + 12 + 4 + read-write + + + MISO_DELAY_MODE + MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle + 16 + 2 + read-write + + + MISO_DELAY_NUM + MISO signals are delayed by system clock cycles + 18 + 3 + read-write + + + MOSI_DELAY_MODE + MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle + 21 + 2 + read-write + + + MOSI_DELAY_NUM + MOSI signals are delayed by system clock cycles + 23 + 3 + read-write + + + CS_DELAY_MODE + spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle + 26 + 2 + read-write + + + CS_DELAY_NUM + spi_cs signal is delayed by system clock cycles + 28 + 4 + read-write + + + + + CLOCK + 0x18 + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. + 18 + 13 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. + 31 + 1 + read-write + + + + + USER + 0x1C + 0x20 + 0x80000040 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. + 0 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable. + 4 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable. + 5 + 1 + read-write + + + CK_I_EDGE + In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits. + 6 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. + 7 + 1 + read-write + + + RD_BYTE_ORDER + In read-data (MISO) phase 1: big-endian 0: little_endian + 10 + 1 + read-write + + + WR_BYTE_ORDER + In command address write-data (MOSI) phases 1: big-endian 0: litte_endian + 11 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. + 16 + 1 + read-write + + + USR_HOLD_POL + It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low + 17 + 1 + read-write + + + USR_DOUT_HOLD + spi is hold at data out state the bit combined with spi_usr_hold_pol bit. + 18 + 1 + read-write + + + USR_DIN_HOLD + spi is hold at data in state the bit combined with spi_usr_hold_pol bit. + 19 + 1 + read-write + + + USR_DUMMY_HOLD + spi is hold at dummy state the bit combined with spi_usr_hold_pol bit. + 20 + 1 + read-write + + + USR_ADDR_HOLD + spi is hold at address state the bit combined with spi_usr_hold_pol bit. + 21 + 1 + read-write + + + USR_CMD_HOLD + spi is hold at command state the bit combined with spi_usr_hold_pol bit. + 22 + 1 + read-write + + + USR_PREP_HOLD + spi is hold at prepare state the bit combined with spi_usr_hold_pol bit. + 23 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + USER1 + 0x20 + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 8 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-only + + + + + USER2 + 0x24 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + 0x28 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 24 + read-write + + + + + MISO_DLEN + 0x2C + 0x20 + + + USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 24 + read-write + + + + + SLV_WR_STATUS + 0x30 + 0x20 + + + SLV_WR_ST + In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition. + 0 + 32 + read-write + + + + + PIN + 0x34 + 0x20 + 0x00000006 + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin + 2 + 1 + read-write + + + CK_DIS + 1: spi clk out disable 0: spi clk out enable + 5 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. + 6 + 3 + read-write + + + MASTER_CK_SEL + In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis. + 11 + 3 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 30 + 1 + read-write + + + + + SLAVE + 0x38 + 0x20 + 0x00000020 + + + SLV_RD_BUF_DONE + The interrupt raw bit for the completion of read-buffer operation in the slave mode. + 0 + 1 + read-write + + + SLV_WR_BUF_DONE + The interrupt raw bit for the completion of write-buffer operation in the slave mode. + 1 + 1 + read-write + + + SLV_RD_STA_DONE + The interrupt raw bit for the completion of read-status operation in the slave mode. + 2 + 1 + read-write + + + SLV_WR_STA_DONE + The interrupt raw bit for the completion of write-status operation in the slave mode. + 3 + 1 + read-write + + + TRANS_DONE + The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. + 4 + 1 + read-write + + + INT_EN + Interrupt enable bits for the below 5 sources + 5 + 5 + read-write + + + CS_I_MODE + In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter. + 10 + 2 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 17 + 3 + read-only + + + SLV_LAST_STATE + In the slave mode it is the state of spi state machine. + 20 + 3 + read-only + + + TRANS_CNT + The operations counter in both the master mode and the slave mode. 4: read-status + 23 + 4 + read-only + + + SLV_CMD_DEFINE + 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer. + 27 + 1 + read-write + + + SLV_WR_RD_STA_EN + write and read status enable in the slave mode + 28 + 1 + read-write + + + SLV_WR_RD_BUF_EN + write and read buffer enable in the slave mode + 29 + 1 + read-write + + + MODE + 1: slave mode 0: master mode. + 30 + 1 + read-write + + + SYNC_RESET + Software reset enable, reset the spi clock line cs line and data lines. + 31 + 1 + read-write + + + + + SLAVE1 + 0x3C + 0x20 + 0x02000000 + + + SLV_RDBUF_DUMMY_EN + In the slave mode it is the enable bit of dummy phase for read-buffer operations. + 0 + 1 + read-write + + + SLV_WRBUF_DUMMY_EN + In the slave mode it is the enable bit of dummy phase for write-buffer operations. + 1 + 1 + read-write + + + SLV_RDSTA_DUMMY_EN + In the slave mode it is the enable bit of dummy phase for read-status operations. + 2 + 1 + read-write + + + SLV_WRSTA_DUMMY_EN + In the slave mode it is the enable bit of dummy phase for write-status operations. + 3 + 1 + read-write + + + SLV_WR_ADDR_BITLEN + In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1). + 4 + 6 + read-write + + + SLV_RD_ADDR_BITLEN + In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1). + 10 + 6 + read-write + + + SLV_STATUS_READBACK + In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS. + 25 + 1 + read-write + + + SLV_STATUS_FAST_EN + In the slave mode enable fast read status. + 26 + 1 + read-write + + + SLV_STATUS_BITLEN + In the slave mode it is the length of status bit. + 27 + 5 + read-write + + + + + SLAVE2 + 0x40 + 0x20 + + + SLV_RDSTA_DUMMY_CYCLELEN + In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1). + 0 + 8 + read-write + + + SLV_WRSTA_DUMMY_CYCLELEN + In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1). + 8 + 8 + read-write + + + SLV_RDBUF_DUMMY_CYCLELEN + In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1). + 16 + 8 + read-write + + + SLV_WRBUF_DUMMY_CYCLELEN + In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1). + 24 + 8 + read-write + + + + + SLAVE3 + 0x44 + 0x20 + + + SLV_RDBUF_CMD_VALUE + In the slave mode it is the value of read-buffer command. + 0 + 8 + read-write + + + SLV_WRBUF_CMD_VALUE + In the slave mode it is the value of write-buffer command. + 8 + 8 + read-write + + + SLV_RDSTA_CMD_VALUE + In the slave mode it is the value of read-status command. + 16 + 8 + read-write + + + SLV_WRSTA_CMD_VALUE + In the slave mode it is the value of write-status command. + 24 + 8 + read-write + + + + + SLV_WRBUF_DLEN + 0x48 + 0x20 + + + SLV_WRBUF_DBITLEN + In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1). + 0 + 24 + read-write + + + + + SLV_RDBUF_DLEN + 0x4C + 0x20 + + + SLV_RDBUF_DBITLEN + In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1). + 0 + 24 + read-write + + + + + CACHE_FCTRL + 0x50 + 0x20 + + + CACHE_REQ_EN + For SPI0 Cache access enable 1: enable 0:disable. + 0 + 1 + read-write + + + CACHE_USR_CMD_4BYTE + For SPI0 cache read flash with 4 bytes command 1: enable 0:disable. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + For SPI0 cache read flash for user define command 1: enable 0:disable. + 2 + 1 + read-write + + + CACHE_FLASH_PES_EN + For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable. + 3 + 1 + read-write + + + + + CACHE_SCTRL + 0x54 + 0x20 + 0x15C04830 + + + USR_SRAM_DIO + For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable + 1 + 1 + read-write + + + USR_SRAM_QIO + For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable + 2 + 1 + read-write + + + USR_WR_SRAM_DUMMY + For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. + 3 + 1 + read-write + + + USR_RD_SRAM_DUMMY + For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. + 4 + 1 + read-write + + + CACHE_SRAM_USR_RCMD + For SPI0 In the spi sram mode cache read sram for user define command. + 5 + 1 + read-write + + + SRAM_BYTES_LEN + For SPI0 In the sram mode it is the byte length of spi read sram data. + 6 + 8 + read-write + + + SRAM_DUMMY_CYCLELEN + For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 8 + read-write + + + SRAM_ADDR_BITLEN + For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). + 22 + 6 + read-write + + + CACHE_SRAM_USR_WCMD + For SPI0 In the spi sram mode cache write sram for user define command + 28 + 1 + read-write + + + + + SRAM_CMD + 0x58 + 0x20 + + + SRAM_DIO + For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done. + 0 + 1 + read-write + + + SRAM_QIO + For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done. + 1 + 1 + read-write + + + SRAM_RSTIO + For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done + 4 + 1 + read-write + + + + + SRAM_DRD_CMD + 0x5C + 0x20 + + + CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0 When cache mode is enable it is the read command value of command phase for SRAM. + 0 + 16 + read-write + + + CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_DWR_CMD + 0x60 + 0x20 + + + CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0 When cache mode is enable it is the write command value of command phase for SRAM. + 0 + 16 + read-write + + + CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SLV_RD_BIT + 0x64 + 0x20 + + + SLV_RDATA_BIT + In the slave mode it is the bit length of read data. The value is the length - 1. + 0 + 24 + read-write + + + + + W0 + 0x80 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + 0x84 + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + 0x88 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + 0x8C + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + 0x90 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + 0x94 + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + 0x98 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + 0x9C + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + 0xA0 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + 0xA4 + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + 0xA8 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + 0xAC + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + 0xB0 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + 0xB4 + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + 0xB8 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + 0xBC + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + TX_CRC + 0xC0 + 0x20 + + + DATA + For SPI1 the value of crc32 for 256 bits data. + 0 + 32 + read-write + + + + + EXT0 + 0xF0 + 0x20 + 0x800A0050 + + + T_PP_TIME + page program delay time by system clock. + 0 + 12 + read-write + + + T_PP_SHIFT + page program delay time shift . + 16 + 4 + read-write + + + T_PP_ENA + page program delay enable. + 31 + 1 + read-write + + + + + EXT1 + 0xF4 + 0x20 + 0x800F0000 + + + T_ERASE_TIME + erase flash delay time by system clock. + 0 + 12 + read-write + + + T_ERASE_SHIFT + erase flash delay time shift. + 16 + 4 + read-write + + + T_ERASE_ENA + erase flash delay enable. + 31 + 1 + read-write + + + + + EXT2 + 0xF8 + 0x20 + + + ST + The status of spi state machine . + 0 + 3 + read-only + + + + + EXT3 + 0xFC + 0x20 + + + INT_HOLD_ENA + This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase. + 0 + 2 + read-write + + + + + DMA_CONF + 0x100 + 0x20 + 0x00000200 + + + IN_RST + The bit is used to reset in dma fsm and in data fifo pointer. + 2 + 1 + read-write + + + OUT_RST + The bit is used to reset out dma fsm and out data fifo pointer. + 3 + 1 + read-write + + + AHBM_FIFO_RST + reset spi dma ahb master fifo pointer. + 4 + 1 + read-write + + + AHBM_RST + reset spi dma ahb master. + 5 + 1 + read-write + + + IN_LOOP_TEST + Set bit to test in link. + 6 + 1 + read-write + + + OUT_LOOP_TEST + Set bit to test out link. + 7 + 1 + read-write + + + OUT_AUTO_WRBACK + when the link is empty jump to next automatically. + 8 + 1 + read-write + + + OUT_EOF_MODE + out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo. + 9 + 1 + read-write + + + OUTDSCR_BURST_EN + read descriptor use burst mode when read data for memory. + 10 + 1 + read-write + + + INDSCR_BURST_EN + read descriptor use burst mode when write data to memory. + 11 + 1 + read-write + + + OUT_DATA_BURST_EN + spi dma read data from memory in burst mode. + 12 + 1 + read-write + + + DMA_RX_STOP + spi dma read data stop when in continue tx/rx mode. + 14 + 1 + read-write + + + DMA_TX_STOP + spi dma write data stop when in continue tx/rx mode. + 15 + 1 + read-write + + + DMA_CONTINUE + spi dma continue tx/rx data. + 16 + 1 + read-write + + + + + DMA_OUT_LINK + 0x104 + 0x20 + + + OUTLINK_ADDR + The address of the first outlink descriptor. + 0 + 20 + read-write + + + OUTLINK_STOP + Set the bit to stop to use outlink descriptor. + 28 + 1 + read-write + + + OUTLINK_START + Set the bit to start to use outlink descriptor. + 29 + 1 + read-write + + + OUTLINK_RESTART + Set the bit to mount on new outlink descriptors. + 30 + 1 + read-write + + + + + DMA_IN_LINK + 0x108 + 0x20 + + + INLINK_ADDR + The address of the first inlink descriptor. + 0 + 20 + read-write + + + INLINK_AUTO_RET + when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong + 20 + 1 + read-write + + + INLINK_STOP + Set the bit to stop to use inlink descriptor. + 28 + 1 + read-write + + + INLINK_START + Set the bit to start to use inlink descriptor. + 29 + 1 + read-write + + + INLINK_RESTART + Set the bit to mount on new inlink descriptors. + 30 + 1 + read-write + + + + + DMA_STATUS + 0x10C + 0x20 + + + DMA_RX_EN + spi dma read data status bit. + 0 + 1 + read-only + + + DMA_TX_EN + spi dma write data status bit. + 1 + 1 + read-only + + + + + DMA_INT_ENA + 0x110 + 0x20 + + + INLINK_DSCR_EMPTY_INT_ENA + The enable bit for lack of enough inlink descriptors. + 0 + 1 + read-write + + + OUTLINK_DSCR_ERROR_INT_ENA + The enable bit for outlink descriptor error. + 1 + 1 + read-write + + + INLINK_DSCR_ERROR_INT_ENA + The enable bit for inlink descriptor error. + 2 + 1 + read-write + + + IN_DONE_INT_ENA + The enable bit for completing usage of a inlink descriptor. + 3 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + The enable bit for receiving error. + 4 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + The enable bit for completing receiving all the packets from host. + 5 + 1 + read-write + + + OUT_DONE_INT_ENA + The enable bit for completing usage of a outlink descriptor . + 6 + 1 + read-write + + + OUT_EOF_INT_ENA + The enable bit for sending a packet to host done. + 7 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + The enable bit for sending all the packets to host done. + 8 + 1 + read-write + + + + + DMA_INT_RAW + 0x114 + 0x20 + + + INLINK_DSCR_EMPTY_INT_RAW + The raw bit for lack of enough inlink descriptors. + 0 + 1 + read-only + + + OUTLINK_DSCR_ERROR_INT_RAW + The raw bit for outlink descriptor error. + 1 + 1 + read-only + + + INLINK_DSCR_ERROR_INT_RAW + The raw bit for inlink descriptor error. + 2 + 1 + read-only + + + IN_DONE_INT_RAW + The raw bit for completing usage of a inlink descriptor. + 3 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + The raw bit for receiving error. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + The raw bit for completing receiving all the packets from host. + 5 + 1 + read-only + + + OUT_DONE_INT_RAW + The raw bit for completing usage of a outlink descriptor. + 6 + 1 + read-only + + + OUT_EOF_INT_RAW + The raw bit for sending a packet to host done. + 7 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + The raw bit for sending all the packets to host done. + 8 + 1 + read-only + + + + + DMA_INT_ST + 0x118 + 0x20 + + + INLINK_DSCR_EMPTY_INT_ST + The status bit for lack of enough inlink descriptors. + 0 + 1 + read-only + + + OUTLINK_DSCR_ERROR_INT_ST + The status bit for outlink descriptor error. + 1 + 1 + read-only + + + INLINK_DSCR_ERROR_INT_ST + The status bit for inlink descriptor error. + 2 + 1 + read-only + + + IN_DONE_INT_ST + The status bit for completing usage of a inlink descriptor. + 3 + 1 + read-only + + + IN_ERR_EOF_INT_ST + The status bit for receiving error. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_ST + The status bit for completing receiving all the packets from host. + 5 + 1 + read-only + + + OUT_DONE_INT_ST + The status bit for completing usage of a outlink descriptor. + 6 + 1 + read-only + + + OUT_EOF_INT_ST + The status bit for sending a packet to host done. + 7 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + The status bit for sending all the packets to host done. + 8 + 1 + read-only + + + + + DMA_INT_CLR + 0x11C + 0x20 + + + INLINK_DSCR_EMPTY_INT_CLR + The clear bit for lack of enough inlink descriptors. + 0 + 1 + read-write + + + OUTLINK_DSCR_ERROR_INT_CLR + The clear bit for outlink descriptor error. + 1 + 1 + read-write + + + INLINK_DSCR_ERROR_INT_CLR + The clear bit for inlink descriptor error. + 2 + 1 + read-write + + + IN_DONE_INT_CLR + The clear bit for completing usage of a inlink descriptor. + 3 + 1 + read-write + + + IN_ERR_EOF_INT_CLR + The clear bit for receiving error. + 4 + 1 + read-write + + + IN_SUC_EOF_INT_CLR + The clear bit for completing receiving all the packets from host. + 5 + 1 + read-write + + + OUT_DONE_INT_CLR + The clear bit for completing usage of a outlink descriptor. + 6 + 1 + read-write + + + OUT_EOF_INT_CLR + The clear bit for sending a packet to host done. + 7 + 1 + read-write + + + OUT_TOTAL_EOF_INT_CLR + The clear bit for sending all the packets to host done. + 8 + 1 + read-write + + + + + IN_ERR_EOF_DES_ADDR + 0x120 + 0x20 + + + DMA_IN_ERR_EOF_DES_ADDR + The inlink descriptor address when spi dma produce receiving error. + 0 + 32 + read-only + + + + + IN_SUC_EOF_DES_ADDR + 0x124 + 0x20 + + + DMA_IN_SUC_EOF_DES_ADDR + The last inlink descriptor address when spi dma produce from_suc_eof. + 0 + 32 + read-only + + + + + INLINK_DSCR + 0x128 + 0x20 + + + DMA_INLINK_DSCR + The content of current in descriptor pointer. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF0 + 0x12C + 0x20 + + + DMA_INLINK_DSCR_BF0 + The content of next in descriptor pointer. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF1 + 0x130 + 0x20 + + + DMA_INLINK_DSCR_BF1 + The content of current in descriptor data buffer pointer. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR + 0x134 + 0x20 + + + DMA_OUT_EOF_BFR_DES_ADDR + The address of buffer relative to the outlink descriptor that produce eof. + 0 + 32 + read-only + + + + + OUT_EOF_DES_ADDR + 0x138 + 0x20 + + + DMA_OUT_EOF_DES_ADDR + The last outlink descriptor address when spi dma produce to_eof. + 0 + 32 + read-only + + + + + OUTLINK_DSCR + 0x13C + 0x20 + + + DMA_OUTLINK_DSCR + The content of current out descriptor pointer. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF0 + 0x140 + 0x20 + + + DMA_OUTLINK_DSCR_BF0 + The content of next out descriptor pointer. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF1 + 0x144 + 0x20 + + + DMA_OUTLINK_DSCR_BF1 + The content of current out descriptor data buffer pointer. + 0 + 32 + read-only + + + + + DMA_RSTATUS + 0x148 + 0x20 + + + DMA_OUT_STATUS + spi dma read data from memory status. + 0 + 32 + read-only + + + + + DMA_TSTATUS + 0x14C + 0x20 + + + DMA_IN_STATUS + spi dma write data to memory status. + 0 + 32 + read-only + + + + + DATE + 0x3FC + 0x20 + 0x01604270 + + + DATE + SPI register version. + 0 + 28 + read-only + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + 0x3FF42000 + + SPI1 + 29 + + + SPI1_DMA + 52 + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + 0x3FF64000 + + SPI2 + 30 + + + SPI2_DMA + 53 + + + + SPI3 + SPI (Serial Peripheral Interface) Controller + 0x3FF65000 + + SPI3 + 31 + + + SPI3_DMA + 54 + + + + TIMG0 + Timer Group + TIMG + 0x3FF5F000 + + 0x0 + 0xB0 + registers + + + TG0_T0_LEVEL + 14 + + + TG0_T1_LEVEL + 15 + + + TG0_WDT_LEVEL + 16 + + + TG0_LACT_LEVEL + 17 + + + TG0_T0_EDGE + 58 + + + TG0_T1_EDGE + 59 + + + TG0_WDT_EDGE + 60 + + + TG0_LACT_EDGE + 61 + + + + T0CONFIG + 0x0 + 0x20 + 0x60002000 + + + ALARM_EN + When set alarm is enabled + 10 + 1 + read-write + + + LEVEL_INT_EN + When set level type interrupt will be generated during alarm + 11 + 1 + read-write + + + EDGE_INT_EN + When set edge type interrupt will be generated during alarm + 12 + 1 + read-write + + + DIVIDER + Timer 0 clock (T0_clk) prescale value. + 13 + 16 + read-write + + + AUTORELOAD + When set timer 0 auto-reload at alarming is enabled + 29 + 1 + read-write + + + INCREASE + When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement. + 30 + 1 + read-write + + + EN + When set timer 0 time-base counter is enabled + 31 + 1 + read-write + + + + + T0LO + 0x4 + 0x20 + + + LO + Register to store timer 0 time-base counter current value lower 32 bits. + 0 + 32 + read-only + + + + + T0HI + 0x8 + 0x20 + + + HI + Register to store timer 0 time-base counter current value higher 32 bits. + 0 + 32 + read-only + + + + + T0UPDATE + 0xC + 0x20 + + + UPDATE + Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above) + 0 + 32 + write-only + + + + + T0ALARMLO + 0x10 + 0x20 + + + ALARM_LO + Timer 0 time-base counter value lower 32 bits that will trigger the alarm + 0 + 32 + read-write + + + + + T0ALARMHI + 0x14 + 0x20 + + + ALARM_HI + Timer 0 time-base counter value higher 32 bits that will trigger the alarm + 0 + 32 + read-write + + + + + T0LOADLO + 0x18 + 0x20 + + + LOAD_LO + Lower 32 bits of the value that will load into timer 0 time-base counter + 0 + 32 + read-write + + + + + T0LOADHI + 0x1C + 0x20 + + + LOAD_HI + higher 32 bits of the value that will load into timer 0 time-base counter + 0 + 32 + read-write + + + + + T0LOAD + 0x20 + 0x20 + + + LOAD + Write any value will trigger timer 0 time-base counter reload + 0 + 32 + write-only + + + + + T1CONFIG + 0x24 + 0x20 + 0x60002000 + + + ALARM_EN + When set alarm is enabled + 10 + 1 + read-write + + + LEVEL_INT_EN + When set level type interrupt will be generated during alarm + 11 + 1 + read-write + + + EDGE_INT_EN + When set edge type interrupt will be generated during alarm + 12 + 1 + read-write + + + DIVIDER + Timer 1 clock (T1_clk) prescale value. + 13 + 16 + read-write + + + AUTORELOAD + When set timer 1 auto-reload at alarming is enabled + 29 + 1 + read-write + + + INCREASE + When set timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement. + 30 + 1 + read-write + + + EN + When set timer 1 time-base counter is enabled + 31 + 1 + read-write + + + + + T1LO + 0x28 + 0x20 + + + LO + Register to store timer 1 time-base counter current value lower 32 bits. + 0 + 32 + read-only + + + + + T1HI + 0x2C + 0x20 + + + HI + Register to store timer 1 time-base counter current value higher 32 bits. + 0 + 32 + read-only + + + + + T1UPDATE + 0x30 + 0x20 + + + UPDATE + Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above) + 0 + 32 + write-only + + + + + T1ALARMLO + 0x34 + 0x20 + + + ALARM_LO + Timer 1 time-base counter value lower 32 bits that will trigger the alarm + 0 + 32 + read-write + + + + + T1ALARMHI + 0x38 + 0x20 + + + ALARM_HI + Timer 1 time-base counter value higher 32 bits that will trigger the alarm + 0 + 32 + read-write + + + + + T1LOADLO + 0x3C + 0x20 + + + LOAD_LO + Lower 32 bits of the value that will load into timer 1 time-base counter + 0 + 32 + read-write + + + + + T1LOADHI + 0x40 + 0x20 + + + LOAD_HI + higher 32 bits of the value that will load into timer 1 time-base counter + 0 + 32 + read-write + + + + + T1LOAD + 0x44 + 0x20 + + + LOAD + Write any value will trigger timer 1 time-base counter reload + 0 + 32 + write-only + + + + + WDTCONFIG0 + 0x48 + 0x20 + 0x0004C000 + + + WDT_FLASHBOOT_MOD_EN + When set flash boot protection is enabled + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us + 15 + 3 + read-write + + WDT_SYS_RESET_LENGTH + read-write + + NS100 + 100ns + 0 + + + NS200 + 200ns + 1 + + + NS300 + 300ns + 2 + + + NS400 + 400ns + 3 + + + NS500 + 500ns + 4 + + + NS800 + 800ns + 5 + + + NS1600 + 1.6us + 6 + + + NS3200 + 3.2us + 7 + + + + + WDT_CPU_RESET_LENGTH + length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us + 18 + 3 + read-write + + WDT_CPU_RESET_LENGTH + read-write + + NS100 + 100ns + 0 + + + NS200 + 200ns + 1 + + + NS300 + 300ns + 2 + + + NS400 + 400ns + 3 + + + NS500 + 500ns + 4 + + + NS800 + 800ns + 5 + + + NS1600 + 1.6us + 6 + + + NS3200 + 3.2us + 7 + + + + + WDT_LEVEL_INT_EN + When set level type interrupt generation is enabled + 21 + 1 + read-write + + + WDT_EDGE_INT_EN + When set edge type interrupt generation is enabled + 22 + 1 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system + 23 + 2 + read-write + + WDT_STG3 + read-write + + OFF + Off + 0 + + + INTERRUPT + Interrupt + 1 + + + RESET + Reset CPU + 2 + + + RESET_SYS + Reset system + 3 + + + + + WDT_STG2 + Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system + 25 + 2 + read-write + + + + WDT_STG1 + Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system + 27 + 2 + read-write + + + + WDT_STG0 + Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system + 29 + 2 + read-write + + + + WDT_EN + When set SWDT is enabled + 31 + 1 + read-write + + + + + WDTCONFIG1 + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + SWDT clock prescale value. Period = 12.5ns * value stored in this register + 16 + 16 + read-write + + + + + WDTCONFIG2 + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value in SWDT clock cycles + 0 + 32 + read-write + + + + + WDTCONFIG3 + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value in SWDT clock cycles + 0 + 32 + read-write + + + + + WDTCONFIG4 + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value in SWDT clock cycles + 0 + 32 + read-write + + + + + WDTCONFIG5 + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value in SWDT clock cycles + 0 + 32 + read-write + + + + + WDTFEED + 0x60 + 0x20 + + + WDT_FEED + Write any value will feed SWDT + 0 + 32 + write-only + + + + + WDTWPROTECT + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If change its value from default then write protection is on. + 0 + 32 + read-write + + + + + RTCCALICFG + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 13 + 2 + read-write + + + RTC_CALI_RDY + 15 + 1 + read-only + + + RTC_CALI_MAX + 16 + 15 + read-write + + + RTC_CALI_START + 31 + 1 + read-write + + + + + RTCCALICFG1 + 0x6C + 0x20 + + + RTC_CALI_VALUE + 7 + 25 + read-only + + + + + LACTCONFIG + 0x70 + 0x20 + 0x60002300 + + + LACT_RTC_ONLY + 7 + 1 + read-write + + + LACT_CPST_EN + 8 + 1 + read-write + + + LACT_LAC_EN + 9 + 1 + read-write + + + LACT_ALARM_EN + 10 + 1 + read-write + + + LACT_LEVEL_INT_EN + 11 + 1 + read-write + + + LACT_EDGE_INT_EN + 12 + 1 + read-write + + + LACT_DIVIDER + 13 + 16 + read-write + + + LACT_AUTORELOAD + 29 + 1 + read-write + + + LACT_INCREASE + 30 + 1 + read-write + + + LACT_EN + 31 + 1 + read-write + + + + + LACTRTC + 0x74 + 0x20 + + + LACT_RTC_STEP_LEN + 6 + 26 + read-write + + + + + LACTLO + 0x78 + 0x20 + + + LACT_LO + 0 + 32 + read-only + + + + + LACTHI + 0x7C + 0x20 + + + LACT_HI + 0 + 32 + read-only + + + + + LACTUPDATE + 0x80 + 0x20 + + + LACT_UPDATE + 0 + 32 + write-only + + + + + LACTALARMLO + 0x84 + 0x20 + + + LACT_ALARM_LO + 0 + 32 + read-write + + + + + LACTALARMHI + 0x88 + 0x20 + + + LACT_ALARM_HI + 0 + 32 + read-write + + + + + LACTLOADLO + 0x8C + 0x20 + + + LACT_LOAD_LO + 0 + 32 + read-write + + + + + LACTLOADHI + 0x90 + 0x20 + + + LACT_LOAD_HI + 0 + 32 + read-write + + + + + LACTLOAD + 0x94 + 0x20 + + + LACT_LOAD + 0 + 32 + write-only + + + + + INT_ENA_TIMERS + 0x98 + 0x20 + + + T0_INT_ENA + interrupt when timer0 alarm + 0 + 1 + read-write + + + T1_INT_ENA + interrupt when timer1 alarm + 1 + 1 + read-write + + + WDT_INT_ENA + Interrupt when an interrupt stage timeout + 2 + 1 + read-write + + + LACT_INT_ENA + 3 + 1 + read-write + + + + + INT_RAW_TIMERS + 0x9C + 0x20 + + + T0_INT_RAW + interrupt when timer0 alarm + 0 + 1 + read-only + + + T1_INT_RAW + interrupt when timer1 alarm + 1 + 1 + read-only + + + WDT_INT_RAW + Interrupt when an interrupt stage timeout + 2 + 1 + read-only + + + LACT_INT_RAW + 3 + 1 + read-only + + + + + INT_ST_TIMERS + 0xA0 + 0x20 + + + T0_INT_ST + interrupt when timer0 alarm + 0 + 1 + read-only + + + T1_INT_ST + interrupt when timer1 alarm + 1 + 1 + read-only + + + WDT_INT_ST + Interrupt when an interrupt stage timeout + 2 + 1 + read-only + + + LACT_INT_ST + 3 + 1 + read-only + + + + + INT_CLR_TIMERS + 0xA4 + 0x20 + + + T0_INT_CLR + interrupt when timer0 alarm + 0 + 1 + write-only + + + T1_INT_CLR + interrupt when timer1 alarm + 1 + 1 + write-only + + + WDT_INT_CLR + Interrupt when an interrupt stage timeout + 2 + 1 + write-only + + + LACT_INT_CLR + 3 + 1 + write-only + + + + + NTIMERS_DATE + 0xF8 + 0x20 + 0x01604290 + + + NTIMERS_DATE + Version of this regfile + 0 + 28 + read-write + + + + + TIMGCLK + 0xFC + 0x20 + + + CLK_EN + Force clock enable for this regfile + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x3FF60000 + + TG1_T0_LEVEL + 18 + + + TG1_T1_LEVEL + 19 + + + TG1_WDT_LEVEL + 20 + + + TG1_LACT_LEVEL + 21 + + + TG1_T0_EDGE + 62 + + + TG1_T1_EDGE + 63 + + + TG1_WDT_EDGE + 64 + + + TG1_LACT_EDGE + 65 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x3FF6B000 + + 0x0 + 0x6C + registers + + + TWAI + 45 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x3FF40000 + + 0x0 + 0x7C + registers + + + UART0 + 34 + + + + FIFO + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + This register stores one byte data read by rx fifo. + 0 + 8 + read-write + + + + + INT_RAW + 0x4 + 0x20 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd). + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects the parity error of data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects data's frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the fifo can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter's fifo are send. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send all the data in fifo. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when rs485 detects the parity error. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when rs485 detects the data frame error. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars. + 18 + 1 + read-only + + + + + INT_ST + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + + + INT_ENA + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + + + INT_CLR + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + + + CLKDIV + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The register value is the integer part of the frequency divider's factor. + 0 + 20 + read-write + + + FRAG + The register value is the decimal part of the frequency divider's factor. + 20 + 4 + read-write + + + + + AUTOBAUD + 0x18 + 0x20 + 0x00001000 + + + EN + This is the enable bit for detecting baudrate. + 0 + 1 + read-write + + + GLITCH_FILT + when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process. + 8 + 8 + read-write + + + + + STATUS + 0x1C + 0x20 + + + RXFIFO_CNT + (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits. + 0 + 8 + read-only + + + ST_URX_OUT + This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1 + 8 + 4 + read-only + + + DSRN + This register stores the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register stores the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register stores the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits. + 16 + 8 + read-only + + + ST_UTX_OUT + This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1 + 24 + 4 + read-only + + + DTRN + The register represent the level value of the internal uart dsr signal. + 29 + 1 + read-only + + + RTSN + This register represent the level value of the internal uart cts signal. + 30 + 1 + read-only + + + TXD + This register represent the level value of the internal uart rxd signal. + 31 + 1 + read-only + + + + + CONF0 + 0x20 + 0x20 + 0x0800001C + + + PARITY + This register is used to configure the parity check mode. 0:even 1:odd + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control.. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send 0 when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable irda loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for irda transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to inverse the level value of irda transmitter's level. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to inverse the level value of irda receiver's level. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable transmitter's flow control function. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable irda protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset uart receiver's fifo. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset uart transmitter's fifo. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1.force clock on for registers.support clock only when write registers + 25 + 1 + read-write + + + ERR_WR_MASK + 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + TICK_REF_ALWAYS_ON + This register is used to select the clock.1.apb clock 0:ref_tick + 27 + 1 + read-write + + + + + CONF1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd). + 0 + 7 + read-write + + + TXFIFO_EMPTY_THRHD + when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd) + 8 + 7 + read-write + + + RX_FLOW_THRHD + when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd). + 16 + 7 + read-write + + + RX_FLOW_EN + This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal + 23 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the timeout value for uart receiver receiving a byte. + 24 + 7 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 31 + 1 + read-write + + + + + LOWPULSE + 0x28 + 0x20 + 0x000FFFFF + + + MIN_CNT + This register stores the value of the minimum duration time for the low level pulse. it is used in baudrate-detect process. + 0 + 20 + read-only + + + + + HIGHPULSE + 0x2C + 0x20 + 0x000FFFFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. it is used in baudrate-detect process. + 0 + 20 + read-only + + + + + RXD_CNT + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. it is used in baudrate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff . + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to clear ctsn to stop the transmitter from sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to set ctsn to enable the transmitter to go on sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send xon char. it is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send xoff char. it is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + When the input rxd edge changes more than this register value. the uart is active from light sleeping mode. + 0 + 10 + read-write + + + + + SWFC_CONF + 0x3C + 0x20 + 0x1311E000 + + + XON_THRESHOLD + when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1. + 8 + 8 + read-write + + + XON_CHAR + This register stores the xon flow control char. + 16 + 8 + read-write + + + XOFF_CHAR + This register stores the xoff flow control char. + 24 + 8 + read-write + + + + + IDLE_CONF + 0x40 + 0x20 + 0x00A40100 + + + RX_IDLE_THRHD + when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + TX_BRK_NUM + This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1. + 20 + 8 + read-write + + + + + RS485_CONF + 0x44 + 0x20 + + + RS485_EN + Set this bit to choose rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable loopback transmitter's output data signal to receiver's input data signal. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + 0x48 + 0x20 + 0x00186A00 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char. + 0 + 24 + read-write + + + + + AT_CMD_POSTCNT + 0x4C + 0x20 + 0x00186A00 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char. + 0 + 24 + read-write + + + + + AT_CMD_GAPTOUT + 0x50 + 0x20 + 0x00001E00 + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars. + 0 + 24 + read-write + + + + + AT_CMD_CHAR + 0x54 + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + 0x58 + 0x20 + 0x00000088 + + + MEM_PD + Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode. + 0 + 1 + read-write + + + RX_SIZE + This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128. + 3 + 4 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128. + 7 + 4 + read-write + + + RX_FLOW_THRHD_H3 + refer to the rx_flow_thrhd's describtion. + 15 + 3 + read-write + + + RX_TOUT_THRHD_H3 + refer to the rx_tout_thrhd's describtion. + 18 + 3 + read-write + + + XON_THRESHOLD_H2 + refer to the uart_xon_threshold's describtion. + 21 + 2 + read-write + + + XOFF_THRESHOLD_H2 + refer to the uart_xoff_threshold's describtion. + 23 + 2 + read-write + + + RX_MEM_FULL_THRHD + refer to the rxfifo_full_thrhd's describtion. + 25 + 3 + read-write + + + TX_MEM_EMPTY_THRHD + refer to txfifo_empty_thrhd 's describtion. + 28 + 3 + read-write + + + + + MEM_TX_STATUS + 0x5C + 0x20 + + + MEM_TX_STATUS + 0 + 24 + read-only + + + + + MEM_RX_STATUS + 0x60 + 0x20 + + + MEM_RX_STATUS + This register stores the current uart rx mem read address and rx mem write address + 0 + 24 + read-only + + + MEM_RX_RD_ADDR + This register stores the rx mem read address + 2 + 11 + read-only + + + MEM_RX_WR_ADDR + This register stores the rx mem write address + 13 + 11 + read-only + + + + + MEM_CNT_STATUS + 0x64 + 0x20 + + + RX_MEM_CNT + refer to the rxfifo_cnt's describtion. + 0 + 3 + read-only + + + TX_MEM_CNT + refer to the txfifo_cnt's describtion. + 3 + 3 + read-only + + + + + POSPULSE + 0x68 + 0x20 + 0x000FFFFF + + + POSEDGE_MIN_CNT + This register stores the count of rxd posedge edge. it is used in boudrate-detect process. + 0 + 20 + read-only + + + + + NEGPULSE + 0x6C + 0x20 + 0x000FFFFF + + + NEGEDGE_MIN_CNT + This register stores the count of rxd negedge edge. it is used in boudrate-detect process. + 0 + 20 + read-only + + + + + DATE + 0x78 + 0x20 + 0x15122500 + + + DATE + 0 + 32 + read-write + + + + + ID + 0x7C + 0x20 + 0x00000500 + + + ID + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x3FF50000 + + UART1 + 35 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x3FF6E000 + + UART2 + 36 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x3FF54000 + + 0x0 + 0xC8 + registers + + + UHCI0 + 12 + + + + CONF0 + 0x0 + 0x20 + 0x00370100 + + + IN_RST + Set this bit to reset in link operations. + 0 + 1 + read-write + + + OUT_RST + Set this bit to reset out link operations. + 1 + 1 + read-write + + + AHBM_FIFO_RST + Set this bit to reset dma ahb fifo. + 2 + 1 + read-write + + + AHBM_RST + Set this bit to reset dma ahb interface. + 3 + 1 + read-write + + + IN_LOOP_TEST + Set this bit to enable loop test for in links. + 4 + 1 + read-write + + + OUT_LOOP_TEST + Set this bit to enable loop test for out links. + 5 + 1 + read-write + + + OUT_AUTO_WRBACK + when in link's length is 0 go on to use the next in link automatically. + 6 + 1 + read-write + + + OUT_NO_RESTART_CLR + don't use + 7 + 1 + read-write + + + OUT_EOF_MODE + Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data + 8 + 1 + read-write + + + UART0_CE + Set this bit to use UART to transmit or receive data. + 9 + 1 + read-write + + + UART1_CE + Set this bit to use UART1 to transmit or receive data. + 10 + 1 + read-write + + + UART2_CE + Set this bit to use UART2 to transmit or receive data. + 11 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to enable DMA in links to use burst mode. + 12 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to enable DMA out links to use burst mode. + 13 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to enable DMA burst MODE + 14 + 1 + read-write + + + MEM_TRANS_EN + 15 + 1 + read-write + + + SEPER_EN + Set this bit to use special char to separate the data frame. + 16 + 1 + read-write + + + HEAD_EN + Set this bit to enable to use head packet before the data frame. + 17 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame + 18 + 1 + read-write + + + UART_IDLE_EOF_EN + Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame. + 19 + 1 + read-write + + + LEN_EOF_EN + Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame. + 20 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1. + 21 + 1 + read-write + + + CLK_EN + Set this bit to enable clock-gating for read or write registers. + 22 + 1 + read-write + + + UART_RX_BRK_EOF_EN + Set this bit to enable to use brk char as the end of a data frame. + 23 + 1 + read-write + + + + + INT_RAW + 0x4 + 0x20 + + + RX_START_INT_RAW + when a separator char has been send it will produce uhci_rx_start_int interrupt. + 0 + 1 + read-only + + + TX_START_INT_RAW + when DMA detects a separator char it will produce uhci_tx_start_int interrupt. + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt. + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt. + 3 + 1 + read-only + + + IN_DONE_INT_RAW + when a in link descriptor has been completed it will produce uhci_in_done_int interrupt. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + when a data packet has been received it will produce uhci_in_suc_eof_int interrupt. + 5 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt. + 6 + 1 + read-only + + + OUT_DONE_INT_RAW + when a out link descriptor is completed it will produce uhci_out_done_int interrupt. + 7 + 1 + read-only + + + OUT_EOF_INT_RAW + when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt. + 8 + 1 + read-only + + + IN_DSCR_ERR_INT_RAW + when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt. + 9 + 1 + read-only + + + OUT_DSCR_ERR_INT_RAW + when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt. + 10 + 1 + read-only + + + IN_DSCR_EMPTY_INT_RAW + when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt. + 11 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_RAW + when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt. + 12 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + When all data have been send it will produce uhci_out_total_eof_int interrupt. + 13 + 1 + read-only + + + SEND_S_Q_INT_RAW + When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet. + 14 + 1 + read-only + + + SEND_A_Q_INT_RAW + When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet. + 15 + 1 + read-only + + + DMA_INFIFO_FULL_WM_INT_RAW + 16 + 1 + read-only + + + + + INT_ST + 0x8 + 0x20 + + + RX_START_INT_ST + 0 + 1 + read-only + + + TX_START_INT_ST + 1 + 1 + read-only + + + RX_HUNG_INT_ST + 2 + 1 + read-only + + + TX_HUNG_INT_ST + 3 + 1 + read-only + + + IN_DONE_INT_ST + 4 + 1 + read-only + + + IN_SUC_EOF_INT_ST + 5 + 1 + read-only + + + IN_ERR_EOF_INT_ST + 6 + 1 + read-only + + + OUT_DONE_INT_ST + 7 + 1 + read-only + + + OUT_EOF_INT_ST + 8 + 1 + read-only + + + IN_DSCR_ERR_INT_ST + 9 + 1 + read-only + + + OUT_DSCR_ERR_INT_ST + 10 + 1 + read-only + + + IN_DSCR_EMPTY_INT_ST + 11 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + 12 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + 13 + 1 + read-only + + + SEND_S_Q_INT_ST + 14 + 1 + read-only + + + SEND_A_Q_INT_ST + 15 + 1 + read-only + + + DMA_INFIFO_FULL_WM_INT_ST + 16 + 1 + read-only + + + + + INT_ENA + 0xC + 0x20 + + + RX_START_INT_ENA + 0 + 1 + read-write + + + TX_START_INT_ENA + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + 3 + 1 + read-write + + + IN_DONE_INT_ENA + 4 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + 5 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + 6 + 1 + read-write + + + OUT_DONE_INT_ENA + 7 + 1 + read-write + + + OUT_EOF_INT_ENA + 8 + 1 + read-write + + + IN_DSCR_ERR_INT_ENA + 9 + 1 + read-write + + + OUT_DSCR_ERR_INT_ENA + 10 + 1 + read-write + + + IN_DSCR_EMPTY_INT_ENA + 11 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + 12 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + 13 + 1 + read-write + + + SEND_S_Q_INT_ENA + 14 + 1 + read-write + + + SEND_A_Q_INT_ENA + 15 + 1 + read-write + + + DMA_INFIFO_FULL_WM_INT_ENA + 16 + 1 + read-write + + + + + INT_CLR + 0x10 + 0x20 + + + RX_START_INT_CLR + 0 + 1 + write-only + + + TX_START_INT_CLR + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + 3 + 1 + write-only + + + IN_DONE_INT_CLR + 4 + 1 + write-only + + + IN_SUC_EOF_INT_CLR + 5 + 1 + write-only + + + IN_ERR_EOF_INT_CLR + 6 + 1 + write-only + + + OUT_DONE_INT_CLR + 7 + 1 + write-only + + + OUT_EOF_INT_CLR + 8 + 1 + write-only + + + IN_DSCR_ERR_INT_CLR + 9 + 1 + write-only + + + OUT_DSCR_ERR_INT_CLR + 10 + 1 + write-only + + + IN_DSCR_EMPTY_INT_CLR + 11 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + 12 + 1 + write-only + + + OUT_TOTAL_EOF_INT_CLR + 13 + 1 + write-only + + + SEND_S_Q_INT_CLR + 14 + 1 + write-only + + + SEND_A_Q_INT_CLR + 15 + 1 + write-only + + + DMA_INFIFO_FULL_WM_INT_CLR + 16 + 1 + write-only + + + + + DMA_OUT_STATUS + 0x14 + 0x20 + 0x00000002 + + + OUT_FULL + 1:DMA out link descriptor's fifo is full. + 0 + 1 + read-only + + + OUT_EMPTY + 1:DMA in link descriptor's fifo is empty. + 1 + 1 + read-only + + + + + DMA_OUT_PUSH + 0x18 + 0x20 + + + OUTFIFO_WDATA + This is the data need to be pushed into out link descriptor's fifo. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data in out link descriptor's fifo. + 16 + 1 + read-write + + + + + DMA_IN_STATUS + 0x1C + 0x20 + 0x00000002 + + + IN_FULL + 0 + 1 + read-only + + + IN_EMPTY + 1 + 1 + read-only + + + RX_ERR_CAUSE + This register stores the errors caused in out link descriptor's data packet. + 4 + 3 + read-only + + + + + DMA_IN_POP + 0x20 + 0x20 + + + INFIFO_RDATA + This register stores the data pop from in link descriptor's fifo. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data in in link descriptor's fifo. + 16 + 1 + read-write + + + + + DMA_OUT_LINK + 0x24 + 0x20 + + + OUTLINK_ADDR + This register stores the least 20 bits of the first out link descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the out link descriptors. + 28 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the out link descriptors. + 29 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to mount on new out link descriptors + 30 + 1 + read-write + + + OUTLINK_PARK + 1£º the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working. + 31 + 1 + read-only + + + + + DMA_IN_LINK + 0x28 + 0x20 + 0x00100000 + + + INLINK_ADDR + This register stores the least 20 bits of the first in link descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + 1:when a packet is wrong in link descriptor returns to the descriptor which is lately used. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the in link descriptors. + 28 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the in link descriptors. + 29 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount on new in link descriptors + 30 + 1 + read-write + + + INLINK_PARK + 1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working + 31 + 1 + read-only + + + + + CONF1 + 0x2C + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable decoder to check check_sum in packet header. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable decoder to check seq num in packet header. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to disable crc calculation. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save packet header . + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to enable hardware replace check_sum in packet header automatically. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to enable hardware replace ack num in packet header automatically. + 5 + 1 + read-write + + + CHECK_OWNER + Set this bit to check the owner bit in link descriptor. + 6 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable software way to add packet header. + 7 + 1 + read-write + + + SW_START + Set this bit to start inserting the packet header. + 8 + 1 + read-write + + + DMA_INFIFO_FULL_THRS + when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt. + 9 + 12 + read-write + + + + + STATE0 + 0x30 + 0x20 + + + STATE0 + 0 + 32 + read-only + + + + + STATE1 + 0x34 + 0x20 + + + STATE1 + 0 + 32 + read-only + + + + + DMA_OUT_EOF_DES_ADDR + 0x38 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of out link descriptoir when eof bit in this descriptor is 1. + 0 + 32 + read-only + + + + + DMA_IN_SUC_EOF_DES_ADDR + 0x3C + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of in link descriptor when eof bit in this descriptor is 1. + 0 + 32 + read-only + + + + + DMA_IN_ERR_EOF_DES_ADDR + 0x40 + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of in link descriptor when there are some errors in this descriptor. + 0 + 32 + read-only + + + + + DMA_OUT_EOF_BFR_DES_ADDR + 0x44 + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of out link descriptor when there are some errors in this descriptor. + 0 + 32 + read-only + + + + + AHB_TEST + 0x48 + 0x20 + + + AHB_TESTMODE + bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0) + 0 + 3 + read-write + + + AHB_TESTADDR + The two bits represent ahb bus address bit[20:19] + 4 + 2 + read-write + + + + + DMA_IN_DSCR + 0x4C + 0x20 + + + INLINK_DSCR + The content of current in link descriptor's third dword + 0 + 32 + read-only + + + + + DMA_IN_DSCR_BF0 + 0x50 + 0x20 + + + INLINK_DSCR_BF0 + The content of current in link descriptor's first dword + 0 + 32 + read-only + + + + + DMA_IN_DSCR_BF1 + 0x54 + 0x20 + + + INLINK_DSCR_BF1 + The content of current in link descriptor's second dword + 0 + 32 + read-only + + + + + DMA_OUT_DSCR + 0x58 + 0x20 + + + OUTLINK_DSCR + The content of current out link descriptor's third dword + 0 + 32 + read-only + + + + + DMA_OUT_DSCR_BF0 + 0x5C + 0x20 + + + OUTLINK_DSCR_BF0 + The content of current out link descriptor's first dword + 0 + 32 + read-only + + + + + DMA_OUT_DSCR_BF1 + 0x60 + 0x20 + + + OUTLINK_DSCR_BF1 + The content of current out link descriptor's second dword + 0 + 32 + read-only + + + + + ESCAPE_CONF + 0x64 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable 0xc0 char decode when DMA receives data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable 0xdb char decode when DMA receives data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable flow control char 0x11 decode when DMA receives data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable flow control char 0x13 decode when DMA receives data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable 0xc0 char replace when DMA sends data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable 0xdb char replace when DMA sends data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable flow control char 0x11 replace when DMA sends data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable flow control char 0x13 replace when DMA sends data. + 7 + 1 + read-write + + + + + HUNG_CONF + 0x68 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift) + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + The enable bit for txfifo receive data timeout + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift) + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send data timeout + 23 + 1 + read-write + + + + + ACK_NUM + 0x6C + 0x20 + + + RX_HEAD + 0x70 + 0x20 + + + RX_HEAD + This register stores the packet header received by DMA + 0 + 32 + read-only + + + + + QUICK_SENT + 0x74 + 0x20 + + + SINGLE_SEND_NUM + The bits are used to choose which short packet + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable send a short packet + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + The bits are used to choose which short packet + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable continuously send the same short packet + 7 + 1 + read-write + + + + + Q0_WORD0 + 0x78 + 0x20 + + + SEND_Q0_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q0_WORD1 + 0x7C + 0x20 + + + SEND_Q0_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q1_WORD0 + 0x80 + 0x20 + + + SEND_Q1_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q1_WORD1 + 0x84 + 0x20 + + + SEND_Q1_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q2_WORD0 + 0x88 + 0x20 + + + SEND_Q2_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q2_WORD1 + 0x8C + 0x20 + + + SEND_Q2_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q3_WORD0 + 0x90 + 0x20 + + + SEND_Q3_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q3_WORD1 + 0x94 + 0x20 + + + SEND_Q3_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q4_WORD0 + 0x98 + 0x20 + + + SEND_Q4_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q4_WORD1 + 0x9C + 0x20 + + + SEND_Q4_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q5_WORD0 + 0xA0 + 0x20 + + + SEND_Q5_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q5_WORD1 + 0xA4 + 0x20 + + + SEND_Q5_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + Q6_WORD0 + 0xA8 + 0x20 + + + SEND_Q6_WORD0 + This register stores the content of short packet's first dword + 0 + 32 + read-write + + + + + Q6_WORD1 + 0xAC + 0x20 + + + SEND_Q6_WORD1 + This register stores the content of short packet's second dword + 0 + 32 + read-write + + + + + ESC_CONF0 + 0xB0 + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + This register stores the seperator char seperator char is used to seperate the data frame. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + This register stores thee first char used to replace seperator char in data. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default. + 16 + 8 + read-write + + + + + ESC_CONF1 + 0xB4 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + This register stores the first substitute char used to replace the seperator char. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + This register stores the first char used to replace reg_esc_seq0 in data. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + This register stores the second char used to replace the reg_esc_seq0 in data + 16 + 8 + read-write + + + + + ESC_CONF2 + 0xB8 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + This register stores the flow control char to turn on the flow_control + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + This register stores the first char used to replace the reg_esc_seq1 in data. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + This register stores the second char used to replace the reg_esc_seq1 in data. + 16 + 8 + read-write + + + + + ESC_CONF3 + 0xBC + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + This register stores the flow_control char to turn off the flow_control + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + This register stores the first char used to replace the reg_esc_seq2 in data. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + This register stores the second char used to replace the reg_esc_seq2 in data. + 16 + 8 + read-write + + + + + PKT_THRES + 0xC0 + 0x20 + 0x00000080 + + + PKT_THRS + when the amount of packet payload is greater than this value the process of receiving data is done. + 0 + 13 + read-write + + + + + DATE + 0xFC + 0x20 + 0x16041001 + + + DATE + version information + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface + 0x3FF4C000 + + UHCI1 + 13 + + + + diff --git a/tools/ide-debug/svd/esp32c2.svd b/tools/ide-debug/svd/esp32c2.svd new file mode 100644 index 0000000..84aa455 --- /dev/null +++ b/tools/ide-debug/svd/esp32c2.svd @@ -0,0 +1,20749 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-C2 + ESP32-C2 + 4 + 32-bit RISC-V MCU + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + APB_CTRL + Advanced Peripheral Bus Controller + APB_CTRL + 0x60026000 + + 0x0 + 0xA0 + registers + + + APB_CTRL + 12 + + + + SYSCLK_CONF + APB_CTRL_SYSCLK_CONF_REG + 0x0 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + reg_pre_div_cnt + 0 + 10 + read-write + + + CLK_320M_EN + reg_clk_320m_en + 10 + 1 + read-write + + + CLK_EN + reg_clk_en + 11 + 1 + read-write + + + RST_TICK_CNT + reg_rst_tick_cnt + 12 + 1 + read-write + + + + + TICK_CONF + APB_CTRL_TICK_CONF_REG + 0x4 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + reg_xtal_tick_num + 0 + 8 + read-write + + + CK8M_TICK_NUM + reg_ck8m_tick_num + 8 + 8 + read-write + + + TICK_ENABLE + reg_tick_enable + 16 + 1 + read-write + + + + + CLK_OUT_EN + APB_CTRL_CLK_OUT_EN_REG + 0x8 + 0x20 + 0x000007FF + + + CLK20_OEN + reg_clk20_oen + 0 + 1 + read-write + + + CLK22_OEN + reg_clk22_oen + 1 + 1 + read-write + + + CLK44_OEN + reg_clk44_oen + 2 + 1 + read-write + + + CLK_BB_OEN + reg_clk_bb_oen + 3 + 1 + read-write + + + CLK80_OEN + reg_clk80_oen + 4 + 1 + read-write + + + CLK160_OEN + reg_clk160_oen + 5 + 1 + read-write + + + CLK_320M_OEN + reg_clk_320m_oen + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + reg_clk_adc_inf_oen + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + reg_clk_dac_cpu_oen + 8 + 1 + read-write + + + CLK40X_BB_OEN + reg_clk40x_bb_oen + 9 + 1 + read-write + + + CLK_XTAL_OEN + reg_clk_xtal_oen + 10 + 1 + read-write + + + + + WIFI_BB_CFG + APB_CTRL_WIFI_BB_CFG_REG + 0xC + 0x20 + + + WIFI_BB_CFG + reg_wifi_bb_cfg + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + APB_CTRL_WIFI_BB_CFG_2_REG + 0x10 + 0x20 + + + WIFI_BB_CFG_2 + reg_wifi_bb_cfg_2 + 0 + 32 + read-write + + + + + WIFI_CLK_EN + APB_CTRL_WIFI_CLK_EN_REG + 0x14 + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + reg_wifi_clk_en + 0 + 32 + read-write + + + + + WIFI_RST_EN + APB_CTRL_WIFI_RST_EN_REG + 0x18 + 0x20 + + + WIFI_RST + reg_wifi_rst + 0 + 32 + read-write + + + + + HOST_INF_SEL + APB_CTRL_HOST_INF_SEL_REG + 0x1C + 0x20 + + + PERI_IO_SWAP + reg_peri_io_swap + 0 + 8 + read-write + + + + + EXT_MEM_PMS_LOCK + APB_CTRL_EXT_MEM_PMS_LOCK_REG + 0x20 + 0x20 + + + EXT_MEM_PMS_LOCK + reg_ext_mem_pms_lock + 0 + 1 + read-write + + + + + FLASH_ACE0_ATTR + APB_CTRL_FLASH_ACE0_ATTR_REG + 0x28 + 0x20 + 0x00000003 + + + FLASH_ACE0_ATTR + reg_flash_ace0_attr + 0 + 2 + read-write + + + + + FLASH_ACE1_ATTR + APB_CTRL_FLASH_ACE1_ATTR_REG + 0x2C + 0x20 + 0x00000003 + + + FLASH_ACE1_ATTR + reg_flash_ace1_attr + 0 + 2 + read-write + + + + + FLASH_ACE2_ATTR + APB_CTRL_FLASH_ACE2_ATTR_REG + 0x30 + 0x20 + 0x00000003 + + + FLASH_ACE2_ATTR + reg_flash_ace2_attr + 0 + 2 + read-write + + + + + FLASH_ACE3_ATTR + APB_CTRL_FLASH_ACE3_ATTR_REG + 0x34 + 0x20 + 0x00000003 + + + FLASH_ACE3_ATTR + reg_flash_ace3_attr + 0 + 2 + read-write + + + + + FLASH_ACE0_ADDR + APB_CTRL_FLASH_ACE0_ADDR_REG + 0x38 + 0x20 + + + S + reg_flash_ace0_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE1_ADDR + APB_CTRL_FLASH_ACE1_ADDR_REG + 0x3C + 0x20 + 0x00400000 + + + S + reg_flash_ace1_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE2_ADDR + APB_CTRL_FLASH_ACE2_ADDR_REG + 0x40 + 0x20 + 0x00800000 + + + S + reg_flash_ace2_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE3_ADDR + APB_CTRL_FLASH_ACE3_ADDR_REG + 0x44 + 0x20 + 0x00C00000 + + + S + reg_flash_ace3_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE0_SIZE + APB_CTRL_FLASH_ACE0_SIZE_REG + 0x48 + 0x20 + 0x00000400 + + + FLASH_ACE0_SIZE + reg_flash_ace0_size + 0 + 13 + read-write + + + + + FLASH_ACE1_SIZE + APB_CTRL_FLASH_ACE1_SIZE_REG + 0x4C + 0x20 + 0x00000400 + + + FLASH_ACE1_SIZE + reg_flash_ace1_size + 0 + 13 + read-write + + + + + FLASH_ACE2_SIZE + APB_CTRL_FLASH_ACE2_SIZE_REG + 0x50 + 0x20 + 0x00000400 + + + FLASH_ACE2_SIZE + reg_flash_ace2_size + 0 + 13 + read-write + + + + + FLASH_ACE3_SIZE + APB_CTRL_FLASH_ACE3_SIZE_REG + 0x54 + 0x20 + 0x00000400 + + + FLASH_ACE3_SIZE + reg_flash_ace3_size + 0 + 13 + read-write + + + + + SPI_MEM_PMS_CTRL + APB_CTRL_SPI_MEM_PMS_CTRL_REG + 0x88 + 0x20 + + + SPI_MEM_REJECT_INT + reg_spi_mem_reject_int + 0 + 1 + read-only + + + SPI_MEM_REJECT_CLR + reg_spi_mem_reject_clr + 1 + 1 + write-only + + + SPI_MEM_REJECT_CDE + reg_spi_mem_reject_cde + 2 + 5 + read-only + + + + + SPI_MEM_REJECT_ADDR + APB_CTRL_SPI_MEM_REJECT_ADDR_REG + 0x8C + 0x20 + + + SPI_MEM_REJECT_ADDR + reg_spi_mem_reject_addr + 0 + 32 + read-only + + + + + SDIO_CTRL + APB_CTRL_SDIO_CTRL_REG + 0x90 + 0x20 + + + SDIO_WIN_ACCESS_EN + reg_sdio_win_access_en + 0 + 1 + read-write + + + + + REDCY_SIG0_REG + APB_CTRL_REDCY_SIG0_REG_REG + 0x94 + 0x20 + + + REDCY_SIG0 + reg_redcy_sig0 + 0 + 31 + read-write + + + REDCY_ANDOR + reg_redcy_andor + 31 + 1 + read-only + + + + + REDCY_SIG1_REG + APB_CTRL_REDCY_SIG1_REG_REG + 0x98 + 0x20 + + + REDCY_SIG1 + reg_redcy_sig1 + 0 + 31 + read-write + + + REDCY_NANDOR + reg_redcy_nandor + 31 + 1 + read-only + + + + + FRONT_END_MEM_PD + APB_CTRL_FRONT_END_MEM_PD_REG + 0x9C + 0x20 + 0x00000055 + + + AGC_MEM_FORCE_PU + reg_agc_mem_force_pu + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + reg_agc_mem_force_pd + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + reg_pbus_mem_force_pu + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + reg_pbus_mem_force_pd + 3 + 1 + read-write + + + DC_MEM_FORCE_PU + reg_dc_mem_force_pu + 4 + 1 + read-write + + + DC_MEM_FORCE_PD + reg_dc_mem_force_pd + 5 + 1 + read-write + + + FREQ_MEM_FORCE_PU + reg_freq_mem_force_pu + 6 + 1 + read-write + + + FREQ_MEM_FORCE_PD + reg_freq_mem_force_pd + 7 + 1 + read-write + + + + + RETENTION_CTRL + APB_CTRL_RETENTION_CTRL_REG + 0xA0 + 0x20 + + + RETENTION_LINK_ADDR + reg_retention_link_addr + 0 + 27 + read-write + + + NOBYPASS_CPU_ISO_RST + reg_nobypass_cpu_iso_rst + 27 + 1 + read-write + + + + + CLKGATE_FORCE_ON + Memory power configuration registers + 0xA4 + 0x20 + 0x0000007F + + + ROM_CLKGATE_FORCE_ON + Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock + 0 + 3 + read-write + + + SRAM_CLKGATE_FORCE_ON + Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock + 3 + 4 + read-write + + + + + MEM_POWER_DOWN + Memory power configuration registers + 0xA8 + 0x20 + 0x0000007F + + + ROM_POWER_DOWN + Set 1 to let rom power down + 0 + 3 + read-write + + + SRAM_POWER_DOWN + Set 1 to let sram power down + 3 + 4 + read-write + + + + + MEM_POWER_UP + Memory power configuration registers + 0xAC + 0x20 + 0x0000007F + + + ROM_POWER_UP + Set 1 to let rom power up + 0 + 3 + read-write + + + SRAM_POWER_UP + Set 1 to let sram power up + 3 + 4 + read-write + + + + + RND_DATA + APB_CTRL_RND_DATA_REG + 0xB0 + 0x20 + + + RND_DATA + reg_rnd_data + 0 + 32 + read-only + + + + + PERI_BACKUP_CONFIG_REG + APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + 0xB4 + 0x20 + 0x00006480 + + + PERI_BACKUP_FLOW_ERR + reg_peri_backup_flow_err + 1 + 2 + read-only + + + PERI_BACKUP_BURST_LIMIT + reg_peri_backup_burst_limit + 4 + 5 + read-write + + + PERI_BACKUP_TOUT_THRES + reg_peri_backup_tout_thres + 9 + 10 + read-write + + + PERI_BACKUP_SIZE + reg_peri_backup_size + 19 + 10 + read-write + + + PERI_BACKUP_START + reg_peri_backup_start + 29 + 1 + write-only + + + PERI_BACKUP_TO_MEM + reg_peri_backup_to_mem + 30 + 1 + read-write + + + PERI_BACKUP_ENA + reg_peri_backup_ena + 31 + 1 + read-write + + + + + PERI_BACKUP_APB_ADDR_REG + APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + 0xB8 + 0x20 + + + BACKUP_APB_START_ADDR + reg_backup_apb_start_addr + 0 + 32 + read-write + + + + + PERI_BACKUP_MEM_ADDR_REG + APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + 0xBC + 0x20 + + + BACKUP_MEM_START_ADDR + reg_backup_mem_start_addr + 0 + 32 + read-write + + + + + PERI_BACKUP_INT_RAW + APB_CTRL_PERI_BACKUP_INT_RAW_REG + 0xC0 + 0x20 + + + PERI_BACKUP_DONE_INT_RAW + reg_peri_backup_done_int_raw + 0 + 1 + read-only + + + PERI_BACKUP_ERR_INT_RAW + reg_peri_backup_err_int_raw + 1 + 1 + read-only + + + + + PERI_BACKUP_INT_ST + APB_CTRL_PERI_BACKUP_INT_ST_REG + 0xC4 + 0x20 + + + PERI_BACKUP_DONE_INT_ST + reg_peri_backup_done_int_st + 0 + 1 + read-only + + + PERI_BACKUP_ERR_INT_ST + reg_peri_backup_err_int_st + 1 + 1 + read-only + + + + + PERI_BACKUP_INT_ENA + APB_CTRL_PERI_BACKUP_INT_ENA_REG + 0xC8 + 0x20 + + + PERI_BACKUP_DONE_INT_ENA + reg_peri_backup_done_int_ena + 0 + 1 + read-write + + + PERI_BACKUP_ERR_INT_ENA + reg_peri_backup_err_int_ena + 1 + 1 + read-write + + + + + PERI_BACKUP_INT_CLR + APB_CTRL_PERI_BACKUP_INT_CLR_REG + 0xD0 + 0x20 + + + PERI_BACKUP_DONE_INT_CLR + reg_peri_backup_done_int_clr + 0 + 1 + write-only + + + PERI_BACKUP_ERR_INT_CLR + reg_peri_backup_err_int_clr + 1 + 1 + write-only + + + + + DATE + APB_CTRL_DATE_REG + 0x3FC + 0x20 + 0x02106080 + + + DATE + reg_dateVersion control + 0 + 32 + read-write + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x68 + registers + + + APB_ADC + 32 + + + + CTRL + register description + 0x0 + 0x20 + 0x40038240 + + + SARADC_START_FORCE + Need add description + 0 + 1 + read-write + + + SARADC_START + Need add description + 1 + 1 + read-write + + + SARADC_SAR_CLK_GATED + Need add description + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 3 + read-write + + + SARADC_SAR_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + register description + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + Need add description + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + register description + 0x8 + 0x20 + + + FILTER_FACTOR1 + Need add description + 26 + 3 + read-write + + + FILTER_FACTOR0 + Need add description + 29 + 3 + read-write + + + + + FSM_WAIT + register description + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + Need add description + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + Need add description + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + Need add description + 16 + 8 + read-write + + + + + SAR1_STATUS + register description + 0x10 + 0x20 + + + SARADC_SAR1_STATUS + Need add description + 0 + 32 + read-only + + + + + SAR2_STATUS + register description + 0x14 + 0x20 + + + SARADC_SAR2_STATUS + Need add description + 0 + 32 + read-only + + + + + SAR_PATT_TAB1 + register description + 0x18 + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR_PATT_TAB2 + register description + 0x1C + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + ONETIME_SAMPLE + register description + 0x20 + 0x20 + 0x1A000000 + + + SARADC_ONETIME_ATTEN + Need add description + 23 + 2 + read-write + + + SARADC_ONETIME_CHANNEL + Need add description + 25 + 4 + read-write + + + SARADC_ONETIME_START + Need add description + 29 + 1 + read-write + + + SARADC2_ONETIME_SAMPLE + Need add description + 30 + 1 + read-write + + + SARADC1_ONETIME_SAMPLE + Need add description + 31 + 1 + read-write + + + + + APB_ADC_ARB_CTRL + register description + 0x24 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + register description + 0x28 + 0x20 + 0x03740000 + + + FILTER_CHANNEL1 + Need add description + 18 + 4 + read-write + + + FILTER_CHANNEL0 + apb_adc1_filter_factor + 22 + 4 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1DATA_STATUS + register description + 0x2C + 0x20 + + + APB_SARADC1_DATA + Need add description + 0 + 17 + read-only + + + + + SAR2DATA_STATUS + register description + 0x30 + 0x20 + + + APB_SARADC2_DATA + Need add description + 0 + 17 + read-only + + + + + THRES0_CTRL + register description + 0x34 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + Need add description + 0 + 4 + read-write + + + THRES0_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES0_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + register description + 0x38 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + Need add description + 0 + 4 + read-write + + + THRES1_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES1_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + register description + 0x3C + 0x20 + + + THRES_ALL_EN + Need add description + 27 + 1 + read-write + + + THRES3_EN + Need add description + 28 + 1 + read-write + + + THRES2_EN + Need add description + 29 + 1 + read-write + + + THRES1_EN + Need add description + 30 + 1 + read-write + + + THRES0_EN + Need add description + 31 + 1 + read-write + + + + + INT_ENA + register description + 0x40 + 0x20 + + + THRES1_LOW_INT_ENA + Need add description + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + Need add description + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + Need add description + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + Need add description + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + Need add description + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + Need add description + 31 + 1 + read-write + + + + + INT_RAW + register description + 0x44 + 0x20 + + + THRES1_LOW_INT_RAW + Need add description + 26 + 1 + read-only + + + THRES0_LOW_INT_RAW + Need add description + 27 + 1 + read-only + + + THRES1_HIGH_INT_RAW + Need add description + 28 + 1 + read-only + + + THRES0_HIGH_INT_RAW + Need add description + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + Need add description + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + Need add description + 31 + 1 + read-only + + + + + INT_ST + register description + 0x48 + 0x20 + + + THRES1_LOW_INT_ST + Need add description + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + Need add description + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + Need add description + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + Need add description + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + Need add description + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + Need add description + 31 + 1 + read-only + + + + + INT_CLR + register description + 0x4C + 0x20 + + + THRES1_LOW_INT_CLR + Need add description + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + Need add description + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + Need add description + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + Need add description + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + Need add description + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + Need add description + 31 + 1 + write-only + + + + + DMA_CONF + register description + 0x50 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + APB_ADC_CLKM_CONF + register description + 0x54 + 0x20 + 0x00000004 + + + REG_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + REG_CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + REG_CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + Need add description + 20 + 1 + read-write + + + REG_CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_TSENS_CTRL + register description + 0x58 + 0x20 + 0x00018000 + + + REG_TSENS_OUT + Need add description + 0 + 8 + read-only + + + REG_TSENS_IN_INV + Need add description + 13 + 1 + read-write + + + REG_TSENS_CLK_DIV + Need add description + 14 + 8 + read-write + + + REG_TSENS_PU + Need add description + 22 + 1 + read-write + + + + + APB_TSENS_CTRL2 + register description + 0x5C + 0x20 + 0x00004002 + + + REG_TSENS_XPD_WAIT + Need add description + 0 + 12 + read-write + + + REG_TSENS_XPD_FORCE + Need add description + 12 + 2 + read-write + + + REG_TSENS_CLK_INV + Need add description + 14 + 1 + read-write + + + TSENS_CLK_SEL + Need add description + 15 + 1 + read-write + + + + + CALI + register description + 0x60 + 0x20 + 0x00008000 + + + CFG + Need add description + 0 + 17 + read-write + + + + + APB_CTRL_DATE + register description + 0x3FC + 0x20 + 0x02107210 + + + DATE + Need add description + 0 + 32 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x600CE000 + + 0x0 + 0x38 + registers + + + + CORE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + enbale sp underlow monitor + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + enbale sp overflow monitor + 1 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + sp underlow monitor interrupt status register + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + sp overflow monitor interupt status register + 1 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + enbale sp underlow monitor interrupt + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + enbale sp overflow monitor interrupt + 1 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + clr sp underlow monitor interrupt + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + clr sp overflow monitor interrupt + 1 + 1 + write-only + + + + + CORE_0_SP_MIN + stack min value + 0x10 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x14 + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x18 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x1C + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x20 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x24 + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x28 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_0_DEBUG_MODE + cpu status register + 0x2C + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CLOCK_GATE + clock gate register + 0x30 + 0x20 + 0x00000001 + + + CLK_EN + clock gate register + 0 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02106020 + + + DATE + version register + 0 + 28 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x84 + registers + + + DMA_CH0 + 33 + + + + INT_RAW_CH0 + DMA_INT_RAW_CH0_REG. + 0x0 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 8 + 1 + read-only + + + INFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 9 + 1 + read-only + + + INFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 10 + 1 + read-only + + + OUTFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 11 + 1 + read-only + + + OUTFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 12 + 1 + read-only + + + + + INT_ST_CH0 + DMA_INT_ST_CH0_REG. + 0x4 + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_OVF + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_UDF + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-only + + + OUTFIFO_OVF + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-only + + + OUTFIFO_UDF + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-only + + + + + INT_ENA_CH0 + DMA_INT_ENA_CH0_REG. + 0x8 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_OVF + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_UDF + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-write + + + OUTFIFO_OVF + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-write + + + OUTFIFO_UDF + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-write + + + + + INT_CLR_CH0 + DMA_INT_CLR_CH0_REG. + 0xC + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 3 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 4 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_OVF + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_UDF + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + write-only + + + OUTFIFO_OVF + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + write-only + + + OUTFIFO_UDF + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + write-only + + + + + AHB_TEST + DMA_AHB_TEST_REG. + 0x40 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + DMA_MISC_CONF_REG. + 0x44 + 0x20 + + + AHBM_RST_INTER + Set this bit, then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + reg_clk_en + 3 + 1 + read-write + + + + + DATE + DMA_DATE_REG. + 0x48 + 0x20 + 0x02105280 + + + DATE + register version. + 0 + 32 + read-write + + + + + IN_CONF0_CH0 + DMA_IN_CONF0_CH0_REG. + 0x70 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + IN_CONF1_CH0 + DMA_IN_CONF1_CH0_REG. + 0x74 + 0x20 + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + INFIFO_STATUS_CH0 + DMA_INFIFO_STATUS_CH0_REG. + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 27 + 1 + read-only + + + + + IN_POP_CH0 + DMA_IN_POP_CH0_REG. + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + IN_LINK_CH0 + DMA_IN_LINK_CH0_REG. + 0x80 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_STATE_CH0 + DMA_IN_STATE_CH0_REG. + 0x84 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH0 + DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH0 + DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + IN_DSCR_CH0 + DMA_IN_DSCR_CH0_REG. + 0x90 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH0 + DMA_IN_DSCR_BF0_CH0_REG. + 0x94 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH0 + DMA_IN_DSCR_BF1_CH0_REG. + 0x98 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + IN_PRI_CH0 + DMA_IN_PRI_CH0_REG. + 0x9C + 0x20 + + + RX_PRI + The priority of Rx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + IN_PERI_SEL_CH0 + DMA_IN_PERI_SEL_CH0_REG. + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + OUT_CONF0_CH0 + DMA_OUT_CONF0_CH0_REG. + 0xD0 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + OUT_CONF1_CH0 + DMA_OUT_CONF1_CH0_REG. + 0xD4 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + OUTFIFO_STATUS_CH0 + DMA_OUTFIFO_STATUS_CH0_REG. + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + + + OUT_PUSH_CH0 + DMA_OUT_PUSH_CH0_REG. + 0xDC + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + OUT_LINK_CH0 + DMA_OUT_LINK_CH0_REG. + 0xE0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_STATE_CH0 + DMA_OUT_STATE_CH0_REG. + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + OUT_EOF_DES_ADDR_CH0 + DMA_OUT_EOF_DES_ADDR_CH0_REG. + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR_CH0 + DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + OUT_DSCR_CH0 + DMA_OUT_DSCR_CH0_REG. + 0xF0 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH0 + DMA_OUT_DSCR_BF0_CH0_REG. + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH0 + DMA_OUT_DSCR_BF1_CH0_REG. + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + OUT_PRI_CH0 + DMA_OUT_PRI_CH0_REG. + 0xFC + 0x20 + + + TX_PRI + The priority of Tx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + OUT_PERI_SEL_CH0 + DMA_OUT_PERI_SEL_CH0_REG. + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x6003E000 + + 0x0 + 0x18 + registers + + + + MULT_INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + I2S RX configure register + 0x1C + 0x20 + + + START + Set this bit to reset receiver + 0 + 1 + read-write + + + RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + KEY_LENGTH + Set this bit to start receiving data + 2 + 1 + read-write + + + SECURITY_MODE + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + CLK_EN + clk gate + 4 + 1 + read-write + + + WORK_MODE + Reserved + 5 + 3 + read-write + + + VERIFICATION_RESULT + Reserve + 8 + 1 + read-only + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02012230 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x60008800 + + 0x0 + 0xC0 + registers + + + EFUSE + 20 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + The content of the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + The content of the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + The content of the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + The content of the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + The content of the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + The content of the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + The content of the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + The content of the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + The content of the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Disable programming of individual eFuses. + 0 + 8 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + The bit be set to disable software read high/low 128-bit of BLK3. + 0 + 2 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. + 2 + 2 + read-only + + + DIS_PAD_JTAG + Set this bit to disable pad jtag. + 4 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + The bit be set to disable icache in download mode. + 5 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + The bit be set to disable manual encryption. + 6 + 1 + read-only + + + SPI_BOOT_ENCRYPT_DECRYPT_CNT + These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. + 7 + 3 + read-only + + + XTS_KEY_LENGTH_256 + The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3. + 10 + 1 + read-only + + + UART_PRINT_CONTROL + Set this bit to disable usb printing. + 11 + 2 + read-only + + + FORCE_SEND_RESUME + Set this bit to force ROM code to send a resume command during SPI boot. + 13 + 1 + read-only + + + DIS_DOWNLOAD_MODE + Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). + 14 + 1 + read-only + + + DIS_DIRECT_BOOT + This bit set means disable direct_boot mode. + 15 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode. + 16 + 1 + read-only + + + FLASH_TPUW + Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value. + 17 + 4 + read-only + + + SECURE_BOOT_EN + The bit be set to enable secure boot. + 21 + 1 + read-only + + + RPT4_RESERVED + Reserved (used for four backups method). + 22 + 10 + read-only + + + + + RD_BLK1_DATA0 + BLOCK1 data register 0. + 0x34 + 0x20 + + + SYSTEM_DATA0 + Stores the bits [0:31] of system data. + 0 + 32 + read-only + + + + + RD_BLK1_DATA1 + BLOCK1 data register 1. + 0x38 + 0x20 + + + SYSTEM_DATA1 + Stores the bits [32:63] of system data. + 0 + 32 + read-only + + + + + RD_BLK1_DATA2 + BLOCK1 data register 2. + 0x3C + 0x20 + + + SYSTEM_DATA2 + Stores the bits [64:87] of system data. + 0 + 24 + read-only + + + + + RD_BLK2_DATA0 + Register 0 of BLOCK2. + 0x40 + 0x20 + + + BLK2_DATA0 + Store the bit [0:31] of MAC. + 0 + 32 + read-only + + + + + RD_BLK2_DATA1 + Register 1 of BLOCK2. + 0x44 + 0x20 + + + MAC_ID_HIGH + Store the bit [31:47] of MAC. + 0 + 16 + read-only + + + WAFER_VERSION + Store wafer version. + 16 + 3 + read-only + + + PKG_VERSION + Store package version. + 19 + 3 + read-only + + + BLK2_EFUSE_VERSION + Store efuse version. + 22 + 3 + read-only + + + RF_REF_I_BIAS_CONFIG + Store rf configuration parameters. + 25 + 4 + read-only + + + LDO_VOL_BIAS_CONFIG_LOW + Store the bit [0:2] of ido configuration parameters. + 29 + 3 + read-only + + + + + RD_BLK2_DATA2 + Register 2 of BLOCK2. + 0x48 + 0x20 + + + LDO_VOL_BIAS_CONFIG_HIGH + Store the bit [3:29] of ido configuration parameters. + 0 + 27 + read-only + + + PVT_LOW + Store the bit [0:4] of pvt. + 27 + 5 + read-only + + + + + RD_BLK2_DATA3 + Register 3 of BLOCK2. + 0x4C + 0x20 + + + PVT_HIGH + Store the bit [5:14] of pvt. + 0 + 10 + read-only + + + ADC_CALIBRATION_0 + Store the bit [0:21] of ADC calibration data. + 10 + 22 + read-only + + + + + RD_BLK2_DATA4 + Register 4 of BLOCK2. + 0x50 + 0x20 + + + ADC_CALIBRATION_1 + Store the bit [22:53] of ADC calibration data. + 0 + 32 + read-only + + + + + RD_BLK2_DATA5 + Register 5 of BLOCK2. + 0x54 + 0x20 + + + ADC_CALIBRATION_2 + Store the bit [54:85] of ADC calibration data. + 0 + 32 + read-only + + + + + RD_BLK2_DATA6 + Register 6 of BLOCK2. + 0x58 + 0x20 + + + ADC_CALIBRATION_3 + Store the bit [86:96] of ADC calibration data. + 0 + 11 + read-only + + + BLK2_RESERVED_DATA_0 + Store the bit [0:20] of block2 reserved data. + 11 + 21 + read-only + + + + + RD_BLK2_DATA7 + Register 7 of BLOCK2. + 0x5C + 0x20 + + + BLK2_RESERVED_DATA_1 + Store the bit [21:52] of block2 reserved data. + 0 + 32 + read-only + + + + + RD_BLK3_DATA0 + Register 0 of BLOCK3. + 0x60 + 0x20 + + + BLK3_DATA0 + Store the first 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA1 + Register 1 of BLOCK3. + 0x64 + 0x20 + + + BLK3_DATA1 + Store the second 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA2 + Register 2 of BLOCK3. + 0x68 + 0x20 + + + BLK3_DATA2 + Store the third 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA3 + Register 3 of BLOCK3. + 0x6C + 0x20 + + + BLK3_DATA3 + Store the fourth 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA4 + Register 4 of BLOCK3. + 0x70 + 0x20 + + + BLK3_DATA4 + Store the fifth 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA5 + Register 5 of BLOCK3. + 0x74 + 0x20 + + + BLK3_DATA5 + Store the sixth 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA6 + Register 6 of BLOCK3. + 0x78 + 0x20 + + + BLK3_DATA6 + Store the seventh 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_BLK3_DATA7 + Register 7 of BLOCK3. + 0x7C + 0x20 + + + BLK3_DATA7 + Store the eighth 32-bit of Block3. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR + Programming error record register 0 of BLOCK0. + 0x80 + 0x20 + + + RD_DIS_ERR + If any bit in RD_DIS is 1, then it indicates a programming error. + 0 + 2 + read-only + + + WDT_DELAY_SEL_ERR + If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + 2 + 2 + read-only + + + DIS_PAD_JTAG_ERR + If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error. + 4 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + If any bit in this filed is 1, then it indicates a programming error. + 5 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + 6 + 1 + read-only + + + SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR + If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error. + 7 + 3 + read-only + + + XTS_KEY_LENGTH_256_ERR + If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error. + 10 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + 11 + 2 + read-only + + + FORCE_SEND_RESUME_ERR + If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error. + 13 + 1 + read-only + + + DIS_DOWNLOAD_MODE_ERR + If any bit in this filed is 1, then it indicates a programming error. + 14 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + If any bit in this filed is 1, then it indicates a programming error. + 15 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + If any bit in this filed is 1, then it indicates a programming error. + 16 + 1 + read-only + + + FLASH_TPUW_ERR + If any bit in this filed is 1, then it indicates a programming error. + 17 + 4 + read-only + + + SECURE_BOOT_EN_ERR + If any bit in this filed is 1, then it indicates a programming error. + 21 + 1 + read-only + + + RPT4_RESERVED_ERR + Reserved. + 22 + 10 + read-only + + + + + RD_RS_ERR + Programming error record register 0 of BLOCK1-10. + 0x84 + 0x20 + + + BLK1_ERR_NUM + The value of this signal means the number of error bytes in block1. + 0 + 3 + read-only + + + BLK1_FAIL + 0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + BLK2_ERR_NUM + The value of this signal means the number of error bytes in block2. + 4 + 3 + read-only + + + BLK2_FAIL + 0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + BLK3_ERR_NUM + The value of this signal means the number of error bytes in block3. + 8 + 3 + read-only + + + BLK3_FAIL + 0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x88 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit and force to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x8C + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x90 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Record the number of bit '1' in BLOCK0. + 10 + 6 + read-only + + + + + CMD + eFuse command register. + 0x94 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively. + 2 + 2 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x98 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x9C + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x100 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x104 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x108 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x10C + 0x20 + 0x12010201 + + + THR_A + Configures hold time for efuse read. + 0 + 8 + read-write + + + TRD + Configures pulse time for efuse read. + 8 + 8 + read-write + + + TSUR_A + Configures setup time for efuse read. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF0 + Configurarion register 0 of eFuse programming timing parameters. + 0x110 + 0x20 + 0x00C80101 + + + THP_A + Configures hold time for efuse program. + 0 + 8 + read-write + + + TPGM_INACTIVE + Configures pulse time for burning '0' bit. + 8 + 8 + read-write + + + TPGM + Configures pulse time for burning '1' bit. + 16 + 16 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x114 + 0x20 + 0x00300001 + + + TSUP_A + Configures setup time for efuse program. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x118 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02108190 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C4000 + + 0x0 + 0x94 + registers + + + + ICACHE_CTRL + This description will be updated in the near future. + 0x0 + 0x20 + + + ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + + + ICACHE_CTRL1 + This description will be updated in the near future. + 0x4 + 0x20 + 0x00000003 + + + ICACHE_SHUT_IBUS + The bit is used to disable core0 ibus, 0: enable, 1: disable + 0 + 1 + read-write + + + ICACHE_SHUT_DBUS + The bit is used to disable core1 ibus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + ICACHE_TAG_POWER_CTRL + This description will be updated in the near future. + 0x8 + 0x20 + 0x00000005 + + + ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + ICACHE_SYNC_CTRL + This description will be updated in the near future. + 0x28 + 0x20 + 0x00000001 + + + ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + ICACHE_SYNC_DONE + The bit is used to indicate invalidate operation is finished. + 1 + 1 + read-only + + + + + ICACHE_SYNC_ADDR + This description will be updated in the near future. + 0x2C + 0x20 + + + ICACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_SYNC_SIZE + This description will be updated in the near future. + 0x30 + 0x20 + + + ICACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + IBUS_TO_FLASH_START_VADDR + This description will be updated in the near future. + 0x54 + 0x20 + 0x42000000 + + + IBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + IBUS_TO_FLASH_END_VADDR + This description will be updated in the near future. + 0x58 + 0x20 + 0x423FFFFF + + + IBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_START_VADDR + This description will be updated in the near future. + 0x5C + 0x20 + 0x3C000000 + + + DBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_END_VADDR + This description will be updated in the near future. + 0x60 + 0x20 + 0x3C3FFFFF + + + DBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + CACHE_ACS_CNT_CLR + This description will be updated in the near future. + 0x64 + 0x20 + + + IBUS_ACS_CNT_CLR + The bit is used to clear ibus counter. + 0 + 1 + write-only + + + DBUS_ACS_CNT_CLR + The bit is used to clear dbus counter. + 1 + 1 + write-only + + + + + CACHE_ILG_INT_ENA + This description will be updated in the near future. + 0x78 + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 0 + 1 + read-write + + + ICACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 1 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 5 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 7 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 8 + 1 + read-write + + + + + CACHE_ILG_INT_CLR + This description will be updated in the near future. + 0x7C + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 0 + 1 + write-only + + + ICACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 1 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 5 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 7 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 8 + 1 + write-only + + + + + CACHE_ILG_INT_ST + This description will be updated in the near future. + 0x80 + 0x20 + + + ICACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 0 + 1 + read-only + + + ICACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 1 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 5 + 1 + read-only + + + IBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + 7 + 1 + read-only + + + IBUS_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + 8 + 1 + read-only + + + DBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + 9 + 1 + read-only + + + DBUS_ACS_FLASH_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash miss counter overflow. + 10 + 1 + read-only + + + + + CORE0_ACS_CACHE_INT_ENA + This description will be updated in the near future. + 0x84 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE0_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE0_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE0_DBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE0_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + CORE0_DBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by dbus trying to write icache + 5 + 1 + read-write + + + + + CORE0_ACS_CACHE_INT_CLR + This description will be updated in the near future. + 0x88 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE0_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE0_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE0_DBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE0_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + CORE0_DBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by dbus trying to write icache + 5 + 1 + write-only + + + + + CORE0_ACS_CACHE_INT_ST + This description will be updated in the near future. + 0x8C + 0x20 + + + CORE0_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE0_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE0_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE0_DBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE0_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + CORE0_DBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by dbus trying to write icache + 5 + 1 + read-only + + + + + CORE0_DBUS_REJECT_ST + This description will be updated in the near future. + 0x90 + 0x20 + + + CORE0_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 3 + 1 + read-only + + + + + CORE0_DBUS_REJECT_VADDR + This description will be updated in the near future. + 0x94 + 0x20 + 0xFFFFFFFF + + + CORE0_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE0_IBUS_REJECT_ST + This description will be updated in the near future. + 0x98 + 0x20 + + + CORE0_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 0 + 3 + read-only + + + CORE0_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 3 + 1 + read-only + + + + + CORE0_IBUS_REJECT_VADDR + This description will be updated in the near future. + 0x9C + 0x20 + 0xFFFFFFFF + + + CORE0_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CACHE_MMU_FAULT_CONTENT + This description will be updated in the near future. + 0xA0 + 0x20 + + + CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 8 + read-only + + + CACHE_MMU_FAULT_CODE + The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. + 10 + 4 + read-only + + + + + CACHE_MMU_FAULT_VADDR + This description will be updated in the near future. + 0xA4 + 0x20 + + + CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + CACHE_WRAP_AROUND_CTRL + This description will be updated in the near future. + 0xA8 + 0x20 + + + CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + + + CACHE_MMU_POWER_CTRL + This description will be updated in the near future. + 0xAC + 0x20 + 0x00000005 + + + CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + CACHE_STATE + This description will be updated in the near future. + 0xB0 + 0x20 + 0x00000001 + + + ICACHE_STATE + The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + This description will be updated in the near future. + 0xB4 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved. + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved. + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + This description will be updated in the near future. + 0xB8 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_MANUAL_CRYPT + The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_AUTO_CRYPT + The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_CRYPT + The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + This description will be updated in the near future. + 0xBC + 0x20 + + + ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + This description will be updated in the near future. + 0xC0 + 0x20 + + + ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + + + CACHE_MMU_OWNER + This description will be updated in the near future. + 0xC4 + 0x20 + + + CACHE_MMU_OWNER + The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus + 0 + 4 + read-write + + + + + CACHE_CONF_MISC + This description will be updated in the near future. + 0xC8 + 0x20 + 0x00000007 + + + CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + CACHE_TRACE_ENA + The bit is used to enable cache trace function. + 2 + 1 + read-write + + + CACHE_MMU_PAGE_SIZE + This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB + 3 + 2 + read-write + + + + + ICACHE_FREEZE + This description will be updated in the near future. + 0xCC + 0x20 + + + ENA + The bit is used to enable icache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate icache freeze success + 2 + 1 + read-only + + + + + ICACHE_ATOMIC_OPERATE_ENA + This description will be updated in the near future. + 0xD0 + 0x20 + 0x00000001 + + + ICACHE_ATOMIC_OPERATE_ENA + The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + CACHE_REQUEST + This description will be updated in the near future. + 0xD4 + 0x20 + + + BYPASS + The bit is used to disable request recording which could cause performance issue + 0 + 1 + read-write + + + + + CLOCK_GATE + This description will be updated in the near future. + 0x100 + 0x20 + 0x00000001 + + + CLK_EN + clock gate enable. + 0 + 1 + read-write + + + + + REG_DATE + This description will be updated in the near future. + 0x3FC + 0x20 + 0x02107050 + + + DATE + version information + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x314 + registers + + + GPIO + 13 + + + GPIO_NMI + 14 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-24 + 0 + 25 + read-write + + + + + OUT_W1TS + GPIO output set register + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-24 + 0 + 25 + write-only + + + + + OUT_W1TC + GPIO output clear register + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-24 + 0 + 25 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-24 + 0 + 25 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-24 + 0 + 25 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-24 + 0 + 25 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-24 + 0 + 25 + read-only + + + + + STATUS + GPIO interrupt status register + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-24 + 0 + 25 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-24 + 0 + 25 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-24 + 0 + 25 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-24 + 0 + 25 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24 + 0 + 25 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-24 + 0 + 25 + read-only + + + + + 25 + 0x4 + 0-24 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-24 + 0 + 26 + read-only + + + + + 128 + 0x4 + 0-127 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + + + IN_SEL + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 5 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 5 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 6 + 1 + read-write + + + + + 25 + 0x4 + 0-24 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000080 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 8 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 + 1 + read-write + + + + + CLOCK_GATE_REG + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + REG_DATE_REG + GPIO version register + 0x6FC + 0x20 + 0x02106190 + + + REG_DATE + version register + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60013000 + + 0x0 + 0x88 + registers + + + I2C_MST + 11 + + + I2C_EXT0 + 22 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x0000020B + + + SDA_FORCE_OUT + 0: direct output, 1: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 0: direct output, 1: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 5 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 5 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 4 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 4 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 4 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02106243 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + INTERRUPT_CORE0 + Interrupt Core + INTERRUPT_CORE0 + 0x600C2000 + + 0x0 + 0x150 + registers + + + + MAC_INTR_MAP + register description + 0x0 + 0x20 + + + WIFI_MAC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_MAC_NMI_MAP + register description + 0x4 + 0x20 + + + WIFI_MAC_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_PWR_INT_MAP + register description + 0x8 + 0x20 + + + WIFI_PWR_INT_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_BB_INT_MAP + register description + 0xC + 0x20 + + + WIFI_BB_INT_MAP + Need add description + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + register description + 0x10 + 0x20 + + + BT_MAC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + register description + 0x14 + 0x20 + + + BT_BB_INT_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + register description + 0x18 + 0x20 + + + BT_BB_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + LP_TIMER_INT_MAP + register description + 0x1C + 0x20 + + + LP_TIMER_INT_MAP + Need add description + 0 + 5 + read-write + + + + + COEX_INT_MAP + register description + 0x20 + 0x20 + + + COEX_INT_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_TIMER_INT_MAP + register description + 0x24 + 0x20 + + + BLE_TIMER_INT_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_SEC_INT_MAP + register description + 0x28 + 0x20 + + + BLE_SEC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + register description + 0x2C + 0x20 + + + I2C_MST_INT_MAP + Need add description + 0 + 5 + read-write + + + + + APB_CTRL_INTR_MAP + register description + 0x30 + 0x20 + + + APB_CTRL_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + register description + 0x34 + 0x20 + + + GPIO_INTERRUPT_PRO_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + register description + 0x38 + 0x20 + + + GPIO_INTERRUPT_PRO_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + register description + 0x3C + 0x20 + + + SPI_INTR_1_MAP + Need add description + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + register description + 0x40 + 0x20 + + + SPI_INTR_2_MAP + Need add description + 0 + 5 + read-write + + + + + UART_INTR_MAP + register description + 0x44 + 0x20 + + + UART_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UART1_INTR_MAP + register description + 0x48 + 0x20 + + + UART1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LEDC_INT_MAP + register description + 0x4C + 0x20 + + + LEDC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + register description + 0x50 + 0x20 + + + EFUSE_INT_MAP + Need add description + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + register description + 0x54 + 0x20 + + + RTC_CORE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + register description + 0x58 + 0x20 + + + I2C_EXT0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + register description + 0x5C + 0x20 + + + TG_T0_INT_MAP + Need add description + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + register description + 0x60 + 0x20 + + + TG_WDT_INT_MAP + Need add description + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + register description + 0x64 + 0x20 + + + CACHE_IA_INT_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + register description + 0x68 + 0x20 + + + SYSTIMER_TARGET0_INT_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + register description + 0x6C + 0x20 + + + SYSTIMER_TARGET1_INT_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + register description + 0x70 + 0x20 + + + SYSTIMER_TARGET2_INT_MAP + Need add description + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + register description + 0x74 + 0x20 + + + SPI_MEM_REJECT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + register description + 0x78 + 0x20 + + + ICACHE_PRELOAD_INT_MAP + Need add description + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + register description + 0x7C + 0x20 + + + ICACHE_SYNC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + register description + 0x80 + 0x20 + + + APB_ADC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_CH0_INT_MAP + register description + 0x84 + 0x20 + + + DMA_CH0_INT_MAP + Need add description + 0 + 5 + read-write + + + + + SHA_INT_MAP + register description + 0x88 + 0x20 + + + SHA_INT_MAP + Need add description + 0 + 5 + read-write + + + + + ECC_INT_MAP + register description + 0x8C + 0x20 + + + ECC_INT_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + register description + 0x90 + 0x20 + + + CPU_INTR_FROM_CPU_0_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + register description + 0x94 + 0x20 + + + CPU_INTR_FROM_CPU_1_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + register description + 0x98 + 0x20 + + + CPU_INTR_FROM_CPU_2_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + register description + 0x9C + 0x20 + + + CPU_INTR_FROM_CPU_3_MAP + Need add description + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + register description + 0xA0 + 0x20 + + + ASSIST_DEBUG_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + register description + 0xA4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + register description + 0xA8 + 0x20 + + + CACHE_CORE0_ACS_INT_MAP + Need add description + 0 + 5 + read-write + + + + + INTR_STATUS_REG_0 + register description + 0xAC + 0x20 + + + INTR_STATUS_0 + Need add description + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + register description + 0xB0 + 0x20 + + + INTR_STATUS_1 + Need add description + 0 + 32 + read-only + + + + + CLOCK_GATE + register description + 0xB4 + 0x20 + 0x00000001 + + + REG_CLK_EN + Need add description + 0 + 1 + read-write + + + + + CPU_INT_ENABLE + register description + 0xB8 + 0x20 + + + CPU_INT_ENABLE + Need add description + 0 + 32 + read-write + + + + + CPU_INT_TYPE + register description + 0xBC + 0x20 + + + CPU_INT_TYPE + Need add description + 0 + 32 + read-write + + + + + CPU_INT_CLEAR + register description + 0xC0 + 0x20 + + + CPU_INT_CLEAR + Need add description + 0 + 32 + read-write + + + + + CPU_INT_EIP_STATUS + register description + 0xC4 + 0x20 + + + CPU_INT_EIP_STATUS + Need add description + 0 + 32 + read-only + + + + + CPU_INT_PRI_0 + register description + 0xC8 + 0x20 + + + CPU_PRI_0_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_1 + register description + 0xCC + 0x20 + + + CPU_PRI_1_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_2 + register description + 0xD0 + 0x20 + + + CPU_PRI_2_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_3 + register description + 0xD4 + 0x20 + + + CPU_PRI_3_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_4 + register description + 0xD8 + 0x20 + + + CPU_PRI_4_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_5 + register description + 0xDC + 0x20 + + + CPU_PRI_5_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_6 + register description + 0xE0 + 0x20 + + + CPU_PRI_6_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_7 + register description + 0xE4 + 0x20 + + + CPU_PRI_7_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_8 + register description + 0xE8 + 0x20 + + + CPU_PRI_8_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_9 + register description + 0xEC + 0x20 + + + CPU_PRI_9_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_10 + register description + 0xF0 + 0x20 + + + CPU_PRI_10_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_11 + register description + 0xF4 + 0x20 + + + CPU_PRI_11_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_12 + register description + 0xF8 + 0x20 + + + CPU_PRI_12_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_13 + register description + 0xFC + 0x20 + + + CPU_PRI_13_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_14 + register description + 0x100 + 0x20 + + + CPU_PRI_14_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_15 + register description + 0x104 + 0x20 + + + CPU_PRI_15_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_16 + register description + 0x108 + 0x20 + + + CPU_PRI_16_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_17 + register description + 0x10C + 0x20 + + + CPU_PRI_17_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_18 + register description + 0x110 + 0x20 + + + CPU_PRI_18_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_19 + register description + 0x114 + 0x20 + + + CPU_PRI_19_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_20 + register description + 0x118 + 0x20 + + + CPU_PRI_20_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_21 + register description + 0x11C + 0x20 + + + CPU_PRI_21_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_22 + register description + 0x120 + 0x20 + + + CPU_PRI_22_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_23 + register description + 0x124 + 0x20 + + + CPU_PRI_23_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_24 + register description + 0x128 + 0x20 + + + CPU_PRI_24_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_25 + register description + 0x12C + 0x20 + + + CPU_PRI_25_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_26 + register description + 0x130 + 0x20 + + + CPU_PRI_26_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_27 + register description + 0x134 + 0x20 + + + CPU_PRI_27_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_28 + register description + 0x138 + 0x20 + + + CPU_PRI_28_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_29 + register description + 0x13C + 0x20 + + + CPU_PRI_29_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_30 + register description + 0x140 + 0x20 + + + CPU_PRI_30_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_PRI_31 + register description + 0x144 + 0x20 + + + CPU_PRI_31_MAP + Need add description + 0 + 4 + read-write + + + + + CPU_INT_THRESH + register description + 0x148 + 0x20 + + + CPU_INT_THRESH + Need add description + 0 + 4 + read-write + + + + + INTERRUPT_REG_DATE + register description + 0x7FC + 0x20 + 0x02108190 + + + INTERRUPT_REG_DATE + Need add description + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0x5C + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x000007FF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 4 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 4 + 4 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 8 + 4 + read-write + + + + + 21 + 0x4 + GPIO%s + IO MUX Configure Register for pad XTAL_32K_P + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02106190 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED PWM (Pulse Width Modulation) Controller + LEDC + 0x60019000 + + 0x0 + 0xB0 + registers + + + LEDC + 19 + + + + 6 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + + + 6 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 14 + read-write + + + + + 6 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 19 + read-write + + + + + 6 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register is used to configure the changing step scale of duty on channel %s. + 0 + 10 + read-write + + + DUTY_CYCLE + The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the number of times the duty cycle will be changed. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. + 30 + 1 + read-write + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 6 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_CH0_R + This register stores the current duty of output signal on channel %s. + 0 + 19 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 4 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 4 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 22 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 23 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 24 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 25 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + CNT + This register stores the current counter value of timer %s. + 0 + 14 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 10 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 11 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 12 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 13 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 14 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 15 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 10 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 10 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 11 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 10 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 11 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 15 + 1 + write-only + + + + + CONF + Global ledc configuration register + 0xD0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19061700 + + + LEDC_DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60026000 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0xB0 + 0x20 + + + + + RTC_CNTL + Real Time Controller + RTC_CNTL + 0x60008000 + + 0x0 + 0x114 + registers + + + RTC_CORE + 21 + + + + OPTIONS0 + register description + 0x0 + 0x20 + 0x1000A000 + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + read-write + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + XTL_EN_WAIT + wait bias_sleep and current source wakeup + 14 + 4 + read-write + + + XTL_EXT_CTR_SEL + Need add desc + 20 + 3 + read-write + + + ANALOG_FORCE_ISO + Need add desc + 25 + 1 + read-write + + + ANALOG_FORCE_NOISO + Need add desc + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + read-write + + + + + SLP_TIMER0 + register description + 0x4 + 0x20 + + + SLP_VAL_LO + Need add desc + 0 + 32 + read-write + + + + + SLP_TIMER1 + register description + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + read-write + + + + + TIME_UPDATE + register description + 0xC + 0x20 + + + TIMER_SYS_STALL + Enable to record system stall time + 27 + 1 + read-write + + + TIMER_XTL_OFF + Enable to record 40M XTAL OFF time + 28 + 1 + read-write + + + TIMER_SYS_RST + enable to record system reset time + 29 + 1 + read-write + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + read-write + + + + + TIME_LOW0 + register description + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + RTC timer low 32 bits + 0 + 32 + read-write + + + + + TIME_HIGH0 + register description + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + RTC timer high 16 bits + 0 + 16 + read-write + + + + + STATE0 + register description + 0x18 + 0x20 + + + SW_CPU_INT + rtc software interrupt to main cpu + 0 + 1 + read-write + + + SLP_REJECT_CAUSE_CLR + clear rtc sleep reject cause + 1 + 1 + read-write + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-write + + + SLP_WAKEUP + leep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + leep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + register description + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + register description + 0x20 + 0x20 + 0x01000000 + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER4 + register description + 0x24 + 0x20 + 0x10200000 + + + DG_WRAP_WAIT_TIMER + Need add desc + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + Need add desc + 25 + 7 + read-write + + + + + TIMER5 + register description + 0x28 + 0x20 + 0x00008000 + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + + + ANA_CONF + register description + 0x2C + 0x20 + 0x00440000 + + + I2C_RESET_POR_FORCE_PD + Need add desc + 18 + 1 + read-write + + + I2C_RESET_POR_FORCE_PU + Need add desc + 19 + 1 + read-write + + + SAR_I2C_PU + PLLA force power up + 22 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up + 30 + 1 + read-write + + + PLL_I2C_PU + Need add desc + 31 + 1 + read-write + + + PLLA_FORCE_PD + PLLA force power down + 23 + 1 + read-write + + + PLLA_FORCE_PU + PLLA force power up + 24 + 1 + read-write + + + + + RESET_STATE + register description + 0x30 + 0x20 + 0x00002000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-write + + + STAT_VECTOR_SEL_PROCPU + PRO CPU state vector sel + 13 + 1 + read-write + + + OCD_HALT_ON_RESET_PROCPU + PROCPU OcdHaltOnReset + 19 + 1 + read-write + + + DRESET_MASK_PROCPU + Need add desc + 20 + 1 + read-write + + + + + WAKEUP_STATE + register description + 0x34 + 0x20 + 0x00060000 + + + WAKEUP_ENA + wakeup enable bitmap + 15 + 17 + read-write + + + + + INT_ENA_RTC + register description + 0x38 + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 9 + 1 + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 10 + 1 + + + SWD_INT_ENA + enable super watch dog interrupt + 15 + 1 + + + BBPLL_CAL_INT_ENA + Need add desc + 20 + 1 + + + + + INT_RAW_RTC + register description + 0x3C + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-write + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-write + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-write + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 9 + 1 + read-write + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 10 + 1 + read-write + + + SWD_INT_RAW + super watch dog interrupt raw + 15 + 1 + read-write + + + BBPLL_CAL_INT_RAW + Need add desc + 20 + 1 + read-write + + + + + INT_ST_RTC + register description + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-write + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-write + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-write + + + BROWN_OUT_INT_ST + brown out interrupt state + 9 + 1 + read-write + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 10 + 1 + read-write + + + SWD_INT_ST + super watch dog interrupt state + 15 + 1 + read-write + + + BBPLL_CAL_INT_ST + Need add desc + 20 + 1 + read-write + + + + + INT_CLR_RTC + register description + 0x44 + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + read-write + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + read-write + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + read-write + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 9 + 1 + read-write + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 10 + 1 + read-write + + + SWD_INT_CLR + Clear super watch dog interrupt state + 15 + 1 + read-write + + + BBPLL_CAL_INT_CLR + Need add desc + 20 + 1 + read-write + + + + + STORE0 + register description + 0x48 + 0x20 + + + SCRATCH0 + Need add desc + 0 + 32 + read-write + + + + + STORE1 + register description + 0x4C + 0x20 + + + SCRATCH1 + Need add desc + 0 + 32 + read-write + + + + + STORE2 + register description + 0x50 + 0x20 + + + SCRATCH2 + Need add desc + 0 + 32 + read-write + + + + + STORE3 + register description + 0x54 + 0x20 + + + SCRATCH3 + Need add desc + 0 + 32 + read-write + + + + + EXT_XTL_CONF + register description + 0x58 + 0x20 + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + Need add desc + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + register description + 0x5C + 0x20 + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + register description + 0x60 + 0x20 + + + SLEEP_REJECT_ENA + sleep reject enable + 12 + 18 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + register description + 0x64 + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + Need add desc + 30 + 2 + read-write + + + + + CLK_CONF + register description + 0x68 + 0x20 + 0x11583218 + + + EFUSE_CLK_FORCE_GATING + Need add desc + 1 + 1 + read-write + + + EFUSE_CLK_FORCE_NOGATING + Need add desc + 2 + 1 + read-write + + + CK8M_DIV_SEL_VLD + used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + 3 + 1 + read-write + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128 + 4 + 2 + read-write + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M + 7 + 1 + read-write + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + XTAL_GLOBAL_FORCE_GATING + Need add desc + 27 + 1 + read-write + + + XTAL_GLOBAL_FORCE_NOGATING + Need add desc + 28 + 1 + read-write + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4 + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + Need add desc + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + register description + 0x6C + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + used to sync div bus. clear vld before set reg_rtc_ana_clk_div + 22 + 1 + read-write + + + ANA_CLK_DIV + Need add desc + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + Need add desc + 31 + 1 + read-write + + + + + BIAS_CONF + register description + 0x70 + 0x20 + 0x00010800 + + + DG_VDD_DRV_B_SLP + Need add desc + 0 + 8 + read-write + + + DG_VDD_DRV_B_SLP_EN + Need add desc + 8 + 1 + read-write + + + BIAS_BUF_IDLE + Need add desc + 10 + 1 + read-write + + + BIAS_BUF_WAKE + Need add desc + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + Need add desc + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + Need add desc + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in active state + 22 + 4 + read-write + + + DBG_ATTEN_ACTIVE + Need add desc + 26 + 4 + read-write + + + + + RTC_CNTL + register description + 0x74 + 0x20 + 0x80000000 + + + DIG_REG_CAL_EN + Need add desc + 7 + 1 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + REGULATOR_FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + Need add desc + 31 + 1 + read-write + + + + + PWC + register description + 0x78 + 0x20 + + + PAD_FORCE_HOLD + rtc pad force hold + 21 + 1 + read-write + + + + + DIG_PWC + register description + 0x7C + 0x20 + 0x00100020 + + + VDD_SPI_PWR_DRV + Need add desc + 0 + 2 + read-write + + + VDD_SPI_PWR_FORCE + Need add desc + 2 + 1 + read-write + + + VDD_SPI_PD_EN + Need add desc + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 4 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force no PD in sleep + 5 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + DG_WRAP_PD_EN + Need add desc + 31 + 1 + read-write + + + + + DIG_ISO + register description + 0x80 + 0x20 + 0x80005080 + + + FORCE_OFF + Need add desc + 7 + 1 + read-write + + + FORCE_ON + Need add desc + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-write + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + read-write + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + Need add desc + 31 + 1 + read-write + + + + + WDTCONFIG0 + register description + 0x84 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 9 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 16 + 3 + read-write + + + WDT_STG3 + 1: interrupt stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en + 28 + 3 + read-write + + + WDT_EN + Need add desc + 31 + 1 + read-write + + + + + WDTCONFIG1 + register description + 0x88 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + Need add desc + 0 + 32 + read-write + + + + + WDTCONFIG2 + register description + 0x8C + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + Need add desc + 0 + 32 + read-write + + + + + WDTCONFIG3 + register description + 0x90 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + Need add desc + 0 + 32 + read-write + + + + + WDTCONFIG4 + register description + 0x94 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + Need add desc + 0 + 32 + read-write + + + + + WDTFEED + register description + 0x98 + 0x20 + + + WDT_FEED + Need add desc + 31 + 1 + read-write + + + + + WDTWPROTECT + register description + 0x9C + 0x20 + + + WDT_WKEY + Need add desc + 0 + 32 + read-write + + + + + SWD_CONF + register description + 0xA0 + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + swd reset flag + 0 + 1 + read-write + + + SWD_FEED_INT + swd interrupt for feeding + 1 + 1 + read-write + + + SWD_BYPASS_RST + Need add desc + 17 + 1 + read-write + + + SWD_SIGNAL_WIDTH + adjust signal width send to swd + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + reset swd reset flag + 28 + 1 + read-write + + + SWD_FEED + Sw feed swd + 29 + 1 + read-write + + + SWD_DISABLE + disabel SWD + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + automatically feed swd when int comes + 31 + 1 + read-write + + + + + SWD_WPROTECT + register description + 0xA4 + 0x20 + + + SWD_WKEY + Need add desc + 0 + 32 + read-write + + + + + SW_CPU_STALL + register description + 0xA8 + 0x20 + + + SW_STALL_PROCPU_C1 + Need add desc + 26 + 6 + read-write + + + + + STORE4 + register description + 0xAC + 0x20 + + + SCRATCH4 + Need add desc + 0 + 32 + read-write + + + + + STORE5 + register description + 0xB0 + 0x20 + + + SCRATCH5 + Need add desc + 0 + 32 + read-write + + + + + STORE6 + register description + 0xB4 + 0x20 + + + SCRATCH6 + Need add desc + 0 + 32 + read-write + + + + + STORE7 + register description + 0xB8 + 0x20 + + + SCRATCH7 + Need add desc + 0 + 32 + read-write + + + + + LOW_POWER_ST + register description + 0xBC + 0x20 + + + XPD_DIG + digital wrap power down + 8 + 1 + read-write + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-write + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-write + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-write + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-write + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-write + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-write + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-write + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-write + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-write + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-write + + + RDY_FOR_WAKEUP + rtc is ready to receive wake up trigger from wake up source + 19 + 1 + read-write + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-write + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-write + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-write + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-write + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-write + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-write + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-write + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-write + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-write + + + + + DIAG0 + register description + 0xC0 + 0x20 + + + LOW_POWER_DIAG1 + Need add desc + 0 + 32 + read-write + + + + + PAD_HOLD + register description + 0xC4 + 0x20 + + + GPIO_PIN0_HOLD + Need add desc + 0 + 1 + read-write + + + GPIO_PIN1_HOLD + Need add desc + 1 + 1 + read-write + + + GPIO_PIN2_HOLD + Need add desc + 2 + 1 + read-write + + + GPIO_PIN3_HOLD + Need add desc + 3 + 1 + read-write + + + GPIO_PIN4_HOLD + Need add desc + 4 + 1 + read-write + + + GPIO_PIN5_HOLD + Need add desc + 5 + 1 + read-write + + + + + DIG_PAD_HOLD + register description + 0xC8 + 0x20 + + + DIG_PAD_HOLD + Need add desc + 0 + 32 + read-write + + + + + BROWN_OUT + register description + 0xCC + 0x20 + 0x43FF0010 + + + BROWN_OUT_INT_WAIT + brown out interrupt wait cycles + 4 + 10 + read-write + + + BROWN_OUT_CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + BROWN_OUT_PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + BROWN_OUT_RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + BROWN_OUT_RST_ENA + enable brown out reset + 26 + 1 + read-write + + + BROWN_OUT_RST_SEL + 1: 4-pos reset + 27 + 1 + read-write + + + BROWN_OUT_ANA_RST_EN + Need add desc + 28 + 1 + read-write + + + BROWN_OUT_CNT_CLR + clear brown out counter + 29 + 1 + read-write + + + BROWN_OUT_ENA + enable brown out + 30 + 1 + read-write + + + DET + Need add desc + 31 + 1 + read-write + + + + + TIME_LOW1 + register description + 0xD0 + 0x20 + + + TIMER_VALUE1_LOW + RTC timer low 32 bits + 0 + 32 + read-write + + + + + TIME_HIGH1 + register description + 0xD4 + 0x20 + + + TIMER_VALUE1_HIGH + RTC timer high 16 bits + 0 + 16 + read-write + + + + + USB_CONF + register description + 0xD8 + 0x20 + + + IO_MUX_RESET_DISABLE + Need add desc + 18 + 1 + read-write + + + + + SLP_REJECT_CAUSE + register description + 0xDC + 0x20 + + + REJECT_CAUSE + sleep reject cause + 0 + 18 + read-write + + + + + OPTION1 + register description + 0xE0 + 0x20 + + + FORCE_DOWNLOAD_BOOT + Need add desc + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + register description + 0xE4 + 0x20 + + + WAKEUP_CAUSE + sleep wakeup cause + 0 + 17 + read-write + + + + + ULP_CP_TIMER_1 + register description + 0xE8 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + INT_ENA_RTC_W1TS + register description + 0xEC + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TS + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA_W1TS + enable sleep reject interrupt + 1 + 1 + read-write + + + WDT_INT_ENA_W1TS + enable RTC WDT interrupt + 3 + 1 + read-write + + + BROWN_OUT_INT_ENA_W1TS + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA_W1TS + enable RTC main timer interrupt + 10 + 1 + read-write + + + SWD_INT_ENA_W1TS + enable super watch dog interrupt + 15 + 1 + read-write + + + BBPLL_CAL_INT_ENA_W1TS + Need add desc + 20 + 1 + read-write + + + + + INT_ENA_RTC_W1TC + register description + 0xF0 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TC + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA_W1TC + enable sleep reject interrupt + 1 + 1 + read-write + + + WDT_INT_ENA_W1TC + enable RTC WDT interrupt + 3 + 1 + read-write + + + BROWN_OUT_INT_ENA_W1TC + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA_W1TC + enable RTC main timer interrupt + 10 + 1 + read-write + + + SWD_INT_ENA_W1TC + enable super watch dog interrupt + 15 + 1 + read-write + + + BBPLL_CAL_INT_ENA_W1TC + Need add desc + 20 + 1 + read-write + + + + + CNTL_RETENTION_CTRL + register description + 0xF4 + 0x20 + 0xA0D00000 + + + RETENTION_CLK_SEL + Need add desc + 18 + 1 + read-write + + + RETENTION_DONE_WAIT + Need add desc + 19 + 3 + read-write + + + RETENTION_CLKOFF_WAIT + Need add desc + 22 + 4 + read-write + + + RETENTION_EN + Need add desc + 26 + 1 + read-write + + + RETENTION_WAIT + wait cycles for rention operation + 27 + 5 + read-write + + + + + FIB_SEL + register description + 0xF8 + 0x20 + 0x00000007 + + + FIB_SEL + select use analog fib signal + 0 + 3 + read-write + + + + + CNTL_GPIO_WAKEUP + register description + 0xFC + 0x20 + + + GPIO_WAKEUP_STATUS + Need add desc + 0 + 6 + read-write + + + GPIO_WAKEUP_STATUS_CLR + Need add desc + 6 + 1 + read-write + + + GPIO_PIN_CLK_GATE + Need add desc + 7 + 1 + read-write + + + GPIO_PIN5_INT_TYPE + Need add desc + 8 + 3 + read-write + + + GPIO_PIN4_INT_TYPE + Need add desc + 11 + 3 + read-write + + + GPIO_PIN3_INT_TYPE + Need add desc + 14 + 3 + read-write + + + GPIO_PIN2_INT_TYPE + Need add desc + 17 + 3 + read-write + + + GPIO_PIN1_INT_TYPE + Need add desc + 20 + 3 + read-write + + + GPIO_PIN0_INT_TYPE + Need add desc + 23 + 3 + read-write + + + GPIO_PIN5_WAKEUP_ENABLE + Need add desc + 26 + 1 + read-write + + + GPIO_PIN4_WAKEUP_ENABLE + Need add desc + 27 + 1 + read-write + + + GPIO_PIN3_WAKEUP_ENABLE + Need add desc + 28 + 1 + read-write + + + GPIO_PIN2_WAKEUP_ENABLE + Need add desc + 29 + 1 + read-write + + + GPIO_PIN1_WAKEUP_ENABLE + Need add desc + 30 + 1 + read-write + + + GPIO_PIN0_WAKEUP_ENABLE + Need add desc + 31 + 1 + read-write + + + + + CNTL_DBG_SEL + register description + 0x100 + 0x20 + + + DEBUG_12M_NO_GATING + Need add desc + 1 + 1 + read-write + + + DEBUG_BIT_SEL + Need add desc + 2 + 5 + read-write + + + DEBUG_SEL0 + Need add desc + 7 + 5 + read-write + + + DEBUG_SEL1 + Need add desc + 12 + 5 + read-write + + + DEBUG_SEL2 + Need add desc + 17 + 5 + read-write + + + DEBUG_SEL3 + Need add desc + 22 + 5 + read-write + + + DEBUG_SEL4 + Need add desc + 27 + 5 + read-write + + + + + CNTL_DBG_MAP + register description + 0x104 + 0x20 + + + GPIO_PIN5_MUX_SEL + Need add desc + 2 + 1 + read-write + + + GPIO_PIN4_MUX_SEL + Need add desc + 3 + 1 + read-write + + + GPIO_PIN3_MUX_SEL + Need add desc + 4 + 1 + read-write + + + GPIO_PIN2_MUX_SEL + Need add desc + 5 + 1 + read-write + + + GPIO_PIN1_MUX_SEL + Need add desc + 6 + 1 + read-write + + + GPIO_PIN0_MUX_SEL + Need add desc + 7 + 1 + read-write + + + GPIO_PIN5_FUN_SEL + Need add desc + 8 + 4 + read-write + + + GPIO_PIN4_FUN_SEL + Need add desc + 12 + 4 + read-write + + + GPIO_PIN3_FUN_SEL + Need add desc + 16 + 4 + read-write + + + GPIO_PIN2_FUN_SEL + Need add desc + 20 + 4 + read-write + + + GPIO_PIN1_FUN_SEL + Need add desc + 24 + 4 + read-write + + + GPIO_PIN0_FUN_SEL + Need add desc + 28 + 4 + read-write + + + + + CNTL_SENSOR_CTRL + register description + 0x108 + 0x20 + + + SAR2_PWDET_CCT + Need add desc + 27 + 3 + read-write + + + FORCE_XPD_SAR + Need add desc + 30 + 2 + read-write + + + + + CNTL_DBG_SAR_SEL + register description + 0x10C + 0x20 + + + SAR_DEBUG_SEL + Need add desc + 27 + 5 + read-write + + + + + CNTL_DATE + register description + 0x1FC + 0x20 + 0x02107190 + + + CNTL_DATE + Need add desc + 0 + 28 + read-write + + + + + + + SENSITIVE + Sensitive + SENSITIVE + 0x600C1000 + + 0x0 + 0x48 + registers + + + + ROM_TABLE_LOCK + register description + 0x0 + 0x20 + + + ROM_TABLE_LOCK + Need add description + 0 + 1 + read-write + + + + + ROM_TABLE + register description + 0x4 + 0x20 + + + ROM_TABLE + Need add description + 0 + 32 + read-write + + + + + APB_PERIPHERAL_ACCESS_0 + register description + 0x8 + 0x20 + + + APB_PERIPHERAL_ACCESS_LOCK + Need add description + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_1 + register description + 0xC + 0x20 + 0x00000001 + + + APB_PERIPHERAL_ACCESS_SPLIT_BURST + Need add description + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_0 + register description + 0x10 + 0x20 + + + INTERNAL_SRAM_USAGE_LOCK + Need add description + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_1 + register description + 0x14 + 0x20 + 0x0000000F + + + INTERNAL_SRAM_USAGE_CPU_CACHE + Need add description + 0 + 1 + read-write + + + INTERNAL_SRAM_USAGE_CPU_SRAM + Need add description + 1 + 3 + read-write + + + + + INTERNAL_SRAM_USAGE_3 + register description + 0x18 + 0x20 + + + INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM + Need add description + 0 + 3 + read-write + + + INTERNAL_SRAM_ALLOC_MAC_DUMP + Need add description + 3 + 1 + read-write + + + + + CACHE_TAG_ACCESS_0 + register description + 0x1C + 0x20 + + + CACHE_TAG_ACCESS_LOCK + Need add description + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + register description + 0x20 + 0x20 + 0x0000000F + + + PRO_I_TAG_RD_ACS + Need add description + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + Need add description + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + Need add description + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + Need add description + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + register description + 0x24 + 0x20 + + + CACHE_MMU_ACCESS_LOCK + Need add description + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + register description + 0x28 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + Need add description + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Need add description + 1 + 1 + read-write + + + + + PIF_ACCESS_MONITOR_0 + register description + 0x2C + 0x20 + + + PIF_ACCESS_MONITOR_LOCK + Need add description + 0 + 1 + read-write + + + + + PIF_ACCESS_MONITOR_1 + register description + 0x30 + 0x20 + 0x00000003 + + + PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR + Need add description + 0 + 1 + read-write + + + PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN + Need add description + 1 + 1 + read-write + + + + + PIF_ACCESS_MONITOR_2 + register description + 0x34 + 0x20 + + + PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR + Need add description + 0 + 1 + read-only + + + PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Need add description + 1 + 2 + read-only + + + + + PIF_ACCESS_MONITOR_3 + register description + 0x38 + 0x20 + + + PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Need add description + 0 + 32 + read-only + + + + + XTS_AES_KEY_UPDATE + register description + 0x3C + 0x20 + + + XTS_AES_KEY_UPDATE + Set this bit to update xts_aes key + 0 + 1 + read-write + + + + + CLOCK_GATE + register description + 0x40 + 0x20 + 0x00000001 + + + CLK_EN + Need add description + 0 + 1 + read-write + + + + + SENSITIVE_REG_DATE + register description + 0xFFC + 0x20 + 0x02106301 + + + SENSITIVE_REG_DATE + Need add description + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 34 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20200616 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60003000 + + 0x0 + 0x48 + registers + + + SPI_MEM_REJECT_CACHE + 29 + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. + 3 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable + 7 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control1 register. + 0xC + 0x20 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. + 30 + 1 + write-only + + + + + CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x00000021 + + + CS_SETUP_TIME + (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 5 + 5 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + Set this bit in 1-division mode. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + TRANS_END + The bit is used to indicate the spi0_mst_st controlled transmitting is done. + 3 + 1 + read-write + + + TRANS_END_INT_ENA + The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. + 4 + 1 + read-write + + + CSPI_ST_TRANS_END + The bit is used to indicate the spi0_slv_st controlled transmitting is done. + 5 + 1 + read-write + + + CSPI_ST_TRANS_END_INT_ENA + The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. + 6 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + For SPI0, Cache access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + CSPI_ST + The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 0 + 4 + read-only + + + EM_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 4 + 3 + read-only + + + CSPI_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + TIMING_CALI + SPI0 timing calibration register + 0xA8 + 0x20 + + + TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-only + + + TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-only + + + EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-only + + + + + DIN_MODE + SPI0 input delay mode control register + 0xAC + 0x20 + + + DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 2 + read-only + + + DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 2 + 2 + read-only + + + DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 4 + 2 + read-only + + + DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 2 + read-only + + + + + DIN_NUM + SPI0 input delay number control register + 0xB0 + 0x20 + + + DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 1 + read-only + + + DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 1 + 1 + read-only + + + DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 1 + read-only + + + DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 3 + 1 + read-only + + + + + DOUT_MODE + SPI0 output delay mode control register + 0xB4 + 0x20 + + + DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-only + + + DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-only + + + DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-only + + + DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-only + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xE0 + 0x20 + + + SPI01_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02106191 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60002000 + + 0x0 + 0xA8 + registers + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI1_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + MSPI_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. + 3 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable + 7 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + WAITI_CMD + The command to wait flash idle(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0005757A + + + FLASH_PER_COMMAND + Program/Erase resume command. + 0 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command. + 8 + 8 + read-write + + + WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing control register + 0xA8 + 0x20 + + + TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-only + + + EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-only + + + + + INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 5 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 5 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. + 0 + 1 + read-only + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. + 1 + 1 + read-only + + + WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-only + + + SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 5 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 5 + 1 + read-only + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02107013 + + + DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI_INTR_1 + 15 + + + SPI_INTR_2 + 16 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-only + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-only + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-only + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-only + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-only + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-only + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-only + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-only + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-only + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-only + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-only + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-only + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-only + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-only + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-only + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-only + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-only + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-only + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-only + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-only + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-only + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-only + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-only + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-only + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-only + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-only + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-only + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-only + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-only + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-only + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-only + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-only + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-only + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-only + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-only + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-only + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-only + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-only + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-only + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-only + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-only + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-only + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-only + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-only + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02106070 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTEM + System + SYSTEM + 0x600C0000 + + 0x0 + 0xA0 + registers + + + + CPU_PERI_CLK_EN + cpu_peripheral clock gating register + 0x0 + 0x20 + + + CLK_EN_ASSIST_DEBUG + Set 1 to open assist_debug module clock + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + Set 1 to open dedicated_gpio module clk + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset register + 0x4 + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + Set 1 to let assist_debug module reset + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + Set 1 to let dedicated_gpio module reset + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu clock config register + 0x8 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field used to sel cpu clock frequent. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field used to sel pll frequent. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask register + 0xC + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set 1 to mask memory power down. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock gating register + 0x10 + 0x20 + 0x71002066 + + + SPI01_CLK_EN + Set 1 to enable SPI01 clock + 1 + 1 + read-write + + + UART_CLK_EN + Set 1 to enable UART clock + 2 + 1 + read-write + + + UART1_CLK_EN + Set 1 to enable UART1 clock + 5 + 1 + read-write + + + SPI2_CLK_EN + Set 1 to enable SPI2 clock + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set 1 to enable I2C_EXT0 clock + 7 + 1 + read-write + + + LEDC_CLK_EN + Set 1 to enable LEDC clock + 11 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set 1 to enable TIMERGROUP clock + 13 + 1 + read-write + + + UART_MEM_CLK_EN + Set 1 to enable UART_MEM clock + 24 + 1 + read-write + + + APB_SARADC_CLK_EN + Set 1 to enable APB_SARADC clock + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set 1 to enable SYSTEMTIMER clock + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set 1 to enable ADC2_ARB clock + 30 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock gating register + 0x14 + 0x20 + + + CRYPTO_ECC_CLK_EN + Set 1 to enable ECC clock + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set 1 to enable SHA clock + 2 + 1 + read-write + + + DMA_CLK_EN + Set 1 to enable DMA clock + 6 + 1 + read-write + + + TSENS_CLK_EN + Set 1 to enable TSENS clock + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + reserved + 0x18 + 0x20 + + + SPI01_RST + Set 1 to let SPI01 reset + 1 + 1 + read-write + + + UART_RST + Set 1 to let UART reset + 2 + 1 + read-write + + + UART1_RST + Set 1 to let UART1 reset + 5 + 1 + read-write + + + SPI2_RST + Set 1 to let SPI2 reset + 6 + 1 + read-write + + + I2C_EXT0_RST + Set 1 to let I2C_EXT0 reset + 7 + 1 + read-write + + + LEDC_RST + Set 1 to let LEDC reset + 11 + 1 + read-write + + + TIMERGROUP_RST + Set 1 to let TIMERGROUP reset + 13 + 1 + read-write + + + UART_MEM_RST + Set 1 to let UART_MEM reset + 24 + 1 + read-write + + + APB_SARADC_RST + Set 1 to let APB_SARADC reset + 28 + 1 + read-write + + + SYSTIMER_RST + Set 1 to let SYSTIMER reset + 29 + 1 + read-write + + + ADC2_ARB_RST + Set 1 to let ADC2_ARB reset + 30 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset register + 0x1C + 0x20 + 0x00000046 + + + CRYPTO_ECC_RST + Set 1 to let CRYPTO_ECC reset + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set 1 to let CRYPTO_SHA reset + 2 + 1 + read-write + + + DMA_RST + Set 1 to let DMA reset + 6 + 1 + read-write + + + TSENS_RST + Set 1 to let TSENS reset + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + clock config register + 0x20 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + This field is lower power clock frequent division factor + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + low power clock configuration register + 0x24 + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + This field is lower power clock frequent division factor b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + This field is lower power clock frequent division factor a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + Set 1 to select rtc-slow clock as rtc low power clock + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set 1 to select 8m clock as rtc low power clock + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set 1 to select xtal clock as rtc low power clock + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set 1 to select xtal32k clock as low power clock + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set 1 to enable RTC low power clock + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt generate register + 0x28 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set 1 to generate cpu interrupt 0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt generate register + 0x2C + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set 1 to generate cpu interrupt 1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt generate register + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set 1 to generate cpu interrupt 2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt generate register + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set 1 to generate cpu interrupt 3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x38 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set 1 to force power up RSA memory. This bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set 1 to force power down RSA memory. This bit has the highest priority. + 2 + 1 + read-write + + + + + EDMA_CTRL + edma clcok and reset register + 0x3C + 0x20 + 0x00000001 + + + EDMA_CLK_ON + Set 1 to enable EDMA clock. + 0 + 1 + read-write + + + EDMA_RESET + Set 1 to let EDMA reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + cache control register + 0x40 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + Set 1 to enable icache clock + 0 + 1 + read-write + + + ICACHE_RESET + Set 1 to let icache reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + Set 1 to enable dcache clock + 2 + 1 + read-write + + + DCACHE_RESET + Set 1 to let dcache reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + 0x44 + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set 1 to enable the SPI manual encrypt. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set 1 to enable download DB encrypt. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set 1 to enable download G0CB decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set 1 to enable download manual encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + fast memory config register + 0x48 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set 1 to start the CRC of RTC memory + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC.1 means finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + reserved + 0x4C + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + eco register + 0x50 + 0x20 + + + REDUNDANT_ECO_DRIVE + reg_redundant_eco_drive + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + reg_redundant_eco_result + 1 + 1 + read-only + + + + + CLOCK_GATE + clock gating register + 0x54 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + SYSCLK_CONF + system clock config register + 0x58 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select soc clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read xtal frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + reg_clk_div_en + 19 + 1 + read-only + + + + + MEM_PVT + mem pvt register + 0x5C + 0x20 + 0x00000003 + + + MEM_PATH_LEN + reg_mem_path_len + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + reg_mem_err_cnt_clr + 4 + 1 + write-only + + + MONITOR_EN + reg_mem_pvt_monitor_en + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + reg_mem_timing_err_cnt + 6 + 16 + read-only + + + MEM_VT_SEL + reg_mem_vt_sel + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + mem pvt register + 0x60 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + reg_comb_path_len_lvt + 0 + 6 + read-write + + + COMB_ERR_CNT_CLR_LVT + reg_comb_err_cnt_clr_lvt + 6 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + reg_comb_pvt_monitor_en_lvt + 7 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + mem pvt register + 0x64 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + reg_comb_path_len_nvt + 0 + 6 + read-write + + + COMB_ERR_CNT_CLR_NVT + reg_comb_err_cnt_clr_nvt + 6 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + reg_comb_pvt_monitor_en_nvt + 7 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + mem pvt register + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + reg_comb_path_len_hvt + 0 + 6 + read-write + + + COMB_ERR_CNT_CLR_HVT + reg_comb_err_cnt_clr_hvt + 6 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + reg_comb_pvt_monitor_en_hvt + 7 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + mem pvt register + 0x6C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + reg_comb_timing_err_cnt_lvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + mem pvt register + 0x70 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + reg_comb_timing_err_cnt_nvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + mem pvt register + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + reg_comb_timing_err_cnt_hvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + mem pvt register + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + reg_comb_timing_err_cnt_lvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + mem pvt register + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + reg_comb_timing_err_cnt_nvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + mem pvt register + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + reg_comb_timing_err_cnt_hvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + mem pvt register + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + reg_comb_timing_err_cnt_lvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + mem pvt register + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + reg_comb_timing_err_cnt_nvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + mem pvt register + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + reg_comb_timing_err_cnt_hvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + mem pvt register + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + reg_comb_timing_err_cnt_lvt_site3 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + mem pvt register + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + reg_comb_timing_err_cnt_nvt_site3 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + mem pvt register + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + reg_comb_timing_err_cnt_hvt_site3 + 0 + 16 + read-only + + + + + REG_DATE + Version register + 0xFFC + 0x20 + 0x02108190 + + + SYSTEM_REG_DATE + reg_system_reg_date + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x78 + registers + + + SYSTIMER_TARGET0 + 26 + + + SYSTIMER_TARGET1 + 27 + + + SYSTIMER_TARGET2 + 28 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02012251 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x6001F000 + + 0x0 + 0x68 + registers + + + TG0_T0_LEVEL + 23 + + + TG0_WDT_LEVEL + 24 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer $x current value, high 22 bits + 0x8 + 0x20 + + + T0_HI + After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter +of timer 0 can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG + 0xC + 0x20 + + + T0_UPDATE + After writing 0 or 1 to TIMG_T31UPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer $x alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer 0 alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer $x alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer 0 alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer $x reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer 0 time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer $x reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer 0 time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + +Write any value to trigger a timer 0 time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk; 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + Reserved + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + Reserved + 15 + 1 + read-only + + + RTC_CALI_MAX + Reserved + 16 + 15 + read-write + + + RTC_CALI_START + Reserved + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + Reserved + 0 + 1 + read-only + + + RTC_CALI_VALUE + Reserved + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 1 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02006191 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x60000000 + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 17 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x0000C060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 9 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 9 + 9 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 18 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 19 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 20 + 1 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 21 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow-control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x000026E0 + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 9 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 9 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00002200 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 9 + read-write + + + XON_CHAR + This register stores the Xon flow control char. + 9 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x000A0012 + + + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 9 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 16 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 26 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 27 + 1 + read-write + + + + + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 + 0x20 + 0x00080100 + + + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x6C + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x78 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + + + ID + This register is used to configure the uart_id. + 0 + 30 + read-write + + + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. + 30 + 1 + read-write + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 31 + 1 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60010000 + + UART1 + 18 + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x600CC000 + + 0x0 + 0x30 + registers + + + + 16 + 0x1 + PLAIN_MEM[%s] + The memory that stores plaintext + 0x0 + 0x8 + + + LINESIZE + XTS-AES line-size register + 0x40 + 0x20 + + + LINESIZE + This bit stores the line size parameter. 0: 16Byte, 1: 32Byte. + 0 + 1 + read-write + + + + + DESTINATION + XTS-AES destination register + 0x44 + 0x20 + + + DESTINATION + This bit stores the destination. 0: flash(default). 1: reserved. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + XTS-AES physical address register + 0x48 + 0x20 + + + PHYSICAL_ADDRESS + Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. + 0 + 30 + read-write + + + + + TRIGGER + XTS-AES trigger register + 0x4C + 0x20 + + + TRIGGER + Set this bit to start manual encryption calculation + 0 + 1 + write-only + + + + + RELEASE + XTS-AES release register + 0x50 + 0x20 + + + RELEASE + Set this bit to release the manual encrypted result, after that the result will be visible to spi + 0 + 1 + write-only + + + + + DESTROY + XTS-AES destroy register + 0x54 + 0x20 + + + DESTROY + Set this bit to destroy XTS-AES result. + 0 + 1 + write-only + + + + + STATE + XTS-AES status register + 0x58 + 0x20 + + + STATE + Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + DATE + XTS-AES version control register + 0x5C + 0x20 + 0x20200623 + + + DATE + Those bits stores the version information of XTS-AES. + 0 + 30 + read-write + + + + + + + diff --git a/tools/ide-debug/svd/esp32c3.svd b/tools/ide-debug/svd/esp32c3.svd new file mode 100644 index 0000000..aea2a98 --- /dev/null +++ b/tools/ide-debug/svd/esp32c3.svd @@ -0,0 +1,36098 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-C3 + ESP32-C3 + 10 + 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xBC + registers + + + AES + 48 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + APB_CTRL + Advanced Peripheral Bus Controller + APB_CTRL + 0x60026000 + + 0x0 + 0xA0 + registers + + + + SYSCLK_CONF + APB_CTRL_SYSCLK_CONF_REG + 0x0 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + reg_pre_div_cnt + 0 + 10 + read-write + + + CLK_320M_EN + reg_clk_320m_en + 10 + 1 + read-write + + + CLK_EN + reg_clk_en + 11 + 1 + read-write + + + RST_TICK_CNT + reg_rst_tick_cnt + 12 + 1 + read-write + + + + + TICK_CONF + APB_CTRL_TICK_CONF_REG + 0x4 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + reg_xtal_tick_num + 0 + 8 + read-write + + + CK8M_TICK_NUM + reg_ck8m_tick_num + 8 + 8 + read-write + + + TICK_ENABLE + reg_tick_enable + 16 + 1 + read-write + + + + + CLK_OUT_EN + APB_CTRL_CLK_OUT_EN_REG + 0x8 + 0x20 + 0x000007FF + + + CLK20_OEN + reg_clk20_oen + 0 + 1 + read-write + + + CLK22_OEN + reg_clk22_oen + 1 + 1 + read-write + + + CLK44_OEN + reg_clk44_oen + 2 + 1 + read-write + + + CLK_BB_OEN + reg_clk_bb_oen + 3 + 1 + read-write + + + CLK80_OEN + reg_clk80_oen + 4 + 1 + read-write + + + CLK160_OEN + reg_clk160_oen + 5 + 1 + read-write + + + CLK_320M_OEN + reg_clk_320m_oen + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + reg_clk_adc_inf_oen + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + reg_clk_dac_cpu_oen + 8 + 1 + read-write + + + CLK40X_BB_OEN + reg_clk40x_bb_oen + 9 + 1 + read-write + + + CLK_XTAL_OEN + reg_clk_xtal_oen + 10 + 1 + read-write + + + + + WIFI_BB_CFG + APB_CTRL_WIFI_BB_CFG_REG + 0xC + 0x20 + + + WIFI_BB_CFG + reg_wifi_bb_cfg + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + APB_CTRL_WIFI_BB_CFG_2_REG + 0x10 + 0x20 + + + WIFI_BB_CFG_2 + reg_wifi_bb_cfg_2 + 0 + 32 + read-write + + + + + WIFI_CLK_EN + APB_CTRL_WIFI_CLK_EN_REG + 0x14 + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + reg_wifi_clk_en + 0 + 32 + read-write + + + + + WIFI_RST_EN + APB_CTRL_WIFI_RST_EN_REG + 0x18 + 0x20 + + + WIFI_RST + reg_wifi_rst + 0 + 32 + read-write + + + + + HOST_INF_SEL + APB_CTRL_HOST_INF_SEL_REG + 0x1C + 0x20 + + + PERI_IO_SWAP + reg_peri_io_swap + 0 + 8 + read-write + + + + + EXT_MEM_PMS_LOCK + APB_CTRL_EXT_MEM_PMS_LOCK_REG + 0x20 + 0x20 + + + EXT_MEM_PMS_LOCK + reg_ext_mem_pms_lock + 0 + 1 + read-write + + + + + FLASH_ACE0_ATTR + APB_CTRL_FLASH_ACE0_ATTR_REG + 0x28 + 0x20 + 0x00000003 + + + FLASH_ACE0_ATTR + reg_flash_ace0_attr + 0 + 2 + read-write + + + + + FLASH_ACE1_ATTR + APB_CTRL_FLASH_ACE1_ATTR_REG + 0x2C + 0x20 + 0x00000003 + + + FLASH_ACE1_ATTR + reg_flash_ace1_attr + 0 + 2 + read-write + + + + + FLASH_ACE2_ATTR + APB_CTRL_FLASH_ACE2_ATTR_REG + 0x30 + 0x20 + 0x00000003 + + + FLASH_ACE2_ATTR + reg_flash_ace2_attr + 0 + 2 + read-write + + + + + FLASH_ACE3_ATTR + APB_CTRL_FLASH_ACE3_ATTR_REG + 0x34 + 0x20 + 0x00000003 + + + FLASH_ACE3_ATTR + reg_flash_ace3_attr + 0 + 2 + read-write + + + + + FLASH_ACE0_ADDR + APB_CTRL_FLASH_ACE0_ADDR_REG + 0x38 + 0x20 + + + S + reg_flash_ace0_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE1_ADDR + APB_CTRL_FLASH_ACE1_ADDR_REG + 0x3C + 0x20 + 0x00400000 + + + S + reg_flash_ace1_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE2_ADDR + APB_CTRL_FLASH_ACE2_ADDR_REG + 0x40 + 0x20 + 0x00800000 + + + S + reg_flash_ace2_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE3_ADDR + APB_CTRL_FLASH_ACE3_ADDR_REG + 0x44 + 0x20 + 0x00C00000 + + + S + reg_flash_ace3_addr_s + 0 + 32 + read-write + + + + + FLASH_ACE0_SIZE + APB_CTRL_FLASH_ACE0_SIZE_REG + 0x48 + 0x20 + 0x00000400 + + + FLASH_ACE0_SIZE + reg_flash_ace0_size + 0 + 13 + read-write + + + + + FLASH_ACE1_SIZE + APB_CTRL_FLASH_ACE1_SIZE_REG + 0x4C + 0x20 + 0x00000400 + + + FLASH_ACE1_SIZE + reg_flash_ace1_size + 0 + 13 + read-write + + + + + FLASH_ACE2_SIZE + APB_CTRL_FLASH_ACE2_SIZE_REG + 0x50 + 0x20 + 0x00000400 + + + FLASH_ACE2_SIZE + reg_flash_ace2_size + 0 + 13 + read-write + + + + + FLASH_ACE3_SIZE + APB_CTRL_FLASH_ACE3_SIZE_REG + 0x54 + 0x20 + 0x00000400 + + + FLASH_ACE3_SIZE + reg_flash_ace3_size + 0 + 13 + read-write + + + + + SPI_MEM_PMS_CTRL + APB_CTRL_SPI_MEM_PMS_CTRL_REG + 0x88 + 0x20 + + + SPI_MEM_REJECT_INT + reg_spi_mem_reject_int + 0 + 1 + read-only + + + SPI_MEM_REJECT_CLR + reg_spi_mem_reject_clr + 1 + 1 + write-only + + + SPI_MEM_REJECT_CDE + reg_spi_mem_reject_cde + 2 + 5 + read-only + + + + + SPI_MEM_REJECT_ADDR + APB_CTRL_SPI_MEM_REJECT_ADDR_REG + 0x8C + 0x20 + + + SPI_MEM_REJECT_ADDR + reg_spi_mem_reject_addr + 0 + 32 + read-only + + + + + SDIO_CTRL + APB_CTRL_SDIO_CTRL_REG + 0x90 + 0x20 + + + SDIO_WIN_ACCESS_EN + reg_sdio_win_access_en + 0 + 1 + read-write + + + + + REDCY_SIG0 + APB_CTRL_REDCY_SIG0_REG_REG + 0x94 + 0x20 + + + REDCY_SIG0 + reg_redcy_sig0 + 0 + 31 + read-write + + + REDCY_ANDOR + reg_redcy_andor + 31 + 1 + read-only + + + + + REDCY_SIG1 + APB_CTRL_REDCY_SIG1_REG_REG + 0x98 + 0x20 + + + REDCY_SIG1 + reg_redcy_sig1 + 0 + 31 + read-write + + + REDCY_NANDOR + reg_redcy_nandor + 31 + 1 + read-only + + + + + FRONT_END_MEM_PD + APB_CTRL_FRONT_END_MEM_PD_REG + 0x9C + 0x20 + 0x00000015 + + + AGC_MEM_FORCE_PU + reg_agc_mem_force_pu + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + reg_agc_mem_force_pd + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + reg_pbus_mem_force_pu + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + reg_pbus_mem_force_pd + 3 + 1 + read-write + + + DC_MEM_FORCE_PU + reg_dc_mem_force_pu + 4 + 1 + read-write + + + DC_MEM_FORCE_PD + reg_dc_mem_force_pd + 5 + 1 + read-write + + + + + RETENTION_CTRL + APB_CTRL_RETENTION_CTRL_REG + 0xA0 + 0x20 + + + RETENTION_LINK_ADDR + reg_retention_link_addr + 0 + 27 + read-write + + + NOBYPASS_CPU_ISO_RST + reg_nobypass_cpu_iso_rst + 27 + 1 + read-write + + + + + CLKGATE_FORCE_ON + APB_CTRL_CLKGATE_FORCE_ON_REG + 0xA4 + 0x20 + 0x0000003F + + + ROM_CLKGATE_FORCE_ON + reg_rom_clkgate_force_on + 0 + 2 + read-write + + + SRAM_CLKGATE_FORCE_ON + reg_sram_clkgate_force_on + 2 + 4 + read-write + + + + + MEM_POWER_DOWN + APB_CTRL_MEM_POWER_DOWN_REG + 0xA8 + 0x20 + + + ROM_POWER_DOWN + reg_rom_power_down + 0 + 2 + read-write + + + SRAM_POWER_DOWN + reg_sram_power_down + 2 + 4 + read-write + + + + + MEM_POWER_UP + APB_CTRL_MEM_POWER_UP_REG + 0xAC + 0x20 + 0x0000003F + + + ROM_POWER_UP + reg_rom_power_up + 0 + 2 + read-write + + + SRAM_POWER_UP + reg_sram_power_up + 2 + 4 + read-write + + + + + RND_DATA + APB_CTRL_RND_DATA_REG + 0xB0 + 0x20 + + + RND_DATA + reg_rnd_data + 0 + 32 + read-only + + + + + PERI_BACKUP_CONFIG + APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + 0xB4 + 0x20 + 0x00006480 + + + PERI_BACKUP_FLOW_ERR + reg_peri_backup_flow_err + 1 + 2 + read-only + + + PERI_BACKUP_BURST_LIMIT + reg_peri_backup_burst_limit + 4 + 5 + read-write + + + PERI_BACKUP_TOUT_THRES + reg_peri_backup_tout_thres + 9 + 10 + read-write + + + PERI_BACKUP_SIZE + reg_peri_backup_size + 19 + 10 + read-write + + + PERI_BACKUP_START + reg_peri_backup_start + 29 + 1 + write-only + + + PERI_BACKUP_TO_MEM + reg_peri_backup_to_mem + 30 + 1 + read-write + + + PERI_BACKUP_ENA + reg_peri_backup_ena + 31 + 1 + read-write + + + + + PERI_BACKUP_APB_ADDR + APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + 0xB8 + 0x20 + + + BACKUP_APB_START_ADDR + reg_backup_apb_start_addr + 0 + 32 + read-write + + + + + PERI_BACKUP_MEM_ADDR + APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + 0xBC + 0x20 + + + BACKUP_MEM_START_ADDR + reg_backup_mem_start_addr + 0 + 32 + read-write + + + + + PERI_BACKUP_INT_RAW + APB_CTRL_PERI_BACKUP_INT_RAW_REG + 0xC0 + 0x20 + + + PERI_BACKUP_DONE_INT_RAW + reg_peri_backup_done_int_raw + 0 + 1 + read-only + + + PERI_BACKUP_ERR_INT_RAW + reg_peri_backup_err_int_raw + 1 + 1 + read-only + + + + + PERI_BACKUP_INT_ST + APB_CTRL_PERI_BACKUP_INT_ST_REG + 0xC4 + 0x20 + + + PERI_BACKUP_DONE_INT_ST + reg_peri_backup_done_int_st + 0 + 1 + read-only + + + PERI_BACKUP_ERR_INT_ST + reg_peri_backup_err_int_st + 1 + 1 + read-only + + + + + PERI_BACKUP_INT_ENA + APB_CTRL_PERI_BACKUP_INT_ENA_REG + 0xC8 + 0x20 + + + PERI_BACKUP_DONE_INT_ENA + reg_peri_backup_done_int_ena + 0 + 1 + read-write + + + PERI_BACKUP_ERR_INT_ENA + reg_peri_backup_err_int_ena + 1 + 1 + read-write + + + + + PERI_BACKUP_INT_CLR + APB_CTRL_PERI_BACKUP_INT_CLR_REG + 0xD0 + 0x20 + + + PERI_BACKUP_DONE_INT_CLR + reg_peri_backup_done_int_clr + 0 + 1 + write-only + + + PERI_BACKUP_ERR_INT_CLR + reg_peri_backup_err_int_clr + 1 + 1 + write-only + + + + + DATE + APB_CTRL_DATE_REG + 0x3FC + 0x20 + 0x02007210 + + + DATE + reg_dateVersion control + 0 + 32 + read-write + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x68 + registers + + + APB_ADC + 43 + + + + CTRL + digital saradc configure register + 0x0 + 0x20 + 0x40038240 + + + SARADC_START_FORCE + select software enable saradc sample + 0 + 1 + read-write + + + SARADC_START + software enable saradc sample + 1 + 1 + read-write + + + SARADC_SAR_CLK_GATED + SAR clock gated + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 3 + read-write + + + SARADC_SAR_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + digital saradc configure register + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable max meas num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + digital saradc configure register + 0x8 + 0x20 + + + APB_SARADC_FILTER_FACTOR1 + Factor of saradc filter1 + 26 + 3 + read-write + + + APB_SARADC_FILTER_FACTOR0 + Factor of saradc filter0 + 29 + 3 + read-write + + + + + FSM_WAIT + digital saradc configure register + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + saradc_xpd_wait + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + saradc_rstb_wait + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + saradc_standby_wait + 16 + 8 + read-write + + + + + SAR1_STATUS + digital saradc configure register + 0x10 + 0x20 + + + SARADC_SAR1_STATUS + saradc1 status about data and channel + 0 + 32 + read-only + + + + + SAR2_STATUS + digital saradc configure register + 0x14 + 0x20 + + + SARADC_SAR2_STATUS + saradc2 status about data and channel + 0 + 32 + read-only + + + + + SAR_PATT_TAB1 + digital saradc configure register + 0x18 + 0x20 + + + SARADC_SAR_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR_PATT_TAB2 + digital saradc configure register + 0x1C + 0x20 + + + SARADC_SAR_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + ONETIME_SAMPLE + digital saradc configure register + 0x20 + 0x20 + 0x1A000000 + + + SARADC_ONETIME_ATTEN + configure onetime atten + 23 + 2 + read-write + + + SARADC_ONETIME_CHANNEL + configure onetime channel + 25 + 4 + read-write + + + SARADC_ONETIME_START + trigger adc onetime sample + 29 + 1 + read-write + + + SARADC2_ONETIME_SAMPLE + enable adc2 onetime sample + 30 + 1 + read-write + + + SARADC1_ONETIME_SAMPLE + enable adc1 onetime sample + 31 + 1 + read-write + + + + + ARB_CTRL + digital saradc configure register + 0x24 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + digital saradc configure register + 0x28 + 0x20 + 0x03740000 + + + APB_SARADC_FILTER_CHANNEL1 + configure filter1 to adc channel + 18 + 4 + read-write + + + APB_SARADC_FILTER_CHANNEL0 + configure filter0 to adc channel + 22 + 4 + read-write + + + APB_SARADC_FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1DATA_STATUS + digital saradc configure register + 0x2C + 0x20 + + + APB_SARADC1_DATA + saradc1 data + 0 + 17 + read-only + + + + + SAR2DATA_STATUS + digital saradc configure register + 0x30 + 0x20 + + + APB_SARADC2_DATA + saradc2 data + 0 + 17 + read-only + + + + + THRES0_CTRL + digital saradc configure register + 0x34 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES0_CHANNEL + configure thres0 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES0_HIGH + saradc thres0 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES0_LOW + saradc thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + digital saradc configure register + 0x38 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES1_CHANNEL + configure thres1 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES1_HIGH + saradc thres1 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES1_LOW + saradc thres1 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + digital saradc configure register + 0x3C + 0x20 + + + APB_SARADC_THRES_ALL_EN + enable thres to all channel + 27 + 1 + read-write + + + APB_SARADC_THRES1_EN + enable thres1 + 30 + 1 + read-write + + + APB_SARADC_THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + digital saradc int register + 0x40 + 0x20 + + + APB_SARADC_THRES1_LOW_INT_ENA + saradc thres1 low interrupt enable + 26 + 1 + read-write + + + APB_SARADC_THRES0_LOW_INT_ENA + saradc thres0 low interrupt enable + 27 + 1 + read-write + + + APB_SARADC_THRES1_HIGH_INT_ENA + saradc thres1 high interrupt enable + 28 + 1 + read-write + + + APB_SARADC_THRES0_HIGH_INT_ENA + saradc thres0 high interrupt enable + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + saradc2 done interrupt enable + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + saradc1 done interrupt enable + 31 + 1 + read-write + + + + + INT_RAW + digital saradc int register + 0x44 + 0x20 + + + APB_SARADC_THRES1_LOW_INT_RAW + saradc thres1 low interrupt raw + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_RAW + saradc thres0 low interrupt raw + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_RAW + saradc thres1 high interrupt raw + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_RAW + saradc thres0 high interrupt raw + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + saradc2 done interrupt raw + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + saradc1 done interrupt raw + 31 + 1 + read-only + + + + + INT_ST + digital saradc int register + 0x48 + 0x20 + + + APB_SARADC_THRES1_LOW_INT_ST + saradc thres1 low interrupt state + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_ST + saradc thres0 low interrupt state + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_ST + saradc thres1 high interrupt state + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_ST + saradc thres0 high interrupt state + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + saradc2 done interrupt state + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + saradc1 done interrupt state + 31 + 1 + read-only + + + + + INT_CLR + digital saradc int register + 0x4C + 0x20 + + + APB_SARADC_THRES1_LOW_INT_CLR + saradc thres1 low interrupt clear + 26 + 1 + write-only + + + APB_SARADC_THRES0_LOW_INT_CLR + saradc thres0 low interrupt clear + 27 + 1 + write-only + + + APB_SARADC_THRES1_HIGH_INT_CLR + saradc thres1 high interrupt clear + 28 + 1 + write-only + + + APB_SARADC_THRES0_HIGH_INT_CLR + saradc thres0 high interrupt clear + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + saradc2 done interrupt clear + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + saradc1 done interrupt clear + 31 + 1 + write-only + + + + + DMA_CONF + digital saradc configure register + 0x50 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + CLKM_CONF + digital saradc configure register + 0x54 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + reg clk en + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_TSENS_CTRL + digital tsens configure register + 0x58 + 0x20 + 0x00018000 + + + TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + TSENS_PU + temperature sensor power up + 22 + 1 + read-write + + + + + TSENS_CTRL2 + digital tsens configure register + 0x5C + 0x20 + 0x00004002 + + + TSENS_XPD_WAIT + the time that power up tsens need wait + 0 + 12 + read-write + + + TSENS_XPD_FORCE + force power up tsens + 12 + 2 + read-write + + + TSENS_CLK_INV + inv tsens clk + 14 + 1 + read-write + + + TSENS_CLK_SEL + tsens clk select + 15 + 1 + read-write + + + + + CALI + digital saradc configure register + 0x60 + 0x20 + 0x00008000 + + + APB_SARADC_CALI_CFG + saradc cali factor + 0 + 17 + read-write + + + + + CTRL_DATE + version + 0x3FC + 0x20 + 0x02007171 + + + DATE + version + 0 + 32 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x600CE000 + + 0x0 + 0xA0 + registers + + + ASSIST_DEBUG + 54 + + + + C0RE_0_MONTR_ENA + ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + reg_core_0_area_dram0_0_rd_ena + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + reg_core_0_area_dram0_0_wr_ena + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + reg_core_0_area_dram0_1_rd_ena + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + reg_core_0_area_dram0_1_wr_ena + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + reg_core_0_area_pif_0_rd_ena + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + reg_core_0_area_pif_0_wr_ena + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + reg_core_0_area_pif_1_rd_ena + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + reg_core_0_area_pif_1_wr_ena + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + reg_core_0_sp_spill_min_ena + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + reg_core_0_sp_spill_max_ena + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + reg_core_0_iram0_exception_monitor_ena + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + reg_core_0_dram0_exception_monitor_ena + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + ASSIST_DEBUG_CORE_0_INTR_RAW_REG + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + reg_core_0_area_dram0_0_rd_raw + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + reg_core_0_area_dram0_0_wr_raw + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + reg_core_0_area_dram0_1_rd_raw + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + reg_core_0_area_dram0_1_wr_raw + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + reg_core_0_area_pif_0_rd_raw + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + reg_core_0_area_pif_0_wr_raw + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + reg_core_0_area_pif_1_rd_raw + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + reg_core_0_area_pif_1_wr_raw + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + reg_core_0_sp_spill_min_raw + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + reg_core_0_sp_spill_max_raw + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + reg_core_0_iram0_exception_monitor_raw + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + reg_core_0_dram0_exception_monitor_raw + 11 + 1 + read-only + + + + + CORE_0_INTR_ENA + ASSIST_DEBUG_CORE_0_INTR_ENA_REG + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_INTR_ENA + reg_core_0_area_dram0_0_rd_intr_ena + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_INTR_ENA + reg_core_0_area_dram0_0_wr_intr_ena + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_INTR_ENA + reg_core_0_area_dram0_1_rd_intr_ena + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_INTR_ENA + reg_core_0_area_dram0_1_wr_intr_ena + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_INTR_ENA + reg_core_0_area_pif_0_rd_intr_ena + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_INTR_ENA + reg_core_0_area_pif_0_wr_intr_ena + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_INTR_ENA + reg_core_0_area_pif_1_rd_intr_ena + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_INTR_ENA + reg_core_0_area_pif_1_wr_intr_ena + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_INTR_ENA + reg_core_0_sp_spill_min_intr_ena + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_INTR_ENA + reg_core_0_sp_spill_max_intr_ena + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + reg_core_0_iram0_exception_monitor_ena + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + reg_core_0_dram0_exception_monitor_ena + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + ASSIST_DEBUG_CORE_0_INTR_CLR_REG + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + reg_core_0_area_dram0_0_rd_clr + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_CLR + reg_core_0_area_dram0_0_wr_clr + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_CLR + reg_core_0_area_dram0_1_rd_clr + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_CLR + reg_core_0_area_dram0_1_wr_clr + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_CLR + reg_core_0_area_pif_0_rd_clr + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_CLR + reg_core_0_area_pif_0_wr_clr + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_CLR + reg_core_0_area_pif_1_rd_clr + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_CLR + reg_core_0_area_pif_1_wr_clr + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_CLR + reg_core_0_sp_spill_min_clr + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_CLR + reg_core_0_sp_spill_max_clr + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + reg_core_0_iram0_exception_monitor_clr + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + reg_core_0_dram0_exception_monitor_clr + 11 + 1 + read-write + + + + + CORE_0_AREA_DRAM0_0_MIN + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + reg_core_0_area_dram0_0_min + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + reg_core_0_area_dram0_0_max + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + reg_core_0_area_dram0_1_min + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + reg_core_0_area_dram0_1_max + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + reg_core_0_area_pif_0_min + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + reg_core_0_area_pif_0_max + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + reg_core_0_area_pif_1_min + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + reg_core_0_area_pif_1_max + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + ASSIST_DEBUG_CORE_0_AREA_PC_REG + 0x30 + 0x20 + + + CORE_0_AREA_PC + reg_core_0_area_pc + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + ASSIST_DEBUG_CORE_0_AREA_SP_REG + 0x34 + 0x20 + + + CORE_0_AREA_SP + reg_core_0_area_sp + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + ASSIST_DEBUG_CORE_0_SP_MIN_REG + 0x38 + 0x20 + + + CORE_0_SP_MIN + reg_core_0_sp_min + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + ASSIST_DEBUG_CORE_0_SP_MAX_REG + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + reg_core_0_sp_max + 0 + 32 + read-write + + + + + CORE_0_SP_PC + ASSIST_DEBUG_CORE_0_SP_PC_REG + 0x40 + 0x20 + + + CORE_0_SP_PC + reg_core_0_sp_pc + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + ASSIST_DEBUG_CORE_0_RCD_EN_REG + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + reg_core_0_rcd_recorden + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + reg_core_0_rcd_pdebugen + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + reg_core_0_rcd_pdebugpc + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + reg_core_0_rcd_pdebugsp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG + 0x68 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG + 0x6C + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + LOG_SETTING + ASSIST_DEBUG_LOG_SETTING + 0x70 + 0x20 + 0x00000080 + + + LOG_ENA + reg_log_ena + 0 + 3 + read-write + + + LOG_MODE + reg_log_mode + 3 + 4 + read-write + + + LOG_MEM_LOOP_ENABLE + reg_log_mem_loop_enable + 7 + 1 + read-write + + + + + LOG_DATA_0 + ASSIST_DEBUG_LOG_DATA_0_REG + 0x74 + 0x20 + + + LOG_DATA_0 + reg_log_data_0 + 0 + 32 + read-write + + + + + LOG_DATA_MASK + ASSIST_DEBUG_LOG_DATA_MASK_REG + 0x78 + 0x20 + + + LOG_DATA_SIZE + reg_log_data_size + 0 + 16 + read-write + + + + + LOG_MIN + ASSIST_DEBUG_LOG_MIN_REG + 0x7C + 0x20 + + + LOG_MIN + reg_log_min + 0 + 32 + read-write + + + + + LOG_MAX + ASSIST_DEBUG_LOG_MAX_REG + 0x80 + 0x20 + + + LOG_MAX + reg_log_max + 0 + 32 + read-write + + + + + LOG_MEM_START + ASSIST_DEBUG_LOG_MEM_START_REG + 0x84 + 0x20 + + + LOG_MEM_START + reg_log_mem_start + 0 + 32 + read-write + + + + + LOG_MEM_END + ASSIST_DEBUG_LOG_MEM_END_REG + 0x88 + 0x20 + + + LOG_MEM_END + reg_log_mem_end + 0 + 32 + read-write + + + + + LOG_MEM_WRITING_ADDR + ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG + 0x8C + 0x20 + + + LOG_MEM_WRITING_ADDR + reg_log_mem_writing_addr + 0 + 32 + read-only + + + + + LOG_MEM_FULL_FLAG + ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG + 0x90 + 0x20 + + + LOG_MEM_FULL_FLAG + reg_log_mem_full_flag + 0 + 1 + read-only + + + CLR_LOG_MEM_FULL_FLAG + reg_clr_log_mem_full_flag + 1 + 1 + read-write + + + + + C0RE_0_LASTPC_BEFORE_EXCEPTION + ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION + 0x94 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + reg_core_0_lastpc_before_exc + 0 + 32 + read-only + + + + + C0RE_0_DEBUG_MODE + ASSIST_DEBUG_C0RE_0_DEBUG_MODE + 0x98 + 0x20 + + + CORE_0_DEBUG_MODE + reg_core_0_debug_mode + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + reg_core_0_debug_module_active + 1 + 1 + read-only + + + + + DATE + ASSIST_DEBUG_DATE_REG + 0x1FC + 0x20 + 0x02008010 + + + ASSIST_DEBUG_DATE + reg_assist_debug_date + 0 + 28 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x174 + registers + + + DMA_CH0 + 44 + + + DMA_CH1 + 45 + + + DMA_CH2 + 46 + + + + INT_RAW_CH0 + DMA_INT_RAW_CH0_REG. + 0x0 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 8 + 1 + read-only + + + INFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 9 + 1 + read-only + + + INFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 10 + 1 + read-only + + + OUTFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 11 + 1 + read-only + + + OUTFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 12 + 1 + read-only + + + + + INT_ST_CH0 + DMA_INT_ST_CH0_REG. + 0x4 + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_OVF + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_UDF + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-only + + + OUTFIFO_OVF + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-only + + + OUTFIFO_UDF + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-only + + + + + INT_ENA_CH0 + DMA_INT_ENA_CH0_REG. + 0x8 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_OVF + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_UDF + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-write + + + OUTFIFO_OVF + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-write + + + OUTFIFO_UDF + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-write + + + + + INT_CLR_CH0 + DMA_INT_CLR_CH0_REG. + 0xC + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 3 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 4 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_OVF + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_UDF + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + write-only + + + OUTFIFO_OVF + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + write-only + + + OUTFIFO_UDF + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + write-only + + + + + INT_RAW_CH1 + DMA_INT_RAW_CH1_REG. + 0x10 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1. + 8 + 1 + read-only + + + INFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow. + 9 + 1 + read-only + + + INFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow. + 10 + 1 + read-only + + + OUTFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow. + 11 + 1 + read-only + + + OUTFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow. + 12 + 1 + read-only + + + + + INT_ST_CH1 + DMA_INT_ST_CH1_REG. + 0x14 + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_OVF + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_UDF + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-only + + + OUTFIFO_OVF + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-only + + + OUTFIFO_UDF + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-only + + + + + INT_ENA_CH1 + DMA_INT_ENA_CH1_REG. + 0x18 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_OVF + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_UDF + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-write + + + OUTFIFO_OVF + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-write + + + OUTFIFO_UDF + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-write + + + + + INT_CLR_CH1 + DMA_INT_CLR_CH1_REG. + 0x1C + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 3 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 4 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_OVF + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_UDF + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + write-only + + + OUTFIFO_OVF + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + write-only + + + OUTFIFO_UDF + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + write-only + + + + + INT_RAW_CH2 + DMA_INT_RAW_CH2_REG. + 0x20 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2. + 8 + 1 + read-only + + + INFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow. + 9 + 1 + read-only + + + INFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow. + 10 + 1 + read-only + + + OUTFIFO_OVF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow. + 11 + 1 + read-only + + + OUTFIFO_UDF + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow. + 12 + 1 + read-only + + + + + INT_ST_CH2 + DMA_INT_ST_CH2_REG. + 0x24 + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_OVF + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_UDF + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-only + + + OUTFIFO_OVF + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-only + + + OUTFIFO_UDF + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-only + + + + + INT_ENA_CH2 + DMA_INT_ENA_CH2_REG. + 0x28 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 3 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 4 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_OVF + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_UDF + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + read-write + + + OUTFIFO_OVF + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + read-write + + + OUTFIFO_UDF + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + read-write + + + + + INT_CLR_CH2 + DMA_INT_CLR_CH2_REG. + 0x2C + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 3 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 4 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 5 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 6 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_OVF + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_UDF + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 10 + 1 + write-only + + + OUTFIFO_OVF + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 11 + 1 + write-only + + + OUTFIFO_UDF + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 12 + 1 + write-only + + + + + AHB_TEST + DMA_AHB_TEST_REG. + 0x40 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + DMA_MISC_CONF_REG. + 0x44 + 0x20 + + + AHBM_RST_INTER + Set this bit, then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + reg_clk_en + 3 + 1 + read-write + + + + + DATE + DMA_DATE_REG. + 0x48 + 0x20 + 0x02008250 + + + DATE + register version. + 0 + 32 + read-write + + + + + IN_CONF0_CH0 + DMA_IN_CONF0_CH0_REG. + 0x70 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + IN_CONF1_CH0 + DMA_IN_CONF1_CH0_REG. + 0x74 + 0x20 + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + INFIFO_STATUS_CH0 + DMA_INFIFO_STATUS_CH0_REG. + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 27 + 1 + read-only + + + + + IN_POP_CH0 + DMA_IN_POP_CH0_REG. + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + IN_LINK_CH0 + DMA_IN_LINK_CH0_REG. + 0x80 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_STATE_CH0 + DMA_IN_STATE_CH0_REG. + 0x84 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH0 + DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH0 + DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + IN_DSCR_CH0 + DMA_IN_DSCR_CH0_REG. + 0x90 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH0 + DMA_IN_DSCR_BF0_CH0_REG. + 0x94 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH0 + DMA_IN_DSCR_BF1_CH0_REG. + 0x98 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + IN_PRI_CH0 + DMA_IN_PRI_CH0_REG. + 0x9C + 0x20 + + + RX_PRI + The priority of Rx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + IN_PERI_SEL_CH0 + DMA_IN_PERI_SEL_CH0_REG. + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + OUT_CONF0_CH0 + DMA_OUT_CONF0_CH0_REG. + 0xD0 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + OUT_CONF1_CH0 + DMA_OUT_CONF1_CH0_REG. + 0xD4 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + OUTFIFO_STATUS_CH0 + DMA_OUTFIFO_STATUS_CH0_REG. + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + + + OUT_PUSH_CH0 + DMA_OUT_PUSH_CH0_REG. + 0xDC + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + OUT_LINK_CH0 + DMA_OUT_LINK_CH0_REG. + 0xE0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_STATE_CH0 + DMA_OUT_STATE_CH0_REG. + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + OUT_EOF_DES_ADDR_CH0 + DMA_OUT_EOF_DES_ADDR_CH0_REG. + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR_CH0 + DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + OUT_DSCR_CH0 + DMA_OUT_DSCR_CH0_REG. + 0xF0 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH0 + DMA_OUT_DSCR_BF0_CH0_REG. + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH0 + DMA_OUT_DSCR_BF1_CH0_REG. + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + OUT_PRI_CH0 + DMA_OUT_PRI_CH0_REG. + 0xFC + 0x20 + + + TX_PRI + The priority of Tx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + OUT_PERI_SEL_CH0 + DMA_OUT_PERI_SEL_CH0_REG. + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + IN_CONF0_CH1 + DMA_IN_CONF0_CH1_REG. + 0x130 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + IN_CONF1_CH1 + DMA_IN_CONF1_CH1_REG. + 0x134 + 0x20 + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + INFIFO_STATUS_CH1 + DMA_INFIFO_STATUS_CH1_REG. + 0x138 + 0x20 + 0x07800003 + + + INFIFO_FULL + L1 Rx FIFO full signal for Rx channel 1. + 0 + 1 + read-only + + + INFIFO_EMPTY + L1 Rx FIFO empty signal for Rx channel 1. + 1 + 1 + read-only + + + INFIFO_CNT + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 27 + 1 + read-only + + + + + IN_POP_CH1 + DMA_IN_POP_CH1_REG. + 0x13C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + IN_LINK_CH1 + DMA_IN_LINK_CH1_REG. + 0x140 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_STATE_CH1 + DMA_IN_STATE_CH1_REG. + 0x144 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH1 + DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. + 0x148 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH1 + DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. + 0x14C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + IN_DSCR_CH1 + DMA_IN_DSCR_CH1_REG. + 0x150 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH1 + DMA_IN_DSCR_BF0_CH1_REG. + 0x154 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH1 + DMA_IN_DSCR_BF1_CH1_REG. + 0x158 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + IN_PRI_CH1 + DMA_IN_PRI_CH1_REG. + 0x15C + 0x20 + + + RX_PRI + The priority of Rx channel 1. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + IN_PERI_SEL_CH1 + DMA_IN_PERI_SEL_CH1_REG. + 0x160 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + OUT_CONF0_CH1 + DMA_OUT_CONF0_CH1_REG. + 0x190 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + OUT_CONF1_CH1 + DMA_OUT_CONF1_CH1_REG. + 0x194 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + OUTFIFO_STATUS_CH1 + DMA_OUTFIFO_STATUS_CH1_REG. + 0x198 + 0x20 + 0x07800002 + + + OUTFIFO_FULL + L1 Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + OUTFIFO_EMPTY + L1 Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + OUTFIFO_CNT + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + + + OUT_PUSH_CH1 + DMA_OUT_PUSH_CH1_REG. + 0x19C + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + OUT_LINK_CH1 + DMA_OUT_LINK_CH1_REG. + 0x1A0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_STATE_CH1 + DMA_OUT_STATE_CH1_REG. + 0x1A4 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + OUT_EOF_DES_ADDR_CH1 + DMA_OUT_EOF_DES_ADDR_CH1_REG. + 0x1A8 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR_CH1 + DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. + 0x1AC + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + OUT_DSCR_CH1 + DMA_OUT_DSCR_CH1_REG. + 0x1B0 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH1 + DMA_OUT_DSCR_BF0_CH1_REG. + 0x1B4 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH1 + DMA_OUT_DSCR_BF1_CH1_REG. + 0x1B8 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + OUT_PRI_CH1 + DMA_OUT_PRI_CH1_REG. + 0x1BC + 0x20 + + + TX_PRI + The priority of Tx channel 1. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + OUT_PERI_SEL_CH1 + DMA_OUT_PERI_SEL_CH1_REG. + 0x1C0 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + IN_CONF0_CH2 + DMA_IN_CONF0_CH2_REG. + 0x1F0 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + IN_CONF1_CH2 + DMA_IN_CONF1_CH2_REG. + 0x1F4 + 0x20 + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + INFIFO_STATUS_CH2 + DMA_INFIFO_STATUS_CH2_REG. + 0x1F8 + 0x20 + 0x07800003 + + + INFIFO_FULL + L1 Rx FIFO full signal for Rx channel 2. + 0 + 1 + read-only + + + INFIFO_EMPTY + L1 Rx FIFO empty signal for Rx channel 2. + 1 + 1 + read-only + + + INFIFO_CNT + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 27 + 1 + read-only + + + + + IN_POP_CH2 + DMA_IN_POP_CH2_REG. + 0x1FC + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + IN_LINK_CH2 + DMA_IN_LINK_CH2_REG. + 0x200 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_STATE_CH2 + DMA_IN_STATE_CH2_REG. + 0x204 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH2 + DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. + 0x208 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH2 + DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. + 0x20C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + IN_DSCR_CH2 + DMA_IN_DSCR_CH2_REG. + 0x210 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH2 + DMA_IN_DSCR_BF0_CH2_REG. + 0x214 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH2 + DMA_IN_DSCR_BF1_CH2_REG. + 0x218 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + IN_PRI_CH2 + DMA_IN_PRI_CH2_REG. + 0x21C + 0x20 + + + RX_PRI + The priority of Rx channel 2. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + IN_PERI_SEL_CH2 + DMA_IN_PERI_SEL_CH2_REG. + 0x220 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + OUT_CONF0_CH2 + DMA_OUT_CONF0_CH2_REG. + 0x250 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + OUT_CONF1_CH2 + DMA_OUT_CONF1_CH2_REG. + 0x254 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + OUTFIFO_STATUS_CH2 + DMA_OUTFIFO_STATUS_CH2_REG. + 0x258 + 0x20 + 0x07800002 + + + OUTFIFO_FULL + L1 Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY + L1 Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B + reserved + 26 + 1 + read-only + + + + + OUT_PUSH_CH2 + DMA_OUT_PUSH_CH2_REG. + 0x25C + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + OUT_LINK_CH2 + DMA_OUT_LINK_CH2_REG. + 0x260 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_STATE_CH2 + DMA_OUT_STATE_CH2_REG. + 0x264 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + OUT_EOF_DES_ADDR_CH2 + DMA_OUT_EOF_DES_ADDR_CH2_REG. + 0x268 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR_CH2 + DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. + 0x26C + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + OUT_DSCR_CH2 + DMA_OUT_DSCR_CH2_REG. + 0x270 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH2 + DMA_OUT_DSCR_BF0_CH2_REG. + 0x274 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH2 + DMA_OUT_DSCR_BF1_CH2_REG. + 0x278 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + OUT_PRI_CH2 + DMA_OUT_PRI_CH2_REG. + 0x27C + 0x20 + + + TX_PRI + The priority of Tx channel 2. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + OUT_PERI_SEL_CH2 + DMA_OUT_PERI_SEL_CH2_REG. + 0x280 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. + 0 + 6 + read-write + + + + + + + DS + Digital Signature + DS + 0x6003D000 + + 0x0 + 0x108C + registers + + + + 512 + 0x1 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x8 + + + 512 + 0x1 + M_MEM[%s] + memory that stores M + 0x200 + 0x8 + + + 512 + 0x1 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x8 + + + 48 + 0x1 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + memory that stores X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x8 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x60008800 + + 0x0 + 0x1CC + registers + + + EFUSE + 24 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + The content of the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + The content of the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + The content of the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + The content of the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + The content of the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + The content of the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + The content of the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + The content of the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + The content of the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Disable programming of individual eFuses. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Set this bit to disable reading from BlOCK4-10. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT + Set this bit to disable boot from RTC RAM. + 7 + 1 + read-only + + + DIS_ICACHE + Set this bit to disable Icache. + 8 + 1 + read-only + + + DIS_USB_JTAG + Set this bit to disable function of usb switch to jtag in module of usb device. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 10 + 1 + read-only + + + DIS_USB_DEVICE + Set this bit to disable usb device. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Set this bit to disable the function that forces chip into download mode. + 12 + 1 + read-only + + + RPT4_RESERVED6 + Reserved (used for four backups method). + 13 + 1 + read-only + + + DIS_CAN + Set this bit to disable CAN function. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Set this bit to disable flash encryption when in download boot modes. + 20 + 1 + read-only + + + USB_DREFH + Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. + 21 + 2 + read-only + + + USB_DREFL + Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Set this bit to exchange USB D+ and D- pins. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO + Set this bit to vdd spi pin function as gpio. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE + Enable btlc gpio. + 27 + 2 + read-only + + + POWERGLITCH_EN + Set this bit to enable power glitch function. + 29 + 1 + read-only + + + POWER_GLITCH_DSENSE + Sample delay configuration of power glitch. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + RPT4_RESERVED2 + Reserved (used for four backups method). + 0 + 16 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Set this bit to enable revoking first secure boot key. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Set this bit to enable revoking second secure boot key. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Set this bit to enable revoking third secure boot key. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + + + KEY_PURPOSE_2 + Purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Purpose of Key5. + 12 + 4 + read-only + + + RPT4_RESERVED3 + Reserved (used for four backups method). + 16 + 4 + read-only + + + SECURE_BOOT_EN + Set this bit to enable secure boot. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Set this bit to enable revoking aggressive secure boot. + 21 + 1 + read-only + + + RPT4_RESERVED0 + Reserved (used for four backups method). + 22 + 6 + read-only + + + FLASH_TPUW + Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT + Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). + 1 + 1 + read-only + + + UART_PRINT_CHANNEL + Selectes the default UART print channel. 0: UART0. 1: UART1. + 2 + 1 + read-only + + + FLASH_ECC_MODE + Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE + Set this bit to disable UART download mode through USB. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + 6 + 2 + read-only + + + PIN_POWER_SELECTION + GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + 8 + 1 + read-only + + + FLASH_TYPE + Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE + Set Flash page size. + 10 + 2 + read-only + + + FLASH_ECC_EN + Set 1 to enable ECC for flash boot. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Set this bit to force ROM code to send a resume command during SPI boot. + 13 + 1 + read-only + + + SECURE_VERSION + Secure version (used by ESP-IDF anti-rollback feature). + 14 + 16 + read-only + + + RPT4_RESERVED1 + Reserved (used for four backups method). + 30 + 2 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED4 + Reserved (used for four backups method). + 0 + 24 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register 0. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register 1. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + SPI_PAD_CONF_0 + Stores the zeroth part of SPI_PAD_CONF. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register 2. + 0x4C + 0x20 + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register 3. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the fist 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register 4. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the fist 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register 5. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register 0 of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register 1 of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register 2 of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register 3 of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register 4 of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register 5 of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register 6 of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register 7 of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register 0 of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register 1 of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register 2 of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register 3 of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register 4 of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register 5 of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register 6 of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register 7 of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register 0 of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register 1 of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register 2 of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register 3 of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register 4 of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register 5 of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register 6 of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register 7 of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register 0 of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register 1 of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register 2 of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register 3 of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register 4 of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register 5 of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register 6 of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register 7 of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register 0 of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register 1 of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register 2 of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register 3 of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register 4 of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register 5 of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register 6 of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register 7 of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register 0 of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register 1 of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register 2 of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register 3 of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register 4 of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register 5 of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register 6 of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register 7 of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register 0 of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register 1 of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register 2 of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register 3 of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register 4 of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register 5 of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register 6 of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register 7 of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register 0 of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register 2 of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register 3 of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register 4 of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register 5 of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register 6 of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register 7 of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register 0 of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 1st 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register 2 of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 2nd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register 3 of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 3rd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register 4 of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 4th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register 5 of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 5th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register 6 of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 6th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register 7 of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 7th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + If any bit in RD_DIS is 1, then it indicates a programming error. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT_ERR + If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + If DIS_ICACHE is 1, then it indicates a programming error. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + If DIS_USB_JTAG is 1, then it indicates a programming error. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error. + 10 + 1 + read-only + + + DIS_USB_DEVICE_ERR + If DIS_USB_DEVICE is 1, then it indicates a programming error. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error. + 12 + 1 + read-only + + + RPT4_RESERVED6_ERR + Reserved. + 13 + 1 + read-only + + + DIS_CAN_ERR + If DIS_CAN is 1, then it indicates a programming error. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + If JTAG_SEL_ENABLE is 1, then it indicates a programming error. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + If SOFT_DIS_JTAG is 1, then it indicates a programming error. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + If DIS_PAD_JTAG is 1, then it indicates a programming error. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error. + 20 + 1 + read-only + + + USB_DREFH_ERR + If any bit in USB_DREFH is 1, then it indicates a programming error. + 21 + 2 + read-only + + + USB_DREFL_ERR + If any bit in USB_DREFL is 1, then it indicates a programming error. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + If USB_EXCHG_PINS is 1, then it indicates a programming error. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO_ERR + If VDD_SPI_AS_GPIO is 1, then it indicates a programming error. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE_ERR + If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error. + 27 + 2 + read-only + + + POWERGLITCH_EN_ERR + If POWERGLITCH_EN is 1, then it indicates a programming error. + 29 + 1 + read-only + + + POWER_GLITCH_DSENSE_ERR + If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + RPT4_RESERVED2_ERR + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL_ERR + If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error. + 12 + 4 + read-only + + + RPT4_RESERVED3_ERR + Reserved. + 16 + 4 + read-only + + + SECURE_BOOT_EN_ERR + If SECURE_BOOT_EN is 1, then it indicates a programming error. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error. + 21 + 1 + read-only + + + RPT4_RESERVED0_ERR + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW_ERR + If any bit in FLASH_TPUM is 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT_ERR + If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL_ERR + If UART_PRINT_CHANNEL is 1, then it indicates a programming error. + 2 + 1 + read-only + + + FLASH_ECC_MODE_ERR + If FLASH_ECC_MODE is 1, then it indicates a programming error. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE_ERR + If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error. + 6 + 2 + read-only + + + PIN_POWER_SELECTION_ERR + If PIN_POWER_SELECTION is 1, then it indicates a programming error. + 8 + 1 + read-only + + + FLASH_TYPE_ERR + If FLASH_TYPE is 1, then it indicates a programming error. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error. + 10 + 2 + read-only + + + FLASH_ECC_EN_ERR + If FLASH_ECC_EN_ERR is 1, then it indicates a programming error. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + If FORCE_SEND_RESUME is 1, then it indicates a programming error. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + If any bit in SECURE_VERSION is 1, then it indicates a programming error. + 14 + 16 + read-only + + + RPT4_RESERVED1_ERR + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED4_ERR + Reserved. + 0 + 24 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit and force to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register; + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + REPEAT_ERR_CNT + Indicates the number of error bits during programming BLOCK0. + 10 + 8 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12000000 + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x00288000 + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02007200 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C4000 + + 0x0 + 0x108 + registers + + + + ICACHE_CTRL + This description will be updated in the near future. + 0x0 + 0x20 + + + ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + + + ICACHE_CTRL1 + This description will be updated in the near future. + 0x4 + 0x20 + 0x00000003 + + + ICACHE_SHUT_IBUS + The bit is used to disable core0 ibus, 0: enable, 1: disable + 0 + 1 + read-write + + + ICACHE_SHUT_DBUS + The bit is used to disable core1 ibus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + ICACHE_TAG_POWER_CTRL + This description will be updated in the near future. + 0x8 + 0x20 + 0x00000005 + + + ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + ICACHE_PRELOCK_CTRL + This description will be updated in the near future. + 0xC + 0x20 + + + ICACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + ICACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + ICACHE_PRELOCK_SCT0_ADDR + This description will be updated in the near future. + 0x10 + 0x20 + + + ICACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT1_ADDR + This description will be updated in the near future. + 0x14 + 0x20 + + + ICACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT_SIZE + This description will be updated in the near future. + 0x18 + 0x20 + + + ICACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + ICACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + ICACHE_LOCK_CTRL + This description will be updated in the near future. + 0x1C + 0x20 + 0x00000004 + + + ICACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + ICACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + ICACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + ICACHE_LOCK_ADDR + This description will be updated in the near future. + 0x20 + 0x20 + + + ICACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_LOCK_SIZE + This description will be updated in the near future. + 0x24 + 0x20 + + + ICACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + ICACHE_SYNC_CTRL + This description will be updated in the near future. + 0x28 + 0x20 + 0x00000001 + + + ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + ICACHE_SYNC_DONE + The bit is used to indicate invalidate operation is finished. + 1 + 1 + read-only + + + + + ICACHE_SYNC_ADDR + This description will be updated in the near future. + 0x2C + 0x20 + + + ICACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_SYNC_SIZE + This description will be updated in the near future. + 0x30 + 0x20 + + + ICACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + ICACHE_PRELOAD_CTRL + This description will be updated in the near future. + 0x34 + 0x20 + 0x00000002 + + + ICACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + ICACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + ICACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + ICACHE_PRELOAD_ADDR + This description will be updated in the near future. + 0x38 + 0x20 + + + ICACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_PRELOAD_SIZE + This description will be updated in the near future. + 0x3C + 0x20 + + + ICACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + ICACHE_AUTOLOAD_CTRL + This description will be updated in the near future. + 0x40 + 0x20 + 0x00000008 + + + ICACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + ICACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + ICACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + ICACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + ICACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + ICACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_ADDR + This description will be updated in the near future. + 0x44 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_SIZE + This description will be updated in the near future. + 0x48 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_ADDR + This description will be updated in the near future. + 0x4C + 0x20 + + + ICACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_SIZE + This description will be updated in the near future. + 0x50 + 0x20 + + + ICACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + IBUS_TO_FLASH_START_VADDR + This description will be updated in the near future. + 0x54 + 0x20 + 0x42000000 + + + IBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + IBUS_TO_FLASH_END_VADDR + This description will be updated in the near future. + 0x58 + 0x20 + 0x427FFFFF + + + IBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_START_VADDR + This description will be updated in the near future. + 0x5C + 0x20 + 0x3C000000 + + + DBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_END_VADDR + This description will be updated in the near future. + 0x60 + 0x20 + 0x3C7FFFFF + + + DBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + CACHE_ACS_CNT_CLR + This description will be updated in the near future. + 0x64 + 0x20 + + + IBUS_ACS_CNT_CLR + The bit is used to clear ibus counter. + 0 + 1 + write-only + + + DBUS_ACS_CNT_CLR + The bit is used to clear dbus counter. + 1 + 1 + write-only + + + + + IBUS_ACS_MISS_CNT + This description will be updated in the near future. + 0x68 + 0x20 + + + IBUS_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus access flash. + 0 + 32 + read-only + + + + + IBUS_ACS_CNT + This description will be updated in the near future. + 0x6C + 0x20 + + + IBUS_ACS_CNT + The bits are used to count the number of ibus access flash through icache. + 0 + 32 + read-only + + + + + DBUS_ACS_FLASH_MISS_CNT + This description will be updated in the near future. + 0x70 + 0x20 + + + DBUS_ACS_FLASH_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access flash. + 0 + 32 + read-only + + + + + DBUS_ACS_CNT + This description will be updated in the near future. + 0x74 + 0x20 + + + DBUS_ACS_CNT + The bits are used to count the number of dbus access flash through icache. + 0 + 32 + read-only + + + + + CACHE_ILG_INT_ENA + This description will be updated in the near future. + 0x78 + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 0 + 1 + read-write + + + ICACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 1 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 5 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 7 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 8 + 1 + read-write + + + + + CACHE_ILG_INT_CLR + This description will be updated in the near future. + 0x7C + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 0 + 1 + write-only + + + ICACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 1 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 5 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 7 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 8 + 1 + write-only + + + + + CACHE_ILG_INT_ST + This description will be updated in the near future. + 0x80 + 0x20 + + + ICACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 0 + 1 + read-only + + + ICACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 1 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 5 + 1 + read-only + + + IBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + 7 + 1 + read-only + + + IBUS_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + 8 + 1 + read-only + + + DBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + 9 + 1 + read-only + + + DBUS_ACS_FLASH_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash miss counter overflow. + 10 + 1 + read-only + + + + + CORE0_ACS_CACHE_INT_ENA + This description will be updated in the near future. + 0x84 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE0_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE0_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE0_DBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE0_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + CORE0_DBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by dbus trying to write icache + 5 + 1 + read-write + + + + + CORE0_ACS_CACHE_INT_CLR + This description will be updated in the near future. + 0x88 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE0_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE0_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE0_DBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE0_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + CORE0_DBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by dbus trying to write icache + 5 + 1 + write-only + + + + + CORE0_ACS_CACHE_INT_ST + This description will be updated in the near future. + 0x8C + 0x20 + + + CORE0_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE0_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE0_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE0_DBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE0_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + CORE0_DBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by dbus trying to write icache + 5 + 1 + read-only + + + + + CORE0_DBUS_REJECT_ST + This description will be updated in the near future. + 0x90 + 0x20 + + + CORE0_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 3 + 1 + read-only + + + + + CORE0_DBUS_REJECT_VADDR + This description will be updated in the near future. + 0x94 + 0x20 + 0xFFFFFFFF + + + CORE0_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE0_IBUS_REJECT_ST + This description will be updated in the near future. + 0x98 + 0x20 + + + CORE0_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 0 + 3 + read-only + + + CORE0_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 3 + 1 + read-only + + + + + CORE0_IBUS_REJECT_VADDR + This description will be updated in the near future. + 0x9C + 0x20 + 0xFFFFFFFF + + + CORE0_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CACHE_MMU_FAULT_CONTENT + This description will be updated in the near future. + 0xA0 + 0x20 + + + CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 10 + read-only + + + CACHE_MMU_FAULT_CODE + The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. + 10 + 4 + read-only + + + + + CACHE_MMU_FAULT_VADDR + This description will be updated in the near future. + 0xA4 + 0x20 + + + CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + CACHE_WRAP_AROUND_CTRL + This description will be updated in the near future. + 0xA8 + 0x20 + + + CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + + + CACHE_MMU_POWER_CTRL + This description will be updated in the near future. + 0xAC + 0x20 + 0x00000005 + + + CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + CACHE_STATE + This description will be updated in the near future. + 0xB0 + 0x20 + 0x00000001 + + + ICACHE_STATE + The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + This description will be updated in the near future. + 0xB4 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved. + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved. + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + This description will be updated in the near future. + 0xB8 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_MANUAL_CRYPT + The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_AUTO_CRYPT + The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_CRYPT + The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + This description will be updated in the near future. + 0xBC + 0x20 + + + ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + This description will be updated in the near future. + 0xC0 + 0x20 + + + ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + + + CACHE_MMU_OWNER + This description will be updated in the near future. + 0xC4 + 0x20 + + + CACHE_MMU_OWNER + The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus + 0 + 4 + read-write + + + + + CACHE_CONF_MISC + This description will be updated in the near future. + 0xC8 + 0x20 + 0x00000007 + + + CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + CACHE_TRACE_ENA + The bit is used to enable cache trace function. + 2 + 1 + read-write + + + + + ICACHE_FREEZE + This description will be updated in the near future. + 0xCC + 0x20 + + + ENA + The bit is used to enable icache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate icache freeze success + 2 + 1 + read-only + + + + + ICACHE_ATOMIC_OPERATE_ENA + This description will be updated in the near future. + 0xD0 + 0x20 + 0x00000001 + + + ICACHE_ATOMIC_OPERATE_ENA + The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + CACHE_REQUEST + This description will be updated in the near future. + 0xD4 + 0x20 + + + BYPASS + The bit is used to disable request recording which could cause performance issue + 0 + 1 + read-write + + + + + IBUS_PMS_TBL_LOCK + This description will be updated in the near future. + 0xD8 + 0x20 + + + IBUS_PMS_LOCK + The bit is used to configure the ibus permission control section boundary0 + 0 + 1 + read-write + + + + + IBUS_PMS_TBL_BOUNDARY0 + This description will be updated in the near future. + 0xDC + 0x20 + + + IBUS_PMS_BOUNDARY0 + The bit is used to configure the ibus permission control section boundary0 + 0 + 12 + read-write + + + + + IBUS_PMS_TBL_BOUNDARY1 + This description will be updated in the near future. + 0xE0 + 0x20 + 0x00000800 + + + IBUS_PMS_BOUNDARY1 + The bit is used to configure the ibus permission control section boundary1 + 0 + 12 + read-write + + + + + IBUS_PMS_TBL_BOUNDARY2 + This description will be updated in the near future. + 0xE4 + 0x20 + 0x00000800 + + + IBUS_PMS_BOUNDARY2 + The bit is used to configure the ibus permission control section boundary2 + 0 + 12 + read-write + + + + + IBUS_PMS_TBL_ATTR + This description will be updated in the near future. + 0xE8 + 0x20 + 0x000000FF + + + IBUS_PMS_SCT1_ATTR + The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1 + 0 + 4 + read-write + + + IBUS_PMS_SCT2_ATTR + The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1 + 4 + 4 + read-write + + + + + DBUS_PMS_TBL_LOCK + This description will be updated in the near future. + 0xEC + 0x20 + + + DBUS_PMS_LOCK + The bit is used to configure the ibus permission control section boundary0 + 0 + 1 + read-write + + + + + DBUS_PMS_TBL_BOUNDARY0 + This description will be updated in the near future. + 0xF0 + 0x20 + + + DBUS_PMS_BOUNDARY0 + The bit is used to configure the dbus permission control section boundary0 + 0 + 12 + read-write + + + + + DBUS_PMS_TBL_BOUNDARY1 + This description will be updated in the near future. + 0xF4 + 0x20 + 0x00000800 + + + DBUS_PMS_BOUNDARY1 + The bit is used to configure the dbus permission control section boundary1 + 0 + 12 + read-write + + + + + DBUS_PMS_TBL_BOUNDARY2 + This description will be updated in the near future. + 0xF8 + 0x20 + 0x00000800 + + + DBUS_PMS_BOUNDARY2 + The bit is used to configure the dbus permission control section boundary2 + 0 + 12 + read-write + + + + + DBUS_PMS_TBL_ATTR + This description will be updated in the near future. + 0xFC + 0x20 + 0x0000000F + + + DBUS_PMS_SCT1_ATTR + The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1 + 0 + 2 + read-write + + + DBUS_PMS_SCT2_ATTR + The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1 + 2 + 2 + read-write + + + + + CLOCK_GATE + This description will be updated in the near future. + 0x100 + 0x20 + 0x00000001 + + + CLK_EN + clock gate enable. + 0 + 1 + read-write + + + + + REG_DATE + This description will be updated in the near future. + 0x3FC + 0x20 + 0x02007160 + + + DATE + version information + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x31C + registers + + + GPIO + 16 + + + GPIO_NMI + 17 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-25 + 0 + 26 + read-write + + + + + OUT_W1TS + GPIO output set register + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-25 + 0 + 26 + write-only + + + + + OUT_W1TC + GPIO output clear register + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-25 + 0 + 26 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-25 + 0 + 26 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-25 + 0 + 26 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-25 + 0 + 26 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-25 + 0 + 26 + read-only + + + + + STATUS + GPIO interrupt status register + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-25 + 0 + 26 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-25 + 0 + 26 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-25 + 0 + 26 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-25 + 0 + 26 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25 + 0 + 26 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-25 + 0 + 26 + read-only + + + + + 26 + 0x4 + 0-25 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-25 + 0 + 26 + read-only + + + + + 128 + 0x4 + 0-127 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + + + IN_SEL + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 5 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 5 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 6 + 1 + read-write + + + + + 26 + 0x4 + 0-25 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000080 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 8 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + REG_DATE + GPIO version register + 0x6FC + 0x20 + 0x02006130 + + + REG_DATE + version register + 0 + 28 + read-write + + + + + + + GPIOSD + Sigma-Delta Modulation + GPIOSD + 0x60004F00 + + 0x0 + 0x1C + registers + + + + 4 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD0_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD0_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + SIGMADELTA_CG + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 31 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + SIGMADELTA_VERSION + Version Control Register + 0x28 + 0x20 + 0x02006230 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60013000 + + 0x0 + 0x90 + registers + + + I2C_EXT0 + 29 + + + + SCL_LOW_PERIOD + I2C_SCL_LOW_PERIOD_REG + 0x0 + 0x20 + + + SCL_LOW_PERIOD + reg_scl_low_period + 0 + 9 + read-write + + + + + CTR + I2C_CTR_REG + 0x4 + 0x20 + 0x0000020B + + + SDA_FORCE_OUT + reg_sda_force_out + 0 + 1 + read-write + + + SCL_FORCE_OUT + reg_scl_force_out + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + reg_sample_scl_level + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + reg_rx_full_ack_level + 3 + 1 + read-write + + + MS_MODE + reg_ms_mode + 4 + 1 + read-write + + + TRANS_START + reg_trans_start + 5 + 1 + write-only + + + TX_LSB_FIRST + reg_tx_lsb_first + 6 + 1 + read-write + + + RX_LSB_FIRST + reg_rx_lsb_first + 7 + 1 + read-write + + + CLK_EN + reg_clk_en + 8 + 1 + read-write + + + ARBITRATION_EN + reg_arbitration_en + 9 + 1 + read-write + + + FSM_RST + reg_fsm_rst + 10 + 1 + write-only + + + CONF_UPGATE + reg_conf_upgate + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + reg_slv_tx_auto_start_en + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + reg_addr_10bit_rw_check_en + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + reg_addr_broadcasting_en + 14 + 1 + read-write + + + + + SR + I2C_SR_REG + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + reg_resp_rec + 0 + 1 + read-only + + + SLAVE_RW + reg_slave_rw + 1 + 1 + read-only + + + ARB_LOST + reg_arb_lost + 3 + 1 + read-only + + + BUS_BUSY + reg_bus_busy + 4 + 1 + read-only + + + SLAVE_ADDRESSED + reg_slave_addressed + 5 + 1 + read-only + + + RXFIFO_CNT + reg_rxfifo_cnt + 8 + 6 + read-only + + + STRETCH_CAUSE + reg_stretch_cause + 14 + 2 + read-only + + + TXFIFO_CNT + reg_txfifo_cnt + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + reg_scl_main_state_last + 24 + 3 + read-only + + + SCL_STATE_LAST + reg_scl_state_last + 28 + 3 + read-only + + + + + TO + I2C_TO_REG + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + reg_time_out_value + 0 + 5 + read-write + + + TIME_OUT_EN + reg_time_out_en + 5 + 1 + read-write + + + + + SLAVE_ADDR + I2C_SLAVE_ADDR_REG + 0x10 + 0x20 + + + SLAVE_ADDR + reg_slave_addr + 0 + 15 + read-write + + + ADDR_10BIT_EN + reg_addr_10bit_en + 31 + 1 + read-write + + + + + FIFO_ST + I2C_FIFO_ST_REG + 0x14 + 0x20 + + + RXFIFO_RADDR + reg_rxfifo_raddr + 0 + 5 + read-only + + + RXFIFO_WADDR + reg_rxfifo_waddr + 5 + 5 + read-only + + + TXFIFO_RADDR + reg_txfifo_raddr + 10 + 5 + read-only + + + TXFIFO_WADDR + reg_txfifo_waddr + 15 + 5 + read-only + + + SLAVE_RW_POINT + reg_slave_rw_point + 22 + 8 + read-only + + + + + FIFO_CONF + I2C_FIFO_CONF_REG + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + reg_rxfifo_wm_thrhd + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + reg_txfifo_wm_thrhd + 5 + 5 + read-write + + + NONFIFO_EN + reg_nonfifo_en + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + reg_fifo_addr_cfg_en + 11 + 1 + read-write + + + RX_FIFO_RST + reg_rx_fifo_rst + 12 + 1 + read-write + + + TX_FIFO_RST + reg_tx_fifo_rst + 13 + 1 + read-write + + + FIFO_PRT_EN + reg_fifo_prt_en + 14 + 1 + read-write + + + + + DATA + I2C_FIFO_DATA_REG + 0x1C + 0x20 + + + FIFO_RDATA + reg_fifo_rdata + 0 + 8 + read-write + + + + + INT_RAW + I2C_INT_RAW_REG + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + reg_rxfifo_wm_int_raw + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + reg_txfifo_wm_int_raw + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + reg_rxfifo_ovf_int_raw + 2 + 1 + read-only + + + END_DETECT_INT_RAW + reg_end_detect_int_raw + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + reg_byte_trans_done_int_raw + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + reg_arbitration_lost_int_raw + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + reg_mst_txfifo_udf_int_raw + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + reg_trans_complete_int_raw + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + reg_time_out_int_raw + 8 + 1 + read-only + + + TRANS_START_INT_RAW + reg_trans_start_int_raw + 9 + 1 + read-only + + + NACK_INT_RAW + reg_nack_int_raw + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + reg_txfifo_ovf_int_raw + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + reg_rxfifo_udf_int_raw + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + reg_scl_st_to_int_raw + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + reg_scl_main_st_to_int_raw + 14 + 1 + read-only + + + DET_START_INT_RAW + reg_det_start_int_raw + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + reg_slave_stretch_int_raw + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + reg_general_call_int_raw + 17 + 1 + read-only + + + + + INT_CLR + I2C_INT_CLR_REG + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + reg_rxfifo_wm_int_clr + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + reg_txfifo_wm_int_clr + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + reg_rxfifo_ovf_int_clr + 2 + 1 + write-only + + + END_DETECT_INT_CLR + reg_end_detect_int_clr + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + reg_byte_trans_done_int_clr + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + reg_arbitration_lost_int_clr + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + reg_mst_txfifo_udf_int_clr + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + reg_trans_complete_int_clr + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + reg_time_out_int_clr + 8 + 1 + write-only + + + TRANS_START_INT_CLR + reg_trans_start_int_clr + 9 + 1 + write-only + + + NACK_INT_CLR + reg_nack_int_clr + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + reg_txfifo_ovf_int_clr + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + reg_rxfifo_udf_int_clr + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + reg_scl_st_to_int_clr + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + reg_scl_main_st_to_int_clr + 14 + 1 + write-only + + + DET_START_INT_CLR + reg_det_start_int_clr + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + reg_slave_stretch_int_clr + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + reg_general_call_int_clr + 17 + 1 + write-only + + + + + INT_ENA + I2C_INT_ENA_REG + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + reg_rxfifo_wm_int_ena + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + reg_txfifo_wm_int_ena + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + reg_rxfifo_ovf_int_ena + 2 + 1 + read-write + + + END_DETECT_INT_ENA + reg_end_detect_int_ena + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + reg_byte_trans_done_int_ena + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + reg_arbitration_lost_int_ena + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + reg_mst_txfifo_udf_int_ena + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + reg_trans_complete_int_ena + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + reg_time_out_int_ena + 8 + 1 + read-write + + + TRANS_START_INT_ENA + reg_trans_start_int_ena + 9 + 1 + read-write + + + NACK_INT_ENA + reg_nack_int_ena + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + reg_txfifo_ovf_int_ena + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + reg_rxfifo_udf_int_ena + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + reg_scl_st_to_int_ena + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + reg_scl_main_st_to_int_ena + 14 + 1 + read-write + + + DET_START_INT_ENA + reg_det_start_int_ena + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + reg_slave_stretch_int_ena + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + reg_general_call_int_ena + 17 + 1 + read-write + + + + + INT_STATUS + I2C_INT_STATUS_REG + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + reg_rxfifo_wm_int_st + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + reg_txfifo_wm_int_st + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + reg_rxfifo_ovf_int_st + 2 + 1 + read-only + + + END_DETECT_INT_ST + reg_end_detect_int_st + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + reg_byte_trans_done_int_st + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + reg_arbitration_lost_int_st + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + reg_mst_txfifo_udf_int_st + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + reg_trans_complete_int_st + 7 + 1 + read-only + + + TIME_OUT_INT_ST + reg_time_out_int_st + 8 + 1 + read-only + + + TRANS_START_INT_ST + reg_trans_start_int_st + 9 + 1 + read-only + + + NACK_INT_ST + reg_nack_int_st + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + reg_txfifo_ovf_int_st + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + reg_rxfifo_udf_int_st + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + reg_scl_st_to_int_st + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + reg_scl_main_st_to_int_st + 14 + 1 + read-only + + + DET_START_INT_ST + reg_det_start_int_st + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + reg_slave_stretch_int_st + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + reg_general_call_int_st + 17 + 1 + read-only + + + + + SDA_HOLD + I2C_SDA_HOLD_REG + 0x30 + 0x20 + + + TIME + reg_sda_hold_time + 0 + 9 + read-write + + + + + SDA_SAMPLE + I2C_SDA_SAMPLE_REG + 0x34 + 0x20 + + + TIME + reg_sda_sample_time + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + I2C_SCL_HIGH_PERIOD_REG + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + reg_scl_high_period + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + reg_scl_wait_high_period + 9 + 7 + read-write + + + + + SCL_START_HOLD + I2C_SCL_START_HOLD_REG + 0x40 + 0x20 + 0x00000008 + + + TIME + reg_scl_start_hold_time + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + I2C_SCL_RSTART_SETUP_REG + 0x44 + 0x20 + 0x00000008 + + + TIME + reg_scl_rstart_setup_time + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + I2C_SCL_STOP_HOLD_REG + 0x48 + 0x20 + 0x00000008 + + + TIME + reg_scl_stop_hold_time + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + I2C_SCL_STOP_SETUP_REG + 0x4C + 0x20 + 0x00000008 + + + TIME + reg_scl_stop_setup_time + 0 + 9 + read-write + + + + + FILTER_CFG + I2C_FILTER_CFG_REG + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + reg_scl_filter_thres + 0 + 4 + read-write + + + SDA_FILTER_THRES + reg_sda_filter_thres + 4 + 4 + read-write + + + SCL_FILTER_EN + reg_scl_filter_en + 8 + 1 + read-write + + + SDA_FILTER_EN + reg_sda_filter_en + 9 + 1 + read-write + + + + + CLK_CONF + I2C_CLK_CONF_REG + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + reg_sclk_div_num + 0 + 8 + read-write + + + SCLK_DIV_A + reg_sclk_div_a + 8 + 6 + read-write + + + SCLK_DIV_B + reg_sclk_div_b + 14 + 6 + read-write + + + SCLK_SEL + reg_sclk_sel + 20 + 1 + read-write + + + SCLK_ACTIVE + reg_sclk_active + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C_COMD%s_REG + 0x58 + 0x20 + + + COMMAND + reg_command + 0 + 14 + read-write + + + COMMAND_DONE + reg_command_done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + I2C_SCL_ST_TIME_OUT_REG + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + reg_scl_st_to_regno more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + I2C_SCL_MAIN_ST_TIME_OUT_REG + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + reg_scl_main_st_to_regno more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + I2C_SCL_SP_CONF_REG + 0x80 + 0x20 + + + SCL_RST_SLV_EN + reg_scl_rst_slv_en + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + reg_scl_rst_slv_num + 1 + 5 + read-write + + + SCL_PD_EN + reg_scl_pd_en + 6 + 1 + read-write + + + SDA_PD_EN + reg_sda_pd_en + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + I2C_SCL_STRETCH_CONF_REG + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + reg_stretch_protect_num + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + reg_slave_scl_stretch_en + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + reg_slave_scl_stretch_clr + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + reg_slave_byte_ack_ctl_en + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + reg_slave_byte_ack_lvl + 13 + 1 + read-write + + + + + DATE + I2C_DATE_REG + 0xF8 + 0x20 + 0x20070201 + + + DATE + reg_date + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C_TXFIFO_START_ADDR_REG + 0x100 + 0x20 + + + TXFIFO_START_ADDR + reg_txfifo_start_addr. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C_RXFIFO_START_ADDR_REG + 0x180 + 0x20 + + + RXFIFO_START_ADDR + reg_rxfifo_start_addr. + 0 + 32 + read-only + + + + + + + I2S + I2S (Inter-IC Sound) Controller + I2S + 0x6002D000 + + 0x0 + 0x5C + registers + + + I2S + 20 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02007220 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Core + INTERRUPT_CORE0 + 0x600C2000 + + 0x0 + 0x19C + registers + + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SW_INTR_0 + 50 + + + SW_INTR_1 + 51 + + + SW_INTR_2 + 52 + + + SW_INTR_3 + 53 + + + + MAC_INTR_MAP + mac intr map register + 0x0 + 0x20 + + + MAC_INTR_MAP + core0_mac_intr_map + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac nmi_intr map register + 0x4 + 0x20 + + + MAC_NMI_MAP + reg_core0_mac_nmi_map + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr intr map register + 0x8 + 0x20 + + + PWR_INTR_MAP + reg_core0_pwr_intr_map + 0 + 5 + read-write + + + + + BB_INT_MAP + bb intr map register + 0xC + 0x20 + + + BB_INT_MAP + reg_core0_bb_int_map + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bt intr map register + 0x10 + 0x20 + + + BT_MAC_INT_MAP + reg_core0_bt_mac_int_map + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bb_bt intr map register + 0x14 + 0x20 + + + BT_BB_INT_MAP + reg_core0_bt_bb_int_map + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bb_bt_nmi intr map register + 0x18 + 0x20 + + + BT_BB_NMI_MAP + reg_core0_bt_bb_nmi_map + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt intr map register + 0x1C + 0x20 + + + RWBT_IRQ_MAP + reg_core0_rwbt_irq_map + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble intr map register + 0x20 + 0x20 + + + RWBLE_IRQ_MAP + reg_core0_rwble_irq_map + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi intr map register + 0x24 + 0x20 + + + RWBT_NMI_MAP + reg_core0_rwbt_nmi_map + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi intr map register + 0x28 + 0x20 + + + RWBLE_NMI_MAP + reg_core0_rwble_nmi_map + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c intr map register + 0x2C + 0x20 + + + I2C_MST_INT_MAP + reg_core0_i2c_mst_int_map + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 intr map register + 0x30 + 0x20 + + + SLC0_INTR_MAP + reg_core0_slc0_intr_map + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 intr map register + 0x34 + 0x20 + + + SLC1_INTR_MAP + reg_core0_slc1_intr_map + 0 + 5 + read-write + + + + + APB_CTRL_INTR_MAP + apb_ctrl intr map register + 0x38 + 0x20 + + + APB_CTRL_INTR_MAP + reg_core0_apb_ctrl_intr_map + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uchi0 intr map register + 0x3C + 0x20 + + + UHCI0_INTR_MAP + reg_core0_uhci0_intr_map + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio intr map register + 0x40 + 0x20 + + + GPIO_INTERRUPT_PRO_MAP + reg_core0_gpio_interrupt_pro_map + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_pro intr map register + 0x44 + 0x20 + + + GPIO_INTERRUPT_PRO_NMI_MAP + reg_core0_gpio_interrupt_pro_nmi_map + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + gpio_pro_nmi intr map register + 0x48 + 0x20 + + + SPI_INTR_1_MAP + reg_core0_spi_intr_1_map + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi1 intr map register + 0x4C + 0x20 + + + SPI_INTR_2_MAP + reg_core0_spi_intr_2_map + 0 + 5 + read-write + + + + + I2S1_INT_MAP + spi2 intr map register + 0x50 + 0x20 + + + I2S1_INT_MAP + reg_core0_i2s1_int_map + 0 + 5 + read-write + + + + + UART_INTR_MAP + i2s1 intr map register + 0x54 + 0x20 + + + UART_INTR_MAP + reg_core0_uart_intr_map + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 intr map register + 0x58 + 0x20 + + + UART1_INTR_MAP + reg_core0_uart1_intr_map + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc intr map register + 0x5C + 0x20 + + + LEDC_INT_MAP + reg_core0_ledc_int_map + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse intr map register + 0x60 + 0x20 + + + EFUSE_INT_MAP + reg_core0_efuse_int_map + 0 + 5 + read-write + + + + + CAN_INT_MAP + can intr map register + 0x64 + 0x20 + + + CAN_INT_MAP + reg_core0_can_int_map + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb intr map register + 0x68 + 0x20 + + + USB_INTR_MAP + reg_core0_usb_intr_map + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc intr map register + 0x6C + 0x20 + + + RTC_CORE_INTR_MAP + reg_core0_rtc_core_intr_map + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt intr map register + 0x70 + 0x20 + + + RMT_INTR_MAP + reg_core0_rmt_intr_map + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c intr map register + 0x74 + 0x20 + + + I2C_EXT0_INTR_MAP + reg_core0_i2c_ext0_intr_map + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer1 intr map register + 0x78 + 0x20 + + + TIMER_INT1_MAP + reg_core0_timer_int1_map + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer2 intr map register + 0x7C + 0x20 + + + TIMER_INT2_MAP + reg_core0_timer_int2_map + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg to intr map register + 0x80 + 0x20 + + + TG_T0_INT_MAP + reg_core0_tg_t0_int_map + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg wdt intr map register + 0x84 + 0x20 + + + TG_WDT_INT_MAP + reg_core0_tg_wdt_int_map + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1 to intr map register + 0x88 + 0x20 + + + TG1_T0_INT_MAP + reg_core0_tg1_t0_int_map + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1 wdt intr map register + 0x8C + 0x20 + + + TG1_WDT_INT_MAP + reg_core0_tg1_wdt_int_map + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache ia intr map register + 0x90 + 0x20 + + + CACHE_IA_INT_MAP + reg_core0_cache_ia_int_map + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer intr map register + 0x94 + 0x20 + + + SYSTIMER_TARGET0_INT_MAP + reg_core0_systimer_target0_int_map + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer target1 intr map register + 0x98 + 0x20 + + + SYSTIMER_TARGET1_INT_MAP + reg_core0_systimer_target1_int_map + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer target2 intr map register + 0x9C + 0x20 + + + SYSTIMER_TARGET2_INT_MAP + reg_core0_systimer_target2_int_map + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi mem reject intr map register + 0xA0 + 0x20 + + + SPI_MEM_REJECT_INTR_MAP + reg_core0_spi_mem_reject_intr_map + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache perload intr map register + 0xA4 + 0x20 + + + ICACHE_PRELOAD_INT_MAP + reg_core0_icache_preload_int_map + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache sync intr map register + 0xA8 + 0x20 + + + ICACHE_SYNC_INT_MAP + reg_core0_icache_sync_int_map + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + adc intr map register + 0xAC + 0x20 + + + APB_ADC_INT_MAP + reg_core0_apb_adc_int_map + 0 + 5 + read-write + + + + + DMA_CH0_INT_MAP + dma ch0 intr map register + 0xB0 + 0x20 + + + DMA_CH0_INT_MAP + reg_core0_dma_ch0_int_map + 0 + 5 + read-write + + + + + DMA_CH1_INT_MAP + dma ch1 intr map register + 0xB4 + 0x20 + + + DMA_CH1_INT_MAP + reg_core0_dma_ch1_int_map + 0 + 5 + read-write + + + + + DMA_CH2_INT_MAP + dma ch2 intr map register + 0xB8 + 0x20 + + + DMA_CH2_INT_MAP + reg_core0_dma_ch2_int_map + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa intr map register + 0xBC + 0x20 + + + RSA_INT_MAP + reg_core0_rsa_int_map + 0 + 5 + read-write + + + + + AES_INT_MAP + aes intr map register + 0xC0 + 0x20 + + + AES_INT_MAP + reg_core0_aes_int_map + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha intr map register + 0xC4 + 0x20 + + + SHA_INT_MAP + reg_core0_sha_int_map + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu from cpu 0 intr map register + 0xC8 + 0x20 + + + CPU_INTR_FROM_CPU_0_MAP + reg_core0_cpu_intr_from_cpu_0_map + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu from cpu 0 intr map register + 0xCC + 0x20 + + + CPU_INTR_FROM_CPU_1_MAP + reg_core0_cpu_intr_from_cpu_1_map + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu from cpu 1 intr map register + 0xD0 + 0x20 + + + CPU_INTR_FROM_CPU_2_MAP + reg_core0_cpu_intr_from_cpu_2_map + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu from cpu 3 intr map register + 0xD4 + 0x20 + + + CPU_INTR_FROM_CPU_3_MAP + reg_core0_cpu_intr_from_cpu_3_map + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist debug intr map register + 0xD8 + 0x20 + + + ASSIST_DEBUG_INTR_MAP + reg_core0_assist_debug_intr_map + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma pms violatile intr map register + 0xDC + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + reg_core0_dma_apbperi_pms_monitor_violate_intr_map + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + iram0 pms violatile intr map register + 0xE0 + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + reg_core0_core_0_iram0_pms_monitor_violate_intr_map + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + mac intr map register + 0xE4 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + reg_core0_core_0_dram0_pms_monitor_violate_intr_map + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + mac intr map register + 0xE8 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + reg_core0_core_0_pif_pms_monitor_violate_intr_map + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + mac intr map register + 0xEC + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + reg_core0_core_0_pif_pms_monitor_violate_size_intr_map + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + mac intr map register + 0xF0 + 0x20 + + + BACKUP_PMS_VIOLATE_INTR_MAP + reg_core0_backup_pms_violate_intr_map + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + mac intr map register + 0xF4 + 0x20 + + + CACHE_CORE0_ACS_INT_MAP + reg_core0_cache_core0_acs_int_map + 0 + 5 + read-write + + + + + INTR_STATUS_REG_0 + mac intr map register + 0xF8 + 0x20 + + + INTR_STATUS_0 + reg_core0_intr_status_0 + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + mac intr map register + 0xFC + 0x20 + + + INTR_STATUS_1 + reg_core0_intr_status_1 + 0 + 32 + read-only + + + + + CLOCK_GATE + mac intr map register + 0x100 + 0x20 + 0x00000001 + + + REG_CLK_EN + reg_core0_reg_clk_en + 0 + 1 + read-write + + + + + CPU_INT_ENABLE + mac intr map register + 0x104 + 0x20 + + + CPU_INT_ENABLE + reg_core0_cpu_int_enable + 0 + 32 + read-write + + + + + CPU_INT_TYPE + mac intr map register + 0x108 + 0x20 + + + CPU_INT_TYPE + reg_core0_cpu_int_type + 0 + 32 + read-write + + + + + CPU_INT_CLEAR + mac intr map register + 0x10C + 0x20 + + + CPU_INT_CLEAR + reg_core0_cpu_int_clear + 0 + 32 + read-write + + + + + CPU_INT_EIP_STATUS + mac intr map register + 0x110 + 0x20 + + + CPU_INT_EIP_STATUS + reg_core0_cpu_int_eip_status + 0 + 32 + read-only + + + + + CPU_INT_PRI_0 + mac intr map register + 0x114 + 0x20 + + + CPU_PRI_0_MAP + reg_core0_cpu_pri_0_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_1 + mac intr map register + 0x118 + 0x20 + + + CPU_PRI_1_MAP + reg_core0_cpu_pri_1_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_2 + mac intr map register + 0x11C + 0x20 + + + CPU_PRI_2_MAP + reg_core0_cpu_pri_2_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_3 + mac intr map register + 0x120 + 0x20 + + + CPU_PRI_3_MAP + reg_core0_cpu_pri_3_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_4 + mac intr map register + 0x124 + 0x20 + + + CPU_PRI_4_MAP + reg_core0_cpu_pri_4_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_5 + mac intr map register + 0x128 + 0x20 + + + CPU_PRI_5_MAP + reg_core0_cpu_pri_5_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_6 + mac intr map register + 0x12C + 0x20 + + + CPU_PRI_6_MAP + reg_core0_cpu_pri_6_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_7 + mac intr map register + 0x130 + 0x20 + + + CPU_PRI_7_MAP + reg_core0_cpu_pri_7_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_8 + mac intr map register + 0x134 + 0x20 + + + CPU_PRI_8_MAP + reg_core0_cpu_pri_8_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_9 + mac intr map register + 0x138 + 0x20 + + + CPU_PRI_9_MAP + reg_core0_cpu_pri_9_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_10 + mac intr map register + 0x13C + 0x20 + + + CPU_PRI_10_MAP + reg_core0_cpu_pri_10_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_11 + mac intr map register + 0x140 + 0x20 + + + CPU_PRI_11_MAP + reg_core0_cpu_pri_11_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_12 + mac intr map register + 0x144 + 0x20 + + + CPU_PRI_12_MAP + reg_core0_cpu_pri_12_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_13 + mac intr map register + 0x148 + 0x20 + + + CPU_PRI_13_MAP + reg_core0_cpu_pri_13_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_14 + mac intr map register + 0x14C + 0x20 + + + CPU_PRI_14_MAP + reg_core0_cpu_pri_14_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_15 + mac intr map register + 0x150 + 0x20 + + + CPU_PRI_15_MAP + reg_core0_cpu_pri_15_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_16 + mac intr map register + 0x154 + 0x20 + + + CPU_PRI_16_MAP + reg_core0_cpu_pri_16_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_17 + mac intr map register + 0x158 + 0x20 + + + CPU_PRI_17_MAP + reg_core0_cpu_pri_17_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_18 + mac intr map register + 0x15C + 0x20 + + + CPU_PRI_18_MAP + reg_core0_cpu_pri_18_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_19 + mac intr map register + 0x160 + 0x20 + + + CPU_PRI_19_MAP + reg_core0_cpu_pri_19_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_20 + mac intr map register + 0x164 + 0x20 + + + CPU_PRI_20_MAP + reg_core0_cpu_pri_20_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_21 + mac intr map register + 0x168 + 0x20 + + + CPU_PRI_21_MAP + reg_core0_cpu_pri_21_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_22 + mac intr map register + 0x16C + 0x20 + + + CPU_PRI_22_MAP + reg_core0_cpu_pri_22_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_23 + mac intr map register + 0x170 + 0x20 + + + CPU_PRI_23_MAP + reg_core0_cpu_pri_23_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_24 + mac intr map register + 0x174 + 0x20 + + + CPU_PRI_24_MAP + reg_core0_cpu_pri_24_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_25 + mac intr map register + 0x178 + 0x20 + + + CPU_PRI_25_MAP + reg_core0_cpu_pri_25_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_26 + mac intr map register + 0x17C + 0x20 + + + CPU_PRI_26_MAP + reg_core0_cpu_pri_26_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_27 + mac intr map register + 0x180 + 0x20 + + + CPU_PRI_27_MAP + reg_core0_cpu_pri_27_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_28 + mac intr map register + 0x184 + 0x20 + + + CPU_PRI_28_MAP + reg_core0_cpu_pri_28_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_29 + mac intr map register + 0x188 + 0x20 + + + CPU_PRI_29_MAP + reg_core0_cpu_pri_29_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_30 + mac intr map register + 0x18C + 0x20 + + + CPU_PRI_30_MAP + reg_core0_cpu_pri_30_map + 0 + 4 + read-write + + + + + CPU_INT_PRI_31 + mac intr map register + 0x190 + 0x20 + + + CPU_PRI_31_MAP + reg_core0_cpu_pri_31_map + 0 + 4 + read-write + + + + + CPU_INT_THRESH + mac intr map register + 0x194 + 0x20 + + + CPU_INT_THRESH + reg_core0_cpu_int_thresh + 0 + 4 + read-write + + + + + INTERRUPT_REG_DATE + mac intr map register + 0x7FC + 0x20 + 0x02007210 + + + INTERRUPT_REG_DATE + reg_core0_interrupt_reg_date + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0x60 + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x000007FF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 4 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 4 + 4 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 8 + 4 + read-write + + + + + 22 + 0x4 + GPIO%s + IO MUX Configure Register for pad XTAL_32K_P + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02006050 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60019000 + + 0x0 + 0xB0 + registers + + + LEDC + 23 + + + + 6 + 0x14 + 0-5 + CH%s_CONF0 + LEDC_LSCH%s_CONF%s. + 0x0 + 0x20 + + + TIMER_SEL + reg_timer_sel_lsch0. + 0 + 2 + read-write + + + SIG_OUT_EN + reg_sig_out_en_lsch0. + 2 + 1 + read-write + + + IDLE_LV + reg_idle_lv_lsch0. + 3 + 1 + read-write + + + PARA_UP + reg_para_up_lsch0. + 4 + 1 + write-only + + + OVF_NUM + reg_ovf_num_lsch0. + 5 + 10 + read-write + + + OVF_CNT_EN + reg_ovf_cnt_en_lsch0. + 15 + 1 + read-write + + + OVF_CNT_RESET + reg_ovf_cnt_reset_lsch0. + 16 + 1 + write-only + + + + + 6 + 0x14 + 0-5 + CH%s_HPOINT + LEDC_LSCH%s_HPOINT. + 0x4 + 0x20 + + + HPOINT + reg_hpoint_lsch0. + 0 + 14 + read-write + + + + + 6 + 0x14 + 0-5 + CH%s_DUTY + LEDC_LSCH%s_DUTY. + 0x8 + 0x20 + + + DUTY + reg_duty_lsch0. + 0 + 19 + read-write + + + + + 6 + 0x14 + 0-5 + CH%s_CONF1 + LEDC_LSCH%s_CONF1. + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + reg_duty_scale_lsch0. + 0 + 10 + read-write + + + DUTY_CYCLE + reg_duty_cycle_lsch0. + 10 + 10 + read-write + + + DUTY_NUM + reg_duty_num_lsch0. + 20 + 10 + read-write + + + DUTY_INC + reg_duty_inc_lsch0. + 30 + 1 + read-write + + + DUTY_START + reg_duty_start_lsch0. + 31 + 1 + read-write + + + + + 6 + 0x14 + 0-5 + CH%s_DUTY_R + LEDC_LSCH%s_DUTY_R. + 0x10 + 0x20 + + + DUTY_R + reg_duty_lsch0_r. + 0 + 19 + read-only + + + + + 4 + 0x8 + 0-3 + TIMER%s_CONF + LEDC_LSTIMER%s_CONF. + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + reg_lstimer0_duty_res. + 0 + 4 + read-write + + + CLK_DIV + reg_clk_div_lstimer0. + 4 + 18 + read-write + + + PAUSE + reg_lstimer0_pause. + 22 + 1 + read-write + + + RST + reg_lstimer0_rst. + 23 + 1 + read-write + + + TICK_SEL + reg_tick_sel_lstimer0. + 24 + 1 + read-write + + + PARA_UP + reg_lstimer0_para_up. + 25 + 1 + write-only + + + + + 4 + 0x8 + 0-3 + TIMER%s_VALUE + LEDC_LSTIMER%s_VALUE. + 0xA4 + 0x20 + + + CNT + reg_lstimer0_cnt. + 0 + 14 + read-only + + + + + INT_RAW + LEDC_INT_RAW. + 0xC0 + 0x20 + + + LSTIMER0_OVF_INT_RAW + reg_lstimer0_ovf_int_raw. + 0 + 1 + read-only + + + LSTIMER1_OVF_INT_RAW + reg_lstimer1_ovf_int_raw. + 1 + 1 + read-only + + + LSTIMER2_OVF_INT_RAW + reg_lstimer2_ovf_int_raw. + 2 + 1 + read-only + + + LSTIMER3_OVF_INT_RAW + reg_lstimer3_ovf_int_raw. + 3 + 1 + read-only + + + DUTY_CHNG_END_LSCH0_INT_RAW + reg_duty_chng_end_lsch0_int_raw. + 4 + 1 + read-only + + + DUTY_CHNG_END_LSCH1_INT_RAW + reg_duty_chng_end_lsch1_int_raw. + 5 + 1 + read-only + + + DUTY_CHNG_END_LSCH2_INT_RAW + reg_duty_chng_end_lsch2_int_raw. + 6 + 1 + read-only + + + DUTY_CHNG_END_LSCH3_INT_RAW + reg_duty_chng_end_lsch3_int_raw. + 7 + 1 + read-only + + + DUTY_CHNG_END_LSCH4_INT_RAW + reg_duty_chng_end_lsch4_int_raw. + 8 + 1 + read-only + + + DUTY_CHNG_END_LSCH5_INT_RAW + reg_duty_chng_end_lsch5_int_raw. + 9 + 1 + read-only + + + OVF_CNT_LSCH0_INT_RAW + reg_ovf_cnt_lsch0_int_raw. + 10 + 1 + read-only + + + OVF_CNT_LSCH1_INT_RAW + reg_ovf_cnt_lsch1_int_raw. + 11 + 1 + read-only + + + OVF_CNT_LSCH2_INT_RAW + reg_ovf_cnt_lsch2_int_raw. + 12 + 1 + read-only + + + OVF_CNT_LSCH3_INT_RAW + reg_ovf_cnt_lsch3_int_raw. + 13 + 1 + read-only + + + OVF_CNT_LSCH4_INT_RAW + reg_ovf_cnt_lsch4_int_raw. + 14 + 1 + read-only + + + OVF_CNT_LSCH5_INT_RAW + reg_ovf_cnt_lsch5_int_raw. + 15 + 1 + read-only + + + + + INT_ST + LEDC_INT_ST. + 0xC4 + 0x20 + + + LSTIMER0_OVF_INT_ST + reg_lstimer0_ovf_int_st. + 0 + 1 + read-only + + + LSTIMER1_OVF_INT_ST + reg_lstimer1_ovf_int_st. + 1 + 1 + read-only + + + LSTIMER2_OVF_INT_ST + reg_lstimer2_ovf_int_st. + 2 + 1 + read-only + + + LSTIMER3_OVF_INT_ST + reg_lstimer3_ovf_int_st. + 3 + 1 + read-only + + + DUTY_CHNG_END_LSCH0_INT_ST + reg_duty_chng_end_lsch0_int_st. + 4 + 1 + read-only + + + DUTY_CHNG_END_LSCH1_INT_ST + reg_duty_chng_end_lsch1_int_st. + 5 + 1 + read-only + + + DUTY_CHNG_END_LSCH2_INT_ST + reg_duty_chng_end_lsch2_int_st. + 6 + 1 + read-only + + + DUTY_CHNG_END_LSCH3_INT_ST + reg_duty_chng_end_lsch3_int_st. + 7 + 1 + read-only + + + DUTY_CHNG_END_LSCH4_INT_ST + reg_duty_chng_end_lsch4_int_st. + 8 + 1 + read-only + + + DUTY_CHNG_END_LSCH5_INT_ST + reg_duty_chng_end_lsch5_int_st. + 9 + 1 + read-only + + + OVF_CNT_LSCH0_INT_ST + reg_ovf_cnt_lsch0_int_st. + 10 + 1 + read-only + + + OVF_CNT_LSCH1_INT_ST + reg_ovf_cnt_lsch1_int_st. + 11 + 1 + read-only + + + OVF_CNT_LSCH2_INT_ST + reg_ovf_cnt_lsch2_int_st. + 12 + 1 + read-only + + + OVF_CNT_LSCH3_INT_ST + reg_ovf_cnt_lsch3_int_st. + 13 + 1 + read-only + + + OVF_CNT_LSCH4_INT_ST + reg_ovf_cnt_lsch4_int_st. + 14 + 1 + read-only + + + OVF_CNT_LSCH5_INT_ST + reg_ovf_cnt_lsch5_int_st. + 15 + 1 + read-only + + + + + INT_ENA + LEDC_INT_ENA. + 0xC8 + 0x20 + + + LSTIMER0_OVF_INT_ENA + reg_lstimer0_ovf_int_ena. + 0 + 1 + read-write + + + LSTIMER1_OVF_INT_ENA + reg_lstimer1_ovf_int_ena. + 1 + 1 + read-write + + + LSTIMER2_OVF_INT_ENA + reg_lstimer2_ovf_int_ena. + 2 + 1 + read-write + + + LSTIMER3_OVF_INT_ENA + reg_lstimer3_ovf_int_ena. + 3 + 1 + read-write + + + DUTY_CHNG_END_LSCH0_INT_ENA + reg_duty_chng_end_lsch0_int_ena. + 4 + 1 + read-write + + + DUTY_CHNG_END_LSCH1_INT_ENA + reg_duty_chng_end_lsch1_int_ena. + 5 + 1 + read-write + + + DUTY_CHNG_END_LSCH2_INT_ENA + reg_duty_chng_end_lsch2_int_ena. + 6 + 1 + read-write + + + DUTY_CHNG_END_LSCH3_INT_ENA + reg_duty_chng_end_lsch3_int_ena. + 7 + 1 + read-write + + + DUTY_CHNG_END_LSCH4_INT_ENA + reg_duty_chng_end_lsch4_int_ena. + 8 + 1 + read-write + + + DUTY_CHNG_END_LSCH5_INT_ENA + reg_duty_chng_end_lsch5_int_ena. + 9 + 1 + read-write + + + OVF_CNT_LSCH0_INT_ENA + reg_ovf_cnt_lsch0_int_ena. + 10 + 1 + read-write + + + OVF_CNT_LSCH1_INT_ENA + reg_ovf_cnt_lsch1_int_ena. + 11 + 1 + read-write + + + OVF_CNT_LSCH2_INT_ENA + reg_ovf_cnt_lsch2_int_ena. + 12 + 1 + read-write + + + OVF_CNT_LSCH3_INT_ENA + reg_ovf_cnt_lsch3_int_ena. + 13 + 1 + read-write + + + OVF_CNT_LSCH4_INT_ENA + reg_ovf_cnt_lsch4_int_ena. + 14 + 1 + read-write + + + OVF_CNT_LSCH5_INT_ENA + reg_ovf_cnt_lsch5_int_ena. + 15 + 1 + read-write + + + + + INT_CLR + LEDC_INT_CLR. + 0xCC + 0x20 + + + LSTIMER0_OVF_INT_CLR + reg_lstimer0_ovf_int_clr. + 0 + 1 + write-only + + + LSTIMER1_OVF_INT_CLR + reg_lstimer1_ovf_int_clr. + 1 + 1 + write-only + + + LSTIMER2_OVF_INT_CLR + reg_lstimer2_ovf_int_clr. + 2 + 1 + write-only + + + LSTIMER3_OVF_INT_CLR + reg_lstimer3_ovf_int_clr. + 3 + 1 + write-only + + + DUTY_CHNG_END_LSCH0_INT_CLR + reg_duty_chng_end_lsch0_int_clr. + 4 + 1 + write-only + + + DUTY_CHNG_END_LSCH1_INT_CLR + reg_duty_chng_end_lsch1_int_clr. + 5 + 1 + write-only + + + DUTY_CHNG_END_LSCH2_INT_CLR + reg_duty_chng_end_lsch2_int_clr. + 6 + 1 + write-only + + + DUTY_CHNG_END_LSCH3_INT_CLR + reg_duty_chng_end_lsch3_int_clr. + 7 + 1 + write-only + + + DUTY_CHNG_END_LSCH4_INT_CLR + reg_duty_chng_end_lsch4_int_clr. + 8 + 1 + write-only + + + DUTY_CHNG_END_LSCH5_INT_CLR + reg_duty_chng_end_lsch5_int_clr. + 9 + 1 + write-only + + + OVF_CNT_LSCH0_INT_CLR + reg_ovf_cnt_lsch0_int_clr. + 10 + 1 + write-only + + + OVF_CNT_LSCH1_INT_CLR + reg_ovf_cnt_lsch1_int_clr. + 11 + 1 + write-only + + + OVF_CNT_LSCH2_INT_CLR + reg_ovf_cnt_lsch2_int_clr. + 12 + 1 + write-only + + + OVF_CNT_LSCH3_INT_CLR + reg_ovf_cnt_lsch3_int_clr. + 13 + 1 + write-only + + + OVF_CNT_LSCH4_INT_CLR + reg_ovf_cnt_lsch4_int_clr. + 14 + 1 + write-only + + + OVF_CNT_LSCH5_INT_CLR + reg_ovf_cnt_lsch5_int_clr. + 15 + 1 + write-only + + + + + CONF + LEDC_CONF. + 0xD0 + 0x20 + + + APB_CLK_SEL + reg_apb_clk_sel. + 0 + 2 + read-write + + + CLK_EN + reg_clk_en. + 31 + 1 + read-write + + + + + DATE + LEDC_DATE. + 0xFC + 0x20 + 0x19061700 + + + LEDC_DATE + reg_ledc_date. + 0 + 32 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x60016000 + + 0x0 + 0x78 + registers + + + RMT + 28 + + + + CH0DATA + RMT_CH0DATA_REG. + 0x0 + 0x20 + + + DATA + Reserved. + 0 + 32 + read-write + + + + + CH1DATA + RMT_CH1DATA_REG. + 0x4 + 0x20 + + + DATA + Reserved. + 0 + 32 + read-write + + + + + CH2DATA + RMT_CH2DATA_REG. + 0x8 + 0x20 + + + DATA + Reserved. + 0 + 32 + read-write + + + + + CH3DATA + RMT_CH3DATA_REG. + 0xC + 0x20 + + + DATA + Reserved. + 0 + 32 + read-write + + + + + 2 + 0x4 + 0-1 + CH%s_TX_CONF0 + RMT_CH%sCONF%s_REG. + 0x10 + 0x20 + 0x00710200 + + + TX_START + reg_tx_start_ch0. + 0 + 1 + write-only + + + MEM_RD_RST + reg_mem_rd_rst_ch0. + 1 + 1 + write-only + + + APB_MEM_RST + reg_apb_mem_rst_ch0. + 2 + 1 + write-only + + + TX_CONTI_MODE + reg_tx_conti_mode_ch0. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN + reg_mem_tx_wrap_en_ch0. + 4 + 1 + read-write + + + IDLE_OUT_LV + reg_idle_out_lv_ch0. + 5 + 1 + read-write + + + IDLE_OUT_EN + reg_idle_out_en_ch0. + 6 + 1 + read-write + + + TX_STOP + reg_tx_stop_ch0. + 7 + 1 + read-write + + + DIV_CNT + reg_div_cnt_ch0. + 8 + 8 + read-write + + + MEM_SIZE + reg_mem_size_ch0. + 16 + 3 + read-write + + + CARRIER_EFF_EN + reg_carrier_eff_en_ch0. + 20 + 1 + read-write + + + CARRIER_EN + reg_carrier_en_ch0. + 21 + 1 + read-write + + + CARRIER_OUT_LV + reg_carrier_out_lv_ch0. + 22 + 1 + read-write + + + AFIFO_RST + reg_afifo_rst_ch0. + 23 + 1 + write-only + + + CONF_UPDATE + reg_reg_conf_update_ch0. + 24 + 1 + write-only + + + + + 2 + 0x8 + 2-3 + CH%s_RX_CONF0 + RMT_CH2CONF0_REG. + 0x18 + 0x20 + 0x30FFFF02 + + + DIV_CNT + reg_div_cnt_ch2. + 0 + 8 + read-write + + + IDLE_THRES + reg_idle_thres_ch2. + 8 + 15 + read-write + + + MEM_SIZE + reg_mem_size_ch2. + 23 + 3 + read-write + + + CARRIER_EN + reg_carrier_en_ch2. + 28 + 1 + read-write + + + CARRIER_OUT_LV + reg_carrier_out_lv_ch2. + 29 + 1 + read-write + + + + + CH2CONF1 + RMT_CH2CONF1_REG. + 0x1C + 0x20 + 0x000001E8 + + + RX_EN + reg_rx_en_ch2. + 0 + 1 + read-write + + + MEM_WR_RST + reg_mem_wr_rst_ch2. + 1 + 1 + write-only + + + APB_MEM_RST + reg_apb_mem_rst_ch2. + 2 + 1 + write-only + + + MEM_OWNER + reg_mem_owner_ch2. + 3 + 1 + read-write + + + RX_FILTER_EN + reg_rx_filter_en_ch2. + 4 + 1 + read-write + + + RX_FILTER_THRES + reg_rx_filter_thres_ch2. + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + reg_mem_rx_wrap_en_ch2. + 13 + 1 + read-write + + + AFIFO_RST + reg_afifo_rst_ch2. + 14 + 1 + write-only + + + CONF_UPDATE + reg_conf_update_ch2. + 15 + 1 + write-only + + + + + CH3CONF1 + RMT_CH3CONF1_REG. + 0x24 + 0x20 + 0x000001E8 + + + RX_EN + reg_rx_en_ch3. + 0 + 1 + read-write + + + MEM_WR_RST + reg_mem_wr_rst_ch3. + 1 + 1 + write-only + + + APB_MEM_RST + reg_apb_mem_rst_ch3. + 2 + 1 + write-only + + + MEM_OWNER + reg_mem_owner_ch3. + 3 + 1 + read-write + + + RX_FILTER_EN + reg_rx_filter_en_ch3. + 4 + 1 + read-write + + + RX_FILTER_THRES + reg_rx_filter_thres_ch3. + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + reg_mem_rx_wrap_en_ch3. + 13 + 1 + read-write + + + AFIFO_RST + reg_afifo_rst_ch3. + 14 + 1 + write-only + + + CONF_UPDATE + reg_conf_update_ch3. + 15 + 1 + write-only + + + + + CH0STATUS + RMT_CH0STATUS_REG. + 0x28 + 0x20 + + + MEM_RADDR_EX + reg_mem_raddr_ex_ch0. + 0 + 9 + read-only + + + STATE + reg_state_ch0. + 9 + 3 + read-only + + + APB_MEM_WADDR + reg_apb_mem_waddr_ch0. + 12 + 9 + read-only + + + APB_MEM_RD_ERR + reg_apb_mem_rd_err_ch0. + 21 + 1 + read-only + + + MEM_EMPTY + reg_mem_empty_ch0. + 22 + 1 + read-only + + + APB_MEM_WR_ERR + reg_apb_mem_wr_err_ch0. + 23 + 1 + read-only + + + APB_MEM_RADDR + reg_apb_mem_raddr_ch0. + 24 + 8 + read-only + + + + + CH1STATUS + RMT_CH1STATUS_REG. + 0x2C + 0x20 + + + MEM_RADDR_EX + reg_mem_raddr_ex_ch1. + 0 + 9 + read-only + + + STATE + reg_state_ch1. + 9 + 3 + read-only + + + APB_MEM_WADDR + reg_apb_mem_waddr_ch1. + 12 + 9 + read-only + + + APB_MEM_RD_ERR + reg_apb_mem_rd_err_ch1. + 21 + 1 + read-only + + + MEM_EMPTY + reg_mem_empty_ch1. + 22 + 1 + read-only + + + APB_MEM_WR_ERR + reg_apb_mem_wr_err_ch1. + 23 + 1 + read-only + + + APB_MEM_RADDR + reg_apb_mem_raddr_ch1. + 24 + 8 + read-only + + + + + CH2STATUS + RMT_CH2STATUS_REG. + 0x30 + 0x20 + + + MEM_WADDR_EX + reg_mem_waddr_ex_ch2. + 0 + 9 + read-only + + + APB_MEM_RADDR + reg_apb_mem_raddr_ch2. + 12 + 9 + read-only + + + STATE + reg_state_ch2. + 22 + 3 + read-only + + + MEM_OWNER_ERR + reg_mem_owner_err_ch2. + 25 + 1 + read-only + + + MEM_FULL + reg_mem_full_ch2. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + reg_apb_mem_rd_err_ch2. + 27 + 1 + read-only + + + + + CH3STATUS + RMT_CH3STATUS_REG. + 0x34 + 0x20 + + + MEM_WADDR_EX + reg_mem_waddr_ex_ch3. + 0 + 9 + read-only + + + APB_MEM_RADDR + reg_apb_mem_raddr_ch3. + 12 + 9 + read-only + + + STATE + reg_state_ch3. + 22 + 3 + read-only + + + MEM_OWNER_ERR + reg_mem_owner_err_ch3. + 25 + 1 + read-only + + + MEM_FULL + reg_mem_full_ch3. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + reg_apb_mem_rd_err_ch3. + 27 + 1 + read-only + + + + + INT_RAW + RMT_INT_RAW_REG. + 0x38 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END_INT_RAW + reg_ch%s_tx_end_int_raw. + 0 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_END_INT_RAW + reg_ch2_rx_end_int_raw. + 2 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR_INT_RAW + reg_ch%s_err_int_raw. + 4 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR_INT_RAW + reg_ch2_err_int_raw. + 6 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT_INT_RAW + reg_ch%s_tx_thr_event_int_raw. + 8 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_RAW + reg_ch2_rx_thr_event_int_raw. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_RAW + reg_ch3_rx_thr_event_int_raw. + 11 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP_INT_RAW + reg_ch%s_tx_loop_int_raw. + 12 + 1 + read-only + + + + + INT_ST + RMT_INT_ST_REG. + 0x3C + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END_INT_ST + reg_ch%s_tx_end_int_st. + 0 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_END_INT_ST + reg_ch2_rx_end_int_st. + 2 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR_INT_ST + reg_ch%s_err_int_st. + 4 + 1 + read-only + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR_INT_ST + reg_ch2_err_int_st. + 6 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT_INT_ST + reg_ch%s_tx_thr_event_int_st. + 8 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_ST + reg_ch2_rx_thr_event_int_st. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_ST + reg_ch3_rx_thr_event_int_st. + 11 + 1 + read-only + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP_INT_ST + reg_ch%s_tx_loop_int_st. + 12 + 1 + read-only + + + + + INT_ENA + RMT_INT_ENA_REG. + 0x40 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END_INT_ENA + reg_ch%s_tx_end_int_ena. + 0 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_END_INT_ENA + reg_ch2_rx_end_int_ena. + 2 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR_INT_ENA + reg_ch%s_err_int_ena. + 4 + 1 + read-write + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR_INT_ENA + reg_ch2_err_int_ena. + 6 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT_INT_ENA + reg_ch%s_tx_thr_event_int_ena. + 8 + 1 + read-write + + + CH2_RX_THR_EVENT_INT_ENA + reg_ch2_rx_thr_event_int_ena. + 10 + 1 + read-write + + + CH3_RX_THR_EVENT_INT_ENA + reg_ch3_rx_thr_event_int_ena. + 11 + 1 + read-write + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP_INT_ENA + reg_ch%s_tx_loop_int_ena. + 12 + 1 + read-write + + + + + INT_CLR + RMT_INT_CLR_REG. + 0x44 + 0x20 + + + 2 + 0x1 + 0-1 + CH%s_TX_END_INT_CLR + reg_ch%s_tx_end_int_clr. + 0 + 1 + write-only + + + 2 + 0x1 + 2-3 + CH%s_RX_END_INT_CLR + reg_ch2_rx_end_int_clr. + 2 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_ERR_INT_CLR + reg_ch%s_err_int_clr. + 4 + 1 + write-only + + + 2 + 0x1 + 2-3 + CH%s_RX_ERR_INT_CLR + reg_ch2_err_int_clr. + 6 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_THR_EVENT_INT_CLR + reg_ch%s_tx_thr_event_int_clr. + 8 + 1 + write-only + + + CH2_RX_THR_EVENT_INT_CLR + reg_ch2_rx_thr_event_int_clr. + 10 + 1 + write-only + + + CH3_RX_THR_EVENT_INT_CLR + reg_ch3_rx_thr_event_int_clr. + 11 + 1 + write-only + + + 2 + 0x1 + 0-1 + CH%s_TX_LOOP_INT_CLR + reg_ch%s_tx_loop_int_clr. + 12 + 1 + write-only + + + + + CH0CARRIER_DUTY + RMT_CH0CARRIER_DUTY_REG. + 0x48 + 0x20 + 0x00400040 + + + CARRIER_LOW + reg_carrier_low_ch0. + 0 + 16 + read-write + + + CARRIER_HIGH + reg_carrier_high_ch0. + 16 + 16 + read-write + + + + + CH1CARRIER_DUTY + RMT_CH1CARRIER_DUTY_REG. + 0x4C + 0x20 + 0x00400040 + + + CARRIER_LOW + reg_carrier_low_ch1. + 0 + 16 + read-write + + + CARRIER_HIGH + reg_carrier_high_ch1. + 16 + 16 + read-write + + + + + CH2_RX_CARRIER_RM + RMT_CH2_RX_CARRIER_RM_REG. + 0x50 + 0x20 + + + CARRIER_LOW_THRES + reg_carrier_low_thres_ch2. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + reg_carrier_high_thres_ch2. + 16 + 16 + read-write + + + + + CH3_RX_CARRIER_RM + RMT_CH3_RX_CARRIER_RM_REG. + 0x54 + 0x20 + + + CARRIER_LOW_THRES + reg_carrier_low_thres_ch3. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + reg_carrier_high_thres_ch3. + 16 + 16 + read-write + + + + + 2 + 0x4 + 0-1 + CH%s_TX_LIM + RMT_CH%s_TX_LIM_REG. + 0x58 + 0x20 + 0x00000080 + + + TX_LIM + reg_rmt_tx_lim_ch0. + 0 + 9 + read-write + + + TX_LOOP_NUM + reg_rmt_tx_loop_num_ch0. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + reg_rmt_tx_loop_cnt_en_ch0. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + reg_loop_count_reset_ch0. + 20 + 1 + write-only + + + + + 2 + 0x4 + 2-3 + CH%s_RX_LIM + RMT_CH2_RX_LIM_REG. + 0x60 + 0x20 + 0x00000080 + + + RX_LIM + reg_rmt_rx_lim_ch2. + 0 + 9 + read-write + + + + + SYS_CONF + RMT_SYS_CONF_REG. + 0x68 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + reg_apb_fifo_mask. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + reg_mem_clk_force_on. + 1 + 1 + read-write + + + MEM_FORCE_PD + reg_rmt_mem_force_pd. + 2 + 1 + read-write + + + MEM_FORCE_PU + reg_rmt_mem_force_pu. + 3 + 1 + read-write + + + SCLK_DIV_NUM + reg_rmt_sclk_div_num. + 4 + 8 + read-write + + + SCLK_DIV_A + reg_rmt_sclk_div_a. + 12 + 6 + read-write + + + SCLK_DIV_B + reg_rmt_sclk_div_b. + 18 + 6 + read-write + + + SCLK_SEL + reg_rmt_sclk_sel. + 24 + 2 + read-write + + + SCLK_ACTIVE + reg_rmt_sclk_active. + 26 + 1 + read-write + + + CLK_EN + reg_clk_en. + 31 + 1 + read-write + + + + + TX_SIM + RMT_TX_SIM_REG. + 0x6C + 0x20 + + + TX_SIM_CH0 + reg_rmt_tx_sim_ch0. + 0 + 1 + read-write + + + TX_SIM_CH1 + reg_rmt_tx_sim_ch1. + 1 + 1 + read-write + + + TX_SIM_EN + reg_rmt_tx_sim_en. + 2 + 1 + read-write + + + + + REF_CNT_RST + RMT_REF_CNT_RST_REG. + 0x70 + 0x20 + + + CH0 + reg_ref_cnt_rst_ch0. + 0 + 1 + write-only + + + CH1 + reg_ref_cnt_rst_ch1. + 1 + 1 + write-only + + + CH2 + reg_ref_cnt_rst_ch2. + 2 + 1 + write-only + + + CH3 + reg_ref_cnt_rst_ch3. + 3 + 1 + write-only + + + + + DATE + RMT_DATE_REG. + 0xCC + 0x20 + 0x02006231 + + + DATE + reg_rmt_date. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60026000 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0xB0 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x74 + registers + + + RSA + 47 + + + + 16 + 0x1 + M_MEM[%s] + The memory that stores M + 0x0 + 0x8 + + + 16 + 0x1 + Z_MEM[%s] + The memory that stores Z + 0x200 + 0x8 + + + 16 + 0x1 + Y_MEM[%s] + The memory that stores Y + 0x400 + 0x8 + + + 16 + 0x1 + X_MEM[%s] + The memory that stores X + 0x600 + 0x8 + + + M_PRIME + RSA M_prime register + 0x800 + 0x20 + + + M_PRIME + Those bits stores m' + 0 + 32 + read-write + + + + + MODE + RSA mode register + 0x804 + 0x20 + + + MODE + rsa mode (rsa length). + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA query clean register + 0x808 + 0x20 + + + QUERY_CLEAN + query clean + 0 + 1 + read-only + + + + + SET_START_MODEXP + RSA modular exponentiation trigger register. + 0x80C + 0x20 + + + SET_START_MODEXP + start modular exponentiation + 0 + 1 + write-only + + + + + SET_START_MODMULT + RSA modular multiplication trigger register. + 0x810 + 0x20 + + + SET_START_MODMULT + start modular multiplication + 0 + 1 + write-only + + + + + SET_START_MULT + RSA normal multiplication trigger register. + 0x814 + 0x20 + + + SET_START_MULT + start multiplicaiton + 0 + 1 + write-only + + + + + QUERY_IDLE + RSA query idle register + 0x818 + 0x20 + + + QUERY_IDLE + query rsa idle. 1'b0: busy, 1'b1: idle + 0 + 1 + read-only + + + + + INT_CLR + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to clear RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + RSA constant time option register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + RSA search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default). + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + RTC_CNTL + Real-Time Clock Control + RTC_CNTL + 0x60008000 + + 0x0 + 0x12C + registers + + + RTC_CORE + 27 + + + + OPTIONS0 + rtc configure register + 0x0 + 0x20 + 0x1C00A000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset + 4 + 1 + write-only + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + XTL_EN_WAIT + wait bias_sleep and current source wakeup + 14 + 4 + read-write + + + XTL_EXT_CTR_SEL + analog configure + 20 + 3 + read-write + + + XTL_FORCE_ISO + analog configure + 23 + 1 + read-write + + + PLL_FORCE_ISO + analog configure + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + analog configure + 25 + 1 + read-write + + + XTL_FORCE_NOISO + analog configure + 26 + 1 + read-write + + + PLL_FORCE_NOISO + analog configure + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + analog configure + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + write-only + + + + + SLP_TIMER0 + rtc configure register + 0x4 + 0x20 + + + SLP_VAL_LO + configure the sleep time + 0 + 32 + read-write + + + + + SLP_TIMER1 + rtc configure register + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + write-only + + + + + TIME_UPDATE + rtc configure register + 0xC + 0x20 + + + TIMER_SYS_STALL + Enable to record system stall time + 27 + 1 + read-write + + + TIMER_XTL_OFF + Enable to record 40M XTAL OFF time + 28 + 1 + read-write + + + TIMER_SYS_RST + enable to record system reset time + 29 + 1 + read-write + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + write-only + + + + + TIME_LOW0 + rtc configure register + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH0 + rtc configure register + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + STATE0 + rtc configure register + 0x18 + 0x20 + + + SW_CPU_INT + rtc software interrupt to main cpu + 0 + 1 + write-only + + + SLP_REJECT_CAUSE_CLR + clear rtc sleep reject cause + 1 + 1 + write-only + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-only + + + SLP_WAKEUP + leep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + leep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + rtc configure register + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + rtc configure register + 0x20 + 0x20 + 0x01000000 + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER3 + rtc configure register + 0x24 + 0x20 + 0x0A080A08 + + + WIFI_WAIT_TIMER + wifi power domain wakeup time + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + wifi power domain power on time + 9 + 7 + read-write + + + BT_WAIT_TIMER + bt power domain wakeup time + 16 + 9 + read-write + + + BT_POWERUP_TIMER + bt power domain power on time + 25 + 7 + read-write + + + + + TIMER4 + rtc configure register + 0x28 + 0x20 + 0x10200A08 + + + CPU_TOP_WAIT_TIMER + cpu top power domain wakeup time + 0 + 9 + read-write + + + CPU_TOP_POWERUP_TIMER + cpu top power domain power on time + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + digital wrap power domain wakeup time + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + digital wrap power domain power on time + 25 + 7 + read-write + + + + + TIMER5 + rtc configure register + 0x2C + 0x20 + 0x00008000 + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + + + TIMER6 + rtc configure register + 0x30 + 0x20 + 0x0A080000 + + + DG_PERI_WAIT_TIMER + digital peri power domain wakeup time + 16 + 9 + read-write + + + DG_PERI_POWERUP_TIMER + digital peri power domain power on time + 25 + 7 + read-write + + + + + ANA_CONF + rtc configure register + 0x34 + 0x20 + 0x00C40000 + + + RESET_POR_FORCE_PD + force no bypass i2c power on reset + 18 + 1 + read-write + + + RESET_POR_FORCE_PU + force bypass i2c power on reset + 19 + 1 + read-write + + + GLITCH_RST_EN + enable glitch reset + 20 + 1 + read-write + + + SAR_I2C_PU + PLLA force power up + 22 + 1 + read-write + + + PLLA_FORCE_PD + PLLA force power down + 23 + 1 + read-write + + + PLLA_FORCE_PU + PLLA force power up + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up + 30 + 1 + read-write + + + PLL_I2C_PU + power up pll i2c + 31 + 1 + read-write + + + + + RESET_STATE + rtc configure register + 0x38 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + STAT_VECTOR_SEL_APPCPU + APP CPU state vector sel + 12 + 1 + read-write + + + STAT_VECTOR_SEL_PROCPU + PRO CPU state vector sel + 13 + 1 + read-write + + + ALL_RESET_FLAG_PROCPU + PRO CPU reset_flag + 14 + 1 + read-only + + + ALL_RESET_FLAG_APPCPU + APP CPU reset flag + 15 + 1 + read-only + + + ALL_RESET_FLAG_CLR_PROCPU + clear PRO CPU reset_flag + 16 + 1 + write-only + + + ALL_RESET_FLAG_CLR_APPCPU + clear APP CPU reset flag + 17 + 1 + write-only + + + OCD_HALT_ON_RESET_APPCPU + APPCPU OcdHaltOnReset + 18 + 1 + read-write + + + OCD_HALT_ON_RESET_PROCPU + PROCPU OcdHaltOnReset + 19 + 1 + read-write + + + JTAG_RESET_FLAG_PROCPU + configure jtag reset configure + 20 + 1 + read-only + + + JTAG_RESET_FLAG_APPCPU + configure jtag reset configure + 21 + 1 + read-only + + + JTAG_RESET_FLAG_CLR_PROCPU + configure jtag reset configure + 22 + 1 + write-only + + + JTAG_RESET_FLAG_CLR_APPCPU + configure jtag reset configure + 23 + 1 + write-only + + + DRESET_MASK_APPCPU + configure dreset configure + 24 + 1 + read-write + + + DRESET_MASK_PROCPU + configure dreset configure + 25 + 1 + read-write + + + + + WAKEUP_STATE + rtc configure register + 0x3C + 0x20 + 0x00060000 + + + WAKEUP_ENA + wakeup enable bitmap + 15 + 17 + read-write + + + + + INT_ENA_RTC + rtc configure register + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + read-write + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + read-write + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 10 + 1 + read-write + + + SWD_INT_ENA + enable super watch dog interrupt + 15 + 1 + read-write + + + XTAL32K_DEAD_INT_ENA + enable xtal32k_dead interrupt + 16 + 1 + read-write + + + GLITCH_DET_INT_ENA + enbale gitch det interrupt + 19 + 1 + read-write + + + BBPLL_CAL_INT_ENA + enbale bbpll cal end interrupt + 20 + 1 + read-write + + + + + INT_RAW_RTC + rtc configure register + 0x44 + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-only + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-only + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 9 + 1 + read-only + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 10 + 1 + read-only + + + SWD_INT_RAW + super watch dog interrupt raw + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_RAW + xtal32k dead detection interrupt raw + 16 + 1 + read-only + + + GLITCH_DET_INT_RAW + glitch_det_interrupt_raw + 19 + 1 + read-only + + + BBPLL_CAL_INT_RAW + bbpll cal end interrupt state + 20 + 1 + read-only + + + + + INT_ST_RTC + rtc configure register + 0x48 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-only + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-only + + + BROWN_OUT_INT_ST + brown out interrupt state + 9 + 1 + read-only + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 10 + 1 + read-only + + + SWD_INT_ST + super watch dog interrupt state + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_ST + xtal32k dead detection interrupt state + 16 + 1 + read-only + + + GLITCH_DET_INT_ST + glitch_det_interrupt state + 19 + 1 + read-only + + + BBPLL_CAL_INT_ST + bbpll cal end interrupt state + 20 + 1 + read-only + + + + + INT_CLR_RTC + rtc configure register + 0x4C + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + write-only + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 9 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 10 + 1 + write-only + + + SWD_INT_CLR + Clear super watch dog interrupt state + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_CLR + Clear RTC WDT interrupt state + 16 + 1 + write-only + + + GLITCH_DET_INT_CLR + Clear glitch det interrupt state + 19 + 1 + write-only + + + BBPLL_CAL_INT_CLR + clear bbpll cal end interrupt state + 20 + 1 + write-only + + + + + STORE0 + rtc configure register + 0x50 + 0x20 + + + SCRATCH0 + reserved register + 0 + 32 + read-write + + + + + STORE1 + rtc configure register + 0x54 + 0x20 + + + SCRATCH1 + reserved register + 0 + 32 + read-write + + + + + STORE2 + rtc configure register + 0x58 + 0x20 + + + SCRATCH2 + reserved register + 0 + 32 + read-write + + + + + STORE3 + rtc configure register + 0x5C + 0x20 + + + SCRATCH3 + reserved register + 0 + 32 + read-write + + + + + EXT_XTL_CONF + rtc configure register + 0x60 + 0x20 + 0x00066C80 + + + XTAL32K_WDT_EN + xtal 32k watch dog enable + 0 + 1 + read-write + + + XTAL32K_WDT_CLK_FO + xtal 32k watch dog clock force on + 1 + 1 + read-write + + + XTAL32K_WDT_RESET + xtal 32k watch dog sw reset + 2 + 1 + read-write + + + XTAL32K_EXT_CLK_FO + xtal 32k external xtal clock force on + 3 + 1 + read-write + + + XTAL32K_AUTO_BACKUP + xtal 32k switch to back up clock when xtal is dead + 4 + 1 + read-write + + + XTAL32K_AUTO_RESTART + xtal 32k restart xtal when xtal is dead + 5 + 1 + read-write + + + XTAL32K_AUTO_RETURN + xtal 32k switch back xtal when xtal is restarted + 6 + 1 + read-write + + + XTAL32K_XPD_FORCE + Xtal 32k xpd control by sw or fsm + 7 + 1 + read-write + + + ENCKINIT_XTAL_32K + apply an internal clock to help xtal 32k to start + 8 + 1 + read-write + + + DBUF_XTAL_32K + 0: single-end buffer 1: differential buffer + 9 + 1 + read-write + + + DGM_XTAL_32K + xtal_32k gm control + 10 + 3 + read-write + + + DRES_XTAL_32K + DRES_XTAL_32K + 13 + 3 + read-write + + + XPD_XTAL_32K + XPD_XTAL_32K + 16 + 1 + read-write + + + DAC_XTAL_32K + DAC_XTAL_32K + 17 + 3 + read-write + + + WDT_STATE + state of 32k_wdt + 20 + 3 + read-only + + + XTAL32K_GPIO_SEL + XTAL_32K sel. 0: external XTAL_32K + 23 + 1 + read-write + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + enable gpio configure xtal power on + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + rtc configure register + 0x64 + 0x20 + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + rtc configure register + 0x68 + 0x20 + + + SLEEP_REJECT_ENA + sleep reject enable + 12 + 18 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + rtc configure register + 0x6C + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + CPU clk sel option + 30 + 2 + read-write + + + + + CLK_CONF + rtc configure register + 0x70 + 0x20 + 0x11583218 + + + EFUSE_CLK_FORCE_GATING + efuse_clk_force_gating + 1 + 1 + read-write + + + EFUSE_CLK_FORCE_NOGATING + efuse_clk_force_nogating + 2 + 1 + read-write + + + CK8M_DIV_SEL_VLD + used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + 3 + 1 + read-write + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128 + 4 + 2 + read-write + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M + 7 + 1 + read-write + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + XTAL_GLOBAL_FORCE_GATING + force enable xtal clk gating + 27 + 1 + read-write + + + XTAL_GLOBAL_FORCE_NOGATING + force bypass xtal clk gating + 28 + 1 + read-write + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4 + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + slelect rtc slow clk + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + rtc configure register + 0x74 + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + used to sync div bus. clear vld before set reg_rtc_ana_clk_div + 22 + 1 + read-write + + + ANA_CLK_DIV + the clk divider num of RTC_CLK + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + flag rtc_slow_clk_next_edge + 31 + 1 + read-write + + + + + SDIO_CONF + rtc configure register + 0x78 + 0x20 + 0x0AB0BE0A + + + SDIO_TIMER_TARGET + timer count to apply reg_sdio_dcap after sdio power on + 0 + 8 + read-write + + + SDIO_DTHDRV + Tieh = 1 mode drive ability. Initially set to 0 to limit charge current + 9 + 2 + read-write + + + SDIO_DCAP + ability to prevent LDO from overshoot + 11 + 2 + read-write + + + SDIO_INITI + add resistor from ldo output to ground. 0: no res + 13 + 2 + read-write + + + SDIO_EN_INITI + 0 to set init[1:0]=0 + 15 + 1 + read-write + + + SDIO_DCURLIM + tune current limit threshold when tieh = 0. About 800mA/(8+d) + 16 + 3 + read-write + + + SDIO_MODECURLIM + select current limit mode + 19 + 1 + read-write + + + SDIO_ENCURLIM + enable current limit + 20 + 1 + read-write + + + SDIO_REG_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + _1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + 31 + 1 + read-write + + + + + BIAS_CONF + rtc configure register + 0x7C + 0x20 + 0x00010800 + + + DG_VDD_DRV_B_SLP + 0 + 8 + read-write + + + DG_VDD_DRV_B_SLP_EN + 8 + 1 + read-write + + + BIAS_BUF_IDLE + bias buf when rtc in normal work state + 10 + 1 + read-write + + + BIAS_BUF_WAKE + bias buf when rtc in wakeup state + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + bias buf when rtc in sleep state + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + bias buf when rtc in monitor state + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in monitor state + 22 + 4 + read-write + + + + + RTC_CNTL + rtc configure register + 0x80 + 0x20 + 0xA0000000 + + + DIG_REG_CAL_EN + software enable digital regulator cali + 7 + 1 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + REGULATOR_FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + RTC_REG force power up + 31 + 1 + read-write + + + + + PWC + rtc configure register + 0x84 + 0x20 + + + PAD_FORCE_HOLD + rtc pad force hold + 21 + 1 + read-write + + + + + DIG_PWC + rtc configure register + 0x88 + 0x20 + 0x00555010 + + + VDD_SPI_PWR_DRV + vdd_spi drv's software value + 0 + 2 + read-write + + + VDD_SPI_PWR_FORCE + vdd_spi drv use software value + 2 + 1 + read-write + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force PU in sleep + 4 + 1 + read-write + + + BT_FORCE_PD + bt force power down + 11 + 1 + read-write + + + BT_FORCE_PU + bt force power up + 12 + 1 + read-write + + + DG_PERI_FORCE_PD + digital peri force power down + 13 + 1 + read-write + + + DG_PERI_FORCE_PU + digital peri force power up + 14 + 1 + read-write + + + FASTMEM_FORCE_LPD + fastmemory retention mode in sleep + 15 + 1 + read-write + + + FASTMEM_FORCE_LPU + fastmemory donlt entry retention mode in sleep + 16 + 1 + read-write + + + WIFI_FORCE_PD + wifi force power down + 17 + 1 + read-write + + + WIFI_FORCE_PU + wifi force power up + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + CPU_TOP_FORCE_PD + cpu core force power down + 21 + 1 + read-write + + + CPU_TOP_FORCE_PU + cpu force power up + 22 + 1 + read-write + + + BT_PD_EN + enable power down bt in sleep + 27 + 1 + read-write + + + DG_PERI_PD_EN + enable power down digital peri in sleep + 28 + 1 + read-write + + + CPU_TOP_PD_EN + enable power down cpu in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + enable power down wifi in sleep + 30 + 1 + read-write + + + DG_WRAP_PD_EN + enable power down digital wrap in sleep + 31 + 1 + read-write + + + + + DIG_ISO + rtc configure register + 0x8C + 0x20 + 0xAA805080 + + + FORCE_OFF + DIG_ISO force off + 7 + 1 + read-write + + + FORCE_ON + DIG_ISO force on + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + BT_FORCE_ISO + bt force ISO + 22 + 1 + read-write + + + BT_FORCE_NOISO + bt force no ISO + 23 + 1 + read-write + + + DG_PERI_FORCE_ISO + Digital peri force ISO + 24 + 1 + read-write + + + DG_PERI_FORCE_NOISO + digital peri force no ISO + 25 + 1 + read-write + + + CPU_TOP_FORCE_ISO + cpu force ISO + 26 + 1 + read-write + + + CPU_TOP_FORCE_NOISO + cpu force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + wifi force ISO + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + wifi force no ISO + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + digital core force no ISO + 31 + 1 + read-write + + + + + WDTCONFIG0 + rtc configure register + 0x90 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 16 + 3 + read-write + + + WDT_STG3 + 1: interrupt stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en + 28 + 3 + read-write + + + WDT_EN + enable rtc wdt + 31 + 1 + read-write + + + + + WDTCONFIG1 + rtc configure register + 0x94 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + the hold time of stage0 + 0 + 32 + read-write + + + + + WDTCONFIG2 + rtc configure register + 0x98 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + the hold time of stage1 + 0 + 32 + read-write + + + + + WDTCONFIG3 + rtc configure register + 0x9C + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + the hold time of stage2 + 0 + 32 + read-write + + + + + WDTCONFIG4 + rtc configure register + 0xA0 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + the hold time of stage3 + 0 + 32 + read-write + + + + + WDTFEED + rtc configure register + 0xA4 + 0x20 + + + WDT_FEED + sw feed rtc wdt + 31 + 1 + write-only + + + + + WDTWPROTECT + rtc configure register + 0xA8 + 0x20 + + + WDT_WKEY + the key of rtc wdt + 0 + 32 + read-write + + + + + SWD_CONF + rtc configure register + 0xAC + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + swd reset flag + 0 + 1 + read-only + + + SWD_FEED_INT + swd interrupt for feeding + 1 + 1 + read-only + + + SWD_BYPASS_RST + Bypass swd rst + 17 + 1 + read-write + + + SWD_SIGNAL_WIDTH + adjust signal width send to swd + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + reset swd reset flag + 28 + 1 + write-only + + + SWD_FEED + Sw feed swd + 29 + 1 + write-only + + + SWD_DISABLE + disabel SWD + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + automatically feed swd when int comes + 31 + 1 + read-write + + + + + SWD_WPROTECT + rtc configure register + 0xB0 + 0x20 + + + SWD_WKEY + the key of super wdt + 0 + 32 + read-write + + + + + SW_CPU_STALL + rtc configure register + 0xB4 + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0] + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + stall cpu by software + 26 + 6 + read-write + + + + + STORE4 + rtc configure register + 0xB8 + 0x20 + + + SCRATCH4 + reserved register + 0 + 32 + read-write + + + + + STORE5 + rtc configure register + 0xBC + 0x20 + + + SCRATCH5 + reserved register + 0 + 32 + read-write + + + + + STORE6 + rtc configure register + 0xC0 + 0x20 + + + SCRATCH6 + reserved register + 0 + 32 + read-write + + + + + STORE7 + rtc configure register + 0xC4 + 0x20 + + + SCRATCH7 + reserved register + 0 + 32 + read-write + + + + + LOW_POWER_ST + rtc configure register + 0xC8 + 0x20 + + + XPD_ROM0 + rom0 power down + 0 + 1 + read-only + + + XPD_DIG_DCDC + External DCDC power down + 2 + 1 + read-only + + + PERI_ISO + rtc peripheral iso + 3 + 1 + read-only + + + XPD_RTC_PERI + rtc peripheral power down + 4 + 1 + read-only + + + WIFI_ISO + wifi iso + 5 + 1 + read-only + + + XPD_WIFI + wifi wrap power down + 6 + 1 + read-only + + + DIG_ISO + digital wrap iso + 7 + 1 + read-only + + + XPD_DIG + digital wrap power down + 8 + 1 + read-only + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-only + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-only + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-only + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-only + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-only + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-only + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-only + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-only + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-only + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-only + + + RDY_FOR_WAKEUP + rtc is ready to receive wake up trigger from wake up source + 19 + 1 + read-only + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-only + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-only + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-only + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-only + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-only + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-only + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-only + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-only + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-only + + + + + DIAG0 + rtc configure register + 0xCC + 0x20 + + + LOW_POWER_DIAG1 + 0 + 32 + read-only + + + + + PAD_HOLD + rtc configure register + 0xD0 + 0x20 + + + GPIO_PIN0_HOLD + the hold configure of rtc gpio0 + 0 + 1 + read-write + + + GPIO_PIN1_HOLD + the hold configure of rtc gpio1 + 1 + 1 + read-write + + + GPIO_PIN2_HOLD + the hold configure of rtc gpio2 + 2 + 1 + read-write + + + GPIO_PIN3_HOLD + the hold configure of rtc gpio3 + 3 + 1 + read-write + + + GPIO_PIN4_HOLD + the hold configure of rtc gpio4 + 4 + 1 + read-write + + + GPIO_PIN5_HOLD + the hold configure of rtc gpio5 + 5 + 1 + read-write + + + + + DIG_PAD_HOLD + rtc configure register + 0xD4 + 0x20 + + + DIG_PAD_HOLD + the configure of digital pad + 0 + 32 + read-write + + + + + BROWN_OUT + rtc configure register + 0xD8 + 0x20 + 0x43FF0010 + + + BROWN_OUT_INT_WAIT + brown out interrupt wait cycles + 4 + 10 + read-write + + + BROWN_OUT_CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + BROWN_OUT_PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + BROWN_OUT_RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + BROWN_OUT_RST_ENA + enable brown out reset + 26 + 1 + read-write + + + BROWN_OUT_RST_SEL + 1: 4-pos reset + 27 + 1 + read-write + + + BROWN_OUT_ANA_RST_EN + brown_out origin reset enable + 28 + 1 + read-write + + + BROWN_OUT_CNT_CLR + clear brown out counter + 29 + 1 + write-only + + + BROWN_OUT_ENA + enable brown out + 30 + 1 + read-write + + + DET + the flag of brown det from analog + 31 + 1 + read-only + + + + + TIME_LOW1 + rtc configure register + 0xDC + 0x20 + + + TIMER_VALUE1_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH1 + rtc configure register + 0xE0 + 0x20 + + + TIMER_VALUE1_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + XTAL32K_CLK_FACTOR + rtc configure register + 0xE4 + 0x20 + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0 + 32 + read-write + + + + + XTAL32K_CONF + rtc configure register + 0xE8 + 0x20 + 0x0FF00000 + + + XTAL32K_RETURN_WAIT + cycles to wait to return noral xtal 32k + 0 + 4 + read-write + + + XTAL32K_RESTART_WAIT + cycles to wait to repower on xtal 32k + 4 + 16 + read-write + + + XTAL32K_WDT_TIMEOUT + If no clock detected for this amount of time + 20 + 8 + read-write + + + XTAL32K_STABLE_THRES + if restarted xtal32k period is smaller than this + 28 + 4 + read-write + + + + + USB_CONF + rtc configure register + 0xEC + 0x20 + + + IO_MUX_RESET_DISABLE + disable io_mux reset + 18 + 1 + read-write + + + + + SLP_REJECT_CAUSE + RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG + 0xF0 + 0x20 + + + REJECT_CAUSE + sleep reject cause + 0 + 18 + read-only + + + + + OPTION1 + rtc configure register + 0xF4 + 0x20 + + + FORCE_DOWNLOAD_BOOT + force chip entry download mode + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG + 0xF8 + 0x20 + + + WAKEUP_CAUSE + sleep wakeup cause + 0 + 17 + read-only + + + + + ULP_CP_TIMER_1 + rtc configure register + 0xFC + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + INT_ENA_RTC_W1TS + rtc configure register + 0x100 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TS + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TS + enable sleep reject interrupt + 1 + 1 + write-only + + + WDT_INT_ENA_W1TS + enable RTC WDT interrupt + 3 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TS + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TS + enable RTC main timer interrupt + 10 + 1 + write-only + + + SWD_INT_ENA_W1TS + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TS + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TS + enbale gitch det interrupt + 19 + 1 + write-only + + + BBPLL_CAL_INT_ENA_W1TS + enbale bbpll cal interrupt + 20 + 1 + write-only + + + + + INT_ENA_RTC_W1TC + rtc configure register + 0x104 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TC + clear sleep wakeup interrupt enable + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TC + clear sleep reject interrupt enable + 1 + 1 + write-only + + + WDT_INT_ENA_W1TC + clear RTC WDT interrupt enable + 3 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TC + clear brown out interrupt enable + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TC + Clear RTC main timer interrupt enable + 10 + 1 + write-only + + + SWD_INT_ENA_W1TC + clear super watch dog interrupt enable + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TC + clear xtal32k_dead interrupt enable + 16 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TC + clear gitch det interrupt enable + 19 + 1 + write-only + + + BBPLL_CAL_INT_ENA_W1TC + clear bbpll cal interrupt enable + 20 + 1 + write-only + + + + + RETENTION_CTRL + rtc configure register + 0x108 + 0x20 + 0xA0D00000 + + + RETENTION_CLK_SEL + Retention clk sel + 18 + 1 + read-write + + + RETENTION_DONE_WAIT + Retention done wait time + 19 + 3 + read-write + + + RETENTION_CLKOFF_WAIT + Retention clkoff wait time + 22 + 4 + read-write + + + RETENTION_EN + enable cpu retention when light sleep + 26 + 1 + read-write + + + RETENTION_WAIT + wait cycles for rention operation + 27 + 5 + read-write + + + + + FIB_SEL + rtc configure register + 0x10C + 0x20 + 0x00000007 + + + FIB_SEL + select use analog fib signal + 0 + 3 + read-write + + + + + GPIO_WAKEUP + rtc configure register + 0x110 + 0x20 + + + GPIO_WAKEUP_STATUS + rtc gpio wakeup flag + 0 + 6 + read-only + + + GPIO_WAKEUP_STATUS_CLR + clear rtc gpio wakeup flag + 6 + 1 + read-write + + + GPIO_PIN_CLK_GATE + enable rtc io clk gate + 7 + 1 + read-write + + + GPIO_PIN5_INT_TYPE + configure gpio wakeup type + 8 + 3 + read-write + + + GPIO_PIN4_INT_TYPE + configure gpio wakeup type + 11 + 3 + read-write + + + GPIO_PIN3_INT_TYPE + configure gpio wakeup type + 14 + 3 + read-write + + + GPIO_PIN2_INT_TYPE + configure gpio wakeup type + 17 + 3 + read-write + + + GPIO_PIN1_INT_TYPE + configure gpio wakeup type + 20 + 3 + read-write + + + GPIO_PIN0_INT_TYPE + configure gpio wakeup type + 23 + 3 + read-write + + + GPIO_PIN5_WAKEUP_ENABLE + enable wakeup from rtc gpio5 + 26 + 1 + read-write + + + GPIO_PIN4_WAKEUP_ENABLE + enable wakeup from rtc gpio4 + 27 + 1 + read-write + + + GPIO_PIN3_WAKEUP_ENABLE + enable wakeup from rtc gpio3 + 28 + 1 + read-write + + + GPIO_PIN2_WAKEUP_ENABLE + enable wakeup from rtc gpio2 + 29 + 1 + read-write + + + GPIO_PIN1_WAKEUP_ENABLE + enable wakeup from rtc gpio1 + 30 + 1 + read-write + + + GPIO_PIN0_WAKEUP_ENABLE + enable wakeup from rtc gpio0 + 31 + 1 + read-write + + + + + DBG_SEL + rtc configure register + 0x114 + 0x20 + + + DEBUG_12M_NO_GATING + use for debug + 1 + 1 + read-write + + + DEBUG_BIT_SEL + use for debug + 2 + 5 + read-write + + + DEBUG_SEL0 + use for debug + 7 + 5 + read-write + + + DEBUG_SEL1 + use for debug + 12 + 5 + read-write + + + DEBUG_SEL2 + use for debug + 17 + 5 + read-write + + + DEBUG_SEL3 + use for debug + 22 + 5 + read-write + + + DEBUG_SEL4 + use for debug + 27 + 5 + read-write + + + + + DBG_MAP + rtc configure register + 0x118 + 0x20 + + + GPIO_PIN5_MUX_SEL + use for debug + 2 + 1 + read-write + + + GPIO_PIN4_MUX_SEL + use for debug + 3 + 1 + read-write + + + GPIO_PIN3_MUX_SEL + use for debug + 4 + 1 + read-write + + + GPIO_PIN2_MUX_SEL + use for debug + 5 + 1 + read-write + + + GPIO_PIN1_MUX_SEL + use for debug + 6 + 1 + read-write + + + GPIO_PIN0_MUX_SEL + use for debug + 7 + 1 + read-write + + + GPIO_PIN5_FUN_SEL + use for debug + 8 + 4 + read-write + + + GPIO_PIN4_FUN_SEL + use for debug + 12 + 4 + read-write + + + GPIO_PIN3_FUN_SEL + use for debug + 16 + 4 + read-write + + + GPIO_PIN2_FUN_SEL + use for debug + 20 + 4 + read-write + + + GPIO_PIN1_FUN_SEL + use for debug + 24 + 4 + read-write + + + GPIO_PIN0_FUN_SEL + use for debug + 28 + 4 + read-write + + + + + SENSOR_CTRL + rtc configure register + 0x11C + 0x20 + + + SAR2_PWDET_CCT + reg_sar2_pwdet_cct + 27 + 3 + read-write + + + FORCE_XPD_SAR + force power up SAR + 30 + 2 + read-write + + + + + DBG_SAR_SEL + rtc configure register + 0x120 + 0x20 + + + SAR_DEBUG_SEL + use for debug + 27 + 5 + read-write + + + + + PG_CTRL + rtc configure register + 0x124 + 0x20 + + + POWER_GLITCH_DSENSE + power glitch desense + 26 + 2 + read-write + + + POWER_GLITCH_FORCE_PD + force disable power glitch + 28 + 1 + read-write + + + POWER_GLITCH_FORCE_PU + force enable power glitch + 29 + 1 + read-write + + + POWER_GLITCH_EFUSE_SEL + use efuse value control power glitch enable + 30 + 1 + read-write + + + POWER_GLITCH_EN + enable power glitch + 31 + 1 + read-write + + + + + DATE + rtc configure register + 0x1FC + 0x20 + 0x02007270 + + + DATE + verision + 0 + 28 + read-write + + + + + + + SENSITIVE + Sensitive + SENSITIVE + 0x600C1000 + + 0x0 + 0x178 + registers + + + + ROM_TABLE_LOCK + SENSITIVE_ROM_TABLE_LOCK_REG + 0x0 + 0x20 + + + ROM_TABLE_LOCK + rom_table_lock + 0 + 1 + read-write + + + + + ROM_TABLE + SENSITIVE_ROM_TABLE_REG + 0x4 + 0x20 + + + ROM_TABLE + rom_table + 0 + 32 + read-write + + + + + PRIVILEGE_MODE_SEL_LOCK + SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG + 0x8 + 0x20 + + + PRIVILEGE_MODE_SEL_LOCK + privilege_mode_sel_lock + 0 + 1 + read-write + + + + + PRIVILEGE_MODE_SEL + SENSITIVE_PRIVILEGE_MODE_SEL_REG + 0xC + 0x20 + + + PRIVILEGE_MODE_SEL + privilege_mode_sel + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_0 + SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG + 0x10 + 0x20 + + + APB_PERIPHERAL_ACCESS_LOCK + apb_peripheral_access_lock + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_1 + SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG + 0x14 + 0x20 + 0x00000001 + + + APB_PERIPHERAL_ACCESS_SPLIT_BURST + apb_peripheral_access_split_burst + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_0 + SENSITIVE_INTERNAL_SRAM_USAGE_0_REG + 0x18 + 0x20 + + + INTERNAL_SRAM_USAGE_LOCK + internal_sram_usage_lock + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_1 + SENSITIVE_INTERNAL_SRAM_USAGE_1_REG + 0x1C + 0x20 + 0x0000000F + + + INTERNAL_SRAM_USAGE_CPU_CACHE + internal_sram_usage_cpu_cache + 0 + 1 + read-write + + + INTERNAL_SRAM_USAGE_CPU_SRAM + internal_sram_usage_cpu_sram + 1 + 3 + read-write + + + + + INTERNAL_SRAM_USAGE_3 + SENSITIVE_INTERNAL_SRAM_USAGE_3_REG + 0x20 + 0x20 + + + INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM + internal_sram_usage_mac_dump_sram + 0 + 3 + read-write + + + INTERNAL_SRAM_ALLOC_MAC_DUMP + internal_sram_alloc_mac_dump + 3 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_4 + SENSITIVE_INTERNAL_SRAM_USAGE_4_REG + 0x24 + 0x20 + + + INTERNAL_SRAM_USAGE_LOG_SRAM + internal_sram_usage_log_sram + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_0 + SENSITIVE_CACHE_TAG_ACCESS_0_REG + 0x28 + 0x20 + + + CACHE_TAG_ACCESS_LOCK + cache_tag_access_lock + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + SENSITIVE_CACHE_TAG_ACCESS_1_REG + 0x2C + 0x20 + 0x0000000F + + + PRO_I_TAG_RD_ACS + pro_i_tag_rd_acs + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + pro_i_tag_wr_acs + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + pro_d_tag_rd_acs + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + pro_d_tag_wr_acs + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + SENSITIVE_CACHE_MMU_ACCESS_0_REG + 0x30 + 0x20 + + + CACHE_MMU_ACCESS_LOCK + cache_mmu_access_lock + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + SENSITIVE_CACHE_MMU_ACCESS_1_REG + 0x34 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + pro_mmu_rd_acs + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + pro_mmu_wr_acs + 1 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG + 0x38 + 0x20 + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + dma_apbperi_spi2_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG + 0x3C + 0x20 + 0x000FF0FF + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG + 0x40 + 0x20 + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK + dma_apbperi_uchi0_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG + 0x44 + 0x20 + 0x000FF0FF + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG + 0x48 + 0x20 + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + dma_apbperi_i2s0_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG + 0x4C + 0x20 + 0x000FF0FF + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG + 0x50 + 0x20 + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + dma_apbperi_mac_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG + 0x54 + 0x20 + 0x000FF0FF + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_mac_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_mac_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_mac_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_mac_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_mac_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_mac_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_mac_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_mac_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG + 0x58 + 0x20 + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + dma_apbperi_backup_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG + 0x5C + 0x20 + 0x000FF0FF + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_backup_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_backup_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_backup_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_backup_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_backup_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_backup_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_backup_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_backup_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG + 0x60 + 0x20 + + + DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + dma_apbperi_lc_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG + 0x64 + 0x20 + 0x000FF0FF + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_lc_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_lc_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_lc_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_lc_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_lc_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_lc_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_lc_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_lc_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG + 0x68 + 0x20 + + + DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + dma_apbperi_aes_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG + 0x6C + 0x20 + 0x000FF0FF + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_aes_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_aes_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_aes_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_aes_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_aes_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_aes_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_aes_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_aes_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG + 0x70 + 0x20 + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + dma_apbperi_sha_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG + 0x74 + 0x20 + 0x000FF0FF + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_sha_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_sha_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_sha_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_sha_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_sha_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_sha_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_sha_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_sha_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG + 0x78 + 0x20 + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + dma_apbperi_adc_dac_pms_constrain_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG + 0x7C + 0x20 + 0x000FF0FF + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_0 + SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG + 0x80 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_LOCK + dma_apbperi_pms_monitor_lock + 0 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_1 + SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG + 0x84 + 0x20 + 0x00000003 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + dma_apbperi_pms_monitor_violate_clr + 0 + 1 + read-write + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + dma_apbperi_pms_monitor_violate_en + 1 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_2 + SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG + 0x88 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + dma_apbperi_pms_monitor_violate_intr + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + dma_apbperi_pms_monitor_violate_status_world + 1 + 2 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + dma_apbperi_pms_monitor_violate_status_addr + 3 + 24 + read-only + + + + + DMA_APBPERI_PMS_MONITOR_3 + SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG + 0x8C + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + dma_apbperi_pms_monitor_violate_status_wr + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + dma_apbperi_pms_monitor_violate_status_byteen + 1 + 4 + read-only + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG + 0x90 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + core_x_iram0_dram0_dma_split_line_constrain_lock + 0 + 1 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG + 0x94 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + core_x_iram0_dram0_dma_sram_category_0 + 0 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + core_x_iram0_dram0_dma_sram_category_1 + 2 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + core_x_iram0_dram0_dma_sram_category_2 + 4 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + core_x_iram0_dram0_dma_sram_splitaddr + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG + 0x98 + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + core_x_iram0_sram_line_0_category_0 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + core_x_iram0_sram_line_0_category_1 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + core_x_iram0_sram_line_0_category_2 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + core_x_iram0_sram_line_0_splitaddr + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG + 0x9C + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + core_x_iram0_sram_line_1_category_0 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + core_x_iram0_sram_line_1_category_1 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + core_x_iram0_sram_line_1_category_2 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + core_x_iram0_sram_line_1_splitaddr + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG + 0xA0 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + core_x_dram0_dma_sram_line_0_category_0 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + core_x_dram0_dma_sram_line_0_category_1 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + core_x_dram0_dma_sram_line_0_category_2 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + core_x_dram0_dma_sram_line_0_splitaddr + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG + 0xA4 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + core_x_dram0_dma_sram_line_1_category_0 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + core_x_dram0_dma_sram_line_1_category_1 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + core_x_dram0_dma_sram_line_1_category_2 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + core_x_dram0_dma_sram_line_1_splitaddr + 14 + 8 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_0 + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + 0xA8 + 0x20 + + + CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + core_x_iram0_pms_constrain_lock + 0 + 1 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_1 + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG + 0xAC + 0x20 + 0x001C7FFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core_x_iram0_pms_constrain_sram_world_1_pms_0 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core_x_iram0_pms_constrain_sram_world_1_pms_1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core_x_iram0_pms_constrain_sram_world_1_pms_2 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core_x_iram0_pms_constrain_sram_world_1_pms_3 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core_x_iram0_pms_constrain_rom_world_1_pms + 18 + 3 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_2 + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG + 0xB0 + 0x20 + 0x001C7FFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core_x_iram0_pms_constrain_sram_world_0_pms_0 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core_x_iram0_pms_constrain_sram_world_0_pms_1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core_x_iram0_pms_constrain_sram_world_0_pms_2 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core_x_iram0_pms_constrain_sram_world_0_pms_3 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core_x_iram0_pms_constrain_rom_world_0_pms + 18 + 3 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_0 + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG + 0xB4 + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_LOCK + core_0_iram0_pms_monitor_lock + 0 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_1 + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG + 0xB8 + 0x20 + 0x00000003 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + core_0_iram0_pms_monitor_violate_clr + 0 + 1 + read-write + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + core_0_iram0_pms_monitor_violate_en + 1 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_2 + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG + 0xBC + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + core_0_iram0_pms_monitor_violate_intr + 0 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + core_0_iram0_pms_monitor_violate_status_wr + 1 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + core_0_iram0_pms_monitor_violate_status_loadstore + 2 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + core_0_iram0_pms_monitor_violate_status_world + 3 + 2 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + core_0_iram0_pms_monitor_violate_status_addr + 5 + 24 + read-only + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_0 + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + 0xC0 + 0x20 + + + CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + core_x_dram0_pms_constrain_lock + 0 + 1 + read-write + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_1 + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG + 0xC4 + 0x20 + 0x0F0FF0FF + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core_x_dram0_pms_constrain_sram_world_0_pms_0 + 0 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core_x_dram0_pms_constrain_sram_world_0_pms_1 + 2 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core_x_dram0_pms_constrain_sram_world_0_pms_2 + 4 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core_x_dram0_pms_constrain_sram_world_0_pms_3 + 6 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core_x_dram0_pms_constrain_sram_world_1_pms_0 + 12 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core_x_dram0_pms_constrain_sram_world_1_pms_1 + 14 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core_x_dram0_pms_constrain_sram_world_1_pms_2 + 16 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core_x_dram0_pms_constrain_sram_world_1_pms_3 + 18 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core_x_dram0_pms_constrain_rom_world_0_pms + 24 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core_x_dram0_pms_constrain_rom_world_1_pms + 26 + 2 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_0 + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG + 0xC8 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_LOCK + core_0_dram0_pms_monitor_lock + 0 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_1 + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG + 0xCC + 0x20 + 0x00000003 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + core_0_dram0_pms_monitor_violate_clr + 0 + 1 + read-write + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + core_0_dram0_pms_monitor_violate_en + 1 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_2 + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG + 0xD0 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + core_0_dram0_pms_monitor_violate_intr + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + core_0_dram0_pms_monitor_violate_status_lock + 1 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + core_0_dram0_pms_monitor_violate_status_world + 2 + 2 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + core_0_dram0_pms_monitor_violate_status_addr + 4 + 24 + read-only + + + + + CORE_0_DRAM0_PMS_MONITOR_3 + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG + 0xD4 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + core_0_dram0_pms_monitor_violate_status_wr + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + core_0_dram0_pms_monitor_violate_status_byteen + 1 + 4 + read-only + + + + + CORE_0_PIF_PMS_CONSTRAIN_0 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG + 0xD8 + 0x20 + + + CORE_0_PIF_PMS_CONSTRAIN_LOCK + core_0_pif_pms_constrain_lock + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_1 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG + 0xDC + 0x20 + 0xCF0FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + core_0_pif_pms_constrain_world_0_uart + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + core_0_pif_pms_constrain_world_0_g0spi_1 + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + core_0_pif_pms_constrain_world_0_g0spi_0 + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + core_0_pif_pms_constrain_world_0_gpio + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + core_0_pif_pms_constrain_world_0_fe2 + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + core_0_pif_pms_constrain_world_0_fe + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER + core_0_pif_pms_constrain_world_0_timer + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + core_0_pif_pms_constrain_world_0_rtc + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + core_0_pif_pms_constrain_world_0_io_mux + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG + core_0_pif_pms_constrain_world_0_wdg + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + core_0_pif_pms_constrain_world_0_misc + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + core_0_pif_pms_constrain_world_0_i2c + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + core_0_pif_pms_constrain_world_0_uart1 + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_2 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG + 0xE0 + 0x20 + 0xFCC30CF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + core_0_pif_pms_constrain_world_0_bt + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + core_0_pif_pms_constrain_world_0_i2c_ext0 + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + core_0_pif_pms_constrain_world_0_uhci0 + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + core_0_pif_pms_constrain_world_0_rmt + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + core_0_pif_pms_constrain_world_0_ledc + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + core_0_pif_pms_constrain_world_0_bb + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + core_0_pif_pms_constrain_world_0_timergroup + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + core_0_pif_pms_constrain_world_0_timergroup1 + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + core_0_pif_pms_constrain_world_0_systimer + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_3 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG + 0xE4 + 0x20 + 0x3CC0CC33 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + core_0_pif_pms_constrain_world_0_spi_2 + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + core_0_pif_pms_constrain_world_0_apb_ctrl + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + core_0_pif_pms_constrain_world_0_can + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + core_0_pif_pms_constrain_world_0_i2s1 + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + core_0_pif_pms_constrain_world_0_rwbt + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + core_0_pif_pms_constrain_world_0_wifimac + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + core_0_pif_pms_constrain_world_0_pwr + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_4 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG + 0xE8 + 0x20 + 0xFFFFF3FC + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + core_0_pif_pms_constrain_world_0_usb_wrap + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + core_0_pif_pms_constrain_world_0_crypto_peri + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + core_0_pif_pms_constrain_world_0_crypto_dma + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + core_0_pif_pms_constrain_world_0_apb_adc + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + core_0_pif_pms_constrain_world_0_bt_pwr + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + core_0_pif_pms_constrain_world_0_usb_device + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + core_0_pif_pms_constrain_world_0_system + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + core_0_pif_pms_constrain_world_0_sensitive + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + core_0_pif_pms_constrain_world_0_interrupt + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + core_0_pif_pms_constrain_world_0_dma_copy + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + core_0_pif_pms_constrain_world_0_cache_config + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + core_0_pif_pms_constrain_world_0_ad + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + core_0_pif_pms_constrain_world_0_dio + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + core_0_pif_pms_constrain_world_0_world_controller + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_5 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG + 0xEC + 0x20 + 0xCF0FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + core_0_pif_pms_constrain_world_1_uart + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + core_0_pif_pms_constrain_world_1_g0spi_1 + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + core_0_pif_pms_constrain_world_1_g0spi_0 + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + core_0_pif_pms_constrain_world_1_gpio + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + core_0_pif_pms_constrain_world_1_fe2 + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + core_0_pif_pms_constrain_world_1_fe + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER + core_0_pif_pms_constrain_world_1_timer + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + core_0_pif_pms_constrain_world_1_rtc + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + core_0_pif_pms_constrain_world_1_io_mux + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG + core_0_pif_pms_constrain_world_1_wdg + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + core_0_pif_pms_constrain_world_1_misc + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + core_0_pif_pms_constrain_world_1_i2c + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + core_0_pif_pms_constrain_world_1_uart1 + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_6 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG + 0xF0 + 0x20 + 0xFCC30CF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + core_0_pif_pms_constrain_world_1_bt + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + core_0_pif_pms_constrain_world_1_i2c_ext0 + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + core_0_pif_pms_constrain_world_1_uhci0 + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + core_0_pif_pms_constrain_world_1_rmt + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + core_0_pif_pms_constrain_world_1_ledc + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + core_0_pif_pms_constrain_world_1_bb + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + core_0_pif_pms_constrain_world_1_timergroup + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + core_0_pif_pms_constrain_world_1_timergroup1 + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + core_0_pif_pms_constrain_world_1_systimer + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_7 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG + 0xF4 + 0x20 + 0x3CC0CC33 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + core_0_pif_pms_constrain_world_1_spi_2 + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + core_0_pif_pms_constrain_world_1_apb_ctrl + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + core_0_pif_pms_constrain_world_1_can + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + core_0_pif_pms_constrain_world_1_i2s1 + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + core_0_pif_pms_constrain_world_1_rwbt + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + core_0_pif_pms_constrain_world_1_wifimac + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + core_0_pif_pms_constrain_world_1_pwr + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_8 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG + 0xF8 + 0x20 + 0xFFFFF3FC + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + core_0_pif_pms_constrain_world_1_usb_wrap + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + core_0_pif_pms_constrain_world_1_crypto_peri + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + core_0_pif_pms_constrain_world_1_crypto_dma + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + core_0_pif_pms_constrain_world_1_apb_adc + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + core_0_pif_pms_constrain_world_1_bt_pwr + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + core_0_pif_pms_constrain_world_1_usb_device + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + core_0_pif_pms_constrain_world_1_system + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + core_0_pif_pms_constrain_world_1_sensitive + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + core_0_pif_pms_constrain_world_1_interrupt + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + core_0_pif_pms_constrain_world_1_dma_copy + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + core_0_pif_pms_constrain_world_1_cache_config + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + core_0_pif_pms_constrain_world_1_ad + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + core_0_pif_pms_constrain_world_1_dio + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + core_0_pif_pms_constrain_world_1_world_controller + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_9 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG + 0xFC + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + core_0_pif_pms_constrain_rtcfast_spltaddr_world_0 + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + core_0_pif_pms_constrain_rtcfast_spltaddr_world_1 + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_10 + SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG + 0x100 + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + core_0_pif_pms_constrain_rtcfast_world_0_l + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + core_0_pif_pms_constrain_rtcfast_world_0_h + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + core_0_pif_pms_constrain_rtcfast_world_1_l + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + core_0_pif_pms_constrain_rtcfast_world_1_h + 9 + 3 + read-write + + + + + REGION_PMS_CONSTRAIN_0 + SENSITIVE_REGION_PMS_CONSTRAIN_0_REG + 0x104 + 0x20 + + + REGION_PMS_CONSTRAIN_LOCK + region_pms_constrain_lock + 0 + 1 + read-write + + + + + REGION_PMS_CONSTRAIN_1 + SENSITIVE_REGION_PMS_CONSTRAIN_1_REG + 0x108 + 0x20 + 0x00003FFF + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + region_pms_constrain_world_0_area_0 + 0 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + region_pms_constrain_world_0_area_1 + 2 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + region_pms_constrain_world_0_area_2 + 4 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + region_pms_constrain_world_0_area_3 + 6 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + region_pms_constrain_world_0_area_4 + 8 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + region_pms_constrain_world_0_area_5 + 10 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + region_pms_constrain_world_0_area_6 + 12 + 2 + read-write + + + + + REGION_PMS_CONSTRAIN_2 + SENSITIVE_REGION_PMS_CONSTRAIN_2_REG + 0x10C + 0x20 + 0x00003FFF + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + region_pms_constrain_world_1_area_0 + 0 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + region_pms_constrain_world_1_area_1 + 2 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + region_pms_constrain_world_1_area_2 + 4 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + region_pms_constrain_world_1_area_3 + 6 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + region_pms_constrain_world_1_area_4 + 8 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + region_pms_constrain_world_1_area_5 + 10 + 2 + read-write + + + REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + region_pms_constrain_world_1_area_6 + 12 + 2 + read-write + + + + + REGION_PMS_CONSTRAIN_3 + SENSITIVE_REGION_PMS_CONSTRAIN_3_REG + 0x110 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_0 + region_pms_constrain_addr_0 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_4 + SENSITIVE_REGION_PMS_CONSTRAIN_4_REG + 0x114 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_1 + region_pms_constrain_addr_1 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_5 + SENSITIVE_REGION_PMS_CONSTRAIN_5_REG + 0x118 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_2 + region_pms_constrain_addr_2 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_6 + SENSITIVE_REGION_PMS_CONSTRAIN_6_REG + 0x11C + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_3 + region_pms_constrain_addr_3 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_7 + SENSITIVE_REGION_PMS_CONSTRAIN_7_REG + 0x120 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_4 + region_pms_constrain_addr_4 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_8 + SENSITIVE_REGION_PMS_CONSTRAIN_8_REG + 0x124 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_5 + region_pms_constrain_addr_5 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_9 + SENSITIVE_REGION_PMS_CONSTRAIN_9_REG + 0x128 + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_6 + region_pms_constrain_addr_6 + 0 + 30 + read-write + + + + + REGION_PMS_CONSTRAIN_10 + SENSITIVE_REGION_PMS_CONSTRAIN_10_REG + 0x12C + 0x20 + + + REGION_PMS_CONSTRAIN_ADDR_7 + region_pms_constrain_addr_7 + 0 + 30 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_0 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG + 0x130 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_LOCK + core_0_pif_pms_monitor_lock + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_1 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG + 0x134 + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + core_0_pif_pms_monitor_violate_clr + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + core_0_pif_pms_monitor_violate_en + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_2 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG + 0x138 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + core_0_pif_pms_monitor_violate_intr + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + core_0_pif_pms_monitor_violate_status_hport_0 + 1 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + core_0_pif_pms_monitor_violate_status_hsize + 2 + 3 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + core_0_pif_pms_monitor_violate_status_hwrite + 5 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + core_0_pif_pms_monitor_violate_status_hworld + 6 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_3 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG + 0x13C + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + core_0_pif_pms_monitor_violate_status_haddr + 0 + 32 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_4 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG + 0x140 + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + core_0_pif_pms_monitor_nonword_violate_clr + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + core_0_pif_pms_monitor_nonword_violate_en + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_5 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG + 0x144 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + core_0_pif_pms_monitor_nonword_violate_intr + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + core_0_pif_pms_monitor_nonword_violate_status_hsize + 1 + 2 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + core_0_pif_pms_monitor_nonword_violate_status_hworld + 3 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_6 + SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG + 0x148 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + core_0_pif_pms_monitor_nonword_violate_status_haddr + 0 + 32 + read-only + + + + + BACKUP_BUS_PMS_CONSTRAIN_0 + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG + 0x14C + 0x20 + + + BACKUP_BUS_PMS_CONSTRAIN_LOCK + backup_bus_pms_constrain_lock + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_1 + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG + 0x150 + 0x20 + 0xCF0FFFFF + + + BACKUP_BUS_PMS_CONSTRAIN_UART + backup_bus_pms_constrain_uart + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + backup_bus_pms_constrain_g0spi_1 + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + backup_bus_pms_constrain_g0spi_0 + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_GPIO + backup_bus_pms_constrain_gpio + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE2 + backup_bus_pms_constrain_fe2 + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE + backup_bus_pms_constrain_fe + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMER + backup_bus_pms_constrain_timer + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTC + backup_bus_pms_constrain_rtc + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + backup_bus_pms_constrain_io_mux + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WDG + backup_bus_pms_constrain_wdg + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_MISC + backup_bus_pms_constrain_misc + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C + backup_bus_pms_constrain_i2c + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART1 + backup_bus_pms_constrain_uart1 + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_2 + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG + 0x154 + 0x20 + 0xFCC30CF3 + + + BACKUP_BUS_PMS_CONSTRAIN_BT + backup_bus_pms_constrain_bt + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + backup_bus_pms_constrain_i2c_ext0 + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + backup_bus_pms_constrain_uhci0 + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RMT + backup_bus_pms_constrain_rmt + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LEDC + backup_bus_pms_constrain_ledc + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BB + backup_bus_pms_constrain_bb + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + backup_bus_pms_constrain_timergroup + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + backup_bus_pms_constrain_timergroup1 + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + backup_bus_pms_constrain_systimer + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_3 + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG + 0x158 + 0x20 + 0x3CC0CC33 + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + backup_bus_pms_constrain_spi_2 + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + backup_bus_pms_constrain_apb_ctrl + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CAN + backup_bus_pms_constrain_can + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S1 + backup_bus_pms_constrain_i2s1 + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RWBT + backup_bus_pms_constrain_rwbt + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + backup_bus_pms_constrain_wifimac + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWR + backup_bus_pms_constrain_pwr + 28 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_4 + SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG + 0x15C + 0x20 + 0x0000F3FC + + + BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + backup_bus_pms_constrain_usb_wrap + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + backup_bus_pms_constrain_crypto_peri + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + backup_bus_pms_constrain_crypto_dma + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + backup_bus_pms_constrain_apb_adc + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + backup_bus_pms_constrain_bt_pwr + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + backup_bus_pms_constrain_usb_device + 14 + 2 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_0 + SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG + 0x160 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_LOCK + backup_bus_pms_monitor_lock + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_1 + SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG + 0x164 + 0x20 + 0x00000003 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + backup_bus_pms_monitor_violate_clr + 0 + 1 + read-write + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + backup_bus_pms_monitor_violate_en + 1 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_2 + SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG + 0x168 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + backup_bus_pms_monitor_violate_intr + 0 + 1 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + backup_bus_pms_monitor_violate_status_htrans + 1 + 2 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + backup_bus_pms_monitor_violate_status_hsize + 3 + 3 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + backup_bus_pms_monitor_violate_status_hwrite + 6 + 1 + read-only + + + + + BACKUP_BUS_PMS_MONITOR_3 + SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG + 0x16C + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + backup_bus_pms_monitor_violate_haddr + 0 + 32 + read-only + + + + + CLOCK_GATE + SENSITIVE_CLOCK_GATE_REG_REG + 0x170 + 0x20 + 0x00000001 + + + CLK_EN + clk_en + 0 + 1 + read-write + + + + + DATE + SENSITIVE_DATE_REG + 0xFFC + 0x20 + 0x02010200 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 49 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20200616 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60003000 + + 0x0 + 0x48 + registers + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. + 3 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable + 7 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control1 register. + 0xC + 0x20 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. + 30 + 1 + write-only + + + + + CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x00000021 + + + CS_SETUP_TIME + (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 5 + 5 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + Set this bit in 1-division mode. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + TRANS_END + The bit is used to indicate the spi0_mst_st controlled transmitting is done. + 3 + 1 + read-write + + + TRANS_END_INT_ENA + The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. + 4 + 1 + read-write + + + CSPI_ST_TRANS_END + The bit is used to indicate the spi0_slv_st controlled transmitting is done. + 5 + 1 + read-write + + + CSPI_ST_TRANS_END_INT_ENA + The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. + 6 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + For SPI0, Cache access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + CSPI_ST + The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 0 + 4 + read-only + + + EM_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 4 + 3 + read-only + + + CSPI_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + TIMING_CALI + SPI0 timing calibration register + 0xA8 + 0x20 + 0x00000001 + + + TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + DIN_MODE + SPI0 input delay mode control register + 0xAC + 0x20 + + + DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 2 + read-write + + + + + DIN_NUM + SPI0 input delay number control register + 0xB0 + 0x20 + + + DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + + + DOUT_MODE + SPI0 output delay mode control register + 0xB4 + 0x20 + + + DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xE0 + 0x20 + + + SPI01_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02007130 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60002000 + + 0x0 + 0xA8 + registers + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI1_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + MSPI_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. + 3 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable + 7 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + WAITI_CMD + The command to wait flash idle(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0005757A + + + FLASH_PER_COMMAND + Program/Erase resume command. + 0 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command. + 8 + 8 + read-write + + + WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing control register + 0xA8 + 0x20 + + + TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. + 0 + 1 + read-only + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. + 1 + 1 + read-only + + + WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-only + + + SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02007170 + + + DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60024000 + + 0x0 + 0x94 + registers + + + SPI2 + 19 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 25 + 1 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 26 + 1 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI DMA interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI DMA interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI DMA interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application. + 19 + 1 + read-write + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application. + 20 + 1 + read-write + + + + + DMA_INT_ST + SPI DMA interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02007220 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTEM + System + SYSTEM + 0x600C0000 + + 0x0 + 0xA0 + registers + + + + CPU_PERI_CLK_EN + cpu_peripheral clock gating register + 0x0 + 0x20 + + + CLK_EN_ASSIST_DEBUG + reg_clk_en_assist_debug + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + reg_clk_en_dedicated_gpio + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset register + 0x4 + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + reg_rst_en_assist_debug + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + reg_rst_en_dedicated_gpio + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu clock config register + 0x8 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + reg_cpuperiod_sel + 0 + 2 + read-write + + + PLL_FREQ_SEL + reg_pll_freq_sel + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + reg_cpu_wait_mode_force_on + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + reg_cpu_waiti_delay_num + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask register + 0xC + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + reg_lslp_mem_pd_mask + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock gating register + 0x10 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + reg_timers_clk_en + 0 + 1 + read-write + + + SPI01_CLK_EN + reg_spi01_clk_en + 1 + 1 + read-write + + + UART_CLK_EN + reg_uart_clk_en + 2 + 1 + read-write + + + WDG_CLK_EN + reg_wdg_clk_en + 3 + 1 + read-write + + + I2S0_CLK_EN + reg_i2s0_clk_en + 4 + 1 + read-write + + + UART1_CLK_EN + reg_uart1_clk_en + 5 + 1 + read-write + + + SPI2_CLK_EN + reg_spi2_clk_en + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + reg_ext0_clk_en + 7 + 1 + read-write + + + UHCI0_CLK_EN + reg_uhci0_clk_en + 8 + 1 + read-write + + + RMT_CLK_EN + reg_rmt_clk_en + 9 + 1 + read-write + + + PCNT_CLK_EN + reg_pcnt_clk_en + 10 + 1 + read-write + + + LEDC_CLK_EN + reg_ledc_clk_en + 11 + 1 + read-write + + + UHCI1_CLK_EN + reg_uhci1_clk_en + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + reg_timergroup_clk_en + 13 + 1 + read-write + + + EFUSE_CLK_EN + reg_efuse_clk_en + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + reg_timergroup1_clk_en + 15 + 1 + read-write + + + SPI3_CLK_EN + reg_spi3_clk_en + 16 + 1 + read-write + + + PWM0_CLK_EN + reg_pwm0_clk_en + 17 + 1 + read-write + + + EXT1_CLK_EN + reg_ext1_clk_en + 18 + 1 + read-write + + + CAN_CLK_EN + reg_can_clk_en + 19 + 1 + read-write + + + PWM1_CLK_EN + reg_pwm1_clk_en + 20 + 1 + read-write + + + I2S1_CLK_EN + reg_i2s1_clk_en + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + reg_spi2_dma_clk_en + 22 + 1 + read-write + + + USB_DEVICE_CLK_EN + reg_usb_device_clk_en + 23 + 1 + read-write + + + UART_MEM_CLK_EN + reg_uart_mem_clk_en + 24 + 1 + read-write + + + PWM2_CLK_EN + reg_pwm2_clk_en + 25 + 1 + read-write + + + PWM3_CLK_EN + reg_pwm3_clk_en + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + reg_spi3_dma_clk_en + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + reg_apb_saradc_clk_en + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + reg_systimer_clk_en + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + reg_adc2_arb_clk_en + 30 + 1 + read-write + + + SPI4_CLK_EN + reg_spi4_clk_en + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock gating register + 0x14 + 0x20 + 0x00000200 + + + CRYPTO_AES_CLK_EN + reg_crypto_aes_clk_en + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + reg_crypto_sha_clk_en + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + reg_crypto_rsa_clk_en + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + reg_crypto_ds_clk_en + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + reg_crypto_hmac_clk_en + 5 + 1 + read-write + + + DMA_CLK_EN + reg_dma_clk_en + 6 + 1 + read-write + + + SDIO_HOST_CLK_EN + reg_sdio_host_clk_en + 7 + 1 + read-write + + + LCD_CAM_CLK_EN + reg_lcd_cam_clk_en + 8 + 1 + read-write + + + UART2_CLK_EN + reg_uart2_clk_en + 9 + 1 + read-write + + + TSENS_CLK_EN + reg_tsens_clk_en + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + reserved + 0x18 + 0x20 + + + TIMERS_RST + reg_timers_rst + 0 + 1 + read-write + + + SPI01_RST + reg_spi01_rst + 1 + 1 + read-write + + + UART_RST + reg_uart_rst + 2 + 1 + read-write + + + WDG_RST + reg_wdg_rst + 3 + 1 + read-write + + + I2S0_RST + reg_i2s0_rst + 4 + 1 + read-write + + + UART1_RST + reg_uart1_rst + 5 + 1 + read-write + + + SPI2_RST + reg_spi2_rst + 6 + 1 + read-write + + + I2C_EXT0_RST + reg_ext0_rst + 7 + 1 + read-write + + + UHCI0_RST + reg_uhci0_rst + 8 + 1 + read-write + + + RMT_RST + reg_rmt_rst + 9 + 1 + read-write + + + PCNT_RST + reg_pcnt_rst + 10 + 1 + read-write + + + LEDC_RST + reg_ledc_rst + 11 + 1 + read-write + + + UHCI1_RST + reg_uhci1_rst + 12 + 1 + read-write + + + TIMERGROUP_RST + reg_timergroup_rst + 13 + 1 + read-write + + + EFUSE_RST + reg_efuse_rst + 14 + 1 + read-write + + + TIMERGROUP1_RST + reg_timergroup1_rst + 15 + 1 + read-write + + + SPI3_RST + reg_spi3_rst + 16 + 1 + read-write + + + PWM0_RST + reg_pwm0_rst + 17 + 1 + read-write + + + EXT1_RST + reg_ext1_rst + 18 + 1 + read-write + + + CAN_RST + reg_can_rst + 19 + 1 + read-write + + + PWM1_RST + reg_pwm1_rst + 20 + 1 + read-write + + + I2S1_RST + reg_i2s1_rst + 21 + 1 + read-write + + + SPI2_DMA_RST + reg_spi2_dma_rst + 22 + 1 + read-write + + + USB_DEVICE_RST + reg_usb_device_rst + 23 + 1 + read-write + + + UART_MEM_RST + reg_uart_mem_rst + 24 + 1 + read-write + + + PWM2_RST + reg_pwm2_rst + 25 + 1 + read-write + + + PWM3_RST + reg_pwm3_rst + 26 + 1 + read-write + + + SPI3_DMA_RST + reg_spi3_dma_rst + 27 + 1 + read-write + + + APB_SARADC_RST + reg_apb_saradc_rst + 28 + 1 + read-write + + + SYSTIMER_RST + reg_systimer_rst + 29 + 1 + read-write + + + ADC2_ARB_RST + reg_adc2_arb_rst + 30 + 1 + read-write + + + SPI4_RST + reg_spi4_rst + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset register + 0x1C + 0x20 + 0x000001FE + + + CRYPTO_AES_RST + reg_crypto_aes_rst + 1 + 1 + read-write + + + CRYPTO_SHA_RST + reg_crypto_sha_rst + 2 + 1 + read-write + + + CRYPTO_RSA_RST + reg_crypto_rsa_rst + 3 + 1 + read-write + + + CRYPTO_DS_RST + reg_crypto_ds_rst + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + reg_crypto_hmac_rst + 5 + 1 + read-write + + + DMA_RST + reg_dma_rst + 6 + 1 + read-write + + + SDIO_HOST_RST + reg_sdio_host_rst + 7 + 1 + read-write + + + LCD_CAM_RST + reg_lcd_cam_rst + 8 + 1 + read-write + + + UART2_RST + reg_uart2_rst + 9 + 1 + read-write + + + TSENS_RST + reg_tsens_rst + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + clock config register + 0x20 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + reg_bt_lpck_div_num + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + clock config register + 0x24 + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + reg_bt_lpck_div_b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + reg_bt_lpck_div_a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + reg_lpclk_sel_rtc_slow + 24 + 1 + read-write + + + LPCLK_SEL_8M + reg_lpclk_sel_8m + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + reg_lpclk_sel_xtal + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + reg_lpclk_sel_xtal32k + 27 + 1 + read-write + + + LPCLK_RTC_EN + reg_lpclk_rtc_en + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt generate register + 0x28 + 0x20 + + + CPU_INTR_FROM_CPU_0 + reg_cpu_intr_from_cpu_0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt generate register + 0x2C + 0x20 + + + CPU_INTR_FROM_CPU_1 + reg_cpu_intr_from_cpu_1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt generate register + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_2 + reg_cpu_intr_from_cpu_2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt generate register + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_3 + reg_cpu_intr_from_cpu_3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x38 + 0x20 + 0x00000001 + + + RSA_MEM_PD + reg_rsa_mem_pd + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + reg_rsa_mem_force_pu + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + reg_rsa_mem_force_pd + 2 + 1 + read-write + + + + + EDMA_CTRL + edma clcok and reset register + 0x3C + 0x20 + 0x00000001 + + + EDMA_CLK_ON + reg_edma_clk_on + 0 + 1 + read-write + + + EDMA_RESET + reg_edma_reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + cache control register + 0x40 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + reg_icache_clk_on + 0 + 1 + read-write + + + ICACHE_RESET + reg_icache_reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + reg_dcache_clk_on + 2 + 1 + read-write + + + DCACHE_RESET + reg_dcache_reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + 0x44 + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + reg_enable_spi_manual_encrypt + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + reg_enable_download_db_encrypt + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + reg_enable_download_g0cb_decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + reg_enable_download_manual_encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + fast memory config register + 0x48 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + reg_rtc_mem_crc_start + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + reg_rtc_mem_crc_addr + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + reg_rtc_mem_crc_len + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + reg_rtc_mem_crc_finish + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + reserved + 0x4C + 0x20 + + + RTC_MEM_CRC_RES + reg_rtc_mem_crc_res + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + eco register + 0x50 + 0x20 + + + REDUNDANT_ECO_DRIVE + reg_redundant_eco_drive + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + reg_redundant_eco_result + 1 + 1 + read-only + + + + + CLOCK_GATE + clock gating register + 0x54 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + SYSCLK_CONF + system clock config register + 0x58 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + reg_pre_div_cnt + 0 + 10 + read-write + + + SOC_CLK_SEL + reg_soc_clk_sel + 10 + 2 + read-write + + + CLK_XTAL_FREQ + reg_clk_xtal_freq + 12 + 7 + read-only + + + CLK_DIV_EN + reg_clk_div_en + 19 + 1 + read-only + + + + + MEM_PVT + mem pvt register + 0x5C + 0x20 + 0x00000003 + + + MEM_PATH_LEN + reg_mem_path_len + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + reg_mem_err_cnt_clr + 4 + 1 + write-only + + + MONITOR_EN + reg_mem_pvt_monitor_en + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + reg_mem_timing_err_cnt + 6 + 16 + read-only + + + MEM_VT_SEL + reg_mem_vt_sel + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + mem pvt register + 0x60 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + reg_comb_path_len_lvt + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_LVT + reg_comb_err_cnt_clr_lvt + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + reg_comb_pvt_monitor_en_lvt + 6 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + mem pvt register + 0x64 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + reg_comb_path_len_nvt + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_NVT + reg_comb_err_cnt_clr_nvt + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + reg_comb_pvt_monitor_en_nvt + 6 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + mem pvt register + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + reg_comb_path_len_hvt + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_HVT + reg_comb_err_cnt_clr_hvt + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + reg_comb_pvt_monitor_en_hvt + 6 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + mem pvt register + 0x6C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + reg_comb_timing_err_cnt_lvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + mem pvt register + 0x70 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + reg_comb_timing_err_cnt_nvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + mem pvt register + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + reg_comb_timing_err_cnt_hvt_site0 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + mem pvt register + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + reg_comb_timing_err_cnt_lvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + mem pvt register + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + reg_comb_timing_err_cnt_nvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + mem pvt register + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + reg_comb_timing_err_cnt_hvt_site1 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + mem pvt register + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + reg_comb_timing_err_cnt_lvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + mem pvt register + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + reg_comb_timing_err_cnt_nvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + mem pvt register + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + reg_comb_timing_err_cnt_hvt_site2 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + mem pvt register + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + reg_comb_timing_err_cnt_lvt_site3 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + mem pvt register + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + reg_comb_timing_err_cnt_nvt_site3 + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + mem pvt register + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + reg_comb_timing_err_cnt_hvt_site3 + 0 + 16 + read-only + + + + + SYSTEM_REG_DATE + Version register + 0xFFC + 0x20 + 0x02007150 + + + SYSTEM_REG_DATE + reg_system_reg_date + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x78 + registers + + + SYSTIMER_TARGET0 + 37 + + + SYSTIMER_TARGET1 + 38 + + + SYSTIMER_TARGET2 + 39 + + + + CONF + SYSTIMER_CONF. + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + SYSTIMER_UNIT0_OP. + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + reg_timer_unit0_value_valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + SYSTIMER_UNIT1_OP. + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + SYSTIMER_UNIT0_LOAD_HI. + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 32 bit + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + SYSTIMER_UNIT0_LOAD_LO. + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bit + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + SYSTIMER_UNIT1_LOAD_HI. + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 32 bit + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + SYSTIMER_UNIT1_LOAD_LO. + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bit + 0 + 32 + read-write + + + + + TARGET0_HI + SYSTIMER_TARGET0_HI. + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 32 bit + 0 + 20 + read-write + + + + + TARGET0_LO + SYSTIMER_TARGET0_LO. + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bit + 0 + 32 + read-write + + + + + TARGET1_HI + SYSTIMER_TARGET1_HI. + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 32 bit + 0 + 20 + read-write + + + + + TARGET1_LO + SYSTIMER_TARGET1_LO. + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bit + 0 + 32 + read-write + + + + + TARGET2_HI + SYSTIMER_TARGET2_HI. + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 32 bit + 0 + 20 + read-write + + + + + TARGET2_LO + SYSTIMER_TARGET2_LO. + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bit + 0 + 32 + read-write + + + + + TARGET0_CONF + SYSTIMER_TARGET0_CONF. + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + SYSTIMER_TARGET1_CONF. + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + SYSTIMER_TARGET2_CONF. + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + SYSTIMER_UNIT0_VALUE_HI. + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 32bit + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + SYSTIMER_UNIT0_VALUE_LO. + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bit + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + SYSTIMER_UNIT1_VALUE_HI. + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 32bit + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + SYSTIMER_UNIT1_VALUE_LO. + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bit + 0 + 32 + read-only + + + + + COMP0_LOAD + SYSTIMER_COMP0_LOAD. + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 load value + 0 + 1 + write-only + + + + + COMP1_LOAD + SYSTIMER_COMP1_LOAD. + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 load value + 0 + 1 + write-only + + + + + COMP2_LOAD + SYSTIMER_COMP2_LOAD. + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 load value + 0 + 1 + write-only + + + + + UNIT0_LOAD + SYSTIMER_UNIT0_LOAD. + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 load value + 0 + 1 + write-only + + + + + UNIT1_LOAD + SYSTIMER_UNIT1_LOAD. + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 load value + 0 + 1 + write-only + + + + + INT_ENA + SYSTIMER_INT_ENA. + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + SYSTIMER_INT_RAW. + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + SYSTIMER_INT_CLR. + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + SYSTIMER_INT_ST. + 0x70 + 0x20 + + + TARGET0_INT_ST + reg_target0_int_st + 0 + 1 + read-only + + + TARGET1_INT_ST + reg_target1_int_st + 1 + 1 + read-only + + + TARGET2_INT_ST + reg_target2_int_st + 2 + 1 + read-only + + + + + DATE + SYSTIMER_DATE. + 0xFC + 0x20 + 0x02006171 + + + DATE + reg_date + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x6001F000 + + 0x0 + 0x68 + registers + + + TG0_T0_LEVEL + 32 + + + TG0_WDT_LEVEL + 33 + + + + T0CONFIG + TIMG_T0CONFIG_REG. + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + reg_t0_use_xtal. + 9 + 1 + read-write + + + ALARM_EN + reg_t0_alarm_en. + 10 + 1 + read-write + + + DIVCNT_RST + reg_t0_divcnt_rst. + 12 + 1 + write-only + + + DIVIDER + reg_t0_divider. + 13 + 16 + read-write + + + AUTORELOAD + reg_t0_autoreload. + 29 + 1 + read-write + + + INCREASE + reg_t0_increase. + 30 + 1 + read-write + + + EN + reg_t0_en. + 31 + 1 + read-write + + + + + T0LO + TIMG_T0LO_REG. + 0x4 + 0x20 + + + LO + t0_lo + 0 + 32 + read-only + + + + + T0HI + TIMG_T0HI_REG. + 0x8 + 0x20 + + + HI + t0_hi + 0 + 22 + read-only + + + + + T0UPDATE + TIMG_T0UPDATE_REG. + 0xC + 0x20 + + + UPDATE + t0_update + 31 + 1 + read-write + + + + + T0ALARMLO + TIMG_T0ALARMLO_REG. + 0x10 + 0x20 + + + ALARM_LO + reg_t0_alarm_lo. + 0 + 32 + read-write + + + + + T0ALARMHI + TIMG_T0ALARMHI_REG. + 0x14 + 0x20 + + + ALARM_HI + reg_t0_alarm_hi. + 0 + 22 + read-write + + + + + T0LOADLO + TIMG_T0LOADLO_REG. + 0x18 + 0x20 + + + LOAD_LO + reg_t0_load_lo. + 0 + 32 + read-write + + + + + T0LOADHI + TIMG_T0LOADHI_REG. + 0x1C + 0x20 + + + LOAD_HI + reg_t0_load_hi. + 0 + 22 + read-write + + + + + T0LOAD + TIMG_T0LOAD_REG. + 0x20 + 0x20 + + + LOAD + t0_load + 0 + 32 + write-only + + + + + WDTCONFIG0 + TIMG_WDTCONFIG0_REG. + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + reg_wdt_appcpu_reset_en. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + reg_wdt_procpu_reset_en. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + reg_wdt_flashboot_mod_en. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + reg_wdt_sys_reset_length. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + reg_wdt_cpu_reset_length. + 18 + 3 + read-write + + + WDT_USE_XTAL + reg_wdt_use_xtal. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + reg_wdt_conf_update_en. + 22 + 1 + write-only + + + WDT_STG3 + reg_wdt_stg3. + 23 + 2 + read-write + + + WDT_STG2 + reg_wdt_stg2. + 25 + 2 + read-write + + + WDT_STG1 + reg_wdt_stg1. + 27 + 2 + read-write + + + WDT_STG0 + reg_wdt_stg0. + 29 + 2 + read-write + + + WDT_EN + reg_wdt_en. + 31 + 1 + read-write + + + + + WDTCONFIG1 + TIMG_WDTCONFIG1_REG. + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + reg_wdt_divcnt_rst. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + reg_wdt_clk_prescale. + 16 + 16 + read-write + + + + + WDTCONFIG2 + TIMG_WDTCONFIG2_REG. + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + reg_wdt_stg0_hold. + 0 + 32 + read-write + + + + + WDTCONFIG3 + TIMG_WDTCONFIG3_REG. + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + reg_wdt_stg1_hold. + 0 + 32 + read-write + + + + + WDTCONFIG4 + TIMG_WDTCONFIG4_REG. + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + reg_wdt_stg2_hold. + 0 + 32 + read-write + + + + + WDTCONFIG5 + TIMG_WDTCONFIG5_REG. + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + reg_wdt_stg3_hold. + 0 + 32 + read-write + + + + + WDTFEED + TIMG_WDTFEED_REG. + 0x60 + 0x20 + + + WDT_FEED + wdt_feed + 0 + 32 + write-only + + + + + WDTWPROTECT + TIMG_WDTWPROTECT_REG. + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + reg_wdt_wkey. + 0 + 32 + read-write + + + + + RTCCALICFG + TIMG_RTCCALICFG_REG. + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + reg_rtc_cali_start_cycling. + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k + 13 + 2 + read-write + + + RTC_CALI_RDY + rtc_cali_rdy + 15 + 1 + read-only + + + RTC_CALI_MAX + reg_rtc_cali_max. + 16 + 15 + read-write + + + RTC_CALI_START + reg_rtc_cali_start. + 31 + 1 + read-write + + + + + RTCCALICFG1 + TIMG_RTCCALICFG1_REG. + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + rtc_cali_cycling_data_vld + 0 + 1 + read-only + + + RTC_CALI_VALUE + rtc_cali_value + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + INT_ENA_TIMG_REG + 0x70 + 0x20 + + + T0_INT_ENA + t0_int_ena + 0 + 1 + read-write + + + WDT_INT_ENA + wdt_int_ena + 1 + 1 + read-write + + + + + INT_RAW_TIMERS + INT_RAW_TIMG_REG + 0x74 + 0x20 + + + T0_INT_RAW + t0_int_raw + 0 + 1 + read-only + + + WDT_INT_RAW + wdt_int_raw + 1 + 1 + read-only + + + + + INT_ST_TIMERS + INT_ST_TIMG_REG + 0x78 + 0x20 + + + T0_INT_ST + t0_int_st + 0 + 1 + read-only + + + WDT_INT_ST + wdt_int_st + 1 + 1 + read-only + + + + + INT_CLR_TIMERS + INT_CLR_TIMG_REG + 0x7C + 0x20 + + + T0_INT_CLR + t0_int_clr + 0 + 1 + write-only + + + WDT_INT_CLR + wdt_int_clr + 1 + 1 + write-only + + + + + RTCCALICFG2 + TIMG_RTCCALICFG2_REG. + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + timeoutindicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold + 7 + 25 + read-write + + + + + NTIMG_DATE + TIMG_NTIMG_DATE_REG. + 0xF8 + 0x20 + 0x02006191 + + + NTIMGS_DATE + reg_ntimers_date. + 0 + 28 + read-write + + + + + REGCLK + TIMG_REGCLK_REG. + 0xFC + 0x20 + 0x60000000 + + + WDT_CLK_IS_ACTIVE + reg_wdt_clk_is_active. + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + reg_timer_clk_is_active. + 30 + 1 + read-write + + + CLK_EN + reg_clk_en. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x60020000 + + TG1_T0_LEVEL + 34 + + + TG1_WDT_LEVEL + 35 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x6C + registers + + + TWAI + 25 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + read-write + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + read-write + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + read-write + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + read-write + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. + 0 + 8 + read-write + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + read-write + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 21 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x0000C060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 9 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 9 + 9 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 18 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 19 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 20 + 1 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 21 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow-control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x000026E0 + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 9 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 9 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00002200 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 9 + read-write + + + XON_CHAR + This register stores the Xon flow control char. + 9 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x000A0012 + + + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 9 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 16 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 26 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 27 + 1 + read-write + + + + + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 + 0x20 + 0x00080100 + + + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x6C + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x78 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + + + ID + This register is used to configure the uart_id. + 0 + 30 + read-write + + + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. + 30 + 1 + read-write + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 31 + 1 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60010000 + + UART1 + 22 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x60014000 + + 0x0 + 0x84 + registers + + + UHCI0 + 15 + + + + CONF0 + a + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1, then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1, then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + a + 0x4 + 0x20 + + + RX_START_INT_RAW + a + 0 + 1 + read-only + + + TX_START_INT_RAW + a + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + a + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + a + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + a + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + a + 5 + 1 + read-only + + + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the + 6 + 1 + read-only + + + APP_CTRL0_INT_RAW + Soft control int raw bit. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Soft control int raw bit. + 8 + 1 + read-write + + + + + INT_ST + a + 0x8 + 0x20 + + + RX_START_INT_ST + a + 0 + 1 + read-only + + + TX_START_INT_ST + a + 1 + 1 + read-only + + + RX_HUNG_INT_ST + a + 2 + 1 + read-only + + + TX_HUNG_INT_ST + a + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + a + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + a + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + a + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + a + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + a + 8 + 1 + read-only + + + + + INT_ENA + a + 0xC + 0x20 + + + RX_START_INT_ENA + a + 0 + 1 + read-write + + + TX_START_INT_ENA + a + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + a + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + a + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + a + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + a + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + a + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + a + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + a + 8 + 1 + read-write + + + + + INT_CLR + a + 0x10 + 0x20 + + + RX_START_INT_CLR + a + 0 + 1 + write-only + + + TX_START_INT_CLR + a + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + a + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + a + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + a + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + a + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + a + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + a + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + a + 8 + 1 + write-only + + + + + CONF1 + a + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + a + 0 + 1 + read-write + + + CHECK_SEQ_EN + a + 1 + 1 + read-write + + + CRC_DISABLE + a + 2 + 1 + read-write + + + SAVE_HEAD + a + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + a + 4 + 1 + read-write + + + TX_ACK_NUM_RE + a + 5 + 1 + read-write + + + WAIT_SW_START + a + 7 + 1 + read-write + + + SW_START + a + 8 + 1 + read-write + + + + + STATE0 + a + 0x18 + 0x20 + + + RX_ERR_CAUSE + a + 0 + 3 + read-only + + + DECODE_STATE + a + 3 + 3 + read-only + + + + + STATE1 + a + 0x1C + 0x20 + + + ENCODE_STATE + a + 0 + 3 + read-only + + + + + ESCAPE_CONF + a + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + a + 0 + 1 + read-write + + + TX_DB_ESC_EN + a + 1 + 1 + read-write + + + TX_11_ESC_EN + a + 2 + 1 + read-write + + + TX_13_ESC_EN + a + 3 + 1 + read-write + + + RX_C0_ESC_EN + a + 4 + 1 + read-write + + + RX_DB_ESC_EN + a + 5 + 1 + read-write + + + RX_11_ESC_EN + a + 6 + 1 + read-write + + + RX_13_ESC_EN + a + 7 + 1 + read-write + + + + + HUNG_CONF + a + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + a + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + a + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + a + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + a + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + a + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + a + 23 + 1 + read-write + + + + + ACK_NUM + a + 0x28 + 0x20 + 0x00000008 + + + ACK_NUM + a + 0 + 3 + read-write + + + LOAD + a + 3 + 1 + write-only + + + + + RX_HEAD + a + 0x2C + 0x20 + + + RX_HEAD + a + 0 + 32 + read-only + + + + + QUICK_SENT + a + 0x30 + 0x20 + + + SINGLE_SEND_NUM + a + 0 + 3 + read-write + + + SINGLE_SEND_EN + a + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + a + 4 + 3 + read-write + + + ALWAYS_SEND_EN + a + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + a + 0x34 + 0x20 + + + SEND_Q0_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + a + 0x38 + 0x20 + + + SEND_Q0_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + a + 0x3C + 0x20 + + + SEND_Q1_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + a + 0x40 + 0x20 + + + SEND_Q1_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + a + 0x44 + 0x20 + + + SEND_Q2_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + a + 0x48 + 0x20 + + + SEND_Q2_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + a + 0x4C + 0x20 + + + SEND_Q3_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + a + 0x50 + 0x20 + + + SEND_Q3_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + a + 0x54 + 0x20 + + + SEND_Q4_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + a + 0x58 + 0x20 + + + SEND_Q4_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + a + 0x5C + 0x20 + + + SEND_Q5_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + a + 0x60 + 0x20 + + + SEND_Q5_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + a + 0x64 + 0x20 + + + SEND_Q6_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + a + 0x68 + 0x20 + + + SEND_Q6_WORD1 + a + 0 + 32 + read-write + + + + + ESC_CONF0 + a + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + a + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + a + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF1 + a + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + a + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF2 + a + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + a + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF3 + a + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + a + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + a + 16 + 8 + read-write + + + + + PKT_THRES + a + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + a + 0 + 13 + read-write + + + + + DATE + a + 0x80 + 0x20 + 0x02007170 + + + DATE + a + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface + 0x6000C000 + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x60043000 + + 0x0 + 0x50 + registers + + + USB_SERIAL_JTAG + 26 + + + + EP1 + USB_DEVICE_EP1_REG. + 0x0 + 0x20 + + + RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + USB_DEVICE_EP1_CONF_REG. + 0x4 + 0x20 + 0x00000002 + + + WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + USB_DEVICE_INT_RAW_REG. + 0x8 + 0x20 + 0x00000008 + + + JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-only + + + SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-only + + + PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-only + + + CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-only + + + CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-only + + + STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-only + + + + + INT_ST + USB_DEVICE_INT_ST_REG. + 0xC + 0x20 + + + JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + + + INT_ENA + USB_DEVICE_INT_ENA_REG. + 0x10 + 0x20 + + + JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + + + INT_CLR + USB_DEVICE_INT_CLR_REG. + 0x14 + 0x20 + + + JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + + + CONF0 + USB_DEVICE_CONF0_REG. + 0x18 + 0x20 + 0x00004200 + + + PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + + + TEST + USB_DEVICE_TEST_REG. + 0x1C + 0x20 + + + ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + + + JFIFO_ST + USB_DEVICE_JFIFO_ST_REG. + 0x20 + 0x20 + 0x00000044 + + + IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + USB_DEVICE_FRAM_NUM_REG. + 0x24 + 0x20 + + + SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + USB_DEVICE_IN_EP0_ST_REG. + 0x28 + 0x20 + 0x00000001 + + + IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + USB_DEVICE_IN_EP1_ST_REG. + 0x2C + 0x20 + 0x00000001 + + + IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + USB_DEVICE_IN_EP2_ST_REG. + 0x30 + 0x20 + 0x00000001 + + + IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + USB_DEVICE_IN_EP3_ST_REG. + 0x34 + 0x20 + 0x00000001 + + + IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + USB_DEVICE_OUT_EP0_ST_REG. + 0x38 + 0x20 + + + OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + USB_DEVICE_OUT_EP1_ST_REG. + 0x3C + 0x20 + + + OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + USB_DEVICE_OUT_EP2_ST_REG. + 0x40 + 0x20 + + + OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + USB_DEVICE_MISC_CONF_REG. + 0x44 + 0x20 + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + USB_DEVICE_MEM_CONF_REG. + 0x48 + 0x20 + 0x00000002 + + + USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + DATE + USB_DEVICE_DATE_REG. + 0x80 + 0x20 + 0x02007300 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x600CC000 + + 0x0 + 0x30 + registers + + + + 16 + 0x1 + PLAIN_MEM[%s] + The memory that stores plaintext + 0x0 + 0x8 + + + LINESIZE + XTS-AES line-size register + 0x40 + 0x20 + + + LINESIZE + This bit stores the line size parameter. 0: 16Byte, 1: 32Byte. + 0 + 1 + read-write + + + + + DESTINATION + XTS-AES destination register + 0x44 + 0x20 + + + DESTINATION + This bit stores the destination. 0: flash(default). 1: reserved. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + XTS-AES physical address register + 0x48 + 0x20 + + + PHYSICAL_ADDRESS + Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. + 0 + 30 + read-write + + + + + TRIGGER + XTS-AES trigger register + 0x4C + 0x20 + + + TRIGGER + Set this bit to start manual encryption calculation + 0 + 1 + write-only + + + + + RELEASE + XTS-AES release register + 0x50 + 0x20 + + + RELEASE + Set this bit to release the manual encrypted result, after that the result will be visible to spi + 0 + 1 + write-only + + + + + DESTROY + XTS-AES destroy register + 0x54 + 0x20 + + + DESTROY + Set this bit to destroy XTS-AES result. + 0 + 1 + write-only + + + + + STATE + XTS-AES status register + 0x58 + 0x20 + + + STATE + Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + DATE + XTS-AES version control register + 0x5C + 0x20 + 0x20200623 + + + DATE + Those bits stores the version information of XTS-AES. + 0 + 30 + read-write + + + + + + + diff --git a/tools/ide-debug/svd/esp32c6.svd b/tools/ide-debug/svd/esp32c6.svd new file mode 100644 index 0000000..33d3464 --- /dev/null +++ b/tools/ide-debug/svd/esp32c6.svd @@ -0,0 +1,70852 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-C6 + ESP32-C6 + 1 + 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x60088000 + + 0x0 + 0xBC + registers + + + AES + 73 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x6000E000 + + 0x0 + 0x70 + registers + + + APB_SARADC + 60 + + + + CTRL + digital saradc configure register + 0x0 + 0x20 + 0x40038240 + + + SARADC_START_FORCE + select software enable saradc sample + 0 + 1 + read-write + + + SARADC_START + software enable saradc sample + 1 + 1 + read-write + + + SARADC_SAR_CLK_GATED + SAR clock gated + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 3 + read-write + + + SARADC_SAR_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC2_PWDET_DRV + enable saradc2 power detect driven func. + 29 + 1 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + digital saradc configure register + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable max meas num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + digital saradc configure register + 0x8 + 0x20 + + + APB_SARADC_FILTER_FACTOR1 + Factor of saradc filter1 + 26 + 3 + read-write + + + APB_SARADC_FILTER_FACTOR0 + Factor of saradc filter0 + 29 + 3 + read-write + + + + + FSM_WAIT + digital saradc configure register + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + saradc_xpd_wait + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + saradc_rstb_wait + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + saradc_standby_wait + 16 + 8 + read-write + + + + + SAR1_STATUS + digital saradc configure register + 0x10 + 0x20 + 0x20000000 + + + SARADC_SAR1_STATUS + saradc1 status about data and channel + 0 + 32 + read-only + + + + + SAR2_STATUS + digital saradc configure register + 0x14 + 0x20 + 0x20000000 + + + SARADC_SAR2_STATUS + saradc2 status about data and channel + 0 + 32 + read-only + + + + + SAR_PATT_TAB1 + digital saradc configure register + 0x18 + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR_PATT_TAB2 + digital saradc configure register + 0x1C + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + ONETIME_SAMPLE + digital saradc configure register + 0x20 + 0x20 + 0x1A000000 + + + SARADC_ONETIME_ATTEN + configure onetime atten + 23 + 2 + read-write + + + SARADC_ONETIME_CHANNEL + configure onetime channel + 25 + 4 + read-write + + + SARADC_ONETIME_START + trigger adc onetime sample + 29 + 1 + read-write + + + SARADC2_ONETIME_SAMPLE + enable adc2 onetime sample + 30 + 1 + read-write + + + SARADC1_ONETIME_SAMPLE + enable adc1 onetime sample + 31 + 1 + read-write + + + + + ARB_CTRL + digital saradc configure register + 0x24 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + digital saradc configure register + 0x28 + 0x20 + 0x03740000 + + + APB_SARADC_FILTER_CHANNEL1 + configure filter1 to adc channel + 18 + 4 + read-write + + + APB_SARADC_FILTER_CHANNEL0 + configure filter0 to adc channel + 22 + 4 + read-write + + + APB_SARADC_FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1DATA_STATUS + digital saradc configure register + 0x2C + 0x20 + + + APB_SARADC1_DATA + saradc1 data + 0 + 17 + read-only + + + + + SAR2DATA_STATUS + digital saradc configure register + 0x30 + 0x20 + + + APB_SARADC2_DATA + saradc2 data + 0 + 17 + read-only + + + + + THRES0_CTRL + digital saradc configure register + 0x34 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES0_CHANNEL + configure thres0 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES0_HIGH + saradc thres0 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES0_LOW + saradc thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + digital saradc configure register + 0x38 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES1_CHANNEL + configure thres1 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES1_HIGH + saradc thres1 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES1_LOW + saradc thres1 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + digital saradc configure register + 0x3C + 0x20 + + + APB_SARADC_THRES_ALL_EN + enable thres to all channel + 27 + 1 + read-write + + + APB_SARADC_THRES1_EN + enable thres1 + 30 + 1 + read-write + + + APB_SARADC_THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + digital saradc int register + 0x40 + 0x20 + + + APB_SARADC_TSENS_INT_ENA + tsens low interrupt enable + 25 + 1 + read-write + + + APB_SARADC_THRES1_LOW_INT_ENA + saradc thres1 low interrupt enable + 26 + 1 + read-write + + + APB_SARADC_THRES0_LOW_INT_ENA + saradc thres0 low interrupt enable + 27 + 1 + read-write + + + APB_SARADC_THRES1_HIGH_INT_ENA + saradc thres1 high interrupt enable + 28 + 1 + read-write + + + APB_SARADC_THRES0_HIGH_INT_ENA + saradc thres0 high interrupt enable + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + saradc2 done interrupt enable + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + saradc1 done interrupt enable + 31 + 1 + read-write + + + + + INT_RAW + digital saradc int register + 0x44 + 0x20 + + + APB_SARADC_TSENS_INT_RAW + saradc tsens interrupt raw + 25 + 1 + read-only + + + APB_SARADC_THRES1_LOW_INT_RAW + saradc thres1 low interrupt raw + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_RAW + saradc thres0 low interrupt raw + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_RAW + saradc thres1 high interrupt raw + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_RAW + saradc thres0 high interrupt raw + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + saradc2 done interrupt raw + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + saradc1 done interrupt raw + 31 + 1 + read-only + + + + + INT_ST + digital saradc int register + 0x48 + 0x20 + + + APB_SARADC_TSENS_INT_ST + saradc tsens interrupt state + 25 + 1 + read-only + + + APB_SARADC_THRES1_LOW_INT_ST + saradc thres1 low interrupt state + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_ST + saradc thres0 low interrupt state + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_ST + saradc thres1 high interrupt state + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_ST + saradc thres0 high interrupt state + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + saradc2 done interrupt state + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + saradc1 done interrupt state + 31 + 1 + read-only + + + + + INT_CLR + digital saradc int register + 0x4C + 0x20 + + + APB_SARADC_TSENS_INT_CLR + saradc tsens interrupt clear + 25 + 1 + write-only + + + APB_SARADC_THRES1_LOW_INT_CLR + saradc thres1 low interrupt clear + 26 + 1 + write-only + + + APB_SARADC_THRES0_LOW_INT_CLR + saradc thres0 low interrupt clear + 27 + 1 + write-only + + + APB_SARADC_THRES1_HIGH_INT_CLR + saradc thres1 high interrupt clear + 28 + 1 + write-only + + + APB_SARADC_THRES0_HIGH_INT_CLR + saradc thres0 high interrupt clear + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + saradc2 done interrupt clear + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + saradc1 done interrupt clear + 31 + 1 + write-only + + + + + DMA_CONF + digital saradc configure register + 0x50 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + CLKM_CONF + digital saradc configure register + 0x54 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + reg clk en + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_TSENS_CTRL + digital tsens configure register + 0x58 + 0x20 + 0x00018080 + + + TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + TSENS_PU + temperature sensor power up + 22 + 1 + read-write + + + + + TSENS_CTRL2 + digital tsens configure register + 0x5C + 0x20 + 0x00004002 + + + TSENS_XPD_WAIT + the time that power up tsens need wait + 0 + 12 + read-write + + + TSENS_XPD_FORCE + force power up tsens + 12 + 2 + read-write + + + TSENS_CLK_INV + inv tsens clk + 14 + 1 + read-write + + + TSENS_CLK_SEL + tsens clk select + 15 + 1 + read-write + + + + + CALI + digital saradc configure register + 0x60 + 0x20 + 0x00008000 + + + APB_SARADC_CALI_CFG + saradc cali factor + 0 + 17 + read-write + + + + + APB_TSENS_WAKE + digital tsens configure register + 0x64 + 0x20 + 0x0000FF00 + + + WAKEUP_TH_LOW + reg_wakeup_th_low + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + reg_wakeup_th_high + 8 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + reg_wakeup_over_upper_th + 16 + 1 + read-only + + + WAKEUP_MODE + reg_wakeup_mode + 17 + 1 + read-write + + + WAKEUP_EN + reg_wakeup_en + 18 + 1 + read-write + + + + + APB_TSENS_SAMPLE + digital tsens configure register + 0x68 + 0x20 + 0x00000014 + + + TSENS_SAMPLE_RATE + HW sample rate + 0 + 16 + read-write + + + TSENS_SAMPLE_EN + HW sample en + 16 + 1 + read-write + + + + + CTRL_DATE + version + 0x3FC + 0x20 + 0x02206240 + + + DATE + version + 0 + 32 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x600C2000 + + 0x0 + 0x80 + registers + + + ASSIST_DEBUG + 26 + + + + C0RE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + C0RE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + C0RE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CLOCK_GATE + clock register + 0x78 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + ATOMIC + Peripheral ATOMIC + ATOMIC + 0x60011000 + + 0x0 + 0x14 + registers + + + + ADDR_LOCK + hardware lock regsiter + 0x0 + 0x20 + + + LOCK + read to acquire hardware lock, write to release hardware lock + 0 + 2 + read-write + + + + + LR_ADDR + gloable lr address regsiter + 0x4 + 0x20 + + + GLOABLE_LR_ADDR + backup gloable address + 0 + 32 + read-write + + + + + LR_VALUE + gloable lr value regsiter + 0x8 + 0x20 + + + GLOABLE_LR_VALUE + backup gloable value + 0 + 32 + read-write + + + + + LOCK_STATUS + lock status regsiter + 0xC + 0x20 + + + LOCK_STATUS + read hareware lock status for debug + 0 + 2 + read-only + + + + + COUNTER + wait counter register + 0x10 + 0x20 + + + WAIT_COUNTER + delay counter + 0 + 16 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x60080000 + + 0x0 + 0x1A4 + registers + + + DMA_IN_CH0 + 66 + + + DMA_IN_CH1 + 67 + + + DMA_IN_CH2 + 68 + + + DMA_OUT_CH0 + 69 + + + DMA_OUT_CH1 + 70 + + + DMA_OUT_CH2 + 71 + + + + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + + + AHB_TEST + reserved + 0x60 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + MISC register + 0x64 + 0x20 + + + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 + 1 + read-write + + + + + DATE + Version control register + 0x68 + 0x20 + 0x02202250 + + + DATE + register version. + 0 + 32 + read-write + + + + + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 + 0x20 + + + IN_RST_CH + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 5 + 1 + read-write + + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 27 + 1 + read-only + + + + + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 + 0x20 + 0x01100000 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 23 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL_CH + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + + + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR_CH + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 22 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC + 0x20 + + + TX_PRI_CH + The priority of Tx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 2 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 + 0x20 + 0x00000008 + + + OUT_RST_CH + This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. + 6 + 1 + read-write + + + + + + + DS + Digital Signature + DS + 0x6008C000 + + 0x0 + 0xA5C + registers + + + + 512 + 0x1 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x8 + + + 512 + 0x1 + M_MEM[%s] + memory that stores M + 0x200 + 0x8 + + + 512 + 0x1 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x8 + + + 48 + 0x1 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x8 + + + 16 + 0x1 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + memory that stores X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x8 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + ECC + Peripheral ECC + ECC + 0x6008B000 + + 0x0 + 0x78 + registers + + + ECC + 76 + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + 0x80000000 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SECURITY_MODE + Reserved + 3 + 1 + read-write + + + CLK_EN + Write 1 to force on register clock gate. + 4 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. + 5 + 3 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 8 + 1 + read-only + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02201240 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 32 + 0x1 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x8 + + + 32 + 0x1 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x8 + + + 32 + 0x1 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x8 + + + + + EFUSE + eFuse Controller + EFUSE + 0x600B0800 + + 0x0 + 0x1D0 + registers + + + EFUSE + 14 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + SWAP_UART_SDIO_EN + Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped. + 7 + 1 + read-only + + + DIS_ICACHE + Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled. + 13 + 1 + read-only + + + DIS_CAN + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DREFH + Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + 21 + 2 + read-only + + + USB_DREFL + Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO + Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned. + 26 + 1 + read-only + + + RPT4_RESERVED0_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + RPT4_RESERVED1_0 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x00080000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + DPA_SEC_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + RPT4_RESERVED2_1 + Reserved. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + RPT4_RESERVED2_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + RPT4_RESERVED3_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + RPT4_RESERVED3_4 + Reserved. + 8 + 1 + read-only + + + RPT4_RESERVED3_3 + Reserved. + 9 + 1 + read-only + + + RPT4_RESERVED3_2 + Reserved. + 10 + 2 + read-only + + + RPT4_RESERVED3_1 + Reserved. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 13 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 14 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 30 + 1 + read-only + + + RPT4_RESERVED3_0 + Reserved. + 31 + 1 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED4_1 + Reserved. + 0 + 24 + read-only + + + RPT4_RESERVED4_0 + Reserved. + 24 + 8 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_SPI_RESERVED + Reserved. + 0 + 14 + read-only + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 14 + 18 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + SWAP_UART_SDIO_EN_ERR + Indicates a programming error of SWAP_UART_SDIO_EN. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + Indicates a programming error of DIS_ICACHE. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + Indicates a programming error of DIS_DOWNLOAD_ICACHE. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_DEVICE. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_CAN. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DREFH_ERR + Indicates a programming error of USB_DREFH. + 21 + 2 + read-only + + + USB_DREFL_ERR + Indicates a programming error of USB_DREFL. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + Indicates a programming error of USB_EXCHG_PINS. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO_ERR + Indicates a programming error of VDD_SPI_AS_GPIO. + 26 + 1 + read-only + + + RPT4_RESERVED0_ERR_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_ERR_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_ERR_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + RPT4_RESERVED1_ERR_0 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + RPT4_RESERVED2_ERR_1 + Reserved. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + RPT4_RESERVED2_ERR_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + USB_PRINT_ERR + Indicates a programming error of UART_PRINT_CHANNEL. + 2 + 1 + read-only + + + RPT4_RESERVED3_ERR_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + RPT4_RESERVED3_ERR_4 + Reserved. + 8 + 1 + read-only + + + RPT4_RESERVED3_ERR_3 + Reserved. + 9 + 1 + read-only + + + RPT4_RESERVED3_ERR_2 + Reserved. + 10 + 2 + read-only + + + RPT4_RESERVED3_ERR_1 + Reserved. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE_VERSION. + 14 + 16 + read-only + + + RPT4_RESERVED3_ERR_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED4_ERR_1 + Reserved. + 0 + 24 + read-only + + + RPT4_RESERVED4_ERR_0 + Reserved. + 24 + 8 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01300001 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00C80190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02206300 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C8000 + + 0x0 + 0x3C8 + registers + + + + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 + 0x20 + + + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + 0 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + 1 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS2 + Reserved + 2 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS3 + Reserved + 3 + 1 + read-only + + + L1_ICACHE_UNDEF_OP + Reserved + 4 + 4 + read-only + + + + + L1_CACHE_CTRL + L1 data Cache(L1-Cache) control register + 0x4 + 0x20 + + + L1_CACHE_SHUT_BUS0 + The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_CACHE_SHUT_BUS1 + The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_CACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_CACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_CACHE_SHUT_DMA + The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable + 4 + 1 + read-only + + + L1_CACHE_UNDEF_OP + Reserved + 8 + 4 + read-write + + + + + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 + 0x20 + + + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + 0 + 1 + read-only + + + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + 1 + 1 + read-only + + + BYPASS_L1_ICACHE2_EN + Reserved + 2 + 1 + read-only + + + BYPASS_L1_ICACHE3_EN + Reserved + 3 + 1 + read-only + + + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 + 1 + read-only + + + + + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC + 0x20 + + + L1_CACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-Cache when multiple cores access L1-Cache. 1: disable, 1: enable. + 0 + 1 + read-only + + + + + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 + 0x20 + + + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2048K + The field is used to configure cachesize of L1-ICache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4096K + The field is used to configure cachesize of L1-ICache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 + 0x20 + + + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 + 0x20 + 0x00000020 + + + L1_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-Cache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-Cache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-Cache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-Cache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-Cache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-Cache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-Cache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-Cache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-Cache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-Cache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_CACHE_CACHESIZE_2048K + The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_CACHE_CACHESIZE_4096K + The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_CACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C + 0x20 + 0x00000004 + + + L1_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 + 0x20 + + + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. + 0 + 1 + read-only + + + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 + read-only + + + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_CACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 + 0x20 + 0x00055555 + + + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 + 0x20 + 0x00055555 + + + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C + 0x20 + + + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + 0 + 1 + read-only + + + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 1 + 1 + read-only + + + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + 4 + 1 + read-only + + + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 + 1 + read-only + + + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 + 1 + read-only + + + L1_ICACHE2_FREEZE_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_FREEZE_MODE + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_FREEZE_DONE + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_FREEZE_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_FREEZE_MODE + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_FREEZE_DONE + Reserved + 14 + 1 + read-only + + + L1_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-Cache. It can be cleared by software. + 16 + 1 + read-write + + + L1_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 + 1 + read-write + + + L1_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-Cache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only + + + + + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 + 0x20 + 0x00033333 + + + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + 0 + 1 + read-only + + + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + 1 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 + 1 + read-only + + + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 + 0x20 + 0x00033333 + + + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + 0 + 1 + read-only + + + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + 1 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. + 4 + 1 + read-only + + + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. + 5 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. + 0 + 1 + read-only + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_CACHE_PRELOCK_CONF + L1 Cache prelock configure register + 0x78 + 0x20 + + + L1_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-Cache. + 0 + 1 + read-write + + + L1_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-Cache. + 1 + 1 + read-write + + + L1_CACHE_PRELOCK_RGID + The bit is used to set the gid of l1 cache prelock. + 2 + 4 + read-only + + + + + L1_CACHE_PRELOCK_SCT0_ADDR + L1 Cache prelock section0 address configure register + 0x7C + 0x20 + + + L1_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 Cache prelock section1 address configure register + 0x80 + 0x20 + + + L1_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT_SIZE + L1 Cache prelock section size configure register + 0x84 + 0x20 + 0x3FFF3FFF + + + L1_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + CACHE_LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 + 0x20 + 0x00000004 + + + CACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done + 0 + 1 + read-write + + + CACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done + 1 + 1 + read-write + + + CACHE_LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + CACHE_LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-only + + + + + CACHE_LOCK_MAP + Lock (manual lock) map configure register + 0x8C + 0x20 + + + CACHE_LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [4]: L1-Cache + 0 + 6 + read-write + + + + + CACHE_LOCK_ADDR + Lock (manual lock) address configure register + 0x90 + 0x20 + + + CACHE_LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + 0 + 32 + read-write + + + + + CACHE_LOCK_SIZE + Lock (manual lock) size configure register + 0x94 + 0x20 + + + CACHE_LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + 0 + 16 + read-write + + + + + CACHE_SYNC_CTRL + Sync-class operation control register + 0x98 + 0x20 + 0x00000001 + + + CACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 0 + 1 + read-write + + + CACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + CACHE_WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + CACHE_WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + CACHE_SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 + read-only + + + CACHE_SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-only + + + + + CACHE_SYNC_MAP + Sync map configure register + 0x9C + 0x20 + 0x0000003F + + + CACHE_SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [4]: L1-Cache + 0 + 6 + read-write + + + + + CACHE_SYNC_ADDR + Sync address configure register + 0xA0 + 0x20 + + + CACHE_SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG + 0 + 32 + read-write + + + + + CACHE_SYNC_SIZE + Sync size configure register + 0xA4 + 0x20 + + + CACHE_SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG + 0 + 24 + read-write + + + + + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 + 0x20 + 0x00000002 + + + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-only + + + + + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC + 0x20 + + + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 + 0x20 + + + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 + 0x20 + 0x00000002 + + + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-only + + + + + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 + 0x20 + + + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC + 0x20 + + + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 + 0x20 + 0x00000002 + + + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 + read-only + + + + + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 + 0x20 + + + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 + 0x20 + + + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC + 0x20 + 0x00000002 + + + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 + read-only + + + + + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 + 0x20 + + + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 + 0x20 + + + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_CACHE_PRELOAD_CTRL + L1 Cache preload-operation control register + 0xD8 + 0x20 + 0x00000002 + + + L1_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_CACHE_PRELOAD_RGID + The bit is used to set the gid of l1 cache preload. + 3 + 4 + read-only + + + + + L1_DCACHE_PRELOAD_ADDR + L1 Cache preload address configure register + 0xDC + 0x20 + + + L1_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOAD_SIZE + L1 Cache preload size configure register + 0xE0 + 0x20 + + + L1_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 + 0x20 + 0x00000002 + + + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. + 8 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. + 9 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 + 0x20 + 0x00000002 + + + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C + 0x20 + 0x00000002 + + + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. + 8 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. + 9 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 + 0x20 + 0x00000002 + + + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + Reserved + 0 + 28 + read-only + + + + + L1_CACHE_AUTOLOAD_CTRL + L1 Cache autoload-operation control register + 0x134 + 0x20 + 0x00000002 + + + L1_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-Cache. + 8 + 1 + read-write + + + L1_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-Cache. + 9 + 1 + read-write + + + L1_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-Cache. + 10 + 1 + read-only + + + L1_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-Cache. + 11 + 1 + read-only + + + L1_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 cache autoload. + 12 + 4 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT0_ADDR + L1 Cache autoload section 0 address configure register + 0x138 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT0_SIZE + L1 Cache autoload section 0 size configure register + 0x13C + 0x20 + + + L1_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT1_ADDR + L1 Cache autoload section 1 address configure register + 0x140 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT1_SIZE + L1 Cache autoload section 1 size configure register + 0x144 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_AUTOLOAD_SCT2_ADDR + L1 Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT2_SIZE + L1 Cache autoload section 2 size configure register + 0x14C + 0x20 + + + L1_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT3_ADDR + L1 Cache autoload section 1 address configure register + 0x150 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-only + + + + + L1_CACHE_AUTOLOAD_SCT3_SIZE + L1 Cache autoload section 1 size configure register + 0x154 + 0x20 + + + L1_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-only + + + + + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 + 0x20 + + + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_BUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ENA + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C + 0x20 + + + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + write-only + + + L1_BUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 + 0x20 + + + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_BUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 + 0x20 + + + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ST + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ST + Reserved + 3 + 1 + read-only + + + L1_BUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_BUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_ST + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x168 + 0x20 + + + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x16C + 0x20 + + + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + write-only + + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x170 + 0x20 + + + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x174 + 0x20 + + + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only + + + L1_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x178 + 0x20 + + + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_CNT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_CNT_ENA + Reserved + 3 + 1 + read-only + + + L1_BUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 + 1 + read-write + + + L1_BUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_CNT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_CNT_ENA + Reserved + 7 + 1 + read-only + + + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 + 1 + read-only + + + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 + 1 + read-only + + + L1_IBUS2_CNT_CLR + Reserved + 18 + 1 + read-only + + + L1_IBUS3_CNT_CLR + Reserved + 19 + 1 + read-only + + + L1_BUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 + 1 + write-only + + + L1_BUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 + 1 + write-only + + + L1_DBUS2_CNT_CLR + Reserved + 22 + 1 + read-only + + + L1_DBUS3_CNT_CLR + Reserved + 23 + 1 + read-only + + + + + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x17C + 0x20 + + + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x180 + 0x20 + + + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x184 + 0x20 + + + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_NXTLVL_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x188 + 0x20 + + + L1_IBUS0_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x18C + 0x20 + + + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x190 + 0x20 + + + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x194 + 0x20 + + + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_NXTLVL_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x198 + 0x20 + + + L1_IBUS1_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x19C + 0x20 + + + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A0 + 0x20 + + + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A4 + 0x20 + + + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_NXTLVL_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1A8 + 0x20 + + + L1_IBUS2_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1AC + 0x20 + + + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B0 + 0x20 + + + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B4 + 0x20 + + + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_NXTLVL_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1B8 + 0x20 + + + L1_IBUS3_NXTLVL_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_HIT_CNT + L1-Cache bus0 Hit-Access Counter register + 0x1BC + 0x20 + + + L1_BUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_MISS_CNT + L1-Cache bus0 Miss-Access Counter register + 0x1C0 + 0x20 + + + L1_BUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_CONFLICT_CNT + L1-Cache bus0 Conflict-Access Counter register + 0x1C4 + 0x20 + + + L1_BUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS0_ACS_NXTLVL_CNT + L1-Cache bus0 Next-Level-Access Counter register + 0x1C8 + 0x20 + + + L1_BUS0_NXTLVL_CNT + The register records the number of times that L1-Cache accesses L2-Cache due to bus0 accessing L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_HIT_CNT + L1-Cache bus1 Hit-Access Counter register + 0x1CC + 0x20 + + + L1_BUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_MISS_CNT + L1-Cache bus1 Miss-Access Counter register + 0x1D0 + 0x20 + + + L1_BUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_CONFLICT_CNT + L1-Cache bus1 Conflict-Access Counter register + 0x1D4 + 0x20 + + + L1_BUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_BUS1_ACS_NXTLVL_CNT + L1-Cache bus1 Next-Level-Access Counter register + 0x1D8 + 0x20 + + + L1_BUS1_NXTLVL_CNT + The register records the number of times that L1-Cache accesses L2-Cache due to bus1 accessing L1-Cache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1DC + 0x20 + + + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1E0 + 0x20 + + + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1E4 + 0x20 + + + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1E8 + 0x20 + + + L1_DBUS2_NXTLVL_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1EC + 0x20 + + + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x1F0 + 0x20 + + + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x1F4 + 0x20 + + + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x1F8 + 0x20 + + + L1_DBUS3_NXTLVL_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x1FC + 0x20 + + + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x200 + 0x20 + + + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x204 + 0x20 + + + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x208 + 0x20 + + + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x20C + 0x20 + + + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x210 + 0x20 + + + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x214 + 0x20 + + + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x218 + 0x20 + + + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_CACHE_ACS_FAIL_ID_ATTR + L1-Cache Access Fail ID/attribution information register + 0x21C + 0x20 + + + L1_CACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-Cache. + 0 + 16 + read-only + + + L1_CACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-Cache. + 16 + 16 + read-only + + + + + L1_DCACHE_ACS_FAIL_ADDR + L1-Cache Access Fail Address information register + 0x220 + 0x20 + + + L1_CACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-Cache. + 0 + 32 + read-only + + + + + L1_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x224 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-Cache preload-operation. If preload operation is done, interrupt occurs. + 4 + 1 + read-write + + + CACHE_SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-Cache preload-operation error. + 11 + 1 + read-write + + + CACHE_SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 + 1 + read-write + + + + + L1_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x228 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + write-only + + + CACHE_SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + write-only + + + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-Cache preload-operation error. + 11 + 1 + write-only + + + CACHE_SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only + + + + + L1_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x22C + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_RAW + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + read-only + + + CACHE_SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-Cache preload-operation error occurs. + 11 + 1 + read-only + + + CACHE_SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 + read-only + + + + + L1_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x230 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-Cache preload-operation is done. + 4 + 1 + read-only + + + CACHE_SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-Cache preload-operation error. + 11 + 1 + read-only + + + CACHE_SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only + + + + + L1_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x234 + 0x20 + + + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. + 0 + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-Cache. + 8 + 2 + read-only + + + CACHE_SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only + + + + + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x238 + 0x20 + + + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 0 + 1 + read-only + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-only + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_CACHE_SYNC_RST + set this bit to reset sync-logic inside L1-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x23C + 0x20 + + + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_CACHE_PLD_RST + set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x240 + 0x20 + + + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + 0 + 1 + read-only + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-only + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, autoload will not work in L1-Cache. This bit should not be active when autoload works in L1-Cache. + 4 + 1 + read-write + + + + + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x244 + 0x20 + + + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + 0 + 1 + read-only + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-only + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 cache where the unallocate request is responsed but not completed. + 4 + 1 + read-write + + + + + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x248 + 0x20 + + + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-only + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-only + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_CACHE_TAG_OBJECT + Set this bit to set L1-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-only + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-only + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_CACHE_MEM_OBJECT + Set this bit to set L1-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 + read-write + + + + + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x24C + 0x20 + + + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L1_CACHE_VADDR + Cache Vaddr register + 0x250 + 0x20 + 0x40000000 + + + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x254 + 0x20 + 0x00000254 + + + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x258 + 0x20 + 0x00000258 + + + LEVEL_SPLIT0 + Reserved + 0 + 32 + read-only + + + + + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x25C + 0x20 + + + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-only + + + L2_CACHE_UNDEF_OP + Reserved + 5 + 4 + read-only + + + + + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x260 + 0x20 + + + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 + read-only + + + + + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x264 + 0x20 + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L2_CACHE_CACHESIZE_2048K + The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L2_CACHE_CACHESIZE_4096K + The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x268 + 0x20 + + + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x26C + 0x20 + + + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 + read-only + + + + + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x270 + 0x20 + + + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-only + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-only + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x274 + 0x20 + + + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-only + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-only + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-only + + + + + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x278 + 0x20 + + + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 + read-only + + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-only + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x27C + 0x20 + + + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-only + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 + read-only + + + + + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x280 + 0x20 + + + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-only + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 + read-only + + + + + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x284 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. + 0 + 1 + read-only + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-only + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 + read-only + + + + + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x288 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x28C + 0x20 + + + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x290 + 0x20 + 0xFFFFFFFF + + + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 16 + read-only + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 + read-only + + + + + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x294 + 0x20 + 0x00000002 + + + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 + read-only + + + + + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x298 + 0x20 + + + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x29C + 0x20 + + + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + 0 + 16 + read-only + + + + + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2A0 + 0x20 + 0x00000002 + + + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + 0 + 1 + read-only + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-only + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-only + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2A4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2A8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2AC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2B0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2B4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2B8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2BC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-only + + + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2C0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-only + + + + + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2C4 + 0x20 + + + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2C8 + 0x20 + + + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2CC + 0x20 + + + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2D0 + 0x20 + + + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2D4 + 0x20 + + + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2D8 + 0x20 + + + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2DC + 0x20 + + + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2E0 + 0x20 + + + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2E4 + 0x20 + + + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + read-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + read-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + read-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + read-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + + + + + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x2E8 + 0x20 + + + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x2EC + 0x20 + + + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x2F0 + 0x20 + + + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_NXTLVL_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x2F4 + 0x20 + + + L2_IBUS0_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x2F8 + 0x20 + + + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x2FC + 0x20 + + + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x300 + 0x20 + + + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_NXTLVL_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x304 + 0x20 + + + L2_IBUS1_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x308 + 0x20 + + + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x30C + 0x20 + + + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x310 + 0x20 + + + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_NXTLVL_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x314 + 0x20 + + + L2_IBUS2_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x318 + 0x20 + + + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x31C + 0x20 + + + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x320 + 0x20 + + + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_NXTLVL_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x324 + 0x20 + + + L2_IBUS3_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x328 + 0x20 + + + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x32C + 0x20 + + + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x330 + 0x20 + + + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x334 + 0x20 + + + L2_DBUS0_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x338 + 0x20 + + + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x33C + 0x20 + + + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x340 + 0x20 + + + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x344 + 0x20 + + + L2_DBUS1_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x348 + 0x20 + + + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x34C + 0x20 + + + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x350 + 0x20 + + + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x354 + 0x20 + + + L2_DBUS2_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x358 + 0x20 + + + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x35C + 0x20 + + + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x360 + 0x20 + + + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x364 + 0x20 + + + L2_DBUS3_NXTLVL_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x368 + 0x20 + + + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. + 0 + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only + + + + + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x36C + 0x20 + + + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. + 0 + 32 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x370 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x374 + 0x20 + + + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x378 + 0x20 + + + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x37C + 0x20 + + + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x380 + 0x20 + + + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only + + + + + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x384 + 0x20 + + + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 + read-only + + + + + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x388 + 0x20 + + + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 + read-only + + + + + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x38C + 0x20 + + + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 + read-only + + + + + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x390 + 0x20 + + + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 + read-only + + + + + L2_CACHE_ACCESS_ATTR_CTRL + L1 Cache access Attribute propagation control register + 0x394 + 0x20 + 0x0000000F + + + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. + 0 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 + read-only + + + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 + read-only + + + + + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x398 + 0x20 + + + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 + read-only + + + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 + read-only + + + + + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x39C + 0x20 + + + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-only + + + + + L2_CACHE_VADDR + Cache Vaddr register + 0x3A0 + 0x20 + 0x40000000 + + + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-only + + + + + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3A4 + 0x20 + 0x000003A4 + + + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-only + + + + + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3A8 + 0x20 + 0x000003A8 + + + LEVEL_SPLIT1 + Reserved + 0 + 32 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x3AC + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3B0 + 0x20 + + + CACHE_REDCY_SIG0 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3B4 + 0x20 + + + CACHE_REDCY_SIG1 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3B8 + 0x20 + + + CACHE_REDCY_SIG2 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3BC + 0x20 + + + CACHE_REDCY_SIG3 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3C0 + 0x20 + + + CACHE_REDCY_SIG4 + Those bits are prepared for ECO. + 0 + 4 + read-only + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02202080 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60091000 + + 0x0 + 0x314 + registers + + + GPIO_PRO + 30 + + + GPIO_PRO_NMI + 31 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-34 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-34 + 0 + 3 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-34 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-34 + 0 + 3 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-34 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-34 + 0 + 3 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-34 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-34 + 0 + 3 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-34 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-34 + 0 + 3 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-34 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-34 + 0 + 3 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + IN1 + GPIO input register for GPIO32-34 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-34 + 0 + 3 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-34 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-34 + 0 + 3 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-34 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-34 + 0 + 3 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-34 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-34 + 0 + 3 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-34 + 0x68 + 0x20 + + + PROCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + PCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + 0x6C + 0x20 + + + PROCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + CPUSDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-34 + 0x70 + 0x20 + + + SDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-34 + 0 + 3 + read-only + + + + + 35 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-34 + 0x150 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-34 + 0 + 3 + read-only + + + + + FUNC0_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + 0x0000003C + + + FUNC0_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC0_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG0_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC6_IN_SEL_CFG + GPIO input function configuration register + 0x16C + 0x20 + 0x0000003C + + + FUNC6_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC6_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG6_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC7_IN_SEL_CFG + GPIO input function configuration register + 0x170 + 0x20 + 0x0000003C + + + FUNC7_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC7_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG7_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC8_IN_SEL_CFG + GPIO input function configuration register + 0x174 + 0x20 + 0x0000003C + + + FUNC8_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC8_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG8_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC9_IN_SEL_CFG + GPIO input function configuration register + 0x178 + 0x20 + 0x00000038 + + + FUNC9_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC9_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG9_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC10_IN_SEL_CFG + GPIO input function configuration register + 0x17C + 0x20 + 0x0000003C + + + FUNC10_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC10_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG10_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC11_IN_SEL_CFG + GPIO input function configuration register + 0x180 + 0x20 + 0x0000003C + + + FUNC11_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC11_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG11_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC12_IN_SEL_CFG + GPIO input function configuration register + 0x184 + 0x20 + 0x0000003C + + + FUNC12_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC12_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG12_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC13_IN_SEL_CFG + GPIO input function configuration register + 0x188 + 0x20 + 0x0000003C + + + FUNC13_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC13_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG13_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC14_IN_SEL_CFG + GPIO input function configuration register + 0x18C + 0x20 + 0x0000003C + + + FUNC14_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC14_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG14_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC15_IN_SEL_CFG + GPIO input function configuration register + 0x190 + 0x20 + 0x0000003C + + + FUNC15_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC15_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG15_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC16_IN_SEL_CFG + GPIO input function configuration register + 0x194 + 0x20 + 0x0000003C + + + FUNC16_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC16_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG16_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC17_IN_SEL_CFG + GPIO input function configuration register + 0x198 + 0x20 + 0x0000003C + + + FUNC17_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC17_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG17_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC19_IN_SEL_CFG + GPIO input function configuration register + 0x1A0 + 0x20 + 0x0000003C + + + FUNC19_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC19_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG19_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC28_IN_SEL_CFG + GPIO input function configuration register + 0x1C4 + 0x20 + 0x0000003C + + + FUNC28_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC28_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG28_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC29_IN_SEL_CFG + GPIO input function configuration register + 0x1C8 + 0x20 + 0x0000003C + + + FUNC29_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC29_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG29_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC30_IN_SEL_CFG + GPIO input function configuration register + 0x1CC + 0x20 + 0x0000003C + + + FUNC30_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC30_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG30_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC31_IN_SEL_CFG + GPIO input function configuration register + 0x1D0 + 0x20 + 0x0000003C + + + FUNC31_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC31_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG31_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC32_IN_SEL_CFG + GPIO input function configuration register + 0x1D4 + 0x20 + 0x0000003C + + + FUNC32_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC32_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG32_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC33_IN_SEL_CFG + GPIO input function configuration register + 0x1D8 + 0x20 + 0x0000003C + + + FUNC33_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC33_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG33_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC34_IN_SEL_CFG + GPIO input function configuration register + 0x1DC + 0x20 + 0x0000003C + + + FUNC34_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC34_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG34_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC35_IN_SEL_CFG + GPIO input function configuration register + 0x1E0 + 0x20 + 0x0000003C + + + FUNC35_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC35_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG35_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC40_IN_SEL_CFG + GPIO input function configuration register + 0x1F4 + 0x20 + 0x0000003C + + + FUNC40_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC40_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG40_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC41_IN_SEL_CFG + GPIO input function configuration register + 0x1F8 + 0x20 + 0x0000003C + + + FUNC41_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC41_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG41_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC42_IN_SEL_CFG + GPIO input function configuration register + 0x1FC + 0x20 + 0x0000003C + + + FUNC42_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC42_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG42_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC45_IN_SEL_CFG + GPIO input function configuration register + 0x208 + 0x20 + 0x00000038 + + + FUNC45_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC45_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG45_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC46_IN_SEL_CFG + GPIO input function configuration register + 0x20C + 0x20 + 0x00000038 + + + FUNC46_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC46_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG46_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC47_IN_SEL_CFG + GPIO input function configuration register + 0x210 + 0x20 + 0x0000003C + + + FUNC47_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC47_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG47_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC48_IN_SEL_CFG + GPIO input function configuration register + 0x214 + 0x20 + 0x0000003C + + + FUNC48_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC48_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG48_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC49_IN_SEL_CFG + GPIO input function configuration register + 0x218 + 0x20 + 0x0000003C + + + FUNC49_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC49_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG49_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC50_IN_SEL_CFG + GPIO input function configuration register + 0x21C + 0x20 + 0x0000003C + + + FUNC50_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC50_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG50_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC51_IN_SEL_CFG + GPIO input function configuration register + 0x220 + 0x20 + 0x0000003C + + + FUNC51_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC51_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG51_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC52_IN_SEL_CFG + GPIO input function configuration register + 0x224 + 0x20 + 0x0000003C + + + FUNC52_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC52_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG52_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC53_IN_SEL_CFG + GPIO input function configuration register + 0x228 + 0x20 + 0x0000003C + + + FUNC53_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC53_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG53_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC54_IN_SEL_CFG + GPIO input function configuration register + 0x22C + 0x20 + 0x0000003C + + + FUNC54_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC54_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG54_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC55_IN_SEL_CFG + GPIO input function configuration register + 0x230 + 0x20 + 0x0000003C + + + FUNC55_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC55_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG55_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC56_IN_SEL_CFG + GPIO input function configuration register + 0x234 + 0x20 + 0x0000003C + + + FUNC56_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC56_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG56_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC57_IN_SEL_CFG + GPIO input function configuration register + 0x238 + 0x20 + 0x0000003C + + + FUNC57_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC57_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG57_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC58_IN_SEL_CFG + GPIO input function configuration register + 0x23C + 0x20 + 0x0000003C + + + FUNC58_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC58_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG58_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC59_IN_SEL_CFG + GPIO input function configuration register + 0x240 + 0x20 + 0x0000003C + + + FUNC59_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC59_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG59_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC60_IN_SEL_CFG + GPIO input function configuration register + 0x244 + 0x20 + 0x0000003C + + + FUNC60_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC60_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG60_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC61_IN_SEL_CFG + GPIO input function configuration register + 0x248 + 0x20 + 0x0000003C + + + FUNC61_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC61_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG61_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC62_IN_SEL_CFG + GPIO input function configuration register + 0x24C + 0x20 + 0x0000003C + + + FUNC62_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC62_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG62_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC63_IN_SEL_CFG + GPIO input function configuration register + 0x250 + 0x20 + 0x0000003C + + + FUNC63_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC63_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG63_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC64_IN_SEL_CFG + GPIO input function configuration register + 0x254 + 0x20 + 0x0000003C + + + FUNC64_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC64_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG64_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC65_IN_SEL_CFG + GPIO input function configuration register + 0x258 + 0x20 + 0x0000003C + + + FUNC65_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC65_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG65_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC66_IN_SEL_CFG + GPIO input function configuration register + 0x25C + 0x20 + 0x0000003C + + + FUNC66_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC66_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG66_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC67_IN_SEL_CFG + GPIO input function configuration register + 0x260 + 0x20 + 0x0000003C + + + FUNC67_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC67_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG67_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC68_IN_SEL_CFG + GPIO input function configuration register + 0x264 + 0x20 + 0x0000003C + + + FUNC68_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC68_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG68_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC69_IN_SEL_CFG + GPIO input function configuration register + 0x268 + 0x20 + 0x0000003C + + + FUNC69_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC69_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG69_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC70_IN_SEL_CFG + GPIO input function configuration register + 0x26C + 0x20 + 0x0000003C + + + FUNC70_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC70_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG70_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC71_IN_SEL_CFG + GPIO input function configuration register + 0x270 + 0x20 + 0x0000003C + + + FUNC71_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC71_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG71_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC72_IN_SEL_CFG + GPIO input function configuration register + 0x274 + 0x20 + 0x0000003C + + + FUNC72_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC72_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG72_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC73_IN_SEL_CFG + GPIO input function configuration register + 0x278 + 0x20 + 0x00000038 + + + FUNC73_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC73_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG73_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC77_IN_SEL_CFG + GPIO input function configuration register + 0x288 + 0x20 + 0x00000038 + + + FUNC77_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC77_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG77_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC81_IN_SEL_CFG + GPIO input function configuration register + 0x298 + 0x20 + 0x0000003C + + + FUNC81_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC81_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG81_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC82_IN_SEL_CFG + GPIO input function configuration register + 0x29C + 0x20 + 0x0000003C + + + FUNC82_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC82_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG82_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC87_IN_SEL_CFG + GPIO input function configuration register + 0x2B0 + 0x20 + 0x0000003C + + + FUNC87_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC87_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG87_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC88_IN_SEL_CFG + GPIO input function configuration register + 0x2B4 + 0x20 + 0x0000003C + + + FUNC88_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC88_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG88_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC89_IN_SEL_CFG + GPIO input function configuration register + 0x2B8 + 0x20 + 0x0000003C + + + FUNC89_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC89_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG89_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC90_IN_SEL_CFG + GPIO input function configuration register + 0x2BC + 0x20 + 0x0000003C + + + FUNC90_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC90_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG90_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC91_IN_SEL_CFG + GPIO input function configuration register + 0x2C0 + 0x20 + 0x0000003C + + + FUNC91_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC91_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG91_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC92_IN_SEL_CFG + GPIO input function configuration register + 0x2C4 + 0x20 + 0x0000003C + + + FUNC92_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC92_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG92_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC93_IN_SEL_CFG + GPIO input function configuration register + 0x2C8 + 0x20 + 0x0000003C + + + FUNC93_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC93_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG93_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC94_IN_SEL_CFG + GPIO input function configuration register + 0x2CC + 0x20 + 0x0000003C + + + FUNC94_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC94_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG94_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC95_IN_SEL_CFG + GPIO input function configuration register + 0x2D0 + 0x20 + 0x0000003C + + + FUNC95_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC95_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG95_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC97_IN_SEL_CFG + GPIO input function configuration register + 0x2D8 + 0x20 + 0x0000003C + + + FUNC97_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC97_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG97_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC98_IN_SEL_CFG + GPIO input function configuration register + 0x2DC + 0x20 + 0x0000003C + + + FUNC98_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC98_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG98_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC99_IN_SEL_CFG + GPIO input function configuration register + 0x2E0 + 0x20 + 0x0000003C + + + FUNC99_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC99_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG99_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC100_IN_SEL_CFG + GPIO input function configuration register + 0x2E4 + 0x20 + 0x0000003C + + + FUNC100_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC100_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG100_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC101_IN_SEL_CFG + GPIO input function configuration register + 0x2E8 + 0x20 + 0x0000003C + + + FUNC101_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC101_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG101_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC102_IN_SEL_CFG + GPIO input function configuration register + 0x2EC + 0x20 + 0x0000003C + + + FUNC102_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC102_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG102_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC103_IN_SEL_CFG + GPIO input function configuration register + 0x2F0 + 0x20 + 0x0000003C + + + FUNC103_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC103_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG103_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC104_IN_SEL_CFG + GPIO input function configuration register + 0x2F4 + 0x20 + 0x0000003C + + + FUNC104_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC104_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG104_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC105_IN_SEL_CFG + GPIO input function configuration register + 0x2F8 + 0x20 + 0x0000003C + + + FUNC105_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC105_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG105_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC106_IN_SEL_CFG + GPIO input function configuration register + 0x2FC + 0x20 + 0x0000003C + + + FUNC106_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC106_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG106_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC107_IN_SEL_CFG + GPIO input function configuration register + 0x300 + 0x20 + 0x0000003C + + + FUNC107_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC107_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG107_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC108_IN_SEL_CFG + GPIO input function configuration register + 0x304 + 0x20 + 0x0000003C + + + FUNC108_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC108_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG108_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC109_IN_SEL_CFG + GPIO input function configuration register + 0x308 + 0x20 + 0x0000003C + + + FUNC109_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC109_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG109_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC110_IN_SEL_CFG + GPIO input function configuration register + 0x30C + 0x20 + 0x0000003C + + + FUNC110_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC110_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG110_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC111_IN_SEL_CFG + GPIO input function configuration register + 0x310 + 0x20 + 0x0000003C + + + FUNC111_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC111_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG111_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC112_IN_SEL_CFG + GPIO input function configuration register + 0x314 + 0x20 + 0x0000003C + + + FUNC112_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC112_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG112_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC113_IN_SEL_CFG + GPIO input function configuration register + 0x318 + 0x20 + 0x0000003C + + + FUNC113_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC113_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG113_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC114_IN_SEL_CFG + GPIO input function configuration register + 0x31C + 0x20 + 0x0000003C + + + FUNC114_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC114_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG114_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC115_IN_SEL_CFG + GPIO input function configuration register + 0x320 + 0x20 + 0x0000003C + + + FUNC115_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC115_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG115_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC116_IN_SEL_CFG + GPIO input function configuration register + 0x324 + 0x20 + 0x0000003C + + + FUNC116_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC116_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG116_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC117_IN_SEL_CFG + GPIO input function configuration register + 0x328 + 0x20 + 0x0000003C + + + FUNC117_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC117_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG117_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC118_IN_SEL_CFG + GPIO input function configuration register + 0x32C + 0x20 + 0x0000003C + + + FUNC118_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC118_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG118_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC119_IN_SEL_CFG + GPIO input function configuration register + 0x330 + 0x20 + 0x0000003C + + + FUNC119_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC119_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG119_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC120_IN_SEL_CFG + GPIO input function configuration register + 0x334 + 0x20 + 0x0000003C + + + FUNC120_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC120_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG120_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC121_IN_SEL_CFG + GPIO input function configuration register + 0x338 + 0x20 + 0x0000003C + + + FUNC121_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC121_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG121_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC122_IN_SEL_CFG + GPIO input function configuration register + 0x33C + 0x20 + 0x0000003C + + + FUNC122_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC122_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG122_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC123_IN_SEL_CFG + GPIO input function configuration register + 0x340 + 0x20 + 0x0000003C + + + FUNC123_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC123_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG123_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC124_IN_SEL_CFG + GPIO input function configuration register + 0x344 + 0x20 + 0x0000003C + + + FUNC124_IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + FUNC124_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG124_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 35 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000080 + + + FUNC_OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 8 + read-write + + + FUNC_OUT_INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 + 1 + read-write + + + FUNC_OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + FUNC_OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + DATE + GPIO version register + 0x6FC + 0x20 + 0x02201120 + + + DATE + version register + 0 + 28 + read-write + + + + + + + GPIOSD + Sigma-Delta Modulation + GPIOSD + 0x60004F00 + + 0x0 + 0x7C + registers + + + + 4 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD0_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD0_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 5 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC + 0x20 + + + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02203050 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HINF + Peripheral HINF + HINF + 0x60016000 + + 0x0 + 0x54 + registers + + + + CFG_DATA0 + Configure sdio cis content + 0x0 + 0x20 + 0x00926666 + + + DEVICE_ID_FN1 + configure device id of function1 in cis + 0 + 16 + read-write + + + USER_ID_FN1 + configure user id of function1 in cis + 16 + 16 + read-write + + + + + CFG_DATA1 + SDIO configuration register + 0x4 + 0x20 + 0x00232011 + + + SDIO_ENABLE + Sdio clock enable + 0 + 1 + read-write + + + SDIO_IOREADY1 + sdio function1 io ready signal in cis + 1 + 1 + read-write + + + HIGHSPEED_ENABLE + Highspeed enable in cccr + 2 + 1 + read-write + + + HIGHSPEED_MODE + highspeed mode status in cccr + 3 + 1 + read-only + + + SDIO_CD_ENABLE + sdio card detect enable + 4 + 1 + read-write + + + SDIO_IOREADY2 + sdio function1 io ready signal in cis + 5 + 1 + read-write + + + SDIO_INT_MASK + mask sdio interrupt in cccr, high active + 6 + 1 + read-write + + + IOENABLE2 + ioe2 status in cccr + 7 + 1 + read-only + + + CD_DISABLE + card disable status in cccr + 8 + 1 + read-only + + + FUNC1_EPS + function1 eps status in fbr + 9 + 1 + read-only + + + EMP + empc status in cccr + 10 + 1 + read-only + + + IOENABLE1 + ioe1 status in cccr + 11 + 1 + read-only + + + SDIO_VER + sdio version in cccr + 12 + 12 + read-write + + + FUNC2_EPS + function2 eps status in fbr + 24 + 1 + read-only + + + SDIO20_CONF + [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat in delayed cycles control,0:no delay, 1:delay 1 cycle. +[25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed mode. +[26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when [12]=0,posedge when highspeed mode enable. +[27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. +[28]: sdio data pad pull up enable + 25 + 7 + read-write + + + + + CFG_TIMING + Timing configuration registers + 0x8 + 0x20 + 0x15780812 + + + NCRC + configure Ncrc parameter in sdr50/104 mode, no more than 6. + 0 + 3 + read-write + + + PST_END_CMD_LOW_VALUE + configure cycles to lower cmd after voltage is changed to 1.8V. + 3 + 7 + read-write + + + PST_END_DATA_LOW_VALUE + configure cycles to lower data after voltage is changed to 1.8V. + 10 + 6 + read-write + + + SDCLK_STOP_THRES + Configure the number of cycles of module clk to judge sdclk has stopped + 16 + 11 + read-write + + + SAMPLE_CLK_DIVIDER + module clk divider to sample sdclk + 28 + 4 + read-write + + + + + CFG_UPDATE + update sdio configurations + 0xC + 0x20 + + + CONF_UPDATE + update the timing configurations + 0 + 1 + write-only + + + + + CFG_DATA7 + SDIO configuration register + 0x1C + 0x20 + 0x23820000 + + + PIN_STATE + configure cis addr 318 and 574 + 0 + 8 + read-write + + + CHIP_STATE + configure cis addr 312, 315, 568 and 571 + 8 + 8 + read-write + + + SDIO_RST + soft reset control for sdio module + 16 + 1 + read-write + + + SDIO_IOREADY0 + sdio io ready, high enable + 17 + 1 + read-write + + + SDIO_MEM_PD + sdio memory power down, high active + 18 + 1 + read-write + + + ESDIO_DATA1_INT_EN + enable sdio interrupt on data1 line + 19 + 1 + read-write + + + SDIO_SWITCH_VOLT_SW + control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + 20 + 1 + read-write + + + DDR50_BLK_LEN_FIX_EN + enable block length to be fixed to 512 bytes in ddr50 mode + 21 + 1 + read-write + + + CLK_EN + sdio apb clock for configuration force on control:0-gating,1-force on. + 22 + 1 + read-write + + + SDDR50 + configure if support sdr50 mode in cccr + 23 + 1 + read-write + + + SSDR104 + configure if support sdr104 mode in cccr + 24 + 1 + read-write + + + SSDR50 + configure if support ddr50 mode in cccr + 25 + 1 + read-write + + + SDTD + configure if support driver type D in cccr + 26 + 1 + read-write + + + SDTA + configure if support driver type A in cccr + 27 + 1 + read-write + + + SDTC + configure if support driver type C in cccr + 28 + 1 + read-write + + + SAI + configure if support asynchronous interrupt in cccr + 29 + 1 + read-write + + + SDIO_WAKEUP_CLR + clear sdio_wake_up signal after the chip wakes up + 30 + 1 + write-only + + + + + CIS_CONF_W0 + SDIO cis configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W0 + Configure cis addr 39~36 + 0 + 32 + read-write + + + + + CIS_CONF_W1 + SDIO cis configuration register + 0x24 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W1 + Configure cis addr 43~40 + 0 + 32 + read-write + + + + + CIS_CONF_W2 + SDIO cis configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W2 + Configure cis addr 47~44 + 0 + 32 + read-write + + + + + CIS_CONF_W3 + SDIO cis configuration register + 0x2C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W3 + Configure cis addr 51~48 + 0 + 32 + read-write + + + + + CIS_CONF_W4 + SDIO cis configuration register + 0x30 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W4 + Configure cis addr 55~52 + 0 + 32 + read-write + + + + + CIS_CONF_W5 + SDIO cis configuration register + 0x34 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W5 + Configure cis addr 59~56 + 0 + 32 + read-write + + + + + CIS_CONF_W6 + SDIO cis configuration register + 0x38 + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W6 + Configure cis addr 63~60 + 0 + 32 + read-write + + + + + CIS_CONF_W7 + SDIO cis configuration register + 0x3C + 0x20 + 0xFFFFFFFF + + + CIS_CONF_W7 + Configure cis addr 67~64 + 0 + 32 + read-write + + + + + CFG_DATA16 + SDIO cis configuration register + 0x40 + 0x20 + 0x00927777 + + + DEVICE_ID_FN2 + configure device id of function2 in cis + 0 + 16 + read-write + + + USER_ID_FN2 + configure user id of function2 in cis + 16 + 16 + read-write + + + + + CFG_UHS1_INT_MODE + configure int to start and end ahead of time in uhs1 mode + 0x44 + 0x20 + + + INTOE_END_AHEAD_MODE + intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 0 + 2 + read-write + + + INT_END_AHEAD_MODE + int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 2 + 2 + read-write + + + INTOE_ST_AHEAD_MODE + intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 4 + 2 + read-write + + + INT_ST_AHEAD_MODE + int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + 6 + 2 + read-write + + + + + CONF_STATUS + func0 config0 status + 0x54 + 0x20 + + + FUNC0_CONFIG0 + func0 config0 (addr: 0x20f0 ) status + 0 + 8 + read-only + + + SDR25_ST + sdr25 status + 8 + 1 + read-only + + + SDR50_ST + sdr50 status + 9 + 1 + read-only + + + SDR104_ST + sdr104 status + 10 + 1 + read-only + + + DDR50_ST + ddr50 status + 11 + 1 + read-only + + + TUNE_ST + tune_st fsm status + 12 + 3 + read-only + + + SDIO_SWITCH_VOLT_ST + sdio switch voltage status:0-3.3V, 1-1.8V. + 15 + 1 + read-only + + + SDIO_SWITCH_END + sdio switch voltage ldo ready + 16 + 1 + read-only + + + + + SDIO_SLAVE_ECO_LOW + sdio_slave redundant control registers + 0xA4 + 0x20 + + + RDN_ECO_LOW + redundant registers for sdio_slave + 0 + 32 + read-write + + + + + SDIO_SLAVE_ECO_HIGH + sdio_slave redundant control registers + 0xA8 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + redundant registers for sdio_slave + 0 + 32 + read-write + + + + + SDIO_SLAVE_ECO_CONF + sdio_slave redundant control registers + 0xAC + 0x20 + + + SDIO_SLAVE_RDN_RESULT + redundant registers for sdio_slave + 0 + 1 + read-only + + + SDIO_SLAVE_RDN_ENA + redundant registers for sdio_slave + 1 + 1 + read-write + + + SDIO_SLAVE_SDIO_CLK_RDN_RESULT + redundant registers for sdio_slave + 2 + 1 + read-only + + + SDIO_SLAVE_SDIO_CLK_RDN_ENA + redundant registers for sdio_slave + 3 + 1 + read-write + + + SDIO_SLAVE_SDCLK_PAD_RDN_RESULT + redundant registers for sdio_slave + 4 + 1 + read-only + + + SDIO_SLAVE_SDCLK_PAD_RDN_ENA + redundant registers for sdio_slave + 5 + 1 + read-write + + + + + SDIO_SLAVE_LDO_CONF + sdio slave ldo control register + 0xB0 + 0x20 + 0x00000014 + + + LDO_READY_CTL_IN_EN + control ldo ready signal by sdio slave itself + 0 + 1 + read-write + + + LDO_READY_THRES + configure ldo ready counting threshold value, the actual counting target is 2^(ldo_ready_thres)-1 + 1 + 5 + read-write + + + LDO_READY_IGNORE_EN + ignore ldo ready signal + 6 + 1 + read-write + + + + + SDIO_DATE + ******* Description *********** + 0xFC + 0x20 + 0x02203150 + + + SDIO_DATE + sdio version date. + 0 + 32 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6008D000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + HP_APM + Peripheral HP_APM + HP_APM + 0x60099000 + + 0x0 + 0x114 + registers + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 16 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION4_ADDR_START + Region address register + 0x34 + 0x20 + + + REGION4_ADDR_START + Start address of region4 + 0 + 32 + read-write + + + + + REGION4_ADDR_END + Region address register + 0x38 + 0x20 + 0xFFFFFFFF + + + REGION4_ADDR_END + End address of region4 + 0 + 32 + read-write + + + + + REGION4_PMS_ATTR + Region access authority attribute register + 0x3C + 0x20 + + + REGION4_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION4_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION4_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION4_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION4_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION4_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION4_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION4_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION4_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION5_ADDR_START + Region address register + 0x40 + 0x20 + + + REGION5_ADDR_START + Start address of region5 + 0 + 32 + read-write + + + + + REGION5_ADDR_END + Region address register + 0x44 + 0x20 + 0xFFFFFFFF + + + REGION5_ADDR_END + End address of region5 + 0 + 32 + read-write + + + + + REGION5_PMS_ATTR + Region access authority attribute register + 0x48 + 0x20 + + + REGION5_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION5_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION5_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION5_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION5_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION5_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION5_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION5_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION5_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION6_ADDR_START + Region address register + 0x4C + 0x20 + + + REGION6_ADDR_START + Start address of region6 + 0 + 32 + read-write + + + + + REGION6_ADDR_END + Region address register + 0x50 + 0x20 + 0xFFFFFFFF + + + REGION6_ADDR_END + End address of region6 + 0 + 32 + read-write + + + + + REGION6_PMS_ATTR + Region access authority attribute register + 0x54 + 0x20 + + + REGION6_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION6_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION6_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION6_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION6_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION6_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION6_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION6_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION6_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION7_ADDR_START + Region address register + 0x58 + 0x20 + + + REGION7_ADDR_START + Start address of region7 + 0 + 32 + read-write + + + + + REGION7_ADDR_END + Region address register + 0x5C + 0x20 + 0xFFFFFFFF + + + REGION7_ADDR_END + End address of region7 + 0 + 32 + read-write + + + + + REGION7_PMS_ATTR + Region access authority attribute register + 0x60 + 0x20 + + + REGION7_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION7_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION7_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION7_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION7_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION7_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION7_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION7_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION7_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION8_ADDR_START + Region address register + 0x64 + 0x20 + + + REGION8_ADDR_START + Start address of region8 + 0 + 32 + read-write + + + + + REGION8_ADDR_END + Region address register + 0x68 + 0x20 + 0xFFFFFFFF + + + REGION8_ADDR_END + End address of region8 + 0 + 32 + read-write + + + + + REGION8_PMS_ATTR + Region access authority attribute register + 0x6C + 0x20 + + + REGION8_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION8_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION8_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION8_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION8_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION8_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION8_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION8_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION8_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION9_ADDR_START + Region address register + 0x70 + 0x20 + + + REGION9_ADDR_START + Start address of region9 + 0 + 32 + read-write + + + + + REGION9_ADDR_END + Region address register + 0x74 + 0x20 + 0xFFFFFFFF + + + REGION9_ADDR_END + End address of region9 + 0 + 32 + read-write + + + + + REGION9_PMS_ATTR + Region access authority attribute register + 0x78 + 0x20 + + + REGION9_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION9_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION9_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION9_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION9_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION9_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION9_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION9_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION9_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION10_ADDR_START + Region address register + 0x7C + 0x20 + + + REGION10_ADDR_START + Start address of region10 + 0 + 32 + read-write + + + + + REGION10_ADDR_END + Region address register + 0x80 + 0x20 + 0xFFFFFFFF + + + REGION10_ADDR_END + End address of region10 + 0 + 32 + read-write + + + + + REGION10_PMS_ATTR + Region access authority attribute register + 0x84 + 0x20 + + + REGION10_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION10_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION10_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION10_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION10_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION10_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION10_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION10_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION10_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION11_ADDR_START + Region address register + 0x88 + 0x20 + + + REGION11_ADDR_START + Start address of region11 + 0 + 32 + read-write + + + + + REGION11_ADDR_END + Region address register + 0x8C + 0x20 + 0xFFFFFFFF + + + REGION11_ADDR_END + End address of region11 + 0 + 32 + read-write + + + + + REGION11_PMS_ATTR + Region access authority attribute register + 0x90 + 0x20 + + + REGION11_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION11_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION11_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION11_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION11_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION11_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION11_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION11_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION11_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION12_ADDR_START + Region address register + 0x94 + 0x20 + + + REGION12_ADDR_START + Start address of region12 + 0 + 32 + read-write + + + + + REGION12_ADDR_END + Region address register + 0x98 + 0x20 + 0xFFFFFFFF + + + REGION12_ADDR_END + End address of region12 + 0 + 32 + read-write + + + + + REGION12_PMS_ATTR + Region access authority attribute register + 0x9C + 0x20 + + + REGION12_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION12_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION12_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION12_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION12_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION12_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION12_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION12_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION12_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION13_ADDR_START + Region address register + 0xA0 + 0x20 + + + REGION13_ADDR_START + Start address of region13 + 0 + 32 + read-write + + + + + REGION13_ADDR_END + Region address register + 0xA4 + 0x20 + 0xFFFFFFFF + + + REGION13_ADDR_END + End address of region13 + 0 + 32 + read-write + + + + + REGION13_PMS_ATTR + Region access authority attribute register + 0xA8 + 0x20 + + + REGION13_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION13_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION13_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION13_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION13_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION13_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION13_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION13_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION13_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION14_ADDR_START + Region address register + 0xAC + 0x20 + + + REGION14_ADDR_START + Start address of region14 + 0 + 32 + read-write + + + + + REGION14_ADDR_END + Region address register + 0xB0 + 0x20 + 0xFFFFFFFF + + + REGION14_ADDR_END + End address of region14 + 0 + 32 + read-write + + + + + REGION14_PMS_ATTR + Region access authority attribute register + 0xB4 + 0x20 + + + REGION14_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION14_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION14_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION14_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION14_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION14_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION14_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION14_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION14_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION15_ADDR_START + Region address register + 0xB8 + 0x20 + + + REGION15_ADDR_START + Start address of region15 + 0 + 32 + read-write + + + + + REGION15_ADDR_END + Region address register + 0xBC + 0x20 + 0xFFFFFFFF + + + REGION15_ADDR_END + End address of region15 + 0 + 32 + read-write + + + + + REGION15_PMS_ATTR + Region access authority attribute register + 0xC0 + 0x20 + + + REGION15_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION15_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION15_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION15_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION15_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION15_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION15_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION15_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION15_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x0000000F + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + M1_PMS_FUNC_EN + PMS M1 function enable + 1 + 1 + read-write + + + M2_PMS_FUNC_EN + PMS M2 function enable + 2 + 1 + read-write + + + M3_PMS_FUNC_EN + PMS M3 function enable + 3 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M2_STATUS + M2 status register + 0xE8 + 0x20 + + + M2_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M2_STATUS_CLR + M2 status clear register + 0xEC + 0x20 + + + M2_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M2_EXCEPTION_INFO0 + M2 exception_info0 register + 0xF0 + 0x20 + + + M2_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M2_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M2_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M2_EXCEPTION_INFO1 + M2 exception_info1 register + 0xF4 + 0x20 + + + M2_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M3_STATUS + M3 status register + 0xF8 + 0x20 + + + M3_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M3_STATUS_CLR + M3 status clear register + 0xFC + 0x20 + + + M3_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M3_EXCEPTION_INFO0 + M3 exception_info0 register + 0x100 + 0x20 + + + M3_EXCEPTION_REGION + Exception region + 0 + 16 + read-only + + + M3_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M3_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M3_EXCEPTION_INFO1 + M3 exception_info1 register + 0x104 + 0x20 + + + M3_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0x108 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + M2_APM_INT_EN + APM M2 interrupt enable + 2 + 1 + read-write + + + M3_APM_INT_EN + APM M3 interrupt enable + 3 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0x10C + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0x7FC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + HP_SYS + Peripheral HP_SYS + HP_SYS + 0x60095000 + + 0x0 + 0x5C + registers + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + 0x0 + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + reserved + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + 3 + 1 + read-write + + + + + SRAM_USAGE_CONF + HP memory usage configuration register + 0x4 + 0x20 + + + CACHE_USAGE + reserved + 0 + 1 + read-only + + + SRAM_USAGE + 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + 8 + 4 + read-write + + + MAC_DUMP_ALLOC + Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + 16 + 1 + read-write + + + + + SEC_DPA_CONF + HP anti-DPA security configuration register + 0x8 + 0x20 + + + SEC_DPA_LEVEL + 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + 0 + 2 + read-write + + + SEC_DPA_CFG_SEL + This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + 2 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_CONF + CPU_PERI_TIMEOUT configuration register + 0xC + 0x20 + 0x0002FFFF + + + CPU_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + CPU_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + CPU_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + 17 + 1 + read-write + + + + + CPU_PERI_TIMEOUT_ADDR + CPU_PERI_TIMEOUT_ADDR register + 0x10 + 0x20 + + + CPU_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + CPU_PERI_TIMEOUT_UID + CPU_PERI_TIMEOUT_UID register + 0x14 + 0x20 + + + CPU_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + HP_PERI_TIMEOUT_CONF + HP_PERI_TIMEOUT configuration register + 0x18 + 0x20 + 0x0002FFFF + + + HP_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + HP_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + HP_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + 17 + 1 + read-write + + + + + HP_PERI_TIMEOUT_ADDR + HP_PERI_TIMEOUT_ADDR register + 0x1C + 0x20 + + + HP_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + HP_PERI_TIMEOUT_UID + HP_PERI_TIMEOUT_UID register + 0x20 + 0x20 + + + HP_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + MODEM_PERI_TIMEOUT_CONF + MODEM_PERI_TIMEOUT configuration register + 0x24 + 0x20 + 0x0002FFFF + + + MODEM_PERI_TIMEOUT_THRES + Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain. + 0 + 16 + read-write + + + MODEM_PERI_TIMEOUT_INT_CLEAR + Set this bit as 1 to clear timeout interrupt + 16 + 1 + write-only + + + MODEM_PERI_TIMEOUT_PROTECT_EN + Set this bit as 1 to enable timeout protection for accessing modem registers + 17 + 1 + read-write + + + + + MODEM_PERI_TIMEOUT_ADDR + MODEM_PERI_TIMEOUT_ADDR register + 0x28 + 0x20 + + + MODEM_PERI_TIMEOUT_ADDR + Record the address information of abnormal access + 0 + 32 + read-only + + + + + MODEM_PERI_TIMEOUT_UID + MODEM_PERI_TIMEOUT_UID register + 0x2C + 0x20 + + + MODEM_PERI_TIMEOUT_UID + Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared. + 0 + 7 + read-only + + + + + SDIO_CTRL + SDIO Control configuration register + 0x30 + 0x20 + 0x00000003 + + + DIS_SDIO_PROB + Set this bit as 1 to disable SDIO_PROB function. disable by default. + 0 + 1 + read-write + + + SDIO_WIN_ACCESS_EN + Enable sdio slave to access other peripherals on the chip + 1 + 1 + read-write + + + + + RETENTION_CONF + Retention configuration register + 0x34 + 0x20 + + + RETENTION_DISABLE + Set this bit as 1 to disable retention function. Not disable by default. + 0 + 1 + read-write + + + + + ROM_TABLE_LOCK + Rom-Table lock register + 0x38 + 0x20 + + + ROM_TABLE_LOCK + XXXX + 0 + 1 + read-write + + + + + ROM_TABLE + Rom-Table register + 0x3C + 0x20 + + + ROM_TABLE + XXXX + 0 + 32 + read-write + + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x40 + 0x20 + + + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 + 1 + read-write + + + + + MEM_TEST_CONF + MEM_TEST configuration register + 0x44 + 0x20 + 0x00000020 + + + HP_MEM_WPULSE + This field controls hp system memory WPULSE parameter. + 0 + 3 + read-write + + + HP_MEM_WA + This field controls hp system memory WA parameter. + 3 + 3 + read-write + + + HP_MEM_RA + This field controls hp system memory RA parameter. + 6 + 2 + read-write + + + + + RND_ECO + redcy eco register. + 0x3E0 + 0x20 + + + REDCY_ENA + Only reserved for ECO. + 0 + 1 + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only + + + + + RND_ECO_LOW + redcy eco low register. + 0x3E4 + 0x20 + + + REDCY_LOW + Only reserved for ECO. + 0 + 32 + read-write + + + + + RND_ECO_HIGH + redcy eco high register. + 0x3E8 + 0x20 + 0xFFFFFFFF + + + REDCY_HIGH + Only reserved for ECO. + 0 + 32 + read-write + + + + + CLOCK_GATE + HP-SYSTEM clock gating configure register + 0x3F8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02206110 + + + DATE + HP-SYSTEM date information/ HP-SYSTEM version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60004000 + + 0x0 + 0x90 + registers + + + I2C_EXT0 + 50 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave, 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND0_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + This is the content of command 1. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND1_DONE + When command 1 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + This is the content of command 2. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND2_DONE + When command 2 is done in I2C Master mode, this bit changes to high +Level. + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + This is the content of command 3. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND3_DONE + When command 3 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + This is the content of command 4. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND4_DONE + When command 4 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + This is the content of command 5. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND5_DONE + When command 5 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + This is the content of command 6. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND6_DONE + When command 6 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + This is the content of command 7. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND7_DONE + When command 7 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2S0 + I2S (Inter-IC Sound) Controller + I2S + 0x6000C000 + + 0x0 + 0x60 + registers + + + I2S1 + 41 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02201070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTMTX_CORE0 + Interrupt Core + INTMTX_CORE0 + 0x60010000 + + 0x0 + 0x148 + registers + + + + WIFI_MAC_INTR_MAP + register description + 0x0 + 0x20 + + + WIFI_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_MAC_NMI_MAP + register description + 0x4 + 0x20 + + + WIFI_MAC_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_PWR_INTR_MAP + register description + 0x8 + 0x20 + + + WIFI_PWR_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + WIFI_BB_INTR_MAP + register description + 0xC + 0x20 + + + WIFI_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_MAC_INTR_MAP + register description + 0x10 + 0x20 + + + BT_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_INTR_MAP + register description + 0x14 + 0x20 + + + BT_BB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + register description + 0x18 + 0x20 + + + BT_BB_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + LP_TIMER_INTR_MAP + register description + 0x1C + 0x20 + + + LP_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + COEX_INTR_MAP + register description + 0x20 + 0x20 + + + COEX_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_TIMER_INTR_MAP + register description + 0x24 + 0x20 + + + BLE_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + BLE_SEC_INTR_MAP + register description + 0x28 + 0x20 + + + BLE_SEC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_MST_INTR_MAP + register description + 0x2C + 0x20 + + + I2C_MST_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ZB_MAC_INTR_MAP + register description + 0x30 + 0x20 + + + ZB_MAC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PMU_INTR_MAP + register description + 0x34 + 0x20 + + + PMU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + EFUSE_INTR_MAP + register description + 0x38 + 0x20 + + + EFUSE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_RTC_TIMER_INTR_MAP + register description + 0x3C + 0x20 + + + LP_RTC_TIMER_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_UART_INTR_MAP + register description + 0x40 + 0x20 + + + LP_UART_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_I2C_INTR_MAP + register description + 0x44 + 0x20 + + + LP_I2C_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_WDT_INTR_MAP + register description + 0x48 + 0x20 + + + LP_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_PERI_TIMEOUT_INTR_MAP + register description + 0x4C + 0x20 + + + LP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M0_INTR_MAP + register description + 0x50 + 0x20 + + + LP_APM_M0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM_M1_INTR_MAP + register description + 0x54 + 0x20 + + + LP_APM_M1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + register description + 0x58 + 0x20 + + + CPU_INTR_FROM_CPU_0_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + register description + 0x5C + 0x20 + + + CPU_INTR_FROM_CPU_1_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + register description + 0x60 + 0x20 + + + CPU_INTR_FROM_CPU_2_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + register description + 0x64 + 0x20 + + + CPU_INTR_FROM_CPU_3_MAP + Need add description + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + register description + 0x68 + 0x20 + + + ASSIST_DEBUG_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TRACE_INTR_MAP + register description + 0x6C + 0x20 + + + TRACE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CACHE_INTR_MAP + register description + 0x70 + 0x20 + + + CACHE_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CPU_PERI_TIMEOUT_INTR_MAP + register description + 0x74 + 0x20 + + + CPU_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + register description + 0x78 + 0x20 + + + GPIO_INTERRUPT_PRO_MAP + Need add description + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + register description + 0x7C + 0x20 + + + GPIO_INTERRUPT_PRO_NMI_MAP + Need add description + 0 + 5 + read-write + + + + + PAU_INTR_MAP + register description + 0x80 + 0x20 + + + PAU_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_PERI_TIMEOUT_INTR_MAP + register description + 0x84 + 0x20 + + + HP_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + MODEM_PERI_TIMEOUT_INTR_MAP + register description + 0x88 + 0x20 + + + MODEM_PERI_TIMEOUT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M0_INTR_MAP + register description + 0x8C + 0x20 + + + HP_APM_M0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M1_INTR_MAP + register description + 0x90 + 0x20 + + + HP_APM_M1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M2_INTR_MAP + register description + 0x94 + 0x20 + + + HP_APM_M2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + HP_APM_M3_INTR_MAP + register description + 0x98 + 0x20 + + + HP_APM_M3_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LP_APM0_INTR_MAP + register description + 0x9C + 0x20 + + + LP_APM0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + MSPI_INTR_MAP + register description + 0xA0 + 0x20 + + + MSPI_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2S1_INTR_MAP + register description + 0xA4 + 0x20 + + + I2S1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + register description + 0xA8 + 0x20 + + + UHCI0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UART0_INTR_MAP + register description + 0xAC + 0x20 + + + UART0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + UART1_INTR_MAP + register description + 0xB0 + 0x20 + + + UART1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + LEDC_INTR_MAP + register description + 0xB4 + 0x20 + + + LEDC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CAN0_INTR_MAP + register description + 0xB8 + 0x20 + + + CAN0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + CAN1_INTR_MAP + register description + 0xBC + 0x20 + + + CAN1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + USB_INTR_MAP + register description + 0xC0 + 0x20 + + + USB_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + RMT_INTR_MAP + register description + 0xC4 + 0x20 + + + RMT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + register description + 0xC8 + 0x20 + + + I2C_EXT0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_T0_INTR_MAP + register description + 0xCC + 0x20 + + + TG0_T0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_T1_INTR_MAP + register description + 0xD0 + 0x20 + + + TG0_T1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG0_WDT_INTR_MAP + register description + 0xD4 + 0x20 + + + TG0_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_T0_INTR_MAP + register description + 0xD8 + 0x20 + + + TG1_T0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_T1_INTR_MAP + register description + 0xDC + 0x20 + + + TG1_T1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + TG1_WDT_INTR_MAP + register description + 0xE0 + 0x20 + + + TG1_WDT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INTR_MAP + register description + 0xE4 + 0x20 + + + SYSTIMER_TARGET0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INTR_MAP + register description + 0xE8 + 0x20 + + + SYSTIMER_TARGET1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INTR_MAP + register description + 0xEC + 0x20 + + + SYSTIMER_TARGET2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + APB_ADC_INTR_MAP + register description + 0xF0 + 0x20 + + + APB_ADC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PWM_INTR_MAP + register description + 0xF4 + 0x20 + + + PWM_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + register description + 0xF8 + 0x20 + + + PCNT_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + PARL_IO_INTR_MAP + register description + 0xFC + 0x20 + + + PARL_IO_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + register description + 0x100 + 0x20 + + + SLC0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + register description + 0x104 + 0x20 + + + SLC1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH0_INTR_MAP + register description + 0x108 + 0x20 + + + DMA_IN_CH0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH1_INTR_MAP + register description + 0x10C + 0x20 + + + DMA_IN_CH1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_IN_CH2_INTR_MAP + register description + 0x110 + 0x20 + + + DMA_IN_CH2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INTR_MAP + register description + 0x114 + 0x20 + + + DMA_OUT_CH0_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INTR_MAP + register description + 0x118 + 0x20 + + + DMA_OUT_CH1_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INTR_MAP + register description + 0x11C + 0x20 + + + DMA_OUT_CH2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + GPSPI2_INTR_MAP + register description + 0x120 + 0x20 + + + GPSPI2_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + AES_INTR_MAP + register description + 0x124 + 0x20 + + + AES_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + SHA_INTR_MAP + register description + 0x128 + 0x20 + + + SHA_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + RSA_INTR_MAP + register description + 0x12C + 0x20 + + + RSA_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + ECC_INTR_MAP + register description + 0x130 + 0x20 + + + ECC_INTR_MAP + Need add description + 0 + 5 + read-write + + + + + INT_STATUS_REG_0 + register description + 0x134 + 0x20 + + + INT_STATUS_0 + Need add description + 0 + 32 + read-only + + + + + INT_STATUS_REG_1 + register description + 0x138 + 0x20 + + + INT_STATUS_1 + Need add description + 0 + 32 + read-only + + + + + INT_STATUS_REG_2 + register description + 0x13C + 0x20 + + + INT_STATUS_2 + Need add description + 0 + 32 + read-only + + + + + CLOCK_GATE + register description + 0x140 + 0x20 + 0x00000001 + + + REG_CLK_EN + Need add description + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + register description + 0x7FC + 0x20 + 0x02203110 + + + INTERRUPT_REG_DATE + Need add description + 0 + 28 + read-write + + + + + + + INTPRI + Peripheral INTPRI + INTPRI + 0x600C5000 + + 0x0 + 0xB8 + registers + + + + CORE0_CPU_INT_ENABLE + register description + 0x0 + 0x20 + + + CORE0_CPU_INT_ENABLE + Need add description + 0 + 32 + read-write + + + + + CORE0_CPU_INT_TYPE + register description + 0x4 + 0x20 + + + CORE0_CPU_INT_TYPE + Need add description + 0 + 32 + read-write + + + + + CORE0_CPU_INT_EIP_STATUS + register description + 0x8 + 0x20 + + + CORE0_CPU_INT_EIP_STATUS + Need add description + 0 + 32 + read-only + + + + + CORE0_CPU_INT_PRI_0 + register description + 0xC + 0x20 + + + CORE0_CPU_PRI_0_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_1 + register description + 0x10 + 0x20 + + + CORE0_CPU_PRI_1_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_2 + register description + 0x14 + 0x20 + + + CORE0_CPU_PRI_2_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_3 + register description + 0x18 + 0x20 + + + CORE0_CPU_PRI_3_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_4 + register description + 0x1C + 0x20 + + + CORE0_CPU_PRI_4_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_5 + register description + 0x20 + 0x20 + + + CORE0_CPU_PRI_5_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_6 + register description + 0x24 + 0x20 + + + CORE0_CPU_PRI_6_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_7 + register description + 0x28 + 0x20 + + + CORE0_CPU_PRI_7_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_8 + register description + 0x2C + 0x20 + + + CORE0_CPU_PRI_8_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_9 + register description + 0x30 + 0x20 + + + CORE0_CPU_PRI_9_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_10 + register description + 0x34 + 0x20 + + + CORE0_CPU_PRI_10_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_11 + register description + 0x38 + 0x20 + + + CORE0_CPU_PRI_11_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_12 + register description + 0x3C + 0x20 + + + CORE0_CPU_PRI_12_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_13 + register description + 0x40 + 0x20 + + + CORE0_CPU_PRI_13_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_14 + register description + 0x44 + 0x20 + + + CORE0_CPU_PRI_14_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_15 + register description + 0x48 + 0x20 + + + CORE0_CPU_PRI_15_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_16 + register description + 0x4C + 0x20 + + + CORE0_CPU_PRI_16_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_17 + register description + 0x50 + 0x20 + + + CORE0_CPU_PRI_17_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_18 + register description + 0x54 + 0x20 + + + CORE0_CPU_PRI_18_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_19 + register description + 0x58 + 0x20 + + + CORE0_CPU_PRI_19_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_20 + register description + 0x5C + 0x20 + + + CORE0_CPU_PRI_20_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_21 + register description + 0x60 + 0x20 + + + CORE0_CPU_PRI_21_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_22 + register description + 0x64 + 0x20 + + + CORE0_CPU_PRI_22_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_23 + register description + 0x68 + 0x20 + + + CORE0_CPU_PRI_23_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_24 + register description + 0x6C + 0x20 + + + CORE0_CPU_PRI_24_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_25 + register description + 0x70 + 0x20 + + + CORE0_CPU_PRI_25_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_26 + register description + 0x74 + 0x20 + + + CORE0_CPU_PRI_26_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_27 + register description + 0x78 + 0x20 + + + CORE0_CPU_PRI_27_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_28 + register description + 0x7C + 0x20 + + + CORE0_CPU_PRI_28_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_29 + register description + 0x80 + 0x20 + + + CORE0_CPU_PRI_29_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_30 + register description + 0x84 + 0x20 + + + CORE0_CPU_PRI_30_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_PRI_31 + register description + 0x88 + 0x20 + + + CORE0_CPU_PRI_31_MAP + Need add description + 0 + 4 + read-write + + + + + CORE0_CPU_INT_THRESH + register description + 0x8C + 0x20 + + + CORE0_CPU_INT_THRESH + Need add description + 0 + 8 + read-write + + + + + CPU_INTR_FROM_CPU_0 + register description + 0x90 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + register description + 0x94 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + register description + 0x98 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Need add description + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + register description + 0x9C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Need add description + 0 + 1 + read-write + + + + + DATE + register description + 0xA0 + 0x20 + 0x02201090 + + + DATE + Need add description + 0 + 28 + read-write + + + + + CLOCK_GATE + register description + 0xA4 + 0x20 + 0x00000001 + + + CLK_EN + Need add description + 0 + 1 + read-write + + + + + CORE0_CPU_INT_CLEAR + register description + 0xA8 + 0x20 + + + CORE0_CPU_INT_CLEAR + Need add description + 0 + 32 + read-write + + + + + RND_ECO + redcy eco register. + 0xAC + 0x20 + + + REDCY_ENA + Only reserved for ECO. + 0 + 1 + read-write + + + REDCY_RESULT + Only reserved for ECO. + 1 + 1 + read-only + + + + + RND_ECO_LOW + redcy eco low register. + 0xB0 + 0x20 + + + REDCY_LOW + Only reserved for ECO. + 0 + 32 + read-write + + + + + RND_ECO_HIGH + redcy eco high register. + 0x3FC + 0x20 + 0xFFFFFFFF + + + REDCY_HIGH + Only reserved for ECO. + 0 + 32 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60090000 + + 0x0 + 0x88 + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x00001DEF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 5 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 5 + 5 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 10 + 5 + read-write + + + + + 31 + 0x4 + GPIO%s + IO MUX Configure Register for pad XTAL_32K_P + 0x4 + 0x20 + 0x00000800 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled. 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + 15 + 1 + read-write + + + + + MODEM_DIAG_EN + GPIO MATRIX Configure Register for modem diag + 0xBC + 0x20 + + + MODEM_DIAG_EN + bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix + 0 + 32 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02201060 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60007000 + + 0x0 + 0x154 + registers + + + LEDC + 45 + + + + 6 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + This field is used to select one of timers for channel %s. + +0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN_CH + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV_CH + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP_CH + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM_CH + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN_CH + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET_CH + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + + + 6 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT_CH + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 6 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY_CH + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 25 + read-write + + + + + 6 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START_CH + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 6 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + This register stores the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x01000000 + + + TIMER_DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV_TIMER + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + TIMER_PAUSE + This bit is used to suspend the counter in timer %s. + 23 + 1 + read-write + + + TIMER_RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 24 + 1 + read-write + + + TICK_SEL_TIMER + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 25 + 1 + read-write + + + TIMER_PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + TIMER_CNT + This register stores the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + + + 6 + 0x10 + CH%s_GAMMA_WR + Ledc ch%s gamma ram write register. + 0x100 + 0x20 + + + CH_GAMMA_DUTY_INC + Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. + +1: Increase 0: Decrease. + 0 + 1 + read-write + + + CH_GAMMA_DUTY_CYCLE + Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + 1 + 10 + read-write + + + CH_GAMMA_SCALE + Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + 11 + 10 + read-write + + + CH_GAMMA_DUTY_NUM + Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + 21 + 10 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address register. + 0x104 + 0x20 + + + CH_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address register. + 0x108 + 0x20 + + + CH_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_DATA + Ledc ch%s gamma ram read data register. + 0x10C + 0x20 + + + CH_GAMMA_RD_DATA + Ledc ch%s gamma ram read data. + 0 + 31 + read-only + + + + + 6 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x180 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Ledc ch%s gamma entry num. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Ledc ch%s gamma pause, write 1 to pause. + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Ledc ch%s gamma resume, write 1 to resume. + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x1A0 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Ledc ch0 duty change end event enable register, write 1 to enable this event. + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Ledc ch1 duty change end event enable register, write 1 to enable this event. + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Ledc ch2 duty change end event enable register, write 1 to enable this event. + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Ledc ch3 duty change end event enable register, write 1 to enable this event. + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Ledc ch4 duty change end event enable register, write 1 to enable this event. + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Ledc ch5 duty change end event enable register, write 1 to enable this event. + 5 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + 13 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Ledc timer0 overflow event enable register, write 1 to enable this event. + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Ledc timer1 overflow event enable register, write 1 to enable this event. + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Ledc timer2 overflow event enable register, write 1 to enable this event. + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Ledc timer3 overflow event enable register, write 1 to enable this event. + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Ledc timer0 compare event enable register, write 1 to enable this event. + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Ledc timer1 compare event enable register, write 1 to enable this event. + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Ledc timer2 compare event enable register, write 1 to enable this event. + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Ledc timer3 compare event enable register, write 1 to enable this event. + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Ledc ch0 duty scale update task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Ledc ch1 duty scale update task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Ledc ch2 duty scale update task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Ledc ch3 duty scale update task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Ledc ch4 duty scale update task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Ledc ch5 duty scale update task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x1A4 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Ledc timer0 res update task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Ledc timer1 res update task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Ledc timer2 res update task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Ledc timer3 res update task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Ledc timer0 capture task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Ledc timer1 capture task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Ledc timer2 capture task enable register, write 1 to enable this task. + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Ledc timer3 capture task enable register, write 1 to enable this task. + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Ledc ch0 signal out disable task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Ledc ch1 signal out disable task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Ledc ch2 signal out disable task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Ledc ch3 signal out disable task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Ledc ch4 signal out disable task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Ledc ch5 signal out disable task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + TASK_TIMER0_RST_EN + Ledc timer0 reset task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Ledc timer1 reset task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Ledc timer2 reset task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Ledc timer3 reset task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Ledc timer0 pause resume task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Ledc timer1 pause resume task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Ledc timer2 pause resume task enable register, write 1 to enable this task. + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Ledc timer3 pause resume task enable register, write 1 to enable this task. + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x1A8 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Ledc ch0 gamma restart task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Ledc ch1 gamma restart task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Ledc ch2 gamma restart task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Ledc ch3 gamma restart task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Ledc ch4 gamma restart task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Ledc ch5 gamma restart task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Ledc ch0 gamma pause task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Ledc ch1 gamma pause task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Ledc ch2 gamma pause task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Ledc ch3 gamma pause task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Ledc ch4 gamma pause task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Ledc ch5 gamma pause task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Ledc ch0 gamma resume task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Ledc ch1 gamma resume task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Ledc ch2 gamma resume task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Ledc ch3 gamma resume task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Ledc ch4 gamma resume task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Ledc ch5 gamma resume task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x1B0 + 0x20 + + + TIMER_CMP + This register stores ledc timer%s compare value. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s count value capture register. + 0x1C0 + 0x20 + + + TIMER_CNT_CAP + This register stores ledc timer%s count value. + 0 + 20 + read-only + + + + + CONF + Global ledc configuration register + 0x1F0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 7 + 1 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0x1FC + 0x20 + 0x02111150 + + + LEDC_DATE + This is the version control register. + 0 + 28 + read-write + + + + + + + LPPERI + Peripheral LPPERI + LPPERI + 0x600B2800 + + 0x0 + 0x28 + registers + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7F000000 + + + RNG_CK_EN + need_des + 24 + 1 + read-write + + + OTP_DBG_CK_EN + need_des + 25 + 1 + read-write + + + LP_UART_CK_EN + need_des + 26 + 1 + read-write + + + LP_IO_CK_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_CK_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_CK_EN + need_des + 29 + 1 + read-write + + + EFUSE_CK_EN + need_des + 30 + 1 + read-write + + + LP_CPU_CK_EN + need_des + 31 + 1 + read-write + + + + + RESET_EN + need_des + 0x4 + 0x20 + + + BUS_RESET_EN + need_des + 23 + 1 + write-only + + + OTP_DBG_RESET_EN + need_des + 25 + 1 + read-write + + + LP_UART_RESET_EN + need_des + 26 + 1 + read-write + + + LP_IO_RESET_EN + need_des + 27 + 1 + read-write + + + LP_EXT_I2C_RESET_EN + need_des + 28 + 1 + read-write + + + LP_ANA_I2C_RESET_EN + need_des + 29 + 1 + read-write + + + EFUSE_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_RESET_EN + need_des + 31 + 1 + write-only + + + + + RNG_DATA + need_des + 0x8 + 0x20 + + + RND_DATA + need_des + 0 + 32 + read-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVALIABLE + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT + need_des + 0x10 + 0x20 + 0xBFFFC000 + + + LP_PERI_TIMEOUT_THRES + need_des + 14 + 16 + read-write + + + LP_PERI_TIMEOUT_INT_CLEAR + need_des + 30 + 1 + write-only + + + LP_PERI_TIMEOUT_PROTECT_EN + need_des + 31 + 1 + read-write + + + + + BUS_TIMEOUT_ADDR + need_des + 0x14 + 0x20 + + + LP_PERI_TIMEOUT_ADDR + need_des + 0 + 32 + read-only + + + + + BUS_TIMEOUT_UID + need_des + 0x18 + 0x20 + + + LP_PERI_TIMEOUT_UID + need_des + 0 + 7 + read-only + + + + + MEM_CTRL + need_des + 0x1C + 0x20 + 0x80000000 + + + UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + UART_WAKEUP_FLAG + need_des + 1 + 1 + read-only + + + UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + INTERRUPT_SOURCE + need_des + 0x20 + 0x20 + + + LP_INTERRUPT_SOURCE + BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int + 0 + 6 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206130 + + + LPPERI_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_ANA + Peripheral LP_ANA + LP_ANA + 0x600B2C00 + + 0x0 + 0x34 + registers + + + + BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + CK_GLITCH_CNTL + need_des + 0x8 + 0x20 + + + CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + FIB_ENABLE + need_des + 0xC + 0x20 + 0xFFFFFFFF + + + ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x10 + 0x20 + + + BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x14 + 0x20 + + + BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x18 + 0x20 + + + BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x1C + 0x20 + + + BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x20 + 0x20 + + + BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-only + + + + + LP_INT_ST + need_des + 0x24 + 0x20 + + + BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x28 + 0x20 + + + BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x2C + 0x20 + + + BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02202260 + + + LP_ANA_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON + Peripheral LP_AON + LP_AON + 0x600B1000 + + 0x0 + 0x5C + registers + + + + STORE0 + need_des + 0x0 + 0x20 + + + LP_AON_STORE0 + need_des + 0 + 32 + read-write + + + + + STORE1 + need_des + 0x4 + 0x20 + + + LP_AON_STORE1 + need_des + 0 + 32 + read-write + + + + + STORE2 + need_des + 0x8 + 0x20 + + + LP_AON_STORE2 + need_des + 0 + 32 + read-write + + + + + STORE3 + need_des + 0xC + 0x20 + + + LP_AON_STORE3 + need_des + 0 + 32 + read-write + + + + + STORE4 + need_des + 0x10 + 0x20 + + + LP_AON_STORE4 + need_des + 0 + 32 + read-write + + + + + STORE5 + need_des + 0x14 + 0x20 + + + LP_AON_STORE5 + need_des + 0 + 32 + read-write + + + + + STORE6 + need_des + 0x18 + 0x20 + + + LP_AON_STORE6 + need_des + 0 + 32 + read-write + + + + + STORE7 + need_des + 0x1C + 0x20 + + + LP_AON_STORE7 + need_des + 0 + 32 + read-write + + + + + STORE8 + need_des + 0x20 + 0x20 + + + LP_AON_STORE8 + need_des + 0 + 32 + read-write + + + + + STORE9 + need_des + 0x24 + 0x20 + + + LP_AON_STORE9 + need_des + 0 + 32 + read-write + + + + + GPIO_MUX + need_des + 0x28 + 0x20 + + + SEL + need_des + 0 + 8 + read-write + + + + + GPIO_HOLD0 + need_des + 0x2C + 0x20 + + + GPIO_HOLD0 + need_des + 0 + 32 + read-write + + + + + GPIO_HOLD1 + need_des + 0x30 + 0x20 + + + GPIO_HOLD1 + need_des + 0 + 32 + read-write + + + + + SYS_CFG + need_des + 0x34 + 0x20 + + + FORCE_DOWNLOAD_BOOT + need_des + 30 + 1 + read-write + + + HPSYS_SW_RESET + need_des + 31 + 1 + write-only + + + + + CPUCORE0_CFG + need_des + 0x38 + 0x20 + 0x40000000 + + + CPU_CORE0_SW_STALL + need_des + 0 + 8 + read-write + + + CPU_CORE0_SW_RESET + need_des + 28 + 1 + write-only + + + CPU_CORE0_OCD_HALT_ON_RESET + need_des + 29 + 1 + read-write + + + CPU_CORE0_STAT_VECTOR_SEL + need_des + 30 + 1 + read-write + + + CPU_CORE0_DRESET_MASK + need_des + 31 + 1 + read-write + + + + + IO_MUX + need_des + 0x3C + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + EXT_WAKEUP_CNTL + need_des + 0x40 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 8 + read-only + + + EXT_WAKEUP_STATUS_CLR + need_des + 14 + 1 + write-only + + + EXT_WAKEUP_SEL + need_des + 15 + 8 + read-write + + + EXT_WAKEUP_LV + need_des + 23 + 8 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + USB + need_des + 0x44 + 0x20 + + + RESET_DISABLE + need_des + 31 + 1 + read-write + + + + + LPBUS + need_des + 0x48 + 0x20 + 0xB0200000 + + + FAST_MEM_WPULSE + This field controls fast memory WPULSE parameter. + 16 + 3 + read-write + + + FAST_MEM_WA + This field controls fast memory WA parameter. + 19 + 3 + read-write + + + FAST_MEM_RA + This field controls fast memory RA parameter. + 22 + 2 + read-write + + + FAST_MEM_MUX_FSM_IDLE + need_des + 28 + 1 + read-only + + + FAST_MEM_MUX_SEL_STATUS + need_des + 29 + 1 + read-only + + + FAST_MEM_MUX_SEL_UPDATE + need_des + 30 + 1 + write-only + + + FAST_MEM_MUX_SEL + need_des + 31 + 1 + read-write + + + + + SDIO_ACTIVE + need_des + 0x4C + 0x20 + 0x02800000 + + + SDIO_ACT_DNUM + need_des + 22 + 10 + read-write + + + + + LPCORE + need_des + 0x50 + 0x20 + + + ETM_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + ETM_WAKEUP_FLAG + need_des + 1 + 1 + read-only + + + DISABLE + need_des + 31 + 1 + read-write + + + + + SAR_CCT + need_des + 0x54 + 0x20 + + + SAR2_PWDET_CCT + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02205280 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_APM + Peripheral LP_APM + LP_APM + 0x600B3800 + + 0x0 + 0x64 + registers + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 4 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000003 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + M1_PMS_FUNC_EN + PMS M1 function enable + 1 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + M1_STATUS + M1 status register + 0xD8 + 0x20 + + + M1_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M1_STATUS_CLR + M1 status clear register + 0xDC + 0x20 + + + M1_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M1_EXCEPTION_INFO0 + M1 exception_info0 register + 0xE0 + 0x20 + + + M1_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M1_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M1_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M1_EXCEPTION_INFO1 + M1 exception_info1 register + 0xE4 + 0x20 + + + M1_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xE8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + M1_APM_INT_EN + APM M1 interrupt enable + 1 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xEC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_APM0 + Peripheral LP_APM0 + LP_APM0 + 0x60099800 + + 0x0 + 0x54 + registers + + + + REGION_FILTER_EN + Region filter enable register + 0x0 + 0x20 + 0x00000001 + + + REGION_FILTER_EN + Region filter enable + 0 + 4 + read-write + + + + + REGION0_ADDR_START + Region address register + 0x4 + 0x20 + + + REGION0_ADDR_START + Start address of region0 + 0 + 32 + read-write + + + + + REGION0_ADDR_END + Region address register + 0x8 + 0x20 + 0xFFFFFFFF + + + REGION0_ADDR_END + End address of region0 + 0 + 32 + read-write + + + + + REGION0_PMS_ATTR + Region access authority attribute register + 0xC + 0x20 + + + REGION0_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION0_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION0_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION0_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION0_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION0_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION0_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION0_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION0_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION1_ADDR_START + Region address register + 0x10 + 0x20 + + + REGION1_ADDR_START + Start address of region1 + 0 + 32 + read-write + + + + + REGION1_ADDR_END + Region address register + 0x14 + 0x20 + 0xFFFFFFFF + + + REGION1_ADDR_END + End address of region1 + 0 + 32 + read-write + + + + + REGION1_PMS_ATTR + Region access authority attribute register + 0x18 + 0x20 + + + REGION1_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION1_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION1_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION1_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION1_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION1_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION1_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION1_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION1_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION2_ADDR_START + Region address register + 0x1C + 0x20 + + + REGION2_ADDR_START + Start address of region2 + 0 + 32 + read-write + + + + + REGION2_ADDR_END + Region address register + 0x20 + 0x20 + 0xFFFFFFFF + + + REGION2_ADDR_END + End address of region2 + 0 + 32 + read-write + + + + + REGION2_PMS_ATTR + Region access authority attribute register + 0x24 + 0x20 + + + REGION2_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION2_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION2_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION2_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION2_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION2_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION2_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION2_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION2_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + REGION3_ADDR_START + Region address register + 0x28 + 0x20 + + + REGION3_ADDR_START + Start address of region3 + 0 + 32 + read-write + + + + + REGION3_ADDR_END + Region address register + 0x2C + 0x20 + 0xFFFFFFFF + + + REGION3_ADDR_END + End address of region3 + 0 + 32 + read-write + + + + + REGION3_PMS_ATTR + Region access authority attribute register + 0x30 + 0x20 + + + REGION3_R0_PMS_X + Region execute authority in REE_MODE0 + 0 + 1 + read-write + + + REGION3_R0_PMS_W + Region write authority in REE_MODE0 + 1 + 1 + read-write + + + REGION3_R0_PMS_R + Region read authority in REE_MODE0 + 2 + 1 + read-write + + + REGION3_R1_PMS_X + Region execute authority in REE_MODE1 + 4 + 1 + read-write + + + REGION3_R1_PMS_W + Region write authority in REE_MODE1 + 5 + 1 + read-write + + + REGION3_R1_PMS_R + Region read authority in REE_MODE1 + 6 + 1 + read-write + + + REGION3_R2_PMS_X + Region execute authority in REE_MODE2 + 8 + 1 + read-write + + + REGION3_R2_PMS_W + Region write authority in REE_MODE2 + 9 + 1 + read-write + + + REGION3_R2_PMS_R + Region read authority in REE_MODE2 + 10 + 1 + read-write + + + + + FUNC_CTRL + PMS function control register + 0xC4 + 0x20 + 0x00000001 + + + M0_PMS_FUNC_EN + PMS M0 function enable + 0 + 1 + read-write + + + + + M0_STATUS + M0 status register + 0xC8 + 0x20 + + + M0_EXCEPTION_STATUS + Exception status + 0 + 2 + read-only + + + + + M0_STATUS_CLR + M0 status clear register + 0xCC + 0x20 + + + M0_REGION_STATUS_CLR + Clear exception status + 0 + 1 + write-only + + + + + M0_EXCEPTION_INFO0 + M0 exception_info0 register + 0xD0 + 0x20 + + + M0_EXCEPTION_REGION + Exception region + 0 + 4 + read-only + + + M0_EXCEPTION_MODE + Exception mode + 16 + 2 + read-only + + + M0_EXCEPTION_ID + Exception id information + 18 + 5 + read-only + + + + + M0_EXCEPTION_INFO1 + M0 exception_info1 register + 0xD4 + 0x20 + + + M0_EXCEPTION_ADDR + Exception addr + 0 + 32 + read-only + + + + + INT_EN + APM interrupt enable register + 0xD8 + 0x20 + + + M0_APM_INT_EN + APM M0 interrupt enable + 0 + 1 + read-write + + + + + CLOCK_GATE + clock gating register + 0xDC + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0x7FC + 0x20 + 0x02205240 + + + DATE + reg_date + 0 + 28 + read-write + + + + + + + LP_CLKRST + Peripheral LP_CLKRST + LP_CLKRST + 0x600B0400 + + 0x0 + 0x34 + registers + + + + LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + FAST_CLK_SEL + need_des + 2 + 1 + read-write + + + LP_PERI_DIV_NUM + need_des + 3 + 8 + read-write + + + + + LP_CLK_PO_EN + need_des + 0x4 + 0x20 + 0x000007FF + + + AON_SLOW_OEN + need_des + 0 + 1 + read-write + + + AON_FAST_OEN + need_des + 1 + 1 + read-write + + + SOSC_OEN + need_des + 2 + 1 + read-write + + + FOSC_OEN + need_des + 3 + 1 + read-write + + + OSC32K_OEN + need_des + 4 + 1 + read-write + + + XTAL32K_OEN + need_des + 5 + 1 + read-write + + + CORE_EFUSE_OEN + need_des + 6 + 1 + read-write + + + SLOW_OEN + need_des + 7 + 1 + read-write + + + FAST_OEN + need_des + 8 + 1 + read-write + + + RNG_OEN + need_des + 9 + 1 + read-write + + + LPBUS_OEN + need_des + 10 + 1 + read-write + + + + + LP_CLK_EN + need_des + 0x8 + 0x20 + + + FAST_ORI_GATE + need_des + 31 + 1 + read-write + + + + + LP_RST_EN + need_des + 0xC + 0x20 + + + AON_EFUSE_CORE_RESET_EN + need_des + 28 + 1 + read-write + + + LP_TIMER_RESET_EN + need_des + 29 + 1 + read-write + + + WDT_RESET_EN + need_des + 30 + 1 + read-write + + + ANA_PERI_RESET_EN + need_des + 31 + 1 + read-write + + + + + RESET_CAUSE + need_des + 0x10 + 0x20 + 0x00000020 + + + RESET_CAUSE + need_des + 0 + 5 + read-only + + + CORE0_RESET_FLAG + need_des + 5 + 1 + read-only + + + CORE0_RESET_CAUSE_CLR + need_des + 29 + 1 + write-only + + + CORE0_RESET_FLAG_SET + need_des + 30 + 1 + write-only + + + CORE0_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + CPU_RESET + need_des + 0x14 + 0x20 + 0x04400000 + + + RTC_WDT_CPU_RESET_LENGTH + need_des + 22 + 3 + read-write + + + RTC_WDT_CPU_RESET_EN + need_des + 25 + 1 + read-write + + + CPU_STALL_WAIT + need_des + 26 + 5 + read-write + + + CPU_STALL_EN + need_des + 31 + 1 + read-write + + + + + FOSC_CNTL + need_des + 0x18 + 0x20 + 0x2B000000 + + + FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + RC32K_CNTL + need_des + 0x1C + 0x20 + 0x2B000000 + + + RC32K_DFREQ + need_des + 22 + 10 + read-write + + + + + CLK_TO_HP + need_des + 0x20 + 0x20 + 0xF0000000 + + + ICG_HP_XTAL32K + need_des + 28 + 1 + read-write + + + ICG_HP_SOSC + need_des + 29 + 1 + read-write + + + ICG_HP_OSC32K + need_des + 30 + 1 + read-write + + + ICG_HP_FOSC + need_des + 31 + 1 + read-write + + + + + LPMEM_FORCE + need_des + 0x24 + 0x20 + + + LPMEM_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LPPERI + need_des + 0x28 + 0x20 + + + LP_I2C_CLK_SEL + need_des + 30 + 1 + read-write + + + LP_UART_CLK_SEL + need_des + 31 + 1 + read-write + + + + + XTAL32K + need_des + 0x2C + 0x20 + 0x66C00000 + + + DRES_XTAL32K + need_des + 22 + 3 + read-write + + + DGM_XTAL32K + need_des + 25 + 3 + read-write + + + DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206090 + + + CLKRST_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_I2C0 + Peripheral LP_I2C0 + LP_I2C0 + 0x600B1800 + + 0x0 + 0x88 + registers + + + + I2C_SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + I2C_SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + I2C_SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + I2C_SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + I2C_SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + I2C_RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + I2C_TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + I2C_TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + I2C_RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + I2C_CLK_EN + Reserved + 8 + 1 + read-write + + + I2C_ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + I2C_FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + I2C_CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + + + I2C_SR + Describe I2C work status. + 0x8 + 0x20 + + + I2C_RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + I2C_ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + I2C_BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + I2C_RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 5 + read-only + + + I2C_TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 5 + read-only + + + I2C_SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + I2C_SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + I2C_TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + I2C_TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + I2C_TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + I2C_FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + I2C_RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 4 + read-only + + + I2C_RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 4 + read-only + + + I2C_TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 4 + read-only + + + I2C_TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 4 + read-only + + + + + I2C_FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + I2C_RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + I2C_TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + I2C_NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + I2C_RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + I2C_TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + I2C_FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + I2C_DATA + Rx FIFO read data. + 0x1C + 0x20 + + + I2C_FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-only + + + + + I2C_INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + I2C_RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + I2C_TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + I2C_RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + I2C_END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + I2C_BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + I2C_ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + I2C_MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + I2C_TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + I2C_TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + I2C_TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + I2C_NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + I2C_TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + I2C_RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + I2C_SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + I2C_SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + I2C_DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + I2C_INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + I2C_RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + I2C_TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + I2C_RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + I2C_END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + I2C_BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + I2C_ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + I2C_MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + I2C_TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + I2C_TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + I2C_TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + I2C_NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + I2C_TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + I2C_RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + I2C_SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + I2C_SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + I2C_DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + I2C_INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + I2C_RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + I2C_TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + I2C_RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + I2C_END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + I2C_BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + I2C_ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + I2C_MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + I2C_TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + I2C_TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + I2C_TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + I2C_NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + I2C_TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + I2C_RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + I2C_SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + I2C_SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + I2C_DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + I2C_INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + I2C_RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + I2C_TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + I2C_RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + I2C_END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + I2C_BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + I2C_ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + I2C_MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + I2C_TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + I2C_TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + I2C_TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + I2C_NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + I2C_TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + I2C_RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + I2C_SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + I2C_SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + I2C_DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + I2C_SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + I2C_SCL_HIGH_PERIOD + This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + I2C_SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + I2C_SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + I2C_FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + I2C_SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + I2C_SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + I2C_SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + I2C_SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + I2C_CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + I2C_SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + I2C_SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + I2C_SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + I2C_SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + I2C_SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + I2C_COMD0 + I2C command register 0 + 0x58 + 0x20 + + + I2C_COMMAND0 + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND0_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD1 + I2C command register 1 + 0x5C + 0x20 + + + I2C_COMMAND1 + This is the content of command 1. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND1_DONE + When command 1 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD2 + I2C command register 2 + 0x60 + 0x20 + + + I2C_COMMAND2 + This is the content of command 2. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND2_DONE + When command 2 is done in I2C Master mode, this bit changes to high +Level. + 31 + 1 + read-write + + + + + I2C_COMD3 + I2C command register 3 + 0x64 + 0x20 + + + I2C_COMMAND3 + This is the content of command 3. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND3_DONE + When command 3 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD4 + I2C command register 4 + 0x68 + 0x20 + + + I2C_COMMAND4 + This is the content of command 4. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND4_DONE + When command 4 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + I2C_COMD5 + I2C command register 5 + 0x6C + 0x20 + + + I2C_COMMAND5 + This is the content of command 5. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND5_DONE + When command 5 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_COMD6 + I2C command register 6 + 0x70 + 0x20 + + + I2C_COMMAND6 + This is the content of command 6. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND6_DONE + When command 6 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_COMD7 + I2C command register 7 + 0x74 + 0x20 + + + I2C_COMMAND7 + This is the content of command 7. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + I2C_COMMAND7_DONE + When command 7 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + I2C_SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + I2C_SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + I2C_SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + I2C_SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + I2C_SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + I2C_SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + I2C_SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + I2C_SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + I2C_SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + I2C_DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + I2C_DATE + This is the the version register. + 0 + 32 + read-write + + + + + I2C_TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + I2C_TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + I2C_RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + I2C_RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_I2C_ANA_MST + Peripheral LP_I2C_ANA_MST + LP_I2C_ANA_MST + 0x600B2400 + + 0x0 + 0x1C + registers + + + + I2C0_CTRL + need_des + 0x0 + 0x20 + + + LP_I2C_ANA_MAST_I2C0_CTRL + need_des + 0 + 25 + read-write + + + LP_I2C_ANA_MAST_I2C0_BUSY + need_des + 25 + 1 + read-only + + + + + I2C0_CONF + need_des + 0x4 + 0x20 + 0x07000000 + + + LP_I2C_ANA_MAST_I2C0_CONF + need_des + 0 + 24 + read-write + + + LP_I2C_ANA_MAST_I2C0_STATUS + reserved + 24 + 8 + read-only + + + + + I2C0_DATA + need_des + 0x8 + 0x20 + 0x00000900 + + + LP_I2C_ANA_MAST_I2C0_RDATA + need_des + 0 + 8 + read-only + + + LP_I2C_ANA_MAST_I2C0_CLK_SEL + need_des + 8 + 3 + read-write + + + LP_I2C_ANA_MAST_I2C_MST_SEL + need des + 11 + 1 + read-write + + + + + ANA_CONF1 + need_des + 0xC + 0x20 + + + LP_I2C_ANA_MAST_ANA_CONF1 + need_des + 0 + 24 + read-write + + + + + NOUSE + need_des + 0x10 + 0x20 + + + LP_I2C_ANA_MAST_I2C_MST_NOUSE + need_des + 0 + 32 + read-write + + + + + DEVICE_EN + need_des + 0x14 + 0x20 + + + LP_I2C_ANA_MAST_I2C_DEVICE_EN + need_des + 0 + 12 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02007301 + + + LP_I2C_ANA_MAST_I2C_MAT_DATE + need_des + 0 + 28 + read-write + + + LP_I2C_ANA_MAST_I2C_MAT_CLK_EN + need_des + 28 + 1 + read-write + + + + + + + LP_IO + Peripheral LP_IO + LP_IO + 0x600B2000 + + 0x0 + 0x7C + registers + + + + OUT_DATA + need des + 0x0 + 0x20 + + + LP_GPIO_OUT_DATA + set lp gpio output data + 0 + 8 + read-write + + + + + OUT_DATA_W1TS + need des + 0x4 + 0x20 + + + LP_GPIO_OUT_DATA_W1TS + set one time output data + 0 + 8 + write-only + + + + + OUT_DATA_W1TC + need des + 0x8 + 0x20 + + + LP_GPIO_OUT_DATA_W1TC + clear one time output data + 0 + 8 + write-only + + + + + OUT_ENABLE + need des + 0xC + 0x20 + + + LP_GPIO_ENABLE + set lp gpio output data + 0 + 8 + read-write + + + + + OUT_ENABLE_W1TS + need des + 0x10 + 0x20 + + + LP_GPIO_ENABLE_W1TS + set one time output data + 0 + 8 + write-only + + + + + OUT_ENABLE_W1TC + need des + 0x14 + 0x20 + + + LP_GPIO_ENABLE_W1TC + clear one time output data + 0 + 8 + write-only + + + + + STATUS + need des + 0x18 + 0x20 + + + LP_GPIO_STATUS_INTERRUPT + set lp gpio output data + 0 + 8 + read-write + + + + + STATUS_W1TS + need des + 0x1C + 0x20 + + + LP_GPIO_STATUS_W1TS + set one time output data + 0 + 8 + write-only + + + + + STATUS_W1TC + need des + 0x20 + 0x20 + + + LP_GPIO_STATUS_W1TC + clear one time output data + 0 + 8 + write-only + + + + + IN + need des + 0x24 + 0x20 + + + LP_GPIO_IN_DATA_NEXT + need des + 0 + 8 + read-only + + + + + PIN0 + need des + 0x28 + 0x20 + + + LP_GPIO0_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO0_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO0_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO0_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO0_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO0_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN1 + need des + 0x2C + 0x20 + + + LP_GPIO1_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO1_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO1_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO1_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO1_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO1_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN2 + need des + 0x30 + 0x20 + + + LP_GPIO2_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO2_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO2_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO2_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO2_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO2_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN3 + need des + 0x34 + 0x20 + + + LP_GPIO3_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO3_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO3_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO3_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO3_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO3_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN4 + need des + 0x38 + 0x20 + + + LP_GPIO4_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO4_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO4_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO4_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO4_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO4_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN5 + need des + 0x3C + 0x20 + + + LP_GPIO5_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO5_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO5_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO5_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO5_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO5_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN6 + need des + 0x40 + 0x20 + + + LP_GPIO6_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO6_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO6_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO6_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO6_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO6_FILTER_EN + need des + 11 + 1 + read-write + + + + + PIN7 + need des + 0x44 + 0x20 + + + LP_GPIO7_SYNC_BYPASS + need des + 0 + 2 + read-write + + + LP_GPIO7_PAD_DRIVER + need des + 2 + 1 + read-write + + + LP_GPIO7_EDGE_WAKEUP_CLR + need des + 3 + 1 + write-only + + + LP_GPIO7_INT_TYPE + need des + 7 + 3 + read-write + + + LP_GPIO7_WAKEUP_ENABLE + need des + 10 + 1 + read-write + + + LP_GPIO7_FILTER_EN + need des + 11 + 1 + read-write + + + + + GPIO0 + need des + 0x48 + 0x20 + + + LP_GPIO0_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO0_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO0_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO0_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO0_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO0_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO0_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO0_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO0_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO0_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO0_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO1 + need des + 0x4C + 0x20 + + + LP_GPIO1_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO1_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO1_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO1_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO1_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO1_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO1_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO1_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO1_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO1_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO1_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO2 + need des + 0x50 + 0x20 + + + LP_GPIO2_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO2_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO2_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO2_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO2_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO2_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO2_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO2_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO2_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO2_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO2_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO3 + need des + 0x54 + 0x20 + + + LP_GPIO3_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO3_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO3_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO3_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO3_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO3_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO3_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO3_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO3_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO3_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO3_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO4 + need des + 0x58 + 0x20 + + + LP_GPIO4_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO4_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO4_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO4_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO4_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO4_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO4_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO4_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO4_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO4_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO4_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO5 + need des + 0x5C + 0x20 + + + LP_GPIO5_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO5_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO5_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO5_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO5_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO5_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO5_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO5_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO5_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO5_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO5_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO6 + need des + 0x60 + 0x20 + + + LP_GPIO6_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO6_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO6_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO6_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO6_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO6_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO6_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO6_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO6_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO6_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO6_MCU_SEL + need des + 12 + 3 + read-write + + + + + GPIO7 + need des + 0x64 + 0x20 + + + LP_GPIO7_MCU_OE + need des + 0 + 1 + read-write + + + LP_GPIO7_SLP_SEL + need des + 1 + 1 + read-write + + + LP_GPIO7_MCU_WPD + need des + 2 + 1 + read-write + + + LP_GPIO7_MCU_WPU + need des + 3 + 1 + read-write + + + LP_GPIO7_MCU_IE + need des + 4 + 1 + read-write + + + LP_GPIO7_MCU_DRV + need des + 5 + 2 + read-write + + + LP_GPIO7_FUN_WPD + need des + 7 + 1 + read-write + + + LP_GPIO7_FUN_WPU + need des + 8 + 1 + read-write + + + LP_GPIO7_FUN_IE + need des + 9 + 1 + read-write + + + LP_GPIO7_FUN_DRV + need des + 10 + 2 + read-write + + + LP_GPIO7_MCU_SEL + need des + 12 + 3 + read-write + + + + + STATUS_INTERRUPT + need des + 0x68 + 0x20 + + + LP_GPIO_STATUS_INTERRUPT_NEXT + need des + 0 + 8 + read-only + + + + + DEBUG_SEL0 + need des + 0x6C + 0x20 + + + LP_DEBUG_SEL0 + need des + 0 + 7 + read-write + + + LP_DEBUG_SEL1 + need des + 7 + 7 + read-write + + + LP_DEBUG_SEL2 + need des + 14 + 7 + read-write + + + LP_DEBUG_SEL3 + need des + 21 + 7 + read-write + + + + + DEBUG_SEL1 + need des + 0x70 + 0x20 + + + LP_DEBUG_SEL4 + need des + 0 + 7 + read-write + + + + + LPI2C + need des + 0x74 + 0x20 + 0xC0000000 + + + LP_I2C_SDA_IE + need des + 30 + 1 + read-write + + + LP_I2C_SCL_IE + need des + 31 + 1 + read-write + + + + + DATE + need des + 0x3FC + 0x20 + 0x02202100 + + + LP_IO_DATE + need des + 0 + 31 + read-write + + + CLK_EN + need des + 31 + 1 + read-write + + + + + + + LP_TEE + Peripheral LP_TEE + LP_TEE + 0x600B3400 + + 0x0 + 0x10 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + 0x00000003 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x4 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + FORCE_ACC_HP + need_des + 0x90 + 0x20 + + + LP_AON_FORCE_ACC_HPMEM_EN + need_des + 0 + 1 + read-write + + + + + DATE + Version register + 0xFC + 0x20 + 0x02205270 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + LP_TIMER + Peripheral LP_TIMER + LP_TIMER + 0x600B0C00 + + 0x0 + 0x4C + registers + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-only + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_UART + Peripheral LP_UART + LP_UART + 0x600B1400 + + 0x0 + 0x84 + registers + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + Configuration register 0 + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit to reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02201260 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + LP_WDT + Peripheral LP_WDT + LP_WDT + 0x600B1C00 + + 0x0 + 0x38 + registers + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + FEED + need_des + 0x14 + 0x20 + + + RTC_WDT_FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-only + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-only + + + + + INT_ST + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + MCPWM + Peripheral MCPWM + MCPWM + 0x60014000 + + 0x0 + 0x130 + registers + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER0_PHASE_DIRECTION + Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER1_PHASE_DIRECTION + Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 16 + read-write + + + TIMER2_PHASE_DIRECTION + Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease + 20 + 1 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + GEN0_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN0_TSTMP_A + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN0_TSTMP_B + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + FH0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN1_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN1_TSTMP_A + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN1_TSTMP_B + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier1 function is enabled. When cleared, carrier1 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + FH1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + GEN2_STMP_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-write + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-write + + + + + GEN2_TSTMP_A + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + GEN2_TSTMP_B + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update. + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DT2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in table + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in table + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in table + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in table + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in table + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in table + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in table + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in table + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DT2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DT2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CARRIER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier2 function is enabled. When cleared, carrier2 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the first pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + FH2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle + 22 + 2 + read-write + + + + + FH2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + FH2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + ch0 capture value status register + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + ch1 capture value status register + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + ch2 capture value status register + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + EVT_EN + MCPWM event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + set this bit high to enable timer0 stop event generate + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + set this bit high to enable timer1 stop event generate + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + set this bit high to enable timer2 stop event generate + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + set this bit high to enable timer0 equal zero event generate + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + set this bit high to enable timer1 equal zero event generate + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + set this bit high to enable timer2 equal zero event generate + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + set this bit high to enable timer0 equal period event generate + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + set this bit high to enable timer1 equal period event generate + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + set this bit high to enable timer2 equal period event generate + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + set this bit high to enable PWM generator0 timer equal a event generate + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + set this bit high to enable PWM generator1 timer equal a event generate + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + set this bit high to enable PWM generator2 timer equal a event generate + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + set this bit high to enable PWM generator0 timer equal b event generate + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + set this bit high to enable PWM generator1 timer equal b event generate + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + set this bit high to enable PWM generator2 timer equal b event generate + 14 + 1 + read-write + + + EVT_F0_EN + set this bit high to enable fault0 event generate + 15 + 1 + read-write + + + EVT_F1_EN + set this bit high to enable fault1 event generate + 16 + 1 + read-write + + + EVT_F2_EN + set this bit high to enable fault2 event generate + 17 + 1 + read-write + + + EVT_F0_CLR_EN + set this bit high to enable fault0 clear event generate + 18 + 1 + read-write + + + EVT_F1_CLR_EN + set this bit high to enable fault1 clear event generate + 19 + 1 + read-write + + + EVT_F2_CLR_EN + set this bit high to enable fault2 clear event generate + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + set this bit high to enable cycle by cycle trip0 event generate + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + set this bit high to enable cycle by cycle trip1 event generate + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + set this bit high to enable cycle by cycle trip2 event generate + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + set this bit high to enable one shot trip0 event generate + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + set this bit high to enable one shot trip1 event generate + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + set this bit high to enable one shot trip2 event generate + 26 + 1 + read-write + + + EVT_CAP0_EN + set this bit high to enable capture0 event generate + 27 + 1 + read-write + + + EVT_CAP1_EN + set this bit high to enable capture1 event generate + 28 + 1 + read-write + + + EVT_CAP2_EN + set this bit high to enable capture2 event generate + 29 + 1 + read-write + + + + + TASK_EN + MCPWM task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + set this bit high to enable all PWM generate stop task receive + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + set this bit high to enable timer0 sync task receive + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + set this bit high to enable timer1 sync task receive + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + set this bit high to enable timer2 sync task receive + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + set this bit high to enable timer0 period update task receive + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + set this bit high to enable timer1 period update task receive + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + set this bit high to enable timer2 period update task receive + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + set this bit high to enable one shot trip0 task receive + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + set this bit high to enable one shot trip1 task receive + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + set this bit high to enable one shot trip2 task receive + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + set this bit high to enable one shot trip0 clear task receive + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + set this bit high to enable one shot trip1 clear task receive + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + set this bit high to enable one shot trip2 clear task receive + 18 + 1 + read-write + + + TASK_CAP0_EN + set this bit high to enable capture0 task receive + 19 + 1 + read-write + + + TASK_CAP1_EN + set this bit high to enable capture1 task receive + 20 + 1 + read-write + + + TASK_CAP2_EN + set this bit high to enable capture2 task receive + 21 + 1 + read-write + + + + + CLK + MCPWM APB configuration register + 0x128 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x12C + 0x20 + 0x02201240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + MEM_MONITOR + Peripheral MEM_MONITOR + MEM_MONITOR + 0x60092000 + + 0x0 + 0x30 + registers + + + + LOG_SETTING + log config regsiter + 0x0 + 0x20 + 0x00000080 + + + LOG_ENA + enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA. + 0 + 3 + read-write + + + LOG_MODE + This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor. + 3 + 4 + read-write + + + LOG_MEM_LOOP_ENABLE + Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + 7 + 1 + read-write + + + + + LOG_CHECK_DATA + check data regsiter + 0x4 + 0x20 + + + LOG_CHECK_DATA + The special check data, when write this special data, it will trigger logging. + 0 + 32 + read-write + + + + + LOG_DATA_MASK + check data mask register + 0x8 + 0x20 + + + LOG_DATA_MASK + byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on. + 0 + 4 + read-write + + + + + LOG_MIN + log boundary regsiter + 0xC + 0x20 + + + LOG_MIN + the min address of log range + 0 + 32 + read-write + + + + + LOG_MAX + log boundary regsiter + 0x10 + 0x20 + + + LOG_MAX + the max address of log range + 0 + 32 + read-write + + + + + LOG_MEM_START + log message store range register + 0x14 + 0x20 + + + LOG_MEM_START + the start address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_END + log message store range register + 0x18 + 0x20 + + + LOG_MEM_END + the end address of writing logging message + 0 + 32 + read-write + + + + + LOG_MEM_CURRENT_ADDR + current writing address. + 0x1C + 0x20 + + + LOG_MEM_CURRENT_ADDR + means next writing address + 0 + 32 + read-only + + + + + LOG_MEM_ADDR_UPDATE + writing address update + 0x20 + 0x20 + + + LOG_MEM_ADDR_UPDATE + Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + 0 + 1 + write-only + + + + + LOG_MEM_FULL_FLAG + full flag status register + 0x24 + 0x20 + + + LOG_MEM_FULL_FLAG + 1 means memory write loop at least one time at the range of MEM_START and MEM_END + 0 + 1 + read-only + + + CLR_LOG_MEM_FULL_FLAG + Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + 1 + 1 + write-only + + + + + CLOCK_GATE + clock gate force on register + 0x28 + 0x20 + + + CLK_EN + Set 1 to force on the clk of mem_monitor register + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02202140 + + + DATE + version register + 0 + 28 + read-write + + + + + + + OTP_DEBUG + Peripheral OTP_DEBUG + OTP_DEBUG + 0x600B3C00 + + 0x0 + 0x210 + registers + + + + WR_DIS + Otp debuger block0 data register1. + 0x0 + 0x20 + + + BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W1 + Otp debuger block0 data register2. + 0x4 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W2 + Otp debuger block0 data register3. + 0x8 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W3 + Otp debuger block0 data register4. + 0xC + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W4 + Otp debuger block0 data register5. + 0x10 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP1_W5 + Otp debuger block0 data register6. + 0x14 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W1 + Otp debuger block0 data register7. + 0x18 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W2 + Otp debuger block0 data register8. + 0x1C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W3 + Otp debuger block0 data register9. + 0x20 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W4 + Otp debuger block0 data register10. + 0x24 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP2_W5 + Otp debuger block0 data register11. + 0x28 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W1 + Otp debuger block0 data register12. + 0x2C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W2 + Otp debuger block0 data register13. + 0x30 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W3 + Otp debuger block0 data register14. + 0x34 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W4 + Otp debuger block0 data register15. + 0x38 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP3_W5 + Otp debuger block0 data register16. + 0x3C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W1 + Otp debuger block0 data register17. + 0x40 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W2 + Otp debuger block0 data register18. + 0x44 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W3 + Otp debuger block0 data register19. + 0x48 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W4 + Otp debuger block0 data register20. + 0x4C + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + BLK0_BACKUP4_W5 + Otp debuger block0 data register21. + 0x50 + 0x20 + + + OTP_BEBUG_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + BLK1_W1 + Otp debuger block1 data register1. + 0x54 + 0x20 + + + BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + BLK1_W2 + Otp debuger block1 data register2. + 0x58 + 0x20 + + + BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + BLK1_W3 + Otp debuger block1 data register3. + 0x5C + 0x20 + + + BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + BLK1_W4 + Otp debuger block1 data register4. + 0x60 + 0x20 + + + BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + BLK1_W5 + Otp debuger block1 data register5. + 0x64 + 0x20 + + + BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + BLK1_W6 + Otp debuger block1 data register6. + 0x68 + 0x20 + + + BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + BLK1_W7 + Otp debuger block1 data register7. + 0x6C + 0x20 + + + BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + BLK1_W8 + Otp debuger block1 data register8. + 0x70 + 0x20 + + + BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + BLK1_W9 + Otp debuger block1 data register9. + 0x74 + 0x20 + + + BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + BLK2_W1 + Otp debuger block2 data register1. + 0x78 + 0x20 + + + BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + BLK2_W2 + Otp debuger block2 data register2. + 0x7C + 0x20 + + + BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + BLK2_W3 + Otp debuger block2 data register3. + 0x80 + 0x20 + + + BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + BLK2_W4 + Otp debuger block2 data register4. + 0x84 + 0x20 + + + BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + BLK2_W5 + Otp debuger block2 data register5. + 0x88 + 0x20 + + + BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + BLK2_W6 + Otp debuger block2 data register6. + 0x8C + 0x20 + + + BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + BLK2_W7 + Otp debuger block2 data register7. + 0x90 + 0x20 + + + BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + BLK2_W8 + Otp debuger block2 data register8. + 0x94 + 0x20 + + + BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + BLK2_W9 + Otp debuger block2 data register9. + 0x98 + 0x20 + + + BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + BLK2_W10 + Otp debuger block2 data register10. + 0x9C + 0x20 + + + BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + BLK2_W11 + Otp debuger block2 data register11. + 0xA0 + 0x20 + + + BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + BLK3_W1 + Otp debuger block3 data register1. + 0xA4 + 0x20 + + + BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + BLK3_W2 + Otp debuger block3 data register2. + 0xA8 + 0x20 + + + BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + BLK3_W3 + Otp debuger block3 data register3. + 0xAC + 0x20 + + + BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + BLK3_W4 + Otp debuger block3 data register4. + 0xB0 + 0x20 + + + BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + BLK3_W5 + Otp debuger block3 data register5. + 0xB4 + 0x20 + + + BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + BLK3_W6 + Otp debuger block3 data register6. + 0xB8 + 0x20 + + + BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + BLK3_W7 + Otp debuger block3 data register7. + 0xBC + 0x20 + + + BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + BLK3_W8 + Otp debuger block3 data register8. + 0xC0 + 0x20 + + + BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + BLK3_W9 + Otp debuger block3 data register9. + 0xC4 + 0x20 + + + BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + BLK3_W10 + Otp debuger block3 data register10. + 0xC8 + 0x20 + + + BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + BLK3_W11 + Otp debuger block3 data register11. + 0xCC + 0x20 + + + BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + BLK4_W1 + Otp debuger block4 data register1. + 0xD0 + 0x20 + + + BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + BLK4_W2 + Otp debuger block4 data register2. + 0xD4 + 0x20 + + + BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + BLK4_W3 + Otp debuger block4 data register3. + 0xD8 + 0x20 + + + BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + BLK4_W4 + Otp debuger block4 data register4. + 0xDC + 0x20 + + + BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + BLK4_W5 + Otp debuger block4 data register5. + 0xE0 + 0x20 + + + BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + BLK4_W6 + Otp debuger block4 data register6. + 0xE4 + 0x20 + + + BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + BLK4_W7 + Otp debuger block4 data register7. + 0xE8 + 0x20 + + + BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + BLK4_W8 + Otp debuger block4 data register8. + 0xEC + 0x20 + + + BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + BLK4_W9 + Otp debuger block4 data register9. + 0xF0 + 0x20 + + + BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + BLK4_W10 + Otp debuger block4 data registe10. + 0xF4 + 0x20 + + + BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + BLK4_W11 + Otp debuger block4 data register11. + 0xF8 + 0x20 + + + BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + BLK5_W1 + Otp debuger block5 data register1. + 0xFC + 0x20 + + + BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + BLK5_W2 + Otp debuger block5 data register2. + 0x100 + 0x20 + + + BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + BLK5_W3 + Otp debuger block5 data register3. + 0x104 + 0x20 + + + BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + BLK5_W4 + Otp debuger block5 data register4. + 0x108 + 0x20 + + + BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + BLK5_W5 + Otp debuger block5 data register5. + 0x10C + 0x20 + + + BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + BLK5_W6 + Otp debuger block5 data register6. + 0x110 + 0x20 + + + BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + BLK5_W7 + Otp debuger block5 data register7. + 0x114 + 0x20 + + + BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + BLK5_W8 + Otp debuger block5 data register8. + 0x118 + 0x20 + + + BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + BLK5_W9 + Otp debuger block5 data register9. + 0x11C + 0x20 + + + BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + BLK5_W10 + Otp debuger block5 data register10. + 0x120 + 0x20 + + + BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + BLK5_W11 + Otp debuger block5 data register11. + 0x124 + 0x20 + + + BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + BLK6_W1 + Otp debuger block6 data register1. + 0x128 + 0x20 + + + BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + BLK6_W2 + Otp debuger block6 data register2. + 0x12C + 0x20 + + + BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + BLK6_W3 + Otp debuger block6 data register3. + 0x130 + 0x20 + + + BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + BLK6_W4 + Otp debuger block6 data register4. + 0x134 + 0x20 + + + BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + BLK6_W5 + Otp debuger block6 data register5. + 0x138 + 0x20 + + + BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + BLK6_W6 + Otp debuger block6 data register6. + 0x13C + 0x20 + + + BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + BLK6_W7 + Otp debuger block6 data register7. + 0x140 + 0x20 + + + BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + BLK6_W8 + Otp debuger block6 data register8. + 0x144 + 0x20 + + + BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + BLK6_W9 + Otp debuger block6 data register9. + 0x148 + 0x20 + + + BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + BLK6_W10 + Otp debuger block6 data register10. + 0x14C + 0x20 + + + BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + BLK6_W11 + Otp debuger block6 data register11. + 0x150 + 0x20 + + + BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + BLK7_W1 + Otp debuger block7 data register1. + 0x154 + 0x20 + + + BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + BLK7_W2 + Otp debuger block7 data register2. + 0x158 + 0x20 + + + BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + BLK7_W3 + Otp debuger block7 data register3. + 0x15C + 0x20 + + + BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + BLK7_W4 + Otp debuger block7 data register4. + 0x160 + 0x20 + + + BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + BLK7_W5 + Otp debuger block7 data register5. + 0x164 + 0x20 + + + BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + BLK7_W6 + Otp debuger block7 data register6. + 0x168 + 0x20 + + + BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + BLK7_W7 + Otp debuger block7 data register7. + 0x16C + 0x20 + + + BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + BLK7_W8 + Otp debuger block7 data register8. + 0x170 + 0x20 + + + BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + BLK7_W9 + Otp debuger block7 data register9. + 0x174 + 0x20 + + + BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + BLK7_W10 + Otp debuger block7 data register10. + 0x178 + 0x20 + + + BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + BLK7_W11 + Otp debuger block7 data register11. + 0x17C + 0x20 + + + BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + BLK8_W1 + Otp debuger block8 data register1. + 0x180 + 0x20 + + + BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + BLK8_W2 + Otp debuger block8 data register2. + 0x184 + 0x20 + + + BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + BLK8_W3 + Otp debuger block8 data register3. + 0x188 + 0x20 + + + BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + BLK8_W4 + Otp debuger block8 data register4. + 0x18C + 0x20 + + + BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + BLK8_W5 + Otp debuger block8 data register5. + 0x190 + 0x20 + + + BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + BLK8_W6 + Otp debuger block8 data register6. + 0x194 + 0x20 + + + BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + BLK8_W7 + Otp debuger block8 data register7. + 0x198 + 0x20 + + + BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + BLK8_W8 + Otp debuger block8 data register8. + 0x19C + 0x20 + + + BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + BLK8_W9 + Otp debuger block8 data register9. + 0x1A0 + 0x20 + + + BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + BLK8_W10 + Otp debuger block8 data register10. + 0x1A4 + 0x20 + + + BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + BLK8_W11 + Otp debuger block8 data register11. + 0x1A8 + 0x20 + + + BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + BLK9_W1 + Otp debuger block9 data register1. + 0x1AC + 0x20 + + + BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + BLK9_W2 + Otp debuger block9 data register2. + 0x1B0 + 0x20 + + + BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + BLK9_W3 + Otp debuger block9 data register3. + 0x1B4 + 0x20 + + + BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + BLK9_W4 + Otp debuger block9 data register4. + 0x1B8 + 0x20 + + + BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + BLK9_W5 + Otp debuger block9 data register5. + 0x1BC + 0x20 + + + BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + BLK9_W6 + Otp debuger block9 data register6. + 0x1C0 + 0x20 + + + BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + BLK9_W7 + Otp debuger block9 data register7. + 0x1C4 + 0x20 + + + BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + BLK9_W8 + Otp debuger block9 data register8. + 0x1C8 + 0x20 + + + BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + BLK9_W9 + Otp debuger block9 data register9. + 0x1CC + 0x20 + + + BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + BLK9_W10 + Otp debuger block9 data register10. + 0x1D0 + 0x20 + + + BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + BLK9_W11 + Otp debuger block9 data register11. + 0x1D4 + 0x20 + + + BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + BLK10_W1 + Otp debuger block10 data register1. + 0x1D8 + 0x20 + + + BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + BLK10_W2 + Otp debuger block10 data register2. + 0x1DC + 0x20 + + + BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + BLK10_W3 + Otp debuger block10 data register3. + 0x1E0 + 0x20 + + + BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + BLK10_W4 + Otp debuger block10 data register4. + 0x1E4 + 0x20 + + + BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + BLK10_W5 + Otp debuger block10 data register5. + 0x1E8 + 0x20 + + + BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + BLK10_W6 + Otp debuger block10 data register6. + 0x1EC + 0x20 + + + BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + BLK10_W7 + Otp debuger block10 data register7. + 0x1F0 + 0x20 + + + BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + BLK10_W8 + Otp debuger block10 data register8. + 0x1F4 + 0x20 + + + BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + BLK10_W9 + Otp debuger block10 data register9. + 0x1F8 + 0x20 + + + BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + BLK10_W10 + Otp debuger block10 data register10. + 0x1FC + 0x20 + + + BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + BLK10_W11 + Otp debuger block10 data register11. + 0x200 + 0x20 + + + BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + CLK + Otp debuger clk_en configuration register. + 0x204 + 0x20 + + + EN + Force clock on for this register file. + 0 + 1 + read-write + + + + + APB2OTP_EN + Otp_debuger apb2otp enable configuration register. + 0x208 + 0x20 + + + APB2OTP_EN + Debug mode enable signal. + 0 + 1 + read-write + + + + + DATE + eFuse version register. + 0x20C + 0x20 + 0x20211028 + + + DATE + Stores otp_debug version. + 0 + 28 + read-write + + + + + + + PARL_IO + Peripheral PARL_IO + PARL_IO + 0x60015000 + + 0x0 + 0x2C + registers + + + PARL_IO + 63 + + + + RX_CFG0 + Parallel RX module configuration register0. + 0x0 + 0x20 + + + RX_EOF_GEN_SEL + Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal. + 0 + 1 + read-write + + + RX_START + Write 1 to start rx global data sampling. + 1 + 1 + read-write + + + RX_DATA_BYTELEN + Configures rx receieved data byte length. + 2 + 16 + read-write + + + RX_SW_EN + Write 1 to enable software data sampling. + 18 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Pulse submode selection. +0000: positive pulse start(data bit included) && positive pulse end(data bit included) +0001: positive pulse start(data bit included) && positive pulse end (data bit excluded) +0010: positive pulse start(data bit excluded) && positive pulse end (data bit included) +0011: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +0100: positive pulse start(data bit included) && length end +0101: positive pulse start(data bit excluded) && length end +0110: negative pulse start(data bit included) && negative pulse end(data bit included) +0111: negative pulse start(data bit included) && negative pulse end (data bit excluded) +1000: negative pulse start(data bit excluded) && negative pulse end (data bit included) +1001: negative pulse start(data bit excluded) && negative pulse end (data bit excluded) +1010: negative pulse start(data bit included) && length end +1011: negative pulse start(data bit excluded) && length end + 19 + 4 + read-write + + + RX_LEVEL_SUBMODE_SEL + Write 0 to sample data at high level of external enable signal. Write 1 to sample data at low level of external enable signal. + 23 + 1 + read-write + + + RX_SMP_MODE_SEL + Rx data sampling mode selection. +000: external level enable mode +001: external pulse enable mode +010: internal software enable mode + 24 + 2 + read-write + + + RX_CLK_EDGE_SEL + Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable sampling data on the falling edge of rx clock. + 26 + 1 + read-write + + + RX_BIT_PACK_ORDER + Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to pack bits into 1byte from LSB when data bus width is 4/2/1 bits. + 27 + 1 + read-write + + + RX_BUS_WID_SEL + Rx data bus width selection. +100: bus width is 1 bit +011: bus width is 2 bits +010: bus width is 4 bits +001: bus width is 8 bits +000: bus width is 16 bits + 28 + 3 + read-write + + + RX_FIFO_SRST + Write 1 to enable soft reset of async fifo in rx module. + 31 + 1 + read-write + + + + + RX_CFG1 + Parallel RX module configuration register1. + 0x4 + 0x20 + 0x0FFFF008 + + + RX_REG_UPDATE + Write 1 to update rx register configuration signals. + 2 + 1 + write-only + + + RX_TIMEOUT_EN + Write 1 to enable timeout count to generate error eof. + 3 + 1 + read-write + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from 16 data lines. + 12 + 4 + read-write + + + RX_TIMEOUT_THRESHOLD + Configures rx threshold of timeout counter. + 16 + 16 + read-write + + + + + TX_CFG0 + Parallel TX module configuration register0. + 0x8 + 0x20 + + + TX_BYTELEN + Configures tx sending data byte length. + 2 + 16 + read-write + + + TX_GATING_EN + Write 1 to enable output tx clock gating. + 18 + 1 + read-write + + + TX_START + Write 1 to start tx global data output. + 19 + 1 + read-write + + + TX_HW_VALID_EN + Write 1 to enable tx hardware data valid signal. + 20 + 1 + read-write + + + TX_SMP_EDGE_SEL + Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable sampling data on the falling edge of tx clock. + 25 + 1 + read-write + + + TX_BIT_UNPACK_ORDER + Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. + 26 + 1 + read-write + + + TX_BUS_WID_SEL + Tx data bus width selection. +100: bus width is 1 bit +011: bus width is 2 bits +010: bus width is 4 bits +001: bus width is 8 bits +000: bus width is 16 bits + 27 + 3 + read-write + + + TX_FIFO_SRST + Write 1 to enable soft reset of async fifo in tx module. + 30 + 1 + read-write + + + + + TX_CFG1 + Parallel TX module configuration register1. + 0xC + 0x20 + + + TX_IDLE_VALUE + Configures data value on tx bus when IDLE state. + 16 + 16 + read-write + + + + + ST + Parallel IO module status register0. + 0x10 + 0x20 + + + TX_READY + Represents the status that tx is ready. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x14 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Write 1 to enable TX_FIFO_REMPTY_INTR. + 0 + 1 + read-write + + + RX_FIFO_WFULL_INT_ENA + Write 1 to enable RX_FIFO_WFULL_INTR. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Write 1 to enable TX_EOF_INTR. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x18 + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INTR. + 0 + 1 + read-only + + + RX_FIFO_WFULL_INT_RAW + The raw interrupt status of RX_FIFO_WFULL_INTR. + 1 + 1 + read-only + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INTR. + 2 + 1 + read-only + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x1C + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INTR. + 0 + 1 + read-only + + + RX_FIFO_WFULL_INT_ST + The masked interrupt status of RX_FIFO_WFULL_INTR. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INTR. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x20 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Write 1 to clear TX_FIFO_REMPTY_INTR. + 0 + 1 + write-only + + + RX_FIFO_WFULL_INT_CLR + Write 1 to clear RX_FIFO_WFULL_INTR. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Write 1 to clear TX_EOF_INTR. + 2 + 1 + write-only + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02202240 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + Peripheral PAU + PAU + 0x60093000 + + 0x0 + 0x4C + registers + + + PAU + 32 + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + RETENTION_LINK_BASE + retention dma link base + 0x30 + 0x20 + + + LINK_BASE_ADDR + retention dma link base + 0 + 27 + read-write + + + + + RETENTION_CFG + retention_cfg + 0x34 + 0x20 + 0xFFFFFFFF + + + RET_INV_CFG + retention inv scan out + 0 + 32 + read-write + + + + + INT_ENA + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-only + + + ERROR_INT_RAW + error flag + 1 + 1 + read-only + + + + + INT_CLR + Read only register for error and done + 0x40 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x44 + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Counter + PCNT + 0x60012000 + + 0x0 + 0x68 + registers + + + PCNT + 62 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PCR + Peripheral PCR + PCR + 0x60096000 + + 0x0 + 0x14C + registers + + + + UART0_CONF + UART0 configuration register + 0x0 + 0x20 + 0x00000001 + + + UART0_CLK_EN + Set 1 to enable uart0 apb clock + 0 + 1 + read-write + + + UART0_RST_EN + Set 0 to reset uart0 module + 1 + 1 + read-write + + + + + UART0_SCLK_CONF + UART0_SCLK configuration register + 0x4 + 0x20 + 0x00700000 + + + UART0_SCLK_DIV_A + The denominator of the frequency divider factor of the uart0 function clock. + 0 + 6 + read-write + + + UART0_SCLK_DIV_B + The numerator of the frequency divider factor of the uart0 function clock. + 6 + 6 + read-write + + + UART0_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart0 function clock. + 12 + 8 + read-write + + + UART0_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART0_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART0_PD_CTRL + UART0 power control register + 0x8 + 0x20 + 0x00000002 + + + UART0_MEM_FORCE_PU + Set this bit to force power down UART0 memory. + 1 + 1 + read-write + + + UART0_MEM_FORCE_PD + Set this bit to force power up UART0 memory. + 2 + 1 + read-write + + + + + UART1_CONF + UART1 configuration register + 0xC + 0x20 + 0x00000001 + + + UART1_CLK_EN + Set 1 to enable uart1 apb clock + 0 + 1 + read-write + + + UART1_RST_EN + Set 0 to reset uart1 module + 1 + 1 + read-write + + + + + UART1_SCLK_CONF + UART1_SCLK configuration register + 0x10 + 0x20 + 0x00700000 + + + UART1_SCLK_DIV_A + The denominator of the frequency divider factor of the uart1 function clock. + 0 + 6 + read-write + + + UART1_SCLK_DIV_B + The numerator of the frequency divider factor of the uart1 function clock. + 6 + 6 + read-write + + + UART1_SCLK_DIV_NUM + The integral part of the frequency divider factor of the uart1 function clock. + 12 + 8 + read-write + + + UART1_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + UART1_SCLK_EN + Set 1 to enable uart0 function clock + 22 + 1 + read-write + + + + + UART1_PD_CTRL + UART1 power control register + 0x14 + 0x20 + 0x00000002 + + + UART1_MEM_FORCE_PU + Set this bit to force power down UART1 memory. + 1 + 1 + read-write + + + UART1_MEM_FORCE_PD + Set this bit to force power up UART1 memory. + 2 + 1 + read-write + + + + + MSPI_CONF + MSPI configuration register + 0x18 + 0x20 + 0x00000005 + + + MSPI_CLK_EN + Set 1 to enable mspi clock, include mspi pll clock + 0 + 1 + read-write + + + MSPI_RST_EN + Set 0 to reset mspi module + 1 + 1 + read-write + + + MSPI_PLL_CLK_EN + Set 1 to enable mspi pll clock + 2 + 1 + read-write + + + + + MSPI_CLK_CONF + MSPI_CLK configuration register + 0x1C + 0x20 + 0x00000300 + + + MSPI_FAST_LS_DIV_NUM + Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-write + + + MSPI_FAST_HS_DIV_NUM + Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a high-speed clock-source such as SPLL. + 8 + 8 + read-write + + + + + I2C_CONF + I2C configuration register + 0x20 + 0x20 + 0x00000001 + + + I2C_CLK_EN + Set 1 to enable i2c apb clock + 0 + 1 + read-write + + + I2C_RST_EN + Set 0 to reset i2c module + 1 + 1 + read-write + + + + + I2C_SCLK_CONF + I2C_SCLK configuration register + 0x24 + 0x20 + 0x00400000 + + + I2C_SCLK_DIV_A + The denominator of the frequency divider factor of the i2c function clock. + 0 + 6 + read-write + + + I2C_SCLK_DIV_B + The numerator of the frequency divider factor of the i2c function clock. + 6 + 6 + read-write + + + I2C_SCLK_DIV_NUM + The integral part of the frequency divider factor of the i2c function clock. + 12 + 8 + read-write + + + I2C_SCLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + I2C_SCLK_EN + Set 1 to enable i2c function clock + 22 + 1 + read-write + + + + + UHCI_CONF + UHCI configuration register + 0x28 + 0x20 + 0x00000001 + + + UHCI_CLK_EN + Set 1 to enable uhci clock + 0 + 1 + read-write + + + UHCI_RST_EN + Set 0 to reset uhci module + 1 + 1 + read-write + + + + + RMT_CONF + RMT configuration register + 0x2C + 0x20 + 0x00000001 + + + RMT_CLK_EN + Set 1 to enable rmt apb clock + 0 + 1 + read-write + + + RMT_RST_EN + Set 0 to reset rmt module + 1 + 1 + read-write + + + + + RMT_SCLK_CONF + RMT_SCLK configuration register + 0x30 + 0x20 + 0x00501000 + + + RMT_SCLK_DIV_A + The denominator of the frequency divider factor of the rmt function clock. + 0 + 6 + read-write + + + RMT_SCLK_DIV_B + The numerator of the frequency divider factor of the rmt function clock. + 6 + 6 + read-write + + + RMT_SCLK_DIV_NUM + The integral part of the frequency divider factor of the rmt function clock. + 12 + 8 + read-write + + + RMT_SCLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL. + 20 + 2 + read-write + + + RMT_SCLK_EN + Set 1 to enable rmt function clock + 22 + 1 + read-write + + + + + LEDC_CONF + LEDC configuration register + 0x34 + 0x20 + 0x00000001 + + + LEDC_CLK_EN + Set 1 to enable ledc apb clock + 0 + 1 + read-write + + + LEDC_RST_EN + Set 0 to reset ledc module + 1 + 1 + read-write + + + + + LEDC_SCLK_CONF + LEDC_SCLK configuration register + 0x38 + 0x20 + 0x00400000 + + + LEDC_SCLK_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL. + 20 + 2 + read-write + + + LEDC_SCLK_EN + Set 1 to enable ledc function clock + 22 + 1 + read-write + + + + + TIMERGROUP0_CONF + TIMERGROUP0 configuration register + 0x3C + 0x20 + 0x00000001 + + + TG0_CLK_EN + Set 1 to enable timer_group0 apb clock + 0 + 1 + read-write + + + TG0_RST_EN + Set 0 to reset timer_group0 module + 1 + 1 + read-write + + + + + TIMERGROUP0_TIMER_CLK_CONF + TIMERGROUP0_TIMER_CLK configuration register + 0x40 + 0x20 + 0x00400000 + + + TG0_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_TIMER_CLK_EN + Set 1 to enable timer_group0 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP0_WDT_CLK_CONF + TIMERGROUP0_WDT_CLK configuration register + 0x44 + 0x20 + 0x00400000 + + + TG0_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG0_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + TIMERGROUP1_CONF + TIMERGROUP1 configuration register + 0x48 + 0x20 + 0x00000001 + + + TG1_CLK_EN + Set 1 to enable timer_group1 apb clock + 0 + 1 + read-write + + + TG1_RST_EN + Set 0 to reset timer_group1 module + 1 + 1 + read-write + + + + + TIMERGROUP1_TIMER_CLK_CONF + TIMERGROUP1_TIMER_CLK configuration register + 0x4C + 0x20 + 0x00400000 + + + TG1_TIMER_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_TIMER_CLK_EN + Set 1 to enable timer_group1 timer clock + 22 + 1 + read-write + + + + + TIMERGROUP1_WDT_CLK_CONF + TIMERGROUP1_WDT_CLK configuration register + 0x50 + 0x20 + 0x00400000 + + + TG1_WDT_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + TG1_WDT_CLK_EN + Set 1 to enable timer_group0 wdt clock + 22 + 1 + read-write + + + + + SYSTIMER_CONF + SYSTIMER configuration register + 0x54 + 0x20 + 0x00000001 + + + SYSTIMER_CLK_EN + Set 1 to enable systimer apb clock + 0 + 1 + read-write + + + SYSTIMER_RST_EN + Set 0 to reset systimer module + 1 + 1 + read-write + + + + + SYSTIMER_FUNC_CLK_CONF + SYSTIMER_FUNC_CLK configuration register + 0x58 + 0x20 + 0x00400000 + + + SYSTIMER_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + SYSTIMER_FUNC_CLK_EN + Set 1 to enable systimer function clock + 22 + 1 + read-write + + + + + TWAI0_CONF + TWAI0 configuration register + 0x5C + 0x20 + 0x00000001 + + + TWAI0_CLK_EN + Set 1 to enable twai0 apb clock + 0 + 1 + read-write + + + TWAI0_RST_EN + Set 0 to reset twai0 module + 1 + 1 + read-write + + + + + TWAI0_FUNC_CLK_CONF + TWAI0_FUNC_CLK configuration register + 0x60 + 0x20 + 0x00400000 + + + TWAI0_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + TWAI0_FUNC_CLK_EN + Set 1 to enable twai0 function clock + 22 + 1 + read-write + + + + + TWAI1_CONF + TWAI1 configuration register + 0x64 + 0x20 + 0x00000001 + + + TWAI1_CLK_EN + Set 1 to enable twai1 apb clock + 0 + 1 + read-write + + + TWAI1_RST_EN + Set 0 to reset twai1 module + 1 + 1 + read-write + + + + + TWAI1_FUNC_CLK_CONF + TWAI1_FUNC_CLK configuration register + 0x68 + 0x20 + 0x00400000 + + + TWAI1_FUNC_CLK_SEL + set this field to select clock-source. 0(default): XTAL, 1: FOSC. + 20 + 1 + read-write + + + TWAI1_FUNC_CLK_EN + Set 1 to enable twai1 function clock + 22 + 1 + read-write + + + + + I2S_CONF + I2S configuration register + 0x6C + 0x20 + 0x00000001 + + + I2S_CLK_EN + Set 1 to enable i2s apb clock + 0 + 1 + read-write + + + I2S_RST_EN + Set 0 to reset i2s module + 1 + 1 + read-write + + + + + I2S_TX_CLKM_CONF + I2S_TX_CLKM configuration register + 0x70 + 0x20 + 0x00402000 + + + I2S_TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 12 + 8 + read-write + + + I2S_TX_CLKM_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_TX_CLKM_EN + Set 1 to enable i2s_tx function clock + 22 + 1 + read-write + + + + + I2S_TX_CLKM_DIV_CONF + I2S_TX_CLKM_DIV configuration register + 0x74 + 0x20 + 0x00000200 + + + I2S_TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_RX_CLKM_CONF + I2S_RX_CLKM configuration register + 0x78 + 0x20 + 0x00402000 + + + I2S_RX_CLKM_DIV_NUM + Integral I2S clock divider value + 12 + 8 + read-write + + + I2S_RX_CLKM_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 20 + 2 + read-write + + + I2S_RX_CLKM_EN + Set 1 to enable i2s_rx function clock + 22 + 1 + read-write + + + I2S_MCLK_SEL + This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + 23 + 1 + read-write + + + + + I2S_RX_CLKM_DIV_CONF + I2S_RX_CLKM_DIV configuration register + 0x7C + 0x20 + 0x00000200 + + + I2S_RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + SARADC_CONF + SARADC configuration register + 0x80 + 0x20 + 0x00000005 + + + SARADC_CLK_EN + no use + 0 + 1 + read-write + + + SARADC_RST_EN + Set 0 to reset function_register of saradc module + 1 + 1 + read-write + + + SARADC_REG_CLK_EN + Set 1 to enable saradc apb clock + 2 + 1 + read-write + + + SARADC_REG_RST_EN + Set 0 to reset apb_register of saradc module + 3 + 1 + read-write + + + + + SARADC_CLKM_CONF + SARADC_CLKM configuration register + 0x84 + 0x20 + 0x00404000 + + + SARADC_CLKM_DIV_A + The denominator of the frequency divider factor of the saradc function clock. + 0 + 6 + read-write + + + SARADC_CLKM_DIV_B + The numerator of the frequency divider factor of the saradc function clock. + 6 + 6 + read-write + + + SARADC_CLKM_DIV_NUM + The integral part of the frequency divider factor of the saradc function clock. + 12 + 8 + read-write + + + SARADC_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SARADC_CLKM_EN + Set 1 to enable saradc function clock + 22 + 1 + read-write + + + + + TSENS_CLK_CONF + TSENS_CLK configuration register + 0x88 + 0x20 + 0x00400000 + + + TSENS_CLK_SEL + set this field to select clock-source. 0(default): FOSC, 1: XTAL. + 20 + 1 + read-write + + + TSENS_CLK_EN + Set 1 to enable tsens clock + 22 + 1 + read-write + + + TSENS_RST_EN + Set 0 to reset tsens module + 23 + 1 + read-write + + + + + USB_DEVICE_CONF + USB_DEVICE configuration register + 0x8C + 0x20 + 0x00000001 + + + USB_DEVICE_CLK_EN + Set 1 to enable usb_device clock + 0 + 1 + read-write + + + USB_DEVICE_RST_EN + Set 0 to reset usb_device module + 1 + 1 + read-write + + + + + INTMTX_CONF + INTMTX configuration register + 0x90 + 0x20 + 0x00000001 + + + INTMTX_CLK_EN + Set 1 to enable intmtx clock + 0 + 1 + read-write + + + INTMTX_RST_EN + Set 0 to reset intmtx module + 1 + 1 + read-write + + + + + PCNT_CONF + PCNT configuration register + 0x94 + 0x20 + 0x00000001 + + + PCNT_CLK_EN + Set 1 to enable pcnt clock + 0 + 1 + read-write + + + PCNT_RST_EN + Set 0 to reset pcnt module + 1 + 1 + read-write + + + + + ETM_CONF + ETM configuration register + 0x98 + 0x20 + 0x00000001 + + + ETM_CLK_EN + Set 1 to enable etm clock + 0 + 1 + read-write + + + ETM_RST_EN + Set 0 to reset etm module + 1 + 1 + read-write + + + + + PWM_CONF + PWM configuration register + 0x9C + 0x20 + 0x00000001 + + + PWM_CLK_EN + Set 1 to enable pwm clock + 0 + 1 + read-write + + + PWM_RST_EN + Set 0 to reset pwm module + 1 + 1 + read-write + + + + + PWM_CLK_CONF + PWM_CLK configuration register + 0xA0 + 0x20 + 0x00404000 + + + PWM_DIV_NUM + The integral part of the frequency divider factor of the pwm function clock. + 12 + 8 + read-write + + + PWM_CLKM_SEL + set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC. + 20 + 2 + read-write + + + PWM_CLKM_EN + set this field as 1 to activate pwm clkm. + 22 + 1 + read-write + + + + + PARL_IO_CONF + PARL_IO configuration register + 0xA4 + 0x20 + 0x00000001 + + + PARL_CLK_EN + Set 1 to enable parl apb clock + 0 + 1 + read-write + + + PARL_RST_EN + Set 0 to reset parl apb reg + 1 + 1 + read-write + + + + + PARL_CLK_RX_CONF + PARL_CLK_RX configuration register + 0xA8 + 0x20 + 0x00040000 + + + PARL_CLK_RX_DIV_NUM + The integral part of the frequency divider factor of the parl rx clock. + 0 + 16 + read-write + + + PARL_CLK_RX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_RX_EN + Set 1 to enable parl rx clock + 18 + 1 + read-write + + + PARL_RX_RST_EN + Set 0 to reset parl rx module + 19 + 1 + read-write + + + + + PARL_CLK_TX_CONF + PARL_CLK_TX configuration register + 0xAC + 0x20 + 0x00040000 + + + PARL_CLK_TX_DIV_NUM + The integral part of the frequency divider factor of the parl tx clock. + 0 + 16 + read-write + + + PARL_CLK_TX_SEL + set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad. + 16 + 2 + read-write + + + PARL_CLK_TX_EN + Set 1 to enable parl tx clock + 18 + 1 + read-write + + + PARL_TX_RST_EN + Set 0 to reset parl tx module + 19 + 1 + read-write + + + + + SDIO_SLAVE_CONF + SDIO_SLAVE configuration register + 0xB0 + 0x20 + 0x00000001 + + + SDIO_SLAVE_CLK_EN + Set 1 to enable sdio_slave clock + 0 + 1 + read-write + + + SDIO_SLAVE_RST_EN + Set 0 to reset sdio_slave module + 1 + 1 + read-write + + + + + PVT_MONITOR_CONF + PVT_MONITOR configuration register + 0xB4 + 0x20 + 0x0000001D + + + PVT_MONITOR_CLK_EN + Set 1 to enable apb clock of pvt module + 0 + 1 + read-write + + + PVT_MONITOR_RST_EN + Set 0 to reset all pvt monitor module + 1 + 1 + read-write + + + PVT_MONITOR_SITE1_CLK_EN + Set 1 to enable function clock of modem pvt module + 2 + 1 + read-write + + + PVT_MONITOR_SITE2_CLK_EN + Set 1 to enable function clock of cpu pvt module + 3 + 1 + read-write + + + PVT_MONITOR_SITE3_CLK_EN + Set 1 to enable function clock of hp_peri pvt module + 4 + 1 + read-write + + + + + PVT_MONITOR_FUNC_CLK_CONF + PVT_MONITOR function clock configuration register + 0xB8 + 0x20 + 0x00400000 + + + PVT_MONITOR_FUNC_CLK_DIV_NUM + The integral part of the frequency divider factor of the pvt_monitor function clock. + 0 + 4 + read-write + + + PVT_MONITOR_FUNC_CLK_SEL + set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3. + 20 + 1 + read-write + + + PVT_MONITOR_FUNC_CLK_EN + Set 1 to enable source clock of pvt sitex + 22 + 1 + read-write + + + + + GDMA_CONF + GDMA configuration register + 0xBC + 0x20 + 0x00000001 + + + GDMA_CLK_EN + Set 1 to enable gdma clock + 0 + 1 + read-write + + + GDMA_RST_EN + Set 0 to reset gdma module + 1 + 1 + read-write + + + + + SPI2_CONF + SPI2 configuration register + 0xC0 + 0x20 + 0x00000001 + + + SPI2_CLK_EN + Set 1 to enable spi2 apb clock + 0 + 1 + read-write + + + SPI2_RST_EN + Set 0 to reset spi2 module + 1 + 1 + read-write + + + + + SPI2_CLKM_CONF + SPI2_CLKM configuration register + 0xC4 + 0x20 + 0x00400000 + + + SPI2_CLKM_SEL + set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved. + 20 + 2 + read-write + + + SPI2_CLKM_EN + Set 1 to enable spi2 function clock + 22 + 1 + read-write + + + + + AES_CONF + AES configuration register + 0xC8 + 0x20 + 0x00000001 + + + AES_CLK_EN + Set 1 to enable aes clock + 0 + 1 + read-write + + + AES_RST_EN + Set 0 to reset aes module + 1 + 1 + read-write + + + + + SHA_CONF + SHA configuration register + 0xCC + 0x20 + 0x00000001 + + + SHA_CLK_EN + Set 1 to enable sha clock + 0 + 1 + read-write + + + SHA_RST_EN + Set 0 to reset sha module + 1 + 1 + read-write + + + + + RSA_CONF + RSA configuration register + 0xD0 + 0x20 + 0x00000001 + + + RSA_CLK_EN + Set 1 to enable rsa clock + 0 + 1 + read-write + + + RSA_RST_EN + Set 0 to reset rsa module + 1 + 1 + read-write + + + + + RSA_PD_CTRL + RSA power control register + 0xD4 + 0x20 + 0x00000002 + + + RSA_MEM_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + ECC_CONF + ECC configuration register + 0xD8 + 0x20 + 0x00000001 + + + ECC_CLK_EN + Set 1 to enable ecc clock + 0 + 1 + read-write + + + ECC_RST_EN + Set 0 to reset ecc module + 1 + 1 + read-write + + + + + ECC_PD_CTRL + ECC power control register + 0xDC + 0x20 + 0x00000002 + + + ECC_MEM_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + ECC_MEM_FORCE_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + DS_CONF + DS configuration register + 0xE0 + 0x20 + 0x00000001 + + + DS_CLK_EN + Set 1 to enable ds clock + 0 + 1 + read-write + + + DS_RST_EN + Set 0 to reset ds module + 1 + 1 + read-write + + + + + HMAC_CONF + HMAC configuration register + 0xE4 + 0x20 + 0x00000001 + + + HMAC_CLK_EN + Set 1 to enable hmac clock + 0 + 1 + read-write + + + HMAC_RST_EN + Set 0 to reset hmac module + 1 + 1 + read-write + + + + + IOMUX_CONF + IOMUX configuration register + 0xE8 + 0x20 + 0x00000001 + + + IOMUX_CLK_EN + Set 1 to enable iomux apb clock + 0 + 1 + read-write + + + IOMUX_RST_EN + Set 0 to reset iomux module + 1 + 1 + read-write + + + + + IOMUX_CLK_CONF + IOMUX_CLK configuration register + 0xEC + 0x20 + 0x00700000 + + + IOMUX_FUNC_CLK_SEL + set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL. + 20 + 2 + read-write + + + IOMUX_FUNC_CLK_EN + Set 1 to enable iomux function clock + 22 + 1 + read-write + + + + + MEM_MONITOR_CONF + MEM_MONITOR configuration register + 0xF0 + 0x20 + 0x00000001 + + + MEM_MONITOR_CLK_EN + Set 1 to enable mem_monitor clock + 0 + 1 + read-write + + + MEM_MONITOR_RST_EN + Set 0 to reset mem_monitor module + 1 + 1 + read-write + + + + + REGDMA_CONF + REGDMA configuration register + 0xF4 + 0x20 + + + REGDMA_CLK_EN + Set 1 to enable regdma clock + 0 + 1 + read-write + + + REGDMA_RST_EN + Set 0 to reset regdma module + 1 + 1 + read-write + + + + + RETENTION_CONF + retention configuration register + 0xF8 + 0x20 + + + RETENTION_CLK_EN + Set 1 to enable retention clock + 0 + 1 + read-write + + + RETENTION_RST_EN + Set 0 to reset retention module + 1 + 1 + read-write + + + + + TRACE_CONF + TRACE configuration register + 0xFC + 0x20 + 0x00000001 + + + TRACE_CLK_EN + Set 1 to enable trace clock + 0 + 1 + read-write + + + TRACE_RST_EN + Set 0 to reset trace module + 1 + 1 + read-write + + + + + ASSIST_CONF + ASSIST configuration register + 0x100 + 0x20 + 0x00000001 + + + ASSIST_CLK_EN + Set 1 to enable assist clock + 0 + 1 + read-write + + + ASSIST_RST_EN + Set 0 to reset assist module + 1 + 1 + read-write + + + + + CACHE_CONF + CACHE configuration register + 0x104 + 0x20 + 0x00000001 + + + CACHE_CLK_EN + Set 1 to enable cache clock + 0 + 1 + read-write + + + CACHE_RST_EN + Set 0 to reset cache module + 1 + 1 + read-write + + + + + MODEM_APB_CONF + MODEM_APB configuration register + 0x108 + 0x20 + 0x00000001 + + + MODEM_APB_CLK_EN + This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). + 0 + 1 + read-write + + + MODEM_RST_EN + Set this file as 1 to reset modem-subsystem. + 1 + 1 + read-write + + + + + TIMEOUT_CONF + TIMEOUT configuration register + 0x10C + 0x20 + + + CPU_TIMEOUT_RST_EN + Set 0 to reset cpu_peri timeout module + 1 + 1 + read-write + + + HP_TIMEOUT_RST_EN + Set 0 to reset hp_peri timeout module and hp_modem timeout module + 2 + 1 + read-write + + + + + SYSCLK_CONF + SYSCLK configuration register + 0x110 + 0x20 + 0x28000200 + + + LS_DIV_NUM + clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC. + 0 + 8 + read-only + + + HS_DIV_NUM + clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + 8 + 8 + read-only + + + SOC_CLK_SEL + This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. + 16 + 2 + read-write + + + CLK_XTAL_FREQ + This field indicates the frequency(MHz) of XTAL. + 24 + 7 + read-only + + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x114 + 0x20 + 0x0000000D + + + CPUPERIOD_SEL + Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + 0 + 2 + read-only + + + PLL_FREQ_SEL + Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + 2 + 1 + read-only + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + CPU_FREQ_CONF + CPU_FREQ configuration register + 0x118 + 0x20 + + + CPU_LS_DIV_NUM + Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. + 0 + 8 + read-write + + + CPU_HS_DIV_NUM + Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. + 8 + 8 + read-write + + + CPU_HS_120M_FORCE + Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. + 16 + 1 + read-write + + + + + AHB_FREQ_CONF + AHB_FREQ configuration register + 0x11C + 0x20 + 0x00000300 + + + AHB_LS_DIV_NUM + Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_LS_DIV_NUM. + 0 + 8 + read-write + + + AHB_HS_DIV_NUM + Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. + 8 + 8 + read-write + + + + + APB_FREQ_CONF + APB_FREQ configuration register + 0x120 + 0x20 + + + APB_DECREASE_DIV_NUM + If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable. + 0 + 8 + read-write + + + APB_DIV_NUM + Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb. + 8 + 8 + read-write + + + + + SYSCLK_FREQ_QUERY_0 + SYSCLK frequency query 0 register + 0x124 + 0x20 + 0x0001E014 + + + FOSC_FREQ + This field indicates the frequency(MHz) of FOSC. + 0 + 8 + read-only + + + PLL_FREQ + This field indicates the frequency(MHz) of SPLL. + 8 + 10 + read-only + + + + + PLL_DIV_CLK_EN + SPLL DIV clock-gating configuration register + 0x128 + 0x20 + 0x0000007F + + + PLL_240M_CLK_EN + This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 0 + 1 + read-write + + + PLL_160M_CLK_EN + This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 1 + 1 + read-write + + + PLL_120M_CLK_EN + This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 2 + 1 + read-write + + + PLL_80M_CLK_EN + This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 3 + 1 + read-write + + + PLL_48M_CLK_EN + This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 4 + 1 + read-write + + + PLL_40M_CLK_EN + This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 5 + 1 + read-write + + + PLL_20M_CLK_EN + This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + 6 + 1 + read-write + + + + + CTRL_CLK_OUT_EN + CLK_OUT_EN configuration register + 0x12C + 0x20 + 0x000007FF + + + CLK20_OEN + Set 1 to enable 20m clock + 0 + 1 + read-write + + + CLK22_OEN + Set 1 to enable 22m clock + 1 + 1 + read-write + + + CLK44_OEN + Set 1 to enable 44m clock + 2 + 1 + read-write + + + CLK_BB_OEN + Set 1 to enable bb clock + 3 + 1 + read-write + + + CLK80_OEN + Set 1 to enable 80m clock + 4 + 1 + read-write + + + CLK160_OEN + Set 1 to enable 160m clock + 5 + 1 + read-write + + + CLK_320M_OEN + Set 1 to enable 320m clock + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + Reserved + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + Reserved + 8 + 1 + read-write + + + CLK40X_BB_OEN + Set 1 to enable 40x_bb clock + 9 + 1 + read-write + + + CLK_XTAL_OEN + Set 1 to enable xtal clock + 10 + 1 + read-write + + + + + CTRL_TICK_CONF + TICK configuration register + 0x130 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + FOSC_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 17 + 1 + read-write + + + + + CTRL_32K_CONF + 32KHz clock configuration register + 0x134 + 0x20 + + + _32K_SEL + This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + 0 + 2 + read-write + + + + + SRAM_POWER_CONF + HP SRAM/ROM configuration register + 0x138 + 0x20 + 0x0000700F + + + SRAM_FORCE_PU + Set this bit to force power up SRAM + 0 + 4 + read-write + + + SRAM_FORCE_PD + Set this bit to force power down SRAM. + 4 + 4 + read-write + + + SRAM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM. + 8 + 4 + read-write + + + ROM_FORCE_PU + Set this bit to force power up ROM + 12 + 3 + read-write + + + ROM_FORCE_PD + Set this bit to force power down ROM. + 15 + 3 + read-write + + + ROM_CLKGATE_FORCE_ON + 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM. + 18 + 3 + read-write + + + + + RESET_EVENT_BYPASS + reset event bypass backdoor configuration register + 0xFF0 + 0x20 + 0x00000002 + + + APM + This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event. + 0 + 1 + read-write + + + RESET_EVENT_BYPASS + This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event. + 1 + 1 + read-write + + + + + FPGA_DEBUG + fpga debug register + 0xFF4 + 0x20 + 0xFFFFFFFF + + + FPGA_DEBUG + Only used in fpga debug. + 0 + 32 + read-write + + + + + CLOCK_GATE + PCR clock gating configure register + 0xFF8 + 0x20 + + + CLK_EN + Set this bit as 1 to force on clock gating. + 0 + 1 + read-write + + + + + DATE + Date register. + 0xFFC + 0x20 + 0x02206150 + + + DATE + PCR version information. + 0 + 28 + read-write + + + + + + + PMU + Peripheral PMU + PMU + 0x600B0000 + + 0x0 + 0x1A8 + registers + + + PMU + 13 + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_VDD_SPI_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 4 + read-write + + + HP_ACTIVE_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_PD_HP_CPU_PD_EN + need_des + 29 + 1 + read-write + + + HP_ACTIVE_PD_HP_AON_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 26 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 27 + 1 + read-write + + + HP_ACTIVE_XPD_BB_I2C + need_des + 28 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL_I2C + need_des + 29 + 1 + read-write + + + HP_ACTIVE_XPD_BBPLL + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 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+ 1 + read-write + + + FORCE_HP_CPU_PD + need_des + 5 + 1 + read-write + + + PD_HP_CPU_MASK + need_des + 6 + 5 + read-write + + + PD_HP_CPU_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_HPPERI_RESERVE + need_des + 0x100 + 0x20 + + + HP_PERI_RESERVE + need_des + 0 + 32 + write-only + + + + + POWER_PD_HPWIFI_CNTL + need_des + 0x104 + 0x20 + 0x0000001C + + + FORCE_HP_WIFI_RESET + need_des + 0 + 1 + read-write + + + FORCE_HP_WIFI_ISO + need_des + 1 + 1 + read-write + + + FORCE_HP_WIFI_PU + need_des + 2 + 1 + read-write + + + FORCE_HP_WIFI_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_HP_WIFI_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_HP_WIFI_PD + need_des + 5 + 1 + read-write + + + PD_HP_WIFI_MASK + need_des + 6 + 5 + read-write + + + PD_HP_WIFI_PD_MASK + need_des + 27 + 5 + read-write + + + + + POWER_PD_LPPERI_CNTL + need_des + 0x108 + 0x20 + 0x0000001C + + + FORCE_LP_PERI_RESET + need_des + 0 + 1 + read-write + + + FORCE_LP_PERI_ISO + need_des + 1 + 1 + read-write + + + FORCE_LP_PERI_PU + need_des + 2 + 1 + read-write + + + FORCE_LP_PERI_NO_RESET + need_des + 3 + 1 + read-write + + + FORCE_LP_PERI_NO_ISO + need_des + 4 + 1 + read-write + + + FORCE_LP_PERI_PD + need_des + 5 + 1 + read-write + + + + + POWER_PD_MEM_CNTL + need_des + 0x10C + 0x20 + 0xFF000000 + + + FORCE_HP_MEM_ISO + need_des + 0 + 4 + read-write + + + FORCE_HP_MEM_PD + need_des + 4 + 4 + read-write + + + FORCE_HP_MEM_NO_ISO + need_des + 24 + 4 + read-write + + + FORCE_HP_MEM_PU + need_des + 28 + 4 + read-write + + + + + POWER_PD_MEM_MASK + need_des + 0x110 + 0x20 + + + PD_HP_MEM2_PD_MASK + need_des + 0 + 5 + read-write + + + PD_HP_MEM1_PD_MASK + need_des + 5 + 5 + read-write + + + PD_HP_MEM0_PD_MASK + need_des + 10 + 5 + read-write + + + PD_HP_MEM2_MASK + need_des + 17 + 5 + read-write + + + PD_HP_MEM1_MASK + need_des + 22 + 5 + read-write + + + PD_HP_MEM0_MASK + need_des + 27 + 5 + read-write + + + + + POWER_HP_PAD + need_des + 0x114 + 0x20 + + + FORCE_HP_PAD_NO_ISO_ALL + need_des + 0 + 1 + read-write + + + FORCE_HP_PAD_ISO_ALL + need_des + 1 + 1 + read-write + + + + + POWER_VDD_SPI_CNTL + need_des + 0x118 + 0x20 + 0x63FC0000 + + + VDD_SPI_PWR_WAIT + need_des + 18 + 11 + read-write + + + VDD_SPI_PWR_SW + need_des + 29 + 2 + read-write + + + VDD_SPI_PWR_SEL_SW + need_des + 31 + 1 + read-write + + + + + POWER_CK_WAIT_CNTL + need_des + 0x11C + 0x20 + 0x01000100 + + + WAIT_XTL_STABLE + need_des + 0 + 16 + read-write + + + WAIT_PLL_STABLE + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_CNTL0 + need_des + 0x120 + 0x20 + + + SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL1 + need_des + 0x124 + 0x20 + + + SLEEP_REJECT_ENA + need_des + 0 + 31 + read-write + + + SLP_REJECT_EN + need_des + 31 + 1 + read-write + + + + + SLP_WAKEUP_CNTL2 + need_des + 0x128 + 0x20 + + + WAKEUP_ENA + need_des + 0 + 32 + read-write + + + + + SLP_WAKEUP_CNTL3 + need_des + 0x12C + 0x20 + + + LP_MIN_SLP_VAL + need_des + 0 + 8 + read-write + + + HP_MIN_SLP_VAL + need_des + 8 + 8 + read-write + + + SLEEP_PRT_SEL + need_des + 16 + 2 + read-write + + + + + SLP_WAKEUP_CNTL4 + need_des + 0x130 + 0x20 + + + SLP_REJECT_CAUSE_CLR + need_des + 31 + 1 + write-only + + + + + SLP_WAKEUP_CNTL5 + need_des + 0x134 + 0x20 + 0x01000080 + + + MODEM_WAIT_TARGET + need_des + 0 + 20 + read-write + + + LP_ANA_WAIT_TARGET + need_des + 24 + 8 + read-write + + + + + SLP_WAKEUP_CNTL6 + need_des + 0x138 + 0x20 + 0x00000080 + + + SOC_WAKEUP_WAIT + need_des + 0 + 20 + read-write + + + SOC_WAKEUP_WAIT_CFG + need_des + 30 + 2 + read-write + + + + + SLP_WAKEUP_CNTL7 + need_des + 0x13C + 0x20 + 0x00010000 + + + ANA_WAIT_TARGET + need_des + 16 + 16 + read-write + + + + + SLP_WAKEUP_STATUS0 + need_des + 0x140 + 0x20 + + + WAKEUP_CAUSE + need_des + 0 + 32 + read-only + + + + + SLP_WAKEUP_STATUS1 + need_des + 0x144 + 0x20 + + + REJECT_CAUSE + need_des + 0 + 32 + read-only + + + + + HP_CK_POWERON + need_des + 0x148 + 0x20 + 0x00000032 + + + I2C_POR_WAIT_TARGET + need_des + 0 + 8 + read-write + + + + + HP_CK_CNTL + need_des + 0x14C + 0x20 + 0x00000A0A + + + MODIFY_ICG_CNTL_WAIT + need_des + 0 + 8 + read-write + + + SWITCH_ICG_CNTL_WAIT + need_des + 8 + 8 + read-write + + + + + POR_STATUS + need_des + 0x150 + 0x20 + 0x80000000 + + + POR_DONE + need_des + 31 + 1 + read-only + + + + + RF_PWC + need_des + 0x154 + 0x20 + 0x08000000 + + + PERIF_I2C_RSTB + need_des + 26 + 1 + read-write + + + XPD_PERIF_I2C + need_des + 27 + 1 + read-write + + + XPD_TXRF_I2C + need_des + 28 + 1 + read-write + + + XPD_RFRX_PBUS + need_des + 29 + 1 + read-write + + + XPD_CKGEN_I2C + need_des + 30 + 1 + read-write + + + XPD_PLL_I2C + need_des + 31 + 1 + read-write + + + + + BACKUP_CFG + need_des + 0x158 + 0x20 + 0x80000000 + + + BACKUP_SYS_CLK_NO_DIV + need_des + 31 + 1 + read-write + + + + + INT_RAW + need_des + 0x15C + 0x20 + + + LP_CPU_EXC_INT_RAW + need_des + 27 + 1 + read-only + + + SDIO_IDLE_INT_RAW + need_des + 28 + 1 + read-only + + + SW_INT_RAW + need_des + 29 + 1 + read-only + + + SOC_SLEEP_REJECT_INT_RAW + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-only + + + + + HP_INT_ST + need_des + 0x160 + 0x20 + + + LP_CPU_EXC_INT_ST + need_des + 27 + 1 + read-only + + + SDIO_IDLE_INT_ST + need_des + 28 + 1 + read-only + + + SW_INT_ST + need_des + 29 + 1 + read-only + + + SOC_SLEEP_REJECT_INT_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + HP_INT_ENA + need_des + 0x164 + 0x20 + + + LP_CPU_EXC_INT_ENA + need_des + 27 + 1 + read-write + + + SDIO_IDLE_INT_ENA + need_des + 28 + 1 + read-write + + + SW_INT_ENA + need_des + 29 + 1 + read-write + + + SOC_SLEEP_REJECT_INT_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + HP_INT_CLR + need_des + 0x168 + 0x20 + + + LP_CPU_EXC_INT_CLR + need_des + 27 + 1 + write-only + + + SDIO_IDLE_INT_CLR + need_des + 28 + 1 + write-only + + + SW_INT_CLR + need_des + 29 + 1 + write-only + + + SOC_SLEEP_REJECT_INT_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x16C + 0x20 + + + LP_CPU_WAKEUP_INT_RAW + need_des + 20 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_END_INT_RAW + need_des + 21 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_END_INT_RAW + need_des + 22 + 1 + read-only + + + SLEEP_SWITCH_MODEM_END_INT_RAW + need_des + 23 + 1 + read-only + + + MODEM_SWITCH_SLEEP_END_INT_RAW + need_des + 24 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_END_INT_RAW + need_des + 25 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_START_INT_RAW + need_des + 26 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_START_INT_RAW + need_des + 27 + 1 + read-only + + + SLEEP_SWITCH_MODEM_START_INT_RAW + need_des + 28 + 1 + read-only + + + MODEM_SWITCH_SLEEP_START_INT_RAW + need_des + 29 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_START_INT_RAW + need_des + 30 + 1 + read-only + + + HP_SW_TRIGGER_INT_RAW + need_des + 31 + 1 + read-only + + + + + LP_INT_ST + need_des + 0x170 + 0x20 + + + LP_CPU_WAKEUP_INT_ST + need_des + 20 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_END_INT_ST + need_des + 21 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_END_INT_ST + need_des + 22 + 1 + read-only + + + SLEEP_SWITCH_MODEM_END_INT_ST + need_des + 23 + 1 + read-only + + + MODEM_SWITCH_SLEEP_END_INT_ST + need_des + 24 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_END_INT_ST + need_des + 25 + 1 + read-only + + + MODEM_SWITCH_ACTIVE_START_INT_ST + need_des + 26 + 1 + read-only + + + SLEEP_SWITCH_ACTIVE_START_INT_ST + need_des + 27 + 1 + read-only + + + SLEEP_SWITCH_MODEM_START_INT_ST + need_des + 28 + 1 + read-only + + + MODEM_SWITCH_SLEEP_START_INT_ST + need_des + 29 + 1 + read-only + + + ACTIVE_SWITCH_SLEEP_START_INT_ST + need_des + 30 + 1 + read-only + + + HP_SW_TRIGGER_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x174 + 0x20 + + + LP_CPU_WAKEUP_INT_ENA + need_des + 20 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_END_INT_ENA + need_des + 21 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_END_INT_ENA + need_des + 22 + 1 + read-write + + + SLEEP_SWITCH_MODEM_END_INT_ENA + need_des + 23 + 1 + read-write + + + MODEM_SWITCH_SLEEP_END_INT_ENA + need_des + 24 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_END_INT_ENA + need_des + 25 + 1 + read-write + + + MODEM_SWITCH_ACTIVE_START_INT_ENA + need_des + 26 + 1 + read-write + + + SLEEP_SWITCH_ACTIVE_START_INT_ENA + need_des + 27 + 1 + read-write + + + SLEEP_SWITCH_MODEM_START_INT_ENA + need_des + 28 + 1 + read-write + + + MODEM_SWITCH_SLEEP_START_INT_ENA + need_des + 29 + 1 + read-write + + + ACTIVE_SWITCH_SLEEP_START_INT_ENA + need_des + 30 + 1 + read-write + + + HP_SW_TRIGGER_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x178 + 0x20 + + + LP_CPU_WAKEUP_INT_CLR + need_des + 20 + 1 + write-only + + + MODEM_SWITCH_ACTIVE_END_INT_CLR + need_des + 21 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_END_INT_CLR + need_des + 22 + 1 + write-only + + + SLEEP_SWITCH_MODEM_END_INT_CLR + need_des + 23 + 1 + write-only + + + MODEM_SWITCH_SLEEP_END_INT_CLR + need_des + 24 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_END_INT_CLR + need_des + 25 + 1 + write-only + + + MODEM_SWITCH_ACTIVE_START_INT_CLR + need_des + 26 + 1 + write-only + + + SLEEP_SWITCH_ACTIVE_START_INT_CLR + need_des + 27 + 1 + write-only + + + SLEEP_SWITCH_MODEM_START_INT_CLR + need_des + 28 + 1 + write-only + + + MODEM_SWITCH_SLEEP_START_INT_CLR + need_des + 29 + 1 + write-only + + + ACTIVE_SWITCH_SLEEP_START_INT_CLR + need_des + 30 + 1 + write-only + + + HP_SW_TRIGGER_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_CPU_PWR0 + need_des + 0x17C + 0x20 + 0x1FF00000 + + + LP_CPU_WAITI_RDY + need_des + 0 + 1 + read-only + + + LP_CPU_STALL_RDY + need_des + 1 + 1 + read-only + + + LP_CPU_FORCE_STALL + need_des + 18 + 1 + read-write + + + LP_CPU_SLP_WAITI_FLAG_EN + need_des + 19 + 1 + read-write + + + LP_CPU_SLP_STALL_FLAG_EN + need_des + 20 + 1 + read-write + + + LP_CPU_SLP_STALL_WAIT + need_des + 21 + 8 + read-write + + + LP_CPU_SLP_STALL_EN + need_des + 29 + 1 + read-write + + + LP_CPU_SLP_RESET_EN + need_des + 30 + 1 + read-write + + + LP_CPU_SLP_BYPASS_INTR_EN + need_des + 31 + 1 + read-write + + + + + LP_CPU_PWR1 + need_des + 0x180 + 0x20 + + + LP_CPU_WAKEUP_EN + need_des + 0 + 16 + read-write + + + LP_CPU_SLEEP_REQ + need_des + 31 + 1 + write-only + + + + + HP_LP_CPU_COMM + need_des + 0x184 + 0x20 + + + LP_TRIGGER_HP + need_des + 30 + 1 + write-only + + + HP_TRIGGER_LP + need_des + 31 + 1 + write-only + + + + + HP_REGULATOR_CFG + need_des + 0x188 + 0x20 + + + DIG_REGULATOR_EN_CAL + need_des + 31 + 1 + read-write + + + + + MAIN_STATE + need_des + 0x18C + 0x20 + 0x08100800 + + + MAIN_LAST_ST_STATE + need_des + 11 + 7 + read-only + + + MAIN_TAR_ST_STATE + need_des + 18 + 7 + read-only + + + MAIN_CUR_ST_STATE + need_des + 25 + 7 + read-only + + + + + PWR_STATE + need_des + 0x190 + 0x20 + 0x00802000 + + + BACKUP_ST_STATE + need_des + 13 + 5 + read-only + + + LP_PWR_ST_STATE + need_des + 18 + 5 + read-only + + + HP_PWR_ST_STATE + need_des + 23 + 9 + read-only + + + + + CLK_STATE0 + need_des + 0x194 + 0x20 + 0x00000003 + + + STABLE_XPD_BBPLL_STATE + need_des + 0 + 1 + read-only + + + STABLE_XPD_XTAL_STATE + need_des + 1 + 1 + read-only + + + SYS_CLK_SLP_SEL_STATE + need_des + 15 + 1 + read-only + + + SYS_CLK_SEL_STATE + need_des + 16 + 2 + read-only + + + SYS_CLK_NO_DIV_STATE + need_des + 18 + 1 + read-only + + + ICG_SYS_CLK_EN_STATE + need_des + 19 + 1 + read-only + + + ICG_MODEM_SWITCH_STATE + need_des + 20 + 1 + read-only + + + ICG_MODEM_CODE_STATE + need_des + 21 + 2 + read-only + + + ICG_SLP_SEL_STATE + need_des + 23 + 1 + read-only + + + ICG_GLOBAL_XTAL_STATE + need_des + 24 + 1 + read-only + + + ICG_GLOBAL_PLL_STATE + need_des + 25 + 1 + read-only + + + ANA_I2C_ISO_EN_STATE + need_des + 26 + 1 + read-only + + + ANA_I2C_RETENTION_STATE + need_des + 27 + 1 + read-only + + + ANA_XPD_BB_I2C_STATE + need_des + 28 + 1 + read-only + + + ANA_XPD_BBPLL_I2C_STATE + need_des + 29 + 1 + read-only + + + ANA_XPD_BBPLL_STATE + need_des + 30 + 1 + read-only + + + ANA_XPD_XTAL_STATE + need_des + 31 + 1 + read-only + + + + + CLK_STATE1 + need_des + 0x198 + 0x20 + 0xFFFFFFFF + + + ICG_FUNC_EN_STATE + need_des + 0 + 32 + read-only + + + + + CLK_STATE2 + need_des + 0x19C + 0x20 + 0xFFFFFFFF + + + ICG_APB_EN_STATE + need_des + 0 + 32 + read-only + + + + + VDD_SPI_STATUS + need_des + 0x1A0 + 0x20 + + + STABLE_VDD_SPI_PWR_DRV + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02206250 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x60006000 + + 0x0 + 0x78 + registers + + + RMT + 49 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 2 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x10 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 3 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 2 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x18 + 0x20 + 0x30FFFF02 + + + DIV_CNT_CH2 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH2 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH2 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 23 + 3 + read-write + + + CARRIER_EN_CH2 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH2 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 2 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x1C + 0x20 + 0x000001E8 + + + RX_EN_CH2 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH2 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH2 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH2 + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH2 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH2 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH2 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH2 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH2 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 2 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x28 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 9 + 3 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 12 + 9 + read-only + + + APB_MEM_RD_ERR_CH0 + This status bit will be set if the offset address out of memory size when reading via APB bus. + 21 + 1 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 22 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 23 + 1 + read-only + + + APB_MEM_RADDR_CH0 + This register records the memory address offset when reading RAM over APB bus. + 24 + 8 + read-only + + + + + 2 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x30 + 0x20 + + + MEM_WADDR_EX_CH2 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + APB_MEM_RADDR_CH2 + This register records the memory address offset when reads RAM over APB bus. + 12 + 9 + read-only + + + STATE_CH2 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH2 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH2 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH2 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x38 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-only + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-only + + + CH2_RX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when reception done. + 2 + 1 + read-only + + + CH3_RX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when reception done. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x3C + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_RX_END_INT_ST + The masked interrupt status bit for CH2_RX_END_INT. + 2 + 1 + read-only + + + CH3_RX_END_INT_ST + The masked interrupt status bit for CH3_RX_END_INT. + 3 + 1 + read-only + + + RX_CH0_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 4 + 1 + read-only + + + RX_CH1_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 5 + 1 + read-only + + + RX_CH2_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 6 + 1 + read-only + + + RX_CH3_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x40 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_RX_END_INT_ENA + The interrupt enable bit for CH2_RX_END_INT. + 2 + 1 + read-write + + + CH3_RX_END_INT_ENA + The interrupt enable bit for CH3_RX_END_INT. + 3 + 1 + read-write + + + CH0_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 4 + 1 + read-write + + + CH1_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 5 + 1 + read-write + + + CH2_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 6 + 1 + read-write + + + CH3_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x44 + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_RX_END_INT_CLR + Set this bit to clear theCH2_RX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_RX_END_INT_CLR + Set this bit to clear theCH3_RX_END_INT interrupt. + 3 + 1 + write-only + + + RX_CH0_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 4 + 1 + write-only + + + RX_CH1_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 5 + 1 + write-only + + + RX_CH2_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 6 + 1 + write-only + + + RX_CH3_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + + + 2 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x48 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH0 + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH0 + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x50 + 0x20 + + + CARRIER_LOW_THRES_CH2 + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH2 + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0x58 + 0x20 + 0x00000080 + + + TX_LIM_CH0 + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH0 + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH0 + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH0 + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH0 + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 2 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0x60 + 0x20 + 0x00000080 + + + RMT_RX_LIM_CH2 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0x68 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + RMT_MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + RMT_MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + RMT_SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + RMT_SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + RMT_SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + RMT_SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + 24 + 2 + read-write + + + RMT_SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0x6C + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 2 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0x70 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + RX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + RX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02108213 + + + RMT_DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x600B2800 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x8 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6008A000 + + 0x0 + 0x74 + registers + + + RSA + 75 + + + + 16 + 0x1 + M_MEM[%s] + The memory that stores M + 0x0 + 0x8 + + + 16 + 0x1 + Z_MEM[%s] + The memory that stores Z + 0x200 + 0x8 + + + 16 + 0x1 + Y_MEM[%s] + The memory that stores Y + 0x400 + 0x8 + + + 16 + 0x1 + X_MEM[%s] + The memory that stores X + 0x600 + 0x8 + + + M_PRIME + RSA M_prime register + 0x800 + 0x20 + + + M_PRIME + Those bits stores m' + 0 + 32 + read-write + + + + + MODE + RSA mode register + 0x804 + 0x20 + + + MODE + rsa mode (rsa length). + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA query clean register + 0x808 + 0x20 + + + QUERY_CLEAN + query clean + 0 + 1 + read-only + + + + + SET_START_MODEXP + RSA modular exponentiation trigger register. + 0x80C + 0x20 + + + SET_START_MODEXP + start modular exponentiation + 0 + 1 + write-only + + + + + SET_START_MODMULT + RSA modular multiplication trigger register. + 0x810 + 0x20 + + + SET_START_MODMULT + start modular multiplication + 0 + 1 + write-only + + + + + SET_START_MULT + RSA normal multiplication trigger register. + 0x814 + 0x20 + + + SET_START_MULT + start multiplicaiton + 0 + 1 + write-only + + + + + QUERY_IDLE + RSA query idle register + 0x818 + 0x20 + + + QUERY_IDLE + query rsa idle. 1'b0: busy, 1'b1: idle + 0 + 1 + read-only + + + + + INT_CLR + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to clear RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + RSA constant time option register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + RSA search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default). + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x60089000 + + 0x0 + 0xB0 + registers + + + SHA + 74 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SLCHOST + Peripheral SLCHOST + SLCHOST + 0x60017000 + + 0x0 + 0x104 + registers + + + + FUNC2_0 + *******Description*********** + 0x10 + 0x20 + + + SLC_FUNC2_INT + *******Description*********** + 24 + 1 + read-write + + + + + FUNC2_1 + *******Description*********** + 0x14 + 0x20 + + + SLC_FUNC2_INT_EN + *******Description*********** + 0 + 1 + read-write + + + + + FUNC2_2 + *******Description*********** + 0x20 + 0x20 + 0x00000001 + + + SLC_FUNC1_MDSTAT + *******Description*********** + 0 + 1 + read-write + + + + + GPIO_STATUS0 + *******Description*********** + 0x34 + 0x20 + + + GPIO_SDIO_INT0 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_STATUS1 + *******Description*********** + 0x38 + 0x20 + + + GPIO_SDIO_INT1 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_IN0 + *******Description*********** + 0x3C + 0x20 + + + GPIO_SDIO_IN0 + *******Description*********** + 0 + 32 + read-only + + + + + GPIO_IN1 + *******Description*********** + 0x40 + 0x20 + + + GPIO_SDIO_IN1 + *******Description*********** + 0 + 32 + read-only + + + + + SLC0HOST_TOKEN_RDATA + *******Description*********** + 0x44 + 0x20 + + + SLC0_TOKEN0 + *******Description*********** + 0 + 12 + read-only + + + SLC0_RX_PF_VALID + *******Description*********** + 12 + 1 + read-only + + + HOSTSLCHOST_SLC0_TOKEN1 + *******Description*********** + 16 + 12 + read-only + + + SLC0_RX_PF_EOF + *******Description*********** + 28 + 4 + read-only + + + + + SLC0_HOST_PF + *******Description*********** + 0x48 + 0x20 + + + SLC0_PF_DATA + *******Description*********** + 0 + 32 + read-only + + + + + SLC1_HOST_PF + *******Description*********** + 0x4C + 0x20 + + + SLC1_PF_DATA + *******Description*********** + 0 + 32 + read-only + + + + + SLC0HOST_INT_RAW + *******Description*********** + 0x50 + 0x20 + + + SLC0_TOHOST_BIT0_INT_RAW + *******Description*********** + 0 + 1 + read-only + + + SLC0_TOHOST_BIT1_INT_RAW + *******Description*********** + 1 + 1 + read-only + + + SLC0_TOHOST_BIT2_INT_RAW + *******Description*********** + 2 + 1 + read-only + + + SLC0_TOHOST_BIT3_INT_RAW + *******Description*********** + 3 + 1 + read-only + + + SLC0_TOHOST_BIT4_INT_RAW + *******Description*********** + 4 + 1 + read-only + + + SLC0_TOHOST_BIT5_INT_RAW + *******Description*********** + 5 + 1 + read-only + + + SLC0_TOHOST_BIT6_INT_RAW + *******Description*********** + 6 + 1 + read-only + + + SLC0_TOHOST_BIT7_INT_RAW + *******Description*********** + 7 + 1 + read-only + + + SLC0_TOKEN0_1TO0_INT_RAW + *******Description*********** + 8 + 1 + read-only + + + SLC0_TOKEN1_1TO0_INT_RAW + *******Description*********** + 9 + 1 + read-only + + + SLC0_TOKEN0_0TO1_INT_RAW + *******Description*********** + 10 + 1 + read-only + + + SLC0_TOKEN1_0TO1_INT_RAW + *******Description*********** + 11 + 1 + read-only + + + SLC0HOST_RX_SOF_INT_RAW + *******Description*********** + 12 + 1 + read-only + + + SLC0HOST_RX_EOF_INT_RAW + *******Description*********** + 13 + 1 + read-only + + + SLC0HOST_RX_START_INT_RAW + *******Description*********** + 14 + 1 + read-only + + + SLC0HOST_TX_START_INT_RAW + *******Description*********** + 15 + 1 + read-only + + + SLC0_RX_UDF_INT_RAW + *******Description*********** + 16 + 1 + read-only + + + SLC0_TX_OVF_INT_RAW + *******Description*********** + 17 + 1 + read-only + + + SLC0_RX_PF_VALID_INT_RAW + *******Description*********** + 18 + 1 + read-only + + + SLC0_EXT_BIT0_INT_RAW + *******Description*********** + 19 + 1 + read-only + + + SLC0_EXT_BIT1_INT_RAW + *******Description*********** + 20 + 1 + read-only + + + SLC0_EXT_BIT2_INT_RAW + *******Description*********** + 21 + 1 + read-only + + + SLC0_EXT_BIT3_INT_RAW + *******Description*********** + 22 + 1 + read-only + + + SLC0_RX_NEW_PACKET_INT_RAW + *******Description*********** + 23 + 1 + read-only + + + SLC0_HOST_RD_RETRY_INT_RAW + *******Description*********** + 24 + 1 + read-only + + + GPIO_SDIO_INT_RAW + *******Description*********** + 25 + 1 + read-only + + + + + SLC1HOST_INT_RAW + *******Description*********** + 0x54 + 0x20 + + + SLC1_TOHOST_BIT0_INT_RAW + *******Description*********** + 0 + 1 + read-only + + + SLC1_TOHOST_BIT1_INT_RAW + *******Description*********** + 1 + 1 + read-only + + + SLC1_TOHOST_BIT2_INT_RAW + *******Description*********** + 2 + 1 + read-only + + + SLC1_TOHOST_BIT3_INT_RAW + *******Description*********** + 3 + 1 + read-only + + + SLC1_TOHOST_BIT4_INT_RAW + *******Description*********** + 4 + 1 + read-only + + + SLC1_TOHOST_BIT5_INT_RAW + *******Description*********** + 5 + 1 + read-only + + + SLC1_TOHOST_BIT6_INT_RAW + *******Description*********** + 6 + 1 + read-only + + + SLC1_TOHOST_BIT7_INT_RAW + *******Description*********** + 7 + 1 + read-only + + + SLC1_TOKEN0_1TO0_INT_RAW + *******Description*********** + 8 + 1 + read-only + + + SLC1_TOKEN1_1TO0_INT_RAW + *******Description*********** + 9 + 1 + read-only + + + SLC1_TOKEN0_0TO1_INT_RAW + *******Description*********** + 10 + 1 + read-only + + + SLC1_TOKEN1_0TO1_INT_RAW + *******Description*********** + 11 + 1 + read-only + + + SLC1HOST_RX_SOF_INT_RAW + *******Description*********** + 12 + 1 + read-only + + + SLC1HOST_RX_EOF_INT_RAW + *******Description*********** + 13 + 1 + read-only + + + SLC1HOST_RX_START_INT_RAW + *******Description*********** + 14 + 1 + read-only + + + SLC1HOST_TX_START_INT_RAW + *******Description*********** + 15 + 1 + read-only + + + SLC1_RX_UDF_INT_RAW + *******Description*********** + 16 + 1 + read-only + + + SLC1_TX_OVF_INT_RAW + *******Description*********** + 17 + 1 + read-only + + + SLC1_RX_PF_VALID_INT_RAW + *******Description*********** + 18 + 1 + read-only + + + SLC1_EXT_BIT0_INT_RAW + *******Description*********** + 19 + 1 + read-only + + + SLC1_EXT_BIT1_INT_RAW + *******Description*********** + 20 + 1 + read-only + + + SLC1_EXT_BIT2_INT_RAW + *******Description*********** + 21 + 1 + read-only + + + SLC1_EXT_BIT3_INT_RAW + *******Description*********** + 22 + 1 + read-only + + + SLC1_WIFI_RX_NEW_PACKET_INT_RAW + *******Description*********** + 23 + 1 + read-only + + + SLC1_HOST_RD_RETRY_INT_RAW + *******Description*********** + 24 + 1 + read-only + + + SLC1_BT_RX_NEW_PACKET_INT_RAW + *******Description*********** + 25 + 1 + read-only + + + + + SLC0HOST_INT_ST + *******Description*********** + 0x58 + 0x20 + + + SLC0_TOHOST_BIT0_INT_ST + *******Description*********** + 0 + 1 + read-only + + + SLC0_TOHOST_BIT1_INT_ST + *******Description*********** + 1 + 1 + read-only + + + SLC0_TOHOST_BIT2_INT_ST + *******Description*********** + 2 + 1 + read-only + + + SLC0_TOHOST_BIT3_INT_ST + *******Description*********** + 3 + 1 + read-only + + + SLC0_TOHOST_BIT4_INT_ST + *******Description*********** + 4 + 1 + read-only + + + SLC0_TOHOST_BIT5_INT_ST + *******Description*********** + 5 + 1 + read-only + + + SLC0_TOHOST_BIT6_INT_ST + *******Description*********** + 6 + 1 + read-only + + + SLC0_TOHOST_BIT7_INT_ST + *******Description*********** + 7 + 1 + read-only + + + SLC0_TOKEN0_1TO0_INT_ST + *******Description*********** + 8 + 1 + read-only + + + SLC0_TOKEN1_1TO0_INT_ST + *******Description*********** + 9 + 1 + read-only + + + SLC0_TOKEN0_0TO1_INT_ST + *******Description*********** + 10 + 1 + read-only + + + SLC0_TOKEN1_0TO1_INT_ST + *******Description*********** + 11 + 1 + read-only + + + SLC0HOST_RX_SOF_INT_ST + *******Description*********** + 12 + 1 + read-only + + + SLC0HOST_RX_EOF_INT_ST + *******Description*********** + 13 + 1 + read-only + + + SLC0HOST_RX_START_INT_ST + *******Description*********** + 14 + 1 + read-only + + + SLC0HOST_TX_START_INT_ST + *******Description*********** + 15 + 1 + read-only + + + SLC0_RX_UDF_INT_ST + *******Description*********** + 16 + 1 + read-only + + + SLC0_TX_OVF_INT_ST + *******Description*********** + 17 + 1 + read-only + + + SLC0_RX_PF_VALID_INT_ST + *******Description*********** + 18 + 1 + read-only + + + SLC0_EXT_BIT0_INT_ST + *******Description*********** + 19 + 1 + read-only + + + SLC0_EXT_BIT1_INT_ST + *******Description*********** + 20 + 1 + read-only + + + SLC0_EXT_BIT2_INT_ST + *******Description*********** + 21 + 1 + read-only + + + SLC0_EXT_BIT3_INT_ST + *******Description*********** + 22 + 1 + read-only + + + SLC0_RX_NEW_PACKET_INT_ST + *******Description*********** + 23 + 1 + read-only + + + SLC0_HOST_RD_RETRY_INT_ST + *******Description*********** + 24 + 1 + read-only + + + GPIO_SDIO_INT_ST + *******Description*********** + 25 + 1 + read-only + + + + + SLC1HOST_INT_ST + *******Description*********** + 0x5C + 0x20 + + + SLC1_TOHOST_BIT0_INT_ST + *******Description*********** + 0 + 1 + read-only + + + SLC1_TOHOST_BIT1_INT_ST + *******Description*********** + 1 + 1 + read-only + + + SLC1_TOHOST_BIT2_INT_ST + *******Description*********** + 2 + 1 + read-only + + + SLC1_TOHOST_BIT3_INT_ST + *******Description*********** + 3 + 1 + read-only + + + SLC1_TOHOST_BIT4_INT_ST + *******Description*********** + 4 + 1 + read-only + + + SLC1_TOHOST_BIT5_INT_ST + *******Description*********** + 5 + 1 + read-only + + + SLC1_TOHOST_BIT6_INT_ST + *******Description*********** + 6 + 1 + read-only + + + SLC1_TOHOST_BIT7_INT_ST + *******Description*********** + 7 + 1 + read-only + + + SLC1_TOKEN0_1TO0_INT_ST + *******Description*********** + 8 + 1 + read-only + + + SLC1_TOKEN1_1TO0_INT_ST + *******Description*********** + 9 + 1 + read-only + + + SLC1_TOKEN0_0TO1_INT_ST + *******Description*********** + 10 + 1 + read-only + + + SLC1_TOKEN1_0TO1_INT_ST + *******Description*********** + 11 + 1 + read-only + + + SLC1HOST_RX_SOF_INT_ST + *******Description*********** + 12 + 1 + read-only + + + SLC1HOST_RX_EOF_INT_ST + *******Description*********** + 13 + 1 + read-only + + + SLC1HOST_RX_START_INT_ST + *******Description*********** + 14 + 1 + read-only + + + SLC1HOST_TX_START_INT_ST + *******Description*********** + 15 + 1 + read-only + + + SLC1_RX_UDF_INT_ST + *******Description*********** + 16 + 1 + read-only + + + SLC1_TX_OVF_INT_ST + *******Description*********** + 17 + 1 + read-only + + + SLC1_RX_PF_VALID_INT_ST + *******Description*********** + 18 + 1 + read-only + + + SLC1_EXT_BIT0_INT_ST + *******Description*********** + 19 + 1 + read-only + + + SLC1_EXT_BIT1_INT_ST + *******Description*********** + 20 + 1 + read-only + + + SLC1_EXT_BIT2_INT_ST + *******Description*********** + 21 + 1 + read-only + + + SLC1_EXT_BIT3_INT_ST + *******Description*********** + 22 + 1 + read-only + + + SLC1_WIFI_RX_NEW_PACKET_INT_ST + *******Description*********** + 23 + 1 + read-only + + + SLC1_HOST_RD_RETRY_INT_ST + *******Description*********** + 24 + 1 + read-only + + + SLC1_BT_RX_NEW_PACKET_INT_ST + *******Description*********** + 25 + 1 + read-only + + + + + PKT_LEN + *******Description*********** + 0x60 + 0x20 + + + HOSTSLCHOST_SLC0_LEN + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + STATE_W0 + *******Description*********** + 0x64 + 0x20 + + + SLCHOST_STATE0 + *******Description*********** + 0 + 8 + read-only + + + SLCHOST_STATE1 + *******Description*********** + 8 + 8 + read-only + + + SLCHOST_STATE2 + *******Description*********** + 16 + 8 + read-only + + + SLCHOST_STATE3 + *******Description*********** + 24 + 8 + read-only + + + + + STATE_W1 + *******Description*********** + 0x68 + 0x20 + + + SLCHOST_STATE4 + *******Description*********** + 0 + 8 + read-only + + + SLCHOST_STATE5 + *******Description*********** + 8 + 8 + read-only + + + SLCHOST_STATE6 + *******Description*********** + 16 + 8 + read-only + + + SLCHOST_STATE7 + *******Description*********** + 24 + 8 + read-only + + + + + CONF_W0 + *******Description*********** + 0x6C + 0x20 + + + SLCHOST_CONF0 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF1 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF2 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF3 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W1 + *******Description*********** + 0x70 + 0x20 + + + SLCHOST_CONF4 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF5 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF6 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF7 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W2 + *******Description*********** + 0x74 + 0x20 + + + SLCHOST_CONF8 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF9 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF10 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF11 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W3 + *******Description*********** + 0x78 + 0x20 + 0x000000C0 + + + SLCHOST_CONF12 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF13 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF14 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF15 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W4 + *******Description*********** + 0x7C + 0x20 + 0x000001FF + + + SLCHOST_CONF16 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF17 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF18 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF19 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W5 + *******Description*********** + 0x80 + 0x20 + + + SLCHOST_CONF20 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF21 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF22 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF23 + *******Description*********** + 24 + 8 + read-write + + + + + WIN_CMD + *******Description*********** + 0x84 + 0x20 + + + SLCHOST_WIN_CMD + *******Description*********** + 0 + 16 + read-write + + + + + CONF_W6 + *******Description*********** + 0x88 + 0x20 + + + SLCHOST_CONF24 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF25 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF26 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF27 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W7 + *******Description*********** + 0x8C + 0x20 + + + SLCHOST_CONF28 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF29 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF30 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF31 + *******Description*********** + 24 + 8 + read-write + + + + + PKT_LEN0 + *******Description*********** + 0x90 + 0x20 + + + HOSTSLCHOST_SLC0_LEN0 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN0_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + PKT_LEN1 + *******Description*********** + 0x94 + 0x20 + + + HOSTSLCHOST_SLC0_LEN1 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN1_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + PKT_LEN2 + *******Description*********** + 0x98 + 0x20 + + + HOSTSLCHOST_SLC0_LEN2 + *******Description*********** + 0 + 20 + read-only + + + HOSTSLCHOST_SLC0_LEN2_CHECK + *******Description*********** + 20 + 12 + read-only + + + + + CONF_W8 + *******Description*********** + 0x9C + 0x20 + + + SLCHOST_CONF32 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF33 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF34 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF35 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W9 + *******Description*********** + 0xA0 + 0x20 + + + SLCHOST_CONF36 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF37 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF38 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF39 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W10 + *******Description*********** + 0xA4 + 0x20 + + + SLCHOST_CONF40 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF41 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF42 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF43 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W11 + *******Description*********** + 0xA8 + 0x20 + + + SLCHOST_CONF44 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF45 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF46 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF47 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W12 + *******Description*********** + 0xAC + 0x20 + + + SLCHOST_CONF48 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF49 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF50 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF51 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W13 + *******Description*********** + 0xB0 + 0x20 + + + SLCHOST_CONF52 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF53 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF54 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF55 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W14 + *******Description*********** + 0xB4 + 0x20 + + + SLCHOST_CONF56 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF57 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF58 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF59 + *******Description*********** + 24 + 8 + read-write + + + + + CONF_W15 + *******Description*********** + 0xB8 + 0x20 + + + SLCHOST_CONF60 + *******Description*********** + 0 + 8 + read-write + + + SLCHOST_CONF61 + *******Description*********** + 8 + 8 + read-write + + + SLCHOST_CONF62 + *******Description*********** + 16 + 8 + read-write + + + SLCHOST_CONF63 + *******Description*********** + 24 + 8 + read-write + + + + + CHECK_SUM0 + *******Description*********** + 0xBC + 0x20 + + + SLCHOST_CHECK_SUM0 + *******Description*********** + 0 + 32 + read-only + + + + + CHECK_SUM1 + *******Description*********** + 0xC0 + 0x20 + 0x0000013F + + + SLCHOST_CHECK_SUM1 + *******Description*********** + 0 + 32 + read-only + + + + + SLC1HOST_TOKEN_RDATA + *******Description*********** + 0xC4 + 0x20 + + + SLC1_TOKEN0 + *******Description*********** + 0 + 12 + read-only + + + SLC1_RX_PF_VALID + *******Description*********** + 12 + 1 + read-only + + + HOSTSLCHOST_SLC1_TOKEN1 + *******Description*********** + 16 + 12 + read-only + + + SLC1_RX_PF_EOF + *******Description*********** + 28 + 4 + read-only + + + + + SLC0HOST_TOKEN_WDATA + *******Description*********** + 0xC8 + 0x20 + + + SLC0HOST_TOKEN0_WD + *******Description*********** + 0 + 12 + read-write + + + SLC0HOST_TOKEN1_WD + *******Description*********** + 16 + 12 + read-write + + + + + SLC1HOST_TOKEN_WDATA + *******Description*********** + 0xCC + 0x20 + + + SLC1HOST_TOKEN0_WD + *******Description*********** + 0 + 12 + read-write + + + SLC1HOST_TOKEN1_WD + *******Description*********** + 16 + 12 + read-write + + + + + TOKEN_CON + *******Description*********** + 0xD0 + 0x20 + + + SLC0HOST_TOKEN0_DEC + *******Description*********** + 0 + 1 + write-only + + + SLC0HOST_TOKEN1_DEC + *******Description*********** + 1 + 1 + write-only + + + SLC0HOST_TOKEN0_WR + *******Description*********** + 2 + 1 + write-only + + + SLC0HOST_TOKEN1_WR + *******Description*********** + 3 + 1 + write-only + + + SLC1HOST_TOKEN0_DEC + *******Description*********** + 4 + 1 + write-only + + + SLC1HOST_TOKEN1_DEC + *******Description*********** + 5 + 1 + write-only + + + SLC1HOST_TOKEN0_WR + *******Description*********** + 6 + 1 + write-only + + + SLC1HOST_TOKEN1_WR + *******Description*********** + 7 + 1 + write-only + + + SLC0HOST_LEN_WR + *******Description*********** + 8 + 1 + write-only + + + + + SLC0HOST_INT_CLR + *******Description*********** + 0xD4 + 0x20 + + + SLC0_TOHOST_BIT0_INT_CLR + *******Description*********** + 0 + 1 + write-only + + + SLC0_TOHOST_BIT1_INT_CLR + *******Description*********** + 1 + 1 + write-only + + + SLC0_TOHOST_BIT2_INT_CLR + *******Description*********** + 2 + 1 + write-only + + + SLC0_TOHOST_BIT3_INT_CLR + *******Description*********** + 3 + 1 + write-only + + + SLC0_TOHOST_BIT4_INT_CLR + *******Description*********** + 4 + 1 + write-only + + + SLC0_TOHOST_BIT5_INT_CLR + *******Description*********** + 5 + 1 + write-only + + + SLC0_TOHOST_BIT6_INT_CLR + *******Description*********** + 6 + 1 + write-only + + + SLC0_TOHOST_BIT7_INT_CLR + *******Description*********** + 7 + 1 + write-only + + + SLC0_TOKEN0_1TO0_INT_CLR + *******Description*********** + 8 + 1 + write-only + + + SLC0_TOKEN1_1TO0_INT_CLR + *******Description*********** + 9 + 1 + write-only + + + SLC0_TOKEN0_0TO1_INT_CLR + *******Description*********** + 10 + 1 + write-only + + + SLC0_TOKEN1_0TO1_INT_CLR + *******Description*********** + 11 + 1 + write-only + + + SLC0HOST_RX_SOF_INT_CLR + *******Description*********** + 12 + 1 + write-only + + + SLC0HOST_RX_EOF_INT_CLR + *******Description*********** + 13 + 1 + write-only + + + SLC0HOST_RX_START_INT_CLR + *******Description*********** + 14 + 1 + write-only + + + SLC0HOST_TX_START_INT_CLR + *******Description*********** + 15 + 1 + write-only + + + SLC0_RX_UDF_INT_CLR + *******Description*********** + 16 + 1 + write-only + + + SLC0_TX_OVF_INT_CLR + *******Description*********** + 17 + 1 + write-only + + + SLC0_RX_PF_VALID_INT_CLR + *******Description*********** + 18 + 1 + write-only + + + SLC0_EXT_BIT0_INT_CLR + *******Description*********** + 19 + 1 + write-only + + + SLC0_EXT_BIT1_INT_CLR + *******Description*********** + 20 + 1 + write-only + + + SLC0_EXT_BIT2_INT_CLR + *******Description*********** + 21 + 1 + write-only + + + SLC0_EXT_BIT3_INT_CLR + *******Description*********** + 22 + 1 + write-only + + + SLC0_RX_NEW_PACKET_INT_CLR + *******Description*********** + 23 + 1 + write-only + + + SLC0_HOST_RD_RETRY_INT_CLR + *******Description*********** + 24 + 1 + write-only + + + GPIO_SDIO_INT_CLR + *******Description*********** + 25 + 1 + write-only + + + + + SLC1HOST_INT_CLR + *******Description*********** + 0xD8 + 0x20 + + + SLC1_TOHOST_BIT0_INT_CLR + *******Description*********** + 0 + 1 + write-only + + + SLC1_TOHOST_BIT1_INT_CLR + *******Description*********** + 1 + 1 + write-only + + + SLC1_TOHOST_BIT2_INT_CLR + *******Description*********** + 2 + 1 + write-only + + + SLC1_TOHOST_BIT3_INT_CLR + *******Description*********** + 3 + 1 + write-only + + + SLC1_TOHOST_BIT4_INT_CLR + *******Description*********** + 4 + 1 + write-only + + + SLC1_TOHOST_BIT5_INT_CLR + *******Description*********** + 5 + 1 + write-only + + + SLC1_TOHOST_BIT6_INT_CLR + *******Description*********** + 6 + 1 + write-only + + + SLC1_TOHOST_BIT7_INT_CLR + *******Description*********** + 7 + 1 + write-only + + + SLC1_TOKEN0_1TO0_INT_CLR + *******Description*********** + 8 + 1 + write-only + + + SLC1_TOKEN1_1TO0_INT_CLR + *******Description*********** + 9 + 1 + write-only + + + SLC1_TOKEN0_0TO1_INT_CLR + *******Description*********** + 10 + 1 + write-only + + + SLC1_TOKEN1_0TO1_INT_CLR + *******Description*********** + 11 + 1 + write-only + + + SLC1HOST_RX_SOF_INT_CLR + *******Description*********** + 12 + 1 + write-only + + + SLC1HOST_RX_EOF_INT_CLR + *******Description*********** + 13 + 1 + write-only + + + SLC1HOST_RX_START_INT_CLR + *******Description*********** + 14 + 1 + write-only + + + SLC1HOST_TX_START_INT_CLR + *******Description*********** + 15 + 1 + write-only + + + SLC1_RX_UDF_INT_CLR + *******Description*********** + 16 + 1 + write-only + + + SLC1_TX_OVF_INT_CLR + *******Description*********** + 17 + 1 + write-only + + + SLC1_RX_PF_VALID_INT_CLR + *******Description*********** + 18 + 1 + write-only + + + SLC1_EXT_BIT0_INT_CLR + *******Description*********** + 19 + 1 + write-only + + + SLC1_EXT_BIT1_INT_CLR + *******Description*********** + 20 + 1 + write-only + + + SLC1_EXT_BIT2_INT_CLR + *******Description*********** + 21 + 1 + write-only + + + SLC1_EXT_BIT3_INT_CLR + *******Description*********** + 22 + 1 + write-only + + + SLC1_WIFI_RX_NEW_PACKET_INT_CLR + *******Description*********** + 23 + 1 + write-only + + + SLC1_HOST_RD_RETRY_INT_CLR + *******Description*********** + 24 + 1 + write-only + + + SLC1_BT_RX_NEW_PACKET_INT_CLR + *******Description*********** + 25 + 1 + write-only + + + + + SLC0HOST_FUNC1_INT_ENA + *******Description*********** + 0xDC + 0x20 + + + FN1_SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN1_SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN1_SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN1_SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN1_SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN1_SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN1_SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN1_SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN1_SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN1_SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN1_SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN1_SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN1_SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN1_SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN1_SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN1_SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN1_SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN1_SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN1_SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN1_GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_FUNC1_INT_ENA + *******Description*********** + 0xE0 + 0x20 + + + FN1_SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN1_SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN1_SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN1_SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN1_SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN1_SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN1_SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN1_SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN1_SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN1_SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN1_SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN1_SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN1_SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN1_SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN1_SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN1_SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN1_SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN1_SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_FUNC2_INT_ENA + *******Description*********** + 0xE4 + 0x20 + + + FN2_SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN2_SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN2_SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN2_SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN2_SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN2_SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN2_SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN2_SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN2_SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN2_SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN2_SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN2_SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN2_SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN2_SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN2_SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN2_SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN2_SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN2_SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN2_SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN2_GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_FUNC2_INT_ENA + *******Description*********** + 0xE8 + 0x20 + + + FN2_SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + FN2_SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + FN2_SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + FN2_SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + FN2_SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + FN2_SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + FN2_SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + FN2_SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + FN2_SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + FN2_SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + FN2_SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + FN2_SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + FN2_SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + FN2_SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + FN2_SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + FN2_SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + FN2_SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + FN2_SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_INT_ENA + *******Description*********** + 0xEC + 0x20 + + + SLC0_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + SLC0_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + SLC0_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + SLC0_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + SLC0_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + SLC0_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + SLC0_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + SLC0_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + SLC0_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + SLC0_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + SLC0_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + SLC0_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + SLC0HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + SLC0HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + SLC0HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + SLC0HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + SLC0_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + SLC0_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + SLC0_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + SLC0_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + SLC0_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + SLC0_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + SLC0_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + SLC0_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + SLC0_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + GPIO_SDIO_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_INT_ENA + *******Description*********** + 0xF0 + 0x20 + + + SLC1_TOHOST_BIT0_INT_ENA + *******Description*********** + 0 + 1 + read-write + + + SLC1_TOHOST_BIT1_INT_ENA + *******Description*********** + 1 + 1 + read-write + + + SLC1_TOHOST_BIT2_INT_ENA + *******Description*********** + 2 + 1 + read-write + + + SLC1_TOHOST_BIT3_INT_ENA + *******Description*********** + 3 + 1 + read-write + + + SLC1_TOHOST_BIT4_INT_ENA + *******Description*********** + 4 + 1 + read-write + + + SLC1_TOHOST_BIT5_INT_ENA + *******Description*********** + 5 + 1 + read-write + + + SLC1_TOHOST_BIT6_INT_ENA + *******Description*********** + 6 + 1 + read-write + + + SLC1_TOHOST_BIT7_INT_ENA + *******Description*********** + 7 + 1 + read-write + + + SLC1_TOKEN0_1TO0_INT_ENA + *******Description*********** + 8 + 1 + read-write + + + SLC1_TOKEN1_1TO0_INT_ENA + *******Description*********** + 9 + 1 + read-write + + + SLC1_TOKEN0_0TO1_INT_ENA + *******Description*********** + 10 + 1 + read-write + + + SLC1_TOKEN1_0TO1_INT_ENA + *******Description*********** + 11 + 1 + read-write + + + SLC1HOST_RX_SOF_INT_ENA + *******Description*********** + 12 + 1 + read-write + + + SLC1HOST_RX_EOF_INT_ENA + *******Description*********** + 13 + 1 + read-write + + + SLC1HOST_RX_START_INT_ENA + *******Description*********** + 14 + 1 + read-write + + + SLC1HOST_TX_START_INT_ENA + *******Description*********** + 15 + 1 + read-write + + + SLC1_RX_UDF_INT_ENA + *******Description*********** + 16 + 1 + read-write + + + SLC1_TX_OVF_INT_ENA + *******Description*********** + 17 + 1 + read-write + + + SLC1_RX_PF_VALID_INT_ENA + *******Description*********** + 18 + 1 + read-write + + + SLC1_EXT_BIT0_INT_ENA + *******Description*********** + 19 + 1 + read-write + + + SLC1_EXT_BIT1_INT_ENA + *******Description*********** + 20 + 1 + read-write + + + SLC1_EXT_BIT2_INT_ENA + *******Description*********** + 21 + 1 + read-write + + + SLC1_EXT_BIT3_INT_ENA + *******Description*********** + 22 + 1 + read-write + + + SLC1_WIFI_RX_NEW_PACKET_INT_ENA + *******Description*********** + 23 + 1 + read-write + + + SLC1_HOST_RD_RETRY_INT_ENA + *******Description*********** + 24 + 1 + read-write + + + SLC1_BT_RX_NEW_PACKET_INT_ENA + *******Description*********** + 25 + 1 + read-write + + + + + SLC0HOST_RX_INFOR + *******Description*********** + 0xF4 + 0x20 + + + SLC0HOST_RX_INFOR + *******Description*********** + 0 + 20 + read-write + + + + + SLC1HOST_RX_INFOR + *******Description*********** + 0xF8 + 0x20 + + + SLC1HOST_RX_INFOR + *******Description*********** + 0 + 20 + read-write + + + + + SLC0HOST_LEN_WD + *******Description*********** + 0xFC + 0x20 + + + SLC0HOST_LEN_WD + *******Description*********** + 0 + 32 + read-write + + + + + SLC_APBWIN_WDATA + *******Description*********** + 0x100 + 0x20 + + + SLC_APBWIN_WDATA + *******Description*********** + 0 + 32 + read-write + + + + + SLC_APBWIN_CONF + *******Description*********** + 0x104 + 0x20 + + + SLC_APBWIN_ADDR + *******Description*********** + 0 + 28 + read-write + + + SLC_APBWIN_WR + *******Description*********** + 28 + 1 + read-write + + + SLC_APBWIN_START + *******Description*********** + 29 + 1 + read-write + + + + + SLC_APBWIN_RDATA + *******Description*********** + 0x108 + 0x20 + + + SLC_APBWIN_RDATA + *******Description*********** + 0 + 32 + read-only + + + + + RDCLR0 + *******Description*********** + 0x10C + 0x20 + 0x0003C044 + + + SLCHOST_SLC0_BIT7_CLRADDR + *******Description*********** + 0 + 9 + read-write + + + SLCHOST_SLC0_BIT6_CLRADDR + *******Description*********** + 9 + 9 + read-write + + + + + RDCLR1 + *******Description*********** + 0x110 + 0x20 + 0x0003C1E0 + + + SLCHOST_SLC1_BIT7_CLRADDR + *******Description*********** + 0 + 9 + read-write + + + SLCHOST_SLC1_BIT6_CLRADDR + *******Description*********** + 9 + 9 + read-write + + + + + SLC0HOST_INT_ENA1 + *******Description*********** + 0x114 + 0x20 + + + SLC0_TOHOST_BIT0_INT_ENA1 + *******Description*********** + 0 + 1 + read-write + + + SLC0_TOHOST_BIT1_INT_ENA1 + *******Description*********** + 1 + 1 + read-write + + + SLC0_TOHOST_BIT2_INT_ENA1 + *******Description*********** + 2 + 1 + read-write + + + SLC0_TOHOST_BIT3_INT_ENA1 + *******Description*********** + 3 + 1 + read-write + + + SLC0_TOHOST_BIT4_INT_ENA1 + *******Description*********** + 4 + 1 + read-write + + + SLC0_TOHOST_BIT5_INT_ENA1 + *******Description*********** + 5 + 1 + read-write + + + SLC0_TOHOST_BIT6_INT_ENA1 + *******Description*********** + 6 + 1 + read-write + + + SLC0_TOHOST_BIT7_INT_ENA1 + *******Description*********** + 7 + 1 + read-write + + + SLC0_TOKEN0_1TO0_INT_ENA1 + *******Description*********** + 8 + 1 + read-write + + + SLC0_TOKEN1_1TO0_INT_ENA1 + *******Description*********** + 9 + 1 + read-write + + + SLC0_TOKEN0_0TO1_INT_ENA1 + *******Description*********** + 10 + 1 + read-write + + + SLC0_TOKEN1_0TO1_INT_ENA1 + *******Description*********** + 11 + 1 + read-write + + + SLC0HOST_RX_SOF_INT_ENA1 + *******Description*********** + 12 + 1 + read-write + + + SLC0HOST_RX_EOF_INT_ENA1 + *******Description*********** + 13 + 1 + read-write + + + SLC0HOST_RX_START_INT_ENA1 + *******Description*********** + 14 + 1 + read-write + + + SLC0HOST_TX_START_INT_ENA1 + *******Description*********** + 15 + 1 + read-write + + + SLC0_RX_UDF_INT_ENA1 + *******Description*********** + 16 + 1 + read-write + + + SLC0_TX_OVF_INT_ENA1 + *******Description*********** + 17 + 1 + read-write + + + SLC0_RX_PF_VALID_INT_ENA1 + *******Description*********** + 18 + 1 + read-write + + + SLC0_EXT_BIT0_INT_ENA1 + *******Description*********** + 19 + 1 + read-write + + + SLC0_EXT_BIT1_INT_ENA1 + *******Description*********** + 20 + 1 + read-write + + + SLC0_EXT_BIT2_INT_ENA1 + *******Description*********** + 21 + 1 + read-write + + + SLC0_EXT_BIT3_INT_ENA1 + *******Description*********** + 22 + 1 + read-write + + + SLC0_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 23 + 1 + read-write + + + SLC0_HOST_RD_RETRY_INT_ENA1 + *******Description*********** + 24 + 1 + read-write + + + GPIO_SDIO_INT_ENA1 + *******Description*********** + 25 + 1 + read-write + + + + + SLC1HOST_INT_ENA1 + *******Description*********** + 0x118 + 0x20 + + + SLC1_TOHOST_BIT0_INT_ENA1 + *******Description*********** + 0 + 1 + read-write + + + SLC1_TOHOST_BIT1_INT_ENA1 + *******Description*********** + 1 + 1 + read-write + + + SLC1_TOHOST_BIT2_INT_ENA1 + *******Description*********** + 2 + 1 + read-write + + + SLC1_TOHOST_BIT3_INT_ENA1 + *******Description*********** + 3 + 1 + read-write + + + SLC1_TOHOST_BIT4_INT_ENA1 + *******Description*********** + 4 + 1 + read-write + + + SLC1_TOHOST_BIT5_INT_ENA1 + *******Description*********** + 5 + 1 + read-write + + + SLC1_TOHOST_BIT6_INT_ENA1 + *******Description*********** + 6 + 1 + read-write + + + SLC1_TOHOST_BIT7_INT_ENA1 + *******Description*********** + 7 + 1 + read-write + + + SLC1_TOKEN0_1TO0_INT_ENA1 + *******Description*********** + 8 + 1 + read-write + + + SLC1_TOKEN1_1TO0_INT_ENA1 + *******Description*********** + 9 + 1 + read-write + + + SLC1_TOKEN0_0TO1_INT_ENA1 + *******Description*********** + 10 + 1 + read-write + + + SLC1_TOKEN1_0TO1_INT_ENA1 + *******Description*********** + 11 + 1 + read-write + + + SLC1HOST_RX_SOF_INT_ENA1 + *******Description*********** + 12 + 1 + read-write + + + SLC1HOST_RX_EOF_INT_ENA1 + *******Description*********** + 13 + 1 + read-write + + + SLC1HOST_RX_START_INT_ENA1 + *******Description*********** + 14 + 1 + read-write + + + SLC1HOST_TX_START_INT_ENA1 + *******Description*********** + 15 + 1 + read-write + + + SLC1_RX_UDF_INT_ENA1 + *******Description*********** + 16 + 1 + read-write + + + SLC1_TX_OVF_INT_ENA1 + *******Description*********** + 17 + 1 + read-write + + + SLC1_RX_PF_VALID_INT_ENA1 + *******Description*********** + 18 + 1 + read-write + + + SLC1_EXT_BIT0_INT_ENA1 + *******Description*********** + 19 + 1 + read-write + + + SLC1_EXT_BIT1_INT_ENA1 + *******Description*********** + 20 + 1 + read-write + + + SLC1_EXT_BIT2_INT_ENA1 + *******Description*********** + 21 + 1 + read-write + + + SLC1_EXT_BIT3_INT_ENA1 + *******Description*********** + 22 + 1 + read-write + + + SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 23 + 1 + read-write + + + SLC1_HOST_RD_RETRY_INT_ENA1 + *******Description*********** + 24 + 1 + read-write + + + SLC1_BT_RX_NEW_PACKET_INT_ENA1 + *******Description*********** + 25 + 1 + read-write + + + + + SLCHOSTDATE + *******Description*********** + 0x178 + 0x20 + 0x21060700 + + + SLCHOST_DATE + *******Description*********** + 0 + 32 + read-write + + + + + SLCHOSTID + *******Description*********** + 0x17C + 0x20 + 0x00000600 + + + SLCHOST_ID + *******Description*********** + 0 + 32 + read-write + + + + + CONF + *******Description*********** + 0x1F0 + 0x20 + + + FRC_SDIO11 + *******Description*********** + 0 + 5 + read-write + + + FRC_SDIO20 + *******Description*********** + 5 + 5 + read-write + + + FRC_NEG_SAMP + *******Description*********** + 10 + 5 + read-write + + + FRC_POS_SAMP + *******Description*********** + 15 + 5 + read-write + + + FRC_QUICK_IN + *******Description*********** + 20 + 5 + read-write + + + SDIO20_INT_DELAY + *******Description*********** + 25 + 1 + read-write + + + SDIO_PAD_PULLUP + *******Description*********** + 26 + 1 + read-write + + + HSPEED_CON_EN + *******Description*********** + 27 + 1 + read-write + + + + + INF_ST + *******Description*********** + 0x1F4 + 0x20 + + + SDIO20_MODE + *******Description*********** + 0 + 5 + read-only + + + SDIO_NEG_SAMP + *******Description*********** + 5 + 5 + read-only + + + SDIO_QUICK_IN + *******Description*********** + 10 + 5 + read-only + + + DLL_ON_SW + dll is controlled by software + 15 + 1 + read-write + + + DLL_ON + Software dll on + 16 + 1 + read-write + + + CLK_MODE_SW + dll clock mode is controlled by software + 17 + 1 + read-write + + + CLK_MODE + Software set clock mode + 18 + 2 + read-write + + + + + + + SOC_ETM + Peripheral SOC_ETM + SOC_ETM + 0x60013000 + + 0x0 + 0x1B0 + registers + + + + CH_ENA_AD0 + channel enable register + 0x0 + 0x20 + + + CH_ENA0 + ch0 enable + 0 + 1 + read-write + + + CH_ENA1 + ch1 enable + 1 + 1 + read-write + + + CH_ENA2 + ch2 enable + 2 + 1 + read-write + + + CH_ENA3 + ch3 enable + 3 + 1 + read-write + + + CH_ENA4 + ch4 enable + 4 + 1 + read-write + + + CH_ENA5 + ch5 enable + 5 + 1 + read-write + + + CH_ENA6 + ch6 enable + 6 + 1 + read-write + + + CH_ENA7 + ch7 enable + 7 + 1 + read-write + + + CH_ENA8 + ch8 enable + 8 + 1 + read-write + + + CH_ENA9 + ch9 enable + 9 + 1 + read-write + + + CH_ENA10 + ch10 enable + 10 + 1 + read-write + + + CH_ENA11 + ch11 enable + 11 + 1 + read-write + + + CH_ENA12 + ch12 enable + 12 + 1 + read-write + + + CH_ENA13 + ch13 enable + 13 + 1 + read-write + + + CH_ENA14 + ch14 enable + 14 + 1 + read-write + + + CH_ENA15 + ch15 enable + 15 + 1 + read-write + + + CH_ENA16 + ch16 enable + 16 + 1 + read-write + + + CH_ENA17 + ch17 enable + 17 + 1 + read-write + + + CH_ENA18 + ch18 enable + 18 + 1 + read-write + + + CH_ENA19 + ch19 enable + 19 + 1 + read-write + + + CH_ENA20 + ch20 enable + 20 + 1 + read-write + + + CH_ENA21 + ch21 enable + 21 + 1 + read-write + + + CH_ENA22 + ch22 enable + 22 + 1 + read-write + + + CH_ENA23 + ch23 enable + 23 + 1 + read-write + + + CH_ENA24 + ch24 enable + 24 + 1 + read-write + + + CH_ENA25 + ch25 enable + 25 + 1 + read-write + + + CH_ENA26 + ch26 enable + 26 + 1 + read-write + + + CH_ENA27 + ch27 enable + 27 + 1 + read-write + + + CH_ENA28 + ch28 enable + 28 + 1 + read-write + + + CH_ENA29 + ch29 enable + 29 + 1 + read-write + + + CH_ENA30 + ch30 enable + 30 + 1 + read-write + + + CH_ENA31 + ch31 enable + 31 + 1 + read-write + + + + + CH_ENA_AD0_SET + channel enable set register + 0x4 + 0x20 + + + CH_SET0 + ch0 set + 0 + 1 + write-only + + + CH_SET1 + ch1 set + 1 + 1 + write-only + + + CH_SET2 + ch2 set + 2 + 1 + write-only + + + CH_SET3 + ch3 set + 3 + 1 + write-only + + + CH_SET4 + ch4 set + 4 + 1 + write-only + + + CH_SET5 + ch5 set + 5 + 1 + write-only + + + CH_SET6 + ch6 set + 6 + 1 + write-only + + + CH_SET7 + ch7 set + 7 + 1 + write-only + + + CH_SET8 + ch8 set + 8 + 1 + write-only + + + CH_SET9 + ch9 set + 9 + 1 + write-only + + + CH_SET10 + ch10 set + 10 + 1 + write-only + + + CH_SET11 + ch11 set + 11 + 1 + write-only + + + CH_SET12 + ch12 set + 12 + 1 + write-only + + + CH_SET13 + ch13 set + 13 + 1 + write-only + + + CH_SET14 + ch14 set + 14 + 1 + write-only + + + CH_SET15 + ch15 set + 15 + 1 + write-only + + + CH_SET16 + ch16 set + 16 + 1 + write-only + + + CH_SET17 + ch17 set + 17 + 1 + write-only + + + CH_SET18 + ch18 set + 18 + 1 + write-only + + + CH_SET19 + ch19 set + 19 + 1 + write-only + + + CH_SET20 + ch20 set + 20 + 1 + write-only + + + CH_SET21 + ch21 set + 21 + 1 + write-only + + + CH_SET22 + ch22 set + 22 + 1 + write-only + + + CH_SET23 + ch23 set + 23 + 1 + write-only + + + CH_SET24 + ch24 set + 24 + 1 + write-only + + + CH_SET25 + ch25 set + 25 + 1 + write-only + + + CH_SET26 + ch26 set + 26 + 1 + write-only + + + CH_SET27 + ch27 set + 27 + 1 + write-only + + + CH_SET28 + ch28 set + 28 + 1 + write-only + + + CH_SET29 + ch29 set + 29 + 1 + write-only + + + CH_SET30 + ch30 set + 30 + 1 + write-only + + + CH_SET31 + ch31 set + 31 + 1 + write-only + + + + + CH_ENA_AD0_CLR + channel enable clear register + 0x8 + 0x20 + + + CH_CLR0 + ch0 clear + 0 + 1 + write-only + + + CH_CLR1 + ch1 clear + 1 + 1 + write-only + + + CH_CLR2 + ch2 clear + 2 + 1 + write-only + + + CH_CLR3 + ch3 clear + 3 + 1 + write-only + + + CH_CLR4 + ch4 clear + 4 + 1 + write-only + + + CH_CLR5 + ch5 clear + 5 + 1 + write-only + + + CH_CLR6 + ch6 clear + 6 + 1 + write-only + + + CH_CLR7 + ch7 clear + 7 + 1 + write-only + + + CH_CLR8 + ch8 clear + 8 + 1 + write-only + + + CH_CLR9 + ch9 clear + 9 + 1 + write-only + + + CH_CLR10 + ch10 clear + 10 + 1 + write-only + + + CH_CLR11 + ch11 clear + 11 + 1 + write-only + + + CH_CLR12 + ch12 clear + 12 + 1 + write-only + + + CH_CLR13 + ch13 clear + 13 + 1 + write-only + + + CH_CLR14 + ch14 clear + 14 + 1 + write-only + + + CH_CLR15 + ch15 clear + 15 + 1 + write-only + + + CH_CLR16 + ch16 clear + 16 + 1 + write-only + + + CH_CLR17 + ch17 clear + 17 + 1 + write-only + + + CH_CLR18 + ch18 clear + 18 + 1 + write-only + + + CH_CLR19 + ch19 clear + 19 + 1 + write-only + + + CH_CLR20 + ch20 clear + 20 + 1 + write-only + + + CH_CLR21 + ch21 clear + 21 + 1 + write-only + + + CH_CLR22 + ch22 clear + 22 + 1 + write-only + + + CH_CLR23 + ch23 clear + 23 + 1 + write-only + + + CH_CLR24 + ch24 clear + 24 + 1 + write-only + + + CH_CLR25 + ch25 clear + 25 + 1 + write-only + + + CH_CLR26 + ch26 clear + 26 + 1 + write-only + + + CH_CLR27 + ch27 clear + 27 + 1 + write-only + + + CH_CLR28 + ch28 clear + 28 + 1 + write-only + + + CH_CLR29 + ch29 clear + 29 + 1 + write-only + + + CH_CLR30 + ch30 clear + 30 + 1 + write-only + + + CH_CLR31 + ch31 clear + 31 + 1 + write-only + + + + + CH_ENA_AD1 + channel enable register + 0xC + 0x20 + + + CH_ENA32 + ch32 enable + 0 + 1 + read-write + + + CH_ENA33 + ch33 enable + 1 + 1 + read-write + + + CH_ENA34 + ch34 enable + 2 + 1 + read-write + + + CH_ENA35 + ch35 enable + 3 + 1 + read-write + + + CH_ENA36 + ch36 enable + 4 + 1 + read-write + + + CH_ENA37 + ch37 enable + 5 + 1 + read-write + + + CH_ENA38 + ch38 enable + 6 + 1 + read-write + + + CH_ENA39 + ch39 enable + 7 + 1 + read-write + + + CH_ENA40 + ch40 enable + 8 + 1 + read-write + + + CH_ENA41 + ch41 enable + 9 + 1 + read-write + + + CH_ENA42 + ch42 enable + 10 + 1 + read-write + + + CH_ENA43 + ch43 enable + 11 + 1 + read-write + + + CH_ENA44 + ch44 enable + 12 + 1 + read-write + + + CH_ENA45 + ch45 enable + 13 + 1 + read-write + + + CH_ENA46 + ch46 enable + 14 + 1 + read-write + + + CH_ENA47 + ch47 enable + 15 + 1 + read-write + + + CH_ENA48 + ch48 enable + 16 + 1 + read-write + + + CH_ENA49 + ch49 enable + 17 + 1 + read-write + + + + + CH_ENA_AD1_SET + channel enable set register + 0x10 + 0x20 + + + CH_SET32 + ch32 set + 0 + 1 + write-only + + + CH_SET33 + ch33 set + 1 + 1 + write-only + + + CH_SET34 + ch34 set + 2 + 1 + write-only + + + CH_SET35 + ch35 set + 3 + 1 + write-only + + + CH_SET36 + ch36 set + 4 + 1 + write-only + + + CH_SET37 + ch37 set + 5 + 1 + write-only + + + CH_SET38 + ch38 set + 6 + 1 + write-only + + + CH_SET39 + ch39 set + 7 + 1 + write-only + + + CH_SET40 + ch40 set + 8 + 1 + write-only + + + CH_SET41 + ch41 set + 9 + 1 + write-only + + + CH_SET42 + ch42 set + 10 + 1 + write-only + + + CH_SET43 + ch43 set + 11 + 1 + write-only + + + CH_SET44 + ch44 set + 12 + 1 + write-only + + + CH_SET45 + ch45 set + 13 + 1 + write-only + + + CH_SET46 + ch46 set + 14 + 1 + write-only + + + CH_SET47 + ch47 set + 15 + 1 + write-only + + + CH_SET48 + ch48 set + 16 + 1 + write-only + + + CH_SET49 + ch49 set + 17 + 1 + write-only + + + + + CH_ENA_AD1_CLR + channel enable clear register + 0x14 + 0x20 + + + CH_CLR32 + ch32 clear + 0 + 1 + write-only + + + CH_CLR33 + ch33 clear + 1 + 1 + write-only + + + CH_CLR34 + ch34 clear + 2 + 1 + write-only + + + CH_CLR35 + ch35 clear + 3 + 1 + write-only + + + CH_CLR36 + ch36 clear + 4 + 1 + write-only + + + CH_CLR37 + ch37 clear + 5 + 1 + write-only + + + CH_CLR38 + ch38 clear + 6 + 1 + write-only + + + CH_CLR39 + ch39 clear + 7 + 1 + write-only + + + CH_CLR40 + ch40 clear + 8 + 1 + write-only + + + CH_CLR41 + ch41 clear + 9 + 1 + write-only + + + CH_CLR42 + ch42 clear + 10 + 1 + write-only + + + CH_CLR43 + ch43 clear + 11 + 1 + write-only + + + CH_CLR44 + ch44 clear + 12 + 1 + write-only + + + CH_CLR45 + ch45 clear + 13 + 1 + write-only + + + CH_CLR46 + ch46 clear + 14 + 1 + write-only + + + CH_CLR47 + ch47 clear + 15 + 1 + write-only + + + CH_CLR48 + ch48 clear + 16 + 1 + write-only + + + CH_CLR49 + ch49 clear + 17 + 1 + write-only + + + + + CH0_EVT_ID + channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + channel5 event id register + 0x40 + 0x20 + + + CH5_EVT_ID + ch5_evt_id + 0 + 8 + read-write + + + + + CH5_TASK_ID + channel5 task id register + 0x44 + 0x20 + + + CH5_TASK_ID + ch5_task_id + 0 + 8 + read-write + + + + + CH6_EVT_ID + channel6 event id register + 0x48 + 0x20 + + + CH6_EVT_ID + ch6_evt_id + 0 + 8 + read-write + + + + + CH6_TASK_ID + channel6 task id register + 0x4C + 0x20 + + + CH6_TASK_ID + ch6_task_id + 0 + 8 + read-write + + + + + CH7_EVT_ID + channel7 event id register + 0x50 + 0x20 + + + CH7_EVT_ID + ch7_evt_id + 0 + 8 + read-write + + + + + CH7_TASK_ID + channel7 task id register + 0x54 + 0x20 + + + CH7_TASK_ID + ch7_task_id + 0 + 8 + read-write + + + + + CH8_EVT_ID + channel8 event id register + 0x58 + 0x20 + + + CH8_EVT_ID + ch8_evt_id + 0 + 8 + read-write + + + + + CH8_TASK_ID + channel8 task id register + 0x5C + 0x20 + + + CH8_TASK_ID + ch8_task_id + 0 + 8 + read-write + + + + + CH9_EVT_ID + channel9 event id register + 0x60 + 0x20 + + + CH9_EVT_ID + ch9_evt_id + 0 + 8 + read-write + + + + + CH9_TASK_ID + channel9 task id register + 0x64 + 0x20 + + + CH9_TASK_ID + ch9_task_id + 0 + 8 + read-write + + + + + CH10_EVT_ID + channel10 event id register + 0x68 + 0x20 + + + CH10_EVT_ID + ch10_evt_id + 0 + 8 + read-write + + + + + CH10_TASK_ID + channel10 task id register + 0x6C + 0x20 + + + CH10_TASK_ID + ch10_task_id + 0 + 8 + read-write + + + + + CH11_EVT_ID + channel11 event id register + 0x70 + 0x20 + + + CH11_EVT_ID + ch11_evt_id + 0 + 8 + read-write + + + + + CH11_TASK_ID + channel11 task id register + 0x74 + 0x20 + + + CH11_TASK_ID + ch11_task_id + 0 + 8 + read-write + + + + + CH12_EVT_ID + channel12 event id register + 0x78 + 0x20 + + + CH12_EVT_ID + ch12_evt_id + 0 + 8 + read-write + + + + + CH12_TASK_ID + channel12 task id register + 0x7C + 0x20 + + + CH12_TASK_ID + ch12_task_id + 0 + 8 + read-write + + + + + CH13_EVT_ID + channel13 event id register + 0x80 + 0x20 + + + CH13_EVT_ID + ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + ch13_task_id + 0 + 8 + read-write + + + + + CH14_EVT_ID + channel14 event id register + 0x88 + 0x20 + + + CH14_EVT_ID + ch14_evt_id + 0 + 8 + read-write + + + + + CH14_TASK_ID + channel14 task id register + 0x8C + 0x20 + + + CH14_TASK_ID + ch14_task_id + 0 + 8 + read-write + + + + + CH15_EVT_ID + channel15 event id register + 0x90 + 0x20 + + + CH15_EVT_ID + ch15_evt_id + 0 + 8 + read-write + + + + + CH15_TASK_ID + channel15 task id register + 0x94 + 0x20 + + + CH15_TASK_ID + ch15_task_id + 0 + 8 + read-write + + + + + CH16_EVT_ID + channel16 event id register + 0x98 + 0x20 + + + CH16_EVT_ID + ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + ch18_task_id + 0 + 8 + read-write + + + + + CH19_EVT_ID + channel19 event id register + 0xB0 + 0x20 + + + CH19_EVT_ID + ch19_evt_id + 0 + 8 + read-write + + + + + CH19_TASK_ID + channel19 task id register + 0xB4 + 0x20 + + + CH19_TASK_ID + ch19_task_id + 0 + 8 + read-write + + + + + CH20_EVT_ID + channel20 event id register + 0xB8 + 0x20 + + + CH20_EVT_ID + ch20_evt_id + 0 + 8 + read-write + + + + + CH20_TASK_ID + channel20 task id register + 0xBC + 0x20 + + + CH20_TASK_ID + ch20_task_id + 0 + 8 + read-write + + + + + CH21_EVT_ID + channel21 event id register + 0xC0 + 0x20 + + + CH21_EVT_ID + ch21_evt_id + 0 + 8 + read-write + + + + + CH21_TASK_ID + channel21 task id register + 0xC4 + 0x20 + + + CH21_TASK_ID + ch21_task_id + 0 + 8 + read-write + + + + + CH22_EVT_ID + channel22 event id register + 0xC8 + 0x20 + + + CH22_EVT_ID + ch22_evt_id + 0 + 8 + read-write + + + + + CH22_TASK_ID + channel22 task id register + 0xCC + 0x20 + + + CH22_TASK_ID + ch22_task_id + 0 + 8 + read-write + + + + + CH23_EVT_ID + channel23 event id register + 0xD0 + 0x20 + + + CH23_EVT_ID + ch23_evt_id + 0 + 8 + read-write + + + + + CH23_TASK_ID + channel23 task id register + 0xD4 + 0x20 + + + CH23_TASK_ID + ch23_task_id + 0 + 8 + read-write + + + + + CH24_EVT_ID + channel24 event id register + 0xD8 + 0x20 + + + CH24_EVT_ID + ch24_evt_id + 0 + 8 + read-write + + + + + CH24_TASK_ID + channel24 task id register + 0xDC + 0x20 + + + CH24_TASK_ID + ch24_task_id + 0 + 8 + read-write + + + + + CH25_EVT_ID + channel25 event id register + 0xE0 + 0x20 + + + CH25_EVT_ID + ch25_evt_id + 0 + 8 + read-write + + + + + CH25_TASK_ID + channel25 task id register + 0xE4 + 0x20 + + + CH25_TASK_ID + ch25_task_id + 0 + 8 + read-write + + + + + CH26_EVT_ID + channel26 event id register + 0xE8 + 0x20 + + + CH26_EVT_ID + ch26_evt_id + 0 + 8 + read-write + + + + + CH26_TASK_ID + channel26 task id register + 0xEC + 0x20 + + + CH26_TASK_ID + ch26_task_id + 0 + 8 + read-write + + + + + CH27_EVT_ID + channel27 event id register + 0xF0 + 0x20 + + + CH27_EVT_ID + ch27_evt_id + 0 + 8 + read-write + + + + + CH27_TASK_ID + channel27 task id register + 0xF4 + 0x20 + + + CH27_TASK_ID + ch27_task_id + 0 + 8 + read-write + + + + + CH28_EVT_ID + channel28 event id register + 0xF8 + 0x20 + + + CH28_EVT_ID + ch28_evt_id + 0 + 8 + read-write + + + + + CH28_TASK_ID + channel28 task id register + 0xFC + 0x20 + + + CH28_TASK_ID + ch28_task_id + 0 + 8 + read-write + + + + + CH29_EVT_ID + channel29 event id register + 0x100 + 0x20 + + + CH29_EVT_ID + ch29_evt_id + 0 + 8 + read-write + + + + + CH29_TASK_ID + channel29 task id register + 0x104 + 0x20 + + + CH29_TASK_ID + ch29_task_id + 0 + 8 + read-write + + + + + CH30_EVT_ID + channel30 event id register + 0x108 + 0x20 + + + CH30_EVT_ID + ch30_evt_id + 0 + 8 + read-write + + + + + CH30_TASK_ID + channel30 task id register + 0x10C + 0x20 + + + CH30_TASK_ID + ch30_task_id + 0 + 8 + read-write + + + + + CH31_EVT_ID + channel31 event id register + 0x110 + 0x20 + + + CH31_EVT_ID + ch31_evt_id + 0 + 8 + read-write + + + + + CH31_TASK_ID + channel31 task id register + 0x114 + 0x20 + + + CH31_TASK_ID + ch31_task_id + 0 + 8 + read-write + + + + + CH32_EVT_ID + channel32 event id register + 0x118 + 0x20 + + + CH32_EVT_ID + ch32_evt_id + 0 + 8 + read-write + + + + + CH32_TASK_ID + channel32 task id register + 0x11C + 0x20 + + + CH32_TASK_ID + ch32_task_id + 0 + 8 + read-write + + + + + CH33_EVT_ID + channel33 event id register + 0x120 + 0x20 + + + CH33_EVT_ID + ch33_evt_id + 0 + 8 + read-write + + + + + CH33_TASK_ID + channel33 task id register + 0x124 + 0x20 + + + CH33_TASK_ID + ch33_task_id + 0 + 8 + read-write + + + + + CH34_EVT_ID + channel34 event id register + 0x128 + 0x20 + + + CH34_EVT_ID + ch34_evt_id + 0 + 8 + read-write + + + + + CH34_TASK_ID + channel34 task id register + 0x12C + 0x20 + + + CH34_TASK_ID + ch34_task_id + 0 + 8 + read-write + + + + + CH35_EVT_ID + channel35 event id register + 0x130 + 0x20 + + + CH35_EVT_ID + ch35_evt_id + 0 + 8 + read-write + + + + + CH35_TASK_ID + channel35 task id register + 0x134 + 0x20 + + + CH35_TASK_ID + ch35_task_id + 0 + 8 + read-write + + + + + CH36_EVT_ID + channel36 event id register + 0x138 + 0x20 + + + CH36_EVT_ID + ch36_evt_id + 0 + 8 + read-write + + + + + CH36_TASK_ID + channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + ch36_task_id + 0 + 8 + read-write + + + + + CH37_EVT_ID + channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + ch37_evt_id + 0 + 8 + read-write + + + + + CH37_TASK_ID + channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + ch37_task_id + 0 + 8 + read-write + + + + + CH38_EVT_ID + channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + ch38_evt_id + 0 + 8 + read-write + + + + + CH38_TASK_ID + channel38 task id register + 0x14C + 0x20 + + + CH38_TASK_ID + ch38_task_id + 0 + 8 + read-write + + + + + CH39_EVT_ID + channel39 event id register + 0x150 + 0x20 + + + CH39_EVT_ID + ch39_evt_id + 0 + 8 + read-write + + + + + CH39_TASK_ID + channel39 task id register + 0x154 + 0x20 + + + CH39_TASK_ID + ch39_task_id + 0 + 8 + read-write + + + + + CH40_EVT_ID + channel40 event id register + 0x158 + 0x20 + + + CH40_EVT_ID + ch40_evt_id + 0 + 8 + read-write + + + + + CH40_TASK_ID + channel40 task id register + 0x15C + 0x20 + + + CH40_TASK_ID + ch40_task_id + 0 + 8 + read-write + + + + + CH41_EVT_ID + channel41 event id register + 0x160 + 0x20 + + + CH41_EVT_ID + ch41_evt_id + 0 + 8 + read-write + + + + + CH41_TASK_ID + channel41 task id register + 0x164 + 0x20 + + + CH41_TASK_ID + ch41_task_id + 0 + 8 + read-write + + + + + CH42_EVT_ID + channel42 event id register + 0x168 + 0x20 + + + CH42_EVT_ID + ch42_evt_id + 0 + 8 + read-write + + + + + CH42_TASK_ID + channel42 task id register + 0x16C + 0x20 + + + CH42_TASK_ID + ch42_task_id + 0 + 8 + read-write + + + + + CH43_EVT_ID + channel43 event id register + 0x170 + 0x20 + + + CH43_EVT_ID + ch43_evt_id + 0 + 8 + read-write + + + + + CH43_TASK_ID + channel43 task id register + 0x174 + 0x20 + + + CH43_TASK_ID + ch43_task_id + 0 + 8 + read-write + + + + + CH44_EVT_ID + channel44 event id register + 0x178 + 0x20 + + + CH44_EVT_ID + ch44_evt_id + 0 + 8 + read-write + + + + + CH44_TASK_ID + channel44 task id register + 0x17C + 0x20 + + + CH44_TASK_ID + ch44_task_id + 0 + 8 + read-write + + + + + CH45_EVT_ID + channel45 event id register + 0x180 + 0x20 + + + CH45_EVT_ID + ch45_evt_id + 0 + 8 + read-write + + + + + CH45_TASK_ID + channel45 task id register + 0x184 + 0x20 + + + CH45_TASK_ID + ch45_task_id + 0 + 8 + read-write + + + + + CH46_EVT_ID + channel46 event id register + 0x188 + 0x20 + + + CH46_EVT_ID + ch46_evt_id + 0 + 8 + read-write + + + + + CH46_TASK_ID + channel46 task id register + 0x18C + 0x20 + + + CH46_TASK_ID + ch46_task_id + 0 + 8 + read-write + + + + + CH47_EVT_ID + channel47 event id register + 0x190 + 0x20 + + + CH47_EVT_ID + ch47_evt_id + 0 + 8 + read-write + + + + + CH47_TASK_ID + channel47 task id register + 0x194 + 0x20 + + + CH47_TASK_ID + ch47_task_id + 0 + 8 + read-write + + + + + CH48_EVT_ID + channel48 event id register + 0x198 + 0x20 + + + CH48_EVT_ID + ch48_evt_id + 0 + 8 + read-write + + + + + CH48_TASK_ID + channel48 task id register + 0x19C + 0x20 + + + CH48_TASK_ID + ch48_task_id + 0 + 8 + read-write + + + + + CH49_EVT_ID + channel49 event id register + 0x1A0 + 0x20 + + + CH49_EVT_ID + ch49_evt_id + 0 + 8 + read-write + + + + + CH49_TASK_ID + channel49 task id register + 0x1A4 + 0x20 + + + CH49_TASK_ID + ch49_task_id + 0 + 8 + read-write + + + + + CLK_EN + etm clock enable register + 0x1A8 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + DATE + etm date register + 0x1AC + 0x20 + 0x02203092 + + + DATE + date + 0 + 28 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60002000 + + 0x0 + 0x138 + registers + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-only + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-only + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-only + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-only + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x00002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-only + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-only + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-only + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-only + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-only + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-only + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-only + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-only + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-only + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-only + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-only + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-only + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-only + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-only + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-only + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-only + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0xC0400000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-only + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-only + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-only + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-only + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-only + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-only + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-only + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-only + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-only + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-only + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-only + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-only + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-only + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-only + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-only + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-only + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-only + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-only + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-only + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-only + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-only + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-only + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-only + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-only + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-only + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-only + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-only + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash ACE section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash ACE section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash ACE section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash ACE section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM ACE section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM ACE section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 26 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-only + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-only + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-only + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 26 + 6 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + 0xFC000000 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-only + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-only + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-only + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-only + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-only + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-only + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-only + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-only + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-only + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-only + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-only + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-only + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-only + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-only + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-only + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-only + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-only + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-only + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-only + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-only + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-only + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-only + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-only + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-only + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 16 + 2 + read-only + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-only + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-only + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-only + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-only + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-only + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-only + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-only + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-only + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-only + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-only + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-only + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-only + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-only + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-only + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-only + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-only + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-only + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MMU_PAGE_SIZE + 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + 3 + 2 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-only + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-only + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-only + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-only + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02203030 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60003000 + + 0x0 + 0xAC + registers + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-only + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-only + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-only + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-only + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02202160 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60081000 + + 0x0 + 0x98 + registers + + + SPI2 + 72 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-only + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-only + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-only + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-only + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-only + + + SPI_USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SPI_CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-only + + + SPI_DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-only + + + SPI_ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-only + + + SPI_CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-only + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-only + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-only + + + SPI_DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-only + + + SPI_DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-only + + + SPI_DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-only + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-only + + + SPI_DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-only + + + SPI_DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-only + + + SPI_DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-only + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-only + + + SPI_DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-only + + + SPI_DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-only + + + SPI_DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-only + + + SPI_D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-only + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-only + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-only + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-only + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02201300 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x6000A000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TEE + Peripheral TEE + TEE + 0x60098000 + + 0x0 + 0x88 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M1_MODE_CTRL + Tee mode control register + 0x4 + 0x20 + 0x00000003 + + + M1_MODE + M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M2_MODE_CTRL + Tee mode control register + 0x8 + 0x20 + + + M2_MODE + M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M3_MODE_CTRL + Tee mode control register + 0xC + 0x20 + 0x00000003 + + + M3_MODE + M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M4_MODE_CTRL + Tee mode control register + 0x10 + 0x20 + 0x00000003 + + + M4_MODE + M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M5_MODE_CTRL + Tee mode control register + 0x14 + 0x20 + 0x00000003 + + + M5_MODE + M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M6_MODE_CTRL + Tee mode control register + 0x18 + 0x20 + 0x00000003 + + + M6_MODE + M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M7_MODE_CTRL + Tee mode control register + 0x1C + 0x20 + 0x00000003 + + + M7_MODE + M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M8_MODE_CTRL + Tee mode control register + 0x20 + 0x20 + 0x00000003 + + + M8_MODE + M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M9_MODE_CTRL + Tee mode control register + 0x24 + 0x20 + 0x00000003 + + + M9_MODE + M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M10_MODE_CTRL + Tee mode control register + 0x28 + 0x20 + 0x00000003 + + + M10_MODE + M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M11_MODE_CTRL + Tee mode control register + 0x2C + 0x20 + 0x00000003 + + + M11_MODE + M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M12_MODE_CTRL + Tee mode control register + 0x30 + 0x20 + 0x00000003 + + + M12_MODE + M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M13_MODE_CTRL + Tee mode control register + 0x34 + 0x20 + 0x00000003 + + + M13_MODE + M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M14_MODE_CTRL + Tee mode control register + 0x38 + 0x20 + 0x00000003 + + + M14_MODE + M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M15_MODE_CTRL + Tee mode control register + 0x3C + 0x20 + 0x00000003 + + + M15_MODE + M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M16_MODE_CTRL + Tee mode control register + 0x40 + 0x20 + 0x00000003 + + + M16_MODE + M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M17_MODE_CTRL + Tee mode control register + 0x44 + 0x20 + 0x00000003 + + + M17_MODE + M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M18_MODE_CTRL + Tee mode control register + 0x48 + 0x20 + 0x00000003 + + + M18_MODE + M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M19_MODE_CTRL + Tee mode control register + 0x4C + 0x20 + 0x00000003 + + + M19_MODE + M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M20_MODE_CTRL + Tee mode control register + 0x50 + 0x20 + 0x00000003 + + + M20_MODE + M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M21_MODE_CTRL + Tee mode control register + 0x54 + 0x20 + 0x00000003 + + + M21_MODE + M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M22_MODE_CTRL + Tee mode control register + 0x58 + 0x20 + 0x00000003 + + + M22_MODE + M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M23_MODE_CTRL + Tee mode control register + 0x5C + 0x20 + 0x00000003 + + + M23_MODE + M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M24_MODE_CTRL + Tee mode control register + 0x60 + 0x20 + 0x00000003 + + + M24_MODE + M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M25_MODE_CTRL + Tee mode control register + 0x64 + 0x20 + 0x00000003 + + + M25_MODE + M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M26_MODE_CTRL + Tee mode control register + 0x68 + 0x20 + 0x00000003 + + + M26_MODE + M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M27_MODE_CTRL + Tee mode control register + 0x6C + 0x20 + 0x00000003 + + + M27_MODE + M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M28_MODE_CTRL + Tee mode control register + 0x70 + 0x20 + 0x00000003 + + + M28_MODE + M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M29_MODE_CTRL + Tee mode control register + 0x74 + 0x20 + 0x00000003 + + + M29_MODE + M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M30_MODE_CTRL + Tee mode control register + 0x78 + 0x20 + 0x00000003 + + + M30_MODE + M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M31_MODE_CTRL + Tee mode control register + 0x7C + 0x20 + 0x00000003 + + + M31_MODE + M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x80 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFFC + 0x20 + 0x02205282 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x60008000 + + 0x0 + 0x68 + registers + + + TG0_T0 + 51 + + + TG0_T1 + 52 + + + TG0_WDT + 53 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + T_USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + T_ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + T_DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + T_DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + T_AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + T_INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + T_EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + T_LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + T_HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + T_UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + T_ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + T_ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + T_LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + T_LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + T_LOAD + +Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 1 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02206072 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x60009000 + + TG1_T0 + 54 + + + TG1_T1 + 55 + + + TG1_WDT + 56 + + + + TRACE + Peripheral TRACE + TRACE + 0x600C0000 + + 0x0 + 0x30 + registers + + + TRACE + 27 + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_STAET_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set this reg, the current_mem_addr will update to start_addr + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + 1 indicate that fifo is empty + 0 + 1 + read-only + + + WORK_STATUS + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clr fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clr mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + [0] set 1 start trace. + 0 + 1 + write-only + + + OFF + set 1 stop trace. + 1 + 1 + write-only + + + MEM_LOOP + if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr + 2 + 1 + read-write + + + RESTART_ENA + enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package. + 3 + 1 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x24 + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: 0: default, cycle count 1: package num count + 24 + 1 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x28 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02203030 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x6000B000 + + 0x0 + 0x80 + registers + + + TWAI0 + 46 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + ACCEPTANCE_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQUEST + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUFFER + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RECEIVE_BUFFER + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TRANSMIT_BUFFER + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + NODE_BUS_OFF + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEGMENT1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEGMENT2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMPLING + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + DATA_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + DATA_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + DATA_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + DATA_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + DATA_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + DATA_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + DATA_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + DATA_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + DATA_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + DATA_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + DATA_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + DATA_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_COUNTER + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + + + TWAI1 + Two-Wire Automotive Interface + 0x6000D000 + + TWAI1 + 47 + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x98 + registers + + + UART0 + 43 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + a + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit to reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02201260 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60001000 + + UART1 + 44 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x60005000 + + 0x0 + 0x84 + registers + + + UHCI0 + 42 + + + + CONF0 + UHCI Configuration Register0 + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + UHCI Interrupt Raw Register + 0x4 + 0x20 + + + RX_START_INT_RAW + Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + 0 + 1 + read-only + + + TX_START_INT_RAW + Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + 5 + 1 + read-only + + + OUT_EOF_INT_RAW + Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + 6 + 1 + read-only + + + APP_CTRL0_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + 8 + 1 + read-write + + + + + INT_ST + UHCI Interrupt Status Register + 0x8 + 0x20 + + + RX_START_INT_ST + Indicates the interrupt status of UHCI_RX_START_INT. + 0 + 1 + read-only + + + TX_START_INT_ST + Indicates the interrupt status of UHCI_TX_START_INT. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + Indicates the interrupt status of UHCI_RX_HUNG_INT. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + Indicates the interrupt status of UHCI_TX_HUNG_INT. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + Indicates the interrupt status of UHCI_OUT_EOF_INT. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL0_INT. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL1_INT. + 8 + 1 + read-only + + + + + INT_ENA + UHCI Interrupt Enable Register + 0xC + 0x20 + + + RX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_START_INT. + 0 + 1 + read-write + + + TX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_START_INT. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + read-write + + + + + INT_CLR + UHCI Interrupt Clear Register + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + write-only + + + + + CONF1 + UHCI Configuration Register1 + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable head checksum check when receiving. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable sequence number check when receiving. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation, and data integrity check bit should 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save data packet head when UHCI receive data. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode data packet with checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode data packet with ACK when reliable data packet is ready. + 5 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + 7 + 1 + read-write + + + SW_START + Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + 8 + 1 + write-only + + + + + STATE0 + UHCI Receive Status Register + 0x18 + 0x20 + + + RX_ERR_CAUSE + Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + Indicates UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI Transmit Status Register + 0x1C + 0x20 + + + ENCODE_STATE + Indicates UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + UHCI Escapes Configuration Register0 + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable resolve char 0xC0 when DMA receiving data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable resolve char 0xDB when DMA receiving data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xDB with special char when DMA receiving data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing 0x11 with special char when DMA receiving data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing 0x13 with special char when DMA receiving data. + 7 + 1 + read-write + + + + + HUNG_CONF + UHCI Hung Configuration Register0 + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when receiving. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when DMA sending data. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI Ack Value Configuration Register0 + 0x28 + 0x20 + + + ACK_NUM + Indicates the ACK number during software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to load the ACK value of UHCI_ACK_NUM. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI Head Register + 0x2C + 0x20 + + + RX_HEAD + Stores the head of received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UCHI Quick send Register + 0x30 + 0x20 + + + SINGLE_SEND_NUM + Configures single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable sending short packet with single_send mode. + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + Configures always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable sending short packet with always_send mode. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + UHCI Q0_WORD0 Quick Send Register + 0x34 + 0x20 + + + SEND_Q0_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + UHCI Q0_WORD1 Quick Send Register + 0x38 + 0x20 + + + SEND_Q0_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + UHCI Q1_WORD0 Quick Send Register + 0x3C + 0x20 + + + SEND_Q1_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + UHCI Q1_WORD1 Quick Send Register + 0x40 + 0x20 + + + SEND_Q1_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + UHCI Q2_WORD0 Quick Send Register + 0x44 + 0x20 + + + SEND_Q2_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + UHCI Q2_WORD1 Quick Send Register + 0x48 + 0x20 + + + SEND_Q2_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + UHCI Q3_WORD0 Quick Send Register + 0x4C + 0x20 + + + SEND_Q3_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + UHCI Q3_WORD1 Quick Send Register + 0x50 + 0x20 + + + SEND_Q3_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + UHCI Q4_WORD0 Quick Send Register + 0x54 + 0x20 + + + SEND_Q4_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + UHCI Q4_WORD1 Quick Send Register + 0x58 + 0x20 + + + SEND_Q4_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + UHCI Q5_WORD0 Quick Send Register + 0x5C + 0x20 + + + SEND_Q5_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + UHCI Q5_WORD1 Quick Send Register + 0x60 + 0x20 + + + SEND_Q5_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + UHCI Q6_WORD0 Quick Send Register + 0x64 + 0x20 + + + SEND_Q6_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + UHCI Q6_WORD1 Quick Send Register + 0x68 + 0x20 + + + SEND_Q6_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + UHCI Escapes Sequence Configuration Register0 + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + Configures the delimiter for encoding, default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + UHCI Escapes Sequence Configuration Register1 + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + Configures the char needing encoding, which is 0xDB as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + UHCI Escapes Sequence Configuration Register2 + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + Configures the char needing encoding, which is 0x11 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + UHCI Escapes Sequence Configuration Register3 + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + Configures the char needing encoding, which is 0x13 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + UCHI Packet Length Configuration Register + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI Version Register + 0x80 + 0x20 + 0x02201100 + + + DATE + Configures version. + 0 + 32 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x6000F000 + + 0x0 + 0x70 + registers + + + USB + 48 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + USB_SERIAL_JTAG_RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-only + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + USB_SERIAL_JTAG_PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + USB_SERIAL_JTAG_PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + USB_SERIAL_JTAG_VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + USB_SERIAL_JTAG_VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + USB_SERIAL_JTAG_VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + USB_SERIAL_JTAG_TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + USB_SERIAL_JTAG_IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + USB_SERIAL_JTAG_SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + USB_SERIAL_JTAG_OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + USB_SERIAL_JTAG_CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + USB_SERIAL_JTAG_RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + USB_SERIAL_JTAG_DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + USB_SERIAL_JTAG_BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + USB_SERIAL_JTAG_BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + USB_SERIAL_JTAG_BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + USB_SERIAL_JTAG_GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + USB_SERIAL_JTAG_GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + USB_SERIAL_JTAG_CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + DATE + Date register + 0x80 + 0x20 + 0x02109220 + + + USB_SERIAL_JTAG_DATE + register version. + 0 + 32 + read-write + + + + + + + diff --git a/tools/ide-debug/svd/esp32h2.svd b/tools/ide-debug/svd/esp32h2.svd new file mode 100644 index 0000000..a19fad0 --- /dev/null +++ b/tools/ide-debug/svd/esp32h2.svd @@ -0,0 +1,29571 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-H2 + ESP32 H-Series + 1 + 32-bit RISC-V MCU & IEEE 802.15.4 & Bluetooth 5 (LE) + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + RV32IMC + r0p0 + little + false + false + 4 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xBC + registers + + + AES + 48 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x70 + registers + + + APB_ADC + 43 + + + + CTRL + digital saradc configure register + 0x0 + 0x20 + 0x40038240 + + + SARADC_START_FORCE + select software enable saradc sample + 0 + 1 + read-write + + + SARADC_START + software enable saradc sample + 1 + 1 + read-write + + + SARADC_SAR_CLK_GATED + SAR clock gated + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 3 + read-write + + + SARADC_SAR_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC2_PWDET_DRV + enable saradc2 power detect driven func. + 29 + 1 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + digital saradc configure register + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable max meas num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + digital saradc configure register + 0x8 + 0x20 + + + APB_SARADC_FILTER_FACTOR1 + Factor of saradc filter1 + 26 + 3 + read-write + + + APB_SARADC_FILTER_FACTOR0 + Factor of saradc filter0 + 29 + 3 + read-write + + + + + FSM_WAIT + digital saradc configure register + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + saradc_xpd_wait + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + saradc_rstb_wait + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + saradc_standby_wait + 16 + 8 + read-write + + + + + SAR1_STATUS + digital saradc configure register + 0x10 + 0x20 + 0x20000000 + + + SARADC_SAR1_STATUS + saradc1 status about data and channel + 0 + 32 + read-only + + + + + SAR2_STATUS + digital saradc configure register + 0x14 + 0x20 + 0x20000000 + + + SARADC_SAR2_STATUS + saradc2 status about data and channel + 0 + 32 + read-only + + + + + SAR_PATT_TAB1 + digital saradc configure register + 0x18 + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR_PATT_TAB2 + digital saradc configure register + 0x1C + 0x20 + 0x00FFFFFF + + + SARADC_SAR_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + ONETIME_SAMPLE + digital saradc configure register + 0x20 + 0x20 + 0x1A000000 + + + SARADC_ONETIME_ATTEN + configure onetime atten + 23 + 2 + read-write + + + SARADC_ONETIME_CHANNEL + configure onetime channel + 25 + 4 + read-write + + + SARADC_ONETIME_START + trigger adc onetime sample + 29 + 1 + read-write + + + SARADC2_ONETIME_SAMPLE + enable adc2 onetime sample + 30 + 1 + read-write + + + SARADC1_ONETIME_SAMPLE + enable adc1 onetime sample + 31 + 1 + read-write + + + + + ARB_CTRL + digital saradc configure register + 0x24 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + digital saradc configure register + 0x28 + 0x20 + 0x03740000 + + + APB_SARADC_FILTER_CHANNEL1 + configure filter1 to adc channel + 18 + 4 + read-write + + + APB_SARADC_FILTER_CHANNEL0 + configure filter0 to adc channel + 22 + 4 + read-write + + + APB_SARADC_FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1DATA_STATUS + digital saradc configure register + 0x2C + 0x20 + + + APB_SARADC1_DATA + saradc1 data + 0 + 17 + read-only + + + + + SAR2DATA_STATUS + digital saradc configure register + 0x30 + 0x20 + + + APB_SARADC2_DATA + saradc2 data + 0 + 17 + read-only + + + + + THRES0_CTRL + digital saradc configure register + 0x34 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES0_CHANNEL + configure thres0 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES0_HIGH + saradc thres0 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES0_LOW + saradc thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + digital saradc configure register + 0x38 + 0x20 + 0x0003FFED + + + APB_SARADC_THRES1_CHANNEL + configure thres1 to adc channel + 0 + 4 + read-write + + + APB_SARADC_THRES1_HIGH + saradc thres1 monitor thres + 5 + 13 + read-write + + + APB_SARADC_THRES1_LOW + saradc thres1 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + digital saradc configure register + 0x3C + 0x20 + + + APB_SARADC_THRES_ALL_EN + enable thres to all channel + 27 + 1 + read-write + + + APB_SARADC_THRES1_EN + enable thres1 + 30 + 1 + read-write + + + APB_SARADC_THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + digital saradc int register + 0x40 + 0x20 + + + APB_SARADC_TSENS_INT_ENA + tsens low interrupt enable + 25 + 1 + read-write + + + APB_SARADC_THRES1_LOW_INT_ENA + saradc thres1 low interrupt enable + 26 + 1 + read-write + + + APB_SARADC_THRES0_LOW_INT_ENA + saradc thres0 low interrupt enable + 27 + 1 + read-write + + + APB_SARADC_THRES1_HIGH_INT_ENA + saradc thres1 high interrupt enable + 28 + 1 + read-write + + + APB_SARADC_THRES0_HIGH_INT_ENA + saradc thres0 high interrupt enable + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + saradc2 done interrupt enable + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + saradc1 done interrupt enable + 31 + 1 + read-write + + + + + INT_RAW + digital saradc int register + 0x44 + 0x20 + + + APB_SARADC_TSENS_INT_RAW + saradc tsens interrupt raw + 25 + 1 + read-only + + + APB_SARADC_THRES1_LOW_INT_RAW + saradc thres1 low interrupt raw + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_RAW + saradc thres0 low interrupt raw + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_RAW + saradc thres1 high interrupt raw + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_RAW + saradc thres0 high interrupt raw + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + saradc2 done interrupt raw + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + saradc1 done interrupt raw + 31 + 1 + read-only + + + + + INT_ST + digital saradc int register + 0x48 + 0x20 + + + APB_SARADC_TSENS_INT_ST + saradc tsens interrupt state + 25 + 1 + read-only + + + APB_SARADC_THRES1_LOW_INT_ST + saradc thres1 low interrupt state + 26 + 1 + read-only + + + APB_SARADC_THRES0_LOW_INT_ST + saradc thres0 low interrupt state + 27 + 1 + read-only + + + APB_SARADC_THRES1_HIGH_INT_ST + saradc thres1 high interrupt state + 28 + 1 + read-only + + + APB_SARADC_THRES0_HIGH_INT_ST + saradc thres0 high interrupt state + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + saradc2 done interrupt state + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + saradc1 done interrupt state + 31 + 1 + read-only + + + + + INT_CLR + digital saradc int register + 0x4C + 0x20 + + + APB_SARADC_TSENS_INT_CLR + saradc tsens interrupt clear + 25 + 1 + write-only + + + APB_SARADC_THRES1_LOW_INT_CLR + saradc thres1 low interrupt clear + 26 + 1 + write-only + + + APB_SARADC_THRES0_LOW_INT_CLR + saradc thres0 low interrupt clear + 27 + 1 + write-only + + + APB_SARADC_THRES1_HIGH_INT_CLR + saradc thres1 high interrupt clear + 28 + 1 + write-only + + + APB_SARADC_THRES0_HIGH_INT_CLR + saradc thres0 high interrupt clear + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + saradc2 done interrupt clear + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + saradc1 done interrupt clear + 31 + 1 + write-only + + + + + DMA_CONF + digital saradc configure register + 0x50 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + CLKM_CONF + digital saradc configure register + 0x54 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + reg clk en + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_TSENS_CTRL + digital tsens configure register + 0x58 + 0x20 + 0x00018080 + + + TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + TSENS_PU + temperature sensor power up + 22 + 1 + read-write + + + + + TSENS_CTRL2 + digital tsens configure register + 0x5C + 0x20 + 0x00004002 + + + TSENS_XPD_WAIT + the time that power up tsens need wait + 0 + 12 + read-write + + + TSENS_XPD_FORCE + force power up tsens + 12 + 2 + read-write + + + TSENS_CLK_INV + inv tsens clk + 14 + 1 + read-write + + + TSENS_CLK_SEL + tsens clk select + 15 + 1 + read-write + + + + + CALI + digital saradc configure register + 0x60 + 0x20 + 0x00008000 + + + APB_SARADC_CALI_CFG + saradc cali factor + 0 + 17 + read-write + + + + + APB_TSENS_WAKE + digital tsens configure register + 0x64 + 0x20 + 0x0000FF00 + + + WAKEUP_TH_LOW + reg_wakeup_th_low + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + reg_wakeup_th_high + 8 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + reg_wakeup_over_upper_th + 16 + 1 + read-only + + + WAKEUP_MODE + reg_wakeup_mode + 17 + 1 + read-write + + + WAKEUP_EN + reg_wakeup_en + 18 + 1 + read-write + + + + + APB_TSENS_SAMPLE + digital tsens configure register + 0x68 + 0x20 + 0x00000014 + + + TSENS_SAMPLE_RATE + HW sample rate + 0 + 16 + read-write + + + TSENS_SAMPLE_EN + HW sample en + 16 + 1 + read-write + + + + + CTRL_DATE + version + 0x3FC + 0x20 + 0x02206240 + + + DATE + version + 0 + 32 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x600CE000 + + 0x0 + 0x80 + registers + + + + C0RE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 25 + 4 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + C0RE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + C0RE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CLOCK_GATE + clock register + 0x78 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + GDMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x1A4 + registers + + + DMA_CH0 + 44 + + + DMA_CH1 + 45 + + + + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + + + AHB_TEST + reserved + 0x60 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + MISC register + 0x64 + 0x20 + + + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 + 1 + read-write + + + + + DATE + Version control register + 0x68 + 0x20 + 0x02202250 + + + DATE + register version. + 0 + 32 + read-write + + + + + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 + 0x20 + + + IN_RST_CH + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 5 + 1 + read-write + + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 27 + 1 + read-only + + + + + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 + 0x20 + 0x01100000 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 23 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL_CH + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + + + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 + 0x20 + 0x00800000 + + + OUTLINK_ADDR_CH + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 22 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC + 0x20 + + + TX_PRI_CH + The priority of Tx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy + 0 + 6 + read-write + + + + + 2 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 + 0x20 + 0x00000008 + + + OUT_RST_CH + This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. + 6 + 1 + read-write + + + + + + + DS + Digital Signature + DS + 0x6008C000 + + 0x0 + 0xA5C + registers + + + + 512 + 0x1 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x8 + + + 512 + 0x1 + M_MEM[%s] + memory that stores M + 0x200 + 0x8 + + + 512 + 0x1 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x8 + + + 48 + 0x1 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x8 + + + 16 + 0x1 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + memory that stores X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x8 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x60039000 + + 0x0 + 0x78 + registers + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + 0x80000000 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + MOD_BASE + The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + 3 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + 4 + 4 + read-write + + + SECURITY_MODE + Reserved + 8 + 1 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 29 + 1 + read-only + + + CLK_EN + Write 1 to force on register clock gate. + 30 + 1 + read-write + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02207180 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 32 + 0x1 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x8 + + + 32 + 0x1 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x8 + + + 32 + 0x1 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x8 + + + + + EFUSE + eFuse Controller + EFUSE + 0x6001A000 + + 0x0 + 0x1D0 + registers + + + EFUSE + 24 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + RPT4_RESERVED0_4 + Reserved. + 7 + 1 + read-only + + + DIS_ICACHE + Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + POWERGLITCH_EN + Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled. + 13 + 1 + read-only + + + DIS_CAN + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DREFH + Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + 21 + 2 + read-only + + + USB_DREFL + Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO + Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned. + 26 + 1 + read-only + + + RPT4_RESERVED0_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + RPT4_RESERVED1_1 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x000C0000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + ECDSA_FORCE_USE_HARDWARE_K + Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + RPT4_RESERVED2_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + RPT4_RESERVED3_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 8 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 25 + 1 + read-only + + + HYS_EN_PAD0 + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. + 26 + 6 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + HYS_EN_PAD1 + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. + 0 + 22 + read-only + + + RPT4_RESERVED4_1 + Reserved. + 22 + 2 + read-only + + + RPT4_RESERVED4_0 + Reserved. + 24 + 8 + read-only + + + + + RD_MAC_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_RESERVED_1 + Reserved. + 0 + 14 + read-only + + + MAC_RESERVED_0 + Reserved. + 14 + 18 + read-only + + + + + RD_MAC_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + MAC_RESERVED_2 + Reserved. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + RPT4_RESERVED0_ERR_4 + Reserved. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + Indicates a programming error of DIS_ICACHE. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + POWERGLITCH_EN_ERR + Indicates a programming error of POWERGLITCH_EN. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_DEVICE. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_CAN. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DREFH_ERR + Indicates a programming error of USB_DREFH. + 21 + 2 + read-only + + + USB_DREFL_ERR + Indicates a programming error of USB_DREFL. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + Indicates a programming error of USB_EXCHG_PINS. + 25 + 1 + read-only + + + VDD_SPI_AS_GPIO_ERR + Indicates a programming error of VDD_SPI_AS_GPIO. + 26 + 1 + read-only + + + RPT4_RESERVED0_ERR_2 + Reserved. + 27 + 2 + read-only + + + RPT4_RESERVED0_ERR_1 + Reserved. + 29 + 1 + read-only + + + RPT4_RESERVED0_ERR_0 + Reserved. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + RPT4_RESERVED1_ERR_0 + Reserved. + 0 + 16 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + RPT4_RESERVED2_ERR_1 + Reserved. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + RPT4_RESERVED2_ERR_0 + Reserved. + 22 + 6 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + USB_PRINT_ERR + Indicates a programming error of UART_PRINT_CHANNEL. + 2 + 1 + read-only + + + RPT4_RESERVED3_ERR_5 + Reserved. + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 8 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE VERSION. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE_ERR + Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + 25 + 1 + read-only + + + HYS_EN_PAD0_ERR + Indicates a programming error of HYS_EN_PAD0. + 26 + 6 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x18C + 0x20 + + + HYS_EN_PAD1_ERR + Indicates a programming error of HYS_EN_PAD1. + 0 + 22 + read-only + + + RPT4_RESERVED4_ERR_1 + Reserved. + 22 + 2 + read-only + + + RPT4_RESERVED4_ERR_0 + Reserved. + 24 + 8 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + CFG_ECDSA_BLK + Configures which block to use for ECDSA key output. + 16 + 4 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + CUR_ECDSA_BLK + Indicates which block is used for ECDSA key output. + 20 + 4 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE17 + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x0F010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01266701 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00A00140 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02208120 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x2A8 + registers + + + GPIO + 16 + + + GPIO_NMI + 17 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + 32 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + FUNC0_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC6_IN_SEL_CFG + GPIO input function configuration register + 0x16C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC7_IN_SEL_CFG + GPIO input function configuration register + 0x170 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC8_IN_SEL_CFG + GPIO input function configuration register + 0x174 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC9_IN_SEL_CFG + GPIO input function configuration register + 0x178 + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC10_IN_SEL_CFG + GPIO input function configuration register + 0x17C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC11_IN_SEL_CFG + GPIO input function configuration register + 0x180 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC12_IN_SEL_CFG + GPIO input function configuration register + 0x184 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC13_IN_SEL_CFG + GPIO input function configuration register + 0x188 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC14_IN_SEL_CFG + GPIO input function configuration register + 0x18C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC15_IN_SEL_CFG + GPIO input function configuration register + 0x190 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC16_IN_SEL_CFG + GPIO input function configuration register + 0x194 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC17_IN_SEL_CFG + GPIO input function configuration register + 0x198 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC19_IN_SEL_CFG + GPIO input function configuration register + 0x1A0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC28_IN_SEL_CFG + GPIO input function configuration register + 0x1C4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC29_IN_SEL_CFG + GPIO input function configuration register + 0x1C8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC30_IN_SEL_CFG + GPIO input function configuration register + 0x1CC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC31_IN_SEL_CFG + GPIO input function configuration register + 0x1D0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC32_IN_SEL_CFG + GPIO input function configuration register + 0x1D4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC33_IN_SEL_CFG + GPIO input function configuration register + 0x1D8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC34_IN_SEL_CFG + GPIO input function configuration register + 0x1DC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC35_IN_SEL_CFG + GPIO input function configuration register + 0x1E0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC40_IN_SEL_CFG + GPIO input function configuration register + 0x1F4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC41_IN_SEL_CFG + GPIO input function configuration register + 0x1F8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC42_IN_SEL_CFG + GPIO input function configuration register + 0x1FC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC45_IN_SEL_CFG + GPIO input function configuration register + 0x208 + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC46_IN_SEL_CFG + GPIO input function configuration register + 0x20C + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC47_IN_SEL_CFG + GPIO input function configuration register + 0x210 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC48_IN_SEL_CFG + GPIO input function configuration register + 0x214 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC49_IN_SEL_CFG + GPIO input function configuration register + 0x218 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC50_IN_SEL_CFG + GPIO input function configuration register + 0x21C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC51_IN_SEL_CFG + GPIO input function configuration register + 0x220 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC52_IN_SEL_CFG + GPIO input function configuration register + 0x224 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC53_IN_SEL_CFG + GPIO input function configuration register + 0x228 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC54_IN_SEL_CFG + GPIO input function configuration register + 0x22C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC55_IN_SEL_CFG + GPIO input function configuration register + 0x230 + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC56_IN_SEL_CFG + GPIO input function configuration register + 0x234 + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC63_IN_SEL_CFG + GPIO input function configuration register + 0x250 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC64_IN_SEL_CFG + GPIO input function configuration register + 0x254 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC65_IN_SEL_CFG + GPIO input function configuration register + 0x258 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC66_IN_SEL_CFG + GPIO input function configuration register + 0x25C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC67_IN_SEL_CFG + GPIO input function configuration register + 0x260 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC68_IN_SEL_CFG + GPIO input function configuration register + 0x264 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC69_IN_SEL_CFG + GPIO input function configuration register + 0x268 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC70_IN_SEL_CFG + GPIO input function configuration register + 0x26C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC71_IN_SEL_CFG + GPIO input function configuration register + 0x270 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC72_IN_SEL_CFG + GPIO input function configuration register + 0x274 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC73_IN_SEL_CFG + GPIO input function configuration register + 0x278 + 0x20 + 0x00000038 + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC81_IN_SEL_CFG + GPIO input function configuration register + 0x298 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC82_IN_SEL_CFG + GPIO input function configuration register + 0x29C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC87_IN_SEL_CFG + GPIO input function configuration register + 0x2B0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC88_IN_SEL_CFG + GPIO input function configuration register + 0x2B4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC89_IN_SEL_CFG + GPIO input function configuration register + 0x2B8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC90_IN_SEL_CFG + GPIO input function configuration register + 0x2BC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC91_IN_SEL_CFG + GPIO input function configuration register + 0x2C0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC92_IN_SEL_CFG + GPIO input function configuration register + 0x2C4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC93_IN_SEL_CFG + GPIO input function configuration register + 0x2C8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC94_IN_SEL_CFG + GPIO input function configuration register + 0x2CC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC95_IN_SEL_CFG + GPIO input function configuration register + 0x2D0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC97_IN_SEL_CFG + GPIO input function configuration register + 0x2D8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC98_IN_SEL_CFG + GPIO input function configuration register + 0x2DC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC99_IN_SEL_CFG + GPIO input function configuration register + 0x2E0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC100_IN_SEL_CFG + GPIO input function configuration register + 0x2E4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC101_IN_SEL_CFG + GPIO input function configuration register + 0x2E8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC102_IN_SEL_CFG + GPIO input function configuration register + 0x2EC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC103_IN_SEL_CFG + GPIO input function configuration register + 0x2F0 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC104_IN_SEL_CFG + GPIO input function configuration register + 0x2F4 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC105_IN_SEL_CFG + GPIO input function configuration register + 0x2F8 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC106_IN_SEL_CFG + GPIO input function configuration register + 0x2FC + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC107_IN_SEL_CFG + GPIO input function configuration register + 0x300 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC108_IN_SEL_CFG + GPIO input function configuration register + 0x304 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC109_IN_SEL_CFG + GPIO input function configuration register + 0x308 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC110_IN_SEL_CFG + GPIO input function configuration register + 0x30C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC111_IN_SEL_CFG + GPIO input function configuration register + 0x310 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC112_IN_SEL_CFG + GPIO input function configuration register + 0x314 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC113_IN_SEL_CFG + GPIO input function configuration register + 0x318 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC114_IN_SEL_CFG + GPIO input function configuration register + 0x31C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC115_IN_SEL_CFG + GPIO input function configuration register + 0x320 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC116_IN_SEL_CFG + GPIO input function configuration register + 0x324 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC117_IN_SEL_CFG + GPIO input function configuration register + 0x328 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC118_IN_SEL_CFG + GPIO input function configuration register + 0x32C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC119_IN_SEL_CFG + GPIO input function configuration register + 0x330 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC120_IN_SEL_CFG + GPIO input function configuration register + 0x334 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC121_IN_SEL_CFG + GPIO input function configuration register + 0x338 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC122_IN_SEL_CFG + GPIO input function configuration register + 0x33C + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC123_IN_SEL_CFG + GPIO input function configuration register + 0x340 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC124_IN_SEL_CFG + GPIO input function configuration register + 0x344 + 0x20 + 0x0000003C + + + IN_SEL + set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 32 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000080 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 8 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 8 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 9 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 10 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + DATE + GPIO version register + 0x6FC + 0x20 + 0x02201120 + + + DATE + version register + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60013000 + + 0x0 + 0x90 + registers + + + I2C + 11 + + + I2C_EXT0 + 29 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + 1: direct output, 0: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1: direct output, 0: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit, +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit, +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave, 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND0 + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND0_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2S0 + I2S (Inter-IC Sound) Controller + I2S + 0x6002D000 + + 0x0 + 0x60 + registers + + + I2S1 + 20 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00C0B600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 4 + 2 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 6 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 + 1 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x00C0F210 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 4 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 5 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 + 6 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x787BC000 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02208250 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0x7C + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x00001DEF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 5 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 5 + 5 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 10 + 5 + read-write + + + + + 28 + 0x4 + GPIO%s + IO MUX Configure Register for pad GPIO0 + 0x4 + 0x20 + 0x00000800 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + 4 + 1 + read-write + + + MCU_DRV + Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 5 + 2 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled. 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + 15 + 1 + read-write + + + HYS_EN + Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled. + 16 + 1 + read-write + + + HYS_SEL + Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + 17 + 1 + read-write + + + + + MODEM_DIAG_EN + GPIO MATRIX Configure Register for modem diag + 0xBC + 0x20 + + + MODEM_DIAG_EN + bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix + 0 + 32 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x02207270 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x60019000 + + 0x0 + 0x154 + registers + + + LEDC + 23 + + + + 6 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + This field is used to select one of timers for channel %s. + +0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN_CH + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV_CH + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP_CH + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM_CH + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN_CH + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET_CH + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + + + 6 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT_CH + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 6 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY_CH + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 25 + read-write + + + + + 6 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START_CH + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 6 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + This register stores the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x01000000 + + + TIMER_DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV_TIMER + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + TIMER_PAUSE + This bit is used to suspend the counter in timer %s. + 23 + 1 + read-write + + + TIMER_RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 24 + 1 + read-write + + + TICK_SEL_TIMER + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 25 + 1 + read-write + + + TIMER_PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + TIMER_CNT + This register stores the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + + + 6 + 0x10 + CH%s_GAMMA_WR + Ledc ch%s gamma ram write register. + 0x100 + 0x20 + + + CH_GAMMA_DUTY_INC + Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. + +1: Increase 0: Decrease. + 0 + 1 + read-write + + + CH_GAMMA_DUTY_CYCLE + Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + 1 + 10 + read-write + + + CH_GAMMA_SCALE + Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + 11 + 10 + read-write + + + CH_GAMMA_DUTY_NUM + Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + 21 + 10 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address register. + 0x104 + 0x20 + + + CH_GAMMA_WR_ADDR + Ledc ch%s gamma ram write address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address register. + 0x108 + 0x20 + + + CH_GAMMA_RD_ADDR + Ledc ch%s gamma ram read address. + 0 + 4 + read-write + + + + + 6 + 0x10 + CH%s_GAMMA_RD_DATA + Ledc ch%s gamma ram read data register. + 0x10C + 0x20 + + + CH_GAMMA_RD_DATA + Ledc ch%s gamma ram read data. + 0 + 31 + read-only + + + + + 6 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x180 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Ledc ch%s gamma entry num. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Ledc ch%s gamma pause, write 1 to pause. + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Ledc ch%s gamma resume, write 1 to resume. + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x1A0 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Ledc ch0 duty change end event enable register, write 1 to enable this event. + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Ledc ch1 duty change end event enable register, write 1 to enable this event. + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Ledc ch2 duty change end event enable register, write 1 to enable this event. + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Ledc ch3 duty change end event enable register, write 1 to enable this event. + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Ledc ch4 duty change end event enable register, write 1 to enable this event. + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Ledc ch5 duty change end event enable register, write 1 to enable this event. + 5 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. + 13 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Ledc timer0 overflow event enable register, write 1 to enable this event. + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Ledc timer1 overflow event enable register, write 1 to enable this event. + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Ledc timer2 overflow event enable register, write 1 to enable this event. + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Ledc timer3 overflow event enable register, write 1 to enable this event. + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Ledc timer0 compare event enable register, write 1 to enable this event. + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Ledc timer1 compare event enable register, write 1 to enable this event. + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Ledc timer2 compare event enable register, write 1 to enable this event. + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Ledc timer3 compare event enable register, write 1 to enable this event. + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Ledc ch0 duty scale update task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Ledc ch1 duty scale update task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Ledc ch2 duty scale update task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Ledc ch3 duty scale update task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Ledc ch4 duty scale update task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Ledc ch5 duty scale update task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x1A4 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Ledc timer0 res update task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Ledc timer1 res update task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Ledc timer2 res update task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Ledc timer3 res update task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Ledc timer0 capture task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Ledc timer1 capture task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Ledc timer2 capture task enable register, write 1 to enable this task. + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Ledc timer3 capture task enable register, write 1 to enable this task. + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Ledc ch0 signal out disable task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Ledc ch1 signal out disable task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Ledc ch2 signal out disable task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Ledc ch3 signal out disable task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Ledc ch4 signal out disable task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Ledc ch5 signal out disable task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Ledc ch0 overflow count reset task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Ledc ch1 overflow count reset task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Ledc ch2 overflow count reset task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Ledc ch3 overflow count reset task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Ledc ch4 overflow count reset task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Ledc ch5 overflow count reset task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + TASK_TIMER0_RST_EN + Ledc timer0 reset task enable register, write 1 to enable this task. + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Ledc timer1 reset task enable register, write 1 to enable this task. + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Ledc timer2 reset task enable register, write 1 to enable this task. + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Ledc timer3 reset task enable register, write 1 to enable this task. + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Ledc timer0 pause resume task enable register, write 1 to enable this task. + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Ledc timer1 pause resume task enable register, write 1 to enable this task. + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Ledc timer2 pause resume task enable register, write 1 to enable this task. + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Ledc timer3 pause resume task enable register, write 1 to enable this task. + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x1A8 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Ledc ch0 gamma restart task enable register, write 1 to enable this task. + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Ledc ch1 gamma restart task enable register, write 1 to enable this task. + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Ledc ch2 gamma restart task enable register, write 1 to enable this task. + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Ledc ch3 gamma restart task enable register, write 1 to enable this task. + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Ledc ch4 gamma restart task enable register, write 1 to enable this task. + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Ledc ch5 gamma restart task enable register, write 1 to enable this task. + 5 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Ledc ch0 gamma pause task enable register, write 1 to enable this task. + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Ledc ch1 gamma pause task enable register, write 1 to enable this task. + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Ledc ch2 gamma pause task enable register, write 1 to enable this task. + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Ledc ch3 gamma pause task enable register, write 1 to enable this task. + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Ledc ch4 gamma pause task enable register, write 1 to enable this task. + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Ledc ch5 gamma pause task enable register, write 1 to enable this task. + 13 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Ledc ch0 gamma resume task enable register, write 1 to enable this task. + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Ledc ch1 gamma resume task enable register, write 1 to enable this task. + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Ledc ch2 gamma resume task enable register, write 1 to enable this task. + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Ledc ch3 gamma resume task enable register, write 1 to enable this task. + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Ledc ch4 gamma resume task enable register, write 1 to enable this task. + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Ledc ch5 gamma resume task enable register, write 1 to enable this task. + 21 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x1B0 + 0x20 + + + TIMER_CMP + This register stores ledc timer%s compare value. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s count value capture register. + 0x1C0 + 0x20 + + + TIMER_CNT_CAP + This register stores ledc timer%s count value. + 0 + 20 + read-only + + + + + CONF + Global ledc configuration register + 0x1F0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + This bit is used to control clock. + +1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. + 7 + 1 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0x1FC + 0x20 + 0x02111150 + + + LEDC_DATE + This is the version control register. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Counter + PCNT + 0x60017000 + + 0x0 + 0x68 + registers + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x18072600 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x60016000 + + 0x0 + 0x78 + registers + + + RMT + 28 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 2 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x10 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 3 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 2 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x18 + 0x20 + 0x30FFFF02 + + + DIV_CNT_CH2 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH2 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH2 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 23 + 3 + read-write + + + CARRIER_EN_CH2 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH2 + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 2 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x1C + 0x20 + 0x000001E8 + + + RX_EN_CH2 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH2 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH2 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH2 + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH2 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH2 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH2 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH2 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH2 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 2 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x28 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 9 + 3 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 12 + 9 + read-only + + + APB_MEM_RD_ERR_CH0 + This status bit will be set if the offset address out of memory size when reading via APB bus. + 21 + 1 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 22 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 23 + 1 + read-only + + + APB_MEM_RADDR_CH0 + This register records the memory address offset when reading RAM over APB bus. + 24 + 8 + read-only + + + + + 2 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x30 + 0x20 + + + MEM_WADDR_EX_CH2 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + APB_MEM_RADDR_CH2 + This register records the memory address offset when reads RAM over APB bus. + 12 + 9 + read-only + + + STATE_CH2 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH2 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH2 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH2 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x38 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-only + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-only + + + CH2_RX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when reception done. + 2 + 1 + read-only + + + CH3_RX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when reception done. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x3C + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_RX_END_INT_ST + The masked interrupt status bit for CH2_RX_END_INT. + 2 + 1 + read-only + + + CH3_RX_END_INT_ST + The masked interrupt status bit for CH3_RX_END_INT. + 3 + 1 + read-only + + + RX_CH0_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 4 + 1 + read-only + + + RX_CH1_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 5 + 1 + read-only + + + RX_CH2_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 6 + 1 + read-only + + + RX_CH3_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x40 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_RX_END_INT_ENA + The interrupt enable bit for CH2_RX_END_INT. + 2 + 1 + read-write + + + CH3_RX_END_INT_ENA + The interrupt enable bit for CH3_RX_END_INT. + 3 + 1 + read-write + + + CH0_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 4 + 1 + read-write + + + CH1_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 5 + 1 + read-write + + + CH2_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 6 + 1 + read-write + + + CH3_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_RX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_RX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x44 + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_RX_END_INT_CLR + Set this bit to clear theCH2_RX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_RX_END_INT_CLR + Set this bit to clear theCH3_RX_END_INT interrupt. + 3 + 1 + write-only + + + RX_CH0_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 4 + 1 + write-only + + + RX_CH1_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 5 + 1 + write-only + + + RX_CH2_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 6 + 1 + write-only + + + RX_CH3_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + + + 2 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x48 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH0 + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH0 + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x50 + 0x20 + + + CARRIER_LOW_THRES_CH2 + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH2 + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 2 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0x58 + 0x20 + 0x00000080 + + + TX_LIM_CH0 + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH0 + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH0 + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH0 + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH0 + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 2 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0x60 + 0x20 + 0x00000080 + + + RMT_RX_LIM_CH2 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0x68 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + RMT_MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + RMT_MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + RMT_SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + RMT_SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + RMT_SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + RMT_SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + 24 + 2 + read-write + + + RMT_SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0x6C + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 2 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0x70 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + RX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + RX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02108213 + + + RMT_DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x600260B0 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x0 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x74 + registers + + + RSA + 47 + + + + 16 + 0x1 + M_MEM[%s] + Represents M + 0x0 + 0x8 + + + 16 + 0x1 + Z_MEM[%s] + Represents Z + 0x200 + 0x8 + + + 16 + 0x1 + Y_MEM[%s] + Represents Y + 0x400 + 0x8 + + + 16 + 0x1 + X_MEM[%s] + Represents X + 0x600 + 0x8 + + + M_PRIME + Represents M’ + 0x800 + 0x20 + + + M_PRIME + Represents M’ + 0 + 32 + read-write + + + + + MODE + Configures RSA length + 0x804 + 0x20 + + + MODE + Configures the RSA length. + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA clean register + 0x808 + 0x20 + + + QUERY_CLEAN + Represents whether or not the RSA memory completes initialization. + +0: Not complete + +1: Completed + + + 0 + 1 + read-only + + + + + SET_START_MODEXP + Starts modular exponentiation + 0x80C + 0x20 + + + SET_START_MODEXP + Configure whether or not to start the modular exponentiation. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + SET_START_MODMULT + Starts modular multiplication + 0x810 + 0x20 + + + SET_START_MODMULT + Configure whether or not to start the modular multiplication. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + SET_START_MULT + Starts multiplication + 0x814 + 0x20 + + + SET_START_MULT + Configure whether or not to start the multiplication. + +0: No effect + +1: Start + + + 0 + 1 + write-only + + + + + QUERY_IDLE + Represents the RSA status + 0x818 + 0x20 + + + QUERY_IDLE + Represents the RSA status. + +0: Busy + +1: Idle + + + 0 + 1 + read-only + + + + + INT_CLR + Clears RSA interrupt + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Write 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + Configures the constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configures the constant_time option. + +0: Acceleration + +1: No acceleration (default) + + + 0 + 1 + read-write + + + + + SEARCH_ENABLE + Configures the search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure the search option. + +0: No acceleration (default) + +1: Acceleration + +This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + Configures the search position + 0x828 + 0x20 + + + SEARCH_POS + Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + Enables the RSA interrupt + 0x82C + 0x20 + + + INT_ENA + Write 1 to enable the RSA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 49 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60003000 + + 0x0 + 0x138 + registers + + + SPI_MEM_REJECT_CACHE + 40 + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-only + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-only + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-only + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-only + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x00002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-only + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-only + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-only + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-only + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-only + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-only + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-only + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-only + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-only + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-only + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-only + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-only + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-only + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-only + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-only + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-only + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0xC0400000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-only + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-only + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-only + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-only + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-only + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-only + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-only + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-only + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-only + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-only + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-only + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-only + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-only + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-only + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-only + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-only + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-only + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-only + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-only + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-only + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-only + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-only + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-only + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-only + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-only + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-only + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-only + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-only + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-only + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-only + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-only + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-only + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-only + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-only + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-only + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash ACE section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash ACE section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash ACE section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash ACE section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM ACE section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM ACE section %s start address value + 0 + 26 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM ACE section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 14 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 26 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-only + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-only + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-only + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 26 + 6 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + 0xFC000000 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 26 + read-only + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-only + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-only + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-only + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-only + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-only + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-only + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-only + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-only + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-only + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-only + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-only + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-only + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-only + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-only + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-only + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-only + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-only + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-only + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-only + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-only + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-only + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-only + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-only + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-only + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 16 + 2 + read-only + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-only + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-only + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-only + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-only + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-only + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-only + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-only + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-only + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-only + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-only + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-only + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-only + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-only + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-only + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-only + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-only + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-only + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MMU_PAGE_SIZE + 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + 3 + 2 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-only + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-only + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-only + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-only + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02203030 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60002000 + + 0x0 + 0xAC + registers + + + SPI1 + 18 + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-only + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-only + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-only + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-only + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-only + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-only + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-only + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-only + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-only + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-only + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-only + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-only + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-only + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-only + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-only + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-only + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-only + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-only + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-only + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-only + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-only + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-only + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02202160 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI2 + 19 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-only + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-only + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-only + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-only + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-only + + + SPI_USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SPI_CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-only + + + SPI_DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-only + + + SPI_ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-only + + + SPI_CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-only + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-only + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-only + + + SPI_DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. + 10 + 2 + read-only + + + SPI_DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. + 12 + 2 + read-only + + + SPI_DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. + 14 + 2 + read-only + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-only + + + SPI_DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-only + + + SPI_DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-only + + + SPI_DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-only + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-only + + + SPI_DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-only + + + SPI_DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-only + + + SPI_DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-only + + + SPI_D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-only + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-only + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-only + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-only + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02201300 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller + 0x60025000 + + + SPI4 + SPI (Serial Peripheral Interface) Controller + 0x60037000 + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0_EDGE + 37 + + + SYSTIMER_TARGET1_EDGE + 38 + + + SYSTIMER_TARGET2_EDGE + 39 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TEE + Peripheral TEE + TEE + 0x60098000 + + 0x0 + 0x88 + registers + + + + M0_MODE_CTRL + Tee mode control register + 0x0 + 0x20 + + + M0_MODE + M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M1_MODE_CTRL + Tee mode control register + 0x4 + 0x20 + 0x00000003 + + + M1_MODE + M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M2_MODE_CTRL + Tee mode control register + 0x8 + 0x20 + + + M2_MODE + M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M3_MODE_CTRL + Tee mode control register + 0xC + 0x20 + 0x00000003 + + + M3_MODE + M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M4_MODE_CTRL + Tee mode control register + 0x10 + 0x20 + 0x00000003 + + + M4_MODE + M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M5_MODE_CTRL + Tee mode control register + 0x14 + 0x20 + 0x00000003 + + + M5_MODE + M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M6_MODE_CTRL + Tee mode control register + 0x18 + 0x20 + 0x00000003 + + + M6_MODE + M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M7_MODE_CTRL + Tee mode control register + 0x1C + 0x20 + 0x00000003 + + + M7_MODE + M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M8_MODE_CTRL + Tee mode control register + 0x20 + 0x20 + 0x00000003 + + + M8_MODE + M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M9_MODE_CTRL + Tee mode control register + 0x24 + 0x20 + 0x00000003 + + + M9_MODE + M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M10_MODE_CTRL + Tee mode control register + 0x28 + 0x20 + 0x00000003 + + + M10_MODE + M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M11_MODE_CTRL + Tee mode control register + 0x2C + 0x20 + 0x00000003 + + + M11_MODE + M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M12_MODE_CTRL + Tee mode control register + 0x30 + 0x20 + 0x00000003 + + + M12_MODE + M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M13_MODE_CTRL + Tee mode control register + 0x34 + 0x20 + 0x00000003 + + + M13_MODE + M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M14_MODE_CTRL + Tee mode control register + 0x38 + 0x20 + 0x00000003 + + + M14_MODE + M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M15_MODE_CTRL + Tee mode control register + 0x3C + 0x20 + 0x00000003 + + + M15_MODE + M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M16_MODE_CTRL + Tee mode control register + 0x40 + 0x20 + 0x00000003 + + + M16_MODE + M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M17_MODE_CTRL + Tee mode control register + 0x44 + 0x20 + 0x00000003 + + + M17_MODE + M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M18_MODE_CTRL + Tee mode control register + 0x48 + 0x20 + 0x00000003 + + + M18_MODE + M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M19_MODE_CTRL + Tee mode control register + 0x4C + 0x20 + 0x00000003 + + + M19_MODE + M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M20_MODE_CTRL + Tee mode control register + 0x50 + 0x20 + 0x00000003 + + + M20_MODE + M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M21_MODE_CTRL + Tee mode control register + 0x54 + 0x20 + 0x00000003 + + + M21_MODE + M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M22_MODE_CTRL + Tee mode control register + 0x58 + 0x20 + 0x00000003 + + + M22_MODE + M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M23_MODE_CTRL + Tee mode control register + 0x5C + 0x20 + 0x00000003 + + + M23_MODE + M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M24_MODE_CTRL + Tee mode control register + 0x60 + 0x20 + 0x00000003 + + + M24_MODE + M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M25_MODE_CTRL + Tee mode control register + 0x64 + 0x20 + 0x00000003 + + + M25_MODE + M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M26_MODE_CTRL + Tee mode control register + 0x68 + 0x20 + 0x00000003 + + + M26_MODE + M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M27_MODE_CTRL + Tee mode control register + 0x6C + 0x20 + 0x00000003 + + + M27_MODE + M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M28_MODE_CTRL + Tee mode control register + 0x70 + 0x20 + 0x00000003 + + + M28_MODE + M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M29_MODE_CTRL + Tee mode control register + 0x74 + 0x20 + 0x00000003 + + + M29_MODE + M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M30_MODE_CTRL + Tee mode control register + 0x78 + 0x20 + 0x00000003 + + + M30_MODE + M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + M31_MODE_CTRL + Tee mode control register + 0x7C + 0x20 + 0x00000003 + + + M31_MODE + M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode + 0 + 2 + read-write + + + + + CLOCK_GATE + Clock gating register + 0x80 + 0x20 + 0x00000001 + + + CLK_EN + reg_clk_en + 0 + 1 + read-write + + + + + DATE + Version register + 0xFFC + 0x20 + 0x02205282 + + + DATE + reg_tee_date + 0 + 28 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x6001F000 + + 0x0 + 0x68 + registers + + + TG0_T0_LEVEL + 32 + + + TG0_WDT_LEVEL + 33 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + T_USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + T_ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + T_DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + T_DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + T_AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + T_INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + T_EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + T_LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + T_HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + T_UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + T_ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + T_ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + T_LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + T_LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + T_LOAD + +Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 1 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 1 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02206072 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x60020000 + + TG1_T0_LEVEL + 34 + + + TG1_WDT_LEVEL + 35 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x80 + registers + + + TWAI + 25 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + ACCEPTANCE_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQUEST + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUFFER + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RECEIVE_BUFFER + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TRANSMIT_BUFFER + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + NODE_BUS_OFF + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEGMENT1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEGMENT2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMPLING + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + DATA_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + DATA_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + DATA_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + DATA_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + DATA_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + DATA_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + DATA_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + DATA_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + DATA_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + DATA_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + DATA_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + DATA_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_COUNTER + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x98 + registers + + + UART0 + 21 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + a + 0x20 + 0x20 + 0x0010001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02207250 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60010000 + + UART1 + 22 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x60014000 + + 0x0 + 0x84 + registers + + + UHCI0 + 15 + + + + CONF0 + a + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + a + 0x4 + 0x20 + + + RX_START_INT_RAW + a + 0 + 1 + read-only + + + TX_START_INT_RAW + a + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + a + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + a + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + a + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + a + 5 + 1 + read-only + + + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the + 6 + 1 + read-only + + + APP_CTRL0_INT_RAW + Soft control int raw bit. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Soft control int raw bit. + 8 + 1 + read-write + + + + + INT_ST + a + 0x8 + 0x20 + + + RX_START_INT_ST + a + 0 + 1 + read-only + + + TX_START_INT_ST + a + 1 + 1 + read-only + + + RX_HUNG_INT_ST + a + 2 + 1 + read-only + + + TX_HUNG_INT_ST + a + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + a + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + a + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + a + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + a + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + a + 8 + 1 + read-only + + + + + INT_ENA + a + 0xC + 0x20 + + + RX_START_INT_ENA + a + 0 + 1 + read-write + + + TX_START_INT_ENA + a + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + a + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + a + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + a + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + a + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + a + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + a + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + a + 8 + 1 + read-write + + + + + INT_CLR + a + 0x10 + 0x20 + + + RX_START_INT_CLR + a + 0 + 1 + write-only + + + TX_START_INT_CLR + a + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + a + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + a + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + a + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + a + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + a + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + a + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + a + 8 + 1 + write-only + + + + + CONF1 + a + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + a + 0 + 1 + read-write + + + CHECK_SEQ_EN + a + 1 + 1 + read-write + + + CRC_DISABLE + a + 2 + 1 + read-write + + + SAVE_HEAD + a + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + a + 4 + 1 + read-write + + + TX_ACK_NUM_RE + a + 5 + 1 + read-write + + + WAIT_SW_START + a + 7 + 1 + read-write + + + SW_START + a + 8 + 1 + write-only + + + + + STATE0 + a + 0x18 + 0x20 + + + RX_ERR_CAUSE + a + 0 + 3 + read-only + + + DECODE_STATE + a + 3 + 3 + read-only + + + + + STATE1 + a + 0x1C + 0x20 + + + ENCODE_STATE + a + 0 + 3 + read-only + + + + + ESCAPE_CONF + a + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + a + 0 + 1 + read-write + + + TX_DB_ESC_EN + a + 1 + 1 + read-write + + + TX_11_ESC_EN + a + 2 + 1 + read-write + + + TX_13_ESC_EN + a + 3 + 1 + read-write + + + RX_C0_ESC_EN + a + 4 + 1 + read-write + + + RX_DB_ESC_EN + a + 5 + 1 + read-write + + + RX_11_ESC_EN + a + 6 + 1 + read-write + + + RX_13_ESC_EN + a + 7 + 1 + read-write + + + + + HUNG_CONF + a + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + a + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + a + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + a + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + a + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + a + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + a + 23 + 1 + read-write + + + + + ACK_NUM + a + 0x28 + 0x20 + + + ACK_NUM + a + 0 + 3 + read-write + + + LOAD + a + 3 + 1 + write-only + + + + + RX_HEAD + a + 0x2C + 0x20 + + + RX_HEAD + a + 0 + 32 + read-only + + + + + QUICK_SENT + a + 0x30 + 0x20 + + + SINGLE_SEND_NUM + a + 0 + 3 + read-write + + + SINGLE_SEND_EN + a + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + a + 4 + 3 + read-write + + + ALWAYS_SEND_EN + a + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + a + 0x34 + 0x20 + + + SEND_Q0_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + a + 0x38 + 0x20 + + + SEND_Q0_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + a + 0x3C + 0x20 + + + SEND_Q1_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + a + 0x40 + 0x20 + + + SEND_Q1_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + a + 0x44 + 0x20 + + + SEND_Q2_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + a + 0x48 + 0x20 + + + SEND_Q2_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + a + 0x4C + 0x20 + + + SEND_Q3_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + a + 0x50 + 0x20 + + + SEND_Q3_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + a + 0x54 + 0x20 + + + SEND_Q4_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + a + 0x58 + 0x20 + + + SEND_Q4_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + a + 0x5C + 0x20 + + + SEND_Q5_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + a + 0x60 + 0x20 + + + SEND_Q5_WORD1 + a + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + a + 0x64 + 0x20 + + + SEND_Q6_WORD0 + a + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + a + 0x68 + 0x20 + + + SEND_Q6_WORD1 + a + 0 + 32 + read-write + + + + + ESC_CONF0 + a + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + a + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + a + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF1 + a + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + a + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF2 + a + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + a + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + a + 16 + 8 + read-write + + + + + ESC_CONF3 + a + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + a + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + a + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + a + 16 + 8 + read-write + + + + + PKT_THRES + a + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + a + 0 + 13 + read-write + + + + + DATE + a + 0x80 + 0x20 + 0x02201100 + + + DATE + a + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface + 0x6000C000 + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x60043000 + + 0x0 + 0x70 + registers + + + USB + 26 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + USB_SERIAL_JTAG_RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-only + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + USB_SERIAL_JTAG_PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + USB_SERIAL_JTAG_PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + USB_SERIAL_JTAG_VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + USB_SERIAL_JTAG_VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + USB_SERIAL_JTAG_VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + USB_SERIAL_JTAG_TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + USB_SERIAL_JTAG_IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + USB_SERIAL_JTAG_SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + USB_SERIAL_JTAG_OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + USB_SERIAL_JTAG_CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + USB_SERIAL_JTAG_RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + USB_SERIAL_JTAG_DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + USB_SERIAL_JTAG_BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + USB_SERIAL_JTAG_BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + USB_SERIAL_JTAG_BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + USB_SERIAL_JTAG_GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + USB_SERIAL_JTAG_GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + USB_SERIAL_JTAG_CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + DATE + Date register + 0x80 + 0x20 + 0x02109220 + + + USB_SERIAL_JTAG_DATE + register version. + 0 + 32 + read-write + + + + + + + diff --git a/tools/ide-debug/svd/esp32s2.svd b/tools/ide-debug/svd/esp32s2.svd new file mode 100644 index 0000000..e3a9efb --- /dev/null +++ b/tools/ide-debug/svd/esp32s2.svd @@ -0,0 +1,45743 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S2 + ESP32-S2 + 11 + 32-bit MCU & 2.4 GHz Wi-Fi + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Xtensa LX7 + r0p0 + little + false + false + 3 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xBC + registers + + + AES + 56 + + + + 8 + 0x4 + KEY_%s + AES key register %s + 0x0 + 0x20 + + + KEY_0 + Stores AES keys. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_IN_%s + Source data register %s + 0x20 + 0x20 + + + TEXT_IN_0 + Stores the source data when the AES Accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_OUT_%s + Result data register %s + 0x30 + 0x20 + + + TEXT_OUT_0 + Stores the result data when the AES Accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + MODE + AES working mode configuration register + 0x40 + 0x20 + + + MODE + Defines the operation type of the AES Accelerator operating under the Typical AES working mode. +& +0x0(AES_EN_128): AES-EN-128 # +0x1(AES_EN_192): AES-EN-192 # +0x2(AES_EN_256): AES-EN-256 # +0x4(AES_DE_128): AES-DE-128 # +0x5(AES_DE_192): AES-DE-192 # +0x6(AES_DE_256): AES-DE-256 +& + 0 + 3 + read-write + + + + + ENDIAN + Endian configuration register + 0x44 + 0x20 + + + ENDIAN + Defines the endianness of input and output texts. +& +[1:0] key endian # +[3:2] text_in endian or in_stream endian # +[5:4] text_out endian or out_stream endian # +& + 0 + 6 + read-write + + + + + TRIGGER + Operation start controlling register + 0x48 + 0x20 + + + TRIGGER + Set this bit to 1 to start AES operation. + 0 + 1 + write-only + + + + + STATE + Operation status register + 0x4C + 0x20 + + + STATE + Stores the working status of the AES Accelerator. For details, see Table 3 for Typical AES working mode and Table 9 for DMA AES working mode. +For typical AES; 0 = idle; 1 = busy. +For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + 0 + 2 + read-only + + + + + 4 + 0x4 + IV_%s + initialization vector + 0x50 + 0x20 + + + IV_0 + This register stores the %sth 32-bit piece of 128-bit initialization vector + 0 + 32 + read-write + + + + + 4 + 0x4 + H_%s + GCM hash subkey + 0x60 + 0x20 + + + H_0 + GCM hash subkey + 0 + 32 + read-only + + + + + 4 + 0x4 + J0_%s + J0 + 0x70 + 0x20 + + + J0_0 + This register stores the %sth 32-bit piece of 128-bit J0 + 0 + 32 + read-write + + + + + 4 + 0x4 + T0_%s + T0 + 0x80 + 0x20 + + + T0_0 + This register stores the %sth 32-bit piece of 128-bit T0 + 0 + 32 + read-only + + + + + DMA_ENABLE + DMA enable register + 0x90 + 0x20 + + + DMA_ENABLE + Defines the working mode of the AES Accelerator. For details, see Table 1. +1'h0: typical AES operation +1'h1: DMA-AES operation + 0 + 1 + read-write + + + + + BLOCK_MODE + Block operation type register + 0x94 + 0x20 + + + BLOCK_MODE + Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. +& +3'h0(BLOCK_MODE_ECB): ECB # +3'h1(BLOCK_MODE_CBC): CBC # +3'h2(BLOCK_MODE_OFB): OFB # +3'h3(BLOCK_MODE_CTR): CTR # +3'h4(BLOCK_MODE_CFB8): CFB-8 # +3'h5(BLOCK_MODE_CFB128): CFB-128 # +3'h6(BLOCK_MODE_GCM): GCM +& + 0 + 3 + read-write + + + + + BLOCK_NUM + Block number configuration register + 0x98 + 0x20 + + + BLOCK_NUM + Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function register + 0x9C + 0x20 + + + INC_SEL + Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 . + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + AAD block number configuration register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Stores the ADD Block Number for the GCM operation. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + Remainder bit number of plaintext/ciphertext + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Stores the Remainder Bit Number for the GCM operation. + 0 + 7 + read-write + + + + + CONTINUE_OP + Operation continue controlling register + 0xA8 + 0x20 + + + CONTINUE_OP + Set this bit to 1 to continue AES operation. + 0 + 1 + write-only + + + + + INT_CLR + DMA-AES interrupt clear register + 0xAC + 0x20 + + + INT_CLR + Set this bit to 1 to clear AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + DMA-AES interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0xB4 + 0x20 + 0x20190514 + + + DATE + Version control register + 0 + 30 + read-write + + + + + DMA_EXIT + Operation exit controlling register + 0xB8 + 0x20 + + + DMA_EXIT + Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES operation. + 0 + 1 + write-only + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x3F440000 + + 0x0 + 0x68 + registers + + + APB_ADC + 89 + + + + CTRL + DIG ADC common configuration + 0x0 + 0x20 + 0x407F8240 + + + START_FORCE + 0: select FSM to start SAR ADC. 1: select software to start SAR ADC. + 0 + 1 + read-write + + + START + Start SAR ADC by software. + 1 + 1 + read-write + + + WORK_MODE + 0: single-channel scan mode. 1: double-channel scan mode. 2: +alternate-channel scan mode. + 3 + 2 + read-write + + + SAR_SEL + 0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode. + 5 + 1 + read-write + + + SAR_CLK_GATED + SAR clock gate enable bit. + 6 + 1 + read-write + + + SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 4 + read-write + + + SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 19 + 4 + read-write + + + SAR1_PATT_P_CLEAR + Clear the pointer of pattern table for DIG ADC1 CTRL. + 23 + 1 + read-write + + + SAR2_PATT_P_CLEAR + Clear the pointer of pattern table for DIG ADC2 CTRL. + 24 + 1 + read-write + + + DATA_SAR_SEL + 1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 25 + 1 + read-write + + + DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 26 + 1 + read-write + + + XPD_SAR_FORCE + Force option to xpd sar blocks. + 27 + 2 + read-write + + + WAIT_ARB_CYCLE + Wait arbit signal stable after sar_done. + 30 + 2 + read-write + + + + + CTRL2 + DIG ADC common configuration + 0x4 + 0x20 + 0x0000A1FE + + + MEAS_NUM_LIMIT + Enable limit times of SAR ADC sample. + 0 + 1 + read-write + + + MAX_MEAS_NUM + Set maximum conversion number. + 1 + 8 + read-write + + + SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not. + 9 + 1 + read-write + + + SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not. + 10 + 1 + read-write + + + TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + TIMER_TARGET + Set SAR ADC timer target. + 12 + 12 + read-write + + + TIMER_EN + Enable SAR ADC timer trigger. + 24 + 1 + read-write + + + + + FSM + digital adc control register + 0x8 + 0x20 + 0x02000000 + + + SAMPLE_NUM + sample number + 16 + 8 + read-write + + + SAMPLE_CYCLE + sample cycles + 24 + 8 + read-write + + + + + FSM_WAIT + configure saradc fsm internal parameter base on test + 0xC + 0x20 + 0x00FF0808 + + + XPD_WAIT + xpd wait + 0 + 8 + read-write + + + RSTB_WAIT + reset time + 8 + 8 + read-write + + + STANDBY_WAIT + standby wait + 16 + 8 + read-write + + + + + SAR1_STATUS + digital adc1 status + 0x10 + 0x20 + + + SAR1_STATUS + digital adc1 status + 0 + 32 + read-only + + + + + SAR2_STATUS + digital adc2 status + 0x14 + 0x20 + + + SAR2_STATUS + digital adc2 status + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0x18 + 0x20 + 0x0F0F0F0F + + + SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0x1C + 0x20 + 0x0F0F0F0F + + + SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0x20 + 0x20 + 0x0F0F0F0F + + + SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0x24 + 0x20 + 0x0F0F0F0F + + + SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0 + 32 + read-write + + + + + SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0x28 + 0x20 + 0x0F0F0F0F + + + SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0x2C + 0x20 + 0x0F0F0F0F + + + SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0x30 + 0x20 + 0x0F0F0F0F + + + SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0x34 + 0x20 + 0x0F0F0F0F + + + SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0 + 32 + read-write + + + + + ARB_CTRL + Configure the settings of DIG ADC2 arbiter + 0x38 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + ADC2 arbiter forces to enable DIG ADC2 CTRL. + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + ADC2 arbiter forces to enable RTC ADC2 CTRL. + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + ADC2 arbiter forces to enable PWDET/PKDET CTRL. + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + ADC2 arbiter force grant. + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set DIG ADC2 CTRL priority. + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set RTC ADC2 CTRL priority. + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set PWDET/PKDET CTRL priority. + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + ADC2 arbiter uses fixed priority. + 12 + 1 + read-write + + + + + FILTER_CTRL + Configure the settings of DIG ADC2 filter + 0x3C + 0x20 + 0x20400000 + + + ADC2_FILTER_RESET + Reset ADC2 filter. + 0 + 1 + read-write + + + ADC1_FILTER_RESET + Reset ADC1 filter. + 1 + 1 + read-write + + + ADC2_FILTER_FACTOR + Set filter factor for DIG ADC2 CRTL. + 16 + 7 + read-write + + + ADC1_FILTER_FACTOR + Set filter factor for DIG ADC1 CRTL. + 23 + 7 + read-write + + + ADC2_FILTER_EN + Enable DIG ADC2 CRTL filter. + 30 + 1 + read-write + + + ADC1_FILTER_EN + Enable DIG ADC1 CRTL filter. + 31 + 1 + read-write + + + + + FILTER_STATUS + Data status of DIG ADC2 filter + 0x40 + 0x20 + + + ADC2_FILTER_DATA + ADC2 filter data. + 0 + 16 + read-only + + + ADC1_FILTER_DATA + ADC1 filter data. + 16 + 16 + read-only + + + + + THRES_CTRL + Configure monitor threshold for DIG ADC2 + 0x44 + 0x20 + + + CLK_EN + Clock gate enable. + 0 + 1 + read-write + + + ADC2_THRES_MODE + 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt. + 2 + 1 + read-write + + + ADC1_THRES_MODE + 1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt. + 3 + 1 + read-write + + + ADC2_THRES + ADC2 threshold. + 4 + 13 + read-write + + + ADC1_THRES + ADC1 threshold. + 17 + 13 + read-write + + + ADC2_THRES_EN + Enable ADC2 threshold monitor. + 30 + 1 + read-write + + + ADC1_THRES_EN + Enable ADC1 threshold monitor. + 31 + 1 + read-write + + + + + INT_ENA + Enable DIG ADC interrupts + 0x48 + 0x20 + + + ADC2_THRES_INT_ENA + Enable bit of APB_SARADC_ADC2_THRES_INT interrupt. + 28 + 1 + read-write + + + ADC1_THRES_INT_ENA + Enable bit of APB_SARADC_ADC1_THRES_INT interrupt. + 29 + 1 + read-write + + + ADC2_DONE_INT_ENA + Enable bit of APB_SARADC_ADC2_DONE_INT interrupt. + 30 + 1 + read-write + + + ADC1_DONE_INT_ENA + Enable bit of APB_SARADC_ADC1_DONE_INT interrupt. + 31 + 1 + read-write + + + + + INT_RAW + DIG ADC interrupt raw bits + 0x4C + 0x20 + + + ADC2_THRES_INT_RAW + Raw bit of APB_SARADC_ADC2_THRES_INT interrupt. + 28 + 1 + read-only + + + ADC1_THRES_INT_RAW + Raw bit of APB_SARADC_ADC1_THRES_INT interrupt. + 29 + 1 + read-only + + + ADC2_DONE_INT_RAW + Raw bit of APB_SARADC_ADC2_DONE_INT interrupt. + 30 + 1 + read-only + + + ADC1_DONE_INT_RAW + Raw bit of APB_SARADC_ADC1_DONE_INT interrupt. + 31 + 1 + read-only + + + + + INT_ST + DIG ADC interrupt status + 0x50 + 0x20 + + + ADC2_THRES_INT_ST + Status of APB_SARADC_ADC2_THRES_INT interrupt. + 28 + 1 + read-only + + + ADC1_THRES_INT_ST + Status of APB_SARADC_ADC1_THRES_INT interrupt. + 29 + 1 + read-only + + + ADC2_DONE_INT_ST + Status of APB_SARADC_ADC2_DONE_INT interrupt. + 30 + 1 + read-only + + + ADC1_DONE_INT_ST + Status of APB_SARADC_ADC1_DONE_INT interrupt. + 31 + 1 + read-only + + + + + INT_CLR + Clear DIG ADC interrupts + 0x54 + 0x20 + + + ADC2_THRES_INT_CLR + Clear bit of APB_SARADC_ADC2_THRES_INT interrupt. + 28 + 1 + write-only + + + ADC1_THRES_INT_CLR + Clear bit of APB_SARADC_ADC1_THRES_INT interrupt. + 29 + 1 + write-only + + + ADC2_DONE_INT_CLR + Clear bit of APB_SARADC_ADC2_DONE_INT interrupt. + 30 + 1 + write-only + + + ADC1_DONE_INT_CLR + Clear bit of APB_SARADC_ADC1_DONE_INT interrupt. + 31 + 1 + write-only + + + + + DMA_CONF + Configure digital ADC DMA path + 0x58 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + Generate dma_in_suc_eof when sample cnt = spi_eof_num. + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + Reset DIG ADC CTRL status. + 30 + 1 + read-write + + + APB_ADC_TRANS + Set this bit, DIG ADC CTRL uses SPI DMA. + 31 + 1 + read-write + + + + + CLKM_CONF + Configure DIG ADC clock + 0x5C + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral DIG_ADC clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_SEL + 1: select APLL. 2: select APB_CLK. Other values: disable clock. + 21 + 2 + read-write + + + + + APB_DAC_CTRL + Configure DAC settings + 0x60 + 0x20 + 0x00002064 + + + DAC_TIMER_TARGET + Set DAC timer target. + 0 + 12 + read-write + + + DAC_TIMER_EN + Enable read dac data. + 12 + 1 + read-write + + + APB_DAC_ALTER_MODE + Enable DAC alter mode. + 13 + 1 + read-write + + + APB_DAC_TRANS + Enable DMA_DAC. + 14 + 1 + read-write + + + DAC_RESET_FIFO + Reset DIG DAC FIFO. + 15 + 1 + read-write + + + APB_DAC_RST + Reset DIG DAC by software. + 16 + 1 + read-write + + + + + APB_CTRL_DATE + Version control register + 0x3FC + 0x20 + 0x01907162 + + + APB_CTRL_DATE + Version control register + 0 + 32 + read-write + + + + + + + DEDICATED_GPIO + Dedicated GPIO + DEDIC_GPIO + 0x3F4CF000 + + 0x0 + 0x30 + registers + + + DEDICATED_GPIO + 27 + + + + OUT_DRT + Dedicated GPIO directive output register + 0x0 + 0x20 + + + VLAUE + This register is used to configure directive output value of 8-channel dedicated GPIO. + 0 + 8 + write-only + + + + + OUT_MSK + Dedicated GPIO mask output register + 0x4 + 0x20 + + + OUT_VALUE + This register is used to configure updated output value of 8-channel dedicated GPIO. + 0 + 8 + write-only + + + OUT_MSK + This register is used to configure channels which would be updated. 1: corresponding channel's output would be updated. + 8 + 8 + write-only + + + + + OUT_IDV + Dedicated GPIO individual output register + 0x8 + 0x20 + + + CH0 + Configure channel 0 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 0 + 2 + write-only + + + CH1 + Configure channel 1 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 2 + 2 + write-only + + + CH2 + Configure channel 2 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 4 + 2 + write-only + + + CH3 + Configure channel 3 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 6 + 2 + write-only + + + CH4 + Configure channel 4 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 8 + 2 + write-only + + + CH5 + Configure channel 5 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 10 + 2 + write-only + + + CH6 + Configure channel 6 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 12 + 2 + write-only + + + CH7 + Configure channel 7 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value. + 14 + 2 + write-only + + + + + OUT_SCAN + Dedicated GPIO output status register + 0xC + 0x20 + + + OUT_STATUS + GPIO out value configured by DEDIC_GPIO_OUT_DRT_REG, DEDIC_GPIO_OUT_MSK_REG, DEDIC_GPIO_OUT_IDV_REG. + 0 + 8 + read-only + + + + + OUT_CPU + Dedicated GPIO output mode selection register + 0x10 + 0x20 + + + SEL0 + Select GPIO out value configured by registers or CPU instructions for channel 0. 0: Configured by registers. 1: configured by CPU instructions. + 0 + 1 + read-write + + + SEL1 + Select GPIO out value configured by registers or CPU instructions for channel 1. 0: Configured by registers. 1: configured by CPU instructions. + 1 + 1 + read-write + + + SEL2 + Select GPIO out value configured by registers or CPU instructions for channel 2. 0: Configured by registers. 1: configured by CPU instructions. + 2 + 1 + read-write + + + SEL3 + Select GPIO out value configured by registers or CPU instructions for channel 3. 0: Configured by registers. 1: configured by CPU instructions. + 3 + 1 + read-write + + + SEL4 + Select GPIO out value configured by registers or CPU instructions for channel 4. 0: Configured by registers. 1: configured by CPU instructions. + 4 + 1 + read-write + + + SEL5 + Select GPIO out value configured by registers or CPU instructions for channel 5. 0: Configured by registers. 1: configured by CPU instructions. + 5 + 1 + read-write + + + SEL6 + Select GPIO out value configured by registers or CPU instructions for channel 6. 0: Configured by registers. 1: configured by CPU instructions. + 6 + 1 + read-write + + + SEL7 + Select GPIO out value configured by registers or CPU instructions for channel 7. 0: Configured by registers. 1: configured by CPU instructions. + 7 + 1 + read-write + + + + + IN_DLY + Dedicated GPIO input delay configuration register + 0x14 + 0x20 + + + CH0 + Configure GPIO0 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 0 + 2 + read-write + + + CH1 + Configure GPIO1 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 2 + 2 + read-write + + + CH2 + Configure GPIO2 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 4 + 2 + read-write + + + CH3 + Configure GPIO3 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 6 + 2 + read-write + + + CH4 + Configure GPIO4 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 8 + 2 + read-write + + + CH5 + Configure GPIO5 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 10 + 2 + read-write + + + CH6 + Configure GPIO6 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 12 + 2 + read-write + + + CH7 + Configure GPIO7 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay. + 14 + 2 + read-write + + + + + IN_SCAN + Dedicated GPIO input status register + 0x18 + 0x20 + + + IN_STATUS + GPIO input value after configured by DEDIC_GPIO_IN_DLY_REG. + 0 + 8 + read-only + + + + + INTR_RCGN + Dedicated GPIO interrupts generation mode register + 0x1C + 0x20 + + + INTR_MODE_CH0 + Configure channel 0 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 0 + 3 + read-write + + + INTR_MODE_CH1 + Configure channel 1 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 3 + 3 + read-write + + + INTR_MODE_CH2 + Configure channel 2 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 6 + 3 + read-write + + + INTR_MODE_CH3 + Configure channel 3 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 9 + 3 + read-write + + + INTR_MODE_CH4 + Configure channel 4 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 12 + 3 + read-write + + + INTR_MODE_CH5 + Configure channel 5 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 15 + 3 + read-write + + + INTR_MODE_CH6 + Configure channel 6 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 18 + 3 + read-write + + + INTR_MODE_CH7 + Configure channel 7 interrupt generate mode. +0/1: do not generate interrupt. +2: low level trigger. +3: high level trigger. +4: falling edge trigger. +5: raising edge trigger. +6/7: falling and raising edge trigger. + 21 + 3 + read-write + + + + + INTR_RAW + Raw interrupt status + 0x20 + 0x20 + + + GPIO0 + This interrupt raw bit turns to high level when dedicated GPIO0 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 0 + 1 + read-only + + + GPIO1 + This interrupt raw bit turns to high level when dedicated GPIO1 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 1 + 1 + read-only + + + GPIO2 + This interrupt raw bit turns to high level when dedicated GPIO2 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 2 + 1 + read-only + + + GPIO3 + This interrupt raw bit turns to high level when dedicated GPIO3 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 3 + 1 + read-only + + + GPIO4 + This interrupt raw bit turns to high level when dedicated GPIO4 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 4 + 1 + read-only + + + GPIO5 + This interrupt raw bit turns to high level when dedicated GPIO5 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 5 + 1 + read-only + + + GPIO6 + This interrupt raw bit turns to high level when dedicated GPIO6 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 6 + 1 + read-only + + + GPIO7 + This interrupt raw bit turns to high level when dedicated GPIO7 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + 7 + 1 + read-only + + + + + INTR_RLS + Interrupt enable bits + 0x24 + 0x20 + + + GPIO0_INT_ENA + The enable bit for DEDIC_GPIO0_INT_ST register. + 0 + 1 + read-write + + + GPIO1_INT_ENA + The enable bit for DEDIC_GPIO1_INT_ST register. + 1 + 1 + read-write + + + GPIO2_INT_ENA + The enable bit for DEDIC_GPIO2_INT_ST register. + 2 + 1 + read-write + + + GPIO3_INT_ENA + The enable bit for DEDIC_GPIO3_INT_ST register. + 3 + 1 + read-write + + + GPIO4_INT_ENA + The enable bit for DEDIC_GPIO4_INT_ST register. + 4 + 1 + read-write + + + GPIO5_INT_ENA + The enable bit for DEDIC_GPIO5_INT_ST register. + 5 + 1 + read-write + + + GPIO6_INT_ENA + The enable bit for DEDIC_GPIO6_INT_ST register. + 6 + 1 + read-write + + + GPIO7_INT_ENA + The enable bit for DEDIC_GPIO7_INT_ST register. + 7 + 1 + read-write + + + + + INTR_ST + Masked interrupt status + 0x28 + 0x20 + + + GPIO0_INT_ST + This is the status bit for DEDIC_GPIO0_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 0 + 1 + read-only + + + GPIO1_INT_ST + This is the status bit for DEDIC_GPIO1_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 1 + 1 + read-only + + + GPIO2_INT_ST + This is the status bit for DEDIC_GPIO2_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 2 + 1 + read-only + + + GPIO3_INT_ST + This is the status bit for DEDIC_GPIO3_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 3 + 1 + read-only + + + GPIO4_INT_ST + This is the status bit for DEDIC_GPIO4_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 4 + 1 + read-only + + + GPIO5_INT_ST + This is the status bit for DEDIC_GPIO5_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 5 + 1 + read-only + + + GPIO6_INT_ST + This is the status bit for DEDIC_GPIO6_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 6 + 1 + read-only + + + GPIO7_INT_ST + This is the status bit for DEDIC_GPIO7_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + 7 + 1 + read-only + + + + + INTR_CLR + Interrupt clear bits + 0x2C + 0x20 + + + GPIO0_INT_CLR + Set this bit to clear the DEDIC_GPIO0_INT_RAW interrupt. + 0 + 1 + write-only + + + GPIO1_INT_CLR + Set this bit to clear the DEDIC_GPIO1_INT_RAW interrupt. + 1 + 1 + write-only + + + GPIO2_INT_CLR + Set this bit to clear the DEDIC_GPIO2_INT_RAW interrupt. + 2 + 1 + write-only + + + GPIO3_INT_CLR + Set this bit to clear the DEDIC_GPIO3_INT_RAW interrupt. + 3 + 1 + write-only + + + GPIO4_INT_CLR + Set this bit to clear the DEDIC_GPIO4_INT_RAW interrupt. + 4 + 1 + write-only + + + GPIO5_INT_CLR + Set this bit to clear the DEDIC_GPIO5_INT_RAW interrupt. + 5 + 1 + write-only + + + GPIO6_INT_CLR + Set this bit to clear the DEDIC_GPIO6_INT_RAW interrupt. + 6 + 1 + write-only + + + GPIO7_INT_CLR + Set this bit to clear the DEDIC_GPIO7_INT_RAW interrupt. + 7 + 1 + write-only + + + + + + + DS + Digital Signature + DS + 0x6003D000 + + 0x0 + 0xA5C + registers + + + + 1584 + 0x1 + C_MEM[%s] + memory C + 0x0 + 0x8 + + + 4 + 0x4 + IV_%s + IV block data. + 0x630 + 0x20 + + + IV_0 + IV block data. + 0 + 32 + write-only + + + + + 512 + 0x1 + X_MEM[%s] + memory X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory Z + 0xA00 + 0x8 + + + SET_START + Activates the DS peripheral + 0xE00 + 0x20 + + + SET_START + Write 1 to this register to activate the DS peripheral. + 0 + 1 + write-only + + + + + SET_ME + Starts DS operation + 0xE04 + 0x20 + + + SET_ME + Write 1 to this register to start DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + Ends DS operation + 0xE08 + 0x20 + + + SET_FINISH + Write 1 to this register to end DS operation. + 0 + 1 + write-only + + + + + QUERY_BUSY + Status of the DS + 0xE0C + 0x20 + + + QUERY_BUSY + 1: The DS peripheral is busy. 0: The DS peripheral is idle. + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + Checks the reason why DS_KEY is not ready. + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + 1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY value from the HMAC peripheral. The biggest value is 15. 0: HMAC is not activated. + 0 + 4 + read-only + + + + + QUERY_CHECK + Queries DS check result + 0xE14 + 0x20 + + + MD_ERROR + 1: MD check fails. 0: MD check passes. + 0 + 1 + read-only + + + PADDING_BAD + 1: The padding check fails. 0: The padding check passes. + 1 + 1 + read-only + + + + + DATE + Version control register + 0xE20 + 0x20 + 0x20190418 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x3F41A000 + + 0x0 + 0x1D0 + registers + + + EFUSE + 46 + + + + 8 + 0x4 + PGM_DATA%s + Register %s that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the %sth 32-bit data to be programmed. + 0 + 32 + read-write + + + + + 3 + 0x4 + PGM_CHECK_VALUE%s + Register %s that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the %sth 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + Register 0 of BLOCK0. + 0x2C + 0x20 + + + WR_DIS + Disables programming of individual eFuses. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + Register 1 of BLOCK0. + 0x30 + 0x20 + + + RD_DIS + Disables software reading from individual eFuse blocks (BLOCK4-10). + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT + Reserved. + 7 + 1 + read-only + + + DIS_ICACHE + Set this bit to disable Icache. + 8 + 1 + read-only + + + DIS_DCACHE + Set this bit to disable Dcache. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Disables Icache when SoC is in Download mode. + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE + Disables Dcache when SoC is in Download mode. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Set this bit to disable the function that forces chip into download mode. + 12 + 1 + read-only + + + DIS_USB + Set this bit to disable USB OTG function. + 13 + 1 + read-only + + + DIS_CAN + Set this bit to disable the TWAI Controller function. + 14 + 1 + read-only + + + DIS_BOOT_REMAP + Disables capability to Remap RAM to ROM address space. + 15 + 1 + read-only + + + RPT4_RESERVED5 + Reserved (used for four backups method). + 16 + 1 + read-only + + + SOFT_DIS_JTAG + Software disables JTAG. When software disabled, JTAG can be activated temporarily by HMAC peripheral. + 17 + 1 + read-only + + + HARD_DIS_JTAG + Hardware disables JTAG permanently. + 18 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Disables flash encryption when in download boot modes. + 19 + 1 + read-only + + + USB_DREFH + Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. + 20 + 2 + read-only + + + USB_DREFL + Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. + 22 + 2 + read-only + + + USB_EXCHG_PINS + Set this bit to exchange USB D+ and D- pins. + 24 + 1 + read-only + + + EXT_PHY_ENABLE + Set this bit to enable external USB PHY. + 25 + 1 + read-only + + + USB_FORCE_NOPERSIST + If set, forces USB BVALID to 1. + 26 + 1 + read-only + + + RPT4_RESERVED0 + Reserved (used for four backups method). + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM + SPI regulator switches current limit mode. + 29 + 1 + read-only + + + VDD_SPI_DREFH + SPI regulator high voltage reference. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + Register 2 of BLOCK0. + 0x34 + 0x20 + + + VDD_SPI_DREFM + SPI regulator medium voltage reference. + 0 + 2 + read-only + + + VDD_SPI_DREFL + SPI regulator low voltage reference. + 2 + 2 + read-only + + + VDD_SPI_XPD + If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. + 4 + 1 + read-only + + + VDD_SPI_TIEH + If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V LDO. 1: VDD_SPI connects to VDD_RTC_IO. + 5 + 1 + read-only + + + VDD_SPI_FORCE + Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT + Set SPI regulator to 0 to configure init[1:0]=0. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM + Set SPI regulator to 1 to enable output current limit. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM + Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + 9 + 3 + read-only + + + VDD_SPI_INIT + Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. + 12 + 2 + read-only + + + VDD_SPI_DCAP + Prevents SPI regulator from overshoot. + 14 + 2 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock cycles. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + If set, revokes use of secure boot key digest 0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + If set, revokes use of secure boot key digest 1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + If set, revokes use of secure boot key digest 2. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Purpose of KEY0. Refer to Table Key Purpose Values. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Purpose of KEY1. Refer to Table Key Purpose Values. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + Register 3 of BLOCK0. + 0x38 + 0x20 + + + KEY_PURPOSE_2 + Purpose of KEY2. Refer to Table Key Purpose Values. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Purpose of KEY3. Refer to Table Key Purpose Values. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Purpose of KEY4. Refer to Table Key Purpose Values. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Purpose of KEY5. Refer to Table Key Purpose Values. + 12 + 4 + read-only + + + KEY_PURPOSE_6 + Purpose of KEY6. Refer to Table Key Purpose Values. + 16 + 4 + read-only + + + SECURE_BOOT_EN + Set this bit to enable secure boot. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Set this bit to enable aggressive secure boot key revocation mode. + 21 + 1 + read-only + + + RPT4_RESERVED1 + Reserved (used for four backups method). + 22 + 6 + read-only + + + FLASH_TPUW + Configures flash startup delay after SoC power-up, in unit of (ms/2). When the value is 15, delay is 7.5 ms. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + Register 4 of BLOCK0. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Set this bit to disable all download boot modes. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT + Set this bit to disable Legacy SPI boot mode. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL + Selects the default UART for printing boot messages. 0: UART0. 1: UART1. + 2 + 1 + read-only + + + RPT4_RESERVED3 + Reserved (used for four backups method). + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE + Set this bit to disable use of USB OTG in UART download boot mode. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode (read/write flash only). + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. + 6 + 2 + read-only + + + PIN_POWER_SELECTION + Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: VDD3P3_CPU. 1: VDD_SPI. + 8 + 1 + read-only + + + FLASH_TYPE + SPI flash type. 0: maximum four data lines, 1: eight data lines. + 9 + 1 + read-only + + + FORCE_SEND_RESUME + If set, forces ROM code to send an SPI flash resume command during SPI boot. + 10 + 1 + read-only + + + SECURE_VERSION + Secure version (used by ESP-IDF anti-rollback feature). + 11 + 16 + read-only + + + RPT4_RESERVED2 + Reserved (used for four backups method). + 27 + 5 + read-only + + + + + RD_REPEAT_DATA4 + Register 5 of BLOCK0. + 0x40 + 0x20 + + + RPT4_RESERVED4 + Reserved (used for four backups method). + 0 + 24 + read-only + + + + + RD_MAC_SPI_SYS_0 + Register 0 of BLOCK1. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + Register 1 of BLOCK1. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + SPI_PAD_CONF_0 + Stores the zeroth part of SPI_PAD_CONF. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + Register 2 of BLOCK1. + 0x4C + 0x20 + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_3 + Register 3 of BLOCK1. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the zeroth part of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + Register 4 of BLOCK1. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the fist part of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + Register 5 of BLOCK1. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second part of the zeroth part of system data. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_SYS_DATA_PART1_%s + Register %s of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the %sth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_USR_DATA%s + Register %s of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the %sth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY0_DATA%s + Register %s of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the %sth 32 bits of KEY0. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY1_DATA%s + Register %s of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the %sth 32 bits of KEY1. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY2_DATA%s + Register %s of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the %sth 32 bits of KEY2. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY3_DATA%s + Register %s of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the %sth 32 bits of KEY3. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY4_DATA%s + Register %s of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the %sth 32 bits of KEY4. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_KEY5_DATA%s + Register %s of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the %sth 32 bits of KEY5. + 0 + 32 + read-only + + + + + 8 + 0x4 + RD_SYS_DATA_PART2_%s + Register %s of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the %sth 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + 8 + 1 + read-only + + + DIS_DCACHE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + DIS_USB_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + 13 + 1 + read-only + + + DIS_CAN_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + 14 + 1 + read-only + + + DIS_BOOT_REMAP_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + 15 + 1 + read-only + + + RPT4_RESERVED5_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + 16 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + 17 + 1 + read-only + + + HARD_DIS_JTAG_ERR + Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + 18 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + 19 + 1 + read-only + + + USB_DREFH_ERR + Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + 20 + 2 + read-only + + + USB_DREFL_ERR + Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + 22 + 2 + read-only + + + USB_EXCHG_PINS_ERR + Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + 24 + 1 + read-only + + + EXT_PHY_ENABLE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + 25 + 1 + read-only + + + USB_FORCE_NOPERSIST_ERR + Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + 26 + 1 + read-only + + + RPT4_RESERVED0_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + 29 + 1 + read-only + + + VDD_SPI_DREFH_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + VDD_SPI_DREFM_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + 0 + 2 + read-only + + + VDD_SPI_DREFL_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + 2 + 2 + read-only + + + VDD_SPI_XPD_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + 4 + 1 + read-only + + + VDD_SPI_TIEH_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + 5 + 1 + read-only + + + VDD_SPI_FORCE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + 9 + 3 + read-only + + + VDD_SPI_INIT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + 12 + 2 + read-only + + + VDD_SPI_DCAP_ERR + Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + 14 + 2 + read-only + + + WDT_DELAY_SEL_ERR + Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + 12 + 4 + read-only + + + KEY_PURPOSE_6_ERR + Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + 16 + 4 + read-only + + + SECURE_BOOT_EN_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + RPT4_RESERVED1_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + 22 + 6 + read-only + + + FLASH_TPUW_ERR + Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL_ERR + Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + 2 + 1 + read-only + + + RPT4_RESERVED3_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + 6 + 2 + read-only + + + PIN_POWER_SELECTION_ERR + Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + 8 + 1 + read-only + + + FLASH_TYPE_ERR + Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + 9 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + 10 + 1 + read-only + + + SECURE_VERSION_ERR + Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + 11 + 16 + read-only + + + RPT4_RESERVED2_ERR + Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + 27 + 5 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED4_ERR + If any bit in RPT4_RESERVED4 is 1, there is a programming error in EFUSE_RPT4_RESERVED4. + 0 + 24 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes in BLOCK1. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that programming BLOCK1 data failed and the number of error bytes is over 5. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes in BLOCK2. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that programming BLOCK2 data failed and the number of error bytes is over 5. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes in BLOCK3. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that programming BLOCK3 data failed and the number of error bytes is over 5. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes in KEY0. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of KEY0 is reliable. 1: Means that programming KEY0 failed and the number of error bytes is over 5. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes in KEY1. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of KEY1 is reliable. 1: Means that programming KEY1 failed and the number of error bytes is over 5. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes in KEY2. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of KEY2 is reliable. 1: Means that programming KEY2 failed and the number of error bytes is over 5. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes in KEY3. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of KEY3 is reliable. 1: Means that programming KEY3 failed and the number of error bytes is over 5. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes in KEY4. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of KEY4 is reliable. 1: Means that programming KEY4 failed and the number of error bytes is over 5. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes in KEY5. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of KEY5 is reliable. 1: Means that programming user data failed and the number of error bytes is over 5. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes in BLOCK10. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that programming BLOCK10 data failed and the number of error bytes is over 5. + 7 + 1 + read-only + + + + + CLK + eFuse clock configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + If set, forces eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + If set, forces to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + If set, forces eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + If set, forces to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuration register. + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command. 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + REPEAT_ERR_CNT + Indicates the number of error bits during programming BLOCK0. + 10 + 8 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12010101 + + + THR_A + Configures the hold time of read operation. + 0 + 8 + read-write + + + TRD + Configures the length of pulse of read operation. + 8 + 8 + read-write + + + TSUR_A + Configures the setup time of read operation. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF0 + Configuration register 0 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x00C80101 + + + THP_A + Configures the hold time of programming operation. + 0 + 8 + read-write + + + TPGM_INACTIVE + Configures the length of pulse during programming 0 to eFuse. + 8 + 8 + read-write + + + TPGM + Configures the length of pulse during programming 1 to eFuse. + 16 + 16 + read-write + + + + + WR_TIM_CONF1 + Configuration register 1 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00288001 + + + TSUP_A + Configures the setup time of programming operation. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configuration register 2 of eFuse programming timing parameters. + 0x1F8 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + Version control register. + 0x1FC + 0x20 + 0x19081100 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x61800000 + + 0x0 + 0x140 + registers + + + + PRO_DCACHE_CTRL + register description + 0x0 + 0x20 + 0x00000100 + + + PRO_DCACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + PRO_DCACHE_SETSIZE_MODE + The bit is used to configure cache memory size.0: 8KB, 1: 16KB + 2 + 1 + read-write + + + PRO_DCACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + 3 + 1 + read-write + + + PRO_DCACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 8 + 1 + read-write + + + PRO_DCACHE_INVALIDATE_DONE + The bit is used to indicate invalidate operation is finished. + 9 + 1 + read-only + + + PRO_DCACHE_FLUSH_ENA + The bit is used to enable flush operation. It will be cleared by hardware after flush operation done. + 10 + 1 + read-write + + + PRO_DCACHE_FLUSH_DONE + The bit is used to indicate flush operation is finished. + 11 + 1 + read-only + + + PRO_DCACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + 12 + 1 + read-write + + + PRO_DCACHE_CLEAN_DONE + The bit is used to indicate clean operation is finished. + 13 + 1 + read-only + + + PRO_DCACHE_LOCK0_EN + The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG. + 14 + 1 + read-write + + + PRO_DCACHE_LOCK1_EN + The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG. + 15 + 1 + read-write + + + PRO_DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable. + 18 + 1 + read-write + + + PRO_DCACHE_AUTOLOAD_DONE + The bit is used to indicate conditional-preload operation is finished. + 19 + 1 + read-only + + + PRO_DCACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 20 + 1 + read-write + + + PRO_DCACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 21 + 1 + read-only + + + PRO_DCACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 22 + 1 + read-write + + + PRO_DCACHE_UNLOCK_DONE + The bit is used to indicate unlock operation is finished. + 23 + 1 + read-only + + + PRO_DCACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 24 + 1 + read-write + + + PRO_DCACHE_LOCK_DONE + The bit is used to indicate lock operation is finished. + 25 + 1 + read-only + + + + + PRO_DCACHE_CTRL1 + register description + 0x4 + 0x20 + 0x00000007 + + + PRO_DCACHE_MASK_BUS0 + The bit is used to disable dbus0, 0: enable, 1: disable + 0 + 1 + read-write + + + PRO_DCACHE_MASK_BUS1 + The bit is used to disable dbus1, 0: enable, 1: disable + 1 + 1 + read-write + + + PRO_DCACHE_MASK_BUS2 + The bit is used to disable dbus2, 0: enable, 1: disable + 2 + 1 + read-write + + + + + PRO_DCACHE_TAG_POWER_CTRL + register description + 0x8 + 0x20 + 0x00000005 + + + PRO_DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + PRO_DCACHE_TAG_MEM_FORCE_PD + The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + PRO_DCACHE_TAG_MEM_FORCE_PU + The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + PRO_DCACHE_LOCK0_ADDR + register description + 0xC + 0x20 + + + PRO_DCACHE_LOCK0_ADDR + The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG + 0 + 32 + read-write + + + + + PRO_DCACHE_LOCK0_SIZE + register description + 0x10 + 0x20 + + + PRO_DCACHE_LOCK0_SIZE + The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG + 0 + 16 + read-write + + + + + PRO_DCACHE_LOCK1_ADDR + register description + 0x14 + 0x20 + + + PRO_DCACHE_LOCK1_ADDR + The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG + 0 + 32 + read-write + + + + + PRO_DCACHE_LOCK1_SIZE + register description + 0x18 + 0x20 + + + PRO_DCACHE_LOCK1_SIZE + The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG + 0 + 16 + read-write + + + + + PRO_DCACHE_MEM_SYNC0 + register description + 0x1C + 0x20 + + + PRO_DCACHE_MEMSYNC_ADDR + The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1. + 0 + 32 + read-write + + + + + PRO_DCACHE_MEM_SYNC1 + register description + 0x20 + 0x20 + + + PRO_DCACHE_MEMSYNC_SIZE + The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0. + 0 + 19 + read-write + + + + + PRO_DCACHE_PRELOAD_ADDR + register description + 0x24 + 0x20 + + + PRO_DCACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + PRO_DCACHE_PRELOAD_SIZE + register description + 0x28 + 0x20 + 0x00000200 + + + PRO_DCACHE_PRELOAD_SIZE + The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.. + 0 + 10 + read-write + + + PRO_DCACHE_PRELOAD_ORDER + The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending. + 10 + 1 + read-write + + + + + PRO_DCACHE_AUTOLOAD_CFG + register description + 0x2C + 0x20 + + + PRO_DCACHE_AUTOLOAD_MODE + Reserved. + 0 + 1 + read-write + + + PRO_DCACHE_AUTOLOAD_STEP + Reserved. + 1 + 2 + read-write + + + PRO_DCACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending. + 3 + 1 + read-write + + + PRO_DCACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 4 + 2 + read-write + + + PRO_DCACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. + 6 + 2 + read-write + + + PRO_DCACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the second section for conditional pre-load operation. + 8 + 1 + read-write + + + PRO_DCACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the first section for conditional pre-load operation. + 9 + 1 + read-write + + + + + PRO_DCACHE_AUTOLOAD_SECTION0_ADDR + register description + 0x30 + 0x20 + + + PRO_DCACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + PRO_DCACHE_AUTOLOAD_SECTION0_SIZE + register description + 0x34 + 0x20 + 0x00008000 + + + PRO_DCACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. + 0 + 24 + read-write + + + + + PRO_DCACHE_AUTOLOAD_SECTION1_ADDR + register description + 0x38 + 0x20 + + + PRO_DCACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + PRO_DCACHE_AUTOLOAD_SECTION1_SIZE + register description + 0x3C + 0x20 + 0x00008000 + + + PRO_DCACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. + 0 + 24 + read-write + + + + + PRO_ICACHE_CTRL + register description + 0x40 + 0x20 + 0x00000100 + + + PRO_ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + PRO_ICACHE_SETSIZE_MODE + The bit is used to configure cache memory size.0: 8KB, 1: 16KB + 2 + 1 + read-write + + + PRO_ICACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + 3 + 1 + read-write + + + PRO_ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 8 + 1 + read-write + + + PRO_ICACHE_INVALIDATE_DONE + The bit is used to indicate invalidate operation is finished. + 9 + 1 + read-only + + + PRO_ICACHE_LOCK0_EN + The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG. + 14 + 1 + read-write + + + PRO_ICACHE_LOCK1_EN + The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG. + 15 + 1 + read-write + + + PRO_ICACHE_AUTOLOAD_ENA + The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable. + 18 + 1 + read-write + + + PRO_ICACHE_AUTOLOAD_DONE + The bit is used to indicate conditional-preload operation is finished. + 19 + 1 + read-only + + + PRO_ICACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 20 + 1 + read-write + + + PRO_ICACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 21 + 1 + read-only + + + PRO_ICACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 22 + 1 + read-write + + + PRO_ICACHE_UNLOCK_DONE + The bit is used to indicate unlock operation is finished. + 23 + 1 + read-only + + + PRO_ICACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 24 + 1 + read-write + + + PRO_ICACHE_LOCK_DONE + The bit is used to indicate lock operation is finished. + 25 + 1 + read-only + + + + + PRO_ICACHE_CTRL1 + register description + 0x44 + 0x20 + 0x00000007 + + + PRO_ICACHE_MASK_BUS0 + The bit is used to disable ibus0, 0: enable, 1: disable + 0 + 1 + read-write + + + PRO_ICACHE_MASK_BUS1 + The bit is used to disable ibus1, 0: enable, 1: disable + 1 + 1 + read-write + + + PRO_ICACHE_MASK_BUS2 + The bit is used to disable ibus2, 0: enable, 1: disable + 2 + 1 + read-write + + + + + PRO_ICACHE_TAG_POWER_CTRL + register description + 0x48 + 0x20 + 0x00000005 + + + PRO_ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + PRO_ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + PRO_ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + PRO_ICACHE_LOCK0_ADDR + register description + 0x4C + 0x20 + + + PRO_ICACHE_LOCK0_ADDR + The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG + 0 + 32 + read-write + + + + + PRO_ICACHE_LOCK0_SIZE + register description + 0x50 + 0x20 + + + PRO_ICACHE_LOCK0_SIZE + The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG + 0 + 16 + read-write + + + + + PRO_ICACHE_LOCK1_ADDR + register description + 0x54 + 0x20 + + + PRO_ICACHE_LOCK1_ADDR + The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG + 0 + 32 + read-write + + + + + PRO_ICACHE_LOCK1_SIZE + register description + 0x58 + 0x20 + + + PRO_ICACHE_LOCK1_SIZE + The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG + 0 + 16 + read-write + + + + + PRO_ICACHE_MEM_SYNC0 + register description + 0x5C + 0x20 + + + PRO_ICACHE_MEMSYNC_ADDR + The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1. + 0 + 32 + read-write + + + + + PRO_ICACHE_MEM_SYNC1 + register description + 0x60 + 0x20 + + + PRO_ICACHE_MEMSYNC_SIZE + The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0. + 0 + 19 + read-write + + + + + PRO_ICACHE_PRELOAD_ADDR + register description + 0x64 + 0x20 + + + PRO_ICACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + PRO_ICACHE_PRELOAD_SIZE + register description + 0x68 + 0x20 + 0x00000200 + + + PRO_ICACHE_PRELOAD_SIZE + The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.. + 0 + 10 + read-write + + + PRO_ICACHE_PRELOAD_ORDER + The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending. + 10 + 1 + read-write + + + + + PRO_ICACHE_AUTOLOAD_CFG + register description + 0x6C + 0x20 + + + PRO_ICACHE_AUTOLOAD_MODE + Reserved. + 0 + 1 + read-write + + + PRO_ICACHE_AUTOLOAD_STEP + Reserved. + 1 + 2 + read-write + + + PRO_ICACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending. + 3 + 1 + read-write + + + PRO_ICACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 4 + 2 + read-write + + + PRO_ICACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. + 6 + 2 + read-write + + + PRO_ICACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the second section for conditional pre-load operation. + 8 + 1 + read-write + + + PRO_ICACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the first section for conditional pre-load operation. + 9 + 1 + read-write + + + + + PRO_ICACHE_AUTOLOAD_SECTION0_ADDR + register description + 0x70 + 0x20 + + + PRO_ICACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + PRO_ICACHE_AUTOLOAD_SECTION0_SIZE + register description + 0x74 + 0x20 + 0x00008000 + + + PRO_ICACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. + 0 + 24 + read-write + + + + + PRO_ICACHE_AUTOLOAD_SECTION1_ADDR + register description + 0x78 + 0x20 + + + PRO_ICACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + PRO_ICACHE_AUTOLOAD_SECTION1_SIZE + register description + 0x7C + 0x20 + 0x00008000 + + + PRO_ICACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. + 0 + 24 + read-write + + + + + IC_PRELOAD_CNT + register description + 0x80 + 0x20 + + + IC_PRELOAD_CNT + The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. + 0 + 16 + read-only + + + + + IC_PRELOAD_MISS_CNT + register description + 0x84 + 0x20 + + + IC_PRELOAD_MISS_CNT + The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. + 0 + 16 + read-only + + + + + IBUS2_ABANDON_CNT + register description + 0x88 + 0x20 + + + IBUS2_ABANDON_CNT + The bits are used to count the number of the abandoned ibus2 access. + 0 + 16 + read-only + + + + + IBUS1_ABANDON_CNT + register description + 0x8C + 0x20 + + + IBUS1_ABANDON_CNT + The bits are used to count the number of the abandoned ibus1 access. + 0 + 16 + read-only + + + + + IBUS0_ABANDON_CNT + register description + 0x90 + 0x20 + + + IBUS0_ABANDON_CNT + The bits are used to count the number of the abandoned ibus0 access. + 0 + 16 + read-only + + + + + IBUS2_ACS_MISS_CNT + register description + 0x94 + 0x20 + + + IBUS2_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus2 access. + 0 + 32 + read-only + + + + + IBUS1_ACS_MISS_CNT + register description + 0x98 + 0x20 + + + IBUS1_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus1 access. + 0 + 32 + read-only + + + + + IBUS0_ACS_MISS_CNT + register description + 0x9C + 0x20 + + + IBUS0_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus0 access. + 0 + 32 + read-only + + + + + IBUS2_ACS_CNT + register description + 0xA0 + 0x20 + + + IBUS2_ACS_CNT + The bits are used to count the number of ibus2 access icache. + 0 + 32 + read-only + + + + + IBUS1_ACS_CNT + register description + 0xA4 + 0x20 + + + IBUS1_ACS_CNT + The bits are used to count the number of ibus1 access icache. + 0 + 32 + read-only + + + + + IBUS0_ACS_CNT + register description + 0xA8 + 0x20 + + + IBUS0_ACS_CNT + The bits are used to count the number of ibus0 access icache. + 0 + 32 + read-only + + + + + DC_PRELOAD_CNT + register description + 0xAC + 0x20 + + + DC_PRELOAD_CNT + The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. + 0 + 16 + read-only + + + + + DC_PRELOAD_EVICT_CNT + register description + 0xB0 + 0x20 + + + DC_PRELOAD_EVICT_CNT + The bits are used to count the number of cache evictions by pre-load which include manual pre-load and conditional pre-load. + 0 + 16 + read-only + + + + + DC_PRELOAD_MISS_CNT + register description + 0xB4 + 0x20 + + + DC_PRELOAD_MISS_CNT + The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. + 0 + 16 + read-only + + + + + DBUS2_ABANDON_CNT + register description + 0xB8 + 0x20 + + + DBUS2_ABANDON_CNT + The bits are used to count the number of the abandoned dbus2 access. + 0 + 16 + read-only + + + + + DBUS1_ABANDON_CNT + register description + 0xBC + 0x20 + + + DBUS1_ABANDON_CNT + The bits are used to count the number of the abandoned dbus1 access. + 0 + 16 + read-only + + + + + DBUS0_ABANDON_CNT + register description + 0xC0 + 0x20 + + + DBUS0_ABANDON_CNT + The bits are used to count the number of the abandoned dbus0 access. + 0 + 16 + read-only + + + + + DBUS2_ACS_WB_CNT + register description + 0xC4 + 0x20 + + + DBUS2_ACS_WB_CNT + The bits are used to count the number of cache evictions by dbus2 access cache. + 0 + 20 + read-only + + + + + DBUS1_ACS_WB_CNT + register description + 0xC8 + 0x20 + + + DBUS1_ACS_WB_CNT + The bits are used to count the number of cache evictions by dbus1 access cache. + 0 + 20 + read-only + + + + + DBUS0_ACS_WB_CNT + register description + 0xCC + 0x20 + + + DBUS0_ACS_WB_CNT + The bits are used to count the number of cache evictions by dbus0 access cache. + 0 + 20 + read-only + + + + + DBUS2_ACS_MISS_CNT + register description + 0xD0 + 0x20 + + + DBUS2_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus2 access. + 0 + 32 + read-only + + + + + DBUS1_ACS_MISS_CNT + register description + 0xD4 + 0x20 + + + DBUS1_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus1 access. + 0 + 32 + read-only + + + + + DBUS0_ACS_MISS_CNT + register description + 0xD8 + 0x20 + + + DBUS0_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus0 access. + 0 + 32 + read-only + + + + + DBUS2_ACS_CNT + register description + 0xDC + 0x20 + + + DBUS2_ACS_CNT + The bits are used to count the number of dbus2 access dcache. + 0 + 32 + read-only + + + + + DBUS1_ACS_CNT + register description + 0xE0 + 0x20 + + + DBUS1_ACS_CNT + The bits are used to count the number of dbus1 access dcache. + 0 + 32 + read-only + + + + + DBUS0_ACS_CNT + register description + 0xE4 + 0x20 + + + DBUS0_ACS_CNT + The bits are used to count the number of dbus0 access dcache. + 0 + 32 + read-only + + + + + CACHE_DBG_INT_ENA + register description + 0xE8 + 0x20 + 0x00000001 + + + CACHE_DBG_EN + The bit is used to activate the cache track function. 1: enable, 0: disable. + 0 + 1 + read-write + + + IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 2 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 3 + 1 + read-write + + + IC_SYNC_SIZE_FAULT_INT_ENA + The bit is used to enable interrupt by manual sync configurations fault. + 4 + 1 + read-write + + + IC_PRELOAD_SIZE_FAULT_INT_ENA + The bit is used to enable interrupt by manual pre-load configurations fault. + 5 + 1 + read-write + + + ICACHE_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 6 + 1 + read-write + + + ICACHE_SET_PRELOAD_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. + 7 + 1 + read-write + + + ICACHE_SET_SYNC_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. + 8 + 1 + read-write + + + ICACHE_SET_LOCK_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. + 9 + 1 + read-write + + + DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 10 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 11 + 1 + read-write + + + DC_SYNC_SIZE_FAULT_INT_ENA + The bit is used to enable interrupt by manual sync configurations fault. + 12 + 1 + read-write + + + DC_PRELOAD_SIZE_FAULT_INT_ENA + The bit is used to enable interrupt by manual pre-load configurations fault. + 13 + 1 + read-write + + + DCACHE_WRITE_FLASH_INT_ENA + The bit is used to enable interrupt by dcache trying to write flash. + 14 + 1 + read-write + + + DCACHE_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 15 + 1 + read-write + + + DCACHE_SET_PRELOAD_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations. + 16 + 1 + read-write + + + DCACHE_SET_SYNC_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations. + 17 + 1 + read-write + + + DCACHE_SET_LOCK_ILG_INT_ENA + The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations. + 18 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 19 + 1 + read-write + + + + + CACHE_DBG_INT_CLR + register description + 0xEC + 0x20 + + + IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 1 + 1 + write-only + + + IC_SYNC_SIZE_FAULT_INT_CLR + The bit is used to clear interrupt by manual sync configurations fault. + 2 + 1 + write-only + + + IC_PRELOAD_SIZE_FAULT_INT_CLR + The bit is used to clear interrupt by manual pre-load configurations fault. + 3 + 1 + write-only + + + ICACHE_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + ICACHE_SET_ILG_INT_CLR + The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. + 5 + 1 + write-only + + + DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 6 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 7 + 1 + write-only + + + DC_SYNC_SIZE_FAULT_INT_CLR + The bit is used to clear interrupt by manual sync configurations fault. + 8 + 1 + write-only + + + DC_PRELOAD_SIZE_FAULT_INT_CLR + The bit is used to clear interrupt by manual pre-load configurations fault. + 9 + 1 + write-only + + + DCACHE_WRITE_FLASH_INT_CLR + The bit is used to clear interrupt by dcache trying to write flash. + 10 + 1 + write-only + + + DCACHE_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 11 + 1 + write-only + + + DCACHE_SET_ILG_INT_CLR + The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations. + 12 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 13 + 1 + write-only + + + + + CACHE_DBG_STATUS0 + register description + 0xF0 + 0x20 + + + IBUS0_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + IBUS1_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access. + 1 + 1 + read-only + + + IBUS2_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access. + 2 + 1 + read-only + + + IBUS0_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus0 counter overflow. + 4 + 1 + read-only + + + IBUS1_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus1 counter overflow. + 5 + 1 + read-only + + + IBUS2_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus2 counter overflow. + 6 + 1 + read-only + + + IBUS0_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus0 miss counter overflow. + 8 + 1 + read-only + + + IBUS1_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus1 miss counter overflow. + 9 + 1 + read-only + + + IBUS2_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus2 miss counter overflow. + 10 + 1 + read-only + + + IBUS0_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by ibus0 abandon counter overflow. + 12 + 1 + read-only + + + IBUS1_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by ibus1 abandon counter overflow. + 13 + 1 + read-only + + + IBUS2_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by ibus2 abandon counter overflow. + 14 + 1 + read-only + + + IC_PRELOAD_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by pre-load miss counter overflow. + 16 + 1 + read-only + + + IC_PRELOAD_CNT_OVF_ST + The bit is used to indicate interrupt by pre-load counter overflow. + 18 + 1 + read-only + + + IC_SYNC_SIZE_FAULT_ST + The bit is used to indicate interrupt by manual sync configurations fault. + 19 + 1 + read-only + + + IC_PRELOAD_SIZE_FAULT_ST + The bit is used to indicate interrupt by manual pre-load configurations fault. + 20 + 1 + read-only + + + ICACHE_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 21 + 1 + read-only + + + ICACHE_SET_PRELOAD_ILG_ST + The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. + 22 + 1 + read-only + + + ICACHE_SET_SYNC_ILG_ST + The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. + 23 + 1 + read-only + + + ICACHE_SET_LOCK_ILG_ST + The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. + 24 + 1 + read-only + + + + + CACHE_DBG_STATUS1 + register description + 0xF4 + 0x20 + + + DBUS0_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access. + 0 + 1 + read-only + + + DBUS1_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access. + 1 + 1 + read-only + + + DBUS2_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access. + 2 + 1 + read-only + + + DBUS0_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus0 counter overflow. + 4 + 1 + read-only + + + DBUS1_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus1 counter overflow. + 5 + 1 + read-only + + + DBUS2_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus2 counter overflow. + 6 + 1 + read-only + + + DBUS0_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus0 miss counter overflow. + 8 + 1 + read-only + + + DBUS1_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus1 miss counter overflow. + 9 + 1 + read-only + + + DBUS2_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus2 miss counter overflow. + 10 + 1 + read-only + + + DBUS0_ACS_WB_CNT_OVF_ST + The bit is used to indicate interrupt by dbus0 eviction counter overflow. + 12 + 1 + read-only + + + DBUS1_ACS_WB_CNT_OVF_ST + The bit is used to indicate interrupt by dbus1 eviction counter overflow. + 13 + 1 + read-only + + + DBUS2_ACS_WB_CNT_OVF_ST + The bit is used to indicate interrupt by dbus2 eviction counter overflow. + 14 + 1 + read-only + + + DBUS0_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by dbus0 abandon counter overflow. + 16 + 1 + read-only + + + DBUS1_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by dbus1 abandon counter overflow. + 17 + 1 + read-only + + + DBUS2_ABANDON_CNT_OVF_ST + The bit is used to indicate interrupt by dbus2 abandon counter overflow. + 18 + 1 + read-only + + + DC_PRELOAD_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by pre-load miss counter overflow. + 20 + 1 + read-only + + + DC_PRELOAD_EVICT_CNT_OVF_ST + The bit is used to indicate interrupt by pre-load eviction counter overflow. + 21 + 1 + read-only + + + DC_PRELOAD_CNT_OVF_ST + The bit is used to indicate interrupt by pre-load counter overflow. + 22 + 1 + read-only + + + DC_SYNC_SIZE_FAULT_ST + The bit is used to indicate interrupt by manual sync configurations fault. + 23 + 1 + read-only + + + DC_PRELOAD_SIZE_FAULT_ST + The bit is used to indicate interrupt by manual pre-load configurations fault. + 24 + 1 + read-only + + + DCACHE_WRITE_FLASH_ST + The bit is used to indicate interrupt by dcache trying to write flash. + 25 + 1 + read-only + + + DCACHE_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 26 + 1 + read-only + + + DCACHE_SET_PRELOAD_ILG_ST + The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations. + 27 + 1 + read-only + + + DCACHE_SET_SYNC_ILG_ST + The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations. + 28 + 1 + read-only + + + DCACHE_SET_LOCK_ILG_ST + The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations. + 29 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 30 + 1 + read-only + + + + + PRO_CACHE_ACS_CNT_CLR + register description + 0xF8 + 0x20 + + + PRO_DCACHE_ACS_CNT_CLR + The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG. + 0 + 1 + write-only + + + PRO_ICACHE_ACS_CNT_CLR + The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG. + 1 + 1 + write-only + + + + + PRO_DCACHE_REJECT_ST + register description + 0xFC + 0x20 + + + PRO_DCACHE_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + PRO_DCACHE_CPU_ATTR + The bits are used to indicate the attribute of CPU access dcache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + + + PRO_DCACHE_REJECT_VADDR + register description + 0x100 + 0x20 + + + PRO_DCACHE_CPU_VADDR + The bits are used to indicate the virtual address of CPU access dcache when authentication fail. + 0 + 32 + read-only + + + + + PRO_ICACHE_REJECT_ST + register description + 0x104 + 0x20 + + + PRO_ICACHE_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + PRO_ICACHE_CPU_ATTR + The bits are used to indicate the attribute of CPU access icache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + + + PRO_ICACHE_REJECT_VADDR + register description + 0x108 + 0x20 + + + PRO_ICACHE_CPU_VADDR + The bits are used to indicate the virtual address of CPU access icache when authentication fail. + 0 + 32 + read-only + + + + + PRO_CACHE_MMU_FAULT_CONTENT + register description + 0x10C + 0x20 + + + PRO_CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 17 + read-only + + + PRO_CACHE_MMU_FAULT_CODE + The bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx + 17 + 3 + read-only + + + + + PRO_CACHE_MMU_FAULT_VADDR + register description + 0x110 + 0x20 + + + PRO_CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + PRO_CACHE_WRAP_AROUND_CTRL + register description + 0x114 + 0x20 + + + PRO_CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + PRO_CACHE_SRAM_RD_WRAP_AROUND + The bit is used to enable wrap around mode when read data from spiram. + 1 + 1 + read-write + + + + + PRO_CACHE_MMU_POWER_CTRL + register description + 0x118 + 0x20 + 0x00000005 + + + PRO_CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + PRO_CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + PRO_CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + PRO_CACHE_STATE + register description + 0x11C + 0x20 + + + PRO_ICACHE_STATE + The bit is used to indicate icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + PRO_DCACHE_STATE + The bit is used to indicate dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 12 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + register description + 0x120 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved. + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved. + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + register description + 0x124 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_DB_ENCRYPT + The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_G0CB_DECRYPT + The bit is used to close clock gating of decrypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT + The bit is used to close clock gating of encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_BRIDGE_ARBITER_CTRL + register description + 0x128 + 0x20 + + + ALLOC_WB_HOLD_ARBITER + Reserved. + 0 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + register description + 0x12C + 0x20 + + + PRO_ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + PRO_ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + PRO_ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + PRO_DCACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by dcache pre-load done. + 3 + 1 + read-only + + + PRO_DCACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by dcache pre-load done. + 4 + 1 + read-write + + + PRO_DCACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by dcache pre-load done. + 5 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + register description + 0x130 + 0x20 + + + PRO_ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + PRO_ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + PRO_ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + PRO_DCACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by dcache sync done. + 3 + 1 + read-only + + + PRO_DCACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by dcache sync done. + 4 + 1 + read-write + + + PRO_DCACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by dcache sync done. + 5 + 1 + write-only + + + + + CACHE_CONF_MISC + register description + 0x134 + 0x20 + 0x00000003 + + + PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + + + CLOCK_GATE + register description + 0x138 + 0x20 + 0x00000001 + + + CLK_EN + Reserved. + 0 + 1 + read-write + + + + + PRO_EXTMEM_REG_DATE + register description + 0x3FC + 0x20 + 0x01904180 + + + PRO_EXTMEM_REG_DATE + Reserved. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x3F404000 + + 0x0 + 0x634 + registers + + + GPIO + 23 + + + GPIO_NMI + 24 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + Reserved + 0 + 32 + read-write + + + + + OUT + GPIO0 ~ 31 output register + 0x4 + 0x20 + + + DATA_ORIG + GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid. + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO0 ~ 31 output bit set register + 0x8 + 0x20 + + + OUT_W1TS + GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT_REG. + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO0 ~ 31 output bit clear register + 0xC + 0x20 + + + OUT_W1TC + GPIO0 ~ 31 output clear register. If the value 1 is written to a bit here, the cor- responding bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT_REG. + 0 + 32 + write-only + + + + + OUT1 + GPIO32 ~ 53 output register + 0x10 + 0x20 + + + DATA_ORIG + GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid. + 0 + 22 + read-write + + + + + OUT1_W1TS + GPIO32 ~ 53 output bit set register + 0x14 + 0x20 + + + OUT1_W1TS + GPIO32 ~ 53 output value set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT1_REG. + 0 + 22 + write-only + + + + + OUT1_W1TC + GPIO32 ~ 53 output bit clear register + 0x18 + 0x20 + + + OUT1_W1TC + GPIO32 ~ 53 output value clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT1_REG. + 0 + 22 + write-only + + + + + SDIO_SELECT + GPIO SDIO selection register + 0x1C + 0x20 + + + SDIO_SEL + Reserved + 0 + 8 + read-write + + + + + ENABLE + GPIO0 ~ 31 output enable register + 0x20 + 0x20 + + + DATA + GPIO0~31 output enable register. + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO0 ~ 31 output enable bit set register + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE_REG. + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO0 ~ 31 output enable bit clear register + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO0 ~ 31 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE_REG. + 0 + 32 + write-only + + + + + ENABLE1 + GPIO32 ~ 53 output enable register + 0x2C + 0x20 + + + DATA + GPIO32~53 output enable register. + 0 + 22 + read-write + + + + + ENABLE1_W1TS + GPIO32 ~ 53 output enable bit set register + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO32 ~ 53 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE1_REG. + 0 + 22 + write-only + + + + + ENABLE1_W1TC + GPIO32 ~ 53 output enable bit clear register + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO32 ~ 53 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE1_REG. + 0 + 22 + write-only + + + + + STRAP + Bootstrap pin value register + 0x38 + 0x20 + + + STRAPPING + GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, GPIO0, and GPIO46 respectively. + 0 + 16 + read-only + + + + + IN + GPIO0 ~ 31 input register + 0x3C + 0x20 + + + DATA_NEXT + GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level. + 0 + 32 + read-write + + + + + IN1 + GPIO32 ~ 53 input register + 0x40 + 0x20 + + + IN_DATA1_NEXT + GPIO32 ~ 53 input value. Each bit represents a pad input value. + 0 + 22 + read-only + + + + + STATUS + GPIO0 ~ 31 interrupt status register + 0x44 + 0x20 + + + INTERRUPT + GPIO0 ~ 31 interrupt status register. + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO0 ~ 31 interrupt status bit set register + 0x48 + 0x20 + + + STATUS_W1TS + GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT. + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO0 ~ 31 interrupt status bit clear register + 0x4C + 0x20 + + + STATUS_W1TC + GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT. + 0 + 32 + write-only + + + + + STATUS1 + GPIO32 ~ 53 interrupt status register + 0x50 + 0x20 + + + INTERRUPT + GPIO32 ~ 53 interrupt status register. + 0 + 22 + read-write + + + + + STATUS1_W1TS + GPIO32 ~ 53 interrupt status bit set register + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. Recommended operation: use this register to set GPIO_STATUS1_REG. + 0 + 22 + write-only + + + + + STATUS1_W1TC + GPIO32 ~ 53 interrupt status bit clear register + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. Recommended operation: use this register to clear GPIO_STATUS1_REG. + 0 + 22 + write-only + + + + + PCPU_INT + GPIO0 ~ 31 PRO_CPU interrupt status register + 0x5C + 0x20 + + + PROCPU_INT + GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG). + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO0 ~ 31 CPU SDIO interrupt status register + 0x64 + 0x20 + + + SDIO_INT + GPIO0~31 CPU SDIO interrupt status. + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO32 ~ 53 PRO_CPU interrupt status register + 0x68 + 0x20 + + + PROCPU1_INT + GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 13 of GPIO_PINn_REG). + 0 + 22 + read-only + + + + + PCPU_NMI_INT1 + GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register + 0x6C + 0x20 + + + PROCPU_NMI1_INT + GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). + 0 + 22 + read-only + + + + + CPUSDIO_INT1 + GPIO32 ~ 53 CPU SDIO interrupt status register + 0x70 + 0x20 + + + SDIO1_INT + GPIO32~53 CPU SDIO interrupt status. + 0 + 22 + read-only + + + + + 54 + 0x4 + PIN%s + Configuration for GPIO pin %s + 0x74 + 0x20 + + + SYNC2_BYPASS + For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. + 0 + 2 + read-write + + + PAD_DRIVER + Pad driver selection. 0: normal output; 1: open drain output.. + 2 + 1 + read-write + + + SYNC1_BYPASS + For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge. + 3 + 2 + read-write + + + INT_TYPE + Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W) + 7 + 3 + read-write + + + WAKEUP_ENABLE + GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + 10 + 1 + read-write + + + CONFIG + Reserved + 11 + 2 + read-write + + + INT_ENA + Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO0 ~ 31 interrupt source register + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt. + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO32 ~ 53 interrupt source register + 0x150 + 0x20 + + + STATUS1_INTERRUPT_NEXT + Interrupt source signal of GPIO32 ~ 53. + 0 + 22 + read-only + + + + + 256 + 0x4 + FUNC%s_IN_SEL_CFG + Peripheral function %s input selection register + 0x154 + 0x20 + + + IN_SEL + Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input. + 0 + 6 + read-write + + + IN_INV_SEL + Invert the input value. 1: invert enabled; 0: invert disabled. + 6 + 1 + read-write + + + SEL + Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals directly to peripheral configured in IO_MUX. + 7 + 1 + read-write + + + + + 54 + 0x4 + FUNC%s_OUT_SEL_CFG + Peripheral output selection for GPIO %s + 0x554 + 0x20 + 0x00000100 + + + OUT_SEL + Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable. + 0 + 9 + read-write + + + INV_SEL + 0: Do not invert the output value; 1: Invert the output value. + 9 + 1 + read-write + + + OEN_SEL + 0: Use output enable signal from peripheral; 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. + 10 + 1 + read-write + + + OEN_INV_SEL + 0: Do not invert the output enable signal; 1: Invert the output enable signal. + 11 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gating register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + Clock gating enable bit. If set to 1, the clock is free running. + 0 + 1 + read-write + + + + + REG_DATE + Version control register + 0x6FC + 0x20 + 0x01905061 + + + DATE + Version control register + 0 + 28 + read-write + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x3F404F00 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty-cycle configuration register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD0_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD0_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + SIGMADELTA_CG + Clock gating configuration register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 31 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + SIGMADELTA_VERSION + Version control register + 0x28 + 0x20 + 0x01802260 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0x9C + registers + + + + SET_START + HMAC start control register + 0x40 + 0x20 + + + SET_START + Set this bit to enable HMAC. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + HMAC parameter configuration register + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + HMAC key configuration register + 0x48 + 0x20 + + + KEY_SET + Select hmac key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + HMAC configuration completion register + 0x4C + 0x20 + + + SET_PARA_END + Set this bit to finish HMAC configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + HMAC one message control register + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + HMAC message continue register + 0x54 + 0x20 + + + SET_TEXT_ING + Set this bit to show there are still some message blocks to be processed. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + HMAC message end register + 0x58 + 0x20 + + + SET_TEXT_END + Set this bit to start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + HMAC read result completion register + 0x5C + 0x20 + + + SET_RESULT_END + Set this bit to end upstream and clear the calculation result. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate JTAG result register + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Set this bit to clear calculation results in JTAG re-enable function under downstream mode. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate digital signature result register + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Set this bit to clear calculation results in DS function under downstream mode. + 0 + 1 + write-only + + + + + QUERY_ERROR + The matching result between key and purpose user configured + 0x68 + 0x20 + + + QUREY_CHECK + Hmac error status. + +0: hmac key and purpose match. + +1: error. + + + 0 + 1 + read-only + + + + + QUERY_BUSY + The busy state of HMAC module + 0x6C + 0x20 + + + BUSY_STATE + The state of Hmac. + +1'b0: idle. + +1'b1: busy. + + + 0 + 1 + read-only + + + + + 16 + 0x4 + WR_MESSAGE_%s + Message register %s + 0x80 + 0x20 + + + WDATA + Store the %sth 32-bit of message. + 0 + 32 + write-only + + + + + 8 + 0x4 + RD_RESULT_%s + Hash result register %s + 0xC0 + 0x20 + + + RDATA + Read the %sth 32-bit of hash result. + 0 + 32 + read-only + + + + + SET_MESSAGE_PAD + Software padding register + 0xF0 + 0x20 + + + SET_TEXT_PAD + Set this bit to let software do padding job. + 0 + 1 + write-only + + + + + ONE_BLOCK + One block message register. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Set this bit to show no padding is required. + 0 + 1 + write-only + + + + + DATE + Version control register + 0xF8 + 0x20 + 0x20190402 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x3F413000 + + 0x0 + 0xA8 + registers + + + I2C_EXT0 + 52 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 14 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000A0B + + + SDA_FORCE_OUT + 0: direct output. 1: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 0: direct output. 1: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. + +1: sample SDA data on the SCL low level. + +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in TX FIFO. + 5 + 1 + read-write + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. + +1: send data from the least significant bit. + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. + +1: receive data from the least significant bit. + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved. + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for I2C bus arbitration function. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the SCL_FSM. + 10 + 1 + read-write + + + REF_ALWAYS_ON + This register is used to control the REF_TICK. + 11 + 1 + read-write + + + + + SR + Describe I2C work status + 0x8 + 0x20 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK. 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave. 0: master writes to slave. + 1 + 1 + read-only + + + TIME_OUT + When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data bit, this field changes to 1. + 2 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data. 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + BYTE_TRANS + This field changes to 1 when one byte is transferred. + 6 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C TX FIFO is empty in slave mode. 2: stretching SCL low when I2C RX FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. + +0: Idle. 1: Address shift. 2: ACK address. 3: RX data. 4: TX data. 5: Send ACK. 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. + +0: Idle. 1: Start. 2: Negative edge. 3: Low. 4: Positive edge. 5: High. 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data + 0xC + 0x20 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB clock cycles. + 0 + 24 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 24 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register + 0x14 + 0x20 + + + RXFIFO_START_ADDR + This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. + 0 + 5 + read-only + + + RXFIFO_END_ADDR + This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. This value refreshes when an I2C_RXFIFO_UDF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated. + 5 + 5 + read-only + + + TXFIFO_START_ADDR + This is the offset address of the first sent data, as described in I2C_NONFIFO_TX_THRES. + 10 + 5 + read-only + + + TXFIFO_END_ADDR + This is the offset address of the last sent data, as described in I2C_NONFIFO_TX_THRES. + +The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated. + 15 + 5 + read-only + + + RX_UPDATE + Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR. + 20 + 1 + write-only + + + TX_UPDATE + Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR. + 21 + 1 + write-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register + 0x18 + 0x20 + 0x0555408B + + + RXFIFO_WM_THRHD + The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB non-FIFO mode. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset RX FIFO. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset TX FIFO. + 13 + 1 + read-write + + + NONFIFO_RX_THRES + When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data. + 14 + 6 + read-write + + + NONFIFO_TX_THRES + When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data. + 20 + 6 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty. + 26 + 1 + read-write + + + + + DATA + RX FIFO read data + 0x1C + 0x20 + + + FIFO_RDATA + The value of RX FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge + 0x30 + 0x20 + + + TIME + This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles. + 0 + 10 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge + 0x34 + 0x20 + + + TIME + This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles. + 0 + 10 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of the SCL clock + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 14 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles. + 14 + 14 + read-write + + + + + SCL_START_HOLD + Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles. + 0 + 10 + read-write + + + + + SCL_RSTART_SETUP + Configures the interval between the positive edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 10 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock edge for a stop condition + 0x48 + 0x20 + + + TIME + This register is used to configure the delay after the STOP condition, in I2C module clock cycles. + 0 + 14 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and SCL positive edge for a stop condition + 0x4C + 0x20 + + + TIME + This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 10 + read-write + + + + + SCL_FILTER_CFG + SCL filter configuration register + 0x50 + 0x20 + 0x00000010 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 4 + 1 + read-write + + + + + SDA_FILTER_CFG + SDA filter configuration register + 0x54 + 0x20 + 0x00000010 + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 4 + 1 + read-write + + + + + 16 + 0x4 + 0-15 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: + +op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. + +byte_num represents the number of bytes that need to be sent or received. + +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x98 + 0x20 + 0x00000100 + + + SCL_ST_TO + The threshold value of SCL_FSM state unchanged period. + 0 + 24 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x9C + 0x20 + 0x00000100 + + + SCL_MAIN_ST_TO + The threshold value of SCL_MAIN_FSM state unchanged period. + 0 + 24 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0xA0 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0xA4 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + + + DATE + Version control register + 0xF8 + 0x20 + 0x19052000 + + + DATE + This is the the version control register. + 0 + 32 + read-write + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller + 0x3F427000 + + I2C_EXT1 + 53 + + + + I2S + I2S (Inter-IC Sound) Controller + I2S + 0x3F40F000 + + 0x0 + 0x88 + registers + + + + CONF + I2S configuration register + 0x8 + 0x20 + 0x000C0300 + + + TX_RESET + Set this bit to reset transmitter. + 0 + 1 + write-only + + + RX_RESET + Set this bit to reset receiver. + 1 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset TX FIFO. + 2 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset RX FIFO. + 3 + 1 + write-only + + + TX_START + Set this bit to start transmitting data. + 4 + 1 + read-write + + + RX_START + Set this bit to start receiving data. + 5 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode. + 6 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode. + 7 + 1 + read-write + + + TX_RIGHT_FIRST + Set this bit to transmit right channel data first. + 8 + 1 + read-write + + + RX_RIGHT_FIRST + Set this bit to receive right channel data first. + 9 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode. + 10 + 1 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode. + 11 + 1 + read-write + + + TX_SHORT_SYNC + Set this bit to enable transmitter in PCM standard mode. + 12 + 1 + read-write + + + RX_SHORT_SYNC + Set this bit to enable receiver in PCM standard mode. + 13 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode. + 14 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode. + 15 + 1 + read-write + + + TX_MSB_RIGHT + Set this bit to place right channel data at the MSB in TX FIFO. + 16 + 1 + read-write + + + RX_MSB_RIGHT + Set this bit to place right channel data at the MSB in RX FIFO. + 17 + 1 + read-write + + + TX_LSB_FIRST_DMA + 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits. + 18 + 1 + read-write + + + RX_LSB_FIRST_DMA + 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits. + 19 + 1 + read-write + + + SIG_LOOPBACK + Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals. + 20 + 1 + read-write + + + TX_FIFO_RESET_ST + I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed. + 21 + 1 + read-only + + + RX_FIFO_RESET_ST + I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed. + 22 + 1 + read-only + + + TX_RESET_ST + I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed. + 23 + 1 + read-only + + + TX_DMA_EQUAL + 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel. + 24 + 1 + read-write + + + RX_DMA_EQUAL + 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel. + 25 + 1 + read-write + + + PRE_REQ_EN + Set this bit to enable I2S to prepare data earlier. + 26 + 1 + read-write + + + TX_BIG_ENDIAN + I2S TX byte endianness. + 27 + 1 + read-write + + + RX_BIG_ENDIAN + I2S RX byte endianness. + 28 + 1 + read-write + + + RX_RESET_ST + I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed. + 29 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC + 0x20 + + + RX_TAKE_DATA_INT_RAW + The raw interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. + 0 + 1 + read-only + + + TX_PUT_DATA_INT_RAW + The raw interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. + 1 + 1 + read-only + + + RX_WFULL_INT_RAW + The raw interrupt status bit for I2S_RX_WFULL_INT interrupt. + 2 + 1 + read-only + + + RX_REMPTY_INT_RAW + The raw interrupt status bit for I2S_RX_REMPTY_INT interrupt. + 3 + 1 + read-only + + + TX_WFULL_INT_RAW + The raw interrupt status bit for I2S_TX_WFULL_INT interrupt. + 4 + 1 + read-only + + + TX_REMPTY_INT_RAW + The raw interrupt status bit for I2S_TX_REMPTY_INT interrupt. + 5 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for I2S_RX_HUNG_INT interrupt. + 6 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for I2S_TX_HUNG_INT interrupt. + 7 + 1 + read-only + + + IN_DONE_INT_RAW + The raw interrupt status bit for I2S_IN_DONE_INT interrupt. + 8 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + The raw interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. + 9 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + Reserved. + 10 + 1 + read-only + + + OUT_DONE_INT_RAW + The raw interrupt status bit for I2S_OUT_DONE_INT interrupt. + 11 + 1 + read-only + + + OUT_EOF_INT_RAW + The raw interrupt status bit for I2S_OUT_EOF_INT interrupt. + 12 + 1 + read-only + + + IN_DSCR_ERR_INT_RAW + The raw interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_RAW + The raw interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_RAW + The raw interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + The raw interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. + 16 + 1 + read-only + + + V_SYNC_INT_RAW + The raw interrupt status bit for I2S_V_SYNC_INT interrupt. + 17 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x10 + 0x20 + + + RX_TAKE_DATA_INT_ST + The masked interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. + 0 + 1 + read-only + + + TX_PUT_DATA_INT_ST + The masked interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. + 1 + 1 + read-only + + + RX_WFULL_INT_ST + The masked interrupt status bit for I2S_RX_WFULL_INT interrupt. + 2 + 1 + read-only + + + RX_REMPTY_INT_ST + The masked interrupt status bit for I2S_RX_REMPTY_INT interrupt. + 3 + 1 + read-only + + + TX_WFULL_INT_ST + The masked interrupt status bit for I2S_TX_WFULL_INT interrupt. + 4 + 1 + read-only + + + TX_REMPTY_INT_ST + The masked interrupt status bit for I2S_TX_REMPTY_INT interrupt. + 5 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for I2S_RX_HUNG_INT interrupt. + 6 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for I2S_TX_HUNG_INT interrupt. + 7 + 1 + read-only + + + IN_DONE_INT_ST + The masked interrupt status bit for I2S_IN_DONE_INT interrupt. + 8 + 1 + read-only + + + IN_SUC_EOF_INT_ST + The masked interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. + 9 + 1 + read-only + + + IN_ERR_EOF_INT_ST + Reserved. + 10 + 1 + read-only + + + OUT_DONE_INT_ST + The masked interrupt status bit for I2S_OUT_DONE_INT interrupt. + 11 + 1 + read-only + + + OUT_EOF_INT_ST + The masked interrupt status bit for I2S_OUT_EOF_INT interrupt. + 12 + 1 + read-only + + + IN_DSCR_ERR_INT_ST + The masked interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. + 13 + 1 + read-only + + + OUT_DSCR_ERR_INT_ST + The masked interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. + 14 + 1 + read-only + + + IN_DSCR_EMPTY_INT_ST + The masked interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. + 15 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + The masked interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. + 16 + 1 + read-only + + + V_SYNC_INT_ST + The masked interrupt status bit for I2S_V_SYNC_INT interrupt. + 17 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x14 + 0x20 + + + RX_TAKE_DATA_INT_ENA + The interrupt enable bit for I2S_RX_TAKE_DATA_INT interrupt. + 0 + 1 + read-write + + + TX_PUT_DATA_INT_ENA + The interrupt enable bit for I2S_TX_PUT_DATA_INT interrupt. + 1 + 1 + read-write + + + RX_WFULL_INT_ENA + The interrupt enable bit for I2S_RX_WFULL_INT interrupt. + 2 + 1 + read-write + + + RX_REMPTY_INT_ENA + The interrupt enable bit for I2S_RX_REMPTY_INT interrupt. + 3 + 1 + read-write + + + TX_WFULL_INT_ENA + The interrupt enable bit for I2S_TX_WFULL_INT interrupt. + 4 + 1 + read-write + + + TX_REMPTY_INT_ENA + The interrupt enable bit for I2S_TX_REMPTY_INT interrupt. + 5 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for I2S_RX_HUNG_INT interrupt. + 6 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for I2S_TX_HUNG_INT interrupt. + 7 + 1 + read-write + + + IN_DONE_INT_ENA + The interrupt enable bit for I2S_IN_DONE_INT interrupt. + 8 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + The interrupt enable bit for I2S_IN_SUC_EOF_INT interrupt. + 9 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + Reserved. + 10 + 1 + read-write + + + OUT_DONE_INT_ENA + The interrupt enable bit for I2S_OUT_DONE_INT interrupt. + 11 + 1 + read-write + + + OUT_EOF_INT_ENA + The interrupt enable bit for I2S_OUT_EOF_INT interrupt. + 12 + 1 + read-write + + + IN_DSCR_ERR_INT_ENA + The interrupt enable bit for I2S_IN_DSCR_ERR_INT interrupt. + 13 + 1 + read-write + + + OUT_DSCR_ERR_INT_ENA + The interrupt enable bit for I2S_OUT_DSCR_ERR_INT interrupt. + 14 + 1 + read-write + + + IN_DSCR_EMPTY_INT_ENA + The interrupt enable bit for I2S_IN_DSCR_EMPTY_INT interrupt. + 15 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + The interrupt enable bit for I2S_OUT_TOTAL_EOF_INT interrupt. + 16 + 1 + read-write + + + V_SYNC_INT_ENA + The interrupt enable bit for I2S_V_SYNC_INT interrupt. + 17 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x18 + 0x20 + + + TAKE_DATA_INT_CLR + Set this bit to clear I2S_RX_TAKE_DATA_INT interrupt. + 0 + 1 + write-only + + + PUT_DATA_INT_CLR + Set this bit to clear I2S_TX_PUT_DATA_INT interrupt. + 1 + 1 + write-only + + + RX_WFULL_INT_CLR + Set this bit to clear I2S_RX_WFULL_INT interrupt. + 2 + 1 + write-only + + + RX_REMPTY_INT_CLR + Set this bit to clear I2S_RX_REMPTY_INT interrupt. + 3 + 1 + write-only + + + TX_WFULL_INT_CLR + Set this bit to clear I2S_TX_WFULL_INT interrupt. + 4 + 1 + write-only + + + TX_REMPTY_INT_CLR + Set this bit to clear I2S_TX_REMPTY_INT interrupt. + 5 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear I2S_RX_HUNG_INT interrupt. + 6 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear I2S_TX_HUNG_INT interrupt. + 7 + 1 + write-only + + + IN_DONE_INT_CLR + Set this bit to clear I2S_IN_DONE_INT interrupt. + 8 + 1 + write-only + + + IN_SUC_EOF_INT_CLR + Set this bit to clear I2S_IN_SUC_EOF_INT interrupt. + 9 + 1 + write-only + + + IN_ERR_EOF_INT_CLR + Reserved. + 10 + 1 + write-only + + + OUT_DONE_INT_CLR + Set this bit to clear I2S_OUT_DONE_INT interrupt. + 11 + 1 + write-only + + + OUT_EOF_INT_CLR + Set this bit to clear I2S_OUT_EOF_INT interrupt. + 12 + 1 + write-only + + + IN_DSCR_ERR_INT_CLR + Set this bit to clear I2S_IN_DSCR_ERR_INT interrupt. + 13 + 1 + write-only + + + OUT_DSCR_ERR_INT_CLR + Set this bit to clear I2S_OUT_DSCR_ERR_INT interrupt. + 14 + 1 + write-only + + + IN_DSCR_EMPTY_INT_CLR + Set this bit to clear I2S_IN_DSCR_EMPTY_INT interrupt. + 15 + 1 + write-only + + + OUT_TOTAL_EOF_INT_CLR + Set this bit to clear I2S_OUT_TOTAL_EOF_INT interrupt. + 16 + 1 + write-only + + + V_SYNC_INT_CLR + Set this bit to clear I2S_V_SYNC_INT interrupt. + 17 + 1 + write-only + + + + + TIMING + I2S timing register + 0x1C + 0x20 + + + TX_BCK_IN_DELAY + Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 0 + 2 + read-write + + + TX_WS_IN_DELAY + Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 2 + 2 + read-write + + + RX_BCK_IN_DELAY + Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 4 + 2 + read-write + + + RX_WS_IN_DELAY + Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 6 + 2 + read-write + + + RX_SD_IN_DELAY + Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 8 + 2 + read-write + + + TX_BCK_OUT_DELAY + Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. + 10 + 2 + read-write + + + TX_WS_OUT_DELAY + Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. + 12 + 2 + read-write + + + TX_SD_OUT_DELAY + Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. + 14 + 2 + read-write + + + RX_WS_OUT_DELAY + Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. + 16 + 2 + read-write + + + RX_BCK_OUT_DELAY + Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles. + 18 + 2 + read-write + + + TX_DSYNC_SW + Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge. + 20 + 1 + read-write + + + RX_DSYNC_SW + Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge. + 21 + 1 + read-write + + + DATA_ENABLE_DELAY + Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles. + 22 + 2 + read-write + + + TX_BCK_IN_INV + Set this bit to invert BCK signal input to the slave transmitter. + 24 + 1 + read-write + + + + + FIFO_CONF + I2S FIFO configuration register + 0x20 + 0x20 + 0x00001820 + + + RX_DATA_NUM + I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM[5:0]. (RX FIFO is almost full threshold.) + 0 + 6 + read-write + + + TX_DATA_NUM + I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM[5:0]. (TX FIFO is almost empty threshold.) + 6 + 6 + read-write + + + DSCR_EN + Set this bit to enable I2S DMA mode. + 12 + 1 + read-write + + + TX_FIFO_MOD + Transmitter FIFO mode configuration bits + 13 + 3 + read-write + + + RX_FIFO_MOD + Receiver FIFO mode configuration bits + 16 + 3 + read-write + + + TX_FIFO_MOD_FORCE_EN + The bit should always be set to 1 + 19 + 1 + read-write + + + RX_FIFO_MOD_FORCE_EN + The bit should always be set to 1 + 20 + 1 + read-write + + + RX_FIFO_SYNC + force write back rx data to memory + 21 + 1 + read-write + + + RX_24MSB_EN + Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo + 22 + 1 + read-write + + + TX_24MSB_EN + Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo + 23 + 1 + read-write + + + + + RXEOF_NUM + I2S DMA RX EOF data length + 0x24 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT. + 0 + 32 + read-write + + + + + CONF_SIGLE_DATA + Constant single channel data + 0x28 + 0x20 + + + SIGLE_DATA + The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT. + 0 + 32 + read-write + + + + + CONF_CHAN + I2S channel configuration register + 0x2C + 0x20 + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 0 + 3 + read-write + + + RX_CHAN_MOD + I2S receiver channel mode configuration bits. + 3 + 2 + read-write + + + + + OUT_LINK + I2S DMA TX configuration register + 0x30 + 0x20 + + + OUTLINK_ADDR + The address of first outlink descriptor. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop outlink descriptor. + 28 + 1 + read-write + + + OUTLINK_START + Set this bit to start outlink descriptor. + 29 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart outlink descriptor. + 30 + 1 + read-write + + + OUTLINK_PARK + 31 + 1 + read-only + + + + + IN_LINK + I2S DMA RX configuration register + 0x34 + 0x20 + + + INLINK_ADDR + The address of first inlink descriptor. + 0 + 20 + read-write + + + INLINK_STOP + Set this bit to stop inlink descriptor. + 28 + 1 + read-write + + + INLINK_START + Set this bit to start inlink descriptor. + 29 + 1 + read-write + + + INLINK_RESTART + Set this bit to restart inlink descriptor. + 30 + 1 + read-write + + + INLINK_PARK + 31 + 1 + read-only + + + + + OUT_EOF_DES_ADDR + Address of outlink descriptor that produces EOF + 0x38 + 0x20 + + + OUT_EOF_DES_ADDR + The address of outlink descriptor that produces EOF. + 0 + 32 + read-only + + + + + IN_EOF_DES_ADDR + Address of inlink descriptor that produces EOF + 0x3C + 0x20 + + + IN_SUC_EOF_DES_ADDR + The address of inlink descriptor that produces EOF. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR + Address of buffer relative to the outlink descriptor that produces EOF + 0x40 + 0x20 + + + OUT_EOF_BFR_DES_ADDR + The address of buffer relative to the outlink descriptor that produces EOF. + 0 + 32 + read-only + + + + + INLINK_DSCR + Address of current inlink descriptor + 0x48 + 0x20 + + + INLINK_DSCR + The address of current inlink descriptor. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF0 + Address of next inlink descriptor + 0x4C + 0x20 + + + INLINK_DSCR_BF0 + The address of next inlink descriptor. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF1 + Address of next inlink data buffer + 0x50 + 0x20 + + + INLINK_DSCR_BF1 + The address of next inlink data buffer. + 0 + 32 + read-only + + + + + OUTLINK_DSCR + Address of current outlink descriptor + 0x54 + 0x20 + + + OUTLINK_DSCR + The address of current outlink descriptor. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF0 + Address of next outlink descriptor + 0x58 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of next outlink descriptor. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF1 + Address of next outlink data buffer + 0x5C + 0x20 + + + OUTLINK_DSCR_BF1 + The address of next outlink data buffer. + 0 + 32 + read-only + + + + + LC_CONF + I2S DMA configuration register + 0x60 + 0x20 + 0x00000100 + + + IN_RST + Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration. + 0 + 1 + read-write + + + OUT_RST + Set this bit to reset out-DMA FSM. Set this bit before the DMA configuration. + 1 + 1 + read-write + + + AHBM_FIFO_RST + Set this bit to reset AHB interface cmdFIFO of DMA. Set this bit before the DMA configuration. + 2 + 1 + read-write + + + AHBM_RST + Set this bit to reset AHB interface of DMA. Set this bit before the DMA configuration. + 3 + 1 + read-write + + + OUT_LOOP_TEST + Set this bit to loop test inlink. + 4 + 1 + read-write + + + IN_LOOP_TEST + Set this bit to loop test outlink. + 5 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable outlink-written-back automatically when out buffer is transmitted done. + 6 + 1 + read-write + + + OUT_NO_RESTART_CLR + Reserved. + 7 + 1 + read-write + + + OUT_EOF_MODE + DMA out EOF flag generation mode. 1: When DMA has popped all data from the FIFO. 0: When AHB has pushed all data to the FIFO. + 8 + 1 + read-write + + + OUTDSCR_BURST_EN + DMA outlink descriptor transfer mode configuration bit. 1: Prepare outlink descriptor with burst mode. 0: Prepare outlink descriptor with byte mode. + 9 + 1 + read-write + + + INDSCR_BURST_EN + DMA inlink descriptor transfer mode configuration bit. 1: Prepare inlink descriptor with burst mode. 0: Prepare inlink descriptor with byte mode. + 10 + 1 + read-write + + + OUT_DATA_BURST_EN + Transmitter data transfer mode configuration bit. 1: Prepare out data with burst mode. 0: Prepare out data with byte mode. + 11 + 1 + read-write + + + CHECK_OWNER + Set this bit to enable check owner bit by hardware. + 12 + 1 + read-write + + + MEM_TRANS_EN + Reserved. + 13 + 1 + read-write + + + EXT_MEM_BK_SIZE + DMA access external memory block size. 0: 16 bytes. 1: 32 bytes. 2: 64 bytes. 3: reserved. + 14 + 2 + read-write + + + + + OUTFIFO_PUSH + APB out FIFO mode register + 0x64 + 0x20 + + + OUTFIFO_WDATA + APB out FIFO write data. + 0 + 9 + read-write + + + OUTFIFO_PUSH + APB out FIFO push. + 16 + 1 + read-write + + + + + INFIFO_POP + APB in FIFO mode register + 0x68 + 0x20 + + + INFIFO_RDATA + APB in FIFO read data. + 0 + 12 + read-only + + + INFIFO_POP + APB in FIFO pop. + 16 + 1 + read-write + + + + + LC_STATE0 + I2S DMA TX status + 0x6C + 0x20 + + + OUTLINK_DSCR_ADDR + I2S DMA out descriptor address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + I2S DMA out descriptor state. + 18 + 2 + read-only + + + OUT_STATE + I2S DMA out data state. + 20 + 3 + read-only + + + OUTFIFO_CNT + The remains of I2S DMA outfifo data. + 23 + 7 + read-only + + + OUT_FULL + I2S DMA outfifo is full. + 30 + 1 + read-only + + + OUT_EMPTY + I2S DMA outfifo is empty. + 31 + 1 + read-only + + + + + LC_STATE1 + I2S DMA RX status + 0x70 + 0x20 + + + INLINK_DSCR_ADDR + I2S DMA in descriptor address. + 0 + 18 + read-only + + + IN_DSCR_STATE + I2S DMA in descriptor state. + 18 + 2 + read-only + + + IN_STATE + I2S DMA in data state. + 20 + 3 + read-only + + + INFIFO_CNT_DEBUG + The remains of I2S DMA infifo data. + 23 + 7 + read-only + + + IN_FULL + I2S DMA infifo is full. + 30 + 1 + read-only + + + IN_EMPTY + I2S DMA infifo is empty. + 31 + 1 + read-only + + + + + LC_HUNG_CONF + I2S Hung configuration register + 0x74 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value. + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to set the tick counter threshold. The tick counter is clocked by APB_CLK. The tick counter threshold is 88000/2^I2S_LC_FIFO_TIMEOUT_SHIFT. The tick counter is reset when it reaches the threshold. + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout. + 11 + 1 + read-write + + + + + CONF1 + I2S configuration register 1 + 0xA0 + 0x20 + 0x00000089 + + + TX_PCM_CONF + Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data + 0 + 3 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 3 + 1 + read-write + + + RX_PCM_CONF + Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data + 4 + 3 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 7 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop the output of BCK signal and WS signal when TX FIFO is empty. + 8 + 1 + read-write + + + TX_ZEROS_RM_EN + Reserved. + 9 + 1 + read-write + + + + + PD_CONF + I2S power-down configuration register + 0xA4 + 0x20 + 0x0000002A + + + FIFO_FORCE_PD + Force FIFO power-down. + 0 + 1 + read-write + + + FIFO_FORCE_PU + Force FIFO power-up. + 1 + 1 + read-write + + + PLC_MEM_FORCE_PD + Force I2S memory power-down. + 2 + 1 + read-write + + + PLC_MEM_FORCE_PU + Force I2S memory power-up. + 3 + 1 + read-write + + + DMA_RAM_FORCE_PD + Force DMA FIFO power-down. + 4 + 1 + read-write + + + DMA_RAM_FORCE_PU + Force DMA FIFO power-up. + 5 + 1 + read-write + + + DMA_RAM_CLK_FO + Set this bit to force on DMA RAM clock. + 6 + 1 + read-write + + + + + CONF2 + I2S configuration register 2 + 0xA8 + 0x20 + + + CAMERA_EN + Set this bit to enable camera mode. + 0 + 1 + read-write + + + LCD_TX_WRX2_EN + LCD WR double for one datum. + 1 + 1 + read-write + + + LCD_TX_SDX2_EN + Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. + 2 + 1 + read-write + + + DATA_ENABLE_TEST_EN + for debug camera mode enable + 3 + 1 + read-write + + + DATA_ENABLE + for debug camera mode enable + 4 + 1 + read-write + + + LCD_EN + Set this bit to enable LCD mode. + 5 + 1 + read-write + + + EXT_ADC_START_EN + Set this bit to enable the function that ADC mode is triggered by external signal. + 6 + 1 + read-write + + + INTER_VALID_EN + Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks. + 7 + 1 + read-write + + + CAM_SYNC_FIFO_RESET + Set this bit to reset FIFO in camera mode. + 8 + 1 + read-write + + + CAM_CLK_LOOPBACK + Set this bit to loopback PCLK from I2S0I_WS_out. + 9 + 1 + read-write + + + VSYNC_FILTER_EN + Set this bit to enable I2S VSYNC filter function. + 10 + 1 + read-write + + + VSYNC_FILTER_THRES + Configure the I2S VSYNC filter threshold value. + 11 + 3 + read-write + + + + + CLKM_CONF + I2S module clock configuration register + 0xAC + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral I2S clock divider value. + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value. + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value. + 14 + 6 + read-write + + + CLK_EN + Set this bit to enable clock gate. + 20 + 1 + read-write + + + CLK_SEL + Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock. + 21 + 2 + read-write + + + + + SAMPLE_RATE_CONF + I2S sample rate register + 0xB0 + 0x20 + 0x00410186 + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 0 + 6 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 6 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure bit length of I2S transmitter channel, the value of which can only be 8, 16, 24 and 32. + 12 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure bit length of I2S receiver channel, the value of which can only be 8, 16, 24 and 32. + 18 + 6 + read-write + + + + + STATE + I2S TX status register + 0xBC + 0x20 + 0x00000001 + + + TX_IDLE + 1: I2S TX is in idle state. 0: I2S TX is at work. + 0 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19052500 + + + DATE + Version control register + 0 + 32 + read-write + + + + + + + INTERRUPT + Interrupt + INTERRUPT + 0x3F4C2000 + + 0x0 + 0x190 + registers + + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + + PRO_MAC_INTR_MAP + MAC_INTR interrupt configuration register + 0x0 + 0x20 + 0x00000010 + + + PRO_MAC_INTR_MAP + This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_MAC_NMI_MAP + MAC_NMI interrupt configuration register + 0x4 + 0x20 + 0x00000010 + + + PRO_MAC_NMI_MAP + This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PWR_INTR_MAP + PWR_INTR interrupt configuration register + 0x8 + 0x20 + 0x00000010 + + + PRO_PWR_INTR_MAP + This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_BB_INT_MAP + BB_INT interrupt configuration register + 0xC + 0x20 + 0x00000010 + + + PRO_BB_INT_MAP + This register is used to map BB_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_BT_MAC_INT_MAP + BT_MAC_INT interrupt configuration register + 0x10 + 0x20 + 0x00000010 + + + PRO_BT_MAC_INT_MAP + This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_BT_BB_INT_MAP + BT_BB_INT interrupt configuration register + 0x14 + 0x20 + 0x00000010 + + + PRO_BT_BB_INT_MAP + This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_BT_BB_NMI_MAP + BT_BB_NMI interrupt configuration register + 0x18 + 0x20 + 0x00000010 + + + PRO_BT_BB_NMI_MAP + This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RWBT_IRQ_MAP + RWBT_IRQ interrupt configuration register + 0x1C + 0x20 + 0x00000010 + + + PRO_RWBT_IRQ_MAP + This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RWBLE_IRQ_MAP + RWBLE_IRQ interrupt configuration register + 0x20 + 0x20 + 0x00000010 + + + PRO_RWBLE_IRQ_MAP + This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RWBT_NMI_MAP + RWBT_NMI interrupt configuration register + 0x24 + 0x20 + 0x00000010 + + + PRO_RWBT_NMI_MAP + This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RWBLE_NMI_MAP + RWBLE_NMI interrupt configuration register + 0x28 + 0x20 + 0x00000010 + + + PRO_RWBLE_NMI_MAP + This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SLC0_INTR_MAP + SLC0_INTR interrupt configuration register + 0x2C + 0x20 + 0x00000010 + + + PRO_SLC0_INTR_MAP + This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SLC1_INTR_MAP + SLC1_INTR interrupt configuration register + 0x30 + 0x20 + 0x00000010 + + + PRO_SLC1_INTR_MAP + This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_UHCI0_INTR_MAP + UHCI0_INTR interrupt configuration register + 0x34 + 0x20 + 0x00000010 + + + PRO_UHCI0_INTR_MAP + This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_UHCI1_INTR_MAP + UHCI1_INTR interrupt configuration register + 0x38 + 0x20 + 0x00000010 + + + PRO_UHCI1_INTR_MAP + This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_T0_LEVEL_INT_MAP + TG_T0_LEVEL_INT interrupt configuration register + 0x3C + 0x20 + 0x00000010 + + + PRO_TG_T0_LEVEL_INT_MAP + This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_T1_LEVEL_INT_MAP + TG_T1_LEVEL_INT interrupt configuration register + 0x40 + 0x20 + 0x00000010 + + + PRO_TG_T1_LEVEL_INT_MAP + This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_WDT_LEVEL_INT_MAP + TG_WDT_LEVEL_INT interrupt configuration register + 0x44 + 0x20 + 0x00000010 + + + PRO_TG_WDT_LEVEL_INT_MAP + This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_LACT_LEVEL_INT_MAP + TG_LACT_LEVEL_INT interrupt configuration register + 0x48 + 0x20 + 0x00000010 + + + PRO_TG_LACT_LEVEL_INT_MAP + This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_T0_LEVEL_INT_MAP + TG1_T0_LEVEL_INT interrupt configuration register + 0x4C + 0x20 + 0x00000010 + + + PRO_TG1_T0_LEVEL_INT_MAP + This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_T1_LEVEL_INT_MAP + TG1_T1_LEVEL_INT interrupt configuration register + 0x50 + 0x20 + 0x00000010 + + + PRO_TG1_T1_LEVEL_INT_MAP + This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_WDT_LEVEL_INT_MAP + TG1_WDT_LEVEL_INT interrupt configuration register + 0x54 + 0x20 + 0x00000010 + + + PRO_TG1_WDT_LEVEL_INT_MAP + This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_LACT_LEVEL_INT_MAP + TG1_LACT_LEVEL_INT interrupt configuration register + 0x58 + 0x20 + 0x00000010 + + + PRO_TG1_LACT_LEVEL_INT_MAP + This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_PRO_MAP + GPIO_INTERRUPT_PRO interrupt configuration register + 0x5C + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_PRO_MAP + This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_PRO_NMI_MAP + GPIO_INTERRUPT_PRO_NMI interrupt configuration register + 0x60 + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_PRO_NMI_MAP + This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_APP_MAP + GPIO_INTERRUPT_APP interrupt configuration register + 0x64 + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_APP_MAP + This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_GPIO_INTERRUPT_APP_NMI_MAP + GPIO_INTERRUPT_APP_NMI interrupt configuration register + 0x68 + 0x20 + 0x00000010 + + + PRO_GPIO_INTERRUPT_APP_NMI_MAP + This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_DEDICATED_GPIO_IN_INTR_MAP + DEDICATED_GPIO_IN_INTR interrupt configuration register + 0x6C + 0x20 + 0x00000010 + + + PRO_DEDICATED_GPIO_IN_INTR_MAP + This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_0_MAP + CPU_INTR_FROM_CPU_0 interrupt configuration register + 0x70 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_0_MAP + This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_1_MAP + CPU_INTR_FROM_CPU_1 interrupt configuration register + 0x74 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_1_MAP + This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_2_MAP + CPU_INTR_FROM_CPU_2 interrupt configuration register + 0x78 + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_2_MAP + This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CPU_INTR_FROM_CPU_3_MAP + CPU_INTR_FROM_CPU_3 interrupt configuration register + 0x7C + 0x20 + 0x00000010 + + + PRO_CPU_INTR_FROM_CPU_3_MAP + This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI_INTR_1_MAP + SPI_INTR_1 interrupt configuration register + 0x80 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_1_MAP + This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI_INTR_2_MAP + SPI_INTR_2 interrupt configuration register + 0x84 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_2_MAP + This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI_INTR_3_MAP + SPI_INTR_3 interrupt configuration register + 0x88 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_3_MAP + This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_I2S0_INT_MAP + I2S0_INT interrupt configuration register + 0x8C + 0x20 + 0x00000010 + + + PRO_I2S0_INT_MAP + This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_I2S1_INT_MAP + I2S1_INT interrupt configuration register + 0x90 + 0x20 + 0x00000010 + + + PRO_I2S1_INT_MAP + This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_UART_INTR_MAP + UART_INT interrupt configuration register + 0x94 + 0x20 + 0x00000010 + + + PRO_UART_INTR_MAP + This register is used to map UART_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_UART1_INTR_MAP + UART1_INT interrupt configuration register + 0x98 + 0x20 + 0x00000010 + + + PRO_UART1_INTR_MAP + This register is used to map UART1_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_UART2_INTR_MAP + UART2_INT interrupt configuration register + 0x9C + 0x20 + 0x00000010 + + + PRO_UART2_INTR_MAP + This register is used to map UART2_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SDIO_HOST_INTERRUPT_MAP + SDIO_HOST_INTERRUPT configuration register + 0xA0 + 0x20 + 0x00000010 + + + PRO_SDIO_HOST_INTERRUPT_MAP + This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PWM0_INTR_MAP + PWM0_INTR interrupt configuration register + 0xA4 + 0x20 + 0x00000010 + + + PRO_PWM0_INTR_MAP + This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PWM1_INTR_MAP + PWM1_INTR interrupt configuration register + 0xA8 + 0x20 + 0x00000010 + + + PRO_PWM1_INTR_MAP + This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PWM2_INTR_MAP + PWM2_INTR interrupt configuration register + 0xAC + 0x20 + 0x00000010 + + + PRO_PWM2_INTR_MAP + This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PWM3_INTR_MAP + PWM3_INTR interrupt configuration register + 0xB0 + 0x20 + 0x00000010 + + + PRO_PWM3_INTR_MAP + This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_LEDC_INT_MAP + LEDC_INTR interrupt configuration register + 0xB4 + 0x20 + 0x00000010 + + + PRO_LEDC_INT_MAP + This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_EFUSE_INT_MAP + EFUSE_INT interrupt configuration register + 0xB8 + 0x20 + 0x00000010 + + + PRO_EFUSE_INT_MAP + This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CAN_INT_MAP + CAN_INT interrupt configuration register + 0xBC + 0x20 + 0x00000010 + + + PRO_CAN_INT_MAP + This register is used to map CAN_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_USB_INTR_MAP + USB_INT interrupt configuration register + 0xC0 + 0x20 + 0x00000010 + + + PRO_USB_INTR_MAP + This register is used to map USB_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RTC_CORE_INTR_MAP + RTC_CORE_INTR interrupt configuration register + 0xC4 + 0x20 + 0x00000010 + + + PRO_RTC_CORE_INTR_MAP + This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RMT_INTR_MAP + RMT_INTR interrupt configuration register + 0xC8 + 0x20 + 0x00000010 + + + PRO_RMT_INTR_MAP + This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PCNT_INTR_MAP + PCNT_INTR interrupt configuration register + 0xCC + 0x20 + 0x00000010 + + + PRO_PCNT_INTR_MAP + This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_I2C_EXT0_INTR_MAP + I2C_EXT0_INTR interrupt configuration register + 0xD0 + 0x20 + 0x00000010 + + + PRO_I2C_EXT0_INTR_MAP + This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_I2C_EXT1_INTR_MAP + I2C_EXT1_INTR interrupt configuration register + 0xD4 + 0x20 + 0x00000010 + + + PRO_I2C_EXT1_INTR_MAP + This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_RSA_INTR_MAP + RSA_INTR interrupt configuration register + 0xD8 + 0x20 + 0x00000010 + + + PRO_RSA_INTR_MAP + This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SHA_INTR_MAP + SHA_INTR interrupt configuration register + 0xDC + 0x20 + 0x00000010 + + + PRO_SHA_INTR_MAP + This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_AES_INTR_MAP + AES_INTR interrupt configuration register + 0xE0 + 0x20 + 0x00000010 + + + PRO_AES_INTR_MAP + This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI2_DMA_INT_MAP + SPI2_DMA_INT interrupt configuration register + 0xE4 + 0x20 + 0x00000010 + + + PRO_SPI2_DMA_INT_MAP + This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI3_DMA_INT_MAP + SPI3_DMA_INT interrupt configuration register + 0xE8 + 0x20 + 0x00000010 + + + PRO_SPI3_DMA_INT_MAP + This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_WDG_INT_MAP + WDG_INT interrupt configuration register + 0xEC + 0x20 + 0x00000010 + + + PRO_WDG_INT_MAP + This register is used to map WDG_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TIMER_INT1_MAP + TIMER_INT1 interrupt configuration register + 0xF0 + 0x20 + 0x00000010 + + + PRO_TIMER_INT1_MAP + This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TIMER_INT2_MAP + TIMER_INT2 interrupt configuration register + 0xF4 + 0x20 + 0x00000010 + + + PRO_TIMER_INT2_MAP + This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_T0_EDGE_INT_MAP + TG_T0_EDGE_INT interrupt configuration register + 0xF8 + 0x20 + 0x00000010 + + + PRO_TG_T0_EDGE_INT_MAP + This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_T1_EDGE_INT_MAP + TG_T1_EDGE_INT interrupt configuration register + 0xFC + 0x20 + 0x00000010 + + + PRO_TG_T1_EDGE_INT_MAP + This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_WDT_EDGE_INT_MAP + TG_WDT_EDGE_INT interrupt configuration register + 0x100 + 0x20 + 0x00000010 + + + PRO_TG_WDT_EDGE_INT_MAP + This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG_LACT_EDGE_INT_MAP + TG_LACT_EDGE_INT interrupt configuration register + 0x104 + 0x20 + 0x00000010 + + + PRO_TG_LACT_EDGE_INT_MAP + This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_T0_EDGE_INT_MAP + TG1_T0_EDGE_INT interrupt configuration register + 0x108 + 0x20 + 0x00000010 + + + PRO_TG1_T0_EDGE_INT_MAP + This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_T1_EDGE_INT_MAP + TG1_T1_EDGE_INT interrupt configuration register + 0x10C + 0x20 + 0x00000010 + + + PRO_TG1_T1_EDGE_INT_MAP + This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_WDT_EDGE_INT_MAP + TG1_WDT_EDGE_INT interrupt configuration register + 0x110 + 0x20 + 0x00000010 + + + PRO_TG1_WDT_EDGE_INT_MAP + This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_TG1_LACT_EDGE_INT_MAP + TG1_LACT_EDGE_INT interrupt configuration register + 0x114 + 0x20 + 0x00000010 + + + PRO_TG1_LACT_EDGE_INT_MAP + This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CACHE_IA_INT_MAP + CACHE_IA_INT interrupt configuration register + 0x118 + 0x20 + 0x00000010 + + + PRO_CACHE_IA_INT_MAP + This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SYSTIMER_TARGET0_INT_MAP + SYSTIMER_TARGET0_INT interrupt configuration register + 0x11C + 0x20 + 0x00000010 + + + PRO_SYSTIMER_TARGET0_INT_MAP + This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SYSTIMER_TARGET1_INT_MAP + SYSTIMER_TARGET1_INT interrupt configuration register + 0x120 + 0x20 + 0x00000010 + + + PRO_SYSTIMER_TARGET1_INT_MAP + This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SYSTIMER_TARGET2_INT_MAP + SYSTIMER_TARGET2_INT interrupt configuration register + 0x124 + 0x20 + 0x00000010 + + + PRO_SYSTIMER_TARGET2_INT_MAP + This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_ASSIST_DEBUG_INTR_MAP + ASSIST_DEBUG_INTR interrupt configuration register + 0x128 + 0x20 + 0x00000010 + + + PRO_ASSIST_DEBUG_INTR_MAP + This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_PRO_IRAM0_ILG_INTR_MAP + PMS_PRO_IRAM0_ILG interrupt configuration register + 0x12C + 0x20 + 0x00000010 + + + PRO_PMS_PRO_IRAM0_ILG_INTR_MAP + This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_PRO_DRAM0_ILG_INTR_MAP + PMS_PRO_DRAM0_ILG interrupt configuration register + 0x130 + 0x20 + 0x00000010 + + + PRO_PMS_PRO_DRAM0_ILG_INTR_MAP + This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_PRO_DPORT_ILG_INTR_MAP + PMS_PRO_DPORT_ILG interrupt configuration register + 0x134 + 0x20 + 0x00000010 + + + PRO_PMS_PRO_DPORT_ILG_INTR_MAP + This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_PRO_AHB_ILG_INTR_MAP + PMS_PRO_AHB_ILG interrupt configuration register + 0x138 + 0x20 + 0x00000010 + + + PRO_PMS_PRO_AHB_ILG_INTR_MAP + This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_PRO_CACHE_ILG_INTR_MAP + PMS_PRO_CACHE_ILG interrupt configuration register + 0x13C + 0x20 + 0x00000010 + + + PRO_PMS_PRO_CACHE_ILG_INTR_MAP + This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_DMA_APB_I_ILG_INTR_MAP + PMS_DMA_APB_I_ILG interrupt configuration register + 0x140 + 0x20 + 0x00000010 + + + PRO_PMS_DMA_APB_I_ILG_INTR_MAP + This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_DMA_RX_I_ILG_INTR_MAP + PMS_DMA_RX_I_ILG interrupt configuration register + 0x144 + 0x20 + 0x00000010 + + + PRO_PMS_DMA_RX_I_ILG_INTR_MAP + This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_PMS_DMA_TX_I_ILG_INTR_MAP + PMS_DMA_TX_I_ILG interrupt configuration register + 0x148 + 0x20 + 0x00000010 + + + PRO_PMS_DMA_TX_I_ILG_INTR_MAP + This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI_MEM_REJECT_INTR_MAP + SPI_MEM_REJECT_INTR interrupt configuration register + 0x14C + 0x20 + 0x00000010 + + + PRO_SPI_MEM_REJECT_INTR_MAP + This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_DMA_COPY_INTR_MAP + DMA_COPY_INTR interrupt configuration register + 0x150 + 0x20 + 0x00000010 + + + PRO_DMA_COPY_INTR_MAP + This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI4_DMA_INT_MAP + SPI4_DMA_INT interrupt configuration register + 0x154 + 0x20 + 0x00000010 + + + PRO_SPI4_DMA_INT_MAP + This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_SPI_INTR_4_MAP + SPI_INTR_4 interrupt configuration register + 0x158 + 0x20 + 0x00000010 + + + PRO_SPI_INTR_4_MAP + This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_DCACHE_PRELOAD_INT_MAP + DCACHE_PRELOAD_INT interrupt configuration register + 0x15C + 0x20 + 0x00000010 + + + PRO_DCACHE_PRELOAD_INT_MAP + This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_ICACHE_PRELOAD_INT_MAP + ICACHE_PRELOAD_INT interrupt configuration register + 0x160 + 0x20 + 0x00000010 + + + PRO_ICACHE_PRELOAD_INT_MAP + This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_APB_ADC_INT_MAP + APB_ADC_INT interrupt configuration register + 0x164 + 0x20 + 0x00000010 + + + PRO_APB_ADC_INT_MAP + This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CRYPTO_DMA_INT_MAP + CRYPTO_DMA_INT interrupt configuration register + 0x168 + 0x20 + 0x00000010 + + + PRO_CRYPTO_DMA_INT_MAP + This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_CPU_PERI_ERROR_INT_MAP + CPU_PERI_ERROR_INT interrupt configuration register + 0x16C + 0x20 + 0x00000010 + + + PRO_CPU_PERI_ERROR_INT_MAP + This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_APB_PERI_ERROR_INT_MAP + APB_PERI_ERROR_INT interrupt configuration register + 0x170 + 0x20 + 0x00000010 + + + PRO_APB_PERI_ERROR_INT_MAP + This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_DCACHE_SYNC_INT_MAP + DCACHE_SYNC_INT interrupt configuration register + 0x174 + 0x20 + 0x00000010 + + + PRO_DCACHE_SYNC_INT_MAP + This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_ICACHE_SYNC_INT_MAP + ICACHE_SYNC_INT interrupt configuration register + 0x178 + 0x20 + 0x00000010 + + + PRO_ICACHE_SYNC_INT_MAP + This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts. + 0 + 5 + read-write + + + + + PRO_INTR_STATUS_0 + Interrupt status register 0 + 0x17C + 0x20 + + + PRO_INTR_STATUS_0 + This register stores the status of the first 32 input interrupt sources. + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_1 + Interrupt status register 1 + 0x180 + 0x20 + + + PRO_INTR_STATUS_1 + This register stores the status of the second 32 input interrupt sources. + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_2 + Interrupt status register 2 + 0x184 + 0x20 + + + PRO_INTR_STATUS_2 + This register stores the status of the last 31 input interrupt sources. + 0 + 32 + read-only + + + + + CLOCK_GATE + NMI interrupt signals mask register + 0x188 + 0x20 + 0x00000001 + + + CLK_EN + This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock. + 0 + 1 + read-write + + + PRO_NMI_MASK_HW + This bit is used to disable all NMI interrupt signals to CPU. + 1 + 1 + read-write + + + + + REG_DATE + Version control register + 0xFFC + 0x20 + 0x01904180 + + + INTERRUPT_REG_DATE + This is the version register. + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x3F409000 + + 0x0 + 0xB4 + registers + + + + PIN_CTRL + Clock output configuration register + 0x0 + 0x20 + 0x000027FF + + + PIN_CLK_OUT1 + Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled. + 0 + 4 + read-write + + + PIN_CLK_OUT2 + Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled. + 4 + 4 + read-write + + + PIN_CLK_OUT3 + Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled. + 8 + 4 + read-write + + + SWITCH_PRT_NUM + IO pin power switch delay, delay unit is one APB clock. + 12 + 3 + read-write + + + PAD_POWER_CTRL + Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V. + 15 + 1 + read-write + + + + + GPIO0 + Configuration register for pin GPIO0 + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO1 + Configuration register for pin GPIO1 + 0x8 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO2 + Configuration register for pin GPIO2 + 0xC + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO3 + Configuration register for pin GPIO3 + 0x10 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO4 + Configuration register for pin GPIO4 + 0x14 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO5 + Configuration register for pin GPIO5 + 0x18 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO6 + Configuration register for pin GPIO6 + 0x1C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO7 + Configuration register for pin GPIO7 + 0x20 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO8 + Configuration register for pin GPIO8 + 0x24 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO9 + Configuration register for pin GPIO9 + 0x28 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO10 + Configuration register for pin GPIO10 + 0x2C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO11 + Configuration register for pin GPIO11 + 0x30 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO12 + Configuration register for pin GPIO12 + 0x34 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO13 + Configuration register for pin GPIO13 + 0x38 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO14 + Configuration register for pin GPIO14 + 0x3C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO19 + Configuration register for pin GPIO19 + 0x50 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO20 + Configuration register for pin GPIO20 + 0x54 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO21 + Configuration register for pin GPIO21 + 0x58 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO33 + Configuration register for pin GPIO33 + 0x88 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO34 + Configuration register for pin GPIO34 + 0x8C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO35 + Configuration register for pin GPIO35 + 0x90 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO36 + Configuration register for pin GPIO36 + 0x94 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO37 + Configuration register for pin GPIO37 + 0x98 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO38 + Configuration register for pin GPIO38 + 0x9C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO45 + Configuration register for pin GPIO45 + 0xB8 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO46 + Configuration register for pin GPIO46 + 0xBC + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x01907160 + + + VERSION + Version control register + 0 + 28 + read-write + + + + + GPIO15 + Configuration register for pin GPIO15 + 0x40 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO16 + Configuration register for pin GPIO16 + 0x44 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO17 + Configuration register for pin GPIO17 + 0x48 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO18 + Configuration register for pin GPIO18 + 0x4C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO26 + Configuration register for pin GPIO26 + 0x6C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO27 + Configuration register for pin GPIO27 + 0x70 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO28 + Configuration register for pin GPIO28 + 0x74 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO29 + Configuration register for pin GPIO29 + 0x78 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO30 + Configuration register for pin GPIO30 + 0x7C + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO31 + Configuration register for pin GPIO31 + 0x80 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO32 + Configuration register for pin GPIO32 + 0x84 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO39 + Configuration register for pin GPIO39 + 0xA0 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO40 + Configuration register for pin GPIO40 + 0xA4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO41 + Configuration register for pin GPIO41 + 0xA8 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO42 + Configuration register for pin GPIO42 + 0xAC + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO43 + Configuration register for pin GPIO43 + 0xB0 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + GPIO44 + Configuration register for pin GPIO44 + 0xB4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pin. 1: Input enabled. 0: Input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled. + 15 + 1 + read-write + + + + + + + LEDC + LED PWM (Pulse Width Modulation) Controller + LEDC + 0x3F419000 + + 0x0 + 0xD8 + registers + + + LEDC + 45 + + + TIMER1 + 60 + + + TIMER2 + 61 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer 0. + +1: select timer 1. + +2: select timer 2. + +3: select timer 3. + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive. + 3 + 1 + read-write + + + PARA_UP + This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + OVF_CNT_RESET_ST + This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + 17 + 1 + read-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 14 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. + 0 + 19 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register is used to configure the changing step scale of duty on channel %s. + 0 + 10 + read-write + + + DUTY_CYCLE + The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the number of times the duty cycle will be changed. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease. + 30 + 1 + read-write + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_R + This register stores the current duty of output signal on channel %s. + 0 + 19 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 4 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. + 4 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 22 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 23 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK. + 24 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 25 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + CNT + This register stores the current counter value of timer %s. + 0 + 14 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + write-only + + + + + CONF + Global ledc configuration register + 0xD0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK. + 0 + 2 + read-write + + + CLK_EN + This bit is used to control clock. 1: Force clock on for register. 0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x3F417000 + + 0x0 + 0x68 + registers + + + PCNT + 51 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U0 + This sets the maximum threshold, in APB_CLK cycles, for the filter. +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U0 + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U0 + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U0 + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN_U0 + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN_U0 + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U0 + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U0 + This register sets the behavior when the signal input of channel 0 detects a negative edge. +1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. + 16 + 2 + read-write + + + CH0_POS_MODE_U0 + This register sets the behavior when the signal input of channel 0 detects a positive edge. +1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter. + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U0 + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. +0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U0 + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. +0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. + 22 + 2 + read-write + + + CH1_NEG_MODE_U0 + This register sets the behavior when the signal input of channel 1 detects a negative edge. +1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. + 24 + 2 + read-write + + + CH1_POS_MODE_U0 + This register sets the behavior when the signal input of channel 1 detects a positive edge. +1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter. + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U0 + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. +0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U0 + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. +0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification. + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U0 + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U0 + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U0 + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM_U0 + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U0 + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U0 + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U0 + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others. + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U0 + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others. + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U0 + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others. + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U0 + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others. + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U0 + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others. + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000055 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 1's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 2's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 3's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 4's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 5's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 6's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 7's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PMS + Permissions Controller + PMS + 0x3F4C1000 + + 0x0 + 0x10C + registers + + + + SDIO_0 + SDIO permission control register 0. + 0x0 + 0x20 + + + SDIO_LOCK + Lock register. Setting to 1 locks SDIO permission control registers. + 0 + 1 + read-write + + + + + SDIO_1 + SDIO permission control register 1. + 0x4 + 0x20 + + + SDIO_DISABLE + Setting to 1 disables the SDIO function. + 0 + 1 + read-write + + + + + MAC_DUMP_0 + MAC dump permission control register 0. + 0x8 + 0x20 + + + MAC_DUMP_LOCK + Lock register. Setting to 1 locks MAC dump permission control registers. + 0 + 1 + read-write + + + + + MAC_DUMP_1 + MAC dump permission control register 1. + 0xC + 0x20 + 0x000000E4 + + + MAC_DUMP_CONNECT + Configure MAC dump connection. + 0 + 12 + read-write + + + + + PRO_IRAM0_0 + IBUS permission control register 0. + 0x10 + 0x20 + + + PRO_IRAM0_LOCK + Lock register. Setting to 1 locks IBUS permission control registers. + 0 + 1 + read-write + + + + + PRO_IRAM0_1 + IBUS permission control register 1. + 0x14 + 0x20 + 0x00000FFF + + + PRO_IRAM0_SRAM_0_F + Setting to 1 grants IBUS permission to fetch SRAM Block 0. + 0 + 1 + read-write + + + PRO_IRAM0_SRAM_0_R + Setting to 1 grants IBUS permission to read SRAM Block 0. + 1 + 1 + read-write + + + PRO_IRAM0_SRAM_0_W + Setting to 1 grants IBUS permission to write SRAM Block 0. + 2 + 1 + read-write + + + PRO_IRAM0_SRAM_1_F + Setting to 1 grants IBUS permission to fetch SRAM Block 1. + 3 + 1 + read-write + + + PRO_IRAM0_SRAM_1_R + Setting to 1 grants IBUS permission to read SRAM Block 1. + 4 + 1 + read-write + + + PRO_IRAM0_SRAM_1_W + Setting to 1 grants IBUS permission to write SRAM Block 1. + 5 + 1 + read-write + + + PRO_IRAM0_SRAM_2_F + Setting to 1 grants IBUS permission to fetch SRAM Block 2. + 6 + 1 + read-write + + + PRO_IRAM0_SRAM_2_R + Setting to 1 grants IBUS permission to read SRAM Block 2. + 7 + 1 + read-write + + + PRO_IRAM0_SRAM_2_W + Setting to 1 grants IBUS permission to write SRAM Block 2. + 8 + 1 + read-write + + + PRO_IRAM0_SRAM_3_F + Setting to 1 grants IBUS permission to fetch SRAM Block 3. + 9 + 1 + read-write + + + PRO_IRAM0_SRAM_3_R + Setting to 1 grants IBUS permission to read SRAM Block 3. + 10 + 1 + read-write + + + PRO_IRAM0_SRAM_3_W + Setting to 1 grants IBUS permission to write SRAM Block 3. + 11 + 1 + read-write + + + + + PRO_IRAM0_2 + IBUS permission control register 2. + 0x18 + 0x20 + 0x007E0000 + + + PRO_IRAM0_SRAM_4_SPLTADDR + Configure the split address of SRAM Block 4-21 for IBUS access. + 0 + 17 + read-write + + + PRO_IRAM0_SRAM_4_L_F + Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 low address region. + 17 + 1 + read-write + + + PRO_IRAM0_SRAM_4_L_R + Setting to 1 grants IBUS permission to read SRAM Block 4-21 low address region. + 18 + 1 + read-write + + + PRO_IRAM0_SRAM_4_L_W + Setting to 1 grants IBUS permission to write SRAM Block 4-21 low address region. + 19 + 1 + read-write + + + PRO_IRAM0_SRAM_4_H_F + Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 high address region. + 20 + 1 + read-write + + + PRO_IRAM0_SRAM_4_H_R + Setting to 1 grants IBUS permission to read SRAM Block 4-21 high address region. + 21 + 1 + read-write + + + PRO_IRAM0_SRAM_4_H_W + Setting to 1 grants IBUS permission to write SRAM Block 4-21 high address region. + 22 + 1 + read-write + + + + + PRO_IRAM0_3 + IBUS permission control register 3. + 0x1C + 0x20 + 0x0001F800 + + + PRO_IRAM0_RTCFAST_SPLTADDR + Configure the split address of RTC FAST for IBUS access. + 0 + 11 + read-write + + + PRO_IRAM0_RTCFAST_L_F + Setting to 1 grants IBUS permission to fetch RTC FAST low address region. + 11 + 1 + read-write + + + PRO_IRAM0_RTCFAST_L_R + Setting to 1 grants IBUS permission to read RTC FAST low address region. + 12 + 1 + read-write + + + PRO_IRAM0_RTCFAST_L_W + Setting to 1 grants IBUS permission to write RTC FAST low address region. + 13 + 1 + read-write + + + PRO_IRAM0_RTCFAST_H_F + Setting to 1 grants IBUS permission to fetch RTC FAST high address region. + 14 + 1 + read-write + + + PRO_IRAM0_RTCFAST_H_R + Setting to 1 grants IBUS permission to read RTC FAST high address region. + 15 + 1 + read-write + + + PRO_IRAM0_RTCFAST_H_W + Setting to 1 grants IBUS permission to write RTC FAST high address region. + 16 + 1 + read-write + + + + + PRO_IRAM0_4 + IBUS permission control register 4. + 0x20 + 0x20 + + + PRO_IRAM0_ILG_CLR + The clear signal for IBUS access interrupt. + 0 + 1 + read-write + + + PRO_IRAM0_ILG_EN + The enable signal for IBUS access interrupt. + 1 + 1 + read-write + + + PRO_IRAM0_ILG_INTR + IBUS access interrupt signal. + 2 + 1 + read-only + + + + + PRO_IRAM0_5 + IBUS status register. + 0x24 + 0x20 + + + PRO_IRAM0_ILG_ST + Record the illegitimate information of IBUS. [21:2]: store the bits [21:2] of IBUS address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation. + 0 + 22 + read-only + + + + + PRO_DRAM0_0 + DBUS permission control register 0. + 0x28 + 0x20 + + + PRO_DRAM0_LOCK + Lock register. Setting to 1 locks DBUS0 permission control registers. + 0 + 1 + read-write + + + + + PRO_DRAM0_1 + DBUS permission control register 1. + 0x2C + 0x20 + 0x1E0000FF + + + PRO_DRAM0_SRAM_0_R + Setting to 1 grants DBUS0 permission to read SRAM Block 0. + 0 + 1 + read-write + + + PRO_DRAM0_SRAM_0_W + Setting to 1 grants DBUS0 permission to write SRAM Block 0. + 1 + 1 + read-write + + + PRO_DRAM0_SRAM_1_R + Setting to 1 grants DBUS0 permission to read SRAM Block 1. + 2 + 1 + read-write + + + PRO_DRAM0_SRAM_1_W + Setting to 1 grants DBUS0 permission to write SRAM Block 1. + 3 + 1 + read-write + + + PRO_DRAM0_SRAM_2_R + Setting to 1 grants DBUS0 permission to read SRAM Block 2. + 4 + 1 + read-write + + + PRO_DRAM0_SRAM_2_W + Setting to 1 grants DBUS0 permission to write SRAM Block 2. + 5 + 1 + read-write + + + PRO_DRAM0_SRAM_3_R + Setting to 1 grants DBUS0 permission to read SRAM Block 3. + 6 + 1 + read-write + + + PRO_DRAM0_SRAM_3_W + Setting to 1 grants DBUS0 permission to write SRAM Block 3. + 7 + 1 + read-write + + + PRO_DRAM0_SRAM_4_SPLTADDR + Configure the split address of SRAM Block 4-21 for DBUS0 access. + 8 + 17 + read-write + + + PRO_DRAM0_SRAM_4_L_R + Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region. + 25 + 1 + read-write + + + PRO_DRAM0_SRAM_4_L_W + Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region. + 26 + 1 + read-write + + + PRO_DRAM0_SRAM_4_H_R + Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region. + 27 + 1 + read-write + + + PRO_DRAM0_SRAM_4_H_W + Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region. + 28 + 1 + read-write + + + + + PRO_DRAM0_2 + DBUS permission control register 2. + 0x30 + 0x20 + 0x00007800 + + + PRO_DRAM0_RTCFAST_SPLTADDR + Configure the split address of RTC FAST for DBUS0 access. + 0 + 11 + read-write + + + PRO_DRAM0_RTCFAST_L_R + Setting to 1 grants DBUS0 permission to read RTC FAST low address region. + 11 + 1 + read-write + + + PRO_DRAM0_RTCFAST_L_W + Setting to 1 grants DBUS0 permission to write RTC FAST low address region. + 12 + 1 + read-write + + + PRO_DRAM0_RTCFAST_H_R + Setting to 1 grants DBUS0 permission to read RTC FAST high address region. + 13 + 1 + read-write + + + PRO_DRAM0_RTCFAST_H_W + Setting to 1 grants DBUS0 permission to write RTC FAST high address region. + 14 + 1 + read-write + + + + + PRO_DRAM0_3 + DBUS permission control register 3. + 0x34 + 0x20 + + + PRO_DRAM0_ILG_CLR + The clear signal for DBUS0 access interrupt. + 0 + 1 + read-write + + + PRO_DRAM0_ILG_EN + The enable signal for DBUS0 access interrupt. + 1 + 1 + read-write + + + PRO_DRAM0_ILG_INTR + DBUS0 access interrupt signal. + 2 + 1 + read-only + + + + + PRO_DRAM0_4 + DBUS status register. + 0x38 + 0x20 + + + PRO_DRAM0_ILG_ST + Record the illegitimate information of DBUS. [25:6]: store the bits [21:2] of DBUS address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: 1 means write operation, 0 means read operation. [3:0]: DBUS0 bus byte enables. + 0 + 26 + read-only + + + + + PRO_DPORT_0 + PeriBus1 permission control register 0. + 0x3C + 0x20 + + + PRO_DPORT_LOCK + Lock register. Setting to 1 locks PeriBus1 permission control registers. + 0 + 1 + read-write + + + + + PRO_DPORT_1 + PeriBus1 permission control register 1. + 0x40 + 0x20 + 0x0000F000 + + + PRO_DPORT_APB_PERIPHERAL_FORBID + Setting to 1 denies PeriBus1 bus???s access to APB peripheral. + 0 + 1 + read-write + + + PRO_DPORT_RTCSLOW_SPLTADDR + Configure the split address of RTC FAST for PeriBus1 access. + 1 + 11 + read-write + + + PRO_DPORT_RTCSLOW_L_R + Setting to 1 grants PeriBus1 permission to read RTC FAST low address region. + 12 + 1 + read-write + + + PRO_DPORT_RTCSLOW_L_W + Setting to 1 grants PeriBus1 permission to write RTC FAST low address region. + 13 + 1 + read-write + + + PRO_DPORT_RTCSLOW_H_R + Setting to 1 grants PeriBus1 permission to read RTC FAST high address region. + 14 + 1 + read-write + + + PRO_DPORT_RTCSLOW_H_W + Setting to 1 grants PeriBus1 permission to write RTC FAST high address region. + 15 + 1 + read-write + + + PRO_DPORT_RESERVE_FIFO_VALID + Configure whether to enable read protection for user-configured FIFO address. + 16 + 4 + read-write + + + + + PRO_DPORT_2 + PeriBus1 permission control register 2. + 0x44 + 0x20 + + + PRO_DPORT_RESERVE_FIFO_0 + Configure read-protection address 0. + 0 + 18 + read-write + + + + + PRO_DPORT_3 + PeriBus1 permission control register 3. + 0x48 + 0x20 + + + PRO_DPORT_RESERVE_FIFO_1 + Configure read-protection address 1. + 0 + 18 + read-write + + + + + PRO_DPORT_4 + PeriBus1 permission control register 4. + 0x4C + 0x20 + + + PRO_DPORT_RESERVE_FIFO_2 + Configure read-protection address 2. + 0 + 18 + read-write + + + + + PRO_DPORT_5 + PeriBus1 permission control register 5. + 0x50 + 0x20 + + + PRO_DPORT_RESERVE_FIFO_3 + Configure read-protection address 3. + 0 + 18 + read-write + + + + + PRO_DPORT_6 + PeriBus1 permission control register 6. + 0x54 + 0x20 + + + PRO_DPORT_ILG_CLR + The clear signal for PeriBus1 access interrupt. + 0 + 1 + read-write + + + PRO_DPORT_ILG_EN + The enable signal for PeriBus1 access interrupt. + 1 + 1 + read-write + + + PRO_DPORT_ILG_INTR + PeriBus1 access interrupt signal. + 2 + 1 + read-only + + + + + PRO_DPORT_7 + PeriBus1 status register. + 0x58 + 0x20 + + + PRO_DPORT_ILG_ST + Record the illegitimate information of PeriBus1. [25:6]: store the bits [21:2] of PeriBus1 address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: if bits [31:22] of PeriBus1 address are 0xfd, then the bit value is 1, otherwise it is 0. [3:0]: PeriBus1 byte enables. + 0 + 26 + read-only + + + + + PRO_AHB_0 + PeriBus2 permission control register 0. + 0x5C + 0x20 + + + PRO_AHB_LOCK + Lock register. Setting to 1 locks PeriBus2 permission control registers. + 0 + 1 + read-write + + + + + PRO_AHB_1 + PeriBus2 permission control register 1. + 0x60 + 0x20 + 0x0001F800 + + + PRO_AHB_RTCSLOW_0_SPLTADDR + Configure the split address of RTCSlow_0 for PeriBus2 access. + 0 + 11 + read-write + + + PRO_AHB_RTCSLOW_0_L_F + Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region. + 11 + 1 + read-write + + + PRO_AHB_RTCSLOW_0_L_R + Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region. + 12 + 1 + read-write + + + PRO_AHB_RTCSLOW_0_L_W + Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region. + 13 + 1 + read-write + + + PRO_AHB_RTCSLOW_0_H_F + Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region. + 14 + 1 + read-write + + + PRO_AHB_RTCSLOW_0_H_R + Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region. + 15 + 1 + read-write + + + PRO_AHB_RTCSLOW_0_H_W + Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region. + 16 + 1 + read-write + + + + + PRO_AHB_2 + PeriBus2 permission control register 2. + 0x64 + 0x20 + 0x0001F800 + + + PRO_AHB_RTCSLOW_1_SPLTADDR + Configure the split address of RTCSlow_1 for PeriBus2 access. + 0 + 11 + read-write + + + PRO_AHB_RTCSLOW_1_L_F + Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region. + 11 + 1 + read-write + + + PRO_AHB_RTCSLOW_1_L_R + Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region. + 12 + 1 + read-write + + + PRO_AHB_RTCSLOW_1_L_W + Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region. + 13 + 1 + read-write + + + PRO_AHB_RTCSLOW_1_H_F + Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region. + 14 + 1 + read-write + + + PRO_AHB_RTCSLOW_1_H_R + Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region. + 15 + 1 + read-write + + + PRO_AHB_RTCSLOW_1_H_W + Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region. + 16 + 1 + read-write + + + + + PRO_AHB_3 + PeriBus2 permission control register 3. + 0x68 + 0x20 + + + PRO_AHB_ILG_CLR + The clear signal for PeriBus2 access interrupt. + 0 + 1 + read-write + + + PRO_AHB_ILG_EN + The enable signal for PeriBus2 access interrupt. + 1 + 1 + read-write + + + PRO_AHB_ILG_INTR + PeriBus2 access interrupt signal. + 2 + 1 + read-only + + + + + PRO_AHB_4 + PeriBus2 status register. + 0x6C + 0x20 + + + PRO_AHB_ILG_ST + Record the illegitimate information of PeriBus2. [31:2]: store the bits [31:2] of PeriBus2 address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation. + 0 + 32 + read-only + + + + + PRO_TRACE_0 + Trace memory permission control register 0. + 0x70 + 0x20 + + + PRO_TRACE_LOCK + Lock register. Setting to 1 locks trace function permission control registers. + 0 + 1 + read-write + + + + + PRO_TRACE_1 + Trace memory permission control register 1. + 0x74 + 0x20 + + + PRO_TRACE_DISABLE + Setting to 1 disables the trace memory function. + 0 + 1 + read-write + + + + + PRO_CACHE_0 + Cache permission control register 0. + 0x78 + 0x20 + + + PRO_CACHE_LOCK + Lock register. Setting to 1 locks cache permission control registers. + 0 + 1 + read-write + + + + + PRO_CACHE_1 + Cache permission control register 1. + 0x7C + 0x20 + + + PRO_CACHE_CONNECT + Configure which SRAM Block will be occupied by Icache or Dcache. + 0 + 16 + read-write + + + + + PRO_CACHE_2 + Cache permission control register 2. + 0x80 + 0x20 + + + PRO_CACHE_ILG_CLR + The clear signal for cache access interrupt. + 0 + 1 + read-write + + + PRO_CACHE_ILG_EN + The enable signal for cache access interrupt. + 1 + 1 + read-write + + + PRO_CACHE_ILG_INTR + Cache access interrupt signal. + 2 + 1 + read-only + + + + + PRO_CACHE_3 + Icache status register. + 0x84 + 0x20 + + + PRO_CACHE_ILG_ST_I + Record the illegitimate information of ICache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Icache bus write byte enables, active low. + 0 + 17 + read-only + + + + + PRO_CACHE_4 + Dcache status register. + 0x88 + 0x20 + + + PRO_CACHE_ILG_ST_D + Record the illegitimate information of Dcache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Dcache bus write byte enables, active low. + 0 + 17 + read-only + + + + + DMA_APB_I_0 + Internal DMA permission control register 0. + 0x8C + 0x20 + + + DMA_APB_I_LOCK + Lock register. Setting to 1 locks internal DMA permission control registers. + 0 + 1 + read-write + + + + + DMA_APB_I_1 + Internal DMA permission control register 1. + 0x90 + 0x20 + 0x1E0000FF + + + DMA_APB_I_SRAM_0_R + Setting to 1 grants internal DMA permission to read SRAM Block 0. + 0 + 1 + read-write + + + DMA_APB_I_SRAM_0_W + Setting to 1 grants internal DMA permission to write SRAM Block 0. + 1 + 1 + read-write + + + DMA_APB_I_SRAM_1_R + Setting to 1 grants internal DMA permission to read SRAM Block 1. + 2 + 1 + read-write + + + DMA_APB_I_SRAM_1_W + Setting to 1 grants internal DMA permission to write SRAM Block 1. + 3 + 1 + read-write + + + DMA_APB_I_SRAM_2_R + Setting to 1 grants internal DMA permission to read SRAM Block 2. + 4 + 1 + read-write + + + DMA_APB_I_SRAM_2_W + Setting to 1 grants internal DMA permission to write SRAM Block 2. + 5 + 1 + read-write + + + DMA_APB_I_SRAM_3_R + Setting to 1 grants internal DMA permission to read SRAM Block 3. + 6 + 1 + read-write + + + DMA_APB_I_SRAM_3_W + Setting to 1 grants internal DMA permission to write SRAM Block 3. + 7 + 1 + read-write + + + DMA_APB_I_SRAM_4_SPLTADDR + Configure the split address of SRAM Block 4-21 for internal DMA access. + 8 + 17 + read-write + + + DMA_APB_I_SRAM_4_L_R + Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region. + 25 + 1 + read-write + + + DMA_APB_I_SRAM_4_L_W + Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region. + 26 + 1 + read-write + + + DMA_APB_I_SRAM_4_H_R + Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region. + 27 + 1 + read-write + + + DMA_APB_I_SRAM_4_H_W + Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region. + 28 + 1 + read-write + + + + + DMA_APB_I_2 + Internal DMA permission control register 2. + 0x94 + 0x20 + + + DMA_APB_I_ILG_CLR + The clear signal for internal DMA access interrupt. + 0 + 1 + read-write + + + DMA_APB_I_ILG_EN + The enable signal for internal DMA access interrupt. + 1 + 1 + read-write + + + DMA_APB_I_ILG_INTR + Internal DMA access interrupt signal. + 2 + 1 + read-only + + + + + DMA_APB_I_3 + Internal DMA status register. + 0x98 + 0x20 + + + DMA_APB_I_ILG_ST + Record the illegitimate information of Internal DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: Internal DMA bus byte enables. + 0 + 23 + read-only + + + + + DMA_RX_I_0 + RX Copy DMA permission control register 0. + 0x9C + 0x20 + + + DMA_RX_I_LOCK + Lock register. Setting to 1 locks RX Copy DMA permission control registers. + 0 + 1 + read-write + + + + + DMA_RX_I_1 + RX Copy DMA permission control register 1. + 0xA0 + 0x20 + 0x1E0000FF + + + DMA_RX_I_SRAM_0_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 0. + 0 + 1 + read-write + + + DMA_RX_I_SRAM_0_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 0. + 1 + 1 + read-write + + + DMA_RX_I_SRAM_1_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 1. + 2 + 1 + read-write + + + DMA_RX_I_SRAM_1_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 1. + 3 + 1 + read-write + + + DMA_RX_I_SRAM_2_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 2. + 4 + 1 + read-write + + + DMA_RX_I_SRAM_2_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 2. + 5 + 1 + read-write + + + DMA_RX_I_SRAM_3_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 3. + 6 + 1 + read-write + + + DMA_RX_I_SRAM_3_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 3. + 7 + 1 + read-write + + + DMA_RX_I_SRAM_4_SPLTADDR + Configure the split address of SRAM Block 4-21 for RX Copy DMA access. + 8 + 17 + read-write + + + DMA_RX_I_SRAM_4_L_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 low address region. + 25 + 1 + read-write + + + DMA_RX_I_SRAM_4_L_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 4-21 low address region. + 26 + 1 + read-write + + + DMA_RX_I_SRAM_4_H_R + Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 high address region. + 27 + 1 + read-write + + + DMA_RX_I_SRAM_4_H_W + Setting to 1 grants RX Copy DMA permission to write SRAM Block 4~21 high address region. + 28 + 1 + read-write + + + + + DMA_RX_I_2 + RX Copy DMA permission control register 2. + 0xA4 + 0x20 + + + DMA_RX_I_ILG_CLR + The clear signal for RX Copy DMA access interrupt. + 0 + 1 + read-write + + + DMA_RX_I_ILG_EN + The enable signal for RX Copy DMA access interrupt. + 1 + 1 + read-write + + + DMA_RX_I_ILG_INTR + RX Copy DMA access interrupt signal. + 2 + 1 + read-only + + + + + DMA_RX_I_3 + RX Copy DMA status register. + 0xA8 + 0x20 + + + DMA_RX_I_ILG_ST + Record the illegitimate information of RX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: RX Copy DMA bus byte enables. + 0 + 23 + read-only + + + + + DMA_TX_I_0 + TX Copy DMA permission control register 0. + 0xAC + 0x20 + + + DMA_TX_I_LOCK + Lock register. Setting to 1 locks TX Copy DMA permission control registers. + 0 + 1 + read-write + + + + + DMA_TX_I_1 + TX Copy DMA permission control register 1. + 0xB0 + 0x20 + 0x1E0000FF + + + DMA_TX_I_SRAM_0_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 0. + 0 + 1 + read-write + + + DMA_TX_I_SRAM_0_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 0. + 1 + 1 + read-write + + + DMA_TX_I_SRAM_1_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 1. + 2 + 1 + read-write + + + DMA_TX_I_SRAM_1_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 1. + 3 + 1 + read-write + + + DMA_TX_I_SRAM_2_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 2. + 4 + 1 + read-write + + + DMA_TX_I_SRAM_2_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 2. + 5 + 1 + read-write + + + DMA_TX_I_SRAM_3_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 3. + 6 + 1 + read-write + + + DMA_TX_I_SRAM_3_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 3. + 7 + 1 + read-write + + + DMA_TX_I_SRAM_4_SPLTADDR + Configure the split address of SRAM Block 4-21 for TX Copy DMA access. + 8 + 17 + read-write + + + DMA_TX_I_SRAM_4_L_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region. + 25 + 1 + read-write + + + DMA_TX_I_SRAM_4_L_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region. + 26 + 1 + read-write + + + DMA_TX_I_SRAM_4_H_R + Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region. + 27 + 1 + read-write + + + DMA_TX_I_SRAM_4_H_W + Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region. + 28 + 1 + read-write + + + + + DMA_TX_I_2 + TX Copy DMA permission control register 2. + 0xB4 + 0x20 + + + DMA_TX_I_ILG_CLR + The clear signal for TX Copy DMA access interrupt. + 0 + 1 + read-write + + + DMA_TX_I_ILG_EN + The enable signal for TX Copy DMA access interrupt. + 1 + 1 + read-write + + + DMA_TX_I_ILG_INTR + TX Copy DMA access interrupt signal. + 2 + 1 + read-only + + + + + DMA_TX_I_3 + TX Copy DMA status register. + 0xB8 + 0x20 + + + DMA_TX_I_ILG_ST + Record the illegitimate information of TX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: TX Copy DMA bus byte enables. + 0 + 23 + read-only + + + + + PRO_BOOT_LOCATION_0 + Boot permission control register 0. + 0xBC + 0x20 + + + PRO_BOOT_LOCATION_LOCK + Lock register. Setting to 1 locks boot remap permission control registers. + 0 + 1 + read-write + + + + + PRO_BOOT_LOCATION_1 + Boot permission control register 1. + 0xC0 + 0x20 + + + PRO_BOOT_REMAP + If set to 1, enable boot remap function. + 0 + 1 + read-write + + + + + CACHE_SOURCE_0 + Cache access permission control register 0. + 0xC4 + 0x20 + + + CACHE_SOURCE_LOCK + Lock register. Setting to 1 locks cache access permission control registers. + 0 + 1 + read-write + + + + + CACHE_SOURCE_1 + Cache access permission control register 1. + 0xC8 + 0x20 + + + PRO_CACHE_I_SOURCE_PRO_IRAM1 + xx + 0 + 1 + read-write + + + PRO_CACHE_I_SOURCE_PRO_IROM0 + xx + 1 + 1 + read-write + + + PRO_CACHE_I_SOURCE_PRO_DROM0 + xx + 2 + 1 + read-write + + + PRO_CACHE_D_SOURCE_PRO_DRAM0 + xx + 3 + 1 + read-write + + + PRO_CACHE_D_SOURCE_PRO_DPORT + xx + 4 + 1 + read-write + + + PRO_CACHE_D_SOURCE_PRO_DROM0 + xx + 5 + 1 + read-write + + + + + APB_PERIPHERAL_0 + Peripheral access permission control register 0. + 0xCC + 0x20 + + + APB_PERIPHERAL_LOCK + Lock register. Setting to 1 locks TX Copy DMA permission control registers. + 0 + 1 + read-write + + + + + APB_PERIPHERAL_1 + Peripheral access permission control register 1. + 0xD0 + 0x20 + 0x00000001 + + + APB_PERIPHERAL_SPLIT_BURST + Setting to 1 splits the data phase of the last access and the address phase of following access. + 0 + 1 + read-write + + + + + OCCUPY_0 + Occupy permission control register 0. + 0xD4 + 0x20 + + + OCCUPY_LOCK + Lock register. Setting to 1 locks occupy permission control registers. + 0 + 1 + read-write + + + + + OCCUPY_1 + Occupy permission control register 1. + 0xD8 + 0x20 + + + OCCUPY_CACHE + Configure whether SRAM Block 0-3 is used as cache memory. + 0 + 4 + read-write + + + + + OCCUPY_2 + Occupy permission control register 2. + 0xDC + 0x20 + + + OCCUPY_MAC_DUMP + Configure whether SRAM Block 18-21 is used as mac dump. + 0 + 4 + read-write + + + + + OCCUPY_3 + Occupy permission control register 3. + 0xE0 + 0x20 + + + OCCUPY_PRO_TRACE + Configure one block of SRAM Block 4-21 is used as trace memory. + 0 + 18 + read-write + + + + + CACHE_TAG_ACCESS_0 + Cache tag permission control register 0. + 0xE4 + 0x20 + + + CACHE_TAG_ACCESS_LOCK + Lock register. Setting to 1 locks cache tag permission control registers. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + Cache tag permission control register 1. + 0xE8 + 0x20 + + + PRO_I_TAG_RD_ACS + Setting to 1 permits read access to Icache tag memory. + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + Setting to 1 permits write access to Icache tag memory. + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + Setting to 1 permits read access to Dcache tag memory. + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + Setting to 1 permits write access to Dcache tag memory. + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + Cache MMU permission control register 0. + 0xEC + 0x20 + + + CACHE_MMU_ACCESS_LOCK + Lock register. Setting to 1 locks cache MMU permission control registers. + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + Cache MMU permission control register 1. + 0xF0 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + Setting to 1 permits read access to MMU memory. + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Setting to 1 permits write access to MMU memory. + 1 + 1 + read-write + + + + + APB_PERIPHERAL_INTR + PeribBus2 permission control register. + 0xF4 + 0x20 + + + APB_PERI_BYTE_ERROR_CLR + The clear signal for APB peripheral interrupt. + 0 + 1 + read-write + + + APB_PERI_BYTE_ERROR_EN + The enable signal for APB peripheral access interrupt. + 1 + 1 + read-write + + + APB_PERI_BYTE_ERROR_INTR + APB peripheral access interrupt signal. + 2 + 1 + read-only + + + + + APB_PERIPHERAL_STATUS + PeribBus2 peripheral access status register. + 0xF8 + 0x20 + + + APB_PERI_BYTE_ERROR_ADDR + Record the illegitimate address of APB peripheral. + 0 + 32 + read-only + + + + + CPU_PERIPHERAL_INTR + PeribBus1 permission control register. + 0xFC + 0x20 + + + CPU_PERI_BYTE_ERROR_CLR + The clear signal for CPU peripheral access interrupt. + 0 + 1 + read-write + + + CPU_PERI_BYTE_ERROR_EN + The enable signal for CPU peripheral access interrupt. + 1 + 1 + read-write + + + CPU_PERI_BYTE_ERROR_INTR + CPU peripheral access interrupt signal. + 2 + 1 + read-only + + + + + CPU_PERIPHERAL_STATUS + PeribBus1 peripheral access status register. + 0x100 + 0x20 + + + CPU_PERI_BYTE_ERROR_ADDR + Record the illegitimate address of CPU peripheral. + 0 + 32 + read-only + + + + + CLOCK_GATE_REG + Clock gate register of permission control. + 0x104 + 0x20 + 0x00000001 + + + CLK_EN + Enable the clock of permission control module when set to 1. + 0 + 1 + read-write + + + + + DATE + Version control register. + 0xFFC + 0x20 + 0x01905090 + + + DATE + Version control register. + 0 + 28 + read-write + + + + + + + RMT + Remote Control Peripheral + RMT + 0x3F416000 + + 0x0 + 0xA0 + registers + + + RMT + 50 + + + + 4 + 0x4 + CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CH_DATA + The read and write data register for CHANNEL%s by apb fifo access. + 0 + 32 + read-write + + + + + 4 + 0x8 + CH%sCONF0 + Channel %s configure register 0 + 0x10 + 0x20 + 0x39100002 + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 16 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 3 + read-write + + + CARRIER_EFF_EN + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 27 + 1 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + CH%sCONF1 + Channel %s configure register 1 + 0x14 + 0x20 + 0x00000F20 + + + TX_START + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + read-write + + + RX_EN + Set this bit to enable receiver to receive data on CHANNEL%s. + 1 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 2 + 1 + write-only + + + MEM_RD_RST + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 3 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 4 + 1 + write-only + + + MEM_OWNER + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: Transmitter is using the ram. + 5 + 1 + read-write + + + TX_CONTI_MODE + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 6 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter's enable bit for CHANNEL%s. + 7 + 1 + read-write + + + RX_FILTER_THRES + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 8 + 8 + read-write + + + CHK_RX_CARRIER_EN + Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s. + 16 + 1 + read-write + + + REF_ALWAYS_ON + This bit is used to select the base clock for CHANNEL%s. + +1'h1: clk_apb 1'h0:clk_ref + 17 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 18 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable-control bit for CHANNEL%s in IDLE state. + 19 + 1 + read-write + + + TX_STOP + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 20 + 1 + read-write + + + + + 4 + 0x4 + CH%sSTATUS + Channel %s status register + 0x30 + 0x20 + + + MEM_WADDR_EX + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 9 + read-only + + + MEM_RADDR_EX + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 10 + 9 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 20 + 3 + read-only + + + MEM_OWNER_ERR + This status bit will be set when the ownership of memory block is wrong. + 23 + 1 + read-only + + + MEM_FULL + This status bit will be set if the receiver receives more data than the memory size. + 24 + 1 + read-only + + + MEM_EMPTY + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + 4 + 0x4 + CH%sADDR + Channel %s address register + 0x40 + 0x20 + + + APB_MEM_WADDR + This register records the memory address offset when writes RAM over APB bus. + 0 + 9 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reads RAM over APB bus. + 10 + 9 + read-only + + + + + INT_RAW + Raw interrupt status + 0x50 + 0x20 + + + 4 + 0x3 + 0-3 + CH%s_TX_END_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + 0 + 1 + read-only + + + 4 + 0x3 + 0-3 + CH%s_RX_END_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when reception done. + 1 + 1 + read-only + + + 4 + 0x3 + 0-3 + CH%s_ERR_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + 2 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + 12 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + 16 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x54 + 0x20 + + + 4 + 0x3 + 0-3 + CH%s_TX_END_INT_ST + The masked interrupt status bit for CH%s_TX_END_INT. + 0 + 1 + read-only + + + 4 + 0x3 + 0-3 + CH%s_RX_END_INT_ST + The masked interrupt status bit for CH%s_RX_END_INT. + 1 + 1 + read-only + + + 4 + 0x3 + 0-3 + CH%s_ERR_INT_ST + The masked interrupt status bit for CH%s_ERR_INT. + 2 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + 12 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ST + The masked interrupt status bit for CH%s_TX_LOOP_INT. + 16 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x58 + 0x20 + + + 4 + 0x3 + 0-3 + CH%s_TX_END_INT_ENA + The interrupt enabled bit for CH%s_TX_END_INT. + 0 + 1 + read-write + + + 4 + 0x3 + 0-3 + CH%s_RX_END_INT_ENA + The interrupt enabled bit for CH%s_RX_END_INT. + 1 + 1 + read-write + + + 4 + 0x3 + 0-3 + CH%s_ERR_INT_ENA + The interrupt enabled bit for CH%s_ERR_INT. + 2 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ENA + The interrupt enabled bit for CH%s_TX_THR_EVENT_INT. + 12 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ENA + The interrupt enabled bit for CH%s_TX_LOOP_INT. + 16 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x5C + 0x20 + + + 4 + 0x3 + 0-3 + CH%s_TX_END_INT_CLR + Set this bit to clear the CH%s_TX_END_INT interrupt. + 0 + 1 + write-only + + + 4 + 0x3 + 0-3 + CH%s_RX_END_INT_CLR + Set this bit to clear the CH%s_RX_END_INT interrupt. + 1 + 1 + write-only + + + 4 + 0x3 + 0-3 + CH%s_ERR_INT_CLR + Set this bit to clear the CH%s_ERR_INT interrupt. + 2 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_CLR + Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt. + 12 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_CLR + Set this bit to clear the CH%s_TX_LOOP_INT interrupt. + 16 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x60 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0x70 + 0x20 + 0x00000080 + + + TX_LIM + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + + + APB_CONF + RMT apb configuration register + 0x80 + 0x20 + 0x00000004 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_TX_WRAP_EN + This is the enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 1 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 3 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 4 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0x84 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0x88 + 0x20 + + + CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + read-write + + + CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + read-write + + + CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + read-write + + + CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x8C + 0x20 + + + CARRIER_LOW_THRES + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + DATE + RMT version register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60035000 + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x110 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x34 + registers + + + RSA + 54 + + + + M_PRIME + Register to store M' + 0x800 + 0x20 + + + M_PRIME + Stores M'. + 0 + 32 + read-write + + + + + MODE + RSA length mode + 0x804 + 0x20 + + + MODE + Stores the mode of modular exponentiation. + 0 + 7 + read-write + + + + + CLEAN + RSA clean register + 0x808 + 0x20 + + + CLEAN + The content of this bit is 1 when memories complete initialization. + 0 + 1 + read-only + + + + + MODEXP_START + Modular exponentiation starting bit + 0x80C + 0x20 + + + MODEXP_START + Set this bit to 1 to start the modular exponentiation. + 0 + 1 + write-only + + + + + MODMULT_START + Modular multiplication starting bit + 0x810 + 0x20 + + + MODMULT_START + Set this bit to 1 to start the modular multiplication. + 0 + 1 + write-only + + + + + MULT_START + Normal multiplication starting bit + 0x814 + 0x20 + + + MULT_START + Set this bit to 1 to start the multiplication. + 0 + 1 + write-only + + + + + IDLE + RSA idle register + 0x818 + 0x20 + + + IDLE + The content of this bit is 1 when the RSA accelerator is idle. + 0 + 1 + read-only + + + + + CLEAR_INTERRUPT + RSA clear interrupt register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Set this bit to 1 to clear the RSA interrupts. + 0 + 1 + write-only + + + + + CONSTANT_TIME + The constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + The search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default). + 0 + 1 + read-write + + + + + SEARCH_POS + The search position + 0x828 + 0x20 + + + SEARCH_POS + Is used to configure the starting address when the acceleration option of search is used. + 0 + 12 + read-write + + + + + INTERRUPT_ENA + RSA interrupt enable register + 0x82C + 0x20 + 0x00000001 + + + INTERRUPT_ENA + Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20190425 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + RTCIO + Peripheral RTCIO + RTCIO + 0x3F408400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO output register + 0x0 + 0x20 + + + GPIO_OUT_DATA + GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + RTC GPIO output bit set register + 0x4 + 0x20 + + + GPIO_OUT_DATA_W1TS + GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + RTC GPIO output bit clear register + 0x8 + 0x20 + + + GPIO_OUT_DATA_W1TC + GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + RTC GPIO output enable register + 0xC + 0x20 + + + REG_RTCIO_REG_GPIO_ENABLE + GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO output enable bit set register + 0x10 + 0x20 + + + REG_RTCIO_REG_GPIO_ENABLE_W1TS + GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG. + 10 + 22 + write-only + + + + + ENABLE_W1TC + RTC GPIO output enable bit clear register + 0x14 + 0x20 + + + ENABLE_W1TC + GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG. + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO interrupt status register + 0x18 + 0x20 + + + GPIO_STATUS_INT + GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt. + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + RTC GPIO interrupt status bit set register + 0x1C + 0x20 + + + GPIO_STATUS_INT_W1TS + GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + RTC GPIO interrupt status bit clear register + 0x20 + 0x20 + + + GPIO_STATUS_INT_W1TC + GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input register + 0x24 + 0x20 + + + GPIO_IN_NEXT + GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level. + 10 + 22 + read-only + + + + + 22 + 0x4 + PIN%s + RTC configuration for pin %s + 0x28 + 0x20 + + + PAD_DRIVER + Pad driver selection. 0: normal output. 1: open drain. + 2 + 1 + read-write + + + GPIO_PIN0_INT_TYPE + GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger. + 7 + 3 + read-write + + + GPIO_PIN0_WAKEUP_ENABLE + GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + RTC debug select register + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + 25 + 1 + read-write + + + + + 15 + 0x4 + TOUCH_PAD%s + Touch pad %s configuration register + 0x84 + 0x20 + 0x52000000 + + + TOUCH_PAD0_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + TOUCH_PAD0_SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + TOUCH_PAD0_SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + TOUCH_PAD0_SLP_SEL + 0: no sleep mode. 1: enable sleep mode. + 16 + 1 + read-write + + + TOUCH_PAD0_FUN_SEL + Function selection. + 17 + 2 + read-write + + + TOUCH_PAD0_MUX_SEL + Connect the RTC pad input to digital pad input. 0 is available. + 19 + 1 + read-write + + + TOUCH_PAD0_XPD + Touch sensor power on. + 20 + 1 + read-write + + + TOUCH_PAD0_TIE_OPT + The tie option of touch sensor. 0: tie low. 1: tie high. + 21 + 1 + read-write + + + TOUCH_PAD0_START + Start touch sensor. + 22 + 1 + read-write + + + TOUCH_PAD0_DAC + Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + 23 + 3 + read-write + + + TOUCH_PAD0_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + TOUCH_PAD0_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + TOUCH_PAD0_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + XTAL_32P_PAD + 32KHz crystal P-pad configuration register + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode. + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode. + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + X32P_FUN_SEL + Function selection. + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + X32P_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + X32P_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + X32P_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + XTAL_32N_PAD + 32KHz crystal N-pad configuration register + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + X32N_SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + X32N_SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + X32N_FUN_SEL + Function selection. + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + X32N_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + X32N_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + X32N_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + PAD_DAC1 + DAC1 configuration register + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + 3 + 8 + read-write + + + PDAC1_XPD_DAC + When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output. + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output. + 12 + 1 + read-write + + + PDAC1_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + PDAC1_SLP_OE + Output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + Input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode. 0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + DAC_1 function selection. + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + PDAC1_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + PDAC1_DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + PAD_DAC2 + DAC2 configuration register + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + 3 + 8 + read-write + + + PDAC2_XPD_DAC + When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output. + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output. + 12 + 1 + read-write + + + PDAC2_FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + PDAC2_SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + PDAC2_SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + PDAC2_FUN_SEL + DAC_2 function selection. + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + PDAC2_RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + PDAC2_RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + PDAC2_DRV + Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD19 + Touch pad 19 configuration register + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD20 + Touch pad 20 configuration register + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + RTC_PAD21 + Touch pad 21 configuration register + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + Input enable in normal execution. + 13 + 1 + read-write + + + SLP_OE + Output enable in sleep mode. + 14 + 1 + read-write + + + SLP_IE + Input enable in sleep mode. + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode. 0: no sleep mode. + 16 + 1 + read-write + + + FUN_SEL + Function selection. + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO. 0: use digital GPIO. + 19 + 1 + read-write + + + RUE + Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. + 27 + 1 + read-write + + + RDE + Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. + 28 + 1 + read-write + + + DRV + Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA. + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + External wake up configuration register + 0xDC + 0x20 + + + SEL + GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. +0: select GPIO0; 1: select GPIO2, etc + 27 + 5 + read-write + + + + + XTL_EXT_CTR + Crystal power down enable GPIO source + 0xE0 + 0x20 + + + SEL + Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. + 27 + 5 + read-write + + + + + SAR_I2C_IO + RTC I2C pad selection + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2. + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3. + 30 + 2 + read-write + + + + + RTC_IO_TOUCH_CTRL + Touch control register + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + 4 + 1 + read-write + + + + + RTC_IO_DATE + Version control register + 0x1FC + 0x20 + 0x01903170 + + + IO_DATE + Version control register + 0 + 28 + read-write + + + + + + + RTC_CNTL + Real Time Controller + RTC_CNTL + 0x3F408000 + + 0x0 + 0x138 + registers + + + RTC_CORE + 49 + + + + OPTIONS0 + Sets the power options of crystal and PLL clocks, and initiates reset by software + 0x0 + 0x20 + 0x1C002000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW. + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2) + 4 + 1 + write-only + + + SW_PROCPU_RST + Set this bit to reset the CPU by SW. + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + Set this bit to FPD BB_I2C. + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + Set this bit to FPU BB_I2C. + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + Set this bit to FPD BB_PLL _I2C. + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + Set this bit to FPU BB_PLL _I2C. + 9 + 1 + read-write + + + BBPLL_FORCE_PD + Set this bit to FPD BB_PLL. + 10 + 1 + read-write + + + BBPLL_FORCE_PU + Set this bit to FPU BB_PLL. + 11 + 1 + read-write + + + XTL_FORCE_PD + Set this bit to FPD the crystal oscillator. + 12 + 1 + read-write + + + XTL_FORCE_PU + Set this bit to FPU the crystal oscillator. + 13 + 1 + read-write + + + XTL_FORCE_ISO + 23 + 1 + read-write + + + PLL_FORCE_ISO + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + 25 + 1 + read-write + + + XTL_FORCE_NOISO + 26 + 1 + read-write + + + PLL_FORCE_NOISO + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + Set this bit to force reset the digital system in deep-sleep. + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + Set this bit to disable force reset to digital system in deep-sleep. + 30 + 1 + read-write + + + SW_SYS_RST + Set this bit to reset the system via SW. + 31 + 1 + write-only + + + + + SLP_TIMER0 + RTC timer threshold register 0 + 0x4 + 0x20 + + + SLP_VAL_LO + Sets the lower 32 bits of the trigger threshold for the RTC timer. + 0 + 32 + read-write + + + + + SLP_TIMER1 + RTC timer threshold register 1 + 0x8 + 0x20 + + + SLP_VAL_HI + Sets the higher 16 bits of the trigger threshold for the RTC timer. + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + Sets this bit to enable the timer alarm. + 16 + 1 + write-only + + + + + TIME_UPDATE + RTC timer update control register + 0xC + 0x20 + + + TIMER_SYS_STALL + Selects the triggering condition for the RTC timer. See details in Table 1-2. + 27 + 1 + read-write + + + TIMER_XTL_OFF + Selects the triggering condition for the RTC timer. See details in Table 1-2. + 28 + 1 + read-write + + + TIMER_SYS_RST + Selects the triggering condition for the RTC timer. See details in Table 1-2. + 29 + 1 + read-write + + + TIME_UPDATE + Selects the triggering condition for the RTC timer. See details in Table 1-2. + 31 + 1 + write-only + + + + + TIME_LOW0 + Stores the lower 32 bits of RTC timer 0. + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + Stores the lower 32 bits of RTC timer 0. + 0 + 32 + read-only + + + + + TIME_HIGH0 + Stores the higher 16 bits of RTC timer 0 + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + Stores the higher 16 bits of RTC timer 0. + 0 + 16 + read-only + + + + + STATE0 + Configures the sleep / reject / wakeup state + 0x18 + 0x20 + + + SW_CPU_INT + Sends a SW RTC interrupt to CPU. + 0 + 1 + write-only + + + SLP_REJECT_CAUSE_CLR + Clears the RTC reject-to-sleep cause. + 1 + 1 + write-only + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge 0: APB to RTC using sync + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + Indicates the SDIO is active. + 28 + 1 + read-only + + + SLP_WAKEUP + Sleep wakeup bit. + 29 + 1 + read-write + + + SLP_REJECT + Sleep reject bit. + 30 + 1 + read-write + + + SLEEP_EN + Sends the chip to sleep. + 31 + 1 + read-write + + + + + TIMER1 + Configures CPU stall options + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + Enables CPU stalling. + 0 + 1 + read-write + + + CPU_STALL_WAIT + Sets the CPU stall waiting cycle (using the RTC fast clock). + 1 + 5 + read-write + + + CK8M_WAIT + Sets the 8 MHz clock waiting (using the RTC slow clock). + 6 + 8 + read-write + + + XTL_BUF_WAIT + Sets the XTAL waiting cycle (using the RTC slow clock). + 14 + 10 + read-write + + + PLL_BUF_WAIT + Sets the PLL waiting cycle (using the RTC slow clock). + 24 + 8 + read-write + + + + + TIMER2 + Configures RTC slow clock and touch controller + 0x20 + 0x20 + 0x01080000 + + + ULPCP_TOUCH_START_WAIT + Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work. + 15 + 9 + read-write + + + MIN_TIME_CK8M_OFF + Sets the minimal cycle for 8 MHz clock (using the RTC slow clock) when powered down. + 24 + 8 + read-write + + + + + TIMER3 + configure some wait time for power on + 0x24 + 0x20 + 0x14160A08 + + + WIFI_WAIT_TIMER + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + 9 + 7 + read-write + + + ROM_RAM_WAIT_TIMER + 16 + 9 + read-write + + + ROM_RAM_POWERUP_TIMER + 25 + 7 + read-write + + + + + TIMER4 + configure some wait time for power on + 0x28 + 0x20 + 0x10200A08 + + + WAIT_TIMER + 0 + 9 + read-write + + + POWERUP_TIMER + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + 25 + 7 + read-write + + + + + TIMER5 + Configures the minimal sleep cycles + 0x2C + 0x20 + 0x12148000 + + + MIN_SLP_VAL + Sets the minimal sleep cycles (using the RTC slow clock). + 8 + 8 + read-write + + + RTCMEM_WAIT_TIMER + 16 + 9 + read-write + + + RTCMEM_POWERUP_TIMER + 25 + 7 + read-write + + + + + TIMER6 + Configure minimal sleep cycles register + 0x30 + 0x20 + 0x10200000 + + + DG_DCDC_WAIT_TIMER + 16 + 9 + read-write + + + DG_DCDC_POWERUP_TIMER + 25 + 7 + read-write + + + + + ANA_CONF + Configures the power options for I2C and PLLA + 0x34 + 0x20 + 0x00A40000 + + + I2C_RESET_POR_FORCE_PD + SLEEP_I2CPOR force pd + 18 + 1 + read-write + + + I2C_RESET_POR_FORCE_PU + SLEEP_I2CPOR force pu + 19 + 1 + read-write + + + GLITCH_RST_EN + Set this bit to enable a reset when the system detects a glitch. + 20 + 1 + read-write + + + SAR_I2C_FORCE_PD + Sets this bit to FPD the SAR_I2C. + 21 + 1 + read-write + + + SAR_I2C_FORCE_PU + Sets this bit to FPU the SAR_I2C. + 22 + 1 + read-write + + + PLLA_FORCE_PD + Sets this bit to FPD the PLLA. + 23 + 1 + read-write + + + PLLA_FORCE_PU + Sets this bit to FPU the PLLA. + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up , otherwise power down + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up , otherwise power down + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up , otherwise power down + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up , otherwise power down + 30 + 1 + read-write + + + PLL_I2C_PU + 1. PLL_I2C power up ,otherwise power down + 31 + 1 + read-write + + + + + RESET_STATE + Indicates the CPU reset source. For more information about the reset cause, please refer to Table \ref{table:resetreasons} in Chapter \ref{module:ResetandClock} \textit{\nameref{module:ResetandClock}}. + 0x38 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + Stores the CPU reset cause. + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + APPCPU_STAT_VECTOR_SEL + APP CPU state vector sel + 12 + 1 + read-write + + + PROCPU_STAT_VECTOR_SEL + Selects the CPU state vector. + 13 + 1 + read-write + + + + + WAKEUP_STATE + Wakeup bitmap enabling register + 0x3C + 0x20 + 0x00060000 + + + WAKEUP_ENA + Enables the wakeup bitmap. + 15 + 17 + read-write + + + + + INT_ENA_RTC + RTC interrupt enabling register + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ENA + Enables interruption when the chip wakes up from sleep. + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + Enables interruption when the chip rejects to go to sleep. + 1 + 1 + read-write + + + SDIO_IDLE_INT_ENA + Enables interruption when the SDIO idles. + 2 + 1 + read-write + + + WDT_INT_ENA + Enables the RTC watchdog interrupt. + 3 + 1 + read-write + + + TOUCH_SCAN_DONE_INT_ENA + Enables interruption upon the completion of a touch scanning. + 4 + 1 + read-write + + + ULP_CP_INT_ENA + Enables the ULP co-processor interrupt. + 5 + 1 + read-write + + + TOUCH_DONE_INT_ENA + Enables interruption upon the completion of a single touch. + 6 + 1 + read-write + + + TOUCH_ACTIVE_INT_ENA + Enables interruption when a touch is detected. + 7 + 1 + read-write + + + TOUCH_INACTIVE_INT_ENA + Enables interruption when a touch is released. + 8 + 1 + read-write + + + BROWN_OUT_INT_ENA + Enables the brown out interrupt. + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA + Enables the RTC main timer interrupt. + 10 + 1 + read-write + + + SARADC1_INT_ENA + Enables the SAR ADC 1 interrupt. + 11 + 1 + read-write + + + TSENS_INT_ENA + Enables the touch sensor interrupt. + 12 + 1 + read-write + + + COCPU_INT_ENA + Enables the ULP-RISCV interrupt. + 13 + 1 + read-write + + + SARADC2_INT_ENA + Enables the SAR ADC 2 interrupt. + 14 + 1 + read-write + + + SWD_INT_ENA + Enables the super watchdog interrupt. + 15 + 1 + read-write + + + XTAL32K_DEAD_INT_ENA + Enables interruption when the 32 kHz crystal is dead. + 16 + 1 + read-write + + + COCPU_TRAP_INT_ENA + Enables interruption when the ULP-RISCV is trapped. + 17 + 1 + read-write + + + TOUCH_TIMEOUT_INT_ENA + Enables interruption when touch sensor times out. + 18 + 1 + read-write + + + GLITCH_DET_INT_ENA + Enables interruption when a glitch is detected. + 19 + 1 + read-write + + + + + INT_RAW_RTC + RTC interrupt raw register + 0x44 + 0x20 + + + SLP_WAKEUP_INT_RAW + Stores the raw interrupt triggered when the chip wakes up from sleep. + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + Stores the raw interrupt triggered when the chip rejects to go to sleep. + 1 + 1 + read-only + + + SDIO_IDLE_INT_RAW + Stores the raw interrupt triggered when the SDIO idles. + 2 + 1 + read-only + + + WDT_INT_RAW + Stores the raw RTC watchdog interrupt. + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_RAW + Stores the raw interrupt triggered upon the completion of a touch scanning. + 4 + 1 + read-only + + + ULP_CP_INT_RAW + Stores the raw ULP co-processor interrupt. + 5 + 1 + read-only + + + TOUCH_DONE_INT_RAW + Stores the raw interrupt triggered upon the completion of a single touch. + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_RAW + Stores the raw interrupt triggered when a touch is detected. + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_RAW + Stores the raw interrupt triggered when a touch is released. + 8 + 1 + read-only + + + BROWN_OUT_INT_RAW + Stores the raw brown out interrupt. + 9 + 1 + read-only + + + MAIN_TIMER_INT_RAW + Stores the raw RTC main timer interrupt. + 10 + 1 + read-only + + + SARADC1_INT_RAW + Stores the raw SAR ADC 1 interrupt. + 11 + 1 + read-only + + + TSENS_INT_RAW + Stores the raw touch sensor interrupt. + 12 + 1 + read-only + + + COCPU_INT_RAW + Stores the raw ULP-RISCV interrupt. + 13 + 1 + read-only + + + SARADC2_INT_RAW + Stores the raw SAR ADC 2 interrupt. + 14 + 1 + read-only + + + SWD_INT_RAW + Stores the raw super watchdog interrupt. + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_RAW + Stores the raw interrupt triggered when the 32 kHz crystal is dead. + 16 + 1 + read-only + + + COCPU_TRAP_INT_RAW + Stores the raw interrupt triggered when the ULP-RISCV is trapped. + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_RAW + Stores the raw interrupt triggered when touch sensor times out. + 18 + 1 + read-only + + + GLITCH_DET_INT_RAW + Stores the raw interrupt triggered when a glitch is detected. + 19 + 1 + read-only + + + + + INT_ST_RTC + RTC interrupt state register + 0x48 + 0x20 + + + SLP_WAKEUP_INT_ST + Stores the status of the interrupt triggered when the chip wakes up from sleep. + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + Stores the status of the interrupt triggered when the chip rejects to go to sleep. + 1 + 1 + read-only + + + SDIO_IDLE_INT_ST + Stores the status of the interrupt triggered when the SDIO idles. + 2 + 1 + read-only + + + WDT_INT_ST + Stores the status of the RTC watchdog interrupt. + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_ST + Stores the status of the interrupt triggered upon the completion of a touch scanning. + 4 + 1 + read-only + + + ULP_CP_INT_ST + Stores the status of the ULP co-processor interrupt. + 5 + 1 + read-only + + + TOUCH_DONE_INT_ST + Stores the status of the interrupt triggered upon the completion of a single touch. + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_ST + Stores the status of the interrupt triggered when a touch is detected. + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_ST + Stores the status of the interrupt triggered when a touch is released. + 8 + 1 + read-only + + + BROWN_OUT_INT_ST + Stores the status of the brown out interrupt. + 9 + 1 + read-only + + + MAIN_TIMER_INT_ST + Stores the status of the RTC main timer interrupt. + 10 + 1 + read-only + + + SARADC1_INT_ST + Stores the status of the SAR ADC 1 interrupt. + 11 + 1 + read-only + + + TSENS_INT_ST + Stores the status of the touch sensor interrupt. + 12 + 1 + read-only + + + COCPU_INT_ST + Stores the status of the ULP-RISCV interrupt. + 13 + 1 + read-only + + + SARADC2_INT_ST + Stores the status of the SAR ADC 2 interrupt. + 14 + 1 + read-only + + + SWD_INT_ST + Stores the status of the super watchdog interrupt. + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_ST + Stores the status of the interrupt triggered when the 32 kHz crystal is dead. + 16 + 1 + read-only + + + COCPU_TRAP_INT_ST + Stores the status of the interrupt triggered when the ULP-RISCV is trapped. + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_ST + Stores the status of the interrupt triggered when touch sensor times out. + 18 + 1 + read-only + + + GLITCH_DET_INT_ST + Stores the status of the interrupt triggered when a glitch is detected. + 19 + 1 + read-only + + + + + INT_CLR_RTC + RTC interrupt clear register + 0x4C + 0x20 + + + SLP_WAKEUP_INT_CLR + Clears the interrupt triggered when the chip wakes up from sleep. + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clears the interrupt triggered when the chip rejects to go to sleep. + 1 + 1 + write-only + + + SDIO_IDLE_INT_CLR + Clears the interrupt triggered when the SDIO idles. + 2 + 1 + write-only + + + WDT_INT_CLR + Enables the RTC watchdog interrupt. + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_CLR + Clears the interrupt triggered upon the completion of a touch scanning. + 4 + 1 + write-only + + + ULP_CP_INT_CLR + Enables the ULP co-processor interrupt. + 5 + 1 + write-only + + + TOUCH_DONE_INT_CLR + Clears the interrupt triggered upon the completion of a single touch. + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_CLR + Clears the interrupt triggered when a touch is detected. + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_CLR + Clears the interrupt triggered when a touch is released. + 8 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clears the brown out interrupt. + 9 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clears the RTC main timer interrupt. + 10 + 1 + write-only + + + SARADC1_INT_CLR + Clears the SAR ADC 1 interrupt. + 11 + 1 + write-only + + + TSENS_INT_CLR + Clears the touch sensor interrupt. + 12 + 1 + write-only + + + COCPU_INT_CLR + Clears the ULP-RISCV interrupt. + 13 + 1 + write-only + + + SARADC2_INT_CLR + Clears the SAR ADC 2 interrupt. + 14 + 1 + write-only + + + SWD_INT_CLR + Clears the super watchdog interrupt. + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_CLR + Clears the interrupt triggered when the 32 kHz crystal is dead. + 16 + 1 + write-only + + + COCPU_TRAP_INT_CLR + Clears the interrupt triggered when the ULP-RISCV is trapped. + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_CLR + Clears the interrupt triggered when touch sensor times out. + 18 + 1 + write-only + + + GLITCH_DET_INT_CLR + Clears the interrupt triggered when a glitch is detected. + 19 + 1 + write-only + + + + + STORE0 + Reservation register 0 + 0x50 + 0x20 + + + SCRATCH0 + Reservation register 0 + 0 + 32 + read-write + + + + + STORE1 + Reservation register 1 + 0x54 + 0x20 + + + SCRATCH1 + Reservation register 1 + 0 + 32 + read-write + + + + + STORE2 + Reservation register 2 + 0x58 + 0x20 + + + SCRATCH2 + Reservation register 2 + 0 + 32 + read-write + + + + + STORE3 + Reservation register 3 + 0x5C + 0x20 + + + SCRATCH3 + Reservation register 3 + 0 + 32 + read-write + + + + + EXT_XTL_CONF + 32 kHz crystal oscillator configuration register + 0x60 + 0x20 + 0x00066C80 + + + XTAL32K_WDT_EN + Set this bit to enable the 32 kHz crystal watchdog. + 0 + 1 + read-write + + + XTAL32K_WDT_CLK_FO + Set this bit to FPU the 32 kHz crystal watchdog clock. + 1 + 1 + read-write + + + XTAL32K_WDT_RESET + Set this bit to reset the 32 kHz crystal watchdog by SW. + 2 + 1 + read-write + + + XTAL32K_EXT_CLK_FO + Set this bit to FPU the external clock of 32 kHz crystal. + 3 + 1 + read-write + + + XTAL32K_AUTO_BACKUP + Set this bit to switch to the backup clock when the 32 kHz crystal is dead. + 4 + 1 + read-write + + + XTAL32K_AUTO_RESTART + Set this bit to restart the 32 kHz crystal automatically when the 32 kHz crystal is dead. + 5 + 1 + read-write + + + XTAL32K_AUTO_RETURN + Set this bit to switch back to 32 kHz crystal when the 32 kHz crystal is restarted. + 6 + 1 + read-write + + + XTAL32K_XPD_FORCE + Set 1 to allow the software to FPD the 32 kHz crystal. Set 0 to allow the FSM to FPD the 32 kHz crystal. (R/W) + 7 + 1 + read-write + + + ENCKINIT_XTAL_32K + Applies an internal clock to help the 32 kHz crystal to start. + 8 + 1 + read-write + + + DBUF_XTAL_32K + 0: single-end buffer 1: differential buffer + 9 + 1 + read-write + + + DGM_XTAL_32K + xtal_32k gm control + 10 + 3 + read-write + + + DRES_XTAL_32K + DRES_XTAL_32K + 13 + 3 + read-write + + + XPD_XTAL_32K + XPD_XTAL_32K + 16 + 1 + read-write + + + DAC_XTAL_32K + DAC_XTAL_32K + 17 + 3 + read-write + + + WDT_STATE + Stores the status of the 32 kHz watchdog. + 20 + 3 + read-only + + + XTAL32K_GPIO_SEL + Selects the 32 kHz crystal clock. 0: selects the external 32 kHz clock. 1: selects clock from the RTC GPIO X32P_C. + 23 + 1 + read-write + + + XTL_EXT_CTR_LV + 0: powers down XTAL at high level 1: powers down XTAL at low level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + Enables the GPIO to power down the crystal oscillator. + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + GPIO wakeup configuration register + 0x64 + 0x20 + + + GPIO_WAKEUP_FILTER + Set this bit to enable the GPIO wakeup event filter. + 29 + 1 + read-write + + + EXT_WAKEUP0_LV + 0: external wakeup 0 at low level 1: external wakeup 0 at high level + 30 + 1 + read-write + + + EXT_WAKEUP1_LV + 0: external wakeup 1 at low level 1: external wakeup 1 at high level + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + Configures sleep / reject options + 0x68 + 0x20 + + + SLEEP_REJECT_ENA + Set this bit to enable reject-to-sleep. + 13 + 17 + read-write + + + LIGHT_SLP_REJECT_EN + Set this bit to enable reject-to-light-sleep. + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + Set this bit to enable reject-to-deep-sleep. + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + CPU sel option + 0x6C + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + 30 + 2 + read-write + + + + + SDIO_ACT_CONF + configure sdio active register + 0x70 + 0x20 + + + SDIO_ACT_DNUM + configure sdio act dnum + 22 + 10 + read-write + + + + + CLK_CONF + RTC clock configuration register + 0x74 + 0x20 + 0x01583218 + + + CK8M_DIV_SEL_VLD + Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock. + 3 + 1 + read-write + + + CK8M_DIV + Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024. + 4 + 2 + read-write + + + ENB_CK8M + Set this bit to disable CK8M and CK8M_D256_OUT. + 6 + 1 + read-write + + + ENB_CK8M_DIV + Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256. + 7 + 1 + read-write + + + DIG_XTAL32K_EN + Set this bit to enable CK_XTAL_32K clock for the digital core. + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + Set this bit to enable CK8M_D256_OUT clock for the digital core. + 9 + 1 + read-write + + + DIG_CLK8M_EN + Set this bit to enable 8 MHz clock for the digital core. + 10 + 1 + read-write + + + CK8M_DIV_SEL + Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + Set this bit to force no gating to crystal during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + Set this bit to disable force gating to 8 MHz crystal during sleep. + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + Set this bit to FPD the 8 MHz clock. + 25 + 1 + read-write + + + CK8M_FORCE_PU + Set this bit to FPU the 8 MHz clock. + 26 + 1 + read-write + + + FAST_CLK_RTC_SEL + Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M. + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256. + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + RTC slow clock configuration register + 0x78 + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock. + 22 + 1 + read-write + + + ANA_CLK_DIV + Set the rtc_clk divider. + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + 31 + 1 + read-write + + + + + SDIO_CONF + configure vddsdio register + 0x7C + 0x20 + 0x02B0BE0A + + + SDIO_TIMER_TARGET + timer count to apply reg_sdio_dcap after sdio power on + 0 + 8 + read-write + + + SDIO_DTHDRV + Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us. + 9 + 2 + read-write + + + SDIO_DCAP + ability to prevent LDO from overshoot + 11 + 2 + read-write + + + SDIO_INITI + add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k + 13 + 2 + read-write + + + SDIO_EN_INITI + 0 to set init[1:0]=0 + 15 + 1 + read-write + + + SDIO_DCURLIM + tune current limit threshold when tieh = 0. About 800mA/(8+d) + 16 + 3 + read-write + + + SDIO_MODECURLIM + select current limit mode + 19 + 1 + read-write + + + SDIO_ENCURLIM + enable current limit + 20 + 1 + read-write + + + SDIO_REG_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG 0: use state machine + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + REG1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 + 31 + 1 + read-write + + + + + BIAS_CONF + configure power register + 0x80 + 0x20 + 0x00010800 + + + BIAS_BUF_IDLE + open bias buf when system in active + 10 + 1 + read-write + + + BIAS_BUF_WAKE + open bias buf when rtc in wakeup + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + open bias buf when rtc in deep sleep + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + open bias buf when rtc in monitor state + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in monitor state + 22 + 4 + read-write + + + ENB_SCK_XTAL + ENB_SCK_XTAL + 26 + 1 + read-write + + + INC_HEARTBEAT_REFRESH + INC_HEARTBEAT_REFRESH + 27 + 1 + read-write + + + DEC_HEARTBEAT_PERIOD + DEC_HEARTBEAT_PERIOD + 28 + 1 + read-write + + + INC_HEARTBEAT_PERIOD + INC_HEARTBEAT_PERIOD + 29 + 1 + read-write + + + DEC_HEARTBEAT_WIDTH + DEC_HEARTBEAT_WIDTH + 30 + 1 + read-write + + + RST_BIAS_I2C + 31 + 1 + read-write + + + + + REG + RTC/DIG regulator configuration register + 0x84 + 0x20 + 0xA9002400 + + + DIG_REG_DBIAS_SLP + Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status. + 8 + 3 + read-write + + + DIG_REG_DBIAS_WAK + Configures the regulation factor for the digital system voltage regulator when the CPU is in active status. + 11 + 3 + read-write + + + SCK_DCAP + Configures the frequency of the RTC clocks. + 14 + 8 + read-write + + + DBIAS_SLP + Configures the regulation factor for the low-power voltage regulator when the CPU is in sleep status. + 22 + 3 + read-write + + + DBIAS_WAK + Configures the regulation factor for the low-power voltage regulator when the CPU is in active status. + 25 + 3 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + REGULATOR_FORCE_PD + Set this bit to FPD the RTC_REG, which means decreasing its voltage to 0.8 V or lower. + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + Set this bit to FPU the RTC_REG. + 31 + 1 + read-write + + + + + PWC + RTC power configuraiton register + 0x88 + 0x20 + 0x00012925 + + + FASTMEM_FORCE_NOISO + Set this bit to disable the force isolation to the RTC fast memory. + 0 + 1 + read-write + + + FASTMEM_FORCE_ISO + Set this bit to force isolate the RTC fast memory. + 1 + 1 + read-write + + + SLOWMEM_FORCE_NOISO + Set this bit to disable the force isolation to the RTC slow memory. + 2 + 1 + read-write + + + SLOWMEM_FORCE_ISO + Set this bit to force isolate the RTC slow memory. + 3 + 1 + read-write + + + FORCE_ISO + Set this bit to force isolate the RTC peripherals. + 4 + 1 + read-write + + + FORCE_NOISO + Set this bit to disable the force isolation to the RTC peripherals. + 5 + 1 + read-write + + + FASTMEM_FOLW_CPU + Set 1 to FPD the RTC fast memory when the CPU is powered down. Set 0 to FPD the RTC fast memory when the RTC main state machine is powered down. + 6 + 1 + read-write + + + FASTMEM_FORCE_LPD + Set this bit to force not retain the RTC fast memory. + 7 + 1 + read-write + + + FASTMEM_FORCE_LPU + Set this bit to force retain the RTC fast memory. + 8 + 1 + read-write + + + SLOWMEM_FOLW_CPU + Set 1 to FPD the RTC slow memory when the CPU is powered down. Set 0 to FPD the RTC slow memory when the RTC main state machine is powered down. + 9 + 1 + read-write + + + SLOWMEM_FORCE_LPD + Set this bit to force not retain the RTC slow memory. + 10 + 1 + read-write + + + SLOWMEM_FORCE_LPU + Set this bit to force retain the RTC slow memory. + 11 + 1 + read-write + + + FASTMEM_FORCE_PD + Set this bit to FPD the RTC fast memory. + 12 + 1 + read-write + + + FASTMEM_FORCE_PU + Set this bit to FPU the RTC fast memory. + 13 + 1 + read-write + + + FASTMEM_PD_EN + Set this bit to enable PD for the RTC fast memory in sleep. + 14 + 1 + read-write + + + SLOWMEM_FORCE_PD + Set this bit to FPD the RTC slow memory. + 15 + 1 + read-write + + + SLOWMEM_FORCE_PU + Set this bit to FPU the RTC slow memory. + 16 + 1 + read-write + + + SLOWMEM_PD_EN + Set this bit to enable PD for the RTC slow memory in sleep. + 17 + 1 + read-write + + + FORCE_PD + Set this bit to FPD the RTC peripherals. + 18 + 1 + read-write + + + FORCE_PU + Set this bit to FPU the RTC peripherals. + 19 + 1 + read-write + + + PD_EN + Set this bit to enable PD for the RTC peripherals in sleep. + 20 + 1 + read-write + + + PAD_FORCE_HOLD + Set this bit the force hold the RTC GPIOs. + 21 + 1 + read-write + + + + + DIG_PWC + Digital system power configuraiton register + 0x8C + 0x20 + 0x00555550 + + + LSLP_MEM_FORCE_PD + Set this bit to FPD the memories in the digital system in sleep. + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + Set this bit to FPU the memories in the digital system. + 4 + 1 + read-write + + + ROM0_FORCE_PD + ROM force power down + 5 + 1 + read-write + + + ROM0_FORCE_PU + ROM force power up + 6 + 1 + read-write + + + INTER_RAM0_FORCE_PD + internal SRAM 0 force power down + 7 + 1 + read-write + + + INTER_RAM0_FORCE_PU + internal SRAM 0 force power up + 8 + 1 + read-write + + + INTER_RAM1_FORCE_PD + internal SRAM 1 force power down + 9 + 1 + read-write + + + INTER_RAM1_FORCE_PU + internal SRAM 1 force power up + 10 + 1 + read-write + + + INTER_RAM2_FORCE_PD + internal SRAM 2 force power down + 11 + 1 + read-write + + + INTER_RAM2_FORCE_PU + internal SRAM 2 force power up + 12 + 1 + read-write + + + INTER_RAM3_FORCE_PD + internal SRAM 3 force power down + 13 + 1 + read-write + + + INTER_RAM3_FORCE_PU + internal SRAM 3 force power up + 14 + 1 + read-write + + + INTER_RAM4_FORCE_PD + internal SRAM 4 force power down + 15 + 1 + read-write + + + INTER_RAM4_FORCE_PU + internal SRAM 4 force power up + 16 + 1 + read-write + + + WIFI_FORCE_PD + Set this bit to FPD the Wi-Fi circuit. + 17 + 1 + read-write + + + WIFI_FORCE_PU + Set this bit to FPU the Wi-Fi circuit. + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + Set this bit to FPD the digital system. + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + Set this bit to FPD the DC-DC convertor in the digital system. + 20 + 1 + read-write + + + DG_DCDC_FORCE_PD + Set this bit to FPD the DC-DC convertor in the digital system. + 21 + 1 + read-write + + + DG_DCDC_FORCE_PU + Set this bit to FPU the DC-DC convertor in the digital system. + 22 + 1 + read-write + + + DG_DCDC_PD_EN + Set this bit to enable PD for the DC-DC convertor in the digital system. + 23 + 1 + read-write + + + ROM0_PD_EN + enable power down ROM in sleep + 24 + 1 + read-write + + + INTER_RAM0_PD_EN + enable power down internal SRAM 0 in sleep + 25 + 1 + read-write + + + INTER_RAM1_PD_EN + enable power down internal SRAM 1 in sleep + 26 + 1 + read-write + + + INTER_RAM2_PD_EN + enable power down internal SRAM 2 in sleep + 27 + 1 + read-write + + + INTER_RAM3_PD_EN + enable power down internal SRAM 3 in sleep + 28 + 1 + read-write + + + INTER_RAM4_PD_EN + enable power down internal SRAM 4 in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + Set this bit to enable PD for the Wi-Fi circuit in sleep. + 30 + 1 + read-write + + + DG_WRAP_PD_EN + Set this bit to enable PD for the digital system in sleep. + 31 + 1 + read-write + + + + + DIG_ISO + Digital system ISO configuration register + 0x90 + 0x20 + 0xAAAA5000 + + + FORCE_OFF + 7 + 1 + read-write + + + FORCE_ON + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + Indicates the auto-hold status of the digital GPIOs. + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + Se this bit to clear the auto-hold enabler for the digital GPIOs. + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + Se this bit to allow the digital GPIOs to enter the autohold status. + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + Set this bit to disable the force isolation to the digital GPIOs. + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + Set this bit to force isolate the digital GPIOs. + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + Set this bit the force unhold the digital GPIOs. + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + Set this bit the force hold the digital GPIOs. + 15 + 1 + read-write + + + ROM0_FORCE_ISO + ROM force ISO + 16 + 1 + read-write + + + ROM0_FORCE_NOISO + ROM force no ISO + 17 + 1 + read-write + + + INTER_RAM0_FORCE_ISO + internal SRAM 0 force ISO + 18 + 1 + read-write + + + INTER_RAM0_FORCE_NOISO + internal SRAM 0 force no ISO + 19 + 1 + read-write + + + INTER_RAM1_FORCE_ISO + internal SRAM 1 force ISO + 20 + 1 + read-write + + + INTER_RAM1_FORCE_NOISO + internal SRAM 1 force no ISO + 21 + 1 + read-write + + + INTER_RAM2_FORCE_ISO + internal SRAM 2 force ISO + 22 + 1 + read-write + + + INTER_RAM2_FORCE_NOISO + internal SRAM 2 force no ISO + 23 + 1 + read-write + + + INTER_RAM3_FORCE_ISO + internal SRAM 3 force ISO + 24 + 1 + read-write + + + INTER_RAM3_FORCE_NOISO + internal SRAM 3 force no ISO + 25 + 1 + read-write + + + INTER_RAM4_FORCE_ISO + internal SRAM 4 force ISO + 26 + 1 + read-write + + + INTER_RAM4_FORCE_NOISO + internal SRAM 4 force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + Set this bit to force isolate the Wi-Fi circuits. + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + Set this bit to disable the force isolation to the Wi-Fi circuits. + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + Set this bit to force isolate the digital system. + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + Set this bit to disable the force isolation to the digital system. + 31 + 1 + read-write + + + + + WDTCONFIG0 + RTC watchdog configuration register + 0x94 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + Set this bit to pause the watchdog in sleep. + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + Set this bit to allow the watchdog to be able to reset CPU. + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + Set this bit to enable watchdog when the chip boots from flash. + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + Sets the length of the system reset counter. + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + Sets the length of the CPU reset counter. + 16 + 3 + read-write + + + WDT_STG3 + 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. + 19 + 3 + read-write + + + WDT_STG2 + 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. + 22 + 3 + read-write + + + WDT_STG1 + 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. + 25 + 3 + read-write + + + WDT_STG0 + 1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage. + 28 + 3 + read-write + + + WDT_EN + Set this bit to enable the RTC watchdog. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Configures the hold time of RTC watchdog at level 1 + 0x98 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + Configures the hold time of RTC watchdog at level 1. + 0 + 32 + read-write + + + + + WDTCONFIG2 + Configures the hold time of RTC watchdog at level 2 + 0x9C + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + Configures the hold time of RTC watchdog at level 2. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Configures the hold time of RTC watchdog at level 3 + 0xA0 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + Configures the hold time of RTC watchdog at level 3. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Configures the hold time of RTC watchdog at level 4 + 0xA4 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + Configures the hold time of RTC watchdog at level 4. + 0 + 32 + read-write + + + + + WDTFEED + RTC watchdog SW feed configuration register + 0xA8 + 0x20 + + + WDT_FEED + Set 1 to feed the RTC watchdog. + 31 + 1 + write-only + + + + + WDTWPROTECT + RTC watchdog write protection configuration register + 0xAC + 0x20 + 0x50D83AA1 + + + WDT_WKEY + Sets the write protection key of the watchdog. + 0 + 32 + read-write + + + + + SWD_CONF + Super watchdog configuration register + 0xB0 + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + Indicates the super watchdog reset flag. + 0 + 1 + read-only + + + SWD_FEED_INT + Receiving this interrupt leads to feeding the super watchdog via SW. + 1 + 1 + read-only + + + SWD_SIGNAL_WIDTH + Adjusts the signal width sent to the super watchdog. + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + Set to reset the super watchdog reset flag. + 28 + 1 + write-only + + + SWD_FEED + Set to feed the super watchdog via SW. + 29 + 1 + write-only + + + SWD_DISABLE + Set this bit to disable super watchdog. + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + Set this bit to enable automatic watchdog feeding upon interrupts. + 31 + 1 + read-write + + + + + SWD_WPROTECT + Super watchdog write protection configuration register + 0xB4 + 0x20 + 0x8F1D312A + + + SWD_WKEY + Sets the write protection key of the super watchdog. + 0 + 32 + read-write + + + + + SW_CPU_STALL + CPU stall configuration register + 0xB8 + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + Set this bit to allow the SW to be able to send the CPU into stalling. + 26 + 6 + read-write + + + + + STORE4 + Reservation register 4 + 0xBC + 0x20 + + + SCRATCH4 + Reservation register 4. + 0 + 32 + read-write + + + + + STORE5 + Reservation register 5 + 0xC0 + 0x20 + + + SCRATCH5 + Reservation register 5. + 0 + 32 + read-write + + + + + STORE6 + Reservation register 6 + 0xC4 + 0x20 + + + SCRATCH6 + Reservation register 6. + 0 + 32 + read-write + + + + + STORE7 + Reservation register 7 + 0xC8 + 0x20 + + + SCRATCH7 + Reservation register 7. + 0 + 32 + read-write + + + + + LOW_POWER_ST + RTC main state machine status register + 0xCC + 0x20 + + + XPD_ROM0 + rom0 power down + 0 + 1 + read-only + + + XPD_DIG_DCDC + External DCDC power down + 2 + 1 + read-only + + + PERI_ISO + rtc peripheral iso + 3 + 1 + read-only + + + XPD_RTC_PERI + rtc peripheral power down + 4 + 1 + read-only + + + WIFI_ISO + wifi iso + 5 + 1 + read-only + + + XPD_WIFI + wifi wrap power down + 6 + 1 + read-only + + + DIG_ISO + digital wrap iso + 7 + 1 + read-only + + + XPD_DIG + digital wrap power down + 8 + 1 + read-only + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-only + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-only + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-only + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-only + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-only + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-only + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-only + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-only + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-only + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-only + + + RDY_FOR_WAKEUP + Indicates the RTC is ready to be triggered by any wakeup source. + 19 + 1 + read-only + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-only + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-only + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-only + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-only + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-only + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-only + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-only + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-only + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-only + + + + + DIAG0 + debug register + 0xD0 + 0x20 + + + LOW_POWER_DIAG1 + 0 + 32 + read-only + + + + + PAD_HOLD + Configures the hold options for RTC GPIOs + 0xD4 + 0x20 + + + TOUCH_PAD0_HOLD + Sets the touch GPIO 0 to hold. + 0 + 1 + read-write + + + TOUCH_PAD1_HOLD + Sets the touch GPIO 1 to hold. + 1 + 1 + read-write + + + TOUCH_PAD2_HOLD + Sets the touch GPIO 2 to hold. + 2 + 1 + read-write + + + TOUCH_PAD3_HOLD + Sets the touch GPIO 3 to hold. + 3 + 1 + read-write + + + TOUCH_PAD4_HOLD + Sets the touch GPIO 4 to hold. + 4 + 1 + read-write + + + TOUCH_PAD5_HOLD + Sets the touch GPIO 5 to hold. + 5 + 1 + read-write + + + TOUCH_PAD6_HOLD + Sets the touch GPIO 6 to hold. + 6 + 1 + read-write + + + TOUCH_PAD7_HOLD + Sets the touch GPIO 7 to hold. + 7 + 1 + read-write + + + TOUCH_PAD8_HOLD + Sets the touch GPIO 8 to hold. + 8 + 1 + read-write + + + TOUCH_PAD9_HOLD + Sets the touch GPIO 9 to hold. + 9 + 1 + read-write + + + TOUCH_PAD10_HOLD + Sets the touch GPIO 10 to hold. + 10 + 1 + read-write + + + TOUCH_PAD11_HOLD + Sets the touch GPIO 11 to hold. + 11 + 1 + read-write + + + TOUCH_PAD12_HOLD + Sets the touch GPIO 12 to hold. + 12 + 1 + read-write + + + TOUCH_PAD13_HOLD + Sets the touch GPIO 13 to hold. + 13 + 1 + read-write + + + TOUCH_PAD14_HOLD + Sets the touch GPIO 14 to hold. + 14 + 1 + read-write + + + X32P_HOLD + Sets the x32p to hold. + 15 + 1 + read-write + + + X32N_HOLD + Sets the x32n to hold. + 16 + 1 + read-write + + + PDAC1_HOLD + Sets the pdac1 to hold. + 17 + 1 + read-write + + + PDAC2_HOLD + Sets the pdac2 to hold. + 18 + 1 + read-write + + + PAD19_HOLD + Sets the RTG GPIO 19 to hold. + 19 + 1 + read-write + + + PAD20_HOLD + Sets the RTG GPIO 20 to hold. + 20 + 1 + read-write + + + PAD21_HOLD + Sets the RTG GPIO 21 to hold. + 21 + 1 + read-write + + + + + DIG_PAD_HOLD + Configures the hold option for digital GPIOs + 0xD8 + 0x20 + + + DIG_PAD_HOLD + Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO). + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + EXT1 wakeup configuration register + 0xDC + 0x20 + + + SEL + Selects a RTC GPIO to be the EXT1 wakeup source. + 0 + 22 + read-write + + + STATUS_CLR + Clears the EXT1 wakeup status. + 22 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + EXT1 wakeup source register + 0xE0 + 0x20 + + + EXT_WAKEUP1_STATUS + Indicates the EXT1 wakeup status. + 0 + 22 + read-only + + + + + BROWN_OUT + Brownout configuration register + 0xE4 + 0x20 + 0x03FF2FF1 + + + BROWN_OUT2_ENA + Enables the brown_out2 to initiate a chip reset. + 0 + 1 + read-write + + + INT_WAIT + Configures the waiting cycle before sending an interrupt. + 4 + 10 + read-write + + + CLOSE_FLASH_ENA + Set this bit to enable PD the flash when a brown-out happens. + 14 + 1 + read-write + + + PD_RF_ENA + Set this bit to enable PD the RF circuits when a brown-out happens. + 15 + 1 + read-write + + + RST_WAIT + Configures the waiting cycle before the reset after a brown-out. + 16 + 10 + read-write + + + RST_ENA + Enables to reset brown-out. + 26 + 1 + read-write + + + RST_SEL + Selects the reset type when a brown-out happens. 1: chip reset 0: system reset. + 27 + 1 + read-write + + + CNT_CLR + Clears the brown-out counter. + 29 + 1 + write-only + + + ENA + Set this bit to enable brown-out detection. + 30 + 1 + read-write + + + DET + Indicates the status of the brown-out signal. + 31 + 1 + read-only + + + + + TIME_LOW1 + Stores the lower 32 bits of RTC timer 1 + 0xE8 + 0x20 + + + TIMER_VALUE1_LOW + Stores the lower 32 bits of RTC timer 1. + 0 + 32 + read-only + + + + + TIME_HIGH1 + Stores the higher 16 bits of RTC timer 1 + 0xEC + 0x20 + + + TIMER_VALUE1_HIGH + Stores the higher 16 bits of RTC timer. + 0 + 16 + read-only + + + + + XTAL32K_CLK_FACTOR + Configures the divider factor for the backup clock of 32 kHz crystal oscillator + 0xF0 + 0x20 + + + XTAL32K_CLK_FACTOR + Configures the divider factor for the 32 kHz crystal oscillator. + 0 + 32 + read-write + + + + + XTAL32K_CONF + 32 kHz crystal oscillator configuration register + 0xF4 + 0x20 + 0x0FF00000 + + + XTAL32K_RETURN_WAIT + Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator. + 0 + 4 + read-write + + + XTAL32K_RESTART_WAIT + Defines the maximum waiting cycle before restarting the 32 kHz crystal oscillator. + 4 + 16 + read-write + + + XTAL32K_WDT_TIMEOUT + Defines the maximum waiting period for clock detection. If no clock is detected after this period, the 32 kHz crystal oscillator can be regarded as dead. + 20 + 8 + read-write + + + XTAL32K_STABLE_THRES + Defines the maximum allowed restarting period, within which the 32 kHz crystal oscillator can be regarded as stable. + 28 + 4 + read-write + + + + + ULP_CP_TIMER + Configure coprocessor timer + 0xF8 + 0x20 + + + ULP_CP_PC_INIT + ULP coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + Enable the option of ULP coprocessor woken up by +RTC GPIO + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + Disable the option of ULP coprocessor woken up by +RTC GPIO + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP coprocessor timer enable bit. 0: Disable hardware +Timer. 1: Enable hardware timer + 31 + 1 + read-write + + + + + ULP_CP_CTRL + ULP-FSM configuration register + 0xFC + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + 11 + 11 + read-write + + + ULP_CP_MEM_OFFSET_CLR + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ULP-FSM clock force on + 28 + 1 + read-write + + + ULP_CP_RESET + ULP-FSM clock software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + Write 1 to start ULP-FSM by software + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-FSM + 31 + 1 + read-write + + + + + COCPU_CTRL + ULP-RISCV configuration register + 0x100 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + ULP-RISCV clock force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + Time from ULP-RISCV startup to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + Time from ULP-RISCV startup to send out +RISCV_START_INT interrupt + 7 + 6 + read-write + + + COCPU_SHUT + Shut down ULP-RISCV + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + Time from shut down ULP-RISCV to disable clock + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + This bit is used to reset ULP-RISCV + 22 + 1 + read-write + + + COCPU_SEL + 0: select ULP-RISCV. 1: select ULP-FSM + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE +signal + 24 + 1 + read-write + + + COCPU_DONE + DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the +timer starts counting + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + Trigger ULP-RISCV register interrupt + 26 + 1 + write-only + + + + + TOUCH_CTRL1 + Touch control register + 0x104 + 0x20 + 0x10000100 + + + TOUCH_SLEEP_CYCLES + Set sleep cycles for touch timer. + 0 + 16 + read-write + + + TOUCH_MEAS_NUM + Configure measurement length (in 8 MHz), i.e., charge/discharge times. + 16 + 16 + read-write + + + + + TOUCH_CTRL2 + Touch control register + 0x108 + 0x20 + 0x000840CC + + + TOUCH_DRANGE + TOUCH attenuation. + 2 + 2 + read-write + + + TOUCH_DREFL + TOUCH reference voltage low. 0: 0.5 V 1: 0.6 V 2: 0.7 V 3: 0.8 V. + 4 + 2 + read-write + + + TOUCH_DREFH + TOUCH reference voltage high. 0: 2.4 V 1: 2.5 V 2: 2.6 V 3: 2.7 V. + 6 + 2 + read-write + + + TOUCH_XPD_BIAS + TOUCH BIAS power switch. + 8 + 1 + read-write + + + TOUCH_REFC + Touch pad 0 reference capacitance. + 9 + 3 + read-write + + + TOUCH_DBIAS + 0: Use bandgap bias. 1: Use self bias. + 12 + 1 + read-write + + + TOUCH_SLP_TIMER_EN + Touch timer enable bit. + 13 + 1 + read-write + + + TOUCH_START_FSM_EN + 0: TOUCH_START and TOUCH_XPD are controlled by soft- ware. 1: TOUCH_START and TOUCH_XPD are controlled by the Touch FSM. + 14 + 1 + read-write + + + TOUCH_START_EN + 1: Start the Touch FSM, only valid when RTC_CNTL_TOUCH_START_FORCE = 1. + 15 + 1 + read-write + + + TOUCH_START_FORCE + 0: Start the Touch FSM by timer. 1: Start Touch FSM by software. + 16 + 1 + read-write + + + TOUCH_XPD_WAIT + The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD. + 17 + 8 + read-write + + + TOUCH_SLP_CYC_DIV + When a touch pad is active, sleep cycle could be divided by this number. + 25 + 2 + read-write + + + TOUCH_TIMER_FORCE_DONE + Force touch timer done. + 27 + 2 + read-write + + + TOUCH_RESET + Reset TOUCH FSM via software. + 29 + 1 + read-write + + + TOUCH_CLK_FO + Touch clock force on. + 30 + 1 + read-write + + + TOUCH_CLKGATE_EN + Touch clock enable bit. + 31 + 1 + read-write + + + + + TOUCH_SCAN_CTRL + Configure touch scan settings + 0x10C + 0x20 + 0xF0000102 + + + TOUCH_DENOISE_RES + Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit. + 0 + 2 + read-write + + + TOUCH_DENOISE_EN + Touch pad 0 will be used to denoise. + 2 + 1 + read-write + + + TOUCH_INACTIVE_CONNECTION + Inactive touch pads connect to 0: HighZ, 1: GND. + 8 + 1 + read-write + + + TOUCH_SHIELD_PAD_EN + Touch pad 14 will be used as shield_pad. + 9 + 1 + read-write + + + TOUCH_SCAN_PAD_MAP + Pad enable map for touch scan mode. + 10 + 15 + read-write + + + TOUCH_BUFDRV + Touch 14 buffer driver strength. + 25 + 3 + read-write + + + TOUCH_OUT_RING + Select out one pad as guard_ring. + 28 + 4 + read-write + + + + + TOUCH_SLP_THRES + Configure the settings of touch sleep pad + 0x110 + 0x20 + 0x78000000 + + + TOUCH_SLP_TH + Set the threshold for touch sleep pad. + 0 + 22 + read-write + + + TOUCH_SLP_APPROACH_EN + Enable the proximity mode of touch sleep pad. + 26 + 1 + read-write + + + TOUCH_SLP_PAD + Select sleep pad. + 27 + 5 + read-write + + + + + TOUCH_APPROACH + Configure touch approach settings + 0x114 + 0x20 + 0x50000000 + + + TOUCH_SLP_CHANNEL_CLR + Clear touch sleep channel. + 23 + 1 + write-only + + + MEAS_TIME + Set the total measurement times for the pads in +proximity mode. Range: 0 – 255. + 24 + 8 + read-write + + + + + TOUCH_FILTER_CTRL + Configure touch filter settings + 0x118 + 0x20 + 0x96AA8800 + + + TOUCH_SMOOTH_LVL + 0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8. + 9 + 2 + read-write + + + TOUCH_JITTER_STEP + Touch jitter step. Range: 0 – 15. + 11 + 4 + read-write + + + TOUCH_NEG_NOISE_LIMIT + Negative threshold counter limit. + 15 + 4 + read-write + + + TOUCH_NEG_NOISE_THRES + Negative noise threshold. + 19 + 2 + read-write + + + TOUCH_NOISE_THRES + Active noise threshold. + 21 + 2 + read-write + + + TOUCH_HYSTERESIS + Touch hysteresis. + 23 + 2 + read-write + + + TOUCH_DEBOUNCE + Debounce counter. + 25 + 3 + read-write + + + TOUCH_FILTER_MODE + Set filter mode. 0: IIR 1/2; 1: IIR 1/4; 2: IIR 1/8; 3: IIR 1/16; 4: IIR 1/32; 5: IIR 1/64; 6: IIR 1/128; 7: Jitter. + 28 + 3 + read-write + + + TOUCH_FILTER_EN + Enable touch filter. + 31 + 1 + read-write + + + + + USB_CONF + configure usb control register + 0x11C + 0x20 + + + USB_VREFH + 0 + 2 + read-write + + + USB_VREFL + 2 + 2 + read-write + + + USB_VREF_OVERRIDE + 4 + 1 + read-write + + + USB_PAD_PULL_OVERRIDE + 5 + 1 + read-write + + + USB_DP_PULLUP + 6 + 1 + read-write + + + USB_DP_PULLDOWN + 7 + 1 + read-write + + + USB_DM_PULLUP + 8 + 1 + read-write + + + USB_DM_PULLDOWN + 9 + 1 + read-write + + + USB_PULLUP_VALUE + 10 + 1 + read-write + + + USB_PAD_ENABLE_OVERRIDE + 11 + 1 + read-write + + + USB_PAD_ENABLE + 12 + 1 + read-write + + + USB_TXM + 13 + 1 + read-write + + + USB_TXP + 14 + 1 + read-write + + + USB_TX_EN + 15 + 1 + read-write + + + USB_TX_EN_OVERRIDE + 16 + 1 + read-write + + + USB_RESET_DISABLE + 17 + 1 + read-write + + + IO_MUX_RESET_DISABLE + 18 + 1 + read-write + + + + + TOUCH_TIMEOUT_CTRL + Configure touch timeout settings + 0x120 + 0x20 + 0x007FFFFF + + + TOUCH_TIMEOUT_NUM + Set touch timeout threshold. + 0 + 22 + read-write + + + TOUCH_TIMEOUT_EN + Enable touch timeout. + 22 + 1 + read-write + + + + + SLP_REJECT_CAUSE + Stores the reject-to-sleep cause. + 0x124 + 0x20 + + + REJECT_CAUSE + Stores the reject-to-sleep cause. + 0 + 17 + read-only + + + + + OPTIONS1 + RTC option register + 0x128 + 0x20 + + + FORCE_DOWNLOAD_BOOT + Set this bit to force the chip to boot from the download mode. + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + Stores the sleep-to-wakeup cause. + 0x12C + 0x20 + + + WAKEUP_CAUSE + Stores the wakeup cause. + 0 + 17 + read-only + + + + + ULP_CP_TIMER_1 + Configure sleep cycle of the timer + 0x130 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + Set sleep cycles for ULP coprocessor timer + 8 + 24 + read-write + + + + + DATE + 0x138 + 0x20 + 0x01906191 + + + CNTL_DATE + 0 + 28 + read-write + + + + + + + RTC_I2C + Peripheral RTC_I2C + RTC_I2C + 0x3F408C00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + Configure the low level width of SCL + 0x0 + 0x20 + 0x00000100 + + + PERIOD + This register is used to configure how many clock cycles SCL +remains low. + 0 + 20 + read-write + + + + + CTRL + Transmission setting + 0x4 + 0x20 + + + SDA_FORCE_OUT + SDA output mode. 0: open drain. 1: push pull. + 0 + 1 + read-write + + + SCL_FORCE_OUT + SCL output mode. 0: open drain. 1: push pull. + 1 + 1 + read-write + + + MS_MODE + Set this bit to configure RTC I²C as a master. + 2 + 1 + read-write + + + TRANS_START + Set this bit to 1, RTC I2C starts sending data. + 3 + 1 + read-write + + + TX_LSB_FIRST + This bit is used to control the sending mode. 0: send data from the most +significant bit. 1: send data from the least significant bit. + 4 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. 0: receive +data from the most significant bit. 1: receive data from the least significant bit. + 5 + 1 + read-write + + + CLK_GATE_EN + RTC I²C controller clock gate. + 29 + 1 + read-write + + + RESET + RTC I²C software reset. + 30 + 1 + read-write + + + CLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + RTC I2C status + 0x8 + 0x20 + + + ACK_REC + The received ACK value. 0: ACK. 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + 0: master writes to slave. 1: master reads from slave. + 1 + 1 + read-only + + + ARB_LOST + When the RTC I2C loses control of SCL line, the register changes to 1. + 2 + 1 + read-only + + + BUS_BUSY + 0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data. + 3 + 1 + read-only + + + SLAVE_ADDRESSED + When the address sent by the master matches the address of the +slave, then this bit will be set. + 4 + 1 + read-only + + + BYTE_TRANS + This field changes to 1 when one byte is transferred. + 5 + 1 + read-only + + + OP_CNT + Indicate which operation is working. + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + Configure RTC I2C timeout + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + Timeout threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + Configure slave address + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode. + 31 + 1 + read-write + + + + + SCL_HIGH + Configure the high level width of SCL + 0x14 + 0x20 + 0x00000100 + + + PERIOD + This register is used to configure how many cycles SCL remains high. + 0 + 20 + read-write + + + + + SDA_DUTY + Configure the SDA hold time after a negative +SCL edge + 0x18 + 0x20 + 0x00000010 + + + NUM + The number of clock cycles between the SDA switch and the falling +edge of SCL. + 0 + 20 + read-write + + + + + SCL_START_PERIOD + Configure the delay between the SDA and SCL +negative edge for a start condition + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + Number of clock cycles to wait after generating a start condition. + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + Configure the delay between SDA and SCL positive edge for a stop condition + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + Number of clock cycles to wait before generating a stop condition. + 0 + 20 + read-write + + + + + INT_CLR + Clear RTC I2C interrupt + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + RTC_I2C_MASTER_TRAN_COMP_INT interrupt +clear bit + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + RTC_I2C_TIME_OUT_INT interrupt clear bit + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + RTC_I2C_ACK_ERR_INT interrupt clear bit + 5 + 1 + write-only + + + RX_DATA_INT_CLR + RTC_I2C_RX_DATA_INT interrupt clear bit + 6 + 1 + write-only + + + TX_DATA_INT_CLR + RTC_I2C_TX_DATA_INT interrupt clear bit + 7 + 1 + write-only + + + DETECT_START_INT_CLR + RTC_I2C_DETECT_START_INT interrupt clear bit + 8 + 1 + write-only + + + + + INT_RAW + RTC I2C raw interrupt + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + RTC_I2C_TIME_OUT_INT interrupt raw bit + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + RTC_I2C_ACK_ERR_INT interrupt raw bit + 5 + 1 + read-only + + + RX_DATA_INT_RAW + RTC_I2C_RX_DATA_INT interrupt raw bit + 6 + 1 + read-only + + + TX_DATA_INT_RAW + RTC_I2C_TX_DATA_INT interrupt raw bit + 7 + 1 + read-only + + + DETECT_START_INT_RAW + RTC_I2C_DETECT_START_INT interrupt raw bit + 8 + 1 + read-only + + + + + INT_ST + RTC I2C interrupt status + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + RTC_I2C_ARBITRATION_LOST_INT interrupt status bit + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + RTC_I2C_TRANS_COMPLETE_INT interrupt status bit + 3 + 1 + read-only + + + TIME_OUT_INT_ST + RTC_I2C_TIME_OUT_INT interrupt status bit + 4 + 1 + read-only + + + ACK_ERR_INT_ST + RTC_I2C_ACK_ERR_INT interrupt status bit + 5 + 1 + read-only + + + RX_DATA_INT_ST + RTC_I2C_RX_DATA_INT interrupt status bit + 6 + 1 + read-only + + + TX_DATA_INT_ST + RTC_I2C_TX_DATA_INT interrupt status bit + 7 + 1 + read-only + + + DETECT_START_INT_ST + RTC_I2C_DETECT_START_INT interrupt status bit + 8 + 1 + read-only + + + + + INT_ENA + Enable RTC I2C interrupt + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + RTC_I2C_TIME_OUT_INT interrupt enable bit + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + RTC_I2C_ACK_ERR_INT interrupt enable bit + 5 + 1 + read-write + + + RX_DATA_INT_ENA + RTC_I2C_RX_DATA_INT interrupt enable bit + 6 + 1 + read-write + + + TX_DATA_INT_ENA + RTC_I2C_TX_DATA_INT interrupt enable bit + 7 + 1 + read-write + + + DETECT_START_INT_ENA + RTC_I2C_DETECT_START_INT interrupt enable bit + 8 + 1 + read-write + + + + + DATA + RTC I2C read data + 0x34 + 0x20 + + + RDATA + Data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + The data sent by slave + 8 + 8 + read-write + + + DONE + RTC I2C transmission is done. + 31 + 1 + read-only + + + + + 16 + 0x4 + 0-15 + CMD%s + RTC I2C Command %s + 0x38 + 0x20 + 0x00000903 + + + COMMAND + Content of command 0. For more information, please refer to the register +I2C_COMD0_REG in Chapter I²C Controller + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done, this bit changes to 1. + 31 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x01905310 + + + DATE + Version control register + 0 + 28 + read-write + + + + + + + SENS + Peripheral SENS + SENS + 0x3F408800 + + 0x0 + 0x110 + registers + + + + SAR_READER1_CTRL + RTC ADC1 data and sampling control + 0x0 + 0x20 + 0x20040002 + + + SAR1_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR1_CLK_GATED + 18 + 1 + read-write + + + SAR1_SAMPLE_NUM + 19 + 8 + read-write + + + SAR1_DATA_INV + Invert SAR ADC1 data. + 28 + 1 + read-write + + + SAR1_INT_EN + Enable SAR ADC1 to send out interrupt. + 29 + 1 + read-write + + + + + SAR_READER1_STATUS + saradc1 status for debug + 0x4 + 0x20 + + + SAR1_READER_STATUS + 0 + 32 + read-only + + + + + SAR_MEAS1_CTRL1 + Configure RTC ADC1 controller + 0x8 + 0x20 + + + RTC_SARADC_RESET + SAR ADC software reset. + 22 + 1 + read-write + + + RTC_SARADC_CLKGATE_EN + Enable bit of SAR ADC clock gate. + 23 + 1 + read-write + + + FORCE_XPD_AMP + 24 + 2 + read-write + + + AMP_RST_FB_FORCE + 26 + 2 + read-write + + + AMP_SHORT_REF_FORCE + 28 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + 30 + 2 + read-write + + + + + SAR_MEAS1_CTRL2 + Control RTC ADC1 conversion and status + 0xC + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data + 0 + 16 + read-only + + + MEAS1_DONE_SAR + Indicate SAR ADC1 conversion is done. + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1. + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by software. 0: SAR ADC1 controller is started by ULP coprocessor. + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap, active only when SENS_SAR1_EN_PAD_FORCE = 1. + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by software. 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor. + 31 + 1 + read-write + + + + + SAR_MEAS1_MUX + Select the controller for SAR ADC1 + 0x10 + 0x20 + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL + 31 + 1 + read-write + + + + + SAR_ATTEN1 + Configure SAR ADC1 attenuation + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc. + 0 + 32 + read-write + + + + + SAR_AMP_CTRL1 + AMP control + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + 16 + 16 + read-write + + + + + SAR_AMP_CTRL2 + AMP control + 0x1C + 0x20 + 0x000A0000 + + + SAR1_DAC_XPD_FSM_IDLE + 0 + 1 + read-write + + + XPD_SAR_AMP_FSM_IDLE + 1 + 1 + read-write + + + AMP_RST_FB_FSM_IDLE + 2 + 1 + read-write + + + AMP_SHORT_REF_FSM_IDLE + 3 + 1 + read-write + + + AMP_SHORT_REF_GND_FSM_IDLE + 4 + 1 + read-write + + + XPD_SAR_FSM_IDLE + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + 16 + 16 + read-write + + + + + SAR_AMP_CTRL3 + AMP control register + 0x20 + 0x20 + 0x007338F3 + + + SAR1_DAC_XPD_FSM + Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software. + 0 + 4 + read-write + + + XPD_SAR_AMP_FSM + 4 + 4 + read-write + + + AMP_RST_FB_FSM + 8 + 4 + read-write + + + AMP_SHORT_REF_FSM + 12 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + 16 + 4 + read-write + + + XPD_SAR_FSM + 20 + 4 + read-write + + + SAR_RSTB_FSM + 24 + 4 + read-write + + + + + SAR_READER2_CTRL + RTC ADC2 data and sampling control + 0x24 + 0x20 + 0x40050002 + + + SAR2_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR2_WAIT_ARB_CYCLE + wait arbit stable after sar_done + 16 + 2 + read-write + + + SAR2_CLK_GATED + 18 + 1 + read-write + + + SAR2_SAMPLE_NUM + 19 + 8 + read-write + + + SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 + read-write + + + SAR2_INT_EN + enable saradc2 to send out interrupt + 30 + 1 + read-write + + + + + SAR_READER2_STATUS + saradc2 status for debug + 0x28 + 0x20 + + + SAR2_READER_STATUS + 0 + 32 + read-only + + + + + SAR_MEAS2_CTRL1 + configure rtc saradc2 + 0x2C + 0x20 + 0x07020200 + + + SAR2_CNTL_STATE + saradc2_cntl_fsm + 0 + 3 + read-only + + + SAR2_PWDET_CAL_EN + rtc control pwdet enable + 3 + 1 + read-write + + + SAR2_PKDET_CAL_EN + rtc control pkdet enable + 4 + 1 + read-write + + + SAR2_EN_TEST + SAR2_EN_TEST + 5 + 1 + read-write + + + SAR2_RSTB_FORCE + 6 + 2 + read-write + + + SAR2_STANDBY_WAIT + 8 + 8 + read-write + + + SAR2_RSTB_WAIT + 16 + 8 + read-write + + + SAR2_XPD_WAIT + 24 + 8 + read-write + + + + + SAR_MEAS2_CTRL2 + Control RTC ADC2 conversion and status + 0x30 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data. + 0 + 16 + read-only + + + MEAS2_DONE_SAR + Indicate SAR ADC2 conversion is done. + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1. + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by software. 0: SAR ADC2 controller is started by ULP coprocessor. + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap, active only whenSENS_SAR2_EN_PAD_FORCE = 1. + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by software. 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor. + 31 + 1 + read-write + + + + + SAR_MEAS2_MUX + Select the controller for SAR ADC2 + 0x34 + 0x20 + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT, PA power detector capacitance tuning. + 28 + 3 + read-write + + + SAR2_RTC_FORCE + In sleep, force to use RTC to control ADC. + 31 + 1 + read-write + + + + + SAR_ATTEN2 + Configure SAR ADC2 attenuation + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc. + 0 + 32 + read-write + + + + + SAR_POWER_XPD_SAR + configure saradc’s power by sw + 0x3C + 0x20 + + + FORCE_XPD_SAR + 29 + 2 + read-write + + + SARCLK_EN + 31 + 1 + read-write + + + + + SAR_SLAVE_ADDR1 + Configure slave addresses 0-1 of RTC I2C + 0x40 + 0x20 + + + I2C_SLAVE_ADDR1 + RTC I2C slave address 1 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR0 + RTC I2C slave address 0 + 11 + 11 + read-write + + + MEAS_STATUS + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + Configure slave addresses 2-3 of RTC I2C + 0x44 + 0x20 + + + I2C_SLAVE_ADDR3 + RTC I2C slave address 3 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR2 + RTC I2C slave address 2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + Configure slave addresses 4-5 of RTC I2C + 0x48 + 0x20 + + + I2C_SLAVE_ADDR5 + RTC I2C slave address 5 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR4 + RTC I2C slave address 4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + Configure slave addresses 6-7 of RTC I2C + 0x4C + 0x20 + + + I2C_SLAVE_ADDR7 + RTC I2C slave address 7 + 0 + 11 + read-write + + + I2C_SLAVE_ADDR6 + RTC I2C slave address 6 + 11 + 11 + read-write + + + + + SAR_TSENS_CTRL + Temperature sensor data control + 0x50 + 0x20 + 0x00019000 + + + TSENS_OUT + Temperature sensor data out. + 0 + 8 + read-only + + + TSENS_READY + Indicate temperature sensor out ready. + 8 + 1 + read-only + + + TSENS_INT_EN + Enable temperature sensor to send out interrupt. + 12 + 1 + read-write + + + TSENS_IN_INV + Invert temperature sensor data. + 13 + 1 + read-write + + + TSENS_CLK_DIV + Temperature sensor clock divider. + 14 + 8 + read-write + + + TSENS_POWER_UP + Temperature sensor power up. + 22 + 1 + read-write + + + TSENS_POWER_UP_FORCE + 1: dump out and power up controlled by software. 0: by FSM. + 23 + 1 + read-write + + + TSENS_DUMP_OUT + Temperature sensor dump out only active when SENS_TSENS_POWER_UP_FORCE = 1. + 24 + 1 + read-write + + + + + SAR_TSENS_CTRL2 + Temperature sensor control + 0x54 + 0x20 + 0x00004002 + + + TSENS_XPD_WAIT + 0 + 12 + read-write + + + TSENS_XPD_FORCE + 12 + 2 + read-write + + + TSENS_CLK_INV + 14 + 1 + read-write + + + TSENS_CLKGATE_EN + Enable temperature sensor clock. + 15 + 1 + read-write + + + TSENS_RESET + Reset temperature sensor. + 16 + 1 + read-write + + + + + SAR_I2C_CTRL + Configure RTC I2C transmission + 0x58 + 0x20 + + + SAR_I2C_CTRL + RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = +1. + 0 + 28 + read-write + + + SAR_I2C_START + Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 0: RTC I2C started by FSM. 1: RTC I2C started by software. + 29 + 1 + read-write + + + + + SAR_TOUCH_CONF + Touch sensor configuration register + 0x5C + 0x20 + 0xFFF07FFF + + + TOUCH_OUTEN + Enable touch controller output. + 0 + 15 + read-write + + + TOUCH_STATUS_CLR + Clear all touch active status. + 15 + 1 + write-only + + + TOUCH_DATA_SEL + 0 and 1: touch_raw_data; 2: base_line; 3: touch_smooth_data. + 16 + 2 + read-write + + + TOUCH_DENOISE_END + Touch denoise done. + 18 + 1 + read-only + + + TOUCH_UNIT_END + Indicate the completion of sampling. + 19 + 1 + read-only + + + TOUCH_APPROACH_PAD2 + Indicate which pad is selected as proximity pad2 + 20 + 4 + read-write + + + TOUCH_APPROACH_PAD1 + Indicate which pad is selected as proximity pad1 + 24 + 4 + read-write + + + TOUCH_APPROACH_PAD0 + Indicate which pad is selected as proximity pad0 + 28 + 4 + read-write + + + + + SAR_TOUCH_THRES1 + Finger threshold for touch pad 1 + 0x60 + 0x20 + + + TOUCH_OUT_TH1 + Finger threshold for touch pad 1 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES2 + Finger threshold for touch pad 2 + 0x64 + 0x20 + + + TOUCH_OUT_TH2 + Finger threshold for touch pad 2 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES3 + Finger threshold for touch pad 3 + 0x68 + 0x20 + + + TOUCH_OUT_TH3 + Finger threshold for touch pad 3 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES4 + Finger threshold for touch pad 4 + 0x6C + 0x20 + + + TOUCH_OUT_TH4 + Finger threshold for touch pad 4 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES5 + Finger threshold for touch pad 5 + 0x70 + 0x20 + + + TOUCH_OUT_TH5 + Finger threshold for touch pad 5 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES6 + Finger threshold for touch pad 6 + 0x74 + 0x20 + + + TOUCH_OUT_TH6 + Finger threshold for touch pad 6 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES7 + Finger threshold for touch pad 7 + 0x78 + 0x20 + + + TOUCH_OUT_TH7 + Finger threshold for touch pad 7 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES8 + Finger threshold for touch pad 8 + 0x7C + 0x20 + + + TOUCH_OUT_TH8 + Finger threshold for touch pad 8 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES9 + Finger threshold for touch pad 9 + 0x80 + 0x20 + + + TOUCH_OUT_TH9 + Finger threshold for touch pad 9 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES10 + Finger threshold for touch pad 10 + 0x84 + 0x20 + + + TOUCH_OUT_TH10 + Finger threshold for touch pad 10 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES11 + Finger threshold for touch pad 11 + 0x88 + 0x20 + + + TOUCH_OUT_TH11 + Finger threshold for touch pad 11 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES12 + Finger threshold for touch pad 12 + 0x8C + 0x20 + + + TOUCH_OUT_TH12 + Finger threshold for touch pad 12 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES13 + Finger threshold for touch pad 13 + 0x90 + 0x20 + + + TOUCH_OUT_TH13 + Finger threshold for touch pad 13 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES14 + Finger threshold for touch pad 14 + 0x94 + 0x20 + + + TOUCH_OUT_TH14 + Finger threshold for touch pad 14 + 0 + 22 + read-write + + + + + SAR_TOUCH_CHN_ST + Touch channel status register + 0xD4 + 0x20 + + + TOUCH_PAD_ACTIVE + Touch active status + 0 + 15 + read-only + + + TOUCH_CHANNEL_CLR + Clear touch channel + 15 + 15 + write-only + + + TOUCH_MEAS_DONE + Signal flag that indicates one touch pad is done. + 31 + 1 + read-only + + + + + SAR_TOUCH_STATUS0 + Status of touch controller + 0xD8 + 0x20 + + + TOUCH_DENOISE_DATA + Denoise measure value from touch sensor 0. + 0 + 22 + read-only + + + TOUCH_SCAN_CURR + Current pad in scan status + 22 + 4 + read-only + + + + + SAR_TOUCH_STATUS1 + Touch pad 1 status + 0xDC + 0x20 + + + TOUCH_PAD1_DATA + The data of touch pad 1, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD1_DEBOUNCE + Touch pad 1 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS2 + Touch pad 2 status + 0xE0 + 0x20 + + + TOUCH_PAD2_DATA + The data of touch pad 2, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD2_DEBOUNCE + Touch pad 2 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS3 + Touch pad 3 status + 0xE4 + 0x20 + + + TOUCH_PAD3_DATA + The data of touch pad 3, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD3_DEBOUNCE + Touch pad 3 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS4 + Touch pad 4 status + 0xE8 + 0x20 + + + TOUCH_PAD4_DATA + The data of touch pad 4, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD4_DEBOUNCE + Touch pad 4 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS5 + Touch pad 5 status + 0xEC + 0x20 + + + TOUCH_PAD5_DATA + The data of touch pad 5, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD5_DEBOUNCE + Touch pad 5 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS6 + Touch pad 6 status + 0xF0 + 0x20 + + + TOUCH_PAD6_DATA + The data of touch pad 6, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD6_DEBOUNCE + Touch pad 6 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS7 + Touch pad 7 status + 0xF4 + 0x20 + + + TOUCH_PAD7_DATA + The data of touch pad 7, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD7_DEBOUNCE + Touch pad 7 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS8 + Touch pad 8 status + 0xF8 + 0x20 + + + TOUCH_PAD8_DATA + The data of touch pad 8, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD8_DEBOUNCE + Touch pad 8 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS9 + Touch pad 9 status + 0xFC + 0x20 + + + TOUCH_PAD9_DATA + The data of touch pad 9, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD9_DEBOUNCE + Touch pad 9 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS10 + Touch pad 10 status + 0x100 + 0x20 + + + TOUCH_PAD10_DATA + The data of touch pad 10, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD10_DEBOUNCE + Touch pad 10 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS11 + Touch pad 11 status + 0x104 + 0x20 + + + TOUCH_PAD11_DATA + The data of touch pad 11, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD11_DEBOUNCE + Touch pad 11 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS12 + Touch pad 12 status + 0x108 + 0x20 + + + TOUCH_PAD12_DATA + The data of touch pad 12, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD12_DEBOUNCE + Touch pad 12 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS13 + Touch pad 13 status + 0x10C + 0x20 + + + TOUCH_PAD13_DATA + The data of touch pad 13, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD13_DEBOUNCE + Touch pad 13 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS14 + Touch pad 14 status + 0x110 + 0x20 + + + TOUCH_PAD14_DATA + The data of touch pad 14, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_PAD14_DEBOUNCE + Touch pad 14 debounce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS15 + Touch sleep pad status + 0x114 + 0x20 + + + TOUCH_SLP_DATA + The data of touch sleep pad, depending on the setting of SENS_TOUCH_DATA_SEL. + 0 + 22 + read-only + + + TOUCH_SLP_DEBOUNCE + Touch sleep pad debouce value. + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS16 + Touch approach count status + 0x118 + 0x20 + + + TOUCH_APPROACH_PAD2_CNT + Count status of proximity pad 2. + 0 + 8 + read-only + + + TOUCH_APPROACH_PAD1_CNT + Count status of proximity pad 1. + 8 + 8 + read-only + + + TOUCH_APPROACH_PAD0_CNT + Count status of proximity pad 0. + 16 + 8 + read-only + + + TOUCH_SLP_APPROACH_CNT + Count status of sleep pad in proximity mode. + 24 + 8 + read-only + + + + + SAR_DAC_CTRL1 + DAC control + 0x11C + 0x20 + + + SW_FSTEP + Frequency step for CW generator can be used to adjust the frequency. + 0 + 16 + read-write + + + SW_TONE_EN + 0: disable CW generator. 1: enable CW generator. + 16 + 1 + read-write + + + DEBUG_BIT_SEL + 17 + 5 + read-write + + + DAC_DIG_FORCE + 0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA. + 22 + 1 + read-write + + + DAC_CLK_FORCE_LOW + 1: force PDAC_CLK to low + 23 + 1 + read-write + + + DAC_CLK_FORCE_HIGH + 1: force PDAC_CLK to high + 24 + 1 + read-write + + + DAC_CLK_INV + 1: invert PDAC_CLK. + 25 + 1 + read-write + + + DAC_RESET + Reset DAC by software. + 26 + 1 + read-write + + + DAC_CLKGATE_EN + DAC clock gate enable bit. + 27 + 1 + read-write + + + + + SAR_DAC_CTRL2 + DAC output control + 0x120 + 0x20 + 0x03000000 + + + DAC_DC1 + DC offset for DAC1 CW generator. + 0 + 8 + read-write + + + DAC_DC2 + DC offset for DAC2 CW generator. + 8 + 8 + read-write + + + DAC_SCALE1 + DAC1 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8. + 16 + 2 + read-write + + + DAC_SCALE2 + DAC2 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8. + 18 + 2 + read-write + + + DAC_INV1 + Invert DAC1. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB. + 20 + 2 + read-write + + + DAC_INV2 + Invert DAC2. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB. + 22 + 2 + read-write + + + DAC_CW_EN1 + 1: select CW generator as source for PDAC1_DAC. 0: select register RT- CIO_PDAC1_DAC as source for PDAC1_DAC. + 24 + 1 + read-write + + + DAC_CW_EN2 + 1: select CW generator as source for PDAC2_DAC. 0: select register RT- CIO_PDAC2_DAC as source for PDAC2_DAC. + 25 + 1 + read-write + + + + + SAR_COCPU_STATE + ULP-RISCV status + 0x124 + 0x20 + + + COCPU_DBG_TRIGGER + Trigger ULP-RISCV debug registers + 25 + 1 + write-only + + + COCPU_CLK_EN + Check ULP-RISCV whether clk on + 26 + 1 + read-only + + + COCPU_RESET_N + Check ULP-RISCV whether in reset state + 27 + 1 + read-only + + + COCPU_EOI + Check ULP-RISCV whether in interrupt state + 28 + 1 + read-only + + + COCPU_TRAP + Check ULP-RISCV whether in trap state + 29 + 1 + read-only + + + COCPU_EBREAK + Check ULP-RISCV whether in ebreak + 30 + 1 + read-only + + + + + SAR_COCPU_INT_RAW + Interrupt raw bit of ULP-RISCV + 0x128 + 0x20 + + + COCPU_TOUCH_DONE_INT_RAW + TOUCH_DONE_INT interrupt raw bit + 0 + 1 + read-only + + + COCPU_TOUCH_INACTIVE_INT_RAW + TOUCH_INACTIVE_INT interrupt raw bit + 1 + 1 + read-only + + + COCPU_TOUCH_ACTIVE_INT_RAW + TOUCH_ACTIVE_INT interrupt raw bit + 2 + 1 + read-only + + + COCPU_SARADC1_INT_RAW + SARADC1_DONE_INT interrupt raw bit + 3 + 1 + read-only + + + COCPU_SARADC2_INT_RAW + SARADC2_DONE_INT interrupt raw bit + 4 + 1 + read-only + + + COCPU_TSENS_INT_RAW + TSENS_DONE_INT interrupt raw bit + 5 + 1 + read-only + + + COCPU_START_INT_RAW + RISCV_START_INT interrupt raw bit + 6 + 1 + read-only + + + COCPU_SW_INT_RAW + SW_INT interrupt raw bit + 7 + 1 + read-only + + + COCPU_SWD_INT_RAW + SWD_INT interrupt raw bit + 8 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + Interrupt enable bit of ULP-RISCV + 0x12C + 0x20 + + + COCPU_TOUCH_DONE_INT_ENA + TOUCH_DONE_INT interrupt enable bit + 0 + 1 + read-write + + + COCPU_TOUCH_INACTIVE_INT_ENA + TOUCH_INACTIVE_INT interrupt enable bit + 1 + 1 + read-write + + + COCPU_TOUCH_ACTIVE_INT_ENA + TOUCH_ACTIVE_INT interrupt enable bit + 2 + 1 + read-write + + + COCPU_SARADC1_INT_ENA + SARADC1_DONE_INT interrupt enable bit + 3 + 1 + read-write + + + COCPU_SARADC2_INT_ENA + SARADC2_DONE_INT interrupt enable bit + 4 + 1 + read-write + + + COCPU_TSENS_INT_ENA + TSENS_DONE_INT interrupt enable bit + 5 + 1 + read-write + + + COCPU_START_INT_ENA + RISCV_START_INT interrupt enable bit + 6 + 1 + read-write + + + COCPU_SW_INT_ENA + SW_INT interrupt enable bit + 7 + 1 + read-write + + + COCPU_SWD_INT_ENA + SWD_INT interrupt enable bit + 8 + 1 + read-write + + + + + SAR_COCPU_INT_ST + Interrupt status bit of ULP-RISCV + 0x130 + 0x20 + + + COCPU_TOUCH_DONE_INT_ST + TOUCH_DONE_INT interrupt status bit + 0 + 1 + read-only + + + COCPU_TOUCH_INACTIVE_INT_ST + TOUCH_INACTIVE_INT interrupt status bit + 1 + 1 + read-only + + + COCPU_TOUCH_ACTIVE_INT_ST + TOUCH_ACTIVE_INT interrupt status bit + 2 + 1 + read-only + + + COCPU_SARADC1_INT_ST + SARADC1_DONE_INT interrupt status bit + 3 + 1 + read-only + + + COCPU_SARADC2_INT_ST + SARADC2_DONE_INT interrupt status bit + 4 + 1 + read-only + + + COCPU_TSENS_INT_ST + TSENS_DONE_INT interrupt status bit + 5 + 1 + read-only + + + COCPU_START_INT_ST + RISCV_START_INT interrupt status bit + 6 + 1 + read-only + + + COCPU_SW_INT_ST + SW_INT interrupt status bit + 7 + 1 + read-only + + + COCPU_SWD_INT_ST + SWD_INT interrupt status bit + 8 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + Interrupt clear bit of ULP-RISCV + 0x134 + 0x20 + + + COCPU_TOUCH_DONE_INT_CLR + TOUCH_DONE_INT interrupt clear bit + 0 + 1 + write-only + + + COCPU_TOUCH_INACTIVE_INT_CLR + TOUCH_INACTIVE_INT interrupt clear bit + 1 + 1 + write-only + + + COCPU_TOUCH_ACTIVE_INT_CLR + TOUCH_ACTIVE_INT interrupt clear bit + 2 + 1 + write-only + + + COCPU_SARADC1_INT_CLR + SARADC1_DONE_INT interrupt clear bit + 3 + 1 + write-only + + + COCPU_SARADC2_INT_CLR + SARADC2_DONE_INT interrupt clear bit + 4 + 1 + write-only + + + COCPU_TSENS_INT_CLR + TSENS_DONE_INT interrupt clear bit + 5 + 1 + write-only + + + COCPU_START_INT_CLR + RISCV_START_INT interrupt clear bit + 6 + 1 + write-only + + + COCPU_SW_INT_CLR + SW_INT interrupt clear bit + 7 + 1 + write-only + + + COCPU_SWD_INT_CLR + SWD_INT interrupt clear bit + 8 + 1 + write-only + + + + + SAR_COCPU_DEBUG + ULP-RISCV debug register + 0x138 + 0x20 + + + COCPU_PC + ULP-RISCV Program counter + 0 + 13 + read-only + + + COCPU_MEM_VLD + ULP-RISCV memory valid output + 13 + 1 + read-only + + + COCPU_MEM_RDY + ULP-RISCV memory ready input + 14 + 1 + read-only + + + COCPU_MEM_WEN + ULP-RISCV memory write enable output + 15 + 4 + read-only + + + COCPU_MEM_ADDR + ULP-RISCV memory address output + 19 + 13 + read-only + + + + + SAR_HALL_CTRL + hall control + 0x13C + 0x20 + 0xA0000000 + + + XPD_HALL + Power on hall sensor and connect to VP and VN + 28 + 1 + read-write + + + XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 29 + 1 + read-write + + + HALL_PHASE + Reverse phase of hall sensor + 30 + 1 + read-write + + + HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_NOUSE + sar nouse + 0x140 + 0x20 + + + SAR_NOUSE + sar nouse + 0 + 32 + read-write + + + + + SAR_IO_MUX_CONF + Configure and reset IO MUX + 0x144 + 0x20 + + + IOMUX_RESET + Reset IO MUX by software + 30 + 1 + read-write + + + IOMUX_CLK_GATE_EN + IO MUX clock gate enable bit + 31 + 1 + read-write + + + + + SARDATE + Version Control Register + 0x148 + 0x20 + 0x01906140 + + + SAR_DATE + Version Control Register + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xF0 + registers + + + SHA + 55 + + + + MODE + Defines the algorithm of SHA accelerator + 0x0 + 0x20 + + + MODE + Defines the SHA algorithm. + 0 + 3 + read-write + + + + + T_STRING + String content register for calculating initial Hash Value (only effective for SHA-512/t) + 0x4 + 0x20 + + + T_STRING + Defines t_string for calculating the initial Hash value for SHA-512/t. + 0 + 32 + read-write + + + + + T_LENGTH + String length register for calculating initial Hash Value (only effective for SHA-512/t) + 0x8 + 0x20 + + + T_LENGTH + Defines t_length for calculating the initial Hash value for SHA-512/t. + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + Block number register (only effective for DMA-SHA) + 0xC + 0x20 + + + DMA_BLOCK_NUM + Defines the DMA-SHA block number. + 0 + 6 + read-write + + + + + START + Starts the SHA accelerator for Typical SHA operation + 0x10 + 0x20 + + + START + Write 1 to start Typical SHA calculation. + 0 + 1 + write-only + + + + + CONTINUE_OP + Continues SHA operation (only effective in Typical SHA mode) + 0x14 + 0x20 + + + CONTINUE_OP + Write 1 to continue Typical SHA calculation. + 0 + 1 + write-only + + + + + BUSY + Indicates if SHA Accelerator is busy or not + 0x18 + 0x20 + + + STATE + Indicates the states of SHA accelerator. +1'h0: idle +1'h1: busy + 0 + 1 + read-only + + + + + DMA_START + Starts the SHA accelerator for DMA-SHA operation + 0x1C + 0x20 + + + DMA_START + Write 1 to start DMA-SHA calculation. + 0 + 1 + write-only + + + + + DMA_CONTINUE + Continues SHA operation (only effective in DMA-SHA mode) + 0x20 + 0x20 + + + DMA_CONTINUE + Write 1 to continue DMA-SHA calculation. + 0 + 1 + write-only + + + + + INT_CLEAR + DMA-SHA interrupt clear register + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clears DMA-SHA interrupt. + 0 + 1 + write-only + + + + + INT_ENA + DMA-SHA interrupt enable register + 0x28 + 0x20 + + + INTERRUPT_ENA + Enables DMA-SHA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x2C + 0x20 + 0x20190402 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + 16 + 0x4 + H_%s + Hash value + 0x40 + 0x20 + + + H_0 + Stores the %sth 32-bit piece of the Hash value. + 0 + 32 + read-write + + + + + 32 + 0x4 + M_%s + Message + 0x80 + 0x20 + + + M_0 + Stores the %sth 32-bit piece of the message. + 0 + 32 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI + 0x3F403000 + + 0x0 + 0x108 + registers + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 23 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value + 0x4 + 0x20 + + + USR_ADDR_VALUE + [31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x002C0000 + + + EXT_HOLD_EN + Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state. + 2 + 1 + read-write + + + DUMMY_OUT + In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + FCMD_DUAL + Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 25 + 1 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 26 + 1 + read-write + + + + + CTRL1 + SPI control register 1 + 0xC + 0x20 + 0x00004010 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + W16_17_WR_ENA + 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state. + 4 + 1 + read-write + + + CS_HOLD_DELAY + SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state. + 14 + 6 + read-write + + + + + CTRL2 + SPI control register 2 + 0x10 + 0x20 + 0x00002000 + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state. + 0 + 13 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state. + 13 + 13 + read-write + + + CS_DELAY_MODE + spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state. + 26 + 3 + read-write + + + CS_DELAY_NUM + spi_cs signal is delayed by system clock cycles. Can be configured in CONF state. + 29 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0x14 + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 13 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x18 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + RD_BYTE_ORDER + In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state. + 10 + 1 + read-write + + + WR_BYTE_ORDER + In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state. + 11 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state. + 14 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + USR_HOLD_POL + It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_DOUT_HOLD + spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 18 + 1 + read-write + + + USR_DIN_HOLD + spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 19 + 1 + read-write + + + USR_DUMMY_HOLD + spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 20 + 1 + read-write + + + USR_ADDR_HOLD + spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 21 + 1 + read-write + + + USR_CMD_HOLD + spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 22 + 1 + read-write + + + USR_PREP_HOLD + spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + 23 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x1C + 0x20 + 0xB8000007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MOSI_DLEN + MOSI length + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 23 + read-write + + + + + MISO_DLEN + MISO length + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 23 + read-write + + + + + MISC + SPI misc register + 0x2C + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + CD_DATA_SET + 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. + 20 + 1 + read-write + + + CD_DUMMY_SET + 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. + 21 + 1 + read-write + + + CD_ADDR_SET + 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. + 22 + 1 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + CD_CMD_SET + 1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state. + 25 + 1 + read-write + + + CD_IDLE_EDGE + The default value of spi_cd. Can be configured in CONF state. + 26 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SLAVE + SPI slave control register + 0x30 + 0x20 + 0x00000200 + + + TRANS_DONE + The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf. + 4 + 1 + read-write + + + INT_RD_BUF_DONE_EN + SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + INT_WR_BUF_DONE_EN + SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + INT_RD_DMA_DONE_EN + SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + INT_WR_DMA_DONE_EN + SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + INT_TRANS_DONE_EN + SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + INT_DMA_SEG_TRANS_EN + SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + SEG_MAGIC_ERR_INT_EN + 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state. + 11 + 1 + read-write + + + TRANS_CNT + The operations counter in both the master mode and the slave mode. + 23 + 4 + read-only + + + TRANS_DONE_AUTO_CLR_EN + SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state. + 29 + 1 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 30 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0x34 + 0x20 + + + SLV_ADDR_ERR_CLR + 1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf. + 10 + 1 + read-write + + + SLV_CMD_ERR_CLR + 1: Clear SPI_SLV_CMD_ERR. 0: not valid. Can be changed by CONF_buf. + 11 + 1 + read-write + + + SLV_NO_QPI_EN + 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported. + 12 + 1 + read-write + + + SLV_ADDR_ERR + 1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received. + 13 + 1 + read-only + + + SLV_CMD_ERR + 1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received. + 14 + 1 + read-only + + + SLV_WR_DMA_DONE + The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf. + 15 + 1 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 16 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 24 + 8 + read-write + + + + + SLV_WRBUF_DLEN + SPI slave Wr_BUF interrupt and CONF control register + 0x38 + 0x20 + 0xD8000000 + + + SLV_WR_BUF_DONE + The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + CONF_BASE_BITLEN + The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0]. + 25 + 7 + read-write + + + + + SLV_RDBUF_DLEN + SPI magic error and slave control register + 0x3C + 0x20 + + + SLV_DMA_RD_BYTELEN + In the slave mode it is the length in bytes for read operations. The register value shall be byte_num. + 0 + 20 + read-write + + + SLV_RD_BUF_DONE + The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + SEG_MAGIC_ERR + 1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others. + 25 + 1 + read-write + + + + + SLV_RD_BYTE + SPI interrupt control register + 0x40 + 0x20 + 0x0A000000 + + + SLV_DATA_BYTELEN + The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits [23:20]. + 0 + 20 + read-write + + + SLV_RDDMA_BYTELEN_EN + 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 20 + 1 + read-write + + + SLV_WRDMA_BYTELEN_EN + 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 21 + 1 + read-write + + + SLV_RDBUF_BYTELEN_EN + 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 22 + 1 + read-write + + + SLV_WRBUF_BYTELEN_EN + 1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 23 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 24 + 4 + read-write + + + SLV_RD_DMA_DONE + The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf. + 30 + 1 + read-write + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 31 + 1 + read-write + + + + + FSM + SPI master status and DMA read byte control register + 0x44 + 0x20 + + + ST + The status of spi state machine. 0: idle state, 1: preparation state, 2: send command state, 3: send data state, 4: red data state, 5:write data state, 6: wait state, 7: done state. + 0 + 4 + read-only + + + MST_DMA_RD_BYTELEN + Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state.. + 12 + 20 + read-write + + + + + HOLD + SPI hold register + 0x48 + 0x20 + + + INT_HOLD_ENA + This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state. + 0 + 2 + read-write + + + VAL + spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state. + 2 + 1 + read-write + + + OUT_EN + Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state. + 3 + 1 + read-write + + + OUT_TIME + set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state. + 4 + 3 + read-write + + + DMA_SEG_TRANS_DONE + 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf. + 7 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x4C + 0x20 + 0x00000200 + + + IN_RST + The bit is used to reset in dma fsm and in data fifo pointer. + 2 + 1 + read-write + + + OUT_RST + The bit is used to reset out dma fsm and out data fifo pointer. + 3 + 1 + read-write + + + AHBM_FIFO_RST + Reset spi dma ahb master fifo pointer. + 4 + 1 + read-write + + + AHBM_RST + Reset spi dma ahb master. + 5 + 1 + read-write + + + IN_LOOP_TEST + Set bit to test in link. + 6 + 1 + read-write + + + OUT_LOOP_TEST + Set bit to test out link. + 7 + 1 + read-write + + + OUT_AUTO_WRBACK + when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0. + 8 + 1 + read-write + + + OUT_EOF_MODE + out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo. + 9 + 1 + read-write + + + OUTDSCR_BURST_EN + read descriptor use burst mode when read data for memory. + 10 + 1 + read-write + + + INDSCR_BURST_EN + read descriptor use burst mode when write data to memory. + 11 + 1 + read-write + + + OUT_DATA_BURST_EN + spi dma read data from memory in burst mode. + 12 + 1 + read-write + + + MEM_TRANS_EN + 1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function. + 13 + 1 + read-write + + + DMA_RX_STOP + spi dma read data stop when in continue tx/rx mode. + 14 + 1 + read-write + + + DMA_TX_STOP + spi dma write data stop when in continue tx/rx mode. + 15 + 1 + read-write + + + DMA_CONTINUE + spi dma continue tx/rx data. + 16 + 1 + read-write + + + SLV_LAST_SEG_POP_CLR + 1: Clear spi_slv_seg_frt_pop_mask. 0 : others + 17 + 1 + read-write + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE. + 20 + 1 + read-write + + + RX_EOF_EN + 1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN[19:0]/ SPI_MST_DMA_RD_BYTELEN[19:0] in spi dma transition. 0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans. + 21 + 1 + read-write + + + DMA_INFIFO_FULL_CLR + 1:Clear spi_dma_infifo_full_vld. 0: Do not control it. + 22 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_CLR + 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it. + 23 + 1 + read-write + + + EXT_MEM_BK_SIZE + Select the external memory block size. + 26 + 2 + read-write + + + DMA_SEG_TRANS_CLR + 1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX. 0: others. Will be cleared in 1 APB CLK cycles by hardware.. + 28 + 1 + read-write + + + + + DMA_OUT_LINK + SPI DMA TX link configuration + 0x50 + 0x20 + + + OUTLINK_ADDR + The address of the first outlink descriptor. + 0 + 20 + read-write + + + OUTLINK_STOP + Set the bit to stop to use outlink descriptor. + 28 + 1 + read-write + + + OUTLINK_START + Set the bit to start to use outlink descriptor. + 29 + 1 + read-write + + + OUTLINK_RESTART + Set the bit to mount on new outlink descriptors. + 30 + 1 + read-write + + + DMA_TX_ENA + spi dma write data status bit. + 31 + 1 + read-write + + + + + DMA_IN_LINK + SPI DMA RX link configuration + 0x54 + 0x20 + + + INLINK_ADDR + The address of the first inlink descriptor. + 0 + 20 + read-write + + + INLINK_AUTO_RET + when the bit is set, the inlink descriptor returns to the first link node when a packet is error. + 20 + 1 + read-write + + + INLINK_STOP + Set the bit to stop to use inlink descriptor. + 28 + 1 + read-write + + + INLINK_START + Set the bit to start to use inlink descriptor. + 29 + 1 + read-write + + + INLINK_RESTART + Set the bit to mount on new inlink descriptors. + 30 + 1 + read-write + + + DMA_RX_ENA + SPI DMA read data status bit. + 31 + 1 + read-write + + + + + DMA_INT_ENA + SPI DMA interrupt enable register + 0x58 + 0x20 + + + INLINK_DSCR_EMPTY_INT_ENA + The enable bit for lack of enough inlink descriptors. Can be configured in CONF state. + 0 + 1 + read-write + + + OUTLINK_DSCR_ERROR_INT_ENA + The enable bit for outlink descriptor error. Can be configured in CONF state. + 1 + 1 + read-write + + + INLINK_DSCR_ERROR_INT_ENA + The enable bit for inlink descriptor error. Can be configured in CONF state. + 2 + 1 + read-write + + + IN_DONE_INT_ENA + The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state. + 3 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + The enable bit for receiving error. Can be configured in CONF state. + 4 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + The enable bit for completing receiving all the packets from host. Can be configured in CONF state. + 5 + 1 + read-write + + + OUT_DONE_INT_ENA + The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state. + 6 + 1 + read-write + + + OUT_EOF_INT_ENA + The enable bit for sending a packet to host done. Can be configured in CONF state. + 7 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + The enable bit for sending all the packets to host done. Can be configured in CONF state. + 8 + 1 + read-write + + + INFIFO_FULL_ERR_INT_ENA + The enable bit for infifo full error interrupt. + 9 + 1 + read-write + + + OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for outfifo empty error interrupt. + 10 + 1 + read-write + + + SLV_CMD6_INT_ENA + The enable bit for SPI slave CMD6 interrupt. + 11 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 12 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 13 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 14 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 15 + 1 + read-write + + + + + DMA_INT_RAW + SPI DMA interrupt raw register + 0x5C + 0x20 + + + INLINK_DSCR_EMPTY_INT_RAW + The raw bit for lack of enough inlink descriptors. Can be configured in CONF state. + 0 + 1 + read-only + + + OUTLINK_DSCR_ERROR_INT_RAW + The raw bit for outlink descriptor error. Can be configured in CONF state. + 1 + 1 + read-only + + + INLINK_DSCR_ERROR_INT_RAW + The raw bit for inlink descriptor error. Can be configured in CONF state. + 2 + 1 + read-only + + + IN_DONE_INT_RAW + The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state. + 3 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + The raw bit for receiving error. Can be configured in CONF state. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + The raw bit for completing receiving all the packets from host. Can be configured in CONF state. + 5 + 1 + read-only + + + OUT_DONE_INT_RAW + The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state. + 6 + 1 + read-only + + + OUT_EOF_INT_RAW + The raw bit for sending a packet to host done. Can be configured in CONF state. + 7 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + The raw bit for sending all the packets to host done. Can be configured in CONF state. + 8 + 1 + read-only + + + INFIFO_FULL_ERR_INT_RAW + 1:SPI_DMA_INFIFO_FULL and spi_push_data_prep are valid, which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf. + 9 + 1 + read-only + + + OUTFIFO_EMPTY_ERR_INT_RAW + 1:SPI_DMA_OUTFIFO_EMPTY and spi_pop_data_prep are valid, which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf. + 10 + 1 + read-only + + + SLV_CMD6_INT_RAW + The raw bit for SPI slave CMD6 interrupt. + 11 + 1 + read-write + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. + 12 + 1 + read-write + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. + 13 + 1 + read-write + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. + 14 + 1 + read-write + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. + 15 + 1 + read-write + + + + + DMA_INT_ST + SPI DMA interrupt status register + 0x60 + 0x20 + + + INLINK_DSCR_EMPTY_INT_ST + The status bit for lack of enough inlink descriptors. + 0 + 1 + read-only + + + OUTLINK_DSCR_ERROR_INT_ST + The status bit for outlink descriptor error. + 1 + 1 + read-only + + + INLINK_DSCR_ERROR_INT_ST + The status bit for inlink descriptor error. + 2 + 1 + read-only + + + IN_DONE_INT_ST + The status bit for completing usage of a inlink descriptor. + 3 + 1 + read-only + + + IN_ERR_EOF_INT_ST + The status bit for receiving error. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_ST + The status bit for completing receiving all the packets from host. + 5 + 1 + read-only + + + OUT_DONE_INT_ST + The status bit for completing usage of a outlink descriptor. + 6 + 1 + read-only + + + OUT_EOF_INT_ST + The status bit for sending a packet to host done. + 7 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + The status bit for sending all the packets to host done. + 8 + 1 + read-only + + + INFIFO_FULL_ERR_INT_ST + The status bit for infifo full error. + 9 + 1 + read-only + + + OUTFIFO_EMPTY_ERR_INT_ST + The status bit for outfifo empty error. + 10 + 1 + read-only + + + SLV_CMD6_INT_ST + The status bit for SPI slave CMD6 interrupt. + 11 + 1 + read-write + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 12 + 1 + read-write + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 13 + 1 + read-write + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 14 + 1 + read-write + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 15 + 1 + read-write + + + + + DMA_INT_CLR + SPI DMA interrupt clear register + 0x64 + 0x20 + + + INLINK_DSCR_EMPTY_INT_CLR + The clear bit for lack of enough inlink descriptors. Can be configured in CONF state. + 0 + 1 + read-write + + + OUTLINK_DSCR_ERROR_INT_CLR + The clear bit for outlink descriptor error. Can be configured in CONF state. + 1 + 1 + read-write + + + INLINK_DSCR_ERROR_INT_CLR + The clear bit for inlink descriptor error. Can be configured in CONF state. + 2 + 1 + read-write + + + IN_DONE_INT_CLR + The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state. + 3 + 1 + read-write + + + IN_ERR_EOF_INT_CLR + The clear bit for receiving error. Can be configured in CONF state. + 4 + 1 + read-write + + + IN_SUC_EOF_INT_CLR + The clear bit for completing receiving all the packets from host. Can be configured in CONF state. + 5 + 1 + read-write + + + OUT_DONE_INT_CLR + The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state. + 6 + 1 + read-write + + + OUT_EOF_INT_CLR + The clear bit for sending a packet to host done. Can be configured in CONF state. + 7 + 1 + read-write + + + OUT_TOTAL_EOF_INT_CLR + The clear bit for sending all the packets to host done. Can be configured in CONF state. + 8 + 1 + read-write + + + INFIFO_FULL_ERR_INT_CLR + 1: Clear SPI_INFIFO_FULL_ERR_INT_RAW. 0: not valid. Can be changed by CONF_buf. + 9 + 1 + read-write + + + OUTFIFO_EMPTY_ERR_INT_CLR + 1: Clear SPI_OUTFIFO_EMPTY_ERR_INT_RAW signal. 0: not valid. Can be changed by CONF_buf. + 10 + 1 + read-write + + + SLV_CMD6_INT_CLR + The clear bit for SPI slave CMD6 interrupt. + 11 + 1 + read-write + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 12 + 1 + read-write + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 13 + 1 + read-write + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 14 + 1 + read-write + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 15 + 1 + read-write + + + + + IN_ERR_EOF_DES_ADDR + The latest SPI DMA RX descriptor address receiving error + 0x68 + 0x20 + + + DMA_IN_ERR_EOF_DES_ADDR + The inlink descriptor address when spi dma produce receiving error. + 0 + 32 + read-only + + + + + IN_SUC_EOF_DES_ADDR + The latest SPI DMA eof RX descriptor address + 0x6C + 0x20 + + + DMA_IN_SUC_EOF_DES_ADDR + The last inlink descriptor address when spi dma produce from_suc_eof. + 0 + 32 + read-only + + + + + INLINK_DSCR + Current SPI DMA RX descriptor pointer + 0x70 + 0x20 + + + DMA_INLINK_DSCR + The content of current in descriptor pointer. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF0 + Next SPI DMA RX descriptor pointer + 0x74 + 0x20 + + + DMA_INLINK_DSCR_BF0 + The content of next in descriptor pointer. + 0 + 32 + read-only + + + + + INLINK_DSCR_BF1 + Current SPI DMA RX buffer pointer + 0x78 + 0x20 + + + DMA_INLINK_DSCR_BF1 + The content of current in descriptor data buffer pointer. + 0 + 32 + read-only + + + + + OUT_EOF_BFR_DES_ADDR + The latest SPI DMA eof TX buffer address + 0x7C + 0x20 + + + DMA_OUT_EOF_BFR_DES_ADDR + The address of buffer relative to the outlink descriptor that produce eof. + 0 + 32 + read-only + + + + + OUT_EOF_DES_ADDR + The latest SPI DMA eof TX descriptor address + 0x80 + 0x20 + + + DMA_OUT_EOF_DES_ADDR + The last outlink descriptor address when spi dma produce to_eof. + 0 + 32 + read-only + + + + + OUTLINK_DSCR + Current SPI DMA TX descriptor pointer + 0x84 + 0x20 + + + DMA_OUTLINK_DSCR + The content of current out descriptor pointer. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF0 + Next SPI DMA TX descriptor pointer + 0x88 + 0x20 + + + DMA_OUTLINK_DSCR_BF0 + The content of next out descriptor pointer. + 0 + 32 + read-only + + + + + OUTLINK_DSCR_BF1 + Current SPI DMA TX buffer pointer + 0x8C + 0x20 + + + DMA_OUTLINK_DSCR_BF1 + The content of current out descriptor data buffer pointer. + 0 + 32 + read-only + + + + + DMA_OUTSTATUS + SPI DMA TX status + 0x90 + 0x20 + 0x80000000 + + + DMA_OUTDSCR_ADDR + SPI dma out descriptor address. + 0 + 18 + read-only + + + DMA_OUTDSCR_STATE + SPI dma out descriptor state. + 18 + 2 + read-only + + + DMA_OUT_STATE + SPI dma out data state. + 20 + 3 + read-only + + + DMA_OUTFIFO_CNT + The remains of SPI dma outfifo data. + 23 + 7 + read-only + + + DMA_OUTFIFO_FULL + SPI dma outfifo is full. + 30 + 1 + read-only + + + DMA_OUTFIFO_EMPTY + SPI dma outfifo is empty. + 31 + 1 + read-only + + + + + DMA_INSTATUS + SPI DMA RX status + 0x94 + 0x20 + 0x80000000 + + + DMA_INDSCR_ADDR + SPI dma in descriptor address. + 0 + 18 + read-only + + + DMA_INDSCR_STATE + SPI dma in descriptor state. + 18 + 2 + read-only + + + DMA_IN_STATE + SPI dma in data state. + 20 + 3 + read-only + + + DMA_INFIFO_CNT + The remains of SPI dma infifo data. + 23 + 7 + read-only + + + DMA_INFIFO_FULL + SPI dma infifo is full. + 30 + 1 + read-only + + + DMA_INFIFO_EMPTY + SPI dma infifo is empty. + 31 + 1 + read-only + + + + + W0 + Data buffer 0 + 0x98 + 0x20 + + + BUF0 + 32 bits data buffer 0, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W1 + Data buffer 1 + 0x9C + 0x20 + + + BUF1 + 32 bits data buffer 1, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W2 + Data buffer 2 + 0xA0 + 0x20 + + + BUF2 + 32 bits data buffer 2, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W3 + Data buffer 3 + 0xA4 + 0x20 + + + BUF3 + 32 bits data buffer 3, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W4 + Data buffer 4 + 0xA8 + 0x20 + + + BUF4 + 32 bits data buffer 4, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W5 + Data buffer 5 + 0xAC + 0x20 + + + BUF5 + 32 bits data buffer 5, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W6 + Data buffer 6 + 0xB0 + 0x20 + + + BUF6 + 32 bits data buffer 6, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W7 + Data buffer 7 + 0xB4 + 0x20 + + + BUF7 + 32 bits data buffer 7, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W8 + Data buffer 8 + 0xB8 + 0x20 + + + BUF8 + 32 bits data buffer 8, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W9 + Data buffer 9 + 0xBC + 0x20 + + + BUF9 + 32 bits data buffer 9, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W10 + Data buffer 10 + 0xC0 + 0x20 + + + BUF10 + 32 bits data buffer 10, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W11 + Data buffer 11 + 0xC4 + 0x20 + + + BUF11 + 32 bits data buffer 11, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W12 + Data buffer 12 + 0xC8 + 0x20 + + + BUF12 + 32 bits data buffer 12, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W13 + Data buffer 13 + 0xCC + 0x20 + + + BUF13 + 32 bits data buffer 13, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W14 + Data buffer 14 + 0xD0 + 0x20 + + + BUF14 + 32 bits data buffer 14, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W15 + Data buffer 15 + 0xD4 + 0x20 + + + BUF15 + 32 bits data buffer 15, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W16 + Data buffer 16 + 0xD8 + 0x20 + + + BUF16 + 32 bits data buffer 16, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + W17 + Data buffer 17 + 0xDC + 0x20 + + + BUF17 + 32 bits data buffer 17, transferred in the unit of byte. Byte addressable in slave half-duplex mode. + 0 + 32 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0xE0 + 0x20 + + + DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 3 + read-write + + + DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 3 + 3 + read-write + + + DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 3 + read-write + + + DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 9 + 3 + read-write + + + DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 3 + read-write + + + DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 15 + 3 + read-write + + + DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 18 + 3 + read-write + + + DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 21 + 3 + read-write + + + TIMING_CLK_ENA + 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state. + 24 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0xE4 + 0x20 + + + DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0xE8 + 0x20 + + + DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 0 + 3 + read-write + + + DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 3 + 3 + read-write + + + DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 6 + 3 + read-write + + + DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 9 + 3 + read-write + + + DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 12 + 3 + read-write + + + DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 15 + 3 + read-write + + + DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 18 + 3 + read-write + + + DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 21 + 3 + read-write + + + + + DOUT_NUM + SPI output delay number configuration + 0xEC + 0x20 + + + DOUT0_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DOUT1_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DOUT2_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DOUT3_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DOUT4_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DOUT5_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DOUT6_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DOUT7_NUM + the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + LCD_CTRL + LCD frame control register + 0xF0 + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. Can be configured in CONF state. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. Can be configured in CONF state. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. Can be configured in CONF state. + 21 + 10 + read-write + + + LCD_MODE_EN + 1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD frame control1 register + 0xF4 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. Can be configured in CONF state. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. Can be configured in CONF state. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. Can be configured in CONF state. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD frame control2 register + 0xF8 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of spi_vsync active pulse in a line. Can be configured in CONF state. + 0 + 7 + read-write + + + VSYNC_IDLE_POL + It is the idle value of spi_vsync. Can be configured in CONF state. + 7 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. + 16 + 7 + read-write + + + HSYNC_IDLE_POL + It is the idle value of spi_hsync. Can be configured in CONF state. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. + 24 + 8 + read-write + + + + + LCD_D_MODE + LCD delay number + 0xFC + 0x20 + + + D_DQS_MODE + the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 0 + 3 + read-write + + + D_CD_MODE + the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 3 + 3 + read-write + + + D_DE_MODE + the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 6 + 3 + read-write + + + D_HSYNC_MODE + the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 9 + 3 + read-write + + + D_VSYNC_MODE + the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state. + 12 + 3 + read-write + + + DE_IDLE_POL + It is the idle value of spi_de. + 15 + 1 + read-write + + + HS_BLANK_EN + 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans. + 16 + 1 + read-write + + + + + LCD_D_NUM + LCD delay mode + 0x100 + 0x20 + + + D_DQS_NUM + the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + D_CD_NUM + the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + D_DE_NUM + the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + D_HSYNC_NUM + the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + D_VSYNC_NUM + the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + + + REG_DATE + SPI version control + 0x3FC + 0x20 + 0x01907240 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + 0x3F402000 + + SPI1 + 32 + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + 0x3F424000 + + SPI2 + 33 + + + SPI2_DMA + 57 + + + + SPI3 + SPI (Serial Peripheral Interface) Controller + 0x3F425000 + + SPI3 + 34 + + + SPI3_DMA + 58 + + + + SPI4 + SPI (Serial Peripheral Interface) Controller + 0x3F437000 + + + SYSTEM + System + SYSTEM + 0x3F4C0000 + + 0x0 + 0x94 + registers + + + + ROM_CTRL_0 + System ROM configuration register 0 + 0x0 + 0x20 + 0x00000003 + + + ROM_FO + This field is used to force on clock gate of internal ROM. + 0 + 2 + read-write + + + + + ROM_CTRL_1 + System ROM configuration register 1 + 0x4 + 0x20 + 0x0000000C + + + ROM_FORCE_PD + This field is used to power down internal ROM. + 0 + 2 + read-write + + + ROM_FORCE_PU + This field is used to power up internal ROM. + 2 + 2 + read-write + + + + + SRAM_CTRL_0 + System SRAM configuration register 0 + 0x8 + 0x20 + 0x003FFFFF + + + SRAM_FO + This field is used to force on clock gate of internal SRAM. + 0 + 22 + read-write + + + + + SRAM_CTRL_1 + System SRAM configuration register 1 + 0xC + 0x20 + + + SRAM_FORCE_PD + This field is used to power down internal SRAM. + 0 + 22 + read-write + + + + + CPU_PERI_CLK_EN + CPU peripheral clock enable register + 0x10 + 0x20 + + + CLK_EN_DEDICATED_GPIO + Set this bit to enable clock of DEDICATED GPIO module. + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + CPU peripheral reset register + 0x14 + 0x20 + 0x00000080 + + + RST_EN_DEDICATED_GPIO + Set this bit to reset DEDICATED GPIO module. + 7 + 1 + read-write + + + + + CPU_PER_CONF + CPU peripheral clock configuration register + 0x18 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field is used to select the clock frequency of CPU or CPU period. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field is used to select the PLL clock frequency based on CPU period. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction. + 4 + 4 + read-write + + + + + JTAG_CTRL_0 + JTAG configuration register 0 + 0x1C + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 + Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_1 + JTAG configuration register 1 + 0x20 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 + Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_2 + JTAG configuration register 2 + 0x24 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 + Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_3 + JTAG configuration register 3 + 0x28 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 + Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_4 + JTAG configuration register 4 + 0x2C + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 + Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_5 + JTAG configuration register 5 + 0x30 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 + Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_6 + JTAG configuration register 6 + 0x34 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 + Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + JTAG_CTRL_7 + JTAG configuration register 7 + 0x38 + 0x20 + + + CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 + Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG. + 0 + 32 + write-only + + + + + MEM_PD_MASK + Memory power-related controlling register (under low-sleep) + 0x3C + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set this bit to allow the memory to work as usual when the chip enters the light-sleep state. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + System peripheral clock (for hardware accelerators) enable register + 0x40 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + Set this bit to enable clock of timers. + 0 + 1 + read-write + + + SPI01_CLK_EN + Set this bit to enable clock of SPI0 and SPI1. + 1 + 1 + read-write + + + UART_CLK_EN + Set this bit to enable clock of UART0. + 2 + 1 + read-write + + + WDG_CLK_EN + Set this bit to enable clock of WDG. + 3 + 1 + read-write + + + I2S0_CLK_EN + Set this bit to enable clock of I2S0. + 4 + 1 + read-write + + + UART1_CLK_EN + Set this bit to enable clock of UART1. + 5 + 1 + read-write + + + SPI2_CLK_EN + Set this bit to enable clock of SPI2. + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set this bit to enable clock of I2C EXT0. + 7 + 1 + read-write + + + UHCI0_CLK_EN + Set this bit to enable clock of UHCI0. + 8 + 1 + read-write + + + RMT_CLK_EN + Set this bit to enable clock of remote controller. + 9 + 1 + read-write + + + PCNT_CLK_EN + Set this bit to enable clock of pulse count. + 10 + 1 + read-write + + + LEDC_CLK_EN + Set this bit to enable clock of LED PWM. + 11 + 1 + read-write + + + UHCI1_CLK_EN + Set this bit to enable clock of UHCI1. + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set this bit to enable clock of timer group0. + 13 + 1 + read-write + + + EFUSE_CLK_EN + Set this bit to enable clock of eFuse. + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + Set this bit to enable clock of timer group1. + 15 + 1 + read-write + + + SPI3_CLK_EN + Set this bit to enable clock of SPI3. + 16 + 1 + read-write + + + PWM0_CLK_EN + Set this bit to enable clock of PWM0. + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + Set this bit to enable clock of I2C EXT1. + 18 + 1 + read-write + + + CAN_CLK_EN + Set this bit to enable clock of CAN. + 19 + 1 + read-write + + + PWM1_CLK_EN + Set this bit to enable clock of PWM1. + 20 + 1 + read-write + + + I2S1_CLK_EN + Set this bit to enable clock of I2S1. + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + Set this bit to enable clock of SPI2 DMA. + 22 + 1 + read-write + + + USB_CLK_EN + Set this bit to enable clock of USB. + 23 + 1 + read-write + + + UART_MEM_CLK_EN + Set this bit to enable clock of UART memory. + 24 + 1 + read-write + + + PWM2_CLK_EN + Set this bit to enable clock of PWM2. + 25 + 1 + read-write + + + PWM3_CLK_EN + Set this bit to enable clock of PWM3. + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + Set this bit to enable clock of SPI3 DMA. + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + Set this bit to enable clock of SAR ADC. + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set this bit to enable clock of system timer. + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set this bit to enable clock of aribiter of ADC2. + 30 + 1 + read-write + + + SPI4_CLK_EN + Set this bit to enable clock of SPI4. + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + System peripheral clock (for hardware accelerators) enable register 1 + 0x44 + 0x20 + + + CRYPTO_AES_CLK_EN + Set this bit to enable clock of cryptography AES. + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set this bit to enable clock of cryptography SHA. + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + Set this bit to enable clock of cryptography RSA. + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + Set this bit to enable clock of cryptography Digital Signature. + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + Set this bit to enable clock of cryptography HMAC. + 5 + 1 + read-write + + + CRYPTO_DMA_CLK_EN + Set this bit to enable clock of cryptography DMA. + 6 + 1 + read-write + + + + + PERIP_RST_EN0 + System peripheral (hardware accelerators) reset register 0 + 0x48 + 0x20 + + + TIMERS_RST + Set this bit to reset timers. + 0 + 1 + read-write + + + SPI01_RST + Set this bit to reset SPI0 and SPI1. + 1 + 1 + read-write + + + UART_RST + Set this bit to reset UART0. + 2 + 1 + read-write + + + WDG_RST + Set this bit to reset WDG. + 3 + 1 + read-write + + + I2S0_RST + Set this bit to reset I2S0. + 4 + 1 + read-write + + + UART1_RST + Set this bit to reset UART1. + 5 + 1 + read-write + + + SPI2_RST + Set this bit to reset SPI2. + 6 + 1 + read-write + + + I2C_EXT0_RST + Set this bit to reset I2C EXT0. + 7 + 1 + read-write + + + UHCI0_RST + Set this bit to reset UHCI0. + 8 + 1 + read-write + + + RMT_RST + Set this bit to reset remote controller. + 9 + 1 + read-write + + + PCNT_RST + Set this bit to reset pulse count. + 10 + 1 + read-write + + + LEDC_RST + Set this bit to reset LED PWM. + 11 + 1 + read-write + + + UHCI1_RST + Set this bit to reset UHCI1. + 12 + 1 + read-write + + + TIMERGROUP_RST + Set this bit to reset timer group0. + 13 + 1 + read-write + + + EFUSE_RST + Set this bit to reset eFuse. + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set this bit to reset timer group1. + 15 + 1 + read-write + + + SPI3_RST + Set this bit to reset SPI3. + 16 + 1 + read-write + + + PWM0_RST + Set this bit to reset PWM0. + 17 + 1 + read-write + + + I2C_EXT1_RST + Set this bit to reset I2C EXT1. + 18 + 1 + read-write + + + CAN_RST + Set this bit to reset CAN. + 19 + 1 + read-write + + + PWM1_RST + Set this bit to reset PWM1. + 20 + 1 + read-write + + + I2S1_RST + Set this bit to reset I2S1. + 21 + 1 + read-write + + + SPI2_DMA_RST + Set this bit to reset SPI2 DMA. + 22 + 1 + read-write + + + USB_RST + Set this bit to reset USB. + 23 + 1 + read-write + + + UART_MEM_RST + Set this bit to reset UART memory. + 24 + 1 + read-write + + + PWM2_RST + Set this bit to reset PWM2. + 25 + 1 + read-write + + + PWM3_RST + Set this bit to reset PWM3. + 26 + 1 + read-write + + + SPI3_DMA_RST + Set this bit to reset SPI3 DMA. + 27 + 1 + read-write + + + APB_SARADC_RST + Set this bit to reset SAR ADC. + 28 + 1 + read-write + + + SYSTIMER_RST + Set this bit to reset system timer. + 29 + 1 + read-write + + + ADC2_ARB_RST + Set this bit to reset aribiter of ADC2. + 30 + 1 + read-write + + + SPI4_RST + Set this bit to reset SPI4. + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + System peripheral (hardware accelerators) reset register 1 + 0x4C + 0x20 + 0x0000007E + + + CRYPTO_AES_RST + Set this bit to reset cryptography AES. + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set this bit to reset cryptography SHA. + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set this bit to reset cryptography RSA. + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set this bit to reset cryptography digital signature. + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set this bit to reset cryptography HMAC. + 5 + 1 + read-write + + + CRYPTO_DMA_RST + Set this bit to reset cryptography DMA. + 6 + 1 + read-write + + + + + LPCK_DIV_INT + Low power clock divider integer register + 0x50 + 0x20 + 0x000000FF + + + LPCK_DIV_NUM + This field is used to set the integer number of the divider value. + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + Divider fraction configuration register for low-power clock + 0x54 + 0x20 + 0x02000000 + + + LPCLK_SEL_RTC_SLOW + Set this bit to select RTC slow clock as the low power clock. + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set this bit to select 8m clock as the low power clock. + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set this bit to select xtal clock as the low power clock. + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set this bit to select xtal32k clock as the low power clock. + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set this bit to enable the RTC low power clock. + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + CPU interrupt controlling register 0 + 0x58 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process. + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + CPU interrupt controlling register 1 + 0x5C + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process. + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + CPU interrupt controlling register 2 + 0x60 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process. + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + CPU interrupt controlling register 3 + 0x64 + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process. + 0 + 1 + read-write + + + + + RSA_PD_CTRL + RSA memory remapping register + 0x68 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up RSA memory. This bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set this bit to force power down RSA memory. This bit has the highest priority. + 2 + 1 + read-write + + + + + BUSTOEXTMEM_ENA + EDMA enable register + 0x6C + 0x20 + 0x00000001 + + + BUSTOEXTMEM_ENA + Set this bit to enable bus to EDMA. + 0 + 1 + read-write + + + + + CACHE_CONTROL + Cache control register + 0x70 + 0x20 + 0x00000003 + + + PRO_ICACHE_CLK_ON + Set this bit to enable clock of i-cache. + 0 + 1 + read-write + + + PRO_DCACHE_CLK_ON + Set this bit to enable clock of d-cache. + 1 + 1 + read-write + + + PRO_CACHE_RESET + Set this bit to reset cache. + 2 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + External memory encrypt and decrypt controlling register + 0x74 + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set this bit to enable Manual Encryption under SPI Boot mode. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set this bit to enable Auto Encryption under Download Boot mode. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set this bit to enable Auto Decryption under Download Boot mode. + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set this bit to enable Manual Encryption under Download Boot mode. + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + RTC fast memory configuration register + 0x78 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set this bit to start the CRC of RTC memory. + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC. High level means finished while low level means not finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + RTC fast memory CRC controlling register + 0x7C + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + Redundant_ECO_Ctrl + Redundant ECO control register + 0x80 + 0x20 + + + REDUNDANT_ECO_DRIVE + The redundant ECO drive bit to avoid optimization in circuits. + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + The redundant ECO result bit to avoid optimization in circuits. + 1 + 1 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x84 + 0x20 + 0x00000001 + + + CLK_EN + Set this bit to enable clock of this module. + 0 + 1 + read-write + + + + + SRAM_CTRL_2 + System SRAM configuration register 2 + 0x88 + 0x20 + 0x003FFFFF + + + SRAM_FORCE_PU + This field is used to power up internal SRAM. + 0 + 22 + read-write + + + + + SYSCLK_CONF + SoC clock configuration register + 0x8C + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL\_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select SOC clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read XTAL frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + Not used, extends from ESP32. + 19 + 1 + read-only + + + + + DATE + Version control register + 0xFFC + 0x20 + 0x01908020 + + + DATE + Version control register. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x3F423000 + + 0x0 + 0x54 + registers + + + SYSTIMER_TARGET0 + 71 + + + SYSTIMER_TARGET1 + 72 + + + SYSTIMER_TARGET2 + 73 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + + + CLK_FO + System timer clock force enable. + 0 + 1 + read-write + + + CLK_EN + Register clock enable. + 31 + 1 + read-write + + + + + LOAD + Load value to system timer + 0x4 + 0x20 + + + TIMER_LOAD + Set this bit to 1, the value stored in SYSTIMER_TIMER_LOAD_HI and in +SYSTIMER_TIMER_LOAD_LO will be loaded to system timer + 31 + 1 + write-only + + + + + LOAD_HI + High 32 bits to be loaded to system timer + 0x8 + 0x20 + + + TIMER_LOAD_HI + The value to be loaded into system timer, high 32 bits. + 0 + 32 + read-write + + + + + LOAD_LO + Low 32 bits to be loaded to system timer + 0xC + 0x20 + + + TIMER_LOAD_LO + The value to be loaded into system timer, low 32 bits. + 0 + 32 + read-write + + + + + STEP + System timer accumulation step + 0x10 + 0x20 + 0x00000450 + + + TIMER_XTAL_STEP + Set system timer increment step when using XTAL_CLK. + 0 + 10 + read-write + + + TIMER_PLL_STEP + Set system timer increment step when using PLL_CLK + 10 + 10 + read-write + + + + + TARGET0_HI + System timer target 0, high 32 bits + 0x14 + 0x20 + + + TIMER_TARGET0_HI + System timer target 0, high 32 bits. + 0 + 32 + read-write + + + + + TARGET0_LO + System timer target 0, low 32 bits + 0x18 + 0x20 + + + TIMER_TARGET0_LO + System timer target 0, low 32 bits. + 0 + 32 + read-write + + + + + TARGET1_HI + System timer target 1, high 32 bits + 0x1C + 0x20 + + + TIMER_TARGET1_HI + System timer target 1, high 32 bits. + 0 + 32 + read-write + + + + + TARGET1_LO + System timer target 1, low 32 bits + 0x20 + 0x20 + + + TIMER_TARGET1_LO + System timer target 1, low 32 bits. + 0 + 32 + read-write + + + + + TARGET2_HI + System timer target 2, high 32 bits + 0x24 + 0x20 + + + TIMER_TARGET2_HI + System timer target 2, high 32 bits. + 0 + 32 + read-write + + + + + TARGET2_LO + System timer target 2, low 32 bits + 0x28 + 0x20 + + + TIMER_TARGET2_LO + System timer target 2, low 32 bits. + 0 + 32 + read-write + + + + + TARGET0_CONF + Configure work mode for system timer target 0 + 0x2C + 0x20 + + + TARGET0_PERIOD + Set alarm period for system timer target 0, only valid in periodic +alarms mode. + 0 + 30 + read-write + + + TARGET0_PERIOD_MODE + Set work mode for system timer target 0. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. + 30 + 1 + read-write + + + TARGET0_WORK_EN + System timer target 0 work enable. + 31 + 1 + read-write + + + + + TARGET1_CONF + Configure work mode for system timer target 1 + 0x30 + 0x20 + + + TARGET1_PERIOD + Set alarm period for system timer target 1, only valid in periodic +alarms mode. + 0 + 30 + read-write + + + TARGET1_PERIOD_MODE + Set work mode for system timer target 1. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. + 30 + 1 + read-write + + + TARGET1_WORK_EN + System timer target 1 work enable. + 31 + 1 + read-write + + + + + TARGET2_CONF + Configure work mode for system timer target 2 + 0x34 + 0x20 + + + TARGET2_PERIOD + Set alarm period for system timer target 2, only valid in periodic +alarms mode. + 0 + 30 + read-write + + + TARGET2_PERIOD_MODE + Set work mode for system timer target 2. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode. + 30 + 1 + read-write + + + TARGET2_WORK_EN + System timer target 2 work enable. + 31 + 1 + read-write + + + + + UNIT0_OP + Read out system timer value + 0x38 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + Check if it is valid to read out timer value from registers. 0: Not +ready to read timer value from registers; 1: Ready to read timer value from registers + 30 + 1 + read-only + + + TIMER_UNIT0_UPDATE + Update system timer value to registers. + 31 + 1 + write-only + + + + + UNIT0_VALUE_HI + System timer value, high 32 bits + 0x3C + 0x20 + + + TIMER_VALUE_HI + System timer value, high 32 bits. + 0 + 32 + read-only + + + + + UNIT0_VALUE_LO + System timer value, low 32 bits + 0x40 + 0x20 + + + TIMER_VALUE_LO + System timer value, low 32 bits. + 0 + 32 + read-only + + + + + INT_ENA + System timer interrupt enable + 0x44 + 0x20 + + + TARGET0_INT_ENA + Interrupt enable bit of system timer target 0. + 0 + 1 + read-write + + + TARGET1_INT_ENA + Interrupt enable bit of system timer target 1. + 1 + 1 + read-write + + + TARGET2_INT_ENA + Interrupt enable bit of system timer target 2. + 2 + 1 + read-write + + + + + INT_RAW + System timer interrupt raw + 0x48 + 0x20 + + + INT0_RAW + Interrupt raw bit of system timer target 0. + 0 + 1 + read-only + + + INT1_RAW + Interrupt raw bit of system timer target 1. + 1 + 1 + read-only + + + INT2_RAW + Interrupt raw bit of system timer target 2. + 2 + 1 + read-only + + + + + INT_CLR + System timer interrupt clear + 0x4C + 0x20 + + + TARGET0_INT_CLR + Interrupt clear bit of system timer target 0. + 0 + 1 + write-only + + + TARGET1_INT_CLR + Interrupt clear bit of system timer target 1. + 1 + 1 + write-only + + + TARGET2_INT_CLR + Interrupt clear bit of system timer target 2. + 2 + 1 + write-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x01807160 + + + DATE + Version control register + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x3F41F000 + + 0x0 + 0xB4 + registers + + + TG0_T0_LEVEL + 15 + + + TG0_T1_LEVEL + 16 + + + TG0_WDT_LEVEL + 17 + + + TG0_LACT_LEVEL + 18 + + + TG0_T0_EDGE + 62 + + + TG0_T1_EDGE + 63 + + + TG0_WDT_EDGE + 64 + + + TG0_LACT_EDGE + 65 + + + + 2 + 0x24 + T%sCONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. + 10 + 1 + read-write + + + LEVEL_INT_EN + When set, an alarm will generate a level type interrupt. + 11 + 1 + read-write + + + EDGE_INT_EN + When set, an alarm will generate an edge type interrupt. + 12 + 1 + read-write + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sLO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sHI + Timer %s current value, high 32 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 32 bits of the time-base counter of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sUPDATE + Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + +Timer %s alarm trigger time-base counter value, high 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADHI + Timer %s reload value, high 32 bits + 0x1C + 0x20 + + + LOAD_HI + High 32 bits of the value that a reload will load onto timer %s time-base counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOAD + Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG + 0x20 + 0x20 + + + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + Reserved. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us. + 18 + 3 + read-write + + + WDT_LEVEL_INT_EN + When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt. + 21 + 1 + read-write + + + WDT_EDGE_INT_EN + When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt. + 22 + 1 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configuration register + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + When set, periodic calibration is enabled. + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + Used to select the clock to be calibrated. 0: RTC_CLK. 1: RTC20M_D256_CLK. 2: XTAL32K_CLK. + 13 + 2 + read-write + + + RTC_CALI_RDY + Set this bit to mark the completion of calibration. + 15 + 1 + read-only + + + RTC_CALI_MAX + Calibration time, in cycles of the clock to be calibrated. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to starts calibration. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configuration register 1 + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + Periodic calibration valid signal. + 0 + 1 + read-only + + + RTC_CALI_VALUE + Calibration value when cycles of clock to be calibrated reach TIMG_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles. + 7 + 25 + read-only + + + + + LACTCONFIG + LACT configuration register + 0x70 + 0x20 + 0x60002300 + + + LACT_USE_REFTICK + Reserved. + 6 + 1 + read-write + + + LACT_RTC_ONLY + Reserved. + 7 + 1 + read-write + + + LACT_CPST_EN + Reserved. + 8 + 1 + read-write + + + LACT_LAC_EN + Reserved. + 9 + 1 + read-write + + + LACT_ALARM_EN + Reserved. + 10 + 1 + read-write + + + LACT_LEVEL_INT_EN + Reserved. + 11 + 1 + read-write + + + LACT_EDGE_INT_EN + Reserved. + 12 + 1 + read-write + + + LACT_DIVIDER + Reserved. + 13 + 16 + read-write + + + LACT_AUTORELOAD + Reserved. + 29 + 1 + read-write + + + LACT_INCREASE + Reserved. + 30 + 1 + read-write + + + LACT_EN + Reserved. + 31 + 1 + read-write + + + + + LACTRTC + LACT RTC register + 0x74 + 0x20 + + + LACT_RTC_STEP_LEN + Reserved. + 6 + 26 + read-write + + + + + LACTLO + LACT low register + 0x78 + 0x20 + + + LACT_LO + Reserved. + 0 + 32 + read-only + + + + + LACTHI + LACT high register + 0x7C + 0x20 + + + LACT_HI + Reserved. + 0 + 32 + read-only + + + + + LACTUPDATE + LACT update register + 0x80 + 0x20 + + + LACT_UPDATE + Reserved. + 0 + 32 + write-only + + + + + LACTALARMLO + LACT alarm low register + 0x84 + 0x20 + + + LACT_ALARM_LO + Reserved. + 0 + 32 + read-write + + + + + LACTALARMHI + LACT alarm high register + 0x88 + 0x20 + + + LACT_ALARM_HI + Reserved. + 0 + 32 + read-write + + + + + LACTLOADLO + LACT load low register + 0x8C + 0x20 + + + LACT_LOAD_LO + Reserved. + 0 + 32 + read-write + + + + + LACTLOADHI + Timer LACT load high register + 0x90 + 0x20 + + + LACT_LOAD_HI + Reserved. + 0 + 32 + read-write + + + + + LACTLOAD + Timer LACT load register + 0x94 + 0x20 + + + LACT_LOAD + Reserved. + 0 + 32 + write-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x98 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + LACT_INT_ENA + The interrupt enable bit for the TIMG_LACT_INT interrupt. + 3 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x9C + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + LACT_INT_RAW + The raw interrupt status bit for the TIMG_LACT_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0xA0 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + LACT_INT_ST + The masked interrupt status bit for the TIMG_LACT_INT interrupt. + 3 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0xA4 + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + LACT_INT_CLR + Set this bit to clear the TIMG_LACT_INT interrupt. + 3 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0xA8 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + TIMERS_DATE + Version control register + 0xF8 + 0x20 + 0x01907261 + + + TIMERS_DATE + Version control register. + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x3F420000 + + TG1_T0_LEVEL + 19 + + + TG1_T1_LEVEL + 20 + + + TG1_WDT_LEVEL + 21 + + + TG1_LACT_LEVEL + 22 + + + TG1_T0_EDGE + 66 + + + TG1_T1_EDGE + 67 + + + TG1_WDT_EDGE + 68 + + + TG1_LACT_EDGE + 69 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x3F42B000 + + 0x0 + 0x6C + registers + + + TWAI + 47 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + read-write + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + read-write + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + read-write + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + read-write + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + read-write + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x3F400000 + + 0x0 + 0x7C + registers + + + UART0 + 37 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a data frame error. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when the receiver receives more data than the capacity of RX FIFO. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when the receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when the receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when the receiver takes more time than UART_RX_TOUT_THRHD to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when the receiver receives an XON character and UART_SW_FLOW_CON_EN is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when the receiver receives an XOFF character and UART_SW_FLOW_CON_EN is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when the transmitter completes sending NULL characters, after all data in TX FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when the transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when the transmitter has sent out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a parity error from the echo of the transmitter in RS485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when the receiver detects a data frame error from the echo of the transmitter in RS485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when a collision is detected between the transmitter and the receiver in RS485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when the receiver detects the configured UART_AT_CMD CHAR. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input RXD edge changes more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for UART_RXFIFO_FULL_INT when UART_RXFIFO_FULL_INT_ENA is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for UART_TXFIFO_EMPTY_INT when UART_TXFIFO_EMPTY_INT_ENA is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for UART_PARITY_ERR_INT when UART_PARITY_ERR_INT_ENA is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for UART_FRM_ERR_INT when UART_FRM_ERR_INT_ENA is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for UART_RXFIFO_OVF_INT when UART_RXFIFO_OVF_INT_ENA is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for UART_DSR_CHG_INT when UART_DSR_CHG_INT_ENA is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for UART_CTS_CHG_INT when UART_CTS_CHG_INT_ENA is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for UART_BRK_DET_INT when UART_BRK_DET_INT_ENA is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for UART_RXFIFO_TOUT_INT when UART_RXFIFO_TOUT_INT_ENA is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for UART_SW_XON_INT when UART_SW_XON_INT_ENA is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for UART_SW_XOFF_INT when UART_SW_XOFF_INT_ENA is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for UART_GLITCH_DET_INT when UART_GLITCH_DET_INT_ENA is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for UART_TX_BRK_DONE_INT when UART_TX_BRK_DONE_INT_ENA is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the status bit for UART_TX_BRK_IDLE_DONE_INT when UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for UART_TX_DONE_INT when UART_TX_DONE_INT_ENA is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for UART_RS485_PARITY_ERR_INT when UART_RS485_PARITY_INT_ENA is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for UART_RS485_FRM_ERR_INT when UART_RS485_FRM_ERR_INT_ENA is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for UART_RS485_CLASH_INT when UART_RS485_CLASH_INT_ENA is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for UART_AT_CMD_CHAR_DET_INT when UART_AT_CMD_CHAR_DET_INT_ENA is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for UART_WAKEUP_INT when UART_WAKEUP_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for UART_RXFIFO_FULL_INT. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for UART_TXFIFO_EMPTY_INT. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for UART_PARITY_ERR_INT. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for UART_FRM_ERR_INT. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for UART_RXFIFO_OVF_INT. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for UART_DSR_CHG_INT. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for UART_CTS_CHG_INT. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for UART_BRK_DET_INT. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for UART_RXFIFO_TOUT_INT. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for UART_SW_XON_INT. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for UART_SW_XOFF_INT. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for UART_GLITCH_DET_INT. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for UART_TX_BRK_DONE_INT. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for UART_TX_BRK_IDLE_DONE_INT. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for UART_TX_DONE_INT. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for UART_RS485_PARITY_ERR_INT. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for UART_RS485_PARITY_ERR_INT. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for UART_RS485_CLASH_INT. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for UART_AT_CMD_CHAR_DET_INT. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for UART_WAKEUP_INT. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear UART_PARITY_ERR_INT interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear UART_FRM_ERR_INT interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear UART_DSR_CHG_INT interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear UART_CTS_CHG_INT interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear UART_BRK_DET_INT interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear UART_RXFIFO_TOUT_INT interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear UART_SW_XON_INT interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear UART_SW_XOFF_INT interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear UART_GLITCH_DET_INT interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear UART_TX_BRK_DONE_INT interrupt. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear UART_TX_DONE_INT interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear UART_RS485_FRM_ERR_INT interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear UART_RS485_CLASH_INT interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear UART_WAKEUP_INT interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divisor. + 0 + 20 + read-write + + + FRAG + The fractional part of the frequency divisor. + 20 + 4 + read-write + + + + + AUTOBAUD + Autobaud configuration register + 0x18 + 0x20 + 0x00001000 + + + EN + This is the enable bit for baud rate detection. + 0 + 1 + read-write + + + GLITCH_FILT + When input pulse width is lower than this value, the pulse is ignored. +This register is used in autobaud detection. + 8 + 8 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + + + RXFIFO_CNT + Stores the number of valid data bytes in RX FIFO. + 0 + 10 + read-only + + + DSRN + This register represents the level of the internal UART DSR signal. + 13 + 1 + read-only + + + CTSN + This register represents the level of the internal UART CTS signal. + 14 + 1 + read-only + + + RXD + This register represents the level of the internal UART RXD signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the number of data bytes in TX FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal UART DTR signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal UART RTS signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal UART TXD signal. + 31 + 1 + read-only + + + + + CONF0 + Configuration register 0 + 0x20 + 0x20 + 0x1800001C + + + PARITY + This register is used to configure the parity check mode. +0: even. 1: odd. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable UART parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. +0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. +1: 1 bit. 2: 1.5 bits. 3: 2 bits. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software RTS signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software DTR signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enable the transmitter to send NULL characters when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1: The IrDA transmitter's 11th bit is the same as 10th bit. 0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable UART loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for the transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the UART RX FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the UART TX FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to invert the level of UART RXD signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to invert the level of UART CTS signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to invert the level of UART DSR signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to invert the level of UART TXD signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to invert the level of UART RTS signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to invert the level of UART DTR signal. + 24 + 1 + read-write + + + CLK_EN + 1: Force clock on for registers. 0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + TICK_REF_ALWAYS_ON + This register is used to select the clock. +1: APB_CLK. +0: REF_TICK. + 27 + 1 + read-write + + + MEM_CLK_EN + The signal to enable UART RAM clock gating. +1: UART RAM powers on, the data of which can be read and written. +0: UART RAM powers down. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x0000C060 + + + RXFIFO_FULL_THRHD + An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value. + 0 + 9 + read-write + + + TXFIFO_EMPTY_THRHD + An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register's value. + 9 + 9 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 29 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. +1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control. + 30 + 1 + read-write + + + RX_TOUT_EN + This is the enable bit for UART receiver's timeout function. + 31 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x000FFFFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate detection. + 0 + 20 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x000FFFFF + + + MIN_CNT + This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate detection. + 0 + 20 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of RXD edge change. It is used in baud rate detection. As baud rate registers UART_REG_LOWPULSE_MIN_CNT, UART_REG_HIGHPULSE_MIN_CNT, UART_REG_POSEDGE_MIN_CNT, and UART_REG_NEGEDGE_MIN_CNT always record the minimal value, UART_REG_RXD_EDGE_CNT indicates the statistic number of RXD edge to find out the minimal value for these baud rate registers. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control characters from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to force the transmitter to send data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send an XON character. This bit is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send an XOFF character. This bit is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow control character configuration + 0x3C + 0x20 + 0x000026E0 + + + XOFF_THRESHOLD + When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character. + 0 + 9 + read-write + + + XOFF_CHAR + This register stores the XOFF flow control character. + 9 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00002200 + + + XON_THRESHOLD + When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character. + 0 + 9 + read-write + + + XON_CHAR + This register stores the XON flow control character. + 9 + 8 + read-write + + + + + IDLE_CONF + Frame end idle time configuration + 0x44 + 0x20 + 0x00A40100 + + + RX_IDLE_THRHD + A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit). + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit). + 10 + 10 + read-write + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1. + 20 + 8 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x48 + 0x20 + + + RS485_EN + Set this bit to choose RS485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable the receiver could receive data when the transmitter is transmitting data in RS485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1: enable RS485 transmitter to send data when RS485 receiver line is busy. +0: RS485 transmitter should not send data when its receiver is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x4C + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first AT_CMD is received by the receiver. +It will not take the next data received as AT_CMD character when the duration is less than this register's value. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last AT_CMD and the next data. +It will not take the previous data as AT_CMD character when the duration is less than this register's value. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x54 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the AT_CMD characters. +It will not take the data as continuous AT_CMD characters when the duration time is less than this register's value. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence selection configuration + 0x58 + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of AT_CMD character. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the number of continuous AT_CMD characters received by the receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x5C + 0x20 + 0x000A0012 + + + RX_SIZE + This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works. + 7 + 9 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit). +The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1. + 16 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART RAM. + 26 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART RAM. + 27 + 1 + read-write + + + + + MEM_TX_STATUS + TX FIFO write and read offset address + 0x60 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in TX FIFO when software writes TX FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in TX FIFO when TX FSM reads data via Tx_FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + RX FIFO write and read offset address + 0x64 + 0x20 + + + APB_RX_RADDR + This register stores the offset address in RX_FIFO when software reads data from RX FIFO via APB. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl writes RX FIFO. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmitter and receiver status + 0x68 + 0x20 + + + ST_URX_OUT + This is the status register of the receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of the transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x6C + 0x20 + 0x000FFFFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in baud rate detection. + 0 + 20 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x70 + 0x20 + 0x000FFFFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in baud rate detection. + 0 + 20 + read-only + + + + + DATE + UART version control register + 0x74 + 0x20 + 0x18082800 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x78 + 0x20 + 0x00000500 + + + ID + This register is used to configure the UART_ID. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x3F410000 + + UART1 + 38 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x3F414000 + + 0x0 + 0xBC + registers + + + UHCI0 + 13 + + + + CONF0 + UHCI configuration register + 0x0 + 0x20 + 0x00370100 + + + IN_RST + Set this bit to reset in DMA FSM. + 0 + 1 + read-write + + + OUT_RST + Set this bit to reset out DMA FSM. + 1 + 1 + read-write + + + AHBM_FIFO_RST + Set this bit to reset AHB interface cmdFIFO of DMA. + 2 + 1 + read-write + + + AHBM_RST + Set this bit to reset AHB interface of DMA. + 3 + 1 + read-write + + + IN_LOOP_TEST + Reserved. + 4 + 1 + read-write + + + OUT_LOOP_TEST + Reserved. + 5 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted. + 6 + 1 + read-write + + + OUT_NO_RESTART_CLR + Reserved. + 7 + 1 + read-write + + + OUT_EOF_MODE + This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. +1: When DMA has popped all data from FIFO. +0: When AHB has pushed all data to FIFO. + 8 + 1 + read-write + + + UART0_CE + Set this bit to link up UHCI and UART0. + 9 + 1 + read-write + + + UART1_CE + Set this bit to link up UHCI and UART1. + 10 + 1 + read-write + + + OUTDSCR_BURST_EN + This register is used to specify DMA transmit descriptor transfer mode. +1: burst mode. +0: byte mode. + 12 + 1 + read-write + + + INDSCR_BURST_EN + This register is used to specify DMA receive descriptor transfer mode. +1: burst mode. +0: byte mode. + 13 + 1 + read-write + + + MEM_TRANS_EN + 1: UHCI transmitted data would be write back into DMA INFIFO. + 15 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special character. + 16 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 17 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 18 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 19 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. +The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. +If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0. + 20 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload. + 21 + 1 + read-write + + + CLK_EN + 1: Force clock on for registers. 0: Support clock only when application writes registers. + 22 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART. + 23 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + + + RX_START_INT_RAW + This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent. + 0 + 1 + read-only + + + TX_START_INT_RAW + This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator. + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value. + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value. + 3 + 1 + read-only + + + IN_DONE_INT_RAW + This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_RAW + This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully. + 5 + 1 + read-only + + + IN_ERR_EOF_INT_RAW + This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor. + 6 + 1 + read-only + + + OUT_DONE_INT_RAW + This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed. + 7 + 1 + read-only + + + OUT_EOF_INT_RAW + This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1. + 8 + 1 + read-only + + + IN_DSCR_ERR_INT_RAW + This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor. + 9 + 1 + read-only + + + OUT_DSCR_ERR_INT_RAW + This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor. + 10 + 1 + read-only + + + IN_DSCR_EMPTY_INT_RAW + This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA. + 11 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_RAW + This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor. + 12 + 1 + read-only + + + OUT_TOTAL_EOF_INT_RAW + This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out. + 13 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode. + 14 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode. + 15 + 1 + read-only + + + DMA_INFIFO_FULL_WM_INT_RAW + This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value. + 16 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RX_START_INT_ST + This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + 0 + 1 + read-only + + + TX_START_INT_ST + This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + 3 + 1 + read-only + + + IN_DONE_INT_ST + This is the masked interrupt bit for UHCI_IN_DONE_INT interrupt when UHCI_IN_DONE_INT_ENA is set to 1. + 4 + 1 + read-only + + + IN_SUC_EOF_INT_ST + This is the masked interrupt bit for UHCI_IN_SUC_EOF_INT interrupt when UHCI_IN_SUC_EOF_INT_ENA is set to 1. + 5 + 1 + read-only + + + IN_ERR_EOF_INT_ST + This is the masked interrupt bit for UHCI_IN_ERR_EOF_INT interrupt when UHCI_IN_ERR_EOF_INT_ENA is set to 1. + 6 + 1 + read-only + + + OUT_DONE_INT_ST + This is the masked interrupt bit for UHCI_OUT_DONE_INT interrupt when UHCI_OUT_DONE_INT_ENA is set to 1. + 7 + 1 + read-only + + + OUT_EOF_INT_ST + This is the masked interrupt bit for UHCI_OUT_EOF_INT interrupt when UHCI_OUT_EOF_INT_ENA is set to 1. + 8 + 1 + read-only + + + IN_DSCR_ERR_INT_ST + This is the masked interrupt bit for UHCI_IN_DSCR_ERR_INT interrupt when UHCI_IN_DSCR_ERR_INT is set to 1. + 9 + 1 + read-only + + + OUT_DSCR_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUT_DSCR_ERR_INT interrupt when UHCI_OUT_DSCR_ERR_INT_ENA is set to 1. + 10 + 1 + read-only + + + IN_DSCR_EMPTY_INT_ST + This is the masked interrupt bit for UHCI_IN_DSCR_EMPTY_INT interrupt when UHCI_IN_DSCR_EMPTY_INT_ENA is set to 1. + 11 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + 12 + 1 + read-only + + + OUT_TOTAL_EOF_INT_ST + This is the masked interrupt bit for UHCI_OUT_TOTAL_EOF_INT interrupt when UHCI_OUT_TOTAL_EOF_INT_ENA is set to 1. + 13 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_S_REG_Q_INT interrupt when UHCI_SEND_S_REG_Q_INT_ENA is set to 1. + 14 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_A_REG_Q_INT interrupt when UHCI_SEND_A_REG_Q_INT_ENA is set to 1. + 15 + 1 + read-only + + + DMA_INFIFO_FULL_WM_INT_ST + This is the masked interrupt bit for UHCI_DMA_INFIFO_FULL_WM_INT INTERRUPT when UHCI_DMA_INFIFO_FULL_WM_INT_ENA is set to 1. + 16 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RX_START_INT_ENA + This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + 0 + 1 + read-write + + + TX_START_INT_ENA + This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + 3 + 1 + read-write + + + IN_DONE_INT_ENA + This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt. + 4 + 1 + read-write + + + IN_SUC_EOF_INT_ENA + This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt. + 5 + 1 + read-write + + + IN_ERR_EOF_INT_ENA + This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt. + 6 + 1 + read-write + + + OUT_DONE_INT_ENA + This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt. + 7 + 1 + read-write + + + OUT_EOF_INT_ENA + This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_ERR_INT_ENA + This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt. + 9 + 1 + read-write + + + OUT_DSCR_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt. + 10 + 1 + read-write + + + IN_DSCR_EMPTY_INT_ENA + This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt. + 11 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + 12 + 1 + read-write + + + OUT_TOTAL_EOF_INT_ENA + This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt. + 13 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt. + 14 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt. + 15 + 1 + read-write + + + DMA_INFIFO_FULL_WM_INT_ENA + This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. + 16 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear UHCI_RX_START_INT interrupt. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear UHCI_TX_START_INT interrupt. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear UHCI_RX_HUNG_INT interrupt. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear UHCI_TX_HUNG_INT interrupt. + 3 + 1 + write-only + + + IN_DONE_INT_CLR + Set this bit to clear UHCI_IN_DONE_INT interrupt. + 4 + 1 + write-only + + + IN_SUC_EOF_INT_CLR + Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt. + 5 + 1 + write-only + + + IN_ERR_EOF_INT_CLR + Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt. + 6 + 1 + write-only + + + OUT_DONE_INT_CLR + Set this bit to clear UHCI_OUT_DONE_INT interrupt. + 7 + 1 + write-only + + + OUT_EOF_INT_CLR + Set this bit to clear UHCI_OUT_EOF_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_ERR_INT_CLR + Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt. + 9 + 1 + write-only + + + OUT_DSCR_ERR_INT_CLR + Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt. + 10 + 1 + write-only + + + IN_DSCR_EMPTY_INT_CLR + Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt. + 11 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + 12 + 1 + write-only + + + OUT_TOTAL_EOF_INT_CLR + Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt. + 13 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt. + 14 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt. + 15 + 1 + write-only + + + DMA_INFIFO_FULL_WM_INT_CLR + Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt. + 16 + 1 + write-only + + + + + DMA_OUT_STATUS + DMA data-output status register + 0x14 + 0x20 + 0x00000002 + + + OUT_FULL + 1: DMA TX FIFO is full. + 0 + 1 + read-only + + + OUT_EMPTY + 1: DMA TX FIFO is empty. + 1 + 1 + read-only + + + + + DMA_OUT_PUSH + Push control register of TX FIFO + 0x18 + 0x20 + + + OUTFIFO_WDATA + This is the data that need to be pushed into TX FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into TX FIFO. + 16 + 1 + read-write + + + + + DMA_IN_STATUS + UHCI data-input status register + 0x1C + 0x20 + 0x00000002 + + + IN_FULL + Data-input FIFO full signal. + 0 + 1 + read-only + + + IN_EMPTY + Data-input FIFO empty signal. + 1 + 1 + read-only + + + RX_ERR_CAUSE + This register indicates the error type when DMA has received a packet with error. +3'b001: Checksum error in the HCI packet; +3'b010: Sequence number error in the HCI packet; +3'b011: CRC bit error in the HCI packet; +3'b100: 0xC0 is found but the received HCI packet is not end; +3'b101: 0xC0 is not found when the HCI packet has been received; +3'b110: CRC check error. + 4 + 3 + read-only + + + + + DMA_IN_POP + Pop control register of RX FIFO + 0x20 + 0x20 + + + INFIFO_RDATA + This register stores the data popping from RX FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from RX FIFO. + 16 + 1 + read-write + + + + + DMA_OUT_LINK + Link descriptor address and control + 0x24 + 0x20 + + + OUTLINK_ADDR + This register is used to specify the least significant 20 bits of the first transmit descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the transmit descriptor. + 28 + 1 + read-write + + + OUTLINK_START + Set this bit to start a new transmit descriptor. + 29 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart the transmit descriptor from the last address. + 30 + 1 + read-write + + + OUTLINK_PARK + 1: the transmit descriptor's FSM is in idle state. +0: the transmit descriptor's FSM is working. + 31 + 1 + read-only + + + + + DMA_IN_LINK + Link descriptor address and control + 0x28 + 0x20 + 0x00100000 + + + INLINK_ADDR + This register is used to specify the least significant 20 bits of the first receive descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + This is the enable bit to return to current receive descriptor's address, when there are some errors in current packet. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the receive descriptors. + 28 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the receive descriptors. + 29 + 1 + read-write + + + INLINK_RESTART + Set this bit to restart new receive descriptors. + 30 + 1 + read-write + + + INLINK_PARK + 1: the receive descriptor's FSM is in idle state. +0: the receive descriptor's FSM is working. + 31 + 1 + read-only + + + + + CONF1 + UHCI configuration register + 0x2C + 0x20 + 0x00000033 + + + CHECK_SUM_EN + This is the enable bit to check header checksum when UHCI receives a data packet. + 0 + 1 + read-write + + + CHECK_SEQ_EN + This is the enable bit to check sequence number when UHCI receives a data packet. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save the packet header when UHCI receives a data packet. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode the data packet with a checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit. + 5 + 1 + read-write + + + CHECK_OWNER + 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor. + 6 + 1 + read-write + + + WAIT_SW_START + The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1. + 7 + 1 + read-write + + + SW_START + If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. + 8 + 1 + read-write + + + DMA_INFIFO_FULL_THRS + This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register. + 9 + 12 + read-write + + + + + STATE0 + UHCI decoder status register + 0x30 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current receive descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + Reserved. + 18 + 2 + read-only + + + IN_STATE + Reserved. + 20 + 3 + read-only + + + INFIFO_CNT_DEBUG + This register stores the number of data bytes in RX FIFO. + 23 + 5 + read-only + + + DECODE_STATE + UHCI decoder status. + 28 + 3 + read-only + + + + + STATE1 + UHCI encoder status register + 0x34 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current transmit descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + Reserved. + 18 + 2 + read-only + + + OUT_STATE + Reserved. + 20 + 3 + read-only + + + OUTFIFO_CNT + This register stores the number of data bytes in TX FIFO. + 23 + 5 + read-only + + + ENCODE_STATE + UHCI encoder status. + 28 + 3 + read-only + + + + + DMA_OUT_EOF_DES_ADDR + Outlink descriptor address when EOF occurs + 0x38 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + DMA_IN_SUC_EOF_DES_ADDR + Inlink descriptor address when EOF occurs + 0x3C + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the receive descriptor when received successful EOF. + 0 + 32 + read-only + + + + + DMA_IN_ERR_EOF_DES_ADDR + Inlink descriptor address when errors occur + 0x40 + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the receive descriptor when there are some errors in this descriptor. + 0 + 32 + read-only + + + + + DMA_OUT_EOF_BFR_DES_ADDR + Outlink descriptor address before the last transmit descriptor + 0x44 + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the transmit descriptor before the last transmit descriptor. + 0 + 32 + read-only + + + + + AHB_TEST + AHB test register + 0x48 + 0x20 + + + AHB_TESTMODE + Reserved. + 0 + 3 + read-write + + + AHB_TESTADDR + Reserved. + 4 + 2 + read-write + + + + + DMA_IN_DSCR + The third word of the next receive descriptor + 0x4C + 0x20 + + + INLINK_DSCR + This register stores the third word of the next receive descriptor. + 0 + 32 + read-only + + + + + DMA_IN_DSCR_BF0 + The third word of current receive descriptor + 0x50 + 0x20 + + + INLINK_DSCR_BF0 + This register stores the third word of the current receive descriptor. + 0 + 32 + read-only + + + + + DMA_OUT_DSCR + The third word of the next transmit descriptor + 0x58 + 0x20 + + + OUTLINK_DSCR + This register stores the third word of the next transmit descriptor. + 0 + 32 + read-only + + + + + DMA_OUT_DSCR_BF0 + The third word of current transmit descriptor + 0x5C + 0x20 + + + OUTLINK_DSCR_BF0 + This register stores the third word of the current transmit descriptor. + 0 + 32 + read-only + + + + + ESCAPE_CONF + Escape character configuration + 0x64 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to decode character 0xC0 when DMA receives data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to decode character 0xDB when DMA receives data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to decode flow control character 0x11 when DMA receives data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to decode flow control character 0x13 when DMA receives data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to replace 0xC0 by special characters when DMA sends data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to replace 0xDB by special characters when DMA sends data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to replace flow control character 0x11 by special characters when DMA sends data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to replace flow control character 0x13 by special characters when DMA sends data. + 7 + 1 + read-write + + + + + HUNG_CONF + Timeout configuration + 0x68 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + This register is used to configure the maximum tick count. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + This is the enable bit for TX FIFO receive timeout. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + This register stores the timeout value. UHCI produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + This register is used to configure the maximum tick count. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send timeout. + 23 + 1 + read-write + + + + + RX_HEAD + UHCI packet header register + 0x70 + 0x20 + + + RX_HEAD + This register stores the header of the current received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UHCI quick_sent configuration register + 0x74 + 0x20 + + + SINGLE_SEND_NUM + This register is used to specify the single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable single_send mode to send short packets. + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + This register is used to specify the always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable always_send mode to send short packets. + 7 + 1 + read-write + + + + + Q0_WORD0 + Q0_WORD0 quick_sent register + 0x78 + 0x20 + + + SEND_Q0_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q0_WORD1 + Q0_WORD1 quick_sent register + 0x7C + 0x20 + + + SEND_Q0_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q1_WORD0 + Q1_WORD0 quick_sent register + 0x80 + 0x20 + + + SEND_Q1_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q1_WORD1 + Q1_WORD1 quick_sent register + 0x84 + 0x20 + + + SEND_Q1_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q2_WORD0 + Q2_WORD0 quick_sent register + 0x88 + 0x20 + + + SEND_Q2_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q2_WORD1 + Q2_WORD1 quick_sent register + 0x8C + 0x20 + + + SEND_Q2_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q3_WORD0 + Q3_WORD0 quick_sent register + 0x90 + 0x20 + + + SEND_Q3_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q3_WORD1 + Q3_WORD1 quick_sent register + 0x94 + 0x20 + + + SEND_Q3_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q4_WORD0 + Q4_WORD0 quick_sent register + 0x98 + 0x20 + + + SEND_Q4_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q4_WORD1 + Q4_WORD1 quick_sent register + 0x9C + 0x20 + + + SEND_Q4_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q5_WORD0 + Q5_WORD0 quick_sent register + 0xA0 + 0x20 + + + SEND_Q5_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q5_WORD1 + Q5_WORD1 quick_sent register + 0xA4 + 0x20 + + + SEND_Q5_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q6_WORD0 + Q6_WORD0 quick_sent register + 0xA8 + 0x20 + + + SEND_Q6_WORD0 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + Q6_WORD1 + Q6_WORD1 quick_sent register + 0xAC + 0x20 + + + SEND_Q6_WORD1 + This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + Escape sequence configuration register 0 + 0xB0 + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + This register is used to define separators to encode data packets. The default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + This register is used to define the second character of SLIP escape sequence. The default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + Escape sequence configuration register 1 + 0xB4 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + This register is used to define a character that need to be encoded. The default value is 0xDB that used as the first character of SLIP escape sequence. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + This register is used to define the second character of SLIP escape sequence. The default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + Escape sequence configuration register 2 + 0xB8 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + This register is used to define a character that need to be encoded. The default value is 0x11 that used as a flow control character. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + This register is used to define the second character of SLIP escape sequence. The default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + Escape sequence configuration register 3 + 0xBC + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + This register is used to define a character that need to be decoded. The default value is 0x13 that used as a flow control character. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + This register is used to define the second character of SLIP escape sequence. The default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + Configure register for packet length + 0xC0 + 0x20 + 0x00000080 + + + PKT_THRS + This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI version control register + 0xFC + 0x20 + 0x18073001 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + USB0 + USB OTG (On-The-Go) + USB + 0x60080000 + + 0x0 + 0x2A0 + registers + + + + GOTGCTL + 0x0 + 0x20 + + + SESREQSCS + 0 + 1 + read-only + + + SESREQ + 1 + 1 + read-write + + + VBVALIDOVEN + 2 + 1 + read-write + + + VBVALIDOVVAL + 3 + 1 + read-write + + + AVALIDOVEN + 4 + 1 + read-write + + + AVALIDOVVAL + 5 + 1 + read-write + + + BVALIDOVEN + 6 + 1 + read-write + + + BVALIDOVVAL + 7 + 1 + read-write + + + HSTNEGSCS + 8 + 1 + read-only + + + HNPREQ + 9 + 1 + read-write + + + HSTSETHNPEN + 10 + 1 + read-write + + + DEVHNPEN + 11 + 1 + read-write + + + EHEN + 12 + 1 + read-write + + + DBNCEFLTRBYPASS + 15 + 1 + read-write + + + CONIDSTS + 16 + 1 + read-only + + + DBNCTIME + 17 + 1 + read-only + + + ASESVLD + 18 + 1 + read-only + + + BSESVLD + 19 + 1 + read-only + + + OTGVER + 20 + 1 + read-write + + + CURMOD + 21 + 1 + read-only + + + + + GOTGINT + 0x4 + 0x20 + + + SESENDDET + 2 + 1 + read-write + + + SESREQSUCSTSCHNG + 8 + 1 + read-write + + + HSTNEGSUCSTSCHNG + 9 + 1 + read-write + + + HSTNEGDET + 17 + 1 + read-write + + + ADEVTOUTCHG + 18 + 1 + read-write + + + DBNCEDONE + 19 + 1 + read-write + + + + + GAHBCFG + 0x8 + 0x20 + + + GLBLLNTRMSK + 0 + 1 + read-write + + + HBSTLEN + 1 + 4 + read-write + + + DMAEN + 5 + 1 + read-write + + + NPTXFEMPLVL + 7 + 1 + read-write + + + PTXFEMPLVL + 8 + 1 + read-write + + + REMMEMSUPP + 21 + 1 + read-write + + + NOTIALLDMAWRIT + 22 + 1 + read-write + + + AHBSINGLE + 23 + 1 + read-write + + + INVDESCENDIANESS + 24 + 1 + read-write + + + + + GUSBCFG + 0xC + 0x20 + 0x00001440 + + + TOUTCAL + 0 + 3 + read-write + + + PHYIF + 3 + 1 + read-write + + + ULPI_UTMI_SEL + 4 + 1 + read-only + + + FSINTF + 5 + 1 + read-write + + + PHYSEL + 6 + 1 + read-only + + + SRPCAP + 8 + 1 + read-write + + + HNPCAP + 9 + 1 + read-write + + + USBTRDTIM + 10 + 4 + read-write + + + TERMSELDLPULSE + 22 + 1 + read-write + + + TXENDDELAY + 28 + 1 + read-write + + + FORCEHSTMODE + 29 + 1 + read-write + + + FORCEDEVMODE + 30 + 1 + read-write + + + CORRUPTTXPKT + 31 + 1 + read-write + + + + + GRSTCTL + 0x10 + 0x20 + + + CSFTRST + 0 + 1 + read-write + + + PIUFSSFTRST + 1 + 1 + read-write + + + FRMCNTRRST + 2 + 1 + read-write + + + RXFFLSH + 4 + 1 + read-write + + + TXFFLSH + 5 + 1 + read-write + + + TXFNUM + 6 + 5 + read-write + + + DMAREQ + 30 + 1 + read-only + + + AHBIDLE + 31 + 1 + read-only + + + + + GINTSTS + 0x14 + 0x20 + + + CURMOD_INT + 0 + 1 + read-only + + + MODEMIS + 1 + 1 + read-write + + + OTGINT + 2 + 1 + read-only + + + SOF + 3 + 1 + read-write + + + RXFLVI + 4 + 1 + read-only + + + NPTXFEMP + 5 + 1 + read-only + + + GINNAKEFF + 6 + 1 + read-only + + + GOUTNAKEFF + 7 + 1 + read-only + + + ERLYSUSP + 10 + 1 + read-write + + + USBSUSP + 11 + 1 + read-write + + + USBRST + 12 + 1 + read-write + + + ENUMDONE + 13 + 1 + read-write + + + ISOOUTDROP + 14 + 1 + read-write + + + EOPF + 15 + 1 + read-write + + + EPMIS + 17 + 1 + read-write + + + IEPINT + 18 + 1 + read-only + + + OEPINT + 19 + 1 + read-only + + + INCOMPISOIN + 20 + 1 + read-write + + + INCOMPIP + 21 + 1 + read-write + + + FETSUSP + 22 + 1 + read-write + + + RESETDET + 23 + 1 + read-write + + + PRTLNT + 24 + 1 + read-only + + + HCHLNT + 25 + 1 + read-only + + + PTXFEMP + 26 + 1 + read-only + + + CONIDSTSCHNG + 28 + 1 + read-write + + + DISCONNINT + 29 + 1 + read-write + + + SESSREQINT + 30 + 1 + read-write + + + WKUPINT + 31 + 1 + read-write + + + + + GINTMSK + 0x18 + 0x20 + + + MODEMISMSK + 1 + 1 + read-write + + + OTGINTMSK + 2 + 1 + read-write + + + SOFMSK + 3 + 1 + read-write + + + RXFLVIMSK + 4 + 1 + read-write + + + NPTXFEMPMSK + 5 + 1 + read-write + + + GINNAKEFFMSK + 6 + 1 + read-write + + + GOUTNACKEFFMSK + 7 + 1 + read-write + + + ERLYSUSPMSK + 10 + 1 + read-write + + + USBSUSPMSK + 11 + 1 + read-write + + + USBRSTMSK + 12 + 1 + read-write + + + ENUMDONEMSK + 13 + 1 + read-write + + + ISOOUTDROPMSK + 14 + 1 + read-write + + + EOPFMSK + 15 + 1 + read-write + + + EPMISMSK + 17 + 1 + read-write + + + IEPINTMSK + 18 + 1 + read-write + + + OEPINTMSK + 19 + 1 + read-write + + + INCOMPISOINMSK + 20 + 1 + read-write + + + INCOMPIPMSK + 21 + 1 + read-write + + + FETSUSPMSK + 22 + 1 + read-write + + + RESETDETMSK + 23 + 1 + read-write + + + PRTLNTMSK + 24 + 1 + read-write + + + HCHINTMSK + 25 + 1 + read-write + + + PTXFEMPMSK + 26 + 1 + read-write + + + CONIDSTSCHNGMSK + 28 + 1 + read-write + + + DISCONNINTMSK + 29 + 1 + read-write + + + SESSREQINTMSK + 30 + 1 + read-write + + + WKUPINTMSK + 31 + 1 + read-write + + + + + GRXSTSR + 0x1C + 0x20 + + + G_CHNUM + 0 + 4 + read-only + + + G_BCNT + 4 + 11 + read-only + + + G_DPID + 15 + 2 + read-only + + + G_PKTSTS + 17 + 4 + read-only + + + G_FN + 21 + 4 + read-only + + + + + GRXSTSP + 0x20 + 0x20 + + + CHNUM + 0 + 4 + read-only + + + BCNT + 4 + 11 + read-only + + + DPID + 15 + 2 + read-only + + + PKTSTS + 17 + 4 + read-only + + + FN + 21 + 4 + read-only + + + + + GRXFSIZ + 0x24 + 0x20 + 0x00000100 + + + RXFDEP + 0 + 16 + read-write + + + + + GNPTXFSIZ + 0x28 + 0x20 + 0x01000100 + + + NPTXFSTADDR + 0 + 16 + read-write + + + NPTXFDEP + 16 + 16 + read-write + + + + + GNPTXSTS + 0x2C + 0x20 + 0x00040100 + + + NPTXFSPCAVAIL + 0 + 16 + read-only + + + NPTXQSPCAVAIL + 16 + 4 + read-only + + + NPTXQTOP + 24 + 7 + read-only + + + + + GSNPSID + 0x40 + 0x20 + 0x4F54400A + + + SYNOPSYSID + 0 + 32 + read-only + + + + + GHWCFG1 + 0x44 + 0x20 + + + EPDIR + 0 + 32 + read-only + + + + + GHWCFG2 + 0x48 + 0x20 + 0x224DD930 + + + OTGMODE + 0 + 3 + read-only + + + OTGARCH + 3 + 2 + read-only + + + SINGPNT + 5 + 1 + read-only + + + HSPHYTYPE + 6 + 2 + read-only + + + FSPHYTYPE + 8 + 2 + read-only + + + NUMDEVEPS + 10 + 4 + read-only + + + NUMHSTCHNL + 14 + 4 + read-only + + + PERIOSUPPORT + 18 + 1 + read-only + + + DYNFIFOSIZING + 19 + 1 + read-only + + + MULTIPROCINTRPT + 20 + 1 + read-only + + + NPTXQDEPTH + 22 + 2 + read-only + + + PTXQDEPTH + 24 + 2 + read-only + + + TKNQDEPTH + 26 + 5 + read-only + + + OTG_ENABLE_IC_USB + 31 + 1 + read-only + + + + + GHWCFG3 + 0x4C + 0x20 + 0x010004B5 + + + XFERSIZEWIDTH + 0 + 4 + read-only + + + PKTSIZEWIDTH + 4 + 3 + read-only + + + OTGEN + 7 + 1 + read-only + + + I2CINTSEL + 8 + 1 + read-only + + + VNDCTLSUPT + 9 + 1 + read-only + + + OPTFEATURE + 10 + 1 + read-only + + + RSTTYPE + 11 + 1 + read-only + + + ADPSUPPORT + 12 + 1 + read-only + + + HSICMODE + 13 + 1 + read-only + + + BCSUPPORT + 14 + 1 + read-only + + + LPMMODE + 15 + 1 + read-only + + + DFIFODEPTH + 16 + 16 + read-only + + + + + GHWCFG4 + 0x50 + 0x20 + 0xD3F0A030 + + + G_NUMDEVPERIOEPS + 0 + 4 + read-only + + + G_PARTIALPWRDN + 4 + 1 + read-only + + + G_AHBFREQ + 5 + 1 + read-only + + + G_HIBERNATION + 6 + 1 + read-only + + + G_EXTENDEDHIBERNATION + 7 + 1 + read-only + + + G_ACGSUPT + 12 + 1 + read-only + + + G_ENHANCEDLPMSUPT + 13 + 1 + read-only + + + G_PHYDATAWIDTH + 14 + 2 + read-only + + + G_NUMCTLEPS + 16 + 4 + read-only + + + G_IDDQFLTR + 20 + 1 + read-only + + + G_VBUSVALIDFLTR + 21 + 1 + read-only + + + G_AVALIDFLTR + 22 + 1 + read-only + + + G_BVALIDFLTR + 23 + 1 + read-only + + + G_SESSENDFLTR + 24 + 1 + read-only + + + G_DEDFIFOMODE + 25 + 1 + read-only + + + G_INEPS + 26 + 4 + read-only + + + G_DESCDMAENABLED + 30 + 1 + read-only + + + G_DESCDMA + 31 + 1 + read-only + + + + + GDFIFOCFG + 0x5C + 0x20 + + + GDFIFOCFG + 0 + 16 + read-write + + + EPINFOBASEADDR + 16 + 16 + read-write + + + + + HPTXFSIZ + 0x100 + 0x20 + 0x10000200 + + + PTXFSTADDR + 0 + 16 + read-write + + + PTXFSIZE + 16 + 16 + read-write + + + + + DIEPTXF1 + 0x104 + 0x20 + 0x10000200 + + + INEP1TXFSTADDR + 0 + 16 + read-write + + + INEP1TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF2 + 0x108 + 0x20 + 0x10000200 + + + INEP2TXFSTADDR + 0 + 16 + read-write + + + INEP2TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF3 + 0x10C + 0x20 + 0x10000200 + + + INEP3TXFSTADDR + 0 + 16 + read-write + + + INEP3TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF4 + 0x110 + 0x20 + 0x10000200 + + + INEP4TXFSTADDR + 0 + 16 + read-write + + + INEP4TXFDEP + 16 + 16 + read-write + + + + + HCFG + 0x400 + 0x20 + + + H_FSLSPCLKSEL + 0 + 2 + read-write + + + H_FSLSSUPP + 2 + 1 + read-write + + + H_ENA32KHZS + 7 + 1 + read-write + + + H_DESCDMA + 23 + 1 + read-write + + + H_FRLISTEN + 24 + 2 + read-write + + + H_PERSCHEDENA + 26 + 1 + read-write + + + H_MODECHTIMEN + 31 + 1 + read-write + + + + + HFIR + 0x404 + 0x20 + 0x000017D7 + + + FRINT + 0 + 16 + read-write + + + HFIRRLDCTRL + 16 + 1 + read-write + + + + + HFNUM + 0x408 + 0x20 + 0x00003FFF + + + FRNUM + 0 + 14 + read-only + + + FRREM + 16 + 16 + read-only + + + + + HPTXSTS + 0x410 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + 0 + 16 + read-only + + + PTXQSPCAVAIL + 16 + 5 + read-only + + + PTXQTOP + 24 + 8 + read-only + + + + + HAINT + 0x414 + 0x20 + + + HAINT + 0 + 8 + read-only + + + + + HAINTMSK + 0x418 + 0x20 + + + HAINTMSK + 0 + 8 + read-write + + + + + HFLBADDR + 0x41C + 0x20 + + + HFLBADDR + 0 + 32 + read-write + + + + + HPRT + 0x440 + 0x20 + + + PRTCONNSTS + 0 + 1 + read-only + + + PRTCONNDET + 1 + 1 + read-write + + + PRTENA + 2 + 1 + read-write + + + PRTENCHNG + 3 + 1 + read-write + + + PRTOVRCURRACT + 4 + 1 + read-only + + + PRTOVRCURRCHNG + 5 + 1 + read-write + + + PRTRES + 6 + 1 + read-write + + + PRTSUSP + 7 + 1 + read-write + + + PRTRST + 8 + 1 + read-write + + + PRTLNSTS + 10 + 2 + read-only + + + PRTPWR + 12 + 1 + read-write + + + PRTTSTCTL + 13 + 4 + read-write + + + PRTSPD + 17 + 2 + read-only + + + + + HCCHAR0 + 0x500 + 0x20 + + + H_MPS0 + 0 + 11 + read-write + + + H_EPNUM0 + 11 + 4 + read-write + + + H_EPDIR0 + 15 + 1 + read-write + + + H_LSPDDEV0 + 17 + 1 + read-write + + + H_EPTYPE0 + 18 + 2 + read-write + + + H_EC0 + 21 + 1 + read-write + + + H_DEVADDR0 + 22 + 7 + read-write + + + H_ODDFRM0 + 29 + 1 + read-write + + + H_CHDIS0 + 30 + 1 + read-write + + + H_CHENA0 + 31 + 1 + read-write + + + + + HCINT0 + 0x508 + 0x20 + + + H_XFERCOMPL0 + 0 + 1 + read-write + + + H_CHHLTD0 + 1 + 1 + read-write + + + H_AHBERR0 + 2 + 1 + read-write + + + H_STALL0 + 3 + 1 + read-write + + + H_NACK0 + 4 + 1 + read-write + + + H_ACK0 + 5 + 1 + read-write + + + H_NYET0 + 6 + 1 + read-write + + + H_XACTERR0 + 7 + 1 + read-write + + + H_BBLERR0 + 8 + 1 + read-write + + + H_FRMOVRUN0 + 9 + 1 + read-write + + + H_DATATGLERR0 + 10 + 1 + read-write + + + H_BNAINTR0 + 11 + 1 + read-write + + + H_XCS_XACT_ERR0 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR0 + 13 + 1 + read-write + + + + + HCINTMSK0 + 0x50C + 0x20 + + + H_XFERCOMPLMSK0 + 0 + 1 + read-write + + + H_CHHLTDMSK0 + 1 + 1 + read-write + + + H_AHBERRMSK0 + 2 + 1 + read-write + + + H_STALLMSK0 + 3 + 1 + read-write + + + H_NAKMSK0 + 4 + 1 + read-write + + + H_ACKMSK0 + 5 + 1 + read-write + + + H_NYETMSK0 + 6 + 1 + read-write + + + H_XACTERRMSK0 + 7 + 1 + read-write + + + H_BBLERRMSK0 + 8 + 1 + read-write + + + H_FRMOVRUNMSK0 + 9 + 1 + read-write + + + H_DATATGLERRMSK0 + 10 + 1 + read-write + + + H_BNAINTRMSK0 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK0 + 13 + 1 + read-write + + + + + HCTSIZ0 + 0x510 + 0x20 + + + H_XFERSIZE0 + 0 + 19 + read-write + + + H_PKTCNT0 + 19 + 10 + read-write + + + H_PID0 + 29 + 2 + read-write + + + H_DOPNG0 + 31 + 1 + read-write + + + + + HCDMA0 + 0x514 + 0x20 + + + H_DMAADDR0 + 0 + 32 + read-write + + + + + HCDMAB0 + 0x51C + 0x20 + + + H_HCDMAB0 + 0 + 32 + read-only + + + + + HCCHAR1 + 0x520 + 0x20 + + + H_MPS1 + 0 + 11 + read-write + + + H_EPNUM1 + 11 + 4 + read-write + + + H_EPDIR1 + 15 + 1 + read-write + + + H_LSPDDEV1 + 17 + 1 + read-write + + + H_EPTYPE1 + 18 + 2 + read-write + + + H_EC1 + 21 + 1 + read-write + + + H_DEVADDR1 + 22 + 7 + read-write + + + H_ODDFRM1 + 29 + 1 + read-write + + + H_CHDIS1 + 30 + 1 + read-write + + + H_CHENA1 + 31 + 1 + read-write + + + + + HCINT1 + 0x528 + 0x20 + + + H_XFERCOMPL1 + 0 + 1 + read-write + + + H_CHHLTD1 + 1 + 1 + read-write + + + H_AHBERR1 + 2 + 1 + read-write + + + H_STALL1 + 3 + 1 + read-write + + + H_NACK1 + 4 + 1 + read-write + + + H_ACK1 + 5 + 1 + read-write + + + H_NYET1 + 6 + 1 + read-write + + + H_XACTERR1 + 7 + 1 + read-write + + + H_BBLERR1 + 8 + 1 + read-write + + + H_FRMOVRUN1 + 9 + 1 + read-write + + + H_DATATGLERR1 + 10 + 1 + read-write + + + H_BNAINTR1 + 11 + 1 + read-write + + + H_XCS_XACT_ERR1 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR1 + 13 + 1 + read-write + + + + + HCINTMSK1 + 0x52C + 0x20 + + + H_XFERCOMPLMSK1 + 0 + 1 + read-write + + + H_CHHLTDMSK1 + 1 + 1 + read-write + + + H_AHBERRMSK1 + 2 + 1 + read-write + + + H_STALLMSK1 + 3 + 1 + read-write + + + H_NAKMSK1 + 4 + 1 + read-write + + + H_ACKMSK1 + 5 + 1 + read-write + + + H_NYETMSK1 + 6 + 1 + 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read-write + + + + + DOEPCTL4 + 0xB80 + 0x20 + 0x00008000 + + + MPS4 + 0 + 11 + read-only + + + USBACTEP4 + 15 + 1 + read-only + + + NAKSTS4 + 17 + 1 + read-only + + + EPTYPE4 + 18 + 2 + read-only + + + SNP4 + 20 + 1 + read-write + + + STALL4 + 21 + 1 + read-write + + + CNAK4 + 26 + 1 + write-only + + + DO_SNAK4 + 27 + 1 + write-only + + + DO_SETD0PID4 + 28 + 1 + write-only + + + DO_SETD1PID4 + 29 + 1 + write-only + + + EPDIS4 + 30 + 1 + read-only + + + EPENA4 + 31 + 1 + read-write + + + + + DOEPINT4 + 0xB88 + 0x20 + + + XFERCOMPL4 + 0 + 1 + read-write + + + EPDISBLD4 + 1 + 1 + read-write + + + AHBERR4 + 2 + 1 + read-write + + + SETUP4 + 3 + 1 + read-write + + + OUTTKNEPDIS4 + 4 + 1 + read-write + + + STSPHSERCVD4 + 5 + 1 + read-write + + + BACK2BACKSETUP4 + 6 + 1 + read-write + + + OUTPKTERR4 + 8 + 1 + read-write + + + BNAINTR4 + 9 + 1 + read-write + + + PKTDRPSTS4 + 11 + 1 + read-write + + + BBLEERR4 + 12 + 1 + read-write + + + NAKINTRPT4 + 13 + 1 + read-write + + + NYEPINTRPT4 + 14 + 1 + read-write + + + STUPPKTRCVD4 + 15 + 1 + read-write + + + + + DOEPTSIZ4 + 0xB90 + 0x20 + + + XFERSIZE4 + 0 + 7 + read-write + + + PKTCNT4 + 19 + 1 + read-write + + + SUPCNT4 + 29 + 2 + read-write + + + + + DOEPDMA4 + 0xB94 + 0x20 + + + DMAADDR4 + 0 + 32 + read-write + + + + + DOEPDMAB4 + 0xB9C + 0x20 + + + DMABUFFERADDR4 + 0 + 32 + read-write + + + + + DOEPCTL5 + 0xBA0 + 0x20 + 0x00008000 + + + MPS5 + 0 + 11 + read-only + + + USBACTEP5 + 15 + 1 + read-only + + + NAKSTS5 + 17 + 1 + read-only + + + EPTYPE5 + 18 + 2 + read-only + + + SNP5 + 20 + 1 + read-write + + + STALL5 + 21 + 1 + read-write + + + CNAK5 + 26 + 1 + write-only + + + DO_SNAK5 + 27 + 1 + write-only + + + DO_SETD0PID5 + 28 + 1 + write-only + + + DO_SETD1PID5 + 29 + 1 + write-only + + + EPDIS5 + 30 + 1 + read-only + + + EPENA5 + 31 + 1 + read-write + + + + + DOEPINT5 + 0xBA8 + 0x20 + + + XFERCOMPL5 + 0 + 1 + read-write + + + EPDISBLD5 + 1 + 1 + read-write + + + AHBERR5 + 2 + 1 + read-write + + + SETUP5 + 3 + 1 + read-write + + + OUTTKNEPDIS5 + 4 + 1 + read-write + + + STSPHSERCVD5 + 5 + 1 + read-write + + + BACK2BACKSETUP5 + 6 + 1 + read-write + + + OUTPKTERR5 + 8 + 1 + read-write + + + BNAINTR5 + 9 + 1 + read-write + + + PKTDRPSTS5 + 11 + 1 + read-write + + + BBLEERR5 + 12 + 1 + read-write + + + NAKINTRPT5 + 13 + 1 + read-write + + + NYEPINTRPT5 + 14 + 1 + read-write + + + STUPPKTRCVD5 + 15 + 1 + read-write + + + + + DOEPTSIZ5 + 0xBB0 + 0x20 + + + XFERSIZE5 + 0 + 7 + read-write + + + PKTCNT5 + 19 + 1 + read-write + + + SUPCNT5 + 29 + 2 + read-write + + + + + DOEPDMA5 + 0xBB4 + 0x20 + + + DMAADDR5 + 0 + 32 + read-write + + + + + DOEPDMAB5 + 0xBBC + 0x20 + + + DMABUFFERADDR5 + 0 + 32 + read-write + + + + + DOEPCTL6 + 0xBC0 + 0x20 + 0x00008000 + + + MPS6 + 0 + 11 + read-only + + + USBACTEP6 + 15 + 1 + read-only + + + NAKSTS6 + 17 + 1 + read-only + + + EPTYPE6 + 18 + 2 + read-only + + + SNP6 + 20 + 1 + read-write + + + STALL6 + 21 + 1 + read-write + + + CNAK6 + 26 + 1 + write-only + + + DO_SNAK6 + 27 + 1 + write-only + + + DO_SETD0PID6 + 28 + 1 + write-only + + + DO_SETD1PID6 + 29 + 1 + write-only + + + EPDIS6 + 30 + 1 + read-only + + + EPENA6 + 31 + 1 + read-write + + + + + DOEPINT6 + 0xBC8 + 0x20 + + + XFERCOMPL6 + 0 + 1 + read-write + + + EPDISBLD6 + 1 + 1 + read-write + + + AHBERR6 + 2 + 1 + read-write + + + SETUP6 + 3 + 1 + read-write + + + OUTTKNEPDIS6 + 4 + 1 + read-write + + + STSPHSERCVD6 + 5 + 1 + read-write + + + BACK2BACKSETUP6 + 6 + 1 + read-write + + + OUTPKTERR6 + 8 + 1 + read-write + + + BNAINTR6 + 9 + 1 + read-write + + + PKTDRPSTS6 + 11 + 1 + read-write + + + BBLEERR6 + 12 + 1 + read-write + + + NAKINTRPT6 + 13 + 1 + read-write + + + NYEPINTRPT6 + 14 + 1 + read-write + + + STUPPKTRCVD6 + 15 + 1 + read-write + + + + + DOEPTSIZ6 + 0xBD0 + 0x20 + + + XFERSIZE6 + 0 + 7 + read-write + + + PKTCNT6 + 19 + 1 + read-write + + + SUPCNT6 + 29 + 2 + read-write + + + + + DOEPDMA6 + 0xBD4 + 0x20 + + + DMAADDR6 + 0 + 32 + read-write + + + + + DOEPDMAB6 + 0xBDC + 0x20 + + + DMABUFFERADDR6 + 0 + 32 + read-write + + + + + PCGCCTL + 0xE00 + 0x20 + + + STOPPCLK + 0 + 1 + read-write + + + GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + 2 + 1 + read-write + + + RSTPDWNMODULE + 3 + 1 + read-write + + + PHYSLEEP + 6 + 1 + read-only + + + L1SUSPENDED + 7 + 1 + read-only + + + RESETAFTERSUSP + 8 + 1 + read-write + + + + + + + USB_WRAP + Peripheral USB_WRAP + USB_WRAP + 0x3F439000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB OTG Wrapper Configure Register + 0x0 + 0x20 + 0x001C0000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers + 31 + 1 + read-write + + + + + TEST_CONF + USB Internal PHY Testing Register + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + DATE + Version Control Register + 0x3FC + 0x20 + 0x02102010 + + + USB_WRAP_DATE + Date register + 0 + 32 + read-write + + + + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x6003A100 + + 0x0 + 0x60 + registers + + + + 16 + 0x4 + PLAIN_%s + Plaintext register %s + 0x100 + 0x20 + + + PLAIN_0 + This register stores %sth 32-bit piece of plaintext. + 0 + 32 + read-write + + + + + LINESIZE + Configures the size of target memory space + 0x140 + 0x20 + + + LINESIZE + Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits. + 0 + 2 + read-write + + + + + DESTINATION + Configures the type of the external memory + 0x144 + 0x20 + + + DESTINATION + Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + Physical address + 0x148 + 0x20 + + + PHYSICAL_ADDRESS + Physical address. + 0 + 30 + read-write + + + + + TRIGGER + Activates AES algorithm + 0x14C + 0x20 + + + TRIGGER + Set to enable manual encryption. + 0 + 1 + write-only + + + + + RELEASE + Release control + 0x150 + 0x20 + + + RELEASE + Set to grant SPI1 access to encrypted result. + 0 + 1 + write-only + + + + + DESTROY + Destroys control + 0x154 + 0x20 + + + DESTROY + Set to destroy encrypted result. + 0 + 1 + write-only + + + + + STATE + Status register + 0x158 + 0x20 + + + STATE + Indicates the status of the Manual Encryption block. 0x0 (XTS_AES_IDLE): idle. 0x1 (XTS_AES_BUSY): busy with encryption. 0x2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_RELEASE): encrypted result is accessible to SPI. + 0 + 2 + read-only + + + + + DATE + Version control register + 0x15C + 0x20 + 0x20190514 + + + DATE + Version control register. + 0 + 30 + read-only + + + + + + + diff --git a/tools/ide-debug/svd/esp32s3.svd b/tools/ide-debug/svd/esp32s3.svd new file mode 100644 index 0000000..a36e851 --- /dev/null +++ b/tools/ide-debug/svd/esp32s3.svd @@ -0,0 +1,67571 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S3 + ESP32-S3 + 12 + 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Xtensa LX7 + r0p0 + little + false + true + 3 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xB8 + registers + + + AES + 77 + + + + 8 + 0x4 + KEY_%s + AES key register %s + 0x0 + 0x20 + + + KEY_0 + Stores AES keys. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_IN_%s + Source data register %s + 0x20 + 0x20 + + + TEXT_IN_0 + Stores the source data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_OUT_%s + Result data register %s + 0x30 + 0x20 + + + TEXT_OUT_0 + Stores the result data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + Defines the key length and the encryption/decryption of the AES accelerator. + 0 + 3 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to 1 to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + AES accelerator working mode register + 0x90 + 0x20 + + + DMA_ENABLE + Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to 1 to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to 1 to clear AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + DMA-AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation. + 0 + 1 + write-only + + + + + + + APB_CTRL + Advanced Peripheral Bus Controller + APB_CTRL + 0x60026000 + + 0x0 + 0xCC + registers + + + + SYSCLK_CONF + ******* Description *********** + 0x0 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + ******* Description *********** + 0 + 10 + read-write + + + CLK_320M_EN + ******* Description *********** + 10 + 1 + read-write + + + CLK_EN + ******* Description *********** + 11 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 12 + 1 + read-write + + + + + TICK_CONF + ******* Description *********** + 0x4 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + CK8M_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + + + CLK_OUT_EN + ******* Description *********** + 0x8 + 0x20 + 0x000007FF + + + CLK20_OEN + ******* Description *********** + 0 + 1 + read-write + + + CLK22_OEN + ******* Description *********** + 1 + 1 + read-write + + + CLK44_OEN + ******* Description *********** + 2 + 1 + read-write + + + CLK_BB_OEN + ******* Description *********** + 3 + 1 + read-write + + + CLK80_OEN + ******* Description *********** + 4 + 1 + read-write + + + CLK160_OEN + ******* Description *********** + 5 + 1 + read-write + + + CLK_320M_OEN + ******* Description *********** + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + ******* Description *********** + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + ******* Description *********** + 8 + 1 + read-write + + + CLK40X_BB_OEN + ******* Description *********** + 9 + 1 + read-write + + + CLK_XTAL_OEN + ******* Description *********** + 10 + 1 + read-write + + + + + WIFI_BB_CFG + ******* Description *********** + 0xC + 0x20 + + + WIFI_BB_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + ******* Description *********** + 0x10 + 0x20 + + + WIFI_BB_CFG_2 + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_CLK_EN + ******* Description *********** + 0x14 + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_RST_EN + ******* Description *********** + 0x18 + 0x20 + + + WIFI_RST + ******* Description *********** + 0 + 32 + read-write + + + + + HOST_INF_SEL + ******* Description *********** + 0x1C + 0x20 + + + PERI_IO_SWAP + ******* Description *********** + 0 + 8 + read-write + + + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0x20 + 0x20 + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0 + 1 + read-write + + + + + EXT_MEM_WRITEBACK_BYPASS + ******* Description *********** + 0x24 + 0x20 + + + WRITEBACK_BYPASS + Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute. + 0 + 1 + read-write + + + + + FLASH_ACE0_ATTR + ******* Description *********** + 0x28 + 0x20 + 0x000000FF + + + FLASH_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE1_ATTR + ******* Description *********** + 0x2C + 0x20 + 0x000000FF + + + FLASH_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE2_ATTR + ******* Description *********** + 0x30 + 0x20 + 0x000000FF + + + FLASH_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE3_ATTR + ******* Description *********** + 0x34 + 0x20 + 0x000000FF + + + FLASH_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE0_ADDR + ******* Description *********** + 0x38 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE1_ADDR + ******* Description *********** + 0x3C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE2_ADDR + ******* Description *********** + 0x40 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE3_ADDR + ******* Description *********** + 0x44 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE0_SIZE + ******* Description *********** + 0x48 + 0x20 + 0x00001000 + + + FLASH_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE1_SIZE + ******* Description *********** + 0x4C + 0x20 + 0x00001000 + + + FLASH_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE2_SIZE + ******* Description *********** + 0x50 + 0x20 + 0x00001000 + + + FLASH_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE3_SIZE + ******* Description *********** + 0x54 + 0x20 + 0x00001000 + + + FLASH_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE0_ATTR + ******* Description *********** + 0x58 + 0x20 + 0x000000FF + + + SRAM_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE1_ATTR + ******* Description *********** + 0x5C + 0x20 + 0x000000FF + + + SRAM_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE2_ATTR + ******* Description *********** + 0x60 + 0x20 + 0x000000FF + + + SRAM_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE3_ATTR + ******* Description *********** + 0x64 + 0x20 + 0x000000FF + + + SRAM_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE0_ADDR + ******* Description *********** + 0x68 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE1_ADDR + ******* Description *********** + 0x6C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE2_ADDR + ******* Description *********** + 0x70 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE3_ADDR + ******* Description *********** + 0x74 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE0_SIZE + ******* Description *********** + 0x78 + 0x20 + 0x00001000 + + + SRAM_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE1_SIZE + ******* Description *********** + 0x7C + 0x20 + 0x00001000 + + + SRAM_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE2_SIZE + ******* Description *********** + 0x80 + 0x20 + 0x00001000 + + + SRAM_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE3_SIZE + ******* Description *********** + 0x84 + 0x20 + 0x00001000 + + + SRAM_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SPI_MEM_PMS_CTRL + ******* Description *********** + 0x88 + 0x20 + + + SPI_MEM_REJECT_INT + ******* Description *********** + 0 + 1 + read-only + + + SPI_MEM_REJECT_CLR + ******* Description *********** + 1 + 1 + write-only + + + SPI_MEM_REJECT_CDE + ******* Description *********** + 2 + 5 + read-only + + + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0x8C + 0x20 + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0 + 32 + read-only + + + + + SDIO_CTRL + ******* Description *********** + 0x90 + 0x20 + + + SDIO_WIN_ACCESS_EN + ******* Description *********** + 0 + 1 + read-write + + + + + REDCY_SIG0 + ******* Description *********** + 0x94 + 0x20 + + + REDCY_SIG0 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_ANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + REDCY_SIG1 + ******* Description *********** + 0x98 + 0x20 + + + REDCY_SIG1 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_NANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + FRONT_END_MEM_PD + ******* Description *********** + 0x9C + 0x20 + 0x00000055 + + + AGC_MEM_FORCE_PU + ******* Description *********** + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + ******* Description *********** + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + ******* Description *********** + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + ******* Description *********** + 3 + 1 + read-write + + + DC_MEM_FORCE_PU + ******* Description *********** + 4 + 1 + read-write + + + DC_MEM_FORCE_PD + ******* Description *********** + 5 + 1 + read-write + + + FREQ_MEM_FORCE_PU + ******* Description *********** + 6 + 1 + read-write + + + FREQ_MEM_FORCE_PD + ******* Description *********** + 7 + 1 + read-write + + + + + SPI_MEM_ECC_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00200000 + + + FLASH_PAGE_SIZE + Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SRAM_PAGE_SIZE + Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 20 + 2 + read-write + + + + + CLKGATE_FORCE_ON + ******* Description *********** + 0xA8 + 0x20 + 0x00003FFF + + + ROM_CLKGATE_FORCE_ON + ******* Description *********** + 0 + 3 + read-write + + + SRAM_CLKGATE_FORCE_ON + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_DOWN + ******* Description *********** + 0xAC + 0x20 + + + ROM_POWER_DOWN + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_DOWN + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_UP + ******* Description *********** + 0xB0 + 0x20 + 0x00003FFF + + + ROM_POWER_UP + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_UP + ******* Description *********** + 3 + 11 + read-write + + + + + RETENTION_CTRL + ******* Description *********** + 0xB4 + 0x20 + + + RETENTION_CPU_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + NOBYPASS_CPU_ISO_RST + ******* Description *********** + 27 + 1 + read-write + + + + + RETENTION_CTRL1 + ******* Description *********** + 0xB8 + 0x20 + + + RETENTION_TAG_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + + + RETENTION_CTRL2 + ******* Description *********** + 0xBC + 0x20 + 0x001FEFF0 + + + RET_ICACHE_SIZE + ******* Description *********** + 4 + 8 + read-write + + + RET_ICACHE_VLD_SIZE + ******* Description *********** + 13 + 8 + read-write + + + RET_ICACHE_START_POINT + ******* Description *********** + 22 + 8 + read-write + + + RET_ICACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL3 + ******* Description *********** + 0xC0 + 0x20 + 0x003FFFF0 + + + RET_DCACHE_SIZE + ******* Description *********** + 4 + 9 + read-write + + + RET_DCACHE_VLD_SIZE + ******* Description *********** + 13 + 9 + read-write + + + RET_DCACHE_START_POINT + ******* Description *********** + 22 + 9 + read-write + + + RET_DCACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL4 + ******* Description *********** + 0xC4 + 0x20 + 0xFFFFFFFF + + + RETENTION_INV_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + RETENTION_CTRL5 + ******* Description *********** + 0xC8 + 0x20 + + + RETENTION_DISABLE + ******* Description *********** + 0 + 1 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02101150 + + + DATE + Version control + 0 + 32 + read-write + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x70 + registers + + + APB_ADC + 65 + + + + CTRL + configure apb saradc controller + 0x0 + 0x20 + 0x407F8240 + + + SARADC_START_FORCE + enable start saradc by sw + 0 + 1 + read-write + + + SARADC_START + start saradc by sw + 1 + 1 + read-write + + + SARADC_WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 3 + 2 + read-write + + + SARADC_SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 5 + 1 + read-write + + + SARADC_SAR_CLK_GATED + enable SAR CLK gate when saradc idle + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 4 + read-write + + + SARADC_SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 19 + 4 + read-write + + + SARADC_SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 24 + 1 + read-write + + + SARADC_DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 25 + 1 + read-write + + + SARADC_DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 26 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + configure apb saradc controller + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable apb saradc limit the sample num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + configure saradc filter + 0x8 + 0x20 + + + FILTER_FACTOR1 + apb saradc factor1 + 26 + 3 + read-write + + + FILTER_FACTOR0 + apb saradc factor0 + 29 + 3 + read-write + + + + + FSM_WAIT + configure apb saradc fsm + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + the cycle which saradc controller in xpd state + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + the cycle which saradc controller in rst state + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + the cycle which saradc controller in standby state + 16 + 8 + read-write + + + + + SAR1_STATUS + saradc1 status for debug + 0x10 + 0x20 + + + SARADC_SAR1_STATUS + saradc1 status + 0 + 32 + read-only + + + + + SAR2_STATUS + saradc2 status for debug + 0x14 + 0x20 + + + SARADC_SAR2_STATUS + saradc2 status + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + configure apb saradc pattern table + 0x18 + 0x20 + + + SARADC_SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + configure apb saradc pattern table + 0x1C + 0x20 + + + SARADC_SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + configure apb saradc pattern table + 0x20 + 0x20 + + + SARADC_SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + configure apb saradc pattern table + 0x24 + 0x20 + + + SARADC_SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + configure apb saradc pattern table + 0x28 + 0x20 + + + SARADC_SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + configure apb saradc pattern table + 0x2C + 0x20 + + + SARADC_SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + configure apb saradc pattern table + 0x30 + 0x20 + + + SARADC_SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + configure apb saradc pattern table + 0x34 + 0x20 + + + SARADC_SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + APB_ADC_ARB_CTRL + configure apb saradc arbit + 0x38 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + configure apb saradc arbit + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + configure the filter1 channel + 14 + 5 + read-write + + + FILTER_CHANNEL0 + configure the filter0 channel + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + APB_SARADC1_DATA_STATUS + get apb saradc sample data + 0x40 + 0x20 + + + APB_SARADC1_DATA + apbsaradc sample data + 0 + 17 + read-only + + + + + THRES0_CTRL + configure apb saradc thres monitor + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES0_HIGH + thres0 monitor high thres + 5 + 13 + read-write + + + THRES0_LOW + thres0 monitor low thres + 18 + 13 + read-write + + + + + THRES1_CTRL + configure apb saradc thres monitor + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES1_HIGH + thres1 monitor high thres + 5 + 13 + read-write + + + THRES1_LOW + thres1 monitor low thres + 18 + 13 + read-write + + + + + THRES_CTRL + configure thres monitor enable + 0x58 + 0x20 + + + THRES_ALL_EN + enable thres0 to monitor all channel + 27 + 1 + read-write + + + THRES3_EN + no public + 28 + 1 + read-write + + + THRES2_EN + no public + 29 + 1 + read-write + + + THRES1_EN + enable thres1 + 30 + 1 + read-write + + + THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + enable interrupt + 0x5C + 0x20 + + + THRES1_LOW_INT_ENA + interrupt of thres1 low + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + interrupt of thres0 low + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + interrupt of thres1 high + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + interrupt of thres0 high + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + interrupt of sar2 done + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + interrupt of sar1 done + 31 + 1 + read-write + + + + + INT_RAW + raw of interrupt + 0x60 + 0x20 + + + THRES1_LOW_INT_RAW + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_RAW + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_RAW + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_RAW + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_ST + state of interrupt + 0x64 + 0x20 + + + THRES1_LOW_INT_ST + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_CLR + clear interrupt + 0x68 + 0x20 + + + THRES1_LOW_INT_CLR + interrupt of thres1 low + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + interrupt of thres0 low + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + interrupt of thres1 high + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + interrupt of thres0 high + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + interrupt of sar2 done + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + interrupt of sar1 done + 31 + 1 + write-only + + + + + DMA_CONF + configure apb saradc dma + 0x6C + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + APB_ADC_CLKM_CONF + configure apb saradc clock + 0x70 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + no public + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_SARADC2_DATA_STATUS + get apb saradc2 sample data + 0x78 + 0x20 + + + APB_SARADC2_DATA + apb saradc2 sample data + 0 + 17 + read-only + + + + + APB_CTRL_DATE + version + 0x3FC + 0x20 + 0x02101180 + + + APB_CTRL_DATE + version + 0 + 32 + read-write + + + + + + + DEBUG_ASSIST + Debug Assist + DEBUG_ASSIST + 0x600CE000 + + 0x0 + 0x15C + registers + + + ASSIST_DEBUG + 83 + + + + CORE_0_INTERRUPT_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTERRUPT_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x30 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_SP + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x34 + 0x20 + + + CORE_0_AREA_PC + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_UNSTABLE + core0 sp unstable configuration register + 0x38 + 0x20 + 0x0000000B + + + CORE_0_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0x3C + 0x20 + + + CORE_0_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + core0 sp region configuration regsiter + 0x40 + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_0_SP_PC + core0 sp pc status register + 0x44 + 0x20 + + + CORE_0_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGENABLE + core0 pdebug configuration register + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGENABLE + Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC + 0 + 1 + read-write + + + + + CORE_0_RCD_RECORDING + core0 pdebug status register + 0x4C + 0x20 + + + CORE_0_RCD_RECORDING + Pdebug record enable,set 1 to record core0 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGINST + core0 pdebug status register + 0x50 + 0x20 + + + CORE_0_RCD_PDEBUGINST + core0 pdebuginst + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebug status register + 0x54 + 0x20 + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebugstatus + 0 + 8 + read-only + + + + + CORE_0_RCD_PDEBUGDATA + core0 pdebug status register + 0x58 + 0x20 + + + CORE_0_RCD_PDEBUGDATA + core0_pdebugdata + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGPC + core0 pdebug status register + 0x5C + 0x20 + + + CORE_0_RCD_PDEBUGPC + core0_pdebugPC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0STAT + core0 pdebug status register + 0x60 + 0x20 + + + CORE_0_RCD_PDEBUGLS0STAT + core0_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0ADDR + core0 pdebug status register + 0x64 + 0x20 + + + CORE_0_RCD_PDEBUGLS0ADDR + core0_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0DATA + core0 pdebug status register + 0x68 + 0x20 + + + CORE_0_RCD_PDEBUGLS0DATA + core0_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_0_RCD_SP + core0 pdebug status register + 0x6C + 0x20 + + + CORE_0_RCD_SP + core0_stack pointer + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x70 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x74 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x78 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x7C + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + core0 bus busy status regsiter + 0x80 + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + core0 bus busy status regsiter + 0x84 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + core0 bus busy configuration regsiter + 0x88 + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + core0 bus busy configuration regsiter + 0x8C + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_INTERRUPT_ENA + Core1 monitor enable configuration register + 0x90 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_RAW + Core1 monitor interrupt status register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTERRUPT_RLS + Core1 monitor interrupt enable register + 0x98 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_CLR + Core1 monitor interrupt clr register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 addr configuration register + 0xB0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 addr configuration register + 0xB4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 addr configuration register + 0xB8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 addr configuration register + 0xBC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + Core1 area sp status register + 0xC0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + Core1 area pc status register + 0xC4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_UNSTABLE + Core1 sp unstable configuration register + 0xC8 + 0x20 + 0x0000000B + + + CORE_1_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_1_SP_MIN + Core1 sp region configuration regsiter + 0xCC + 0x20 + + + CORE_1_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + Core1 sp region configuration regsiter + 0xD0 + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_1_SP_PC + Core1 sp pc status register + 0xD4 + 0x20 + + + CORE_1_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGENABLE + Core1 pdebug configuration register + 0xD8 + 0x20 + + + CORE_1_RCD_PDEBUGENABLE + Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC + 0 + 1 + read-write + + + + + CORE_1_RCD_RECORDING + Core1 pdebug status register + 0xDC + 0x20 + + + CORE_1_RCD_RECORDING + Pdebug record enable,set 1 to record Core1 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGINST + Core1 pdebug status register + 0xE0 + 0x20 + + + CORE_1_RCD_PDEBUGINST + Core1 pdebuginst + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebug status register + 0xE4 + 0x20 + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebugstatus + 0 + 8 + read-only + + + + + CORE_1_RCD_PDEBUGDATA + Core1 pdebug status register + 0xE8 + 0x20 + + + CORE_1_RCD_PDEBUGDATA + Core1_pdebugdata + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGPC + Core1 pdebug status register + 0xEC + 0x20 + + + CORE_1_RCD_PDEBUGPC + Core1_pdebugPC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0STAT + Core1 pdebug status register + 0xF0 + 0x20 + + + CORE_1_RCD_PDEBUGLS0STAT + Core1_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1 pdebug status register + 0xF4 + 0x20 + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0DATA + Core1 pdebug status register + 0xF8 + 0x20 + + + CORE_1_RCD_PDEBUGLS0DATA + Core1_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_1_RCD_SP + Core1 pdebug status register + 0xFC + 0x20 + + + CORE_1_RCD_SP + Core1_stack pointer + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x100 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x104 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x108 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x10C + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + Core1 bus busy status regsiter + 0x110 + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + Core1 bus busy status regsiter + 0x114 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + Core1 bus busy status regsiter + 0x118 + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + Core1 bus busy status regsiter + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + bus busy configuration register + 0x120 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + busy monitor window cycle + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + bus busy configuration register + 0x124 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt + 0 + 20 + read-write + + + + + LOG_SETTING + log set register + 0x128 + 0x20 + 0x00000040 + + + LOG_ENA + bus moniter enable: [0]Core1,[1]core1,[2]dma + 0 + 3 + read-write + + + LOG_MODE + check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word + 3 + 3 + read-write + + + LOG_MEM_LOOP_ENABLE + mem_loop enable,1 means that loop write + 6 + 1 + read-write + + + + + LOG_DATA_0 + log check data register + 0x12C + 0x20 + + + LOG_DATA_0 + check data0 + 0 + 32 + read-write + + + + + LOG_DATA_1 + log check data register + 0x130 + 0x20 + + + LOG_DATA_1 + check data1 + 0 + 32 + read-write + + + + + LOG_DATA_2 + log check data register + 0x134 + 0x20 + + + LOG_DATA_2 + check data2 + 0 + 32 + read-write + + + + + LOG_DATA_3 + log check data register + 0x138 + 0x20 + + + LOG_DATA_3 + check data3 + 0 + 32 + read-write + + + + + LOG_DATA_MASK + log check data mask register + 0x13C + 0x20 + + + LOG_DATA_SIZE + data mask + 0 + 16 + read-write + + + + + LOG_MIN + log check region configuration register + 0x140 + 0x20 + + + LOG_MIN + check region min addr + 0 + 32 + read-write + + + + + LOG_MAX + log check region configuration register + 0x144 + 0x20 + + + LOG_MAX + check region max addr + 0 + 32 + read-write + + + + + LOG_MEM_START + log mem region configuration register + 0x148 + 0x20 + + + LOG_MEM_START + mem start addr + 0 + 32 + read-write + + + + + LOG_MEM_END + log mem region configuration register + 0x14C + 0x20 + + + LOG_MEM_END + mem end addr + 0 + 32 + read-write + + + + + LOG_MEM_WRITING_ADDR + log mem addr status register + 0x150 + 0x20 + + + LOG_MEM_WRITING_ADDR + mem current addr, it means next writing addr + 0 + 32 + read-only + + + + + LOG_MEM_FULL_FLAG + log mem status register + 0x154 + 0x20 + + + LOG_MEM_FULL_FLAG + when it's 1,show that mem write loop morte than one time. + 0 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02003040 + + + DATE + version register + 0 + 28 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x320 + registers + + + DMA_IN_CH0 + 66 + + + DMA_IN_CH1 + 67 + + + DMA_IN_CH2 + 68 + + + DMA_IN_CH3 + 69 + + + DMA_IN_CH4 + 70 + + + DMA_OUT_CH0 + 71 + + + DMA_OUT_CH1 + 72 + + + DMA_OUT_CH2 + 73 + + + DMA_OUT_CH3 + 74 + + + DMA_OUT_CH4 + 75 + + + APB_PMS_MONITOR_VIOLATE + 84 + + + DMA_EXTMEM_REJECT + 98 + + + + 5 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x0 + 0x20 + + + IN_RST + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + 5 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x4 + 0x20 + 0x0000000C + + + DMA_INFIFO_FULL_THRS + This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. + 0 + 12 + read-write + + + IN_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + IN_EXT_MEM_BK_SIZE + Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + IN_INT_RAW_CH%s + Raw status interrupt of Rx channel 0 + 0x8 + 0x20 + + + IN_DONE + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_FULL_WM + The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. + 5 + 1 + read-only + + + INFIFO_OVF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 6 + 1 + read-only + + + INFIFO_UDF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 7 + 1 + read-only + + + INFIFO_OVF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. + 8 + 1 + read-only + + + INFIFO_UDF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. + 9 + 1 + read-only + + + + + 5 + 0xC0 + IN_INT_ST_CH%s + Masked interrupt of Rx channel 0 + 0xC + 0x20 + + + IN_DONE + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_FULL_WM + The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L1 + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L1 + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_OVF_L3 + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_UDF_L3 + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 5 + 0xC0 + IN_INT_ENA_CH%s + Interrupt enable bits of Rx channel 0 + 0x10 + 0x20 + + + IN_DONE + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_FULL_WM + The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L1 + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L1 + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_OVF_L3 + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_UDF_L3 + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 5 + 0xC0 + IN_INT_CLR_CH%s + Interrupt clear bits of Rx channel 0 + 0x14 + 0x20 + + + IN_DONE + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + DMA_INFIFO_FULL_WM + Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L1 + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L1 + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_OVF_L3 + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_UDF_L3 + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + 5 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x0F00003A + + + INFIFO_FULL_L1 + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1 + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_FULL_L2 + L2 Rx FIFO full signal for Rx channel 0. + 2 + 1 + read-only + + + INFIFO_EMPTY_L2 + L2 Rx FIFO empty signal for Rx channel 0. + 3 + 1 + read-only + + + INFIFO_FULL_L3 + L3 Rx FIFO full signal for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_EMPTY_L3 + L3 Rx FIFO empty signal for Rx channel 0. + 5 + 1 + read-only + + + INFIFO_CNT_L1 + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 6 + 6 + read-only + + + INFIFO_CNT_L2 + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 12 + 7 + read-only + + + INFIFO_CNT_L3 + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 19 + 5 + read-only + + + IN_REMAIN_UNDER_1B_L3 + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_2B_L3 + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_3B_L3 + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_4B_L3 + reserved + 27 + 1 + read-only + + + IN_BUF_HUNGRY + reserved + 28 + 1 + read-only + + + + + 5 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + 5 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x01100000 + + + INLINK_ADDR + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 5 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x24 + 0x20 + + + INLINK_DSCR_ADDR + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE + reserved + 18 + 2 + read-only + + + IN_STATE + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x28 + 0x20 + + + IN_SUC_EOF_DES_ADDR + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x2C + 0x20 + + + IN_ERR_EOF_DES_ADDR + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x30 + 0x20 + + + INLINK_DSCR + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_BF0 + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_WIGHT_CH%s + Weight register of Rx channel 0 + 0x3C + 0x20 + 0x00000F00 + + + RX_WEIGHT + The weight of Rx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x44 + 0x20 + + + RX_PRI + The priority of Rx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x48 + 0x20 + 0x0000003F + + + PERI_IN_SEL + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + 5 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 0 + 0x60 + 0x20 + 0x00000008 + + + OUT_RST + This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + 5 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0x64 + 0x20 + + + OUT_CHECK_OWNER + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + OUT_EXT_MEM_BK_SIZE + Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + OUT_INT_RAW_CH%s + Raw status interrupt of Tx channel 0 + 0x68 + 0x20 + + + OUT_DONE + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-only + + + OUT_EOF + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1 + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-only + + + OUTFIFO_OVF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. + 6 + 1 + read-only + + + OUTFIFO_UDF_L3 + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. + 7 + 1 + read-only + + + + + 5 + 0xC0 + OUT_INT_ST_CH%s + Masked interrupt of Tx channel 0 + 0x6C + 0x20 + + + OUT_DONE + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1 + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1 + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L3 + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L3 + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-only + + + + + 5 + 0xC0 + OUT_INT_ENA_CH%s + Interrupt enable bits of Tx channel 0 + 0x70 + 0x20 + + + OUT_DONE + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1 + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1 + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L3 + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L3 + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-write + + + + + 5 + 0xC0 + OUT_INT_CLR_CH%s + Interrupt clear bits of Tx channel 0 + 0x74 + 0x20 + + + OUT_DONE + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1 + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1 + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L3 + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L3 + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + write-only + + + + + 5 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0x78 + 0x20 + 0x0780002A + + + OUTFIFO_FULL_L1 + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L1 + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_FULL_L2 + L2 Tx FIFO full signal for Tx channel 0. + 2 + 1 + read-only + + + OUTFIFO_EMPTY_L2 + L2 Tx FIFO empty signal for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_FULL_L3 + L3 Tx FIFO full signal for Tx channel 0. + 4 + 1 + read-only + + + OUTFIFO_EMPTY_L3 + L3 Tx FIFO empty signal for Tx channel 0. + 5 + 1 + read-only + + + OUTFIFO_CNT_L1 + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 6 + 5 + read-only + + + OUTFIFO_CNT_L2 + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 11 + 7 + read-only + + + OUTFIFO_CNT_L3 + The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. + 18 + 5 + read-only + + + OUT_REMAIN_UNDER_1B_L3 + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_L3 + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_L3 + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_L3 + reserved + 26 + 1 + read-only + + + + + 5 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0x7C + 0x20 + + + OUTFIFO_WDATA + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + 5 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0x80 + 0x20 + 0x00800000 + + + OUTLINK_ADDR + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 5 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0x84 + 0x20 + + + OUTLINK_DSCR_ADDR + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE + reserved + 18 + 2 + read-only + + + OUT_STATE + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0x88 + 0x20 + + + OUT_EOF_DES_ADDR + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0x8C + 0x20 + + + OUT_EOF_BFR_DES_ADDR + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0x90 + 0x20 + + + OUTLINK_DSCR + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0x94 + 0x20 + + + OUTLINK_DSCR_BF0 + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0x98 + 0x20 + + + OUTLINK_DSCR_BF1 + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_WIGHT_CH%s + Weight register of Rx channel 0 + 0x9C + 0x20 + 0x00000F00 + + + TX_WEIGHT + The weight of Tx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xA4 + 0x20 + + + TX_PRI + The priority of Tx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0xA8 + 0x20 + 0x0000003F + + + PERI_OUT_SEL + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + AHB_TEST + reserved + 0x3C0 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + PD_CONF + reserved + 0x3C4 + 0x20 + 0x00000020 + + + DMA_RAM_FORCE_PD + Set this bit to force power down DMA internal memory. + 4 + 1 + read-write + + + DMA_RAM_FORCE_PU + Set this bit to force power up DMA internal memory + 5 + 1 + read-write + + + DMA_RAM_CLK_FO + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + MISC_CONF + MISC register + 0x3C8 + 0x20 + + + AHBM_RST_INTER + Set this bit, then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + AHBM_RST_EXTER + Set this bit, then clear this bit to reset the external ahb FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + 5 + 0x8 + IN_SRAM_SIZE_CH%s + Receive L2 FIFO depth of Rx channel 0 + 0x3CC + 0x20 + 0x0000000E + + + IN_SIZE + This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + 5 + 0x8 + OUT_SRAM_SIZE_CH%s + Transmit L2 FIFO depth of Tx channel 0 + 0x3D0 + 0x20 + 0x0000000E + + + OUT_SIZE + This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + EXTMEM_REJECT_ADDR + Reject address accessing external RAM + 0x3F4 + 0x20 + + + EXTMEM_REJECT_ADDR + This register store the first address rejected by permission control when accessing external RAM. + 0 + 32 + read-only + + + + + EXTMEM_REJECT_ST + Reject status accessing external RAM + 0x3F8 + 0x20 + + + EXTMEM_REJECT_ATRR + The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE. + 0 + 2 + read-only + + + EXTMEM_REJECT_CHANNEL_NUM + The register indicate the reject accessing from which channel. + 2 + 4 + read-only + + + EXTMEM_REJECT_PERI_NUM + This register indicate reject accessing from which peripheral. + 6 + 6 + read-only + + + + + EXTMEM_REJECT_INT_RAW + Raw interrupt status of external RAM permission + 0x3FC + 0x20 + + + EXTMEM_REJECT_INT_RAW + The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control. + 0 + 1 + read-only + + + + + EXTMEM_REJECT_INT_ST + Masked interrupt status of external RAM permission + 0x400 + 0x20 + + + EXTMEM_REJECT_INT_ST + The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-only + + + + + EXTMEM_REJECT_INT_ENA + Interrupt enable bits of external RAM permission + 0x404 + 0x20 + + + EXTMEM_REJECT_INT_ENA + The interrupt enable bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-write + + + + + EXTMEM_REJECT_INT_CLR + Interrupt clear bits of external RAM permission + 0x408 + 0x20 + + + EXTMEM_REJECT_INT_CLR + Set this bit to clear the EXTMEM_REJECT_INT interrupt. + 0 + 1 + write-only + + + + + DATE + Version control register + 0x40C + 0x20 + 0x02101180 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + DS + Digital Signature + DS + 0x6003D000 + + 0x0 + 0xA5C + registers + + + + 1584 + 0x1 + C_MEM[%s] + Memory C + 0x0 + 0x8 + + + 4 + 0x4 + IV_%s + IV block data + 0x630 + 0x20 + + + IV_0 + Stores IV block data + 0 + 32 + read-write + + + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0xA00 + 0x8 + + + SET_START + Activates the DS peripheral + 0xE00 + 0x20 + + + SET_START + Write 1 to this register to active the DS peripheral + 0 + 1 + write-only + + + + + SET_ME + Starts DS operation + 0xE04 + 0x20 + + + SET_ME + Write 1 to this register to start DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + Ends DS operation + 0xE08 + 0x20 + + + SET_FINISH + Write 1 to this register to end DS operation. + 0 + 1 + write-only + + + + + QUERY_BUSY + Status of the DS perihperal + 0xE0C + 0x20 + + + QUERY_BUSY + Stores the status of the DS peripheral. 1: The DS peripheral is busy. 0: The DS peripheral is idle. + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + Checks the reason why DS_KEY is not ready + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + 1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY from the HMAC peripheral. (The biggest value is 15). 0: HMAC is not activated. + 0 + 4 + read-only + + + + + QUERY_CHECK + Queries DS check result + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1: The MD check fails. 0: The MD check passes. + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1: The padding check fails. 0: The padding check passes. + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20191217 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x60007000 + + 0x0 + 0x1CC + registers + + + EFUSE + 36 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + The content of the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + The content of the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + The content of the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + The content of the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + The content of the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + The content of the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + The content of the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + The content of the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + The content of the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Disable programming of individual eFuses. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Set this bit to disable reading from BlOCK4-10. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT + Set this bit to disable boot from RTC RAM. + 7 + 1 + read-only + + + DIS_ICACHE + Set this bit to disable Icache. + 8 + 1 + read-only + + + DIS_DCACHE + Set this bit to disable Dcache. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE + Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Set this bit to disable the function that forces chip into download mode. + 12 + 1 + read-only + + + DIS_USB + Set this bit to disable USB function. + 13 + 1 + read-only + + + DIS_CAN + Set this bit to disable CAN function. + 14 + 1 + read-only + + + DIS_APP_CPU + Disable app cpu. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Set this bit to disable flash encryption when in download boot modes. + 20 + 1 + read-only + + + USB_DREFH + Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. + 21 + 2 + read-only + + + USB_DREFL + Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Set this bit to exchange USB D+ and D- pins. + 25 + 1 + read-only + + + EXT_PHY_ENABLE + Set this bit to enable external PHY. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE + Bluetooth GPIO signal output security level control. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM + SPI regulator switches current limit mode. + 29 + 1 + read-only + + + VDD_SPI_DREFH + SPI regulator high voltage reference. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + VDD_SPI_DREFM + SPI regulator medium voltage reference. + 0 + 2 + read-only + + + VDD_SPI_DREFL + SPI regulator low voltage reference. + 2 + 2 + read-only + + + VDD_SPI_XPD + SPI regulator power up signal. + 4 + 1 + read-only + + + VDD_SPI_TIEH + SPI regulator output is short connected to VDD3P3_RTC_IO. + 5 + 1 + read-only + + + VDD_SPI_FORCE + Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT + Set SPI regulator to 0 to configure init[1:0]=0. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM + Set SPI regulator to 1 to enable output current limit. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM + Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + 9 + 3 + read-only + + + VDD_SPI_INIT + Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + 12 + 2 + read-only + + + VDD_SPI_DCAP + Prevents SPI regulator from overshoot. + 14 + 2 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Set this bit to enable revoking first secure boot key. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Set this bit to enable revoking second secure boot key. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Set this bit to enable revoking third secure boot key. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + + + KEY_PURPOSE_2 + Purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Purpose of Key5. + 12 + 4 + read-only + + + RPT4_RESERVED0 + Reserved (used for four backups method). + 16 + 4 + read-only + + + SECURE_BOOT_EN + Set this bit to enable secure boot. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Set this bit to enable revoking aggressive secure boot. + 21 + 1 + read-only + + + DIS_USB_JTAG + Set this bit to disable function of usb switch to jtag in module of usb device. + 22 + 1 + read-only + + + DIS_USB_DEVICE + Set this bit to disable usb device. + 23 + 1 + read-only + + + STRAP_JTAG_SEL + Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + 24 + 1 + read-only + + + USB_PHY_SEL + This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE + Sample delay configuration of power glitch. + 26 + 2 + read-only + + + FLASH_TPUW + Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT + Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). + 1 + 1 + read-only + + + UART_PRINT_CHANNEL + Selectes the default UART print channel. 0: UART0. 1: UART1. + 2 + 1 + read-only + + + FLASH_ECC_MODE + Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE + Set this bit to disable UART download mode through USB. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + 6 + 2 + read-only + + + PIN_POWER_SELECTION + GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + 8 + 1 + read-only + + + FLASH_TYPE + Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE + Set Flash page size. + 10 + 2 + read-only + + + FLASH_ECC_EN + Set 1 to enable ECC for flash boot. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Set this bit to force ROM code to send a resume command during SPI boot. + 13 + 1 + read-only + + + SECURE_VERSION + Secure version (used by ESP-IDF anti-rollback feature). + 14 + 16 + read-only + + + POWERGLITCH_EN + Set this bit to enable power glitch function. + 30 + 1 + read-only + + + RPT4_RESERVED1 + Reserved (used for four backups method). + 31 + 1 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED2 + Reserved (used for four backups method). + 0 + 24 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register 0. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register 1. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + SPI_PAD_CONF_0 + Stores the zeroth part of SPI_PAD_CONF. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register 2. + 0x4C + 0x20 + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register 3. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the fist 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register 4. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the fist 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register 5. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register 0 of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register 1 of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register 2 of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register 3 of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register 4 of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register 5 of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register 6 of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register 7 of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register 0 of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register 1 of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register 2 of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register 3 of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register 4 of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register 5 of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register 6 of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register 7 of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register 0 of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register 1 of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register 2 of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register 3 of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register 4 of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register 5 of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register 6 of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register 7 of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register 0 of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register 1 of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register 2 of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register 3 of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register 4 of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register 5 of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register 6 of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register 7 of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register 0 of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register 1 of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register 2 of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register 3 of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register 4 of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register 5 of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register 6 of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register 7 of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register 0 of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register 1 of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register 2 of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register 3 of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register 4 of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register 5 of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register 6 of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register 7 of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register 0 of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register 1 of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register 2 of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register 3 of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register 4 of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register 5 of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register 6 of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register 7 of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register 0 of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register 2 of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register 3 of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register 4 of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register 5 of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register 6 of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register 7 of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register 0 of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 1st 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register 2 of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 2nd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register 3 of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 3rd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register 4 of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 4th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register 5 of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 5th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register 6 of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 6th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register 7 of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 7th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + DIS_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + DIS_USB_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + DIS_CAN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 1 + read-only + + + DIS_APP_CPU_ERR + If any bits in this filed are 1, then it indicates a programming error. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + USB_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 2 + read-only + + + USB_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + EXT_PHY_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 29 + 1 + read-only + + + VDD_SPI_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + VDD_SPI_DREFM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 2 + read-only + + + VDD_SPI_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 2 + read-only + + + VDD_SPI_XPD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + VDD_SPI_TIEH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + VDD_SPI_FORCE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 3 + read-only + + + VDD_SPI_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 2 + read-only + + + VDD_SPI_DCAP_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 2 + read-only + + + WDT_DELAY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 4 + read-only + + + RPT4_RESERVED0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 4 + read-only + + + SECURE_BOOT_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + DIS_USB_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + DIS_USB_DEVICE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + STRAP_JTAG_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 1 + read-only + + + USB_PHY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 2 + read-only + + + FLASH_TPUW_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 1 + read-only + + + FLASH_ECC_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 2 + read-only + + + PIN_POWER_SELECTION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + FLASH_TYPE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 2 + read-only + + + FLASH_ECC_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 16 + read-only + + + POWERGLITCH_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 1 + read-only + + + RPT4_RESERVED1_ERR + Reserved. + 31 + 1 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 24 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit and force to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + REPEAT_ERR_CNT + Indicates the number of error bits during programming BLOCK0. + 10 + 8 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12000000 + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00288000 + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F8 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02101290 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C4000 + + 0x0 + 0x17C + registers + + + + DCACHE_CTRL + ******* Description *********** + 0x0 + 0x20 + + + DCACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + DCACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 32KB, 1: 64KB + 2 + 1 + read-write + + + DCACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes + 3 + 2 + read-write + + + + + DCACHE_CTRL1 + ******* Description *********** + 0x4 + 0x20 + 0x00000003 + + + DCACHE_SHUT_CORE0_BUS + The bit is used to disable core0 dbus, 0: enable, 1: disable + 0 + 1 + read-write + + + DCACHE_SHUT_CORE1_BUS + The bit is used to disable core1 dbus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + DCACHE_TAG_POWER_CTRL + ******* Description *********** + 0x8 + 0x20 + 0x00000005 + + + DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PD + The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PU + The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + DCACHE_PRELOCK_CTRL + ******* Description *********** + 0xC + 0x20 + + + DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + DCACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x10 + 0x20 + + + DCACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x14 + 0x20 + + + DCACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x18 + 0x20 + + + DCACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + DCACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + DCACHE_LOCK_CTRL + ******* Description *********** + 0x1C + 0x20 + 0x00000004 + + + DCACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + DCACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + DCACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + DCACHE_LOCK_ADDR + ******* Description *********** + 0x20 + 0x20 + + + DCACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_LOCK_SIZE + ******* Description *********** + 0x24 + 0x20 + + + DCACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_SYNC_CTRL + ******* Description *********** + 0x28 + 0x20 + 0x00000001 + + + DCACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + DCACHE_WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. + 1 + 1 + read-write + + + DCACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + 2 + 1 + read-write + + + DCACHE_SYNC_DONE + The bit is used to indicate clean/writeback/invalidate operation is finished. + 3 + 1 + read-only + + + + + DCACHE_SYNC_ADDR + ******* Description *********** + 0x2C + 0x20 + + + DCACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_SYNC_SIZE + ******* Description *********** + 0x30 + 0x20 + + + DCACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + DCACHE_OCCUPY_CTRL + ******* Description *********** + 0x34 + 0x20 + 0x00000002 + + + DCACHE_OCCUPY_ENA + The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation. + 0 + 1 + read-write + + + DCACHE_OCCUPY_DONE + The bit is used to indicate occupy operation is finished. + 1 + 1 + read-only + + + + + DCACHE_OCCUPY_ADDR + ******* Description *********** + 0x38 + 0x20 + + + DCACHE_OCCUPY_ADDR + The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_OCCUPY_SIZE + ******* Description *********** + 0x3C + 0x20 + + + DCACHE_OCCUPY_SIZE + The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_PRELOAD_CTRL + ******* Description *********** + 0x40 + 0x20 + 0x00000002 + + + DCACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + DCACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + DCACHE_PRELOAD_ADDR + ******* Description *********** + 0x44 + 0x20 + + + DCACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_PRELOAD_SIZE + ******* Description *********** + 0x48 + 0x20 + + + DCACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + DCACHE_AUTOLOAD_CTRL + ******* Description *********** + 0x4C + 0x20 + 0x00000008 + + + DCACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + DCACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + DCACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + DCACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + DCACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + DCACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + DCACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in dcache. + 9 + 1 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0x50 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0x54 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0x58 + 0x20 + + + DCACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0x5C + 0x20 + + + DCACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + ICACHE_CTRL + ******* Description *********** + 0x60 + 0x20 + + + ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + ICACHE_WAY_MODE + The bit is used to configure cache way mode.0: 4-way, 1: 8-way + 1 + 1 + read-write + + + ICACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 16KB, 1: 32KB + 2 + 1 + read-write + + + ICACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + 3 + 1 + read-write + + + + + ICACHE_CTRL1 + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + ICACHE_SHUT_CORE0_BUS + The bit is used to disable core0 ibus, 0: enable, 1: disable + 0 + 1 + read-write + + + ICACHE_SHUT_CORE1_BUS + The bit is used to disable core1 ibus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + ICACHE_TAG_POWER_CTRL + ******* Description *********** + 0x68 + 0x20 + 0x00000005 + + + ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + ICACHE_PRELOCK_CTRL + ******* Description *********** + 0x6C + 0x20 + + + ICACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + ICACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + ICACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x70 + 0x20 + + + ICACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x74 + 0x20 + + + ICACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x78 + 0x20 + + + ICACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + ICACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + ICACHE_LOCK_CTRL + ******* Description *********** + 0x7C + 0x20 + 0x00000004 + + + ICACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + ICACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + ICACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + ICACHE_LOCK_ADDR + ******* Description *********** + 0x80 + 0x20 + + + ICACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_LOCK_SIZE + ******* Description *********** + 0x84 + 0x20 + + + ICACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + ICACHE_SYNC_CTRL + ******* Description *********** + 0x88 + 0x20 + 0x00000001 + + + ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + ICACHE_SYNC_DONE + The bit is used to indicate invalidate operation is finished. + 1 + 1 + read-only + + + + + ICACHE_SYNC_ADDR + ******* Description *********** + 0x8C + 0x20 + + + ICACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_SYNC_SIZE + ******* Description *********** + 0x90 + 0x20 + + + ICACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + ICACHE_PRELOAD_CTRL + ******* Description *********** + 0x94 + 0x20 + 0x00000002 + + + ICACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + ICACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + ICACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + ICACHE_PRELOAD_ADDR + ******* Description *********** + 0x98 + 0x20 + + + ICACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_PRELOAD_SIZE + ******* Description *********** + 0x9C + 0x20 + + + ICACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + ICACHE_AUTOLOAD_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00000008 + + + ICACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + ICACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + ICACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + ICACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + ICACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + ICACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + ICACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + ICACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in icache. + 9 + 1 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0xA4 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0xA8 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0xAC + 0x20 + + + ICACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0xB0 + 0x20 + + + ICACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + IBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xB4 + 0x20 + 0x44000000 + + + IBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + IBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xB8 + 0x20 + 0x47FFFFFF + + + IBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xBC + 0x20 + + + DBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xC0 + 0x20 + + + DBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + CACHE_ACS_CNT_CLR + ******* Description *********** + 0xC4 + 0x20 + + + DCACHE_ACS_CNT_CLR + The bit is used to clear dcache counter. + 0 + 1 + write-only + + + ICACHE_ACS_CNT_CLR + The bit is used to clear icache counter. + 1 + 1 + write-only + + + + + IBUS_ACS_MISS_CNT + ******* Description *********** + 0xC8 + 0x20 + + + IBUS_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus access flash/spiram. + 0 + 32 + read-only + + + + + IBUS_ACS_CNT + ******* Description *********** + 0xCC + 0x20 + + + IBUS_ACS_CNT + The bits are used to count the number of ibus access flash/spiram through icache. + 0 + 32 + read-only + + + + + DBUS_ACS_FLASH_MISS_CNT + ******* Description *********** + 0xD0 + 0x20 + + + DBUS_ACS_FLASH_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access flash. + 0 + 32 + read-only + + + + + DBUS_ACS_SPIRAM_MISS_CNT + ******* Description *********** + 0xD4 + 0x20 + + + DBUS_ACS_SPIRAM_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access spiram. + 0 + 32 + read-only + + + + + DBUS_ACS_CNT + ******* Description *********** + 0xD8 + 0x20 + + + DBUS_ACS_CNT + The bits are used to count the number of dbus access flash/spiram through dcache. + 0 + 32 + read-only + + + + + CACHE_ILG_INT_ENA + ******* Description *********** + 0xDC + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 0 + 1 + read-write + + + ICACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 1 + 1 + read-write + + + DCACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 2 + 1 + read-write + + + DCACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 3 + 1 + read-write + + + DCACHE_WRITE_FLASH_INT_ENA + The bit is used to enable interrupt by dcache trying to write flash. + 4 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 5 + 1 + read-write + + + DCACHE_OCCUPY_EXC_INT_ENA + The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 7 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 8 + 1 + read-write + + + + + CACHE_ILG_INT_CLR + ******* Description *********** + 0xE0 + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 0 + 1 + write-only + + + ICACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 1 + 1 + write-only + + + DCACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 2 + 1 + write-only + + + DCACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 3 + 1 + write-only + + + DCACHE_WRITE_FLASH_INT_CLR + The bit is used to clear interrupt by dcache trying to write flash. + 4 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 5 + 1 + write-only + + + DCACHE_OCCUPY_EXC_INT_CLR + The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 7 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 8 + 1 + write-only + + + + + CACHE_ILG_INT_ST + ******* Description *********** + 0xE4 + 0x20 + + + ICACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 0 + 1 + read-only + + + ICACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 1 + 1 + read-only + + + DCACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 2 + 1 + read-only + + + DCACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 3 + 1 + read-only + + + DCACHE_WRITE_FLASH_ST + The bit is used to indicate interrupt by dcache trying to write flash. + 4 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 5 + 1 + read-only + + + DCACHE_OCCUPY_EXC_ST + The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-only + + + IBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + 7 + 1 + read-only + + + IBUS_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + 8 + 1 + read-only + + + DBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + 9 + 1 + read-only + + + DBUS_ACS_FLASH_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash miss counter overflow. + 10 + 1 + read-only + + + DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access spiram miss counter overflow. + 11 + 1 + read-only + + + + + CORE0_ACS_CACHE_INT_ENA + ******* Description *********** + 0xE8 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE0_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE0_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE0_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE0_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE0_ACS_CACHE_INT_CLR + ******* Description *********** + 0xEC + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE0_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE0_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE0_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE0_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE0_ACS_CACHE_INT_ST + ******* Description *********** + 0xF0 + 0x20 + + + CORE0_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE0_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE0_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE0_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE0_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE1_ACS_CACHE_INT_ENA + ******* Description *********** + 0xF4 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE1_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE1_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE1_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE1_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE1_ACS_CACHE_INT_CLR + ******* Description *********** + 0xF8 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE1_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE1_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE1_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE1_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE1_ACS_CACHE_INT_ST + ******* Description *********** + 0xFC + 0x20 + + + CORE1_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE1_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE1_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE1_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE1_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE0_DBUS_REJECT_ST + ******* Description *********** + 0x100 + 0x20 + + + CORE0_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE0_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_DBUS_REJECT_VADDR + ******* Description *********** + 0x104 + 0x20 + 0xFFFFFFFF + + + CORE0_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE0_IBUS_REJECT_ST + ******* Description *********** + 0x108 + 0x20 + + + CORE0_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE0_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_IBUS_REJECT_VADDR + ******* Description *********** + 0x10C + 0x20 + 0xFFFFFFFF + + + CORE0_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_DBUS_REJECT_ST + ******* Description *********** + 0x110 + 0x20 + + + CORE1_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE1_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_DBUS_REJECT_VADDR + ******* Description *********** + 0x114 + 0x20 + 0xFFFFFFFF + + + CORE1_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_IBUS_REJECT_ST + ******* Description *********** + 0x118 + 0x20 + + + CORE1_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE1_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_IBUS_REJECT_VADDR + ******* Description *********** + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE1_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CACHE_MMU_FAULT_CONTENT + ******* Description *********** + 0x120 + 0x20 + + + CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 16 + read-only + + + CACHE_MMU_FAULT_CODE + The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. + 16 + 4 + read-only + + + + + CACHE_MMU_FAULT_VADDR + ******* Description *********** + 0x124 + 0x20 + + + CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + CACHE_WRAP_AROUND_CTRL + ******* Description *********** + 0x128 + 0x20 + + + CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + CACHE_SRAM_RD_WRAP_AROUND + The bit is used to enable wrap around mode when read data from spiram. + 1 + 1 + read-write + + + + + CACHE_MMU_POWER_CTRL + ******* Description *********** + 0x12C + 0x20 + 0x00000005 + + + CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + CACHE_STATE + ******* Description *********** + 0x130 + 0x20 + + + ICACHE_STATE + The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + DCACHE_STATE + The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 12 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + ******* Description *********** + 0x134 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + ******* Description *********** + 0x138 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_MANUAL_CRYPT + The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_AUTO_CRYPT + The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_CRYPT + The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_BRIDGE_ARBITER_CTRL + ******* Description *********** + 0x13C + 0x20 + + + ALLOC_WB_HOLD_ARBITER + Reserved + 0 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + ******* Description *********** + 0x140 + 0x20 + + + ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + DCACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by dcache pre-load done. + 3 + 1 + read-only + + + DCACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by dcache pre-load done. + 4 + 1 + read-write + + + DCACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by dcache pre-load done. + 5 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + ******* Description *********** + 0x144 + 0x20 + + + ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + DCACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by dcache sync done. + 3 + 1 + read-only + + + DCACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by dcache sync done. + 4 + 1 + read-write + + + DCACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by dcache sync done. + 5 + 1 + write-only + + + + + CACHE_MMU_OWNER + ******* Description *********** + 0x148 + 0x20 + + + CACHE_MMU_OWNER + The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved. + 0 + 24 + read-write + + + + + CACHE_CONF_MISC + ******* Description *********** + 0x14C + 0x20 + 0x00000007 + + + CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + CACHE_TRACE_ENA + The bit is used to enable cache trace function. + 2 + 1 + read-write + + + + + DCACHE_FREEZE + ******* Description *********** + 0x150 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable dcache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate dcache freeze success + 2 + 1 + read-only + + + + + ICACHE_FREEZE + ******* Description *********** + 0x154 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable icache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate icache freeze success + 2 + 1 + read-only + + + + + ICACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x158 + 0x20 + 0x00000001 + + + ICACHE_ATOMIC_OPERATE_ENA + The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + DCACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x15C + 0x20 + 0x00000001 + + + DCACHE_ATOMIC_OPERATE_ENA + The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + CACHE_REQUEST + ******* Description *********** + 0x160 + 0x20 + + + BYPASS + The bit is used to disable request recording which could cause performance issue + 0 + 1 + read-write + + + + + CLOCK_GATE + ******* Description *********** + 0x164 + 0x20 + 0x00000001 + + + CLK_EN + Reserved + 0 + 1 + read-write + + + + + CACHE_TAG_OBJECT_CTRL + ******* Description *********** + 0x180 + 0x20 + + + ICACHE_TAG_OBJECT + Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + DCACHE_TAG_OBJECT + Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + + + CACHE_TAG_WAY_OBJECT + ******* Description *********** + 0x184 + 0x20 + + + CACHE_TAG_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7. + 0 + 3 + read-write + + + + + CACHE_VADDR + ******* Description *********** + 0x188 + 0x20 + + + CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + CACHE_TAG_CONTENT + ******* Description *********** + 0x18C + 0x20 + + + CACHE_TAG_CONTENT + This is a constant place where we can write data to or read data from the tag memory on the specified cache. + 0 + 32 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02012310 + + + DATE + version information. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x634 + registers + + + GPIO + 16 + + + GPIO_NMI + 17 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-53 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-53 + 0 + 22 + + + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0 + 22 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0 + 22 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-53 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-53 + 0 + 22 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0 + 22 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0 + 22 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-write + + + + + IN1 + GPIO input register for GPIO32-53 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-53 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0 + 22 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0 + 22 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0x68 + 0x20 + + + PROCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + PCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0x6C + 0x20 + + + PROCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + CPUSDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0x70 + 0x20 + + + SDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + 54 + 0x4 + 0-53 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0x150 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0 + 22 + read-only + + + + + 256 + 0x4 + 0-255 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + + + IN_SEL + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 54 + 0x4 + 0-53 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000100 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + REG_DATE + GPIO version register + 0x6FC + 0x20 + 0x01907040 + + + REG_DATE + version register + 0 + 28 + read-write + + + + + + + GPIOSD + Sigma-Delta Modulation + GPIOSD + 0x60004F00 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + SIGMADELTA_CG + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 31 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + SIGMADELTA_VERSION + Version Control Register + 0x28 + 0x20 + 0x01802260 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x02101070 + + + DATE + Hmac date information/ hmac version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60013000 + + 0x0 + 0x90 + registers + + + I2C_MST + 11 + + + I2C_EXT0 + 42 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x0000020B + + + SDA_FORCE_OUT + 0: direct output; 1: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 0: direct output; 1: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit; +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit; +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave; 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL;1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x20070201 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller + 0x60027000 + + I2C_EXT1 + 43 + + + + I2S0 + I2S (Inter-IC Sound) Controller + I2S + 0x6000F000 + + 0x0 + 0x5C + registers + + + I2S0 + 25 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 21 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 22 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller + I2S1 + 0x6002D000 + + 0x0 + 0x54 + registers + + + I2S1 + 26 + + + + I2S_INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + I2S_RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + I2S_TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + I2S_RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + I2S_TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + I2S_INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + I2S_RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + I2S_TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + I2S_RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + I2S_TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + I2S_INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + I2S_RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + I2S_TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + I2S_RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + I2S_TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + I2S_INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + I2S_RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + I2S_TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + I2S_RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + I2S_TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + I2S_RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + I2S_RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + I2S_RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + I2S_RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + I2S_RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + I2S_RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + I2S_RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + I2S_RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + I2S_RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + I2S_RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + I2S_RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + I2S_RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + I2S_RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + I2S_RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + I2S_RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + I2S_RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + I2S_RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + I2S_RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + I2S_TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + I2S_TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + I2S_TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + I2S_TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + I2S_TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + I2S_TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + I2S_TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + I2S_TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + I2S_TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + I2S_TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + I2S_TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + I2S_TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + I2S_TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + I2S_TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + I2S_TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + I2S_TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + I2S_TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + I2S_TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + I2S_TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + I2S_TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + I2S_SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + I2S_RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + I2S_RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + I2S_RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + I2S_RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + I2S_RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + I2S_RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + I2S_RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + I2S_TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + I2S_TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + I2S_TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + I2S_TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + I2S_TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + I2S_TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + I2S_TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + I2S_TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + I2S_RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + I2S_RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + I2S_RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + I2S_RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + I2S_MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + I2S_TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + I2S_TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + I2S_TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + I2S_TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + I2S_CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + I2S_RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + I2S_RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + I2S_TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + I2S_RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + I2S_RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + I2S_RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + I2S_RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + I2S_RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + I2S_RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + I2S_RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + I2S_RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + I2S_RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + I2S_RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + I2S_TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + I2S_TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + I2S_TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + I2S_TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + I2S_TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + I2S_TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + I2S_TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + I2S_TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + I2S_TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + I2S_TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + I2S_TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + I2S_TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + I2S_TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + I2S_TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + I2S_TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + I2S_TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + I2S_TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + I2S_TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + I2S_TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + I2S_RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + I2S_RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + I2S_RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + I2S_RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + I2S_RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + I2S_RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + I2S_TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + I2S_TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + I2S_TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + I2S_TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + I2S_TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + I2S_TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + I2S_TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + I2S_LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + I2S_LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + I2S_LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + I2S_LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + I2S_RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + I2S_RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + I2S_CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + I2S_SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + I2S_STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + I2S_TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + I2S_DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + I2S_DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Core + INTERRUPT_CORE0 + 0x600C2000 + + 0x0 + 0x1A4 + registers + + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_BB + 2 + + + BT_MAC + 3 + + + BT_BB + 4 + + + BT_BB_NMI + 5 + + + RWBT + 6 + + + RWBLE + 7 + + + RWBT_NMI + 8 + + + RWBLE_NMI + 9 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE + 85 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE + 86 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE + 87 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE + 88 + + + CACHE_CORE0_ACS + 94 + + + + PRO_MAC_INTR_MAP + mac interrupt configuration register + 0x0 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x4 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x8 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0xC + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x10 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x14 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x18 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x1C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x20 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x24 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map mac rwbt_nmi to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x28 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x2C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x30 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x34 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x38 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x3C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x40 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x44 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x48 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x4C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x50 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x54 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x58 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x5C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x60 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x64 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x68 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x6C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x70 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x74 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x78 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x7C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x80 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x84 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x88 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x8C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x90 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x94 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x98 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x9C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0xA0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0xA4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0xA8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0xAC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0xB0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0xB4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0xB8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0xBC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0xC0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0xC4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0xC8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0xCC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0xD0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0xD4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0xD8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0xDC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0xE0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0xE4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0xE8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0xEC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0xF0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0xF4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0xF8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0xFC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x100 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x104 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x108 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x10C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x110 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x114 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x118 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x11C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x120 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x124 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x128 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x12C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x130 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x134 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x138 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x13C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x140 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x144 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x148 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x14C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x150 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x154 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x158 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x15C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x160 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x164 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x168 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x16C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x170 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x174 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x178 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x17C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x180 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x184 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x188 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PRO_INTR_STATUS_0 + interrupt status register + 0x18C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_1 + interrupt status register + 0x190 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_2 + interrupt status register + 0x194 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_3 + interrupt status register + 0x198 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x19C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0x7FC + 0x20 + 0x02012300 + + + INTERRUPT_REG_DATE + version register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Core + INTERRUPT_CORE1 + 0x600C2800 + + 0x0 + 0x1A4 + registers + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE + 89 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE + 90 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE + 91 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE + 92 + + + CACHE_CORE1_ACS + 95 + + + + APP_MAC_INTR_MAP + mac interrupt configuration register + 0x800 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x804 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x808 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0x80C + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x810 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x814 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x818 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x81C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x820 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x824 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map rwbt_nmi interupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x828 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x82C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x830 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x834 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x838 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x83C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x840 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x844 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x848 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x84C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x850 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x854 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x858 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x85C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x860 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x864 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x868 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x86C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x870 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x874 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x878 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x87C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x880 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x884 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x888 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x88C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x890 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x894 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x898 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x89C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0x8A0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0x8A4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0x8A8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0x8AC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0x8B0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0x8B4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0x8B8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0x8BC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0x8C0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0x8C4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0x8C8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0x8CC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0x8D0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0x8D4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0x8D8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0x8DC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0x8E0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0x8E4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0x8E8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0x8EC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0x8F0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0x8F4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0x8F8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0x8FC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x900 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x904 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x908 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x90C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x910 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x914 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x918 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x91C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x920 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x924 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x928 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x92C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x930 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x934 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x938 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x93C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x940 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x944 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x948 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x94C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x950 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x954 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x958 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x95C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x960 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x964 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x968 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x96C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x970 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x974 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x978 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x97C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x980 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x984 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x988 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APP_INTR_STATUS_0 + interrupt status register + 0x98C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_1 + interrupt status register + 0x990 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_2 + interrupt status register + 0x994 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_3 + interrupt status register + 0x998 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x99C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0xFFC + 0x20 + 0x02012300 + + + INTERRUPT_DATE + version register + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0xCC + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x000007FF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 4 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 4 + 4 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 8 + 4 + read-write + + + + + 49 + 0x4 + GPIO%s + IO MUX Configure Register for pad GPIO0 + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x01907160 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LCD_CAM + Peripheral LCD_CAM + LCD_CAM + 0x60041000 + + 0x0 + 0x48 + registers + + + + LCD_CLOCK + LCD clock register + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + Camera configuration register + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + Camera configuration register + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + Camera configuration register + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD configuration register + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD configuration register + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_8BITS_ORDER + 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + 19 + 1 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 20 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 21 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_2BYTE_EN + 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD configuration register + 0x18 + 0x20 + 0x000000D6 + + + LCD_AFIFO_THRESHOLD_NUM + The awfull threshold number of lcd_afifo. + 1 + 5 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD configuration register + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable reg mode input vsync, hsync, de. 0: Disable. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD configuration register + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD configuration register + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_CMD_VAL + LCD configuration register + 0x28 + 0x20 + + + LCD_CMD_VALUE + The LCD write command value. + 0 + 32 + read-write + + + + + LCD_DLY_MODE + LCD configuration register + 0x30 + 0x20 + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + + + LCD_DATA_DOUT_MODE + LCD configuration register + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCD_camera DMA inturrupt enable register + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCD_camera DMA raw inturrupt status register + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCD_camera DMA masked inturrupt status register + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCD_camera DMA inturrupt clear register + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02003020 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED PWM (Pulse Width Modulation) Controller + LEDC + 0x60019000 + + 0x0 + 0xD8 + registers + + + LEDC + 35 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer0 + +1: select timer1 + +2: select timer2 + +3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + OVF_CNT_RESET_ST + This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + 17 + 1 + read-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 14 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 19 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register is used to configure the changing step scale of duty on channel %s. + 0 + 10 + read-write + + + DUTY_CYCLE + The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the number of times the duty cycle will be changed. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. + 30 + 1 + read-write + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_R + This register stores the current duty of output signal on channel %s. + 0 + 19 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 4 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 4 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 22 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 23 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 24 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 25 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + CNT + This register stores the current counter value of timer %s. + 0 + 14 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + write-only + + + + + CONF + Global ledc configuration register + 0xD0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19040200 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x60017000 + + 0x0 + 0x68 + registers + + + PCNT + 41 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PERI_BACKUP + Peripheral PERI_BACKUP + PERI_BACKUP + 0x6002A000 + + 0x0 + 0x30 + registers + + + PERI_BACKUP + 97 + + + + CONFIG + x + 0x0 + 0x20 + 0x00006480 + + + FLOW_ERR + x + 0 + 3 + read-only + + + ADDR_MAP_MODE + x + 3 + 1 + read-write + + + BURST_LIMIT + x + 4 + 5 + read-write + + + TOUT_THRES + x + 9 + 10 + read-write + + + SIZE + x + 19 + 10 + read-write + + + START + x + 29 + 1 + write-only + + + TO_MEM + x + 30 + 1 + read-write + + + ENA + x + 31 + 1 + read-write + + + + + APB_ADDR + x + 0x4 + 0x20 + + + APB_START_ADDR + x + 0 + 32 + read-write + + + + + MEM_ADDR + x + 0x8 + 0x20 + + + MEM_START_ADDR + x + 0 + 32 + read-write + + + + + REG_MAP0 + x + 0xC + 0x20 + + + MAP0 + x + 0 + 32 + read-write + + + + + REG_MAP1 + x + 0x10 + 0x20 + + + MAP1 + x + 0 + 32 + read-write + + + + + REG_MAP2 + x + 0x14 + 0x20 + + + MAP2 + x + 0 + 32 + read-write + + + + + REG_MAP3 + x + 0x18 + 0x20 + + + MAP3 + x + 0 + 32 + read-write + + + + + INT_RAW + x + 0x1C + 0x20 + + + DONE_INT_RAW + x + 0 + 1 + read-only + + + ERR_INT_RAW + x + 1 + 1 + read-only + + + + + INT_ST + x + 0x20 + 0x20 + + + DONE_INT_ST + x + 0 + 1 + read-only + + + ERR_INT_ST + x + 1 + 1 + read-only + + + + + INT_ENA + x + 0x24 + 0x20 + + + DONE_INT_ENA + x + 0 + 1 + read-write + + + ERR_INT_ENA + x + 1 + 1 + read-write + + + + + INT_CLR + x + 0x28 + 0x20 + + + DONE_INT_CLR + x + 0 + 1 + write-only + + + ERR_INT_CLR + x + 1 + 1 + write-only + + + + + DATE + x + 0xFC + 0x20 + 0x02012300 + + + DATE + x + 0 + 28 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + + + PWM0 + Peripheral PWM0 + PWM + 0x6001E000 + + 0x0 + 0x128 + registers + + + PWM0 + 31 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + CMPR0_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR0_VALUE0 + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR0_VALUE1 + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + TZ0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR1_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR1_VALUE0 + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR1_VALUE1 + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + TZ1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR2_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR2_VALUE0 + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR2_VALUE1 + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + TZ2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + Write 1 will force a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + Value of last capture on channel 0 + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + Value of last capture on channel 1 + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + Value of last capture on channel 2 + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + CLK + MCPWM APB configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x124 + 0x20 + 0x01509110 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PWM1 + 0x6002C000 + + PWM1 + 32 + + + + RMT + Remote control + RMT + 0x60016000 + + 0x0 + 0xD0 + registers + + + RMT + 40 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + CH%s_TX_CONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST + Reserved + 23 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + CH%s_RX_CONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + CH%s_RX_CONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST + Reserved + 14 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + CH%s_TX_STATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + CH%s_RX_STATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + 0 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + 4 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ST + The masked interrupt status bit for CH%s_TX_END_INT. + 0 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ST + The masked interrupt status bit for CH%s_ERR_INT. + 4 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ST + The masked interrupt status bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ENA + The interrupt enable bit for CH%s_TX_END_INT. + 0 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ENA + The interrupt enable bit for CH%s_ERR_INT. + 4 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ENA + The interrupt enable bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_CLR + Set this bit to clear theCH%s_TX_END_INT interrupt. + 0 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_CLR + Set this bit to clear theCH%s_ERR_INT interrupt. + 4 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_CLR + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + 4 + 0x1 + RX_CH4,RX_CH5,RX_CH6,RX_CH7 + CH%s_RX_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + 8 + 0x1 + TX_REF_CNT_RST_CH0,TX_REF_CNT_RST_CH1,TX_REF_CNT_RST_CH2,TX_REF_CNT_RST_CH3,RX_REF_CNT_RST_CH4,RX_REF_CNT_RST_CH5,RX_REF_CNT_RST_CH6,RX_REF_CNT_RST_CH7 + CH%s + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02101181 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60034F6C + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x110 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x834 + registers + + + RSA + 76 + + + + 512 + 0x1 + M_MEM[%s] + Memory M + 0x0 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0x200 + 0x8 + + + 512 + 0x1 + Y_MEM[%s] + Memory Y + 0x400 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x600 + 0x8 + + + M_PRIME + RSA M' register + 0x800 + 0x20 + + + M_PRIME + Stores M' + 0 + 32 + read-write + + + + + MODE + RSA length mode register + 0x804 + 0x20 + + + MODE + Stores the RSA length mode + 0 + 7 + read-write + + + + + CLEAN + RSA clean register + 0x808 + 0x20 + + + CLEAN + The content of this bit is 1 when memories complete initialization. + 0 + 1 + read-only + + + + + MODEXP_START + Modular exponentiation trigger register. + 0x80C + 0x20 + + + MODEXP_START + Set this bit to 1 to start the modular exponentiation. + 0 + 1 + write-only + + + + + MODMULT_START + Modular multiplication trigger register. + 0x810 + 0x20 + + + MODMULT_START + Set this bit to 1 to start the modular multiplication + 0 + 1 + write-only + + + + + MULT_START + Normal multiplication trigger register. + 0x814 + 0x20 + + + MULT_START + Set this bit to 1 to start the multiplicaiton. + 0 + 1 + write-only + + + + + IDLE + RSA idle register + 0x818 + 0x20 + + + IDLE + The content of this bit is 1 when the RSA accelerator is idle. + 0 + 1 + read-only + + + + + CLEAR_INTERRUPT + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + CONSTANT_TIME option control register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + SEARCH option enable register + 0x824 + 0x20 + + + SEARCH_ENABLE + Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + This field is used to configure the starting search position when the acceleration option of SEARCH is used. + 0 + 12 + read-write + + + + + INTERRUPT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INTERRUPT_ENA + Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20191231 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + RTC_CNTL + Real Time Controller + RTC_CNTL + 0x60008000 + + 0x0 + 0x15C + registers + + + RTC_CORE + 39 + + + + OPTIONS0 + RTC common configure register + 0x0 + 0x20 + 0x1C00A000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset + 4 + 1 + write-only + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + XTL_EN_WAIT + wait bias_sleep and current source wakeup + 14 + 4 + read-write + + + XTL_FORCE_ISO + No public + 23 + 1 + read-write + + + PLL_FORCE_ISO + No public + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + No public + 25 + 1 + read-write + + + XTL_FORCE_NOISO + No public + 26 + 1 + read-write + + + PLL_FORCE_NOISO + No public + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + No public + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + write-only + + + + + SLP_TIMER0 + configure min sleep time + 0x4 + 0x20 + + + SLP_VAL_LO + RTC sleep timer low 32 bits + 0 + 32 + read-write + + + + + SLP_TIMER1 + configure sleep time hi + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + write-only + + + + + TIME_UPDATE + update rtc main timer + 0xC + 0x20 + + + TIMER_SYS_STALL + Enable to record system stall time + 27 + 1 + read-write + + + TIMER_XTL_OFF + Enable to record 40M XTAL OFF time + 28 + 1 + read-write + + + TIMER_SYS_RST + enable to record system reset time + 29 + 1 + read-write + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + write-only + + + + + TIME_LOW0 + read rtc_main timer low bits + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH0 + read rtc_main timer high bits + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + STATE0 + configure chip sleep + 0x18 + 0x20 + + + SW_CPU_INT + rtc software interrupt to main cpu + 0 + 1 + write-only + + + SLP_REJECT_CAUSE_CLR + clear rtc sleep reject cause + 1 + 1 + write-only + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge, 0: APB to RTC using sync + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-only + + + SLP_WAKEUP + leep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + leep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + rtc state wait time + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + rtc monitor state delay time + 0x20 + 0x20 + 0x01080000 + + + ULPCP_TOUCH_START_WAIT + wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + 15 + 9 + read-write + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER3 + No public + 0x24 + 0x20 + 0x14160A08 + + + WIFI_WAIT_TIMER + No public + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + No public + 9 + 7 + read-write + + + BT_WAIT_TIMER + No public + 16 + 9 + read-write + + + BT_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER4 + No public + 0x28 + 0x20 + 0x10200A08 + + + WAIT_TIMER + No public + 0 + 9 + read-write + + + POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER5 + configure min sleep time + 0x2C + 0x20 + 0x00008000 + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + + + TIMER6 + No public + 0x30 + 0x20 + 0x10200A08 + + + CPU_TOP_WAIT_TIMER + No public + 0 + 9 + read-write + + + CPU_TOP_POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_PERI_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_PERI_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + ANA_CONF + analog configure register + 0x34 + 0x20 + 0x00440000 + + + I2C_RESET_POR_FORCE_PD + force down I2C_RESET_POR + 18 + 1 + read-write + + + I2C_RESET_POR_FORCE_PU + force on I2C_RESET_POR + 19 + 1 + read-write + + + GLITCH_RST_EN + enable clk glitch + 20 + 1 + read-write + + + SAR_I2C_PU + PLLA force power up + 22 + 1 + read-write + + + ANALOG_TOP_ISO_SLEEP + PLLA force power down + 23 + 1 + read-write + + + ANALOG_TOP_ISO_MONITOR + PLLA force power up + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up, otherwise power down + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up, otherwise power down + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up, otherwise power down + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up, otherwise power down + 30 + 1 + read-write + + + PLL_I2C_PU + power on pll i2c + 31 + 1 + read-write + + + + + RESET_STATE + get reset state + 0x38 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + APPCPU_STAT_VECTOR_SEL + APP CPU state vector sel + 12 + 1 + read-write + + + PROCPU_STAT_VECTOR_SEL + PRO CPU state vector sel + 13 + 1 + read-write + + + RESET_FLAG_PROCPU + PRO CPU reset_flag + 14 + 1 + read-only + + + RESET_FLAG_APPCPU + APP CPU reset flag + 15 + 1 + read-only + + + RESET_FLAG_PROCPU_CLR + clear PRO CPU reset_flag + 16 + 1 + write-only + + + RESET_FLAG_APPCPU_CLR + clear APP CPU reset flag + 17 + 1 + write-only + + + APPCPU_OCD_HALT_ON_RESET + APPCPU OcdHaltOnReset + 18 + 1 + read-write + + + PROCPU_OCD_HALT_ON_RESET + PROCPU OcdHaltOnReset + 19 + 1 + read-write + + + RESET_FLAG_JTAG_PROCPU + jtag reset flag + 20 + 1 + read-only + + + RESET_FLAG_JTAG_APPCPU + jtag reset flag + 21 + 1 + read-only + + + RESET_FLAG_JTAG_PROCPU_CLR + clear jtag reset flag + 22 + 1 + write-only + + + RESET_FLAG_JTAG_APPCPU_CLR + clear jtag reset flag + 23 + 1 + write-only + + + APP_DRESET_MASK + bypass cpu1 dreset + 24 + 1 + read-write + + + PRO_DRESET_MASK + bypass cpu0 dreset + 25 + 1 + read-write + + + + + WAKEUP_STATE + configure wakeup state + 0x3C + 0x20 + 0x00060000 + + + WAKEUP_ENA + wakeup enable bitmap + 15 + 17 + read-write + + + + + INT_ENA_RTC + configure rtc interrupt register + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + read-write + + + SDIO_IDLE_INT_ENA + enable SDIO idle interrupt + 2 + 1 + read-write + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + read-write + + + TOUCH_SCAN_DONE_INT_ENA + enable touch scan done interrupt + 4 + 1 + read-write + + + ULP_CP_INT_ENA + enable ULP-coprocessor interrupt + 5 + 1 + read-write + + + TOUCH_DONE_INT_ENA + enable touch done interrupt + 6 + 1 + read-write + + + TOUCH_ACTIVE_INT_ENA + enable touch active interrupt + 7 + 1 + read-write + + + TOUCH_INACTIVE_INT_ENA + enable touch inactive interrupt + 8 + 1 + read-write + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 10 + 1 + read-write + + + SARADC1_INT_ENA + enable saradc1 interrupt + 11 + 1 + read-write + + + TSENS_INT_ENA + enable tsens interrupt + 12 + 1 + read-write + + + COCPU_INT_ENA + enable riscV cocpu interrupt + 13 + 1 + read-write + + + SARADC2_INT_ENA + enable saradc2 interrupt + 14 + 1 + read-write + + + SWD_INT_ENA + enable super watch dog interrupt + 15 + 1 + read-write + + + XTAL32K_DEAD_INT_ENA + enable xtal32k_dead interrupt + 16 + 1 + read-write + + + COCPU_TRAP_INT_ENA + enable cocpu trap interrupt + 17 + 1 + read-write + + + TOUCH_TIMEOUT_INT_ENA + enable touch timeout interrupt + 18 + 1 + read-write + + + GLITCH_DET_INT_ENA + enbale gitch det interrupt + 19 + 1 + read-write + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA + touch approach mode loop interrupt + 20 + 1 + read-write + + + + + INT_RAW_RTC + rtc interrupt register + 0x44 + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-only + + + SDIO_IDLE_INT_RAW + SDIO idle interrupt raw + 2 + 1 + read-only + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_RAW + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_RAW + ULP-coprocessor interrupt raw + 5 + 1 + read-only + + + TOUCH_DONE_INT_RAW + touch interrupt raw + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_RAW + touch active interrupt raw + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_RAW + touch inactive interrupt raw + 8 + 1 + read-only + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 9 + 1 + read-only + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 10 + 1 + read-only + + + SARADC1_INT_RAW + saradc1 interrupt raw + 11 + 1 + read-only + + + TSENS_INT_RAW + tsens interrupt raw + 12 + 1 + read-only + + + COCPU_INT_RAW + riscV cocpu interrupt raw + 13 + 1 + read-only + + + SARADC2_INT_RAW + saradc2 interrupt raw + 14 + 1 + read-only + + + SWD_INT_RAW + super watch dog interrupt raw + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_RAW + xtal32k dead detection interrupt raw + 16 + 1 + read-only + + + COCPU_TRAP_INT_RAW + cocpu trap interrupt raw + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_RAW + touch timeout interrupt raw + 18 + 1 + read-only + + + GLITCH_DET_INT_RAW + glitch_det_interrupt_raw + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_RAW + touch approach mode loop interrupt raw + 20 + 1 + read-write + + + + + INT_ST_RTC + rtc interrupt register + 0x48 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-only + + + SDIO_IDLE_INT_ST + SDIO idle interrupt state + 2 + 1 + read-only + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_ST + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_ST + ULP-coprocessor interrupt state + 5 + 1 + read-only + + + TOUCH_DONE_INT_ST + touch done interrupt state + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_ST + touch active interrupt state + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_ST + touch inactive interrupt state + 8 + 1 + read-only + + + BROWN_OUT_INT_ST + brown out interrupt state + 9 + 1 + read-only + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 10 + 1 + read-only + + + SARADC1_INT_ST + saradc1 interrupt state + 11 + 1 + read-only + + + TSENS_INT_ST + tsens interrupt state + 12 + 1 + read-only + + + COCPU_INT_ST + riscV cocpu interrupt state + 13 + 1 + read-only + + + SARADC2_INT_ST + saradc2 interrupt state + 14 + 1 + read-only + + + SWD_INT_ST + super watch dog interrupt state + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_ST + xtal32k dead detection interrupt state + 16 + 1 + read-only + + + COCPU_TRAP_INT_ST + cocpu trap interrupt state + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_ST + Touch timeout interrupt state + 18 + 1 + read-only + + + GLITCH_DET_INT_ST + glitch_det_interrupt state + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ST + touch approach mode loop interrupt state + 20 + 1 + read-only + + + + + INT_CLR_RTC + rtc interrupt register + 0x4C + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + write-only + + + SDIO_IDLE_INT_CLR + Clear SDIO idle interrupt state + 2 + 1 + write-only + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_CLR + clear touch scan done interrupt raw + 4 + 1 + write-only + + + ULP_CP_INT_CLR + Clear ULP-coprocessor interrupt state + 5 + 1 + write-only + + + TOUCH_DONE_INT_CLR + Clear touch done interrupt state + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_CLR + Clear touch active interrupt state + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_CLR + Clear touch inactive interrupt state + 8 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 9 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 10 + 1 + write-only + + + SARADC1_INT_CLR + Clear saradc1 interrupt state + 11 + 1 + write-only + + + TSENS_INT_CLR + Clear tsens interrupt state + 12 + 1 + write-only + + + COCPU_INT_CLR + Clear riscV cocpu interrupt state + 13 + 1 + write-only + + + SARADC2_INT_CLR + Clear saradc2 interrupt state + 14 + 1 + write-only + + + SWD_INT_CLR + Clear super watch dog interrupt state + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_CLR + Clear RTC WDT interrupt state + 16 + 1 + write-only + + + COCPU_TRAP_INT_CLR + Clear cocpu trap interrupt state + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_CLR + Clear touch timeout interrupt state + 18 + 1 + write-only + + + GLITCH_DET_INT_CLR + Clear glitch det interrupt state + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_CLR + cleartouch approach mode loop interrupt state + 20 + 1 + write-only + + + + + STORE0 + Reserved register + 0x50 + 0x20 + + + SCRATCH0 + Reserved register + 0 + 32 + read-write + + + + + STORE1 + Reserved register + 0x54 + 0x20 + + + SCRATCH1 + Reserved register + 0 + 32 + read-write + + + + + STORE2 + Reserved register + 0x58 + 0x20 + + + SCRATCH2 + Reserved register + 0 + 32 + read-write + + + + + STORE3 + Reserved register + 0x5C + 0x20 + + + SCRATCH3 + Reserved register + 0 + 32 + read-write + + + + + EXT_XTL_CONF + Reserved register + 0x60 + 0x20 + 0x00066C80 + + + XTAL32K_WDT_EN + xtal 32k watch dog enable + 0 + 1 + read-write + + + XTAL32K_WDT_CLK_FO + xtal 32k watch dog clock force on + 1 + 1 + read-write + + + XTAL32K_WDT_RESET + xtal 32k watch dog sw reset + 2 + 1 + read-write + + + XTAL32K_EXT_CLK_FO + xtal 32k external xtal clock force on + 3 + 1 + read-write + + + XTAL32K_AUTO_BACKUP + xtal 32k switch to back up clock when xtal is dead + 4 + 1 + read-write + + + XTAL32K_AUTO_RESTART + xtal 32k restart xtal when xtal is dead + 5 + 1 + read-write + + + XTAL32K_AUTO_RETURN + xtal 32k switch back xtal when xtal is restarted + 6 + 1 + read-write + + + XTAL32K_XPD_FORCE + Xtal 32k xpd control by sw or fsm + 7 + 1 + read-write + + + ENCKINIT_XTAL_32K + apply an internal clock to help xtal 32k to start + 8 + 1 + read-write + + + DBUF_XTAL_32K + 0: single-end buffer 1: differential buffer + 9 + 1 + read-write + + + DGM_XTAL_32K + xtal_32k gm control + 10 + 3 + read-write + + + DRES_XTAL_32K + DRES_XTAL_32K + 13 + 3 + read-write + + + XPD_XTAL_32K + XPD_XTAL_32K + 16 + 1 + read-write + + + DAC_XTAL_32K + DAC_XTAL_32K + 17 + 3 + read-write + + + WDT_STATE + state of 32k_wdt + 20 + 3 + read-only + + + XTAL32K_GPIO_SEL + XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C + 23 + 1 + read-write + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level, 1: power down XTAL at low level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + Reserved register + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + ext wakeup configure + 0x64 + 0x20 + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 29 + 1 + read-write + + + EXT_WAKEUP0_LV + 0: external wakeup at low level, 1: external wakeup at high level + 30 + 1 + read-write + + + EXT_WAKEUP1_LV + 0: external wakeup at low level, 1: external wakeup at high level + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + reject sleep register + 0x68 + 0x20 + + + SLEEP_REJECT_ENA + sleep reject enable + 12 + 18 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + conigure cpu freq + 0x6C + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + conigure cpu freq + 30 + 2 + read-write + + + + + SDIO_ACT_CONF + No public + 0x70 + 0x20 + + + SDIO_ACT_DNUM + No public + 22 + 10 + read-write + + + + + CLK_CONF + configure clock register + 0x74 + 0x20 + 0x1158321C + + + EFUSE_CLK_FORCE_GATING + force efuse clk gating + 1 + 1 + read-write + + + EFUSE_CLK_FORCE_NOGATING + force efuse clk nogating + 2 + 1 + read-write + + + CK8M_DIV_SEL_VLD + used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk + 3 + 1 + read-write + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024. + 4 + 2 + read-write + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256 + 7 + 1 + read-write + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + XTAL_GLOBAL_FORCE_GATING + force global xtal gating + 27 + 1 + read-write + + + XTAL_GLOBAL_FORCE_NOGATING + force global xtal no gating + 28 + 1 + read-write + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + select slow clock + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + configure slow clk + 0x78 + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk + 22 + 1 + read-write + + + ANA_CLK_DIV + rtc clk div + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + No public + 31 + 1 + read-write + + + + + SDIO_CONF + configure flash power + 0x7C + 0x20 + 0x0AB0BE0A + + + SDIO_TIMER_TARGET + timer count to apply reg_sdio_dcap after sdio power on + 0 + 8 + read-write + + + SDIO_DTHDRV + Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us. + 9 + 2 + read-write + + + SDIO_DCAP + ability to prevent LDO from overshoot + 11 + 2 + read-write + + + SDIO_INITI + add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k + 13 + 2 + read-write + + + SDIO_EN_INITI + 0 to set init[1:0]=0 + 15 + 1 + read-write + + + SDIO_DCURLIM + tune current limit threshold when tieh = 0. About 800mA/(8+d) + 16 + 3 + read-write + + + SDIO_MODECURLIM + select current limit mode + 19 + 1 + read-write + + + SDIO_ENCURLIM + enable current limit + 20 + 1 + read-write + + + SDIO_REG_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG, 0: use state machine + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + REG1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + power on flash regulator + 31 + 1 + read-write + + + + + BIAS_CONF + No public + 0x80 + 0x20 + 0x00010800 + + + BIAS_BUF_IDLE + No public + 10 + 1 + read-write + + + BIAS_BUF_WAKE + No public + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + No public + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + No public + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in monitor state + 22 + 4 + read-write + + + DBG_ATTEN_WAKEUP + No public + 26 + 4 + read-write + + + + + RTC + configure rtc regulator + 0x84 + 0x20 + 0xA0000000 + + + DIG_REG_CAL_EN + enable dig regulator cali + 7 + 1 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + REGULATOR_FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 31 + 1 + read-write + + + + + PWC + configure rtc power + 0x88 + 0x20 + 0x00000925 + + + FASTMEM_FORCE_NOISO + Fast RTC memory force no ISO + 0 + 1 + read-write + + + FASTMEM_FORCE_ISO + Fast RTC memory force ISO + 1 + 1 + read-write + + + SLOWMEM_FORCE_NOISO + RTC memory force no ISO + 2 + 1 + read-write + + + SLOWMEM_FORCE_ISO + RTC memory force ISO + 3 + 1 + read-write + + + FORCE_ISO + rtc_peri force ISO + 4 + 1 + read-write + + + FORCE_NOISO + rtc_peri force no ISO + 5 + 1 + read-write + + + FASTMEM_FOLW_CPU + 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine + 6 + 1 + read-write + + + FASTMEM_FORCE_LPD + Fast RTC memory force PD + 7 + 1 + read-write + + + FASTMEM_FORCE_LPU + Fast RTC memory force no PD + 8 + 1 + read-write + + + SLOWMEM_FOLW_CPU + 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine + 9 + 1 + read-write + + + SLOWMEM_FORCE_LPD + RTC memory force PD + 10 + 1 + read-write + + + SLOWMEM_FORCE_LPU + RTC memory force no PD + 11 + 1 + read-write + + + FORCE_PD + rtc_peri force power down + 18 + 1 + read-write + + + FORCE_PU + rtc_peri force power up + 19 + 1 + read-write + + + PD_EN + enable power down rtc_peri in sleep + 20 + 1 + read-write + + + PAD_FORCE_HOLD + rtc pad force hold + 21 + 1 + read-write + + + + + REGULATOR_DRV_CTRL + No public + 0x8C + 0x20 + + + REGULATOR_DRV_B_MONITOR + No public + 0 + 6 + read-write + + + REGULATOR_DRV_B_SLP + No public + 6 + 6 + read-write + + + DG_VDD_DRV_B_SLP + No public + 12 + 8 + read-write + + + DG_VDD_DRV_B_MONITOR + No public + 20 + 8 + read-write + + + + + DIG_PWC + configure digital power + 0x90 + 0x20 + 0x00545010 + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force no PD in sleep + 4 + 1 + read-write + + + BT_FORCE_PD + internal SRAM 2 force power down + 11 + 1 + read-write + + + BT_FORCE_PU + internal SRAM 2 force power up + 12 + 1 + read-write + + + DG_PERI_FORCE_PD + internal SRAM 3 force power down + 13 + 1 + read-write + + + DG_PERI_FORCE_PU + internal SRAM 3 force power up + 14 + 1 + read-write + + + WIFI_FORCE_PD + wifi force power down + 17 + 1 + read-write + + + WIFI_FORCE_PU + wifi force power up + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + CPU_TOP_FORCE_PD + digital dcdc force power down + 21 + 1 + read-write + + + CPU_TOP_FORCE_PU + digital dcdc force power up + 22 + 1 + read-write + + + BT_PD_EN + enable power down internal SRAM 2 in sleep + 27 + 1 + read-write + + + DG_PERI_PD_EN + enable power down internal SRAM 3 in sleep + 28 + 1 + read-write + + + CPU_TOP_PD_EN + enable power down internal SRAM 4 in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + enable power down wifi in sleep + 30 + 1 + read-write + + + DG_WRAP_PD_EN + enable power down all digital logic + 31 + 1 + read-write + + + + + DIG_ISO + congigure digital power isolation + 0x94 + 0x20 + 0xAA805080 + + + FORCE_OFF + No public + 7 + 1 + read-write + + + FORCE_ON + No public + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + BT_FORCE_ISO + internal SRAM 2 force ISO + 22 + 1 + read-write + + + BT_FORCE_NOISO + internal SRAM 2 force no ISO + 23 + 1 + read-write + + + DG_PERI_FORCE_ISO + internal SRAM 3 force ISO + 24 + 1 + read-write + + + DG_PERI_FORCE_NOISO + internal SRAM 3 force no ISO + 25 + 1 + read-write + + + CPU_TOP_FORCE_ISO + internal SRAM 4 force ISO + 26 + 1 + read-write + + + CPU_TOP_FORCE_NOISO + internal SRAM 4 force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + wifi force ISO + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + wifi force no ISO + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + digita core force no ISO + 31 + 1 + read-write + + + + + WDTCONFIG0 + configure rtc watch dog + 0x98 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 16 + 3 + read-write + + + WDT_STG3 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 28 + 3 + read-write + + + WDT_EN + enable rtc watch dog + 31 + 1 + read-write + + + + + WDTCONFIG1 + stage0 hold time + 0x9C + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + stage0 hold time + 0 + 32 + read-write + + + + + WDTCONFIG2 + stage1 hold time + 0xA0 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + stage1 hold time + 0 + 32 + read-write + + + + + WDTCONFIG3 + stage2 hold time + 0xA4 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + stage2 hold time + 0 + 32 + read-write + + + + + WDTCONFIG4 + stage3 hold time + 0xA8 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + stage3 hold time + 0 + 32 + read-write + + + + + WDTFEED + rtc wdt feed + 0xAC + 0x20 + + + WDT_FEED + rtc wdt feed + 31 + 1 + write-only + + + + + WDTWPROTECT + configure rtc watch dog + 0xB0 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + rtc watch dog key + 0 + 32 + read-write + + + + + SWD_CONF + congfigure super watch dog + 0xB4 + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + swd reset flag + 0 + 1 + read-only + + + SWD_FEED_INT + swd interrupt for feeding + 1 + 1 + read-only + + + SWD_BYPASS_RST + bypass super watch dog reset + 17 + 1 + read-write + + + SWD_SIGNAL_WIDTH + adjust signal width send to swd + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + reset swd reset flag + 28 + 1 + write-only + + + SWD_FEED + Sw feed swd + 29 + 1 + write-only + + + SWD_DISABLE + disabel SWD + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + automatically feed swd when int comes + 31 + 1 + read-write + + + + + SWD_WPROTECT + super watch dog key + 0xB8 + 0x20 + 0x8F1D312A + + + SWD_WKEY + super watch dog key + 0 + 32 + read-write + + + + + SW_CPU_STALL + configure cpu stall by sw + 0xBC + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 26 + 6 + read-write + + + + + STORE4 + reserved register + 0xC0 + 0x20 + + + SCRATCH4 + reserved register + 0 + 32 + read-write + + + + + STORE5 + reserved register + 0xC4 + 0x20 + + + SCRATCH5 + reserved register + 0 + 32 + read-write + + + + + STORE6 + reserved register + 0xC8 + 0x20 + + + SCRATCH6 + reserved register + 0 + 32 + read-write + + + + + STORE7 + reserved register + 0xCC + 0x20 + + + SCRATCH7 + reserved register + 0 + 32 + read-write + + + + + LOW_POWER_ST + reserved register + 0xD0 + 0x20 + + + XPD_ROM0 + rom0 power down + 0 + 1 + read-only + + + XPD_DIG_DCDC + External DCDC power down + 2 + 1 + read-only + + + PERI_ISO + rtc peripheral iso + 3 + 1 + read-only + + + XPD_RTC_PERI + rtc peripheral power down + 4 + 1 + read-only + + + WIFI_ISO + wifi iso + 5 + 1 + read-only + + + XPD_WIFI + wifi wrap power down + 6 + 1 + read-only + + + DIG_ISO + digital wrap iso + 7 + 1 + read-only + + + XPD_DIG + digital wrap power down + 8 + 1 + read-only + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-only + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-only + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-only + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-only + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-only + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-only + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-only + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-only + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-only + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-only + + + RDY_FOR_WAKEUP + rtc is ready to receive wake up trigger from wake up source + 19 + 1 + read-only + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-only + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-only + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-only + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-only + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-only + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-only + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-only + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-only + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-only + + + + + DIAG0 + No public + 0xD4 + 0x20 + + + LOW_POWER_DIAG1 + No public + 0 + 32 + read-only + + + + + PAD_HOLD + rtc pad hold configure + 0xD8 + 0x20 + + + TOUCH_PAD0_HOLD + hold rtc pad0 + 0 + 1 + read-write + + + TOUCH_PAD1_HOLD + hold rtc pad-1 + 1 + 1 + read-write + + + TOUCH_PAD2_HOLD + hold rtc pad-2 + 2 + 1 + read-write + + + TOUCH_PAD3_HOLD + hold rtc pad-3 + 3 + 1 + read-write + + + TOUCH_PAD4_HOLD + hold rtc pad-4 + 4 + 1 + read-write + + + TOUCH_PAD5_HOLD + hold rtc pad-5 + 5 + 1 + read-write + + + TOUCH_PAD6_HOLD + hold rtc pad-6 + 6 + 1 + read-write + + + TOUCH_PAD7_HOLD + hold rtc pad-7 + 7 + 1 + read-write + + + TOUCH_PAD8_HOLD + hold rtc pad-8 + 8 + 1 + read-write + + + TOUCH_PAD9_HOLD + hold rtc pad-9 + 9 + 1 + read-write + + + TOUCH_PAD10_HOLD + hold rtc pad-10 + 10 + 1 + read-write + + + TOUCH_PAD11_HOLD + hold rtc pad-11 + 11 + 1 + read-write + + + TOUCH_PAD12_HOLD + hold rtc pad-12 + 12 + 1 + read-write + + + TOUCH_PAD13_HOLD + hold rtc pad-13 + 13 + 1 + read-write + + + TOUCH_PAD14_HOLD + hold rtc pad-14 + 14 + 1 + read-write + + + X32P_HOLD + hold rtc pad-15 + 15 + 1 + read-write + + + X32N_HOLD + hold rtc pad-16 + 16 + 1 + read-write + + + PDAC1_HOLD + hold rtc pad-17 + 17 + 1 + read-write + + + PDAC2_HOLD + hold rtc pad-18 + 18 + 1 + read-write + + + PAD19_HOLD + hold rtc pad-19 + 19 + 1 + read-write + + + PAD20_HOLD + hold rtc pad-20 + 20 + 1 + read-write + + + PAD21_HOLD + hold rtc pad-21 + 21 + 1 + read-write + + + + + DIG_PAD_HOLD + configure digtal pad hold + 0xDC + 0x20 + + + DIG_PAD_HOLD + configure digtal pad hold + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + configure ext1 wakeup + 0xE0 + 0x20 + + + EXT_WAKEUP1_SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 22 + read-write + + + EXT_WAKEUP1_STATUS_CLR + clear ext wakeup1 status + 22 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + check ext wakeup1 status + 0xE4 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 22 + read-only + + + + + BROWN_OUT + congfigure brownout + 0xE8 + 0x20 + 0x43FF0010 + + + BROWN_OUT_INT_WAIT + brown out interrupt wait cycles + 4 + 10 + read-write + + + BROWN_OUT_CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + BROWN_OUT_PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + BROWN_OUT_RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + BROWN_OUT_RST_ENA + enable brown out reset + 26 + 1 + read-write + + + BROWN_OUT_RST_SEL + 1: 4-pos reset, 0: sys_reset + 27 + 1 + read-write + + + BROWN_OUT_ANA_RST_EN + enable brown out reset en + 28 + 1 + read-write + + + BROWN_OUT_CNT_CLR + clear brown out counter + 29 + 1 + write-only + + + BROWN_OUT_ENA + enable brown out + 30 + 1 + read-write + + + DET + get brown out detect + 31 + 1 + read-only + + + + + TIME_LOW1 + RTC timer low 32 bits + 0xEC + 0x20 + + + TIMER_VALUE1_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH1 + RTC timer high 16 bits + 0xF0 + 0x20 + + + TIMER_VALUE1_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0xF4 + 0x20 + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0 + 32 + read-write + + + + + XTAL32K_CONF + configure xtal32k + 0xF8 + 0x20 + 0x0FF00000 + + + XTAL32K_RETURN_WAIT + cycles to wait to return noral xtal 32k + 0 + 4 + read-write + + + XTAL32K_RESTART_WAIT + cycles to wait to repower on xtal 32k + 4 + 16 + read-write + + + XTAL32K_WDT_TIMEOUT + If no clock detected for this amount of time 32k is regarded as dead + 20 + 8 + read-write + + + XTAL32K_STABLE_THRES + if restarted xtal32k period is smaller than this, it is regarded as stable + 28 + 4 + read-write + + + + + ULP_CP_TIMER + configure ulp + 0xFC + 0x20 + + + ULP_CP_PC_INIT + ULP-coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + ULP-coprocessor wakeup by GPIO enable + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + ULP-coprocessor wakeup by GPIO state clear + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP-coprocessor timer enable bit + 31 + 1 + read-write + + + + + ULP_CP_CTRL + configure ulp + 0x100 + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + No public + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + No public + 11 + 11 + read-write + + + ULP_CP_MEM_OFFST_CLR + No public + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ulp coprocessor clk force on + 28 + 1 + read-write + + + ULP_CP_RESET + ulp coprocessor clk software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + 1: ULP-coprocessor is started by SW + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-coprocessor + 31 + 1 + read-write + + + + + COCPU_CTRL + configure ulp-riscv + 0x104 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + cocpu clk force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + time from start cocpu to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + time from start cocpu to give start interrupt + 7 + 6 + read-write + + + COCPU_SHUT + to shut cocpu + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + time from shut cocpu to disable clk + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + to reset cocpu + 22 + 1 + read-write + + + COCPU_SEL + 1: old ULP 0: new riscV + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 1: select riscv done 0: select ulp done + 24 + 1 + read-write + + + COCPU_DONE + done signal used by riscv to control timer. + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + trigger cocpu register interrupt + 26 + 1 + write-only + + + COCPU_CLKGATE_EN + open ulp-riscv clk gate + 27 + 1 + read-write + + + + + TOUCH_CTRL1 + configure touch controller + 0x108 + 0x20 + 0x10000100 + + + TOUCH_SLEEP_CYCLES + sleep cycles for timer + 0 + 16 + read-write + + + TOUCH_MEAS_NUM + the meas length (in 8MHz) + 16 + 16 + read-write + + + + + TOUCH_CTRL2 + configure touch controller + 0x10C + 0x20 + 0x000840CC + + + TOUCH_DRANGE + TOUCH_DRANGE + 2 + 2 + read-write + + + TOUCH_DREFL + TOUCH_DREFL + 4 + 2 + read-write + + + TOUCH_DREFH + TOUCH_DREFH + 6 + 2 + read-write + + + TOUCH_XPD_BIAS + TOUCH_XPD_BIAS + 8 + 1 + read-write + + + TOUCH_REFC + TOUCH pad0 reference cap + 9 + 3 + read-write + + + TOUCH_DBIAS + 1:use self bias 0:use bandgap bias + 12 + 1 + read-write + + + TOUCH_SLP_TIMER_EN + touch timer enable bit + 13 + 1 + read-write + + + TOUCH_START_FSM_EN + 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm + 14 + 1 + read-write + + + TOUCH_START_EN + 1: start touch fsm + 15 + 1 + read-write + + + TOUCH_START_FORCE + 1: to start touch fsm by SW + 16 + 1 + read-write + + + TOUCH_XPD_WAIT + the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + 17 + 8 + read-write + + + TOUCH_SLP_CYC_DIV + when a touch pad is active sleep cycle could be divided by this number + 25 + 2 + read-write + + + TOUCH_TIMER_FORCE_DONE + force touch timer done + 27 + 2 + read-write + + + TOUCH_RESET + reset upgrade touch + 29 + 1 + read-write + + + TOUCH_CLK_FO + touch clock force on + 30 + 1 + read-write + + + TOUCH_CLKGATE_EN + touch clock enable + 31 + 1 + read-write + + + + + TOUCH_SCAN_CTRL + configure touch controller + 0x110 + 0x20 + 0xF0000102 + + + TOUCH_DENOISE_RES + De-noise resolution: 12/10/8/4 bit + 0 + 2 + read-write + + + TOUCH_DENOISE_EN + touch pad0 will be used to de-noise + 2 + 1 + read-write + + + TOUCH_INACTIVE_CONNECTION + inactive touch pads connect to 1: gnd 0: HighZ + 8 + 1 + read-write + + + TOUCH_SHIELD_PAD_EN + touch pad14 will be used as shield + 9 + 1 + read-write + + + TOUCH_SCAN_PAD_MAP + touch scan mode pad enable map + 10 + 15 + read-write + + + TOUCH_BUFDRV + touch7 buffer driver strength + 25 + 3 + read-write + + + TOUCH_OUT_RING + select out ring pad + 28 + 4 + read-write + + + + + TOUCH_SLP_THRES + configure touch controller + 0x114 + 0x20 + 0x78000000 + + + TOUCH_SLP_TH + the threshold for sleep touch pad + 0 + 22 + read-write + + + TOUCH_SLP_APPROACH_EN + sleep pad approach function enable + 26 + 1 + read-write + + + TOUCH_SLP_PAD + configure which pad as slp pad + 27 + 5 + read-write + + + + + TOUCH_APPROACH + configure touch controller + 0x118 + 0x20 + 0x50000000 + + + TOUCH_SLP_CHANNEL_CLR + clear touch slp channel + 23 + 1 + write-only + + + TOUCH_APPROACH_MEAS_TIME + approach pads total meas times + 24 + 8 + read-write + + + + + TOUCH_FILTER_CTRL + configure touch controller + 0x11C + 0x20 + 0x96AA8800 + + + TOUCH_BYPASS_NEG_NOISE_THRES + bypass neg noise thres + 7 + 1 + read-write + + + TOUCH_BYPASS_NOISE_THRES + bypaas noise thres + 8 + 1 + read-write + + + TOUCH_SMOOTH_LVL + smooth filter factor + 9 + 2 + read-write + + + TOUCH_JITTER_STEP + touch jitter step + 11 + 4 + read-write + + + TOUCH_NEG_NOISE_LIMIT + negative threshold counter limit + 15 + 4 + read-write + + + TOUCH_NEG_NOISE_THRES + neg noise thres + 19 + 2 + read-write + + + TOUCH_NOISE_THRES + noise thres + 21 + 2 + read-write + + + TOUCH_HYSTERESIS + hysteresis + 23 + 2 + read-write + + + TOUCH_DEBOUNCE + debounce counter + 25 + 3 + read-write + + + TOUCH_FILTER_MODE + 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter + 28 + 3 + read-write + + + TOUCH_FILTER_EN + touch filter enable + 31 + 1 + read-write + + + + + USB_CONF + usb configure + 0x120 + 0x20 + + + USB_VREFH + reg_usb_vrefh + 0 + 2 + read-write + + + USB_VREFL + reg_usb_vrefl + 2 + 2 + read-write + + + USB_VREF_OVERRIDE + reg_usb_vref_override + 4 + 1 + read-write + + + USB_PAD_PULL_OVERRIDE + reg_usb_pad_pull_override + 5 + 1 + read-write + + + USB_DP_PULLUP + reg_usb_dp_pullup + 6 + 1 + read-write + + + USB_DP_PULLDOWN + reg_usb_dp_pulldown + 7 + 1 + read-write + + + USB_DM_PULLUP + reg_usb_dm_pullup + 8 + 1 + read-write + + + USB_DM_PULLDOWN + reg_usb_dm_pulldown + 9 + 1 + read-write + + + USB_PULLUP_VALUE + reg_usb_pullup_value + 10 + 1 + read-write + + + USB_PAD_ENABLE_OVERRIDE + reg_usb_pad_enable_override + 11 + 1 + read-write + + + USB_PAD_ENABLE + reg_usb_pad_enable + 12 + 1 + read-write + + + USB_TXM + reg_usb_txm + 13 + 1 + read-write + + + USB_TXP + reg_usb_txp + 14 + 1 + read-write + + + USB_TX_EN + reg_usb_tx_en + 15 + 1 + read-write + + + USB_TX_EN_OVERRIDE + reg_usb_tx_en_override + 16 + 1 + read-write + + + USB_RESET_DISABLE + reg_usb_reset_disable + 17 + 1 + read-write + + + IO_MUX_RESET_DISABLE + reg_io_mux_reset_disable + 18 + 1 + read-write + + + SW_USB_PHY_SEL + reg_sw_usb_phy_sel + 19 + 1 + read-write + + + SW_HW_USB_PHY_SEL + reg_sw_hw_usb_phy_sel + 20 + 1 + read-write + + + + + TOUCH_TIMEOUT_CTRL + configure touch controller + 0x124 + 0x20 + 0x007FFFFF + + + TOUCH_TIMEOUT_NUM + configure touch timerout time + 0 + 22 + read-write + + + TOUCH_TIMEOUT_EN + enable touch timerout + 22 + 1 + read-write + + + + + SLP_REJECT_CAUSE + get reject casue + 0x128 + 0x20 + + + REJECT_CAUSE + sleep reject cause + 0 + 18 + read-only + + + + + OPTION1 + rtc common configure + 0x12C + 0x20 + + + FORCE_DOWNLOAD_BOOT + force chip entry download boot by sw + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + get wakeup cause + 0x130 + 0x20 + + + WAKEUP_CAUSE + sleep wakeup cause + 0 + 17 + read-only + + + + + ULP_CP_TIMER_1 + configure ulp sleep time + 0x134 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + INT_ENA_RTC_W1TS + oneset rtc interrupt + 0x138 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TS + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TS + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TS + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TS + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TS + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TS + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TS + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TS + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TS + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TS + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TS + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TS + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TS + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TS + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TS + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TS + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TS + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TS + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TS + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TS + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + INT_ENA_RTC_W1TC + oneset clr rtc interrupt enable + 0x13C + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TC + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TC + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TC + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TC + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TC + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TC + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TC + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TC + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TC + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TC + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TC + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TC + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TC + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TC + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TC + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TC + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TC + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TC + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TC + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TC + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + RETENTION_CTRL + configure retention + 0x140 + 0x20 + 0x28340000 + + + RETENTION_TAG_MODE + No public + 10 + 4 + read-write + + + RETENTION_TARGET + congfigure retention target cpu and/or tag + 14 + 2 + read-write + + + RETENTION_CLK_SEL + No public + 16 + 1 + read-write + + + RETENTION_DONE_WAIT + wait retention done cycle + 17 + 3 + read-write + + + RETENTION_CLKOFF_WAIT + wait clk off cycle + 20 + 4 + read-write + + + RETENTION_EN + enable retention + 24 + 1 + read-write + + + RETENTION_WAIT + wait cycles for rention operation + 25 + 7 + read-write + + + + + PG_CTRL + configure power glitch + 0x144 + 0x20 + + + POWER_GLITCH_DSENSE + GLITCH_DSENSE + 26 + 2 + read-write + + + POWER_GLITCH_FORCE_PD + force power glitch disable + 28 + 1 + read-write + + + POWER_GLITCH_FORCE_PU + force power glitch enable + 29 + 1 + read-write + + + POWER_GLITCH_EFUSE_SEL + select use analog fib signal + 30 + 1 + read-write + + + POWER_GLITCH_EN + enable power glitch + 31 + 1 + read-write + + + + + FIB_SEL + No public + 0x148 + 0x20 + 0x00000007 + + + FIB_SEL + No public + 0 + 3 + read-write + + + + + TOUCH_DAC + configure touch dac + 0x14C + 0x20 + + + TOUCH_PAD9_DAC + configure touch pad dac9 + 2 + 3 + read-write + + + TOUCH_PAD8_DAC + configure touch pad dac8 + 5 + 3 + read-write + + + TOUCH_PAD7_DAC + configure touch pad dac7 + 8 + 3 + read-write + + + TOUCH_PAD6_DAC + configure touch pad dac6 + 11 + 3 + read-write + + + TOUCH_PAD5_DAC + configure touch pad dac5 + 14 + 3 + read-write + + + TOUCH_PAD4_DAC + configure touch pad dac4 + 17 + 3 + read-write + + + TOUCH_PAD3_DAC + configure touch pad dac3 + 20 + 3 + read-write + + + TOUCH_PAD2_DAC + configure touch pad dac2 + 23 + 3 + read-write + + + TOUCH_PAD1_DAC + configure touch pad dac1 + 26 + 3 + read-write + + + TOUCH_PAD0_DAC + configure touch pad dac0 + 29 + 3 + read-write + + + + + TOUCH_DAC1 + configure touch dac + 0x150 + 0x20 + + + TOUCH_PAD14_DAC + configure touch pad dac14 + 17 + 3 + read-write + + + TOUCH_PAD13_DAC + configure touch pad dac13 + 20 + 3 + read-write + + + TOUCH_PAD12_DAC + configure touch pad dac12 + 23 + 3 + read-write + + + TOUCH_PAD11_DAC + configure touch pad dac11 + 26 + 3 + read-write + + + TOUCH_PAD10_DAC + configure touch pad dac10 + 29 + 3 + read-write + + + + + COCPU_DISABLE + configure ulp diable + 0x154 + 0x20 + + + DISABLE_RTC_CPU + configure ulp diable + 31 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02101271 + + + DATE + version register + 0 + 28 + read-write + + + + + + + RTC_I2C + Peripheral RTC_I2C + RTC_I2C + 0x60008C00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + configure low scl period + 0x0 + 0x20 + 0x00000100 + + + PERIOD + time period that scl =0 + 0 + 20 + read-write + + + + + CTRL + configure i2c ctrl + 0x4 + 0x20 + + + SDA_FORCE_OUT + 1=push pull,0=open drain + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1=push pull,0=open drain + 1 + 1 + read-write + + + MS_MODE + 1=master,0=slave + 2 + 1 + read-write + + + TRANS_START + force start + 3 + 1 + read-write + + + TX_LSB_FIRST + transit lsb first + 4 + 1 + read-write + + + RX_LSB_FIRST + receive lsb first + 5 + 1 + read-write + + + I2C_CTRL_CLK_GATE_EN + configure i2c ctrl clk enable + 29 + 1 + read-write + + + I2C_RESET + rtc i2c sw reset + 30 + 1 + read-write + + + I2CCLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + get i2c status + 0x8 + 0x20 + + + ACK_REC + ack response + 0 + 1 + read-only + + + SLAVE_RW + slave read or write + 1 + 1 + read-only + + + ARB_LOST + arbitration is lost + 2 + 1 + read-only + + + BUS_BUSY + bus is busy + 3 + 1 + read-only + + + SLAVE_ADDRESSED + slave reg sub address + 4 + 1 + read-only + + + BYTE_TRANS + One byte transit done + 5 + 1 + read-only + + + OP_CNT + which operation is working + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + configure time out + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + time out threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + configure slave id + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + i2c 10bit mode enable + 31 + 1 + read-write + + + + + SCL_HIGH + configure high scl period + 0x14 + 0x20 + 0x00000100 + + + PERIOD + time period that scl = 1 + 0 + 20 + read-write + + + + + SDA_DUTY + configure sda duty + 0x18 + 0x20 + 0x00000010 + + + NUM + time period for SDA to toggle after SCL goes low + 0 + 20 + read-write + + + + + SCL_START_PERIOD + configure scl start period + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + time period for SCL to toggle after I2C start is triggered + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + configure scl stop period + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + time period for SCL to stop after I2C end is triggered + 0 + 20 + read-write + + + + + INT_CLR + interrupt clear register + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + clear slave transit complete interrupt + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + clear arbitration lost interrupt + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + clear master transit complete interrupt + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + clear transit complete interrupt + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + clear time out interrupt + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + clear ack error interrupt + 5 + 1 + write-only + + + RX_DATA_INT_CLR + clear receive data interrupt + 6 + 1 + write-only + + + TX_DATA_INT_CLR + clear transit load data complete interrupt + 7 + 1 + write-only + + + DETECT_START_INT_CLR + clear detect start interrupt + 8 + 1 + write-only + + + + + INT_RAW + interrupt raw register + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + slave transit complete interrupt raw + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + arbitration lost interrupt raw + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + master transit complete interrupt raw + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + transit complete interrupt raw + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + time out interrupt raw + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + ack error interrupt raw + 5 + 1 + read-only + + + RX_DATA_INT_RAW + receive data interrupt raw + 6 + 1 + read-only + + + TX_DATA_INT_RAW + transit data interrupt raw + 7 + 1 + read-only + + + DETECT_START_INT_RAW + detect start interrupt raw + 8 + 1 + read-only + + + + + INT_ST + interrupt state register + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + slave transit complete interrupt state + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + arbitration lost interrupt state + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + master transit complete interrupt state + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + transit complete interrupt state + 3 + 1 + read-only + + + TIME_OUT_INT_ST + time out interrupt state + 4 + 1 + read-only + + + ACK_ERR_INT_ST + ack error interrupt state + 5 + 1 + read-only + + + RX_DATA_INT_ST + receive data interrupt state + 6 + 1 + read-only + + + TX_DATA_INT_ST + transit data interrupt state + 7 + 1 + read-only + + + DETECT_START_INT_ST + detect start interrupt state + 8 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + enable slave transit complete interrupt + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + enable arbitration lost interrupt + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + enable master transit complete interrupt + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + enable transit complete interrupt + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + enable time out interrupt + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + enable eack error interrupt + 5 + 1 + read-write + + + RX_DATA_INT_ENA + enable receive data interrupt + 6 + 1 + read-write + + + TX_DATA_INT_ENA + enable transit data interrupt + 7 + 1 + read-write + + + DETECT_START_INT_ENA + enable detect start interrupt + 8 + 1 + read-write + + + + + DATA + get i2c data status + 0x34 + 0x20 + + + I2C_RDATA + data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + data sent by slave + 8 + 8 + read-write + + + I2C_DONE + i2c done + 31 + 1 + read-only + + + + + CMD0 + i2c commond0 register + 0x38 + 0x20 + 0x00000903 + + + COMMAND0 + command0 + 0 + 14 + read-write + + + COMMAND0_DONE + command0_done + 31 + 1 + read-only + + + + + CMD1 + i2c commond1 register + 0x3C + 0x20 + 0x00001901 + + + COMMAND1 + command1 + 0 + 14 + read-write + + + COMMAND1_DONE + command1_done + 31 + 1 + read-only + + + + + CMD2 + i2c commond2 register + 0x40 + 0x20 + 0x00000902 + + + COMMAND2 + command2 + 0 + 14 + read-write + + + COMMAND2_DONE + command2_done + 31 + 1 + read-only + + + + + CMD3 + i2c commond3 register + 0x44 + 0x20 + 0x00000101 + + + COMMAND3 + command3 + 0 + 14 + read-write + + + COMMAND3_DONE + command3_done + 31 + 1 + read-only + + + + + CMD4 + i2c commond4 register + 0x48 + 0x20 + 0x00000901 + + + COMMAND4 + command4 + 0 + 14 + read-write + + + COMMAND4_DONE + command4_done + 31 + 1 + read-only + + + + + CMD5 + i2c commond5_register + 0x4C + 0x20 + 0x00001701 + + + COMMAND5 + command5 + 0 + 14 + read-write + + + COMMAND5_DONE + command5_done + 31 + 1 + read-only + + + + + CMD6 + i2c commond6 register + 0x50 + 0x20 + 0x00001901 + + + COMMAND6 + command6 + 0 + 14 + read-write + + + COMMAND6_DONE + command6_done + 31 + 1 + read-only + + + + + CMD7 + i2c commond7 register + 0x54 + 0x20 + 0x00000904 + + + COMMAND7 + command7 + 0 + 14 + read-write + + + COMMAND7_DONE + command7_done + 31 + 1 + read-only + + + + + CMD8 + i2c commond8 register + 0x58 + 0x20 + 0x00001901 + + + COMMAND8 + command8 + 0 + 14 + read-write + + + COMMAND8_DONE + command8_done + 31 + 1 + read-only + + + + + CMD9 + i2c commond9 register + 0x5C + 0x20 + 0x00000903 + + + COMMAND9 + command9 + 0 + 14 + read-write + + + COMMAND9_DONE + command9_done + 31 + 1 + read-only + + + + + CMD10 + i2c commond10 register + 0x60 + 0x20 + 0x00000101 + + + COMMAND10 + command10 + 0 + 14 + read-write + + + COMMAND10_DONE + command10_done + 31 + 1 + read-only + + + + + CMD11 + i2c commond11 register + 0x64 + 0x20 + 0x00000901 + + + COMMAND11 + command11 + 0 + 14 + read-write + + + COMMAND11_DONE + command11_done + 31 + 1 + read-only + + + + + CMD12 + i2c commond12 register + 0x68 + 0x20 + 0x00001701 + + + COMMAND12 + command12 + 0 + 14 + read-write + + + COMMAND12_DONE + command12_done + 31 + 1 + read-only + + + + + CMD13 + i2c commond13 register + 0x6C + 0x20 + 0x00001901 + + + COMMAND13 + command13 + 0 + 14 + read-write + + + COMMAND13_DONE + command13_done + 31 + 1 + read-only + + + + + CMD14 + i2c commond14 register + 0x70 + 0x20 + + + COMMAND14 + command14 + 0 + 14 + read-write + + + COMMAND14_DONE + command14_done + 31 + 1 + read-only + + + + + CMD15 + i2c commond15 register + 0x74 + 0x20 + + + COMMAND15 + command15 + 0 + 14 + read-write + + + COMMAND15_DONE + command15_done + 31 + 1 + read-only + + + + + DATE + version register + 0xFC + 0x20 + 0x01905310 + + + I2C_DATE + version + 0 + 28 + read-write + + + + + + + RTCIO + Peripheral RTC_IO + RTC_IO + 0x60008400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO 0 ~ 21 output data register + 0x0 + 0x20 + + + DATA + RTC GPIO 0 ~ 21 output data + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + one set RTC GPIO output data + 0x4 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TS + RTC GPIO 0 ~ 21 output data write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + one clear RTC GPIO output data + 0x8 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TC + RTC GPIO 0 ~ 21 output data write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + Configure RTC GPIO output enable + 0xC + 0x20 + + + RTC_GPIO_ENABLE + RTC GPIO 0 ~ 21 enable + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + one set RTC GPIO output enable + 0x10 + 0x20 + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO 0 ~ 21 enable write 1 to set + 10 + 22 + write-only + + + + + ENABLE_W1TC + one clear RTC GPIO output enable + 0x14 + 0x20 + + + ENABLE_W1TC + RTC GPIO 0 ~ 21 enable write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO 0 ~ 21 interrupt status + 0x18 + 0x20 + + + INT + RTC GPIO 0 ~ 21 interrupt status + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + One set RTC GPIO 0 ~ 21 interrupt status + 0x1C + 0x20 + + + RTC_GPIO_STATUS_INT_W1TS + RTC GPIO 0 ~ 21 interrupt status write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + One clear RTC GPIO 0 ~ 21 interrupt status + 0x20 + 0x20 + + + RTC_GPIO_STATUS_INT_W1TC + RTC GPIO 0 ~ 21 interrupt status write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input data + 0x24 + 0x20 + + + NEXT + RTC GPIO input data + 10 + 22 + read-only + + + + + 22 + 0x4 + 0-21 + PIN%s + configure RTC GPIO%s + 0x28 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + configure rtc debug + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + configure rtc debug + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + configure rtc debug + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + configure rtc debug + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + configure rtc debug + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + configure rtc debug + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + configure rtc debug + 25 + 1 + read-write + + + + + TOUCH_PAD0 + configure RTC PAD0 + 0x84 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD1 + configure RTC PAD1 + 0x88 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD2 + configure RTC PAD2 + 0x8C + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD3 + configure RTC PAD3 + 0x90 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD4 + configure RTC PAD4 + 0x94 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD5 + configure RTC PAD5 + 0x98 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD6 + configure RTC PAD6 + 0x9C + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD7 + configure RTC PAD7 + 0xA0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD8 + configure RTC PAD8 + 0xA4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD9 + configure RTC PAD9 + 0xA8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD10 + configure RTC PAD10 + 0xAC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD11 + configure RTC PAD11 + 0xB0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD12 + configure RTC PAD12 + 0xB4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD13 + configure RTC PAD13 + 0xB8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD14 + configure RTC PAD14 + 0xBC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32P_PAD + configure RTC PAD15 + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32P_FUN_SEL + function sel + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32P_RUE + RUE + 27 + 1 + read-write + + + X32P_RDE + RDE + 28 + 1 + read-write + + + X32P_DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32N_PAD + configure RTC PAD16 + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32N_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32N_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32N_FUN_SEL + function sel + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32N_RUE + RUE + 27 + 1 + read-write + + + X32N_RDE + RDE + 28 + 1 + read-write + + + X32N_DRV + DRV + 29 + 2 + read-write + + + + + PAD_DAC1 + configure RTC PAD17 + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + PDAC1_DAC + 3 + 8 + read-write + + + PDAC1_XPD_DAC + PDAC1_XPD_DAC + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC + 12 + 1 + read-write + + + PDAC1_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC1_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + PDAC1_RUE + 27 + 1 + read-write + + + PDAC1_RDE + PDAC1_RDE + 28 + 1 + read-write + + + PDAC1_DRV + PDAC1_DRV + 29 + 2 + read-write + + + + + PAD_DAC2 + configure RTC PAD18 + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + PDAC2_DAC + 3 + 8 + read-write + + + PDAC2_XPD_DAC + PDAC2_XPD_DAC + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC + 12 + 1 + read-write + + + PDAC2_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC2_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC2_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC2_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC2_RUE + PDAC2_RUE + 27 + 1 + read-write + + + PDAC2_RDE + PDAC2_RDE + 28 + 1 + read-write + + + PDAC2_DRV + PDAC2_DRV + 29 + 2 + read-write + + + + + RTC_PAD19 + configure RTC PAD19 + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD20 + configure RTC PAD20 + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD21 + configure RTC PAD21 + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + configure EXT0 wakeup + 0xDC + 0x20 + + + SEL + ******* Description configure*** + 27 + 5 + read-write + + + + + XTL_EXT_CTR + configure gpio pd XTAL + 0xE0 + 0x20 + + + SEL + select RTC GPIO 0 ~ 17 to control XTAL + 27 + 5 + read-write + + + + + SAR_I2C_IO + configure rtc i2c mux + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + ******* Description configure*** + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + ******* Description configure*** + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + ******* Description configure*** + 30 + 2 + read-write + + + + + TOUCH_CTRL + configure touch pad bufmode + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + BUF_SEL when touch work without fsm + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + BUF_MODE when touch work without fsm + 4 + 1 + read-write + + + + + DATE + version + 0x1FC + 0x20 + 0x02101180 + + + DATE + version + 0 + 28 + read-write + + + + + + + SENS + Peripheral SENS + SENS + 0x60008800 + + 0x0 + 0x11C + registers + + + + SAR_READER1_CTRL + configure saradc1 reader + 0x0 + 0x20 + 0x20040002 + + + SAR_SAR1_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR1_CLK_GATED + no public + 18 + 1 + read-write + + + SAR_SAR1_SAMPLE_NUM + no public + 19 + 8 + read-write + + + SAR_SAR1_DATA_INV + Invert SAR ADC1 data + 28 + 1 + read-write + + + SAR_SAR1_INT_EN + enable saradc1 to send out interrupt + 29 + 1 + read-write + + + + + SAR_READER1_STATUS + get saradc1 reader controller status + 0x4 + 0x20 + + + SAR_SAR1_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS1_CTRL1 + no public + 0x8 + 0x20 + + + SAR_FORCE_XPD_AMP + no public + 24 + 2 + read-write + + + SAR_AMP_RST_FB_FORCE + no public + 26 + 2 + read-write + + + SAR_AMP_SHORT_REF_FORCE + no public + 28 + 2 + read-write + + + SAR_AMP_SHORT_REF_GND_FORCE + no public + 30 + 2 + read-write + + + + + SAR_MEAS1_CTRL2 + configure saradc1 controller + 0xC + 0x20 + + + SAR_MEAS1_DATA_SAR + SAR ADC1 data + 0 + 16 + read-only + + + SAR_MEAS1_DONE_SAR + SAR ADC1 conversion done indication + 16 + 1 + read-only + + + SAR_MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion + 17 + 1 + read-write + + + SAR_MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR_SAR1_EN_PAD + SAR ADC1 pad enable bitmap + 19 + 12 + read-write + + + SAR_SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS1_MUX + configure saradc1 controller + 0x10 + 0x20 + + + SAR_SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL + 31 + 1 + read-write + + + + + SAR_ATTEN1 + configure saradc1 controller + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR_SAR1_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_AMP_CTRL1 + no public + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + no public + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL2 + no public + 0x1C + 0x20 + 0x000A0000 + + + SAR_SAR1_DAC_XPD_FSM_IDLE + no public + 0 + 1 + read-write + + + SAR_XPD_SAR_AMP_FSM_IDLE + no public + 1 + 1 + read-write + + + SAR_AMP_RST_FB_FSM_IDLE + no public + 2 + 1 + read-write + + + SAR_AMP_SHORT_REF_FSM_IDLE + no public + 3 + 1 + read-write + + + SAR_AMP_SHORT_REF_GND_FSM_IDLE + no public + 4 + 1 + read-write + + + SAR_XPD_SAR_FSM_IDLE + no public + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + no public + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL3 + no public + 0x20 + 0x20 + 0x007338F3 + + + SAR_SAR1_DAC_XPD_FSM + no public + 0 + 4 + read-write + + + SAR_XPD_SAR_AMP_FSM + no public + 4 + 4 + read-write + + + SAR_AMP_RST_FB_FSM + no public + 8 + 4 + read-write + + + SAR_AMP_SHORT_REF_FSM + no public + 12 + 4 + read-write + + + SAR_AMP_SHORT_REF_GND_FSM + no public + 16 + 4 + read-write + + + SAR_XPD_SAR_FSM + no public + 20 + 4 + read-write + + + SAR_RSTB_FSM + no public + 24 + 4 + read-write + + + + + SAR_READER2_CTRL + configure saradc2 reader + 0x24 + 0x20 + 0x40050002 + + + SAR_SAR2_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR2_WAIT_ARB_CYCLE + wait arbit stable after sar_done + 16 + 2 + read-write + + + SAR_SAR2_CLK_GATED + ******* Description *********** + 18 + 1 + read-write + + + SAR_SAR2_SAMPLE_NUM + ******* Description *********** + 19 + 8 + read-write + + + SAR_SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 + read-write + + + SAR_SAR2_INT_EN + enable saradc2 to send out interrupt + 30 + 1 + read-write + + + + + SAR_READER2_STATUS + get saradc1 reader controller status + 0x28 + 0x20 + + + SAR_SAR2_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS2_CTRL1 + configure saradc2 controller + 0x2C + 0x20 + 0x07020200 + + + SAR_SAR2_CNTL_STATE + saradc2_cntl_fsm + 0 + 3 + read-only + + + SAR_SAR2_PWDET_CAL_EN + rtc control pwdet enable + 3 + 1 + read-write + + + SAR_SAR2_PKDET_CAL_EN + rtc control pkdet enable + 4 + 1 + read-write + + + SAR_SAR2_EN_TEST + SAR2_EN_TEST + 5 + 1 + read-write + + + SAR_SAR2_RSTB_FORCE + no public + 6 + 2 + read-write + + + SAR_SAR2_STANDBY_WAIT + no public + 8 + 8 + read-write + + + SAR_SAR2_RSTB_WAIT + no public + 16 + 8 + read-write + + + SAR_SAR2_XPD_WAIT + no public + 24 + 8 + read-write + + + + + SAR_MEAS2_CTRL2 + configure saradc2 controller + 0x30 + 0x20 + + + SAR_MEAS2_DATA_SAR + SAR ADC2 data + 0 + 16 + read-only + + + SAR_MEAS2_DONE_SAR + SAR ADC2 conversion done indication + 16 + 1 + read-only + + + SAR_MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion + 17 + 1 + read-write + + + SAR_MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR_SAR2_EN_PAD + SAR ADC2 pad enable bitmap + 19 + 12 + read-write + + + SAR_SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS2_MUX + configure saradc2 controller + 0x34 + 0x20 + + + SAR_SAR2_PWDET_CCT + SAR2_PWDET_CCT + 28 + 3 + read-write + + + SAR_SAR2_RTC_FORCE + in sleep, force to use rtc to control ADC + 31 + 1 + read-write + + + + + SAR_ATTEN2 + configure saradc2 controller + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR_SAR2_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_POWER_XPD_SAR + configure power of saradc + 0x3C + 0x20 + + + SAR_FORCE_XPD_SAR + force power on/off saradc + 29 + 2 + read-write + + + SAR_SARCLK_EN + no public + 31 + 1 + read-write + + + + + SAR_SLAVE_ADDR1 + configure i2c slave address + 0x40 + 0x20 + + + SAR_I2C_SLAVE_ADDR1 + configure i2c slave address1 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR0 + configure i2c slave address0 + 11 + 11 + read-write + + + SAR_SARADC_MEAS_STATUS + no public + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + configure i2c slave address + 0x44 + 0x20 + + + SAR_I2C_SLAVE_ADDR3 + configure i2c slave address3 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR2 + configure i2c slave address2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + configure i2c slave address + 0x48 + 0x20 + + + SAR_I2C_SLAVE_ADDR5 + configure i2c slave address5 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR4 + configure i2c slave address4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + configure i2c slave address + 0x4C + 0x20 + + + SAR_I2C_SLAVE_ADDR7 + configure i2c slave address7 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR6 + configure i2c slave address6 + 11 + 11 + read-write + + + + + SAR_TSENS_CTRL + configure tsens controller + 0x50 + 0x20 + 0x00019000 + + + SAR_TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + SAR_TSENS_READY + indicate temperature sensor out ready + 8 + 1 + read-only + + + SAR_TSENS_INT_EN + enable temperature sensor to send out interrupt + 12 + 1 + read-write + + + SAR_TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + SAR_TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + SAR_TSENS_POWER_UP + temperature sensor power up + 22 + 1 + read-write + + + SAR_TSENS_POWER_UP_FORCE + 1: dump out & power up controlled by SW 0: by FSM + 23 + 1 + read-write + + + SAR_TSENS_DUMP_OUT + temperature sensor dump out only active when reg_tsens_power_up_force = 1 + 24 + 1 + read-write + + + + + SAR_TSENS_CTRL2 + configure tsens controller + 0x54 + 0x20 + 0x00004002 + + + SAR_TSENS_XPD_WAIT + no public + 0 + 12 + read-write + + + SAR_TSENS_XPD_FORCE + no public + 12 + 2 + read-write + + + SAR_TSENS_CLK_INV + no public + 14 + 1 + read-write + + + + + SAR_I2C_CTRL + configure rtc i2c controller by sw + 0x58 + 0x20 + + + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 + 0 + 28 + read-write + + + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 + 1 + read-write + + + + + SAR_TOUCH_CONF + configure touch controller + 0x5C + 0x20 + 0xFFF07FFF + + + SAR_TOUCH_OUTEN + touch controller output enable + 0 + 15 + read-write + + + SAR_TOUCH_STATUS_CLR + clear all touch active status + 15 + 1 + write-only + + + SAR_TOUCH_DATA_SEL + 3: smooth data 2: baseline 1,0: raw_data + 16 + 2 + read-write + + + SAR_TOUCH_DENOISE_END + touch_denoise_done + 18 + 1 + read-only + + + SAR_TOUCH_UNIT_END + touch_unit_done + 19 + 1 + read-only + + + SAR_TOUCH_APPROACH_PAD2 + indicate which pad is approach pad2 + 20 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD1 + indicate which pad is approach pad1 + 24 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD0 + indicate which pad is approach pad0 + 28 + 4 + read-write + + + + + SAR_TOUCH_DENOISE + configure touch controller + 0x60 + 0x20 + + + DATA + configure touch controller + 0 + 22 + read-only + + + + + SAR_TOUCH_THRES1 + configure touch thres of touch pad + 0x64 + 0x20 + + + SAR_TOUCH_OUT_TH1 + Finger threshold for touch pad 1 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES2 + configure touch thres of touch pad + 0x68 + 0x20 + + + SAR_TOUCH_OUT_TH2 + Finger threshold for touch pad 2 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES3 + configure touch thres of touch pad + 0x6C + 0x20 + + + SAR_TOUCH_OUT_TH3 + Finger threshold for touch pad 3 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES4 + configure touch thres of touch pad + 0x70 + 0x20 + + + SAR_TOUCH_OUT_TH4 + Finger threshold for touch pad 4 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES5 + configure touch thres of touch pad + 0x74 + 0x20 + + + SAR_TOUCH_OUT_TH5 + Finger threshold for touch pad 5 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES6 + configure touch thres of touch pad + 0x78 + 0x20 + + + SAR_TOUCH_OUT_TH6 + Finger threshold for touch pad 6 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES7 + configure touch thres of touch pad + 0x7C + 0x20 + + + SAR_TOUCH_OUT_TH7 + Finger threshold for touch pad 7 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES8 + configure touch thres of touch pad + 0x80 + 0x20 + + + SAR_TOUCH_OUT_TH8 + Finger threshold for touch pad 8 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES9 + configure touch thres of touch pad + 0x84 + 0x20 + + + SAR_TOUCH_OUT_TH9 + Finger threshold for touch pad 9 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES10 + configure touch thres of touch pad + 0x88 + 0x20 + + + SAR_TOUCH_OUT_TH10 + Finger threshold for touch pad 10 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES11 + configure touch thres of touch pad + 0x8C + 0x20 + + + SAR_TOUCH_OUT_TH11 + Finger threshold for touch pad 11 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES12 + configure touch thres of touch pad + 0x90 + 0x20 + + + SAR_TOUCH_OUT_TH12 + Finger threshold for touch pad 12 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES13 + configure touch thres of touch pad + 0x94 + 0x20 + + + SAR_TOUCH_OUT_TH13 + Finger threshold for touch pad 13 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES14 + configure touch thres of touch pad + 0x98 + 0x20 + + + SAR_TOUCH_OUT_TH14 + Finger threshold for touch pad 14 + 0 + 22 + read-write + + + + + SAR_TOUCH_CHN_ST + Get touch channel status + 0x9C + 0x20 + + + SAR_TOUCH_PAD_ACTIVE + touch active status + 0 + 15 + read-only + + + SAR_TOUCH_CHANNEL_CLR + Clear touch channel + 15 + 15 + write-only + + + SAR_TOUCH_MEAS_DONE + get touch meas done + 31 + 1 + read-only + + + + + SAR_TOUCH_STATUS0 + get touch scan status + 0xA0 + 0x20 + + + SAR_TOUCH_SCAN_CURR + current sample channel + 22 + 4 + read-only + + + + + SAR_TOUCH_STATUS1 + touch channel status of touch pad 1 + 0xA4 + 0x20 + + + SAR_TOUCH_PAD1_DATA + touch data debounce of touch pad 1 + 0 + 22 + read-only + + + SAR_TOUCH_PAD1_DEBOUNCE + touch current debounce of touch pad 1 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS2 + touch channel status of touch pad 2 + 0xA8 + 0x20 + + + SAR_TOUCH_PAD2_DATA + touch data debounce of touch pad 2 + 0 + 22 + read-only + + + SAR_TOUCH_PAD2_DEBOUNCE + touch current debounce of touch pad 2 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS3 + touch channel status of touch pad 3 + 0xAC + 0x20 + + + SAR_TOUCH_PAD3_DATA + touch data debounce of touch pad 3 + 0 + 22 + read-only + + + SAR_TOUCH_PAD3_DEBOUNCE + touch current debounce of touch pad 3 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS4 + touch channel status of touch pad 4 + 0xB0 + 0x20 + + + SAR_TOUCH_PAD4_DATA + touch data debounce of touch pad 4 + 0 + 22 + read-only + + + SAR_TOUCH_PAD4_DEBOUNCE + touch current debounce of touch pad 4 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS5 + touch channel status of touch pad 5 + 0xB4 + 0x20 + + + SAR_TOUCH_PAD5_DATA + touch data debounce of touch pad 5 + 0 + 22 + read-only + + + SAR_TOUCH_PAD5_DEBOUNCE + touch current debounce of touch pad 5 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS6 + touch channel status of touch pad 6 + 0xB8 + 0x20 + + + SAR_TOUCH_PAD6_DATA + touch data debounce of touch pad 6 + 0 + 22 + read-only + + + SAR_TOUCH_PAD6_DEBOUNCE + touch current debounce of touch pad 6 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS7 + touch channel status of touch pad 7 + 0xBC + 0x20 + + + SAR_TOUCH_PAD7_DATA + touch data debounce of touch pad 7 + 0 + 22 + read-only + + + SAR_TOUCH_PAD7_DEBOUNCE + touch current debounce of touch pad 7 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS8 + touch channel status of touch pad 8 + 0xC0 + 0x20 + + + SAR_TOUCH_PAD8_DATA + touch data debounce of touch pad 8 + 0 + 22 + read-only + + + SAR_TOUCH_PAD8_DEBOUNCE + touch current debounce of touch pad 8 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS9 + touch channel status of touch pad 9 + 0xC4 + 0x20 + + + SAR_TOUCH_PAD9_DATA + touch data debounce of touch pad 9 + 0 + 22 + read-only + + + SAR_TOUCH_PAD9_DEBOUNCE + touch current debounce of touch pad 9 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS10 + touch channel status of touch pad 10 + 0xC8 + 0x20 + + + SAR_TOUCH_PAD10_DATA + touch data debounce of touch pad 10 + 0 + 22 + read-only + + + SAR_TOUCH_PAD10_DEBOUNCE + touch current debounce of touch pad 10 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS11 + touch channel status of touch pad 11 + 0xCC + 0x20 + + + SAR_TOUCH_PAD11_DATA + touch data debounce of touch pad 11 + 0 + 22 + read-only + + + SAR_TOUCH_PAD11_DEBOUNCE + touch current debounce of touch pad 11 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS12 + touch channel status of touch pad 12 + 0xD0 + 0x20 + + + SAR_TOUCH_PAD12_DATA + touch data debounce of touch pad 12 + 0 + 22 + read-only + + + SAR_TOUCH_PAD12_DEBOUNCE + touch current debounce of touch pad 12 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS13 + touch channel status of touch pad 13 + 0xD4 + 0x20 + + + SAR_TOUCH_PAD13_DATA + touch data debounce of touch pad 13 + 0 + 22 + read-only + + + SAR_TOUCH_PAD13_DEBOUNCE + touch current debounce of touch pad 13 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS14 + touch channel status of touch pad 14 + 0xD8 + 0x20 + + + SAR_TOUCH_PAD14_DATA + touch data debounce of touch pad 14 + 0 + 22 + read-only + + + SAR_TOUCH_PAD14_DEBOUNCE + touch current debounce of touch pad 14 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS15 + touch channel status of sleep pad + 0xDC + 0x20 + + + SAR_TOUCH_SLP_DATA + touch data debounce of sleep pad + 0 + 22 + read-only + + + SAR_TOUCH_SLP_DEBOUNCE + touch current debounce of sleep pad + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS16 + touch channel status of approach mode + 0xE0 + 0x20 + + + SAR_TOUCH_APPROACH_PAD2_CNT + touch current approach count of approach pad2 + 0 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD1_CNT + touch current approach count of approach pad1 + 8 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD0_CNT + touch current approach count of approach pad0 + 16 + 8 + read-only + + + SAR_TOUCH_SLP_APPROACH_CNT + touch current approach count of slp pad + 24 + 8 + read-only + + + + + SAR_COCPU_STATE + get cocpu status + 0xE4 + 0x20 + + + SAR_COCPU_DBG_TRIGGER + trigger cocpu debug registers + 25 + 1 + write-only + + + SAR_COCPU_CLK_EN_ST + check cocpu whether clk on + 26 + 1 + read-only + + + SAR_COCPU_RESET_N + check cocpu whether in reset state + 27 + 1 + read-only + + + SAR_COCPU_EOI + check cocpu whether in interrupt state + 28 + 1 + read-only + + + SAR_COCPU_TRAP + check cocpu whether in trap state + 29 + 1 + read-only + + + SAR_COCPU_EBREAK + check cocpu whether in ebreak + 30 + 1 + read-only + + + + + SAR_COCPU_INT_RAW + the interrupt raw of ulp + 0xE8 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_RAW + int from touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_RAW + int from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_RAW + int from touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_RAW + int from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_RAW + int from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_RAW + int from tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_RAW + int from start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_RAW + int from software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_RAW + int from super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + int from timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + int from approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + int from touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + the interrupt enable of ulp + 0xEC + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA + int enable of touch done + 0 + 1 + read-write + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA + int enable of from touch inactive + 1 + 1 + read-write + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA + int enable of touch active + 2 + 1 + read-write + + + SAR_COCPU_SARADC1_INT_ENA + int enable of from saradc1 + 3 + 1 + read-write + + + SAR_COCPU_SARADC2_INT_ENA + int enable of from saradc2 + 4 + 1 + read-write + + + SAR_COCPU_TSENS_INT_ENA + int enable of tsens + 5 + 1 + read-write + + + SAR_COCPU_START_INT_ENA + int enable of start + 6 + 1 + read-write + + + SAR_COCPU_SW_INT_ENA + int enable of software + 7 + 1 + read-write + + + SAR_COCPU_SWD_INT_ENA + int enable of super watch dog + 8 + 1 + read-write + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + int enable of timeout done + 9 + 1 + read-write + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + int enable of approach loop done + 10 + 1 + read-write + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + int enable of touch scan done + 11 + 1 + read-write + + + + + SAR_COCPU_INT_ST + the interrupt state of ulp + 0xF0 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ST + int state of touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ST + int state of from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ST + int state of touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_ST + int state of from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_ST + int state of from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_ST + int state of tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_ST + int state of start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_ST + int state of software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_ST + int state of super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ST + int state of timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + int state of approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + int state of touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + the interrupt clear of ulp + 0xF4 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_CLR + int clear of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_CLR + int clear of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_CLR + int clear of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_CLR + int clear of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_CLR + int clear of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_CLR + int clear of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_CLR + int clear of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_CLR + int clear of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_CLR + int clear of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + int clear of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + int clear of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + int clear of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_DEBUG + Ulp-riscv debug signal + 0xF8 + 0x20 + + + SAR_COCPU_PC + cocpu Program counter + 0 + 13 + read-only + + + SAR_COCPU_MEM_VLD + cocpu mem valid output + 13 + 1 + read-only + + + SAR_COCPU_MEM_RDY + cocpu mem ready input + 14 + 1 + read-only + + + SAR_COCPU_MEM_WEN + cocpu mem write enable output + 15 + 4 + read-only + + + SAR_COCPU_MEM_ADDR + cocpu mem address output + 19 + 13 + read-only + + + + + SAR_HALL_CTRL + no public + 0xFC + 0x20 + 0xA0000000 + + + SAR_XPD_HALL + Power on hall sensor and connect to VP and VN + 28 + 1 + read-write + + + SAR_XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 29 + 1 + read-write + + + SAR_HALL_PHASE + Reverse phase of hall sensor + 30 + 1 + read-write + + + SAR_HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_NOUSE + no public + 0x100 + 0x20 + + + SAR_NOUSE + no public + 0 + 32 + read-write + + + + + SAR_PERI_CLK_GATE_CONF + the peri clock gate of rtc peri + 0x104 + 0x20 + + + SAR_RTC_I2C_CLK_EN + enable rtc i2c clock + 27 + 1 + read-write + + + SAR_TSENS_CLK_EN + enable tsens clock + 29 + 1 + read-write + + + SAR_SARADC_CLK_EN + enbale saradc clock + 30 + 1 + read-write + + + SAR_IOMUX_CLK_EN + enable io_mux clock + 31 + 1 + read-write + + + + + SAR_PERI_RESET_CONF + the peri reset of rtc peri + 0x108 + 0x20 + + + SAR_COCPU_RESET + enable ulp-riscv reset + 25 + 1 + read-write + + + SAR_RTC_I2C_RESET + Reserved. + 27 + 1 + read-write + + + SAR_TSENS_RESET + enbale saradc reset + 29 + 1 + read-write + + + SAR_SARADC_RESET + enable io_mux reset + 30 + 1 + read-write + + + + + SAR_COCPU_INT_ENA_W1TS + the interrupt enable of ulp + 0x10C + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS + int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS + int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS + int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TS + int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TS + int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TS + int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TS + int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TS + int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TS + int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS + int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS + int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_INT_ENA_W1TC + the interrupt enable clear of ulp + 0x110 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC + Clear int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC + Clear int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC + Clear int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TC + Clear int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TC + Clear int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TC + Clear int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TC + Clear int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TC + Clear int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TC + Clear int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC + Clear int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + Clear int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC + Clear int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_DEBUG_CONF + rtc peri debug configure + 0x114 + 0x20 + + + SAR_DEBUG_BIT_SEL + no public + 0 + 5 + read-write + + + + + SAR_SARDATE + version + 0x1FC + 0x20 + 0x02101180 + + + SAR_DATE + version + 0 + 28 + read-write + + + + + + + SENSITIVE + Peripheral SENSITIVE + SENSITIVE + 0x600C1000 + + 0x0 + 0x314 + registers + + + + CACHE_DATAARRAY_CONNECT_0 + Cache data array configuration register 0. + 0x0 + 0x20 + + + CACHE_DATAARRAY_CONNECT_LOCK + Set 1 to lock cache data array registers. + 0 + 1 + read-write + + + + + CACHE_DATAARRAY_CONNECT_1 + Cache data array configuration register 1. + 0x4 + 0x20 + 0x000000FF + + + CACHE_DATAARRAY_CONNECT_FLATTEN + Cache data array connection configuration. + 0 + 8 + read-write + + + + + APB_PERIPHERAL_ACCESS_0 + APB peripheral configuration register 0. + 0x8 + 0x20 + + + APB_PERIPHERAL_ACCESS_LOCK + Set 1 to lock APB peripheral Configuration Register. + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_1 + APB peripheral configuration register 1. + 0xC + 0x20 + 0x00000001 + + + APB_PERIPHERAL_ACCESS_SPLIT_BURST + Set 1 to support split function for AHB access to APB peripherals. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_0 + Internal SRAM configuration register 0. + 0x10 + 0x20 + + + INTERNAL_SRAM_USAGE_LOCK + Set 1 to lock internal SRAM Configuration Register. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_1 + Internal SRAM configuration register 1. + 0x14 + 0x20 + 0x000007FF + + + INTERNAL_SRAM_ICACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. + 0 + 2 + read-write + + + INTERNAL_SRAM_DCACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. + 2 + 2 + read-write + + + INTERNAL_SRAM_CPU_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. + 4 + 7 + read-write + + + + + INTERNAL_SRAM_USAGE_2 + Internal SRAM configuration register 2. + 0x18 + 0x20 + + + INTERNAL_SRAM_CORE0_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + 0 + 7 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + 7 + 7 + read-write + + + INTERNAL_SRAM_CORE0_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. + 14 + 2 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + 16 + 2 + read-write + + + + + INTERNAL_SRAM_USAGE_3 + Internal SRAM configuration register 3. + 0x1C + 0x20 + + + INTERNAL_SRAM_MAC_DUMP_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + 0 + 4 + read-write + + + + + INTERNAL_SRAM_USAGE_4 + Internal SRAM configuration register 4. + 0x20 + 0x20 + + + INTERNAL_SRAM_LOG_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + 0 + 7 + read-write + + + + + RETENTION_DISABLE + Retention configuration register. + 0x24 + 0x20 + + + RETENTION_DISABLE + Set 1 to disable retention function and lock disable state. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_0 + Cache tag configuration register 0. + 0x28 + 0x20 + + + CACHE_TAG_ACCESS_LOCK + Set 1 to lock cache tag Configuration Register. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + Cache tag configuration register 1. + 0x2C + 0x20 + 0x0000000F + + + PRO_I_TAG_RD_ACS + Set 1 to enable Icache read access tag memory. + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + Set 1 to enable Icache wrtie access tag memory. + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + Set 1 to enable Dcache read access tag memory. + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + Set 1 to enable Dcache wrtie access tag memory. + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + Cache MMU configuration register 0. + 0x30 + 0x20 + + + CACHE_MMU_ACCESS_LOCK + Set 1 to lock cache MMU registers. + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + Cache MMU configuration register 1. + 0x34 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + Set 1 to enable read access MMU memory. + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Set 1 to enable write access MMU memory. + 1 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + spi2 dma permission configuration register 0. + 0x38 + 0x20 + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + Set 1 to lock spi2 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + spi2 dma permission configuration register 1. + 0x3C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 + spi2's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 + spi2's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 + spi2's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 + spi2's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi2's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi2's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 + spi3 dma permission configuration register 0. + 0x40 + 0x20 + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK + Set 1 to lock spi3 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 + spi3 dma permission configuration register 1. + 0x44 + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 + spi3's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 + spi3's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 + spi3's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 + spi3's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi3's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi3's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 + uhci0 dma permission configuration register 0. + 0x48 + 0x20 + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK + Set 1 to lock uhci0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 + uhci0 dma permission configuration register 1. + 0x4C + 0x20 + 0x00000FFF + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 + uhci0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 + uhci0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 + uhci0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 + uhci0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + uhci0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + uhci0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + i2s0 dma permission configuration register 0. + 0x50 + 0x20 + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + i2s0 dma permission configuration register 1. + 0x54 + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 + i2s0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 + i2s0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 + i2s0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 + i2s0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 + i2s1 dma permission configuration register 0. + 0x58 + 0x20 + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s1 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 + i2s1 dma permission configuration register 1. + 0x5C + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 + i2s1's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 + i2s1's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 + i2s1's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 + i2s1's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s1's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s1's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + mac dma permission configuration register 0. + 0x60 + 0x20 + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + Set 1 to lock mac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + mac dma permission configuration register 1. + 0x64 + 0x20 + 0x00000FFF + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 + mac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 + mac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 + mac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 + mac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + mac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + mac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + backup dma permission configuration register 0. + 0x68 + 0x20 + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + Set 1 to lock backup dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + backup dma permission configuration register 1. + 0x6C + 0x20 + 0x00000FFF + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 + backup's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 + backup's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 + backup's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 + backup's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + backup's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + backup's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_0 + aes dma permission configuration register 0. + 0x70 + 0x20 + + + DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + Set 1 to lock aes dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_1 + aes dma permission configuration register 1. + 0x74 + 0x20 + 0x00000FFF + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 + aes's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 + aes's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 + aes's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 + aes's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + aes's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + aes's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + sha dma permission configuration register 0. + 0x78 + 0x20 + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + Set 1 to lock sha dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + sha dma permission configuration register 1. + 0x7C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 + sha's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 + sha's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 + sha's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 + sha's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sha's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sha's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + adc_dac dma permission configuration register 0. + 0x80 + 0x20 + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + Set 1 to lock adc_dac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + adc_dac dma permission configuration register 1. + 0x84 + 0x20 + 0x00000FFF + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 + adc_dac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 + adc_dac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 + adc_dac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 + adc_dac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + adc_dac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + adc_dac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_0 + rmt dma permission configuration register 0. + 0x88 + 0x20 + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK + Set 1 to lock rmt dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_1 + rmt dma permission configuration register 1. + 0x8C + 0x20 + 0x00000FFF + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 + rmt's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 + rmt's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 + rmt's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 + rmt's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + rmt's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + rmt's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 + lcd_cam dma permission configuration register 0. + 0x90 + 0x20 + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK + Set 1 to lock lcd_cam dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 + lcd_cam dma permission configuration register 1. + 0x94 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 + lcd_cam's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 + lcd_cam's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 + lcd_cam's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 + lcd_cam's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lcd_cam's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lcd_cam's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_0 + usb dma permission configuration register 0. + 0x98 + 0x20 + + + DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK + Set 1 to lock usb dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_1 + usb dma permission configuration register 1. + 0x9C + 0x20 + 0x00000FFF + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 + usb's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 + usb's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 + usb's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 + usb's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + usb's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + usb's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_0 + lc dma permission configuration register 0. + 0xA0 + 0x20 + + + DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + Set 1 to lock lc dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_1 + lc dma permission configuration register 1. + 0xA4 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 + lc's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 + lc's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 + lc's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 + lc's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lc's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lc's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 + sdio dma permission configuration register 0. + 0xA8 + 0x20 + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK + Set 1 to lock sdio dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 + sdio dma permission configuration register 1. + 0xAC + 0x20 + 0x00000FFF + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 + sdio's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 + sdio's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 + sdio's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 + sdio's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sdio's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sdio's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_0 + dma permission monitor configuration register 0. + 0xB0 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_LOCK + Set 1 to lock dma permission monitor Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_1 + dma permission monitor configuration register 1. + 0xB4 + 0x20 + 0x00000003 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear dma_pms_monitor_violate interrupt + 0 + 1 + read-write + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt. + 1 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_2 + dma permission monitor configuration register 2. + 0xB8 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + recorded dma's interrupt status when dma access violated permission + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded dma's world status when dma access violated permission + 1 + 2 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16 + 3 + 22 + read-only + + + + + DMA_APBPERI_PMS_MONITOR_3 + dma permission monitor configuration register 3. + 0xBC + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + recorded dma's write status when dma access violated permission, 1(write), 0(read) + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded dma's byte enable status when dma access violated permission + 1 + 16 + read-only + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + sram split line configuration register 0 + 0xC0 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + Set 1 to lock sram split configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + sram split line configuration register 1 + 0xC4 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + sram split line configuration register 1 + 0xC8 + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + sram split line configuration register 1 + 0xCC + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + sram split line configuration register 1 + 0xD0 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + sram split line configuration register 1 + 0xD4 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_0 + corex iram0 permission configuration register 0 + 0xD8 + 0x20 + + + CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex iram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_1 + corex iram0 permission configuration register 0 + 0xDC + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_2 + corex iram0 permission configuration register 1 + 0xE0 + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_0 + core0 iram0 permission monitor configuration register 0 + 0xE4 + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_1 + core0 iram0 permission monitor configuration register 1 + 0xE8 + 0x20 + 0x00000003 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_2 + core0 iram0 permission monitor configuration register 2 + 0xEC + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_1_IRAM0_PMS_MONITOR_0 + core1 iram0 permission monitor configuration register 0 + 0xF0 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_1 + core1 iram0 permission monitor configuration register 1 + 0xF4 + 0x20 + 0x00000003 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_2 + core1 iram0 permission monitor configuration register 2 + 0xF8 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_0 + corex dram0 permission configuration register 0 + 0xFC + 0x20 + + + CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex dram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_1 + corex dram0 permission configuration register 1 + 0x100 + 0x20 + 0x0FFFFFFF + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of data region0 of SRAM in world0. + 0 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of data region1 of SRAM in world0. + 2 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of data region2 of SRAM in world0. + 4 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of data region3 of SRAM in world0. + 6 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world0. + 8 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world0. + 10 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of data region0 of SRAM in world1. + 12 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of data region1 of SRAM in world1. + 14 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of data region2 of SRAM in world1. + 16 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of data region3 of SRAM in world1. + 18 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world1. + 20 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world1. + 22 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission(sotre,load) of rom in world0. + 24 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission(sotre,load) of rom in world1. + 26 + 2 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_0 + core0 dram0 permission monitor configuration register 0 + 0x104 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_1 + core0 dram0 permission monitor configuration register 1 + 0x108 + 0x20 + 0x00000003 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_2 + core0 dram0 permission monitor configuration register 2. + 0x10C + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core0 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_0_DRAM0_PMS_MONITOR_3 + core0 dram0 permission monitor configuration register 3. + 0x110 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core0 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_0 + core1 dram0 permission monitor configuration register 0 + 0x114 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_1 + core1 dram0 permission monitor configuration register 1 + 0x118 + 0x20 + 0x00000003 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_2 + core1 dram0 permission monitor configuration register 2. + 0x11C + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core1 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_3 + core1 dram0 permission monitor configuration register 3. + 0x120 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core1 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_0_PIF_PMS_CONSTRAIN_0 + Core0 access peripherals permission configuration register 0. + 0x124 + 0x20 + + + CORE_0_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 access peripherals permission Configuration Register. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_1 + Core0 access peripherals permission configuration register 1. + 0x128 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core0 access uart permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core0 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core0 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core0 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core0 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core0 access fe permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core0 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core0 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core0 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core0 access misc permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core0 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core0 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core0 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_2 + Core0 access peripherals permission configuration register 2. + 0x12C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core0 access bt permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core0 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core0 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core0 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core0 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core0 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core0 access slc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core0 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core0 access backup permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core0 access bb permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core0 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core0 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core0 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core0 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_3 + Core0 access peripherals permission configuration register 3. + 0x130 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core0 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core0 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core0 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core0 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core0 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core0 access can permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core0 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core0 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core0 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core0 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core0 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core0 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_4 + Core0 access peripherals permission configuration register 4. + 0x134 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core0 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core0 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core0 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core0 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core0 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core0 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core0 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core0 access usb permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core0 access system permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core0 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core0 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core0 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core0 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core0 access ad permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core0 access dio permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core0 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_5 + Core0 access peripherals permission configuration register 5. + 0x138 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core0 access uart permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core0 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core0 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core0 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core0 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core0 access fe permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core0 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core0 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core0 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core0 access misc permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core0 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core0 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core0 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_6 + Core0 access peripherals permission configuration register 6. + 0x13C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core0 access bt permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core0 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core0 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core0 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core0 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core0 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core0 access slc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core0 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core0 access backup permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core0 access bb permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core0 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core0 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core0 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core0 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_7 + Core0 access peripherals permission configuration register 7. + 0x140 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core0 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core0 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core0 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core0 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core0 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core0 access can permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core0 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core0 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core0 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core0 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core0 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core0 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_8 + Core0 access peripherals permission configuration register 8. + 0x144 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core0 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core0 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core0 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core0 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core0 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core0 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core0 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core0 access usb permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core0 access system permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core0 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core0 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core0 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core0 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core0 access ad permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core0 access dio permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core0 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_9 + Core0 access peripherals permission configuration register 9. + 0x148 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_10 + Core0 access peripherals permission configuration register 10. + 0x14C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_11 + Core0 access peripherals permission configuration register 11. + 0x150 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_12 + Core0 access peripherals permission configuration register 12. + 0x154 + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_13 + Core0 access peripherals permission configuration register 13. + 0x158 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_14 + Core0 access peripherals permission configuration register 14. + 0x15C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_0 + Core0 region permission register 0. + 0x160 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 region permission registers. + 0 + 1 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_1 + Core0 region permission register 1. + 0x164 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_2 + Core0 region permission register 2. + 0x168 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_3 + Core0 region permission register 3. + 0x16C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_4 + Core0 region permission register 4. + 0x170 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_5 + Core0 region permission register 5. + 0x174 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_6 + Core0 region permission register 6. + 0x178 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_7 + Core0 region permission register 7. + 0x17C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_8 + Core0 region permission register 8. + 0x180 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_9 + Core0 region permission register 9. + 0x184 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_10 + Core0 region permission register 10. + 0x188 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_11 + Core0 region permission register 11. + 0x18C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_12 + Core0 region permission register 12. + 0x190 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_13 + Core0 region permission register 13. + 0x194 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_14 + Core0 region permission register 14. + 0x198 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core0. + 0 + 30 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_0 + Core0 permission report register 0. + 0x19C + 0x20 + + + CORE_0_PIF_PMS_MONITOR_LOCK + Set 1 to lock core0 permission report registers. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_1 + Core0 permission report register 1. + 0x1A0 + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_2 + Core0 permission report register 2. + 0x1A4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + Record core0 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core0 initiate illegal access. + 1 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core0 initate illegal access. + 2 + 3 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core0 initiate illegal access. + 5 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_3 + Core0 permission report register 3. + 0x1A8 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core0 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_4 + Core0 permission report register 4. + 0x1AC + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_5 + Core0 permission report register 5. + 0x1B0 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core0 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core0 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_6 + Core0 permission report register 6. + 0x1B4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core0 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_0_VECBASE_OVERRIDE_LOCK + core0 vecbase override configuration register 0 + 0x1B8 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_LOCK + Set 1 to lock core0 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_0 + core0 vecbase override configuration register 0 + 0x1BC + 0x20 + 0x00000001 + + + CORE_0_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_1 + core0 vecbase override configuration register 1 + 0x1C0 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core0 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_0_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_2 + core0 vecbase override configuration register 1 + 0x1C4 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core0 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core0 toomanyexception override configuration register 0. + 0x1C8 + 0x20 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core0 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core0 toomanyexception override configuration register 1. + 0x1CC + 0x20 + 0x00000001 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_0 + Core1 access peripherals permission configuration register 0. + 0x1D0 + 0x20 + + + CORE_1_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 pif permission configuration register. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_1 + Core1 access peripherals permission configuration register 1. + 0x1D4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core1 access uart permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core1 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core1 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core1 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core1 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core1 access fe permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core1 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core1 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core1 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core1 access misc permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core1 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core1 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core1 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_2 + Core1 access peripherals permission configuration register 2. + 0x1D8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core1 access bt permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core1 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core1 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core1 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core1 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core1 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core1 access slc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core1 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core1 access backup permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core1 access bb permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core1 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core1 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core1 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core1 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_3 + Core1 access peripherals permission configuration register 3. + 0x1DC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core1 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core1 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core1 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core1 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core1 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core1 access can permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core1 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core1 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core1 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core1 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core1 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core1 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_4 + Core1 access peripherals permission configuration register 4. + 0x1E0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core1 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core1 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core1 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core1 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core1 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core1 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core1 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core1 access usb permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core1 access system permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core1 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core1 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core1 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core1 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core1 access ad permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core1 access dio permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core1 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_5 + Core1 access peripherals permission configuration register 5. + 0x1E4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core1 access uart permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core1 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core1 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core1 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core1 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core1 access fe permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core1 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core1 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core1 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core1 access misc permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core1 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core1 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core1 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_6 + Core1 access peripherals permission configuration register 6. + 0x1E8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core1 access bt permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core1 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core1 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core1 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core1 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core1 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core1 access slc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core1 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core1 access backup permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core1 access bb permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core1 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core1 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core1 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core1 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_7 + Core1 access peripherals permission configuration register 7. + 0x1EC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core1 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core1 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core1 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core1 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core1 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core1 access can permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core1 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core1 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core1 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core1 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core1 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core1 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_8 + Core1 access peripherals permission configuration register 8. + 0x1F0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core1 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core1 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core1 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core1 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core1 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core1 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core1 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core1 access usb permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core1 access system permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core1 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core1 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core1 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core1 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core1 access ad permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core1 access dio permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core1 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_9 + Core1 access peripherals permission configuration register 9. + 0x1F4 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_10 + core1 access peripherals permission configuration register 10. + 0x1F8 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_11 + core1 access peripherals permission configuration register 11. + 0x1FC + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_12 + core1 access peripherals permission configuration register 12. + 0x200 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_13 + core1 access peripherals permission configuration register 13. + 0x204 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_14 + core1 access peripherals permission configuration register 14. + 0x208 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_0 + core1 region permission register 0. + 0x20C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 region permission registers. + 0 + 1 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_1 + core1 region permission register 1. + 0x210 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_2 + core1 region permission register 2. + 0x214 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_3 + core1 region permission register 3. + 0x218 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_4 + core1 region permission register 4. + 0x21C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_5 + core1 region permission register 5. + 0x220 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_6 + core1 region permission register 6. + 0x224 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_7 + core1 region permission register 7. + 0x228 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_8 + core1 region permission register 8. + 0x22C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_9 + core1 region permission register 9. + 0x230 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_10 + core1 region permission register 10. + 0x234 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_11 + core1 region permission register 11. + 0x238 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_12 + core1 region permission register 12. + 0x23C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_13 + core1 region permission register 13. + 0x240 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_14 + core1 region permission register 14. + 0x244 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core1. + 0 + 30 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_0 + core1 permission report register 0. + 0x248 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_LOCK + Set 1 to lock core1 permission report registers. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_1 + core1 permission report register 1. + 0x24C + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_2 + core1 permission report register 2. + 0x250 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR + Record core1 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core1 initiate illegal access. + 1 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core1 initate illegal access. + 2 + 3 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core1 initiate illegal access. + 5 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_3 + core1 permission report register 3. + 0x254 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core1 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_4 + core1 permission report register 4. + 0x258 + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_5 + core1 permission report register 5. + 0x25C + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core1 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core1 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_6 + core1 permission report register 6. + 0x260 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core1 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_1_VECBASE_OVERRIDE_LOCK + core1 vecbase override configuration register 0 + 0x264 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_LOCK + Set 1 to lock core1 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_0 + core1 vecbase override configuration register 0 + 0x268 + 0x20 + 0x00000001 + + + CORE_1_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_1 + core1 vecbase override configuration register 1 + 0x26C + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core1 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_1_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_2 + core1 vecbase override configuration register 1 + 0x270 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core1 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core1 toomanyexception override configuration register 0. + 0x274 + 0x20 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core1 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core1 toomanyexception override configuration register 1. + 0x278 + 0x20 + 0x00000001 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_0 + BackUp access peripherals permission configuration register 0. + 0x27C + 0x20 + + + BACKUP_BUS_PMS_CONSTRAIN_LOCK + Set 1 to lock BackUp permission configuration registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_1 + BackUp access peripherals permission configuration register 1. + 0x280 + 0x20 + 0xFF33CFFF + + + BACKUP_BUS_PMS_CONSTRAIN_UART + BackUp access uart permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + BackUp access g0spi_1 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + BackUp access g0spi_0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_GPIO + BackUp access gpio permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE2 + BackUp access fe2 permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE + BackUp access fe permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTC + BackUp access rtc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + BackUp access io_mux permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_HINF + BackUp access hinf permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_MISC + BackUp access misc permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C + BackUp access i2c permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S0 + BackUp access i2s0 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART1 + BackUp access uart1 permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_2 + BackUp access peripherals permission configuration register 2. + 0x284 + 0x20 + 0xFFCFFFF3 + + + BACKUP_BUS_PMS_CONSTRAIN_BT + BackUp access bt permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + BackUp access i2c_ext0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + BackUp access uhci0 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLCHOST + BackUp access slchost permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RMT + BackUp access rmt permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PCNT + BackUp access pcnt permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLC + BackUp access slc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LEDC + BackUp access ledc permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BACKUP + BackUp access backup permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BB + BackUp access bb permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM0 + BackUp access pwm0 permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + BackUp access timergroup permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + BackUp access timergroup1 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + BackUp access systimer permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_3 + BackUp access peripherals permission configuration register 3. + 0x288 + 0x20 + 0x3CC3FFFF + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + BackUp access spi_2 permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_3 + BackUp access spi_3 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + BackUp access apb_ctrl permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 + BackUp access i2c_ext1 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST + BackUp access sdio_host permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CAN + BackUp access can permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM1 + BackUp access pwm1 permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S1 + BackUp access i2s1 permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART2 + BackUp access uart2 permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RWBT + BackUp access rwbt permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + BackUp access wifimac permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWR + BackUp access pwr permission. + 28 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_4 + BackUp access peripherals permission configuration register 4. + 0x28C + 0x20 + 0xFFFFFFFF + + + BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + BackUp access usb_device permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + BackUp access usb_wrap permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + BackUp access crypto_peri permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + BackUp access crypto_dma permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + BackUp access apb_adc permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM + BackUp access lcd_cam permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + BackUp access bt_pwr permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB + BackUp access usb permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTEM + BackUp access system permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE + BackUp access sensitive permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT + BackUp access interrupt permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY + BackUp access dma_copy permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG + BackUp access cache_config permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_AD + BackUp access ad permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DIO + BackUp access dio permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER + BackUp access world_controller permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_5 + BackUp access peripherals permission configuration register 5. + 0x290 + 0x20 + 0x000007FF + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR + BackUp access rtcfast_spltaddr permission. + 0 + 11 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_6 + BackUp access peripherals permission configuration register 6. + 0x294 + 0x20 + 0x0000003F + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L + BackUp access rtcfast_l permission. + 0 + 3 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H + BackUp access rtcfast_h permission. + 3 + 3 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_0 + BackUp permission report register 0. + 0x298 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_LOCK + Set 1 to lock BackUp permission report registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_1 + BackUp permission report register 1. + 0x29C + 0x20 + 0x00000003 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that BackUp initiate illegal access. + 0 + 1 + read-write + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that BackUp initiate illegal access. + 1 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_2 + BackUp permission report register 2. + 0x2A0 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + Record BackUp illegal access interrupt state. + 0 + 1 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + Record htrans when BackUp initate illegal access. + 1 + 2 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when BackUp initate illegal access. + 3 + 3 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when BackUp initiate illegal access. + 6 + 1 + read-only + + + + + BACKUP_BUS_PMS_MONITOR_3 + BackUp permission report register 3. + 0x2A4 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + Record address information when BackUp initiate illegal access. + 0 + 32 + read-only + + + + + EDMA_BOUNDARY_LOCK + EDMA boundary lock register. + 0x2A8 + 0x20 + + + EDMA_BOUNDARY_LOCK + Set 1 to lock EDMA boundary registers. + 0 + 1 + read-write + + + + + EDMA_BOUNDARY_0 + EDMA boundary 0 configuration + 0x2AC + 0x20 + + + EDMA_BOUNDARY_0 + This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_1 + EDMA boundary 1 configuration + 0x2B0 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_1 + This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_2 + EDMA boundary 2 configuration + 0x2B4 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_2 + This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_PMS_SPI2_LOCK + EDMA-SPI2 permission lock register. + 0x2B8 + 0x20 + + + EDMA_PMS_SPI2_LOCK + Set 1 to lock EDMA-SPI2 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI2 + EDMA-SPI2 permission control register. + 0x2BC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SPI3_LOCK + EDMA-SPI3 permission lock register. + 0x2C0 + 0x20 + + + EDMA_PMS_SPI3_LOCK + Set 1 to lock EDMA-SPI3 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI3 + EDMA-SPI3 permission control register. + 0x2C4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_UHCI0_LOCK + EDMA-UHCI0 permission lock register. + 0x2C8 + 0x20 + + + EDMA_PMS_UHCI0_LOCK + Set 1 to lock EDMA-UHCI0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_UHCI0 + EDMA-UHCI0 permission control register. + 0x2CC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S0_LOCK + EDMA-I2S0 permission lock register. + 0x2D0 + 0x20 + + + EDMA_PMS_I2S0_LOCK + Set 1 to lock EDMA-I2S0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S0 + EDMA-I2S0 permission control register. + 0x2D4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S1_LOCK + EDMA-I2S1 permission lock register. + 0x2D8 + 0x20 + + + EDMA_PMS_I2S1_LOCK + Set 1 to lock EDMA-I2S1 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S1 + EDMA-I2S1 permission control register. + 0x2DC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_LCD_CAM_LOCK + EDMA-LCD/CAM permission lock register. + 0x2E0 + 0x20 + + + EDMA_PMS_LCD_CAM_LOCK + Set 1 to lock EDMA-LCD/CAM permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_LCD_CAM + EDMA-LCD/CAM permission control register. + 0x2E4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_AES_LOCK + EDMA-AES permission lock register. + 0x2E8 + 0x20 + + + EDMA_PMS_AES_LOCK + Set 1 to lock EDMA-AES permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_AES + EDMA-AES permission control register. + 0x2EC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SHA_LOCK + EDMA-SHA permission lock register. + 0x2F0 + 0x20 + + + EDMA_PMS_SHA_LOCK + Set 1 to lock EDMA-SHA permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SHA + EDMA-SHA permission control register. + 0x2F4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_ADC_DAC_LOCK + EDMA-ADC/DAC permission lock register. + 0x2F8 + 0x20 + + + EDMA_PMS_ADC_DAC_LOCK + Set 1 to lock EDMA-ADC/DAC permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_ADC_DAC + EDMA-ADC/DAC permission control register. + 0x2FC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_RMT_LOCK + EDMA-RMT permission lock register. + 0x300 + 0x20 + + + EDMA_PMS_RMT_LOCK + Set 1 to lock EDMA-RMT permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_RMT + EDMA-RMT permission control register. + 0x304 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + CLOCK_GATE_REG + Sensitive module clock gate configuration register. + 0x308 + 0x20 + 0x00000001 + + + REG_CLK_EN + Set 1 to enable clock gate function. + 0 + 1 + read-write + + + + + RTC_PMS + RTC coprocessor permission register. + 0x30C + 0x20 + + + DIS_RTC_CPU + Set 1 to disable rtc coprocessor. + 0 + 1 + read-write + + + + + DATE + Sensitive version register. + 0xFFC + 0x20 + 0x02101280 + + + DATE + Sensitive Date register. + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 78 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + sha mode + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + sha t_string(used if and only if mode == sha_256/t) + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + sha t_length(used if and only if mode == sha_256/t) + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + dma-sha block number + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + sha busy state. 1'b0: idle 1'b1: busy + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + start dma-sha + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + continue dma-sha + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + clear sha interrupt + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + sha interrupt enable register. 1'b0: disable(default) 1'b1: enable + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20190402 + + + DATE + sha date information/ sha version information + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60003000 + + 0x0 + 0x98 + registers + + + SPI_MEM_REJECT + 60 + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control 1 register. + 0xC + 0x20 + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. + 30 + 1 + read-write + + + + + CTRL2 + SPI0 control 2 register. + 0x10 + 0x20 + 0x00002C21 + + + CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI0 accesses to flash. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 6 + 1 + read-write + + + CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 7 + 1 + read-write + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the DUMMY phase of an SPI transfer. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI0 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + FSUB_PIN + Flash is connected to SPI SUBPIN bus. + 7 + 1 + read-write + + + SSUB_PIN + Ext_RAM is connected to SPI SUBPIN bus. + 8 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 external RAM bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + Set this bit to enable Cache's access and SPI0's transfer. + 0 + 1 + read-write + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. + 2 + 1 + read-write + + + FDIN_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + CACHE_USR_SCMD_4BYTE + Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + 0 + 1 + read-write + + + USR_SRAM_DIO + Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + 1 + 1 + read-write + + + USR_SRAM_QIO + Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + 2 + 1 + read-write + + + USR_WR_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations. + 3 + 1 + read-write + + + USR_RD_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations. + 4 + 1 + read-write + + + CACHE_SRAM_USR_RCMD + 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2. + 5 + 1 + read-write + + + SRAM_RDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer. + 6 + 6 + read-write + + + SRAM_ADDR_BITLEN + When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + CACHE_SRAM_USR_WCMD + 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3. + 20 + 1 + read-write + + + SRAM_OCT + Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. + 21 + 1 + read-write + + + SRAM_WDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer. + 22 + 6 + read-write + + + + + SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + + + SCLK_MODE + SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + SWB_MODE + Mode bits when SPI0 accesses to Ext_RAM. + 2 + 8 + read-write + + + SDIN_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. + 10 + 1 + read-write + + + SDOUT_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 11 + 1 + read-write + + + SADDR_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 12 + 1 + read-write + + + SCMD_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. + 13 + 1 + read-write + + + SDIN_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. + 14 + 1 + read-write + + + SDOUT_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 15 + 1 + read-write + + + SADDR_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 16 + 1 + read-write + + + SCMD_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. + 17 + 1 + read-write + + + SDIN_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. + 18 + 1 + read-write + + + SDOUT_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. + 19 + 1 + read-write + + + SADDR_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. + 20 + 1 + read-write + + + SCMD_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. + 21 + 1 + read-write + + + SDUMMY_OUT + When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 22 + 1 + read-write + + + + + SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + CACHE_SRAM_USR_RD_CMD_VALUE + When SPI0 reads Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_RD_CMD_BITLEN + When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + CACHE_SRAM_USR_WR_CMD_VALUE + When SPI0 writes Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_WR_CMD_BITLEN + When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_CLK + SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + 0x50 + 0x20 + 0x00030103 + + + SCLKCNT_L + It must equal to the value of SPI_MEM_SCLKCNT_N. + 0 + 8 + read-write + + + SCLKCNT_H + It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + SCLKCNT_N + When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + 16 + 8 + read-write + + + SCLK_EQU_SYSCLK + When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + FSM + SPI0 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + TIMING_CALI + SPI0 timing compensation register when accesses to flash. + 0xA8 + 0x20 + + + TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DIN_MODE + MSPI input timing delay mode control register when accesses to flash. + 0xAC + 0x20 + + + DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + DIN_NUM + MSPI input timing delay number control register when accesses to flash. + 0xB0 + 0x20 + + + DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + DOUT_MODE + MSPI output timing delay mode control register when accesses to flash. + 0xB4 + 0x20 + + + DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + SPI0 Ext_RAM timing compensation register. + 0xBC + 0x20 + + + SPI_SMEM_TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI input timing delay mode control register when accesses to Ext_RAM. + 0xC0 + 0x20 + + + SPI_SMEM_DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI input timing delay number control register when accesses to Ext_RAM. + 0xC4 + 0x20 + + + SPI_SMEM_DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI output timing delay mode control register when accesses to Ext_RAM. + 0xC8 + 0x20 + + + SPI_SMEM_DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + ECC_CTRL + MSPI ECC control register + 0xCC + 0x20 + 0x0000000A + + + ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 0 + 8 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 8 + 1 + read-write + + + + + ECC_ERR_ADDR + MSPI ECC error address register + 0xD0 + 0x20 + + + ECC_ERR_ADDR + These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 32 + read-only + + + + + ECC_ERR_BIT + MSPI ECC error bits register + 0xD4 + 0x20 + + + ECC_DATA_ERR_BIT + It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 6 + 7 + read-only + + + ECC_CHK_ERR_BIT + When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte. + 13 + 3 + read-only + + + ECC_BYTE_ERR + It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 16 + 1 + read-only + + + ECC_ERR_CNT + This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 17 + 8 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0xDC + 0x20 + 0x0000B084 + + + SPI_SMEM_CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + 16 + 1 + read-write + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 24 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + + + DDR + SPI0 flash DDR mode control register + 0xE0 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to swap TX data of a word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xE4 + 0x20 + 0x00003020 + + + EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the ddr psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + DQS_LOOP_MODE + When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xEC + 0x20 + + + CORE_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. + 4 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-only + + + ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. + 4 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + SPI_SMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM. + 0 + 2 + read-write + + + SPI_FMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash. + 2 + 2 + read-write + + + SPI_SPICLK_PAD_DRV_CTL_EN + SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. + 4 + 1 + read-write + + + DATE + SPI register version. + 5 + 23 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60002000 + + 0x0 + 0xB4 + registers + + + SPI1 + 20 + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + Two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + FWRITE_DUAL + Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + 12 + 1 + read-write + + + FWRITE_QUAD + Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + 13 + 1 + read-write + + + FWRITE_DIO + Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + 14 + 1 + read-write + + + FWRITE_QIO + Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + Set this bit to enable the DOUT phase of an write-data operation. + 27 + 1 + read-write + + + USR_MISO + Set this bit to enable enable the DIN phase of a read-data operation. + 28 + 1 + read-write + + + USR_DUMMY + Set this bit to enable enable the DUMMY phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + Set this bit to enable enable the ADDR phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + Set this bit to enable enable the CMD phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 write-data bit length register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of DOUT phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 read-data bit length register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of DIN phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 read control register. + 0x2C + 0x20 + + + STATUS + The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI1 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI1 misc register. + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. + 0 + 1 + read-write + + + CS1_DIS + Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + AUTO_PER + Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + 11 + 1 + read-write + + + + + TX_CRC + SPI1 CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + FDIN_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + FSM + SPI1 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_EN + Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + 0 + 1 + read-write + + + WAITI_DUMMY + Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + 1 + 1 + read-write + + + WAITI_CMD + The command value of auto wait flash idle transfer(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend control register + 0x9C + 0x20 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + Set this bit to add delay time after program erase resume(PER) is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + Set this bit to add delay time after program erase suspend(PES) command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES transfer trigger PES transfer option. + 4 + 1 + read-write + + + PESR_IDLE_EN + 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. + 5 + 1 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0000EAF4 + + + FLASH_PES_EN + Set this bit to enable auto-suspend function. + 0 + 1 + read-write + + + FLASH_PER_COMMAND + Program/Erase resume command value. + 1 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command value. + 9 + 8 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + 0 + 1 + read-write + + + FLASH_HPM_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_256 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_256 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing compensation register when accesses to flash or Ext_RAM. + 0xA8 + 0x20 + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DDR + SPI1 DDR control register + 0xE0 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0: in SDR mode. + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDRmode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder TX data of the word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-only + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-only + + + BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 3 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI2 + 21 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-only + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-only + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-only + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-only + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-only + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-only + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-only + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-only + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02101190 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller + 0x60025000 + + SPI3 + 22 + + + + SYSTEM + System + SYSTEM + 0x600C0000 + + 0x0 + 0xA8 + registers + + + + CORE_1_CONTROL_0 + Core0 control regiter 0 + 0x0 + 0x20 + 0x00000004 + + + CONTROL_CORE_1_RUNSTALL + Set 1 to stall core1 + 0 + 1 + read-write + + + CONTROL_CORE_1_CLKGATE_EN + Set 1 to open core1 clock + 1 + 1 + read-write + + + CONTROL_CORE_1_RESETING + Set 1 to let core1 reset + 2 + 1 + read-write + + + + + CORE_1_CONTROL_1 + Core0 control regiter 1 + 0x4 + 0x20 + + + CONTROL_CORE_1_MESSAGE + it's only a R/W register, no function, software can write any value + 0 + 32 + read-write + + + + + CPU_PERI_CLK_EN + cpu_peripheral clock configuration register + 0x8 + 0x20 + + + CLK_EN_ASSIST_DEBUG + Set 1 to open assist_debug module clock + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + Set 1 to open dedicated_gpio module clk + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset configuration regsiter + 0xC + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + Set 1 to let assist_debug module reset + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + Set 1 to let dedicated_gpio module reset + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu peripheral clock configuration register + 0x10 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field used to sel cpu clock frequent. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field used to sel pll frequent. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask configuration register + 0x14 + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set 1 to mask memory power down. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock configuration regsiter 0 + 0x18 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + Set 1 to enable TIMERS clock + 0 + 1 + read-write + + + SPI01_CLK_EN + Set 1 to enable SPI01 clock + 1 + 1 + read-write + + + UART_CLK_EN + Set 1 to enable UART clock + 2 + 1 + read-write + + + WDG_CLK_EN + Set 1 to enable WDG clock + 3 + 1 + read-write + + + I2S0_CLK_EN + Set 1 to enable I2S0 clock + 4 + 1 + read-write + + + UART1_CLK_EN + Set 1 to enable UART1 clock + 5 + 1 + read-write + + + SPI2_CLK_EN + Set 1 to enable SPI2 clock + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set 1 to enable I2C_EXT0 clock + 7 + 1 + read-write + + + UHCI0_CLK_EN + Set 1 to enable UHCI0 clock + 8 + 1 + read-write + + + RMT_CLK_EN + Set 1 to enable RMT clock + 9 + 1 + read-write + + + PCNT_CLK_EN + Set 1 to enable PCNT clock + 10 + 1 + read-write + + + LEDC_CLK_EN + Set 1 to enable LEDC clock + 11 + 1 + read-write + + + UHCI1_CLK_EN + Set 1 to enable UHCI1 clock + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set 1 to enable TIMERGROUP clock + 13 + 1 + read-write + + + EFUSE_CLK_EN + Set 1 to enable EFUSE clock + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + Set 1 to enable TIMERGROUP1 clock + 15 + 1 + read-write + + + SPI3_CLK_EN + Set 1 to enable SPI3 clock + 16 + 1 + read-write + + + PWM0_CLK_EN + Set 1 to enable PWM0 clock + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + Set 1 to enable I2C_EXT1 clock + 18 + 1 + read-write + + + CAN_CLK_EN + Set 1 to enable CAN clock + 19 + 1 + read-write + + + PWM1_CLK_EN + Set 1 to enable PWM1 clock + 20 + 1 + read-write + + + I2S1_CLK_EN + Set 1 to enable I2S1 clock + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + Set 1 to enable SPI2_DMA clock + 22 + 1 + read-write + + + USB_CLK_EN + Set 1 to enable USB clock + 23 + 1 + read-write + + + UART_MEM_CLK_EN + Set 1 to enable UART_MEM clock + 24 + 1 + read-write + + + PWM2_CLK_EN + Set 1 to enable PWM2 clock + 25 + 1 + read-write + + + PWM3_CLK_EN + Set 1 to enable PWM3 clock + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + Set 1 to enable SPI4 clock + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + Set 1 to enable APB_SARADC clock + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set 1 to enable SYSTEMTIMER clock + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set 1 to enable ADC2_ARB clock + 30 + 1 + read-write + + + SPI4_CLK_EN + Set 1 to enable SPI4 clock + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock configuration regsiter 1 + 0x1C + 0x20 + 0x00000600 + + + PERI_BACKUP_CLK_EN + Set 1 to enable BACKUP clock + 0 + 1 + read-write + + + CRYPTO_AES_CLK_EN + Set 1 to enable AES clock + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set 1 to enable SHA clock + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + Set 1 to enable RSA clock + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + Set 1 to enable DS clock + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + Set 1 to enable HMAC clock + 5 + 1 + read-write + + + DMA_CLK_EN + Set 1 to enable DMA clock + 6 + 1 + read-write + + + SDIO_HOST_CLK_EN + Set 1 to enable SDIO_HOST clock + 7 + 1 + read-write + + + LCD_CAM_CLK_EN + Set 1 to enable LCD_CAM clock + 8 + 1 + read-write + + + UART2_CLK_EN + Set 1 to enable UART2 clock + 9 + 1 + read-write + + + USB_DEVICE_CLK_EN + Set 1 to enable USB_DEVICE clock + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + peripheral reset configuration register0 + 0x20 + 0x20 + + + TIMERS_RST + Set 1 to let TIMERS reset + 0 + 1 + read-write + + + SPI01_RST + Set 1 to let SPI01 reset + 1 + 1 + read-write + + + UART_RST + Set 1 to let UART reset + 2 + 1 + read-write + + + WDG_RST + Set 1 to let WDG reset + 3 + 1 + read-write + + + I2S0_RST + Set 1 to let I2S0 reset + 4 + 1 + read-write + + + UART1_RST + Set 1 to let UART1 reset + 5 + 1 + read-write + + + SPI2_RST + Set 1 to let SPI2 reset + 6 + 1 + read-write + + + I2C_EXT0_RST + Set 1 to let I2C_EXT0 reset + 7 + 1 + read-write + + + UHCI0_RST + Set 1 to let UHCI0 reset + 8 + 1 + read-write + + + RMT_RST + Set 1 to let RMT reset + 9 + 1 + read-write + + + PCNT_RST + Set 1 to let PCNT reset + 10 + 1 + read-write + + + LEDC_RST + Set 1 to let LEDC reset + 11 + 1 + read-write + + + UHCI1_RST + Set 1 to let UHCI1 reset + 12 + 1 + read-write + + + TIMERGROUP_RST + Set 1 to let TIMERGROUP reset + 13 + 1 + read-write + + + EFUSE_RST + Set 1 to let EFUSE reset + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set 1 to let TIMERGROUP1 reset + 15 + 1 + read-write + + + SPI3_RST + Set 1 to let SPI3 reset + 16 + 1 + read-write + + + PWM0_RST + Set 1 to let PWM0 reset + 17 + 1 + read-write + + + I2C_EXT1_RST + Set 1 to let I2C_EXT1 reset + 18 + 1 + read-write + + + CAN_RST + Set 1 to let CAN reset + 19 + 1 + read-write + + + PWM1_RST + Set 1 to let PWM1 reset + 20 + 1 + read-write + + + I2S1_RST + Set 1 to let I2S1 reset + 21 + 1 + read-write + + + SPI2_DMA_RST + Set 1 to let SPI2 reset + 22 + 1 + read-write + + + USB_RST + Set 1 to let USB reset + 23 + 1 + read-write + + + UART_MEM_RST + Set 1 to let UART_MEM reset + 24 + 1 + read-write + + + PWM2_RST + Set 1 to let PWM2 reset + 25 + 1 + read-write + + + PWM3_RST + Set 1 to let PWM3 reset + 26 + 1 + read-write + + + SPI3_DMA_RST + Set 1 to let SPI3 reset + 27 + 1 + read-write + + + APB_SARADC_RST + Set 1 to let APB_SARADC reset + 28 + 1 + read-write + + + SYSTIMER_RST + Set 1 to let SYSTIMER reset + 29 + 1 + read-write + + + ADC2_ARB_RST + Set 1 to let ADC2_ARB reset + 30 + 1 + read-write + + + SPI4_RST + Set 1 to let SPI4 reset + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset configuration regsiter 1 + 0x24 + 0x20 + 0x000001FE + + + PERI_BACKUP_RST + Set 1 to let BACKUP reset + 0 + 1 + read-write + + + CRYPTO_AES_RST + Set 1 to let CRYPTO_AES reset + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set 1 to let CRYPTO_SHA reset + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set 1 to let CRYPTO_RSA reset + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set 1 to let CRYPTO_DS reset + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set 1 to let CRYPTO_HMAC reset + 5 + 1 + read-write + + + DMA_RST + Set 1 to let DMA reset + 6 + 1 + read-write + + + SDIO_HOST_RST + Set 1 to let SDIO_HOST reset + 7 + 1 + read-write + + + LCD_CAM_RST + Set 1 to let LCD_CAM reset + 8 + 1 + read-write + + + UART2_RST + Set 1 to let UART2 reset + 9 + 1 + read-write + + + USB_DEVICE_RST + Set 1 to let USB_DEVICE reset + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + low power clock frequent division factor configuration regsiter + 0x28 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + This field is lower power clock frequent division factor + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + low power clock configuration register + 0x2C + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + This field is lower power clock frequent division factor b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + This field is lower power clock frequent division factor a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + Set 1 to select rtc-slow clock as rtc low power clock + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set 1 to select 8m clock as rtc low power clock + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set 1 to select xtal clock as rtc low power clock + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set 1 to select xtal32k clock as low power clock + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set 1 to enable RTC low power clock + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt source register 0 + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set 1 to generate cpu interrupt 0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt source register 1 + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set 1 to generate cpu interrupt 1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt source register 2 + 0x38 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set 1 to generate cpu interrupt 2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt source register 3 + 0x3C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set 1 to generate cpu interrupt 3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x40 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set 1 to force power up RSA memory, this bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set 1 to force power down RSA memory,this bit has the highest priority. + 2 + 1 + read-write + + + + + EDMA_CTRL + EDMA control register + 0x44 + 0x20 + 0x00000001 + + + EDMA_CLK_ON + Set 1 to enable EDMA clock. + 0 + 1 + read-write + + + EDMA_RESET + Set 1 to let EDMA reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + Cache control register + 0x48 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + Set 1 to enable icache clock + 0 + 1 + read-write + + + ICACHE_RESET + Set 1 to let icache reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + Set 1 to enable dcache clock + 2 + 1 + read-write + + + DCACHE_RESET + Set 1 to let dcache reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + External memory encrypt and decrypt control register + 0x4C + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set 1 to enable the SPI manual encrypt. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set 1 to enable download DB encrypt. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set 1 to enable download G0CB decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set 1 to enable download manual encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + RTC fast memory configuration register + 0x50 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set 1 to start the CRC of RTC memory + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC.1 means finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + RTC fast memory CRC control register + 0x54 + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + ******* Description *********** + 0x58 + 0x20 + + + REDUNDANT_ECO_DRIVE + ******* Description *********** + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + ******* Description *********** + 1 + 1 + read-only + + + + + CLOCK_GATE + ******* Description *********** + 0x5C + 0x20 + 0x00000001 + + + CLK_EN + ******* Description *********** + 0 + 1 + read-write + + + + + SYSCLK_CONF + System clock configuration register. + 0x60 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select soc clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read xtal frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + Reserved. + 19 + 1 + read-only + + + + + MEM_PVT + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + MEM_PATH_LEN + ******* Description *********** + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + ******* Description *********** + 4 + 1 + write-only + + + MONITOR_EN + ******* Description *********** + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + ******* Description *********** + 6 + 16 + read-only + + + MEM_VT_SEL + ******* Description *********** + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + ******* Description *********** + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_LVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + ******* Description *********** + 0x6C + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_NVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + ******* Description *********** + 0x70 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_HVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + ******* Description *********** + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + ******* Description *********** + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + ******* Description *********** + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + ******* Description *********** + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + ******* Description *********** + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + ******* Description *********** + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + ******* Description *********** + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + ******* Description *********** + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + ******* Description *********** + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + ******* Description *********** + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + ******* Description *********** + 0x9C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + ******* Description *********** + 0xA0 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + DATE + version register + 0xFFC + 0x20 + 0x02101220 + + + DATE + version register + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02012251 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x6001F000 + + 0x0 + 0x8C + registers + + + TG0_T0_LEVEL + 50 + + + TG0_T1_LEVEL + 51 + + + TG0_WDT_LEVEL + 52 + + + + 2 + 0x24 + T%sCONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sLO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sHI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + 2 + 0x24 + T%sUPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + +Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + Reserved + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + Reserved + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + Reserved + 15 + 1 + read-only + + + RTC_CALI_MAX + Reserved + 16 + 15 + read-write + + + RTC_CALI_START + Reserved + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + Reserved + 0 + 1 + read-only + + + RTC_CALI_VALUE + Reserved + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02003071 + + + NTIMERS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + + + CLK_EN + Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x60020000 + + TG1_T0_LEVEL + 53 + + + TG1_T1_LEVEL + 54 + + + TG1_WDT_LEVEL + 55 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x6C + registers + + + TWAI + 45 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + read-write + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + read-write + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + read-write + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + read-write + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + read-write + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 27 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00018060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 10 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 10 + 10 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 20 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 21 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 22 + 1 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 23 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow-control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00004CE0 + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 10 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 10 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00004400 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 10 + read-write + + + XON_CHAR + This register stores the Xon flow control char. + 10 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x00140012 + + + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 10 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 17 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 27 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 28 + 1 + read-write + + + + + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 + 0x20 + 0x00100200 + + + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x6C + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x78 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + + + ID + This register is used to configure the uart_id. + 0 + 30 + read-write + + + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. + 30 + 1 + read-write + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 31 + 1 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60010000 + + UART1 + 28 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x6002E000 + + UART2 + 29 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x60014000 + + 0x0 + 0x88 + registers + + + UHCI0 + 14 + + + + CONF0 + UHCI configuration register + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1, then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1, then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + UART2_CE + Set this bit to link up HCI and UART2. + 4 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + + + RX_START_INT_RAW + This is the interrupt raw bit. Triggered when a separator char has been sent. + 0 + 1 + read-only + + + TX_START_INT_RAW + This is the interrupt raw bit. Triggered when UHCI detects a separator char. + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. + 5 + 1 + read-only + + + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. + 6 + 1 + read-only + + + APP_CTRL0_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. + 8 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RX_START_INT_ST + This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + 0 + 1 + read-only + + + TX_START_INT_ST + This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. + 8 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RX_START_INT_ENA + This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + 0 + 1 + read-write + + + TX_START_INT_ENA + This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear UHCI_RX_START_INT interrupt. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear UHCI_TX_START_INT interrupt. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear UHCI_RX_HUNG_INT interrupt. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear UHCI_TX_HUNG_INT interrupt. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + write-only + + + + + APP_INT_SET + Software interrupt trigger source + 0x14 + 0x20 + + + APP_CTRL0_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. + 0 + 1 + write-only + + + APP_CTRL1_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. + 1 + 1 + write-only + + + + + CONF1 + UHCI configuration register + 0x18 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + This is the enable bit to check header checksum when UHCI receives a data packet. + 0 + 1 + read-write + + + CHECK_SEQ_EN + This is the enable bit to check sequence number when UHCI receives a data packet. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save the packet header when HCI receives a data packet. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode the data packet with a checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. + 5 + 1 + read-write + + + WAIT_SW_START + The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. + 7 + 1 + read-write + + + SW_START + If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. + 8 + 1 + read-write + + + + + STATE0 + UHCI receive status + 0x1C + 0x20 + + + RX_ERR_CAUSE + This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI transmit status + 0x20 + 0x20 + + + ENCODE_STATE + UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + Escape character configuration + 0x24 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable decoding char 0xc0 when DMA receives data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable decoding char 0xdb when DMA receives data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable decoding flow control char 0x11 when DMA receives data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable decoding flow control char 0x13 when DMA receives data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xc0 by special char when DMA sends data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xdb by special char when DMA sends data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. + 7 + 1 + read-write + + + + + HUNG_CONF + Timeout configuration + 0x28 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + This is the enable bit for Tx-FIFO receive-data timeout. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send-data timeout. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI ACK number configuration + 0x2C + 0x20 + 0x00000008 + + + ACK_NUM + This ACK number used in software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI packet header register + 0x30 + 0x20 + + + RX_HEAD + This register stores the header of the current received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UHCI quick send configuration register + 0x34 + 0x20 + + + SINGLE_SEND_NUM + This register is used to specify the single_send register. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable single_send mode to send short packet. + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + This register is used to specify the always_send register. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable always_send mode to send short packet. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + Q0_WORD0 quick_sent register + 0x38 + 0x20 + + + SEND_Q0_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + Q0_WORD1 quick_sent register + 0x3C + 0x20 + + + SEND_Q0_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + Q1_WORD0 quick_sent register + 0x40 + 0x20 + + + SEND_Q1_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + Q1_WORD1 quick_sent register + 0x44 + 0x20 + + + SEND_Q1_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + Q2_WORD0 quick_sent register + 0x48 + 0x20 + + + SEND_Q2_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + Q2_WORD1 quick_sent register + 0x4C + 0x20 + + + SEND_Q2_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + Q3_WORD0 quick_sent register + 0x50 + 0x20 + + + SEND_Q3_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + Q3_WORD1 quick_sent register + 0x54 + 0x20 + + + SEND_Q3_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + Q4_WORD0 quick_sent register + 0x58 + 0x20 + + + SEND_Q4_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + Q4_WORD1 quick_sent register + 0x5C + 0x20 + + + SEND_Q4_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + Q5_WORD0 quick_sent register + 0x60 + 0x20 + + + SEND_Q5_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + Q5_WORD1 quick_sent register + 0x64 + 0x20 + + + SEND_Q5_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + Q6_WORD0 quick_sent register + 0x68 + 0x20 + + + SEND_Q6_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + Q6_WORD1 quick_sent register + 0x6C + 0x20 + + + SEND_Q6_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + Escape sequence configuration register 0 + 0x70 + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + This register is used to define the separate char that need to be encoded, default is 0xc0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc. + 16 + 8 + read-write + + + + + ESC_CONF1 + Escape sequence configuration register 1 + 0x74 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd. + 16 + 8 + read-write + + + + + ESC_CONF2 + Escape sequence configuration register 2 + 0x78 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde. + 16 + 8 + read-write + + + + + ESC_CONF3 + Escape sequence configuration register 3 + 0x7C + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf. + 16 + 8 + read-write + + + + + PKT_THRES + Configure register for packet length + 0x80 + 0x20 + 0x00000080 + + + PKT_THRS + This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI version control register + 0x84 + 0x20 + 0x02010090 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface + 0x6000C000 + + + USB0 + USB OTG (On-The-Go) + USB + 0x60080000 + + 0x0 + 0x2A0 + registers + + + + GOTGCTL + 0x0 + 0x20 + + + SESREQSCS + 0 + 1 + read-only + + + SESREQ + 1 + 1 + read-write + + + VBVALIDOVEN + 2 + 1 + read-write + + + VBVALIDOVVAL + 3 + 1 + read-write + + + AVALIDOVEN + 4 + 1 + read-write + + + AVALIDOVVAL + 5 + 1 + read-write + + + BVALIDOVEN + 6 + 1 + read-write + + + BVALIDOVVAL + 7 + 1 + read-write + + + HSTNEGSCS + 8 + 1 + read-only + + + HNPREQ + 9 + 1 + read-write + + + HSTSETHNPEN + 10 + 1 + read-write + + + DEVHNPEN + 11 + 1 + read-write + + + EHEN + 12 + 1 + read-write + + + DBNCEFLTRBYPASS + 15 + 1 + read-write + + + CONIDSTS + 16 + 1 + read-only + + + DBNCTIME + 17 + 1 + read-only + + + ASESVLD + 18 + 1 + read-only + + + BSESVLD + 19 + 1 + read-only + + + OTGVER + 20 + 1 + read-write + + + CURMOD + 21 + 1 + read-only + + + + + GOTGINT + 0x4 + 0x20 + + + SESENDDET + 2 + 1 + read-write + + + SESREQSUCSTSCHNG + 8 + 1 + read-write + + + HSTNEGSUCSTSCHNG + 9 + 1 + read-write + + + HSTNEGDET + 17 + 1 + read-write + + + ADEVTOUTCHG + 18 + 1 + read-write + + + DBNCEDONE + 19 + 1 + read-write + + + + + GAHBCFG + 0x8 + 0x20 + + + GLBLLNTRMSK + 0 + 1 + read-write + + + HBSTLEN + 1 + 4 + read-write + + + DMAEN + 5 + 1 + read-write + + + NPTXFEMPLVL + 7 + 1 + read-write + + + PTXFEMPLVL + 8 + 1 + read-write + + + REMMEMSUPP + 21 + 1 + read-write + + + NOTIALLDMAWRIT + 22 + 1 + read-write + + + AHBSINGLE + 23 + 1 + read-write + + + INVDESCENDIANESS + 24 + 1 + read-write + + + + + GUSBCFG + 0xC + 0x20 + 0x00001440 + + + TOUTCAL + 0 + 3 + read-write + + + PHYIF + 3 + 1 + read-write + + + ULPI_UTMI_SEL + 4 + 1 + read-only + + + FSINTF + 5 + 1 + read-write + + + PHYSEL + 6 + 1 + read-only + + + SRPCAP + 8 + 1 + read-write + + + HNPCAP + 9 + 1 + read-write + + + USBTRDTIM + 10 + 4 + read-write + + + TERMSELDLPULSE + 22 + 1 + read-write + + + TXENDDELAY + 28 + 1 + read-write + + + FORCEHSTMODE + 29 + 1 + read-write + + + FORCEDEVMODE + 30 + 1 + read-write + + + CORRUPTTXPKT + 31 + 1 + read-write + + + + + GRSTCTL + 0x10 + 0x20 + + + CSFTRST + 0 + 1 + read-write + + + PIUFSSFTRST + 1 + 1 + read-write + + + FRMCNTRRST + 2 + 1 + read-write + + + RXFFLSH + 4 + 1 + read-write + + + TXFFLSH + 5 + 1 + read-write + + + TXFNUM + 6 + 5 + read-write + + + DMAREQ + 30 + 1 + read-only + + + AHBIDLE + 31 + 1 + read-only + + + + + GINTSTS + 0x14 + 0x20 + + + CURMOD_INT + 0 + 1 + read-only + + + MODEMIS + 1 + 1 + read-write + + + OTGINT + 2 + 1 + read-only + + + SOF + 3 + 1 + read-write + + + RXFLVI + 4 + 1 + read-only + + + NPTXFEMP + 5 + 1 + read-only + + + GINNAKEFF + 6 + 1 + read-only + + + GOUTNAKEFF + 7 + 1 + read-only + + + ERLYSUSP + 10 + 1 + read-write + + + USBSUSP + 11 + 1 + read-write + + + USBRST + 12 + 1 + read-write + + + ENUMDONE + 13 + 1 + read-write + + + ISOOUTDROP + 14 + 1 + read-write + + + EOPF + 15 + 1 + read-write + + + EPMIS + 17 + 1 + read-write + + + IEPINT + 18 + 1 + read-only + + + OEPINT + 19 + 1 + read-only + + + INCOMPISOIN + 20 + 1 + read-write + + + INCOMPIP + 21 + 1 + read-write + + + FETSUSP + 22 + 1 + read-write + + + RESETDET + 23 + 1 + read-write + + + PRTLNT + 24 + 1 + read-only + + + HCHLNT + 25 + 1 + read-only + + + PTXFEMP + 26 + 1 + read-only + + + CONIDSTSCHNG + 28 + 1 + read-write + + + DISCONNINT + 29 + 1 + read-write + + + SESSREQINT + 30 + 1 + read-write + + + WKUPINT + 31 + 1 + read-write + + + + + GINTMSK + 0x18 + 0x20 + + + MODEMISMSK + 1 + 1 + read-write + + + OTGINTMSK + 2 + 1 + read-write + + + SOFMSK + 3 + 1 + read-write + + + RXFLVIMSK + 4 + 1 + read-write + + + NPTXFEMPMSK + 5 + 1 + read-write + + + GINNAKEFFMSK + 6 + 1 + read-write + + + GOUTNACKEFFMSK + 7 + 1 + read-write + + + ERLYSUSPMSK + 10 + 1 + read-write + + + USBSUSPMSK + 11 + 1 + read-write + + + USBRSTMSK + 12 + 1 + read-write + + + ENUMDONEMSK + 13 + 1 + read-write + + + ISOOUTDROPMSK + 14 + 1 + read-write + + + EOPFMSK + 15 + 1 + read-write + + + EPMISMSK + 17 + 1 + read-write + + + IEPINTMSK + 18 + 1 + read-write + + + OEPINTMSK + 19 + 1 + read-write + + + INCOMPISOINMSK + 20 + 1 + read-write + + + INCOMPIPMSK + 21 + 1 + read-write + + + FETSUSPMSK + 22 + 1 + read-write + + + RESETDETMSK + 23 + 1 + read-write + + + PRTLNTMSK + 24 + 1 + read-write + + + HCHINTMSK + 25 + 1 + read-write + + + PTXFEMPMSK + 26 + 1 + read-write + + + CONIDSTSCHNGMSK + 28 + 1 + read-write + + + DISCONNINTMSK + 29 + 1 + read-write + + + SESSREQINTMSK + 30 + 1 + read-write + + + WKUPINTMSK + 31 + 1 + read-write + + + + + GRXSTSR + 0x1C + 0x20 + + + G_CHNUM + 0 + 4 + read-only + + + G_BCNT + 4 + 11 + read-only + + + G_DPID + 15 + 2 + read-only + + + G_PKTSTS + 17 + 4 + read-only + + + G_FN + 21 + 4 + read-only + + + + + GRXSTSP + 0x20 + 0x20 + + + CHNUM + 0 + 4 + read-only + + + BCNT + 4 + 11 + read-only + + + DPID + 15 + 2 + read-only + + + PKTSTS + 17 + 4 + read-only + + + FN + 21 + 4 + read-only + + + + + GRXFSIZ + 0x24 + 0x20 + 0x00000100 + + + RXFDEP + 0 + 16 + read-write + + + + + GNPTXFSIZ + 0x28 + 0x20 + 0x01000100 + + + NPTXFSTADDR + 0 + 16 + read-write + + + NPTXFDEP + 16 + 16 + read-write + + + + + GNPTXSTS + 0x2C + 0x20 + 0x00040100 + + + NPTXFSPCAVAIL + 0 + 16 + read-only + + + NPTXQSPCAVAIL + 16 + 4 + read-only + + + NPTXQTOP + 24 + 7 + read-only + + + + + GSNPSID + 0x40 + 0x20 + 0x4F54400A + + + SYNOPSYSID + 0 + 32 + read-only + + + + + GHWCFG1 + 0x44 + 0x20 + + + EPDIR + 0 + 32 + read-only + + + + + GHWCFG2 + 0x48 + 0x20 + 0x224DD930 + + + OTGMODE + 0 + 3 + read-only + + + OTGARCH + 3 + 2 + read-only + + + SINGPNT + 5 + 1 + read-only + + + HSPHYTYPE + 6 + 2 + read-only + + + FSPHYTYPE + 8 + 2 + read-only + + + NUMDEVEPS + 10 + 4 + read-only + + + NUMHSTCHNL + 14 + 4 + read-only + + + PERIOSUPPORT + 18 + 1 + read-only + + + DYNFIFOSIZING + 19 + 1 + read-only + + + MULTIPROCINTRPT + 20 + 1 + read-only + + + NPTXQDEPTH + 22 + 2 + read-only + + + PTXQDEPTH + 24 + 2 + read-only + + + TKNQDEPTH + 26 + 5 + read-only + + + OTG_ENABLE_IC_USB + 31 + 1 + read-only + + + + + GHWCFG3 + 0x4C + 0x20 + 0x010004B5 + + + XFERSIZEWIDTH + 0 + 4 + read-only + + + PKTSIZEWIDTH + 4 + 3 + read-only + + + OTGEN + 7 + 1 + read-only + + + I2CINTSEL + 8 + 1 + read-only + + + VNDCTLSUPT + 9 + 1 + read-only + + + OPTFEATURE + 10 + 1 + read-only + + + RSTTYPE + 11 + 1 + read-only + + + ADPSUPPORT + 12 + 1 + read-only + + + HSICMODE + 13 + 1 + read-only + + + BCSUPPORT + 14 + 1 + read-only + + + LPMMODE + 15 + 1 + read-only + + + DFIFODEPTH + 16 + 16 + read-only + + + + + GHWCFG4 + 0x50 + 0x20 + 0xD3F0A030 + + + G_NUMDEVPERIOEPS + 0 + 4 + read-only + + + G_PARTIALPWRDN + 4 + 1 + read-only + + + G_AHBFREQ + 5 + 1 + read-only + + + G_HIBERNATION + 6 + 1 + read-only + + + G_EXTENDEDHIBERNATION + 7 + 1 + read-only + + + G_ACGSUPT + 12 + 1 + read-only + + + G_ENHANCEDLPMSUPT + 13 + 1 + read-only + + + G_PHYDATAWIDTH + 14 + 2 + read-only + + + G_NUMCTLEPS + 16 + 4 + read-only + + + G_IDDQFLTR + 20 + 1 + read-only + + + G_VBUSVALIDFLTR + 21 + 1 + read-only + + + G_AVALIDFLTR + 22 + 1 + read-only + + + G_BVALIDFLTR + 23 + 1 + read-only + + + G_SESSENDFLTR + 24 + 1 + read-only + + + G_DEDFIFOMODE + 25 + 1 + read-only + + + G_INEPS + 26 + 4 + read-only + + + G_DESCDMAENABLED + 30 + 1 + read-only + + + G_DESCDMA + 31 + 1 + read-only + + + + + GDFIFOCFG + 0x5C + 0x20 + + + GDFIFOCFG + 0 + 16 + read-write + + + EPINFOBASEADDR + 16 + 16 + read-write + + + + + HPTXFSIZ + 0x100 + 0x20 + 0x10000200 + + + PTXFSTADDR + 0 + 16 + read-write + + + PTXFSIZE + 16 + 16 + read-write + + + + + DIEPTXF1 + 0x104 + 0x20 + 0x10000200 + + + INEP1TXFSTADDR + 0 + 16 + read-write + + + INEP1TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF2 + 0x108 + 0x20 + 0x10000200 + + + INEP2TXFSTADDR + 0 + 16 + read-write + + + INEP2TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF3 + 0x10C + 0x20 + 0x10000200 + + + INEP3TXFSTADDR + 0 + 16 + read-write + + + INEP3TXFDEP + 16 + 16 + read-write + + + + + DIEPTXF4 + 0x110 + 0x20 + 0x10000200 + + + INEP4TXFSTADDR + 0 + 16 + read-write + + + INEP4TXFDEP + 16 + 16 + read-write + + + + + HCFG + 0x400 + 0x20 + + + H_FSLSPCLKSEL + 0 + 2 + read-write + + + H_FSLSSUPP + 2 + 1 + read-write + + + H_ENA32KHZS + 7 + 1 + read-write + + + H_DESCDMA + 23 + 1 + read-write + + + H_FRLISTEN + 24 + 2 + read-write + + + H_PERSCHEDENA + 26 + 1 + read-write + + + H_MODECHTIMEN + 31 + 1 + read-write + + + + + HFIR + 0x404 + 0x20 + 0x000017D7 + + + FRINT + 0 + 16 + read-write + + + HFIRRLDCTRL + 16 + 1 + read-write + + + + + HFNUM + 0x408 + 0x20 + 0x00003FFF + + + FRNUM + 0 + 14 + read-only + + + FRREM + 16 + 16 + read-only + + + + + HPTXSTS + 0x410 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + 0 + 16 + read-only + + + PTXQSPCAVAIL + 16 + 5 + read-only + + + PTXQTOP + 24 + 8 + read-only + + + + + HAINT + 0x414 + 0x20 + + + HAINT + 0 + 8 + read-only + + + + + HAINTMSK + 0x418 + 0x20 + + + HAINTMSK + 0 + 8 + read-write + + + + + HFLBADDR + 0x41C + 0x20 + + + HFLBADDR + 0 + 32 + read-write + + + + + HPRT + 0x440 + 0x20 + + + PRTCONNSTS + 0 + 1 + read-only + + + PRTCONNDET + 1 + 1 + read-write + + + PRTENA + 2 + 1 + read-write + + + PRTENCHNG + 3 + 1 + read-write + + + PRTOVRCURRACT + 4 + 1 + read-only + + + PRTOVRCURRCHNG + 5 + 1 + read-write + + + PRTRES + 6 + 1 + read-write + + + PRTSUSP + 7 + 1 + read-write + + + PRTRST + 8 + 1 + read-write + + + PRTLNSTS + 10 + 2 + read-only + + + PRTPWR + 12 + 1 + read-write + + + PRTTSTCTL + 13 + 4 + read-write + + + PRTSPD + 17 + 2 + read-only + + + + + HCCHAR0 + 0x500 + 0x20 + + + H_MPS0 + 0 + 11 + read-write + + + H_EPNUM0 + 11 + 4 + read-write + + + H_EPDIR0 + 15 + 1 + read-write + + + H_LSPDDEV0 + 17 + 1 + read-write + + + H_EPTYPE0 + 18 + 2 + read-write + + + H_EC0 + 21 + 1 + read-write + + + H_DEVADDR0 + 22 + 7 + read-write + + + H_ODDFRM0 + 29 + 1 + read-write + + + H_CHDIS0 + 30 + 1 + read-write + + + H_CHENA0 + 31 + 1 + read-write + + + + + HCINT0 + 0x508 + 0x20 + + + H_XFERCOMPL0 + 0 + 1 + read-write + + + H_CHHLTD0 + 1 + 1 + read-write + + + H_AHBERR0 + 2 + 1 + read-write + + + H_STALL0 + 3 + 1 + read-write + + + H_NACK0 + 4 + 1 + read-write + + + H_ACK0 + 5 + 1 + read-write + + + H_NYET0 + 6 + 1 + read-write + + + H_XACTERR0 + 7 + 1 + read-write + + + H_BBLERR0 + 8 + 1 + read-write + + + H_FRMOVRUN0 + 9 + 1 + read-write + + + H_DATATGLERR0 + 10 + 1 + read-write + + + H_BNAINTR0 + 11 + 1 + read-write + + + H_XCS_XACT_ERR0 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR0 + 13 + 1 + read-write + + + + + HCINTMSK0 + 0x50C + 0x20 + + + H_XFERCOMPLMSK0 + 0 + 1 + read-write + + + H_CHHLTDMSK0 + 1 + 1 + read-write + + + H_AHBERRMSK0 + 2 + 1 + read-write + + + H_STALLMSK0 + 3 + 1 + read-write + + + H_NAKMSK0 + 4 + 1 + read-write + + + H_ACKMSK0 + 5 + 1 + read-write + + + H_NYETMSK0 + 6 + 1 + read-write + + + H_XACTERRMSK0 + 7 + 1 + read-write + + + H_BBLERRMSK0 + 8 + 1 + read-write + + + H_FRMOVRUNMSK0 + 9 + 1 + read-write + + + H_DATATGLERRMSK0 + 10 + 1 + read-write + + + H_BNAINTRMSK0 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK0 + 13 + 1 + read-write + + + + + HCTSIZ0 + 0x510 + 0x20 + + + H_XFERSIZE0 + 0 + 19 + read-write + + + H_PKTCNT0 + 19 + 10 + read-write + + + H_PID0 + 29 + 2 + read-write + + + H_DOPNG0 + 31 + 1 + read-write + + + + + HCDMA0 + 0x514 + 0x20 + + + H_DMAADDR0 + 0 + 32 + read-write + + + + + HCDMAB0 + 0x51C + 0x20 + + + H_HCDMAB0 + 0 + 32 + read-only + + + + + HCCHAR1 + 0x520 + 0x20 + + + H_MPS1 + 0 + 11 + read-write + + + H_EPNUM1 + 11 + 4 + read-write + + + H_EPDIR1 + 15 + 1 + read-write + + + H_LSPDDEV1 + 17 + 1 + read-write + + + H_EPTYPE1 + 18 + 2 + read-write + + + H_EC1 + 21 + 1 + read-write + + + H_DEVADDR1 + 22 + 7 + read-write + + + H_ODDFRM1 + 29 + 1 + read-write + + + H_CHDIS1 + 30 + 1 + read-write + + + H_CHENA1 + 31 + 1 + read-write + + + + + HCINT1 + 0x528 + 0x20 + + + H_XFERCOMPL1 + 0 + 1 + read-write + + + H_CHHLTD1 + 1 + 1 + read-write + + + H_AHBERR1 + 2 + 1 + read-write + + + H_STALL1 + 3 + 1 + read-write + + + H_NACK1 + 4 + 1 + read-write + + + H_ACK1 + 5 + 1 + read-write + + + H_NYET1 + 6 + 1 + read-write + + + H_XACTERR1 + 7 + 1 + read-write + + + H_BBLERR1 + 8 + 1 + read-write + + + H_FRMOVRUN1 + 9 + 1 + read-write + + + H_DATATGLERR1 + 10 + 1 + read-write + + + H_BNAINTR1 + 11 + 1 + read-write + + + H_XCS_XACT_ERR1 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR1 + 13 + 1 + read-write + + + + + HCINTMSK1 + 0x52C + 0x20 + + + H_XFERCOMPLMSK1 + 0 + 1 + read-write + + + H_CHHLTDMSK1 + 1 + 1 + read-write + + + H_AHBERRMSK1 + 2 + 1 + read-write + + + H_STALLMSK1 + 3 + 1 + read-write + + + H_NAKMSK1 + 4 + 1 + read-write + + + H_ACKMSK1 + 5 + 1 + read-write + + + H_NYETMSK1 + 6 + 1 + read-write + + + H_XACTERRMSK1 + 7 + 1 + read-write + + + H_BBLERRMSK1 + 8 + 1 + read-write + + + H_FRMOVRUNMSK1 + 9 + 1 + read-write + + + H_DATATGLERRMSK1 + 10 + 1 + read-write + + + H_BNAINTRMSK1 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK1 + 13 + 1 + read-write + + + + + HCTSIZ1 + 0x530 + 0x20 + + + H_XFERSIZE1 + 0 + 19 + read-write + + + H_PKTCNT1 + 19 + 10 + read-write + + + H_PID1 + 29 + 2 + read-write + + + H_DOPNG1 + 31 + 1 + read-write + + + + + HCDMA1 + 0x534 + 0x20 + + + H_DMAADDR1 + 0 + 32 + read-write + + + + + HCDMAB1 + 0x53C + 0x20 + + + H_HCDMAB1 + 0 + 32 + read-only + + + + + HCCHAR2 + 0x540 + 0x20 + + + H_MPS2 + 0 + 11 + read-write + + + H_EPNUM2 + 11 + 4 + read-write + + + H_EPDIR2 + 15 + 1 + read-write + + + H_LSPDDEV2 + 17 + 1 + read-write + + + H_EPTYPE2 + 18 + 2 + read-write + + + H_EC2 + 21 + 1 + read-write + + + H_DEVADDR2 + 22 + 7 + read-write + + + H_ODDFRM2 + 29 + 1 + read-write + + + H_CHDIS2 + 30 + 1 + read-write + + + H_CHENA2 + 31 + 1 + read-write + + + + + HCINT2 + 0x548 + 0x20 + + + H_XFERCOMPL2 + 0 + 1 + read-write + + + H_CHHLTD2 + 1 + 1 + read-write + + + H_AHBERR2 + 2 + 1 + read-write + + + H_STALL2 + 3 + 1 + read-write + + + H_NACK2 + 4 + 1 + read-write + + + H_ACK2 + 5 + 1 + read-write + + + H_NYET2 + 6 + 1 + read-write + + + H_XACTERR2 + 7 + 1 + read-write + + + H_BBLERR2 + 8 + 1 + read-write + + + H_FRMOVRUN2 + 9 + 1 + read-write + + + H_DATATGLERR2 + 10 + 1 + read-write + + + H_BNAINTR2 + 11 + 1 + read-write + + + H_XCS_XACT_ERR2 + 12 + 1 + read-write + + + H_DESC_LST_ROLLINTR2 + 13 + 1 + read-write + + + + + HCINTMSK2 + 0x54C + 0x20 + + + H_XFERCOMPLMSK2 + 0 + 1 + read-write + + + H_CHHLTDMSK2 + 1 + 1 + read-write + + + H_AHBERRMSK2 + 2 + 1 + read-write + + + H_STALLMSK2 + 3 + 1 + read-write + + + H_NAKMSK2 + 4 + 1 + read-write + + + H_ACKMSK2 + 5 + 1 + read-write + + + H_NYETMSK2 + 6 + 1 + read-write + + + H_XACTERRMSK2 + 7 + 1 + read-write + + + H_BBLERRMSK2 + 8 + 1 + read-write + + + H_FRMOVRUNMSK2 + 9 + 1 + read-write + + + H_DATATGLERRMSK2 + 10 + 1 + read-write + + + H_BNAINTRMSK2 + 11 + 1 + read-write + + + H_DESC_LST_ROLLINTRMSK2 + 13 + 1 + read-write + + + + + HCTSIZ2 + 0x550 + 0x20 + + + H_XFERSIZE2 + 0 + 19 + read-write + + + H_PKTCNT2 + 19 + 10 + read-write + + + H_PID2 + 29 + 2 + read-write + + + H_DOPNG2 + 31 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write-only + + + DO_SETD0PID4 + 28 + 1 + write-only + + + DO_SETD1PID4 + 29 + 1 + write-only + + + EPDIS4 + 30 + 1 + read-only + + + EPENA4 + 31 + 1 + read-write + + + + + DOEPINT4 + 0xB88 + 0x20 + + + XFERCOMPL4 + 0 + 1 + read-write + + + EPDISBLD4 + 1 + 1 + read-write + + + AHBERR4 + 2 + 1 + read-write + + + SETUP4 + 3 + 1 + read-write + + + OUTTKNEPDIS4 + 4 + 1 + read-write + + + STSPHSERCVD4 + 5 + 1 + read-write + + + BACK2BACKSETUP4 + 6 + 1 + read-write + + + OUTPKTERR4 + 8 + 1 + read-write + + + BNAINTR4 + 9 + 1 + read-write + + + PKTDRPSTS4 + 11 + 1 + read-write + + + BBLEERR4 + 12 + 1 + read-write + + + NAKINTRPT4 + 13 + 1 + read-write + + + NYEPINTRPT4 + 14 + 1 + read-write + + + STUPPKTRCVD4 + 15 + 1 + read-write + + + + + DOEPTSIZ4 + 0xB90 + 0x20 + + + XFERSIZE4 + 0 + 7 + read-write + + + PKTCNT4 + 19 + 1 + read-write + + + SUPCNT4 + 29 + 2 + read-write + + + + + DOEPDMA4 + 0xB94 + 0x20 + + + DMAADDR4 + 0 + 32 + read-write + + + + + DOEPDMAB4 + 0xB9C + 0x20 + + + DMABUFFERADDR4 + 0 + 32 + read-write + + + + + DOEPCTL5 + 0xBA0 + 0x20 + 0x00008000 + + + MPS5 + 0 + 11 + read-only + + + USBACTEP5 + 15 + 1 + read-only + + + NAKSTS5 + 17 + 1 + read-only + + + EPTYPE5 + 18 + 2 + read-only + + + SNP5 + 20 + 1 + read-write + + + STALL5 + 21 + 1 + read-write + + + CNAK5 + 26 + 1 + write-only + + + DO_SNAK5 + 27 + 1 + write-only + + + DO_SETD0PID5 + 28 + 1 + write-only + + + DO_SETD1PID5 + 29 + 1 + write-only + + + EPDIS5 + 30 + 1 + read-only + + + EPENA5 + 31 + 1 + read-write + + + + + DOEPINT5 + 0xBA8 + 0x20 + + + XFERCOMPL5 + 0 + 1 + read-write + + + EPDISBLD5 + 1 + 1 + read-write + + + AHBERR5 + 2 + 1 + read-write + + + SETUP5 + 3 + 1 + read-write + + + OUTTKNEPDIS5 + 4 + 1 + read-write + + + STSPHSERCVD5 + 5 + 1 + read-write + + + BACK2BACKSETUP5 + 6 + 1 + read-write + + + OUTPKTERR5 + 8 + 1 + read-write + + + BNAINTR5 + 9 + 1 + read-write + + + PKTDRPSTS5 + 11 + 1 + read-write + + + BBLEERR5 + 12 + 1 + read-write + + + NAKINTRPT5 + 13 + 1 + read-write + + + NYEPINTRPT5 + 14 + 1 + read-write + + + STUPPKTRCVD5 + 15 + 1 + read-write + + + + + DOEPTSIZ5 + 0xBB0 + 0x20 + + + XFERSIZE5 + 0 + 7 + read-write + + + PKTCNT5 + 19 + 1 + read-write + + + SUPCNT5 + 29 + 2 + read-write + + + + + DOEPDMA5 + 0xBB4 + 0x20 + + + DMAADDR5 + 0 + 32 + read-write + + + + + DOEPDMAB5 + 0xBBC + 0x20 + + + DMABUFFERADDR5 + 0 + 32 + read-write + + + + + DOEPCTL6 + 0xBC0 + 0x20 + 0x00008000 + + + MPS6 + 0 + 11 + read-only + + + USBACTEP6 + 15 + 1 + read-only + + + NAKSTS6 + 17 + 1 + read-only + + + EPTYPE6 + 18 + 2 + read-only + + + SNP6 + 20 + 1 + read-write + + + STALL6 + 21 + 1 + read-write + + + CNAK6 + 26 + 1 + write-only + + + DO_SNAK6 + 27 + 1 + write-only + + + DO_SETD0PID6 + 28 + 1 + write-only + + + DO_SETD1PID6 + 29 + 1 + write-only + + + EPDIS6 + 30 + 1 + read-only + + + EPENA6 + 31 + 1 + read-write + + + + + DOEPINT6 + 0xBC8 + 0x20 + + + XFERCOMPL6 + 0 + 1 + read-write + + + EPDISBLD6 + 1 + 1 + read-write + + + AHBERR6 + 2 + 1 + read-write + + + SETUP6 + 3 + 1 + read-write + + + OUTTKNEPDIS6 + 4 + 1 + read-write + + + STSPHSERCVD6 + 5 + 1 + read-write + + + BACK2BACKSETUP6 + 6 + 1 + read-write + + + OUTPKTERR6 + 8 + 1 + read-write + + + BNAINTR6 + 9 + 1 + read-write + + + PKTDRPSTS6 + 11 + 1 + read-write + + + BBLEERR6 + 12 + 1 + read-write + + + NAKINTRPT6 + 13 + 1 + read-write + + + NYEPINTRPT6 + 14 + 1 + read-write + + + STUPPKTRCVD6 + 15 + 1 + read-write + + + + + DOEPTSIZ6 + 0xBD0 + 0x20 + + + XFERSIZE6 + 0 + 7 + read-write + + + PKTCNT6 + 19 + 1 + read-write + + + SUPCNT6 + 29 + 2 + read-write + + + + + DOEPDMA6 + 0xBD4 + 0x20 + + + DMAADDR6 + 0 + 32 + read-write + + + + + DOEPDMAB6 + 0xBDC + 0x20 + + + DMABUFFERADDR6 + 0 + 32 + read-write + + + + + PCGCCTL + 0xE00 + 0x20 + + + STOPPCLK + 0 + 1 + read-write + + + GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + 2 + 1 + read-write + + + RSTPDWNMODULE + 3 + 1 + read-write + + + PHYSLEEP + 6 + 1 + read-only + + + L1SUSPENDED + 7 + 1 + read-only + + + RESETAFTERSUSP + 8 + 1 + read-write + + + + + + + USB_DEVICE + Peripheral USB_DEVICE + USB_DEVICE + 0x60038000 + + 0x0 + 0x50 + registers + + + USB_DEVICE + 96 + + + + EP1 + Endpoint 1 FIFO register + 0x0 + 0x20 + + + RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Endpoint 1 configure and status register + 0x4 + 0x20 + 0x00000002 + + + WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Raw status interrupt + 0x8 + 0x20 + 0x00000008 + + + JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-only + + + SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-only + + + PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-only + + + CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-only + + + CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-only + + + STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-only + + + + + INT_ST + Masked interrupt + 0xC + 0x20 + + + JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x10 + 0x20 + + + JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x14 + 0x20 + + + JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + + + CONF0 + Configure 0 register + 0x18 + 0x20 + 0x00004200 + + + PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + PHY_TX_EDGE_SEL + 0: TX output at clock negedge. 1: Tx output at clock posedge. + 15 + 1 + read-write + + + USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 16 + 1 + read-write + + + + + TEST + USB Internal PHY test register + 0x1C + 0x20 + + + ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + USB-JTAG FIFO status + 0x20 + 0x20 + 0x00000044 + + + IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + SOF frame number + 0x24 + 0x20 + + + SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + IN Endpoint 0 status + 0x28 + 0x20 + 0x00000001 + + + IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + IN Endpoint 1 status + 0x2C + 0x20 + 0x00000001 + + + IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + IN Endpoint 2 status + 0x30 + 0x20 + 0x00000001 + + + IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + IN Endpoint 3 status + 0x34 + 0x20 + 0x00000001 + + + IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + OUT Endpoint 0 status + 0x38 + 0x20 + + + OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + OUT Endpoint 1 status + 0x3C + 0x20 + + + OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + OUT Endpoint 2 status + 0x40 + 0x20 + + + OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + MISC register + 0x44 + 0x20 + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Power control + 0x48 + 0x20 + 0x00000002 + + + USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02101200 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + Peripheral USB_WRAP + USB_WRAP + 0x60039000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB OTG Wrapper Configure Register + 0x0 + 0x20 + 0x001C0000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers + 31 + 1 + read-write + + + + + TEST_CONF + USB Internal PHY Testing Register + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + DATE + Version Control Register + 0x3FC + 0x20 + 0x02102010 + + + USB_WRAP_DATE + Date register + 0 + 32 + read-write + + + + + + + WCL + Peripheral WCL + WCL + 0x600D0000 + + 0x0 + 0x160 + registers + + + + Core_0_ENTRY_1_ADDR + Core_0 Entry 1 address configuration Register + 0x0 + 0x20 + + + CORE_0_ENTRY_1_ADDR + Core_0 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_2_ADDR + Core_0 Entry 2 address configuration Register + 0x4 + 0x20 + + + CORE_0_ENTRY_2_ADDR + Core_0 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_3_ADDR + Core_0 Entry 3 address configuration Register + 0x8 + 0x20 + + + CORE_0_ENTRY_3_ADDR + Core_0 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_4_ADDR + Core_0 Entry 4 address configuration Register + 0xC + 0x20 + + + CORE_0_ENTRY_4_ADDR + Core_0 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_5_ADDR + Core_0 Entry 5 address configuration Register + 0x10 + 0x20 + + + CORE_0_ENTRY_5_ADDR + Core_0 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_6_ADDR + Core_0 Entry 6 address configuration Register + 0x14 + 0x20 + + + CORE_0_ENTRY_6_ADDR + Core_0 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_7_ADDR + Core_0 Entry 7 address configuration Register + 0x18 + 0x20 + + + CORE_0_ENTRY_7_ADDR + Core_0 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_8_ADDR + Core_0 Entry 8 address configuration Register + 0x1C + 0x20 + + + CORE_0_ENTRY_8_ADDR + Core_0 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_9_ADDR + Core_0 Entry 9 address configuration Register + 0x20 + 0x20 + + + CORE_0_ENTRY_9_ADDR + Core_0 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_10_ADDR + Core_0 Entry 10 address configuration Register + 0x24 + 0x20 + + + CORE_0_ENTRY_10_ADDR + Core_0 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_11_ADDR + Core_0 Entry 11 address configuration Register + 0x28 + 0x20 + + + CORE_0_ENTRY_11_ADDR + Core_0 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_12_ADDR + Core_0 Entry 12 address configuration Register + 0x2C + 0x20 + + + CORE_0_ENTRY_12_ADDR + Core_0 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_13_ADDR + Core_0 Entry 13 address configuration Register + 0x30 + 0x20 + + + CORE_0_ENTRY_13_ADDR + Core_0 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_CHECK + Core_0 Entry check configuration Register + 0x7C + 0x20 + 0x00000002 + + + CORE_0_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_0_STATUSTABLE1 + Status register of world switch of entry 1 + 0x80 + 0x20 + + + CORE_0_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_0_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE2 + Status register of world switch of entry 2 + 0x84 + 0x20 + + + CORE_0_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_0_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE3 + Status register of world switch of entry 3 + 0x88 + 0x20 + + + CORE_0_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_0_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE4 + Status register of world switch of entry 4 + 0x8C + 0x20 + + + CORE_0_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_0_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE5 + Status register of world switch of entry 5 + 0x90 + 0x20 + + + CORE_0_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_0_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE6 + Status register of world switch of entry 6 + 0x94 + 0x20 + + + CORE_0_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_0_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE7 + Status register of world switch of entry 7 + 0x98 + 0x20 + + + CORE_0_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_0_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE8 + Status register of world switch of entry 8 + 0x9C + 0x20 + + + CORE_0_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_0_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE9 + Status register of world switch of entry 9 + 0xA0 + 0x20 + + + CORE_0_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_0_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE10 + Status register of world switch of entry 10 + 0xA4 + 0x20 + + + CORE_0_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_0_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE11 + Status register of world switch of entry 11 + 0xA8 + 0x20 + + + CORE_0_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_0_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE12 + Status register of world switch of entry 12 + 0xAC + 0x20 + + + CORE_0_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_0_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE13 + Status register of world switch of entry 13 + 0xB0 + 0x20 + + + CORE_0_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_0_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE_CURRENT + Status register of statustable current + 0xFC + 0x20 + + + CORE_0_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2 + 1 + 13 + read-write + + + + + Core_0_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x100 + 0x20 + + + CORE_0_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_0_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x104 + 0x20 + + + CORE_0_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_0_MESSAGE_PHASE + Clear writer_buffer status register + 0x108 + 0x20 + + + CORE_0_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_0_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_0_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking data + 5 + 1 + read-only + + + CORE_0_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking address. + 6 + 1 + read-only + + + + + Core_0_World_TRIGGER_ADDR + Core_0 trigger address configuration Register + 0x140 + 0x20 + + + CORE_0_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_0_World_PREPARE + Core_0 prepare world configuration Register + 0x144 + 0x20 + + + CORE_0_WORLD_PREPARE + This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_0_World_UPDATE + Core_0 configuration update register + 0x148 + 0x20 + + + CORE_0_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_Cancel + Core_0 configuration cancel register + 0x14C + 0x20 + + + CORE_0_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_IRam0 + Core_0 Iram0 world register + 0x150 + 0x20 + + + CORE_0_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_0_World_DRam0_PIF + Core_0 dram0 and PIF world register + 0x154 + 0x20 + + + CORE_0_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_0_World_Phase + Core_0 world status register + 0x158 + 0x20 + + + CORE_0_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1, 1 means value. + 0 + 1 + read-only + + + + + Core_0_NMI_MASK_ENABLE + Core_0 NMI mask enable register + 0x180 + 0x20 + + + CORE_0_NMI_MASK_ENABLE + this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_TRIGGER_ADDR + Core_0 NMI mask trigger address register + 0x184 + 0x20 + + + CORE_0_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails + 0 + 32 + read-write + + + + + Core_0_NMI_MASK_DISABLE + Core_0 NMI mask disable register + 0x188 + 0x20 + + + CORE_0_NMI_MASK_DISABLE + this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_CANCLE + Core_0 NMI mask disable register + 0x18C + 0x20 + + + CORE_0_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_0_NMI_MASK + Core_0 NMI mask register + 0x190 + 0x20 + + + CORE_0_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_0_NMI_MASK_PHASE + Core_0 NMI mask phase register + 0x194 + 0x20 + + + CORE_0_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + Core_1_ENTRY_1_ADDR + Core_1 Entry 1 address configuration Register + 0x400 + 0x20 + + + CORE_1_ENTRY_1_ADDR + Core_1 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_2_ADDR + Core_1 Entry 2 address configuration Register + 0x404 + 0x20 + + + CORE_1_ENTRY_2_ADDR + Core_1 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_3_ADDR + Core_1 Entry 3 address configuration Register + 0x408 + 0x20 + + + CORE_1_ENTRY_3_ADDR + Core_1 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_4_ADDR + Core_1 Entry 4 address configuration Register + 0x40C + 0x20 + + + CORE_1_ENTRY_4_ADDR + Core_1 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_5_ADDR + Core_1 Entry 5 address configuration Register + 0x410 + 0x20 + + + CORE_1_ENTRY_5_ADDR + Core_1 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_6_ADDR + Core_1 Entry 6 address configuration Register + 0x414 + 0x20 + + + CORE_1_ENTRY_6_ADDR + Core_1 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_7_ADDR + Core_1 Entry 7 address configuration Register + 0x418 + 0x20 + + + CORE_1_ENTRY_7_ADDR + Core_1 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_8_ADDR + Core_1 Entry 8 address configuration Register + 0x41C + 0x20 + + + CORE_1_ENTRY_8_ADDR + Core_1 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_9_ADDR + Core_1 Entry 9 address configuration Register + 0x420 + 0x20 + + + CORE_1_ENTRY_9_ADDR + Core_1 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_10_ADDR + Core_1 Entry 10 address configuration Register + 0x424 + 0x20 + + + CORE_1_ENTRY_10_ADDR + Core_1 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_11_ADDR + Core_1 Entry 11 address configuration Register + 0x428 + 0x20 + + + CORE_1_ENTRY_11_ADDR + Core_1 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_12_ADDR + Core_1 Entry 12 address configuration Register + 0x42C + 0x20 + + + CORE_1_ENTRY_12_ADDR + Core_1 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_13_ADDR + Core_1 Entry 13 address configuration Register + 0x430 + 0x20 + + + CORE_1_ENTRY_13_ADDR + Core_1 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_CHECK + Core_1 Entry check configuration Register + 0x47C + 0x20 + 0x00000002 + + + CORE_1_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_1_STATUSTABLE1 + Status register of world switch of entry 1 + 0x480 + 0x20 + + + CORE_1_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_1_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE2 + Status register of world switch of entry 2 + 0x484 + 0x20 + + + CORE_1_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_1_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE3 + Status register of world switch of entry 3 + 0x488 + 0x20 + + + CORE_1_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_1_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE4 + Status register of world switch of entry 4 + 0x48C + 0x20 + + + CORE_1_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_1_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE5 + Status register of world switch of entry 5 + 0x490 + 0x20 + + + CORE_1_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_1_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE6 + Status register of world switch of entry 6 + 0x494 + 0x20 + + + CORE_1_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_1_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE7 + Status register of world switch of entry 7 + 0x498 + 0x20 + + + CORE_1_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_1_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE8 + Status register of world switch of entry 8 + 0x49C + 0x20 + + + CORE_1_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_1_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE9 + Status register of world switch of entry 9 + 0x4A0 + 0x20 + + + CORE_1_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_1_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE10 + Status register of world switch of entry 10 + 0x4A4 + 0x20 + + + CORE_1_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_1_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE11 + Status register of world switch of entry 11 + 0x4A8 + 0x20 + + + CORE_1_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_1_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE12 + Status register of world switch of entry 12 + 0x4AC + 0x20 + + + CORE_1_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_1_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE13 + Status register of world switch of entry 13 + 0x4B0 + 0x20 + + + CORE_1_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_1_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE_CURRENT + Status register of statustable current + 0x4FC + 0x20 + + + CORE_1_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1 + 1 + 13 + read-write + + + + + Core_1_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x500 + 0x20 + + + CORE_1_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_1_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x504 + 0x20 + + + CORE_1_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_1_MESSAGE_PHASE + Clear writer_buffer status register + 0x508 + 0x20 + + + CORE_1_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_1_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_1_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking data + 5 + 1 + read-only + + + CORE_1_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking address. + 6 + 1 + read-only + + + + + Core_1_World_TRIGGER_ADDR + Core_1 trigger address configuration Register + 0x540 + 0x20 + + + CORE_1_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_1_World_PREPARE + Core_1 prepare world configuration Register + 0x544 + 0x20 + + + CORE_1_WORLD_PREPARE + This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_1_World_UPDATE + Core_1 configuration update register + 0x548 + 0x20 + + + CORE_1_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_Cancel + Core_1 configuration cancel register + 0x54C + 0x20 + + + CORE_1_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_IRam0 + Core_1 Iram0 world register + 0x550 + 0x20 + + + CORE_1_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_1_World_DRam0_PIF + Core_1 dram0 and PIF world register + 0x554 + 0x20 + + + CORE_1_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_1_World_Phase + Core_0 world status register + 0x558 + 0x20 + + + CORE_1_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1,1 means value. + 0 + 1 + read-only + + + + + Core_1_NMI_MASK_ENABLE + Core_1 NMI mask enable register + 0x580 + 0x20 + + + CORE_1_NMI_MASK_ENABLE + this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_TRIGGER_ADDR + Core_1 NMI mask trigger addr register + 0x584 + 0x20 + + + CORE_1_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address + 0 + 32 + read-write + + + + + Core_1_NMI_MASK_DISABLE + Core_1 NMI mask disable register + 0x588 + 0x20 + + + CORE_1_NMI_MASK_DISABLE + this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_CANCLE + Core_1 NMI mask disable register + 0x58C + 0x20 + + + CORE_1_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_1_NMI_MASK + Core_1 NMI mask register + 0x590 + 0x20 + + + CORE_1_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_1_NMI_MASK_PHASE + Core_1 NMI mask phase register + 0x594 + 0x20 + + + CORE_1_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x600CC000 + + 0x0 + 0x60 + registers + + + + 16 + 0x4 + PLAIN_%s + Plaintext register %s + 0x0 + 0x20 + + + PLAIN_0 + Stores the nth 32-bit piece of plaintext. + 0 + 32 + read-write + + + + + LINESIZE + XTS-AES line-size register + 0x40 + 0x20 + + + LINESIZE + Configures the data size of one encryption. + 0 + 1 + read-write + + + + + DESTINATION + XTS-AES destination register + 0x44 + 0x20 + + + DESTINATION + Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + physical address + 0x48 + 0x20 + + + PHYSICAL_ADDRESS + Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes. + 0 + 30 + read-write + + + + + TRIGGER + XTS-AES trigger register + 0x4C + 0x20 + + + TRIGGER + Write 1 to activate manual encryption. + 0 + 1 + write-only + + + + + RELEASE + XTS-AES release control register + 0x50 + 0x20 + + + RELEASE + Write 1 to grant SPI1 access to encrypted result. + 0 + 1 + write-only + + + + + DESTROY + XTS-AES destroy control register + 0x54 + 0x20 + + + DESTROY + Write 1 to destroy encrypted result. + 0 + 1 + write-only + + + + + STATE + XTS-AES status register + 0x58 + 0x20 + + + STATE + Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI. + 0 + 2 + read-only + + + + + DATE + XTS-AES version control register + 0x5C + 0x20 + 0x20200111 + + + DATE + Manual Encryption block version information. + 0 + 30 + read-write + + + + + + + diff --git a/tools/ide-debug/svd/esp8266.svd b/tools/ide-debug/svd/esp8266.svd new file mode 100644 index 0000000..ea9df2d --- /dev/null +++ b/tools/ide-debug/svd/esp8266.svd @@ -0,0 +1,6446 @@ + + + ESP8266 + 1.0 + ESP8266 + 8 + 32 + + Xtensa LX106 + 1 + little + false + true + 3 + false + + + + DPORT + 0x3ff00000 + + 0 + 0x00000040 + registers + + + + EDGE_INT_ENABLE + 0x4 + EDGE_INT_ENABLE + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + DPORT_CTL + 0x14 + DPORT_CTL + 32 + 0x00000000 + + + DPORT_CTL_DOUBLE_CLK + 0 + 1 + read-write + + + + + + + EFUSE + 0x3ff00050 + + 0 + 0x00000080 + registers + + + + EFUSE_DATA0 + 0x0 + EFUSE_DATA0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA1 + 0x4 + EFUSE_DATA1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA2 + 0x8 + EFUSE_DATA2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA3 + 0xc + EFUSE_DATA3 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + GPIO + 0x60000300 + + 0 + 0x000003a0 + registers + + + + GPIO_OUT + 0x0 + BT-Coexist Selection register + 32 + 0x00000000 + + + GPIO_BT_SEL + BT-Coexist Selection register + 16 + 16 + read-write + + + GPIO_OUT_DATA + The output value when the GPIO pin is set as output. + 0 + 16 + read-write + + + + + GPIO_OUT_W1TS + 0x4 + GPIO_OUT_W1TS + 32 + 0x00000000 + + + GPIO_OUT_DATA_W1TS + Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA + 0 + 16 + write-only + + + + + GPIO_OUT_W1TC + 0x8 + GPIO_OUT_W1TC + 32 + 0x00000000 + + + GPIO_OUT_DATA_W1TC + Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA + 0 + 16 + write-only + + + + + GPIO_ENABLE + 0xc + GPIO_ENABLE + 32 + 0x00000000 + + + GPIO_SDIO_SEL + SDIO-dis selection register + 16 + 6 + read-write + + + GPIO_ENABLE_DATA + The output enable register. + 0 + 16 + read-write + + + + + GPIO_ENABLE_W1TS + 0x10 + GPIO_ENABLE_W1TS + 32 + 0x00000000 + + + GPIO_ENABLE_DATA_W1TS + Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA + 0 + 16 + write-only + + + + + GPIO_ENABLE_W1TC + 0x14 + GPIO_ENABLE_W1TC + 32 + 0x00000000 + + + GPIO_ENABLE_DATA_W1TC + Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA + 0 + 16 + write-only + + + + + GPIO_IN + 0x18 + The values of the strapping pins. + 32 + 0x00000000 + + + GPIO_STRAPPING + The values of the strapping pins. + 16 + 16 + read-write + + + GPIO_IN_DATA + The values of the GPIO pins when the GPIO pin is set as input. + 0 + 16 + read-write + + + + + GPIO_STATUS + 0x1c + GPIO_STATUS + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT + Interrupt enable register. + 0 + 16 + read-write + + + + + GPIO_STATUS_W1TS + 0x20 + GPIO_STATUS_W1TS + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT_W1TS + Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT + 0 + 16 + write-only + + + + + GPIO_STATUS_W1TC + 0x24 + GPIO_STATUS_W1TC + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT_W1TC + Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT + 0 + 16 + write-only + + + + + GPIO_PIN0 + 0x28 + GPIO_PIN0 + 32 + 0x00000000 + + + GPIO_PIN0_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN0_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN0_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN0_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN1 + 0x2c + GPIO_PIN1 + 32 + 0x00000000 + + + GPIO_PIN1_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN1_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN1_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN1_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN2 + 0x30 + GPIO_PIN2 + 32 + 0x00000000 + + + GPIO_PIN2_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN2_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN2_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN2_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN3 + 0x34 + GPIO_PIN3 + 32 + 0x00000000 + + + GPIO_PIN3_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN3_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN3_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN3_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN4 + 0x38 + GPIO_PIN4 + 32 + 0x00000000 + + + GPIO_PIN4_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN4_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN4_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN4_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN5 + 0x3c + GPIO_PIN5 + 32 + 0x00000000 + + + GPIO_PIN5_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN5_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN5_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN5_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN6 + 0x40 + GPIO_PIN6 + 32 + 0x00000000 + + + GPIO_PIN6_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN6_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN6_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN6_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN7 + 0x44 + GPIO_PIN7 + 32 + 0x00000000 + + + GPIO_PIN7_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN7_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN7_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN7_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN8 + 0x48 + GPIO_PIN8 + 32 + 0x00000000 + + + GPIO_PIN8_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN8_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN8_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN8_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN9 + 0x4c + GPIO_PIN9 + 32 + 0x00000000 + + + GPIO_PIN9_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN9_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN9_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN9_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN10 + 0x50 + GPIO_PIN10 + 32 + 0x00000000 + + + GPIO_PIN10_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN10_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN10_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN10_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN11 + 0x54 + GPIO_PIN11 + 32 + 0x00000000 + + + GPIO_PIN11_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN11_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN11_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN11_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN12 + 0x58 + GPIO_PIN12 + 32 + 0x00000000 + + + GPIO_PIN12_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN12_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN12_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN12_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN13 + 0x5c + GPIO_PIN13 + 32 + 0x00000000 + + + GPIO_PIN13_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN13_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN13_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN13_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN14 + 0x60 + GPIO_PIN14 + 32 + 0x00000000 + + + GPIO_PIN14_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN14_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN14_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN14_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_PIN15 + 0x64 + GPIO_PIN15 + 32 + 0x00000000 + + + GPIO_PIN15_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5 + 10 + 1 + read-write + + + GPIO_PIN15_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level + 7 + 3 + read-write + + + GPIO_PIN15_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + + + GPIO_PIN15_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + + + + + GPIO_SIGMA_DELTA + 0x68 + GPIO_SIGMA_DELTA + 32 + 0x00000000 + + + SIGMA_DELTA_ENABLE + 1: enable sigma-delta; 0: disable + 16 + 1 + read-write + + + SIGMA_DELTA_PRESCALAR + Clock pre-divider for sigma-delta. + 8 + 8 + read-write + + + SIGMA_DELTA_TARGET + target level of the sigma-delta. It is a signed byte. + 0 + 8 + read-write + + + + + GPIO_RTC_CALIB_SYNC + 0x6c + Positvie edge of this bit will trigger the RTC-clock-calibration process. + 32 + 0x00000000 + + + RTC_CALIB_START + Positvie edge of this bit will trigger the RTC-clock-calibration process. + 31 + 1 + read-write + + + RTC_PERIOD_NUM + The cycle number of RTC-clock during RTC-clock-calibration + 0 + 10 + read-write + + + + + GPIO_RTC_CALIB_VALUE + 0x70 + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 32 + 0x00000000 + + + RTC_CALIB_RDY + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 31 + 1 + read-write + + + RTC_CALIB_RDY_REAL + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 30 + 1 + read-write + + + RTC_CALIB_VALUE + The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock + 0 + 20 + read-write + + + + + + + I2S + 0x60000e00 + + 0 + 0x00000160 + registers + + + + I2STXFIFO + 0x0 + I2STXFIFO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + I2SRXFIFO + 0x4 + I2SRXFIFO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + I2SCONF + 0x8 + I2SCONF + 32 + 0x00000000 + + + I2S_BCK_DIV_NUM + 22 + 6 + read-write + + + I2S_CLKM_DIV_NUM + 16 + 6 + read-write + + + I2S_BITS_MOD + 12 + 4 + read-write + + + I2S_RECE_MSB_SHIFT + 11 + 1 + read-write + + + I2S_TRANS_MSB_SHIFT + 10 + 1 + read-write + + + I2S_I2S_RX_START + 9 + 1 + read-write + + + I2S_I2S_TX_START + 8 + 1 + read-write + + + I2S_MSB_RIGHT + 7 + 1 + read-write + + + I2S_RIGHT_FIRST + 6 + 1 + read-write + + + I2S_RECE_SLAVE_MOD + 5 + 1 + read-write + + + I2S_TRANS_SLAVE_MOD + 4 + 1 + read-write + + + I2S_I2S_RX_FIFO_RESET + 3 + 1 + read-write + + + I2S_I2S_TX_FIFO_RESET + 2 + 1 + read-write + + + I2S_I2S_RX_RESET + 1 + 1 + read-write + + + I2S_I2S_TX_RESET + 0 + 1 + read-write + + + + + I2SINT_RAW + 0xc + I2SINT_RAW + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_RAW + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_RAW + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_RAW + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_RAW + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_RAW + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_RAW + 0 + 1 + read-write + + + + + I2SINT_ST + 0x10 + I2SINT_ST + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_ST + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_ST + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_ST + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_ST + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_ST + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_ST + 0 + 1 + read-write + + + + + I2SINT_ENA + 0x14 + I2SINT_ENA + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_ENA + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_ENA + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_ENA + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_ENA + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_ENA + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_ENA + 0 + 1 + read-write + + + + + I2SINT_CLR + 0x18 + I2SINT_CLR + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_CLR + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_CLR + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_CLR + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_CLR + 2 + 1 + read-write + + + I2S_I2S_PUT_DATA_INT_CLR + 1 + 1 + read-write + + + I2S_I2S_TAKE_DATA_INT_CLR + 0 + 1 + read-write + + + + + I2STIMING + 0x1c + I2STIMING + 32 + 0x00000000 + + + I2S_TRANS_BCK_IN_INV + 22 + 1 + read-write + + + I2S_RECE_DSYNC_SW + 21 + 1 + read-write + + + I2S_TRANS_DSYNC_SW + 20 + 1 + read-write + + + I2S_RECE_BCK_OUT_DELAY + 18 + 2 + read-write + + + I2S_RECE_WS_OUT_DELAY + 16 + 2 + read-write + + + I2S_TRANS_SD_OUT_DELAY + 14 + 2 + read-write + + + I2S_TRANS_WS_OUT_DELAY + 12 + 2 + read-write + + + I2S_TRANS_BCK_OUT_DELAY + 10 + 2 + read-write + + + I2S_RECE_SD_IN_DELAY + 8 + 2 + read-write + + + I2S_RECE_WS_IN_DELAY + 6 + 2 + read-write + + + I2S_RECE_BCK_IN_DELAY + 4 + 2 + read-write + + + I2S_TRANS_WS_IN_DELAY + 2 + 2 + read-write + + + I2S_TRANS_BCK_IN_DELAY + 0 + 2 + read-write + + + + + I2S_FIFO_CONF + 0x20 + I2S_FIFO_CONF + 32 + 0x00000000 + + + I2S_I2S_RX_FIFO_MOD + 16 + 3 + read-write + + + I2S_I2S_TX_FIFO_MOD + 13 + 3 + read-write + + + I2S_I2S_DSCR_EN + 12 + 1 + read-write + + + I2S_I2S_TX_DATA_NUM + 6 + 6 + read-write + + + I2S_I2S_RX_DATA_NUM + 0 + 6 + read-write + + + + + I2SRXEOF_NUM + 0x24 + I2SRXEOF_NUM + 32 + 0x00000000 + + + I2S_I2S_RX_EOF_NUM + 0 + 32 + read-write + + + + + I2SCONF_SIGLE_DATA + 0x28 + I2SCONF_SIGLE_DATA + 32 + 0x00000000 + + + I2S_I2S_SIGLE_DATA + 0 + 32 + read-write + + + + + + + IO_MUX + 0x60000800 + + 0 + 0x00000220 + registers + + + + IO_MUX_CONF + 0x0 + IO_MUX_CONF + 32 + 0x00000000 + + + SPI0_CLK_EQU_SYS_CLK + 8 + 1 + read-write + + + SPI1_CLK_EQU_SYS_CLK + 9 + 1 + read-write + + + + + IO_MUX_MTDI + 0x4 + IO_MUX_MTDI + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_MTCK + 0x8 + IO_MUX_MTCK + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_MTMS + 0xc + IO_MUX_MTMS + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_MTDO + 0x10 + IO_MUX_MTDO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_U0RXD + 0x14 + IO_MUX_U0RXD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_U0TXD + 0x18 + IO_MUX_U0TXD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_CLK + 0x1c + IO_MUX_SD_CLK + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_DATA0 + 0x20 + IO_MUX_SD_DATA0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_DATA1 + 0x24 + IO_MUX_SD_DATA1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_DATA2 + 0x28 + IO_MUX_SD_DATA2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_DATA3 + 0x2c + IO_MUX_SD_DATA3 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_SD_CMD + 0x30 + IO_MUX_SD_CMD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_GPIO0 + 0x34 + IO_MUX_GPIO0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_GPIO2 + 0x38 + IO_MUX_GPIO2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_GPIO4 + 0x3c + IO_MUX_GPIO4 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + IO_MUX_GPIO5 + 0x40 + IO_MUX_GPIO5 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + RTC + 0x60000700 + + 0 + 0x00000040 + registers + + + + RTC_STORE0 + 0x30 + RTC_STORE0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + RTC_STATE1 + 0x14 + RTC_STATE1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + SLC + 0x60000b00 + + 0 + 0x00000400 + registers + + + + SLC_CONF0 + 0x0 + SLC_CONF0 + 32 + 0x00000000 + + + SLC_MODE + 12 + 2 + read-write + + + SLC_DATA_BURST_EN + 9 + 1 + read-write + + + SLC_DSCR_BURST_EN + 8 + 1 + read-write + + + SLC_RX_NO_RESTART_CLR + 7 + 1 + read-write + + + SLC_RX_AUTO_WRBACK + 6 + 1 + read-write + + + SLC_RX_LOOP_TEST + 5 + 1 + read-write + + + SLC_TX_LOOP_TEST + 4 + 1 + read-write + + + SLC_AHBM_RST + 3 + 1 + read-write + + + SLC_AHBM_FIFO_RST + 2 + 1 + read-write + + + SLC_RXLINK_RST + 1 + 1 + read-write + + + SLC_TXLINK_RST + 0 + 1 + read-write + + + + + SLC_INT_RAW + 0x4 + SLC_INT_RAW + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_RAW + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_RAW + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_RAW + 19 + 1 + read-write + + + SLC_TOHOST_INT_RAW + 18 + 1 + read-write + + + SLC_RX_EOF_INT_RAW + 17 + 1 + read-write + + + SLC_RX_DONE_INT_RAW + 16 + 1 + read-write + + + SLC_TX_EOF_INT_RAW + 15 + 1 + read-write + + + SLC_TX_DONE_INT_RAW + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_RAW + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_RAW + 12 + 1 + read-write + + + SLC_TX_OVF_INT_RAW + 11 + 1 + read-write + + + SLC_RX_UDF_INT_RAW + 10 + 1 + read-write + + + SLC_TX_START_INT_RAW + 9 + 1 + read-write + + + SLC_RX_START_INT_RAW + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_RAW + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_RAW + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_RAW + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_RAW + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_RAW + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_RAW + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_RAW + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_RAW + 0 + 1 + read-write + + + + + SLC_INT_STATUS + 0x8 + SLC_INT_STATUS + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_ST + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_ST + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_ST + 19 + 1 + read-write + + + SLC_TOHOST_INT_ST + 18 + 1 + read-write + + + SLC_RX_EOF_INT_ST + 17 + 1 + read-write + + + SLC_RX_DONE_INT_ST + 16 + 1 + read-write + + + SLC_TX_EOF_INT_ST + 15 + 1 + read-write + + + SLC_TX_DONE_INT_ST + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_ST + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_ST + 12 + 1 + read-write + + + SLC_TX_OVF_INT_ST + 11 + 1 + read-write + + + SLC_RX_UDF_INT_ST + 10 + 1 + read-write + + + SLC_TX_START_INT_ST + 9 + 1 + read-write + + + SLC_RX_START_INT_ST + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_ST + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_ST + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_ST + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_ST + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_ST + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_ST + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_ST + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_ST + 0 + 1 + read-write + + + + + SLC_INT_ENA + 0xc + SLC_INT_ENA + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_ENA + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_ENA + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_ENA + 19 + 1 + read-write + + + SLC_TOHOST_INT_ENA + 18 + 1 + read-write + + + SLC_RX_EOF_INT_ENA + 17 + 1 + read-write + + + SLC_RX_DONE_INT_ENA + 16 + 1 + read-write + + + SLC_TX_EOF_INT_ENA + 15 + 1 + read-write + + + SLC_TX_DONE_INT_ENA + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_ENA + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_ENA + 12 + 1 + read-write + + + SLC_TX_OVF_INT_ENA + 11 + 1 + read-write + + + SLC_RX_UDF_INT_ENA + 10 + 1 + read-write + + + SLC_TX_START_INT_ENA + 9 + 1 + read-write + + + SLC_RX_START_INT_ENA + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + + + SLC_INT_CLR + 0x10 + SLC_INT_CLR + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_CLR + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_CLR + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_CLR + 19 + 1 + read-write + + + SLC_TOHOST_INT_CLR + 18 + 1 + read-write + + + SLC_RX_EOF_INT_CLR + 17 + 1 + read-write + + + SLC_RX_DONE_INT_CLR + 16 + 1 + read-write + + + SLC_TX_EOF_INT_CLR + 15 + 1 + read-write + + + SLC_TX_DONE_INT_CLR + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_CLR + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_CLR + 12 + 1 + read-write + + + SLC_TX_OVF_INT_CLR + 11 + 1 + read-write + + + SLC_RX_UDF_INT_CLR + 10 + 1 + read-write + + + SLC_TX_START_INT_CLR + 9 + 1 + read-write + + + SLC_RX_START_INT_CLR + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_CLR + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_CLR + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_CLR + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_CLR + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_CLR + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_CLR + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_CLR + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_CLR + 0 + 1 + read-write + + + + + SLC_RX_STATUS + 0x14 + SLC_RX_STATUS + 32 + 0x00000000 + + + SLC_RX_EMPTY + 1 + 1 + read-write + + + SLC_RX_FULL + 0 + 1 + read-write + + + + + SLC_RX_FIFO_PUSH + 0x18 + SLC_RX_FIFO_PUSH + 32 + 0x00000000 + + + SLC_RXFIFO_PUSH + 16 + 1 + read-write + + + SLC_RXFIFO_WDATA + 0 + 9 + read-write + + + + + SLC_TX_STATUS + 0x1c + SLC_TX_STATUS + 32 + 0x00000000 + + + SLC_TX_EMPTY + 1 + 1 + read-write + + + SLC_TX_FULL + 0 + 1 + read-write + + + + + SLC_TX_FIFO_POP + 0x20 + SLC_TX_FIFO_POP + 32 + 0x00000000 + + + SLC_TXFIFO_POP + 16 + 1 + read-write + + + SLC_TXFIFO_RDATA + 0 + 11 + read-write + + + + + SLC_RX_LINK + 0x24 + SLC_RX_LINK + 32 + 0x00000000 + + + SLC_RXLINK_PARK + 31 + 1 + read-write + + + SLC_RXLINK_RESTART + 30 + 1 + read-write + + + SLC_RXLINK_START + 29 + 1 + read-write + + + SLC_RXLINK_STOP + 28 + 1 + read-write + + + SLC_RXLINK_ADDR + 0 + 20 + read-write + + + + + SLC_TX_LINK + 0x28 + SLC_TX_LINK + 32 + 0x00000000 + + + SLC_TXLINK_PARK + 31 + 1 + read-write + + + SLC_TXLINK_RESTART + 30 + 1 + read-write + + + SLC_TXLINK_START + 29 + 1 + read-write + + + SLC_TXLINK_STOP + 28 + 1 + read-write + + + SLC_TXLINK_ADDR + 0 + 20 + read-write + + + + + SLC_INTVEC_TOHOST + 0x2c + SLC_INTVEC_TOHOST + 32 + 0x00000000 + + + SLC_TOHOST_INTVEC + 0 + 8 + read-write + + + + + SLC_TOKEN0 + 0x30 + SLC_TOKEN0 + 32 + 0x00000000 + + + SLC_TOKEN0 + 16 + 12 + read-write + + + SLC_TOKEN0_LOCAL_INC_MORE + 14 + 1 + read-write + + + SLC_TOKEN0_LOCAL_INC + 13 + 1 + read-write + + + SLC_TOKEN0_LOCAL_WR + 12 + 1 + read-write + + + SLC_TOKEN0_LOCAL_WDATA + 0 + 12 + read-write + + + + + SLC_TOKEN1 + 0x34 + SLC_TOKEN1 + 32 + 0x00000000 + + + SLC_TOKEN1 + 16 + 12 + read-write + + + SLC_TOKEN1_LOCAL_INC_MORE + 14 + 1 + read-write + + + SLC_TOKEN1_LOCAL_INC + 13 + 1 + read-write + + + SLC_TOKEN1_LOCAL_WR + 12 + 1 + read-write + + + SLC_TOKEN1_LOCAL_WDATA + 0 + 12 + read-write + + + + + SLC_CONF1 + 0x38 + SLC_CONF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_STATE0 + 0x3c + SLC_STATE0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_STATE1 + 0x40 + SLC_STATE1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_BRIDGE_CONF + 0x44 + SLC_BRIDGE_CONF + 32 + 0x00000000 + + + SLC_TX_PUSH_IDLE_NUM + 16 + 16 + read-write + + + SLC_TX_DUMMY_MODE + 12 + 1 + read-write + + + SLC_FIFO_MAP_ENA + 8 + 4 + read-write + + + SLC_TXEOF_ENA + 0 + 6 + read-write + + + + + SLC_RX_EOF_DES_ADDR + 0x48 + SLC_RX_EOF_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TX_EOF_DES_ADDR + 0x4c + SLC_TX_EOF_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RX_EOF_BFR_DES_ADDR + 0x50 + SLC_RX_EOF_BFR_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_AHB_TEST + 0x54 + SLC_AHB_TEST + 32 + 0x00000000 + + + SLC_AHB_TESTADDR + 4 + 2 + read-write + + + SLC_AHB_TESTMODE + 0 + 3 + read-write + + + + + SLC_SDIO_ST + 0x58 + SLC_SDIO_ST + 32 + 0x00000000 + + + SLC_BUS_ST + 12 + 3 + read-write + + + SLC_SDIO_WAKEUP + 8 + 1 + read-write + + + SLC_FUNC_ST + 4 + 4 + read-write + + + SLC_CMD_ST + 0 + 3 + read-write + + + + + SLC_RX_DSCR_CONF + 0x5c + SLC_RX_DSCR_CONF + 32 + 0x00000000 + + + SLC_INFOR_NO_REPLACE + 9 + 1 + read-write + + + SLC_TOKEN_NO_REPLACE + 8 + 1 + read-write + + + + + SLC_TXLINK_DSCR + 0x60 + SLC_TXLINK_DSCR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TXLINK_DSCR_BF0 + 0x64 + SLC_TXLINK_DSCR_BF0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TXLINK_DSCR_BF1 + 0x68 + SLC_TXLINK_DSCR_BF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR + 0x6c + SLC_RXLINK_DSCR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR_BF0 + 0x70 + SLC_RXLINK_DSCR_BF0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR_BF1 + 0x74 + SLC_RXLINK_DSCR_BF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_DATE + 0x78 + SLC_DATE + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_ID + 0x7c + SLC_ID + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + SPI0 + 0x60000200 + + 0 + 0x00000400 + registers + + + + SPI_CMD + 0x0 + In the master mode, it is the start bit of a single operation. Self-clear by hardware + 32 + 0x00000000 + + + spi_usr + In the master mode, it is the start bit of a single operation. Self-clear by hardware + 18 + 1 + read-write + + + + + SPI_ADDR + 0x4 + In the master mode, it is the value of address in "address" phase. + 32 + 0x00000000 + + + iodata_start_addr + In the master mode, it is the value of address in "address" phase. + 0 + 32 + read-write + + + + + SPI_CTRL + 0x8 + SPI_CTRL + 32 + 0x00000000 + + + spi_wr_bit_order + In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first + 26 + 1 + read-write + + + spi_rd_bit_order + In "read-data" (MISO) phase, 1: LSB first; 0: MSB first + 25 + 1 + read-write + + + spi_qio_mode + In the read operations, "address" phase and "read-data" phase apply 4 signals + 24 + 1 + read-write + + + spi_dio_mode + In the read operations, "address" phase and "read-data" phase apply 2 signals + 23 + 1 + read-write + + + spi_qout_mode + In the read operations, "read-data" phase apply 4 signals + 20 + 1 + read-write + + + spi_dout_mode + In the read operations, "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fastrd_mode + this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode + 13 + 1 + read-write + + + + + SPI_RD_STATUS + 0x10 + In the slave mode, this register are the status register for the master to read out. + 32 + 0x00000000 + + + slv_rd_status + In the slave mode, this register are the status register for the master to read out. + 0 + 32 + read-write + + + + + SPI_CTRL2 + 0x14 + spi_cs signal is delayed by 80MHz clock cycles + 32 + 0x00000000 + + + spi_cs_delay_num + spi_cs signal is delayed by 80MHz clock cycles + 28 + 4 + read-write + + + spi_cs_delay_mode + spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 26 + 2 + read-write + + + spi_mosi_delay_num + MOSI signals are delayed by 80MHz clock cycles + 23 + 3 + read-write + + + spi_mosi_delay_mode + MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 21 + 2 + read-write + + + spi_miso_delay_num + MISO signals are delayed by 80MHz clock cycles + 18 + 3 + read-write + + + spi_miso_delay_mode + MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 16 + 2 + read-write + + + + + SPI_CLOCK + 0x18 + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + 32 + 0x00000000 + + + spi_clk_equ_sysclk + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + 31 + 1 + read-write + + + spi_clkdiv_pre + In the master mode, it is pre-divider of spi_clk. + 18 + 13 + read-write + + + spi_clkcnt_N + In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + 12 + 6 + read-write + + + spi_clkcnt_H + In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0. + 6 + 6 + read-write + + + spi_clkcnt_L + In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0. + 0 + 6 + read-write + + + + + SPI_USER + 0x1c + This bit enable the "command" phase of an operation. + 32 + 0x00000000 + + + spi_usr_command + This bit enable the "command" phase of an operation. + 31 + 1 + read-write + + + spi_usr_addr + This bit enable the "address" phase of an operation. + 30 + 1 + read-write + + + spi_usr_dummy + This bit enable the "dummy" phase of an operation. + 29 + 1 + read-write + + + spi_usr_miso + This bit enable the "read-data" phase of an operation. + 28 + 1 + read-write + + + spi_usr_mosi + This bit enable the "write-data" phase of an operation. + 27 + 1 + read-write + + + reg_usr_mosi_highpart + 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 + 25 + 1 + read-write + + + reg_usr_miso_highpart + 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 + 24 + 1 + read-write + + + spi_sio + 1: mosi and miso signals share the same pin + 16 + 1 + read-write + + + spi_fwrite_qio + In the write operations, "address" phase and "read-data" phase apply 4 signals + 15 + 1 + read-write + + + spi_fwrite_dio + In the write operations, "address" phase and "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fwrite_quad + In the write operations, "read-data" phase apply 4 signals + 13 + 1 + read-write + + + spi_fwrite_dual + In the write operations, "read-data" phase apply 2 signals + 12 + 1 + read-write + + + spi_wr_byte_order + In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian + 11 + 1 + read-write + + + spi_rd_byte_order + In "read-data" (MISO) phase, 1: little-endian; 0: big_endian + 10 + 1 + read-write + + + spi_ck_i_edge + In the slave mode, 1: rising-edge; 0: falling-edge + 6 + 1 + read-write + + + + + SPI_USER1 + 0x20 + The length in bits of "address" phase. The register value shall be (bit_num-1) + 32 + 0x00000000 + + + reg_usr_addr_bitlen + The length in bits of "address" phase. The register value shall be (bit_num-1) + 26 + 6 + read-write + + + reg_usr_mosi_bitlen + The length in bits of "write-data" phase. The register value shall be (bit_num-1) + 17 + 9 + read-write + + + reg_usr_miso_bitlen + The length in bits of "read-data" phase. The register value shall be (bit_num-1) + 8 + 9 + read-write + + + reg_usr_dummy_cyclelen + The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1) + 0 + 8 + read-write + + + + + SPI_USER2 + 0x24 + The length in bits of "command" phase. The register value shall be (bit_num-1) + 32 + 0x00000000 + + + reg_usr_command_bitlen + The length in bits of "command" phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + reg_usr_command_value + The value of "command" phase + 0 + 16 + read-write + + + + + SPI_WR_STATUS + 0x28 + In the slave mode, this register are the status register for the master to write into. + 32 + 0x00000000 + + + slv_wr_status + In the slave mode, this register are the status register for the master to write into. + 0 + 32 + read-write + + + + + SPI_PIN + 0x2c + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 32 + 0x00000000 + + + spi_cs2_dis + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 2 + 1 + read-write + + + spi_cs1_dis + 1: disable CS1; 0: spi_cs signal is from/to CS1 pin + 1 + 1 + read-write + + + spi_cs0_dis + 1: disable CS0; 0: spi_cs signal is from/to CS0 pin + 0 + 1 + read-write + + + + + SPI_SLAVE + 0x30 + It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + 32 + 0x00000000 + + + spi_sync_reset + It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + 31 + 1 + read-write + + + spi_slave_mode + 1: slave mode, 0: master mode. + 30 + 1 + read-write + + + slv_cmd_define + 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". + 27 + 1 + read-write + + + spi_trans_cnt + The operations counter in both the master mode and the slave mode. + 23 + 4 + read-only + + + spi_int_en + Interrupt enable bits for the below 5 sources + 5 + 5 + read-write + + + spi_trans_done + The interrupt raw bit for the completement of any operation in both the master mode and the slave mode. + 4 + 1 + read-write + + + slv_wr_sta_done + The interrupt raw bit for the completement of "write-status" operation in the slave mode. + 3 + 1 + read-write + + + slv_rd_sta_done + The interrupt raw bit for the completement of "read-status" operation in the slave mode. + 2 + 1 + read-write + + + slv_wr_buf_done + The interrupt raw bit for the completement of "write-buffer" operation in the slave mode. + 1 + 1 + read-write + + + slv_rd_buf_done + The interrupt raw bit for the completement of "read-buffer" operation in the slave mode. + 0 + 1 + read-write + + + + + SPI_SLAVE1 + 0x34 + In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + 32 + 0x00000000 + + + slv_status_bitlen + In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + 27 + 5 + read-write + + + slv_buf_bitlen + In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1) + 16 + 9 + read-write + + + slv_rd_addr_bitlen + In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1) + 10 + 6 + read-write + + + slv_wr_addr_bitlen + In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1) + 4 + 6 + read-write + + + slv_wrsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations. + 3 + 1 + read-write + + + slv_rdsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations. + 2 + 1 + read-write + + + slv_wrbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations. + 1 + 1 + read-write + + + slv_rdbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations. + 0 + 1 + read-write + + + + + SPI_SLAVE2 + 0x38 + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + 32 + 0x00000000 + + + slv_wrbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + 24 + 8 + read-write + + + slv_rdbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1) + 16 + 8 + read-write + + + slv_wrsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1) + 8 + 8 + read-write + + + slv_rdsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1) + 0 + 8 + read-write + + + + + SPI_SLAVE3 + 0x3c + In slave mode, it is the value of "write-status" command + 32 + 0x00000000 + + + slv_wrsta_cmd_value + In slave mode, it is the value of "write-status" command + 24 + 8 + read-write + + + slv_rdsta_cmd_value + In slave mode, it is the value of "read-status" command + 16 + 8 + read-write + + + slv_wrbuf_cmd_value + In slave mode, it is the value of "write-buffer" command + 8 + 8 + read-write + + + slv_rdbuf_cmd_value + In slave mode, it is the value of "read-buffer" command + 0 + 8 + read-write + + + + + SPI_EXT3 + 0xfc + This register is for two SPI masters to share the same cs, clock and data signals. + 32 + 0x00000000 + + + reg_int_hold_ena + This register is for two SPI masters to share the same cs, clock and data signals. + 0 + 2 + read-write + + + + + SPI_W0 + 0x40 + the data inside the buffer of the SPI module, word 0 + 32 + 0x00000000 + + + spi_w0 + the data inside the buffer of the SPI module, word 0 + 0 + 32 + read-write + + + + + SPI_W1 + 0x44 + the data inside the buffer of the SPI module, word 1 + 32 + 0x00000000 + + + spi_w1 + the data inside the buffer of the SPI module, word 1 + 0 + 32 + read-write + + + + + SPI_W2 + 0x48 + the data inside the buffer of the SPI module, word 2 + 32 + 0x00000000 + + + spi_w2 + the data inside the buffer of the SPI module, word 2 + 0 + 32 + read-write + + + + + SPI_W3 + 0x4c + the data inside the buffer of the SPI module, word 3 + 32 + 0x00000000 + + + spi_w3 + the data inside the buffer of the SPI module, word 3 + 0 + 32 + read-write + + + + + SPI_W4 + 0x50 + the data inside the buffer of the SPI module, word 4 + 32 + 0x00000000 + + + spi_w4 + the data inside the buffer of the SPI module, word 4 + 0 + 32 + read-write + + + + + SPI_W5 + 0x54 + the data inside the buffer of the SPI module, word 5 + 32 + 0x00000000 + + + spi_w5 + the data inside the buffer of the SPI module, word 5 + 0 + 32 + read-write + + + + + SPI_W6 + 0x58 + the data inside the buffer of the SPI module, word 6 + 32 + 0x00000000 + + + spi_w6 + the data inside the buffer of the SPI module, word 6 + 0 + 32 + read-write + + + + + SPI_W7 + 0x5c + the data inside the buffer of the SPI module, word 7 + 32 + 0x00000000 + + + spi_w7 + the data inside the buffer of the SPI module, word 7 + 0 + 32 + read-write + + + + + SPI_W8 + 0x60 + the data inside the buffer of the SPI module, word 8 + 32 + 0x00000000 + + + spi_w8 + the data inside the buffer of the SPI module, word 8 + 0 + 32 + read-write + + + + + SPI_W9 + 0x64 + the data inside the buffer of the SPI module, word 9 + 32 + 0x00000000 + + + spi_w9 + the data inside the buffer of the SPI module, word 9 + 0 + 32 + read-write + + + + + SPI_W10 + 0x68 + the data inside the buffer of the SPI module, word 10 + 32 + 0x00000000 + + + spi_w10 + the data inside the buffer of the SPI module, word 10 + 0 + 32 + read-write + + + + + SPI_W11 + 0x6c + the data inside the buffer of the SPI module, word 11 + 32 + 0x00000000 + + + spi_w11 + the data inside the buffer of the SPI module, word 11 + 0 + 32 + read-write + + + + + SPI_W12 + 0x70 + the data inside the buffer of the SPI module, word 12 + 32 + 0x00000000 + + + spi_w12 + the data inside the buffer of the SPI module, word 12 + 0 + 32 + read-write + + + + + SPI_W13 + 0x74 + the data inside the buffer of the SPI module, word 13 + 32 + 0x00000000 + + + spi_w13 + the data inside the buffer of the SPI module, word 13 + 0 + 32 + read-write + + + + + SPI_W14 + 0x78 + the data inside the buffer of the SPI module, word 14 + 32 + 0x00000000 + + + spi_w14 + the data inside the buffer of the SPI module, word 14 + 0 + 32 + read-write + + + + + SPI_W15 + 0x7c + the data inside the buffer of the SPI module, word 15 + 32 + 0x00000000 + + + spi_w15 + the data inside the buffer of the SPI module, word 15 + 0 + 32 + read-write + + + + + + + SPI1 + 0x60000100 + + 0 + 0x00000400 + registers + + + + SPI_CMD + 0x0 + In the master mode, it is the start bit of a single operation. Self-clear by hardware + 32 + 0x00000000 + + + spi_usr + In the master mode, it is the start bit of a single operation. Self-clear by hardware + 18 + 1 + read-write + + + + + SPI_ADDR + 0x4 + In the master mode, it is the value of address in "address" phase. + 32 + 0x00000000 + + + iodata_start_addr + In the master mode, it is the value of address in "address" phase. + 0 + 32 + read-write + + + + + SPI_CTRL + 0x8 + SPI_CTRL + 32 + 0x00000000 + + + spi_wr_bit_order + In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first + 26 + 1 + read-write + + + spi_rd_bit_order + In "read-data" (MISO) phase, 1: LSB first; 0: MSB first + 25 + 1 + read-write + + + spi_qio_mode + In the read operations, "address" phase and "read-data" phase apply 4 signals + 24 + 1 + read-write + + + spi_dio_mode + In the read operations, "address" phase and "read-data" phase apply 2 signals + 23 + 1 + read-write + + + spi_qout_mode + In the read operations, "read-data" phase apply 4 signals + 20 + 1 + read-write + + + spi_dout_mode + In the read operations, "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fastrd_mode + this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode + 13 + 1 + read-write + + + + + SPI_RD_STATUS + 0x10 + In the slave mode, this register are the status register for the master to read out. + 32 + 0x00000000 + + + slv_rd_status + In the slave mode, this register are the status register for the master to read out. + 0 + 32 + read-write + + + + + SPI_CTRL2 + 0x14 + spi_cs signal is delayed by 80MHz clock cycles + 32 + 0x00000000 + + + spi_cs_delay_num + spi_cs signal is delayed by 80MHz clock cycles + 28 + 4 + read-write + + + spi_cs_delay_mode + spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 26 + 2 + read-write + + + spi_mosi_delay_num + MOSI signals are delayed by 80MHz clock cycles + 23 + 3 + read-write + + + spi_mosi_delay_mode + MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 21 + 2 + read-write + + + spi_miso_delay_num + MISO signals are delayed by 80MHz clock cycles + 18 + 3 + read-write + + + spi_miso_delay_mode + MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + 16 + 2 + read-write + + + + + SPI_CLOCK + 0x18 + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + 32 + 0x00000000 + + + spi_clk_equ_sysclk + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock. + 31 + 1 + read-write + + + spi_clkdiv_pre + In the master mode, it is pre-divider of spi_clk. + 18 + 13 + read-write + + + spi_clkcnt_N + In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + 12 + 6 + read-write + + + spi_clkcnt_H + In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0. + 6 + 6 + read-write + + + spi_clkcnt_L + In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0. + 0 + 6 + read-write + + + + + SPI_USER + 0x1c + This bit enable the "command" phase of an operation. + 32 + 0x00000000 + + + spi_usr_command + This bit enable the "command" phase of an operation. + 31 + 1 + read-write + + + spi_usr_addr + This bit enable the "address" phase of an operation. + 30 + 1 + read-write + + + spi_usr_dummy + This bit enable the "dummy" phase of an operation. + 29 + 1 + read-write + + + spi_usr_miso + This bit enable the "read-data" phase of an operation. + 28 + 1 + read-write + + + spi_usr_mosi + This bit enable the "write-data" phase of an operation. + 27 + 1 + read-write + + + reg_usr_mosi_highpart + 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 + 25 + 1 + read-write + + + reg_usr_miso_highpart + 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 + 24 + 1 + read-write + + + spi_sio + 1: mosi and miso signals share the same pin + 16 + 1 + read-write + + + spi_fwrite_qio + In the write operations, "address" phase and "read-data" phase apply 4 signals + 15 + 1 + read-write + + + spi_fwrite_dio + In the write operations, "address" phase and "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fwrite_quad + In the write operations, "read-data" phase apply 4 signals + 13 + 1 + read-write + + + spi_fwrite_dual + In the write operations, "read-data" phase apply 2 signals + 12 + 1 + read-write + + + spi_wr_byte_order + In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian + 11 + 1 + read-write + + + spi_rd_byte_order + In "read-data" (MISO) phase, 1: little-endian; 0: big_endian + 10 + 1 + read-write + + + spi_ck_i_edge + In the slave mode, 1: rising-edge; 0: falling-edge + 6 + 1 + read-write + + + + + SPI_USER1 + 0x20 + The length in bits of "address" phase. The register value shall be (bit_num-1) + 32 + 0x00000000 + + + reg_usr_addr_bitlen + The length in bits of "address" phase. The register value shall be (bit_num-1) + 26 + 6 + read-write + + + reg_usr_mosi_bitlen + The length in bits of "write-data" phase. The register value shall be (bit_num-1) + 17 + 9 + read-write + + + reg_usr_miso_bitlen + The length in bits of "read-data" phase. The register value shall be (bit_num-1) + 8 + 9 + read-write + + + reg_usr_dummy_cyclelen + The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1) + 0 + 8 + read-write + + + + + SPI_USER2 + 0x24 + The length in bits of "command" phase. The register value shall be (bit_num-1) + 32 + 0x00000000 + + + reg_usr_command_bitlen + The length in bits of "command" phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + reg_usr_command_value + The value of "command" phase + 0 + 16 + read-write + + + + + SPI_WR_STATUS + 0x28 + In the slave mode, this register are the status register for the master to write into. + 32 + 0x00000000 + + + slv_wr_status + In the slave mode, this register are the status register for the master to write into. + 0 + 32 + read-write + + + + + SPI_PIN + 0x2c + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 32 + 0x00000000 + + + spi_cs2_dis + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 2 + 1 + read-write + + + spi_cs1_dis + 1: disable CS1; 0: spi_cs signal is from/to CS1 pin + 1 + 1 + read-write + + + spi_cs0_dis + 1: disable CS0; 0: spi_cs signal is from/to CS0 pin + 0 + 1 + read-write + + + + + SPI_SLAVE + 0x30 + It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + 32 + 0x00000000 + + + spi_sync_reset + It is the synchronous reset signal of the module. This bit is self-cleared by hardware. + 31 + 1 + read-write + + + spi_slave_mode + 1: slave mode, 0: master mode. + 30 + 1 + read-write + + + slv_cmd_define + 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". + 27 + 1 + read-write + + + spi_trans_cnt + The operations counter in both the master mode and the slave mode. + 23 + 4 + read-only + + + spi_int_en + Interrupt enable bits for the below 5 sources + 5 + 5 + read-write + + + spi_trans_done + The interrupt raw bit for the completement of any operation in both the master mode and the slave mode. + 4 + 1 + read-write + + + slv_wr_sta_done + The interrupt raw bit for the completement of "write-status" operation in the slave mode. + 3 + 1 + read-write + + + slv_rd_sta_done + The interrupt raw bit for the completement of "read-status" operation in the slave mode. + 2 + 1 + read-write + + + slv_wr_buf_done + The interrupt raw bit for the completement of "write-buffer" operation in the slave mode. + 1 + 1 + read-write + + + slv_rd_buf_done + The interrupt raw bit for the completement of "read-buffer" operation in the slave mode. + 0 + 1 + read-write + + + + + SPI_SLAVE1 + 0x34 + In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + 32 + 0x00000000 + + + slv_status_bitlen + In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1) + 27 + 5 + read-write + + + slv_buf_bitlen + In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1) + 16 + 9 + read-write + + + slv_rd_addr_bitlen + In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1) + 10 + 6 + read-write + + + slv_wr_addr_bitlen + In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1) + 4 + 6 + read-write + + + slv_wrsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations. + 3 + 1 + read-write + + + slv_rdsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations. + 2 + 1 + read-write + + + slv_wrbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations. + 1 + 1 + read-write + + + slv_rdbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations. + 0 + 1 + read-write + + + + + SPI_SLAVE2 + 0x38 + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + 32 + 0x00000000 + + + slv_wrbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1) + 24 + 8 + read-write + + + slv_rdbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1) + 16 + 8 + read-write + + + slv_wrsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1) + 8 + 8 + read-write + + + slv_rdsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1) + 0 + 8 + read-write + + + + + SPI_SLAVE3 + 0x3c + In slave mode, it is the value of "write-status" command + 32 + 0x00000000 + + + slv_wrsta_cmd_value + In slave mode, it is the value of "write-status" command + 24 + 8 + read-write + + + slv_rdsta_cmd_value + In slave mode, it is the value of "read-status" command + 16 + 8 + read-write + + + slv_wrbuf_cmd_value + In slave mode, it is the value of "write-buffer" command + 8 + 8 + read-write + + + slv_rdbuf_cmd_value + In slave mode, it is the value of "read-buffer" command + 0 + 8 + read-write + + + + + SPI_EXT3 + 0xfc + This register is for two SPI masters to share the same cs, clock and data signals. + 32 + 0x00000000 + + + reg_int_hold_ena + This register is for two SPI masters to share the same cs, clock and data signals. + 0 + 2 + read-write + + + + + SPI_W0 + 0x40 + the data inside the buffer of the SPI module, word 0 + 32 + 0x00000000 + + + spi_w0 + the data inside the buffer of the SPI module, word 0 + 0 + 32 + read-write + + + + + SPI_W1 + 0x44 + the data inside the buffer of the SPI module, word 1 + 32 + 0x00000000 + + + spi_w1 + the data inside the buffer of the SPI module, word 1 + 0 + 32 + read-write + + + + + SPI_W2 + 0x48 + the data inside the buffer of the SPI module, word 2 + 32 + 0x00000000 + + + spi_w2 + the data inside the buffer of the SPI module, word 2 + 0 + 32 + read-write + + + + + SPI_W3 + 0x4c + the data inside the buffer of the SPI module, word 3 + 32 + 0x00000000 + + + spi_w3 + the data inside the buffer of the SPI module, word 3 + 0 + 32 + read-write + + + + + SPI_W4 + 0x50 + the data inside the buffer of the SPI module, word 4 + 32 + 0x00000000 + + + spi_w4 + the data inside the buffer of the SPI module, word 4 + 0 + 32 + read-write + + + + + SPI_W5 + 0x54 + the data inside the buffer of the SPI module, word 5 + 32 + 0x00000000 + + + spi_w5 + the data inside the buffer of the SPI module, word 5 + 0 + 32 + read-write + + + + + SPI_W6 + 0x58 + the data inside the buffer of the SPI module, word 6 + 32 + 0x00000000 + + + spi_w6 + the data inside the buffer of the SPI module, word 6 + 0 + 32 + read-write + + + + + SPI_W7 + 0x5c + the data inside the buffer of the SPI module, word 7 + 32 + 0x00000000 + + + spi_w7 + the data inside the buffer of the SPI module, word 7 + 0 + 32 + read-write + + + + + SPI_W8 + 0x60 + the data inside the buffer of the SPI module, word 8 + 32 + 0x00000000 + + + spi_w8 + the data inside the buffer of the SPI module, word 8 + 0 + 32 + read-write + + + + + SPI_W9 + 0x64 + the data inside the buffer of the SPI module, word 9 + 32 + 0x00000000 + + + spi_w9 + the data inside the buffer of the SPI module, word 9 + 0 + 32 + read-write + + + + + SPI_W10 + 0x68 + the data inside the buffer of the SPI module, word 10 + 32 + 0x00000000 + + + spi_w10 + the data inside the buffer of the SPI module, word 10 + 0 + 32 + read-write + + + + + SPI_W11 + 0x6c + the data inside the buffer of the SPI module, word 11 + 32 + 0x00000000 + + + spi_w11 + the data inside the buffer of the SPI module, word 11 + 0 + 32 + read-write + + + + + SPI_W12 + 0x70 + the data inside the buffer of the SPI module, word 12 + 32 + 0x00000000 + + + spi_w12 + the data inside the buffer of the SPI module, word 12 + 0 + 32 + read-write + + + + + SPI_W13 + 0x74 + the data inside the buffer of the SPI module, word 13 + 32 + 0x00000000 + + + spi_w13 + the data inside the buffer of the SPI module, word 13 + 0 + 32 + read-write + + + + + SPI_W14 + 0x78 + the data inside the buffer of the SPI module, word 14 + 32 + 0x00000000 + + + spi_w14 + the data inside the buffer of the SPI module, word 14 + 0 + 32 + read-write + + + + + SPI_W15 + 0x7c + the data inside the buffer of the SPI module, word 15 + 32 + 0x00000000 + + + spi_w15 + the data inside the buffer of the SPI module, word 15 + 0 + 32 + read-write + + + + + + + TIMER + 0x60000600 + + 0 + 0x00000120 + registers + + + + FRC1_LOAD + 0x0 + the load value into the counter + 32 + 0x00000000 + + + frc1_load_value + the load value into the counter + 0 + 23 + read-write + + + + + FRC1_COUNT + 0x4 + the current value of the counter. It is a decreasingcounter. + 32 + 0x00000000 + + + frc1_count + the current value of the counter. It is a decreasingcounter. + 0 + 23 + read-only + + + + + FRC1_CTRL + 0x8 + FRC1_CTRL + 32 + 0x00000000 + + + frc1_int + the status of the interrupt, when the count isdereased to zero + 8 + 1 + read-only + + + frc1_ctrl + bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level + 0 + 8 + read-write + + + + + FRC1_INT + 0xc + FRC1_INT + 32 + 0x00000000 + + + frc1_int_clr_mask + write to clear the status of the interrupt, if theinterrupt type is "level" + 0 + 1 + read-write + + + + + FRC2_LOAD + 0x20 + the load value into the counter + 32 + 0x00000000 + + + frc2_load_value + the load value into the counter + 0 + 32 + read-write + + + + + FRC2_COUNT + 0x24 + the current value of the counter. It is a increasingcounter. + 32 + 0x00000000 + + + frc2_count + the current value of the counter. It is a increasingcounter. + 0 + 32 + read-only + + + + + FRC2_CTRL + 0x28 + FRC2_CTRL + 32 + 0x00000000 + + + frc2_int + the status of the interrupt, when the count is equal tothe alarm value + 8 + 1 + read-only + + + frc2_ctrl + bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level + 0 + 8 + read-write + + + + + FRC2_INT + 0x2c + FRC2_INT + 32 + 0x00000000 + + + frc2_int_clr_mask + write to clear the status of the interrupt, if theinterrupt type is "level" + 0 + 1 + read-write + + + + + FRC2_ALARM + 0x30 + the alarm value for the counter + 32 + 0x00000000 + + + frc2_alarm + the alarm value for the counter + 0 + 32 + read-write + + + + + + + UART0 + 0x60000000 + + 0 + 0x000001e0 + registers + + + + UART_FIFO + 0x0 + UART FIFO,length 128 + 32 + 0x00000000 + + + rxfifo_rd_byte + R/W share the same address + 0 + 8 + read-only + + + + + UART_INT_RAW + 0x4 + UART INTERRUPT RAW STATE + 32 + 0x00000000 + + + rxfifo_tout_int_raw + The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD) + 8 + 1 + read-only + + + brk_det_int_raw + The interrupt raw bit for Rx byte start error + 7 + 1 + read-only + + + cts_chg_int_raw + The interrupt raw bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_raw + The interrupt raw bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_raw + The interrupt raw bit for rx fifo overflow + 4 + 1 + read-only + + + frm_err_int_raw + The interrupt raw bit for other rx error + 3 + 1 + read-only + + + parity_err_int_raw + The interrupt raw bit for parity check error + 2 + 1 + read-only + + + txfifo_empty_int_raw + The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits) + 1 + 1 + read-only + + + rxfifo_full_int_raw + The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits) + 0 + 1 + read-only + + + + + UART_INT_ST + 0x8 + UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + 32 + 0x00000000 + + + rxfifo_tout_int_st + The interrupt state bit for Rx time-out event + 8 + 1 + read-only + + + brk_det_int_st + The interrupt state bit for rx byte start error + 7 + 1 + read-only + + + cts_chg_int_st + The interrupt state bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_st + The interrupt state bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_st + The interrupt state bit for RX fifo overflow + 4 + 1 + read-only + + + frm_err_int_st + The interrupt state for other rx error + 3 + 1 + read-only + + + parity_err_int_st + The interrupt state bit for rx parity error + 2 + 1 + read-only + + + txfifo_empty_int_st + The interrupt state bit for TX fifo empty + 1 + 1 + read-only + + + rxfifo_full_int_st + The interrupt state bit for RX fifo full event + 0 + 1 + read-only + + + + + UART_INT_ENA + 0xc + UART INTERRUPT ENABLE REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_ena + The interrupt enable bit for rx time-out interrupt + 8 + 1 + read-write + + + brk_det_int_ena + The interrupt enable bit for rx byte start error + 7 + 1 + read-write + + + cts_chg_int_ena + The interrupt enable bit for CTS changing level + 6 + 1 + read-write + + + dsr_chg_int_ena + The interrupt enable bit for DSR changing level + 5 + 1 + read-write + + + rxfifo_ovf_int_ena + The interrupt enable bit for rx fifo overflow + 4 + 1 + read-write + + + frm_err_int_ena + The interrupt enable bit for other rx error + 3 + 1 + read-write + + + parity_err_int_ena + The interrupt enable bit for parity error + 2 + 1 + read-write + + + txfifo_empty_int_ena + The interrupt enable bit for tx fifo empty event + 1 + 1 + read-write + + + rxfifo_full_int_ena + The interrupt enable bit for rx fifo full event + 0 + 1 + read-write + + + + + UART_INT_CLR + 0x10 + UART INTERRUPT CLEAR REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_clr + Set this bit to clear the rx time-out interrupt + 8 + 1 + write-only + + + brk_det_int_clr + Set this bit to clear the rx byte start interrupt + 7 + 1 + write-only + + + cts_chg_int_clr + Set this bit to clear the CTS changing interrupt + 6 + 1 + write-only + + + dsr_chg_int_clr + Set this bit to clear the DSR changing interrupt + 5 + 1 + write-only + + + rxfifo_ovf_int_clr + Set this bit to clear the rx fifo over-flow interrupt + 4 + 1 + write-only + + + frm_err_int_clr + Set this bit to clear other rx error interrupt + 3 + 1 + write-only + + + parity_err_int_clr + Set this bit to clear the parity error interrupt + 2 + 1 + write-only + + + txfifo_empty_int_clr + Set this bit to clear the tx fifo empty interrupt + 1 + 1 + write-only + + + rxfifo_full_int_clr + Set this bit to clear the rx fifo full interrupt + 0 + 1 + write-only + + + + + UART_CLKDIV + 0x14 + UART CLK DIV REGISTER + 32 + 0x00000000 + + + uart_clkdiv + BAUDRATE = UART_CLK_FREQ / UART_CLKDIV + 0 + 20 + read-write + + + + + UART_AUTOBAUD + 0x18 + UART BAUDRATE DETECT REGISTER + 32 + 0x00000000 + + + glitch_filt + 8 + 8 + read-write + + + autobaud_en + Set this bit to enable baudrate detect + 0 + 1 + read-write + + + + + UART_STATUS + 0x1c + UART STATUS REGISTER + 32 + 0x00000000 + + + txd + The level of the uart txd pin + 31 + 1 + read-only + + + rtsn + The level of uart rts pin + 30 + 1 + read-only + + + dtrn + The level of uart dtr pin + 29 + 1 + read-only + + + txfifo_cnt + Number of data in UART TX fifo + 16 + 8 + read-only + + + rxd + The level of uart rxd pin + 15 + 1 + read-only + + + ctsn + The level of uart cts pin + 14 + 1 + read-only + + + dsrn + The level of uart dsr pin + 13 + 1 + read-only + + + rxfifo_cnt + Number of data in uart rx fifo + 0 + 8 + read-only + + + + + UART_CONF0 + 0x20 + UART CONFIG0(UART0 and UART1) + 32 + 0x00000000 + + + uart_dtr_inv + Set this bit to inverse uart dtr level + 24 + 1 + read-write + + + uart_rts_inv + Set this bit to inverse uart rts level + 23 + 1 + read-write + + + uart_txd_inv + Set this bit to inverse uart txd level + 22 + 1 + read-write + + + uart_dsr_inv + Set this bit to inverse uart dsr level + 21 + 1 + read-write + + + uart_cts_inv + Set this bit to inverse uart cts level + 20 + 1 + read-write + + + uart_rxd_inv + Set this bit to inverse uart rxd level + 19 + 1 + read-write + + + txfifo_rst + Set this bit to reset uart tx fifo + 18 + 1 + read-write + + + rxfifo_rst + Set this bit to reset uart rx fifo + 17 + 1 + read-write + + + tx_flow_en + Set this bit to enable uart tx hardware flow control + 15 + 1 + read-write + + + uart_loopback + Set this bit to enable uart loopback test mode + 14 + 1 + read-write + + + txd_brk + RESERVED, DO NOT CHANGE THIS BIT + 8 + 1 + read-write + + + sw_dtr + sw dtr + 7 + 1 + read-write + + + sw_rts + sw rts + 6 + 1 + read-write + + + stop_bit_num + Set stop bit: 1:1bit 2:1.5bits 3:2bits + 4 + 2 + read-write + + + bit_num + Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits + 2 + 2 + read-write + + + parity_en + Set this bit to enable uart parity check + 1 + 1 + read-write + + + parity + Set parity check: 0:even 1:odd, UART CONFIG1 + 0 + 1 + read-write + + + + + UART_CONF1 + 0x24 + Set this bit to enable rx time-out function + 32 + 0x00000000 + + + rx_tout_en + Set this bit to enable rx time-out function + 31 + 1 + read-write + + + rx_tout_thrhd + Config bits for rx time-out threshold,uint: byte,0-127 + 24 + 7 + read-write + + + rx_flow_en + Set this bit to enable rx hardware flow control + 23 + 1 + read-write + + + rx_flow_thrhd + The config bits for rx flow control threshold,0-127 + 16 + 7 + read-write + + + txfifo_empty_thrhd + The config bits for tx fifo empty threshold,0-127 + 8 + 7 + read-write + + + rxfifo_full_thrhd + The config bits for rx fifo full threshold,0-127 + 0 + 7 + read-write + + + + + UART_LOWPULSE + 0x28 + UART_LOWPULSE + 32 + 0x00000000 + + + lowpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_HIGHPULSE + 0x2c + UART_HIGHPULSE + 32 + 0x00000000 + + + highpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_RXD_CNT + 0x30 + UART_RXD_CNT + 32 + 0x00000000 + + + rxd_edge_cnt + used in baudrate detect + 0 + 10 + read-only + + + + + UART_DATE + 0x78 + UART HW INFO + 32 + 0x00000000 + + + uart_date + UART HW INFO + 0 + 32 + read-write + + + + + UART_ID + 0x7c + UART_ID + 32 + 0x00000000 + + + uart_id + 0 + 32 + read-write + + + + + + + UART1 + 0x60000f00 + + 0 + 0x000001e0 + registers + + + + UART_FIFO + 0x0 + UART FIFO,length 128 + 32 + 0x00000000 + + + rxfifo_rd_byte + R/W share the same address + 0 + 8 + read-only + + + + + UART_INT_RAW + 0x4 + UART INTERRUPT RAW STATE + 32 + 0x00000000 + + + rxfifo_tout_int_raw + The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD) + 8 + 1 + read-only + + + brk_det_int_raw + The interrupt raw bit for Rx byte start error + 7 + 1 + read-only + + + cts_chg_int_raw + The interrupt raw bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_raw + The interrupt raw bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_raw + The interrupt raw bit for rx fifo overflow + 4 + 1 + read-only + + + frm_err_int_raw + The interrupt raw bit for other rx error + 3 + 1 + read-only + + + parity_err_int_raw + The interrupt raw bit for parity check error + 2 + 1 + read-only + + + txfifo_empty_int_raw + The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits) + 1 + 1 + read-only + + + rxfifo_full_int_raw + The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits) + 0 + 1 + read-only + + + + + UART_INT_ST + 0x8 + UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + 32 + 0x00000000 + + + rxfifo_tout_int_st + The interrupt state bit for Rx time-out event + 8 + 1 + read-only + + + brk_det_int_st + The interrupt state bit for rx byte start error + 7 + 1 + read-only + + + cts_chg_int_st + The interrupt state bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_st + The interrupt state bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_st + The interrupt state bit for RX fifo overflow + 4 + 1 + read-only + + + frm_err_int_st + The interrupt state for other rx error + 3 + 1 + read-only + + + parity_err_int_st + The interrupt state bit for rx parity error + 2 + 1 + read-only + + + txfifo_empty_int_st + The interrupt state bit for TX fifo empty + 1 + 1 + read-only + + + rxfifo_full_int_st + The interrupt state bit for RX fifo full event + 0 + 1 + read-only + + + + + UART_INT_ENA + 0xc + UART INTERRUPT ENABLE REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_ena + The interrupt enable bit for rx time-out interrupt + 8 + 1 + read-write + + + brk_det_int_ena + The interrupt enable bit for rx byte start error + 7 + 1 + read-write + + + cts_chg_int_ena + The interrupt enable bit for CTS changing level + 6 + 1 + read-write + + + dsr_chg_int_ena + The interrupt enable bit for DSR changing level + 5 + 1 + read-write + + + rxfifo_ovf_int_ena + The interrupt enable bit for rx fifo overflow + 4 + 1 + read-write + + + frm_err_int_ena + The interrupt enable bit for other rx error + 3 + 1 + read-write + + + parity_err_int_ena + The interrupt enable bit for parity error + 2 + 1 + read-write + + + txfifo_empty_int_ena + The interrupt enable bit for tx fifo empty event + 1 + 1 + read-write + + + rxfifo_full_int_ena + The interrupt enable bit for rx fifo full event + 0 + 1 + read-write + + + + + UART_INT_CLR + 0x10 + UART INTERRUPT CLEAR REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_clr + Set this bit to clear the rx time-out interrupt + 8 + 1 + write-only + + + brk_det_int_clr + Set this bit to clear the rx byte start interrupt + 7 + 1 + write-only + + + cts_chg_int_clr + Set this bit to clear the CTS changing interrupt + 6 + 1 + write-only + + + dsr_chg_int_clr + Set this bit to clear the DSR changing interrupt + 5 + 1 + write-only + + + rxfifo_ovf_int_clr + Set this bit to clear the rx fifo over-flow interrupt + 4 + 1 + write-only + + + frm_err_int_clr + Set this bit to clear other rx error interrupt + 3 + 1 + write-only + + + parity_err_int_clr + Set this bit to clear the parity error interrupt + 2 + 1 + write-only + + + txfifo_empty_int_clr + Set this bit to clear the tx fifo empty interrupt + 1 + 1 + write-only + + + rxfifo_full_int_clr + Set this bit to clear the rx fifo full interrupt + 0 + 1 + write-only + + + + + UART_CLKDIV + 0x14 + UART CLK DIV REGISTER + 32 + 0x00000000 + + + uart_clkdiv + BAUDRATE = UART_CLK_FREQ / UART_CLKDIV + 0 + 20 + read-write + + + + + UART_AUTOBAUD + 0x18 + UART BAUDRATE DETECT REGISTER + 32 + 0x00000000 + + + glitch_filt + 8 + 8 + read-write + + + autobaud_en + Set this bit to enable baudrate detect + 0 + 1 + read-write + + + + + UART_STATUS + 0x1c + UART STATUS REGISTER + 32 + 0x00000000 + + + txd + The level of the uart txd pin + 31 + 1 + read-only + + + rtsn + The level of uart rts pin + 30 + 1 + read-only + + + dtrn + The level of uart dtr pin + 29 + 1 + read-only + + + txfifo_cnt + Number of data in UART TX fifo + 16 + 8 + read-only + + + rxd + The level of uart rxd pin + 15 + 1 + read-only + + + ctsn + The level of uart cts pin + 14 + 1 + read-only + + + dsrn + The level of uart dsr pin + 13 + 1 + read-only + + + rxfifo_cnt + Number of data in uart rx fifo + 0 + 8 + read-only + + + + + UART_CONF0 + 0x20 + UART CONFIG0(UART0 and UART1) + 32 + 0x00000000 + + + uart_dtr_inv + Set this bit to inverse uart dtr level + 24 + 1 + read-write + + + uart_rts_inv + Set this bit to inverse uart rts level + 23 + 1 + read-write + + + uart_txd_inv + Set this bit to inverse uart txd level + 22 + 1 + read-write + + + uart_dsr_inv + Set this bit to inverse uart dsr level + 21 + 1 + read-write + + + uart_cts_inv + Set this bit to inverse uart cts level + 20 + 1 + read-write + + + uart_rxd_inv + Set this bit to inverse uart rxd level + 19 + 1 + read-write + + + txfifo_rst + Set this bit to reset uart tx fifo + 18 + 1 + read-write + + + rxfifo_rst + Set this bit to reset uart rx fifo + 17 + 1 + read-write + + + tx_flow_en + Set this bit to enable uart tx hardware flow control + 15 + 1 + read-write + + + uart_loopback + Set this bit to enable uart loopback test mode + 14 + 1 + read-write + + + txd_brk + RESERVED, DO NOT CHANGE THIS BIT + 8 + 1 + read-write + + + sw_dtr + sw dtr + 7 + 1 + read-write + + + sw_rts + sw rts + 6 + 1 + read-write + + + stop_bit_num + Set stop bit: 1:1bit 2:1.5bits 3:2bits + 4 + 2 + read-write + + + bit_num + Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits + 2 + 2 + read-write + + + parity_en + Set this bit to enable uart parity check + 1 + 1 + read-write + + + parity + Set parity check: 0:even 1:odd, UART CONFIG1 + 0 + 1 + read-write + + + + + UART_CONF1 + 0x24 + Set this bit to enable rx time-out function + 32 + 0x00000000 + + + rx_tout_en + Set this bit to enable rx time-out function + 31 + 1 + read-write + + + rx_tout_thrhd + Config bits for rx time-out threshold,uint: byte,0-127 + 24 + 7 + read-write + + + rx_flow_en + Set this bit to enable rx hardware flow control + 23 + 1 + read-write + + + rx_flow_thrhd + The config bits for rx flow control threshold,0-127 + 16 + 7 + read-write + + + txfifo_empty_thrhd + The config bits for tx fifo empty threshold,0-127 + 8 + 7 + read-write + + + rxfifo_full_thrhd + The config bits for rx fifo full threshold,0-127 + 0 + 7 + read-write + + + + + UART_LOWPULSE + 0x28 + UART_LOWPULSE + 32 + 0x00000000 + + + lowpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_HIGHPULSE + 0x2c + UART_HIGHPULSE + 32 + 0x00000000 + + + highpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_RXD_CNT + 0x30 + UART_RXD_CNT + 32 + 0x00000000 + + + rxd_edge_cnt + used in baudrate detect + 0 + 10 + read-only + + + + + UART_DATE + 0x78 + UART HW INFO + 32 + 0x00000000 + + + uart_date + UART HW INFO + 0 + 32 + read-write + + + + + UART_ID + 0x7c + UART_ID + 32 + 0x00000000 + + + uart_id + 0 + 32 + read-write + + + + + + + WDT + 0x60000900 + + 0 + 0x00000080 + registers + + + + WDT_CTL + 0x0 + WDT_CTL + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_OP + 0x4 + WDT_OP + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_OP_ND + 0x8 + WDT_OP_ND + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_RST + 0x14 + WDT_RST + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + diff --git a/tools/partitions/app3M_fat9M_16MB.csv b/tools/partitions/app3M_fat9M_16MB.csv new file mode 100644 index 0000000..b1dbf15 --- /dev/null +++ b/tools/partitions/app3M_fat9M_16MB.csv @@ -0,0 +1,8 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +app1, app, ota_1, 0x310000,0x300000, +ffat, data, fat, 0x610000,0x9E0000, +coredump, data, coredump,0xFF0000,0x10000, +# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage diff --git a/tools/partitions/app3M_fat9M_fact512k_16MB.csv b/tools/partitions/app3M_fat9M_fact512k_16MB.csv new file mode 100644 index 0000000..dac4603 --- /dev/null +++ b/tools/partitions/app3M_fat9M_fact512k_16MB.csv @@ -0,0 +1,9 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +app1, app, ota_1, 0x310000, 0x300000, +ffat, data, fat, 0x610000, 0x960000, +factory, app, factory, 0xF70000, 0x80000, +coredump, data, coredump, 0xFF0000, 0x10000, +# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage diff --git a/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv b/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv new file mode 100644 index 0000000..3b8909d --- /dev/null +++ b/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv @@ -0,0 +1,8 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +app1, app, ota_1, 0x310000, 0x300000, +spiffs, data, spiffs, 0x610000, 0x960000, +factory, app, factory, 0xF70000, 0x80000, +coredump, data, coredump, 0xFF0000, 0x10000, diff --git a/tools/partitions/bare_minimum_2MB.csv b/tools/partitions/bare_minimum_2MB.csv new file mode 100644 index 0000000..e688a47 --- /dev/null +++ b/tools/partitions/bare_minimum_2MB.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 36K, 20K, +factory, app, factory, 64K, 1900K, diff --git a/tools/partitions/boot_app0.bin b/tools/partitions/boot_app0.bin new file mode 100644 index 0000000..13562ca Binary files /dev/null and b/tools/partitions/boot_app0.bin differ diff --git a/tools/partitions/default.bin b/tools/partitions/default.bin new file mode 100644 index 0000000..eabbf0c Binary files /dev/null and b/tools/partitions/default.bin differ diff --git a/tools/partitions/default.csv b/tools/partitions/default.csv new file mode 100644 index 0000000..960469b --- /dev/null +++ b/tools/partitions/default.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +spiffs, data, spiffs, 0x290000,0x160000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/default_16MB.csv b/tools/partitions/default_16MB.csv new file mode 100644 index 0000000..67d7737 --- /dev/null +++ b/tools/partitions/default_16MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x640000, +app1, app, ota_1, 0x650000,0x640000, +spiffs, data, spiffs, 0xc90000,0x360000, +coredump, data, coredump,0xFF0000,0x10000, diff --git a/tools/partitions/default_32MB.csv b/tools/partitions/default_32MB.csv new file mode 100644 index 0000000..dd07ac3 --- /dev/null +++ b/tools/partitions/default_32MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0xC80000, +app1, app, ota_1, 0xC90000,0xC80000, +spiffs, data, spiffs, 0x1910000,0x6C0000, +coredump, data, coredump,0x1FF0000,0x10000, diff --git a/tools/partitions/default_8MB.csv b/tools/partitions/default_8MB.csv new file mode 100644 index 0000000..4e92afa --- /dev/null +++ b/tools/partitions/default_8MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x330000, +app1, app, ota_1, 0x340000,0x330000, +spiffs, data, spiffs, 0x670000,0x180000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/default_ffat.csv b/tools/partitions/default_ffat.csv new file mode 100644 index 0000000..008bd39 --- /dev/null +++ b/tools/partitions/default_ffat.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +ffat, data, fat, 0x290000,0x160000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/default_ffat_8MB.csv b/tools/partitions/default_ffat_8MB.csv new file mode 100644 index 0000000..2791bf7 --- /dev/null +++ b/tools/partitions/default_ffat_8MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x330000, +app1, app, ota_1, 0x340000,0x330000, +ffat, data, fat, 0x670000,0x180000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/esp_sr_16.csv b/tools/partitions/esp_sr_16.csv new file mode 100644 index 0000000..97e41c4 --- /dev/null +++ b/tools/partitions/esp_sr_16.csv @@ -0,0 +1,8 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +app1, app, ota_1, 0x310000, 0x300000, +spiffs, data, spiffs, 0x610000, 0x700000, +model, data, spiffs, 0xD10000, 0x2E0000, +coredump, data, coredump,0xFF0000, 0x10000, diff --git a/tools/partitions/ffat.csv b/tools/partitions/ffat.csv new file mode 100644 index 0000000..189f70c --- /dev/null +++ b/tools/partitions/ffat.csv @@ -0,0 +1,8 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x200000, +app1, app, ota_1, 0x210000,0x200000, +ffat, data, fat, 0x410000,0xBE0000, +coredump, data, coredump,0xFF0000,0x10000, +# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage diff --git a/tools/partitions/huge_app.csv b/tools/partitions/huge_app.csv new file mode 100644 index 0000000..1d00925 --- /dev/null +++ b/tools/partitions/huge_app.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +spiffs, data, spiffs, 0x310000,0xE0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/large_fat_32MB.csv b/tools/partitions/large_fat_32MB.csv new file mode 100644 index 0000000..70b73fe --- /dev/null +++ b/tools/partitions/large_fat_32MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x480000, +app1, app, ota_1, 0x490000,0x480000, +ffat, data, fat, 0x910000,0x16E0000, +coredump, data, coredump,0x1FF0000,0x10000, diff --git a/tools/partitions/large_ffat_8MB.csv b/tools/partitions/large_ffat_8MB.csv new file mode 100644 index 0000000..20632d6 --- /dev/null +++ b/tools/partitions/large_ffat_8MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +ffat, data, fat, 0x290000,0x560000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/large_littlefs_32MB.csv b/tools/partitions/large_littlefs_32MB.csv new file mode 100644 index 0000000..34d4254 --- /dev/null +++ b/tools/partitions/large_littlefs_32MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x480000, +app1, app, ota_1, 0x490000,0x480000, +spiffs, data, spiffs, 0x910000,0x16E0000, +coredump, data, coredump,0x1FF0000,0x10000, diff --git a/tools/partitions/large_spiffs_16MB.csv b/tools/partitions/large_spiffs_16MB.csv new file mode 100644 index 0000000..a048343 --- /dev/null +++ b/tools/partitions/large_spiffs_16MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x480000, +app1, app, ota_1, 0x490000,0x480000, +spiffs, data, spiffs, 0x910000,0x6E0000, +coredump, data, coredump,0xFF0000,0x10000, diff --git a/tools/partitions/large_spiffs_8MB.csv b/tools/partitions/large_spiffs_8MB.csv new file mode 100644 index 0000000..ecf87c6 --- /dev/null +++ b/tools/partitions/large_spiffs_8MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +spiffs, data, spiffs, 0x290000,0x560000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv b/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv new file mode 100644 index 0000000..f3781c2 --- /dev/null +++ b/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv @@ -0,0 +1,11 @@ +## 4 Apps + Factory +## Name, Type, SubType, Offset, Size +nvs, data, nvs, 0x9000, 0x5000 +otadata, data, ota, 0xe000, 0x2000 +ota_0, 0, ota_0, 0x10000, 0x300000 +ota_1, 0, ota_1, 0x310000, 0x300000 +ota_2, 0, ota_2, 0x610000, 0x300000 +ota_3, 0, ota_3, 0x910000, 0x300000 +firmware, app, factory, 0xC10000, 0x0F0000 +spiffs, data, spiffs, 0xD00000, 0x2F0000 +coredump, data, coredump, 0xFF0000, 0x10000 diff --git a/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv b/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv new file mode 100644 index 0000000..6840e86 --- /dev/null +++ b/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv @@ -0,0 +1,13 @@ +# 6 Apps + Factory +# Name, Type, SubType, Offset, Size +nvs, data, nvs, 0x9000, 0x5000 +otadata, data, ota, 0xe000, 0x2000 +ota_0, 0, ota_0, 0x10000, 0x200000 +ota_1, 0, ota_1, 0x210000, 0x200000 +ota_2, 0, ota_2, 0x410000, 0x200000 +ota_3, 0, ota_3, 0x610000, 0x200000 +ota_4, 0, ota_4, 0x810000, 0x200000 +ota_5, 0, ota_5, 0xA10000, 0x200000 +firmware, app, factory, 0xC10000, 0x0F0000 +spiffs, data, spiffs, 0xD00000, 0x2F0000 +coredump, data, coredump, 0xFF0000, 0x10000 diff --git a/tools/partitions/max_app_32MB.csv b/tools/partitions/max_app_32MB.csv new file mode 100644 index 0000000..e9122d2 --- /dev/null +++ b/tools/partitions/max_app_32MB.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xE000, 0x2000, +app0, app, factory, 0x10000, 0x1FE0000, +coredump, data, coredump, 0x1FF0000, 0x10000, diff --git a/tools/partitions/max_app_4MB.csv b/tools/partitions/max_app_4MB.csv new file mode 100644 index 0000000..ec30c10 --- /dev/null +++ b/tools/partitions/max_app_4MB.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, factory, 0x10000, 0x3E0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/max_app_8MB.csv b/tools/partitions/max_app_8MB.csv new file mode 100644 index 0000000..502d9fe --- /dev/null +++ b/tools/partitions/max_app_8MB.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, factory, 0x10000, 0x7E0000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/min_spiffs.csv b/tools/partitions/min_spiffs.csv new file mode 100644 index 0000000..0990a3b --- /dev/null +++ b/tools/partitions/min_spiffs.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x1E0000, +app1, app, ota_1, 0x1F0000,0x1E0000, +spiffs, data, spiffs, 0x3D0000,0x20000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/minimal.csv b/tools/partitions/minimal.csv new file mode 100644 index 0000000..32c70ab --- /dev/null +++ b/tools/partitions/minimal.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +spiffs, data, spiffs, 0x150000, 0xA0000, +coredump, data, coredump,0x1F0000, 0x10000, diff --git a/tools/partitions/no_fs.csv b/tools/partitions/no_fs.csv new file mode 100644 index 0000000..a9078ee --- /dev/null +++ b/tools/partitions/no_fs.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x1F0000, +app1, app, ota_1, 0x200000,0x1F0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/no_ota.csv b/tools/partitions/no_ota.csv new file mode 100644 index 0000000..173a4e1 --- /dev/null +++ b/tools/partitions/no_ota.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x200000, +spiffs, data, spiffs, 0x210000,0x1E0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/noota_3g.csv b/tools/partitions/noota_3g.csv new file mode 100644 index 0000000..71d9f5e --- /dev/null +++ b/tools/partitions/noota_3g.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x100000, +spiffs, data, spiffs, 0x110000,0x2E0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/noota_3gffat.csv b/tools/partitions/noota_3gffat.csv new file mode 100644 index 0000000..4712dd1 --- /dev/null +++ b/tools/partitions/noota_3gffat.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x100000, +ffat, data, fat, 0x110000,0x2E0000, +coredump, data, coredump,0x3F0000,0x10000, +# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage diff --git a/tools/partitions/noota_ffat.csv b/tools/partitions/noota_ffat.csv new file mode 100644 index 0000000..86c3067 --- /dev/null +++ b/tools/partitions/noota_ffat.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x200000, +ffat, data, fat, 0x210000,0x1E0000, +coredump, data, coredump,0x3F0000,0x10000, +# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage diff --git a/tools/partitions/ota_nofs_4MB.csv b/tools/partitions/ota_nofs_4MB.csv new file mode 100644 index 0000000..04240ba --- /dev/null +++ b/tools/partitions/ota_nofs_4MB.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags + nvs, data, nvs, 0x9000, 0x5000, + otadata, data, ota, 0xE000, 0x2000, + app0, app, ota_0, 0x10000, 0x1F0000, + app1, app, ota_1, 0x200000, 0x1F0000, +coredump, data, coredump, 0x3F0000, 0x10000, diff --git a/tools/partitions/rainmaker.csv b/tools/partitions/rainmaker.csv new file mode 100644 index 0000000..1eabd86 --- /dev/null +++ b/tools/partitions/rainmaker.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +ota_0, app, ota_0, 0x10000, 0x1E0000, +ota_1, app, ota_1, 0x1F0000, 0x1E0000, +fctry, data, nvs, 0x3D0000, 0x6000, +coredump, data, coredump,0x3F0000, 0x10000, diff --git a/tools/partitions/rainmaker_4MB_no_ota.csv b/tools/partitions/rainmaker_4MB_no_ota.csv new file mode 100644 index 0000000..ec10004 --- /dev/null +++ b/tools/partitions/rainmaker_4MB_no_ota.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +ota_0, app, ota_0, 0x10000, 0x3DA000, +fctry, data, nvs, 0x3EA000, 0x6000, +coredump, data, coredump,0x3F0000, 0x10000, diff --git a/tools/partitions/rainmaker_8MB.csv b/tools/partitions/rainmaker_8MB.csv new file mode 100644 index 0000000..6bad399 --- /dev/null +++ b/tools/partitions/rainmaker_8MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +ota_0, app, ota_0, 0x10000, 0x3EA000, +ota_1, app, ota_1, 0x400000, 0x3EA000, +fctry, data, nvs, 0x7EA000, 0x6000, +coredump, data, coredump,0x7F0000, 0x10000, diff --git a/tools/partitions/storage_4MB_noota.csv b/tools/partitions/storage_4MB_noota.csv new file mode 100644 index 0000000..cbec05a --- /dev/null +++ b/tools/partitions/storage_4MB_noota.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +app0, app, factory, 0x10000, 0x200000, +nvs, data, nvs, 0x210000, 0x100000, +spiffs, data, spiffs, 0x310000, 0xE0000, +coredump, data, coredump,0x3F0000, 0x10000, diff --git a/tools/partitions/tinyuf2-partitions-16MB-noota.csv b/tools/partitions/tinyuf2-partitions-16MB-noota.csv new file mode 100644 index 0000000..0df5972 --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-16MB-noota.csv @@ -0,0 +1,9 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 4096K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/tools/partitions/tinyuf2-partitions-16MB.csv b/tools/partitions/tinyuf2-partitions-16MB.csv new file mode 100644 index 0000000..55f6c2b --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-16MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 2048K, +ota_1, app, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/tools/partitions/tinyuf2-partitions-4MB-noota.csv b/tools/partitions/tinyuf2-partitions-4MB-noota.csv new file mode 100644 index 0000000..ab7fa86 --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-4MB-noota.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table, 0x8000, 4K + +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 2816K, +uf2, app, factory,0x2d0000, 256K, +ffat, data, fat, 0x310000, 960K, diff --git a/tools/partitions/tinyuf2-partitions-4MB.csv b/tools/partitions/tinyuf2-partitions-4MB.csv new file mode 100644 index 0000000..f3112a2 --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-4MB.csv @@ -0,0 +1,11 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table, 0x8000, 4K + +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 1408K, +ota_1, app, ota_1, 0x170000, 1408K, +uf2, app, factory,0x2d0000, 256K, +ffat, data, fat, 0x310000, 960K, diff --git a/tools/partitions/tinyuf2-partitions-8MB-noota.csv b/tools/partitions/tinyuf2-partitions-8MB-noota.csv new file mode 100644 index 0000000..cef4329 --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-8MB-noota.csv @@ -0,0 +1,9 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 4096K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/tools/partitions/tinyuf2-partitions-8MB.csv b/tools/partitions/tinyuf2-partitions-8MB.csv new file mode 100644 index 0000000..a68b39e --- /dev/null +++ b/tools/partitions/tinyuf2-partitions-8MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 2048K, +ota_1, app, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/tools/partitions/zigbee.csv b/tools/partitions/zigbee.csv new file mode 100644 index 0000000..938d59b --- /dev/null +++ b/tools/partitions/zigbee.csv @@ -0,0 +1,9 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +spiffs, data, spiffs, 0x290000,0x15B000, +zb_storage, data, fat, 0x3EB000,0x4000, +zb_fct, data, fat, 0x3EF000,0x1000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/zigbee_2MB.csv b/tools/partitions/zigbee_2MB.csv new file mode 100644 index 0000000..7034f9b --- /dev/null +++ b/tools/partitions/zigbee_2MB.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +factory, app, factory, 0x10000, 0x140000, +spiffs, data, spiffs, 0x150000,0x9B000, +zb_storage, data, fat, 0x1EB000,0x4000, +zb_fct, data, fat, 0x1EF000,0x1000, +coredump, data, coredump,0x1F0000,0x10000, diff --git a/tools/partitions/zigbee_8MB.csv b/tools/partitions/zigbee_8MB.csv new file mode 100644 index 0000000..fdf46fb --- /dev/null +++ b/tools/partitions/zigbee_8MB.csv @@ -0,0 +1,9 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x340000, +app1, app, ota_1, 0x350000,0x340000, +spiffs, data, spiffs, 0x690000,0x15B000, +zb_storage, data, fat, 0x7EB000,0x4000, +zb_fct, data, fat, 0x7EF000,0x1000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/partitions/zigbee_zczr.csv b/tools/partitions/zigbee_zczr.csv new file mode 100644 index 0000000..e734e1d --- /dev/null +++ b/tools/partitions/zigbee_zczr.csv @@ -0,0 +1,10 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x140000, +app1, app, ota_1, 0x150000,0x140000, +spiffs, data, spiffs, 0x290000,0x15A000, +zb_storage, data, fat, 0x3EA000,0x4000, +zb_fct, data, fat, 0x3EE000,0x1000, +rcp_fw, data, spiffs, 0x3EF000,0x1000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/tools/partitions/zigbee_zczr_2MB.csv b/tools/partitions/zigbee_zczr_2MB.csv new file mode 100644 index 0000000..10484ee --- /dev/null +++ b/tools/partitions/zigbee_zczr_2MB.csv @@ -0,0 +1,8 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +factory, app, factory, 0x10000, 0x140000, +spiffs, data, spiffs, 0x150000,0x9A000, +zb_storage, data, fat, 0x1EA000,0x4000, +zb_fct, data, fat, 0x1EE000,0x1000, +rcp_fw, data, spiffs, 0x1EF000,0x1000, +coredump, data, coredump,0x1F0000,0x10000, diff --git a/tools/partitions/zigbee_zczr_8MB.csv b/tools/partitions/zigbee_zczr_8MB.csv new file mode 100644 index 0000000..70dd680 --- /dev/null +++ b/tools/partitions/zigbee_zczr_8MB.csv @@ -0,0 +1,10 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x340000, +app1, app, ota_1, 0x350000,0x340000, +spiffs, data, spiffs, 0x690000,0x15A000, +zb_storage, data, fat, 0x7EA000,0x4000, +zb_fct, data, fat, 0x7EE000,0x1000, +rcp_fw, data, spiffs, 0x7EF000,0x1000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/tools/pioarduino-build.py b/tools/pioarduino-build.py new file mode 100644 index 0000000..ac0a743 --- /dev/null +++ b/tools/pioarduino-build.py @@ -0,0 +1,263 @@ +# Copyright 2014-present PlatformIO +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Arduino + +Arduino Wiring-based Framework allows writing cross-platform software to +control devices attached to a wide range of Arduino boards to create all +kinds of creative coding, interactive objects, spaces or physical experiences. + +http://arduino.cc/en/Reference/HomePage +""" + +# Extends: https://github.com/pioarduino/platform-espressif32/blob/develop/builder/main.py + +from os.path import abspath, basename, isdir, isfile, join +from copy import deepcopy +from SCons.Script import DefaultEnvironment, SConscript + +env = DefaultEnvironment() +platform = env.PioPlatform() +board_config = env.BoardConfig() +build_mcu = board_config.get("build.mcu", "").lower() +chip_variant = board_config.get("build.chip_variant", "").lower() +chip_variant = chip_variant if chip_variant else build_mcu +partitions_name = board_config.get("build.partitions", board_config.get("build.arduino.partitions", "")) + +FRAMEWORK_DIR = platform.get_package_dir("framework-arduinoespressif32") +FRAMEWORK_LIBS_DIR = platform.get_package_dir("framework-arduinoespressif32-libs") +assert isdir(FRAMEWORK_DIR) + + +# +# Helpers +# + + +def get_partition_table_csv(variants_dir): + fwpartitions_dir = join(FRAMEWORK_DIR, "tools", "partitions") + variant_partitions_dir = join(variants_dir, board_config.get("build.variant", "")) + + if partitions_name: + # A custom partitions file is selected + if isfile(env.subst(join(variant_partitions_dir, partitions_name))): + return join(variant_partitions_dir, partitions_name) + + return abspath( + join(fwpartitions_dir, partitions_name) + if isfile(env.subst(join(fwpartitions_dir, partitions_name))) + else partitions_name + ) + + variant_partitions = join(variant_partitions_dir, "partitions.csv") + return variant_partitions if isfile(env.subst(variant_partitions)) else join(fwpartitions_dir, "default.csv") + + +def get_bootloader_image(variants_dir): + bootloader_image_file = "bootloader.bin" + if partitions_name.endswith("tinyuf2.csv"): + bootloader_image_file = "bootloader-tinyuf2.bin" + + variant_bootloader = join( + variants_dir, + board_config.get("build.variant", ""), + board_config.get("build.arduino.custom_bootloader", bootloader_image_file), + ) + + return ( + variant_bootloader + if isfile(env.subst(variant_bootloader)) + else generate_bootloader_image( + join( + FRAMEWORK_LIBS_DIR, + chip_variant, + "bin", + "bootloader_${__get_board_boot_mode(__env__)}_${__get_board_f_boot(__env__)}.elf", + ) + ) + ) + + +def generate_bootloader_image(bootloader_elf): + bootloader_cmd = env.Command( + join("$BUILD_DIR", "bootloader.bin"), + bootloader_elf, + env.VerboseAction( + " ".join( + [ + "$OBJCOPY", + "--chip", + build_mcu, + "elf2image", + "--flash-mode", + "${__get_board_flash_mode(__env__)}", + "--flash-freq", + "${__get_board_f_image(__env__)}", + "--flash-size", + board_config.get("upload.flash_size", "4MB"), + "-o", + "$TARGET", + "$SOURCES", + ] + ), + "Building $TARGET", + ), + ) + + env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", bootloader_cmd) + + # Because the Command always returns a NodeList, we have to + # access the first element in the list to get the Node object + # that actually represents the bootloader image. + # Also, this file is later used in generic Python code, so the + # Node object in converted to a generic string + return str(bootloader_cmd[0]) + + +def add_tinyuf2_extra_image(): + tinuf2_image = board_config.get( + "upload.arduino.tinyuf2_image", + join(variants_dir, board_config.get("build.variant", ""), "tinyuf2.bin"), + ) + + # Add the UF2 image only if it exists and it's not already added + if not isfile(env.subst(tinuf2_image)): + print("Warning! The `%s` UF2 bootloader image doesn't exist" % env.subst(tinuf2_image)) + return + + if any("tinyuf2.bin" == basename(extra_image[1]) for extra_image in env.get("FLASH_EXTRA_IMAGES", [])): + print("Warning! An extra UF2 bootloader image is already added!") + return + + env.Append( + FLASH_EXTRA_IMAGES=[ + ( + board_config.get( + "upload.arduino.uf2_bootloader_offset", + ("0x2d0000" if env.subst("$BOARD").startswith("adafruit") else "0x410000"), + ), + tinuf2_image, + ), + ] + ) + + +# +# Run target-specific script to populate the environment with proper build flags +# + +SConscript( + join( + FRAMEWORK_LIBS_DIR, + chip_variant, + "pioarduino-build.py", + ) +) + +# +# Additional flags specific to Arduino core (not based on IDF) +# + +env.Append( + CFLAGS=["-Werror=return-type"], + CXXFLAGS=["-Werror=return-type"], +) + +# +# Target: Build Core Library +# + +# Set -DARDUINO_CORE_BUILD only for the core library +corelib_env = env.Clone() +corelib_env.Append(CPPDEFINES=["ARDUINO_CORE_BUILD"]) + +libs = [] + +variants_dir = join(FRAMEWORK_DIR, "variants") + +if "build.variants_dir" in board_config: + variants_dir = join("$PROJECT_DIR", board_config.get("build.variants_dir")) + +if "build.variant" in board_config: + env.Append(CPPPATH=[join(variants_dir, board_config.get("build.variant"))]) + corelib_env.Append(CPPPATH=[join(variants_dir, board_config.get("build.variant"))]) + corelib_env.BuildSources( + join("$BUILD_DIR", "FrameworkArduinoVariant"), + join(variants_dir, board_config.get("build.variant")), + ) + +libs.append( + corelib_env.BuildLibrary( + join("$BUILD_DIR", "FrameworkArduino"), + join(FRAMEWORK_DIR, "cores", board_config.get("build.core")), + ) +) + +env.Prepend(LIBS=libs) + +# +# Process framework extra images +# + +env.Append( + LIBSOURCE_DIRS=[join(FRAMEWORK_DIR, "libraries")], + FLASH_EXTRA_IMAGES=[ + ( + ( + "0x1000" + if build_mcu in ["esp32", "esp32s2"] + else ("0x2000" if build_mcu in ["esp32p4", "esp32c5"] else "0x0000") + ), + get_bootloader_image(variants_dir), + ), + ( + board_config.get("upload.arduino.partitions_bin", "0x8000"), + join(env.subst("$BUILD_DIR"), "partitions.bin"), + ), + ( + board_config.get("upload.arduino.boot_app0", "0xe000"), + join(FRAMEWORK_DIR, "tools", "partitions", "boot_app0.bin"), + ), + ] + + [(offset, join(FRAMEWORK_DIR, img)) for offset, img in board_config.get("upload.arduino.flash_extra_images", [])], +) + +# Add an extra UF2 image if the 'TinyUF2' partition is selected +if partitions_name.endswith("tinyuf2.csv") or board_config.get("upload.arduino.tinyuf2_image", ""): + add_tinyuf2_extra_image() + +# +# Generate partition table +# + +env.Replace(PARTITIONS_TABLE_CSV=get_partition_table_csv(variants_dir)) + +partition_table = env.Command( + join("$BUILD_DIR", "partitions.bin"), + "$PARTITIONS_TABLE_CSV", + env.VerboseAction( + '"$PYTHONEXE" "%s" -q $SOURCE $TARGET' % join(FRAMEWORK_DIR, "tools", "gen_esp32part.py"), + "Generating partitions $TARGET", + ), +) +env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", partition_table) + +# +# Adjust the `esptoolpy` command in the `ElfToBin` builder with firmware checksum offset +# + +action = deepcopy(env["BUILDERS"]["ElfToBin"].action) +action.cmd_list = env["BUILDERS"]["ElfToBin"].action.cmd_list.replace("-o", "--elf-sha256-offset 0xb0 -o") +env["BUILDERS"]["ElfToBin"].action = action diff --git a/variants/AirM2M_CORE_ESP32C3/pins_arduino.h b/variants/AirM2M_CORE_ESP32C3/pins_arduino.h new file mode 100644 index 0000000..ea40027 --- /dev/null +++ b/variants/AirM2M_CORE_ESP32C3/pins_arduino.h @@ -0,0 +1,30 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 12; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t LED_BUILTIN_AUX = 13; + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 3; +static const uint8_t MISO = 10; +static const uint8_t SCK = 2; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/AirM2M_CORE_ESP32C3/variant.cpp b/variants/AirM2M_CORE_ESP32C3/variant.cpp new file mode 100644 index 0000000..01bd641 --- /dev/null +++ b/variants/AirM2M_CORE_ESP32C3/variant.cpp @@ -0,0 +1,9 @@ +#include "Arduino.h" + +extern "C" void initVariant(void) { + // Stop LEDs floating + pinMode(LED_BUILTIN, OUTPUT); + digitalWrite(LED_BUILTIN, LOW); + pinMode(LED_BUILTIN_AUX, OUTPUT); + digitalWrite(LED_BUILTIN_AUX, LOW); +} diff --git a/variants/Aventen_S3_Sync/pins_arduino.h b/variants/Aventen_S3_Sync/pins_arduino.h new file mode 100644 index 0000000..bc7eee3 --- /dev/null +++ b/variants/Aventen_S3_Sync/pins_arduino.h @@ -0,0 +1,62 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 +#define USB_MANUFACTURER "Aventen" +#define USB_PRODUCT "Aventen S3 Sync" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 2; +static const uint8_t SCL = 3; +static const uint8_t SCL_1 = 21; +static const uint8_t SDA_1 = 20; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t ALS = 17; +static const uint8_t RGB_DI = 38; +static const uint8_t RF_SW = 37; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; +static const uint8_t T15 = 15; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Bee_Data_Logger/pins_arduino.h b/variants/Bee_Data_Logger/pins_arduino.h new file mode 100644 index 0000000..2fa1026 --- /dev/null +++ b/variants/Bee_Data_Logger/pins_arduino.h @@ -0,0 +1,78 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x815C +#define USB_MANUFACTURER "Smart Bee Designs" +#define USB_PRODUCT "Bee Data Logger" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 37; +static const uint8_t SCL = 36; + +static const uint8_t SS = 47; +static const uint8_t MOSI = 46; +static const uint8_t MISO = 45; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 48; + +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; +static const uint8_t A7 = 7; +static const uint8_t A8 = 8; +static const uint8_t A9 = 9; + +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D38 = 38; +static const uint8_t D39 = 39; +static const uint8_t D41 = 41; +static const uint8_t D42 = 42; +static const uint8_t D43 = 43; +static const uint8_t D44 = 44; + +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t BOOT_BTN = 0; +static const uint8_t VBAT_VOLTAGE = 1; +#define BAT_VOLT_PIN VBAT_VOLTAGE +static const uint8_t VBUS_SENSE = 2; +static const uint8_t LDO2 = 34; +static const uint8_t RGB_DATA = 40; +static const uint8_t RGB_PWR = 34; + +#define PIN_RGB_LED RGB_DATA +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#endif /* Pins_Arduino_h */ diff --git a/variants/Bee_Motion/pins_arduino.h b/variants/Bee_Motion/pins_arduino.h new file mode 100644 index 0000000..a2d6616 --- /dev/null +++ b/variants/Bee_Motion/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x810D +#define USB_MANUFACTURER "Smart Bee Designs" +#define USB_PRODUCT "Bee Motion S3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 36; +static const uint8_t SCL = 37; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 16; +static const uint8_t MISO = 38; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 15; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +static const uint8_t T1 = 1; +static const uint8_t T3 = 3; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T14 = 14; + +static const uint8_t BOOT_BTN = 0; +static const uint8_t PIR = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Bee_Motion_Mini/pins_arduino.h b/variants/Bee_Motion_Mini/pins_arduino.h new file mode 100644 index 0000000..376125c --- /dev/null +++ b/variants/Bee_Motion_Mini/pins_arduino.h @@ -0,0 +1,27 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t BOOT_BTN = 9; +static const uint8_t PIR = 5; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Bee_Motion_S3/pins_arduino.h b/variants/Bee_Motion_S3/pins_arduino.h new file mode 100644 index 0000000..38a5a9a --- /dev/null +++ b/variants/Bee_Motion_S3/pins_arduino.h @@ -0,0 +1,86 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8113 +#define USB_MANUFACTURER "Smart Bee Designs" +#define USB_PRODUCT "Bee Motion S3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 37; +static const uint8_t SCL = 36; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 16; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 17; + +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; +static const uint8_t A7 = 7; +static const uint8_t A8 = 8; +static const uint8_t A9 = 9; +static const uint8_t A10 = 10; +static const uint8_t A11 = 11; +static const uint8_t A12 = 12; +static const uint8_t A13 = 13; +static const uint8_t A14 = 14; +static const uint8_t A15 = 15; + +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D11 = 11; +static const uint8_t D12 = 12; +static const uint8_t D14 = 14; +static const uint8_t D15 = 15; +static const uint8_t D16 = 16; +static const uint8_t D17 = 17; +static const uint8_t D35 = 35; +static const uint8_t D36 = 36; +static const uint8_t D37 = 37; +static const uint8_t D43 = 43; +static const uint8_t D44 = 44; + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t BOOT_BTN = 0; +static const uint8_t VBAT_VOLTAGE = 1; +#define BAT_VOLT_PIN VBAT_VOLTAGE +static const uint8_t VBUS_SENSE = 2; +static const uint8_t PIR = 4; +static const uint8_t LIGHT = 3; +static const uint8_t LDO2 = 34; +static const uint8_t RGB_DATA = 40; +static const uint8_t RGB_PWR = 34; + +#define PIN_RGB_LED RGB_DATA +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#endif /* Pins_Arduino_h */ diff --git a/variants/Bee_S3/pins_arduino.h b/variants/Bee_S3/pins_arduino.h new file mode 100644 index 0000000..906a8c6 --- /dev/null +++ b/variants/Bee_S3/pins_arduino.h @@ -0,0 +1,75 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8110 +#define USB_MANUFACTURER "Smart Bee Designs" +#define USB_PRODUCT "BeeS3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 37; +static const uint8_t SCL = 36; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 38; +static const uint8_t SDO = 35; +static const uint8_t SDI = 38; +static const uint8_t SCK = 39; + +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; +static const uint8_t A7 = 7; +static const uint8_t A8 = 8; +static const uint8_t A9 = 9; +static const uint8_t A10 = 10; + +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D35 = 35; +static const uint8_t D36 = 36; +static const uint8_t D37 = 37; +static const uint8_t D38 = 38; +static const uint8_t D39 = 39; +static const uint8_t D43 = 43; +static const uint8_t D44 = 44; + +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; + +static const uint8_t VBAT_VOLTAGE = 1; +#define BAT_VOLT_PIN VBAT_VOLTAGE + +static const uint8_t RGB_DATA = 48; +static const uint8_t RGB_PWR = 34; + +#define PIN_RGB_LED RGB_DATA +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#endif /* Pins_Arduino_h */ diff --git a/variants/BharatPi-A7672S-4G/pins_arduino.h b/variants/BharatPi-A7672S-4G/pins_arduino.h new file mode 100644 index 0000000..bf1fab0 --- /dev/null +++ b/variants/BharatPi-A7672S-4G/pins_arduino.h @@ -0,0 +1,31 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t A0 = 14; +static const uint8_t A1 = 13; +static const uint8_t A2 = 12; +static const uint8_t A3 = 4; +static const uint8_t A4 = 2; +static const uint8_t A5 = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t TX_4G = 17; +static const uint8_t RX_4G = 16; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/BharatPi-LoRa/pins_arduino.h b/variants/BharatPi-LoRa/pins_arduino.h new file mode 100644 index 0000000..a42e583 --- /dev/null +++ b/variants/BharatPi-LoRa/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t A0 = 14; +static const uint8_t A1 = 13; +static const uint8_t A2 = 12; +static const uint8_t A3 = 4; +static const uint8_t A4 = 2; +static const uint8_t A5 = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t TX2 = 17; +static const uint8_t RX2 = 16; + +static const uint8_t LORA_SS = 4; +static const uint8_t RST = 14; +static const uint8_t DIO0 = 2; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/BharatPi-Node-Wifi/pins_arduino.h b/variants/BharatPi-Node-Wifi/pins_arduino.h new file mode 100644 index 0000000..3b15128 --- /dev/null +++ b/variants/BharatPi-Node-Wifi/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SAFFRON_LED = 12; +static const uint8_t WHITE_LED = 2; +static const uint8_t GREEN_LED = 13; + +static const uint8_t A0 = 14; +static const uint8_t A1 = 13; +static const uint8_t A2 = 12; +static const uint8_t A3 = 4; +static const uint8_t A4 = 2; +static const uint8_t A5 = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t TX2 = 17; +static const uint8_t RX2 = 16; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ET-Board/pins_arduino.h b/variants/ET-Board/pins_arduino.h new file mode 100644 index 0000000..ec2c1f4 --- /dev/null +++ b/variants/ET-Board/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 34; +static const uint8_t RX = 35; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 29; +static const uint8_t MOSI = 37; +static const uint8_t MISO = 31; +static const uint8_t SCK = 30; + +static const uint8_t A0 = 36; // BUILTIN_Potentiometer +static const uint8_t A1 = 39; // BUILTIN_CDS +static const uint8_t A2 = 32; // BUILTIN_temperature +static const uint8_t A3 = 33; // Analog Input +static const uint8_t A4 = 34; // Analog Input +static const uint8_t A5 = 35; // Analog Input +static const uint8_t A6 = 25; // Analog Input +static const uint8_t A7 = 26; // Analog Input + +static const uint8_t D2 = 27; // BUILTIN_LED_Red +static const uint8_t D3 = 14; // BUILTIN_LED_Blue +static const uint8_t D4 = 12; // BUILTIN_LED_Green +static const uint8_t D5 = 13; // BUILTIN_LED_Yellow +static const uint8_t D6 = 15; // BUILTIN_BUTTON_Red +static const uint8_t D7 = 16; // BUILTIN_BUTTON_Blue +static const uint8_t D8 = 17; // BUILTIN_BUTTON_Green +static const uint8_t D9 = 4; // BUILTIN_BUTTON_Yellow + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Edgebox-ESP-100/pins_arduino.h b/variants/Edgebox-ESP-100/pins_arduino.h new file mode 100644 index 0000000..d2f54a8 --- /dev/null +++ b/variants/Edgebox-ESP-100/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +//Programming and Debugging Port +static const uint8_t TXD = 43; +static const uint8_t RXD = 44; +static const uint8_t RST = 0; + +//I2C +static const uint8_t SDA = 20; +static const uint8_t SCL = 19; + +//I2C INT fro RTC PCF8563 +static const uint8_t I2C_INT = 9; + +//SPI BUS for W5500 Ethernet Port Driver +static const uint8_t SS = 10; +static const uint8_t MOSI = 12; +static const uint8_t MISO = 11; +static const uint8_t SCK = 13; +static const uint8_t ETH_INT = 14; +static const uint8_t ETH_RST = 15; + +//A7670G +static const uint8_t LTE_PWR_EN = 16; +static const uint8_t LTE_PWR_KEY = 21; +static const uint8_t LTE_TXD = 48; +static const uint8_t LTE_RXD = 47; + +//RS485 +static const uint8_t RS485_TXD = 17; +static const uint8_t RS485_RXD = 18; +static const uint8_t RS485_RTS = 8; + +//CAN BUS +static const uint8_t CAN_TXD = 1; +static const uint8_t CAN_RXD = 2; + +//BUZZER +static const uint8_t BUZZER = 45; + +static const uint8_t DO0 = 40; +static const uint8_t DO1 = 39; +static const uint8_t DO2 = 38; +static const uint8_t DO3 = 37; +static const uint8_t DO4 = 36; +static const uint8_t DO5 = 35; + +static const uint8_t DI0 = 4; +static const uint8_t DI1 = 5; +static const uint8_t DI2 = 6; +static const uint8_t DI3 = 7; + +static const uint8_t AO0 = 42; +static const uint8_t AO1 = 41; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Geekble_ESP32C3/pins_arduino.h b/variants/Geekble_ESP32C3/pins_arduino.h new file mode 100644 index 0000000..56bda11 --- /dev/null +++ b/variants/Geekble_ESP32C3/pins_arduino.h @@ -0,0 +1,39 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 10; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SW_BUILTIN = 9; +#define BUILTIN_SW SW_BUILTIN // backward compatibility +#define SW_BUILTIN SW_BUILTIN // allow testing #ifdef SW_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +//static const uint8_t A5 = 5; // ADC1 no longer supported + +#endif /* Pins_Arduino_h */ diff --git a/variants/Geekble_Nano_ESP32S3/pins_arduino.h b/variants/Geekble_Nano_ESP32S3/pins_arduino.h new file mode 100644 index 0000000..657c0d5 --- /dev/null +++ b/variants/Geekble_Nano_ESP32S3/pins_arduino.h @@ -0,0 +1,74 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x82C5 +#define USB_MANUFACTURER "Geekble" +#define USB_PRODUCT "Geekble nano ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t D0 = 44; // also RX +static const uint8_t D1 = 43; // also TX +static const uint8_t D2 = 5; +static const uint8_t D3 = 6; // also CTS +static const uint8_t D4 = 7; // also DSR +static const uint8_t D5 = 8; +static const uint8_t D6 = 9; +static const uint8_t D7 = 10; +static const uint8_t D8 = 17; +static const uint8_t D9 = 18; +static const uint8_t D10 = 21; // also SS +static const uint8_t D11 = 38; // also MOSI +static const uint8_t D12 = 47; // also MISO +static const uint8_t D13 = 48; // also SCK, LED_BUILTIN + +static const uint8_t A0 = 1; // also DTR +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 11; // also SDA +static const uint8_t A5 = 12; // also SCL +static const uint8_t A6 = 13; +static const uint8_t A7 = 14; + +// alternate pin functions + +static const uint8_t LED_BUILTIN = D13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SW_BUILTIN = 0; + +static const uint8_t TX = D1; +static const uint8_t RX = D0; +static const uint8_t RTS = 45; +static const uint8_t CTS = D3; +static const uint8_t DTR = A0; +static const uint8_t DSR = D4; + +static const uint8_t SS = D10; +static const uint8_t MOSI = D11; +static const uint8_t MISO = D12; +static const uint8_t SCK = D13; + +static const uint8_t SDA = A4; +static const uint8_t SCL = A5; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#define PIN_I2S_SCK D7 +#define PIN_I2S_FS D8 +#define PIN_I2S_SD D9 +#define PIN_I2S_SD_OUT D9 // same as bidir +#define PIN_I2S_SD_IN D10 + +#endif /* Pins_Arduino_h */ diff --git a/variants/Microduino-esp32/pins_arduino.h b/variants/Microduino-esp32/pins_arduino.h new file mode 100644 index 0000000..7d7c22f --- /dev/null +++ b/variants/Microduino-esp32/pins_arduino.h @@ -0,0 +1,81 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = -1; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define MTDO 15 +#define MTDI 12 +#define MTMS 14 +#define MTCK 13 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 22; //23; +static const uint8_t SCL = 21; //19; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 12; +static const uint8_t SCL1 = 13; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 12; +static const uint8_t A1 = 13; +static const uint8_t A2 = 15; +static const uint8_t A3 = 4; +static const uint8_t A6 = 38; +static const uint8_t A7 = 37; + +static const uint8_t A8 = 32; +static const uint8_t A9 = 33; +static const uint8_t A10 = 25; +static const uint8_t A11 = 26; +static const uint8_t A12 = 27; +static const uint8_t A13 = 14; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 16; +static const uint8_t D3 = 17; +static const uint8_t D4 = 32; //ADC1_CH4 +static const uint8_t D5 = 33; //ADC1_CH5 +static const uint8_t D6 = 25; //ADC2_CH8 DAC_1 +static const uint8_t D7 = 26; //ADC2_CH9 DAC_2 +static const uint8_t D8 = 27; //ADC2_CH7 +static const uint8_t D9 = 14; //ADC2_CH6 +static const uint8_t D10 = 5; +static const uint8_t D11 = 23; +static const uint8_t D12 = 19; +static const uint8_t D13 = 18; +static const uint8_t D14 = 12; +static const uint8_t D15 = 13; +static const uint8_t D16 = 15; +static const uint8_t D17 = 4; +static const uint8_t D18 = 22; +static const uint8_t D19 = 21; +static const uint8_t D20 = 38; +static const uint8_t D21 = 37; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Nebula_S3/pins_arduino.h b/variants/Nebula_S3/pins_arduino.h new file mode 100644 index 0000000..cc18cda --- /dev/null +++ b/variants/Nebula_S3/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 45; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SDA1 = 2; +static const uint8_t SCL1 = 1; + +static const uint8_t SS = 41; +static const uint8_t MOSI = 40; +static const uint8_t MISO = 39; +static const uint8_t SCK = 38; + +static const uint8_t D0 = 1; +static const uint8_t D1 = 2; +static const uint8_t D2 = 44; +static const uint8_t D3 = 43; +static const uint8_t D4 = 42; +static const uint8_t D5 = 41; +static const uint8_t D6 = 40; +static const uint8_t D7 = 39; +static const uint8_t D8 = 38; +static const uint8_t D9 = 27; +static const uint8_t D10 = 45; +static const uint8_t D11 = 4; +static const uint8_t D12 = 5; +static const uint8_t D13 = 6; +static const uint8_t D14 = 7; +static const uint8_t D15 = 15; +static const uint8_t D16 = 16; +static const uint8_t D17 = 17; +static const uint8_t D18 = 18; + +static const uint8_t A0 = 4; +static const uint8_t A1 = 5; +static const uint8_t A2 = 6; +static const uint8_t A3 = 7; +static const uint8_t A4 = 1; +static const uint8_t A5 = 2; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Pcbcupid_GLYPH_C3/pins_arduino.h b/variants/Pcbcupid_GLYPH_C3/pins_arduino.h new file mode 100644 index 0000000..5475de8 --- /dev/null +++ b/variants/Pcbcupid_GLYPH_C3/pins_arduino.h @@ -0,0 +1,44 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 1; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +//MSR Used in on-board battery measurement +static const uint8_t BAT_MEASURE = 0; +#define BAT_VOLT_PIN BAT_MEASURE +#define MSR BAT_MEASURE + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 3; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 7; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Pcbcupid_GLYPH_C6/pins_arduino.h b/variants/Pcbcupid_GLYPH_C6/pins_arduino.h new file mode 100644 index 0000000..223afbc --- /dev/null +++ b/variants/Pcbcupid_GLYPH_C6/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 14; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +//MSR Used in on-board battery measurement +static const uint8_t BAT_MEASURE = 0; +#define BAT_VOLT_PIN BAT_MEASURE +#define MSR BAT_MEASURE + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 20; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 23; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D14 = 14; +static const uint8_t D15 = 15; +static const uint8_t D16 = 16; +static const uint8_t D17 = 17; +static const uint8_t D18 = 18; +static const uint8_t D19 = 19; +static const uint8_t D20 = 20; +static const uint8_t D21 = 21; +static const uint8_t D22 = 22; +static const uint8_t D23 = 23; + +#endif /* Pins_Arduino_h */ diff --git a/variants/Pcbcupid_GLYPH_H2/pins_arduino.h b/variants/Pcbcupid_GLYPH_H2/pins_arduino.h new file mode 100644 index 0000000..edc108a --- /dev/null +++ b/variants/Pcbcupid_GLYPH_H2/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 0; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +//MSR Used in on-board battery measurement +static const uint8_t BAT_MEASURE = 1; +#define BAT_VOLT_PIN BAT_MEASURE +#define MSR BAT_MEASURE + +static const uint8_t TX = 24; +static const uint8_t RX = 23; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 3; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 25; +static const uint8_t SCK = 11; + +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D11 = 11; +static const uint8_t D12 = 12; +static const uint8_t D13 = 13; +static const uint8_t D14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/S_ODI_Ultra_v1/pins_arduino.h b/variants/S_ODI_Ultra_v1/pins_arduino.h new file mode 100644 index 0000000..430ae8b --- /dev/null +++ b/variants/S_ODI_Ultra_v1/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +static const uint8_t LED_BUILTINB = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define BUILTIN_LED2 LED_BUILTINB + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ + +/* compatible with SPELEC S.ODI Ultra v1.0 (based on ESP32 Series)*/ diff --git a/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h b/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h new file mode 100644 index 0000000..564c9fe --- /dev/null +++ b/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t TX1 = 0; +static const uint8_t RX1 = 1; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 20; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 9; +static const uint8_t SCK = 8; + +static const uint8_t A0 = 2; +static const uint8_t A1 = 3; +static const uint8_t A2 = 4; +static const uint8_t A3 = 5; + +static const uint8_t D0 = 2; +static const uint8_t D1 = 3; +static const uint8_t D2 = 4; +static const uint8_t D3 = 5; +static const uint8_t D4 = 6; +static const uint8_t D5 = 7; +static const uint8_t D6 = 21; +static const uint8_t D7 = 20; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +static const uint8_t GPIO_IIC_DATA = 5; +static const uint8_t GPIO_IIC_CLOCK = 6; +static const uint8_t GPIO_PWRKEY = 7; +static const uint8_t GPIO_GSM_ENABLE = 10; +static const uint8_t GPIO_TPS_ENABLE = 4; +static const uint8_t GPIO_INT1 = 3; +static const uint8_t GPIO_ANALOG_IN = 2; +static const uint8_t GPIO_SOS = 9; +static const uint8_t GPIO_CHG_IN = 4; +static const uint8_t GPIO_LED_SIGNAL = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h b/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h new file mode 100644 index 0000000..564c9fe --- /dev/null +++ b/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t TX1 = 0; +static const uint8_t RX1 = 1; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 20; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 9; +static const uint8_t SCK = 8; + +static const uint8_t A0 = 2; +static const uint8_t A1 = 3; +static const uint8_t A2 = 4; +static const uint8_t A3 = 5; + +static const uint8_t D0 = 2; +static const uint8_t D1 = 3; +static const uint8_t D2 = 4; +static const uint8_t D3 = 5; +static const uint8_t D4 = 6; +static const uint8_t D5 = 7; +static const uint8_t D6 = 21; +static const uint8_t D7 = 20; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +static const uint8_t GPIO_IIC_DATA = 5; +static const uint8_t GPIO_IIC_CLOCK = 6; +static const uint8_t GPIO_PWRKEY = 7; +static const uint8_t GPIO_GSM_ENABLE = 10; +static const uint8_t GPIO_TPS_ENABLE = 4; +static const uint8_t GPIO_INT1 = 3; +static const uint8_t GPIO_ANALOG_IN = 2; +static const uint8_t GPIO_SOS = 9; +static const uint8_t GPIO_CHG_IN = 4; +static const uint8_t GPIO_LED_SIGNAL = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ViraLink-G0.1/pins_arduino.h b/variants/ViraLink-G0.1/pins_arduino.h new file mode 100644 index 0000000..7e11a91 --- /dev/null +++ b/variants/ViraLink-G0.1/pins_arduino.h @@ -0,0 +1,46 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t RESET_KEY = 0; + +static const uint8_t RS485_TX = 32; +static const uint8_t RS485_RX = 35; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 16; + +static const uint8_t BUZZER = 12; +static const uint8_t RELAY1_PIN = 2; +static const uint8_t RELAY2_PIN = 13; +static const uint8_t RELAY3_PIN = 14; +static const uint8_t RELAY4_PIN = 33; + +static const uint8_t Wiegand1_D0 = 15; +static const uint8_t Wiegand1_D1 = 34; + +static const uint8_t Wiegand2_D0 = 39; +static const uint8_t Wiegand2_D1 = 36; + +static const uint8_t ETH_CLK_OUT = 17; + +static const uint8_t EMAC_MDIO = 18; +static const uint8_t EMAC_TXD0 = 19; +static const uint8_t EMAC_TX_EN = 21; +static const uint8_t EMAC_TXD1 = 22; +static const uint8_t EMAC_MDC = 23; +static const uint8_t EMAC_RXD0 = 25; +static const uint8_t EMAC_RXD1 = 26; +static const uint8_t EMAC_RXD_DV = 27; + +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ViraLink-G1.1/pins_arduino.h b/variants/ViraLink-G1.1/pins_arduino.h new file mode 100644 index 0000000..e509b0d --- /dev/null +++ b/variants/ViraLink-G1.1/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t RESET_KEY = 0; + +static const uint8_t RF433 = 5; + +static const uint8_t RS485_TX = 32; +static const uint8_t RS485_RX = 35; + +static const uint8_t GSM1_TX = 15; +static const uint8_t GSM1_RX = 34; + +static const uint8_t GSM2_TX = 32; +static const uint8_t GSM2_RX = 35; + +static const uint8_t GSM_PWR = 33; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 16; + +static const uint8_t EXT1 = 12; +static const uint8_t EXT2 = 13; +static const uint8_t PCF1_INT = 14; + +static const uint8_t Wiegand1_D0 = 15; +static const uint8_t Wiegand1_D1 = 34; + +static const uint8_t Wiegand2_D0 = 39; +static const uint8_t Wiegand2_D1 = 36; + +static const uint8_t ETH_CLK_OUT = 17; + +static const uint8_t EMAC_MDIO = 18; +static const uint8_t EMAC_TXD0 = 19; +static const uint8_t EMAC_TX_EN = 21; +static const uint8_t EMAC_TXD1 = 22; +static const uint8_t EMAC_MDC = 23; +static const uint8_t EMAC_RXD0 = 25; +static const uint8_t EMAC_RXD1 = 26; +static const uint8_t EMAC_RXD_DV = 27; + +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32C3/pins_arduino.h b/variants/XIAO_ESP32C3/pins_arduino.h new file mode 100644 index 0000000..061e743 --- /dev/null +++ b/variants/XIAO_ESP32C3/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 20; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 9; +static const uint8_t SCK = 8; + +static const uint8_t A0 = 2; +static const uint8_t A1 = 3; +static const uint8_t A2 = 4; + +static const uint8_t D0 = 2; +static const uint8_t D1 = 3; +static const uint8_t D2 = 4; +static const uint8_t D3 = 5; +static const uint8_t D4 = 6; +static const uint8_t D5 = 7; +static const uint8_t D6 = 21; +static const uint8_t D7 = 20; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32C5/pins_arduino.h b/variants/XIAO_ESP32C5/pins_arduino.h new file mode 100644 index 0000000..a955994 --- /dev/null +++ b/variants/XIAO_ESP32C5/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x2886 +#define USB_PID 0x0067 + +static const uint8_t LED_BUILTIN = 27; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 11; +static const uint8_t RX = 12; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 24; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 9; +static const uint8_t SCK = 8; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; + +static const uint8_t D0 = 1; +static const uint8_t D1 = 0; +static const uint8_t D2 = 25; +static const uint8_t D3 = 7; +static const uint8_t D4 = 23; +static const uint8_t D5 = 24; +static const uint8_t D6 = 11; +static const uint8_t D7 = 12; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +static const uint8_t BAT_VOLT_PIN = 6; +static const uint8_t BAT_VOLT_PIN_EN = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32C6/pins_arduino.h b/variants/XIAO_ESP32C6/pins_arduino.h new file mode 100644 index 0000000..c90a339 --- /dev/null +++ b/variants/XIAO_ESP32C6/pins_arduino.h @@ -0,0 +1,47 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x2886 +#define USB_PID 0x0048 +#define USB_MANUFACTURER "Seeed Studio" +#define USB_PRODUCT "XIAO ESP32-C6" +#define USB_SERIAL "" + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 22; +static const uint8_t SCL = 23; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 20; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 21; +static const uint8_t D4 = 22; +static const uint8_t D5 = 23; +static const uint8_t D6 = 16; +static const uint8_t D7 = 17; +static const uint8_t D8 = 19; +static const uint8_t D9 = 20; +static const uint8_t D10 = 18; + +static const uint8_t WIFI_ENABLE = 3; +static const uint8_t WIFI_ANT_CONFIG = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32C6/variant.cpp b/variants/XIAO_ESP32C6/variant.cpp new file mode 100644 index 0000000..07bd848 --- /dev/null +++ b/variants/XIAO_ESP32C6/variant.cpp @@ -0,0 +1,21 @@ +/* +*By setting the WIFI_ENABLE and WIFI_ANT_CONFIG pins, +* +*the XIAO_ESP32C6 will turn on the on-board antenna by default after power-on +* +*https://wiki.seeedstudio.com/xiao_esp32c6_getting_started/ +*/ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +void initVariant(void) { + pinMode(WIFI_ENABLE, OUTPUT); + digitalWrite(WIFI_ENABLE, LOW); //turn on this function + + pinMode(WIFI_ANT_CONFIG, OUTPUT); + digitalWrite(WIFI_ANT_CONFIG, LOW); //use built-in antenna, set HIGH to use external antenna +} +} diff --git a/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin b/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..465e294 Binary files /dev/null and b/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin differ diff --git a/variants/XIAO_ESP32S3/partitions-8MB.csv b/variants/XIAO_ESP32S3/partitions-8MB.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/XIAO_ESP32S3/partitions-8MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/XIAO_ESP32S3/pins_arduino.h b/variants/XIAO_ESP32S3/pins_arduino.h new file mode 100644 index 0000000..b019fd2 --- /dev/null +++ b/variants/XIAO_ESP32S3/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x2886 +#define USB_PID 0x0056 + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 44; +static const uint8_t MOSI = 9; +static const uint8_t MISO = 8; +static const uint8_t SCK = 7; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A8 = 7; +static const uint8_t A9 = 8; +static const uint8_t A10 = 9; + +static const uint8_t D0 = 1; +static const uint8_t D1 = 2; +static const uint8_t D2 = 3; +static const uint8_t D3 = 4; +static const uint8_t D4 = 5; +static const uint8_t D5 = 6; +static const uint8_t D6 = 43; +static const uint8_t D7 = 44; +static const uint8_t D8 = 7; +static const uint8_t D9 = 8; +static const uint8_t D10 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32S3/tinyuf2.bin b/variants/XIAO_ESP32S3/tinyuf2.bin new file mode 100644 index 0000000..95d1c4c Binary files /dev/null and b/variants/XIAO_ESP32S3/tinyuf2.bin differ diff --git a/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin b/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin new file mode 100644 index 0000000..465e294 Binary files /dev/null and b/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin differ diff --git a/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv b/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/XIAO_ESP32S3_Plus/pins_arduino.h b/variants/XIAO_ESP32S3_Plus/pins_arduino.h new file mode 100644 index 0000000..ba7d1a5 --- /dev/null +++ b/variants/XIAO_ESP32S3_Plus/pins_arduino.h @@ -0,0 +1,91 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x2886 +#define USB_PID 0x0063 + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TX1 = 42; +static const uint8_t RX1 = 41; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 44; +static const uint8_t MOSI = 9; +static const uint8_t MISO = 8; +static const uint8_t SCK = 7; + +static const uint8_t MOSI1 = 11; +static const uint8_t MISO1 = 12; +static const uint8_t SCK1 = 13; + +static const uint8_t I2S_SCK = 39; +static const uint8_t I2S_SD = 38; +static const uint8_t I2S_WS = 40; + +static const uint8_t MTCK = 39; +static const uint8_t MTDO = 40; +static const uint8_t MTDI = 41; +static const uint8_t MTMS = 42; + +static const uint8_t DVP_Y8 = 11; +static const uint8_t DVP_YP = 12; +static const uint8_t DVP_PCLK = 13; +static const uint8_t DVP_VSYNC = 38; +static const uint8_t CAM_SCL = 39; +static const uint8_t CAM_SDA = 40; +static const uint8_t XMCLK = 10; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A8 = 7; +static const uint8_t A9 = 8; +static const uint8_t A10 = 9; +static const uint8_t ADC_BAT = 10; +#define BAT_VOLT_PIN ADC_BAT + +static const uint8_t D0 = 1; +static const uint8_t D1 = 2; +static const uint8_t D2 = 3; +static const uint8_t D3 = 4; +static const uint8_t D4 = 5; +static const uint8_t D5 = 6; +static const uint8_t D6 = 43; +static const uint8_t D7 = 44; +static const uint8_t D8 = 7; +static const uint8_t D9 = 8; +static const uint8_t D10 = 9; +static const uint8_t D11 = 38; +static const uint8_t D12 = 39; +static const uint8_t D13 = 40; +static const uint8_t D14 = 41; +static const uint8_t D15 = 42; +static const uint8_t D16 = 10; +static const uint8_t D17 = 13; +static const uint8_t D18 = 12; +static const uint8_t D19 = 11; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +#endif /* Pins_Arduino_h */ diff --git a/variants/XIAO_ESP32S3_Plus/tinyuf2.bin b/variants/XIAO_ESP32S3_Plus/tinyuf2.bin new file mode 100644 index 0000000..95d1c4c Binary files /dev/null and b/variants/XIAO_ESP32S3_Plus/tinyuf2.bin differ diff --git a/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..65cadaf Binary files /dev/null and b/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_camera_esp32s3/pins_arduino.h b/variants/adafruit_camera_esp32s3/pins_arduino.h new file mode 100644 index 0000000..16dd31d --- /dev/null +++ b/variants/adafruit_camera_esp32s3/pins_arduino.h @@ -0,0 +1,83 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8117 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Camera ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t PIN_NEOPIXEL = 1; +static const uint8_t NEOPIXEL_PIN = 1; + +//By making LED_BUILTIN have the same value of RGB_BUILTIN +//NeoPixel LED can also be used as LED_BUILTIN with digitalMode() + digitalWrite() +static const uint8_t LED_BUILTIN = PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t TFT_BACKLIGHT = 45; +static const uint8_t TFT_DC = 40; +static const uint8_t TFT_CS = 39; +static const uint8_t TFT_RESET = 38; +static const uint8_t TFT_RST = 38; + +static const uint8_t SD_CS = 48; +static const uint8_t SD_CHIP_SELECT = 48; +static const uint8_t SPEAKER = 46; + +static const uint8_t SCL = 33; +static const uint8_t SDA = 34; + +static const uint8_t SS = 48; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t BATT_MONITOR = 4; +#define BAT_VOLT_PIN BATT_MONITOR +static const uint8_t SHUTTER_BUTTON = 0; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#define AWEXP_SPKR_SD 0 +#define AWEXP_BUTTON_SEL 1 +#define AWEXP_SD_DET 8 +#define AWEXP_SD_PWR 9 +#define AWEXP_BUTTON_OK 11 +#define AWEXP_BUTTON_RIGHT 12 +#define AWEXP_BUTTON_UP 13 +#define AWEXP_BUTTON_LEFT 14 +#define AWEXP_BUTTON_DOWN 15 + +#define RESET_GPIO_NUM 47 +#define PWDN_GPIO_NUM 21 +#define XCLK_GPIO_NUM 8 +#define SIOD_GPIO_NUM SDA +#define SIOC_GPIO_NUM SCL + +#define Y9_GPIO_NUM 7 +#define Y8_GPIO_NUM 9 +#define Y7_GPIO_NUM 10 +#define Y6_GPIO_NUM 12 +#define Y5_GPIO_NUM 14 +#define Y4_GPIO_NUM 16 +#define Y3_GPIO_NUM 15 +#define Y2_GPIO_NUM 13 +#define VSYNC_GPIO_NUM 5 +#define HREF_GPIO_NUM 6 +#define PCLK_GPIO_NUM 11 + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_camera_esp32s3/tinyuf2.bin b/variants/adafruit_camera_esp32s3/tinyuf2.bin new file mode 100644 index 0000000..b1b4931 Binary files /dev/null and b/variants/adafruit_camera_esp32s3/tinyuf2.bin differ diff --git a/variants/adafruit_camera_esp32s3/variant.cpp b/variants/adafruit_camera_esp32s3/variant.cpp new file mode 100644 index 0000000..4655d30 --- /dev/null +++ b/variants/adafruit_camera_esp32s3/variant.cpp @@ -0,0 +1,43 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + pinMode(TFT_BACKLIGHT, OUTPUT); + digitalWrite(TFT_BACKLIGHT, LOW); + pinMode(SD_CS, OUTPUT); + digitalWrite(SD_CS, HIGH); + pinMode(TFT_CS, OUTPUT); + digitalWrite(TFT_CS, HIGH); + pinMode(TFT_RESET, OUTPUT); + digitalWrite(TFT_RESET, LOW); + delay(1); + digitalWrite(TFT_RESET, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32_v2/pins_arduino.h b/variants/adafruit_feather_esp32_v2/pins_arduino.h new file mode 100644 index 0000000..1b95efd --- /dev/null +++ b/variants/adafruit_feather_esp32_v2/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t TX = 8; +static const uint8_t RX = 7; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 22; +static const uint8_t SCL = 20; + +static const uint8_t SS = 33; +static const uint8_t MOSI = 19; +static const uint8_t MISO = 21; +static const uint8_t SCK = 5; + +// mapping to match other feathers and also in order +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 34; +static const uint8_t A3 = 39; +static const uint8_t A4 = 36; +static const uint8_t A5 = 4; +static const uint8_t A6 = 14; +static const uint8_t A7 = 32; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 35; + +// vbat measure +#define BATT_MONITOR 35 +#define BAT_VOLT_PIN BATT_MONITOR + +// internal switch +#define BUTTON 38 + +// User LED +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Neopixel +#define PIN_NEOPIXEL 0 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +// Neopixel & I2C power +#define NEOPIXEL_I2C_POWER 2 + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32_v2/variant.cpp b/variants/adafruit_feather_esp32_v2/variant.cpp new file mode 100644 index 0000000..576afb6 --- /dev/null +++ b/variants/adafruit_feather_esp32_v2/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels & I2C + pinMode(NEOPIXEL_I2C_POWER, OUTPUT); + digitalWrite(NEOPIXEL_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32c6/pins_arduino.h b/variants/adafruit_feather_esp32c6/pins_arduino.h new file mode 100644 index 0000000..c4ae4ba --- /dev/null +++ b/variants/adafruit_feather_esp32c6/pins_arduino.h @@ -0,0 +1,38 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_NEOPIXEL 9 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_I2C_POWER 20 // I2C power pin +#define PIN_NEOPIXEL_I2C_POWER 20 // I2C power pin + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 19; +static const uint8_t SCL = 18; + +static const uint8_t SS = 0; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 23; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 4; +static const uint8_t A2 = 6; +static const uint8_t A3 = 5; +static const uint8_t A4 = 3; +static const uint8_t A5 = 2; +static const uint8_t A6 = 0; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32c6/variant.cpp b/variants/adafruit_feather_esp32c6/variant.cpp new file mode 100644 index 0000000..576afb6 --- /dev/null +++ b/variants/adafruit_feather_esp32c6/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels & I2C + pinMode(NEOPIXEL_I2C_POWER, OUTPUT); + digitalWrite(NEOPIXEL_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..c87c70a Binary files /dev/null and b/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2/pins_arduino.h b/variants/adafruit_feather_esp32s2/pins_arduino.h new file mode 100644 index 0000000..72ab65a --- /dev/null +++ b/variants/adafruit_feather_esp32s2/pins_arduino.h @@ -0,0 +1,62 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80EB +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on +#define I2C_POWER 7 // I2C power pin +#define PIN_I2C_POWER 7 // I2C power pin + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s2/tinyuf2.bin b/variants/adafruit_feather_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..f74a612 Binary files /dev/null and b/variants/adafruit_feather_esp32s2/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2/variant.cpp b/variants/adafruit_feather_esp32s2/variant.cpp new file mode 100644 index 0000000..56d9ea0 --- /dev/null +++ b/variants/adafruit_feather_esp32s2/variant.cpp @@ -0,0 +1,44 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + + // turn on the I2C power by setting pin to opposite of 'rest state' + pinMode(PIN_I2C_POWER, INPUT); + delay(1); + bool polarity = digitalRead(PIN_I2C_POWER); + pinMode(PIN_I2C_POWER, OUTPUT); + digitalWrite(PIN_I2C_POWER, !polarity); +} +} diff --git a/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin new file mode 100644 index 0000000..bb4b220 Binary files /dev/null and b/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h b/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h new file mode 100644 index 0000000..92902cc --- /dev/null +++ b/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80ED +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S2 Reverse TFT" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +#define TFT_I2C_POWER 7 +#define TFT_CS 42 +#define TFT_RST 41 +#define TFT_DC 40 +#define TFT_BACKLITE 45 + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin b/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin new file mode 100644 index 0000000..249593b Binary files /dev/null and b/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2_reversetft/variant.cpp b/variants/adafruit_feather_esp32s2_reversetft/variant.cpp new file mode 100644 index 0000000..403faaa --- /dev/null +++ b/variants/adafruit_feather_esp32s2_reversetft/variant.cpp @@ -0,0 +1,39 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has power control pins, and we must set them to output and high + // in order to enable the NeoPixels, TFT & I2C + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + pinMode(TFT_I2C_POWER, OUTPUT); + digitalWrite(TFT_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin new file mode 100644 index 0000000..3d1c246 Binary files /dev/null and b/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2_tft/pins_arduino.h b/variants/adafruit_feather_esp32s2_tft/pins_arduino.h new file mode 100644 index 0000000..8c3059a --- /dev/null +++ b/variants/adafruit_feather_esp32s2_tft/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x810F +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S2 TFT" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 34 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +#define TFT_I2C_POWER 21 +#define TFT_CS 7 +#define TFT_RST 40 +#define TFT_DC 39 +#define TFT_BACKLITE 45 + +static const uint8_t SDA = 42; +static const uint8_t SCL = 41; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 1; +static const uint8_t RX = 2; +#define TX1 TX +#define RX1 RX + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin b/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin new file mode 100644 index 0000000..839edd1 Binary files /dev/null and b/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s2_tft/variant.cpp b/variants/adafruit_feather_esp32s2_tft/variant.cpp new file mode 100644 index 0000000..403faaa --- /dev/null +++ b/variants/adafruit_feather_esp32s2_tft/variant.cpp @@ -0,0 +1,39 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has power control pins, and we must set them to output and high + // in order to enable the NeoPixels, TFT & I2C + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + pinMode(TFT_I2C_POWER, OUTPUT); + digitalWrite(TFT_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..f731239 Binary files /dev/null and b/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3/pins_arduino.h b/variants/adafruit_feather_esp32s3/pins_arduino.h new file mode 100644 index 0000000..991a57c --- /dev/null +++ b/variants/adafruit_feather_esp32s3/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x811B +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on +#define I2C_POWER 7 // I2C power pin +#define PIN_I2C_POWER 7 // I2C power pin + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; +static const uint8_t A6 = 3; +static const uint8_t A7 = 4; +static const uint8_t A8 = 5; +static const uint8_t A9 = 6; +static const uint8_t A10 = 9; +static const uint8_t A11 = 10; +static const uint8_t A12 = 11; +static const uint8_t A13 = 12; +static const uint8_t A14 = 13; + +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s3/tinyuf2.bin b/variants/adafruit_feather_esp32s3/tinyuf2.bin new file mode 100644 index 0000000..62d0b6b Binary files /dev/null and b/variants/adafruit_feather_esp32s3/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3/variant.cpp b/variants/adafruit_feather_esp32s3/variant.cpp new file mode 100644 index 0000000..e431b7c --- /dev/null +++ b/variants/adafruit_feather_esp32s3/variant.cpp @@ -0,0 +1,41 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + + // turn on the I2C power by setting LDO enable pin 'high' + pinMode(PIN_I2C_POWER, OUTPUT); + digitalWrite(PIN_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin new file mode 100644 index 0000000..199cdab Binary files /dev/null and b/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h b/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h new file mode 100644 index 0000000..34fe2eb --- /dev/null +++ b/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8113 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S3 No PSRAM" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on +#define I2C_POWER 7 // I2C power pin +#define PIN_I2C_POWER 7 // I2C power pin + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; +static const uint8_t A6 = 3; +static const uint8_t A7 = 4; +static const uint8_t A8 = 5; +static const uint8_t A9 = 6; +static const uint8_t A10 = 9; +static const uint8_t A11 = 10; +static const uint8_t A12 = 11; +static const uint8_t A13 = 12; +static const uint8_t A14 = 13; + +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin b/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin new file mode 100644 index 0000000..dda6636 Binary files /dev/null and b/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_nopsram/variant.cpp b/variants/adafruit_feather_esp32s3_nopsram/variant.cpp new file mode 100644 index 0000000..e431b7c --- /dev/null +++ b/variants/adafruit_feather_esp32s3_nopsram/variant.cpp @@ -0,0 +1,41 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + + // turn on the I2C power by setting LDO enable pin 'high' + pinMode(PIN_I2C_POWER, OUTPUT); + digitalWrite(PIN_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin new file mode 100644 index 0000000..e822c1f Binary files /dev/null and b/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h b/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h new file mode 100644 index 0000000..ea955ff --- /dev/null +++ b/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8123 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S3 Reverse TFT" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +#define TFT_I2C_POWER 7 +#define TFT_CS 42 +#define TFT_RST 41 +#define TFT_DC 40 +#define TFT_BACKLITE 45 + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin b/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin new file mode 100644 index 0000000..86345d6 Binary files /dev/null and b/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_reversetft/variant.cpp b/variants/adafruit_feather_esp32s3_reversetft/variant.cpp new file mode 100644 index 0000000..403faaa --- /dev/null +++ b/variants/adafruit_feather_esp32s3_reversetft/variant.cpp @@ -0,0 +1,39 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has power control pins, and we must set them to output and high + // in order to enable the NeoPixels, TFT & I2C + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + pinMode(TFT_I2C_POWER, OUTPUT); + digitalWrite(TFT_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin new file mode 100644 index 0000000..2ab3ebc Binary files /dev/null and b/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_tft/pins_arduino.h b/variants/adafruit_feather_esp32s3_tft/pins_arduino.h new file mode 100644 index 0000000..3e007c7 --- /dev/null +++ b/variants/adafruit_feather_esp32s3_tft/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x811D +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Feather ESP32-S3 TFT" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 34 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +#define TFT_I2C_POWER 21 +#define TFT_CS 7 +#define TFT_RST 40 +#define TFT_DC 39 +#define TFT_BACKLITE 45 + +static const uint8_t SDA = 42; +static const uint8_t SCL = 41; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 1; +static const uint8_t RX = 2; +#define TX1 TX +#define RX1 RX + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin b/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin new file mode 100644 index 0000000..035ba42 Binary files /dev/null and b/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin differ diff --git a/variants/adafruit_feather_esp32s3_tft/variant.cpp b/variants/adafruit_feather_esp32s3_tft/variant.cpp new file mode 100644 index 0000000..403faaa --- /dev/null +++ b/variants/adafruit_feather_esp32s3_tft/variant.cpp @@ -0,0 +1,39 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has power control pins, and we must set them to output and high + // in order to enable the NeoPixels, TFT & I2C + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); + pinMode(TFT_I2C_POWER, OUTPUT); + digitalWrite(TFT_I2C_POWER, HIGH); +} +} diff --git a/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..e4146b1 Binary files /dev/null and b/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_funhouse_esp32s2/pins_arduino.h b/variants/adafruit_funhouse_esp32s2/pins_arduino.h new file mode 100644 index 0000000..d9faac7 --- /dev/null +++ b/variants/adafruit_funhouse_esp32s2/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80F9 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Funhouse ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +#define LED_BUILTIN 37 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +#define PIN_BUTTON1 3 +#define PIN_BUTTON2 4 +#define PIN_BUTTON3 5 +#define PIN_BUTTON4 0 // BOOT0 switch + +static const uint8_t PIN_DOTSTAR_DATA = 14; +static const uint8_t PIN_DOTSTAR_CLOCK = 15; + +static const uint8_t TFT_BACKLIGHT = 21; +static const uint8_t TFT_DC = 39; +static const uint8_t TFT_CS = 40; +static const uint8_t TFT_RESET = 41; + +static const uint8_t SPEAKER = 42; +static const uint8_t BUTTON_DOWN = PIN_BUTTON1; +static const uint8_t BUTTON_SELECT = PIN_BUTTON2; +static const uint8_t BUTTON_UP = PIN_BUTTON3; +static const uint8_t SENSOR_PIR = 16; +static const uint8_t SENSOR_LIGHT = 18; + +static const uint8_t SDA = 34; +static const uint8_t SCL = 33; + +static const uint8_t SS = 40; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 2; +static const uint8_t A2 = 1; +static const uint8_t A3 = 18; // light sensor + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_funhouse_esp32s2/tinyuf2.bin b/variants/adafruit_funhouse_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..1e75fb3 Binary files /dev/null and b/variants/adafruit_funhouse_esp32s2/tinyuf2.bin differ diff --git a/variants/adafruit_funhouse_esp32s2/variant.cpp b/variants/adafruit_funhouse_esp32s2/variant.cpp new file mode 100644 index 0000000..971bf53 --- /dev/null +++ b/variants/adafruit_funhouse_esp32s2/variant.cpp @@ -0,0 +1,32 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) {} +} diff --git a/variants/adafruit_itsybitsy_esp32/pins_arduino.h b/variants/adafruit_itsybitsy_esp32/pins_arduino.h new file mode 100644 index 0000000..801dc15 --- /dev/null +++ b/variants/adafruit_itsybitsy_esp32/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// User LED +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Neopixel +static const uint8_t PIN_NEOPIXEL = 0; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t NEOPIXEL_POWER = 2; + +static const uint8_t TX = 20; +static const uint8_t RX = 8; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 15; +static const uint8_t SCL = 27; + +static const uint8_t SS = 32; +static const uint8_t MOSI = 21; +static const uint8_t MISO = 22; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 25; +static const uint8_t A1 = 26; +static const uint8_t A2 = 4; +static const uint8_t A3 = 38; +static const uint8_t A4 = 37; +static const uint8_t A5 = 36; + +// internal switch +static const uint8_t BUTTON = 35; + +static const uint8_t T0 = 4; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_itsybitsy_esp32/variant.cpp b/variants/adafruit_itsybitsy_esp32/variant.cpp new file mode 100644 index 0000000..7809ec2 --- /dev/null +++ b/variants/adafruit_itsybitsy_esp32/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); +} +} diff --git a/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..5f5afe5 Binary files /dev/null and b/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_magtag29_esp32s2/pins_arduino.h b/variants/adafruit_magtag29_esp32s2/pins_arduino.h new file mode 100644 index 0000000..8e3d2c8 --- /dev/null +++ b/variants/adafruit_magtag29_esp32s2/pins_arduino.h @@ -0,0 +1,89 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80E5 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "EPD MagTag 2.9\" ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 1 // D1 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 4 // number of neopixels +#define NEOPIXEL_POWER 21 // power pin +#define NEOPIXEL_POWER_ON LOW // power pin state when on + +#define PIN_BUTTON1 15 +#define PIN_BUTTON2 14 +#define PIN_BUTTON3 12 +#define PIN_BUTTON4 11 +#define PIN_BUTTON5 0 // BOOT0 switch + +static const uint8_t EPD_BUSY = 5; +static const uint8_t EPD_RESET = 6; +static const uint8_t EPD_DC = 7; +static const uint8_t EPD_CS = 8; + +static const uint8_t ACCEL_IRQ = 9; + +static const uint8_t BUTTON_A = PIN_BUTTON1; +static const uint8_t BUTTON_B = PIN_BUTTON2; +static const uint8_t BUTTON_C = PIN_BUTTON3; +static const uint8_t BUTTON_D = PIN_BUTTON4; + +static const uint8_t LIGHT_SENSOR = 3; +static const uint8_t BATT_MONITOR = 4; +#define BAT_VOLT_PIN BATT_MONITOR +static const uint8_t SPEAKER_SHUTDOWN = 16; + +static const uint8_t SDA = 33; +static const uint8_t SCL = 34; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 1; +static const uint8_t A3 = 2; +static const uint8_t A4 = 3; +static const uint8_t A5 = 4; +static const uint8_t A6 = 5; +static const uint8_t A7 = 6; +static const uint8_t A8 = 7; +static const uint8_t A9 = 8; +static const uint8_t A10 = 9; +static const uint8_t A11 = 10; +static const uint8_t A12 = 11; +static const uint8_t A13 = 12; +static const uint8_t A14 = 13; +static const uint8_t A15 = 14; +static const uint8_t A16 = 15; +static const uint8_t A17 = 16; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T10 = 10; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_magtag29_esp32s2/tinyuf2.bin b/variants/adafruit_magtag29_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..5b1c92e Binary files /dev/null and b/variants/adafruit_magtag29_esp32s2/tinyuf2.bin differ diff --git a/variants/adafruit_magtag29_esp32s2/variant.cpp b/variants/adafruit_magtag29_esp32s2/variant.cpp new file mode 100644 index 0000000..971bf53 --- /dev/null +++ b/variants/adafruit_magtag29_esp32s2/variant.cpp @@ -0,0 +1,32 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) {} +} diff --git a/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..ed3a4aa Binary files /dev/null and b/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_matrixportal_esp32s3/pins_arduino.h b/variants/adafruit_matrixportal_esp32s3/pins_arduino.h new file mode 100644 index 0000000..9843c54 --- /dev/null +++ b/variants/adafruit_matrixportal_esp32s3/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8125 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "MatrixPortal ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +#define PIN_NEOPIXEL 4 +#define NEOPIXEL_PIN 4 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 +#define PIN_LIGHTSENSOR A5 + +#define PIN_BUTTON_UP 6 +#define PIN_BUTTON_DOWN 7 + +static const uint8_t TX = 18; +static const uint8_t RX = 8; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 16; +static const uint8_t SCL = 17; + +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + +static const uint8_t A0 = 12; +static const uint8_t A1 = 3; +static const uint8_t A2 = 9; +static const uint8_t A3 = 10; +static const uint8_t A4 = 11; +static const uint8_t A5 = 5; // Light + +static const uint8_t T3 = 3; // Touch pin IDs map directly +static const uint8_t T8 = 8; // to underlying GPIO numbers NOT +static const uint8_t T9 = 9; // the analog numbers on board silk +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin b/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin new file mode 100644 index 0000000..d671d11 Binary files /dev/null and b/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin differ diff --git a/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..434a61c Binary files /dev/null and b/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_metro_esp32s2/pins_arduino.h b/variants/adafruit_metro_esp32s2/pins_arduino.h new file mode 100644 index 0000000..cef937d --- /dev/null +++ b/variants/adafruit_metro_esp32s2/pins_arduino.h @@ -0,0 +1,78 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80DF +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Metro ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +#define LED_BUILTIN 42 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 45 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 + +#define PIN_BUTTON1 0 // BOOT0 switch + +static const uint8_t TX = 5; +static const uint8_t RX = 6; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 33; +static const uint8_t SCL = 34; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 1; +static const uint8_t A3 = 2; +static const uint8_t A4 = 3; +static const uint8_t A5 = 4; +static const uint8_t A6 = 5; +static const uint8_t A7 = 6; +static const uint8_t A8 = 7; +static const uint8_t A9 = 8; +static const uint8_t A10 = 9; +static const uint8_t A11 = 10; +static const uint8_t A12 = 11; +static const uint8_t A13 = 12; +static const uint8_t A14 = 13; +static const uint8_t A15 = 14; +static const uint8_t A16 = 15; +static const uint8_t A17 = 16; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_metro_esp32s2/tinyuf2.bin b/variants/adafruit_metro_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..4350be6 Binary files /dev/null and b/variants/adafruit_metro_esp32s2/tinyuf2.bin differ diff --git a/variants/adafruit_metro_esp32s2/variant.cpp b/variants/adafruit_metro_esp32s2/variant.cpp new file mode 100644 index 0000000..971bf53 --- /dev/null +++ b/variants/adafruit_metro_esp32s2/variant.cpp @@ -0,0 +1,32 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) {} +} diff --git a/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..0ef7720 Binary files /dev/null and b/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_metro_esp32s3/pins_arduino.h b/variants/adafruit_metro_esp32s3/pins_arduino.h new file mode 100644 index 0000000..9e2cff7 --- /dev/null +++ b/variants/adafruit_metro_esp32s3/pins_arduino.h @@ -0,0 +1,76 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8145 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Metro ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// Neopixel +#define PIN_NEOPIXEL 46 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 + +#define PIN_BUTTON1 0 // BOOT0 switch + +static const uint8_t TX = 40; +static const uint8_t RX = 41; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 47; +static const uint8_t SCL = 48; + +static const uint8_t SS = 45; +static const uint8_t MOSI = 42; +static const uint8_t SCK = 39; +static const uint8_t MISO = 21; + +static const uint8_t A0 = 14; +static const uint8_t A1 = 15; +static const uint8_t A2 = 16; +static const uint8_t A3 = 17; +static const uint8_t A4 = 18; +static const uint8_t A5 = 1; + +static const uint8_t A6 = 40; +static const uint8_t A7 = 41; +static const uint8_t A8 = 2; +static const uint8_t A9 = 3; +static const uint8_t A10 = 4; +static const uint8_t A11 = 5; +static const uint8_t A12 = 6; +static const uint8_t A13 = 7; +static const uint8_t A14 = 8; +static const uint8_t A15 = 9; +static const uint8_t A16 = 10; +static const uint8_t A17 = 11; +static const uint8_t A18 = 12; +static const uint8_t A19 = 13; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_metro_esp32s3/tinyuf2.bin b/variants/adafruit_metro_esp32s3/tinyuf2.bin new file mode 100644 index 0000000..aea78b0 Binary files /dev/null and b/variants/adafruit_metro_esp32s3/tinyuf2.bin differ diff --git a/variants/adafruit_metro_esp32s3/variant.cpp b/variants/adafruit_metro_esp32s3/variant.cpp new file mode 100644 index 0000000..7adcc6f --- /dev/null +++ b/variants/adafruit_metro_esp32s3/variant.cpp @@ -0,0 +1,36 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // default SD_CS to input pullup (we cannot have built in pullup since its + // a strapping pin!) + pinMode(SS, INPUT_PULLUP); +} +} diff --git a/variants/adafruit_qtpy_esp32/pins_arduino.h b/variants/adafruit_qtpy_esp32/pins_arduino.h new file mode 100644 index 0000000..b422377 --- /dev/null +++ b/variants/adafruit_qtpy_esp32/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// Neopixel +#define PIN_NEOPIXEL 5 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_POWER 8 + +static const uint8_t TX = 32; +static const uint8_t RX = 7; + +#define TX1 32 +#define RX1 7 + +static const uint8_t SDA = 4; +static const uint8_t SCL = 33; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 22; +static const uint8_t SCL1 = 19; + +static const uint8_t SS = 27; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 27; +static const uint8_t A3 = 15; +static const uint8_t A4 = 4; +static const uint8_t A5 = 33; +static const uint8_t A6 = 32; +static const uint8_t A7 = 7; +static const uint8_t A8 = 14; +static const uint8_t A9 = 12; +static const uint8_t A10 = 13; + +static const uint8_t BUTTON = 0; + +static const uint8_t T0 = 4; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qtpy_esp32/variant.cpp b/variants/adafruit_qtpy_esp32/variant.cpp new file mode 100644 index 0000000..7809ec2 --- /dev/null +++ b/variants/adafruit_qtpy_esp32/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); +} +} diff --git a/variants/adafruit_qtpy_esp32c3/pins_arduino.h b/variants/adafruit_qtpy_esp32c3/pins_arduino.h new file mode 100644 index 0000000..92d2591 --- /dev/null +++ b/variants/adafruit_qtpy_esp32c3/pins_arduino.h @@ -0,0 +1,37 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define BUTTON 9 + +// Neopixel +#define PIN_NEOPIXEL 2 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 6; +static const uint8_t MOSI = 7; +static const uint8_t MISO = 8; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 4; +static const uint8_t A1 = 3; +static const uint8_t A2 = 1; +static const uint8_t A3 = 0; +static const uint8_t A4 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..5ce1a3b Binary files /dev/null and b/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s2/pins_arduino.h b/variants/adafruit_qtpy_esp32s2/pins_arduino.h new file mode 100644 index 0000000..3baf080 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s2/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8111 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "QT Py ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +// Neopixel +#define PIN_NEOPIXEL 39 +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 38 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +static const uint8_t SDA = 7; +static const uint8_t SCL = 6; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 41; +static const uint8_t SCL1 = 40; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 9; +static const uint8_t A3 = 8; +static const uint8_t A4 = 7; +static const uint8_t A5 = 6; +static const uint8_t A6 = 5; +static const uint8_t A7 = 16; + +static const uint8_t TX = 5; +static const uint8_t RX = 16; +#define TX1 TX +#define RX1 RX + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qtpy_esp32s2/tinyuf2.bin b/variants/adafruit_qtpy_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..3ce657e Binary files /dev/null and b/variants/adafruit_qtpy_esp32s2/tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s2/variant.cpp b/variants/adafruit_qtpy_esp32s2/variant.cpp new file mode 100644 index 0000000..7809ec2 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s2/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); +} +} diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..e82118a Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h b/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h new file mode 100644 index 0000000..1202ad1 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8143 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "QT Py ESP32-S3 (4MB Flash 2MB PSRAM)" +#define USB_SERIAL "" // Empty string for MAC address + +#define PIN_NEOPIXEL 39 +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 38 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 5; +static const uint8_t RX = 16; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 7; +static const uint8_t SCL = 6; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 41; +static const uint8_t SCL1 = 40; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 9; +static const uint8_t A3 = 8; +static const uint8_t A4 = 7; +static const uint8_t A5 = 6; +static const uint8_t A6 = 5; +static const uint8_t A7 = 16; + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin new file mode 100644 index 0000000..2526253 Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp b/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp new file mode 100644 index 0000000..7809ec2 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); +} +} diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin new file mode 100644 index 0000000..d4e57a7 Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h b/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h new file mode 100644 index 0000000..55b4f43 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x8119 +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "QT Py ESP32-S3 No PSRAM" +#define USB_SERIAL "" // Empty string for MAC address + +#define PIN_NEOPIXEL 39 +#define NEOPIXEL_NUM 1 // number of neopixels +#define NEOPIXEL_POWER 38 // power pin +#define NEOPIXEL_POWER_ON HIGH // power pin state when on + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 5; +static const uint8_t RX = 16; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 7; +static const uint8_t SCL = 6; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 41; +static const uint8_t SCL1 = 40; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 9; +static const uint8_t A3 = 8; +static const uint8_t A4 = 7; +static const uint8_t A5 = 6; +static const uint8_t A6 = 5; +static const uint8_t A7 = 16; + +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin new file mode 100644 index 0000000..328e67b Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin differ diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp b/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp new file mode 100644 index 0000000..7809ec2 --- /dev/null +++ b/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the NeoPixels. + pinMode(NEOPIXEL_POWER, OUTPUT); + digitalWrite(NEOPIXEL_POWER, HIGH); +} +} diff --git a/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin b/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin new file mode 100644 index 0000000..7b6ba14 Binary files /dev/null and b/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin differ diff --git a/variants/adafruit_qualia_s3_rgb666/pins_arduino.h b/variants/adafruit_qualia_s3_rgb666/pins_arduino.h new file mode 100644 index 0000000..da1ed3c --- /dev/null +++ b/variants/adafruit_qualia_s3_rgb666/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x239A +#define USB_PID 0x8147 + +#define USB_MANUFACTURER "Adafruit" +#define USB_PRODUCT "Qualia ESP32-S3 RGB666" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t PCA_TFT_SCK = 0; +static const uint8_t PCA_TFT_CS = 1; +static const uint8_t PCA_TFT_RESET = 2; +static const uint8_t PCA_CPT_IRQ = 3; +static const uint8_t PCA_TFT_BACKLIGHT = 4; +static const uint8_t PCA_BUTTON_UP = 5; +static const uint8_t PCA_BUTTON_DOWN = 6; +static const uint8_t PCA_TFT_MOSI = 7; + +static const uint8_t TX = 16; +static const uint8_t RX = 17; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 8; +static const uint8_t SCL = 18; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 7; +static const uint8_t MISO = 6; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 16; + +static const uint8_t T3 = 3; // Touch pin IDs map directly +static const uint8_t T8 = 8; // to underlying GPIO numbers NOT +static const uint8_t T9 = 9; // the analog numbers on board silk +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; + +static const uint8_t TFT_R1 = 11; +static const uint8_t TFT_R2 = 10; +static const uint8_t TFT_R3 = 9; +static const uint8_t TFT_R4 = 46; +static const uint8_t TFT_R5 = 3; +static const uint8_t TFT_G0 = 48; +static const uint8_t TFT_G1 = 47; +static const uint8_t TFT_G2 = 21; +static const uint8_t TFT_G3 = 14; +static const uint8_t TFT_G4 = 13; +static const uint8_t TFT_G5 = 12; +static const uint8_t TFT_B1 = 40; +static const uint8_t TFT_B2 = 39; +static const uint8_t TFT_B3 = 38; +static const uint8_t TFT_B4 = 0; +static const uint8_t TFT_B5 = 45; +static const uint8_t TFT_PCLK = 1; +static const uint8_t TFT_DE = 2; +static const uint8_t TFT_HSYNC = 41; +static const uint8_t TFT_VSYNC = 42; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin b/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin new file mode 100644 index 0000000..9d70252 Binary files /dev/null and b/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin differ diff --git a/variants/adafruit_qualia_s3_rgb666/variant.cpp b/variants/adafruit_qualia_s3_rgb666/variant.cpp new file mode 100644 index 0000000..4b76e26 --- /dev/null +++ b/variants/adafruit_qualia_s3_rgb666/variant.cpp @@ -0,0 +1,35 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // default SD_CS to input pullup + pinMode(SS, INPUT_PULLUP); +} +} diff --git a/variants/adafruit_sparklemotion_esp32/pins_arduino.h b/variants/adafruit_sparklemotion_esp32/pins_arduino.h new file mode 100644 index 0000000..99043a9 --- /dev/null +++ b/variants/adafruit_sparklemotion_esp32/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// User LED +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Neopixel +static const uint8_t PIN_NEOPIXEL = 2; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 9; +static const uint8_t RX = 10; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 14; +static const uint8_t SCL = 13; + +static const uint8_t SS = 23; +static const uint8_t MOSI = 9; +static const uint8_t MISO = 10; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 27; + +// internal switch +static const uint8_t BUTTON = 0; + +static const uint8_t T0 = 27; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h b/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h new file mode 100644 index 0000000..2af307d --- /dev/null +++ b/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// User LED +static const uint8_t LED_BUILTIN = 12; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Neopixel +static const uint8_t PIN_NEOPIXEL = 18; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 25; +static const uint8_t RX = 26; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 19; +static const uint8_t SCL = 22; + +static const uint8_t SS = 14; +static const uint8_t MOSI = 25; +static const uint8_t MISO = 26; +static const uint8_t SCK = 27; + +static const uint8_t A0 = 13; + +// internal switch +static const uint8_t BUTTON = 0; + +static const uint8_t T0 = 13; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/adafruit_sparklemotionstick_esp32/pins_arduino.h b/variants/adafruit_sparklemotionstick_esp32/pins_arduino.h new file mode 100644 index 0000000..e0d9482 --- /dev/null +++ b/variants/adafruit_sparklemotionstick_esp32/pins_arduino.h @@ -0,0 +1,40 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// User LED +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Neopixel +static const uint8_t PIN_NEOPIXEL = 18; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 25; // not broken out, defined to fix compilation +static const uint8_t RX = 26; // not broken out, defined to fix compilation + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 13; // not broken out, defined to fix compilation +static const uint8_t SCL = 15; // not broken out, defined to fix compilation + +static const uint8_t SS = 19; // not broken out, defined to fix compilation +static const uint8_t MOSI = 21; // output to drive dotstars +static const uint8_t SCK = 22; // output to drive dotstars +static const uint8_t MISO = 23; // not broken out, defined to fix compilation + +static const uint8_t A0 = 2; // not broken out, defined to fix compilation + +// internal switch +static const uint8_t BUTTON = 0; + +static const uint8_t DAC1 = 25; // not broken out, defined to fix compilation +static const uint8_t DAC2 = 26; // not broken out, defined to fix compilation + +#endif /* Pins_Arduino_h */ diff --git a/variants/alfredo-nou3/pins_arduino.h b/variants/alfredo-nou3/pins_arduino.h new file mode 100644 index 0000000..8b5a7d5 --- /dev/null +++ b/variants/alfredo-nou3/pins_arduino.h @@ -0,0 +1,28 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#define USB_VID 0xAFD0 +#define USB_PID 0x0003 +#define USB_MANUFACTURER "Alfredo" +#define USB_PRODUCT "NoU3" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 45 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +//static const uint8_t TX = 39; +//static const uint8_t RX = 40; +//#define TX1 TX +//#define RX1 RX + +static const uint8_t SDA = -1; +static const uint8_t SCL = -1; + +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t SCK = -1; +static const uint8_t MISO = -1; + +#endif /* Pins_Arduino_h */ diff --git a/variants/alksesp32/pins_arduino.h b/variants/alksesp32/pins_arduino.h new file mode 100644 index 0000000..95238aa --- /dev/null +++ b/variants/alksesp32/pins_arduino.h @@ -0,0 +1,78 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define ALKSESP32 // tell library to not map pins again + +static const uint8_t LED_BUILTIN = 23; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t D0 = 40; +static const uint8_t D1 = 41; +static const uint8_t D2 = 15; +static const uint8_t D3 = 2; +static const uint8_t D4 = 0; +static const uint8_t D5 = 4; +static const uint8_t D6 = 16; +static const uint8_t D7 = 17; +static const uint8_t D8 = 5; +static const uint8_t D9 = 18; +static const uint8_t D10 = 19; +static const uint8_t D11 = 21; +static const uint8_t D12 = 22; +static const uint8_t D13 = 23; + +static const uint8_t A0 = 32; +static const uint8_t A1 = 33; +static const uint8_t A2 = 25; +static const uint8_t A3 = 26; +static const uint8_t A4 = 27; +static const uint8_t A5 = 14; +static const uint8_t A6 = 12; +static const uint8_t A7 = 15; + +static const uint8_t L_R = 22; +static const uint8_t L_G = 17; +static const uint8_t L_Y = 23; +static const uint8_t L_B = 5; +static const uint8_t L_RGB_R = 4; +static const uint8_t L_RGB_G = 21; +static const uint8_t L_RGB_B = 16; + +static const uint8_t SW1 = 15; +static const uint8_t SW2 = 2; +static const uint8_t SW3 = 0; + +static const uint8_t POT1 = 32; +static const uint8_t POT2 = 33; + +static const uint8_t PIEZO1 = 19; +static const uint8_t PIEZO2 = 18; + +static const uint8_t PHOTO = 25; + +static const uint8_t DHT_PIN = 26; + +static const uint8_t S1 = 4; +static const uint8_t S2 = 16; +static const uint8_t S3 = 18; +static const uint8_t S4 = 19; +static const uint8_t S5 = 21; + +static const uint8_t SDA = 27; +static const uint8_t SCL = 14; + +static const uint8_t SS = 19; +static const uint8_t MOSI = 21; +static const uint8_t MISO = 22; +static const uint8_t SCK = 23; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/arduino_nano_nora/dfu_callbacks.cpp b/variants/arduino_nano_nora/dfu_callbacks.cpp new file mode 100644 index 0000000..fa7d57d --- /dev/null +++ b/variants/arduino_nano_nora/dfu_callbacks.cpp @@ -0,0 +1,105 @@ +#include "Arduino.h" + +#include +#include + +// defines an "Update" object accessed only by this translation unit +// (also, the object requires MD5Builder internally) +namespace { +// ignore '{anonymous}::MD5Builder::...() defined but not used' warnings +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" +#include "../../libraries/Update/src/Updater.cpp" +#include "../../cores/esp32/HEXBuilder.cpp" +#include "../../cores/esp32/MD5Builder.cpp" +#pragma GCC diagnostic pop +} // namespace + +#define ALT_COUNT 1 + +//--------------------------------------------------------------------+ +// DFU callbacks +// Note: alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc. +//--------------------------------------------------------------------+ + +uint16_t load_dfu_ota_descriptor(uint8_t *dst, uint8_t *itf) { +#define DFU_ATTRS (DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_CAN_UPLOAD | DFU_ATTR_MANIFESTATION_TOLERANT) + + uint8_t str_index = tinyusb_add_string_descriptor("Arduino DFU"); + uint8_t descriptor[TUD_DFU_DESC_LEN(ALT_COUNT)] = { + // Interface number, string index, attributes, detach timeout, transfer size */ + TUD_DFU_DESCRIPTOR(*itf, ALT_COUNT, str_index, DFU_ATTRS, 100, CFG_TUD_DFU_XFER_BUFSIZE), + }; + *itf += 1; + memcpy(dst, descriptor, TUD_DFU_DESC_LEN(ALT_COUNT)); + return TUD_DFU_DESC_LEN(ALT_COUNT); +} + +// Invoked right before tud_dfu_download_cb() (state=DFU_DNBUSY) or tud_dfu_manifest_cb() (state=DFU_MANIFEST) +// Application return timeout in milliseconds (bwPollTimeout) for the next download/manifest operation. +// During this period, USB host won't try to communicate with us. +uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) { + if (state == DFU_DNBUSY) { + // longest delay for Flash writing + return 10; + } else if (state == DFU_MANIFEST) { + // time for esp32_ota_set_boot_partition to check final image + return 100; + } + + return 0; +} + +// Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests +// This callback could be returned before flashing op is complete (async). +// Once finished flashing, application must call tud_dfu_finish_flashing() +void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const *data, uint16_t length) { + if (!Update.isRunning()) { + // this is the first data block, start update if possible + if (!Update.begin()) { + tud_dfu_finish_flashing(DFU_STATUS_ERR_TARGET); + return; + } + } + + // write a block of data to Flash + // XXX: Update API is needlessly non-const + size_t written = Update.write(const_cast(data), length); + tud_dfu_finish_flashing((written == length) ? DFU_STATUS_OK : DFU_STATUS_ERR_WRITE); +} + +// Invoked when download process is complete, received DFU_DNLOAD (wLength=0) following by DFU_GETSTATUS (state=Manifest) +// Application can do checksum, or actual flashing if buffered entire image previously. +// Once finished flashing, application must call tud_dfu_finish_flashing() +void tud_dfu_manifest_cb(uint8_t alt) { + (void)alt; + bool ok = Update.end(true); + + // flashing op for manifest is complete + tud_dfu_finish_flashing(ok ? DFU_STATUS_OK : DFU_STATUS_ERR_VERIFY); +} + +// Invoked when received DFU_UPLOAD request +// Application must populate data with up to length bytes and +// Return the number of written bytes +uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t *data, uint16_t length) { + (void)alt; + (void)block_num; + (void)data; + (void)length; + + // not implemented + return 0; +} + +// Invoked when the Host has terminated a download or upload transfer +void tud_dfu_abort_cb(uint8_t alt) { + (void)alt; + // ignore +} + +// Invoked when a DFU_DETACH request is received +void tud_dfu_detach_cb(void) { + // done, reboot + esp_restart(); +} diff --git a/variants/arduino_nano_nora/double_tap.c b/variants/arduino_nano_nora/double_tap.c new file mode 100644 index 0000000..e371be6 --- /dev/null +++ b/variants/arduino_nano_nora/double_tap.c @@ -0,0 +1,69 @@ +#include + +#include +#include +#include + +#include "double_tap.h" + +#define NUM_TOKENS 3 +static const uint32_t MAGIC_TOKENS[NUM_TOKENS] = { + 0xf01681de, + 0xbd729b29, + 0xd359be7a, +}; + +static void *magic_area; +static uint32_t backup_area[NUM_TOKENS]; + +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0) +// Current IDF does not map external RAM to a fixed address. +// The actual VMA depends on other enabled devices, so the precise +// location must be discovered. +#include +#include +static uintptr_t get_extram_data_high(void) { + // get a pointer into SRAM area (only the address is useful) + void *psram_ptr = heap_caps_malloc(16, MALLOC_CAP_SPIRAM); + heap_caps_free(psram_ptr); + + // keep moving backwards until leaving PSRAM area + uintptr_t psram_base_addr = (uintptr_t)psram_ptr; + psram_base_addr &= ~(CONFIG_MMU_PAGE_SIZE - 1); // align to start of page + while (esp_psram_check_ptr_addr((void *)psram_base_addr)) { + psram_base_addr -= CONFIG_MMU_PAGE_SIZE; + } + + // offset is one page from start of PSRAM + return psram_base_addr + CONFIG_MMU_PAGE_SIZE + esp_psram_get_size(); +} +#else +#include +#define get_extram_data_high() ((uintptr_t)SOC_EXTRAM_DATA_HIGH) +#endif + +void double_tap_init(void) { + // magic location block ends 0x20 bytes from end of PSRAM + magic_area = (void *)(get_extram_data_high() - 0x20 - sizeof(MAGIC_TOKENS)); +} + +void double_tap_mark() { + memcpy(backup_area, magic_area, sizeof(MAGIC_TOKENS)); + memcpy(magic_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS)); + Cache_WriteBack_Addr((uintptr_t)magic_area, sizeof(MAGIC_TOKENS)); +} + +void double_tap_invalidate() { + if (memcmp(backup_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS))) { + // different contents: restore backup + memcpy(magic_area, backup_area, sizeof(MAGIC_TOKENS)); + } else { + // clear memory + memset(magic_area, 0, sizeof(MAGIC_TOKENS)); + } + Cache_WriteBack_Addr((uintptr_t)magic_area, sizeof(MAGIC_TOKENS)); +} + +bool double_tap_check_match() { + return (memcmp(magic_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS)) == 0); +} diff --git a/variants/arduino_nano_nora/double_tap.h b/variants/arduino_nano_nora/double_tap.h new file mode 100644 index 0000000..e797f4f --- /dev/null +++ b/variants/arduino_nano_nora/double_tap.h @@ -0,0 +1,20 @@ +#ifndef __DOUBLE_TAP_H__ +#define __DOUBLE_TAP_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void double_tap_init(void); +void double_tap_mark(void); +void double_tap_invalidate(void); +bool double_tap_check_match(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DOUBLE_TAP_H__ */ diff --git a/variants/arduino_nano_nora/extra/nora_recovery/README.md b/variants/arduino_nano_nora/extra/nora_recovery/README.md new file mode 100644 index 0000000..786027d --- /dev/null +++ b/variants/arduino_nano_nora/extra/nora_recovery/README.md @@ -0,0 +1,49 @@ + +# Arduino Nano Nora Recovery Sketch + +This sketch implements the DFU recovery mode logic, called by all sketches +when a double tap on the RESET button is detected. It should not be uploaded +as any other sketch; instead, this should be compiled and then flashed in +the module's `factory` partition. + +## Compilation + +The binary can be compiled with the Arduino 2.x IDE or CLI using the +`nano_nora` variant. In particular, using the CLI the resulting binary +can be exported to the `build` directory with the `-e` switch to +`arduino-cli compile`. + +## Automatic installation + +By replacing the binary in the current folder, automatic installation +can be performed by running the "Upload with Programmer" action on any +sketch in the Arduino 2.x IDE or CLI. In particular, using the CLI the +binary can be installed via the command: + +``` +arduino-cli compile -u --programmer esptool +``` + +## Manual installation + +Once compiled, the binary can also be installed on a board using `esptool.py` +with the following command: + +``` +esptool.py --chip esp32s3 --port "/dev/ttyACM0" --baud 921600 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 80m --flash_size 16MB 0xF70000 "nora_recovery.ino.bin" +``` + +where: +- `esptool.py` is located in your core's install path under `tools/esptool_py`; +- `/dev/ttyACM0` is the serial port exposed by the board to be used; +- `0xF70000` is the factory partition address (make sure it matches the + offset in the variant's `{build.partitions}` file); +- `nora_recovery.ino.bin` is the compiled sketch image. + +Due to a BSP issue, the first call to `esptool.py` will enter the hardware +bootloader for programming, but fail with an "Input/output error". This is +a known issue; calling the program again with the same arguments will now +work correctly. + +Once flashing is complete, a power cycle (or RESET button tap) is required +to leave the `esptool.py` flashing mode and load user sketches. diff --git a/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino new file mode 100644 index 0000000..fbaa340 --- /dev/null +++ b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino @@ -0,0 +1,100 @@ +#include "USB.h" + +#define USB_TIMEOUT_MS 15000 +#define POLL_DELAY_MS 60 +#define FADESTEP 8 + +void pulse_led() { + static uint32_t pulse_width = 0; + static uint8_t dir = 0; + + if (dir) { + pulse_width -= FADESTEP; + if (pulse_width < FADESTEP) { + dir = 0U; + pulse_width = FADESTEP; + } + } else { + pulse_width += FADESTEP; + if (pulse_width > 255) { + dir = 1U; + pulse_width = 255; + } + } + + analogWrite(LED_GREEN, pulse_width); +} + +#include +#include +#include +#include +const esp_partition_t *find_previous_firmware() { + extern bool _recovery_active; + if (!_recovery_active) { + // user flashed this recovery sketch to an OTA partition + // stay here and wait for a proper firmware + return NULL; + } + + // booting from factory partition, look for a valid OTA image + esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL); + for (; it != NULL; it = esp_partition_next(it)) { + const esp_partition_t *part = esp_partition_get(it); + if (part->subtype != ESP_PARTITION_SUBTYPE_APP_FACTORY) { + esp_partition_pos_t candidate = {part->address, part->size}; + esp_image_metadata_t meta; + if (esp_image_verify(ESP_IMAGE_VERIFY_SILENT, &candidate, &meta) == ESP_OK) { + // found, use it + return part; + } + } + } + + return NULL; +} + +const esp_partition_t *user_part = NULL; + +void setup() { + user_part = find_previous_firmware(); + if (user_part) { + esp_ota_set_boot_partition(user_part); + } + + extern bool _recovery_marker_found; + if (!_recovery_marker_found && user_part) { + // recovery marker not found, probable cold start + // try starting previous firmware immediately + esp_restart(); + } + + // recovery marker found, or nothing else to load + printf("Recovery firmware started, waiting for USB\r\n"); +} + +void loop() { + static int elapsed_ms = 0; + + pulse_led(); + delay(POLL_DELAY_MS); + if (USB) { + // wait indefinitely for DFU to complete + elapsed_ms = 0; + } else { + // wait for USB connection + elapsed_ms += POLL_DELAY_MS; + } + + if (elapsed_ms > USB_TIMEOUT_MS) { + elapsed_ms = 0; + // timed out, try loading previous firmware + if (user_part) { + // there was a valid FW image, load it + analogWrite(LED_GREEN, 255); + printf("Leaving recovery firmware\r\n"); + delay(200); + esp_restart(); // does not return + } + } +} diff --git a/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin new file mode 100644 index 0000000..ee5e7d5 Binary files /dev/null and b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin differ diff --git a/variants/arduino_nano_nora/io_pin_remap.cpp b/variants/arduino_nano_nora/io_pin_remap.cpp new file mode 100644 index 0000000..f615f57 --- /dev/null +++ b/variants/arduino_nano_nora/io_pin_remap.cpp @@ -0,0 +1,73 @@ +#if defined(BOARD_HAS_PIN_REMAP) && !defined(ARDUINO_CORE_BUILD) +// -DARDUINO_CORE_BUILD must be set for core files only, to avoid extra +// remapping steps that would create all sorts of issues in the core. +// Removing -DBOARD_HAS_PIN_REMAP at least does correctly restore the +// use of GPIO numbers in the API. +#error This build system is not supported. Please rebuild without BOARD_HAS_PIN_REMAP. +#endif + +#if !defined(BOARD_HAS_PIN_REMAP) +// This board uses pin mapping but the build system has disabled it +#warning The build system forces the Arduino API to use GPIO numbers on a board that has custom pin mapping. +#elif defined(BOARD_USES_HW_GPIO_NUMBERS) +// The user has chosen to disable pin mapping. +#warning The Arduino API will use GPIO numbers for this build. +#endif + +#include "Arduino.h" + +// NOTE: This must match with the remapped pin sequence in pins_arduino.h +static const int8_t TO_GPIO_NUMBER[] = { + 44, // [ 0] D0, RX + 43, // [ 1] D1, TX + 5, // [ 2] D2 + 6, // [ 3] D3, CTS + 7, // [ 4] D4, DSR + 8, // [ 5] D5 + 9, // [ 6] D6 + 10, // [ 7] D7 + 17, // [ 8] D8 + 18, // [ 9] D9 + 21, // [10] D10, SS + 38, // [11] D11, MOSI + 47, // [12] D12, MISO + 48, // [13] D13, SCK, LED_BUILTIN + 46, // [14] LED_RED + 0, // [15] LED_GREEN + 45, // [16] LED_BLUE, RTS + 1, // [17] A0, DTR + 2, // [18] A1 + 3, // [19] A2 + 4, // [20] A3 + 11, // [21] A4, SDA + 12, // [22] A5, SCL + 13, // [23] A6 + 14, // [24] A7 +}; + +#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS) + +int8_t digitalPinToGPIONumber(int8_t digitalPin) { + if ((digitalPin < 0) || (digitalPin >= NUM_DIGITAL_PINS)) { + return -1; + } + return TO_GPIO_NUMBER[digitalPin]; +} + +int8_t gpioNumberToDigitalPin(int8_t gpioNumber) { + if (gpioNumber < 0) { + return -1; + } + + // slow linear table lookup + for (int8_t digitalPin = 0; digitalPin < NUM_DIGITAL_PINS; ++digitalPin) { + if (TO_GPIO_NUMBER[digitalPin] == gpioNumber) { + return digitalPin; + } + } + + // not found + return -1; +} + +#endif diff --git a/variants/arduino_nano_nora/pins_arduino.h b/variants/arduino_nano_nora/pins_arduino.h new file mode 100644 index 0000000..2772d6f --- /dev/null +++ b/variants/arduino_nano_nora/pins_arduino.h @@ -0,0 +1,114 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x2341 +#define USB_PID 0x0070 + +#ifndef __cplusplus +#define constexpr const +#endif + +// primary pin names + +#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS) + +// Arduino style definitions (API uses Dx) + +static constexpr uint8_t D0 = 0; // also RX +static constexpr uint8_t D1 = 1; // also TX +static constexpr uint8_t D2 = 2; +static constexpr uint8_t D3 = 3; // also CTS +static constexpr uint8_t D4 = 4; // also DSR +static constexpr uint8_t D5 = 5; +static constexpr uint8_t D6 = 6; +static constexpr uint8_t D7 = 7; +static constexpr uint8_t D8 = 8; +static constexpr uint8_t D9 = 9; +static constexpr uint8_t D10 = 10; // also SS +static constexpr uint8_t D11 = 11; // also MOSI +static constexpr uint8_t D12 = 12; // also MISO +static constexpr uint8_t D13 = 13; // also SCK, LED_BUILTIN +static constexpr uint8_t LED_RED = 14; +static constexpr uint8_t LED_GREEN = 15; +static constexpr uint8_t LED_BLUE = 16; // also RTS + +static constexpr uint8_t A0 = 17; // also DTR +static constexpr uint8_t A1 = 18; +static constexpr uint8_t A2 = 19; +static constexpr uint8_t A3 = 20; +static constexpr uint8_t A4 = 21; // also SDA +static constexpr uint8_t A5 = 22; // also SCL +static constexpr uint8_t A6 = 23; +static constexpr uint8_t A7 = 24; + +#else + +// ESP32-style definitions (API uses GPIOx) + +static constexpr uint8_t D0 = 44; // also RX +static constexpr uint8_t D1 = 43; // also TX +static constexpr uint8_t D2 = 5; +static constexpr uint8_t D3 = 6; // also CTS +static constexpr uint8_t D4 = 7; // also DSR +static constexpr uint8_t D5 = 8; +static constexpr uint8_t D6 = 9; +static constexpr uint8_t D7 = 10; +static constexpr uint8_t D8 = 17; +static constexpr uint8_t D9 = 18; +static constexpr uint8_t D10 = 21; // also SS +static constexpr uint8_t D11 = 38; // also MOSI +static constexpr uint8_t D12 = 47; // also MISO +static constexpr uint8_t D13 = 48; // also SCK, LED_BUILTIN +static constexpr uint8_t LED_RED = 46; +static constexpr uint8_t LED_GREEN = 0; +static constexpr uint8_t LED_BLUE = 45; // also RTS + +static constexpr uint8_t A0 = 1; // also DTR +static constexpr uint8_t A1 = 2; +static constexpr uint8_t A2 = 3; +static constexpr uint8_t A3 = 4; +static constexpr uint8_t A4 = 11; // also SDA +static constexpr uint8_t A5 = 12; // also SCL +static constexpr uint8_t A6 = 13; +static constexpr uint8_t A7 = 14; + +#endif + +// Aliases + +static constexpr uint8_t LEDR = LED_RED; +static constexpr uint8_t LEDG = LED_GREEN; +static constexpr uint8_t LEDB = LED_BLUE; + +// alternate pin functions + +static constexpr uint8_t LED_BUILTIN = D13; + +static constexpr uint8_t TX = D1; +static constexpr uint8_t RX = D0; +static constexpr uint8_t RTS = LED_BLUE; +static constexpr uint8_t CTS = D3; +static constexpr uint8_t DTR = A0; +static constexpr uint8_t DSR = D4; + +static constexpr uint8_t SS = D10; +static constexpr uint8_t MOSI = D11; +static constexpr uint8_t MISO = D12; +static constexpr uint8_t SCK = D13; + +static constexpr uint8_t SDA = A4; +static constexpr uint8_t SCL = A5; + +#define PIN_I2S_SCK D7 +#define PIN_I2S_FS D8 +#define PIN_I2S_SD D9 +#define PIN_I2S_SD_OUT D9 // same as bidir +#define PIN_I2S_SD_IN D10 + +#ifndef __cplusplus +#undef constexpr +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/arduino_nano_nora/variant.cpp b/variants/arduino_nano_nora/variant.cpp new file mode 100644 index 0000000..df28d0d --- /dev/null +++ b/variants/arduino_nano_nora/variant.cpp @@ -0,0 +1,101 @@ +// Enable pin remapping in this file, so pin constants are meaningful +#undef ARDUINO_CORE_BUILD + +#include "Arduino.h" + +#include "double_tap.h" + +#include +#include +#include + +extern "C" { +void initVariant() { + // nothing to do +} +} + +// global, accessible from recovery sketch +bool _recovery_marker_found; // double tap detected +bool _recovery_active; // running from factory partition + +#define DELAY_US 10000 +#define FADESTEP 8 +static void rgb_pulse_delay(void) { + // Bv R^ G x + int widths[4] = {192, 64, 0, 0}; + int dec_led = 0; + + // initialize RGB signals from weak pinstraps + pinMode(LED_RED, OUTPUT); + pinMode(LED_GREEN, OUTPUT); + pinMode(LED_BLUE, OUTPUT); + while (dec_led < 3) { + widths[dec_led] -= FADESTEP; + widths[dec_led + 1] += FADESTEP; + if (widths[dec_led] <= 0) { + widths[dec_led] = 0; + dec_led = dec_led + 1; + widths[dec_led] = 255; + } + + analogWrite(LED_RED, 255 - widths[1]); + analogWrite(LED_GREEN, 255 - widths[2]); + analogWrite(LED_BLUE, 255 - widths[0]); + delayMicroseconds(DELAY_US); + } + + // reset pins to digital HIGH before leaving + digitalWrite(LED_RED, HIGH); + digitalWrite(LED_GREEN, HIGH); + digitalWrite(LED_BLUE, HIGH); +} + +static void NANO_ESP32_enter_bootloader(void) { + if (!_recovery_active) { + // check for valid partition scheme + const esp_partition_t *ota_part = esp_ota_get_next_update_partition(NULL); + const esp_partition_t *fact_part = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_FACTORY, NULL); + if (ota_part && fact_part) { + // set tokens so the recovery FW will find them + double_tap_mark(); + // invalidate other OTA image + esp_partition_erase_range(ota_part, 0, 4096); + // activate factory partition + esp_ota_set_boot_partition(fact_part); + } + } + + esp_restart(); +} + +static void boot_double_tap_logic() { + const esp_partition_t *part = esp_ota_get_running_partition(); + _recovery_active = (part->subtype == ESP_PARTITION_SUBTYPE_APP_FACTORY); + + double_tap_init(); + + _recovery_marker_found = double_tap_check_match(); + if (_recovery_marker_found && !_recovery_active) { + // double tap detected in user application, reboot to factory + NANO_ESP32_enter_bootloader(); + } + + // delay with mark set then proceed + // - for normal startup, to detect first double tap + // - in recovery mode, to ignore several short presses + double_tap_mark(); + rgb_pulse_delay(); + double_tap_invalidate(); +} + +namespace { +class DoubleTap { +public: + DoubleTap() { + boot_double_tap_logic(); + } +}; + +DoubleTap dt __attribute__((init_priority(101))); +} // namespace diff --git a/variants/arduino_nesso_n1/pins_arduino.h b/variants/arduino_nesso_n1/pins_arduino.h new file mode 100644 index 0000000..ce8a4db --- /dev/null +++ b/variants/arduino_nesso_n1/pins_arduino.h @@ -0,0 +1,82 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 +#define USB_MANUFACTURER "Arduino" +#define USB_PRODUCT "Nesso N1" +#define USB_SERIAL "" + +static const uint8_t TX = -1; +static const uint8_t RX = -1; + +static const uint8_t SDA = 10; +static const uint8_t SCL = 8; + +static const uint8_t MOSI = 21; +static const uint8_t MISO = 22; +static const uint8_t SCK = 20; +static const uint8_t SS = 23; + +static const uint8_t D1 = 7; +static const uint8_t D2 = 2; +static const uint8_t D3 = 6; + +static const uint8_t IR_TX_PIN = 9; +static const uint8_t BEEP_PIN = 11; + +static const uint8_t GROVE_IO_0 = 5; +static const uint8_t GROVE_IO_1 = 4; + +static const uint8_t LORA_IRQ = 15; +static const uint8_t LORA_CS = 23; +static const uint8_t LORA_BUSY = 19; + +static const uint8_t SYS_IRQ = 3; + +static const uint8_t LCD_CS = 17; +static const uint8_t LCD_RS = 16; + +#if !defined(MAIN_ESP32_HAL_GPIO_H_) && defined(__cplusplus) /* && !defined(ARDUINO_CORE_BUILD) */ + +#define ATTRIBUTE_ERROR __attribute__((error("Please include Arduino_Nesso_N1.h"))) + +class ExpanderPinError { +public: + ExpanderPinError(uint16_t p){}; +}; + +void ATTRIBUTE_ERROR pinMode(ExpanderPinError pin, uint8_t mode); +void ATTRIBUTE_ERROR digitalWrite(ExpanderPinError pin, uint8_t val); +int ATTRIBUTE_ERROR digitalRead(ExpanderPinError pin); + +extern ExpanderPinError _LORA_LNA_ENABLE; +extern ExpanderPinError _LORA_ANTENNA_SWITCH; +extern ExpanderPinError _LORA_ENABLE; +extern ExpanderPinError _POWEROFF; +extern ExpanderPinError _GROVE_POWER_EN; +extern ExpanderPinError _VIN_DETECT; +extern ExpanderPinError _LCD_RESET; +extern ExpanderPinError _LCD_BACKLIGHT; +extern ExpanderPinError _LED_BUILTIN; +extern ExpanderPinError _KEY1; +extern ExpanderPinError _KEY2; + +#define LORA_LNA_ENABLE _LORA_LNA_ENABLE +#define LORA_ANTENNA_SWITCH _LORA_ANTENNA_SWITCH +#define LORA_ENABLE _LORA_ENABLE +#define POWEROFF _POWEROFF +#define GROVE_POWER_EN _GROVE_POWER_EN +#define VIN_DETECT _VIN_DETECT +#define LCD_RESET _LCD_RESET +#define LCD_BACKLIGHT _LCD_BACKLIGHT +#define LED_BUILTIN _LED_BUILTIN +#define KEY1 _KEY1 +#define KEY2 _KEY2 + +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/aslcanx2/default_8MB_ffat.csv b/variants/aslcanx2/default_8MB_ffat.csv new file mode 100644 index 0000000..2791bf7 --- /dev/null +++ b/variants/aslcanx2/default_8MB_ffat.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x330000, +app1, app, ota_1, 0x340000,0x330000, +ffat, data, fat, 0x670000,0x180000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/variants/aslcanx2/pins_arduino.h b/variants/aslcanx2/pins_arduino.h new file mode 100644 index 0000000..eb876a0 --- /dev/null +++ b/variants/aslcanx2/pins_arduino.h @@ -0,0 +1,65 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x16D0 +#define USB_PID 0x07F2 + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t CAN1_RX = 6; +static const uint8_t CAN1_TX = 7; + +static const uint8_t SS = -1; +static const uint8_t CS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/atd147_s3/pins_arduino.h b/variants/atd147_s3/pins_arduino.h new file mode 100644 index 0000000..873ca21 --- /dev/null +++ b/variants/atd147_s3/pins_arduino.h @@ -0,0 +1,67 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +#define LCD_CS SS +#define LCD_SCK SCK +#define LCD_SDA MOSI +static const uint8_t LCD_DC = 21; +static const uint8_t LCD_RES = 14; + +static const uint8_t BTN_A = 4; +static const uint8_t BTN_B = 5; +static const uint8_t BTN_C = 45; +#define KEY_BUILTIN BTN_A + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/atd35s3/pins_arduino.h b/variants/atd35s3/pins_arduino.h new file mode 100644 index 0000000..c973693 --- /dev/null +++ b/variants/atd35s3/pins_arduino.h @@ -0,0 +1,78 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// LCD pin +#define LCD_CS SS +#define LCD_SCK SCK +#define LCD_SDA MOSI +static const uint8_t LCD_DC = 21; +static const uint8_t LCD_RES = 14; +static const uint8_t LCD_BL = 3; + +// MicroSD Card pin +static const uint8_t SD_CS = 18; +static const uint8_t SD_CD = 17; + +static const uint8_t BTN_A = 4; +#define KEY_BUILTIN BTN_A + +static const uint8_t LED_BUILTIN = 5; + +// DAC pin +static const uint8_t DAC_DIN = 47; +static const uint8_t DAC_BCLK = 48; +static const uint8_t DAC_WS = 45; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin b/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..d52b958 Binary files /dev/null and b/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv b/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv new file mode 100644 index 0000000..003418c --- /dev/null +++ b/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/variants/atmegazero_esp32s2/pins_arduino.h b/variants/atmegazero_esp32s2/pins_arduino.h new file mode 100644 index 0000000..dda442c --- /dev/null +++ b/variants/atmegazero_esp32s2/pins_arduino.h @@ -0,0 +1,60 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x800A +#define USB_MANUFACTURER "ATMegaZero" +#define USB_PRODUCT "ATMZ-ESP32S2" +#define USB_SERIAL "" + +static const uint8_t RGB_LED_PIN = 40; +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = (RGB_LED_PIN + SOC_GPIO_PIN_COUNT); +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t PD5 = 0; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 38; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 13; +static const uint8_t A3 = 12; +static const uint8_t A4 = 6; +static const uint8_t A5 = 3; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/atmegazero_esp32s2/tinyuf2.bin b/variants/atmegazero_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..6e78e54 Binary files /dev/null and b/variants/atmegazero_esp32s2/tinyuf2.bin differ diff --git a/variants/axiometa_genesis_one/pins_arduino.h b/variants/axiometa_genesis_one/pins_arduino.h new file mode 100644 index 0000000..bfe8635 --- /dev/null +++ b/variants/axiometa_genesis_one/pins_arduino.h @@ -0,0 +1,106 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Battery monitoring (voltage divider /2) +#define VBAT_SENSE 10 + +// Battery voltage reading macro +#define getBatteryVoltage() ((analogRead(VBAT_SENSE) / 4095.0) * 3.3 * 2.0) + +// Fixed communication pins (shared across all ports) +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 47; +static const uint8_t SCL = 48; + +static const uint8_t SS = 1; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 12; +static const uint8_t SCK = 13; + +// Port 1 IO pins +static const uint8_t P1_IO0 = 1; +static const uint8_t P1_IO1 = 14; +static const uint8_t P1_IO2 = 41; + +// Port 2 IO pins +static const uint8_t P2_IO0 = 2; +static const uint8_t P2_IO1 = 15; +static const uint8_t P2_IO2 = 42; + +// Port 3 IO pins +static const uint8_t P3_IO0 = 3; +static const uint8_t P3_IO1 = 16; +static const uint8_t P3_IO2 = 45; + +// Port 4 IO pins +static const uint8_t P4_IO0 = 4; +static const uint8_t P4_IO1 = 17; +static const uint8_t P4_IO2 = 46; + +// Port 5 IO pins +static const uint8_t P5_IO0 = 5; +static const uint8_t P5_IO1 = 18; +static const uint8_t P5_IO2 = 21; + +// Port 6 IO pins +static const uint8_t P6_IO0 = 6; +static const uint8_t P6_IO1 = 40; +static const uint8_t P6_IO2 = 38; + +// Port 7 IO pins +static const uint8_t P7_IO0 = 7; +static const uint8_t P7_IO1 = 9; +static const uint8_t P7_IO2 = 39; + +// Port 8 IO pins +static const uint8_t P8_IO0 = 8; +static const uint8_t P8_IO1 = 43; +static const uint8_t P8_IO2 = 44; + +// Analog capable pins (ESP32-S3 specific) +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +// Touch capable pins (ESP32-S3 specific) +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/axiometa_pixie_m1/pins_arduino.h b/variants/axiometa_pixie_m1/pins_arduino.h new file mode 100644 index 0000000..d318030 --- /dev/null +++ b/variants/axiometa_pixie_m1/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Pixie has a built in RGB LED WS2812B and a regular LED +#define PIN_RGB_LED 21 +#define PIN_LED 11 +// Regular built-in LED (pin 11) - for use with digitalWrite() +#define LED_BUILTIN PIN_LED +#define BUILTIN_LED LED_BUILTIN // backward compatibility +// RGB LED (pin 21) - use with RGB library functions +#define RGB_LED PIN_RGB_LED +// Allow testing for LED_BUILTIN +#ifdef LED_BUILTIN +// Defined and ready to use +#endif + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 10; +static const uint8_t SCL = 11; + +static const uint8_t SS = 1; +static const uint8_t MOSI = 12; +static const uint8_t MISO = 13; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/bpi-bit/pins_arduino.h b/variants/bpi-bit/pins_arduino.h new file mode 100644 index 0000000..42a820a --- /dev/null +++ b/variants/bpi-bit/pins_arduino.h @@ -0,0 +1,62 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t BUZZER = 25; + +static const uint8_t BUTTON_A = 35; +static const uint8_t BUTTON_B = 27; + +// RGB LED Matrix 5 x 5 +static const uint8_t RGB_LED = 4; + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +#define LED_BUILTIN (RGB_LED + SOC_GPIO_PIN_COUNT) // Just a single LED in the Matrix +#define BUILTIN_LED LED_BUILTIN // backward compatibility +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 +static const uint8_t LIGHT_SENSOR1 = 36; +static const uint8_t LIGHT_SENSOR2 = 39; + +static const uint8_t TEMPERATURE_SENSOR = 34; + +static const uint8_t MPU9250_INT = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t P0 = 25; +static const uint8_t P1 = 32; +static const uint8_t P2 = 33; +static const uint8_t P3 = 13; +static const uint8_t P4 = 15; +static const uint8_t P5 = 35; +static const uint8_t P6 = 12; +static const uint8_t P7 = 14; +static const uint8_t P8 = 16; +static const uint8_t P9 = 17; +static const uint8_t P10 = 26; +static const uint8_t P11 = 27; +static const uint8_t P12 = 2; +static const uint8_t P13 = 18; +static const uint8_t P14 = 19; +static const uint8_t P15 = 23; +static const uint8_t P16 = 5; +static const uint8_t P19 = 22; +static const uint8_t P20 = 21; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/bpi_leaf_s3/pins_arduino.h b/variants/bpi_leaf_s3/pins_arduino.h new file mode 100644 index 0000000..3a22a46 --- /dev/null +++ b/variants/bpi_leaf_s3/pins_arduino.h @@ -0,0 +1,72 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x80df +#define USB_MANUFACTURER "Banana Pi" +#define USB_PRODUCT "BPI-Leaf-S3" +#define USB_SERIAL "" + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +#define PIN_RGB_LED 48 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 25 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 15; +static const uint8_t SCL = 16; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/cezerio_dev_esp32c6/pins_arduino.h b/variants/cezerio_dev_esp32c6/pins_arduino.h new file mode 100644 index 0000000..3ffc59a --- /dev/null +++ b/variants/cezerio_dev_esp32c6/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 +#define USB_MANUFACTURER "RFtek Electronics" +#define USB_PRODUCT "cezerio dev ESP32C6" +#define USB_SERIAL "" + +#define PIN_RGB_LED 3 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t BUT_BUILTIN = 9; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN +#define BOOT BUT_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 7; + +static const uint8_t SS = 14; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 23; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +static const uint8_t MATRIX = 18; + +static const uint8_t IMUSD = 8; +static const uint8_t IMUSC = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/cezerio_mini_dev_esp32c6/pins_arduino.h b/variants/cezerio_mini_dev_esp32c6/pins_arduino.h new file mode 100644 index 0000000..e7ef94e --- /dev/null +++ b/variants/cezerio_mini_dev_esp32c6/pins_arduino.h @@ -0,0 +1,47 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 +#define USB_MANUFACTURER "RFtek Electronics" +#define USB_PRODUCT "cezerio mini dev ESP32C6" +#define USB_SERIAL "" + +#define PIN_RGB_LED 20 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t BUT_BUILTIN = 9; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN +#define BOOT BUT_BUILTIN + +static const uint8_t TX = 7; +static const uint8_t RX = 14; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t MOSI = 19; +static const uint8_t MISO = 21; +static const uint8_t SCK = 18; +static const uint8_t SS = 17; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A6 = 6; + +static const uint8_t MATRIX = 4; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ch_denky/pins_arduino.h b/variants/ch_denky/pins_arduino.h new file mode 100644 index 0000000..11792a1 --- /dev/null +++ b/variants/ch_denky/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +// Specific CH2i (Charles Hallard) Boards +// 1st Revision Denky with ESP WROOM32 + LoRa RN2483 module +#if defined(ARDUINO_DENKY_WROOM32) +#define PUSH_BUTTON 0 +#define TIC_ENABLE_PIN 4 +#define TIC_RX_PIN 33 +#define LORA_TX_PIN 26 +#define LORA_RX_PIN 27 +#define LORA_RESET 14 +#define RGB_LED_PIN 25 + +// 2nd Utra Small version with ESP Pico-D4-V3-02 +#elif defined(ARDUINO_DENKY_PICOV3) +// RGB Led Pins +#define LED_RED_PIN 27 +#define LED_GRN_PIN 26 +#define LED_BLU_PIN 25 + +// Teleinfo RXD pin is connected to ESP32-PICO-V3-02 GPIO8 +#define TIC_RX_PIN 8 +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/circuitart_zero_s3/bootloader_tinyuf2.bin b/variants/circuitart_zero_s3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..9010051 Binary files /dev/null and b/variants/circuitart_zero_s3/bootloader_tinyuf2.bin differ diff --git a/variants/circuitart_zero_s3/partitions_tinyuf2.csv b/variants/circuitart_zero_s3/partitions_tinyuf2.csv new file mode 100644 index 0000000..55f6c2b --- /dev/null +++ b/variants/circuitart_zero_s3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, app, ota_0, 0x10000, 2048K, +ota_1, app, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/variants/circuitart_zero_s3/pins_arduino.h b/variants/circuitart_zero_s3/pins_arduino.h new file mode 100644 index 0000000..adf38ca --- /dev/null +++ b/variants/circuitart_zero_s3/pins_arduino.h @@ -0,0 +1,137 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x80DB +#define USB_MANUFACTURER "CircuitART" +#define USB_PRODUCT "ZeroS3" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 46 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// RGB LED +#define PIN_RGB_LED 47 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking +#define RGB_BUILTIN (PIN_RGB_LED + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +#define RGBLED_NUM 1 // number of RGB LEDs + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TFT_DC = 5; +static const uint8_t TFT_CS = 39; +static const uint8_t TFT_RST = 40; +static const uint8_t TFT_RESET = 40; + +static const uint8_t SD_CS = 42; +static const uint8_t SD_CHIP_SELECT = 42; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +static const uint8_t TX0 = 43; +static const uint8_t RX0 = 44; + +static const uint8_t TX1 = 40; +static const uint8_t RX2 = 41; + +static const uint8_t SDA = 33; +static const uint8_t SCL = 34; + +static const uint8_t SS = 39; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; +static const uint8_t T15 = 15; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D11 = 11; +static const uint8_t D12 = 12; +static const uint8_t D13 = 13; +static const uint8_t D14 = 14; +static const uint8_t D15 = 15; +static const uint8_t D16 = 16; +static const uint8_t D17 = 17; +static const uint8_t D18 = 18; +static const uint8_t D33 = 33; +static const uint8_t D34 = 34; +static const uint8_t D35 = 35; +static const uint8_t D36 = 36; +static const uint8_t D37 = 37; +static const uint8_t D38 = 38; +static const uint8_t D39 = 39; +static const uint8_t D40 = 40; +static const uint8_t D41 = 41; + +// Camera +#define TFT_CAM_POWER 21 + +#define PWDN_GPIO_NUM -1 // connected through expander +#define RESET_GPIO_NUM -1 // connected through expander +#define XCLK_GPIO_NUM 15 +#define SIOD_GPIO_NUM SDA +#define SIOC_GPIO_NUM SCL + +#define Y9_GPIO_NUM 14 //16 +#define Y8_GPIO_NUM 13 //14 +#define Y7_GPIO_NUM 11 //13 +#define Y6_GPIO_NUM 10 +#define Y5_GPIO_NUM 9 //8 +#define Y4_GPIO_NUM 8 //6 +#define Y3_GPIO_NUM 7 +#define Y2_GPIO_NUM 6 //9 +#define VSYNC_GPIO_NUM 38 +#define HREF_GPIO_NUM 48 +#define PCLK_GPIO_NUM 16 //11 + +#endif /* Pins_Arduino_h */ diff --git a/variants/circuitart_zero_s3/tinyuf2.bin b/variants/circuitart_zero_s3/tinyuf2.bin new file mode 100644 index 0000000..5c4db29 Binary files /dev/null and b/variants/circuitart_zero_s3/tinyuf2.bin differ diff --git a/variants/cnrs_aw2eth/pins_arduino.h b/variants/cnrs_aw2eth/pins_arduino.h new file mode 100644 index 0000000..11b4ba8 --- /dev/null +++ b/variants/cnrs_aw2eth/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 9; +static const uint8_t SCL = 10; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 14; +static const uint8_t MISO = 13; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/codecell/pins_arduino.h b/variants/codecell/pins_arduino.h new file mode 100644 index 0000000..b4b0f0b --- /dev/null +++ b/variants/codecell/pins_arduino.h @@ -0,0 +1,25 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/connaxio_espoir/pins_arduino.h b/variants/connaxio_espoir/pins_arduino.h new file mode 100644 index 0000000..2a6a47e --- /dev/null +++ b/variants/connaxio_espoir/pins_arduino.h @@ -0,0 +1,77 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/* variant: Espoir + * vendor: Connaxio + * url: https://www.connaxio.com/electronics/espoir/ + */ + +#include + +/* USB UART */ +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +/* mikroBUS UART */ +static const uint8_t TX1 = 10; +static const uint8_t RX1 = 9; + +/* mikroBUS I2C */ +static const uint8_t SDA = 23; +static const uint8_t SCL = 18; + +/* mikroBUS SPI */ +static const uint8_t SS = 15; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +/* Default analog pins */ +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A6 = 34; + +/* Alternative analog pins */ +static const uint8_t A10 = 4; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; + +/* Touch pins */ +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; + +/* Other pin names */ +static const uint8_t AN = 36; +static const uint8_t RST = 5; +static const uint8_t PWM = 2; +static const uint8_t INT = 4; +static const uint8_t CS = 15; +static const uint8_t SDO = 13; +static const uint8_t SDI = 12; + +/* Ethernet interface */ +static const uint8_t ETH_INT = 35; +#define ETH_PHY_ADDR 0 +#define ETH_PHY_POWER -1 +#define ETH_PHY_MDC 32 +#define ETH_PHY_MDIO 33 +#define ETH_PHY_TYPE ETH_PHY_KSZ8081 +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN + +/* USB interface */ +#define USB_VID 0x10C4 // Silabs's VID +#define USB_PID 0x8D9A // Espoir's PID, requires Silab USB PHY +#define USB_MANUFACTURER "Connaxio" +#define USB_PRODUCT "Espoir" +#define USB_SERIAL "" + +#endif /* Pins_Arduino_h */ diff --git a/variants/crabik_slot_esp32_s3/pins_arduino.h b/variants/crabik_slot_esp32_s3/pins_arduino.h new file mode 100644 index 0000000..0f18a90 --- /dev/null +++ b/variants/crabik_slot_esp32_s3/pins_arduino.h @@ -0,0 +1,80 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x814D // for user apps (https://github.com/espressif/usb-pids/pull/77) +#define USB_MANUFACTURER "Crabik" +#define USB_PRODUCT "Slot ESP32-S3" +#define USB_SERIAL "" + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t S1 = 1; +static const uint8_t S2 = 12; +static const uint8_t S3 = 2; +static const uint8_t S4 = 11; +static const uint8_t S5 = 17; +static const uint8_t S6 = 18; +static const uint8_t S7 = 3; +static const uint8_t S8 = 4; +static const uint8_t S9 = 5; +static const uint8_t S10 = 6; +static const uint8_t S11 = 7; +static const uint8_t S12 = 8; +static const uint8_t S13 = 9; +static const uint8_t S14 = 10; +static const uint8_t S15 = 45; +static const uint8_t S16 = 46; +static const uint8_t S17 = 48; +static const uint8_t S18 = 47; +static const uint8_t S19 = 33; +static const uint8_t S20 = 34; + +static const uint8_t TX = S12; +static const uint8_t RX = S11; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 13; +static const uint8_t SCL = 14; +static const uint8_t D = SDA; +static const uint8_t C = SCL; + +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; +static const uint8_t DO = MOSI; +static const uint8_t DI = MISO; +static const uint8_t CLK = SCK; +static const uint8_t CS1 = S5; +static const uint8_t CS2 = S6; +static const uint8_t SS = CS1; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; + +static const uint8_t USB_DN = 19; +static const uint8_t USB_DP = 20; + +static const uint8_t BOOT_BTN = 0; +static const uint8_t USER_LED = LED_BUILTIN; + +static const uint8_t EN_TROYKA = 15; + +static const uint8_t LIPO_ALERT = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/cyobot_v2_esp32s3/pins_arduino.h b/variants/cyobot_v2_esp32s3/pins_arduino.h new file mode 100644 index 0000000..d913251 --- /dev/null +++ b/variants/cyobot_v2_esp32s3/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_MANUFACTURER "CYOBot" +#define USB_PRODUCT "CYOBrain ESP32S3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t BUTTON0 = 4; +static const uint8_t BUTTON1 = 38; +static const uint8_t LED = 24; + +static const uint8_t BAT_MEAS = 6; +#define BAT_VOLT_PIN BAT_MEAS +static const uint8_t CHAR_DET = 23; + +static const uint8_t NEO_BASE = 7; +static const uint8_t NEO_BRAIN = 15; + +static const uint8_t I2S0_MCLK = 16; +static const uint8_t I2S0_DSDIN = 8; +static const uint8_t I2S0_SCLK = 9; +static const uint8_t I2S0_LRCK = 45; + +static const uint8_t SDA = 17; +static const uint8_t SCL = 18; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 2; +static const uint8_t MISO = 42; +static const uint8_t SCK = 41; + +static const uint8_t ENCODER1_A = 39; +static const uint8_t ENCODER1_B = 40; +static const uint8_t ENCODER2_B = 19; +static const uint8_t ENCODER2_A = 20; + +static const uint8_t UART1_RXD = 3; +static const uint8_t UART1_TXD = 1; + +static const uint8_t GPIO46 = 46; +static const uint8_t ESP_IO0 = 0; + +static const uint8_t SD_OUT = 10; +static const uint8_t SD_SPI_MOSI = 11; +static const uint8_t SD_SPI_CLK = 12; +static const uint8_t SD_SPI_MISO = 13; +static const uint8_t SD_SPI_CS = 14; + +static const uint8_t PA_CTRL = 25; + +#endif /* Pins_Arduino_h */ diff --git a/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin b/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin new file mode 100644 index 0000000..6e7ea8a Binary files /dev/null and b/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin differ diff --git a/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv b/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/cytron_maker_feather_aiot_s3/pins_arduino.h b/variants/cytron_maker_feather_aiot_s3/pins_arduino.h new file mode 100644 index 0000000..566ae25 --- /dev/null +++ b/variants/cytron_maker_feather_aiot_s3/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80F8 +#define USB_MANUFACTURER "Cytron" +#define USB_PRODUCT "Maker Feather AIoT S3" +#define USB_SERIAL "" + +static const uint8_t LED_BUILTIN = 2; // Status LED. +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + 46; // RGB LED. +#define RGB_BUILTIN RGB_BUILTIN // necessary to make digitalWrite/digitalMode find it +#define RGB_BRIGHTNESS 64 + +#define LED LED_BUILTIN +#define RGB RGB_BUILTIN +#define RGB_LED_PIN RGB_BUILTIN +#define RGB_BRIGHTNESS 65 + +#define VP_EN 11 // V Peripheral Enable. +#define BUZZER 12 // Piezo Buzzer. +#define BOOT 0 // Boot Button. +#define BUTTON 3 // User Button. + +#define VIN 13 // Vin Sense. +#define VBATT 13 +#define BAT_VOLT_PIN VBATT +#define VOLTAGE_MONITOR 13 + +static const uint8_t TX = 15; +static const uint8_t RX = 16; + +static const uint8_t SDA = 42; +static const uint8_t SCL = 41; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 8; +static const uint8_t SCK = 17; +static const uint8_t MISO = 18; + +static const uint8_t A0 = 10; +static const uint8_t A1 = 9; +static const uint8_t A2 = 6; +static const uint8_t A3 = 5; +static const uint8_t A4 = 4; +static const uint8_t A5 = 7; + +static const uint8_t A6 = 17; +static const uint8_t A7 = 8; +static const uint8_t A8 = 18; +static const uint8_t A9 = 16; +static const uint8_t A10 = 15; +static const uint8_t A11 = 14; +static const uint8_t A12 = 13; + +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin b/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin new file mode 100644 index 0000000..a43bff0 Binary files /dev/null and b/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin differ diff --git a/variants/cytron_maker_feather_aiot_s3/variant.cpp b/variants/cytron_maker_feather_aiot_s3/variant.cpp new file mode 100644 index 0000000..9ac4da2 --- /dev/null +++ b/variants/cytron_maker_feather_aiot_s3/variant.cpp @@ -0,0 +1,36 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Wai Weng for Cytron Technologies + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // Turn on VPeripheral by default. + pinMode(VP_EN, OUTPUT); + digitalWrite(VP_EN, HIGH); +} +} diff --git a/variants/d-duino-32/pins_arduino.h b/variants/d-duino-32/pins_arduino.h new file mode 100644 index 0000000..b149554 --- /dev/null +++ b/variants/d-duino-32/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 4; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +// Wemos Grove Shield +static const uint8_t D1 = 5; +static const uint8_t D2 = 4; +static const uint8_t D3 = 0; +static const uint8_t D4 = 2; +static const uint8_t D5 = 14; +static const uint8_t D6 = 12; +static const uint8_t D7 = 13; +static const uint8_t D8 = 15; +static const uint8_t D9 = 3; +static const uint8_t D10 = 1; + +// OLed +static const uint8_t OLED_SCL = SCL; +static const uint8_t OLED_SDA = SDA; + +#endif /* Pins_Arduino_h */ diff --git a/variants/d1_mini32/pins_arduino.h b/variants/d1_mini32/pins_arduino.h new file mode 100644 index 0000000..1275629 --- /dev/null +++ b/variants/d1_mini32/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include <../d32/d32_core.h> + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +static const uint8_t _VBAT = 35; // battery voltage +#define BAT_VOLT_PIN _VBAT + +#define PIN_WIRE_SDA SDA // backward compatibility +#define PIN_WIRE_SCL SCL // backward compatibility + +static const uint8_t D0 = 26; +static const uint8_t D1 = 22; +static const uint8_t D2 = 21; +static const uint8_t D3 = 17; +static const uint8_t D4 = 16; +static const uint8_t D5 = 18; +static const uint8_t D6 = 19; +static const uint8_t D7 = 23; +static const uint8_t D8 = 5; +static const uint8_t RXD = 3; +static const uint8_t TXD = 1; + +#define PIN_SPI_SS SS // backward compatibility +#define PIN_SPI_MOSI MOSI // backward compatibility +#define PIN_SPI_MISO MISO // backward compatibility +#define PIN_SPI_SCK SCK // backward compatibility + +#define PIN_A0 A0 // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/d1_uno32/pins_arduino.h b/variants/d1_uno32/pins_arduino.h new file mode 100644 index 0000000..7eefc21 --- /dev/null +++ b/variants/d1_uno32/pins_arduino.h @@ -0,0 +1,55 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +// Board Pinmap: https://www.botnroll.com/en/esp/3639-wemos-d1-r32-w-esp32-uno-r3-pinout.html + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 2; +static const uint8_t A1 = 4; +static const uint8_t A2 = 35; +static const uint8_t A3 = 34; +static const uint8_t A4 = 36; +static const uint8_t A5 = 39; + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define PIN_WIRE_SDA SDA // backward compatibility +#define PIN_WIRE_SCL SCL // backward compatibility + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 26; +static const uint8_t D3 = 25; +static const uint8_t D4 = 17; +static const uint8_t D5 = 16; +static const uint8_t D6 = 27; +static const uint8_t D7 = 14; +static const uint8_t D8 = 12; +static const uint8_t D9 = 13; +static const uint8_t D10 = 5; +static const uint8_t D11 = 23; +static const uint8_t D12 = 19; +static const uint8_t D13 = 18; + +#define PIN_SPI_SS SS // backward compatibility +#define PIN_SPI_MOSI MOSI // backward compatibility +#define PIN_SPI_MISO MISO // backward compatibility +#define PIN_SPI_SCK SCK // backward compatibility + +#define PIN_A0 A0 // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/d32/d32_core.h b/variants/d32/d32_core.h new file mode 100644 index 0000000..3d63759 --- /dev/null +++ b/variants/d32/d32_core.h @@ -0,0 +1,46 @@ +#ifndef _D32_CORE_H_ +#define _D32_CORE_H_ + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif diff --git a/variants/d32/pins_arduino.h b/variants/d32/pins_arduino.h new file mode 100644 index 0000000..6b94d65 --- /dev/null +++ b/variants/d32/pins_arduino.h @@ -0,0 +1,13 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +static const uint8_t _VBAT = 35; // battery voltage +#define BAT_VOLT_PIN _VBAT + +#endif /* Pins_Arduino_h */ diff --git a/variants/d32_pro/pins_arduino.h b/variants/d32_pro/pins_arduino.h new file mode 100644 index 0000000..2e01636 --- /dev/null +++ b/variants/d32_pro/pins_arduino.h @@ -0,0 +1,23 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include <../d32/d32_core.h> + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t _VBAT = 35; // battery voltage +#define BAT_VOLT_PIN _VBAT + +#define TF_CS 4 // TF (Micro SD Card) CS pin +#define TS_CS 12 // Touch Screen CS pin +#define TFT_CS 14 // TFT CS pin +#define TFT_LED 32 // TFT backlight control pin +#define TFT_RST 33 // TFT reset pin +#define TFT_DC 27 // TFT DC pin + +#define SS TF_CS + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapkart/pins_arduino.h b/variants/deneyapkart/pins_arduino.h new file mode 100644 index 0000000..c03f1eb --- /dev/null +++ b/variants/deneyapkart/pins_arduino.h @@ -0,0 +1,89 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define LEDB LED_BUILTIN +#define LEDR 3 +#define LEDG 1 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY +#define BOOT GPKEY + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 4; +static const uint8_t SCL = 15; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 5; +static const uint8_t MISO = 18; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 34; +static const uint8_t A3 = 35; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; + +static const uint8_t T0 = 32; +static const uint8_t T1 = 33; +static const uint8_t T2 = 27; +static const uint8_t T3 = 14; +static const uint8_t T4 = 12; +static const uint8_t T5 = 13; + +static const uint8_t D0 = 23; +static const uint8_t D1 = 22; +static const uint8_t D2 = 1; +static const uint8_t D3 = 3; +static const uint8_t D4 = 21; +static const uint8_t D5 = 19; +static const uint8_t D6 = 18; +static const uint8_t D7 = 5; +static const uint8_t D8 = 0; +static const uint8_t D9 = 2; +static const uint8_t D10 = 4; +static const uint8_t D11 = 15; +static const uint8_t D12 = 13; +static const uint8_t D13 = 12; +static const uint8_t D14 = 14; +static const uint8_t D15 = 27; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t PWM0 = 23; +static const uint8_t PWM1 = 22; + +static const uint8_t CAMSD = 33; +static const uint8_t CAMSC = 25; +static const uint8_t CAMD2 = 19; +static const uint8_t CAMD3 = 22; +static const uint8_t CAMD4 = 23; +static const uint8_t CAMD5 = 21; +static const uint8_t CAMD6 = 18; +static const uint8_t CAMD7 = 26; +static const uint8_t CAMD8 = 35; +static const uint8_t CAMD9 = 34; +static const uint8_t CAMPC = 5; +static const uint8_t CAMXC = 32; +static const uint8_t CAMH = 39; +static const uint8_t CAMV = 36; + +static const uint8_t MICD = 12; +static const uint8_t MICC = 13; + +static const uint8_t IMUSD = 4; +static const uint8_t IMUSC = 15; + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapkart1A/pins_arduino.h b/variants/deneyapkart1A/pins_arduino.h new file mode 100644 index 0000000..b1f0c3f --- /dev/null +++ b/variants/deneyapkart1A/pins_arduino.h @@ -0,0 +1,89 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 13; //D12 +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY +#define BOOT GPKEY + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 4; +static const uint8_t SCL = 15; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 5; +static const uint8_t MISO = 18; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 34; +static const uint8_t A3 = 35; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; + +static const uint8_t T0 = 32; +static const uint8_t T1 = 33; +static const uint8_t T2 = 27; +static const uint8_t T3 = 14; +static const uint8_t T4 = 12; +static const uint8_t T5 = 13; + +static const uint8_t D0 = 23; +static const uint8_t D1 = 22; +static const uint8_t D2 = 1; +static const uint8_t D3 = 3; +static const uint8_t D4 = 21; +static const uint8_t D5 = 19; +static const uint8_t D6 = 18; +static const uint8_t D7 = 5; +static const uint8_t D8 = 0; +static const uint8_t D9 = 2; +static const uint8_t D10 = 4; +static const uint8_t D11 = 15; +static const uint8_t D12 = 13; +static const uint8_t D13 = 12; +static const uint8_t D14 = 14; +static const uint8_t D15 = 27; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t PWM0 = 23; +static const uint8_t PWM1 = 22; + +static const uint8_t CAMSD = 33; +static const uint8_t CAMSC = 25; +static const uint8_t CAMD2 = 19; +static const uint8_t CAMD3 = 22; +static const uint8_t CAMD4 = 23; +static const uint8_t CAMD5 = 21; +static const uint8_t CAMD6 = 18; +static const uint8_t CAMD7 = 26; +static const uint8_t CAMD8 = 35; +static const uint8_t CAMD9 = 34; +static const uint8_t CAMPC = 5; +static const uint8_t CAMXC = 32; +static const uint8_t CAMH = 39; +static const uint8_t CAMV = 36; + +static const uint8_t SDMI = 2; +static const uint8_t SDMO = 14; +static const uint8_t SDCS = 12; +static const uint8_t SDCK = 27; + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapkart1Av2/pins_arduino.h b/variants/deneyapkart1Av2/pins_arduino.h new file mode 100644 index 0000000..7e1e409 --- /dev/null +++ b/variants/deneyapkart1Av2/pins_arduino.h @@ -0,0 +1,107 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8147 +#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)" +#define USB_PRODUCT "DENEYAP KART 1A v2" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; //D9 +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 47; +static const uint8_t SCL = 21; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 39; +static const uint8_t MISO = 40; +static const uint8_t SCK = 41; + +static const uint8_t A0 = 4; +static const uint8_t A1 = 5; +static const uint8_t A2 = 6; +static const uint8_t A3 = 7; +static const uint8_t A4 = 15; +static const uint8_t A5 = 16; +static const uint8_t A6 = 17; +static const uint8_t A7 = 18; +static const uint8_t A8 = 9; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 5; +static const uint8_t T2 = 6; +static const uint8_t T3 = 7; +static const uint8_t T4 = 8; +static const uint8_t T5 = 3; +static const uint8_t T6 = 10; +static const uint8_t T7 = 1; +static const uint8_t T8 = 2; + +static const uint8_t D0 = 1; +static const uint8_t D1 = 2; +static const uint8_t D2 = 43; +static const uint8_t D3 = 44; +static const uint8_t D4 = 42; +static const uint8_t D5 = 41; +static const uint8_t D6 = 40; +static const uint8_t D7 = 39; +static const uint8_t D8 = 38; +static const uint8_t D9 = 48; +static const uint8_t D10 = 47; +static const uint8_t D11 = 21; +static const uint8_t D12 = 10; +static const uint8_t D13 = 3; +static const uint8_t D14 = 8; +static const uint8_t D15 = 0; +static const uint8_t D16 = 13; +static const uint8_t D17 = 12; +static const uint8_t D18 = 11; +static const uint8_t D19 = 14; + +static const uint8_t PWM0 = 15; +static const uint8_t PWM1 = 16; +static const uint8_t PWM2 = 17; +static const uint8_t PWM3 = 18; +static const uint8_t PWM4 = 38; + +static const uint8_t CAMSD = 4; +static const uint8_t CAMSC = 5; +static const uint8_t CAMD2 = 41; +static const uint8_t CAMD3 = 2; +static const uint8_t CAMD4 = 1; +static const uint8_t CAMD5 = 42; +static const uint8_t CAMD6 = 40; +static const uint8_t CAMD7 = 38; +static const uint8_t CAMD8 = 17; +static const uint8_t CAMD9 = 15; +static const uint8_t CAMPC = 39; +static const uint8_t CAMXC = 16; +static const uint8_t CAMH = 7; +static const uint8_t CAMV = 6; + +static const uint8_t SDMI = 14; +static const uint8_t SDMO = 12; +static const uint8_t SDCS = 11; +static const uint8_t SDCK = 13; + +static const uint8_t BAT = 9; +#define BAT_VOLT_PIN BAT + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapkartg/pins_arduino.h b/variants/deneyapkartg/pins_arduino.h new file mode 100644 index 0000000..f9d9048 --- /dev/null +++ b/variants/deneyapkartg/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x814A +#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)" +#define USB_PRODUCT "DENEYAP KART G" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 10; //D3 +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t GPKEY = 9; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY +#define BT GPKEY + +static const uint8_t TX = 21; +static const uint8_t RX = 20; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 8; +static const uint8_t SCL = 2; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; + +static const uint8_t D0 = 20; +static const uint8_t D1 = 21; +static const uint8_t D2 = 9; +static const uint8_t D3 = 10; +static const uint8_t D4 = 8; +static const uint8_t D5 = 7; +static const uint8_t D6 = 2; + +static const uint8_t PWM0 = 0; +static const uint8_t PWM1 = 1; +static const uint8_t PWM2 = 3; + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapkartv2/pins_arduino.h b/variants/deneyapkartv2/pins_arduino.h new file mode 100644 index 0000000..0167516 --- /dev/null +++ b/variants/deneyapkartv2/pins_arduino.h @@ -0,0 +1,124 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x82EB +#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)" +#define USB_PRODUCT "DENEYAP KART v2" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 46; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 47; +static const uint8_t SCL = 21; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 39; +static const uint8_t MISO = 40; +static const uint8_t SCK = 41; + +static const uint8_t A0 = 4; +static const uint8_t A1 = 5; +static const uint8_t A2 = 6; +static const uint8_t A3 = 7; +static const uint8_t A4 = 15; +static const uint8_t A5 = 16; +static const uint8_t A6 = 17; +static const uint8_t A7 = 18; +static const uint8_t A8 = 8; +static const uint8_t A9 = 9; +static const uint8_t A10 = 10; +static const uint8_t A11 = 11; +static const uint8_t A12 = 2; +static const uint8_t A13 = 1; +static const uint8_t A14 = 3; +static const uint8_t A15 = 12; +static const uint8_t A16 = 13; +static const uint8_t A17 = 14; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 5; +static const uint8_t T2 = 6; +static const uint8_t T3 = 7; +static const uint8_t T4 = 8; +static const uint8_t T5 = 9; +static const uint8_t T6 = 10; +static const uint8_t T7 = 11; +static const uint8_t T8 = 2; +static const uint8_t T9 = 1; +static const uint8_t T10 = 3; +static const uint8_t T11 = 12; +static const uint8_t T12 = 13; +static const uint8_t T13 = 14; + +static const uint8_t D0 = 1; +static const uint8_t D1 = 2; +static const uint8_t D2 = 43; +static const uint8_t D3 = 44; +static const uint8_t D4 = 42; +static const uint8_t D5 = 41; +static const uint8_t D6 = 40; +static const uint8_t D7 = 39; +static const uint8_t D8 = 38; +static const uint8_t D9 = 48; +static const uint8_t D10 = 47; +static const uint8_t D11 = 21; +static const uint8_t D12 = 11; +static const uint8_t D13 = 10; +static const uint8_t D14 = 9; +static const uint8_t D15 = 8; +static const uint8_t D16 = 18; +static const uint8_t D17 = 17; +static const uint8_t D18 = 16; +static const uint8_t D19 = 15; +static const uint8_t D20 = 7; +static const uint8_t D21 = 6; +static const uint8_t D22 = 5; +static const uint8_t D23 = 4; +static const uint8_t D24 = 46; +static const uint8_t D25 = 0; +static const uint8_t D26 = 3; +static const uint8_t D27 = 12; +static const uint8_t D28 = 13; +static const uint8_t D29 = 14; + +static const uint8_t CAMSD = 4; +static const uint8_t CAMSC = 5; +static const uint8_t CAMD2 = 41; +static const uint8_t CAMD3 = 2; +static const uint8_t CAMD4 = 1; +static const uint8_t CAMD5 = 42; +static const uint8_t CAMD6 = 40; +static const uint8_t CAMD7 = 38; +static const uint8_t CAMD8 = 17; +static const uint8_t CAMD9 = 15; +static const uint8_t CAMPC = 39; +static const uint8_t CAMXC = 16; +static const uint8_t CAMH = 7; +static const uint8_t CAMV = 6; + +static const uint8_t SDCM = 12; +static const uint8_t SDCK = 13; +static const uint8_t SDDA = 14; + +static const uint8_t BAT = 3; +#define BAT_VOLT_PIN BAT + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapmini/pins_arduino.h b/variants/deneyapmini/pins_arduino.h new file mode 100644 index 0000000..ee6ec69 --- /dev/null +++ b/variants/deneyapmini/pins_arduino.h @@ -0,0 +1,88 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x8141 +#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)" +#define USB_PRODUCT "DENEYAP MINI" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define LEDB LED_BUILTIN +#define LEDR 34 +#define LEDG 33 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY +#define BT GPKEY + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 36; +static const uint8_t SCL = 37; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 40; +static const uint8_t MISO = 39; +static const uint8_t SCK = 38; + +static const uint8_t A0 = 8; +static const uint8_t A1 = 9; +static const uint8_t A2 = 10; +static const uint8_t A3 = 11; +static const uint8_t A4 = 12; +static const uint8_t A5 = 13; +static const uint8_t A6 = 16; + +static const uint8_t T0 = 8; +static const uint8_t T1 = 9; +static const uint8_t T2 = 10; +static const uint8_t T3 = 11; +static const uint8_t T4 = 12; +static const uint8_t T5 = 13; + +static const uint8_t D0 = 44; +static const uint8_t D1 = 43; +static const uint8_t D2 = 42; +static const uint8_t D3 = 41; +static const uint8_t D4 = 40; +static const uint8_t D5 = 39; +static const uint8_t D6 = 38; +static const uint8_t D7 = 37; +static const uint8_t D8 = 36; +static const uint8_t D9 = 26; +static const uint8_t D10 = 21; +static const uint8_t D11 = 18; +static const uint8_t D12 = 17; +static const uint8_t D13 = 0; +static const uint8_t D14 = 35; +static const uint8_t D15 = 33; +static const uint8_t D16 = 34; + +static const uint8_t PWM0 = 42; +static const uint8_t PWM1 = 41; + +static const uint8_t DAC0 = 17; +static const uint8_t DAC1 = 18; + +/* +#define SD SDA +#define SC SCL + +#define MO MOSI +#define MI MISO +#define MC SCK + +#define DA0 DAC0 +#define DA1 DAC1 +*/ + +#endif /* Pins_Arduino_h */ diff --git a/variants/deneyapminiv2/pins_arduino.h b/variants/deneyapminiv2/pins_arduino.h new file mode 100644 index 0000000..009ca10 --- /dev/null +++ b/variants/deneyapminiv2/pins_arduino.h @@ -0,0 +1,88 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8144 +#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)" +#define USB_PRODUCT "DENEYAP MINI v2" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 33; //D14 +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGBLED LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t GPKEY = 0; +#define KEY_BUILTIN GPKEY +#define BUILTIN_KEY GPKEY + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 36; +static const uint8_t SCL = 37; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 40; +static const uint8_t MISO = 39; +static const uint8_t SCK = 38; + +static const uint8_t A0 = 7; +static const uint8_t A1 = 8; +static const uint8_t A2 = 9; +static const uint8_t A3 = 10; +static const uint8_t A4 = 11; +static const uint8_t A5 = 12; +static const uint8_t A6 = 13; +static const uint8_t A7 = 16; + +static const uint8_t T0 = 7; +static const uint8_t T1 = 8; +static const uint8_t T2 = 9; +static const uint8_t T3 = 10; +static const uint8_t T4 = 11; +static const uint8_t T5 = 12; +static const uint8_t T6 = 13; + +static const uint8_t D0 = 44; +static const uint8_t D1 = 43; +static const uint8_t D2 = 42; +static const uint8_t D3 = 41; +static const uint8_t D4 = 40; +static const uint8_t D5 = 39; +static const uint8_t D6 = 38; +static const uint8_t D7 = 37; +static const uint8_t D8 = 36; +static const uint8_t D9 = 26; +static const uint8_t D10 = 21; +static const uint8_t D11 = 18; +static const uint8_t D12 = 17; +static const uint8_t D13 = 0; +static const uint8_t D14 = 33; + +static const uint8_t PWM0 = 42; +static const uint8_t PWM1 = 41; + +static const uint8_t DAC0 = 17; +static const uint8_t DAC1 = 18; + +/* +#define SD SDA +#define SC SCL + +#define MO MOSI +#define MI MISO +#define MC SCK + +#define DA0 DAC0 +#define DA1 DAC1 +*/ + +#endif /* Pins_Arduino_h */ diff --git a/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin b/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..59fe0a4 Binary files /dev/null and b/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv b/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv new file mode 100644 index 0000000..164ba0d --- /dev/null +++ b/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv @@ -0,0 +1,11 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table, 0x8000, 4K + +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 1408K, +ota_1, 0, ota_1, 0x170000, 1408K, +uf2, app, factory,0x2d0000, 256K, +ffat, data, fat, 0x310000, 960K, diff --git a/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h b/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h new file mode 100644 index 0000000..7f053b3 --- /dev/null +++ b/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x80FF +#define USB_MANUFACTURER "Department of Alchemy" +#define USB_PRODUCT "MiniMain ESP32-S2" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +// RGB LED +#define PIN_RGB_LED 33 +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWritee() for blinking +#define RGB_BUILTIN (PIN_RGB_LED + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +#define RGBLED_NUM 1 // number of RGB LEDs +#define RGBLED_POWER 21 // power pin +#define RGBLED_POWER_ON HIGH // power pin state when on +#define PIN_SERVO 2 // servo pin +#define PIN_ISOLATED_INPUT 40 // optocoupled input + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 18; +static const uint8_t A1 = 17; +static const uint8_t A2 = 16; +static const uint8_t A3 = 15; +static const uint8_t A4 = 14; +static const uint8_t A5 = 8; + +static const uint8_t TX = 39; +static const uint8_t RX = 38; +#define TX1 TX +#define RX1 RX + +static const uint8_t T2 = 2; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin b/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..5ab2d2d Binary files /dev/null and b/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin differ diff --git a/variants/department_of_alchemy_minimain_esp32s2/variant.cpp b/variants/department_of_alchemy_minimain_esp32s2/variant.cpp new file mode 100644 index 0000000..ee4eaa8 --- /dev/null +++ b/variants/department_of_alchemy_minimain_esp32s2/variant.cpp @@ -0,0 +1,37 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // This board has a power control pin, and we must set it to output and high + // in order to enable the RGB LEDs. + pinMode(RGBLED_POWER, OUTPUT); + digitalWrite(RGBLED_POWER, HIGH); +} +} diff --git a/variants/dfrobot_beetle_esp32c3/pins_arduino.h b/variants/dfrobot_beetle_esp32c3/pins_arduino.h new file mode 100644 index 0000000..49fd71e --- /dev/null +++ b/variants/dfrobot_beetle_esp32c3/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x3343 +#define USB_PID 0x8364 +#define USB_MANUFACTURER "DFRobot" +#define USB_PRODUCT "Beetle ESP32-C3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = 10; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#define GDI_DISPLAY_FPC_INTERFACE +#ifdef GDI_DISPLAY_FPC_INTERFACE + +#define GDI_BLK LED_BUILTIN +#define GDI_SPI_SCLK SCK +#define GDI_SPI_MOSI MOSI +#define GDI_SPI_MISO MISO +#define GDI_DC A1 +#define GDI_RES A2 +#define GDI_CS SS +#define GDI_SDCS A0 +#define GDI_TCS A3 +#define GDI_SCL SCL +#define GDI_SDA SDA + +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_beetle_esp32c6/pins_arduino.h b/variants/dfrobot_beetle_esp32c6/pins_arduino.h new file mode 100644 index 0000000..fb3c1a7 --- /dev/null +++ b/variants/dfrobot_beetle_esp32c6/pins_arduino.h @@ -0,0 +1,22 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 19; +static const uint8_t SCL = 20; + +static const uint8_t SS = 4; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 21; +static const uint8_t SCK = 23; + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h new file mode 100644 index 0000000..57f7b60 --- /dev/null +++ b/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 19; +static const uint8_t SCL = 20; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 21; +static const uint8_t SCK = 23; + +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; + +static const uint8_t D2 = 8; +static const uint8_t D3 = 14; +static const uint8_t D6 = 1; +static const uint8_t D7 = 18; +static const uint8_t D9 = 9; +static const uint8_t D11 = 7; +static const uint8_t D12 = 6; +static const uint8_t D13 = 15; + +#define GDI_DISPLAY_FPC_INTERFACE +#ifdef GDI_DISPLAY_FPC_INTERFACE + +#define GDI_BLK D13 +#define GDI_SPI_SCLK SCK +#define GDI_SPI_MOSI MOSI +#define GDI_SPI_MISO MISO +#define GDI_DC D2 +#define GDI_RES D3 +#define GDI_CS D6 //LCD_CS +#define GDI_SDCS D7 +#define GDI_FCS -1 +#define GDI_TCS D12 +#define GDI_SCL SCL +#define GDI_SDA SDA +#define GDI_INT D11 +#define GDI_BUSY_TE -1 + +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h new file mode 100644 index 0000000..3048c5f --- /dev/null +++ b/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +typedef unsigned char uint8_t; + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +static const uint8_t TX2 = 17; +static const uint8_t RX2 = 16; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 25; +static const uint8_t D3 = 26; +static const uint8_t D4 = 27; +static const uint8_t D5 = 0; +static const uint8_t D6 = 14; +static const uint8_t D7 = 13; +static const uint8_t D8 = 5; +static const uint8_t D9 = 2; +static const uint8_t D10 = 17; +static const uint8_t D11 = 16; +static const uint8_t D12 = 4; +static const uint8_t D13 = 12; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 34; +static const uint8_t A3 = 35; +static const uint8_t A4 = 15; +static const uint8_t A5 = 35; +static const uint8_t A6 = 4; +static const uint8_t A7 = 0; +static const uint8_t A8 = 2; +static const uint8_t A9 = 13; +static const uint8_t A10 = 12; +static const uint8_t A11 = 14; +static const uint8_t A12 = 27; +static const uint8_t A13 = 25; +static const uint8_t A14 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h new file mode 100644 index 0000000..76a2e9a --- /dev/null +++ b/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h @@ -0,0 +1,81 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x3343 +#define USB_PID 0x83CF +#define USB_MANUFACTURER "DFRobot" +#define USB_PRODUCT "FireBeetle 2 ESP32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 1; +static const uint8_t SCL = 2; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 16; +static const uint8_t SCK = 17; + +static const uint8_t A0 = 4; +static const uint8_t A1 = 5; +static const uint8_t A2 = 6; +static const uint8_t A3 = 8; +static const uint8_t A4 = 10; +static const uint8_t A5 = 11; + +static const uint8_t D2 = 3; +static const uint8_t D3 = 38; +static const uint8_t D5 = 7; +static const uint8_t D6 = 18; +static const uint8_t D7 = 9; +static const uint8_t D9 = 0; +static const uint8_t D10 = 14; +static const uint8_t D11 = 13; +static const uint8_t D12 = 12; +static const uint8_t D13 = 21; +static const uint8_t D14 = 47; + +static const uint8_t LED_BUILTIN = D13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#define GDI_DISPLAY_FPC_INTERFACE +#ifdef GDI_DISPLAY_FPC_INTERFACE + +#define GDI_BLK 21 +#define GDI_SPI_SCLK SCK +#define GDI_SPI_MOSI MOSI +#define GDI_SPI_MISO MISO +#define GDI_DC 3 +#define GDI_RES 38 +#define GDI_CS 18 +#define GDI_SDCS 9 +#define GDI_FCS 7 +#define GDI_TCS 12 +#define GDI_SCL SCL +#define GDI_SDA SDA +#define GDI_INT 13 +#define GDI_BUSY_TE 14 + +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_lorawan_esp32s3/pins_arduino.h b/variants/dfrobot_lorawan_esp32s3/pins_arduino.h new file mode 100644 index 0000000..c690cac --- /dev/null +++ b/variants/dfrobot_lorawan_esp32s3/pins_arduino.h @@ -0,0 +1,34 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define LED_BUILTIN 21 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +#define LORA_ANTPWR 42 //RXEN +#define LORA_RST 41 //RST +#define LORA_BUSY 40 //BUSY +#define LORA_DIO1 4 //DIO + +static const uint8_t LORA_SS = 10; +static const uint8_t LORA_MOSI = 6; +static const uint8_t LORA_MISO = 5; +static const uint8_t LORA_SCK = 7; + +static const uint8_t SS = 17; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +#define TFT_DC 14 +#define TFT_CS 17 +#define TFT_RST 15 +#define TFT_BL 16 // Backlight pin + +#endif /* Pins_Arduino_h */ diff --git a/variants/dfrobot_romeo_esp32s3/pins_arduino.h b/variants/dfrobot_romeo_esp32s3/pins_arduino.h new file mode 100644 index 0000000..3eb3f56 --- /dev/null +++ b/variants/dfrobot_romeo_esp32s3/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 1; +static const uint8_t SCL = 2; + +static const uint8_t MOSI = 15; +static const uint8_t MISO = 16; +static const uint8_t SCK = 17; +static const uint8_t SS = 18; + +#define GDI_DISPLAY_FPC_INTERFACE +#ifdef GDI_DISPLAY_FPC_INTERFACE + +#define GDI_BLK 21 +#define GDI_SPI_SCLK SCK +#define GDI_SPI_MOSI MOSI +#define GDI_SPI_MISO MISO +#define GDI_DC 3 +#define GDI_RES 38 +#define GDI_CS 18 +#define GDI_SDCS 0 +#define GDI_FCS 7 +#define GDI_TCS 12 +#define GDI_SCL SCL +#define GDI_SDA SDA +#define GDI_INT 13 +#define GDI_BUSY_TE 14 + +#endif /* GDI_DISPLAY_FPC_INTERFACE */ + +// CAM +#define CAM_DVP_INTERFACE +#ifdef CAM_DVP_INTERFACE + +#define CAM_D5 4 +#define CAM_PCLK 5 +#define CAM_VSYNC 6 +#define CAM_D6 7 +#define CAM_D7 8 +#define CAM_D8 46 +#define CAM_D9 48 +#define CAM_XMCLK 45 +#define CAM_D2 39 +#define CAM_D3 40 +#define CAM_D4 41 +#define CAM_HREF 42 +#define CAM_SCL SCL +#define CAM_SDA SDA + +#endif /* CAM_DVP_INTERFACE */ + +// Motor +#define MOTOR_INTERFACE +#ifdef MOTOR_INTERFACE + +#define M1_EN 12 +#define M1_PH 13 +#define M2_EN 14 +#define M2_PH 21 +#define M3_EN 9 +#define M3_PH 10 +#define M4_EN 47 +#define M4_PH 11 + +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/doitESP32devkitV1/pins_arduino.h b/variants/doitESP32devkitV1/pins_arduino.h new file mode 100644 index 0000000..8e1d004 --- /dev/null +++ b/variants/doitESP32devkitV1/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/doitESPduino32/pins_arduino.h b/variants/doitESPduino32/pins_arduino.h new file mode 100644 index 0000000..ff6f071 --- /dev/null +++ b/variants/doitESPduino32/pins_arduino.h @@ -0,0 +1,94 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +//SPI +static const uint8_t IO5 = 5; //SS +static const uint8_t IO23 = 23; //MOSI +static const uint8_t IO19 = 19; //MISO +static const uint8_t IO18 = 18; //SCK + +static const uint8_t SS = IO5; +static const uint8_t MOSI = IO23; +static const uint8_t MISO = IO19; +static const uint8_t SCK = IO18; + +//ANALOG +static const uint8_t IO36 = 36; +static const uint8_t IO39 = 39; +static const uint8_t IO4 = 4; +static const uint8_t IO2 = 2; +static const uint8_t IO35 = 35; +//ANALOG+ +static const uint8_t IO15 = 15; +static const uint8_t IO33 = 33; +static const uint8_t IO32 = 32; +static const uint8_t IO0 = 0; + +//DIGITAL +static const uint8_t IO13 = 13; +static const uint8_t IO12 = 12; +static const uint8_t IO14 = 14; +static const uint8_t IO27 = 27; +static const uint8_t IO16 = 16; +static const uint8_t IO17 = 17; +static const uint8_t IO25 = 25; +static const uint8_t IO26 = 26; +static const uint8_t TX0 = 1; +static const uint8_t RX0 = 3; +//TFlash(uSD) +static const uint8_t SD2 = 9; +static const uint8_t SD3 = 10; +static const uint8_t CMD = 11; +static const uint8_t CLK = 6; +static const uint8_t SD0 = 7; +static const uint8_t SD1 = 8; + +//Arduino Uno backward compatibility +static const uint8_t A0 = 2; +static const uint8_t A1 = 4; +static const uint8_t A2 = 35; +static const uint8_t A3 = 34; +static const uint8_t A4 = 36; +static const uint8_t A5 = 39; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 26; +static const uint8_t D3 = 25; +static const uint8_t D4 = 17; +static const uint8_t D5 = 16; +static const uint8_t D6 = 27; +static const uint8_t D7 = 14; +static const uint8_t D8 = 12; +static const uint8_t D9 = 13; +static const uint8_t D10 = 5; +static const uint8_t D11 = 23; +static const uint8_t D12 = 19; +static const uint8_t D13 = 18; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define PIN_WIRE_SDA SDA // backward compatibility +#define PIN_WIRE_SCL SCL // backward compatibility + +#define PIN_SPI_SS SS // backward compatibility +#define PIN_SPI_MOSI MOSI // backward compatibility +#define PIN_SPI_MISO MISO // backward compatibility +#define PIN_SPI_SCK SCK // backward compatibility + +#define PIN_A0 A0 // backward compatibility + +// ESP-WROOM-32 does not have GPIO 14, 20(NC), 24, 28, 29, 30, 31, 36, 37, 38, 40+ +// All pins should be PWM capable. The board is a clone of WeMos D1 R32. + +#endif /* Pins_Arduino_h */ diff --git a/variants/dpu_esp32/pins_arduino.h b/variants/dpu_esp32/pins_arduino.h new file mode 100644 index 0000000..adc8ebd --- /dev/null +++ b/variants/dpu_esp32/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; +static const uint8_t SS = 15; + +static const uint8_t TP_RST = 21; +static const uint8_t TP_INT = 19; +static const uint8_t TFT_BL = 18; +static const uint8_t TFT_CS = 15; +static const uint8_t TFT_DC = 27; +static const uint8_t TFT_RST = 32; +static const uint8_t SD_CS = 23; +static const uint8_t SD_CD = 22; +#endif /* Pins_Arduino_h */ diff --git a/variants/elecrow_crowpanel_7/pins_arduino.h b/variants/elecrow_crowpanel_7/pins_arduino.h new file mode 100644 index 0000000..6b55d35 --- /dev/null +++ b/variants/elecrow_crowpanel_7/pins_arduino.h @@ -0,0 +1,65 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x1a86 +#define USB_PID 0x7523 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 37; +static const uint8_t RX = 40; + +static const uint8_t TXD2 = 17; +static const uint8_t RXD2 = 18; + +static const uint8_t SDA = 19; +static const uint8_t SCL = 20; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G17 = 17; +static const uint8_t G18 = 18; +static const uint8_t G19 = 19; +static const uint8_t G20 = 20; +static const uint8_t G21 = 21; +static const uint8_t G33 = 33; +static const uint8_t G34 = 34; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G45 = 45; +static const uint8_t G46 = 46; +static const uint8_t G47 = 47; +static const uint8_t G48 = 48; + +static const uint8_t ADC = 38; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-devkit-lipo/pins_arduino.h b/variants/esp32-devkit-lipo/pins_arduino.h new file mode 100644 index 0000000..44dfe7c --- /dev/null +++ b/variants/esp32-devkit-lipo/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define TX1 33 // Ext1 pin 8 +#define RX1 25 // Ext1 pin 9 + +#define TX2 19 // Ext2 pin 8 +#define RX2 18 // Ext2 pin 9 + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-evb/pins_arduino.h b/variants/esp32-evb/pins_arduino.h new file mode 100644 index 0000000..346ef1f --- /dev/null +++ b/variants/esp32-evb/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t KEY_BUILTIN = 34; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define TX1 4 +#define RX1 36 + +#define TX2 17 +#define RX2 16 + +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_PHY_ADDR 0 +#define ETH_PHY_MDC 23 +#define ETH_PHY_MDIO 18 +#define ETH_PHY_POWER -1 // no GPIO used to toggle power supply, always on +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN // clock supplied by CR1 + +static const uint8_t SDA = 13; +static const uint8_t SCL = 16; + +static const uint8_t SS = 17; +static const uint8_t MOSI = 2; +static const uint8_t MISO = 15; +static const uint8_t SCK = 14; + +#define BOARD_HAS_1BIT_SDMMC +#define BOARD_MAX_SDMMC_FREQ SDMMC_FREQ_DEFAULT + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-gateway/pins_arduino.h b/variants/esp32-gateway/pins_arduino.h new file mode 100644 index 0000000..64f7ad0 --- /dev/null +++ b/variants/esp32-gateway/pins_arduino.h @@ -0,0 +1,43 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#if defined(ARDUINO_ESP32_GATEWAY_E) || defined(ARDUINO_ESP32_GATEWAY_F) +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_PHY_ADDR 0 +#define ETH_PHY_MDC 23 +#define ETH_PHY_MDIO 18 +#define ETH_PHY_POWER 5 +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT +#endif + +static const uint8_t LED_BUILTIN = 33; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 34; + +static const uint8_t SCL = 16; // This is extension pin 11 +static const uint8_t SDA = 32; // This is extension pin 13 + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A7 = 35; + +static const uint8_t T9 = 32; + +#if defined(ARDUINO_ESP32_GATEWAY_F) +#define BOARD_HAS_1BIT_SDMMC +#endif + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-gateway/variant.cpp b/variants/esp32-gateway/variant.cpp new file mode 100644 index 0000000..045cc14 --- /dev/null +++ b/variants/esp32-gateway/variant.cpp @@ -0,0 +1,35 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Olimex Ltd (support@olimex.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" +#include "driver/gpio.h" + +extern "C" { +// Initialize variant/board, called before setup() +void initVariant(void) { + // Change the drive strength of the digital output num 17 from the default value 20mA to 5mA + gpio_set_drive_capability((gpio_num_t)GPIO_NUM_17, GPIO_DRIVE_CAP_0); +} +} diff --git a/variants/esp32-poe-iso/pins_arduino.h b/variants/esp32-poe-iso/pins_arduino.h new file mode 100644 index 0000000..7a6f59e --- /dev/null +++ b/variants/esp32-poe-iso/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_PHY_ADDR 0 +#define ETH_PHY_MDC 23 +#define ETH_PHY_MDIO 18 +#define ETH_PHY_POWER 12 +#if defined BOARD_HAS_PSRAM // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_OUT +#else +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT +#endif + +static const uint8_t KEY_BUILTIN = 34; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define TX1 4 +#define RX1 36 + +#define TX2 33 // ext2 pin 5 +#define RX2 35 // ext2 pin 3 + +static const uint8_t SDA = 13; +#if defined BOARD_HAS_PSRAM // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO +static const uint8_t SCL = 33; +#else +static const uint8_t SCL = 16; +#endif + +static const uint8_t SS = 5; +static const uint8_t MOSI = 2; +static const uint8_t MISO = 15; +static const uint8_t SCK = 14; + +#define BOARD_HAS_1BIT_SDMMC + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-poe/pins_arduino.h b/variants/esp32-poe/pins_arduino.h new file mode 100644 index 0000000..7a6f59e --- /dev/null +++ b/variants/esp32-poe/pins_arduino.h @@ -0,0 +1,42 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_PHY_ADDR 0 +#define ETH_PHY_MDC 23 +#define ETH_PHY_MDIO 18 +#define ETH_PHY_POWER 12 +#if defined BOARD_HAS_PSRAM // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_OUT +#else +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT +#endif + +static const uint8_t KEY_BUILTIN = 34; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define TX1 4 +#define RX1 36 + +#define TX2 33 // ext2 pin 5 +#define RX2 35 // ext2 pin 3 + +static const uint8_t SDA = 13; +#if defined BOARD_HAS_PSRAM // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO +static const uint8_t SCL = 33; +#else +static const uint8_t SCL = 16; +#endif + +static const uint8_t SS = 5; +static const uint8_t MOSI = 2; +static const uint8_t MISO = 15; +static const uint8_t SCK = 14; + +#define BOARD_HAS_1BIT_SDMMC + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-sbc-fabgl/pins_arduino.h b/variants/esp32-sbc-fabgl/pins_arduino.h new file mode 100644 index 0000000..3663de7 --- /dev/null +++ b/variants/esp32-sbc-fabgl/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h b/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h new file mode 100644 index 0000000..12d35f7 --- /dev/null +++ b/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 18; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define TX1 12 +#define RX1 13 +#define TX2 33 +#define RX2 39 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SCL = 4; +static const uint8_t SDA = 15; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 32; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +#define ETH_PHY_ADDR 1 +#define ETH_PHY_POWER 2 +#define ETH_PHY_MDC 16 +#define ETH_PHY_MDIO 14 +#define ETH_PHY_TYPE ETH_PHY_DP83848 +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h b/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h new file mode 100644 index 0000000..4be9c7f --- /dev/null +++ b/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 18; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define TX1 12 +#define RX1 13 +#define TX2 33 +#define RX2 39 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SCL = 4; +static const uint8_t SDA = 15; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 32; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +#define ETH_PHY_ADDR 0 +#define ETH_PHY_POWER 2 +#define ETH_PHY_MDC 16 +#define ETH_PHY_MDIO 14 +#define ETH_PHY_TYPE ETH_PHY_RTL8201 +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32-trueverit-iot-driver/pins_arduino.h b/variants/esp32-trueverit-iot-driver/pins_arduino.h new file mode 100644 index 0000000..2f1edcf --- /dev/null +++ b/variants/esp32-trueverit-iot-driver/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 18; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define TX1 12 +#define RX1 13 +#define TX2 33 +#define RX2 39 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SCL = 4; +static const uint8_t SDA = 15; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 32; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +#define ETH_PHY_ADDR 0 +#define ETH_PHY_POWER -1 +#define ETH_PHY_MDC 16 +#define ETH_PHY_MDIO 14 +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32/pins_arduino.h b/variants/esp32/pins_arduino.h new file mode 100644 index 0000000..3663de7 --- /dev/null +++ b/variants/esp32/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp320/pins_arduino.h b/variants/esp320/pins_arduino.h new file mode 100644 index 0000000..cb9152a --- /dev/null +++ b/variants/esp320/pins_arduino.h @@ -0,0 +1,21 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 2; +static const uint8_t SCL = 14; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv b/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv new file mode 100644 index 0000000..d3b9316 --- /dev/null +++ b/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0xFE0000, +coredump, data,coredump, 0xFF0000, 0x10000, diff --git a/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv b/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv new file mode 100644 index 0000000..431c235 --- /dev/null +++ b/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000,0x200000, +app1, app, ota_1, 0x210000,0x200000, +spiffs, data, spiffs, 0x410000,0xBE0000, +coredump, data, coredump,0xFF0000,0x10000, diff --git a/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv b/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv new file mode 100644 index 0000000..a048343 --- /dev/null +++ b/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x480000, +app1, app, ota_1, 0x490000,0x480000, +spiffs, data, spiffs, 0x910000,0x6E0000, +coredump, data, coredump,0xFF0000,0x10000, diff --git a/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv b/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv new file mode 100644 index 0000000..840a2f0 --- /dev/null +++ b/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000,0x7F0000, +app1, app, ota_1, 0x800000,0x7F0000, +coredump, data,coredump, 0xFF0000, 0x10000, diff --git a/variants/esp32_s3r8n16/pins_arduino.h b/variants/esp32_s3r8n16/pins_arduino.h new file mode 100644 index 0000000..ca2dda0 --- /dev/null +++ b/variants/esp32_s3r8n16/pins_arduino.h @@ -0,0 +1,23 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 +#define USB_MANUFACTURER "4D Systems Pty Ltd" +#define USB_PRODUCT "4D Systems gen4-ESP32 16MB Modules (ESP32-S3R8n16)" +//#define USB_CLASS 2 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 17; +static const uint8_t SCL = 18; + +static const uint8_t SS = -1; // Modified elsewhere +static const uint8_t MOSI = -1; // Modified elsewhere +static const uint8_t MISO = -1; // Modified elsewhere +static const uint8_t SCK = -1; // Modified elsewhere + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c2/pins_arduino.h b/variants/esp32c2/pins_arduino.h new file mode 100644 index 0000000..70024ea --- /dev/null +++ b/variants/esp32c2/pins_arduino.h @@ -0,0 +1,28 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 20; +static const uint8_t RX = 19; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c3-devkit-lipo/pins_arduino.h b/variants/esp32c3-devkit-lipo/pins_arduino.h new file mode 100644 index 0000000..318882b --- /dev/null +++ b/variants/esp32c3-devkit-lipo/pins_arduino.h @@ -0,0 +1,39 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUT_BUILTIN = 9; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +// define I2C pins +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; +// define SPI pins +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +// external power sense - disabled by default - check the schematic +//static const uint8_t PWR_SENSE = 4; +// battery measurement - disabled by default - check the schematic +//static const uint8_t BAT_SENSE = 3; +// #define BAT_VOLT_PIN BAT_SENSE +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c3/pins_arduino.h b/variants/esp32c3/pins_arduino.h new file mode 100644 index 0000000..179ce63 --- /dev/null +++ b/variants/esp32c3/pins_arduino.h @@ -0,0 +1,34 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c5/pins_arduino.h b/variants/esp32c5/pins_arduino.h new file mode 100644 index 0000000..e3a7e57 --- /dev/null +++ b/variants/esp32c5/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 27 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 11; +static const uint8_t RX = 12; + +// static const uint8_t USB_DM = 13; +// static const uint8_t USB_DP = 14; + +static const uint8_t SDA = 0; +static const uint8_t SCL = 1; + +static const uint8_t SS = 6; +static const uint8_t MOSI = 8; +static const uint8_t MISO = 9; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; + +// LP I2C Pins are fixed on ESP32-C5 +static const uint8_t LP_SDA = 2; +static const uint8_t LP_SCL = 3; +#define WIRE1_PIN_DEFINED +#define SDA1 LP_SDA +#define SCL1 LP_SCL + +// LP UART Pins are fixed on ESP32-C5 +static const uint8_t LP_RX = 4; +static const uint8_t LP_TX = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c6-evb/pins_arduino.h b/variants/esp32c6-evb/pins_arduino.h new file mode 100644 index 0000000..a0b0d80 --- /dev/null +++ b/variants/esp32c6-evb/pins_arduino.h @@ -0,0 +1,49 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUT_BUILTIN = 9; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN + +#define REL1 10 +#define REL2 11 +#define REL3 22 +#define REL4 23 + +#define DIN1 1 +#define DIN2 2 +#define DIN3 3 +#define DIN4 15 + +// available at UEXT and pUEXT + +static const uint8_t TX1 = 5; +static const uint8_t RX1 = 4; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 20; +static const uint8_t SCK = 19; +// available at UEXT and pUEXT - + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c6/pins_arduino.h b/variants/esp32c6/pins_arduino.h new file mode 100644 index 0000000..348db9f --- /dev/null +++ b/variants/esp32c6/pins_arduino.h @@ -0,0 +1,40 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 19; +static const uint8_t MISO = 20; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +// LP I2C Pins are fixed on ESP32-C6 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32c61/pins_arduino.h b/variants/esp32c61/pins_arduino.h new file mode 100644 index 0000000..dd25d0e --- /dev/null +++ b/variants/esp32c61/pins_arduino.h @@ -0,0 +1,37 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 11; +static const uint8_t RX = 10; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 25; +static const uint8_t MOSI = 26; +static const uint8_t MISO = 27; +static const uint8_t SCK = 28; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +// LP I2C Pins are fixed on ESP32-C61 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32da/pins_arduino.h b/variants/esp32da/pins_arduino.h new file mode 100644 index 0000000..212cb93 --- /dev/null +++ b/variants/esp32da/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#define BOARD_HAS_DUAL_ANTENNA +static const uint8_t ANT1 = 2; +static const uint8_t ANT2 = 25; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32h2-devkit-lipo/pins_arduino.h b/variants/esp32h2-devkit-lipo/pins_arduino.h new file mode 100644 index 0000000..bb15be3 --- /dev/null +++ b/variants/esp32h2-devkit-lipo/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t KEY_BUILTIN = 9; + +static const uint8_t TX = 24; +static const uint8_t RX = 23; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 22; + +static const uint8_t SS = 0; +static const uint8_t MOSI = 25; +static const uint8_t MISO = 11; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32h2/pins_arduino.h b/variants/esp32h2/pins_arduino.h new file mode 100644 index 0000000..108d874 --- /dev/null +++ b/variants/esp32h2/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 24; +static const uint8_t RX = 23; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 22; + +static const uint8_t SS = 0; +static const uint8_t MOSI = 25; +static const uint8_t MISO = 11; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32micromod/pins_arduino.h b/variants/esp32micromod/pins_arduino.h new file mode 100644 index 0000000..24f6be1 --- /dev/null +++ b/variants/esp32micromod/pins_arduino.h @@ -0,0 +1,67 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#define TX1 17 +#define RX1 16 + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; +static const uint8_t I2C_INT = 4; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 26; +static const uint8_t SCL1 = 25; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 34; +static const uint8_t A1 = 35; +static const uint8_t BATT_VIN = 39; +#define BAT_VOLT_PIN BATT_VIN + +static const uint8_t PWM0 = 13; +static const uint8_t PWM1 = 12; + +static const uint8_t D0 = 14; +static const uint8_t D1 = 27; + +static const uint8_t G0 = 15; +static const uint8_t G1 = 25; +static const uint8_t G2 = 26; +static const uint8_t G3 = 17; +static const uint8_t G4 = 16; +static const uint8_t G5 = 32; +static const uint8_t G6 = 33; + +static const uint8_t AUD_OUT = 17; +static const uint8_t AUD_IN = 16; +static const uint8_t AUD_LRCLK = 25; +static const uint8_t AUD_BCLK = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32p4/pins_arduino.h b/variants/esp32p4/pins_arduino.h new file mode 100644 index 0000000..cbb1e87 --- /dev/null +++ b/variants/esp32p4/pins_arduino.h @@ -0,0 +1,85 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BOOT_MODE 35 +// BOOT_MODE2 36 pullup + +static const uint8_t TX = 37; +static const uint8_t RX = 38; + +static const uint8_t SDA = 7; +static const uint8_t SCL = 8; + +// Use GPIOs 36 or lower on the P4 DevKit to avoid LDO power issues with high numbered GPIOs. +static const uint8_t SS = 26; +static const uint8_t MOSI = 32; +static const uint8_t MISO = 33; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 16; +static const uint8_t A1 = 17; +static const uint8_t A2 = 18; +static const uint8_t A3 = 19; +static const uint8_t A4 = 20; +static const uint8_t A5 = 21; +static const uint8_t A6 = 22; +static const uint8_t A7 = 23; +static const uint8_t A8 = 49; +static const uint8_t A9 = 50; +static const uint8_t A10 = 51; +static const uint8_t A11 = 52; +static const uint8_t A12 = 53; +static const uint8_t A13 = 54; + +static const uint8_t T0 = 2; +static const uint8_t T1 = 3; +static const uint8_t T2 = 4; +static const uint8_t T3 = 5; +static const uint8_t T4 = 6; +static const uint8_t T5 = 7; +static const uint8_t T6 = 8; +static const uint8_t T7 = 9; +static const uint8_t T8 = 10; +static const uint8_t T9 = 11; +static const uint8_t T10 = 12; +static const uint8_t T11 = 13; +static const uint8_t T12 = 14; +static const uint8_t T13 = 15; + +/* ESP32-P4 EV Function board specific definitions */ +//ETH +#define ETH_PHY_TYPE ETH_PHY_TLK110 +#define ETH_PHY_ADDR 1 +#define ETH_PHY_MDC 31 +#define ETH_PHY_MDIO 52 +#define ETH_PHY_POWER 51 +#define ETH_RMII_TX_EN 49 +#define ETH_RMII_TX0 34 +#define ETH_RMII_TX1 35 +#define ETH_RMII_RX0 29 +#define ETH_RMII_RX1_EN 30 +#define ETH_RMII_CRS_DV 28 +#define ETH_RMII_CLK 50 +#define ETH_CLK_MODE EMAC_CLK_EXT_IN + +//SDMMC +#define BOARD_HAS_SDMMC +#define BOARD_SDMMC_SLOT 0 +#define BOARD_SDMMC_POWER_CHANNEL 4 +#define BOARD_SDMMC_POWER_PIN 45 +#define BOARD_SDMMC_POWER_ON_LEVEL LOW + +//WIFI - ESP32C6 +#define BOARD_HAS_SDIO_ESP_HOSTED +#define BOARD_SDIO_ESP_HOSTED_CLK 18 +#define BOARD_SDIO_ESP_HOSTED_CMD 19 +#define BOARD_SDIO_ESP_HOSTED_D0 14 +#define BOARD_SDIO_ESP_HOSTED_D1 15 +#define BOARD_SDIO_ESP_HOSTED_D2 16 +#define BOARD_SDIO_ESP_HOSTED_D3 17 +#define BOARD_SDIO_ESP_HOSTED_RESET 54 + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32p4_4ds_mipi/pins_arduino.h b/variants/esp32p4_4ds_mipi/pins_arduino.h new file mode 100644 index 0000000..d4a1109 --- /dev/null +++ b/variants/esp32p4_4ds_mipi/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// Use default UART0 pins +static const uint8_t TX = 37; +static const uint8_t RX = 38; + +// Default pins (7 and 8) are used by on-board components already, +// for libraries, this can be set manually +// so let's keep the default for the user +static const uint8_t SDA = 2; // careful, also used as T0 pin +static const uint8_t SCL = 3; // careful, also used as T1 pin + +static const uint8_t SCK = 6; // careful, also used as T2 pin +static const uint8_t MOSI = 14; // careful, also used as T1 pin +static const uint8_t MISO = 15; // careful, also used as T0 pin +static const uint8_t SS = 16; // careful, also used as A9 pin + +static const uint8_t A0 = 21; +static const uint8_t A1 = 20; +static const uint8_t A2 = 19; +static const uint8_t A3 = 18; +static const uint8_t A4 = 17; +static const uint8_t A5 = 52; +static const uint8_t A6 = 51; +static const uint8_t A7 = 50; +static const uint8_t A8 = 49; +static const uint8_t A9 = 16; // careful, also used as SPI SS pin + +static const uint8_t T0 = 15; // careful, also used as SPI MISO pin +static const uint8_t T1 = 14; // careful, also used as SPI MOSI pin +static const uint8_t T2 = 6; // careful, also used as SPI SCK pin +static const uint8_t T3 = 3; // careful, also used as I2C SCL pin +static const uint8_t T4 = 2; // careful, also used as I2C SDA pin + +/* 4D Systems ESP32-P4 board specific definitions */ +// LCD +#define LCD_INTERFACE_MIPI + +#define LCD_BL_IO 22 +#define LCD_BL_ON_LEVEL 1 +#define LCD_BL_OFF_LEVEL !LCD_BL_ON_LEVEL + +#define LCD_RST_IO 23 +#define LCD_RST_ACTIVE_HIGH true + +// I2C for on-board components +#define I2C_SDA 7 +#define I2C_SCL 8 + +// Touch +#define CTP_RST 4 +#define CTP_INT 5 + +// Audio +#define AMP_CTRL 53 +#define I2S_DSDIN 9 +#define I2S_LRCK 10 +#define I2S_ASDOUT 11 +#define I2S_SCLK 12 +#define I2S_MCLK 13 + +// SDMMC +#define BOARD_HAS_SDMMC +#define BOARD_SDMMC_SLOT 0 +#define BOARD_SDMMC_POWER_CHANNEL 4 +#define BOARD_SDMMC_POWER_PIN 45 +#define BOARD_SDMMC_POWER_ON_LEVEL LOW + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32p4_4ds_mipi_round/pins_arduino.h b/variants/esp32p4_4ds_mipi_round/pins_arduino.h new file mode 100644 index 0000000..c017db2 --- /dev/null +++ b/variants/esp32p4_4ds_mipi_round/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// Use default UART0 pins +static const uint8_t TX = 37; +static const uint8_t RX = 38; + +// Default pins (7 and 8) are used by on-board components already, +// for libraries, this can be set manually +// so let's keep the default for the user +static const uint8_t SDA = 2; // careful, also used as T0 pin +static const uint8_t SCL = 3; // careful, also used as T1 pin + +static const uint8_t SCK = 6; // careful, also used as T2 pin +static const uint8_t MOSI = 14; // careful, also used as T1 pin +static const uint8_t MISO = 15; // careful, also used as T0 pin +static const uint8_t SS = 16; // careful, also used as A9 pin + +static const uint8_t A0 = 21; +static const uint8_t A1 = 20; +static const uint8_t A2 = 19; +static const uint8_t A3 = 18; +static const uint8_t A4 = 17; +static const uint8_t A5 = 52; +static const uint8_t A6 = 51; +static const uint8_t A7 = 50; +static const uint8_t A8 = 49; +static const uint8_t A9 = 16; // careful, also used as SPI SS pin + +static const uint8_t T0 = 15; // careful, also used as SPI MISO pin +static const uint8_t T1 = 14; // careful, also used as SPI MOSI pin +static const uint8_t T2 = 6; // careful, also used as SPI SCK pin +static const uint8_t T3 = 3; // careful, also used as I2C SCL pin +static const uint8_t T4 = 2; // careful, also used as I2C SDA pin + +/* 4D Systems ESP32-P4 round board specific definitions */ +// LCD +#define LCD_INTERFACE_MIPI + +#define LCD_BL_IO 22 +#define LCD_BL_ON_LEVEL 1 +#define LCD_BL_OFF_LEVEL !LCD_BL_ON_LEVEL + +#define LCD_RST_IO 23 +#define LCD_RST_ACTIVE_HIGH true + +// I2C for on-board components +#define I2C_SDA 7 +#define I2C_SCL 8 + +// Touch +#define CTP_RST 4 +#define CTP_INT 5 + +// Audio +#define AMP_CTRL 53 +#define I2S_DSDIN 9 +#define I2S_LRCK 10 +#define I2S_ASDOUT 11 +#define I2S_SCLK 12 +#define I2S_MCLK 13 + +// SDMMC +#define BOARD_HAS_SDMMC +#define BOARD_SDMMC_SLOT 0 +#define BOARD_SDMMC_POWER_CHANNEL 4 +#define BOARD_SDMMC_POWER_PIN 45 +#define BOARD_SDMMC_POWER_ON_LEVEL LOW + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32p4_core_board/pins_arduino.h b/variants/esp32p4_core_board/pins_arduino.h new file mode 100644 index 0000000..1834cc6 --- /dev/null +++ b/variants/esp32p4_core_board/pins_arduino.h @@ -0,0 +1,75 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BOOT_MODE 35 +// BOOT_MODE2 36 pullup + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 44 +// and change this setup for the chosen pin (for example 38) +#define PIN_RGB_LED 44 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 37; +static const uint8_t RX = 38; + +static const uint8_t SDA = 7; +static const uint8_t SCL = 8; + +// Use GPIOs 36 or lower on the P4 DevKit to avoid LDO power issues with high numbered GPIOs. +static const uint8_t SS = 30; +static const uint8_t MOSI = 33; +static const uint8_t MISO = 32; +static const uint8_t SCK = 31; + +static const uint8_t A0 = 16; +static const uint8_t A1 = 17; +static const uint8_t A2 = 18; +static const uint8_t A3 = 19; +static const uint8_t A4 = 20; +static const uint8_t A5 = 21; +static const uint8_t A6 = 22; +static const uint8_t A7 = 23; +static const uint8_t A8 = 49; +static const uint8_t A9 = 50; +static const uint8_t A10 = 51; +static const uint8_t A11 = 52; +static const uint8_t A12 = 53; +static const uint8_t A13 = 54; + +static const uint8_t T0 = 2; +static const uint8_t T1 = 3; +static const uint8_t T2 = 4; +static const uint8_t T3 = 5; +static const uint8_t T4 = 6; +static const uint8_t T5 = 7; +static const uint8_t T6 = 8; +static const uint8_t T7 = 9; +static const uint8_t T8 = 10; +static const uint8_t T9 = 11; +static const uint8_t T10 = 12; +static const uint8_t T11 = 13; +static const uint8_t T12 = 14; +static const uint8_t T13 = 15; + +//WIFI - ESP32C6 +#define BOARD_HAS_SDIO_ESP_HOSTED +#define BOARD_SDIO_ESP_HOSTED_RESET 54 // chip_pu +#define BOARD_SDIO_ESP_HOSTED_BOOT 53 // io 9 +#define BOARD_SDIO_ESP_HOSTED_CMD 52 // io 18 +#define BOARD_SDIO_ESP_HOSTED_CLK 51 // io 19 +#define BOARD_SDIO_ESP_HOSTED_D0 50 // io 20 +#define BOARD_SDIO_ESP_HOSTED_D1 49 // io 21 +#define BOARD_SDIO_ESP_HOSTED_D2 48 // io 22 +#define BOARD_SDIO_ESP_HOSTED_D3 47 // io 23 + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s2-devkit-lipo-usb/pins_arduino.h b/variants/esp32s2-devkit-lipo-usb/pins_arduino.h new file mode 100644 index 0000000..207fa8a --- /dev/null +++ b/variants/esp32s2-devkit-lipo-usb/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 18 +#define RGB_BUILTIN PIN_RGB_LED +#define RGB_BRIGHTNESS 64 + +static const uint8_t BUT_BUILTIN = 0; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +// external power sense - disabled by default - check the schematic +//static const uint8_t PWR_SENSE = 7; +// battery measurement - disabled by default - check the schematic +//static const uint8_t BAT_SENSE = 8; +// #define BAT_VOLT_PIN BAT_SENSE + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s2-devkit-lipo/pins_arduino.h b/variants/esp32s2-devkit-lipo/pins_arduino.h new file mode 100644 index 0000000..fed7bd6 --- /dev/null +++ b/variants/esp32s2-devkit-lipo/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 18 +#define RGB_BUILTIN PIN_RGB_LED +#define RGB_BRIGHTNESS 64 + +static const uint8_t BUT_BUILTIN = 0; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// define I2C pins +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +// define SPI pins +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +// external power sense - disabled by default - check the schematic +//static const uint8_t PWR_SENSE = 7; +// battery measurement - disabled by default - check the schematic +//static const uint8_t BAT_SENSE = 8; +// #define BAT_VOLT_PIN BAT_SENSE + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s2/pins_arduino.h b/variants/esp32s2/pins_arduino.h new file mode 100644 index 0000000..27391ef --- /dev/null +++ b/variants/esp32s2/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// GPIO pin for Saola-1 & DevKitM-1 = 18 +#define PIN_RGB_LED 18 +// GPIO pin for Kaluga = 45 +//#define PIN_RGB_LED 45 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s2thing_plus/pins_arduino.h b/variants/esp32s2thing_plus/pins_arduino.h new file mode 100644 index 0000000..a0520dc --- /dev/null +++ b/variants/esp32s2thing_plus/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x1B4F +#define USB_PID 0x0027 +#define USB_MANUFACTURER "SparkFun" +#define USB_PRODUCT "ESP32-S2 Thing Plus" +#define USB_SERIAL "" + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +#define TX1 34 +#define RX1 33 + +static const uint8_t SDA = 1; +static const uint8_t SCL = 2; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 14; +static const uint8_t A3 = 9; +static const uint8_t A4 = 7; +static const uint8_t A5 = 5; + +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s2usb/pins_arduino.h b/variants/esp32s2usb/pins_arduino.h new file mode 100644 index 0000000..4d31e12 --- /dev/null +++ b/variants/esp32s2usb/pins_arduino.h @@ -0,0 +1,72 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Default USB Settings +#define USB_VID 0x303A +#define USB_PID 0x0003 +#define USB_MANUFACTURER "Espressif Systems" +#define USB_PRODUCT "ESP32-S2-USB" +#define USB_SERIAL "0" +#define USB_WEBUSB_ENABLED false +#define USB_WEBUSB_URL "https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html" + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "ESP32-S2" //max 8 chars +#define USB_FW_MSC_PRODUCT_ID "Firmware MSC" //max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.23" //max 4 chars +#define USB_FW_MSC_VOLUME_NAME "S2-Firmware" //max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3-devkit-lipo/pins_arduino.h b/variants/esp32s3-devkit-lipo/pins_arduino.h new file mode 100644 index 0000000..7ff17f1 --- /dev/null +++ b/variants/esp32s3-devkit-lipo/pins_arduino.h @@ -0,0 +1,76 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 38; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUT_BUILTIN = 0; +#define BUILTIN_BUT BUT_BUILTIN // backward compatibility +#define BUT_BUILTIN BUT_BUILTIN // allow testing #ifdef BUT_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// available at pUEXT + +static const uint8_t TX1 = 17; +static const uint8_t RX1 = 18; + +static const uint8_t SDA = 48; +static const uint8_t SCL = 47; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; +// available at pUEXT - + +// external power sense +static const uint8_t PWR_SENSE = 5; +// battery measurement +static const uint8_t BAT_SENSE = 6; +#define BAT_VOLT_PIN BAT_SENSE + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3/pins_arduino.h b/variants/esp32s3/pins_arduino.h new file mode 100644 index 0000000..623d684 --- /dev/null +++ b/variants/esp32s3/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +#define PIN_RGB_LED 48 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3_powerfeather/pins_arduino.h b/variants/esp32s3_powerfeather/pins_arduino.h new file mode 100644 index 0000000..f5f3b20 --- /dev/null +++ b/variants/esp32s3_powerfeather/pins_arduino.h @@ -0,0 +1,55 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x81BB +#define USB_MANUFACTURER "PowerFeather" +#define USB_PRODUCT "ESP32-S3 PowerFeather" +#define USB_SERIAL "" + +static const uint8_t ALARM = 21; +static const uint8_t INT = 5; + +static const uint8_t LED = 46; +static const uint8_t BTN = 0; +static const uint8_t EN = 7; + +static const uint8_t TX = 44; +static const uint8_t RX = 42; +static const uint8_t TX0 = 43; + +static const uint8_t SS = -1; +static const uint8_t MISO = 41; +static const uint8_t MOSI = 40; +static const uint8_t SCK = 39; + +static const uint8_t SCL = 36; +static const uint8_t SDA = 35; + +#define WIRE1_PIN_DEFINED 1 +static const uint8_t SCL1 = 48; +static const uint8_t SDA1 = 47; + +static const uint8_t A0 = 10; +static const uint8_t A1 = 9; +static const uint8_t A2 = 8; +static const uint8_t A3 = 3; +static const uint8_t A4 = 2; +static const uint8_t A5 = 1; + +static const uint8_t D5 = 15; +static const uint8_t D6 = 16; +static const uint8_t D7 = 37; +static const uint8_t D8 = 6; +static const uint8_t D9 = 17; +static const uint8_t D10 = 18; +static const uint8_t D11 = 45; +static const uint8_t D12 = 12; +static const uint8_t D13 = 11; + +#define LED_BUILTIN 46 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3box/pins_arduino.h b/variants/esp32s3box/pins_arduino.h new file mode 100644 index 0000000..8fb0a8c --- /dev/null +++ b/variants/esp32s3box/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 40; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; + +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +// Wire1 for ES7210 MIC ADC, ES8311 I2S DAC, ICM-42607-P IMU and TT21100 Touch Panel +#define I2C_SDA 8 +#define I2C_SCL 18 + +#define ES7210_ADDR 0x40 //MIC ADC +#define ES8311_ADDR 0x18 //I2S DAC +#define ICM42607P_ADDR 0x68 //IMU +#define TT21100_ADDR 0x24 //Touch Panel + +#define TFT_DC 4 +#define TFT_CS 5 +#define TFT_MOSI 6 +#define TFT_CLK 7 +#define TFT_MISO 0 +#define TFT_BL 45 +#define TFT_RST 48 + +#define I2S_LRCK 47 +#define I2S_MCLK 2 +#define I2S_SCLK 17 +#define I2S_SDIN 16 +#define I2S_DOUT 15 + +#define PA_PIN 46 //Audio Amp Power +#define MUTE_PIN 1 //MUTE Button +#define TS_IRQ 3 //Touch Screen IRQ + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3camlcd/pins_arduino.h b/variants/esp32s3camlcd/pins_arduino.h new file mode 100644 index 0000000..ca734b9 --- /dev/null +++ b/variants/esp32s3camlcd/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 17; +static const uint8_t SCL = 18; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// Wire1 for Cam and TS +#define I2C_SDA 17 +#define I2C_SCL 18 + +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 40 +#define SIOD_GPIO_NUM 17 +#define SIOC_GPIO_NUM 18 +#define Y9_GPIO_NUM 39 +#define Y8_GPIO_NUM 41 +#define Y7_GPIO_NUM 42 +#define Y6_GPIO_NUM 12 +#define Y5_GPIO_NUM 3 +#define Y4_GPIO_NUM 14 +#define Y3_GPIO_NUM 47 +#define Y2_GPIO_NUM 13 +#define VSYNC_GPIO_NUM 21 +#define HREF_GPIO_NUM 38 +#define PCLK_GPIO_NUM 11 + +#define TFT_FREQ 40000000 +#define TFT_BITS 8 +#define TFT_WIDTH 480 +#define TFT_HEIGHT 320 +#define TFT_WR 4 +#define TFT_DC 2 +#define TFT_D0 45 +#define TFT_D1 16 +#define TFT_D2 15 +#define TFT_D3 10 +#define TFT_D4 8 +#define TFT_D5 7 +#define TFT_D6 6 +#define TFT_D7 5 + +#define SDMMC_CMD 20 +#define SDMMC_CLK 9 +#define SDMMC_DATA 19 + +#define MIC_CLK 0 +#define MIC_DATA 1 + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3usbotg/pins_arduino.h b/variants/esp32s3usbotg/pins_arduino.h new file mode 100644 index 0000000..13b9d24 --- /dev/null +++ b/variants/esp32s3usbotg/pins_arduino.h @@ -0,0 +1,97 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 45; +static const uint8_t SCL = 46; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; + +static const uint8_t T3 = 3; + +// SDCARD Slot +#define BOARD_HAS_SDMMC +#define SDMMC_D2 33 // SDMMC Data2 +#define SDMMC_D3 34 // SDMMC Data3 / SPI CS +#define SDMMC_CMD 35 // SDMMC CMD / SPI MOSI +#define SDMMC_CLK 36 // SDMMC CLK / SPI SCK +#define SDMMC_D0 37 // SDMMC Data0 / SPI MISO +#define SDMMC_D1 38 // SDMMC Data1 +#define BOARD_MAX_SDMMC_FREQ SDMMC_FREQ_DEFAULT + +// 240x240 LCD +#define BOARD_HAS_SPI_LCD +#define LCD_MODEL ST7789 +#define LCD_WIDTH 240 +#define LCD_HEIGHT 240 // *RAM height is actually 320! +#define LCD_MISO -1 // LCD Does not use MISO. +#define LCD_DC 4 // Used to switch data and command status. +#define LCD_CS 5 // used to enable LCD, low level to enable. +#define LCD_CLK 6 // LCD SPI Clock. +#define LCD_MOSI 7 // LCD SPI MOSI. +#define LCD_RST 8 // used to reset LCD, low level to reset. +#define LCD_BL 9 // LCD backlight control. + +// Buttons +#define BUTTON_OK 0 // OK button, low level when pressed. +#define BUTTON_UP 10 // UP button, low level when pressed. +#define BUTTON_DOWN 11 // Down button, low level when pressed. +#define BUTTON_MENU 14 // Menu button, low level when pressed. + +// LEDs +#define LED_GREEN 15 // the light is lit when set high level. +#define LED_YELLOW 16 // the light is lit when set high level. + +// Board Controls +#define DEV_VBUS_EN 12 // High level to enable DEV_VBUS power supply. +#define BOOST_EN 13 // High level to enable Battery Boost circuit. +#define LIMIT_EN 17 // Enable USB_HOST current limiting IC, high level enable. +#define USB_HOST_EN \ + 18 // Used to switch the USB interface. When high level, the USB_HOST interface is enabled. When low level, the USB_DEV interface is enabled. + +// Board Sensors +#define OVER_CURRENT 21 // Current overrun signal, high level means overrun. +#define HOST_VOLTS 1 // USB_DEV voltage monitoring, ADC1 channel 0. actual_v = value_v * 3.7 +#define BAT_VOLTS 2 // Battery voltage monitoring, ADC1 channel 1. actual_v = value_v * 2 +#define BAT_VOLT_PIN BAT_VOLTS + +// USB Port +#define USB_DN 19 // USB D- +#define USB_DP 20 // USB D+ + +// Bottom header +#define MTCK 39 +#define MTDO 40 +#define MTDI 41 +#define MTMS 42 +// #define FREE_6 3 // Idle, can be customized. +// #define FREE_4 26 // Idle, can be customized. +// #define FREE_1 45 // Idle, can be customized. +// #define FREE_2 46 // Idle, can be customized. +// #define FREE_5 47 // Idle, can be customized. +// #define FREE_3 48 // Idle, can be customized. + +typedef enum { + USB_HOST_POWER_OFF, + USB_HOST_POWER_VBUS, + USB_HOST_POWER_BAT +} UsbHostPower_t; +void usbHostPower(UsbHostPower_t mode); +void usbHostEnable(bool enable); + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32s3usbotg/variant.cpp b/variants/esp32s3usbotg/variant.cpp new file mode 100644 index 0000000..a8de800 --- /dev/null +++ b/variants/esp32s3usbotg/variant.cpp @@ -0,0 +1,52 @@ +#include "Arduino.h" + +void usbHostPower(UsbHostPower_t mode) { + static UsbHostPower_t m = USB_HOST_POWER_OFF; + if (m == mode) { + return; + } + if (mode == USB_HOST_POWER_OFF) { + digitalWrite(LIMIT_EN, LOW); + if (m == USB_HOST_POWER_VBUS) { + digitalWrite(DEV_VBUS_EN, LOW); + } else if (m == USB_HOST_POWER_BAT) { + digitalWrite(BOOST_EN, LOW); + } + } else if (mode == USB_HOST_POWER_VBUS) { + if (m == USB_HOST_POWER_BAT) { + digitalWrite(BOOST_EN, LOW); + } + digitalWrite(DEV_VBUS_EN, HIGH); + } else if (mode == USB_HOST_POWER_BAT) { + if (m == USB_HOST_POWER_VBUS) { + digitalWrite(DEV_VBUS_EN, LOW); + } + digitalWrite(BOOST_EN, HIGH); + } + if (mode != USB_HOST_POWER_OFF) { + digitalWrite(LIMIT_EN, HIGH); + } + m = mode; +} + +void usbHostEnable(bool enable) { + digitalWrite(USB_HOST_EN, enable); +} + +extern "C" void initVariant(void) { + // Route USB to Device Side + pinMode(BOOST_EN, OUTPUT); + digitalWrite(BOOST_EN, LOW); + pinMode(LIMIT_EN, OUTPUT); + digitalWrite(LIMIT_EN, LOW); + pinMode(DEV_VBUS_EN, OUTPUT); + digitalWrite(DEV_VBUS_EN, LOW); + pinMode(USB_HOST_EN, OUTPUT); + digitalWrite(USB_HOST_EN, LOW); + + // Turn Off LCD + pinMode(LCD_RST, OUTPUT); + digitalWrite(LCD_RST, LOW); + pinMode(LCD_BL, OUTPUT); + digitalWrite(LCD_BL, LOW); +} diff --git a/variants/esp32thing/pins_arduino.h b/variants/esp32thing/pins_arduino.h new file mode 100644 index 0000000..00abcdf --- /dev/null +++ b/variants/esp32thing/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define F_XTAL_MHZ 26 //SparkFun ESP32 Thing has 26MHz Crystal + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32thing_plus/pins_arduino.h b/variants/esp32thing_plus/pins_arduino.h new file mode 100644 index 0000000..0803c67 --- /dev/null +++ b/variants/esp32thing_plus/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 17; +static const uint8_t RX = 16; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 33; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +// mapping to match other feathers and also in order +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 34; +static const uint8_t A3 = 39; +static const uint8_t A4 = 36; +static const uint8_t A5 = 4; +static const uint8_t A6 = 14; +static const uint8_t A7 = 32; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32thing_plus_c/pins_arduino.h b/variants/esp32thing_plus_c/pins_arduino.h new file mode 100644 index 0000000..ca7b6c6 --- /dev/null +++ b/variants/esp32thing_plus_c/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + 2; +#define RGB_BUILTIN RGB_BUILTIN // necessary to make digitalWrite/digitalMode find it +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 17; +static const uint8_t RX = 16; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 34; +static const uint8_t A3 = 39; +static const uint8_t A4 = 36; +static const uint8_t A5 = 35; +static const uint8_t A6 = 14; +static const uint8_t A7 = 32; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp32vn-iot-uno/pins_arduino.h b/variants/esp32vn-iot-uno/pins_arduino.h new file mode 100644 index 0000000..167e649 --- /dev/null +++ b/variants/esp32vn-iot-uno/pins_arduino.h @@ -0,0 +1,44 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/esp_c3_m1_i_kit/pins_arduino.h b/variants/esp_c3_m1_i_kit/pins_arduino.h new file mode 100644 index 0000000..01ee56d --- /dev/null +++ b/variants/esp_c3_m1_i_kit/pins_arduino.h @@ -0,0 +1,43 @@ +/* + For more information about this board: + https://docs.ai-thinker.com/_media/esp32/docs/nodemcu-esp-c3-m1-i-kit_v1.2.0_specification.pdf +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// User LEDs are also connected to USB D- and D+ +static const uint8_t LED_WARM = 18; +static const uint8_t LED_COLD = 19; + +// RGB LED +static const uint8_t LED_RED = 3; +static const uint8_t LED_GREEN = 4; +static const uint8_t LED_BLUE = 5; + +static const uint8_t LED_BUILTIN = LED_WARM; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// Standard ESP32-C3 GPIOs +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/espea32/pins_arduino.h b/variants/espea32/pins_arduino.h new file mode 100644 index 0000000..bc0d7a1 --- /dev/null +++ b/variants/espea32/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/espectro32/pins_arduino.h b/variants/espectro32/pins_arduino.h new file mode 100644 index 0000000..7f6dbb1 --- /dev/null +++ b/variants/espectro32/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#ifndef ESPECTRO32_VERSION +#define ESPECTRO32_VERSION 1 +#endif + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SD_SS = 33; +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/espino32/pins_arduino.h b/variants/espino32/pins_arduino.h new file mode 100644 index 0000000..840fd86 --- /dev/null +++ b/variants/espino32/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 16; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUILTIN_KEY = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/feather_esp32/pins_arduino.h b/variants/feather_esp32/pins_arduino.h new file mode 100644 index 0000000..4078b78 --- /dev/null +++ b/variants/feather_esp32/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 17; +static const uint8_t RX = 16; + +#define TX1 TX +#define RX1 RX + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 33; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +// mapping to match other feathers and also in order +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 34; +static const uint8_t A3 = 39; +static const uint8_t A4 = 36; +static const uint8_t A5 = 4; +static const uint8_t A6 = 14; +static const uint8_t A7 = 32; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +// vbat measure +static const uint8_t BATT_MONITOR = 35; +#define BAT_VOLT_PIN BATT_MONITOR +static const uint8_t A13 = 35; +//static const uint8_t Ax = 0; // not used/available +//static const uint8_t Ax = 2; // not used/available + +static const uint8_t T0 = 4; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/fed4/pins_arduino.h b/variants/fed4/pins_arduino.h new file mode 100644 index 0000000..46705a3 --- /dev/null +++ b/variants/fed4/pins_arduino.h @@ -0,0 +1,80 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x82E5 +#define USB_MANUFACTURER "Smart Bee Designs LLC" +#define USB_PRODUCT "FED4" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; +static const uint8_t SDA2 = 20; +static const uint8_t SCL2 = 19; + +static const uint8_t SS = 47; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; +static const uint8_t SDCS = 10; // sd cs pin +static const uint8_t DSCS = 14; //display cs pin + +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D8 = 8; +static const uint8_t D13 = 13; +static const uint8_t D9 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; + +static const uint8_t BOOT_BTN = 0; +static const uint8_t VBAT_VOLTAGE = 7; +#define BAT_VOLT_PIN VBAT_VOLTAGE +static const uint8_t LDO2 = 47; +static const uint8_t STATUS_RGB = 35; +static const uint8_t RGB_STRIP = 36; +static const uint8_t INTERRUPT_PIN = 18; +static const uint8_t USER_BTN_1 = 14; +static const uint8_t USER_BTN_2 = 39; +static const uint8_t USER_BTN_3 = 40; +static const uint8_t AMP_DIN = 39; +static const uint8_t AMP_SD = 42; +static const uint8_t AMP_BCLK = 45; +static const uint8_t AMP_LRCLK = 48; +static const uint8_t MSBY = 15; +static const uint8_t TRRS_1 = 4; +static const uint8_t TRRS_2 = 2; +static const uint8_t TRRS_3 = 3; + +#define PIN_RGB_LED STATUS_RGB +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#endif /* Pins_Arduino_h */ diff --git a/variants/firebeetle32/pins_arduino.h b/variants/firebeetle32/pins_arduino.h new file mode 100644 index 0000000..60a35d6 --- /dev/null +++ b/variants/firebeetle32/pins_arduino.h @@ -0,0 +1,65 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +typedef unsigned char uint8_t; + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 25; +static const uint8_t D3 = 26; +static const uint8_t D4 = 27; +static const uint8_t D5 = 9; +static const uint8_t D6 = 10; +static const uint8_t D7 = 13; +static const uint8_t D8 = 5; +static const uint8_t D9 = 2; +static const uint8_t D10 = 0; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 34; +static const uint8_t A3 = 35; +static const uint8_t A4 = 15; +static const uint8_t A5 = 35; +static const uint8_t A6 = 4; +static const uint8_t A7 = 0; +static const uint8_t A8 = 2; +static const uint8_t A9 = 13; +static const uint8_t A10 = 12; +static const uint8_t A11 = 14; +static const uint8_t A12 = 27; +static const uint8_t A13 = 25; +static const uint8_t A14 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/fm-devkit/pins_arduino.h b/variants/fm-devkit/pins_arduino.h new file mode 100644 index 0000000..63a6d86 --- /dev/null +++ b/variants/fm-devkit/pins_arduino.h @@ -0,0 +1,47 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +// IO +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +static const uint8_t SW1 = 4; +static const uint8_t SW2 = 18; +static const uint8_t SW3 = 19; +static const uint8_t SW4 = 21; + +//I2S DAC +static const uint8_t I2S_MCLK = 2; // CLOCK must be an integer multiplier of SCLK +static const uint8_t I2S_LRCLK = 25; // LRCLK +static const uint8_t I2S_SCLK = 26; // SCLK - Fs (44100 Hz) +static const uint8_t I2S_DOUT = 22; // DATA + +//GPIO +static const uint8_t D0 = 34; // GPI - Input Only +static const uint8_t D1 = 35; // GPI - Input Only +static const uint8_t D2 = 32; // GPO - Output Only +static const uint8_t D3 = 33; // GPO - Output Only +static const uint8_t D4 = 27; +static const uint8_t D5 = 14; +static const uint8_t D6 = 12; +static const uint8_t D7 = 13; +static const uint8_t D8 = 15; +static const uint8_t D9 = 23; +static const uint8_t D10 = 0; + +// I2C BUS, 2k2 hardware pull-ups +static const uint8_t SDA = 16; +static const uint8_t SCL = 17; + +// SPI - unused but you can create your own definition in your sketch +static const int8_t SCK = -1; +static const int8_t MISO = -1; +static const int8_t MOSI = -1; +static const int8_t SS = -1; + +#endif /* Pins_Arduino_h */ diff --git a/variants/fobe_quill_esp32s3_mesh/bootloader-tinyuf2.bin b/variants/fobe_quill_esp32s3_mesh/bootloader-tinyuf2.bin new file mode 100644 index 0000000..b832659 Binary files /dev/null and b/variants/fobe_quill_esp32s3_mesh/bootloader-tinyuf2.bin differ diff --git a/variants/fobe_quill_esp32s3_mesh/pins_arduino.h b/variants/fobe_quill_esp32s3_mesh/pins_arduino.h new file mode 100644 index 0000000..97e587a --- /dev/null +++ b/variants/fobe_quill_esp32s3_mesh/pins_arduino.h @@ -0,0 +1,108 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x82F4 +#define USB_MANUFACTURER "FoBE Studio" +#define USB_PRODUCT "FoBE Quill ESP32S3 Mesh" +#define USB_SERIAL "" // Empty string for MAC address + +// User LED +#define LED_BUILTIN 11 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +/* + * Battery + */ +#define PIN_VBAT (10) +#define BAT_VOLT_PIN PIN_VBAT + +/* + * Buttons + */ +#define PIN_BUTTON1 (0) + +/* + * Serial interfaces + */ +static const uint8_t TX = 9; +static const uint8_t RX = 8; + +/* + * Wire Interfaces + */ +static const uint8_t SDA = 14; +static const uint8_t SCL = 13; + +/* + * SPI interfaces + */ +static const uint8_t SS = 45; +static const uint8_t MOSI = 39; +static const uint8_t SCK = 40; +static const uint8_t MISO = 41; + +/* + * Screen + */ +#define PIN_OLED_SDA (14) +#define PIN_OLED_SCL (13) +#define PIN_OLED_EN (12) + +/* + * LoRa + */ +#define PIN_SX126X_NSS (45) +#define PIN_SX126X_DIO1 (42) +#define PIN_SX126X_BUSY (43) +#define PIN_SX126X_RESET (44) +#define PIN_SX126X_TXEN (-1) +#define PIN_SX126X_RXEN (46) +#define SX126X_DIO2_AS_RF_SWITCH +#define SX126X_DIO3_TCXO_VOLTAGE 1.8 + +/* + * MFP + */ +#define PIN_MFP1 (38) +#define PIN_MFP2 (37) +#define PIN_MFP3 (36) +#define PIN_MFP4 (35) + +/* + * Power + */ +#define PIN_PERI_EN (1) + +/* + * PINs + */ +static const uint8_t A0 = 2; +static const uint8_t A1 = 3; +static const uint8_t A2 = 4; +static const uint8_t A3 = 5; +static const uint8_t A4 = 6; +static const uint8_t A5 = 7; +static const uint8_t D0 = 8; +static const uint8_t D1 = 9; +static const uint8_t D2 = 11; +static const uint8_t D3 = 38; +static const uint8_t D4 = 37; +static const uint8_t D5 = 36; +static const uint8_t D6 = 35; +static const uint8_t D7 = 34; +static const uint8_t D8 = 33; +static const uint8_t D9 = 47; +static const uint8_t D10 = 48; +static const uint8_t D11 = 21; +static const uint8_t D12 = 18; +static const uint8_t D13 = 17; +static const uint8_t MTCK = 39; +static const uint8_t MTDO = 40; +static const uint8_t MTDI = 41; +static const uint8_t MTMS = 42; + +#endif /* Pins_Arduino_h */ diff --git a/variants/fobe_quill_esp32s3_mesh/tinyuf2.bin b/variants/fobe_quill_esp32s3_mesh/tinyuf2.bin new file mode 100644 index 0000000..b854b19 Binary files /dev/null and b/variants/fobe_quill_esp32s3_mesh/tinyuf2.bin differ diff --git a/variants/fobe_quill_esp32s3_mesh/variant.cpp b/variants/fobe_quill_esp32s3_mesh/variant.cpp new file mode 100644 index 0000000..32ef46f --- /dev/null +++ b/variants/fobe_quill_esp32s3_mesh/variant.cpp @@ -0,0 +1,15 @@ +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +void initVariant(void) { + // Turn on the peripheral power + pinMode(PIN_PERI_EN, OUTPUT); + digitalWrite(PIN_PERI_EN, HIGH); + + // Turn on the OLED power + pinMode(PIN_OLED_EN, OUTPUT); + digitalWrite(PIN_OLED_EN, LOW); +} +} diff --git a/variants/franzininho_wifi_esp32s2/pins_arduino.h b/variants/franzininho_wifi_esp32s2/pins_arduino.h new file mode 100644 index 0000000..b75fcc7 --- /dev/null +++ b/variants/franzininho_wifi_esp32s2/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80A9 +#define USB_MANUFACTURER "Franzininho" +#define USB_PRODUCT "Franzininho WIFI" +#define USB_SERIAL "0" +#define USB_WEBUSB_ENABLED false + +static const uint8_t PIN_RGB_LED = 18; +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT); +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h b/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h new file mode 100644 index 0000000..db213cb --- /dev/null +++ b/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h @@ -0,0 +1,80 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80A9 +#define USB_MANUFACTURER "Franzininho" +#define USB_PRODUCT "Franzininho WIFI MSC" +#define USB_SERIAL "0" +#define USB_WEBUSB_ENABLED false + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "ESP32-S2" //max 8 chars +#define USB_FW_MSC_PRODUCT_ID "Firmware MSC" //max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.23" //max 4 chars +#define USB_FW_MSC_VOLUME_NAME "S2-Firmware" //max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +static const uint8_t PIN_RGB_LED = 18; +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT); +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/fri3d_2024_esp32s3/pins_arduino.h b/variants/fri3d_2024_esp32s3/pins_arduino.h new file mode 100644 index 0000000..7470daf --- /dev/null +++ b/variants/fri3d_2024_esp32s3/pins_arduino.h @@ -0,0 +1,128 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 9; +static const uint8_t SCL = 18; + +static const uint8_t SS = 14; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 8; +static const uint8_t SCK = 7; + +#define X_FRI3D_BADGE_2024 // General Define for use in sketches or lib files +#define X_WS2812_NUM_LEDS 5 // Number of RBG LEDs + +#define PIN_I2C_SDA SDA +#define PIN_I2C_SCL SCL +#define PIN_WS2812 12 +#define X_WS2812_NUM_LEDS 5 + +#define PIN_LED 21 +#define PIN_IR_RECEIVER 11 +#define PIN_BLASTER 10 +#define PIN_BUZZER 46 +#define PIN_BATTERY 13 +#define BAT_VOLT_PIN PIN_BATTERY + +#define PIN_SDCARD_CS SS + +#define PIN_JOY_X 1 +#define PIN_JOY_Y 3 + +#define PIN_A 39 +#define PIN_B 40 +#define PIN_X 38 +#define PIN_Y 41 +#define PIN_MENU 45 +#define PIN_START 0 + +#define PIN_AUX 42 // Fri3d Badge 2024 Aux Pwr + +#define CHANNEL_BUZZER 0 + +// Fri3d Badge 2024 Accelero Gyro +#define X_ACCELERO_GYRO 21 + +// I2S microphone on communicator addon +#define I2S_MIC_CHANNEL I2S_CHANNEL_FMT_ONLY_LEFT +#define I2S_MIC_SERIAL_CLOCK 17 //serial clock SCLK: pin SCK +#define I2S_MIC_LEFT_RIGHT_CLOCK 47 //left/right clock LRCK: pin WS +#define I2S_MIC_SERIAL_DATA 15 //serial data DIN: pin SD + +// Fri3d Badge 2024 LCD +// For using display with TFT_eSPI library +#define USER_SETUP_LOADED +#define SPI_FREQUENCY 80000000 +#define ST7789_DRIVER +#define USE_HSPI_PORT + +#define TFT_RGB_ORDER TFT_BGR //# swap red and blue byte order +#define TFT_INVERSION_OFF +#define TFT_WIDTH 296 //;setting these will init the eSPI lib with correct dimensions +#define TFT_HEIGHT 240 //;setting these will init the eSPI lib with correct dimensions +#define TFT_MISO MISO +#define TFT_MOSI MOSI +#define TFT_SCLK SCK +#define TFT_CS 5 +#define TFT_DC 4 +#define TFT_RST 48 +#define LOAD_GLCD 1 +#define LOAD_FONT2 +#define LOAD_FONT4 +#define LOAD_FONT6 +#define LOAD_FONT7 +#define LOAD_FONT8 +#define LOAD_GFXFF +#define SMOOTH_FONT +#define SPI_FREQUENCY 80000000 + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/frog32/pins_arduino.h b/variants/frog32/pins_arduino.h new file mode 100644 index 0000000..3663de7 --- /dev/null +++ b/variants/frog32/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/gpy/pins_arduino.h b/variants/gpy/pins_arduino.h new file mode 100644 index 0000000..93d3e5b --- /dev/null +++ b/variants/gpy/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// Sequans Monarch LTE Cat M1/NB1 modem +// NOTE: The Pycom pinout as well as spec sheet block diagram / pin details +// incorrectly list the LTE pins. The correct pins are defined in the source and CSV +// at https://github.com/pycom/pycom-micropython-sigfox/tree/master/esp32/boards/GPY. +#define LTE_CTS 18 // GPIO18 - Sequans modem CTS +#define LTE_RTS 19 // GPIO19 - Sequans modem RTS (pull low to communicate) +#define LTE_RX 23 // GPIO23 - Sequans modem RX +#define LTE_TX 5 // GPIO5 - Sequans modem TX +#define LTE_WAKE 27 // GPIO27 - Sequans modem wake-up interrupt +#define LTE_BAUD 921600 + +// RGB LED +#define PIN_RGB_LED 0 // ->2812 RGB !!! +static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define ANT_SELECT 21 // GPIO21 - WiFi external / internal antenna switch + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SS = 17; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 37; +static const uint8_t SCK = 13; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/healthypi4/pins_arduino.h b/variants/healthypi4/pins_arduino.h new file mode 100644 index 0000000..2b8707f --- /dev/null +++ b/variants/healthypi4/pins_arduino.h @@ -0,0 +1,65 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 17; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADS1292_DRDY_PIN = 26; +static const uint8_t ADS1292_CS_PIN = 13; +static const uint8_t ADS1292_START_PIN = 14; +static const uint8_t ADS1292_PWDN_PIN = 27; +static const uint8_t AFE4490_CS_PIN = 21; +static const uint8_t AFE4490_DRDY_PIN = 39; +static const uint8_t AFE4490_PWDN_PIN = 4; + +static const uint8_t PUSH_BUTTON = 17; +static const uint8_t SLIDE_SWITCH = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_capsule_sensor_v3/partitions.csv b/variants/heltec_capsule_sensor_v3/partitions.csv new file mode 100644 index 0000000..b363a41 --- /dev/null +++ b/variants/heltec_capsule_sensor_v3/partitions.csv @@ -0,0 +1,10 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x009000, 0x005000, +otadata, data, ota, 0x00e000, 0x002000, +app, app, ota_0, 0x010000, 0x250000, +flashApp, app, ota_1, 0x260000, 0x0A0000, +spiffs, data, spiffs, 0x300000, 0x100000, +factory, app, factory, 0x400000, 0x100000, +secondApp,app, ota_2, 0x500000, 0x2D0000, +key_data, 0x40, 0x00, 0x7D0000, 0x020000, +coredump, data, coredump,0x7F0000,0x10000, diff --git a/variants/heltec_capsule_sensor_v3/pins_arduino.h b/variants/heltec_capsule_sensor_v3/pins_arduino.h new file mode 100644 index 0000000..7dd673f --- /dev/null +++ b/variants/heltec_capsule_sensor_v3/pins_arduino.h @@ -0,0 +1,86 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define HELTEC_CAPSULE_SENSOR_V3 true + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 42; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 21; +static const uint8_t LED0 = 33; +static const uint8_t LED1 = 34; +static const uint8_t USER_BUTTON = 18; + +static const uint8_t GPS_RX_PIN = 5; +static const uint8_t GPS_TX_PIN = 4; +static const uint8_t GPS_RESET_PIN = 3; +static const uint8_t GPS_PPS_PIN = 1; + +static const uint8_t ADC_BATTERY_PIN = 7; +#define BAT_VOLT_PIN ADC_BATTERY_PIN +static const uint8_t ADC_BATTERY_CTRL_PIN = 36; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_ht_de01/pins_arduino.h b/variants/heltec_ht_de01/pins_arduino.h new file mode 100644 index 0000000..5969274 --- /dev/null +++ b/variants/heltec_ht_de01/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define HT_DE01 true + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 45; +static const uint8_t LED = 18; +static const uint8_t RST_EINK = 6; +static const uint8_t BUSY_EINK = 7; +static const uint8_t CLK_EINK = 3; +static const uint8_t CS_EINK = 5; +static const uint8_t DC_EINK = 4; +static const uint8_t SDI_EINK = 2; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_vision_master_e290/pins_arduino.h b/variants/heltec_vision_master_e290/pins_arduino.h new file mode 100644 index 0000000..7940cdd --- /dev/null +++ b/variants/heltec_vision_master_e290/pins_arduino.h @@ -0,0 +1,72 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Vision_Master_E290 true +#define DISPLAY_HEIGHT 128 +#define DISPLAY_WIDTH 296 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 39; +static const uint8_t SCL = 38; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 18; +static const uint8_t Eink_SDI = 1; +static const uint8_t Eink_CLK = 2; +static const uint8_t Eink_CS = 3; +static const uint8_t Eink_DC = 4; +static const uint8_t Eink_RST = 5; +static const uint8_t Eink_BUSY = 6; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_vision_master_e_213/pins_arduino.h b/variants/heltec_vision_master_e_213/pins_arduino.h new file mode 100644 index 0000000..003528f --- /dev/null +++ b/variants/heltec_vision_master_e_213/pins_arduino.h @@ -0,0 +1,72 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Vision_Master_E213 true +#define DISPLAY_HEIGHT 122 +#define DISPLAY_WIDTH 250 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 39; +static const uint8_t SCL = 38; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 18; +static const uint8_t Eink_BUSY = 1; +static const uint8_t Eink_DC = 2; +static const uint8_t Eink_RST = 3; +static const uint8_t Eink_CLK = 4; +static const uint8_t Eink_CS = 5; +static const uint8_t Eink_SDI = 6; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_vision_master_t190/pins_arduino.h b/variants/heltec_vision_master_t190/pins_arduino.h new file mode 100644 index 0000000..6c5fbf9 --- /dev/null +++ b/variants/heltec_vision_master_t190/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Vision_Master_T190 true +#define DISPLAY_HEIGHT 170 +#define DISPLAY_WIDTH 320 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 2; +static const uint8_t SCL = 1; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 5; +static const uint8_t TFT_SCL = 38; +static const uint8_t TFT_CS = 39; +static const uint8_t TFT_RST = 40; +static const uint8_t TFT_RS = 47; +static const uint8_t TFT_SDA = 48; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wifi_kit_32/pins_arduino.h b/variants/heltec_wifi_kit_32/pins_arduino.h new file mode 100644 index 0000000..0bac8fa --- /dev/null +++ b/variants/heltec_wifi_kit_32/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIFI_Kit_32 true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +#define F_XTAL_MHZ 26 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_OLED = 16; +static const uint8_t SCL_OLED = 15; +static const uint8_t SDA_OLED = 4; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wifi_kit_32_V3/pins_arduino.h b/variants/heltec_wifi_kit_32_V3/pins_arduino.h new file mode 100644 index 0000000..c8f42a0 --- /dev/null +++ b/variants/heltec_wifi_kit_32_V3/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIFI_Kit_32_V3 true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 42; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 36; +static const uint8_t LED = 35; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wifi_lora_32/pins_arduino.h b/variants/heltec_wifi_lora_32/pins_arduino.h new file mode 100644 index 0000000..d4e78df --- /dev/null +++ b/variants/heltec_wifi_lora_32/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIFI_LoRa_32 true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +#define F_XTAL_MHZ 26 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_OLED = 16; +static const uint8_t SCL_OLED = 15; +static const uint8_t SDA_OLED = 4; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 33; +static const uint8_t DIO2 = 32; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wifi_lora_32_V2/pins_arduino.h b/variants/heltec_wifi_lora_32_V2/pins_arduino.h new file mode 100644 index 0000000..7ddca80 --- /dev/null +++ b/variants/heltec_wifi_lora_32_V2/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIFI_LoRa_32_V2 true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_OLED = 16; +static const uint8_t SCL_OLED = 15; +static const uint8_t SDA_OLED = 4; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 35; +static const uint8_t DIO2 = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wifi_lora_32_V3/pins_arduino.h b/variants/heltec_wifi_lora_32_V3/pins_arduino.h new file mode 100644 index 0000000..031bc0e --- /dev/null +++ b/variants/heltec_wifi_lora_32_V3/pins_arduino.h @@ -0,0 +1,74 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIFI_LoRa_32_V3 true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 42; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 36; +static const uint8_t LED = 35; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_bridge/pins_arduino.h b/variants/heltec_wireless_bridge/pins_arduino.h new file mode 100644 index 0000000..e5cbf32 --- /dev/null +++ b/variants/heltec_wireless_bridge/pins_arduino.h @@ -0,0 +1,31 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIRELESS_BRIDGE true + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t BLE_LED = 25; +static const uint8_t WIFI_LED = 23; +static const uint8_t LoRa_LED = 22; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 35; +static const uint8_t DIO2 = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_mini_shell/pins_arduino.h b/variants/heltec_wireless_mini_shell/pins_arduino.h new file mode 100644 index 0000000..05675ee --- /dev/null +++ b/variants/heltec_wireless_mini_shell/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define WIRELESS_MINI_SHELL true + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_paper/pins_arduino.h b/variants/heltec_wireless_paper/pins_arduino.h new file mode 100644 index 0000000..727148b --- /dev/null +++ b/variants/heltec_wireless_paper/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define WIRELESS_PAPER true +#define DISPLAY_HEIGHT 64 +#define DISPLAY_WIDTH 128 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 45; +static const uint8_t LED = 18; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_shell_v3/pins_arduino.h b/variants/heltec_wireless_shell_v3/pins_arduino.h new file mode 100644 index 0000000..72eccd0 --- /dev/null +++ b/variants/heltec_wireless_shell_v3/pins_arduino.h @@ -0,0 +1,77 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +//#include "soc/soc_caps.h" + +#define HELTEC_WIRELESS_SHELL_V3 true +#define DISPLAY_HEIGHT 0 +#define DISPLAY_WIDTH 0 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//static const uint8_t SDA = 41; +//static const uint8_t SCL = 42; +static const uint8_t SDA = 2; +static const uint8_t SCL = 3; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 36; +static const uint8_t LED = 35; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_stick/pins_arduino.h b/variants/heltec_wireless_stick/pins_arduino.h new file mode 100644 index 0000000..3bebf07 --- /dev/null +++ b/variants/heltec_wireless_stick/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Wireless_Stick true +#define DISPLAY_HEIGHT 32 +#define DISPLAY_WIDTH 64 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_OLED = 16; +static const uint8_t SCL_OLED = 15; +static const uint8_t SDA_OLED = 4; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 35; +static const uint8_t DIO2 = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_stick_V1/pins_arduino.h b/variants/heltec_wireless_stick_V1/pins_arduino.h new file mode 100644 index 0000000..5f9f85f --- /dev/null +++ b/variants/heltec_wireless_stick_V1/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Wireless_Stick true +#define DISPLAY_HEIGHT 32 +#define DISPLAY_WIDTH 64 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_OLED = 16; +static const uint8_t SCL_OLED = 15; +static const uint8_t SDA_OLED = 4; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 33; +static const uint8_t DIO2 = 32; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_stick_lite/pins_arduino.h b/variants/heltec_wireless_stick_lite/pins_arduino.h new file mode 100644 index 0000000..f5b4a5f --- /dev/null +++ b/variants/heltec_wireless_stick_lite/pins_arduino.h @@ -0,0 +1,65 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Wireless_Stick_Lite true +#define DISPLAY_HEIGHT 0 +#define DISPLAY_WIDTH 0 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t Vext = 21; +static const uint8_t LED = 25; +static const uint8_t RST_LoRa = 14; +static const uint8_t DIO0 = 26; +static const uint8_t DIO1 = 35; +static const uint8_t DIO2 = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_stick_lite_v3/pins_arduino.h b/variants/heltec_wireless_stick_lite_v3/pins_arduino.h new file mode 100644 index 0000000..8882fcc --- /dev/null +++ b/variants/heltec_wireless_stick_lite_v3/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define Wireless_Stick_Lite_V3 true +#define DISPLAY_HEIGHT 0 +#define DISPLAY_WIDTH 0 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 2; +static const uint8_t SCL = 3; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 12; +static const uint8_t A8 = 14; +static const uint8_t A9 = 15; +static const uint8_t A10 = 16; +static const uint8_t A11 = 17; +static const uint8_t A12 = 18; +static const uint8_t A13 = 19; +static const uint8_t A14 = 20; + +static const uint8_t T0 = 1; +static const uint8_t T1 = 2; +static const uint8_t T2 = 3; +static const uint8_t T3 = 4; +static const uint8_t T4 = 5; +static const uint8_t T5 = 6; +static const uint8_t T6 = 7; + +static const uint8_t Vext = 36; +static const uint8_t LED = 35; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_stick_v3/pins_arduino.h b/variants/heltec_wireless_stick_v3/pins_arduino.h new file mode 100644 index 0000000..6a55395 --- /dev/null +++ b/variants/heltec_wireless_stick_v3/pins_arduino.h @@ -0,0 +1,81 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define WIRELESS_STICK_V3 true + +#define DISPLAY_HEIGHT 32 +#define DISPLAY_WIDTH 64 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 42; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 36; +static const uint8_t LED = 35; +static const uint8_t RST_OLED = 21; +static const uint8_t SCL_OLED = 18; +static const uint8_t SDA_OLED = 17; + +static const uint8_t RST_LoRa = 12; +static const uint8_t BUSY_LoRa = 13; +static const uint8_t DIO0 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/heltec_wireless_tracker/pins_arduino.h b/variants/heltec_wireless_tracker/pins_arduino.h new file mode 100644 index 0000000..08c2ce2 --- /dev/null +++ b/variants/heltec_wireless_tracker/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 41; +static const uint8_t SCL = 42; + +static const uint8_t SS = 8; +static const uint8_t MOSI = 10; +static const uint8_t MISO = 11; +static const uint8_t SCK = 9; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t Vext = 3; +static const uint8_t LED = 18; +static const uint8_t RST_OLED = 39; +static const uint8_t SCL_OLED = 41; +static const uint8_t SDA_OLED = 42; +#endif /* Pins_Arduino_h */ diff --git a/variants/honeylemon/pins_arduino.h b/variants/honeylemon/pins_arduino.h new file mode 100644 index 0000000..567989a --- /dev/null +++ b/variants/honeylemon/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUILTIN_KEY = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/hornbill32dev/pins_arduino.h b/variants/hornbill32dev/pins_arduino.h new file mode 100644 index 0000000..0bd626a --- /dev/null +++ b/variants/hornbill32dev/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/hornbill32minima/pins_arduino.h b/variants/hornbill32minima/pins_arduino.h new file mode 100644 index 0000000..74ecf87 --- /dev/null +++ b/variants/hornbill32minima/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; //taken out on pgm header +static const uint8_t RX = 3; //taken out on pgm header + +static const uint8_t SDA = 21; //1 +static const uint8_t SCL = 22; //2 + +static const uint8_t SS = 2; //3 +static const uint8_t MOSI = 23; //4 +static const uint8_t MISO = 19; //5 +static const uint8_t SCK = 18; //6 + +static const uint8_t A6 = 34; //7 +static const uint8_t A7 = 35; //8 +static const uint8_t A10 = 4; //9 +static const uint8_t A11 = 0; // taken out on pgm header +static const uint8_t A12 = 2; // with SPI SS +static const uint8_t A13 = 15; //10 +static const uint8_t A14 = 13; //11 + +static const uint8_t DAC1 = 25; //12 +static const uint8_t DAC2 = 26; //13 + +static const uint8_t T0 = 4; //used +static const uint8_t T1 = 0; // taken out on pgm header +static const uint8_t T2 = 2; //used +static const uint8_t T3 = 15; //used + +#endif /* Pins_Arduino_h */ diff --git a/variants/huidu_hd_wf2/pins_arduino.h b/variants/huidu_hd_wf2/pins_arduino.h new file mode 100644 index 0000000..6068e4d --- /dev/null +++ b/variants/huidu_hd_wf2/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Huidu HD-WF2 - esp32-s3 HUB75 driver board +// https://www.hdwell.com/Product/index46.html +// https://github.com/mrcodetastic/ESP32-HUB75-MatrixPanel-DMA/discussions/667 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define WF2_X1_R1_PIN 2 +#define WF2_X1_R2_PIN 3 +#define WF2_X1_G1_PIN 6 +#define WF2_X1_G2_PIN 7 +#define WF2_X1_B1_PIN 10 +#define WF2_X1_B2_PIN 11 +#define WF2_X1_E_PIN 21 + +#define WF2_X2_R1_PIN 4 +#define WF2_X2_R2_PIN 5 +#define WF2_X2_G1_PIN 8 +#define WF2_X2_G2_PIN 9 +#define WF2_X2_B1_PIN 12 +#define WF2_X2_B2_PIN 13 +#define WF2_X2_E_PIN -1 // Currently unknown, so X2 port will not work (yet) with 1/32 scan panels + +#define WF2_A_PIN 39 +#define WF2_B_PIN 38 +#define WF2_C_PIN 37 +#define WF2_D_PIN 36 +#define WF2_OE_PIN 35 +#define WF2_CLK_PIN 34 +#define WF2_LAT_PIN 33 + +#define WF2_BUTTON_TEST 17 // Test key button on PCB, 1=normal, 0=pressed +#define WF2_LED_RUN_PIN 40 // Status LED on PCB +#define WF2_BM8563_I2C_SDA 41 // RTC BM8563 I2C port +#define WF2_BM8563_I2C_SCL 42 +#define WF2_USB_DN_PIN 19 // USB D- +#define WF2_USB_DP_PIN 20 // USB D+ + +#define WF2_PCB1_PIN 45 // open pad on PCB +#define WF2_PCB2_PIN 46 // open pad on PCB + +#define LED_BUILTIN WF2_LED_RUN_PIN +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = WF2_BM8563_I2C_SDA; +static const uint8_t SCL = WF2_BM8563_I2C_SCL; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +#endif /* Pins_Arduino_h */ diff --git a/variants/huidu_hd_wf4/pins_arduino.h b/variants/huidu_hd_wf4/pins_arduino.h new file mode 100644 index 0000000..5b86674 --- /dev/null +++ b/variants/huidu_hd_wf4/pins_arduino.h @@ -0,0 +1,111 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Huidu HD-WF4 - esp32-s3 HUB75 driver board +// https://www.hdwell.com/Product/index46.html +// https://github.com/mrcodetastic/ESP32-HUB75-MatrixPanel-DMA/discussions/667 + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define WF4_A_PIN 39 +#define WF4_B_PIN 38 +#define WF4_C_PIN 37 +#define WF4_D_PIN 36 +#define WF4_E_PIN 21 +#define WF4_OE_PIN 35 +#define WF4_CLK_PIN 34 +#define WF4_LAT_PIN 33 + +// X1 HUB75 +#define WF4_X1_R1_PIN 2 +#define WF4_X1_R2_PIN 3 +#define WF4_X1_G1_PIN 6 +#define WF4_X1_G2_PIN 7 +#define WF4_X1_B1_PIN 10 +#define WF4_X1_B2_PIN 11 +#define WF4_X1_CS_PIN 45 // CS gpio must be set HIGH to enable X1 output + +// X2 HUB75 +#define WF4_X2_R1_PIN 4 +#define WF4_X2_R2_PIN 5 +#define WF4_X2_G1_PIN 8 +#define WF4_X2_G2_PIN 9 +#define WF4_X2_B1_PIN 12 +#define WF4_X2_B2_PIN 13 +#define WF4_X2_CS_PIN WF4_X1_CS_PIN // CS gpio must be set HIGH to enable X2 output + +// X3 HUB75 +#define WF4_X3_R1_PIN 2 +#define WF4_X3_R2_PIN 3 +#define WF4_X3_G1_PIN 6 +#define WF4_X3_G2_PIN 7 +#define WF4_X3_B1_PIN 10 +#define WF4_X3_B2_PIN 11 +#define WF4_X3_CS_PIN 14 // CS gpio must be set HIGH to enable X3 output + +// X4 HUB75 +#define WF4_X4_R1_PIN 4 +#define WF4_X4_R2_PIN 5 +#define WF4_X4_G1_PIN 8 +#define WF4_X4_G2_PIN 9 +#define WF4_X4_B1_PIN 12 +#define WF4_X4_B2_PIN 13 +#define WF4_X4_CS_PIN WF4_X3_CS_PIN // CS gpio must be set HIGH to enable X4 output + +// P1 is a UART connector +#define WF4_P1_RX_PIN 44 +#define WF4_P1_TX_PIN 43 + +// P2: PCB holes gpio/gnd +#define WF4_P2_DATA_PIN 0 // GPIO0 boot + +// P5: temperature sensor connector +#define WF4_P5_DATA_PIN 16 + +// P7: VCC/GPIO holes on PCB +#define WF4_P7_DATA_PIN 1 + +// P11: IR connector +#define WF4_P11_DATA_PIN 15 + +// P12: two gpio's, Vcc, GND +#define WF4_P12_DATA1_PIN 47 +#define WF4_P12_DATA2_PIN 18 + +// S1 Button +#define WF4_S1_DATA_PIN 17 + +// S2-S3 PCB holes +#define WF4_S2_DATA_PIN 48 +#define WF4_S3_DATA_PIN 26 +#define WF4_S4_DATA_PIN 46 + +#define WF4_BUTTON_TEST WF4_S1_PIN // Test key button on PCB, 1=normal, 0=pressed +#define WF4_LED_RUN_PIN 40 // Status LED on PCB +#define WF4_BM8563_I2C_SDA 41 // RTC BM8563 I2C port +#define WF4_BM8563_I2C_SCL 42 +#define WF4_USB_DN_PIN 19 // USB-A D- +#define WF4_USB_DP_PIN 20 // USB-A D+ + +#define LED_BUILTIN WF4_LED_RUN_PIN +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = WF4_P1_TX_PIN; +static const uint8_t RX = WF4_P1_RX_PIN; + +static const uint8_t SDA = WF4_BM8563_I2C_SDA; +static const uint8_t SCL = WF4_BM8563_I2C_SCL; + +// there is no dedicated SPI connector on board, but SPI could be accessed via PCB holes +static const uint8_t SS = WF4_S2_DATA_PIN; +static const uint8_t MOSI = WF4_S3_DATA_PIN; +static const uint8_t MISO = WF4_S4_DATA_PIN; +static const uint8_t SCK = WF4_P7_DATA_PIN; + +// touch pins are mostly busy with HUB75 ports +static const uint8_t T1 = WF4_P7_DATA_PIN; + +#endif /* Pins_Arduino_h */ diff --git a/variants/imbrios-logsens-v1p1/pins_arduino.h b/variants/imbrios-logsens-v1p1/pins_arduino.h new file mode 100644 index 0000000..bece598 --- /dev/null +++ b/variants/imbrios-logsens-v1p1/pins_arduino.h @@ -0,0 +1,95 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Renaming few signals +#define SPI_CLK SCK // IO14 +#define SPI_MISO MISO // IO12 +#define SPI_MOSI MOSI // IO13 +#define SPI_CS0 SS // IO15, Default SPI CS: Extension Header, Pin_3 +#define SD_SPI_CS1 SPI_CS1 // SPI Chip Select: MicroSD Card +#define LED_WIFI_LINK LED1_BUILDIN // LED6 on the LogSens V1.1 Board +#define LED_WIFI_ACT \ + LED2_BUILDIN // LED7 on the LogSens V1.1 Board\ + +/* LED_BUILTIN is kept for compatibility reason; mapped to LED2 on the LogSens V1.1 Board */ +static const uint8_t LED_BUILTIN = 33; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +/* UART0: Serial Port for Programming and Debugging on the LogSens V1.1 Board */ +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +#ifdef BOARD_VARIANT_RS485 +/* UART2: Serial Port connected to RS485 transceiver on the LogSens V1.1 Board */ +static const uint8_t UART2_TX = 17; +static const uint8_t UART2_RX = 16; +static const uint8_t UART2_RTS = 4; +#endif /* BOARD_VARIANT_RS485 */ + +#ifdef BOARD_VARIANT_CAN +/* CAN Bus connected to CAN transceiver on the LogSens V1.1 Board */ +static const uint8_t CAN_TX = 17; +static const uint8_t CAN_RX = 16; +static const uint8_t CAN_TXDE = 4; +#endif /* BOARD_VARIANT_CAN */ + +/* I2C Bus: Shared between RTC chip, Expansion Header (X3), Sensor Header (X7) on the LogSens V1.1 Board */ +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +/* SPI Bus: Shared between MicroSD Card (X6) and Expansion Header (X3) */ +static const uint8_t SS = 15; // SPI Chip Select - 0; Connected to Extension Header, Pin_3 on the LogSens V1.1 Board +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +static const uint8_t SS1 = 23; // SPI Chip Select - 1; connected to MicroSD Card on the LogSens V1.1 Board + +/* Software Controlled: IO, LEDs and Switches */ +static const uint8_t BUZZER_CTRL = 19; // Signal connected to MOSFET gate pin to control connector (X8) +static const uint8_t SD_CARD_DETECT = 35; // MicroSD Card (X6): Card Detect Signal + +static const uint8_t SW2_BUILDIN = 0; // Tactile Switch-2 (SW2); ESP32 BOOT0 pin, Use it with care !! +static const uint8_t SW3_BUILDIN = 36; // Tactile Switch-3 (SW3) +static const uint8_t SW4_BUILDIN = 34; // Tactile Switch-4 (SW4) + +static const uint8_t LED1_BUILDIN = 32; // Connected to LogSens V1.1: LED6 +static const uint8_t LED2_BUILDIN = 33; // Connected to LogSens V1.1: LED7 + +/* Analog Input Channels accessible on the LogSens V1.1 Board */ +//static const uint8_t A0 = 36; +//static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +//static const uint8_t A6 = 34; +//static const uint8_t A7 = 35; +//static const uint8_t A10 = 4; +//static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +//static const uint8_t A14 = 13; +//static const uint8_t A15 = 12; +//static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +//static const uint8_t T0 = 4; +//static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +//static const uint8_t T4 = 13; +//static const uint8_t T5 = 12; +//static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +/* DAC Channels accessible on the LogSens V1.1 Board */ +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/intorobot-fig/pins_arduino.h b/variants/intorobot-fig/pins_arduino.h new file mode 100644 index 0000000..d6a1349 --- /dev/null +++ b/variants/intorobot-fig/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_R_BUILTIN = 27; +static const uint8_t RGB_G_BUILTIN = 21; +static const uint8_t RGB_B_BUILTIN = 22; + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 19; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 16; +static const uint8_t MISO = 17; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 35; +static const uint8_t A3 = 25; +static const uint8_t A4 = 26; +static const uint8_t A5 = 14; +static const uint8_t A6 = 12; +static const uint8_t A7 = 15; +static const uint8_t A8 = 13; +static const uint8_t A9 = 2; + +static const uint8_t D0 = 19; +static const uint8_t D1 = 23; +static const uint8_t D2 = 18; +static const uint8_t D3 = 17; +static const uint8_t D4 = 16; +static const uint8_t D5 = 5; +static const uint8_t D6 = 4; + +static const uint8_t T0 = 19; +static const uint8_t T1 = 23; +static const uint8_t T2 = 18; +static const uint8_t T3 = 17; +static const uint8_t T4 = 16; +static const uint8_t T5 = 5; +static const uint8_t T6 = 4; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ioxesp32/pins_arduino.h b/variants/ioxesp32/pins_arduino.h new file mode 100644 index 0000000..bc0d7a1 --- /dev/null +++ b/variants/ioxesp32/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ioxesp32c6/pins_arduino.h b/variants/ioxesp32c6/pins_arduino.h new file mode 100644 index 0000000..bcd2011 --- /dev/null +++ b/variants/ioxesp32c6/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 20; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/jczn_2432s028r/partitions_all_app_4MB.csv b/variants/jczn_2432s028r/partitions_all_app_4MB.csv new file mode 100644 index 0000000..25eeb8c --- /dev/null +++ b/variants/jczn_2432s028r/partitions_all_app_4MB.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +factory, app, factory, 0x10000, 0x3F0000, diff --git a/variants/jczn_2432s028r/partitions_otanofs_4MB.csv b/variants/jczn_2432s028r/partitions_otanofs_4MB.csv new file mode 100644 index 0000000..04240ba --- /dev/null +++ b/variants/jczn_2432s028r/partitions_otanofs_4MB.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags + nvs, data, nvs, 0x9000, 0x5000, + otadata, data, ota, 0xE000, 0x2000, + app0, app, ota_0, 0x10000, 0x1F0000, + app1, app, ota_1, 0x200000, 0x1F0000, +coredump, data, coredump, 0x3F0000, 0x10000, diff --git a/variants/jczn_2432s028r/pins_arduino.h b/variants/jczn_2432s028r/pins_arduino.h new file mode 100644 index 0000000..ba10d0f --- /dev/null +++ b/variants/jczn_2432s028r/pins_arduino.h @@ -0,0 +1,91 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t D35 = 35; +static const uint8_t D22 = 22; +static const uint8_t D27 = 27; +static const uint8_t D21 = 21; + +static const uint8_t A6 = 34; +static const uint8_t A17 = 27; + +static const uint8_t T7 = 27; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#define CYD_TP_IRQ 36 +#define CYD_TP_MOSI 32 +#define CYD_TP_MISO 39 +#define CYD_TP_CLK 25 +#define CYD_TP_CS 33 +#define CYD_TP_DIN CYD_TP_MOSI +#define CYD_TP_OUT CYD_TP_MOSI +#define CYD_TP_SPI_BUS VSPI + +#define CYD_TFT_DC 2 +#define CYD_TFT_MISO 12 +#define CYD_TFT_MOSI 13 +#define CYD_TFT_SCK 14 +#define CYD_TFT_CS 15 +#define CYD_TFT_RS CYD_TFT_DC +#define CYD_TFT_SDO CYD_TFT_MISO +#define CYD_TFT_SDI CYD_TFT_MOSI +#define CYD_TFT_SPI_BUS HSPI + +#define CYD_TFT_WIDTH 320 +#define CYD_TFT_HEIGHT 240 +#define CYD_SCREEN_WIDTH CYD_TFT_WIDTH +#define CYD_SCREEN_HEIGHT CYD_TFT_HEIGHT + +#define CYD_TFT_BL 21 +#define CYD_TFT_BL_ENABLE() ((pinMode(CYD_TFT_BL, OUTPUT))) +#define CYD_TFT_BL_OFF() (digitalWrite(CYD_TFT_BL, 0)) +#define CYD_TFT_BL_ON() (digitalWrite(CYD_TFT_BL, 1)) + +#define CYD_LED_RED 4 +#define CYD_LED_GREEN 16 +#define CYD_LED_BLUE 17 + +#define CYD_AUDIO_OUT 26 + +#define CYD_USER_BUTTON 0 + +#define CYD_SD_SS 5 +#define CYD_SD_MOSI 23 +#define CYD_SD_MISO 19 +#define CYD_SD_SCK 18 +#define CYD_SD_SPI_BUS VSPI + +#define CYD_LDR 34 + +#define CYD_LED_RED_OFF() (digitalWrite(CYD_LED_RED, 1)) +#define CYD_LED_RED_ON() (digitalWrite(CYD_LED_RED, 0)) +#define CYD_LED_GREEN_OFF() (digitalWrite(CYD_LED_GREEN, 1)) +#define CYD_LED_GREEN_ON() (digitalWrite(CYD_LED_GREEN, 0)) +#define CYD_LED_BLUE_OFF() (digitalWrite(CYD_LED_BLUE, 1)) +#define CYD_LED_BLUE_ON() (digitalWrite(CYD_LED_BLUE, 0)) +#define CYD_LED_RGB_OFF() \ + CYD_LED_RED_OFF(); \ + CYD_LED_GREEN_OFF(); \ + CYD_LED_BLUE_OFF() +#define CYD_LED_RGB_ON() \ + CYD_LED_RED_ON(); \ + CYD_LED_GREEN_ON(); \ + CYD_LED_BLUE_ON() +#define CYD_LED_WHITE_OFF() CYD_LED_RGB_OFF() +#define CYD_LED_WHITE_ON() CYD_LED_RGB_ON() + +#endif /* Pins_Arduino_h */ diff --git a/variants/jczn_2432s028r/variant.cpp b/variants/jczn_2432s028r/variant.cpp new file mode 100644 index 0000000..a56fc4c --- /dev/null +++ b/variants/jczn_2432s028r/variant.cpp @@ -0,0 +1,13 @@ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { +// Initialize variant/board, called before setup() +void initVariant(void) { + pinMode(CYD_LED_RED, OUTPUT); + pinMode(CYD_LED_GREEN, OUTPUT); + pinMode(CYD_LED_BLUE, OUTPUT); + CYD_LED_RGB_OFF(); +} +} diff --git a/variants/kodedot/custom_ota_override.cpp b/variants/kodedot/custom_ota_override.cpp new file mode 100644 index 0000000..a41db01 --- /dev/null +++ b/variants/kodedot/custom_ota_override.cpp @@ -0,0 +1,14 @@ +// custom_ota_override.cpp +// This function overrides the weak definition of `verifyRollbackLater()` in the kode dot board. + +extern "C" { +// Declare the weak function symbol to override it +bool verifyRollbackLater() __attribute__((weak)); +} + +// Custom implementation of verifyRollbackLater() +// Returning `true` prevents the OTA image from being automatically marked as valid. +// This ensures that the system will roll back to the previous image unless it is explicitly validated later. +bool verifyRollbackLater() { + return true; +} diff --git a/variants/kodedot/kodedot_partitions.csv b/variants/kodedot/kodedot_partitions.csv new file mode 100644 index 0000000..f073233 --- /dev/null +++ b/variants/kodedot/kodedot_partitions.csv @@ -0,0 +1,7 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +otadata, data, ota, 0x10000, 0x2000, +ota_0, app, ota_0, 0x20000, 0x3E0000, +ota_1, app, ota_1, 0x400000, 0x800000, +storage, data, spiffs, 0xC00000, 0x400000, diff --git a/variants/kodedot/pins_arduino.h b/variants/kodedot/pins_arduino.h new file mode 100644 index 0000000..e692443 --- /dev/null +++ b/variants/kodedot/pins_arduino.h @@ -0,0 +1,110 @@ +/* + ──────────────────────────────────────────────────────────────────────── + KodeDot – ESP32-S3R8 Variant (rev. with OPI flash/PSRAM) + Pin definition file for the Arduino-ESP32 core + ──────────────────────────────────────────────────────────────────────── + * External 2 × 10 connector → simple aliases PIN1 … PIN20 + * On-board QSPI LCD 410×502 @40 MHz (SPI3_HOST) + * micro-SD on SDMMC (1-bit) + * Dual-I²C: external (GPIO37/36) + internal-sensors (GPIO48/47) + * USB VID/PID 0x303A:0x1001 +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include + +/*──────────────── USB device descriptor ────────────────*/ +#define USB_VID 0x303A // Espressif Systems VID +#define USB_PID 0x1001 // Product ID: KodeDot-S3 + +/*──────────────── UART0 (Arduino Serial) ────────────────*/ +static const uint8_t TX = 43; // U0TXD – PIN16 on the 2×10 header +static const uint8_t RX = 44; // U0RXD – PIN18 on the 2×10 header + +/*──────────────── I²C buses ─────────────────────────────*/ +/* External expansion bus → header pins 11/13 */ +static const uint8_t SCL = 37; // GPIO37 – PIN12 +static const uint8_t SDA = 36; // GPIO36 – PIN14 + +/* Internal sensor/touch bus (not on header) */ +#define INT_I2C_SCL 47 // GPIO47 +#define INT_I2C_SDA 48 // GPIO48 + +/*──────────────── SDMMC – micro-SD (1-bit) ───────────────*/ +#define BOARD_HAS_SD_SDMMC +#define SDMMC_CMD 5 // SD_CMD +#define SDMMC_CLK 6 // SD_CLK +#define SDMMC_D0 7 // SD_D0 +#define SD_CS -1 // No CS pin in SDMMC mode + +/*──────────────── QSPI LCD (SPI3_HOST) ─────────────────– + * Controller: ST7789 / 4-line SPI (no D/C pin) + * Resolution: 410×502 px, 16 bpp, RGB color-space + * Clock: 40 MHz + */ +#define BOARD_HAS_SPI_LCD +#define LCD_MODEL ST7789 +#define LCD_WIDTH 410 +#define LCD_HEIGHT 502 + +#define LCD_HOST SPI3_HOST +#define LCD_SCK 17 // GPIO17 • QSPI_CLK +#define LCD_MOSI 15 // GPIO15 • QSPI_IO0 (D0) +#define LCD_IO1 14 // GPIO14 • QSPI_IO1 (D1) +#define LCD_IO2 16 // GPIO16 • QSPI_IO2 (D2) +#define LCD_IO3 10 // GPIO10 • QSPI_IO3 (D3) +#define LCD_CS 9 // GPIO09 +#define LCD_RST 8 // GPIO08 +#define LCD_DC -1 // not used in 4-line SPI + +/*──────────────── Analog / Touch pads ────────────────*/ +static const uint8_t A0 = 11; // PIN4 – GPIO11 / TOUCH11 / ADC2_CH0 +static const uint8_t A1 = 12; // PIN6 – GPIO12 / TOUCH12 / ADC2_CH1 +static const uint8_t A2 = 13; // PIN8 – GPIO13 / TOUCH13 / ADC2_CH2 +static const uint8_t A3 = 14; // PIN10 – GPIO14 / TOUCH14 / ADC2_CH3 +static const uint8_t T0 = A0, T1 = A1, T2 = A2, T3 = A3; + +/*──────────────── On-board controls & indicator ─────────*/ +#define BUTTON_TOP 0 // GPIO00 – BOOT • active-LOW +#define BUTTON_BOTTOM -1 // via IO expander • no direct GPIO +#define NEOPIXEL_PIN 4 // GPIO04 – WS2812 +#define LED_BUILTIN NEOPIXEL_PIN + +/*──────────────── JTAG (also on connector) ──────────────*/ +#define MTCK 39 // PIN11 – GPIO39 +#define MTDO 40 // PIN13 – GPIO40 +#define MTDI 41 // PIN15 – GPIO41 +#define MTMS 42 // PIN17 – GPIO42 + +/*──────────────── 2×10 header: simple aliases ─────────── + NOTE: power pins (1 = 5 V, 2 = 3 V3, 19/20 = GND) are **not** + exposed as GPIO numbers – they remain undefined here. */ +#define PIN3 1 // GPIO01 / TOUCH1 / ADC1_CH0 +#define PIN4 11 // GPIO11 / TOUCH11 / ADC2_CH0 +#define PIN5 2 // GPIO02 / TOUCH2 / ADC1_CH1 +#define PIN6 12 // GPIO12 / TOUCH12 / ADC2_CH1 +#define PIN7 3 // GPIO03 / TOUCH3 / ADC1_CH2 +#define PIN8 13 // GPIO13 / TOUCH13 / ADC2_CH2 +#define PIN9 4 // GPIO04 / TOUCH4 / ADC1_CH3 +#define PIN10 14 // GPIO14 / TOUCH14 / ADC2_CH3 +#define PIN11 39 // MTCK +#define PIN12 37 // SCL (external I²C) +#define PIN13 40 // MTDO +#define PIN14 36 // SDA (external I²C) +#define PIN15 41 // MTDI +#define PIN16 43 // TX (U0TXD) +#define PIN17 42 // MTMS +#define PIN18 44 // RX (U0RXD) +/* PIN1, PIN2, PIN19, PIN20 are power/ground and deliberately + left undefined – they are **not** usable as GPIO. */ + +/* ==== Default SPI pins for library compatibility ==== */ +#define SCK 17 // LCD_SCK • QSPI_CLK +#define MISO -1 // No MISO available in this design +#define MOSI 15 // LCD_MOSI • QSPI_IO0 +#define SS 9 // LCD_CS + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t3_s3_lr1121/pins_arduino.h b/variants/lilygo_t3_s3_lr1121/pins_arduino.h new file mode 100644 index 0000000..4259d4c --- /dev/null +++ b/variants/lilygo_t3_s3_lr1121/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x820A + +static const uint8_t LED_BUILTIN = 37; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BAT_VOLT = 1; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +#define WIRE1_PIN_DEFINED //QWIIC +static const uint8_t SDA1 = 10; +static const uint8_t SCL1 = 21; + +// SD Card SPI +static const uint8_t SS = 13; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +#define LORA_SCK 5 // LR1121 SCK +#define LORA_MISO 3 // LR1121 MISO +#define LORA_MOSI 6 // LR1121 MOSI +#define LORA_CS 7 // LR1121 CS +#define LORA_RST 8 // LR1121 RST + +#define LORA_DIO9 36 // LR1121 DIO9 +#define LORA_BUSY 34 // LR1121 BUSY +#define LORA_IRQ LORA_DIO9 + +// P1 +static const uint8_t PIN_42 = 45; +static const uint8_t PIN_46 = 46; +static const uint8_t PIN_45 = 45; +static const uint8_t PIN_41 = 41; +static const uint8_t PIN_40 = 40; +static const uint8_t PIN_39 = 39; +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_38 = 38; + +// P2 +static const uint8_t PIN_37 = 37; +static const uint8_t PIN_36 = 36; +static const uint8_t PIN_0 = 0; +static const uint8_t PIN_35 = 35; +static const uint8_t PIN_34 = 34; +static const uint8_t PIN_33 = 33; +static const uint8_t PIN_47 = 47; +static const uint8_t PIN_48 = 48; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_8 = 8; +static const uint8_t PIN_15 = 15; +static const uint8_t PIN_16 = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t3_s3_sx1262/pins_arduino.h b/variants/lilygo_t3_s3_sx1262/pins_arduino.h new file mode 100644 index 0000000..8211473 --- /dev/null +++ b/variants/lilygo_t3_s3_sx1262/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x820A + +static const uint8_t LED_BUILTIN = 37; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BAT_VOLT = 1; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +#define WIRE1_PIN_DEFINED //QWIIC +static const uint8_t SDA1 = 10; +static const uint8_t SCL1 = 21; + +// SD Card SPI +static const uint8_t SS = 13; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +#define LORA_SCK 5 // SX1262 SCK +#define LORA_MISO 3 // SX1262 MISO +#define LORA_MOSI 6 // SX1262 MOSI +#define LORA_CS 7 // SX1262 CS +#define LORA_RST 8 // SX1262 RST + +#define LORA_DIO1 33 //SX1262 DIO1 +#define LORA_BUSY 34 +#define LORA_IRQ LORA_DIO1 + +// P1 +static const uint8_t PIN_42 = 45; +static const uint8_t PIN_46 = 46; +static const uint8_t PIN_45 = 45; +static const uint8_t PIN_41 = 41; +static const uint8_t PIN_40 = 40; +static const uint8_t PIN_39 = 39; +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_38 = 38; + +// P2 +static const uint8_t PIN_37 = 37; +static const uint8_t PIN_36 = 36; +static const uint8_t PIN_0 = 0; +static const uint8_t PIN_35 = 35; +static const uint8_t PIN_34 = 34; +static const uint8_t PIN_33 = 33; +static const uint8_t PIN_47 = 47; +static const uint8_t PIN_48 = 48; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_8 = 8; +static const uint8_t PIN_15 = 15; +static const uint8_t PIN_16 = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t3_s3_sx127x/pins_arduino.h b/variants/lilygo_t3_s3_sx127x/pins_arduino.h new file mode 100644 index 0000000..8b73a6b --- /dev/null +++ b/variants/lilygo_t3_s3_sx127x/pins_arduino.h @@ -0,0 +1,74 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x820A + +static const uint8_t LED_BUILTIN = 37; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BAT_VOLT = 1; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +#define WIRE1_PIN_DEFINED //QWIIC +static const uint8_t SDA1 = 10; +static const uint8_t SCL1 = 21; + +// SD Card SPI +static const uint8_t SS = 13; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +#define LORA_SCK 5 // SX1276/SX1278 SCK +#define LORA_MISO 3 // SX1276/SX1278 MISO +#define LORA_MOSI 6 // SX1276/SX1278 MOSI +#define LORA_CS 7 // SX1276/SX1278 CS +#define LORA_RST 8 // SX1276/SX1278 RST + +#define LORA_DIO0 9 //IRQ +#define LORA_DIO1 33 +#define LORA_DIO2 34 +#define LORA_DIO3 21 +#define LORA_DIO4 10 +#define LORA_DIO5 36 + +#define LORA_IRQ LORA_DIO0 +#define LORA_BUSY LORA_DIO1 + +// P1 +static const uint8_t PIN_42 = 45; +static const uint8_t PIN_46 = 46; +static const uint8_t PIN_45 = 45; +static const uint8_t PIN_41 = 41; +static const uint8_t PIN_40 = 40; +static const uint8_t PIN_39 = 39; +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_38 = 38; + +// P2 +static const uint8_t PIN_37 = 37; +static const uint8_t PIN_36 = 36; +static const uint8_t PIN_0 = 0; +static const uint8_t PIN_35 = 35; +static const uint8_t PIN_34 = 34; +static const uint8_t PIN_33 = 33; +static const uint8_t PIN_47 = 47; +static const uint8_t PIN_48 = 48; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_8 = 8; +static const uint8_t PIN_15 = 15; +static const uint8_t PIN_16 = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t3_s3_sx1280/pins_arduino.h b/variants/lilygo_t3_s3_sx1280/pins_arduino.h new file mode 100644 index 0000000..567dd65 --- /dev/null +++ b/variants/lilygo_t3_s3_sx1280/pins_arduino.h @@ -0,0 +1,68 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x820A + +static const uint8_t LED_BUILTIN = 37; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BAT_VOLT = 1; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +#define WIRE1_PIN_DEFINED //QWIIC +static const uint8_t SDA1 = 10; +static const uint8_t SCL1 = 21; + +// SD Card SPI +static const uint8_t SS = 13; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +#define LORA_SCK 5 // SX1280 SCK +#define LORA_MISO 3 // SX1280 MISO +#define LORA_MOSI 6 // SX1280 MOSI +#define LORA_CS 7 // SX1280 CS +#define LORA_RST 8 // SX1280 RST + +#define LORA_DIO1 9 // SX1280 DIO1 +#define LORA_BUSY 36 // SX1280 BUSY +#define LORA_IRQ LORA_DIO1 + +// P1 +static const uint8_t PIN_42 = 45; +static const uint8_t PIN_46 = 46; +static const uint8_t PIN_45 = 45; +static const uint8_t PIN_41 = 41; +static const uint8_t PIN_40 = 40; +static const uint8_t PIN_39 = 39; +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_38 = 38; + +// P2 +static const uint8_t PIN_37 = 37; +static const uint8_t PIN_36 = 36; +static const uint8_t PIN_0 = 0; +static const uint8_t PIN_35 = 35; +static const uint8_t PIN_34 = 34; +static const uint8_t PIN_33 = 33; +static const uint8_t PIN_47 = 47; +static const uint8_t PIN_48 = 48; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_8 = 8; +static const uint8_t PIN_15 = 15; +static const uint8_t PIN_16 = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h b/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h new file mode 100644 index 0000000..e691320 --- /dev/null +++ b/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h @@ -0,0 +1,67 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x820A + +static const uint8_t LED_BUILTIN = 37; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BAT_VOLT = 1; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +// SD Card SPI +static const uint8_t SS = 13; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +#define LORA_SCK 5 // SX1280PA SCK +#define LORA_MISO 3 // SX1280PA MISO +#define LORA_MOSI 6 // SX1280PA MOSI +#define LORA_CS 7 // SX1280PA CS +#define LORA_RST 8 // SX1280PA RST + +#define LORA_DIO1 9 // SX1280 DIO1 +#define LORA_BUSY 36 // SX1280 BUSY +#define LORA_IRQ LORA_DIO1 + +#define LORA_RX 21 // SX1280PA RX SWITCH +#define LORA_TX 10 // SX1280PA TX SWITCH + +// P1 +static const uint8_t PIN_42 = 45; +static const uint8_t PIN_46 = 46; +static const uint8_t PIN_45 = 45; +static const uint8_t PIN_41 = 41; +static const uint8_t PIN_40 = 40; +static const uint8_t PIN_39 = 39; +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_38 = 38; + +// P2 +static const uint8_t PIN_37 = 37; +static const uint8_t PIN_36 = 36; +static const uint8_t PIN_0 = 0; +static const uint8_t PIN_35 = 35; +static const uint8_t PIN_34 = 34; +static const uint8_t PIN_33 = 33; +static const uint8_t PIN_47 = 47; +static const uint8_t PIN_48 = 48; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_8 = 8; +static const uint8_t PIN_15 = 15; +static const uint8_t PIN_16 = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t_display/pins_arduino.h b/variants/lilygo_t_display/pins_arduino.h new file mode 100644 index 0000000..b560f64 --- /dev/null +++ b/variants/lilygo_t_display/pins_arduino.h @@ -0,0 +1,60 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x1A86 +#define USB_PID 0x55D4 +#define USB_MANUFACTURER "Lilygo" +#define USB_PRODUCT "T-Display" +#define USB_SERIAL "" + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t VBAT = 34; +#define BAT_VOLT_PIN VBAT + +static const uint8_t RIGHT_BUTTON = 35; +static const uint8_t LEFT_BUTTON = 0; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t_display_s3/pins_arduino.h b/variants/lilygo_t_display_s3/pins_arduino.h new file mode 100644 index 0000000..1790765 --- /dev/null +++ b/variants/lilygo_t_display_s3/pins_arduino.h @@ -0,0 +1,83 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t BUTTON_1 = 0; +static const uint8_t BUTTON_2 = 14; +static const uint8_t BAT_VOLT = 4; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t TP_RESET = 21; +static const uint8_t TP_INIT = 16; + +// ST7789 IPS TFT 170x320 +static const uint8_t LCD_BL = 38; +static const uint8_t LCD_D0 = 39; +static const uint8_t LCD_D1 = 40; +static const uint8_t LCD_D2 = 41; +static const uint8_t LCD_D3 = 42; +static const uint8_t LCD_D4 = 45; +static const uint8_t LCD_D5 = 46; +static const uint8_t LCD_D6 = 47; +static const uint8_t LCD_D7 = 48; +static const uint8_t LCD_WR = 8; +static const uint8_t LCD_RD = 9; +static const uint8_t LCD_DC = 7; +static const uint8_t LCD_CS = 6; +static const uint8_t LCD_RES = 5; +static const uint8_t LCD_POWER_ON = 15; + +// P1 +static const uint8_t PIN_43 = 43; +static const uint8_t PIN_44 = 44; +static const uint8_t PIN_18 = 18; +static const uint8_t PIN_17 = 17; +static const uint8_t PIN_21 = 21; +static const uint8_t PIN_16 = 16; + +// P2 +static const uint8_t PIN_1 = 1; +static const uint8_t PIN_2 = 2; +static const uint8_t PIN_3 = 3; +static const uint8_t PIN_10 = 10; +static const uint8_t PIN_11 = 11; +static const uint8_t PIN_12 = 12; +static const uint8_t PIN_13 = 13; + +// Analog +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +// Touch +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_t_eth_lite/pins_arduino.h b/variants/lilygo_t_eth_lite/pins_arduino.h new file mode 100644 index 0000000..cb8fed7 --- /dev/null +++ b/variants/lilygo_t_eth_lite/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 15; +static const uint8_t SCL = 16; + +static const uint8_t SS = 4; +static const uint8_t MISO = 5; +static const uint8_t MOSI = 6; +static const uint8_t SCK = 7; +static const uint8_t SD_SS = 42; + +// Analog +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; + +// Touch +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; + +// Ethernet +#define ETH_PHY_TYPE ETH_PHY_W5500 +#define ETH_PHY_ADDR 1 +#define ETH_PHY_CS 9 +#define ETH_PHY_IRQ 13 +#define ETH_PHY_RST 14 +#define ETH_PHY_SPI_HOST SPI2_HOST +#define ETH_PHY_SPI_SCK 10 +#define ETH_PHY_SPI_MISO 11 +#define ETH_PHY_SPI_MOSI 12 + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_tlora_pager/pins_arduino.h b/variants/lilygo_tlora_pager/pins_arduino.h new file mode 100644 index 0000000..fb57b5d --- /dev/null +++ b/variants/lilygo_tlora_pager/pins_arduino.h @@ -0,0 +1,102 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#ifndef digitalPinToInterrupt +#define digitalPinToInterrupt(p) (((p) < 48) ? (p) : -1) +#endif + +#define USB_VID 0x303a +#define USB_PID 0x82D4 +#define USB_MANUFACTURER "LILYGO" +#define USB_PRODUCT "T-LoRa-Pager" + +// ST7796 +#define DISP_WIDTH (222) +#define DISP_HEIGHT (480) +#define SD_CS (21) + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// BHI260,PCF85063,BQ25896,DRV2605L,ES8311 share I2C Bus +static const uint8_t SDA = 3; +static const uint8_t SCL = 2; + +// Default sd cs pin +static const uint8_t SS = SD_CS; +static const uint8_t MOSI = 34; +static const uint8_t MISO = 33; +static const uint8_t SCK = 35; + +#define KB_INT (6) +#define KB_BACKLIGHT (46) + +// Rotary +#define ROTARY_A (40) +#define ROTARY_B (41) +#define ROTARY_C (7) + +// Interrupt IO port +#define RTC_INT (1) +#define NFC_INT (5) +#define SENSOR_INT (8) +#define NFC_CS (39) + +// ES8311 +#define I2S_WS (18) +#define I2S_SCK (11) +#define I2S_MCLK (10) +#define I2S_SDOUT (45) +#define I2S_SDIN (17) + +// GPS +#define GPS_TX (12) +#define GPS_RX (4) +#define GPS_PPS (13) + +// LoRa, SD, ST25R3916 card share SPI bus +#define LORA_SCK (SCK) // share spi bus +#define LORA_MISO (MISO) // share spi bus +#define LORA_MOSI (MOSI) // share spi bus +#define LORA_CS (36) +#define LORA_RST (47) +#define LORA_BUSY (48) +#define LORA_IRQ (14) + +// SPI interface display +#define DISP_MOSI (MOSI) +#define DISP_MISO (MISO) +#define DISP_SCK (SCK) +#define DISP_RST (-1) +#define DISP_CS (38) +#define DISP_DC (37) +#define DISP_BL (42) + +// External expansion chip IO definition +#define EXPANDS_DRV_EN (0) +#define EXPANDS_AMP_EN (1) +#define EXPANDS_KB_RST (2) +#define EXPANDS_LORA_EN (3) +#define EXPANDS_GPS_EN (4) +#define EXPANDS_NFC_EN (5) +#define EXPANDS_GPS_RST (7) +#define EXPANDS_KB_EN (8) +#define EXPANDS_GPIO_EN (9) +#define EXPANDS_SD_DET (10) +#define EXPANDS_SD_PULLEN (11) +#define EXPANDS_SD_EN (12) + +// Peripheral definition exists +#define USING_AUDIO_CODEC +#define USING_XL9555_EXPANDS +#define USING_PPM_MANAGE +#define USING_BQ_GAUGE +#define USING_INPUT_DEV_ROTARY +#define USING_INPUT_DEV_KEYBOARD +#define USING_ST25R3916 +#define USING_BHI260_SENSOR +#define HAS_SD_CARD_SOCKET + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_twatch_s3/pins_arduino.h b/variants/lilygo_twatch_s3/pins_arduino.h new file mode 100644 index 0000000..05543de --- /dev/null +++ b/variants/lilygo_twatch_s3/pins_arduino.h @@ -0,0 +1,76 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x821B +#define USB_MANUFACTURER "LILYGO" +#define USB_PRODUCT "T-Watch-S3" + +#define DISP_WIDTH (240) +#define DISP_HEIGHT (240) + +#define DISP_MOSI (13) +#define DISP_MISO (-1) +#define DISP_SCK (18) +#define DISP_RST (-1) +#define DISP_CS (12) +#define DISP_DC (38) +#define DISP_BL (45) + +// touch screen +#define TP_INT (16) +#define TP_SDA (39) +#define TP_SCL (40) + +// Interrupt IO port +#define RTC_INT (17) +#define PMU_INT (21) +#define SENSOR_INT (14) + +// PDM microphone +#define MIC_SCK (44) +#define MIC_DAT (47) + +// MAX98357A +#define I2S_BCLK (48) +#define I2S_WCLK (15) +#define I2S_DOUT (46) + +#define IR_SEND (2) + +// TX, RX pin connected to GPS +static const uint8_t TX = 42; +static const uint8_t RX = 41; + +// BMA423,PCF8563,AXP2101,DRV2605L share I2C Bus +static const uint8_t SDA = 10; +static const uint8_t SCL = 11; + +// Default sd cs pin +static const uint8_t SS = 5; +static const uint8_t MOSI = 1; +static const uint8_t MISO = 4; +static const uint8_t SCK = 3; + +// LoRa and SD card share SPI bus +#define LORA_SCK (SCK) // share spi bus +#define LORA_MISO (MISO) // share spi bus +#define LORA_MOSI (MOSI) // share spi bus +#define LORA_CS (5) +#define LORA_RST (8) +#define LORA_BUSY (7) +#define LORA_IRQ (9) + +#define GPS_TX (TX) +#define GPS_RX (RX) + +// Peripheral definition exists +#define USING_PCM_AMPLIFIER +#define USING_PDM_MICROPHONE +#define USING_PMU_MANAGE +#define USING_INPUT_DEV_TOUCHPAD +#define USING_IR_REMOTE + +#endif /* Pins_Arduino_h */ diff --git a/variants/lilygo_twatch_ultra/pins_arduino.h b/variants/lilygo_twatch_ultra/pins_arduino.h new file mode 100644 index 0000000..91797e6 --- /dev/null +++ b/variants/lilygo_twatch_ultra/pins_arduino.h @@ -0,0 +1,93 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#ifndef digitalPinToInterrupt +#define digitalPinToInterrupt(p) (((p) < 48) ? (p) : -1) +#endif + +#define USB_VID 0x303a +#define USB_PID 0x8227 +#define USB_MANUFACTURER "LILYGO" +#define USB_PRODUCT "T-Watch-Ultra" + +#define DISP_WIDTH 502 +#define DISP_HEIGHT 410 + +// QSPI interface display +#define DISP_D0 (38) +#define DISP_D1 (39) +#define DISP_D2 (42) +#define DISP_D3 (45) +#define DISP_SCK (40) +#define DISP_CS (41) +#define DISP_RST (37) +#define DISP_TE (6) + +// Interrupt IO port +#define TP_INT (12) +#define RTC_INT (1) +#define PMU_INT (7) +#define NFC_INT (5) +#define SENSOR_INT (8) +#define NFC_CS (4) + +// PDM microphone +#define MIC_SCK (17) +#define MIC_DAT (18) + +// MAX98357A +#define I2S_BCLK (9) +#define I2S_WCLK (10) +#define I2S_DOUT (11) + +#define SD_CS (21) + +// TX, RX pin connected to GPS +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// BHI260,PCF85063,AXP2101,DRV2605L share I2C Bus +static const uint8_t SDA = 3; +static const uint8_t SCL = 2; + +// Default sd cs pin +static const uint8_t SS = SD_CS; +static const uint8_t MOSI = 34; +static const uint8_t MISO = 33; +static const uint8_t SCK = 35; + +#define GPS_TX (TX) +#define GPS_RX (RX) +#define GPS_PPS (13) + +#define TP_SDA (SDA) +#define TP_SCL (SCL) + +// LoRa and SD card share SPI bus +#define LORA_SCK (SCK) // share spi bus +#define LORA_MISO (MISO) // share spi bus +#define LORA_MOSI (MOSI) // share spi bus +#define LORA_CS (36) +#define LORA_RST (47) +#define LORA_BUSY (48) +#define LORA_IRQ (14) + +// External expansion chip IO definition +#define EXPANDS_DRV_EN (6) +#define EXPANDS_DISP_EN (7) +#define EXPANDS_TOUCH_RST (8) +#define EXPANDS_SD_DET (10) + +// Peripheral definition exists +#define USING_XL9555_EXPANDS +#define USING_PCM_AMPLIFIER +#define USING_PDM_MICROPHONE +#define USING_PMU_MANAGE +#define USING_INPUT_DEV_TOUCHPAD +#define USING_ST25R3916 +#define USING_BHI260_SENSOR +#define HAS_SD_CARD_SOCKET + +#endif /* Pins_Arduino_h */ diff --git a/variants/lionbit/pins_arduino.h b/variants/lionbit/pins_arduino.h new file mode 100644 index 0000000..5e1ee23 --- /dev/null +++ b/variants/lionbit/pins_arduino.h @@ -0,0 +1,89 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 0; // GPIO0, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1,EMAC_TX_CLK +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SWITCH_A = 2; // GPIO2, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0,SD_DATA0 +static const uint8_t SWITCH_B = 4; // GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1,SD_DATA1, EMAC_TX_ER + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +/* LionBit pin setup */ +static const uint8_t D0 = 3; //Rx GPIO3, U0RXD, CLK_OUT2 +static const uint8_t D1 = 1; //TX GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2 +//------------------------------------------------------------------- + +//Please do not use while using QIO SPI mode ; Use only DIO flash mode +static const uint8_t D2 = 9; //I/O U1RX GPIO9, SD_DATA2, SPIHD, HS1_DATA2, U1RXD +static const uint8_t D3 = 10; //I/O U1TX GPIO10, SD_DATA3, SPIWP, HS1_DATA3, U1TXD +//------------------------------------------------------------------- +static const uint8_t U1RX = 9; //I/O U1RX +static const uint8_t U1TX = 10; //I/O U1TX + +//Second Segment - Sector -01 (Voltage (*5v or 3.3V) can be selected by using D4-7 Jumper +static const uint8_t D4 = 16; //I/O U2RX GPIO16, HS1_DATA4, U2RXD, EMAC_CLK_OUT +static const uint8_t D5 = 17; //I/O U2TX GPIO17, HS1_DATA5, U2TXD, EMAC_CLK_OUT_180 +static const uint8_t D6 = 21; //I/O SDA GPIO21, VSPIHD, EMAC_TX_EN +static const uint8_t D7 = 22; //I/O SCl GPIO22, VSPIWP, U0RTS, EMAC_TXD1 + +//Second Segment - Sector -02 (Voltage (*5v or 3.3V) can be selected by using D8-11 Jumper +static const uint8_t D8 = 5; //I/O GPIO5, VSPICS0, HS1_DATA6, EMAC_RX_CLK +static const uint8_t D9 = + 23; //I/O GPIO23, VSPID, HS1_STROBE **********************************************Don not use when display "ON or USE"************************* +static const uint8_t D10 = 19; //I/O GPIO19, VSPIQ, U0CTS, EMAC_TXD0 +static const uint8_t D11 = + 18; //I/O GPIO18, VSPICLK, HS1_DATA7 **********************************************Don not use when display "ON or USE"************************* + +// Analog to Digital Converter (Support 5V) ADC2 pins not recommended while using Wifi +static const uint8_t A0 /*ADC2_CH3 */ = 12; //MAX 5V,I/O GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI, HSPIQ, HS2_DATA2,SD_DATA2, EMAC_TXD3 +static const uint8_t A1 /*ADC1_CH0 */ = 14; //MAX 5V,I/O GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK,SD_CLK, EMAC_TXD2 +static const uint8_t A2 /*ADC2_CH6 */ = + 34; //MAX 5V,GPIO34, ADC1_CH6, RTC_GPIO4 ***********************/////////////////////Connected LDR///////////////////////////// +static const uint8_t A3 /*ADC1_CH7 */ = 35; //MAX 5V,GPIO35, ADC1_CH7, RTC_GPIO5 +static const uint8_t A4 /*ADC2_CH5 */ = 15; //MAX 5V,GPIO15, ADC2_CH3, TOUCH3, MTDO, HSPICS0, RTC_GPIO13, HS2_CMD,SD_CMD, EMAC_RXD3 +static const uint8_t A5 /*ADC2_CH4 */ = 13; //MAX 5V,GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3,SD_DATA3, EMAC_RX_ER + //------------------------------------------------------------------- + +//------------------Touch Sensors------------------------------------------------- +static const uint8_t VP = 36; // GPIO36, ADC1_CH0, RTC_GPIO0 +static const uint8_t VN = 39; // GPIO39, ADC1_CH3, RTC_GPIO3 + +static const uint8_t T0 = 36; +static const uint8_t T1 = 39; + +static const uint8_t DAC1 = 25; // I/O GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0 +static const uint8_t DAC2 = 26; // I/O GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1 + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +/* Hardware HSPI */ +static const uint8_t MOSI = 13; // 13; +static const uint8_t MISO = 12; // 12; +static const uint8_t SCK = 14; // 14; +static const uint8_t SS = 15; // 15; + +/* Software VSPI [Note : D9 and D11 Do not use when display "ON or USE"]*/ +static const uint8_t VMOSI = 23; //23 /*Do not use when display "ON or USE"*/ +static const uint8_t VMISO = 19; // 19 +static const uint8_t VSCK = 18; // 18 /*Do not use when display "ON or USE"*/ +static const uint8_t VSS = 5; // 5 + +// Inbuilt Display Unit 128*128 ST7735 Driver +static const uint8_t RST = 33; // - RESET GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output),ADC1_CH5, TOUCH8, RTC_GPIO8 +static const uint8_t CLK = 18; // - (18) CLK (D11) and D9 pin will engaged when display "ON or USE" +static const uint8_t CS = 27; // - CS GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV +static const uint8_t DC = 32; //- DC/A0 GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4,TOUCH9, RTC_GPIO9 +static const uint8_t ST_MOSI = 23; // - MOSI (D9) This D9 pin will engaged when display "ON or USE" + +static const uint8_t MTDO = 15; // A4 JTAG SIGNAL -> TDO +static const uint8_t MTDI = 12; // A0 JTAG SIGNAL -> TDI +static const uint8_t MTCK = 13; // A5 JTAG SIGNAL -> TCK +static const uint8_t MTMS = 14; // A1 JTAG SIGNAL -> TMS + +#endif /* Pins_Arduino_h */ diff --git a/variants/lionbits3/pins_arduino.h b/variants/lionbits3/pins_arduino.h new file mode 100644 index 0000000..260b732 --- /dev/null +++ b/variants/lionbits3/pins_arduino.h @@ -0,0 +1,92 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 0; //GPIO0, +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SWITCH_A = 46; //GPIO46, +static const uint8_t SWITCH_B = 47; //GPIO47, +//Wifi and Bluetooth LEDs +static const uint8_t WIFI_LED = 38; +static const uint8_t BT_LED = 37; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +//------------------------------------------------------------------- +static const uint8_t U1RX = 9; //IO,GPIO9 +static const uint8_t U1TX = 10; //IO,GPIO10 +/* LionBits3 pin setup */ +static const uint8_t D0 = 3; //RX,GPIO3,MCPWM +static const uint8_t D1 = 1; //TX,GPIO1,ADC1_CH0,MCPWM +static const uint8_t D2 = 9; //IO,GPIO9,ADC1_CH8,TOUCH9,MCPWM +static const uint8_t D3 = 10; //IO,GPIO10,ADC1_CH9,TOUCH10,MCPWM +static const uint8_t D4 = 11; //IO,GPIO11,ADC2_CH0,TOUCH11,MCPWM +static const uint8_t D5 = 12; //IO,GPIO12,ADC2_CH1,TOUCH12,MCPWM +static const uint8_t D6 = 13; //IO,GPIO13,ADC2_CH2,TOUCH13,MCPWM +static const uint8_t D7 = 14; //IO,GPIO14,ADC2_CH3,TOUCH14,MCPWM +static const uint8_t D8 = 15; //IO,GPIO15,ADC2_CH4,MCPWM +static const uint8_t D9 = 16; //IO,GPIO16,ADC2_CH5,MCPWM +static const uint8_t D10 = 17; //IO,GPIO17,ADC2_CH6,MCPWM +static const uint8_t D11 = 18; //IO,GPIO18,ADC2_CH7,MCPWM +static const uint8_t D12 = 8; //IO,GPIO8,ADC1_CH7,MCPWM +static const uint8_t D13 = 39; //IO,GPIO39,MCPWM +static const uint8_t D14 = 40; //IO,GPIO40,MCPWM +static const uint8_t D15 = 41; //IO,GPIO41,MCPWM +static const uint8_t D16 = 48; //IO,GPIO48,MCPWM +static const uint8_t D17 = 21; //IO,GPIO21,MCPWM + +//Other pins. +static const uint8_t BUZZER = 21; +static const uint8_t LDR = 7; + +static const uint8_t RGBLED = 48; + +// Analog to Digital Converter (Support 5V) ADC2 pins not recommended while using Wifi +static const uint8_t A0 = 2; //IO,GPIO2,ADC1_CH1,TOUCH2,MCPWM +static const uint8_t A1 = 1; //IO,GPIO1,ADC1_CH0,TOUCH1,MCPWM +static const uint8_t A2 = 3; //IO,GPIO3,ADC1_CH2,TOUCH3,MCPWM +static const uint8_t A3 = 4; //IO,GPIO4,ADC1_CH3,TOUCH4,MCPWM +static const uint8_t A4 = 5; //IO,GPIO5,ADC1_CH4,TOUCH5,MCPWM +static const uint8_t A5 = 6; //IO,GPIO6,ADC1_CH5,TOUCH6,MCPWM +static const uint8_t A6 = 7; //IO,GPIO7,ADC1_CH6,TOUCH7,MCPWM +static const uint8_t AD1 = 7; //IO,GPIO7,ADC1_CH6,TOUCH7,MCPWM + +// Inbuilt Display Unit 128*128 ST7735 Driver New + +static const uint8_t SDA = 40; //GPIO40; +static const uint8_t SCL = 41; //GPIO41; + +/* Hardware HSPI */ +static const uint8_t MOSI = 35; //GPIO35; +static const uint8_t MISO = 37; //GPIO37; +static const uint8_t SCK = 36; //GPIO36; +static const uint8_t SS = 34; //GPIO34; +static const uint8_t SDO = 35; //GPIO35; +static const uint8_t SDI = 37; //GPIO37; +//---------------------------------- + +static const uint8_t TFT_RST = 38; //GPIO38; +static const uint8_t TFT_SCLK = 35; //GPIO35; +static const uint8_t TFT_CS = 42; //GPIO42; +static const uint8_t TFT_DC = 37; //GPIO37; +static const uint8_t TFT_MOSI = 36; //GPIO36; + +static const uint8_t LCD_A0 = 37; //GPIO37, +static const uint8_t LCD_BACK_LIGHT = 45; //GPIO45, +static const uint8_t DAC1 = 21; //GPIO21, +//LCD additional pins + +//Adafruit 128*128 ST7735 Driver New +static const uint8_t rst = 38; +static const uint8_t sclk = 35; +static const uint8_t cs = 42; +static const uint8_t dc = 37; +static const uint8_t mosi = 36; + +#define VP 36 //GPIO36, +#define VN 39 //GPIO39, + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin32-lite/pins_arduino.h b/variants/lolin32-lite/pins_arduino.h new file mode 100644 index 0000000..140d06b --- /dev/null +++ b/variants/lolin32-lite/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t LED_BUILTIN = 22; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 19; +static const uint8_t SCL = 23; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin32/pins_arduino.h b/variants/lolin32/pins_arduino.h new file mode 100644 index 0000000..12ca95c --- /dev/null +++ b/variants/lolin32/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_c3_mini/pins_arduino.h b/variants/lolin_c3_mini/pins_arduino.h new file mode 100644 index 0000000..0236f02 --- /dev/null +++ b/variants/lolin_c3_mini/pins_arduino.h @@ -0,0 +1,36 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// based on https://www.wemos.cc/en/latest/c3/c3_mini.html +// WS2812 RGB LED on pin 7 +#define PIN_RGB_LED 7 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 10; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 4; +static const uint8_t MISO = 3; +static const uint8_t SCK = 2; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_c3_pico/pins_arduino.h b/variants/lolin_c3_pico/pins_arduino.h new file mode 100644 index 0000000..781d6e6 --- /dev/null +++ b/variants/lolin_c3_pico/pins_arduino.h @@ -0,0 +1,42 @@ +// https://www.wemos.cc/en/latest/c3/c3_pico.html + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// based on https://www.wemos.cc/en/latest/c3/c3_pico.html +// WS2812 RGB LED on pin 7 +#define PIN_RGB_LED 7 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 10; + +static const uint8_t VBAT = 3; +#define BAT_VOLT_PIN VBAT + +static const uint8_t SCK = 1; +static const uint8_t MISO = 0; +static const uint8_t MOSI = 4; +static const uint8_t SS = 5; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s2_mini/pins_arduino.h b/variants/lolin_s2_mini/pins_arduino.h new file mode 100644 index 0000000..50b821a --- /dev/null +++ b/variants/lolin_s2_mini/pins_arduino.h @@ -0,0 +1,74 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Default USB Settings +#define USB_VID 0x303a +#define USB_PID 0x80C2 +#define USB_MANUFACTURER "WEMOS.CC" +#define USB_PRODUCT "LOLIN-S2-MINI" +#define USB_SERIAL "0" + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "ESP32-S2" //max 8 chars +#define USB_FW_MSC_PRODUCT_ID "Firmware MSC" //max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.23" //max 4 chars +#define USB_FW_MSC_VOLUME_NAME "S2-Firmware" //max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +static const uint8_t LED_BUILTIN = 15; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 39; +static const uint8_t RX = 37; + +static const uint8_t SDA = 33; +static const uint8_t SCL = 35; + +static const uint8_t SS = 12; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 9; +static const uint8_t SCK = 7; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s2_pico/pins_arduino.h b/variants/lolin_s2_pico/pins_arduino.h new file mode 100644 index 0000000..d98528c --- /dev/null +++ b/variants/lolin_s2_pico/pins_arduino.h @@ -0,0 +1,76 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Default USB Settings +#define USB_VID 0x303a +#define USB_PID 0x80C5 +#define USB_MANUFACTURER "WEMOS.CC" +#define USB_PRODUCT "LOLIN-S2-PICO" +#define USB_SERIAL "0" + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "ESP32-S2" //max 8 chars +#define USB_FW_MSC_PRODUCT_ID "Firmware MSC" //max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.23" //max 4 chars +#define USB_FW_MSC_VOLUME_NAME "S2-Firmware" //max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +static const uint8_t LED_BUILTIN = 10; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 38; +static const uint8_t RX = 33; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t S2_PICO_OLED_RESET = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s3/pins_arduino.h b/variants/lolin_s3/pins_arduino.h new file mode 100644 index 0000000..0c23654 --- /dev/null +++ b/variants/lolin_s3/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 38 + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 42; +static const uint8_t SCL = 41; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s3_mini/pins_arduino.h b/variants/lolin_s3_mini/pins_arduino.h new file mode 100644 index 0000000..361d323 --- /dev/null +++ b/variants/lolin_s3_mini/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x8167 + +static const uint8_t LED_BUILTIN = 47 + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 +// This board has a builtin RGB LED that works with a different signal color order +// Other order options can be found in https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/esp32-hal-rgb-led.h +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 35; +static const uint8_t SCL = 36; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s3_mini_pro/pins_arduino.h b/variants/lolin_s3_mini_pro/pins_arduino.h new file mode 100644 index 0000000..1c5f6c2 --- /dev/null +++ b/variants/lolin_s3_mini_pro/pins_arduino.h @@ -0,0 +1,77 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x8216 + +static const uint8_t LED_BUILTIN = 8 + SOC_GPIO_PIN_COUNT; +; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 5 +#define RGB_POWER 7 //RGB LED POWER PIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 11; + +static const uint8_t SS = 37; +static const uint8_t MOSI = 38; +static const uint8_t MISO = 39; +static const uint8_t SCK = 40; + +//TFT +static const uint8_t TFT_BL = 33; +static const uint8_t TFT_DC = 36; +static const uint8_t TFT_CS = 35; +static const uint8_t TFT_RST = 34; + +//IR +static const uint8_t PIN_IR = 9; + +//BUTTON +static const uint8_t BUTTON_LEFT = 0; +static const uint8_t BUTTON_OK = 47; +static const uint8_t BUTTON_RIGHT = 48; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lolin_s3_mini_pro/variant.cpp b/variants/lolin_s3_mini_pro/variant.cpp new file mode 100644 index 0000000..72b340b --- /dev/null +++ b/variants/lolin_s3_mini_pro/variant.cpp @@ -0,0 +1,31 @@ +/* + */ + +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + // IR + pinMode(PIN_IR, OUTPUT); + digitalWrite(PIN_IR, LOW); + // RGB + pinMode(RGB_POWER, OUTPUT); + digitalWrite(RGB_POWER, LOW); + // BUTTON + pinMode(BUTTON_LEFT, INPUT_PULLUP); + pinMode(BUTTON_OK, INPUT_PULLUP); + pinMode(BUTTON_RIGHT, INPUT_PULLUP); + // TFT + pinMode(TFT_BL, OUTPUT); + digitalWrite(TFT_BL, LOW); + pinMode(TFT_CS, OUTPUT); + digitalWrite(TFT_CS, HIGH); + pinMode(TFT_RST, OUTPUT); + digitalWrite(TFT_RST, LOW); + delay(1); + digitalWrite(TFT_RST, HIGH); +} +} diff --git a/variants/lolin_s3_pro/pins_arduino.h b/variants/lolin_s3_pro/pins_arduino.h new file mode 100644 index 0000000..7f2cd93 --- /dev/null +++ b/variants/lolin_s3_pro/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x8161 + +static const uint8_t LED_BUILTIN = 38 + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 9; +static const uint8_t SCL = 10; + +static const uint8_t SS = 0; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t TF_CS = 46; + +static const uint8_t TS_CS = 45; +static const uint8_t TFT_CS = 48; +static const uint8_t TFT_DC = 47; +static const uint8_t TFT_RST = 21; +static const uint8_t TFT_LED = 14; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lopy/pins_arduino.h b/variants/lopy/pins_arduino.h new file mode 100644 index 0000000..f7e2ee0 --- /dev/null +++ b/variants/lopy/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 17 // GPIO17 - SX1276 CS +#define LORA_RST 18 // GPIO18 - SX1276 RST +#define LORA_IRQ 23 // GPIO23 - SX1276 IO0 +#define LORA_IO0 LORA_IRQ // alias +#define LORA_IO1 LORA_IRQ // tied by diode to IO0 +#define LORA_IO2 LORA_IRQ // tied by diode to IO0 + +// RGB LED +#define PIN_RGB_LED 0 // ->2812 RGB !!! +static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define ANT_SELECT 16 // GPIO16 - External Antenna Switch + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SS = 17; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 37; +static const uint8_t SCK = 13; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/lopy4/pins_arduino.h b/variants/lopy4/pins_arduino.h new file mode 100644 index 0000000..eb36b30 --- /dev/null +++ b/variants/lopy4/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 18 // GPIO18 - SX1276 CS +#define LORA_IRQ 23 // GPIO23 - SX1276 IO0 +#define LORA_IO0 LORA_IRQ // alias +#define LORA_IO1 LORA_IRQ // tied by diode to IO0 +#define LORA_IO2 LORA_IRQ // tied by diode to IO0 +#define LORA_RST NOT_A_PIN + +// RGB LED +#define PIN_RGB_LED 0 // ->2812 RGB !!! +static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define ANT_SELECT 21 // GPIO21 - External Antenna Switch + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 37; +static const uint8_t SCK = 13; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_atom/pins_arduino.h b/variants/m5stack_atom/pins_arduino.h new file mode 100644 index 0000000..8a84565 --- /dev/null +++ b/variants/m5stack_atom/pins_arduino.h @@ -0,0 +1,41 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 26; +static const uint8_t SCL = 32; + +static const uint8_t G12 = 12; +static const uint8_t G19 = 19; +static const uint8_t G21 = 21; +static const uint8_t G22 = 22; +static const uint8_t G23 = 23; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G27 = 27; +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; +static const uint8_t G39 = 39; + +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G37 = 37; +static const uint8_t G36 = 36; +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +static const uint8_t SS = 19; +static const uint8_t MOSI = 33; +static const uint8_t MISO = 23; +static const uint8_t SCK = 22; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_atoms3/pins_arduino.h b/variants/m5stack_atoms3/pins_arduino.h new file mode 100644 index 0000000..739cddf --- /dev/null +++ b/variants/m5stack_atoms3/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// The board RGB led is connected to GPIO #35 +#define PIN_RGB_LED 35 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 38; +static const uint8_t SCL = 39; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 21; +static const uint8_t MISO = -1; +static const uint8_t SCK = 17; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G36 = 36; +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G42 = 42; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_capsule/pins_arduino.h b/variants/m5stack_capsule/pins_arduino.h new file mode 100644 index 0000000..0209d21 --- /dev/null +++ b/variants/m5stack_capsule/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +static const uint8_t SS = 11; +static const uint8_t MOSI = 12; +static const uint8_t MISO = 39; +static const uint8_t SCK = 14; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_cardputer/pins_arduino.h b/variants/m5stack_cardputer/pins_arduino.h new file mode 100644 index 0000000..2c50f97 --- /dev/null +++ b/variants/m5stack_cardputer/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +static const uint8_t SS = 12; +static const uint8_t MOSI = 14; +static const uint8_t MISO = 39; +static const uint8_t SCK = 40; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_core/pins_arduino.h b/variants/m5stack_core/pins_arduino.h new file mode 100644 index 0000000..cf807aa --- /dev/null +++ b/variants/m5stack_core/pins_arduino.h @@ -0,0 +1,47 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t TXD2 = 17; +static const uint8_t RXD2 = 16; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G19 = 19; +static const uint8_t G18 = 18; +static const uint8_t G3 = 3; +static const uint8_t G16 = 16; +static const uint8_t G21 = 21; +static const uint8_t G2 = 2; +static const uint8_t G12 = 12; +static const uint8_t G15 = 15; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G1 = 1; +static const uint8_t G17 = 17; +static const uint8_t G22 = 22; +static const uint8_t G5 = 5; +static const uint8_t G13 = 13; +static const uint8_t G0 = 0; +static const uint8_t G34 = 34; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_core2/pins_arduino.h b/variants/m5stack_core2/pins_arduino.h new file mode 100644 index 0000000..a4bd6bb --- /dev/null +++ b/variants/m5stack_core2/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define TX2 14 +#define RX2 13 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 38; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G38 = 38; +static const uint8_t G18 = 18; +static const uint8_t G3 = 3; +static const uint8_t G13 = 13; +static const uint8_t G21 = 21; +static const uint8_t G32 = 32; +static const uint8_t G27 = 27; +static const uint8_t G2 = 2; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G1 = 1; +static const uint8_t G14 = 14; +static const uint8_t G22 = 22; +static const uint8_t G33 = 33; +static const uint8_t G19 = 19; +static const uint8_t G0 = 0; +static const uint8_t G34 = 34; + +static const uint8_t G12 = 12; +static const uint8_t G15 = 15; +static const uint8_t G17 = 17; +static const uint8_t G5 = 5; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_coreink/pins_arduino.h b/variants/m5stack_coreink/pins_arduino.h new file mode 100644 index 0000000..5d6f3ea --- /dev/null +++ b/variants/m5stack_coreink/pins_arduino.h @@ -0,0 +1,49 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define TX2 14 +#define RX2 13 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 9; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 34; +static const uint8_t SCK = 18; + +static const uint8_t G26 = 26; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; + +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; + +static const uint8_t G21 = 21; +static const uint8_t G22 = 22; + +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; + +static const uint8_t G12 = 12; +static const uint8_t G19 = 19; + +static const uint8_t G5 = 5; +static const uint8_t G10 = 10; +static const uint8_t G2 = 2; +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G39 = 39; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_cores3/pins_arduino.h b/variants/m5stack_cores3/pins_arduino.h new file mode 100644 index 0000000..301d833 --- /dev/null +++ b/variants/m5stack_cores3/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 17; +static const uint8_t RXD2 = 18; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 11; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 37; +static const uint8_t MISO = 35; +static const uint8_t SCK = 36; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G17 = 17; +static const uint8_t G18 = 18; +static const uint8_t G19 = 19; +static const uint8_t G20 = 20; +static const uint8_t G21 = 21; +static const uint8_t G33 = 33; +static const uint8_t G34 = 34; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G45 = 45; +static const uint8_t G46 = 46; + +static const uint8_t ADC = 10; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_dial/pins_arduino.h b/variants/m5stack_dial/pins_arduino.h new file mode 100644 index 0000000..2c50f97 --- /dev/null +++ b/variants/m5stack_dial/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +static const uint8_t SS = 12; +static const uint8_t MOSI = 14; +static const uint8_t MISO = 39; +static const uint8_t SCK = 40; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_dinmeter/pins_arduino.h b/variants/m5stack_dinmeter/pins_arduino.h new file mode 100644 index 0000000..2c50f97 --- /dev/null +++ b/variants/m5stack_dinmeter/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +static const uint8_t SS = 12; +static const uint8_t MOSI = 14; +static const uint8_t MISO = 39; +static const uint8_t SCK = 40; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_fire/pins_arduino.h b/variants/m5stack_fire/pins_arduino.h new file mode 100644 index 0000000..2202e6b --- /dev/null +++ b/variants/m5stack_fire/pins_arduino.h @@ -0,0 +1,44 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 4; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G19 = 19; +static const uint8_t G18 = 18; +static const uint8_t G3 = 3; +static const uint8_t G16 = 16; +static const uint8_t G21 = 21; +static const uint8_t G2 = 2; +static const uint8_t G12 = 12; +static const uint8_t G15 = 15; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G1 = 1; +static const uint8_t G17 = 17; +static const uint8_t G22 = 22; +static const uint8_t G5 = 5; +static const uint8_t G13 = 13; +static const uint8_t G0 = 0; +static const uint8_t G34 = 34; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_nanoc6/pins_arduino.h b/variants/m5stack_nanoc6/pins_arduino.h new file mode 100644 index 0000000..8f16e0a --- /dev/null +++ b/variants/m5stack_nanoc6/pins_arduino.h @@ -0,0 +1,45 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 +#define USB_MANUFACTURER "M5Stack" +#define USB_PRODUCT "NanoC6" +#define USB_SERIAL "" + +static const uint8_t LED_BUILTIN = 7; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 2; +static const uint8_t SCL = 1; + +static const uint8_t SS = 4; // Not connected +static const uint8_t MOSI = 5; // Not connected +static const uint8_t MISO = 6; // Not connected +static const uint8_t SCK = 8; // Not connected + +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 7; +static const uint8_t D5 = 8; +static const uint8_t D6 = 9; + +static const uint8_t BLUE_LED_PIN = 7; +static const uint8_t BTN_PIN = 9; +static const uint8_t IR_TX_PIN = 3; +static const uint8_t RGB_LED_PWR_PIN = 19; +static const uint8_t RGB_LED_DATA_PIN = 20; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_paper/pins_arduino.h b/variants/m5stack_paper/pins_arduino.h new file mode 100644 index 0000000..02ccc73 --- /dev/null +++ b/variants/m5stack_paper/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define TX2 14 +#define RX2 13 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 25; +static const uint8_t SCL = 32; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 12; +static const uint8_t MISO = 13; +static const uint8_t SCK = 14; + +static const uint8_t G25 = 25; +static const uint8_t G32 = 32; + +static const uint8_t G26 = 26; +static const uint8_t G33 = 33; + +static const uint8_t G18 = 18; +static const uint8_t G19 = 19; + +static const uint8_t G21 = 21; +static const uint8_t G22 = 22; + +static const uint8_t G36 = 36; +static const uint8_t G2 = 2; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G23 = 23; + +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G39 = 39; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_poe_cam/pins_arduino.h b/variants/m5stack_poe_cam/pins_arduino.h new file mode 100644 index 0000000..9ae9b23 --- /dev/null +++ b/variants/m5stack_poe_cam/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 25; +static const uint8_t SCL = 33; + +// Modified elsewhere +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t MISO = -1; +static const uint8_t SCK = -1; + +static const uint8_t G23 = 23; +static const uint8_t G25 = 25; +static const uint8_t G27 = 27; +static const uint8_t G22 = 22; +static const uint8_t G26 = 26; +static const uint8_t G21 = 21; +static const uint8_t G32 = 32; +static const uint8_t G35 = 35; +static const uint8_t G34 = 34; +static const uint8_t G5 = 5; +static const uint8_t G39 = 39; +static const uint8_t G18 = 18; +static const uint8_t G36 = 36; +static const uint8_t G19 = 19; +static const uint8_t G15 = 15; + +static const uint8_t G2 = 2; +static const uint8_t G33 = 33; + +static const uint8_t G13 = 13; +static const uint8_t G4 = 4; + +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stamp_c3/pins_arduino.h b/variants/m5stack_stamp_c3/pins_arduino.h new file mode 100644 index 0000000..629fc1b --- /dev/null +++ b/variants/m5stack_stamp_c3/pins_arduino.h @@ -0,0 +1,24 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stamp_pico/pins_arduino.h b/variants/m5stack_stamp_pico/pins_arduino.h new file mode 100644 index 0000000..37a17ff --- /dev/null +++ b/variants/m5stack_stamp_pico/pins_arduino.h @@ -0,0 +1,31 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 19; +static const uint8_t MOSI = 26; +static const uint8_t MISO = 36; +static const uint8_t SCK = 18; + +static const uint8_t G26 = 26; +static const uint8_t G36 = 36; +static const uint8_t G18 = 18; +static const uint8_t G19 = 19; +static const uint8_t G21 = 21; +static const uint8_t G22 = 22; +static const uint8_t G25 = 25; +static const uint8_t G1 = 1; +static const uint8_t G3 = 3; +static const uint8_t G0 = 0; + +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stamp_s3/pins_arduino.h b/variants/m5stack_stamp_s3/pins_arduino.h new file mode 100644 index 0000000..595da52 --- /dev/null +++ b/variants/m5stack_stamp_s3/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +// Modified elsewhere +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t MISO = -1; +static const uint8_t SCK = -1; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_station/pins_arduino.h b/variants/m5stack_station/pins_arduino.h new file mode 100644 index 0000000..d8285fe --- /dev/null +++ b/variants/m5stack_station/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t TXD1 = 14; +static const uint8_t RXD1 = 13; + +static const uint8_t TXD2 = 17; +static const uint8_t RXD2 = 16; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = -1; +static const uint8_t SCK = 18; + +static const uint8_t G1 = 1; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G16 = 16; +static const uint8_t G17 = 17; +static const uint8_t G18 = 18; +static const uint8_t G19 = 19; +static const uint8_t G23 = 23; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G37 = 37; +static const uint8_t G38 = 38; +static const uint8_t G39 = 39; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stickc/pins_arduino.h b/variants/m5stack_stickc/pins_arduino.h new file mode 100644 index 0000000..1948afc --- /dev/null +++ b/variants/m5stack_stickc/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 36; +static const uint8_t SCK = 13; + +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G37 = 37; +static const uint8_t G39 = 39; +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; +static const uint8_t G26 = 26; +static const uint8_t G36 = 36; +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stickc_plus/pins_arduino.h b/variants/m5stack_stickc_plus/pins_arduino.h new file mode 100644 index 0000000..1948afc --- /dev/null +++ b/variants/m5stack_stickc_plus/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 36; +static const uint8_t SCK = 13; + +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G37 = 37; +static const uint8_t G39 = 39; +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; +static const uint8_t G26 = 26; +static const uint8_t G36 = 36; +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_stickc_plus2/pins_arduino.h b/variants/m5stack_stickc_plus2/pins_arduino.h new file mode 100644 index 0000000..1948afc --- /dev/null +++ b/variants/m5stack_stickc_plus2/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 36; +static const uint8_t SCK = 13; + +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G37 = 37; +static const uint8_t G39 = 39; +static const uint8_t G32 = 32; +static const uint8_t G33 = 33; +static const uint8_t G26 = 26; +static const uint8_t G36 = 36; +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_tab5/pins_arduino.h b/variants/m5stack_tab5/pins_arduino.h new file mode 100644 index 0000000..9f91ef7 --- /dev/null +++ b/variants/m5stack_tab5/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BOOT_MODE 35 +// BOOT_MODE2 36 pullup + +static const uint8_t TX = 37; +static const uint8_t RX = 38; + +static const uint8_t SDA = 53; +static const uint8_t SCL = 54; + +// Use GPIOs 36 or lower on the P4 DevKit to avoid LDO power issues with high numbered GPIOs. +static const uint8_t SS = 26; +static const uint8_t MOSI = 32; +static const uint8_t MISO = 33; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 16; +static const uint8_t A1 = 17; +static const uint8_t A2 = 18; +static const uint8_t A3 = 19; +static const uint8_t A4 = 20; +static const uint8_t A5 = 21; +static const uint8_t A6 = 22; +static const uint8_t A7 = 23; +static const uint8_t A8 = 49; +static const uint8_t A9 = 50; +static const uint8_t A10 = 51; +static const uint8_t A11 = 52; +static const uint8_t A12 = 53; +static const uint8_t A13 = 54; + +static const uint8_t T0 = 2; +static const uint8_t T1 = 3; +static const uint8_t T2 = 4; +static const uint8_t T3 = 5; +static const uint8_t T4 = 6; +static const uint8_t T5 = 7; +static const uint8_t T6 = 8; +static const uint8_t T7 = 9; +static const uint8_t T8 = 10; +static const uint8_t T9 = 11; +static const uint8_t T10 = 12; +static const uint8_t T11 = 13; +static const uint8_t T12 = 14; +static const uint8_t T13 = 15; + +//SDMMC +#define BOARD_HAS_SDMMC +#define BOARD_SDMMC_SLOT 0 + +//WIFI - ESP32C6 +#define BOARD_HAS_SDIO_ESP_HOSTED +#define BOARD_SDIO_ESP_HOSTED_CLK 12 +#define BOARD_SDIO_ESP_HOSTED_CMD 13 +#define BOARD_SDIO_ESP_HOSTED_D0 11 +#define BOARD_SDIO_ESP_HOSTED_D1 10 +#define BOARD_SDIO_ESP_HOSTED_D2 9 +#define BOARD_SDIO_ESP_HOSTED_D3 8 +#define BOARD_SDIO_ESP_HOSTED_RESET 15 + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_timer_cam/pins_arduino.h b/variants/m5stack_timer_cam/pins_arduino.h new file mode 100644 index 0000000..8c11964 --- /dev/null +++ b/variants/m5stack_timer_cam/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 13; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G25 = 25; +static const uint8_t G27 = 27; +static const uint8_t G22 = 22; +static const uint8_t G26 = 26; +static const uint8_t G21 = 21; +static const uint8_t G32 = 32; +static const uint8_t G35 = 35; +static const uint8_t G34 = 34; +static const uint8_t G5 = 5; +static const uint8_t G39 = 39; +static const uint8_t G18 = 18; +static const uint8_t G36 = 36; +static const uint8_t G19 = 19; +static const uint8_t G15 = 15; + +static const uint8_t G2 = 2; +static const uint8_t G33 = 33; + +static const uint8_t G13 = 13; +static const uint8_t G4 = 4; + +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_tough/pins_arduino.h b/variants/m5stack_tough/pins_arduino.h new file mode 100644 index 0000000..f9d5b8c --- /dev/null +++ b/variants/m5stack_tough/pins_arduino.h @@ -0,0 +1,49 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 32; +static const uint8_t SCL = 33; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 38; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G38 = 38; +static const uint8_t G18 = 18; +static const uint8_t G3 = 3; +static const uint8_t G13 = 13; +static const uint8_t G21 = 21; +static const uint8_t G32 = 32; +static const uint8_t G27 = 27; +static const uint8_t G2 = 2; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G1 = 1; +static const uint8_t G14 = 14; +static const uint8_t G22 = 22; +static const uint8_t G33 = 33; +static const uint8_t G19 = 19; +static const uint8_t G0 = 0; +static const uint8_t G34 = 34; + +static const uint8_t G12 = 12; +static const uint8_t G15 = 15; +static const uint8_t G17 = 17; +static const uint8_t G5 = 5; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_unit_cam/pins_arduino.h b/variants/m5stack_unit_cam/pins_arduino.h new file mode 100644 index 0000000..453e1c4 --- /dev/null +++ b/variants/m5stack_unit_cam/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 17; +static const uint8_t SCL = 16; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G25 = 25; +static const uint8_t G27 = 27; +static const uint8_t G22 = 22; +static const uint8_t G26 = 26; +static const uint8_t G21 = 21; +static const uint8_t G32 = 32; +static const uint8_t G35 = 35; +static const uint8_t G34 = 34; +static const uint8_t G5 = 5; +static const uint8_t G39 = 39; +static const uint8_t G18 = 18; +static const uint8_t G36 = 36; +static const uint8_t G19 = 19; +static const uint8_t G15 = 15; + +static const uint8_t G2 = 2; +static const uint8_t G33 = 33; + +static const uint8_t G13 = 13; +static const uint8_t G4 = 4; + +static const uint8_t G0 = 0; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/m5stack_unit_cams3/pins_arduino.h b/variants/m5stack_unit_cams3/pins_arduino.h new file mode 100644 index 0000000..595da52 --- /dev/null +++ b/variants/m5stack_unit_cams3/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TXD2 = 1; +static const uint8_t RXD2 = 2; + +static const uint8_t SDA = 13; +static const uint8_t SCL = 15; + +// Modified elsewhere +static const uint8_t SS = -1; +static const uint8_t MOSI = -1; +static const uint8_t MISO = -1; +static const uint8_t SCK = -1; + +static const uint8_t G0 = 0; +static const uint8_t G1 = 1; +static const uint8_t G2 = 2; +static const uint8_t G3 = 3; +static const uint8_t G4 = 4; +static const uint8_t G5 = 5; +static const uint8_t G6 = 6; +static const uint8_t G7 = 7; +static const uint8_t G8 = 8; +static const uint8_t G9 = 9; +static const uint8_t G10 = 10; +static const uint8_t G11 = 11; +static const uint8_t G12 = 12; +static const uint8_t G13 = 13; +static const uint8_t G14 = 14; +static const uint8_t G15 = 15; +static const uint8_t G39 = 39; +static const uint8_t G40 = 40; +static const uint8_t G41 = 41; +static const uint8_t G42 = 42; +static const uint8_t G43 = 43; +static const uint8_t G44 = 44; +static const uint8_t G46 = 46; + +static const uint8_t ADC1 = 7; +static const uint8_t ADC2 = 8; + +#endif /* Pins_Arduino_h */ diff --git a/variants/magicbit/pins_arduino.h b/variants/magicbit/pins_arduino.h new file mode 100644 index 0000000..093cfcc --- /dev/null +++ b/variants/magicbit/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t BUZZER = 25; +static const uint8_t RED_LED = 27; +static const uint8_t YELLOW_LED = 18; +static const uint8_t GREEN_LED = 16; +static const uint8_t BLUE_LED = 17; +static const uint8_t LDR = 36; +static const uint8_t POT = 39; +static const uint8_t RIGHT_PUTTON = 34; +static const uint8_t LEFT_BUTTON = 35; +static const uint8_t MOTOR1A = 27; +static const uint8_t MOTOR1B = 18; +static const uint8_t MOTOR2A = 16; +static const uint8_t MOTOR2B = 17; + +static const uint8_t LED_BUILTIN = 16; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#endif /* Pins_Arduino_h */ diff --git a/variants/makergo_c3_supermini/pins_arduino.h b/variants/makergo_c3_supermini/pins_arduino.h new file mode 100644 index 0000000..349e248 --- /dev/null +++ b/variants/makergo_c3_supermini/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define TX1 0 +#define RX1 1 + +static const uint8_t LED_BUILTIN = 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BOOT_BUILTIN = 9; // built-in boot button + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/makergo_c6_supermini/pins_arduino.h b/variants/makergo_c6_supermini/pins_arduino.h new file mode 100644 index 0000000..fb801ed --- /dev/null +++ b/variants/makergo_c6_supermini/pins_arduino.h @@ -0,0 +1,101 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" +/* + Arduino Pin Definitions for MakerGO ESP32 C6 SuperMini + +-----------------------------------------------------------------------------+ + | | | | # | | USB | | # | | | | + |:---:|:-------:|:------:|:--:|:--:|:---:|:--:|:--:|:--------:|:-------:|:---:| + | D16 | TX | GPIO16 | 1 | | TOP | | 20 | 5V | | | + | D17 | RX | GPIO17 | 2 | | | | 19 | GND | | | + | D0 | A0 | GPIO0 | 3 | | | | 18 | 3V3(OUT) | | | + | D1 | A1 | GPIO1 | 4 | | | | 17 | GPIO20 | SDA | D14 | + | D2 | A2 | GPIO2 | 5 | | | | 16 | GPIO19 | SCL | D12 | + | D3 | A3 | GPIO3 | 6 | | | | 15 | GPIO18 | | D11 | + | D4 | SS/A4 | GPIO4 | 7 | | 21 | | 14 | GPIO15 | LED | D13 | + | D5 | MOSI/A5 | GPIO5 | 8 | 23 | 22 | | 13 | GPIO14 | | D10 | + | D6 | MISO/A6 | GPIO6 | 9 | | | 24 | 12 | GPIO9 | BOOT | D9 | + | D7 | SCK | GPIO7 | 10 | | | 25 | 11 | GPIO8 | RGB_LED | D8 | + | | | | | | ↑ | | | | | | + +----------------------------------- | -------------------------------------+ + | + | | | | # | | | | | # | | | | + |:---:|:-------:|:------:|:--:|:--:|:---:|:--:|:--:|:--------:|:-------:|:---:| + | D19 | | GPIO21 | 21 | | | | | | | | + | D20 | | GPIO22 | 22 | | | | 24 | GPIO12 | | D15 | + | D21 | | GPIO23 | 23 | | | | 25 | GPIO13 | | D18 | + +-----------------------------------------------------------------------------+ +*/ +// The built-in RGB LED is connected to this pin +static const uint8_t PIN_RGB_LED = 8; +#define PIN_RGB_LED PIN_RGB_LED // allow testing #ifdef PIN_RGB_LED + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +// but also used in new Arduino API rgbLedWrite() +static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define RGB_BUILTIN RGB_BUILTIN // allow testing #ifdef RGB_BUILTIN + +// Define default brightness for the built-in RGB LED +#define RGB_BRIGHTNESS 32 // default brightness level (0-255) + +// Define the color order for the built-in RGB LED +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_GRB // default WS2812B color order + +// Define the built-in LED pin (blue LED) +static const uint8_t LED_BUILTIN = 15; +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 20; +static const uint8_t SCL = 19; + +static const uint8_t SS = 4; +static const uint8_t MOSI = 5; +static const uint8_t MISO = 6; +static const uint8_t SCK = 7; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; // Note: A4 overlaps with SS +static const uint8_t A5 = 5; // Note: A5 overlaps with MOSI +static const uint8_t A6 = 6; // Note: A6 overlaps with MISO or SDA1 + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; // Note: D4 overlaps with SS +static const uint8_t D5 = 5; // Note: D5 overlaps with MOSI +static const uint8_t D6 = 6; // Note: D6 overlaps with MISO or SDA1 +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; // Note: D8 overlaps with PIN_RGB_LED +static const uint8_t D9 = 9; +static const uint8_t D10 = 14; +static const uint8_t D11 = 18; +static const uint8_t D12 = 19; // Note: D12 overlaps with SCL +static const uint8_t D13 = 15; // Note: D13 overlaps with LED_BUILTIN +static const uint8_t D14 = 20; // Note: D14 overlaps with SDA +static const uint8_t D15 = 12; +static const uint8_t D16 = 16; // Note: D16 overlaps with TX +static const uint8_t D17 = 17; // Note: D17 overlaps with RX +static const uint8_t D18 = 13; +static const uint8_t D19 = 21; +static const uint8_t D20 = 22; +static const uint8_t D21 = 23; + +// LP I2C Pins are fixed on ESP32-C6 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define BUILTIN_RGB RGB_BUILTIN // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/mant1s/pins_arduino.h b/variants/mant1s/pins_arduino.h new file mode 100644 index 0000000..b0b7e54 --- /dev/null +++ b/variants/mant1s/pins_arduino.h @@ -0,0 +1,38 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SCL = 32; +static const uint8_t SDA = 33; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; + +#define ETH_PHY_ADDR 0 +#define ETH_PHY_POWER -1 +#define ETH_PHY_MDC 8 +#define ETH_PHY_MDIO 7 +#define ETH_PHY_TYPE ETH_PHY_LAN867X +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN + +#endif /* Pins_Arduino_h */ diff --git a/variants/metro_esp-32/pins_arduino.h b/variants/metro_esp-32/pins_arduino.h new file mode 100644 index 0000000..675ea79 --- /dev/null +++ b/variants/metro_esp-32/pins_arduino.h @@ -0,0 +1,22 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t ADR = 12; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/mgbot-iotik32a/pins_arduino.h b/variants/mgbot-iotik32a/pins_arduino.h new file mode 100644 index 0000000..10d1033 --- /dev/null +++ b/variants/mgbot-iotik32a/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 4; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +#define TXD TX +#define RXD RX + +static const uint8_t TX2 = 17; +static const uint8_t RX2 = 16; +#define TXD2 TX2 +#define RXD2 RX2 + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/mgbot-iotik32b/pins_arduino.h b/variants/mgbot-iotik32b/pins_arduino.h new file mode 100644 index 0000000..05678e7 --- /dev/null +++ b/variants/mgbot-iotik32b/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 18; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// IR receiver +static const uint8_t IR = 27; +#define IR_RECV IR +#define IR_INPUT IR + +static const uint8_t TX = 1; +static const uint8_t RX = 3; +#define TXD TX +#define RXD RX + +static const uint8_t TX2 = 17; +static const uint8_t RX2 = 16; +#define TXD2 TX2 +#define RXD2 RX2 + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/mhetesp32devkit/pins_arduino.h b/variants/mhetesp32devkit/pins_arduino.h new file mode 100644 index 0000000..8e1d004 --- /dev/null +++ b/variants/mhetesp32devkit/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/mhetesp32minikit/pins_arduino.h b/variants/mhetesp32minikit/pins_arduino.h new file mode 100644 index 0000000..8e1d004 --- /dev/null +++ b/variants/mhetesp32minikit/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/micro_s2/pins_arduino.h b/variants/micro_s2/pins_arduino.h new file mode 100644 index 0000000..4227994 --- /dev/null +++ b/variants/micro_s2/pins_arduino.h @@ -0,0 +1,75 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x239A +#define USB_PID 0x80C5 +#define USB_MANUFACTURER "microDev" +#define USB_PRODUCT "microS2" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t PIXEL_BUILTIN = 33; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (PIXEL_BUILTIN + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t BUTTON_BUILTIN = 0; + +#endif /* Pins_Arduino_h */ diff --git a/variants/mpython/pins_arduino.h b/variants/mpython/pins_arduino.h new file mode 100644 index 0000000..98994e6 --- /dev/null +++ b/variants/mpython/pins_arduino.h @@ -0,0 +1,80 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t P0 = 33; +static const uint8_t P1 = 32; +static const uint8_t P2 = 35; +static const uint8_t P3 = 34; +static const uint8_t P4 = 39; +static const uint8_t P5 = 0; +static const uint8_t P6 = 16; +static const uint8_t P7 = 17; +static const uint8_t P8 = 26; +static const uint8_t P9 = 25; +static const uint8_t P10 = 36; +static const uint8_t P11 = 2; +static const uint8_t P13 = 18; +static const uint8_t P14 = 19; +static const uint8_t P15 = 21; +static const uint8_t P16 = 5; +static const uint8_t P19 = 22; +static const uint8_t P20 = 23; + +static const uint8_t P = 27; +static const uint8_t Y = 14; +static const uint8_t T = 12; +static const uint8_t H = 13; +static const uint8_t O = 15; +static const uint8_t N = 4; + +static const uint8_t BTN_A = 0; +static const uint8_t BTN_B = 2; +static const uint8_t SOUND = 36; +static const uint8_t LIGHT = 39; +static const uint8_t BUZZER = 16; + +#endif /* Pins_Arduino_h */ diff --git a/variants/namino_arancio/pins_arduino.h b/variants/namino_arancio/pins_arduino.h new file mode 100644 index 0000000..78000a4 --- /dev/null +++ b/variants/namino_arancio/pins_arduino.h @@ -0,0 +1,197 @@ +// +// Copyright (c) 2023 Namino Team, version: 1.0.20 @ 2023-10-06 +// +// +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define NAMINO_ARANCIO_BOARD + +/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t GPIO4 = 4; +static const uint8_t GPIO5 = 5; +static const uint8_t GPIO6 = 6; +static const uint8_t GPIO7 = 7; +static const uint8_t GPIO15 = 15; +static const uint8_t GPIO16 = 16; +static const uint8_t GPIO17 = 17; +static const uint8_t GPIO18 = 18; +static const uint8_t GPIO8 = 8; +static const uint8_t GPIO19 = 19; +static const uint8_t GPIO20 = 20; +static const uint8_t GPIO3 = 3; +static const uint8_t GPIO46 = 46; +static const uint8_t GPIO9 = 9; +static const uint8_t GPIO10 = 10; +static const uint8_t GPIO11 = 11; +static const uint8_t GPIO12 = 12; +static const uint8_t GPIO13 = 13; +static const uint8_t GPIO14 = 14; +static const uint8_t GPIO21 = 21; +static const uint8_t GPIO47 = 47; +static const uint8_t GPIO48 = 48; +static const uint8_t GPIO45 = 45; +static const uint8_t GPIO0 = 0; +static const uint8_t GPIO35 = 35; +static const uint8_t GPIO36 = 36; +static const uint8_t GPIO37 = 37; +static const uint8_t GPIO38 = 38; +static const uint8_t GPIO39 = 39; +static const uint8_t GPIO40 = 40; +static const uint8_t GPIO41 = 41; +static const uint8_t GPIO42 = 42; +static const uint8_t GPIO44 = 44; +static const uint8_t GPIO43 = 43; +static const uint8_t GPIO2 = 2; +static const uint8_t GPIO1 = 1; + +static const uint8_t RESET_ADD_ON = GPIO46; +static const uint8_t SS = GPIO10; +static const uint8_t MOSI = GPIO11; +static const uint8_t MISO = GPIO13; +static const uint8_t SCK = GPIO12; +// SPI SD CARD +static const uint8_t CS_SDCARD = GPIO2; +// prog pins +static const uint8_t BOOT_MODE = GPIO47; +static const uint8_t ISP_TX = GPIO17; +static const uint8_t ISP_RX = GPIO18; +static const uint8_t NM_RESET = GPIO48; +/* End Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t ADC1_CH3 = GPIO4; +static const uint8_t ADC1_CH4 = GPIO5; +static const uint8_t ADC1_CH5 = GPIO6; +static const uint8_t ADC1_CH6 = GPIO7; +static const uint8_t ADC2_CH4 = GPIO15; +static const uint8_t ADC2_CH5 = GPIO16; +static const uint8_t ADC2_CH6 = GPIO17; +static const uint8_t ADC2_CH7 = GPIO18; +static const uint8_t ADC1_CH7 = GPIO8; +static const uint8_t ADC2_CH8 = GPIO19; +static const uint8_t ADC2_CH9 = GPIO20; +static const uint8_t ADC1_CH2 = GPIO3; +static const uint8_t ADC1_CH8 = GPIO9; +static const uint8_t ADC1_CH9 = GPIO10; +static const uint8_t ADC2_CH0 = GPIO11; +static const uint8_t ADC2_CH1 = GPIO12; +static const uint8_t ADC2_CH2 = GPIO13; +static const uint8_t ADC2_CH3 = GPIO14; +static const uint8_t ADC1_CH1 = GPIO2; +static const uint8_t ADC1_CH0 = GPIO1; +/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t TOUCH4 = GPIO4; +static const uint8_t TOUCH5 = GPIO5; +static const uint8_t TOUCH6 = GPIO6; +static const uint8_t TOUCH7 = GPIO7; +static const uint8_t TOUCH8 = GPIO8; +static const uint8_t TOUCH3 = GPIO3; +static const uint8_t TOUCH9 = GPIO9; +static const uint8_t TOUCH10 = GPIO10; +static const uint8_t TOUCH11 = GPIO11; +static const uint8_t TOUCH12 = GPIO12; +static const uint8_t TOUCH13 = GPIO13; +static const uint8_t TOUCH14 = GPIO14; +static const uint8_t TOUCH2 = GPIO2; +static const uint8_t TOUCH1 = GPIO1; +/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ + +static const uint8_t TX = GPIO17; +static const uint8_t RX = GPIO18; + +static const uint8_t SDA = GPIO1; +static const uint8_t SCL = GPIO0; +static const uint8_t NAMINO_ARANCIO_I2C_SDA = SDA; +static const uint8_t NAMINO_ARANCIO_I2C_SCL = SCL; +static const uint8_t NM_I2C_SDA = SDA; +static const uint8_t NM_I2C_SCL = SCL; + +static const uint8_t A0 = ADC1_CH0; +static const uint8_t A1 = ADC1_CH1; +static const uint8_t A2 = ADC1_CH2; +static const uint8_t A3 = ADC1_CH3; +static const uint8_t A4 = ADC1_CH4; +static const uint8_t A5 = ADC1_CH5; +static const uint8_t A6 = ADC1_CH6; +static const uint8_t A7 = ADC1_CH7; +static const uint8_t A8 = ADC2_CH0; +static const uint8_t A9 = ADC2_CH1; +static const uint8_t A10 = ADC2_CH2; +static const uint8_t A11 = ADC2_CH3; +static const uint8_t A12 = ADC2_CH4; +static const uint8_t A13 = ADC2_CH5; +static const uint8_t A14 = ADC2_CH6; +static const uint8_t A15 = ADC2_CH7; + +static const uint8_t DAC1 = 0; +static const uint8_t DAC2 = 0; + +/* Begin Arduino naming */ +static const uint8_t RESET_ARDUINO = GPIO46; +static const uint8_t PC0 = GPIO3; +static const uint8_t PC1 = GPIO4; +static const uint8_t PC2 = GPIO5; +static const uint8_t PC3 = GPIO6; +static const uint8_t PC4 = GPIO7; +static const uint8_t PC5 = GPIO8; +static const uint8_t PB5 = GPIO35; +static const uint8_t PB4 = GPIO36; +static const uint8_t PB3 = GPIO37; +static const uint8_t PB2 = GPIO38; +static const uint8_t PB1 = GPIO39; +static const uint8_t PB0 = GPIO40; +static const uint8_t PD7 = GPIO41; +static const uint8_t PD6 = GPIO42; +static const uint8_t PD5 = GPIO21; +static const uint8_t PD4 = GPIO16; +static const uint8_t PD3 = GPIO14; +static const uint8_t PD2 = GPIO9; +static const uint8_t PD1 = GPIO17; +static const uint8_t PD0 = GPIO18; +/* End Arduino naming */ + +/* Begin alternate naming */ +static const uint8_t J1_io0 = SCL; + +static const uint8_t J2_35 = PB5; +static const uint8_t J2_36 = PB4; +static const uint8_t J2_37 = PB3; +static const uint8_t J2_38 = PB2; +static const uint8_t J2_39 = PB1; +static const uint8_t J2_40 = PB0; + +static const uint8_t J3_io8 = PD7; +static const uint8_t J3_7 = PD6; +static const uint8_t J3_21 = PD5; +static const uint8_t J3_16 = PD4; +static const uint8_t J3_14 = PD3; +static const uint8_t J3_9 = PD2; +static const uint8_t J3_17 = TX; +static const uint8_t J3_18 = RX; + +static const uint8_t J4_cs_io2 = CS_SDCARD; +static const uint8_t J4_sclk = SCK; +static const uint8_t J4_mosi = MOSI; +static const uint8_t J4_miso = MISO; + +static const uint8_t J9_io3 = PC0; +static const uint8_t J9_4 = PC1; +static const uint8_t J9_5 = PC2; +static const uint8_t J9_6 = PC3; +static const uint8_t J9_7 = PC4; +static const uint8_t J9_8 = PC5; + +static const uint8_t J10_enc_A = 0; +static const uint8_t J10_enc_B = 0; +static const uint8_t J10_sw = 0; +/* End alternate naming */ + +#endif /* Pins_Arduino_h */ diff --git a/variants/namino_bianco/pins_arduino.h b/variants/namino_bianco/pins_arduino.h new file mode 100644 index 0000000..48c9449 --- /dev/null +++ b/variants/namino_bianco/pins_arduino.h @@ -0,0 +1,197 @@ +// +// Copyright (c) 2023 Namino Team, bianco version: 1.0.1 @ 2023-10-06 +// +// +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define NAMINO_BIANCO_BOARD + +/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t GPIO4 = 4; +static const uint8_t GPIO5 = 5; +static const uint8_t GPIO6 = 6; +static const uint8_t GPIO7 = 7; +static const uint8_t GPIO15 = 15; +static const uint8_t GPIO16 = 16; +static const uint8_t GPIO17 = 17; +static const uint8_t GPIO18 = 18; +static const uint8_t GPIO8 = 8; +static const uint8_t GPIO19 = 19; +static const uint8_t GPIO20 = 20; +static const uint8_t GPIO3 = 3; +static const uint8_t GPIO46 = 46; +static const uint8_t GPIO9 = 9; +static const uint8_t GPIO10 = 10; +static const uint8_t GPIO11 = 11; +static const uint8_t GPIO12 = 12; +static const uint8_t GPIO13 = 13; +static const uint8_t GPIO14 = 14; +static const uint8_t GPIO21 = 21; +static const uint8_t GPIO47 = 47; +static const uint8_t GPIO48 = 48; +static const uint8_t GPIO45 = 45; +static const uint8_t GPIO0 = 0; +static const uint8_t GPIO35 = 35; +static const uint8_t GPIO36 = 36; +static const uint8_t GPIO37 = 37; +static const uint8_t GPIO38 = 38; +static const uint8_t GPIO39 = 39; +static const uint8_t GPIO40 = 40; +static const uint8_t GPIO41 = 41; +static const uint8_t GPIO42 = 42; +static const uint8_t GPIO44 = 44; +static const uint8_t GPIO43 = 43; +static const uint8_t GPIO2 = 2; +static const uint8_t GPIO1 = 1; + +static const uint8_t SS = GPIO48; +static const uint8_t MOSI = GPIO11; +static const uint8_t MISO = GPIO13; +static const uint8_t SCK = GPIO12; + +/* End Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t ADC1_CH3 = GPIO4; +static const uint8_t ADC1_CH4 = GPIO5; +static const uint8_t ADC1_CH5 = GPIO6; +static const uint8_t ADC1_CH6 = GPIO7; +static const uint8_t ADC2_CH4 = GPIO15; +static const uint8_t ADC2_CH5 = GPIO16; +static const uint8_t ADC2_CH6 = GPIO17; +static const uint8_t ADC2_CH7 = GPIO18; +static const uint8_t ADC1_CH7 = GPIO8; +static const uint8_t ADC2_CH8 = GPIO19; +static const uint8_t ADC2_CH9 = GPIO20; +static const uint8_t ADC1_CH2 = GPIO3; +static const uint8_t ADC1_CH8 = GPIO9; +static const uint8_t ADC1_CH9 = GPIO10; +static const uint8_t ADC2_CH0 = GPIO11; +static const uint8_t ADC2_CH1 = GPIO12; +static const uint8_t ADC2_CH2 = GPIO13; +static const uint8_t ADC2_CH3 = GPIO14; +static const uint8_t ADC1_CH1 = GPIO2; +static const uint8_t ADC1_CH0 = GPIO1; +/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t TOUCH4 = GPIO4; +static const uint8_t TOUCH5 = GPIO5; +static const uint8_t TOUCH6 = GPIO6; +static const uint8_t TOUCH7 = GPIO7; +static const uint8_t TOUCH8 = GPIO8; +static const uint8_t TOUCH3 = GPIO3; +static const uint8_t TOUCH9 = GPIO9; +static const uint8_t TOUCH10 = GPIO10; +static const uint8_t TOUCH11 = GPIO11; +static const uint8_t TOUCH12 = GPIO12; +static const uint8_t TOUCH13 = GPIO13; +static const uint8_t TOUCH14 = GPIO14; +static const uint8_t TOUCH2 = GPIO2; +static const uint8_t TOUCH1 = GPIO1; +/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ + +static const uint8_t TX = GPIO17; +static const uint8_t RX = GPIO18; + +static const uint8_t SDA = GPIO1; +static const uint8_t SCL = GPIO2; +static const uint8_t NM_I2C_SDA = SDA; +static const uint8_t NM_I2C_SCL = SCL; + +static const uint8_t A0 = ADC1_CH2; +static const uint8_t A1 = ADC1_CH3; +static const uint8_t A2 = ADC1_CH4; +static const uint8_t A3 = ADC1_CH5; +static const uint8_t A4 = ADC1_CH6; +static const uint8_t A5 = ADC2_CH4; +static const uint8_t A6 = 0; +static const uint8_t A7 = 0; +static const uint8_t A8 = 0; +static const uint8_t A9 = 0; +static const uint8_t A10 = 0; +static const uint8_t A11 = 0; +static const uint8_t A12 = 0; +static const uint8_t A13 = 0; +static const uint8_t A14 = 0; +static const uint8_t A15 = 0; + +static const uint8_t DAC1 = 0; +static const uint8_t DAC2 = 0; + +/* Begin Arduino naming */ +static const uint8_t RESET_ARDUINO = 0; +static const uint8_t PC0 = GPIO3; +static const uint8_t PC1 = GPIO4; +static const uint8_t PC2 = GPIO5; +static const uint8_t PC3 = GPIO6; +static const uint8_t PC4 = GPIO7; +static const uint8_t PC5 = GPIO15; +static const uint8_t PB5 = GPIO35; +static const uint8_t PB4 = GPIO36; +static const uint8_t PB3 = GPIO37; +static const uint8_t PB2 = GPIO38; +static const uint8_t PB1 = GPIO39; +static const uint8_t PB0 = GPIO40; +static const uint8_t PD7 = GPIO41; +static const uint8_t PD6 = GPIO42; +static const uint8_t PD5 = GPIO21; +static const uint8_t PD4 = GPIO16; +static const uint8_t PD3 = GPIO14; +static const uint8_t PD2 = GPIO47; +static const uint8_t PD1 = GPIO17; +static const uint8_t PD0 = GPIO18; +/* End Arduino naming */ + +/* Begin alternate naming */ +static const uint8_t PB_SCL = SCL; +static const uint8_t PB_SDA = SDA; +static const uint8_t PB_35 = PB5; +static const uint8_t PB_36 = PB4; +static const uint8_t PB_37 = PB3; +static const uint8_t PB_38 = PB2; +static const uint8_t PB_39 = PB1; +static const uint8_t PB_40 = PB0; + +static const uint8_t PD_io41 = PD7; +static const uint8_t PD_42 = PD6; +static const uint8_t PD_21 = PD5; +static const uint8_t PD_16 = PD4; +static const uint8_t PD_14 = PD3; +static const uint8_t PD_47 = PD2; +static const uint8_t PD_17 = TX; +static const uint8_t PD_18 = RX; + +static const uint8_t PC_io3 = PC0; +static const uint8_t PC_4 = PC1; +static const uint8_t PC_5 = PC2; +static const uint8_t PC_6 = PC3; +static const uint8_t PC_7 = PC4; +static const uint8_t PC_15 = PC5; + +static const uint8_t M1_3_AN = GPIO3; +static const uint8_t M1_RST = 0; +static const uint8_t M1_48_CS = SS; +static const uint8_t M1_12_SCK = SCK; +static const uint8_t M1_13_MISO = MISO; +static const uint8_t M1_11_MOSI = MOSI; +static const uint8_t M2_47_PWM = GPIO47; +static const uint8_t M2_14_INT = GPIO14; +static const uint8_t M2_18_RX = GPIO18; +static const uint8_t M2_17_TX = GPIO17; +static const uint8_t M2_2_SCL = SCL; +static const uint8_t M2_1_SDA = SDA; + +static const uint8_t J3_SCL = SCL; +static const uint8_t J3_SDA = SDA; + +/* End alternate naming */ + +#endif /* Pins_Arduino_h */ diff --git a/variants/namino_rosso/pins_arduino.h b/variants/namino_rosso/pins_arduino.h new file mode 100644 index 0000000..90508e9 --- /dev/null +++ b/variants/namino_rosso/pins_arduino.h @@ -0,0 +1,197 @@ +// +// Copyright (c) 2023 Namino Team, version: 1.0.20 @ 2023-10-06 +// +// +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define NAMINO_ROSSO_BOARD + +/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t GPIO4 = 4; +static const uint8_t GPIO5 = 5; +static const uint8_t GPIO6 = 6; +static const uint8_t GPIO7 = 7; +static const uint8_t GPIO15 = 15; +static const uint8_t GPIO16 = 16; +static const uint8_t GPIO17 = 17; +static const uint8_t GPIO18 = 18; +static const uint8_t GPIO8 = 8; +static const uint8_t GPIO19 = 19; +static const uint8_t GPIO20 = 20; +static const uint8_t GPIO3 = 3; +static const uint8_t GPIO46 = 46; +static const uint8_t GPIO9 = 9; +static const uint8_t GPIO10 = 10; +static const uint8_t GPIO11 = 11; +static const uint8_t GPIO12 = 12; +static const uint8_t GPIO13 = 13; +static const uint8_t GPIO14 = 14; +static const uint8_t GPIO21 = 21; +static const uint8_t GPIO47 = 47; +static const uint8_t GPIO48 = 48; +static const uint8_t GPIO45 = 45; +static const uint8_t GPIO0 = 0; +static const uint8_t GPIO35 = 35; +static const uint8_t GPIO36 = 36; +static const uint8_t GPIO37 = 37; +static const uint8_t GPIO38 = 38; +static const uint8_t GPIO39 = 39; +static const uint8_t GPIO40 = 40; +static const uint8_t GPIO41 = 41; +static const uint8_t GPIO42 = 42; +static const uint8_t GPIO44 = 44; +static const uint8_t GPIO43 = 43; +static const uint8_t GPIO2 = 2; +static const uint8_t GPIO1 = 1; + +static const uint8_t RESET_ADD_ON = GPIO46; +static const uint8_t SS = GPIO10; +static const uint8_t MOSI = GPIO11; +static const uint8_t MISO = GPIO13; +static const uint8_t SCK = GPIO12; +// SPI SD CARD +static const uint8_t CS_SDCARD = GPIO2; +// prog pins +static const uint8_t BOOT_MODE = GPIO47; +static const uint8_t ISP_TX = GPIO17; +static const uint8_t ISP_RX = GPIO18; +static const uint8_t NM_RESET = GPIO48; +/* End Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t ADC1_CH3 = GPIO4; +static const uint8_t ADC1_CH4 = GPIO5; +static const uint8_t ADC1_CH5 = GPIO6; +static const uint8_t ADC1_CH6 = GPIO7; +static const uint8_t ADC2_CH4 = GPIO15; +static const uint8_t ADC2_CH5 = GPIO16; +static const uint8_t ADC2_CH6 = GPIO17; +static const uint8_t ADC2_CH7 = GPIO18; +static const uint8_t ADC1_CH7 = GPIO8; +static const uint8_t ADC2_CH8 = GPIO19; +static const uint8_t ADC2_CH9 = GPIO20; +static const uint8_t ADC1_CH2 = GPIO3; +static const uint8_t ADC1_CH8 = GPIO9; +static const uint8_t ADC1_CH9 = GPIO10; +static const uint8_t ADC2_CH0 = GPIO11; +static const uint8_t ADC2_CH1 = GPIO12; +static const uint8_t ADC2_CH2 = GPIO13; +static const uint8_t ADC2_CH3 = GPIO14; +static const uint8_t ADC1_CH1 = GPIO2; +static const uint8_t ADC1_CH0 = GPIO1; +/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */ + +/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ +static const uint8_t TOUCH4 = GPIO4; +static const uint8_t TOUCH5 = GPIO5; +static const uint8_t TOUCH6 = GPIO6; +static const uint8_t TOUCH7 = GPIO7; +static const uint8_t TOUCH8 = GPIO8; +static const uint8_t TOUCH3 = GPIO3; +static const uint8_t TOUCH9 = GPIO9; +static const uint8_t TOUCH10 = GPIO10; +static const uint8_t TOUCH11 = GPIO11; +static const uint8_t TOUCH12 = GPIO12; +static const uint8_t TOUCH13 = GPIO13; +static const uint8_t TOUCH14 = GPIO14; +static const uint8_t TOUCH2 = GPIO2; +static const uint8_t TOUCH1 = GPIO1; +/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */ + +static const uint8_t TX = GPIO17; +static const uint8_t RX = GPIO18; + +static const uint8_t SDA = GPIO1; +static const uint8_t SCL = GPIO0; +static const uint8_t NAMINO_ARANCIO_I2C_SDA = SDA; +static const uint8_t NAMINO_ARANCIO_I2C_SCL = SCL; +static const uint8_t NM_I2C_SDA = SDA; +static const uint8_t NM_I2C_SCL = SCL; + +static const uint8_t A0 = ADC1_CH0; +static const uint8_t A1 = ADC1_CH1; +static const uint8_t A2 = ADC1_CH2; +static const uint8_t A3 = ADC1_CH3; +static const uint8_t A4 = ADC1_CH4; +static const uint8_t A5 = ADC1_CH5; +static const uint8_t A6 = ADC1_CH6; +static const uint8_t A7 = ADC1_CH7; +static const uint8_t A8 = ADC2_CH0; +static const uint8_t A9 = ADC2_CH1; +static const uint8_t A10 = ADC2_CH2; +static const uint8_t A11 = ADC2_CH3; +static const uint8_t A12 = ADC2_CH4; +static const uint8_t A13 = ADC2_CH5; +static const uint8_t A14 = ADC2_CH6; +static const uint8_t A15 = ADC2_CH7; + +static const uint8_t DAC1 = 0; +static const uint8_t DAC2 = 0; + +/* Begin Arduino naming */ +static const uint8_t RESET_ARDUINO = GPIO46; +static const uint8_t PC0 = GPIO3; +static const uint8_t PC1 = GPIO4; +static const uint8_t PC2 = GPIO5; +static const uint8_t PC3 = GPIO6; +static const uint8_t PC4 = GPIO7; +static const uint8_t PC5 = GPIO8; +static const uint8_t PB5 = GPIO35; +static const uint8_t PB4 = GPIO36; +static const uint8_t PB3 = GPIO37; +static const uint8_t PB2 = GPIO38; +static const uint8_t PB1 = GPIO39; +static const uint8_t PB0 = GPIO40; +static const uint8_t PD7 = GPIO41; +static const uint8_t PD6 = GPIO42; +static const uint8_t PD5 = GPIO21; +static const uint8_t PD4 = GPIO16; +static const uint8_t PD3 = GPIO14; +static const uint8_t PD2 = GPIO9; +static const uint8_t PD1 = GPIO17; +static const uint8_t PD0 = GPIO18; +/* End Arduino naming */ + +/* Begin alternate naming */ +static const uint8_t J1_io0 = SCL; + +static const uint8_t J2_35 = PB5; +static const uint8_t J2_36 = PB4; +static const uint8_t J2_37 = PB3; +static const uint8_t J2_38 = PB2; +static const uint8_t J2_39 = PB1; +static const uint8_t J2_40 = PB0; + +static const uint8_t J3_io8 = PD7; +static const uint8_t J3_7 = PD6; +static const uint8_t J3_21 = PD5; +static const uint8_t J3_16 = PD4; +static const uint8_t J3_14 = PD3; +static const uint8_t J3_9 = PD2; +static const uint8_t J3_17 = TX; +static const uint8_t J3_18 = RX; + +static const uint8_t J4_cs_io2 = CS_SDCARD; +static const uint8_t J4_sclk = SCK; +static const uint8_t J4_mosi = MOSI; +static const uint8_t J4_miso = MISO; + +static const uint8_t J9_io3 = PC0; +static const uint8_t J9_4 = PC1; +static const uint8_t J9_5 = PC2; +static const uint8_t J9_6 = PC3; +static const uint8_t J9_7 = PC4; +static const uint8_t J9_8 = PC5; + +static const uint8_t J10_enc_A = 0; +static const uint8_t J10_enc_B = 0; +static const uint8_t J10_sw = 0; +/* End alternate naming */ + +#endif /* Pins_Arduino_h */ diff --git a/variants/nano32/pins_arduino.h b/variants/nano32/pins_arduino.h new file mode 100644 index 0000000..840fd86 --- /dev/null +++ b/variants/nano32/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 16; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BUILTIN_KEY = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/nina_w10/pins_arduino.h b/variants/nina_w10/pins_arduino.h new file mode 100644 index 0000000..ea1c5ab --- /dev/null +++ b/variants/nina_w10/pins_arduino.h @@ -0,0 +1,78 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_GREEN = 33; +static const uint8_t LED_RED = 23; +static const uint8_t LED_BLUE = 21; +static const uint8_t SW1 = 33; +static const uint8_t SW2 = 27; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 26; +static const uint8_t D3 = 25; +static const uint8_t D4 = 35; +static const uint8_t D5 = 27; +static const uint8_t D6 = 22; +static const uint8_t D7 = 0; +static const uint8_t D8 = 15; +static const uint8_t D9 = 14; +static const uint8_t D10 = 5; +static const uint8_t D11 = 19; +static const uint8_t D12 = 23; +static const uint8_t D13 = 18; +static const uint8_t D14 = 13; +static const uint8_t D15 = 12; + +static const uint8_t D16 = 32; +static const uint8_t D17 = 33; +static const uint8_t D18 = 21; +static const uint8_t D19 = 34; +static const uint8_t D20 = 36; +static const uint8_t D21 = 39; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/node32s/pins_arduino.h b/variants/node32s/pins_arduino.h new file mode 100644 index 0000000..e7c7a87 --- /dev/null +++ b/variants/node32s/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/nodemcu-32s/pins_arduino.h b/variants/nodemcu-32s/pins_arduino.h new file mode 100644 index 0000000..e7c7a87 --- /dev/null +++ b/variants/nodemcu-32s/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/nologo_esp32c3_super_mini/pins_arduino.h b/variants/nologo_esp32c3_super_mini/pins_arduino.h new file mode 100644 index 0000000..fdcc730 --- /dev/null +++ b/variants/nologo_esp32c3_super_mini/pins_arduino.h @@ -0,0 +1,28 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/nologo_esp32s3_pico/pins_arduino.h b/variants/nologo_esp32s3_pico/pins_arduino.h new file mode 100644 index 0000000..5284168 --- /dev/null +++ b/variants/nologo_esp32s3_pico/pins_arduino.h @@ -0,0 +1,37 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 21; +#define BUILTIN_LED LED_BUILTIN +#define LED_BUILTIN LED_BUILTIN +#define RGB_BUILTIN SOC_GPIO_PIN_COUNT + LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +// SPI - unused but you can create your own definition in your sketch +static const int8_t SCK = -1; +static const int8_t MISO = -1; +static const int8_t MOSI = -1; +static const int8_t SS = -1; + +// I2C - unused but you can create your own definition in your sketch +static const uint8_t SDA = -1; +static const uint8_t SCL = -1; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; + +#endif /* Pins_Arduino_h */ diff --git a/variants/nora_w10/pins_arduino.h b/variants/nora_w10/pins_arduino.h new file mode 100644 index 0000000..a833fbb --- /dev/null +++ b/variants/nora_w10/pins_arduino.h @@ -0,0 +1,84 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// The pin assignments in this file are based on u-blox EVK-NORA-W1, a Arduino compatible board. +// For your own module design you can freely chose the pins available on the module module pins + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +static const uint8_t RTS = 45; +static const uint8_t CTS = 6; +static const uint8_t DTR = 1; +static const uint8_t DSR = 7; + +static const uint8_t SW1 = 46; +static const uint8_t SW2 = 0; // BOOT +static const uint8_t SW3 = 47; +static const uint8_t SW4 = 48; + +static const uint8_t LED_RED = 5; +static const uint8_t LED_GREEN = 2; +static const uint8_t LED_BLUE = 8; +#define BUILTIN_LED LED_BLUE // backward compatibility +#define LED_BUILTIN LED_BLUE + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 11; +static const uint8_t A1 = 12; +static const uint8_t A2 = 13; +static const uint8_t A3 = 5; +static const uint8_t A4 = 15; +static const uint8_t A5 = 16; + +static const uint8_t D0 = 44; // RX0 +static const uint8_t D1 = 43; // TX0 +static const uint8_t D2 = 46; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 14; +static const uint8_t D7 = 10; + +static const uint8_t D8 = 33; +static const uint8_t D9 = 38; +static const uint8_t D10 = 34; // SS +static const uint8_t D11 = 35; // MOSI +static const uint8_t D12 = 37; // MISO +static const uint8_t D13 = 36; // SCK +static const uint8_t SDA1 = 21; +static const uint8_t SCL1 = 0; + +static const uint8_t D14 = 45; // RTS +static const uint8_t D15 = 6; // CTS +static const uint8_t D16 = 1; // DTR +static const uint8_t D17 = 7; // DSR +static const uint8_t D18 = 47; +static const uint8_t D19 = 48; +static const uint8_t SDA = 18; +static const uint8_t SCL = 17; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/odroid_esp32/pins_arduino.h b/variants/odroid_esp32/pins_arduino.h new file mode 100644 index 0000000..f89dfff --- /dev/null +++ b/variants/odroid_esp32/pins_arduino.h @@ -0,0 +1,27 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 15; +static const uint8_t SCL = 4; + +static const uint8_t SS = 22; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t ADC1 = 35; +static const uint8_t ADC2 = 36; + +#endif /* Pins_Arduino_h */ diff --git a/variants/onehorse32dev/pins_arduino.h b/variants/onehorse32dev/pins_arduino.h new file mode 100644 index 0000000..06364e5 --- /dev/null +++ b/variants/onehorse32dev/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/openkb/pins_arduino.h b/variants/openkb/pins_arduino.h new file mode 100644 index 0000000..0ceccde --- /dev/null +++ b/variants/openkb/pins_arduino.h @@ -0,0 +1,83 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 16; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t LDR_PIN = 36; + +static const uint8_t SW1 = 16; +static const uint8_t SW2 = 14; + +static const uint8_t BT_LED = 17; +static const uint8_t WIFI_LED = 2; +static const uint8_t NTP_LED = 15; +static const uint8_t IOT_LED = 12; + +static const uint8_t BUZZER = 13; + +static const uint8_t INPUT1 = 32; +static const uint8_t INPUT2 = 33; +static const uint8_t INPUT3 = 34; +static const uint8_t INPUT4 = 35; + +static const uint8_t OUTPUT1 = 26; +static const uint8_t OUTPUT2 = 27; + +static const uint8_t SDA0 = 21; +static const uint8_t SCL0 = 22; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 4; +static const uint8_t SCL1 = 5; + +static const uint8_t KB_GPIO18 = 18; +static const uint8_t KB_GPIO19 = 19; +static const uint8_t KB_GPIO23 = 23; + +#endif /* Pins_Arduino_h */ diff --git a/variants/oroca_edubot/pins_arduino.h b/variants/oroca_edubot/pins_arduino.h new file mode 100644 index 0000000..3022bcf --- /dev/null +++ b/variants/oroca_edubot/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 17; +static const uint8_t RX = 16; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 34; +static const uint8_t A1 = 39; +static const uint8_t A2 = 36; +static const uint8_t A3 = 33; + +static const uint8_t D0 = 4; +static const uint8_t D1 = 16; +static const uint8_t D2 = 17; +static const uint8_t D3 = 22; +static const uint8_t D4 = 23; +static const uint8_t D5 = 5; +static const uint8_t D6 = 18; +static const uint8_t D7 = 19; +static const uint8_t D8 = 33; + +// vbat measure +static const uint8_t VBAT = 35; +#define BAT_VOLT_PIN VBAT + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pandabyte_x32/pins_arduino.h b/variants/pandabyte_x32/pins_arduino.h new file mode 100644 index 0000000..0978bf7 --- /dev/null +++ b/variants/pandabyte_x32/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +static const uint8_t RGB_BUILTIN = 12; +static const uint8_t BUTTON_BUILTIN = 4; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pandabyte_xc3m/pins_arduino.h b/variants/pandabyte_xc3m/pins_arduino.h new file mode 100644 index 0000000..f55cec7 --- /dev/null +++ b/variants/pandabyte_xc3m/pins_arduino.h @@ -0,0 +1,41 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 5; +static const uint8_t RGB_BUILTIN = 6; +static const uint8_t BUTTON_BUILTIN = 7; + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 1; +static const uint8_t SCL = 0; + +static const uint8_t SS = 3; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D18 = 18; +static const uint8_t D19 = 19; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pandabyte_xc5/pins_arduino.h b/variants/pandabyte_xc5/pins_arduino.h new file mode 100644 index 0000000..b187278 --- /dev/null +++ b/variants/pandabyte_xc5/pins_arduino.h @@ -0,0 +1,43 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 23; +static const uint8_t RGB_BUILTIN = 10; +static const uint8_t BUTTON_BUILTIN = 24; + +static const uint8_t TX = 11; +static const uint8_t RX = 12; + +// static const uint8_t USB_DM = 13; +// static const uint8_t USB_DP = 14; + +static const uint8_t SDA = 0; +static const uint8_t SCL = 1; + +static const uint8_t SS = 6; +static const uint8_t MOSI = 8; +static const uint8_t MISO = 9; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; + +// LP I2C Pins are fixed on ESP32-C5 +static const uint8_t LP_SDA = 2; +static const uint8_t LP_SCL = 3; +#define WIRE1_PIN_DEFINED +#define SDA1 LP_SDA +#define SCL1 LP_SCL + +// LP UART Pins are fixed on ESP32-C5 +static const uint8_t LP_RX = 4; +static const uint8_t LP_TX = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pandabyte_xc6/pins_arduino.h b/variants/pandabyte_xc6/pins_arduino.h new file mode 100644 index 0000000..50580c5 --- /dev/null +++ b/variants/pandabyte_xc6/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 3; +static const uint8_t RGB_BUILTIN = 23; +static const uint8_t BUTTON_BUILTIN = 22; + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 19; +static const uint8_t MISO = 20; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +// LP I2C Pins are fixed on ESP32-C6 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pandabyte_xs3/pins_arduino.h b/variants/pandabyte_xs3/pins_arduino.h new file mode 100644 index 0000000..2348265 --- /dev/null +++ b/variants/pandabyte_xs3/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 2; +static const uint8_t RGB_BUILTIN = 12; +static const uint8_t BUTTON_BUILTIN = 21; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pico32/pins_arduino.h b/variants/pico32/pins_arduino.h new file mode 100644 index 0000000..3663de7 --- /dev/null +++ b/variants/pico32/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/piranha_esp-32/pins_arduino.h b/variants/piranha_esp-32/pins_arduino.h new file mode 100644 index 0000000..57616da --- /dev/null +++ b/variants/piranha_esp-32/pins_arduino.h @@ -0,0 +1,40 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A11 = 0; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T1 = 0; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/pocket_32/pins_arduino.h b/variants/pocket_32/pins_arduino.h new file mode 100644 index 0000000..9c904d0 --- /dev/null +++ b/variants/pocket_32/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 16; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/quantum/pins_arduino.h b/variants/quantum/pins_arduino.h new file mode 100644 index 0000000..3663de7 --- /dev/null +++ b/variants/quantum/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/rakwireless_rak3112/pins_arduino.h b/variants/rakwireless_rak3112/pins_arduino.h new file mode 100644 index 0000000..2ba615f --- /dev/null +++ b/variants/rakwireless_rak3112/pins_arduino.h @@ -0,0 +1,67 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Reference: RAK3112 Module Datasheet +// https://docs.rakwireless.com/product-categories/wisduo/rak3112-module/datasheet/ + +// Note:GPIO33,GPIO34,GPIO35.GPIO36,GPIO37 is not available in the 8MB and 16MB Octal PSRAM version + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define LED_GREEN 46 +#define LED_BLUE 45 + +static const uint8_t LED_BUILTIN = LED_GREEN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t BAT_VOLT = 21; +#define BAT_VOLT_PIN BAT_VOLT + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t TX1 = 43; // UART1 default TX pin for RAK3112 +static const uint8_t RX1 = 44; // UART1 default RX pin for RAK3112 + +static const uint8_t SDA = 9; +static const uint8_t SCL = 40; + +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 17; +static const uint8_t SCL1 = 18; + +static const uint8_t SS = 12; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 10; +static const uint8_t SCK = 13; + +#define LORA_ANT_SWITCH 4 // Antenna switch power control pin + +#define LORA_SCK 5 // SX1262 SCK +#define LORA_MISO 3 // SX1262 MISO +#define LORA_MOSI 6 // SX1262 MOSI +#define LORA_CS 7 // SX1262 CS +#define LORA_RST 8 // SX1262 RST + +#define LORA_DIO1 47 //SX1262 DIO1 +#define LORA_BUSY 48 +#define LORA_IRQ LORA_DIO1 + +// For WisBlock modules, see: https://docs.rakwireless.com/Product-Categories/WisBlock/ +#define WB_IO1 21 +#define WB_IO2 14 +#define WB_IO3 41 +#define WB_IO4 42 +#define WB_IO5 38 +#define WB_IO6 39 +#define WB_A0 1 +#define WB_A1 2 +#define WB_CS 12 +#define WB_LED1 46 +#define WB_LED2 45 + +#endif /* Pins_Arduino_h */ diff --git a/variants/redpill_esp32s3/pins_arduino.h b/variants/redpill_esp32s3/pins_arduino.h new file mode 100644 index 0000000..21ad8b6 --- /dev/null +++ b/variants/redpill_esp32s3/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 3; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 15; +static const uint8_t MOSI = 16; +static const uint8_t MISO = 17; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/redpill_esp32s3/tinyuf2.bin b/variants/redpill_esp32s3/tinyuf2.bin new file mode 100644 index 0000000..3b10b6f Binary files /dev/null and b/variants/redpill_esp32s3/tinyuf2.bin differ diff --git a/variants/roboheart_hercules/pins_arduino.h b/variants/roboheart_hercules/pins_arduino.h new file mode 100644 index 0000000..e477716 --- /dev/null +++ b/variants/roboheart_hercules/pins_arduino.h @@ -0,0 +1,96 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// Motor driver pins +#define MOTOR_A_IN1 25 // PHASE/IN1 +#define MOTOR_A_IN2 26 // ENABLE/IN2 + +#define MOTOR_B_IN1 27 // PHASE/IN1 +#define MOTOR_B_IN2 32 // ENABLE/IN2 + +#define MOTOR_C_IN1 33 // PHASE/IN1 +#define MOTOR_C_IN2 4 // ENABLE/IN2 + +#define SLEEP_MOTOR_ABC 2 // nSLEEP + +#define LED_ROBOHEART 13 // Built in LED +#define BUILTIN_LED LED_ROBOHEART // backward compatibility +#define LED_BUILTIN LED_ROBOHEART + +#define BUTTON_ROBOHEART 0 // Button + +// I2C IMU sensor +#define IMU_SDA 21 +#define IMU_SCL 22 + +#define RXD1 16 +#define TXD1 17 + +// GSM Vela connector board pins +#define GSM_PWRKEY 12 +#define GSM_DTR 13 +#define GSM_CTS 15 +#define GSM_RTS 14 +#define GSM_TX TXD1 +#define GSM_RX RXD1 +#define BATTERY_PIN 36 // Battery ADC pin +#define BAT_VOLT_PIN BATTERY_PIN + +static const uint8_t TX = 35; +static const uint8_t RX = 34; + +static const uint8_t TXD2 = 17; +static const uint8_t RXD2 = 16; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t G23 = 23; +static const uint8_t G19 = 19; +static const uint8_t G18 = 18; +static const uint8_t G3 = 3; +static const uint8_t G16 = 16; +static const uint8_t G21 = 21; +static const uint8_t G2 = 2; +static const uint8_t G12 = 12; +static const uint8_t G15 = 15; +static const uint8_t G35 = 35; +static const uint8_t G36 = 36; +static const uint8_t G25 = 25; +static const uint8_t G26 = 26; +static const uint8_t G1 = 1; +static const uint8_t G17 = 17; +static const uint8_t G22 = 22; +static const uint8_t G5 = 5; +static const uint8_t G13 = 13; +static const uint8_t G0 = 0; +static const uint8_t G34 = 34; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/rootmaker/pins_arduino.h b/variants/rootmaker/pins_arduino.h new file mode 100644 index 0000000..dddc358 --- /dev/null +++ b/variants/rootmaker/pins_arduino.h @@ -0,0 +1,140 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 45 +// and change this setup for the chosen pin (for example 38) +#define PIN_RGB_LED 45 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 7 + +// UART0 +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// 6Dsensor + LED +static const uint8_t SEN_INT = 42; +static const uint8_t SDA = 41; +static const uint8_t SCL = 40; + +// LCD +static const uint8_t LCD_SDA = 9; +static const uint8_t LCD_BL = 7; +static const uint8_t LCD_CS = 5; +static const uint8_t LCD_RS = 3; +static const uint8_t LCD_SCK = 12; +static const uint8_t LCD_RST = 14; + +// TP +static const uint8_t TP_INT = 1; +static const uint8_t TP_SDA = 41; +static const uint8_t TP_SCL = 40; +static const uint8_t TP_RST = 2; + +// SPI +static const uint8_t SS = 29; +static const uint8_t MOSI = 31; +static const uint8_t MISO = 32; +static const uint8_t SCK = 30; +static const uint8_t WP = 28; +static const uint8_t HD = 27; + +// 4个扩展接口 +static const uint8_t PORT1_SDA = 15; +static const uint8_t PORT1_SCL = 16; + +static const uint8_t PORT2_SDA = 19; +static const uint8_t PORT2_SCL = 20; + +static const uint8_t PORT3_SDA = 13; +static const uint8_t PORT3_SCL = 14; + +static const uint8_t PORT4_SDA = 17; +static const uint8_t PORT4_SCL = 18; + +// F_BUS +static const uint8_t F_BUS7 = 45; +static const uint8_t F_BUS8 = 41; +static const uint8_t F_BUS9 = 40; +static const uint8_t F_BUS10 = 35; +static const uint8_t F_BUS11 = 33; +static const uint8_t F_BUS12 = 39; +static const uint8_t F_BUS13 = 38; +static const uint8_t F_BUS14 = 37; +static const uint8_t F_BUS15 = 36; +static const uint8_t F_BUS16 = 34; +static const uint8_t F_BUS17 = 21; + +static const uint8_t F_BUS24 = 20; +static const uint8_t F_BUS25 = 19; +static const uint8_t F_BUS26 = 18; +static const uint8_t F_BUS27 = 17; +static const uint8_t F_BUS28 = 16; +static const uint8_t F_BUS29 = 15; +static const uint8_t F_BUS30 = 14; +static const uint8_t F_BUS31 = 13; +static const uint8_t F_BUS32 = 48; +static const uint8_t F_BUS33 = 47; +static const uint8_t F_BUS34 = 46; + +// S_BUS +static const uint8_t S_BUS1 = 48; +static const uint8_t S_BUS2 = 47; +static const uint8_t S_BUS3 = 46; +static const uint8_t S_BUS4 = 38; +static const uint8_t S_BUS5 = 39; +static const uint8_t S_BUS6 = 33; +static const uint8_t S_BUS7 = 35; +static const uint8_t S_BUS8 = 40; +static const uint8_t S_BUS9 = 41; +static const uint8_t S_BUS10 = 45; +static const uint8_t S_BUS11 = 37; +static const uint8_t S_BUS12 = 36; +static const uint8_t S_BUS13 = 34; +static const uint8_t S_BUS14 = 21; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sensebox_eye/APOTA.bin b/variants/sensebox_eye/APOTA.bin new file mode 100644 index 0000000..18547ce Binary files /dev/null and b/variants/sensebox_eye/APOTA.bin differ diff --git a/variants/sensebox_eye/APOTA.ino b/variants/sensebox_eye/APOTA.ino new file mode 100644 index 0000000..58c1116 --- /dev/null +++ b/variants/sensebox_eye/APOTA.ino @@ -0,0 +1,301 @@ +// APOTA is an Arduino fallback sketch that is written to OTA1_Partition. +// APOTA opens an access point which waits to receive a .bin file on /sketch. +// After successful upload, the file is written to OTA0_Partition, and the microcontroller reboots to the newly uploaded sketch. + +#define DISPLAY_ENABLED + +#include +#include +#include +#include +#include +#include +#ifdef DISPLAY_ENABLED +#define SCREEN_WIDTH 128 +#define SCREEN_HEIGHT 64 +#define OLED_RESET -1 +#include +#include +Adafruit_SSD1306 display(SCREEN_WIDTH, SCREEN_HEIGHT, &Wire, OLED_RESET); +#include +Adafruit_NeoPixel rgb_led = Adafruit_NeoPixel(1, PIN_LED, NEO_GRB + NEO_KHZ800); + +#endif +#include "esp_partition.h" +#include "esp_ota_ops.h" +#include "esp_system.h" + +String ssid; +uint8_t mac[6]; + +// Create an instance of the server +WebServer server(80); +bool displayEnabled; + +const int BUTTON_PIN = 0; // GPIO for the button +volatile unsigned long lastPressTime = 0; // Time of last button press +volatile bool doublePressDetected = false; // Flag for double press +const unsigned long doublePressInterval = 500; // Max. time (in ms) between two presses for double press +volatile int pressCount = 0; // Counts the button presses + +const unsigned char epd_bitmap_wifi[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x01, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x07, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x1f, 0xe0, 0xff, 0x00, 0x00, + 0x00, 0x3f, 0x00, 0x0f, 0x80, 0x00, 0x00, 0x7c, 0x00, 0x03, 0xe0, 0x00, 0x00, 0xf0, 0x00, 0x01, 0xf0, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x78, 0x00, + 0x03, 0xc0, 0x00, 0x00, 0x38, 0x00, 0x07, 0x80, 0x00, 0x00, 0x1c, 0x00, 0x0f, 0x00, 0x06, 0x00, 0x0e, 0x00, 0x0e, 0x00, 0x7f, 0xe0, 0x0e, 0x00, + 0x0c, 0x01, 0xff, 0xf0, 0x06, 0x00, 0x00, 0x07, 0xff, 0xfc, 0x02, 0x00, 0x00, 0x0f, 0x80, 0x3e, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x0f, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x07, 0x80, 0x00, 0x00, 0x38, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x70, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x70, 0x00, 0x00, 0xc0, 0x00, + 0x00, 0x20, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, + 0x00, 0x01, 0xe0, 0xf0, 0x00, 0x00, 0x00, 0x01, 0xc0, 0x78, 0x00, 0x00, 0x00, 0x03, 0x80, 0x38, 0x00, 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +// 'checkmark', 44x44px +const unsigned char epd_bitmap_checkmark[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x0f, 0x83, 0xc0, 0x00, 0x00, 0x00, 0x07, 0xc7, 0x80, 0x00, 0x00, 0x00, 0x03, 0xef, 0x00, 0x00, 0x00, + 0x00, 0x01, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +void IRAM_ATTR handleButtonPress() { + unsigned long currentTime = millis(); // Get current time + + // Debounce: If the current press is too close to the last one, ignore it + if (currentTime - lastPressTime > 50) { + pressCount++; // Count the button press + + // Check if this is the second press within the double-press interval + if (pressCount == 2 && (currentTime - lastPressTime <= doublePressInterval)) { + doublePressDetected = true; // Double press detected + pressCount = 0; // Reset counter + } + + lastPressTime = currentTime; // Update the time of the last press + } +} + +// Function to switch the boot partition to OTA0 +void setBootPartitionToOTA0() { + const esp_partition_t *ota0_partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_OTA_0, NULL); + + if (ota0_partition) { + // Set OTA0 as new boot partition + esp_ota_set_boot_partition(ota0_partition); + Serial.println("Boot partition changed to OTA0. Restarting..."); + + // Restart to boot from the new partition + esp_restart(); + } else { + Serial.println("OTA0 partition not found!"); + } +} + +void setupDisplay() { + Wire.begin(PIN_QWIIC_SDA, PIN_QWIIC_SCL); + displayEnabled = Wire.requestFrom(0x3D, 1); // Check if the display is connected + if (displayEnabled) { + display.begin(SSD1306_SWITCHCAPVCC, 0x3D); + display.display(); + delay(100); + display.clearDisplay(); + } +} + +void displayStatusBar(int progress) { + display.clearDisplay(); + display.setCursor(16, 8); + display.println("Sketch is being"); + display.setCursor(32, 22); + display.println("uploaded!"); + + display.fillRect(0, SCREEN_HEIGHT - 24, SCREEN_WIDTH - 4, 8, BLACK); // Clear status bar area + display.drawRect(0, SCREEN_HEIGHT - 24, SCREEN_WIDTH - 4, 8, WHITE); // Draw border + int filledWidth = (progress * SCREEN_WIDTH - 4) / 100; // Calculate progress width + display.fillRect(1, SCREEN_HEIGHT - 23, filledWidth - 4, 6, WHITE); // Fill progress bar + + display.setCursor((SCREEN_WIDTH / 2) - 12, SCREEN_HEIGHT - 10); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.print(progress); + display.println(" %"); + display.display(); +} + +void displayWelcomeScreen() { + display.clearDisplay(); + + // Draw WiFi symbol + display.drawBitmap(0, 12, epd_bitmap_wifi, 44, 44, WHITE); + + // Display SSID text + display.setCursor(52, 13); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println("Connect"); + display.setCursor(60, 27); + display.println("with:"); + + // Display SSID + display.setCursor(40, 43); + display.setTextSize(1); // Larger text for SSID + display.print(ssid); + + display.display(); +} + +void displaySuccessScreen() { + display.clearDisplay(); + + // Draw WiFi symbol + display.drawBitmap(0, 12, epd_bitmap_checkmark, 44, 44, WHITE); + + // Display SSID text + display.setCursor(48, 22); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println("Successfully"); + display.setCursor(48, 36); + display.println("uploaded!"); + + display.display(); +} + +void wipeDisplay() { + display.clearDisplay(); + display.println(""); + display.display(); +} + +void setupWiFi() { + WiFi.macAddress(mac); + char macLastFour[5]; + snprintf(macLastFour, sizeof(macLastFour), "%02X%02X", mac[4], mac[5]); + ssid = "senseBox:" + String(macLastFour); + + // Define the IP address, gateway, and subnet mask + IPAddress local_IP(192, 168, 1, 1); // The new IP address + IPAddress gateway(192, 168, 1, 1); // Gateway address (can be the same as the AP's IP) + IPAddress subnet(255, 255, 255, 0); // Subnet mask + + // Set the IP address, gateway, and subnet mask of the access point + WiFi.softAPConfig(local_IP, gateway, subnet); + + // Start the access point + WiFi.softAP(ssid.c_str()); +} + +void setupOTA() { + // Handle updating process + server.on( + "/sketch", HTTP_POST, + []() { + server.sendHeader("Connection", "close"); + server.send(200, "text/plain", (Update.hasError()) ? "FAIL" : "OK"); + ESP.restart(); + }, + []() { + HTTPUpload &upload = server.upload(); + + if (upload.status == UPLOAD_FILE_START) { + Serial.setDebugOutput(true); + size_t fsize = UPDATE_SIZE_UNKNOWN; + if (server.clientContentLength() > 0) { + fsize = server.clientContentLength(); + } + Serial.printf("Receiving Update: %s, Size: %d\n", upload.filename.c_str(), fsize); + + Serial.printf("Update: %s\n", upload.filename.c_str()); + if (!Update.begin(fsize)) { //start with max available size + Update.printError(Serial); + } + } else if (upload.status == UPLOAD_FILE_WRITE) { + /* flashing firmware to ESP*/ + if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) { + Update.printError(Serial); + } else { + int progress = (Update.progress() * 100) / Update.size(); + if (displayEnabled) { + displayStatusBar(progress); // Update progress on display + } + rgb_led.setPixelColor(0, rgb_led.Color(255, 255, 51)); + rgb_led.show(); + } + } else if (upload.status == UPLOAD_FILE_END) { + if (Update.end(true)) { //true to set the size to the current progress + if (displayEnabled) { + displaySuccessScreen(); + delay(3000); + wipeDisplay(); + } + rgb_led.setPixelColor(0, rgb_led.Color(51, 51, 255)); + rgb_led.show(); + } else { + Update.printError(Serial); + } + Serial.setDebugOutput(false); + } + yield(); + } + ); +} + +void setup() { + // Start Serial communication + Serial.begin(115200); + rgb_led.begin(); + rgb_led.setBrightness(15); + rgb_led.setPixelColor(0, rgb_led.Color(51, 51, 255)); + rgb_led.show(); + + // Configure button pin as input + pinMode(BUTTON_PIN, INPUT_PULLUP); + + // Interrupt for the button + attachInterrupt(digitalPinToInterrupt(BUTTON_PIN), handleButtonPress, FALLING); + +#ifdef DISPLAY_ENABLED + setupDisplay(); +#endif + setupWiFi(); + // Set the ESP32 as an access point + setupOTA(); + server.begin(); +} + +void loop() { + // Handle client requests + server.handleClient(); + +#ifdef DISPLAY_ENABLED + if (displayEnabled) { + displayWelcomeScreen(); + } +#endif + + if (doublePressDetected) { + Serial.println("Double press detected!"); + setBootPartitionToOTA0(); +#ifdef DISPLAY_ENABLED + if (displayEnabled) { + display.setCursor(0, 0); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println(""); + display.display(); + delay(50); + } +#endif + // Restart to boot from the new partition + esp_restart(); + } +} diff --git a/variants/sensebox_eye/bootloader-tinyuf2.bin b/variants/sensebox_eye/bootloader-tinyuf2.bin new file mode 100644 index 0000000..7a83be0 Binary files /dev/null and b/variants/sensebox_eye/bootloader-tinyuf2.bin differ diff --git a/variants/sensebox_eye/partitions-16MB-tinyuf2.csv b/variants/sensebox_eye/partitions-16MB-tinyuf2.csv new file mode 100644 index 0000000..55dc621 --- /dev/null +++ b/variants/sensebox_eye/partitions-16MB-tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/variants/sensebox_eye/pins_arduino.h b/variants/sensebox_eye/pins_arduino.h new file mode 100644 index 0000000..70c2bd8 --- /dev/null +++ b/variants/sensebox_eye/pins_arduino.h @@ -0,0 +1,90 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x82D1 +#define USB_MANUFACTURER "senseBox" +#define USB_PRODUCT "Eye ESP32S3" +#define USB_SERIAL "" // Empty string for MAC address + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "senseBox" // max 8 chars +#define USB_FW_MSC_PRODUCT_ID "Eye ESP32S3" // max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.00" // max 4 chars +#define USB_FW_MSC_VOLUME_NAME "senseBox" // max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +#define PIN_RGB_LED 45 // RGB LED +#define RGBLED_PIN 45 // RGB LED +#define PIN_LED 45 +#define RGBLED_NUM 1 // number of RGB LEDs + +// Default I2C QWIIC-Ports +static const uint8_t SDA = 2; +static const uint8_t SCL = 1; +#define PIN_QWIIC_SDA 2 +#define PIN_QWIIC_SCL 1 + +// IO Pins +#define PIN_IO14 14 +static const uint8_t A14 = PIN_IO14; // Analog +static const uint8_t D14 = PIN_IO14; // Digital +static const uint8_t T14 = PIN_IO14; // Touch +#define PIN_IO48 48 +static const uint8_t A48 = PIN_IO48; // Analog +static const uint8_t D48 = PIN_IO48; // Digital +static const uint8_t T48 = PIN_IO48; // Touch + +// Button +#define PIN_BUTTON 47 + +// UART Port +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define PIN_UART_TXD 43 +#define PIN_UART_RXD 44 +#define PIN_UART_ENABLE 26 + +// SD-Card +#define MISO 40 +#define MOSI 38 +#define SCK 39 +#define SS 41 +#define SD_ENABLE 3 + +#define PIN_SD_MISO 40 +#define PIN_SD_MOSI 38 +#define PIN_SD_SCLK 39 +#define PIN_SD_CS 41 +#define PIN_SD_ENABLE 3 + +// USB +#define PIN_USB_DM 19 +#define PIN_USB_DP 20 + +// Camera +#define PWDN_GPIO_NUM 46 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 15 +#define SIOD_GPIO_NUM 4 +#define SIOC_GPIO_NUM 5 + +#define Y9_GPIO_NUM 16 +#define Y8_GPIO_NUM 17 +#define Y7_GPIO_NUM 18 +#define Y6_GPIO_NUM 12 +#define Y5_GPIO_NUM 10 +#define Y4_GPIO_NUM 8 +#define Y3_GPIO_NUM 9 +#define Y2_GPIO_NUM 11 +#define VSYNC_GPIO_NUM 6 +#define HREF_GPIO_NUM 7 +#define PCLK_GPIO_NUM 13 + +// LoRa +#define LORA_TX 43 +#define LORA_RX 44 + +#endif /* Pins_Arduino_h */ diff --git a/variants/sensebox_eye/tinyuf2.bin b/variants/sensebox_eye/tinyuf2.bin new file mode 100644 index 0000000..67c00aa Binary files /dev/null and b/variants/sensebox_eye/tinyuf2.bin differ diff --git a/variants/sensebox_eye/variant.cpp b/variants/sensebox_eye/variant.cpp new file mode 100644 index 0000000..cd86cde --- /dev/null +++ b/variants/sensebox_eye/variant.cpp @@ -0,0 +1,39 @@ +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" +#include "esp_log.h" +#include "esp_partition.h" +#include "esp_system.h" +#include "esp_ota_ops.h" + +extern "C" { + +void blinkLED(uint8_t r, uint8_t g, uint8_t b) { + rgbLedWrite(PIN_LED, r, g, b); + delay(20); + rgbLedWrite(PIN_LED, 0x00, 0x00, 0x00); // off +} + +void initVariant(void) { + // define button pin + pinMode(47, INPUT_PULLUP); + + // Check if button is pressed + if (digitalRead(47) == LOW) { + // When the button is pressed and then released, boot into the OTA1 partition + const esp_partition_t *ota1_partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_OTA_1, NULL); + + if (ota1_partition) { + esp_err_t err = esp_ota_set_boot_partition(ota1_partition); + if (err == ESP_OK) { + blinkLED(0x00, 0x00, 0x10); // blue + esp_restart(); // restart, to boot OTA1 partition + } else { + blinkLED(0x10, 0x00, 0x00); // red + ESP_LOGE("OTA", "Error setting OTA1 partition: %s", esp_err_to_name(err)); + } + } + } else { + blinkLED(0x00, 0x10, 0x00); // green + } +} +} diff --git a/variants/sensebox_mcu_esp32s2/APOTA.bin b/variants/sensebox_mcu_esp32s2/APOTA.bin new file mode 100644 index 0000000..ebe676c Binary files /dev/null and b/variants/sensebox_mcu_esp32s2/APOTA.bin differ diff --git a/variants/sensebox_mcu_esp32s2/APOTA.ino b/variants/sensebox_mcu_esp32s2/APOTA.ino new file mode 100644 index 0000000..ef0fa7d --- /dev/null +++ b/variants/sensebox_mcu_esp32s2/APOTA.ino @@ -0,0 +1,287 @@ +// APOTA is an Arduino fallback sketch that is written to OTA1_Partition. +// APOTA opens an access point which waits to receive a .bin file on /sketch. +// After successful upload, the file is written to OTA0_Partition, and the microcontroller reboots to the newly uploaded sketch. + +#define DISPLAY_ENABLED + +#include +#include +#include +#include +#include +#include +#ifdef DISPLAY_ENABLED +#define SCREEN_WIDTH 128 +#define SCREEN_HEIGHT 64 +#define OLED_RESET -1 +#include +#include +Adafruit_SSD1306 display(SCREEN_WIDTH, SCREEN_HEIGHT, &Wire, OLED_RESET); +#include +Adafruit_NeoPixel rgb_led_1 = Adafruit_NeoPixel(1, 1, NEO_GRB + NEO_KHZ800); + +#endif +#include "esp_partition.h" +#include "esp_ota_ops.h" +#include "esp_system.h" + +String ssid; +uint8_t mac[6]; + +// Create an instance of the server +WebServer server(80); +bool displayEnabled; + +const int BUTTON_PIN = 0; // GPIO for the button +volatile unsigned long lastPressTime = 0; // Time of last button press +volatile bool doublePressDetected = false; // Flag for double press +const unsigned long doublePressInterval = 500; // Max. time (in ms) between two presses for double press +volatile int pressCount = 0; // Counts the button presses + +const unsigned char epd_bitmap_wifi[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x01, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x07, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x1f, 0xe0, 0xff, 0x00, 0x00, + 0x00, 0x3f, 0x00, 0x0f, 0x80, 0x00, 0x00, 0x7c, 0x00, 0x03, 0xe0, 0x00, 0x00, 0xf0, 0x00, 0x01, 0xf0, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x78, 0x00, + 0x03, 0xc0, 0x00, 0x00, 0x38, 0x00, 0x07, 0x80, 0x00, 0x00, 0x1c, 0x00, 0x0f, 0x00, 0x06, 0x00, 0x0e, 0x00, 0x0e, 0x00, 0x7f, 0xe0, 0x0e, 0x00, + 0x0c, 0x01, 0xff, 0xf0, 0x06, 0x00, 0x00, 0x07, 0xff, 0xfc, 0x02, 0x00, 0x00, 0x0f, 0x80, 0x3e, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x0f, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x07, 0x80, 0x00, 0x00, 0x38, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x70, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x70, 0x00, 0x00, 0xc0, 0x00, + 0x00, 0x20, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, + 0x00, 0x01, 0xe0, 0xf0, 0x00, 0x00, 0x00, 0x01, 0xc0, 0x78, 0x00, 0x00, 0x00, 0x03, 0x80, 0x38, 0x00, 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +// 'checkmark', 44x44px +const unsigned char epd_bitmap_checkmark[] PROGMEM = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x0f, 0x83, 0xc0, 0x00, 0x00, 0x00, 0x07, 0xc7, 0x80, 0x00, 0x00, 0x00, 0x03, 0xef, 0x00, 0x00, 0x00, + 0x00, 0x01, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +void IRAM_ATTR handleButtonPress() { + unsigned long currentTime = millis(); // Get current time + + // Debounce: If the current press is too close to the last one, ignore it + if (currentTime - lastPressTime > 50) { + pressCount++; // Count the button press + + // Check if this is the second press within the double-press interval + if (pressCount == 2 && (currentTime - lastPressTime <= doublePressInterval)) { + doublePressDetected = true; // Double press detected + pressCount = 0; // Reset counter + } + + lastPressTime = currentTime; // Update the time of the last press + } +} + +// Function to switch the boot partition to OTA1 +void setBootPartitionToOTA0() { + const esp_partition_t *ota0_partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_OTA_0, NULL); + + if (ota0_partition) { + // Set OTA1 as new boot partition + esp_ota_set_boot_partition(ota0_partition); + Serial.println("Boot partition changed to OTA0. Restarting..."); + + // Restart to boot from the new partition + esp_restart(); + } else { + Serial.println("OTA1 partition not found!"); + } +} + +void setupDisplay() { + displayEnabled = display.begin(SSD1306_SWITCHCAPVCC, 0x3D); + if (displayEnabled) { + display.display(); + delay(100); + display.clearDisplay(); + } +} + +void displayStatusBar(int progress) { + display.clearDisplay(); + display.setCursor(16, 8); + display.println("Sketch is being"); + display.setCursor(32, 22); + display.println("uploaded!"); + + display.fillRect(0, SCREEN_HEIGHT - 24, SCREEN_WIDTH - 4, 8, BLACK); // Clear status bar area + display.drawRect(0, SCREEN_HEIGHT - 24, SCREEN_WIDTH - 4, 8, WHITE); // Draw border + int filledWidth = (progress * SCREEN_WIDTH - 4) / 100; // Calculate progress width + display.fillRect(1, SCREEN_HEIGHT - 23, filledWidth - 4, 6, WHITE); // Fill progress bar + + display.setCursor((SCREEN_WIDTH / 2) - 12, SCREEN_HEIGHT - 10); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.print(progress); + display.println(" %"); + display.display(); +} + +void displayWelcomeScreen() { + display.clearDisplay(); + + // Draw WiFi symbol + display.drawBitmap(0, 12, epd_bitmap_wifi, 44, 44, WHITE); + + // Display SSID text + display.setCursor(52, 13); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println("Connect"); + display.setCursor(60, 27); + display.println("with:"); + + // Display SSID + display.setCursor(40, 43); + display.setTextSize(1); // Larger text for SSID + display.print(ssid); + + display.display(); +} + +void displaySuccessScreen() { + display.clearDisplay(); + + // Draw WiFi symbol + display.drawBitmap(0, 12, epd_bitmap_checkmark, 44, 44, WHITE); + + // Display SSID text + display.setCursor(48, 22); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println("Successfully"); + display.setCursor(48, 36); + display.println("uploaded!"); + + display.display(); +} + +void wipeDisplay() { + display.clearDisplay(); + display.println(""); + display.display(); +} + +void setupWiFi() { + WiFi.macAddress(mac); + char macLastFour[5]; + snprintf(macLastFour, sizeof(macLastFour), "%02X%02X", mac[4], mac[5]); + ssid = "senseBox:" + String(macLastFour); + + // Define the IP address, gateway, and subnet mask + IPAddress local_IP(192, 168, 1, 1); // The new IP address + IPAddress gateway(192, 168, 1, 1); // Gateway address (can be the same as the AP's IP) + IPAddress subnet(255, 255, 255, 0); // Subnet mask + + // Set the IP address, gateway, and subnet mask of the access point + WiFi.softAPConfig(local_IP, gateway, subnet); + + // Start the access point + WiFi.softAP(ssid.c_str()); +} + +void setupOTA() { + // Handle updating process + server.on( + "/sketch", HTTP_POST, + []() { + server.sendHeader("Connection", "close"); + server.send(200, "text/plain", (Update.hasError()) ? "FAIL" : "OK"); + ESP.restart(); + }, + []() { + HTTPUpload &upload = server.upload(); + + if (upload.status == UPLOAD_FILE_START) { + Serial.setDebugOutput(true); + size_t fsize = UPDATE_SIZE_UNKNOWN; + if (server.clientContentLength() > 0) { + fsize = server.clientContentLength(); + } + Serial.printf("Receiving Update: %s, Size: %d\n", upload.filename.c_str(), fsize); + + Serial.printf("Update: %s\n", upload.filename.c_str()); + if (!Update.begin(fsize)) { //start with max available size + Update.printError(Serial); + } + } else if (upload.status == UPLOAD_FILE_WRITE) { + /* flashing firmware to ESP*/ + if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) { + Update.printError(Serial); + } else { + int progress = (Update.progress() * 100) / Update.size(); + displayStatusBar(progress); // Update progress on status bar + } + } else if (upload.status == UPLOAD_FILE_END) { + if (Update.end(true)) { //true to set the size to the current progress + displaySuccessScreen(); + delay(3000); + wipeDisplay(); + } else { + Update.printError(Serial); + } + Serial.setDebugOutput(false); + } + yield(); + } + ); +} + +void setup() { + // Start Serial communication + Serial.begin(115200); + rgb_led_1.begin(); + rgb_led_1.setBrightness(30); + rgb_led_1.setPixelColor(0, rgb_led_1.Color(51, 51, 255)); + rgb_led_1.show(); + + // Configure button pin as input + pinMode(BUTTON_PIN, INPUT_PULLUP); + + // Interrupt for the button + attachInterrupt(digitalPinToInterrupt(BUTTON_PIN), handleButtonPress, FALLING); + +#ifdef DISPLAY_ENABLED + setupDisplay(); +#endif + setupWiFi(); + // Set the ESP32 as an access point + setupOTA(); + server.begin(); +} + +void loop() { + // Handle client requests + server.handleClient(); + +#ifdef DISPLAY_ENABLED + displayWelcomeScreen(); +#endif + + if (doublePressDetected) { + Serial.println("Double press detected!"); + setBootPartitionToOTA0(); +#ifdef DISPLAY_ENABLED + display.setCursor(0, 0); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println(""); + display.display(); + delay(50); +#endif + // Restart to boot from the new partition + esp_restart(); + } +} diff --git a/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin b/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin new file mode 100644 index 0000000..3e0f1f3 Binary files /dev/null and b/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin differ diff --git a/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv b/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv new file mode 100644 index 0000000..164ba0d --- /dev/null +++ b/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv @@ -0,0 +1,11 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table, 0x8000, 4K + +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 1408K, +ota_1, 0, ota_1, 0x170000, 1408K, +uf2, app, factory,0x2d0000, 256K, +ffat, data, fat, 0x310000, 960K, diff --git a/variants/sensebox_mcu_esp32s2/pins_arduino.h b/variants/sensebox_mcu_esp32s2/pins_arduino.h new file mode 100644 index 0000000..62acb6a --- /dev/null +++ b/variants/sensebox_mcu_esp32s2/pins_arduino.h @@ -0,0 +1,133 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x81B8 +#define USB_MANUFACTURER "senseBox" +#define USB_PRODUCT "MCU-S2 ESP32S2" +#define USB_SERIAL "" // Empty string for MAC address + +// Default USB FirmwareMSC Settings +#define USB_FW_MSC_VENDOR_ID "senseBox" // max 8 chars +#define USB_FW_MSC_PRODUCT_ID "MCU-S2 ESP32S2" // max 16 chars +#define USB_FW_MSC_PRODUCT_REVISION "1.00" // max 4 chars +#define USB_FW_MSC_VOLUME_NAME "senseBox" // max 11 chars +#define USB_FW_MSC_SERIAL_NUMBER 0x00000000 + +#define PIN_RGB_LED 1 // RGB LED +#define RGBLED_PIN 1 // RGB LED +#define RGBLED_NUM 1 // number of RGB LEDs + +// Default I2C QWIIC-Ports +static const uint8_t SDA = 39; +static const uint8_t SCL = 40; +#define PIN_QWIIC_SDA 39 +#define PIN_QWIIC_SCL 40 + +// Secondary I2C MPU6050 +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SCL1 = 42; +static const uint8_t SDA1 = 45; +#define PIN_I2C_SCL 42 +#define PIN_I2C_SDA 45 +#define PIN_I2C_INT 46 + +// SPI +static const uint8_t SS = 42; +static const uint8_t MOSI = 35; +static const uint8_t SCK = 36; +static const uint8_t MISO = 37; + +// XBEE Pins +#define PIN_XBEE_ENABLE 41 +#define PIN_XBEE_INT 33 +#define PIN_XBEE_CS 34 +#define PIN_XBEE_MOSI 35 +#define PIN_XBEE_SCLK 36 +#define PIN_XBEE_MISO 37 +#define PIN_XBEE_RESET 38 +#define PIN_XBEE_TXD 17 +#define PIN_XBEE_RXD 18 + +// Alias XB1 +#define PIN_XB1_ENABLE 41 +#define PIN_XB1_INT 33 +#define PIN_XB1_CS 34 +#define PIN_XB1_MOSI 35 +#define PIN_XB1_SCLK 36 +#define PIN_XB1_MISO 37 +#define PIN_XB1_RESET 38 +#define PIN_XB1_TXD 17 +#define PIN_XB1_RXD 18 + +// IO Pins +#define PIN_LED 1 +#define PIN_IO2 2 +#define PIN_IO3 3 +#define PIN_IO4 4 +#define PIN_IO5 5 +#define PIN_IO6 6 +#define PIN_IO7 7 +#define IO_ENABLE 8 + +static const uint8_t A2 = PIN_IO2; +static const uint8_t A3 = PIN_IO3; +static const uint8_t A4 = PIN_IO4; +static const uint8_t A5 = PIN_IO5; +static const uint8_t A6 = PIN_IO6; +static const uint8_t A7 = PIN_IO7; + +static const uint8_t D2 = PIN_IO2; +static const uint8_t D3 = PIN_IO3; +static const uint8_t D4 = PIN_IO4; +static const uint8_t D5 = PIN_IO5; +static const uint8_t D6 = PIN_IO6; +static const uint8_t D7 = PIN_IO7; + +// UART Port +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define PIN_UART_TXD 43 +#define PIN_UART_RXD 44 +#define PIN_UART_ENABLE 26 + +// UART XBee +static const uint8_t TX1 = 17; +static const uint8_t RX1 = 18; + +// PD-Sensor +#define PD_SENSE 14 +#define PD_ENABLE 21 +#define PIN_PD_ENABLE 21 + +// SD-Card +#define VSPI_MISO 13 +#define VSPI_MOSI 11 +#define VSPI_SCLK 12 +#define VSPI_SS 10 +#define SD_ENABLE 9 + +#define PIN_SD_ENABLE 9 +#define PIN_SD_CS 10 +#define PIN_SD_MOSI 11 +#define PIN_SD_SCLK 12 +#define PIN_SD_MISO 13 + +// USB +#define PIN_USB_DM 19 +#define PIN_USB_DP 20 + +// Touch Pins +static const uint8_t T2 = PIN_IO2; +static const uint8_t T3 = PIN_IO3; +static const uint8_t T4 = PIN_IO4; +static const uint8_t T5 = PIN_IO5; +static const uint8_t T6 = PIN_IO6; +static const uint8_t T7 = PIN_IO7; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sensebox_mcu_esp32s2/tinyuf2.bin b/variants/sensebox_mcu_esp32s2/tinyuf2.bin new file mode 100644 index 0000000..bdc4d83 Binary files /dev/null and b/variants/sensebox_mcu_esp32s2/tinyuf2.bin differ diff --git a/variants/sensebox_mcu_esp32s2/variant.cpp b/variants/sensebox_mcu_esp32s2/variant.cpp new file mode 100644 index 0000000..aa1eb3d --- /dev/null +++ b/variants/sensebox_mcu_esp32s2/variant.cpp @@ -0,0 +1,72 @@ +#include "esp32-hal-gpio.h" +#include "pins_arduino.h" +#include "esp_partition.h" +#include "esp_system.h" +#include "esp_ota_ops.h" +#include "esp_log.h" +#include + +extern "C" { + +// Initialize variant/board, called before setup() +void initVariant(void) { + //enable IO Pins by default + pinMode(IO_ENABLE, OUTPUT); + digitalWrite(IO_ENABLE, LOW); + + //reset RGB + pinMode(PIN_RGB_LED, OUTPUT); + digitalWrite(PIN_RGB_LED, LOW); + + //enable XBEE by default + pinMode(PIN_XB1_ENABLE, OUTPUT); + digitalWrite(PIN_XB1_ENABLE, LOW); + + //enable UART only for chip without PSRAM + esp_chip_info_t chip_info; + esp_chip_info(&chip_info); + if (chip_info.revision <= 0) { + pinMode(PIN_UART_ENABLE, OUTPUT); + digitalWrite(PIN_UART_ENABLE, LOW); + } + + //enable PD-Sensor by default + pinMode(PD_ENABLE, OUTPUT); + digitalWrite(PD_ENABLE, HIGH); + + // define button pin + const int PIN_BUTTON = 0; + pinMode(PIN_BUTTON, INPUT_PULLUP); + + // keep button pressed + unsigned long pressStartTime = 0; + bool buttonPressed = false; + + // Wait 5 seconds for the button to be pressed + unsigned long startTime = millis(); + + // Check if button is pressed + while (millis() - startTime < 5000) { + if (digitalRead(PIN_BUTTON) == LOW) { + if (!buttonPressed) { + // The button was pressed + buttonPressed = true; + } + } else if (buttonPressed) { + // When the button is pressed and then released, boot into the OTA1 partition + const esp_partition_t *ota1_partition = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_OTA_1, NULL); + + if (ota1_partition) { + esp_err_t err = esp_ota_set_boot_partition(ota1_partition); + if (err == ESP_OK) { + esp_restart(); // restart, to boot OTA1 partition + } else { + ESP_LOGE("OTA", "Error setting OTA1 partition: %s", esp_err_to_name(err)); + } + } + // Abort after releasing the button + break; + } + } +} +} diff --git a/variants/soldered_nula_deepsleep_esp32s3/pins_arduino.h b/variants/soldered_nula_deepsleep_esp32s3/pins_arduino.h new file mode 100644 index 0000000..9819aa4 --- /dev/null +++ b/variants/soldered_nula_deepsleep_esp32s3/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x82fc + +#define PIN_RGB_LED 2 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/soldered_nula_mini_esp32c6/pins_arduino.h b/variants/soldered_nula_mini_esp32c6/pins_arduino.h new file mode 100644 index 0000000..058ebdd --- /dev/null +++ b/variants/soldered_nula_mini_esp32c6/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 23; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t USER_BTN = 9; + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 3; +static const uint8_t MISO = 4; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sonoff_dualr3/pins_arduino.h b/variants/sonoff_dualr3/pins_arduino.h new file mode 100644 index 0000000..e7d6c6c --- /dev/null +++ b/variants/sonoff_dualr3/pins_arduino.h @@ -0,0 +1,19 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t BUTTON = 0; +static const uint8_t LED_LINK = 13; +static const uint8_t RELAY_2 = 14; +static const uint8_t RELAY_1 = 27; +static const uint8_t SWITCH_2 = 33; +static const uint8_t SWITCH_1 = 32; + +static const uint8_t CSE7761_TX = 25; +static const uint8_t CSE7761_RX = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_esp32_iot_redboard/pins_arduino.h b/variants/sparkfun_esp32_iot_redboard/pins_arduino.h new file mode 100644 index 0000000..f6226fd --- /dev/null +++ b/variants/sparkfun_esp32_iot_redboard/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +static const uint8_t LED_BUILTIN = 18; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +#define RGB_LED_PIN 2 //WS2812 LED +static const uint8_t RGB_BUILTIN = (SOC_GPIO_PIN_COUNT + RGB_LED_PIN); +#define RGB_BUILTIN RGB_BUILTIN // necessary to make digitalWrite/digitalMode find it +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h b/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h new file mode 100644 index 0000000..ca021a1 --- /dev/null +++ b/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h @@ -0,0 +1,31 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = 23; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 3; +static const uint8_t MISO = 4; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h b/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h new file mode 100644 index 0000000..61c939a --- /dev/null +++ b/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 23 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 20; +static const uint8_t MISO = 21; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h b/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h new file mode 100644 index 0000000..7c5e0c1 --- /dev/null +++ b/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +//#define USB_VID 0x303A +//#define USB_PID 0x1001 +//#define USB_MANUFACTURER "Sparkfun" +//#define USB_PRODUCT "ESP32-S3 Thing Plus" +#define USB_SERIAL "" + +#define LED_PIN 46 //Pin 46 on Thing Plus C S3 is connected to WS2812 LED +#define COLOR_ORDER GRB +#define CHIPSET WS2812 +#define NUM_LEDS 1 +#define BRIGHTNESS 25 +#define LED_BUILTIN LED_PIN +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t LED = LED_PIN; +static const uint8_t STAT_LED = 0; +static const uint8_t BTN = 0; +static const uint8_t Q_EN = 45; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SS = 10; +static const uint8_t MISO = 13; //POCI +static const uint8_t MOSI = 11; //PICO +static const uint8_t SCK = 12; + +static const uint8_t SCL = 9; +static const uint8_t SDA = 8; + +static const uint8_t A0 = 10; +static const uint8_t A1 = 14; +static const uint8_t A2 = 15; +static const uint8_t A3 = 16; +static const uint8_t A4 = 17; +static const uint8_t A5 = 18; + +static const uint8_t GPIO0 = 21; +static const uint8_t GPIO1 = 7; +static const uint8_t GPIO2 = 6; +static const uint8_t GPIO3 = 5; +static const uint8_t GPIO4 = 4; +static const uint8_t GPIO5 = 2; +static const uint8_t GPIO6 = 1; + +static const uint8_t FREEBIE = 42; + +static const uint8_t SDIO_DET = 48; +static const uint8_t SDIO0 = 39; +static const uint8_t SDIO1 = 40; +static const uint8_t SDIO2 = 47; +static const uint8_t SDIO3 = 33; +static const uint8_t SDIO_CLK = 38; +static const uint8_t SDIO_CMD = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h b/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h new file mode 100644 index 0000000..589b72e --- /dev/null +++ b/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const int LED_BUILTIN = 17; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 16; +static const uint8_t MOSI = 13; +static const uint8_t MISO = 12; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h b/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h new file mode 100644 index 0000000..4ad646f --- /dev/null +++ b/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h @@ -0,0 +1,48 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x1B4F +#define USB_PID 0x0035 +#define USB_MANUFACTURER "SparkFun" +#define USB_PRODUCT "SparkFun_Pro_Micro-ESP32C3" +#define USB_SERIAL "" // Empty string for MAC address + +static const uint8_t LED_BUILTIN = 10; + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 6; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 3; +static const uint8_t MISO = 1; +static const uint8_t SCK = 0; + +static const uint8_t PIN_I2S_SCK = 6; // Frame clock, no bit clock +static const uint8_t PIN_I2S_SD_DOUT = 7; // data out +static const uint8_t PIN_I2S_SD_IN = 5; // data in +static const uint8_t PIN_I2S_FS = 10; // frame select + +#endif /* Pins_Arduino_h */ diff --git a/variants/tamc_termod_s3/pins_arduino.h b/variants/tamc_termod_s3/pins_arduino.h new file mode 100644 index 0000000..4e989c8 --- /dev/null +++ b/variants/tamc_termod_s3/pins_arduino.h @@ -0,0 +1,103 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +// This board has no NeoLED or any User LED + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t BAT_LV = 1; +#define BAT_VOLT_PIN BAT_LV +static const uint8_t CHG = 2; +static const uint8_t TFT_CS = 10; +static const uint8_t TFT_DC = 18; +static const uint8_t TFT_RST = 14; +static const uint8_t TFT_BCKL = 48; // TFT Backlight is enabled by soldering JP2 together +static const uint8_t SD_CS = 21; +static const uint8_t SD_CD = 47; // uSD Card Detect is enabled by soldering JP1 together. + +#define DISPLAY_PORTRAIT 2 +#define DISPLAY_LANDSCAPE 3 +#define DISPLAY_PORTRAIT_FLIP 0 +#define DISPLAY_LANDSCAPE_FLIP 1 + +#define DISPLAY_WIDTH 240 +#define DISPLAY_HEIGHT 320 + +/** + * Get battery voltage in volts + * @return Battery voltage in volts + */ +float getBatteryVoltage(); +/** + * Get battery level in percent + * @return Battery level in percent(0-100) + */ +float getBatteryCapacity(); +/** + * Get battery charge state + * @return Battery charge state(true=charging, false=not charging) + */ +bool getChargingState(); +/** + * Set on charge start callback + * @param func On charge start Callback function + */ +void setOnChargeStart(void (*func)()); +/** + * Set on charge end callback + * @param func On charge end Callback function + */ +void setOnChargeEnd(void (*func)()); + +#endif /* Pins_Arduino_h */ diff --git a/variants/tamc_termod_s3/variant.cpp b/variants/tamc_termod_s3/variant.cpp new file mode 100644 index 0000000..cc255c3 --- /dev/null +++ b/variants/tamc_termod_s3/variant.cpp @@ -0,0 +1,43 @@ +#include "Arduino.h" +#include "pins_arduino.h" + +float getBatteryVoltage() { + int analogVolt = analogReadMilliVolts(1); + float voltage = analogVolt / 1000.0; + voltage = voltage * (100.0 + 200.0) / 200.0; + return voltage; +} + +float getBatteryCapacity() { + float voltage = getBatteryVoltage(); + float capacity = (voltage - 3.3) / (4.2 - 3.3) * 100.0; + capacity = constrain(capacity, 0, 100); + return capacity; +} + +bool getChargingState() { + return !digitalRead(CHG); +} + +void (*__onChargeStart__)(); +void (*__onChargeEnd__)(); +void setOnChargeStart(void (*func)()) { + __onChargeStart__ = func; +} +void setOnChargeEnd(void (*func)()) { + __onChargeEnd__ = func; +} + +void ARDUINO_ISR_ATTR chargeIsr() { + if (getChargingState()) { + __onChargeStart__(); + } else { + __onChargeEnd__(); + } +} + +extern "C" void initVariant(void) { + pinMode(CHG, INPUT_PULLUP); + attachInterrupt(CHG, chargeIsr, CHANGE); + analogReadResolution(12); +} diff --git a/variants/tbeam/pins_arduino.h b/variants/tbeam/pins_arduino.h new file mode 100644 index 0000000..4be8494 --- /dev/null +++ b/variants/tbeam/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 18 // GPIO18 - SX1276 CS +#define LORA_RST 23 // GPIO23 - SX1276 RST +#define LORA_IRQ 26 // GPIO26 - SX1276 IO0 +#define LORA_IO0 LORA_IRQ // alias +#define LORA_IO1 33 // GPIO33 - SX1276 IO1 -> wired on pcb AND connected to header pin LORA1 +#define LORA_IO2 32 // GPIO32 - SX1276 IO2 -> wired on pcb AND connected to header pin LORA2 + +static const uint8_t KEY_BUILTIN = 39; + +static const uint8_t LED_BUILTIN = 14; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A14 = 13; +static const uint8_t A16 = 14; +static const uint8_t A18 = 25; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T4 = 13; +static const uint8_t T6 = 14; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; + +#endif /* Pins_Arduino_h */ diff --git a/variants/thingpulse_epulse_feather/pins_arduino.h b/variants/thingpulse_epulse_feather/pins_arduino.h new file mode 100644 index 0000000..92a421e --- /dev/null +++ b/variants/thingpulse_epulse_feather/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = -1; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t MOSI = 18; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; +static const uint8_t SS = -1; + +// mapping to match other feathers and also in order +static const uint8_t A0 = 26; +static const uint8_t A1 = 25; +static const uint8_t A2 = 34; +static const uint8_t A3 = 39; +static const uint8_t A4 = 36; +static const uint8_t A5 = 4; +static const uint8_t A6 = 14; +static const uint8_t A7 = 32; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +// vbat measure +static const uint8_t BATT_MONITOR = 35; // Note: voltage divider 2.2M/4.7M +#define BAT_VOLT_PIN BATT_MONITOR +static const uint8_t A13 = 35; +//static const uint8_t Ax = 0; // not used/available +//static const uint8_t Ax = 2; // not used/available? GPIO02 is available! + +// touch inputs +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/thingpulse_epulse_feather_c6/pins_arduino.h b/variants/thingpulse_epulse_feather_c6/pins_arduino.h new file mode 100644 index 0000000..55afea9 --- /dev/null +++ b/variants/thingpulse_epulse_feather_c6/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 19; +static const uint8_t MISO = 20; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-lora32-v1/pins_arduino.h b/variants/ttgo-lora32-v1/pins_arduino.h new file mode 100644 index 0000000..85bfe5f --- /dev/null +++ b/variants/ttgo-lora32-v1/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// I2C OLED Display works with SSD1306 driver +#define OLED_SDA 4 +#define OLED_SCL 15 +#define OLED_RST 16 + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 18 // GPIO18 - SX1276 CS +#define LORA_RST 14 // GPIO14 - SX1276 RST +#define LORA_IRQ 26 // GPIO26 - SX1276 IRQ (interrupt request) + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-lora32-v2/pins_arduino.h b/variants/ttgo-lora32-v2/pins_arduino.h new file mode 100644 index 0000000..7e29ee9 --- /dev/null +++ b/variants/ttgo-lora32-v2/pins_arduino.h @@ -0,0 +1,75 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// I2C OLED Display works with SSD1306 driver +#define OLED_SDA 21 +#define OLED_SCL 22 +#define OLED_RST 16 + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 18 // GPIO18 - SX1276 CS +#define LORA_RST 12 // GPIO14 - SX1276 RST +#define LORA_IRQ 26 // GPIO26 - SX1276 IRQ (interrupt request) + +// SD card +#define SD_SCK 14 +#define SD_MISO 2 +#define SD_MOSI 15 +#define SD_CS 13 + +static const uint8_t LED_BUILTIN = 22; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-lora32-v21new/pins_arduino.h b/variants/ttgo-lora32-v21new/pins_arduino.h new file mode 100644 index 0000000..06bb27e --- /dev/null +++ b/variants/ttgo-lora32-v21new/pins_arduino.h @@ -0,0 +1,83 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/************************* +* Definitions for TTGO-Lora32-V2.1.6 Boards +* Labeled with T3 v1.6 20180606 +* or sold as TTGO-LoRa32 2.1 Revision 1.6 +************************/ + +#include + +// I2C OLED Display works with SSD1306 driver +#define OLED_SDA 21 +#define OLED_SCL 22 +#define OLED_RST 16 + +// SPI LoRa Radio +#define LORA_SCK 5 // GPIO5 - SX1276 SCK +#define LORA_MISO 19 // GPIO19 - SX1276 MISO +#define LORA_MOSI 27 // GPIO27 - SX1276 MOSI +#define LORA_CS 18 // GPIO18 - SX1276 CS +#define LORA_RST 23 // GPIO23 - SX1276 RST +#define LORA_IRQ 26 // GPIO26 - SX1276 IRQ (interrupt request) +#define LORA_D1 33 // GPIO33 - SX1276 IO1 (for LMIC Arduino library) +#define LORA_D2 32 // GPIO32 - SX1276 IO2 + +// SD card +#define SD_SCK 14 +#define SD_MISO 2 +#define SD_MOSI 15 +#define SD_CS 13 + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 27; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-t-oi-plus/pins_arduino.h b/variants/ttgo-t-oi-plus/pins_arduino.h new file mode 100644 index 0000000..e34c921 --- /dev/null +++ b/variants/ttgo-t-oi-plus/pins_arduino.h @@ -0,0 +1,28 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 3; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 19; +static const uint8_t SCL = 18; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A1 = 2; +static const uint8_t A2 = 4; +static const uint8_t A3 = 5; + +static const uint8_t BAT_ADC_PIN = 2; +#define BAT_VOLT_PIN BAT_ADC_PIN + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-t1/pins_arduino.h b/variants/ttgo-t1/pins_arduino.h new file mode 100644 index 0000000..b8da346 --- /dev/null +++ b/variants/ttgo-t1/pins_arduino.h @@ -0,0 +1,55 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t LED_BUILTIN = 22; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 21; +// Despite the many diagrams from TTGO showing SCL on pin 22, due to the on-board LED +// also on this pin it is better to shift to 23 instead to avoid issues. +static const uint8_t SCL = 23; + +// These are the settings used for the on-board SD card slot +static const uint8_t SS = 13; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-t7-v13-mini32/pins_arduino.h b/variants/ttgo-t7-v13-mini32/pins_arduino.h new file mode 100644 index 0000000..23a98d7 --- /dev/null +++ b/variants/ttgo-t7-v13-mini32/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t LED_BUILTIN = 22; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ttgo-t7-v14-mini32/pins_arduino.h b/variants/ttgo-t7-v14-mini32/pins_arduino.h new file mode 100644 index 0000000..f3ebba9 --- /dev/null +++ b/variants/ttgo-t7-v14-mini32/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t LED_BUILTIN = 19; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/turta_iot_node/pins_arduino.h b/variants/turta_iot_node/pins_arduino.h new file mode 100644 index 0000000..e5fbc40 --- /dev/null +++ b/variants/turta_iot_node/pins_arduino.h @@ -0,0 +1,66 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// LED +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +// UART +static const uint8_t TX = 10; +static const uint8_t RX = 9; + +// I2C +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +// SPI +static const uint8_t SS = 21; +static const uint8_t MOSI = 18; +static const uint8_t MISO = 19; +static const uint8_t SCK = 5; + +// Analog Inputs +static const uint8_t A0 = 4; +static const uint8_t A1 = 25; +static const uint8_t A2 = 26; +static const uint8_t A3 = 27; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A8 = 38; + +// Right side +static const uint8_t T0 = 4; +static const uint8_t T1 = 25; +static const uint8_t T2 = 26; +static const uint8_t T3 = 27; +static const uint8_t T4 = 32; +static const uint8_t T5 = 33; +static const uint8_t T6 = 34; +static const uint8_t T7 = 35; + +// Left side +static const uint8_t T8 = 22; +static const uint8_t T9 = 23; +static const uint8_t T10 = 10; +static const uint8_t T11 = 9; +static const uint8_t T12 = 21; +static const uint8_t T13 = 5; +static const uint8_t T14 = 18; +static const uint8_t T15 = 19; + +// Module +static const uint8_t T16 = 37; +static const uint8_t T17 = 14; +static const uint8_t T18 = 2; +static const uint8_t T19 = 38; + +// DAC +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/twatch/pins_arduino.h b/variants/twatch/pins_arduino.h new file mode 100644 index 0000000..1d69ae5 --- /dev/null +++ b/variants/twatch/pins_arduino.h @@ -0,0 +1,35 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +// touch screen +#define TP_SDA 23 +#define TP_SCL 32 +#define TP_INT 38 + +// Interrupt IO port +#define RTC_INT 37 +#define APX20X_INT 35 +#define BMA42X_INT1 39 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +//Serial1 Already assigned to GPS LORA +#define TX1 33 +#define RX1 34 + +// Already assigned to BMA423 PCF8563 and external extensions +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; +// SPI has been configured as an SD card slot and must be removed when downloading +static const uint8_t SS = 13; +static const uint8_t MOSI = 15; +static const uint8_t MISO = 2; +static const uint8_t SCK = 14; +// Externally programmable IO +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/twinaiot/pins_arduino.h b/variants/twinaiot/pins_arduino.h new file mode 100644 index 0000000..a08f3b7 --- /dev/null +++ b/variants/twinaiot/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define RGB_PIN 15 + +static const uint8_t LED_BUILTIN = 35; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN RGB_PIN + +static const uint8_t TX = 39; +static const uint8_t RX = 40; + +static const uint8_t SDA = 39; +static const uint8_t SCL = 40; + +static const uint8_t SS = 1; +static const uint8_t MOSI = 2; +static const uint8_t MISO = 3; +static const uint8_t SCK = 4; + +static const uint8_t D6_OUT_PIN = 35; +static const uint8_t D9_OUT_PIN = 36; +static const uint8_t D10_OUT_PIN = 10; + +static const uint8_t TOUCH_PIN = 13; + +static const uint8_t TRIG_PIN = 5; // GPIO connected to HC-SR04 TRIG +static const uint8_t ECHO_PIN = 6; // GPIO connected to HC-SR04 ECHO + +static const uint8_t latchPin = 34; +static const uint8_t clockPin = 47; +static const uint8_t dataPin = 48; + +static const uint8_t D_IN_4 = 8; +static const uint8_t D_IN_8 = 11; +static const uint8_t D_IN_12 = 9; + +static const uint8_t AN_IN_4 = 17; +static const uint8_t AN_IN_8 = 16; +static const uint8_t AN_IN_12 = 7; + +static const uint8_t S1pin = 37; +static const uint8_t S2pin = 38; +static const uint8_t S3pin = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_edu_esp32/pins_arduino.h b/variants/uPesy_edu_esp32/pins_arduino.h new file mode 100644 index 0000000..c3349d9 --- /dev/null +++ b/variants/uPesy_edu_esp32/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 33; +static const uint8_t A1 = 32; +static const uint8_t A2 = 35; +static const uint8_t A3 = 34; +static const uint8_t A4 = 36; +static const uint8_t A5 = 39; + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN + +#define PIN_WIRE_SDA SDA // backward compatibility +#define PIN_WIRE_SCL SCL // backward compatibility + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 26; +static const uint8_t D3 = 25; +static const uint8_t D4 = 17; +static const uint8_t D5 = 16; +static const uint8_t D6 = 27; +static const uint8_t D7 = 14; +static const uint8_t D8 = 12; +static const uint8_t D9 = 13; +static const uint8_t D10 = 5; +static const uint8_t D11 = 23; +static const uint8_t D12 = 19; +static const uint8_t D13 = 18; + +#define PIN_SPI_SS SS // backward compatibility +#define PIN_SPI_MOSI MOSI // backward compatibility +#define PIN_SPI_MISO MISO // backward compatibility +#define PIN_SPI_SCK SCK // backward compatibility + +#define PIN_A0 A0 // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_esp32_wroom_devkit/pins_arduino.h b/variants/uPesy_esp32_wroom_devkit/pins_arduino.h new file mode 100644 index 0000000..8e1d004 --- /dev/null +++ b/variants/uPesy_esp32_wroom_devkit/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_esp32_wrover_devkit/pins_arduino.h b/variants/uPesy_esp32_wrover_devkit/pins_arduino.h new file mode 100644 index 0000000..8e1d004 --- /dev/null +++ b/variants/uPesy_esp32_wrover_devkit/pins_arduino.h @@ -0,0 +1,52 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_esp32c3_basic/pins_arduino.h b/variants/uPesy_esp32c3_basic/pins_arduino.h new file mode 100644 index 0000000..6dcabdf --- /dev/null +++ b/variants/uPesy_esp32c3_basic/pins_arduino.h @@ -0,0 +1,33 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x8195 +#define USB_MANUFACTURER "uPesy Electronics" +#define USB_PRODUCT "uPesy ESP32C3 Basic" +#define USB_SERIAL "" + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 3; +static const uint8_t SCL = 10; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +static const uint8_t VBAT_SENSE = 0; +#define BAT_VOLT_PIN VBAT_SENSE + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_esp32c3_mini/pins_arduino.h b/variants/uPesy_esp32c3_mini/pins_arduino.h new file mode 100644 index 0000000..a2c3e1f --- /dev/null +++ b/variants/uPesy_esp32c3_mini/pins_arduino.h @@ -0,0 +1,32 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x819B +#define USB_MANUFACTURER "uPesy Electronics" +#define USB_PRODUCT "uPesy ESP32C3 Mini" +#define USB_SERIAL "" + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 3; +static const uint8_t SCL = 10; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +static const uint8_t VBAT_SENSE = 0; +#define BAT_VOLT_PIN VBAT_SENSE + +#endif /* Pins_Arduino_h */ diff --git a/variants/uPesy_esp32s3_basic/pins_arduino.h b/variants/uPesy_esp32s3_basic/pins_arduino.h new file mode 100644 index 0000000..85d9c2c --- /dev/null +++ b/variants/uPesy_esp32s3_basic/pins_arduino.h @@ -0,0 +1,79 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8192 +#define USB_MANUFACTURER "uPesy Electronics" +#define USB_PRODUCT "uPesy ESP32S3 Basic" +#define USB_SERIAL "" + +static const uint8_t RGB_DATA = 38; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +static const uint8_t TX0 = 43; +static const uint8_t RX0 = 44; + +static const uint8_t TX1 = 17; +static const uint8_t RX1 = 18; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t MTMS = 42; +static const uint8_t MTDI = 41; +static const uint8_t MTDO = 40; +static const uint8_t MTCK = 39; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_bling/bootloader_tinyuf2.bin b/variants/um_bling/bootloader_tinyuf2.bin new file mode 100644 index 0000000..847c813 Binary files /dev/null and b/variants/um_bling/bootloader_tinyuf2.bin differ diff --git a/variants/um_bling/partitions_tinyuf2.csv b/variants/um_bling/partitions_tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/um_bling/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/um_bling/pins_arduino.h b/variants/um_bling/pins_arduino.h new file mode 100644 index 0000000..0e09f46 --- /dev/null +++ b/variants/um_bling/pins_arduino.h @@ -0,0 +1,81 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x817F +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "BLING!" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 21; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t SD_CS = 21; +static const uint8_t SD_DETECT = 38; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t BUTTON_A = 11; +static const uint8_t BUTTON_B = 10; +static const uint8_t BUTTON_C = 33; +static const uint8_t BUTTON_D = 34; + +static const uint8_t VBAT_SENSE = 17; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 16; + +static const uint8_t I2S_MIC_SEL = 39; +static const uint8_t I2S_MIC_WS = 40; +static const uint8_t I2S_MIC_DATA = 41; +static const uint8_t I2S_MIC_BCLK = 42; + +static const uint8_t I2S_AMP_SD = 4; +static const uint8_t I2S_AMP_DATA = 3; +static const uint8_t I2S_AMP_BCLK = 2; +static const uint8_t I2S_AMP_WS = 1; + +static const uint8_t RTC_INT = 7; + +static const uint8_t RGB_DATA = 18; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 6; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_bling/tinyuf2.bin b/variants/um_bling/tinyuf2.bin new file mode 100644 index 0000000..c5ef0c3 Binary files /dev/null and b/variants/um_bling/tinyuf2.bin differ diff --git a/variants/um_edges3_d/pins_arduino.h b/variants/um_edges3_d/pins_arduino.h new file mode 100644 index 0000000..f54ceb5 --- /dev/null +++ b/variants/um_edges3_d/pins_arduino.h @@ -0,0 +1,46 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x82DC +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "EdgeS3[D]" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_feathers2/pins_arduino.h b/variants/um_feathers2/pins_arduino.h new file mode 100644 index 0000000..c108c49 --- /dev/null +++ b/variants/um_feathers2/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x239A +#define USB_PID 0x80AB +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "FeatherS2" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t LDO_2_POWER = 21; + +static const uint8_t APA_DATA = 40; +static const uint8_t APA_CLK = 45; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_feathers2neo/pins_arduino.h b/variants/um_feathers2neo/pins_arduino.h new file mode 100644 index 0000000..08434f5 --- /dev/null +++ b/variants/um_feathers2neo/pins_arduino.h @@ -0,0 +1,71 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x239A +#define USB_PID 0x80B4 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "FeatherS2 Neo" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 14; +static const uint8_t A3 = 12; +static const uint8_t A4 = 6; +static const uint8_t A5 = 5; +static const uint8_t A6 = 1; +static const uint8_t A7 = 3; +static const uint8_t A8 = 7; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; + +static const uint8_t T1 = 1; +static const uint8_t T3 = 3; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t NEOPIXEL_MATRIX_DATA = 21; +static const uint8_t NEOPIXEL_MATRIX_PWR = 4; + +static const uint8_t NEOPIXEL_DATA = 40; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (NEOPIXEL_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t NEOPIXEL_PWR = 39; + +static const uint8_t VBAT_SENSE = 2; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_feathers3/bootloader_tinyuf2.bin b/variants/um_feathers3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..5a2cde3 Binary files /dev/null and b/variants/um_feathers3/bootloader_tinyuf2.bin differ diff --git a/variants/um_feathers3/partitions_tinyuf2.csv b/variants/um_feathers3/partitions_tinyuf2.csv new file mode 100644 index 0000000..003418c --- /dev/null +++ b/variants/um_feathers3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/variants/um_feathers3/pins_arduino.h b/variants/um_feathers3/pins_arduino.h new file mode 100644 index 0000000..594d979 --- /dev/null +++ b/variants/um_feathers3/pins_arduino.h @@ -0,0 +1,73 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80D6 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "FeatherS3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +#define WIRE1_PIN_DEFINED 1 // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin) +static const uint8_t SDA1 = 16; +static const uint8_t SCL1 = 15; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; + +static const uint8_t T1 = 1; +static const uint8_t T3 = 3; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T14 = 14; + +static const uint8_t VBAT_SENSE = 2; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 34; + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t RGB_DATA = 40; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t RGB_PWR = 39; +static const uint8_t LDO2 = 39; +static const uint8_t LED = 13; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_feathers3/tinyuf2.bin b/variants/um_feathers3/tinyuf2.bin new file mode 100644 index 0000000..1780447 Binary files /dev/null and b/variants/um_feathers3/tinyuf2.bin differ diff --git a/variants/um_feathers3neo/pins_arduino.h b/variants/um_feathers3neo/pins_arduino.h new file mode 100644 index 0000000..de177c0 --- /dev/null +++ b/variants/um_feathers3neo/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x81FB +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "FeatherS3 Neo" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 17; +static const uint8_t A1 = 18; +static const uint8_t A2 = 14; +static const uint8_t A3 = 12; +static const uint8_t A4 = 6; +static const uint8_t A5 = 5; +static const uint8_t A6 = 1; +static const uint8_t A7 = 3; +static const uint8_t A8 = 7; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 8; +static const uint8_t A12 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T3 = 3; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T14 = 14; + +static const uint8_t VBAT_SENSE = 2; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 15; + +// User LED +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t RGB_DATA = 40; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 + +static const uint8_t RGB_PWR = 39; +static const uint8_t RGB_MATRIX_PWR = 39; +static const uint8_t RGB_MATRIX_DATA = 16; +static const uint8_t LED = 13; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_nanos3/bootloader_tinyuf2.bin b/variants/um_nanos3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..e89596f Binary files /dev/null and b/variants/um_nanos3/bootloader_tinyuf2.bin differ diff --git a/variants/um_nanos3/partitions_tinyuf2.csv b/variants/um_nanos3/partitions_tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/um_nanos3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/um_nanos3/pins_arduino.h b/variants/um_nanos3/pins_arduino.h new file mode 100644 index 0000000..66aef21 --- /dev/null +++ b/variants/um_nanos3/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8179 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "Nanos3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t RGB_DATA = 41; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 42; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_nanos3/tinyuf2.bin b/variants/um_nanos3/tinyuf2.bin new file mode 100644 index 0000000..b2723dc Binary files /dev/null and b/variants/um_nanos3/tinyuf2.bin differ diff --git a/variants/um_omgs3/bootloader_tinyuf2.bin b/variants/um_omgs3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..84bab25 Binary files /dev/null and b/variants/um_omgs3/bootloader_tinyuf2.bin differ diff --git a/variants/um_omgs3/partitions_tinyuf2.csv b/variants/um_omgs3/partitions_tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/um_omgs3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/um_omgs3/pins_arduino.h b/variants/um_omgs3/pins_arduino.h new file mode 100644 index 0000000..81164c4 --- /dev/null +++ b/variants/um_omgs3/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8224 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "OMGS3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 3; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SDO = 6; +static const uint8_t SDI = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t VBUS_SENSE = 33; + +static const uint8_t RGB_DATA = 35; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 34; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_omgs3/tinyuf2.bin b/variants/um_omgs3/tinyuf2.bin new file mode 100644 index 0000000..fccd290 Binary files /dev/null and b/variants/um_omgs3/tinyuf2.bin differ diff --git a/variants/um_pros3/bootloader_tinyuf2.bin b/variants/um_pros3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..e92ef2b Binary files /dev/null and b/variants/um_pros3/bootloader_tinyuf2.bin differ diff --git a/variants/um_pros3/partitions_tinyuf2.csv b/variants/um_pros3/partitions_tinyuf2.csv new file mode 100644 index 0000000..003418c --- /dev/null +++ b/variants/um_pros3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 11968K, diff --git a/variants/um_pros3/pins_arduino.h b/variants/um_pros3/pins_arduino.h new file mode 100644 index 0000000..59600e7 --- /dev/null +++ b/variants/um_pros3/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80D3 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "ProS3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t VBAT_SENSE = 10; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 33; + +static const uint8_t RGB_DATA = 18; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 17; +static const uint8_t LDO2 = 17; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_pros3/tinyuf2.bin b/variants/um_pros3/tinyuf2.bin new file mode 100644 index 0000000..1e8ee8c Binary files /dev/null and b/variants/um_pros3/tinyuf2.bin differ diff --git a/variants/um_squixl/pins_arduino.h b/variants/um_squixl/pins_arduino.h new file mode 100644 index 0000000..4546cdb --- /dev/null +++ b/variants/um_squixl/pins_arduino.h @@ -0,0 +1,23 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x82DF +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "SQUiXL" +#define USB_SERIAL "" + +static const uint8_t SDA = 1; +static const uint8_t SCL = 2; + +static const uint8_t SS = 42; +static const uint8_t MOSI = 46; +static const uint8_t MISO = 41; +static const uint8_t SDO = 46; +static const uint8_t SDI = 41; +static const uint8_t SCK = 45; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_tinyc6/pins_arduino.h b/variants/um_tinyc6/pins_arduino.h new file mode 100644 index 0000000..21e4f42 --- /dev/null +++ b/variants/um_tinyc6/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x1001 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "TinyC6" +#define USB_SERIAL "" + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 6; +static const uint8_t SCL = 7; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 21; +static const uint8_t MISO = 20; +static const uint8_t SDO = 21; +static const uint8_t SDI = 20; +static const uint8_t SCK = 19; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t VBAT_SENSE = 4; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 10; + +static const uint8_t RGB_DATA = 23; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 22; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_tinypico/pins_arduino.h b/variants/um_tinypico/pins_arduino.h new file mode 100644 index 0000000..ce7f6dd --- /dev/null +++ b/variants/um_tinypico/pins_arduino.h @@ -0,0 +1,54 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SDO = 23; +static const uint8_t SDI = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +static const uint8_t APA_POWER = 13; +static const uint8_t APA_DATA = 2; +static const uint8_t APA_CLK = 12; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_tinys2/pins_arduino.h b/variants/um_tinys2/pins_arduino.h new file mode 100644 index 0000000..b72215c --- /dev/null +++ b/variants/um_tinys2/pins_arduino.h @@ -0,0 +1,80 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x8001 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "TinyS2" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 14; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +static const uint8_t DAC1 = 17; +static const uint8_t DAC2 = 18; + +static const uint8_t VBAT_SENSE = 3; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 21; + +static const uint8_t RGB_DATA = 1; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 2; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_tinys3/bootloader_tinyuf2.bin b/variants/um_tinys3/bootloader_tinyuf2.bin new file mode 100644 index 0000000..e89596f Binary files /dev/null and b/variants/um_tinys3/bootloader_tinyuf2.bin differ diff --git a/variants/um_tinys3/partitions_tinyuf2.csv b/variants/um_tinys3/partitions_tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/um_tinys3/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/um_tinys3/pins_arduino.h b/variants/um_tinys3/pins_arduino.h new file mode 100644 index 0000000..7bc0d80 --- /dev/null +++ b/variants/um_tinys3/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303A +#define USB_PID 0x80D0 +#define USB_MANUFACTURER "Unexpected Maker" +#define USB_PRODUCT "TinyS3" +#define USB_SERIAL "" + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 34; +static const uint8_t MOSI = 35; +static const uint8_t MISO = 37; +static const uint8_t SDO = 35; +static const uint8_t SDI = 37; +static const uint8_t SCK = 36; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; + +static const uint8_t VBAT_SENSE = 10; +#define BAT_VOLT_PIN VBAT_SENSE +static const uint8_t VBUS_SENSE = 33; + +static const uint8_t RGB_DATA = 18; +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN (RGB_DATA + SOC_GPIO_PIN_COUNT) +#define RGB_BRIGHTNESS 64 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t RGB_PWR = 17; + +#endif /* Pins_Arduino_h */ diff --git a/variants/um_tinys3/tinyuf2.bin b/variants/um_tinys3/tinyuf2.bin new file mode 100644 index 0000000..b2723dc Binary files /dev/null and b/variants/um_tinys3/tinyuf2.bin differ diff --git a/variants/unphone8/pins_arduino.h b/variants/unphone8/pins_arduino.h new file mode 100644 index 0000000..0fcd7d1 --- /dev/null +++ b/variants/unphone8/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x16D0 +#define USB_PID 0x1178 + +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = 37; +static const uint8_t RX = 36; + +static const uint8_t SDA = 1; +static const uint8_t SCL = 2; + +static const uint8_t SS = 3; +static const uint8_t MOSI = 39; +static const uint8_t MISO = 40; +static const uint8_t SCK = 38; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 8; +static const uint8_t A3 = 9; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 14; +static const uint8_t A7 = 7; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 2; +static const uint8_t T2 = 8; +static const uint8_t T3 = 9; +static const uint8_t T4 = 5; +static const uint8_t T5 = 6; +static const uint8_t T6 = 14; +static const uint8_t T7 = 7; +static const uint8_t T8 = 15; +static const uint8_t T9 = 33; +static const uint8_t T10 = 27; +static const uint8_t T11 = 12; +static const uint8_t T12 = 13; +static const uint8_t T13 = 14; +static const uint8_t T14 = 15; + +#endif /* Pins_Arduino_h */ diff --git a/variants/unphone9/pins_arduino.h b/variants/unphone9/pins_arduino.h new file mode 100644 index 0000000..983feb2 --- /dev/null +++ b/variants/unphone9/pins_arduino.h @@ -0,0 +1,69 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x16D0 +#define USB_PID 0x1178 + +#define LED_BUILTIN 13 +#define BUILTIN_LED LED_BUILTIN // backward compatibility + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 3; +static const uint8_t SCL = 4; + +static const uint8_t SS = 13; +static const uint8_t MOSI = 40; +static const uint8_t MISO = 41; +static const uint8_t SCK = 39; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 8; +static const uint8_t A3 = 9; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 14; +static const uint8_t A7 = 7; +static const uint8_t A8 = 15; +static const uint8_t A9 = 33; +static const uint8_t A10 = 27; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 2; +static const uint8_t T2 = 8; +static const uint8_t T3 = 9; +static const uint8_t T4 = 5; +static const uint8_t T5 = 6; +static const uint8_t T6 = 14; +static const uint8_t T7 = 7; +static const uint8_t T8 = 15; +static const uint8_t T9 = 33; +static const uint8_t T10 = 27; +static const uint8_t T11 = 12; +static const uint8_t T12 = 13; +static const uint8_t T13 = 14; +static const uint8_t T14 = 15; + +static const uint8_t D5 = 14; +static const uint8_t D6 = 7; +static const uint8_t D9 = 15; +static const uint8_t D10 = 16; +static const uint8_t D11 = 17; +static const uint8_t D12 = 12; +static const uint8_t D13 = 13; +static const uint8_t D21 = 47; +#define UNPHONE_D_PINS_MAPPED + +#endif /* Pins_Arduino_h */ diff --git a/variants/vintlabsdevkitv1/pins_arduino.h b/variants/vintlabsdevkitv1/pins_arduino.h new file mode 100644 index 0000000..ddffe2d --- /dev/null +++ b/variants/vintlabsdevkitv1/pins_arduino.h @@ -0,0 +1,62 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +// PWM Driver pins for PWM Driver board +static const uint8_t PWM0 = 12; +static const uint8_t PWM1 = 13; +static const uint8_t PWM2 = 14; +static const uint8_t PWM3 = 15; +static const uint8_t PWM4 = 16; +static const uint8_t PWM5 = 17; +static const uint8_t PWM6 = 18; +static const uint8_t PWM7 = 19; + +#endif /* Pins_Arduino_h */ diff --git a/variants/walter/pins_arduino.h b/variants/walter/pins_arduino.h new file mode 100644 index 0000000..53076e7 --- /dev/null +++ b/variants/walter/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303a +#define USB_PID 0x1001 +#define USB_MANUFACTURER "DPTechnics" +#define USB_PRODUCT "Walter" +#define USB_SERIAL "" + +#define MODEM_TX 48 // Sequans modem UART0 TX +#define MODEM_RX 14 // Sequans modem UART0 RX +#define MODEM_CTS 47 // Sequans modem UART0 CTS +#define MODEM_RTS 19 // Sequans modem UART0 RTS +#define MODEM_RESET 45 // Sequans modem reset signal +#define MODEM_WAKE 46 // Sequans modem wake signal + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; + +#endif /* Pins_Arduino_h */ diff --git a/variants/watchy/pins_arduino.h b/variants/watchy/pins_arduino.h new file mode 100644 index 0000000..edb9364 --- /dev/null +++ b/variants/watchy/pins_arduino.h @@ -0,0 +1,51 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t MENU_BTN_PIN = 26; +static const uint8_t BACK_BTN_PIN = 25; +static const uint8_t DOWN_BTN_PIN = 4; +static const uint8_t DISPLAY_CS = 5; +static const uint8_t DISPLAY_RES = 9; +static const uint8_t DISPLAY_DC = 10; +static const uint8_t DISPLAY_BUSY = 19; +static const uint8_t ACC_INT_1_PIN = 14; +static const uint8_t ACC_INT_2_PIN = 12; +static const uint8_t VIB_MOTOR_PIN = 13; +static const uint8_t RTC_INT_PIN = 27; + +#if defined(ARDUINO_WATCHY_V10) +static const uint8_t UP_BTN_PIN = 32; +static const uint8_t BATT_ADC_PIN = 33; +#define BAT_VOLT_PIN BATT_ADC_PIN +#define RTC_TYPE 1 //DS3231 +#elif defined(ARDUINO_WATCHY_V15) +static const uint8_t UP_BTN_PIN = 32; +static const uint8_t BATT_ADC_PIN = 35; +#define RTC_TYPE 2 //PCF8563 +#elif defined(ARDUINO_WATCHY_V20) +static const uint8_t UP_BTN_PIN = 35; +static const uint8_t BATT_ADC_PIN = 34; +#define RTC_TYPE 2 //PCF8563 +#endif + +#define UP_BTN_MASK (BIT64(UP_BTN_PIN)) +#define MENU_BTN_MASK (BIT64(MENU_BTN_PIN)) +#define BACK_BTN_MASK (BIT64(BACK_BTN_PIN)) +#define DOWN_BTN_MASK (BIT64(DOWN_BTN_PIN)) +#define ACC_INT_MASK (BIT64(ACC_INT_1_PIN)) +#define BTN_PIN_MASK (MENU_BTN_MASK | BACK_BTN_MASK | UP_BTN_MASK | DOWN_BTN_MASK) + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_c3_zero/pins_arduino.h b/variants/waveshare_esp32_c3_zero/pins_arduino.h new file mode 100644 index 0000000..02247e9 --- /dev/null +++ b/variants/waveshare_esp32_c3_zero/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 10 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 +// Define the color order for the built-in RGB LED +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 6; +static const uint8_t D7 = 7; +static const uint8_t D8 = 8; +static const uint8_t D9 = 9; +static const uint8_t D10 = 10; +static const uint8_t D11 = 20; +static const uint8_t D12 = 21; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_c6_zero/pins_arduino.h b/variants/waveshare_esp32_c6_zero/pins_arduino.h new file mode 100644 index 0000000..f03eebd --- /dev/null +++ b/variants/waveshare_esp32_c6_zero/pins_arduino.h @@ -0,0 +1,105 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" +/* + Arduino Pin Definitions for Waveshare ESP32-C6-Zero + +----------------------------------------------------------------+ + | | | | # | USB | # | | | | + |:---:|:-------:|:--------:|:--:|:---:|:--:|:------:|:----:|:---:| + | | | 5V | 1 | TOP | 18 | GPIO16 | TX | D16 | + | | | GND | 2 | TOP | 17 | GPIO17 | RX | D17 | + | | | 3V3(OUT) | 3 | TOP | 16 | GPIO14 | SDA | D12 | + | D0 | A0 | GPIO0 | 4 | TOP | 15 | GPIO15 | SCL | D11 | + | D1 | A1 | GPIO1 | 5 | TOP | 14 | GPIO18 | SS | D10 | + | D2 | A2 | GPIO2 | 6 | TOP | 13 | GPIO19 | MOSI | D9 | + | D3 | A3 | GPIO3 | 7 | TOP | 12 | GPIO20 | MISO | D8 | + | D4 | A4 | GPIO4 | 8 | TOP | 11 | GPIO21 | SCK | D7 | + | D5 | A5 | GPIO5 | 9 | TOP | 10 | GPIO22 | | D6 | + +----------------------------------------------------------------+ + + +----------------------------------------------------------------+ + | | | | # | USB | # | | | | + |:---:|:-------:|:--------:|:--:|:---:|:--:|:------:|:----:|:---:| + | | | | | BOT | | | | | + | | | | | BOT | | | | | + | D21 | | GPIO13 | 19 | BOT | | | | | + | D20 | | GPIO12 | 20 | BOT | | | | | + | D19 | | GPIO23 | 21 | BOT | | | | | + | D18 | BOOT | GPIO9 | 22 | BOT | | | | | + | D13 | RGB_LED | GPIO8 | 23 | BOT | | | | | + | D15 | | GPIO7 | 24 | BOT | | | | | + | D14 | A6 | GPIO6 | 25 | BOT | | | | | + +----------------------------------------------------------------+ +*/ +// The built-in RGB LED is connected to this pin +static const uint8_t PIN_RGB_LED = 8; +#define PIN_RGB_LED PIN_RGB_LED // allow testing #ifdef PIN_RGB_LED + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +// but also used in new Arduino API rgbLedWrite() +static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define RGB_BUILTIN RGB_BUILTIN // allow testing #ifdef RGB_BUILTIN + +// Define default brightness for the built-in RGB LED +#define RGB_BRIGHTNESS 32 // default brightness level (0-255) + +// Define the color order for the built-in RGB LED +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB + +// Define the built-in as LED pin (RGB LED) to use with digitalWrite() +static const uint8_t LED_BUILTIN = RGB_BUILTIN; +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 16; +static const uint8_t RX = 17; + +static const uint8_t SDA = 14; +static const uint8_t SCL = 15; + +static const uint8_t SS = 18; +static const uint8_t MOSI = 19; +static const uint8_t MISO = 20; +static const uint8_t SCK = 21; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; +static const uint8_t A6 = 6; + +static const uint8_t D0 = 0; +static const uint8_t D1 = 1; +static const uint8_t D2 = 2; +static const uint8_t D3 = 3; +static const uint8_t D4 = 4; +static const uint8_t D5 = 5; +static const uint8_t D6 = 22; +static const uint8_t D7 = 21; +static const uint8_t D8 = 20; +static const uint8_t D9 = 19; +static const uint8_t D10 = 18; +static const uint8_t D11 = 15; +static const uint8_t D12 = 14; +static const uint8_t D13 = 8; +static const uint8_t D14 = 6; +static const uint8_t D15 = 7; +static const uint8_t D16 = 16; +static const uint8_t D17 = 17; +static const uint8_t D18 = 9; +static const uint8_t D19 = 23; +static const uint8_t D20 = 12; +static const uint8_t D21 = 13; + +// LP I2C Pins are fixed on ESP32-C6 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define BUILTIN_RGB RGB_BUILTIN // backward compatibility + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h new file mode 100644 index 0000000..2539f20 --- /dev/null +++ b/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8258 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-1.46" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h new file mode 100644 index 0000000..b79a970 --- /dev/null +++ b/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x828A + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-LCD-1.47" +#define USB_SERIAL "" + +#define PIN_RGB_LED 38 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h new file mode 100644 index 0000000..5fafc59 --- /dev/null +++ b/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h @@ -0,0 +1,103 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8221 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-LCD-1.69" +#define USB_SERIAL "" + +// display for ST7789V2 +#define WS_LCD_DC 4 +#define WS_LCD_CS 5 +#define WS_LCD_SCL 6 +#define WS_LCD_SDA 7 +#define WS_LCD_RST 8 +#define WS_LCD_BL 15 + +// Onboard RTC for PCF85063 +#define WS_RTC_SCL 10 +#define WS_RTC_SDA 11 +#define WS_RTC_ADDRESS 0x51 +#define WS_RTC_INT 41 + +// Onboard QMI8658 IMU +#define WS_QMI8658_SDA 11 +#define WS_QMI8658_SCL 10 +#define WS_QMI8658_ADDRESS 0x6B +#define WS_QMI8658_INT1 38 + +// Onboard Electric buzzer & Custom buttons +// GPIO and PSRAM conflict, need to pay attention when using +#define WS_BUZZ 33 // Please pull down the level when using +#define WS_SYS_OUT 36 +#define WS_SYS_EN 35 + +// Partial voltage measurement method +#define WS_BAT_ADC 1 +#define BAT_VOLT_PIN WS_BAT_ADC + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h new file mode 100644 index 0000000..f8542f0 --- /dev/null +++ b/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8290 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-LCD-1.85" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h b/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h new file mode 100644 index 0000000..f389f5e --- /dev/null +++ b/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8273 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Relay-6CH" +#define USB_SERIAL "" + +#define PIN_RGB_LED 38 + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h new file mode 100644 index 0000000..1c06e9c --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h @@ -0,0 +1,50 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x824A + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-1.43" +#define USB_SERIAL "" + +// display QSPI SPI2 +#define QSPI_CS 9 +#define QSPI_SCK 10 +#define QSPI_D0 11 +#define QSPI_D1 12 +#define QSPI_D2 13 +#define QSPI_D3 14 +#define AMOLED_RESET 21 +#define AMOLED_TE -1 +#define AMOLED_PWR_EN -1 +// Touch I2C +#define TP_SCL 48 +#define TP_SDA 47 +#define TP_RST -1 +#define TP_INT -1 + +// RTC +#define RTC_INT 15 +// Partial voltage measurement method +#define BAT_ADC 4 +#define BAT_VOLT_PIN BAT_ADC +// Onboard QMI8658 IMU +#define QMI_INT1 8 + +static const uint8_t SDA = 47; +static const uint8_t SCL = 48; +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//esp32s3-PSFlash SPI1/SPI0 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h new file mode 100644 index 0000000..47aabe9 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h @@ -0,0 +1,56 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8249 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-1.64" +#define USB_SERIAL "" + +// display QSPI SPI2 +#define QSPI_CS 9 +#define QSPI_SCK 10 +#define QSPI_D0 11 +#define QSPI_D1 12 +#define QSPI_D2 13 +#define QSPI_D3 14 +#define AMOLED_RESET 21 +#define AMOLED_TE -1 +#define AMOLED_PWR_EN -1 + +// Touch I2C +#define TP_SCL 48 +#define TP_SDA 47 +#define TP_RST -1 +#define TP_INT -1 + +//key +#define KEY_0 0 +//ADC +#define BAT_ADC 4 +#define BAT_VOLT_PIN BAT_ADC + +//SD_CARD +#define SD_CS 38 +#define SD_MOSI 39 +#define SD_MISO 40 +#define SD_SCLK 41 + +static const uint8_t SDA = 47; +static const uint8_t SCL = 48; + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//esp32s3-PSFlash SPI1/SPI0 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h new file mode 100644 index 0000000..de8bcae --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h @@ -0,0 +1,87 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8255 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-1.8" +#define USB_SERIAL "" + +// display for SH8601 +#define WS_LCD_CS 12 +#define WS_QSPI_SIO0 4 +#define WS_QSPI_SI1 5 +#define WS_QSPI_SI2 6 +#define WS_QSPI_SI3 7 +#define WS_QSPI_SCL 11 + +// Touch for FT3168 +#define WS_TP_INT 21 + +// Onboard Electric buzzer & Custom buttons +// GPIO and PSRAM conflict, need to pay attention when using + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 14; +static const uint8_t SCL = 15; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h new file mode 100644 index 0000000..6145406 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x824B + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-1.91" +#define USB_SERIAL "" + +// display QSPI SPI2 +#define QSPI_CS 6 +#define QSPI_SCK 47 +#define QSPI_D0 18 +#define QSPI_D1 7 +#define QSPI_D2 48 +#define QSPI_D3 5 +#define AMOLED_RESET 17 +#define AMOLED_TE -1 +#define AMOLED_PWR_EN -1 +// Touch I2C +#define TP_SCL 39 +#define TP_SDA 40 +#define TP_RST -1 +#define TP_INT -1 + +// Partial voltage measurement method +#define BAT_ADC 1 +#define BAT_VOLT_PIN BAT_ADC +// Onboard QMI8658 IMU +#define QMI_INT1 45 +#define QMI_INT1 46 + +//SD +#define SD_CS 9 +#define SD_MISO 8 +#define SD_MOSI 42 +#define SD_CLK 47 + +//i2c + +static const uint8_t SDA = 40; +static const uint8_t SCL = 39; + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//esp32s3-PSFlash SPI1/SPI0 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_206/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_206/pins_arduino.h new file mode 100644 index 0000000..7afdcf6 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_206/pins_arduino.h @@ -0,0 +1,70 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// SDMMC (1-bit) +#define BOARD_HAS_SD_SDMMC +#define SDMMC_CLK 2 +#define SDMMC_CMD 1 +#define SDMMC_D0 3 +#define SDMMC_CS 17 + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-2.06" +#define USB_SERIAL "" + +// display AMOLED SPI2 +#define AMOLED_CS 12 +#define AMOLED_SCK 11 +#define AMOLED_D0 4 +#define AMOLED_D1 5 +#define AMOLED_D2 6 +#define AMOLED_D3 7 +#define AMOLED_RESET 8 +#define AMOLED_TE 13 +#define AMOLED_PWR_EN 21 +#define AMOLED_WIDTH 410 +#define AMOLED_HEIGHT 502 + +// Touch I2C +#define TP_SCL 14 +#define TP_SDA 15 +#define TP_RST 9 +#define TP_INT 38 + +// Onboard RTC for PCF85063 +#define RTC_SCL 14 +#define RTC_SDA 15 +#define RTC_ADDRESS 0x51 +#define RTC_INT 39 + +// Onboard QMI8658 IMU +#define QMI8658_SDA 14 +#define QMI8658_SCL 15 +#define QMI8658_ADDRESS 0x6b +#define QMI8658_INT1 21 + +// Partial voltage measurement method +#define BAT_ADC 33 +#define BAT_VOLT_PIN BAT_ADC + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 15; +static const uint8_t SCL = 14; + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//esp32s3-PSFlash SPI1/SPI0 +#define SS 32 // FSPICS0 +#define MOSI 35 // FSPID +#define MISO 34 // FSPIQ +#define SCK 33 // FSPICLK +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h new file mode 100644 index 0000000..0b9ee51 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h @@ -0,0 +1,61 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8242 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-AMOLED-2.41" +#define USB_SERIAL "" + +// display QSPI SPI2 +#define QSPI_CS 9 +#define QSPI_SCK 10 +#define QSPI_D0 11 +#define QSPI_D1 12 +#define QSPI_D2 13 +#define QSPI_D3 14 +#define AMOLED_RESET 21 +#define AMOLED_TE -1 +#define AMOLED_PWR_EN -1 + +// Touch I2C +#define TP_SCL 48 +#define TP_SDA 47 +#define TP_RST -1 +#define TP_INT -1 + +// Onboard RTC for PCF85063 +#define RTC_SCL 48 +#define RTC_SDA 47 +#define RTC_ADDRESS 0x51 +#define RTC_INT -1 + +// Onboard QMI8658 IMU +#define QMI8658_SDA 47 +#define QMI8658_SCL 48 +#define QMI8658_ADDRESS 0x6b +#define QMI8658_INT1 -1 + +// Partial voltage measurement method +#define BAT_ADC 17 +#define BAT_VOLT_PIN BAT_ADC + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 47; +static const uint8_t SCL = 48; + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +//esp32s3-PSFlash SPI1/SPI0 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h new file mode 100644 index 0000000..1c14bfe --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8287 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-1.85-Box" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h new file mode 100644 index 0000000..d512bda --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h @@ -0,0 +1,109 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x821e + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-1.69" +#define USB_SERIAL "" + +// display for ST7789V2 +#define WS_LCD_DC 4 +#define WS_LCD_CS 5 +#define WS_LCD_SCL 6 +#define WS_LCD_SDA 7 +#define WS_LCD_RST 8 +#define WS_LCD_BL 15 + +// Touch for CST816T +#define WS_TP_SCL 10 +#define WS_TP_SDA 11 +#define WS_TP_RST 13 +#define WS_TP_INT 14 + +// Onboard RTC for PCF85063 +#define WS_RTC_SCL 10 +#define WS_RTC_SDA 11 +#define WS_RTC_ADDRESS 0x51 +#define WS_RTC_INT 41 + +// Onboard QMI8658 IMU +#define WS_QMI8658_SDA 11 +#define WS_QMI8658_SCL 10 +#define WS_QMI8658_ADDRESS 0x6B +#define WS_QMI8658_INT1 38 + +// Onboard Electric buzzer & Custom buttons +// GPIO and PSRAM conflict, need to pay attention when using +#define WS_BUZZ 33 // Please pull down the level when using +#define WS_SYS_OUT 36 +#define WS_SYS_EN 35 + +// Partial voltage measurement method +#define WS_BAT_ADC 1 +#define BAT_VOLT_PIN WS_BAT_ADC + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h new file mode 100644 index 0000000..863590e --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8290 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-1.85" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h new file mode 100644 index 0000000..438da04 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x825B + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-2.1" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 7; +static const uint8_t SDA = 15; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h new file mode 100644 index 0000000..a6c76a7 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x825E + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-2.8" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h new file mode 100644 index 0000000..a6c76a7 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x825E + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-2.8" +#define USB_SERIAL "" + +// I2C pins +static const uint8_t SCL = 10; +static const uint8_t SDA = 11; + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; +static const uint8_t A18 = 19; +static const uint8_t A19 = 20; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h new file mode 100644 index 0000000..f4a08ea --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h @@ -0,0 +1,73 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x823D + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-4" +#define USB_SERIAL "" + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = -1; +static const uint8_t SCL = -1; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h new file mode 100644 index 0000000..9b60b50 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h @@ -0,0 +1,116 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x822E + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-4.3" +#define USB_SERIAL "" + +// display for ST7262 +#define WS_LCD_B3 14 +#define WS_LCD_B4 38 +#define WS_LCD_B5 18 +#define WS_LCD_B6 17 +#define WS_LCD_B7 10 + +#define WS_LCD_G2 39 +#define WS_LCD_G3 0 +#define WS_LCD_G4 45 +#define WS_LCD_G5 48 +#define WS_LCD_G6 47 +#define WS_LCD_G7 21 + +#define WS_LCD_R3 1 +#define WS_LCD_R4 2 +#define WS_LCD_R5 42 +#define WS_LCD_R6 41 +#define WS_LCD_R7 40 + +#define WS_LCD_VSYNC 3 +#define WS_LCD_HSYNC 46 +#define WS_LCD_PCLK 7 +#define WS_LCD_DE 5 + +// Touch for gt911 +#define WS_TP_SDA 8 +#define WS_TP_SCL 9 +#define WS_TP_RST -1 +#define WS_TP_INT 4 + +//RS485 +#define WS_RS485_RXD 16 +#define WS_RS485_TXD 15 + +//CAN +#define WS_CAN_RXD 19 +#define WS_CAN_TXD 20 + +//Onboard CH422G IO expander +#define WS_CH422G_SDA 8 +#define WS_CH422G_SCL 9 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h new file mode 100644 index 0000000..f3bcb40 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h @@ -0,0 +1,116 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8231 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-4.3B" +#define USB_SERIAL "" + +// display for ST7262 +#define WS_LCD_B3 14 +#define WS_LCD_B4 38 +#define WS_LCD_B5 18 +#define WS_LCD_B6 17 +#define WS_LCD_B7 10 + +#define WS_LCD_G2 39 +#define WS_LCD_G3 0 +#define WS_LCD_G4 45 +#define WS_LCD_G5 48 +#define WS_LCD_G6 47 +#define WS_LCD_G7 21 + +#define WS_LCD_R3 1 +#define WS_LCD_R4 2 +#define WS_LCD_R5 42 +#define WS_LCD_R6 41 +#define WS_LCD_R7 40 + +#define WS_LCD_VSYNC 3 +#define WS_LCD_HSYNC 46 +#define WS_LCD_PCLK 7 +#define WS_LCD_DE 5 + +// Touch for gt911 +#define WS_TP_SDA 8 +#define WS_TP_SCL 9 +#define WS_TP_RST -1 +#define WS_TP_INT 4 + +//RS485 +#define WS_RS485_RXD 43 +#define WS_RS485_TXD 44 + +//CAN +#define WS_CAN_RXD 15 +#define WS_CAN_TXD 16 + +//Onboard CH422G IO expander +#define WS_CH422G_SDA 8 +#define WS_CH422G_SCL 9 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h new file mode 100644 index 0000000..135dc0d --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h @@ -0,0 +1,116 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8237 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-5" +#define USB_SERIAL "" + +// display for ST7262 +#define WS_LCD_B3 14 +#define WS_LCD_B4 38 +#define WS_LCD_B5 18 +#define WS_LCD_B6 17 +#define WS_LCD_B7 10 + +#define WS_LCD_G2 39 +#define WS_LCD_G3 0 +#define WS_LCD_G4 45 +#define WS_LCD_G5 48 +#define WS_LCD_G6 47 +#define WS_LCD_G7 21 + +#define WS_LCD_R3 1 +#define WS_LCD_R4 2 +#define WS_LCD_R5 42 +#define WS_LCD_R6 41 +#define WS_LCD_R7 40 + +#define WS_LCD_VSYNC 3 +#define WS_LCD_HSYNC 46 +#define WS_LCD_PCLK 7 +#define WS_LCD_DE 5 + +// Touch for gt911 +#define WS_TP_SDA 8 +#define WS_TP_SCL 9 +#define WS_TP_RST -1 +#define WS_TP_INT 4 + +//RS485 +#define WS_RS485_RXD 43 +#define WS_RS485_TXD 44 + +//CAN +#define WS_CAN_RXD 15 +#define WS_CAN_TXD 16 + +//Onboard CH422G IO expander +#define WS_CH422G_SDA 8 +#define WS_CH422G_SCL 9 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h new file mode 100644 index 0000000..e882960 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h @@ -0,0 +1,116 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x823A + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-5B" +#define USB_SERIAL "" + +// display for ST7262 +#define WS_LCD_B3 14 +#define WS_LCD_B4 38 +#define WS_LCD_B5 18 +#define WS_LCD_B6 17 +#define WS_LCD_B7 10 + +#define WS_LCD_G2 39 +#define WS_LCD_G3 0 +#define WS_LCD_G4 45 +#define WS_LCD_G5 48 +#define WS_LCD_G6 47 +#define WS_LCD_G7 21 + +#define WS_LCD_R3 1 +#define WS_LCD_R4 2 +#define WS_LCD_R5 42 +#define WS_LCD_R6 41 +#define WS_LCD_R7 40 + +#define WS_LCD_VSYNC 3 +#define WS_LCD_HSYNC 46 +#define WS_LCD_PCLK 7 +#define WS_LCD_DE 5 + +// Touch for gt911 +#define WS_TP_SDA 8 +#define WS_TP_SCL 9 +#define WS_TP_RST -1 +#define WS_TP_INT 4 + +//RS485 +#define WS_RS485_RXD 43 +#define WS_RS485_TXD 44 + +//CAN +#define WS_CAN_RXD 15 +#define WS_CAN_TXD 16 + +//Onboard CH422G IO expander +#define WS_CH422G_SDA 8 +#define WS_CH422G_SCL 9 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h new file mode 100644 index 0000000..357edf7 --- /dev/null +++ b/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h @@ -0,0 +1,116 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x8234 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Touch-LCD-7" +#define USB_SERIAL "" + +// display for ST7262 +#define WS_LCD_B3 14 +#define WS_LCD_B4 38 +#define WS_LCD_B5 18 +#define WS_LCD_B6 17 +#define WS_LCD_B7 10 + +#define WS_LCD_G2 39 +#define WS_LCD_G3 0 +#define WS_LCD_G4 45 +#define WS_LCD_G5 48 +#define WS_LCD_G6 47 +#define WS_LCD_G7 21 + +#define WS_LCD_R3 1 +#define WS_LCD_R4 2 +#define WS_LCD_R5 42 +#define WS_LCD_R6 41 +#define WS_LCD_R7 40 + +#define WS_LCD_VSYNC 3 +#define WS_LCD_HSYNC 46 +#define WS_LCD_PCLK 7 +#define WS_LCD_DE 5 + +// Touch for gt911 +#define WS_TP_SDA 8 +#define WS_TP_SCL 9 +#define WS_TP_RST -1 +#define WS_TP_INT 4 + +//RS485 +#define WS_RS485_RXD 16 +#define WS_RS485_TXD 15 + +//CAN +#define WS_CAN_RXD 19 +#define WS_CAN_TXD 20 + +//Onboard CH422G IO expander +#define WS_CH422G_SDA 8 +#define WS_CH422G_SCL 9 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 10; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO17 = 17; +static const uint8_t OUTPUT_IO18 = 18; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32_s3_zero/pins_arduino.h b/variants/waveshare_esp32_s3_zero/pins_arduino.h new file mode 100644 index 0000000..d3d4b7a --- /dev/null +++ b/variants/waveshare_esp32_s3_zero/pins_arduino.h @@ -0,0 +1,92 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x822B +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Zero" +#define USB_SERIAL "" // Empty string for MAC address + +// Onboard WS2812 RGB LED +#define WS_RGB 21 + +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + WS_RGB; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 +// Define the color order for the built-in RGB LED +#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB + +// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT +static const uint8_t OUTPUT_IO1 = 1; +static const uint8_t OUTPUT_IO2 = 2; +static const uint8_t OUTPUT_IO3 = 3; +static const uint8_t OUTPUT_IO4 = 4; +static const uint8_t OUTPUT_IO5 = 5; +static const uint8_t OUTPUT_IO6 = 6; +static const uint8_t OUTPUT_IO7 = 7; +static const uint8_t OUTPUT_IO8 = 8; +static const uint8_t OUTPUT_IO9 = 9; +static const uint8_t OUTPUT_IO10 = 10; +static const uint8_t OUTPUT_IO11 = 11; +static const uint8_t OUTPUT_IO12 = 12; +static const uint8_t OUTPUT_IO13 = 13; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = -1; +static const uint8_t SCL = -1; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h b/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h new file mode 100644 index 0000000..02228eb --- /dev/null +++ b/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h @@ -0,0 +1,37 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x1A86 +#define USB_PID 0x55D3 +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3 Touch LCD 1.28" +#define USB_SERIAL "" // Empty string for MAC address + +#define LCD_BACKLIGHT 2 +#define LCD_DC 8 +#define LCD_RST 14 + +#define TP_INT 5 +#define TP_RST 13 + +#define IMU_INT1 4 +#define IMU_INT2 3 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; +#define TX1 TX +#define RX1 RX + +static const uint8_t SCL = 7; +static const uint8_t SDA = 6; + +static const uint8_t SS = 9; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 12; +static const uint8_t SCK = 10; + +static const uint8_t A0 = 1; // Connected through voltage divider to battery pin + +#endif /* Pins_Arduino_h */ diff --git a/variants/weact_studio_esp32c3/pins_arduino.h b/variants/weact_studio_esp32c3/pins_arduino.h new file mode 100644 index 0000000..fdcc730 --- /dev/null +++ b/variants/weact_studio_esp32c3/pins_arduino.h @@ -0,0 +1,28 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 8; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 6; +static const uint8_t MISO = 5; +static const uint8_t SCK = 4; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wesp32/pins_arduino.h b/variants/wesp32/pins_arduino.h new file mode 100644 index 0000000..7be7f87 --- /dev/null +++ b/variants/wesp32/pins_arduino.h @@ -0,0 +1,41 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define TX1 12 +#define RX1 13 +#define TX2 33 +#define RX2 39 + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SCL = 4; +static const uint8_t SDA = 15; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 32; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; + +static const uint8_t T0 = 4; +static const uint8_t T2 = 2; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +#define ETH_PHY_ADDR 0 +#define ETH_PHY_POWER -1 +#define ETH_PHY_MDC 16 +#define ETH_PHY_MDIO 17 +#define ETH_PHY_TYPE ETH_PHY_RTL8201 +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN + +#endif /* Pins_Arduino_h */ diff --git a/variants/widora-air/pins_arduino.h b/variants/widora-air/pins_arduino.h new file mode 100644 index 0000000..2240bbe --- /dev/null +++ b/variants/widora-air/pins_arduino.h @@ -0,0 +1,53 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 25; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 19; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 16; +static const uint8_t MISO = 17; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 39; +static const uint8_t A2 = 35; +static const uint8_t A3 = 25; +static const uint8_t A4 = 26; +static const uint8_t A5 = 14; +static const uint8_t A6 = 12; +static const uint8_t A7 = 15; +static const uint8_t A8 = 13; +static const uint8_t A9 = 2; + +static const uint8_t D0 = 19; +static const uint8_t D1 = 23; +static const uint8_t D2 = 18; +static const uint8_t D3 = 17; +static const uint8_t D4 = 16; +static const uint8_t D5 = 5; +static const uint8_t D6 = 4; + +static const uint8_t T0 = 19; +static const uint8_t T1 = 23; +static const uint8_t T2 = 18; +static const uint8_t T3 = 17; +static const uint8_t T4 = 16; +static const uint8_t T5 = 5; +static const uint8_t T6 = 4; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wifiduino32/pins_arduino.h b/variants/wifiduino32/pins_arduino.h new file mode 100644 index 0000000..5334a5c --- /dev/null +++ b/variants/wifiduino32/pins_arduino.h @@ -0,0 +1,59 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 2; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t KEY_BUILTIN = 0; + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 5; +static const uint8_t SCL = 16; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +static const uint8_t A0 = 27; +static const uint8_t A1 = 14; +static const uint8_t A2 = 12; +static const uint8_t A3 = 35; +static const uint8_t A4 = 13; +static const uint8_t A5 = 4; + +static const uint8_t D0 = 3; +static const uint8_t D1 = 1; +static const uint8_t D2 = 17; +static const uint8_t D3 = 15; +static const uint8_t D4 = 32; +static const uint8_t D5 = 33; +static const uint8_t D6 = 25; +static const uint8_t D7 = 26; +static const uint8_t D8 = 23; +static const uint8_t D9 = 22; +static const uint8_t D10 = 21; +static const uint8_t D11 = 19; +static const uint8_t D12 = 18; +static const uint8_t D13 = 2; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wifiduino32s3/pins_arduino.h b/variants/wifiduino32s3/pins_arduino.h new file mode 100644 index 0000000..4fc0813 --- /dev/null +++ b/variants/wifiduino32s3/pins_arduino.h @@ -0,0 +1,58 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define USB_VID 0x303a +#define USB_PID 0x1001 +#define USB_MANUFACTURER "openjumper" +#define USB_PRODUCT "Wifiduino32-S3" +#define USB_SERIAL "" // Empty string for MAC address + +// Some boards have too low voltage on this pin (board design bug) +// Use different pin with 3V and connect with 48 +// and change this setup for the chosen pin (for example 38) +#define PIN_RGB_LED 48 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +static const uint8_t D0 = 44; +static const uint8_t D1 = 43; +static const uint8_t D2 = 45; +static const uint8_t D3 = 46; +static const uint8_t D4 = 47; +static const uint8_t D5 = 48; +static const uint8_t D6 = 18; +static const uint8_t D7 = 17; +static const uint8_t D8 = 21; +static const uint8_t D9 = 42; +static const uint8_t D10 = 41; +static const uint8_t D11 = 40; +static const uint8_t D12 = 38; +static const uint8_t D13 = 39; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wifiduinov2/pins_arduino.h b/variants/wifiduinov2/pins_arduino.h new file mode 100644 index 0000000..916de50 --- /dev/null +++ b/variants/wifiduinov2/pins_arduino.h @@ -0,0 +1,43 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 13; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 21; +static const uint8_t RX = 20; + +static const uint8_t SDA = 4; +static const uint8_t SCL = 5; + +static const uint8_t SS = 7; +static const uint8_t MOSI = 3; +static const uint8_t MISO = 10; +static const uint8_t SCK = 2; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; +static const uint8_t A4 = 4; +static const uint8_t A5 = 5; + +static const uint8_t D0 = 20; +static const uint8_t D1 = 21; +static const uint8_t D2 = 9; +static const uint8_t D3 = 13; +static const uint8_t D4 = 12; +static const uint8_t D5 = 11; +static const uint8_t D6 = 6; +static const uint8_t D7 = 18; +static const uint8_t D8 = 19; +static const uint8_t D9 = 8; +static const uint8_t D10 = 7; +static const uint8_t D11 = 3; +static const uint8_t D12 = 10; +static const uint8_t D13 = 2; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wipy3/pins_arduino.h b/variants/wipy3/pins_arduino.h new file mode 100644 index 0000000..a9fda1e --- /dev/null +++ b/variants/wipy3/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// RGB LED +#define PIN_RGB_LED 0 // ->2812 RGB !!! +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT); +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +#define ANT_SELECT 21 // GPIO21 - External Antenna Switch + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 12; +static const uint8_t SCL = 13; + +static const uint8_t SS = 2; +static const uint8_t MOSI = 22; +static const uint8_t MISO = 37; +static const uint8_t SCK = 13; + +static const uint8_t A0 = 36; +static const uint8_t A1 = 37; +static const uint8_t A2 = 38; +static const uint8_t A3 = 39; +static const uint8_t A4 = 32; +static const uint8_t A5 = 33; +static const uint8_t A6 = 34; +static const uint8_t A7 = 35; +static const uint8_t A10 = 4; +static const uint8_t A11 = 0; +static const uint8_t A12 = 2; +static const uint8_t A13 = 15; +static const uint8_t A14 = 13; +static const uint8_t A15 = 12; +static const uint8_t A16 = 14; +static const uint8_t A17 = 27; +static const uint8_t A18 = 25; +static const uint8_t A19 = 26; + +static const uint8_t T0 = 4; +static const uint8_t T1 = 0; +static const uint8_t T2 = 2; +static const uint8_t T3 = 15; +static const uint8_t T4 = 13; +static const uint8_t T5 = 12; +static const uint8_t T6 = 14; +static const uint8_t T7 = 27; +static const uint8_t T8 = 33; +static const uint8_t T9 = 32; + +static const uint8_t DAC1 = 25; +static const uint8_t DAC2 = 26; + +#endif /* Pins_Arduino_h */ diff --git a/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv b/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv new file mode 100755 index 0000000..25eeb8c --- /dev/null +++ b/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv @@ -0,0 +1,3 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +factory, app, factory, 0x10000, 0x3F0000, diff --git a/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv b/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv new file mode 100755 index 0000000..04240ba --- /dev/null +++ b/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags + nvs, data, nvs, 0x9000, 0x5000, + otadata, data, ota, 0xE000, 0x2000, + app0, app, ota_0, 0x10000, 0x1F0000, + app1, app, ota_1, 0x200000, 0x1F0000, +coredump, data, coredump, 0x3F0000, 0x10000, diff --git a/variants/ws_esp32_s3_matrix/pins_arduino.h b/variants/ws_esp32_s3_matrix/pins_arduino.h new file mode 100644 index 0000000..ab06705 --- /dev/null +++ b/variants/ws_esp32_s3_matrix/pins_arduino.h @@ -0,0 +1,77 @@ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +// BN: ESP32 Family Device +#define USB_VID 0x303a +#define USB_PID 0x1001 + +#define USB_MANUFACTURER "Waveshare" +#define USB_PRODUCT "ESP32-S3-Matrix" +#define USB_SERIAL "" + +// Onboard 8 x 8 Matrix panel +#define WS_MATRIX_DIN 14 + +// Onboard QMI8658 IMU +#define WS_IMU_SDA 11 +#define WS_IMU_SCL 12 +#define WS_IMU_ADDRESS 0x6B +#define WS_IMU_INT1 10 +#define WS_IMU_INT2 13 + +// UART0 pins +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +// Def for I2C that shares the IMU I2C pins +static const uint8_t SDA = 11; +static const uint8_t SCL = 12; + +// Mapping based on the ESP32S3 data sheet - alternate for SPI2 +static const uint8_t SS = 34; // FSPICS0 +static const uint8_t MOSI = 35; // FSPID +static const uint8_t MISO = 37; // FSPIQ +static const uint8_t SCK = 36; // FSPICLK + +// Analog capable pins on the header +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; + +// GPIO capable pins on the header +static const uint8_t D0 = 7; +static const uint8_t D1 = 6; +static const uint8_t D2 = 5; +static const uint8_t D3 = 4; +static const uint8_t D4 = 3; +static const uint8_t D5 = 2; +static const uint8_t D6 = 1; +static const uint8_t D7 = 44; +static const uint8_t D8 = 43; +static const uint8_t D9 = 40; +static const uint8_t D10 = 39; +static const uint8_t D11 = 38; +static const uint8_t D12 = 37; +static const uint8_t D13 = 36; +static const uint8_t D14 = 35; +static const uint8_t D15 = 34; +static const uint8_t D16 = 33; + +// Touch input capable pins on the header +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wt32-eth01/pins_arduino.h b/variants/wt32-eth01/pins_arduino.h new file mode 100644 index 0000000..f5fb704 --- /dev/null +++ b/variants/wt32-eth01/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/** + * Variant: WT32-ETH01 + * Vendor: Wireless-Tag + * Url: http://www.wireless-tag.com/portfolio/wt32-eth01/ + */ + +#include + +// interface to Ethernet PHY (LAN8720A) +#define ETH_PHY_ADDR 1 +#define ETH_PHY_POWER 16 +#define ETH_PHY_MDC 23 +#define ETH_PHY_MDIO 18 +#define ETH_PHY_TYPE ETH_PHY_LAN8720 +#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN + +// general purpose IO pins +static const uint8_t IO0 = 0; +static const uint8_t IO1 = 1; // TXD0 / TX0 pin +static const uint8_t IO2 = 2; +static const uint8_t IO3 = 3; // RXD0 / RX0 pin +static const uint8_t IO4 = 4; +static const uint8_t IO5 = 5; // RXD2 / RXD pin +static const uint8_t IO12 = 12; +static const uint8_t IO14 = 14; +static const uint8_t IO15 = 15; +static const uint8_t IO17 = 17; // TXD2 / TXD pin +static const uint8_t IO32 = 32; // CFG pin +static const uint8_t IO33 = 33; // 485_EN pin + +// input-only pins +static const uint8_t IO35 = 35; +static const uint8_t IO36 = 36; +static const uint8_t IO39 = 39; + +// UART interfaces +static const uint8_t TXD0 = 1, TX0 = 1; +static const uint8_t RXD0 = 3, RX0 = 3; +static const uint8_t TXD2 = 17, TXD = 17; +static const uint8_t RXD2 = 5, RXD = 5; +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +//SPI VSPI default pins +static const uint8_t SS = -1; +static const uint8_t MOSI = 14; +static const uint8_t MISO = 15; +static const uint8_t SCK = 12; + +//I2C default pins +static const uint8_t SDA = 33; +static const uint8_t SCL = 32; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wt32-sc01-plus/bootloader_tinyuf2.bin b/variants/wt32-sc01-plus/bootloader_tinyuf2.bin new file mode 100644 index 0000000..e89596f Binary files /dev/null and b/variants/wt32-sc01-plus/bootloader_tinyuf2.bin differ diff --git a/variants/wt32-sc01-plus/partitions_tinyuf2.csv b/variants/wt32-sc01-plus/partitions_tinyuf2.csv new file mode 100644 index 0000000..4026378 --- /dev/null +++ b/variants/wt32-sc01-plus/partitions_tinyuf2.csv @@ -0,0 +1,10 @@ +# ESP-IDF Partition Table +# Name, Type, SubType, Offset, Size, Flags +# bootloader.bin,, 0x1000, 32K +# partition table,, 0x8000, 4K +nvs, data, nvs, 0x9000, 20K, +otadata, data, ota, 0xe000, 8K, +ota_0, 0, ota_0, 0x10000, 2048K, +ota_1, 0, ota_1, 0x210000, 2048K, +uf2, app, factory,0x410000, 256K, +ffat, data, fat, 0x450000, 3776K, diff --git a/variants/wt32-sc01-plus/pins_arduino.h b/variants/wt32-sc01-plus/pins_arduino.h new file mode 100644 index 0000000..ef418d9 --- /dev/null +++ b/variants/wt32-sc01-plus/pins_arduino.h @@ -0,0 +1,64 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +/** + * Variant: WT32-SC01 PLUS + * Vendor: Wireless-Tag + * Url: http://www.wireless-tag.com/portfolio/wt32-eth01/ + */ + +#include + +#define USB_VID 0x303A +#define USB_PID 0x80D0 +#define USB_MANUFACTURER "PANLEE" +#define USB_PRODUCT "SC01PLUS" +#define USB_SERIAL "" +//GENERAL I/O +static const uint8_t BOOT_0 = 0; +static const uint8_t IO1 = 10; +static const uint8_t IO2 = 11; +static const uint8_t IO3 = 12; +static const uint8_t IO4 = 13; +static const uint8_t IO5 = 14; +static const uint8_t IO6 = 21; +//RS485 +static const uint8_t TX = 42; +static const uint8_t RX = 1; +static const uint8_t RTS = 2; +//TOUCHSCREEN +static const uint8_t BL_PWM = 45; //BACKLIGHT PWM +static const uint8_t LCD_RESET = 4; //LCD RESET, MULTIPLEXED WITH TOUCH RESET +static const uint8_t LCD_RS = 0; //COMMAND/DATA +static const uint8_t LCD_WR = 47; //WRITE CLOCK +static const uint8_t LCD_TE = 48; //FRAME SYNC +static const uint8_t LCD_DB0 = 9; +static const uint8_t LCD_DB1 = 46; +static const uint8_t LCD_DB2 = 3; +static const uint8_t LCD_DB3 = 8; +static const uint8_t LCD_DB4 = 18; +static const uint8_t LCD_DB5 = 17; +static const uint8_t LCD_DB6 = 16; +static const uint8_t LCD_DB7 = 15; + +//SPEAKER +static const uint8_t LRCK = 35; +static const uint8_t BCLK = 36; +static const uint8_t DOUT = 37; + +//TOUCHSCREEN DIGITIZER +static const uint8_t TP_INT = 7; +static const uint8_t SDA = 6; +static const uint8_t SCL = 5; +static const uint8_t RST = 4; +//MICRO SD CARD +static const uint8_t SD_CS = 41; +static const uint8_t SD_DI = 40; //MOSI +static const uint8_t SD_DO = 38; //MISO +static const uint8_t SD_CLK = 39; +static const uint8_t SS = 41; +static const uint8_t MOSI = 40; +static const uint8_t MISO = 38; +static const uint8_t SCK = 39; + +#endif /* Pins_Arduino_h */ diff --git a/variants/wt32-sc01-plus/tinyuf2.bin b/variants/wt32-sc01-plus/tinyuf2.bin new file mode 100644 index 0000000..b2723dc Binary files /dev/null and b/variants/wt32-sc01-plus/tinyuf2.bin differ diff --git a/variants/xinabox/pins_arduino.h b/variants/xinabox/pins_arduino.h new file mode 100644 index 0000000..eeabcd7 --- /dev/null +++ b/variants/xinabox/pins_arduino.h @@ -0,0 +1,21 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 27; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 1; +static const uint8_t RX = 3; + +static const uint8_t SDA = 21; +static const uint8_t SCL = 22; + +static const uint8_t SS = 5; +static const uint8_t MOSI = 23; +static const uint8_t MISO = 19; +static const uint8_t SCK = 18; + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_amp/pins_arduino.h b/variants/yb_esp32s3_amp/pins_arduino.h new file mode 100644 index 0000000..e838223 --- /dev/null +++ b/variants/yb_esp32s3_amp/pins_arduino.h @@ -0,0 +1,60 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +// I2S for onboard MAX98357A only +static const uint8_t I2S_BCLK = 5; +static const uint8_t I2S_LRCLK = 6; +static const uint8_t I2S_DOUT = 7; + +// SPI for onboard microSD only +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// SPI2 for public usage +static const uint8_t SS2 = 38; +static const uint8_t MOSI2 = 39; +static const uint8_t MISO2 = 41; +static const uint8_t SCK2 = 40; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 8; +static const uint8_t A5 = 9; +static const uint8_t A6 = 10; +static const uint8_t A7 = 14; +static const uint8_t A8 = 15; +static const uint8_t A9 = 16; +static const uint8_t A10 = 17; +static const uint8_t A11 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T14 = 14; + +#define PIN_DAC_MUTE 47 // only if solder bridge "DAC_MUTE" is closed + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_amp_v2/pins_arduino.h b/variants/yb_esp32s3_amp_v2/pins_arduino.h new file mode 100644 index 0000000..34d454f --- /dev/null +++ b/variants/yb_esp32s3_amp_v2/pins_arduino.h @@ -0,0 +1,57 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +//I2S for onboard MAX98357A only +static const uint8_t I2S_BCLK = 5; +static const uint8_t I2S_LRCLK = 6; +static const uint8_t I2S_DOUT = 7; + +// SPI for onboard microSD only +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// SPI2 for public usage +static const uint8_t SS2 = 38; +static const uint8_t MOSI2 = 39; +static const uint8_t MISO2 = 41; +static const uint8_t SCK2 = 40; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 8; +static const uint8_t A5 = 9; +static const uint8_t A6 = 10; +static const uint8_t A7 = 14; +static const uint8_t A8 = 15; +static const uint8_t A9 = 16; +static const uint8_t A10 = 17; +static const uint8_t A11 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T14 = 14; + +#define PIN_DAC_MUTE 47 // only if solder bridge "DAC_MUTE" is closed + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_amp_v3/pins_arduino.h b/variants/yb_esp32s3_amp_v3/pins_arduino.h new file mode 100644 index 0000000..0b6ff0f --- /dev/null +++ b/variants/yb_esp32s3_amp_v3/pins_arduino.h @@ -0,0 +1,60 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +//I2S for onboard MAX98357A only +static const uint8_t I2S_BCLK = 5; +static const uint8_t I2S_LRCLK = 6; +static const uint8_t I2S_DOUT = 7; + +// SPI for onboard microSD only +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// SPI2 for public usage +static const uint8_t SS2 = 38; +static const uint8_t MOSI2 = 39; +static const uint8_t MISO2 = 41; +static const uint8_t SCK2 = 40; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 8; +static const uint8_t A5 = 9; +static const uint8_t A6 = 10; +static const uint8_t A7 = 14; +static const uint8_t A8 = 15; +static const uint8_t A9 = 16; +static const uint8_t A10 = 17; +static const uint8_t A11 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T14 = 14; + +#define PIN_DAC_MUTE 47 // only if solder bridge "DAC_MUTE" is closed + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_dac/pins_arduino.h b/variants/yb_esp32s3_dac/pins_arduino.h new file mode 100644 index 0000000..c96d676 --- /dev/null +++ b/variants/yb_esp32s3_dac/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +// TLV320DAC3101 Stereo Audio DAC +static const uint8_t TLV_RESET = 21; // if resp. solder bridge is closed (default closed) +static const uint8_t TLV_INT = 48; // if resp. solder bridge is closed (default open) + +// I2S for onboard TLV320DAC3101 +static const uint8_t I2S_MCLK = 4; // if resp. solder bridge is closed (default open) +static const uint8_t I2S_BCLK = 5; +static const uint8_t I2S_LRCLK = 6; +static const uint8_t I2S_DOUT = 7; + +// SPI for onboard microSD +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// SPI2 for public usage +static const uint8_t SS2 = 38; +static const uint8_t MOSI2 = 39; +static const uint8_t MISO2 = 41; +static const uint8_t SCK2 = 40; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 8; +static const uint8_t A5 = 9; +static const uint8_t A6 = 10; +static const uint8_t A7 = 14; +static const uint8_t A8 = 15; +static const uint8_t A9 = 16; +static const uint8_t A10 = 17; +static const uint8_t A11 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_drv/pins_arduino.h b/variants/yb_esp32s3_drv/pins_arduino.h new file mode 100644 index 0000000..06de47e --- /dev/null +++ b/variants/yb_esp32s3_drv/pins_arduino.h @@ -0,0 +1,60 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// 2 connectors (X, Y) with 4 driver channels each +static const uint8_t X1 = 35; +static const uint8_t X2 = 36; +static const uint8_t X3 = 37; +static const uint8_t X4 = 38; +static const uint8_t Y1 = 4; +static const uint8_t Y2 = 5; +static const uint8_t Y3 = 6; +static const uint8_t Y4 = 7; + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 8; +static const uint8_t A4 = 9; +static const uint8_t A5 = 10; +static const uint8_t A6 = 11; +static const uint8_t A7 = 12; +static const uint8_t A8 = 13; +static const uint8_t A9 = 14; +static const uint8_t A10 = 15; +static const uint8_t A11 = 16; +static const uint8_t A12 = 17; +static const uint8_t A13 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */ diff --git a/variants/yb_esp32s3_eth/pins_arduino.h b/variants/yb_esp32s3_eth/pins_arduino.h new file mode 100644 index 0000000..77fcf69 --- /dev/null +++ b/variants/yb_esp32s3_eth/pins_arduino.h @@ -0,0 +1,63 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#define USB_VID 0x303A +#define USB_PID 0x1001 + +static const uint8_t LED_BUILTIN = 47; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN + +static const uint8_t TX = 43; +static const uint8_t RX = 44; + +static const uint8_t SDA = 8; +static const uint8_t SCL = 9; + +static const uint8_t SS = 10; +static const uint8_t MOSI = 11; +static const uint8_t MISO = 13; +static const uint8_t SCK = 12; + +// Definitions for onboard WIZnet W5500 ethernet controller chip +static const uint8_t W5500_SS = 14; // W5500 chip select +static const uint8_t W5500_INT = 18; // available only if solder bridge "INT" is closed (default open) +static const uint8_t W5500_RST = 21; // set GPIO21 to INPUT (high impedance) if RST signal is unused + +static const uint8_t A0 = 1; +static const uint8_t A1 = 2; +static const uint8_t A2 = 3; +static const uint8_t A3 = 4; +static const uint8_t A4 = 5; +static const uint8_t A5 = 6; +static const uint8_t A6 = 7; +static const uint8_t A7 = 8; +static const uint8_t A8 = 9; +static const uint8_t A9 = 10; +static const uint8_t A10 = 11; +static const uint8_t A11 = 12; +static const uint8_t A12 = 13; +static const uint8_t A13 = 14; +static const uint8_t A14 = 15; +static const uint8_t A15 = 16; +static const uint8_t A16 = 17; +static const uint8_t A17 = 18; + +static const uint8_t T1 = 1; +static const uint8_t T2 = 2; +static const uint8_t T3 = 3; +static const uint8_t T4 = 4; +static const uint8_t T5 = 5; +static const uint8_t T6 = 6; +static const uint8_t T7 = 7; +static const uint8_t T8 = 8; +static const uint8_t T9 = 9; +static const uint8_t T10 = 10; +static const uint8_t T11 = 11; +static const uint8_t T12 = 12; +static const uint8_t T13 = 13; +static const uint8_t T14 = 14; + +#endif /* Pins_Arduino_h */